Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 24
- Errors: 0
- Kernel Errors: 36
- Boot result: PASS
1 01:20:05.954036 lava-dispatcher, installed at version: 2024.01
2 01:20:05.954242 start: 0 validate
3 01:20:05.954409 Start time: 2024-04-23 01:20:05.954402+00:00 (UTC)
4 01:20:05.954529 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:20:05.954653 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:20:06.225972 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:20:06.226702 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:20:06.484044 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:20:06.484736 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:20:06.742199 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:20:06.743014 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:20:07.002466 Using caching service: 'http://localhost/cache/?uri=%s'
13 01:20:07.003349 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 01:20:07.269618 validate duration: 1.32
16 01:20:07.270910 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:20:07.271437 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:20:07.271936 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:20:07.272563 Not decompressing ramdisk as can be used compressed.
20 01:20:07.273029 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 01:20:07.273395 saving as /var/lib/lava/dispatcher/tmp/13468747/tftp-deploy-8daeronz/ramdisk/initrd.cpio.gz
22 01:20:07.273758 total size: 5628169 (5 MB)
23 01:20:07.280324 progress 0 % (0 MB)
24 01:20:07.289318 progress 5 % (0 MB)
25 01:20:07.298334 progress 10 % (0 MB)
26 01:20:07.305745 progress 15 % (0 MB)
27 01:20:07.312267 progress 20 % (1 MB)
28 01:20:07.316544 progress 25 % (1 MB)
29 01:20:07.320377 progress 30 % (1 MB)
30 01:20:07.323783 progress 35 % (1 MB)
31 01:20:07.326394 progress 40 % (2 MB)
32 01:20:07.329219 progress 45 % (2 MB)
33 01:20:07.331414 progress 50 % (2 MB)
34 01:20:07.333816 progress 55 % (2 MB)
35 01:20:07.336037 progress 60 % (3 MB)
36 01:20:07.338019 progress 65 % (3 MB)
37 01:20:07.340158 progress 70 % (3 MB)
38 01:20:07.341894 progress 75 % (4 MB)
39 01:20:07.343910 progress 80 % (4 MB)
40 01:20:07.345545 progress 85 % (4 MB)
41 01:20:07.347437 progress 90 % (4 MB)
42 01:20:07.349196 progress 95 % (5 MB)
43 01:20:07.350732 progress 100 % (5 MB)
44 01:20:07.350983 5 MB downloaded in 0.08 s (69.48 MB/s)
45 01:20:07.351189 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:20:07.351457 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:20:07.351544 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:20:07.351630 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:20:07.351770 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 01:20:07.351845 saving as /var/lib/lava/dispatcher/tmp/13468747/tftp-deploy-8daeronz/kernel/Image
52 01:20:07.351908 total size: 54352384 (51 MB)
53 01:20:07.351971 No compression specified
54 01:20:07.353182 progress 0 % (0 MB)
55 01:20:07.367377 progress 5 % (2 MB)
56 01:20:07.381156 progress 10 % (5 MB)
57 01:20:07.394945 progress 15 % (7 MB)
58 01:20:07.408536 progress 20 % (10 MB)
59 01:20:07.422261 progress 25 % (12 MB)
60 01:20:07.436037 progress 30 % (15 MB)
61 01:20:07.450164 progress 35 % (18 MB)
62 01:20:07.463959 progress 40 % (20 MB)
63 01:20:07.477722 progress 45 % (23 MB)
64 01:20:07.491494 progress 50 % (25 MB)
65 01:20:07.505222 progress 55 % (28 MB)
66 01:20:07.518828 progress 60 % (31 MB)
67 01:20:07.532500 progress 65 % (33 MB)
68 01:20:07.546244 progress 70 % (36 MB)
69 01:20:07.560097 progress 75 % (38 MB)
70 01:20:07.573633 progress 80 % (41 MB)
71 01:20:07.587420 progress 85 % (44 MB)
72 01:20:07.601198 progress 90 % (46 MB)
73 01:20:07.614812 progress 95 % (49 MB)
74 01:20:07.628240 progress 100 % (51 MB)
75 01:20:07.628455 51 MB downloaded in 0.28 s (187.44 MB/s)
76 01:20:07.628606 end: 1.2.1 http-download (duration 00:00:00) [common]
78 01:20:07.628844 end: 1.2 download-retry (duration 00:00:00) [common]
79 01:20:07.628931 start: 1.3 download-retry (timeout 00:10:00) [common]
80 01:20:07.629018 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 01:20:07.629155 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 01:20:07.629225 saving as /var/lib/lava/dispatcher/tmp/13468747/tftp-deploy-8daeronz/dtb/mt8192-asurada-spherion-r0.dtb
83 01:20:07.629286 total size: 47230 (0 MB)
84 01:20:07.629348 No compression specified
85 01:20:07.630468 progress 69 % (0 MB)
86 01:20:07.630737 progress 100 % (0 MB)
87 01:20:07.630895 0 MB downloaded in 0.00 s (28.05 MB/s)
88 01:20:07.631016 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:20:07.631235 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:20:07.631318 start: 1.4 download-retry (timeout 00:10:00) [common]
92 01:20:07.631399 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 01:20:07.631508 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 01:20:07.631575 saving as /var/lib/lava/dispatcher/tmp/13468747/tftp-deploy-8daeronz/nfsrootfs/full.rootfs.tar
95 01:20:07.631635 total size: 120894716 (115 MB)
96 01:20:07.631696 Using unxz to decompress xz
97 01:20:07.637402 progress 0 % (0 MB)
98 01:20:07.980916 progress 5 % (5 MB)
99 01:20:08.338783 progress 10 % (11 MB)
100 01:20:08.689293 progress 15 % (17 MB)
101 01:20:09.016026 progress 20 % (23 MB)
102 01:20:09.310208 progress 25 % (28 MB)
103 01:20:09.674220 progress 30 % (34 MB)
104 01:20:10.014437 progress 35 % (40 MB)
105 01:20:10.179029 progress 40 % (46 MB)
106 01:20:10.356629 progress 45 % (51 MB)
107 01:20:10.663379 progress 50 % (57 MB)
108 01:20:11.094216 progress 55 % (63 MB)
109 01:20:11.433713 progress 60 % (69 MB)
110 01:20:11.771685 progress 65 % (74 MB)
111 01:20:12.110939 progress 70 % (80 MB)
112 01:20:12.462609 progress 75 % (86 MB)
113 01:20:12.799034 progress 80 % (92 MB)
114 01:20:13.132765 progress 85 % (98 MB)
115 01:20:13.483536 progress 90 % (103 MB)
116 01:20:13.804406 progress 95 % (109 MB)
117 01:20:14.154144 progress 100 % (115 MB)
118 01:20:14.159425 115 MB downloaded in 6.53 s (17.66 MB/s)
119 01:20:14.159681 end: 1.4.1 http-download (duration 00:00:07) [common]
121 01:20:14.159943 end: 1.4 download-retry (duration 00:00:07) [common]
122 01:20:14.160032 start: 1.5 download-retry (timeout 00:09:53) [common]
123 01:20:14.160117 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 01:20:14.160266 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 01:20:14.160338 saving as /var/lib/lava/dispatcher/tmp/13468747/tftp-deploy-8daeronz/modules/modules.tar
126 01:20:14.160400 total size: 8638160 (8 MB)
127 01:20:14.160464 Using unxz to decompress xz
128 01:20:14.164466 progress 0 % (0 MB)
129 01:20:14.183466 progress 5 % (0 MB)
130 01:20:14.207505 progress 10 % (0 MB)
131 01:20:14.231041 progress 15 % (1 MB)
132 01:20:14.253839 progress 20 % (1 MB)
133 01:20:14.278029 progress 25 % (2 MB)
134 01:20:14.303177 progress 30 % (2 MB)
135 01:20:14.326748 progress 35 % (2 MB)
136 01:20:14.351282 progress 40 % (3 MB)
137 01:20:14.374753 progress 45 % (3 MB)
138 01:20:14.398942 progress 50 % (4 MB)
139 01:20:14.422991 progress 55 % (4 MB)
140 01:20:14.450326 progress 60 % (4 MB)
141 01:20:14.475129 progress 65 % (5 MB)
142 01:20:14.499380 progress 70 % (5 MB)
143 01:20:14.523046 progress 75 % (6 MB)
144 01:20:14.547677 progress 80 % (6 MB)
145 01:20:14.575295 progress 85 % (7 MB)
146 01:20:14.600802 progress 90 % (7 MB)
147 01:20:14.629713 progress 95 % (7 MB)
148 01:20:14.655523 progress 100 % (8 MB)
149 01:20:14.661237 8 MB downloaded in 0.50 s (16.45 MB/s)
150 01:20:14.661484 end: 1.5.1 http-download (duration 00:00:01) [common]
152 01:20:14.661744 end: 1.5 download-retry (duration 00:00:01) [common]
153 01:20:14.661836 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 01:20:14.661931 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 01:20:18.166247 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13468747/extract-nfsrootfs-v5xyip58
156 01:20:18.166478 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 01:20:18.166583 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 01:20:18.166756 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il
159 01:20:18.166890 makedir: /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin
160 01:20:18.166991 makedir: /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/tests
161 01:20:18.167090 makedir: /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/results
162 01:20:18.167190 Creating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-add-keys
163 01:20:18.167334 Creating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-add-sources
164 01:20:18.167461 Creating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-background-process-start
165 01:20:18.167586 Creating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-background-process-stop
166 01:20:18.167711 Creating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-common-functions
167 01:20:18.167834 Creating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-echo-ipv4
168 01:20:18.167958 Creating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-install-packages
169 01:20:18.168081 Creating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-installed-packages
170 01:20:18.168203 Creating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-os-build
171 01:20:18.168325 Creating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-probe-channel
172 01:20:18.168448 Creating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-probe-ip
173 01:20:18.168570 Creating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-target-ip
174 01:20:18.168692 Creating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-target-mac
175 01:20:18.168813 Creating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-target-storage
176 01:20:18.168942 Creating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-test-case
177 01:20:18.169064 Creating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-test-event
178 01:20:18.169188 Creating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-test-feedback
179 01:20:18.169309 Creating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-test-raise
180 01:20:18.169430 Creating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-test-reference
181 01:20:18.169552 Creating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-test-runner
182 01:20:18.169687 Creating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-test-set
183 01:20:18.169809 Creating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-test-shell
184 01:20:18.169939 Updating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-add-keys (debian)
185 01:20:18.171630 Updating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-add-sources (debian)
186 01:20:18.172748 Updating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-install-packages (debian)
187 01:20:18.173069 Updating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-installed-packages (debian)
188 01:20:18.173367 Updating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/bin/lava-os-build (debian)
189 01:20:18.173665 Creating /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/environment
190 01:20:18.173767 LAVA metadata
191 01:20:18.173837 - LAVA_JOB_ID=13468747
192 01:20:18.173903 - LAVA_DISPATCHER_IP=192.168.201.1
193 01:20:18.174017 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 01:20:18.174086 skipped lava-vland-overlay
195 01:20:18.174160 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 01:20:18.174237 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 01:20:18.174307 skipped lava-multinode-overlay
198 01:20:18.174419 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 01:20:18.174496 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 01:20:18.174568 Loading test definitions
201 01:20:18.174653 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 01:20:18.174747 Using /lava-13468747 at stage 0
203 01:20:18.175052 uuid=13468747_1.6.2.3.1 testdef=None
204 01:20:18.175152 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 01:20:18.175244 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 01:20:18.175684 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 01:20:18.175907 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 01:20:18.176455 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 01:20:18.176701 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 01:20:18.177245 runner path: /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/0/tests/0_timesync-off test_uuid 13468747_1.6.2.3.1
213 01:20:18.177401 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 01:20:18.177620 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 01:20:18.177692 Using /lava-13468747 at stage 0
217 01:20:18.177811 Fetching tests from https://github.com/kernelci/test-definitions.git
218 01:20:18.177896 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/0/tests/1_kselftest-dt'
219 01:20:20.079603 Running '/usr/bin/git checkout kernelci.org
220 01:20:20.155683 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 01:20:20.156628 uuid=13468747_1.6.2.3.5 testdef=None
222 01:20:20.156817 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 01:20:20.157176 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 01:20:20.158401 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 01:20:20.158630 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 01:20:20.159850 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 01:20:20.160087 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 01:20:20.161638 runner path: /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/0/tests/1_kselftest-dt test_uuid 13468747_1.6.2.3.5
232 01:20:20.161758 BOARD='mt8192-asurada-spherion-r0'
233 01:20:20.161849 BRANCH='cip'
234 01:20:20.161939 SKIPFILE='/dev/null'
235 01:20:20.162029 SKIP_INSTALL='True'
236 01:20:20.162114 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 01:20:20.162200 TST_CASENAME=''
238 01:20:20.162284 TST_CMDFILES='dt'
239 01:20:20.162509 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 01:20:20.162854 Creating lava-test-runner.conf files
242 01:20:20.162944 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13468747/lava-overlay-k8jb22il/lava-13468747/0 for stage 0
243 01:20:20.163065 - 0_timesync-off
244 01:20:20.163162 - 1_kselftest-dt
245 01:20:20.163287 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 01:20:20.163403 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 01:20:27.710423 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 01:20:27.710575 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:40) [common]
249 01:20:27.710664 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 01:20:27.710758 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 01:20:27.710849 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:40) [common]
252 01:20:27.873364 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 01:20:27.873758 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 01:20:27.873871 extracting modules file /var/lib/lava/dispatcher/tmp/13468747/tftp-deploy-8daeronz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13468747/extract-nfsrootfs-v5xyip58
255 01:20:28.086743 extracting modules file /var/lib/lava/dispatcher/tmp/13468747/tftp-deploy-8daeronz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13468747/extract-overlay-ramdisk-jvejdssw/ramdisk
256 01:20:28.302537 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 01:20:28.302694 start: 1.6.5 apply-overlay-tftp (timeout 00:09:39) [common]
258 01:20:28.302792 [common] Applying overlay to NFS
259 01:20:28.302876 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13468747/compress-overlay-f3x97wcg/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13468747/extract-nfsrootfs-v5xyip58
260 01:20:29.210787 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 01:20:29.210958 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 01:20:29.211056 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 01:20:29.211139 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 01:20:29.211216 Building ramdisk /var/lib/lava/dispatcher/tmp/13468747/extract-overlay-ramdisk-jvejdssw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13468747/extract-overlay-ramdisk-jvejdssw/ramdisk
265 01:20:29.515090 >> 130624 blocks
266 01:20:31.520198 rename /var/lib/lava/dispatcher/tmp/13468747/extract-overlay-ramdisk-jvejdssw/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13468747/tftp-deploy-8daeronz/ramdisk/ramdisk.cpio.gz
267 01:20:31.520648 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 01:20:31.520771 start: 1.6.8 prepare-kernel (timeout 00:09:36) [common]
269 01:20:31.520935 start: 1.6.8.1 prepare-fit (timeout 00:09:36) [common]
270 01:20:31.521070 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13468747/tftp-deploy-8daeronz/kernel/Image'
271 01:20:44.172575 Returned 0 in 12 seconds
272 01:20:44.273592 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13468747/tftp-deploy-8daeronz/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13468747/tftp-deploy-8daeronz/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13468747/tftp-deploy-8daeronz/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13468747/tftp-deploy-8daeronz/kernel/image.itb
273 01:20:44.644214 output: FIT description: Kernel Image image with one or more FDT blobs
274 01:20:44.644598 output: Created: Tue Apr 23 02:20:44 2024
275 01:20:44.644672 output: Image 0 (kernel-1)
276 01:20:44.644738 output: Description:
277 01:20:44.644804 output: Created: Tue Apr 23 02:20:44 2024
278 01:20:44.644865 output: Type: Kernel Image
279 01:20:44.644924 output: Compression: lzma compressed
280 01:20:44.644980 output: Data Size: 12910050 Bytes = 12607.47 KiB = 12.31 MiB
281 01:20:44.645035 output: Architecture: AArch64
282 01:20:44.645099 output: OS: Linux
283 01:20:44.645190 output: Load Address: 0x00000000
284 01:20:44.645251 output: Entry Point: 0x00000000
285 01:20:44.645308 output: Hash algo: crc32
286 01:20:44.645365 output: Hash value: 1126c3f9
287 01:20:44.645420 output: Image 1 (fdt-1)
288 01:20:44.645478 output: Description: mt8192-asurada-spherion-r0
289 01:20:44.645531 output: Created: Tue Apr 23 02:20:44 2024
290 01:20:44.645584 output: Type: Flat Device Tree
291 01:20:44.645637 output: Compression: uncompressed
292 01:20:44.645690 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
293 01:20:44.645746 output: Architecture: AArch64
294 01:20:44.645798 output: Hash algo: crc32
295 01:20:44.645850 output: Hash value: 4bf0d1ac
296 01:20:44.645902 output: Image 2 (ramdisk-1)
297 01:20:44.645954 output: Description: unavailable
298 01:20:44.646007 output: Created: Tue Apr 23 02:20:44 2024
299 01:20:44.646059 output: Type: RAMDisk Image
300 01:20:44.646111 output: Compression: Unknown Compression
301 01:20:44.646163 output: Data Size: 18777429 Bytes = 18337.33 KiB = 17.91 MiB
302 01:20:44.646215 output: Architecture: AArch64
303 01:20:44.646267 output: OS: Linux
304 01:20:44.646327 output: Load Address: unavailable
305 01:20:44.646381 output: Entry Point: unavailable
306 01:20:44.646433 output: Hash algo: crc32
307 01:20:44.646485 output: Hash value: 5f1498e3
308 01:20:44.646537 output: Default Configuration: 'conf-1'
309 01:20:44.646590 output: Configuration 0 (conf-1)
310 01:20:44.646642 output: Description: mt8192-asurada-spherion-r0
311 01:20:44.646694 output: Kernel: kernel-1
312 01:20:44.646746 output: Init Ramdisk: ramdisk-1
313 01:20:44.646797 output: FDT: fdt-1
314 01:20:44.646849 output: Loadables: kernel-1
315 01:20:44.646900 output:
316 01:20:44.647103 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 01:20:44.647196 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 01:20:44.647300 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
319 01:20:44.647390 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:23) [common]
320 01:20:44.647472 No LXC device requested
321 01:20:44.647549 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 01:20:44.647633 start: 1.8 deploy-device-env (timeout 00:09:23) [common]
323 01:20:44.647709 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 01:20:44.647778 Checking files for TFTP limit of 4294967296 bytes.
325 01:20:44.648270 end: 1 tftp-deploy (duration 00:00:37) [common]
326 01:20:44.648379 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 01:20:44.648476 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 01:20:44.648601 substitutions:
329 01:20:44.648667 - {DTB}: 13468747/tftp-deploy-8daeronz/dtb/mt8192-asurada-spherion-r0.dtb
330 01:20:44.648731 - {INITRD}: 13468747/tftp-deploy-8daeronz/ramdisk/ramdisk.cpio.gz
331 01:20:44.648789 - {KERNEL}: 13468747/tftp-deploy-8daeronz/kernel/Image
332 01:20:44.648846 - {LAVA_MAC}: None
333 01:20:44.648902 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13468747/extract-nfsrootfs-v5xyip58
334 01:20:44.648957 - {NFS_SERVER_IP}: 192.168.201.1
335 01:20:44.649012 - {PRESEED_CONFIG}: None
336 01:20:44.649065 - {PRESEED_LOCAL}: None
337 01:20:44.649119 - {RAMDISK}: 13468747/tftp-deploy-8daeronz/ramdisk/ramdisk.cpio.gz
338 01:20:44.649172 - {ROOT_PART}: None
339 01:20:44.649226 - {ROOT}: None
340 01:20:44.649279 - {SERVER_IP}: 192.168.201.1
341 01:20:44.649332 - {TEE}: None
342 01:20:44.649385 Parsed boot commands:
343 01:20:44.649437 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 01:20:44.649617 Parsed boot commands: tftpboot 192.168.201.1 13468747/tftp-deploy-8daeronz/kernel/image.itb 13468747/tftp-deploy-8daeronz/kernel/cmdline
345 01:20:44.649704 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 01:20:44.649789 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 01:20:44.649878 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 01:20:44.649961 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 01:20:44.650035 Not connected, no need to disconnect.
350 01:20:44.650107 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 01:20:44.650191 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 01:20:44.650261 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 01:20:44.654067 Setting prompt string to ['lava-test: # ']
354 01:20:44.654435 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 01:20:44.654543 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 01:20:44.654634 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 01:20:44.654731 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 01:20:44.654931 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
359 01:20:49.793441 >> Command sent successfully.
360 01:20:49.795840 Returned 0 in 5 seconds
361 01:20:49.896256 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 01:20:49.896589 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 01:20:49.896699 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 01:20:49.896826 Setting prompt string to 'Starting depthcharge on Spherion...'
366 01:20:49.896921 Changing prompt to 'Starting depthcharge on Spherion...'
367 01:20:49.896990 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 01:20:49.897262 [Enter `^Ec?' for help]
369 01:20:50.073264
370 01:20:50.073422
371 01:20:50.073495 F0: 102B 0000
372 01:20:50.073560
373 01:20:50.073624 F3: 1001 0000 [0200]
374 01:20:50.076487
375 01:20:50.076569 F3: 1001 0000
376 01:20:50.076637
377 01:20:50.076700 F7: 102D 0000
378 01:20:50.076760
379 01:20:50.079226 F1: 0000 0000
380 01:20:50.079310
381 01:20:50.079375 V0: 0000 0000 [0001]
382 01:20:50.079439
383 01:20:50.082766 00: 0007 8000
384 01:20:50.082854
385 01:20:50.082919 01: 0000 0000
386 01:20:50.082982
387 01:20:50.085983 BP: 0C00 0209 [0000]
388 01:20:50.086066
389 01:20:50.086134 G0: 1182 0000
390 01:20:50.086195
391 01:20:50.089311 EC: 0000 0021 [4000]
392 01:20:50.089393
393 01:20:50.089458 S7: 0000 0000 [0000]
394 01:20:50.089519
395 01:20:50.093257 CC: 0000 0000 [0001]
396 01:20:50.093341
397 01:20:50.093407 T0: 0000 0040 [010F]
398 01:20:50.093469
399 01:20:50.093527 Jump to BL
400 01:20:50.093584
401 01:20:50.120125
402 01:20:50.120276
403 01:20:50.120346
404 01:20:50.127370 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 01:20:50.130716 ARM64: Exception handlers installed.
406 01:20:50.134187 ARM64: Testing exception
407 01:20:50.137212 ARM64: Done test exception
408 01:20:50.144545 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 01:20:50.154615 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 01:20:50.161361 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 01:20:50.171424 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 01:20:50.178313 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 01:20:50.184833 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 01:20:50.196978 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 01:20:50.203232 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 01:20:50.222646 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 01:20:50.226052 WDT: Last reset was cold boot
418 01:20:50.229712 SPI1(PAD0) initialized at 2873684 Hz
419 01:20:50.232713 SPI5(PAD0) initialized at 992727 Hz
420 01:20:50.236350 VBOOT: Loading verstage.
421 01:20:50.242683 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 01:20:50.245993 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 01:20:50.249790 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 01:20:50.253053 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 01:20:50.259986 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 01:20:50.266970 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 01:20:50.278241 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 01:20:50.278392
429 01:20:50.278461
430 01:20:50.288449 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 01:20:50.291715 ARM64: Exception handlers installed.
432 01:20:50.291800 ARM64: Testing exception
433 01:20:50.294990 ARM64: Done test exception
434 01:20:50.298734 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 01:20:50.305404 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 01:20:50.318988 Probing TPM: . done!
437 01:20:50.319103 TPM ready after 0 ms
438 01:20:50.326095 Connected to device vid:did:rid of 1ae0:0028:00
439 01:20:50.333124 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 01:20:50.392592 Initialized TPM device CR50 revision 0
441 01:20:50.402983 tlcl_send_startup: Startup return code is 0
442 01:20:50.403098 TPM: setup succeeded
443 01:20:50.414616 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 01:20:50.423195 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 01:20:50.437274 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 01:20:50.445142 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 01:20:50.448935 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 01:20:50.452228 in-header: 03 07 00 00 08 00 00 00
449 01:20:50.456072 in-data: aa e4 47 04 13 02 00 00
450 01:20:50.456159 Chrome EC: UHEPI supported
451 01:20:50.462703 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 01:20:50.466520 in-header: 03 95 00 00 08 00 00 00
453 01:20:50.470102 in-data: 18 20 20 08 00 00 00 00
454 01:20:50.470188 Phase 1
455 01:20:50.473565 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 01:20:50.481481 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 01:20:50.488881 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 01:20:50.488984 Recovery requested (1009000e)
459 01:20:50.499996 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 01:20:50.504563 tlcl_extend: response is 0
461 01:20:50.514010 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 01:20:50.519455 tlcl_extend: response is 0
463 01:20:50.526765 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 01:20:50.546563 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 01:20:50.553346 BS: bootblock times (exec / console): total (unknown) / 149 ms
466 01:20:50.553450
467 01:20:50.553519
468 01:20:50.563677 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 01:20:50.566424 ARM64: Exception handlers installed.
470 01:20:50.569642 ARM64: Testing exception
471 01:20:50.569726 ARM64: Done test exception
472 01:20:50.592183 pmic_efuse_setting: Set efuses in 11 msecs
473 01:20:50.595200 pmwrap_interface_init: Select PMIF_VLD_RDY
474 01:20:50.602298 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 01:20:50.605622 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 01:20:50.613301 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 01:20:50.616301 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 01:20:50.620118 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 01:20:50.623881 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 01:20:50.631882 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 01:20:50.635621 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 01:20:50.639331 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 01:20:50.642524 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 01:20:50.650124 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 01:20:50.654198 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 01:20:50.658228 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 01:20:50.665371 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 01:20:50.669002 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 01:20:50.676722 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 01:20:50.680527 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 01:20:50.688116 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 01:20:50.691499 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 01:20:50.698822 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 01:20:50.702667 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 01:20:50.710375 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 01:20:50.713984 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 01:20:50.721329 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 01:20:50.724972 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 01:20:50.732113 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 01:20:50.736384 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 01:20:50.739941 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 01:20:50.747157 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 01:20:50.751447 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 01:20:50.754713 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 01:20:50.762053 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 01:20:50.765525 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 01:20:50.769441 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 01:20:50.777047 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 01:20:50.780791 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 01:20:50.788413 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 01:20:50.792063 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 01:20:50.795456 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 01:20:50.799026 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 01:20:50.803279 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 01:20:50.810537 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 01:20:50.814502 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 01:20:50.818277 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 01:20:50.822048 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 01:20:50.825712 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 01:20:50.829603 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 01:20:50.833047 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 01:20:50.840640 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 01:20:50.843992 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 01:20:50.847685 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 01:20:50.855379 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 01:20:50.863144 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 01:20:50.866529 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 01:20:50.877183 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 01:20:50.884682 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 01:20:50.888455 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 01:20:50.892490 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 01:20:50.899688 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 01:20:50.906642 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x26
534 01:20:50.910364 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 01:20:50.913975 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 01:20:50.921476 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 01:20:50.930186 [RTC]rtc_get_frequency_meter,154: input=15, output=757
538 01:20:50.939265 [RTC]rtc_get_frequency_meter,154: input=23, output=942
539 01:20:50.948440 [RTC]rtc_get_frequency_meter,154: input=19, output=851
540 01:20:50.958130 [RTC]rtc_get_frequency_meter,154: input=17, output=805
541 01:20:50.967786 [RTC]rtc_get_frequency_meter,154: input=16, output=782
542 01:20:50.977224 [RTC]rtc_get_frequency_meter,154: input=16, output=781
543 01:20:50.988416 [RTC]rtc_get_frequency_meter,154: input=17, output=804
544 01:20:50.991669 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 01:20:50.995863 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 01:20:50.999404 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 01:20:51.002676 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 01:20:51.010818 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 01:20:51.010920 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 01:20:51.015270 ADC[4]: Raw value=905465 ID=7
551 01:20:51.018642 ADC[3]: Raw value=213810 ID=1
552 01:20:51.018730 RAM Code: 0x71
553 01:20:51.022353 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 01:20:51.029605 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 01:20:51.037291 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 01:20:51.044780 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 01:20:51.048360 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 01:20:51.051775 in-header: 03 07 00 00 08 00 00 00
559 01:20:51.055662 in-data: aa e4 47 04 13 02 00 00
560 01:20:51.055825 Chrome EC: UHEPI supported
561 01:20:51.063092 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 01:20:51.066241 in-header: 03 95 00 00 08 00 00 00
563 01:20:51.070228 in-data: 18 20 20 08 00 00 00 00
564 01:20:51.074175 MRC: failed to locate region type 0.
565 01:20:51.081494 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 01:20:51.081596 DRAM-K: Running full calibration
567 01:20:51.089268 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 01:20:51.092775 header.status = 0x0
569 01:20:51.092865 header.version = 0x6 (expected: 0x6)
570 01:20:51.096617 header.size = 0xd00 (expected: 0xd00)
571 01:20:51.100490 header.flags = 0x0
572 01:20:51.104039 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 01:20:51.124715 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
574 01:20:51.132456 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 01:20:51.132631 dram_init: ddr_geometry: 2
576 01:20:51.136106 [EMI] MDL number = 2
577 01:20:51.136204 [EMI] Get MDL freq = 0
578 01:20:51.139579 dram_init: ddr_type: 0
579 01:20:51.139744 is_discrete_lpddr4: 1
580 01:20:51.143730 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 01:20:51.143916
582 01:20:51.144041
583 01:20:51.146964 [Bian_co] ETT version 0.0.0.1
584 01:20:51.150724 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 01:20:51.151036
586 01:20:51.154430 dramc_set_vcore_voltage set vcore to 650000
587 01:20:51.158538 Read voltage for 800, 4
588 01:20:51.158668 Vio18 = 0
589 01:20:51.158737 Vcore = 650000
590 01:20:51.162908 Vdram = 0
591 01:20:51.163039 Vddq = 0
592 01:20:51.163133 Vmddr = 0
593 01:20:51.166117 dram_init: config_dvfs: 1
594 01:20:51.169793 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 01:20:51.177293 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 01:20:51.180955 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 01:20:51.185014 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 01:20:51.188590 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 01:20:51.191905 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 01:20:51.192055 MEM_TYPE=3, freq_sel=18
601 01:20:51.195679 sv_algorithm_assistance_LP4_1600
602 01:20:51.199434 ============ PULL DRAM RESETB DOWN ============
603 01:20:51.205859 ========== PULL DRAM RESETB DOWN end =========
604 01:20:51.209307 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 01:20:51.212755 ===================================
606 01:20:51.216629 LPDDR4 DRAM CONFIGURATION
607 01:20:51.219619 ===================================
608 01:20:51.219776 EX_ROW_EN[0] = 0x0
609 01:20:51.223346 EX_ROW_EN[1] = 0x0
610 01:20:51.223480 LP4Y_EN = 0x0
611 01:20:51.227335 WORK_FSP = 0x0
612 01:20:51.227487 WL = 0x2
613 01:20:51.231119 RL = 0x2
614 01:20:51.231230 BL = 0x2
615 01:20:51.234154 RPST = 0x0
616 01:20:51.234325 RD_PRE = 0x0
617 01:20:51.234460 WR_PRE = 0x1
618 01:20:51.238008 WR_PST = 0x0
619 01:20:51.238155 DBI_WR = 0x0
620 01:20:51.241202 DBI_RD = 0x0
621 01:20:51.241353 OTF = 0x1
622 01:20:51.244299 ===================================
623 01:20:51.247949 ===================================
624 01:20:51.251654 ANA top config
625 01:20:51.254763 ===================================
626 01:20:51.257828 DLL_ASYNC_EN = 0
627 01:20:51.257948 ALL_SLAVE_EN = 1
628 01:20:51.261513 NEW_RANK_MODE = 1
629 01:20:51.264674 DLL_IDLE_MODE = 1
630 01:20:51.267943 LP45_APHY_COMB_EN = 1
631 01:20:51.268056 TX_ODT_DIS = 1
632 01:20:51.271443 NEW_8X_MODE = 1
633 01:20:51.275236 ===================================
634 01:20:51.279249 ===================================
635 01:20:51.282265 data_rate = 1600
636 01:20:51.285771 CKR = 1
637 01:20:51.285915 DQ_P2S_RATIO = 8
638 01:20:51.289484 ===================================
639 01:20:51.291940 CA_P2S_RATIO = 8
640 01:20:51.295698 DQ_CA_OPEN = 0
641 01:20:51.298878 DQ_SEMI_OPEN = 0
642 01:20:51.302280 CA_SEMI_OPEN = 0
643 01:20:51.305794 CA_FULL_RATE = 0
644 01:20:51.305899 DQ_CKDIV4_EN = 1
645 01:20:51.309124 CA_CKDIV4_EN = 1
646 01:20:51.312016 CA_PREDIV_EN = 0
647 01:20:51.315405 PH8_DLY = 0
648 01:20:51.319253 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 01:20:51.322645 DQ_AAMCK_DIV = 4
650 01:20:51.322757 CA_AAMCK_DIV = 4
651 01:20:51.325843 CA_ADMCK_DIV = 4
652 01:20:51.328870 DQ_TRACK_CA_EN = 0
653 01:20:51.332185 CA_PICK = 800
654 01:20:51.335865 CA_MCKIO = 800
655 01:20:51.339746 MCKIO_SEMI = 0
656 01:20:51.339856 PLL_FREQ = 3068
657 01:20:51.343003 DQ_UI_PI_RATIO = 32
658 01:20:51.346715 CA_UI_PI_RATIO = 0
659 01:20:51.350427 ===================================
660 01:20:51.354033 ===================================
661 01:20:51.354142 memory_type:LPDDR4
662 01:20:51.358002 GP_NUM : 10
663 01:20:51.358118 SRAM_EN : 1
664 01:20:51.361928 MD32_EN : 0
665 01:20:51.365523 ===================================
666 01:20:51.365635 [ANA_INIT] >>>>>>>>>>>>>>
667 01:20:51.369489 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 01:20:51.373143 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 01:20:51.376706 ===================================
670 01:20:51.380183 data_rate = 1600,PCW = 0X7600
671 01:20:51.383397 ===================================
672 01:20:51.386769 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 01:20:51.389798 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 01:20:51.396476 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 01:20:51.400302 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 01:20:51.406790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 01:20:51.410290 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 01:20:51.410387 [ANA_INIT] flow start
679 01:20:51.413432 [ANA_INIT] PLL >>>>>>>>
680 01:20:51.413549 [ANA_INIT] PLL <<<<<<<<
681 01:20:51.416476 [ANA_INIT] MIDPI >>>>>>>>
682 01:20:51.420171 [ANA_INIT] MIDPI <<<<<<<<
683 01:20:51.423388 [ANA_INIT] DLL >>>>>>>>
684 01:20:51.423496 [ANA_INIT] flow end
685 01:20:51.426808 ============ LP4 DIFF to SE enter ============
686 01:20:51.433656 ============ LP4 DIFF to SE exit ============
687 01:20:51.433777 [ANA_INIT] <<<<<<<<<<<<<
688 01:20:51.437010 [Flow] Enable top DCM control >>>>>
689 01:20:51.440560 [Flow] Enable top DCM control <<<<<
690 01:20:51.443750 Enable DLL master slave shuffle
691 01:20:51.450160 ==============================================================
692 01:20:51.450281 Gating Mode config
693 01:20:51.456615 ==============================================================
694 01:20:51.460116 Config description:
695 01:20:51.470231 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 01:20:51.473802 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 01:20:51.480239 SELPH_MODE 0: By rank 1: By Phase
698 01:20:51.486568 ==============================================================
699 01:20:51.489832 GAT_TRACK_EN = 1
700 01:20:51.490043 RX_GATING_MODE = 2
701 01:20:51.493252 RX_GATING_TRACK_MODE = 2
702 01:20:51.497106 SELPH_MODE = 1
703 01:20:51.499922 PICG_EARLY_EN = 1
704 01:20:51.503777 VALID_LAT_VALUE = 1
705 01:20:51.509885 ==============================================================
706 01:20:51.513158 Enter into Gating configuration >>>>
707 01:20:51.516975 Exit from Gating configuration <<<<
708 01:20:51.520036 Enter into DVFS_PRE_config >>>>>
709 01:20:51.530240 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 01:20:51.533414 Exit from DVFS_PRE_config <<<<<
711 01:20:51.536538 Enter into PICG configuration >>>>
712 01:20:51.539995 Exit from PICG configuration <<<<
713 01:20:51.543372 [RX_INPUT] configuration >>>>>
714 01:20:51.543476 [RX_INPUT] configuration <<<<<
715 01:20:51.549977 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 01:20:51.557130 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 01:20:51.560113 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 01:20:51.566928 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 01:20:51.573794 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 01:20:51.580329 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 01:20:51.583564 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 01:20:51.587245 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 01:20:51.593697 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 01:20:51.597135 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 01:20:51.600343 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 01:20:51.603506 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 01:20:51.607013 ===================================
728 01:20:51.610322 LPDDR4 DRAM CONFIGURATION
729 01:20:51.613847 ===================================
730 01:20:51.617127 EX_ROW_EN[0] = 0x0
731 01:20:51.617215 EX_ROW_EN[1] = 0x0
732 01:20:51.620511 LP4Y_EN = 0x0
733 01:20:51.620623 WORK_FSP = 0x0
734 01:20:51.623492 WL = 0x2
735 01:20:51.623576 RL = 0x2
736 01:20:51.627198 BL = 0x2
737 01:20:51.627286 RPST = 0x0
738 01:20:51.630360 RD_PRE = 0x0
739 01:20:51.630444 WR_PRE = 0x1
740 01:20:51.633539 WR_PST = 0x0
741 01:20:51.633622 DBI_WR = 0x0
742 01:20:51.636721 DBI_RD = 0x0
743 01:20:51.636832 OTF = 0x1
744 01:20:51.640628 ===================================
745 01:20:51.647086 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 01:20:51.650670 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 01:20:51.654134 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 01:20:51.657177 ===================================
749 01:20:51.660470 LPDDR4 DRAM CONFIGURATION
750 01:20:51.663447 ===================================
751 01:20:51.667105 EX_ROW_EN[0] = 0x10
752 01:20:51.667191 EX_ROW_EN[1] = 0x0
753 01:20:51.670159 LP4Y_EN = 0x0
754 01:20:51.670242 WORK_FSP = 0x0
755 01:20:51.673642 WL = 0x2
756 01:20:51.673730 RL = 0x2
757 01:20:51.677456 BL = 0x2
758 01:20:51.677540 RPST = 0x0
759 01:20:51.680631 RD_PRE = 0x0
760 01:20:51.680714 WR_PRE = 0x1
761 01:20:51.683575 WR_PST = 0x0
762 01:20:51.683658 DBI_WR = 0x0
763 01:20:51.686922 DBI_RD = 0x0
764 01:20:51.687004 OTF = 0x1
765 01:20:51.690784 ===================================
766 01:20:51.697070 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 01:20:51.701601 nWR fixed to 40
768 01:20:51.704704 [ModeRegInit_LP4] CH0 RK0
769 01:20:51.704788 [ModeRegInit_LP4] CH0 RK1
770 01:20:51.708275 [ModeRegInit_LP4] CH1 RK0
771 01:20:51.711723 [ModeRegInit_LP4] CH1 RK1
772 01:20:51.711806 match AC timing 13
773 01:20:51.718573 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 01:20:51.721718 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 01:20:51.724912 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 01:20:51.731584 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 01:20:51.735069 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 01:20:51.735153 [EMI DOE] emi_dcm 0
779 01:20:51.741745 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 01:20:51.741834 ==
781 01:20:51.745484 Dram Type= 6, Freq= 0, CH_0, rank 0
782 01:20:51.748749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 01:20:51.748834 ==
784 01:20:51.755069 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 01:20:51.758234 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 01:20:51.768832 [CA 0] Center 36 (6~67) winsize 62
787 01:20:51.772283 [CA 1] Center 36 (6~67) winsize 62
788 01:20:51.775410 [CA 2] Center 34 (4~65) winsize 62
789 01:20:51.779025 [CA 3] Center 33 (3~64) winsize 62
790 01:20:51.782224 [CA 4] Center 33 (3~64) winsize 62
791 01:20:51.785671 [CA 5] Center 32 (3~62) winsize 60
792 01:20:51.785817
793 01:20:51.789294 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 01:20:51.789378
795 01:20:51.792346 [CATrainingPosCal] consider 1 rank data
796 01:20:51.796140 u2DelayCellTimex100 = 270/100 ps
797 01:20:51.798846 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 01:20:51.802279 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 01:20:51.808788 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 01:20:51.812631 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
801 01:20:51.815624 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
802 01:20:51.819272 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
803 01:20:51.819428
804 01:20:51.822421 CA PerBit enable=1, Macro0, CA PI delay=32
805 01:20:51.822578
806 01:20:51.826031 [CBTSetCACLKResult] CA Dly = 32
807 01:20:51.826187 CS Dly: 4 (0~35)
808 01:20:51.826365 ==
809 01:20:51.828965 Dram Type= 6, Freq= 0, CH_0, rank 1
810 01:20:51.835821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 01:20:51.835980 ==
812 01:20:51.839284 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 01:20:51.845535 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 01:20:51.854987 [CA 0] Center 36 (6~67) winsize 62
815 01:20:51.858416 [CA 1] Center 36 (6~67) winsize 62
816 01:20:51.862265 [CA 2] Center 34 (3~65) winsize 63
817 01:20:51.865354 [CA 3] Center 34 (4~65) winsize 62
818 01:20:51.868575 [CA 4] Center 32 (2~63) winsize 62
819 01:20:51.871829 [CA 5] Center 32 (2~63) winsize 62
820 01:20:51.871983
821 01:20:51.875392 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 01:20:51.875546
823 01:20:51.878656 [CATrainingPosCal] consider 2 rank data
824 01:20:51.881564 u2DelayCellTimex100 = 270/100 ps
825 01:20:51.885327 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 01:20:51.888613 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 01:20:51.895109 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
828 01:20:51.898661 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
829 01:20:51.902153 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
830 01:20:51.905256 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
831 01:20:51.905410
832 01:20:51.908573 CA PerBit enable=1, Macro0, CA PI delay=32
833 01:20:51.908730
834 01:20:51.912086 [CBTSetCACLKResult] CA Dly = 32
835 01:20:51.912239 CS Dly: 4 (0~36)
836 01:20:51.912382
837 01:20:51.915357 ----->DramcWriteLeveling(PI) begin...
838 01:20:51.915513 ==
839 01:20:51.919136 Dram Type= 6, Freq= 0, CH_0, rank 0
840 01:20:51.922813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 01:20:51.926703 ==
842 01:20:51.926869 Write leveling (Byte 0): 35 => 35
843 01:20:51.930410 Write leveling (Byte 1): 30 => 30
844 01:20:51.934104 DramcWriteLeveling(PI) end<-----
845 01:20:51.934262
846 01:20:51.934433 ==
847 01:20:51.937764 Dram Type= 6, Freq= 0, CH_0, rank 0
848 01:20:51.941299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 01:20:51.941460 ==
850 01:20:51.944233 [Gating] SW mode calibration
851 01:20:51.951740 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 01:20:51.958485 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 01:20:51.961586 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 01:20:51.964704 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 01:20:51.968553 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
856 01:20:51.975057 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 01:20:51.978691 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 01:20:51.981837 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 01:20:51.988305 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 01:20:51.991986 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 01:20:51.995031 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 01:20:52.001532 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 01:20:52.005111 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 01:20:52.008574 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 01:20:52.015079 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 01:20:52.018505 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 01:20:52.021909 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 01:20:52.028546 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 01:20:52.032006 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 01:20:52.035716 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
871 01:20:52.038610 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
872 01:20:52.045368 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 01:20:52.048395 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 01:20:52.052068 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 01:20:52.058810 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 01:20:52.062198 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 01:20:52.065604 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 01:20:52.072095 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 01:20:52.075629 0 9 8 | B1->B0 | 2323 2d2d | 1 0 | (1 1) (0 0)
880 01:20:52.078928 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
881 01:20:52.085122 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 01:20:52.088898 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 01:20:52.092070 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 01:20:52.098345 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 01:20:52.101899 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 01:20:52.104956 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 0)
887 01:20:52.112193 0 10 8 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
888 01:20:52.115378 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
889 01:20:52.118504 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 01:20:52.125227 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 01:20:52.128544 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 01:20:52.131901 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 01:20:52.135226 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 01:20:52.141979 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
895 01:20:52.145124 0 11 8 | B1->B0 | 2b2b 4040 | 0 0 | (0 0) (0 0)
896 01:20:52.148746 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
897 01:20:52.154882 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 01:20:52.158204 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 01:20:52.162097 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 01:20:52.168477 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 01:20:52.171778 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 01:20:52.175111 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 01:20:52.182409 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
904 01:20:52.185474 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 01:20:52.188557 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 01:20:52.194978 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 01:20:52.198547 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 01:20:52.201803 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 01:20:52.208280 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 01:20:52.211951 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 01:20:52.215334 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 01:20:52.221780 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 01:20:52.224975 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 01:20:52.228585 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 01:20:52.231903 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 01:20:52.238935 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 01:20:52.242071 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 01:20:52.245603 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 01:20:52.251992 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
920 01:20:52.255227 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 01:20:52.258792 Total UI for P1: 0, mck2ui 16
922 01:20:52.261790 best dqsien dly found for B0: ( 0, 14, 6)
923 01:20:52.265243 Total UI for P1: 0, mck2ui 16
924 01:20:52.268413 best dqsien dly found for B1: ( 0, 14, 10)
925 01:20:52.272150 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 01:20:52.276405 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
927 01:20:52.276502
928 01:20:52.279187 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 01:20:52.282926 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 01:20:52.286096 [Gating] SW calibration Done
931 01:20:52.286184 ==
932 01:20:52.289243 Dram Type= 6, Freq= 0, CH_0, rank 0
933 01:20:52.292420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 01:20:52.292518 ==
935 01:20:52.295774 RX Vref Scan: 0
936 01:20:52.295862
937 01:20:52.295928 RX Vref 0 -> 0, step: 1
938 01:20:52.299025
939 01:20:52.299116 RX Delay -130 -> 252, step: 16
940 01:20:52.305904 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 01:20:52.309135 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
942 01:20:52.312948 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 01:20:52.316261 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 01:20:52.319179 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 01:20:52.325817 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 01:20:52.329736 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
947 01:20:52.332818 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
948 01:20:52.336271 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
949 01:20:52.339611 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
950 01:20:52.346186 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 01:20:52.349256 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
952 01:20:52.352495 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 01:20:52.356093 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 01:20:52.359294 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
955 01:20:52.366072 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 01:20:52.366154 ==
957 01:20:52.369158 Dram Type= 6, Freq= 0, CH_0, rank 0
958 01:20:52.372658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 01:20:52.372742 ==
960 01:20:52.372807 DQS Delay:
961 01:20:52.375791 DQS0 = 0, DQS1 = 0
962 01:20:52.375872 DQM Delay:
963 01:20:52.378995 DQM0 = 89, DQM1 = 81
964 01:20:52.379077 DQ Delay:
965 01:20:52.382952 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
966 01:20:52.385951 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
967 01:20:52.389632 DQ8 =69, DQ9 =77, DQ10 =77, DQ11 =77
968 01:20:52.392328 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
969 01:20:52.392412
970 01:20:52.392479
971 01:20:52.392539 ==
972 01:20:52.396059 Dram Type= 6, Freq= 0, CH_0, rank 0
973 01:20:52.398879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 01:20:52.398963 ==
975 01:20:52.402749
976 01:20:52.402832
977 01:20:52.402897 TX Vref Scan disable
978 01:20:52.405944 == TX Byte 0 ==
979 01:20:52.409154 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
980 01:20:52.412753 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
981 01:20:52.415844 == TX Byte 1 ==
982 01:20:52.418880 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
983 01:20:52.422428 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
984 01:20:52.422535 ==
985 01:20:52.425752 Dram Type= 6, Freq= 0, CH_0, rank 0
986 01:20:52.432809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 01:20:52.432939 ==
988 01:20:52.444562 TX Vref=22, minBit 8, minWin=27, winSum=445
989 01:20:52.448529 TX Vref=24, minBit 8, minWin=27, winSum=451
990 01:20:52.451270 TX Vref=26, minBit 8, minWin=27, winSum=453
991 01:20:52.455043 TX Vref=28, minBit 8, minWin=28, winSum=457
992 01:20:52.458053 TX Vref=30, minBit 8, minWin=28, winSum=459
993 01:20:52.461772 TX Vref=32, minBit 2, minWin=28, winSum=455
994 01:20:52.467991 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30
995 01:20:52.468082
996 01:20:52.471238 Final TX Range 1 Vref 30
997 01:20:52.471323
998 01:20:52.471390 ==
999 01:20:52.474594 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 01:20:52.478195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 01:20:52.478296 ==
1002 01:20:52.478390
1003 01:20:52.481489
1004 01:20:52.481574 TX Vref Scan disable
1005 01:20:52.485082 == TX Byte 0 ==
1006 01:20:52.488022 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1007 01:20:52.491879 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1008 01:20:52.495114 == TX Byte 1 ==
1009 01:20:52.498187 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1010 01:20:52.501463 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1011 01:20:52.501548
1012 01:20:52.505181 [DATLAT]
1013 01:20:52.505265 Freq=800, CH0 RK0
1014 01:20:52.505331
1015 01:20:52.508124 DATLAT Default: 0xa
1016 01:20:52.508209 0, 0xFFFF, sum = 0
1017 01:20:52.511808 1, 0xFFFF, sum = 0
1018 01:20:52.511897 2, 0xFFFF, sum = 0
1019 01:20:52.514926 3, 0xFFFF, sum = 0
1020 01:20:52.515010 4, 0xFFFF, sum = 0
1021 01:20:52.518493 5, 0xFFFF, sum = 0
1022 01:20:52.518620 6, 0xFFFF, sum = 0
1023 01:20:52.521624 7, 0xFFFF, sum = 0
1024 01:20:52.524919 8, 0xFFFF, sum = 0
1025 01:20:52.525011 9, 0x0, sum = 1
1026 01:20:52.525079 10, 0x0, sum = 2
1027 01:20:52.528161 11, 0x0, sum = 3
1028 01:20:52.528245 12, 0x0, sum = 4
1029 01:20:52.531790 best_step = 10
1030 01:20:52.531872
1031 01:20:52.531936 ==
1032 01:20:52.534799 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 01:20:52.538296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 01:20:52.538403 ==
1035 01:20:52.541264 RX Vref Scan: 1
1036 01:20:52.541346
1037 01:20:52.541411 Set Vref Range= 32 -> 127
1038 01:20:52.541474
1039 01:20:52.544914 RX Vref 32 -> 127, step: 1
1040 01:20:52.544997
1041 01:20:52.548438 RX Delay -79 -> 252, step: 8
1042 01:20:52.548521
1043 01:20:52.551711 Set Vref, RX VrefLevel [Byte0]: 32
1044 01:20:52.555545 [Byte1]: 32
1045 01:20:52.555627
1046 01:20:52.558540 Set Vref, RX VrefLevel [Byte0]: 33
1047 01:20:52.561522 [Byte1]: 33
1048 01:20:52.565363
1049 01:20:52.565445 Set Vref, RX VrefLevel [Byte0]: 34
1050 01:20:52.568414 [Byte1]: 34
1051 01:20:52.572824
1052 01:20:52.572907 Set Vref, RX VrefLevel [Byte0]: 35
1053 01:20:52.575902 [Byte1]: 35
1054 01:20:52.580377
1055 01:20:52.580459 Set Vref, RX VrefLevel [Byte0]: 36
1056 01:20:52.583772 [Byte1]: 36
1057 01:20:52.588426
1058 01:20:52.588511 Set Vref, RX VrefLevel [Byte0]: 37
1059 01:20:52.591845 [Byte1]: 37
1060 01:20:52.596082
1061 01:20:52.596167 Set Vref, RX VrefLevel [Byte0]: 38
1062 01:20:52.599253 [Byte1]: 38
1063 01:20:52.603019
1064 01:20:52.603103 Set Vref, RX VrefLevel [Byte0]: 39
1065 01:20:52.606011 [Byte1]: 39
1066 01:20:52.610681
1067 01:20:52.610765 Set Vref, RX VrefLevel [Byte0]: 40
1068 01:20:52.613822 [Byte1]: 40
1069 01:20:52.618571
1070 01:20:52.618681 Set Vref, RX VrefLevel [Byte0]: 41
1071 01:20:52.621711 [Byte1]: 41
1072 01:20:52.625532
1073 01:20:52.625649 Set Vref, RX VrefLevel [Byte0]: 42
1074 01:20:52.628883 [Byte1]: 42
1075 01:20:52.632727
1076 01:20:52.632810 Set Vref, RX VrefLevel [Byte0]: 43
1077 01:20:52.636462 [Byte1]: 43
1078 01:20:52.640741
1079 01:20:52.640858 Set Vref, RX VrefLevel [Byte0]: 44
1080 01:20:52.643986 [Byte1]: 44
1081 01:20:52.648107
1082 01:20:52.648189 Set Vref, RX VrefLevel [Byte0]: 45
1083 01:20:52.651561 [Byte1]: 45
1084 01:20:52.655652
1085 01:20:52.655734 Set Vref, RX VrefLevel [Byte0]: 46
1086 01:20:52.658840 [Byte1]: 46
1087 01:20:52.662985
1088 01:20:52.663067 Set Vref, RX VrefLevel [Byte0]: 47
1089 01:20:52.666678 [Byte1]: 47
1090 01:20:52.670356
1091 01:20:52.670440 Set Vref, RX VrefLevel [Byte0]: 48
1092 01:20:52.674037 [Byte1]: 48
1093 01:20:52.678175
1094 01:20:52.678257 Set Vref, RX VrefLevel [Byte0]: 49
1095 01:20:52.681724 [Byte1]: 49
1096 01:20:52.686071
1097 01:20:52.686154 Set Vref, RX VrefLevel [Byte0]: 50
1098 01:20:52.689693 [Byte1]: 50
1099 01:20:52.693317
1100 01:20:52.693400 Set Vref, RX VrefLevel [Byte0]: 51
1101 01:20:52.696815 [Byte1]: 51
1102 01:20:52.700881
1103 01:20:52.700965 Set Vref, RX VrefLevel [Byte0]: 52
1104 01:20:52.704341 [Byte1]: 52
1105 01:20:52.708872
1106 01:20:52.708956 Set Vref, RX VrefLevel [Byte0]: 53
1107 01:20:52.712043 [Byte1]: 53
1108 01:20:52.715824
1109 01:20:52.715906 Set Vref, RX VrefLevel [Byte0]: 54
1110 01:20:52.719690 [Byte1]: 54
1111 01:20:52.723779
1112 01:20:52.723861 Set Vref, RX VrefLevel [Byte0]: 55
1113 01:20:52.726715 [Byte1]: 55
1114 01:20:52.730758
1115 01:20:52.730841 Set Vref, RX VrefLevel [Byte0]: 56
1116 01:20:52.734501 [Byte1]: 56
1117 01:20:52.738377
1118 01:20:52.738460 Set Vref, RX VrefLevel [Byte0]: 57
1119 01:20:52.741735 [Byte1]: 57
1120 01:20:52.746336
1121 01:20:52.746420 Set Vref, RX VrefLevel [Byte0]: 58
1122 01:20:52.749238 [Byte1]: 58
1123 01:20:52.753859
1124 01:20:52.753942 Set Vref, RX VrefLevel [Byte0]: 59
1125 01:20:52.757004 [Byte1]: 59
1126 01:20:52.761236
1127 01:20:52.761318 Set Vref, RX VrefLevel [Byte0]: 60
1128 01:20:52.764541 [Byte1]: 60
1129 01:20:52.768520
1130 01:20:52.768602 Set Vref, RX VrefLevel [Byte0]: 61
1131 01:20:52.772138 [Byte1]: 61
1132 01:20:52.776183
1133 01:20:52.776265 Set Vref, RX VrefLevel [Byte0]: 62
1134 01:20:52.779389 [Byte1]: 62
1135 01:20:52.783753
1136 01:20:52.783836 Set Vref, RX VrefLevel [Byte0]: 63
1137 01:20:52.786920 [Byte1]: 63
1138 01:20:52.791473
1139 01:20:52.791556 Set Vref, RX VrefLevel [Byte0]: 64
1140 01:20:52.794684 [Byte1]: 64
1141 01:20:52.798996
1142 01:20:52.799162 Set Vref, RX VrefLevel [Byte0]: 65
1143 01:20:52.802599 [Byte1]: 65
1144 01:20:52.806930
1145 01:20:52.807013 Set Vref, RX VrefLevel [Byte0]: 66
1146 01:20:52.809691 [Byte1]: 66
1147 01:20:52.814040
1148 01:20:52.814122 Set Vref, RX VrefLevel [Byte0]: 67
1149 01:20:52.817506 [Byte1]: 67
1150 01:20:52.821871
1151 01:20:52.821954 Set Vref, RX VrefLevel [Byte0]: 68
1152 01:20:52.824889 [Byte1]: 68
1153 01:20:52.829363
1154 01:20:52.829448 Set Vref, RX VrefLevel [Byte0]: 69
1155 01:20:52.832373 [Byte1]: 69
1156 01:20:52.836724
1157 01:20:52.836807 Set Vref, RX VrefLevel [Byte0]: 70
1158 01:20:52.840102 [Byte1]: 70
1159 01:20:52.844664
1160 01:20:52.844747 Set Vref, RX VrefLevel [Byte0]: 71
1161 01:20:52.847823 [Byte1]: 71
1162 01:20:52.851699
1163 01:20:52.851782 Set Vref, RX VrefLevel [Byte0]: 72
1164 01:20:52.855440 [Byte1]: 72
1165 01:20:52.859187
1166 01:20:52.859269 Set Vref, RX VrefLevel [Byte0]: 73
1167 01:20:52.862607 [Byte1]: 73
1168 01:20:52.866981
1169 01:20:52.867062 Set Vref, RX VrefLevel [Byte0]: 74
1170 01:20:52.870308 [Byte1]: 74
1171 01:20:52.874721
1172 01:20:52.874803 Set Vref, RX VrefLevel [Byte0]: 75
1173 01:20:52.877928 [Byte1]: 75
1174 01:20:52.881851
1175 01:20:52.881932 Set Vref, RX VrefLevel [Byte0]: 76
1176 01:20:52.885581 [Byte1]: 76
1177 01:20:52.889298
1178 01:20:52.889380 Set Vref, RX VrefLevel [Byte0]: 77
1179 01:20:52.893249 [Byte1]: 77
1180 01:20:52.897432
1181 01:20:52.897513 Set Vref, RX VrefLevel [Byte0]: 78
1182 01:20:52.900399 [Byte1]: 78
1183 01:20:52.904886
1184 01:20:52.904968 Final RX Vref Byte 0 = 49 to rank0
1185 01:20:52.908016 Final RX Vref Byte 1 = 66 to rank0
1186 01:20:52.911728 Final RX Vref Byte 0 = 49 to rank1
1187 01:20:52.914901 Final RX Vref Byte 1 = 66 to rank1==
1188 01:20:52.918053 Dram Type= 6, Freq= 0, CH_0, rank 0
1189 01:20:52.921386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1190 01:20:52.924548 ==
1191 01:20:52.924630 DQS Delay:
1192 01:20:52.924695 DQS0 = 0, DQS1 = 0
1193 01:20:52.928241 DQM Delay:
1194 01:20:52.928324 DQM0 = 91, DQM1 = 85
1195 01:20:52.931661 DQ Delay:
1196 01:20:52.934568 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =88
1197 01:20:52.938008 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1198 01:20:52.941348 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1199 01:20:52.944580 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1200 01:20:52.944661
1201 01:20:52.944725
1202 01:20:52.951520 [DQSOSCAuto] RK0, (LSB)MR18= 0x493f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1203 01:20:52.955133 CH0 RK0: MR19=606, MR18=493F
1204 01:20:52.961272 CH0_RK0: MR19=0x606, MR18=0x493F, DQSOSC=391, MR23=63, INC=96, DEC=64
1205 01:20:52.961365
1206 01:20:52.964953 ----->DramcWriteLeveling(PI) begin...
1207 01:20:52.965030 ==
1208 01:20:52.968116 Dram Type= 6, Freq= 0, CH_0, rank 1
1209 01:20:52.971273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1210 01:20:52.971356 ==
1211 01:20:52.974635 Write leveling (Byte 0): 36 => 36
1212 01:20:52.977729 Write leveling (Byte 1): 31 => 31
1213 01:20:52.981646 DramcWriteLeveling(PI) end<-----
1214 01:20:52.981727
1215 01:20:52.981791 ==
1216 01:20:52.984773 Dram Type= 6, Freq= 0, CH_0, rank 1
1217 01:20:52.988086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1218 01:20:52.988168 ==
1219 01:20:53.031730 [Gating] SW mode calibration
1220 01:20:53.031865 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1221 01:20:53.032128 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1222 01:20:53.032890 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1223 01:20:53.033155 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1224 01:20:53.033227 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1225 01:20:53.033810 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 01:20:53.034392 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 01:20:53.034670 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 01:20:53.073325 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 01:20:53.073475 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 01:20:53.073802 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 01:20:53.073890 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 01:20:53.073966 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 01:20:53.074220 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 01:20:53.074335 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 01:20:53.074596 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 01:20:53.075089 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 01:20:53.077729 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 01:20:53.080978 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 01:20:53.084296 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 01:20:53.087640 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1241 01:20:53.091100 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 01:20:53.094546 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 01:20:53.100846 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 01:20:53.104707 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 01:20:53.107875 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 01:20:53.114223 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 01:20:53.117902 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 01:20:53.121474 0 9 8 | B1->B0 | 2e2e 2929 | 1 1 | (1 1) (1 1)
1249 01:20:53.127855 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 01:20:53.131748 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 01:20:53.134893 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 01:20:53.141174 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 01:20:53.144487 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 01:20:53.147923 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 01:20:53.154797 0 10 4 | B1->B0 | 3131 3333 | 0 0 | (0 0) (0 0)
1256 01:20:53.157847 0 10 8 | B1->B0 | 2a2a 2d2d | 0 0 | (0 0) (0 1)
1257 01:20:53.161243 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 01:20:53.165029 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 01:20:53.172533 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 01:20:53.176270 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 01:20:53.180204 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 01:20:53.183333 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 01:20:53.190155 0 11 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1264 01:20:53.193451 0 11 8 | B1->B0 | 3e3e 3636 | 0 0 | (0 0) (0 0)
1265 01:20:53.196730 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 01:20:53.200435 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 01:20:53.206650 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 01:20:53.210239 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 01:20:53.213748 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 01:20:53.220217 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 01:20:53.223829 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 01:20:53.226654 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1273 01:20:53.233383 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 01:20:53.237140 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 01:20:53.240272 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 01:20:53.246682 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 01:20:53.250241 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 01:20:53.253800 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 01:20:53.259969 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 01:20:53.263598 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 01:20:53.266830 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 01:20:53.270187 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 01:20:53.277204 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 01:20:53.280215 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 01:20:53.283555 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 01:20:53.290763 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 01:20:53.293949 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 01:20:53.297019 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1289 01:20:53.303783 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1290 01:20:53.303878 Total UI for P1: 0, mck2ui 16
1291 01:20:53.310653 best dqsien dly found for B0: ( 0, 14, 8)
1292 01:20:53.310741 Total UI for P1: 0, mck2ui 16
1293 01:20:53.317492 best dqsien dly found for B1: ( 0, 14, 8)
1294 01:20:53.320495 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1295 01:20:53.323998 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1296 01:20:53.324080
1297 01:20:53.327027 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1298 01:20:53.330143 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1299 01:20:53.333603 [Gating] SW calibration Done
1300 01:20:53.333687 ==
1301 01:20:53.336687 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 01:20:53.340270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 01:20:53.340353 ==
1304 01:20:53.343627 RX Vref Scan: 0
1305 01:20:53.343708
1306 01:20:53.343771 RX Vref 0 -> 0, step: 1
1307 01:20:53.343830
1308 01:20:53.347218 RX Delay -130 -> 252, step: 16
1309 01:20:53.350390 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1310 01:20:53.357136 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1311 01:20:53.360056 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1312 01:20:53.363715 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1313 01:20:53.366768 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1314 01:20:53.370147 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1315 01:20:53.377137 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1316 01:20:53.380258 iDelay=206, Bit 7, Center 101 (-2 ~ 205) 208
1317 01:20:53.383358 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1318 01:20:53.387105 iDelay=206, Bit 9, Center 69 (-34 ~ 173) 208
1319 01:20:53.390306 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1320 01:20:53.393701 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1321 01:20:53.400741 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1322 01:20:53.403747 iDelay=206, Bit 13, Center 77 (-34 ~ 189) 224
1323 01:20:53.407507 iDelay=206, Bit 14, Center 101 (-2 ~ 205) 208
1324 01:20:53.410657 iDelay=206, Bit 15, Center 85 (-18 ~ 189) 208
1325 01:20:53.410741 ==
1326 01:20:53.414166 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 01:20:53.420473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 01:20:53.420566 ==
1329 01:20:53.420630 DQS Delay:
1330 01:20:53.423588 DQS0 = 0, DQS1 = 0
1331 01:20:53.423670 DQM Delay:
1332 01:20:53.423733 DQM0 = 90, DQM1 = 81
1333 01:20:53.427449 DQ Delay:
1334 01:20:53.430386 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
1335 01:20:53.434146 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1336 01:20:53.437241 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1337 01:20:53.440331 DQ12 =85, DQ13 =77, DQ14 =101, DQ15 =85
1338 01:20:53.440415
1339 01:20:53.440478
1340 01:20:53.440536 ==
1341 01:20:53.443554 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 01:20:53.447327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 01:20:53.447410 ==
1344 01:20:53.447474
1345 01:20:53.447533
1346 01:20:53.450209 TX Vref Scan disable
1347 01:20:53.453529 == TX Byte 0 ==
1348 01:20:53.457436 Update DQ dly =587 (2 ,2, 11) DQ OEN =(1 ,7)
1349 01:20:53.460126 Update DQM dly =587 (2 ,2, 11) DQM OEN =(1 ,7)
1350 01:20:53.463899 == TX Byte 1 ==
1351 01:20:53.467462 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1352 01:20:53.470331 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1353 01:20:53.470428 ==
1354 01:20:53.473432 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 01:20:53.477066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 01:20:53.477149 ==
1357 01:20:53.492273 TX Vref=22, minBit 8, minWin=27, winSum=447
1358 01:20:53.495720 TX Vref=24, minBit 8, minWin=27, winSum=449
1359 01:20:53.498549 TX Vref=26, minBit 1, minWin=28, winSum=456
1360 01:20:53.502162 TX Vref=28, minBit 4, minWin=28, winSum=458
1361 01:20:53.505320 TX Vref=30, minBit 7, minWin=28, winSum=458
1362 01:20:53.508452 TX Vref=32, minBit 1, minWin=28, winSum=451
1363 01:20:53.515307 [TxChooseVref] Worse bit 4, Min win 28, Win sum 458, Final Vref 28
1364 01:20:53.515401
1365 01:20:53.518592 Final TX Range 1 Vref 28
1366 01:20:53.518689
1367 01:20:53.518764 ==
1368 01:20:53.521692 Dram Type= 6, Freq= 0, CH_0, rank 1
1369 01:20:53.525422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 01:20:53.525506 ==
1371 01:20:53.525569
1372 01:20:53.528418
1373 01:20:53.528519 TX Vref Scan disable
1374 01:20:53.532217 == TX Byte 0 ==
1375 01:20:53.535345 Update DQ dly =587 (2 ,2, 11) DQ OEN =(1 ,7)
1376 01:20:53.538383 Update DQM dly =587 (2 ,2, 11) DQM OEN =(1 ,7)
1377 01:20:53.542184 == TX Byte 1 ==
1378 01:20:53.545130 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1379 01:20:53.548437 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1380 01:20:53.551712
1381 01:20:53.551793 [DATLAT]
1382 01:20:53.551855 Freq=800, CH0 RK1
1383 01:20:53.551913
1384 01:20:53.555309 DATLAT Default: 0xa
1385 01:20:53.555389 0, 0xFFFF, sum = 0
1386 01:20:53.558697 1, 0xFFFF, sum = 0
1387 01:20:53.558779 2, 0xFFFF, sum = 0
1388 01:20:53.561722 3, 0xFFFF, sum = 0
1389 01:20:53.561802 4, 0xFFFF, sum = 0
1390 01:20:53.564993 5, 0xFFFF, sum = 0
1391 01:20:53.568284 6, 0xFFFF, sum = 0
1392 01:20:53.568364 7, 0xFFFF, sum = 0
1393 01:20:53.572004 8, 0xFFFF, sum = 0
1394 01:20:53.572086 9, 0x0, sum = 1
1395 01:20:53.572150 10, 0x0, sum = 2
1396 01:20:53.575223 11, 0x0, sum = 3
1397 01:20:53.575308 12, 0x0, sum = 4
1398 01:20:53.578564 best_step = 10
1399 01:20:53.578643
1400 01:20:53.578706 ==
1401 01:20:53.582118 Dram Type= 6, Freq= 0, CH_0, rank 1
1402 01:20:53.585444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1403 01:20:53.585527 ==
1404 01:20:53.588468 RX Vref Scan: 0
1405 01:20:53.588546
1406 01:20:53.588608 RX Vref 0 -> 0, step: 1
1407 01:20:53.588667
1408 01:20:53.592027 RX Delay -79 -> 252, step: 8
1409 01:20:53.598745 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1410 01:20:53.601882 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1411 01:20:53.605149 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1412 01:20:53.608771 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
1413 01:20:53.611983 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1414 01:20:53.618326 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1415 01:20:53.621817 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
1416 01:20:53.625060 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1417 01:20:53.628739 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1418 01:20:53.631744 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1419 01:20:53.638684 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
1420 01:20:53.641792 iDelay=209, Bit 11, Center 72 (-31 ~ 176) 208
1421 01:20:53.645583 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1422 01:20:53.648527 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1423 01:20:53.651708 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1424 01:20:53.658806 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1425 01:20:53.658892 ==
1426 01:20:53.662023 Dram Type= 6, Freq= 0, CH_0, rank 1
1427 01:20:53.665253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1428 01:20:53.665333 ==
1429 01:20:53.665397 DQS Delay:
1430 01:20:53.668492 DQS0 = 0, DQS1 = 0
1431 01:20:53.668572 DQM Delay:
1432 01:20:53.671698 DQM0 = 92, DQM1 = 82
1433 01:20:53.671778 DQ Delay:
1434 01:20:53.675703 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =92
1435 01:20:53.678940 DQ4 =96, DQ5 =84, DQ6 =96, DQ7 =100
1436 01:20:53.681562 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =72
1437 01:20:53.685531 DQ12 =92, DQ13 =84, DQ14 =92, DQ15 =88
1438 01:20:53.685611
1439 01:20:53.685673
1440 01:20:53.691892 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f0f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
1441 01:20:53.694983 CH0 RK1: MR19=606, MR18=3F0F
1442 01:20:53.701618 CH0_RK1: MR19=0x606, MR18=0x3F0F, DQSOSC=393, MR23=63, INC=95, DEC=63
1443 01:20:53.705086 [RxdqsGatingPostProcess] freq 800
1444 01:20:53.711594 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1445 01:20:53.715495 Pre-setting of DQS Precalculation
1446 01:20:53.718838 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1447 01:20:53.718922 ==
1448 01:20:53.721850 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 01:20:53.725168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1450 01:20:53.725250 ==
1451 01:20:53.731984 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1452 01:20:53.738467 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1453 01:20:53.747233 [CA 0] Center 36 (6~67) winsize 62
1454 01:20:53.750202 [CA 1] Center 36 (6~67) winsize 62
1455 01:20:53.753417 [CA 2] Center 34 (4~65) winsize 62
1456 01:20:53.756683 [CA 3] Center 34 (4~65) winsize 62
1457 01:20:53.760471 [CA 4] Center 34 (4~65) winsize 62
1458 01:20:53.763597 [CA 5] Center 34 (4~65) winsize 62
1459 01:20:53.763677
1460 01:20:53.766786 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1461 01:20:53.766868
1462 01:20:53.769952 [CATrainingPosCal] consider 1 rank data
1463 01:20:53.773182 u2DelayCellTimex100 = 270/100 ps
1464 01:20:53.777089 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1465 01:20:53.780747 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1466 01:20:53.787179 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1467 01:20:53.790556 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1468 01:20:53.793336 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1469 01:20:53.796845 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1470 01:20:53.796928
1471 01:20:53.800164 CA PerBit enable=1, Macro0, CA PI delay=34
1472 01:20:53.800264
1473 01:20:53.803703 [CBTSetCACLKResult] CA Dly = 34
1474 01:20:53.803785 CS Dly: 5 (0~36)
1475 01:20:53.803849 ==
1476 01:20:53.806856 Dram Type= 6, Freq= 0, CH_1, rank 1
1477 01:20:53.813882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1478 01:20:53.813967 ==
1479 01:20:53.816907 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1480 01:20:53.823870 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1481 01:20:53.833422 [CA 0] Center 37 (6~68) winsize 63
1482 01:20:53.836956 [CA 1] Center 37 (6~68) winsize 63
1483 01:20:53.840671 [CA 2] Center 35 (4~66) winsize 63
1484 01:20:53.844372 [CA 3] Center 34 (4~65) winsize 62
1485 01:20:53.848294 [CA 4] Center 35 (5~65) winsize 61
1486 01:20:53.851787 [CA 5] Center 34 (4~65) winsize 62
1487 01:20:53.851871
1488 01:20:53.855309 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1489 01:20:53.855391
1490 01:20:53.859262 [CATrainingPosCal] consider 2 rank data
1491 01:20:53.859346 u2DelayCellTimex100 = 270/100 ps
1492 01:20:53.863077 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1493 01:20:53.866233 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1494 01:20:53.873090 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1495 01:20:53.876384 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1496 01:20:53.879623 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1497 01:20:53.882817 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1498 01:20:53.882897
1499 01:20:53.886122 CA PerBit enable=1, Macro0, CA PI delay=34
1500 01:20:53.886203
1501 01:20:53.889981 [CBTSetCACLKResult] CA Dly = 34
1502 01:20:53.890061 CS Dly: 6 (0~38)
1503 01:20:53.890125
1504 01:20:53.892995 ----->DramcWriteLeveling(PI) begin...
1505 01:20:53.896532 ==
1506 01:20:53.896612 Dram Type= 6, Freq= 0, CH_1, rank 0
1507 01:20:53.903398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1508 01:20:53.903484 ==
1509 01:20:53.906771 Write leveling (Byte 0): 25 => 25
1510 01:20:53.909341 Write leveling (Byte 1): 27 => 27
1511 01:20:53.912853 DramcWriteLeveling(PI) end<-----
1512 01:20:53.912950
1513 01:20:53.913015 ==
1514 01:20:53.916874 Dram Type= 6, Freq= 0, CH_1, rank 0
1515 01:20:53.920016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1516 01:20:53.920124 ==
1517 01:20:53.923328 [Gating] SW mode calibration
1518 01:20:53.930134 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1519 01:20:53.933605 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1520 01:20:53.940036 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1521 01:20:53.943634 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1522 01:20:53.946964 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 01:20:53.954191 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 01:20:53.956711 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 01:20:53.959847 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 01:20:53.966899 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 01:20:53.969805 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 01:20:53.973119 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 01:20:53.976524 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 01:20:53.983167 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 01:20:53.986440 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 01:20:53.989961 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 01:20:53.996817 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 01:20:53.999860 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 01:20:54.003540 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 01:20:54.009745 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 01:20:54.013850 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1538 01:20:54.016763 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 01:20:54.023542 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 01:20:54.026743 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 01:20:54.029963 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 01:20:54.036983 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 01:20:54.039969 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 01:20:54.043682 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 01:20:54.050002 0 9 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
1546 01:20:54.053211 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1547 01:20:54.087938 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 01:20:54.088096 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 01:20:54.088161 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 01:20:54.088222 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 01:20:54.088281 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 01:20:54.088338 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1553 01:20:54.088409 0 10 4 | B1->B0 | 3434 2d2d | 1 1 | (0 1) (0 1)
1554 01:20:54.088467 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1555 01:20:54.093043 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 01:20:54.096595 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 01:20:54.099681 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 01:20:54.106651 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 01:20:54.109976 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 01:20:54.113683 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 01:20:54.120149 0 11 4 | B1->B0 | 2d2d 3939 | 0 1 | (0 0) (0 0)
1562 01:20:54.123141 0 11 8 | B1->B0 | 3c3c 4545 | 0 0 | (0 0) (0 0)
1563 01:20:54.126662 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 01:20:54.133659 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 01:20:54.136820 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 01:20:54.140168 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 01:20:54.146740 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 01:20:54.149915 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 01:20:54.153103 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1570 01:20:54.160310 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 01:20:54.163768 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 01:20:54.166793 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 01:20:54.169931 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 01:20:54.176638 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 01:20:54.180484 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 01:20:54.183623 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 01:20:54.189802 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 01:20:54.193607 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 01:20:54.196975 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 01:20:54.203136 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 01:20:54.206566 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 01:20:54.210249 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 01:20:54.217301 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 01:20:54.220452 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 01:20:54.223768 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1586 01:20:54.226757 Total UI for P1: 0, mck2ui 16
1587 01:20:54.230110 best dqsien dly found for B0: ( 0, 14, 2)
1588 01:20:54.232978 Total UI for P1: 0, mck2ui 16
1589 01:20:54.236707 best dqsien dly found for B1: ( 0, 14, 2)
1590 01:20:54.239887 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1591 01:20:54.243459 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1592 01:20:54.243544
1593 01:20:54.246816 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1594 01:20:54.253382 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1595 01:20:54.253463 [Gating] SW calibration Done
1596 01:20:54.253534 ==
1597 01:20:54.256748 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 01:20:54.262914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 01:20:54.263000 ==
1600 01:20:54.263065 RX Vref Scan: 0
1601 01:20:54.263124
1602 01:20:54.266634 RX Vref 0 -> 0, step: 1
1603 01:20:54.266719
1604 01:20:54.269795 RX Delay -130 -> 252, step: 16
1605 01:20:54.273540 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1606 01:20:54.276520 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1607 01:20:54.279936 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1608 01:20:54.286456 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1609 01:20:54.289818 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1610 01:20:54.293768 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1611 01:20:54.296792 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1612 01:20:54.299938 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1613 01:20:54.303646 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1614 01:20:54.309934 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1615 01:20:54.313403 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1616 01:20:54.317204 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1617 01:20:54.320258 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1618 01:20:54.327171 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1619 01:20:54.330422 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1620 01:20:54.333811 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1621 01:20:54.333895 ==
1622 01:20:54.337124 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 01:20:54.340321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 01:20:54.340404 ==
1625 01:20:54.343643 DQS Delay:
1626 01:20:54.343725 DQS0 = 0, DQS1 = 0
1627 01:20:54.343789 DQM Delay:
1628 01:20:54.346815 DQM0 = 92, DQM1 = 87
1629 01:20:54.346908 DQ Delay:
1630 01:20:54.350538 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1631 01:20:54.353794 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1632 01:20:54.356810 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1633 01:20:54.360504 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1634 01:20:54.360577
1635 01:20:54.360639
1636 01:20:54.360696 ==
1637 01:20:54.363743 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 01:20:54.370125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 01:20:54.370200 ==
1640 01:20:54.370262
1641 01:20:54.370344
1642 01:20:54.370402 TX Vref Scan disable
1643 01:20:54.373759 == TX Byte 0 ==
1644 01:20:54.377500 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1645 01:20:54.383992 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1646 01:20:54.384074 == TX Byte 1 ==
1647 01:20:54.387079 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1648 01:20:54.393917 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1649 01:20:54.393999 ==
1650 01:20:54.397447 Dram Type= 6, Freq= 0, CH_1, rank 0
1651 01:20:54.400476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1652 01:20:54.400558 ==
1653 01:20:54.413053 TX Vref=22, minBit 1, minWin=26, winSum=438
1654 01:20:54.416613 TX Vref=24, minBit 1, minWin=26, winSum=444
1655 01:20:54.420512 TX Vref=26, minBit 1, minWin=27, winSum=444
1656 01:20:54.423439 TX Vref=28, minBit 3, minWin=27, winSum=445
1657 01:20:54.426563 TX Vref=30, minBit 0, minWin=27, winSum=449
1658 01:20:54.429740 TX Vref=32, minBit 0, minWin=27, winSum=444
1659 01:20:54.436897 [TxChooseVref] Worse bit 0, Min win 27, Win sum 449, Final Vref 30
1660 01:20:54.436983
1661 01:20:54.440206 Final TX Range 1 Vref 30
1662 01:20:54.440289
1663 01:20:54.440353 ==
1664 01:20:54.443266 Dram Type= 6, Freq= 0, CH_1, rank 0
1665 01:20:54.446485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1666 01:20:54.446567 ==
1667 01:20:54.446631
1668 01:20:54.446691
1669 01:20:54.450023 TX Vref Scan disable
1670 01:20:54.453342 == TX Byte 0 ==
1671 01:20:54.456899 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1672 01:20:54.459943 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1673 01:20:54.463591 == TX Byte 1 ==
1674 01:20:54.467350 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1675 01:20:54.470450 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1676 01:20:54.470532
1677 01:20:54.473513 [DATLAT]
1678 01:20:54.473594 Freq=800, CH1 RK0
1679 01:20:54.473659
1680 01:20:54.476785 DATLAT Default: 0xa
1681 01:20:54.476866 0, 0xFFFF, sum = 0
1682 01:20:54.479913 1, 0xFFFF, sum = 0
1683 01:20:54.479995 2, 0xFFFF, sum = 0
1684 01:20:54.483636 3, 0xFFFF, sum = 0
1685 01:20:54.483721 4, 0xFFFF, sum = 0
1686 01:20:54.486997 5, 0xFFFF, sum = 0
1687 01:20:54.487079 6, 0xFFFF, sum = 0
1688 01:20:54.490091 7, 0xFFFF, sum = 0
1689 01:20:54.490172 8, 0xFFFF, sum = 0
1690 01:20:54.493662 9, 0x0, sum = 1
1691 01:20:54.493770 10, 0x0, sum = 2
1692 01:20:54.496842 11, 0x0, sum = 3
1693 01:20:54.496924 12, 0x0, sum = 4
1694 01:20:54.499947 best_step = 10
1695 01:20:54.500052
1696 01:20:54.500143 ==
1697 01:20:54.503163 Dram Type= 6, Freq= 0, CH_1, rank 0
1698 01:20:54.506445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1699 01:20:54.506527 ==
1700 01:20:54.509959 RX Vref Scan: 1
1701 01:20:54.510040
1702 01:20:54.510103 Set Vref Range= 32 -> 127
1703 01:20:54.510163
1704 01:20:54.513456 RX Vref 32 -> 127, step: 1
1705 01:20:54.513537
1706 01:20:54.516697 RX Delay -79 -> 252, step: 8
1707 01:20:54.516779
1708 01:20:54.520014 Set Vref, RX VrefLevel [Byte0]: 32
1709 01:20:54.523398 [Byte1]: 32
1710 01:20:54.523484
1711 01:20:54.526686 Set Vref, RX VrefLevel [Byte0]: 33
1712 01:20:54.529771 [Byte1]: 33
1713 01:20:54.529871
1714 01:20:54.533670 Set Vref, RX VrefLevel [Byte0]: 34
1715 01:20:54.536397 [Byte1]: 34
1716 01:20:54.540570
1717 01:20:54.540651 Set Vref, RX VrefLevel [Byte0]: 35
1718 01:20:54.543779 [Byte1]: 35
1719 01:20:54.548257
1720 01:20:54.548338 Set Vref, RX VrefLevel [Byte0]: 36
1721 01:20:54.551879 [Byte1]: 36
1722 01:20:54.555723
1723 01:20:54.555804 Set Vref, RX VrefLevel [Byte0]: 37
1724 01:20:54.558961 [Byte1]: 37
1725 01:20:54.563300
1726 01:20:54.563381 Set Vref, RX VrefLevel [Byte0]: 38
1727 01:20:54.566347 [Byte1]: 38
1728 01:20:54.571049
1729 01:20:54.571130 Set Vref, RX VrefLevel [Byte0]: 39
1730 01:20:54.573897 [Byte1]: 39
1731 01:20:54.578480
1732 01:20:54.578561 Set Vref, RX VrefLevel [Byte0]: 40
1733 01:20:54.581409 [Byte1]: 40
1734 01:20:54.585754
1735 01:20:54.585835 Set Vref, RX VrefLevel [Byte0]: 41
1736 01:20:54.589065 [Byte1]: 41
1737 01:20:54.593619
1738 01:20:54.593701 Set Vref, RX VrefLevel [Byte0]: 42
1739 01:20:54.596658 [Byte1]: 42
1740 01:20:54.600846
1741 01:20:54.600944 Set Vref, RX VrefLevel [Byte0]: 43
1742 01:20:54.604760 [Byte1]: 43
1743 01:20:54.608389
1744 01:20:54.608470 Set Vref, RX VrefLevel [Byte0]: 44
1745 01:20:54.612129 [Byte1]: 44
1746 01:20:54.616114
1747 01:20:54.616196 Set Vref, RX VrefLevel [Byte0]: 45
1748 01:20:54.619104 [Byte1]: 45
1749 01:20:54.623324
1750 01:20:54.623440 Set Vref, RX VrefLevel [Byte0]: 46
1751 01:20:54.627039 [Byte1]: 46
1752 01:20:54.630919
1753 01:20:54.631035 Set Vref, RX VrefLevel [Byte0]: 47
1754 01:20:54.634704 [Byte1]: 47
1755 01:20:54.638897
1756 01:20:54.639013 Set Vref, RX VrefLevel [Byte0]: 48
1757 01:20:54.642058 [Byte1]: 48
1758 01:20:54.646189
1759 01:20:54.646313 Set Vref, RX VrefLevel [Byte0]: 49
1760 01:20:54.649608 [Byte1]: 49
1761 01:20:54.653750
1762 01:20:54.653861 Set Vref, RX VrefLevel [Byte0]: 50
1763 01:20:54.657113 [Byte1]: 50
1764 01:20:54.661606
1765 01:20:54.661718 Set Vref, RX VrefLevel [Byte0]: 51
1766 01:20:54.664665 [Byte1]: 51
1767 01:20:54.668667
1768 01:20:54.668781 Set Vref, RX VrefLevel [Byte0]: 52
1769 01:20:54.672547 [Byte1]: 52
1770 01:20:54.676235
1771 01:20:54.676346 Set Vref, RX VrefLevel [Byte0]: 53
1772 01:20:54.679606 [Byte1]: 53
1773 01:20:54.683828
1774 01:20:54.683938 Set Vref, RX VrefLevel [Byte0]: 54
1775 01:20:54.687310 [Byte1]: 54
1776 01:20:54.691380
1777 01:20:54.691490 Set Vref, RX VrefLevel [Byte0]: 55
1778 01:20:54.695062 [Byte1]: 55
1779 01:20:54.699226
1780 01:20:54.699336 Set Vref, RX VrefLevel [Byte0]: 56
1781 01:20:54.702177 [Byte1]: 56
1782 01:20:54.706449
1783 01:20:54.706559 Set Vref, RX VrefLevel [Byte0]: 57
1784 01:20:54.710247 [Byte1]: 57
1785 01:20:54.713937
1786 01:20:54.714047 Set Vref, RX VrefLevel [Byte0]: 58
1787 01:20:54.717322 [Byte1]: 58
1788 01:20:54.721693
1789 01:20:54.721804 Set Vref, RX VrefLevel [Byte0]: 59
1790 01:20:54.725262 [Byte1]: 59
1791 01:20:54.729240
1792 01:20:54.729353 Set Vref, RX VrefLevel [Byte0]: 60
1793 01:20:54.732917 [Byte1]: 60
1794 01:20:54.736736
1795 01:20:54.736847 Set Vref, RX VrefLevel [Byte0]: 61
1796 01:20:54.740048 [Byte1]: 61
1797 01:20:54.744467
1798 01:20:54.744577 Set Vref, RX VrefLevel [Byte0]: 62
1799 01:20:54.747584 [Byte1]: 62
1800 01:20:54.752132
1801 01:20:54.752241 Set Vref, RX VrefLevel [Byte0]: 63
1802 01:20:54.755595 [Byte1]: 63
1803 01:20:54.759492
1804 01:20:54.759603 Set Vref, RX VrefLevel [Byte0]: 64
1805 01:20:54.762943 [Byte1]: 64
1806 01:20:54.766803
1807 01:20:54.766914 Set Vref, RX VrefLevel [Byte0]: 65
1808 01:20:54.770109 [Byte1]: 65
1809 01:20:54.774654
1810 01:20:54.774765 Set Vref, RX VrefLevel [Byte0]: 66
1811 01:20:54.778099 [Byte1]: 66
1812 01:20:54.782559
1813 01:20:54.782671 Set Vref, RX VrefLevel [Byte0]: 67
1814 01:20:54.785871 [Byte1]: 67
1815 01:20:54.790129
1816 01:20:54.790256 Set Vref, RX VrefLevel [Byte0]: 68
1817 01:20:54.793024 [Byte1]: 68
1818 01:20:54.797453
1819 01:20:54.797625 Set Vref, RX VrefLevel [Byte0]: 69
1820 01:20:54.800544 [Byte1]: 69
1821 01:20:54.805022
1822 01:20:54.805137 Set Vref, RX VrefLevel [Byte0]: 70
1823 01:20:54.808091 [Byte1]: 70
1824 01:20:54.812732
1825 01:20:54.812843 Set Vref, RX VrefLevel [Byte0]: 71
1826 01:20:54.815773 [Byte1]: 71
1827 01:20:54.819728
1828 01:20:54.819838 Set Vref, RX VrefLevel [Byte0]: 72
1829 01:20:54.823171 [Byte1]: 72
1830 01:20:54.827651
1831 01:20:54.827763 Final RX Vref Byte 0 = 55 to rank0
1832 01:20:54.830791 Final RX Vref Byte 1 = 59 to rank0
1833 01:20:54.834202 Final RX Vref Byte 0 = 55 to rank1
1834 01:20:54.837687 Final RX Vref Byte 1 = 59 to rank1==
1835 01:20:54.840604 Dram Type= 6, Freq= 0, CH_1, rank 0
1836 01:20:54.843949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1837 01:20:54.847287 ==
1838 01:20:54.847398 DQS Delay:
1839 01:20:54.847498 DQS0 = 0, DQS1 = 0
1840 01:20:54.851112 DQM Delay:
1841 01:20:54.851222 DQM0 = 95, DQM1 = 89
1842 01:20:54.854055 DQ Delay:
1843 01:20:54.857492 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1844 01:20:54.857606 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1845 01:20:54.861258 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1846 01:20:54.864311 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1847 01:20:54.867364
1848 01:20:54.867474
1849 01:20:54.874424 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b47, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
1850 01:20:54.877770 CH1 RK0: MR19=606, MR18=2B47
1851 01:20:54.883898 CH1_RK0: MR19=0x606, MR18=0x2B47, DQSOSC=392, MR23=63, INC=96, DEC=64
1852 01:20:54.884018
1853 01:20:54.887668 ----->DramcWriteLeveling(PI) begin...
1854 01:20:54.887781 ==
1855 01:20:54.890864 Dram Type= 6, Freq= 0, CH_1, rank 1
1856 01:20:54.894220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1857 01:20:54.894341 ==
1858 01:20:54.897726 Write leveling (Byte 0): 27 => 27
1859 01:20:54.900688 Write leveling (Byte 1): 28 => 28
1860 01:20:54.904760 DramcWriteLeveling(PI) end<-----
1861 01:20:54.904872
1862 01:20:54.904971 ==
1863 01:20:54.907747 Dram Type= 6, Freq= 0, CH_1, rank 1
1864 01:20:54.911075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1865 01:20:54.911186 ==
1866 01:20:54.914217 [Gating] SW mode calibration
1867 01:20:54.921299 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1868 01:20:54.928102 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1869 01:20:54.930976 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1870 01:20:54.934143 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 01:20:54.941424 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 01:20:54.944416 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 01:20:54.947599 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 01:20:54.954248 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 01:20:54.957429 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 01:20:54.961101 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 01:20:54.967674 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 01:20:54.970721 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 01:20:54.974096 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 01:20:54.980942 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 01:20:54.984215 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 01:20:54.987569 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 01:20:54.990942 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 01:20:54.997229 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 01:20:55.001056 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 01:20:55.003939 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1887 01:20:55.010968 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1888 01:20:55.014182 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 01:20:55.017506 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 01:20:55.024402 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 01:20:55.027480 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 01:20:55.031298 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 01:20:55.037281 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 01:20:55.041134 0 9 4 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
1895 01:20:55.044309 0 9 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
1896 01:20:55.050711 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 01:20:55.054355 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 01:20:55.057460 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 01:20:55.064553 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 01:20:55.067706 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 01:20:55.070894 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 01:20:55.074656 0 10 4 | B1->B0 | 2e2e 3030 | 1 1 | (1 0) (1 1)
1903 01:20:55.080930 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 01:20:55.084417 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 01:20:55.088140 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 01:20:55.094313 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 01:20:55.097543 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 01:20:55.100740 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 01:20:55.107469 0 11 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1910 01:20:55.110947 0 11 4 | B1->B0 | 3737 2929 | 1 0 | (0 0) (0 0)
1911 01:20:55.114792 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 01:20:55.121202 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 01:20:55.124301 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 01:20:55.127929 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 01:20:55.134420 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 01:20:55.137633 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 01:20:55.141115 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 01:20:55.144769 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1919 01:20:55.151642 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 01:20:55.154865 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 01:20:55.157806 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 01:20:55.164628 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 01:20:55.167901 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 01:20:55.171215 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 01:20:55.178175 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 01:20:55.181204 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 01:20:55.184435 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 01:20:55.191179 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 01:20:55.194311 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 01:20:55.198148 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 01:20:55.204576 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 01:20:55.207837 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 01:20:55.211311 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 01:20:55.217957 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1935 01:20:55.218046 Total UI for P1: 0, mck2ui 16
1936 01:20:55.221701 best dqsien dly found for B1: ( 0, 14, 2)
1937 01:20:55.228001 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 01:20:55.231364 Total UI for P1: 0, mck2ui 16
1939 01:20:55.234764 best dqsien dly found for B0: ( 0, 14, 6)
1940 01:20:55.238144 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1941 01:20:55.241617 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1942 01:20:55.241721
1943 01:20:55.244462 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1944 01:20:55.248079 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1945 01:20:55.251610 [Gating] SW calibration Done
1946 01:20:55.251691 ==
1947 01:20:55.254998 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 01:20:55.258343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 01:20:55.258426 ==
1950 01:20:55.261475 RX Vref Scan: 0
1951 01:20:55.261594
1952 01:20:55.261702 RX Vref 0 -> 0, step: 1
1953 01:20:55.261806
1954 01:20:55.264522 RX Delay -130 -> 252, step: 16
1955 01:20:55.271584 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1956 01:20:55.274652 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1957 01:20:55.277908 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1958 01:20:55.281224 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1959 01:20:55.284452 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1960 01:20:55.291270 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1961 01:20:55.294809 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1962 01:20:55.297773 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1963 01:20:55.301627 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1964 01:20:55.304591 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1965 01:20:55.307762 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1966 01:20:55.314913 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1967 01:20:55.317831 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1968 01:20:55.321348 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1969 01:20:55.324390 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1970 01:20:55.331335 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1971 01:20:55.331455 ==
1972 01:20:55.334555 Dram Type= 6, Freq= 0, CH_1, rank 1
1973 01:20:55.337799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1974 01:20:55.337917 ==
1975 01:20:55.338023 DQS Delay:
1976 01:20:55.341491 DQS0 = 0, DQS1 = 0
1977 01:20:55.341609 DQM Delay:
1978 01:20:55.345105 DQM0 = 92, DQM1 = 87
1979 01:20:55.345220 DQ Delay:
1980 01:20:55.348297 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1981 01:20:55.351570 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1982 01:20:55.354427 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1983 01:20:55.357849 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1984 01:20:55.357966
1985 01:20:55.358072
1986 01:20:55.358175 ==
1987 01:20:55.361070 Dram Type= 6, Freq= 0, CH_1, rank 1
1988 01:20:55.364419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1989 01:20:55.364540 ==
1990 01:20:55.364648
1991 01:20:55.368043
1992 01:20:55.368158 TX Vref Scan disable
1993 01:20:55.371358 == TX Byte 0 ==
1994 01:20:55.374826 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1995 01:20:55.378152 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1996 01:20:55.381302 == TX Byte 1 ==
1997 01:20:55.384528 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1998 01:20:55.388224 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1999 01:20:55.388341 ==
2000 01:20:55.391543 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 01:20:55.397635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 01:20:55.397754 ==
2003 01:20:55.409382 TX Vref=22, minBit 1, minWin=26, winSum=441
2004 01:20:55.413142 TX Vref=24, minBit 1, minWin=26, winSum=445
2005 01:20:55.416407 TX Vref=26, minBit 1, minWin=27, winSum=449
2006 01:20:55.419568 TX Vref=28, minBit 2, minWin=27, winSum=453
2007 01:20:55.422666 TX Vref=30, minBit 2, minWin=27, winSum=452
2008 01:20:55.429512 TX Vref=32, minBit 2, minWin=27, winSum=446
2009 01:20:55.433170 [TxChooseVref] Worse bit 2, Min win 27, Win sum 453, Final Vref 28
2010 01:20:55.433290
2011 01:20:55.436325 Final TX Range 1 Vref 28
2012 01:20:55.436443
2013 01:20:55.436550 ==
2014 01:20:55.439255 Dram Type= 6, Freq= 0, CH_1, rank 1
2015 01:20:55.443131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2016 01:20:55.443249 ==
2017 01:20:55.443356
2018 01:20:55.446294
2019 01:20:55.446443 TX Vref Scan disable
2020 01:20:55.449908 == TX Byte 0 ==
2021 01:20:55.452501 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2022 01:20:55.455952 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2023 01:20:55.459364 == TX Byte 1 ==
2024 01:20:55.462708 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2025 01:20:55.466501 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2026 01:20:55.469516
2027 01:20:55.469631 [DATLAT]
2028 01:20:55.469737 Freq=800, CH1 RK1
2029 01:20:55.469842
2030 01:20:55.472551 DATLAT Default: 0xa
2031 01:20:55.472668 0, 0xFFFF, sum = 0
2032 01:20:55.476160 1, 0xFFFF, sum = 0
2033 01:20:55.476278 2, 0xFFFF, sum = 0
2034 01:20:55.479728 3, 0xFFFF, sum = 0
2035 01:20:55.479847 4, 0xFFFF, sum = 0
2036 01:20:55.482756 5, 0xFFFF, sum = 0
2037 01:20:55.486011 6, 0xFFFF, sum = 0
2038 01:20:55.486131 7, 0xFFFF, sum = 0
2039 01:20:55.489318 8, 0xFFFF, sum = 0
2040 01:20:55.489437 9, 0x0, sum = 1
2041 01:20:55.489547 10, 0x0, sum = 2
2042 01:20:55.492795 11, 0x0, sum = 3
2043 01:20:55.492913 12, 0x0, sum = 4
2044 01:20:55.496005 best_step = 10
2045 01:20:55.496120
2046 01:20:55.496225 ==
2047 01:20:55.499741 Dram Type= 6, Freq= 0, CH_1, rank 1
2048 01:20:55.502665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2049 01:20:55.502783 ==
2050 01:20:55.506169 RX Vref Scan: 0
2051 01:20:55.506284
2052 01:20:55.506396 RX Vref 0 -> 0, step: 1
2053 01:20:55.506497
2054 01:20:55.509349 RX Delay -79 -> 252, step: 8
2055 01:20:55.516341 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2056 01:20:55.519548 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2057 01:20:55.522843 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2058 01:20:55.526017 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2059 01:20:55.529896 iDelay=209, Bit 4, Center 96 (1 ~ 192) 192
2060 01:20:55.532786 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2061 01:20:55.539778 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2062 01:20:55.543135 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2063 01:20:55.546290 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2064 01:20:55.549668 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2065 01:20:55.552838 iDelay=209, Bit 10, Center 92 (-7 ~ 192) 200
2066 01:20:55.556609 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2067 01:20:55.563491 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2068 01:20:55.566340 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2069 01:20:55.569683 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2070 01:20:55.573389 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2071 01:20:55.573506 ==
2072 01:20:55.576615 Dram Type= 6, Freq= 0, CH_1, rank 1
2073 01:20:55.583541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2074 01:20:55.583740 ==
2075 01:20:55.583848 DQS Delay:
2076 01:20:55.583933 DQS0 = 0, DQS1 = 0
2077 01:20:55.586518 DQM Delay:
2078 01:20:55.586645 DQM0 = 98, DQM1 = 91
2079 01:20:55.589972 DQ Delay:
2080 01:20:55.593116 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2081 01:20:55.596275 DQ4 =96, DQ5 =112, DQ6 =108, DQ7 =96
2082 01:20:55.599852 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2083 01:20:55.603458 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2084 01:20:55.603576
2085 01:20:55.603684
2086 01:20:55.609513 [DQSOSCAuto] RK1, (LSB)MR18= 0x450f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2087 01:20:55.613470 CH1 RK1: MR19=606, MR18=450F
2088 01:20:55.619575 CH1_RK1: MR19=0x606, MR18=0x450F, DQSOSC=392, MR23=63, INC=96, DEC=64
2089 01:20:55.623319 [RxdqsGatingPostProcess] freq 800
2090 01:20:55.626510 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2091 01:20:55.629603 Pre-setting of DQS Precalculation
2092 01:20:55.636106 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2093 01:20:55.643001 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2094 01:20:55.649933 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2095 01:20:55.650053
2096 01:20:55.650159
2097 01:20:55.652792 [Calibration Summary] 1600 Mbps
2098 01:20:55.652909 CH 0, Rank 0
2099 01:20:55.656441 SW Impedance : PASS
2100 01:20:55.660122 DUTY Scan : NO K
2101 01:20:55.660240 ZQ Calibration : PASS
2102 01:20:55.663467 Jitter Meter : NO K
2103 01:20:55.666658 CBT Training : PASS
2104 01:20:55.666777 Write leveling : PASS
2105 01:20:55.670030 RX DQS gating : PASS
2106 01:20:55.673091 RX DQ/DQS(RDDQC) : PASS
2107 01:20:55.673207 TX DQ/DQS : PASS
2108 01:20:55.676486 RX DATLAT : PASS
2109 01:20:55.676603 RX DQ/DQS(Engine): PASS
2110 01:20:55.679478 TX OE : NO K
2111 01:20:55.679597 All Pass.
2112 01:20:55.679703
2113 01:20:55.683357 CH 0, Rank 1
2114 01:20:55.683473 SW Impedance : PASS
2115 01:20:55.686788 DUTY Scan : NO K
2116 01:20:55.689949 ZQ Calibration : PASS
2117 01:20:55.690066 Jitter Meter : NO K
2118 01:20:55.693263 CBT Training : PASS
2119 01:20:55.696423 Write leveling : PASS
2120 01:20:55.696541 RX DQS gating : PASS
2121 01:20:55.700089 RX DQ/DQS(RDDQC) : PASS
2122 01:20:55.703189 TX DQ/DQS : PASS
2123 01:20:55.703309 RX DATLAT : PASS
2124 01:20:55.706195 RX DQ/DQS(Engine): PASS
2125 01:20:55.709761 TX OE : NO K
2126 01:20:55.709877 All Pass.
2127 01:20:55.709984
2128 01:20:55.710087 CH 1, Rank 0
2129 01:20:55.712984 SW Impedance : PASS
2130 01:20:55.716122 DUTY Scan : NO K
2131 01:20:55.716238 ZQ Calibration : PASS
2132 01:20:55.719640 Jitter Meter : NO K
2133 01:20:55.722775 CBT Training : PASS
2134 01:20:55.722893 Write leveling : PASS
2135 01:20:55.726256 RX DQS gating : PASS
2136 01:20:55.726419 RX DQ/DQS(RDDQC) : PASS
2137 01:20:55.729879 TX DQ/DQS : PASS
2138 01:20:55.733168 RX DATLAT : PASS
2139 01:20:55.733286 RX DQ/DQS(Engine): PASS
2140 01:20:55.736463 TX OE : NO K
2141 01:20:55.736581 All Pass.
2142 01:20:55.736686
2143 01:20:55.739946 CH 1, Rank 1
2144 01:20:55.740064 SW Impedance : PASS
2145 01:20:55.743319 DUTY Scan : NO K
2146 01:20:55.746516 ZQ Calibration : PASS
2147 01:20:55.746631 Jitter Meter : NO K
2148 01:20:55.749639 CBT Training : PASS
2149 01:20:55.752777 Write leveling : PASS
2150 01:20:55.752896 RX DQS gating : PASS
2151 01:20:55.756461 RX DQ/DQS(RDDQC) : PASS
2152 01:20:55.759399 TX DQ/DQS : PASS
2153 01:20:55.759517 RX DATLAT : PASS
2154 01:20:55.762869 RX DQ/DQS(Engine): PASS
2155 01:20:55.766467 TX OE : NO K
2156 01:20:55.766583 All Pass.
2157 01:20:55.766689
2158 01:20:55.766790 DramC Write-DBI off
2159 01:20:55.769779 PER_BANK_REFRESH: Hybrid Mode
2160 01:20:55.772781 TX_TRACKING: ON
2161 01:20:55.776472 [GetDramInforAfterCalByMRR] Vendor 6.
2162 01:20:55.779526 [GetDramInforAfterCalByMRR] Revision 606.
2163 01:20:55.783301 [GetDramInforAfterCalByMRR] Revision 2 0.
2164 01:20:55.783420 MR0 0x3b3b
2165 01:20:55.786187 MR8 0x5151
2166 01:20:55.789690 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2167 01:20:55.789805
2168 01:20:55.789913 MR0 0x3b3b
2169 01:20:55.790017 MR8 0x5151
2170 01:20:55.792751 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2171 01:20:55.792867
2172 01:20:55.802793 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2173 01:20:55.806468 [FAST_K] Save calibration result to emmc
2174 01:20:55.809509 [FAST_K] Save calibration result to emmc
2175 01:20:55.813327 dram_init: config_dvfs: 1
2176 01:20:55.816064 dramc_set_vcore_voltage set vcore to 662500
2177 01:20:55.819958 Read voltage for 1200, 2
2178 01:20:55.820074 Vio18 = 0
2179 01:20:55.822819 Vcore = 662500
2180 01:20:55.822934 Vdram = 0
2181 01:20:55.823041 Vddq = 0
2182 01:20:55.823142 Vmddr = 0
2183 01:20:55.829558 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2184 01:20:55.833255 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2185 01:20:55.836376 MEM_TYPE=3, freq_sel=15
2186 01:20:55.839415 sv_algorithm_assistance_LP4_1600
2187 01:20:55.842736 ============ PULL DRAM RESETB DOWN ============
2188 01:20:55.849613 ========== PULL DRAM RESETB DOWN end =========
2189 01:20:55.853046 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2190 01:20:55.856112 ===================================
2191 01:20:55.859990 LPDDR4 DRAM CONFIGURATION
2192 01:20:55.863038 ===================================
2193 01:20:55.863156 EX_ROW_EN[0] = 0x0
2194 01:20:55.866574 EX_ROW_EN[1] = 0x0
2195 01:20:55.866693 LP4Y_EN = 0x0
2196 01:20:55.869634 WORK_FSP = 0x0
2197 01:20:55.869749 WL = 0x4
2198 01:20:55.873031 RL = 0x4
2199 01:20:55.873148 BL = 0x2
2200 01:20:55.876752 RPST = 0x0
2201 01:20:55.876870 RD_PRE = 0x0
2202 01:20:55.879389 WR_PRE = 0x1
2203 01:20:55.879507 WR_PST = 0x0
2204 01:20:55.883064 DBI_WR = 0x0
2205 01:20:55.883182 DBI_RD = 0x0
2206 01:20:55.886236 OTF = 0x1
2207 01:20:55.889848 ===================================
2208 01:20:55.893010 ===================================
2209 01:20:55.893129 ANA top config
2210 01:20:55.896471 ===================================
2211 01:20:55.899831 DLL_ASYNC_EN = 0
2212 01:20:55.903249 ALL_SLAVE_EN = 0
2213 01:20:55.906492 NEW_RANK_MODE = 1
2214 01:20:55.906610 DLL_IDLE_MODE = 1
2215 01:20:55.909552 LP45_APHY_COMB_EN = 1
2216 01:20:55.913309 TX_ODT_DIS = 1
2217 01:20:55.916364 NEW_8X_MODE = 1
2218 01:20:55.919552 ===================================
2219 01:20:55.923073 ===================================
2220 01:20:55.926232 data_rate = 2400
2221 01:20:55.926351 CKR = 1
2222 01:20:55.929829 DQ_P2S_RATIO = 8
2223 01:20:55.932834 ===================================
2224 01:20:55.936512 CA_P2S_RATIO = 8
2225 01:20:55.939758 DQ_CA_OPEN = 0
2226 01:20:55.942963 DQ_SEMI_OPEN = 0
2227 01:20:55.946248 CA_SEMI_OPEN = 0
2228 01:20:55.946371 CA_FULL_RATE = 0
2229 01:20:55.949824 DQ_CKDIV4_EN = 0
2230 01:20:55.953153 CA_CKDIV4_EN = 0
2231 01:20:55.956254 CA_PREDIV_EN = 0
2232 01:20:55.959726 PH8_DLY = 17
2233 01:20:55.962769 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2234 01:20:55.962888 DQ_AAMCK_DIV = 4
2235 01:20:55.966388 CA_AAMCK_DIV = 4
2236 01:20:55.969551 CA_ADMCK_DIV = 4
2237 01:20:55.972738 DQ_TRACK_CA_EN = 0
2238 01:20:55.976245 CA_PICK = 1200
2239 01:20:55.979913 CA_MCKIO = 1200
2240 01:20:55.982848 MCKIO_SEMI = 0
2241 01:20:55.982965 PLL_FREQ = 2366
2242 01:20:55.985999 DQ_UI_PI_RATIO = 32
2243 01:20:55.989506 CA_UI_PI_RATIO = 0
2244 01:20:55.992656 ===================================
2245 01:20:55.996495 ===================================
2246 01:20:55.999855 memory_type:LPDDR4
2247 01:20:55.999972 GP_NUM : 10
2248 01:20:56.002654 SRAM_EN : 1
2249 01:20:56.006215 MD32_EN : 0
2250 01:20:56.009604 ===================================
2251 01:20:56.009721 [ANA_INIT] >>>>>>>>>>>>>>
2252 01:20:56.012813 <<<<<< [CONFIGURE PHASE]: ANA_TX
2253 01:20:56.015945 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2254 01:20:56.019395 ===================================
2255 01:20:56.023171 data_rate = 2400,PCW = 0X5b00
2256 01:20:56.026458 ===================================
2257 01:20:56.029824 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2258 01:20:56.036087 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2259 01:20:56.039368 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2260 01:20:56.046530 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2261 01:20:56.049846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2262 01:20:56.053100 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2263 01:20:56.053217 [ANA_INIT] flow start
2264 01:20:56.056191 [ANA_INIT] PLL >>>>>>>>
2265 01:20:56.059878 [ANA_INIT] PLL <<<<<<<<
2266 01:20:56.059996 [ANA_INIT] MIDPI >>>>>>>>
2267 01:20:56.062742 [ANA_INIT] MIDPI <<<<<<<<
2268 01:20:56.066067 [ANA_INIT] DLL >>>>>>>>
2269 01:20:56.069226 [ANA_INIT] DLL <<<<<<<<
2270 01:20:56.069343 [ANA_INIT] flow end
2271 01:20:56.072728 ============ LP4 DIFF to SE enter ============
2272 01:20:56.080027 ============ LP4 DIFF to SE exit ============
2273 01:20:56.080148 [ANA_INIT] <<<<<<<<<<<<<
2274 01:20:56.082932 [Flow] Enable top DCM control >>>>>
2275 01:20:56.085975 [Flow] Enable top DCM control <<<<<
2276 01:20:56.089439 Enable DLL master slave shuffle
2277 01:20:56.096172 ==============================================================
2278 01:20:56.096293 Gating Mode config
2279 01:20:56.103339 ==============================================================
2280 01:20:56.106286 Config description:
2281 01:20:56.112804 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2282 01:20:56.119644 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2283 01:20:56.126482 SELPH_MODE 0: By rank 1: By Phase
2284 01:20:56.129820 ==============================================================
2285 01:20:56.133280 GAT_TRACK_EN = 1
2286 01:20:56.136147 RX_GATING_MODE = 2
2287 01:20:56.140235 RX_GATING_TRACK_MODE = 2
2288 01:20:56.142981 SELPH_MODE = 1
2289 01:20:56.146922 PICG_EARLY_EN = 1
2290 01:20:56.149712 VALID_LAT_VALUE = 1
2291 01:20:56.156795 ==============================================================
2292 01:20:56.159760 Enter into Gating configuration >>>>
2293 01:20:56.162825 Exit from Gating configuration <<<<
2294 01:20:56.166554 Enter into DVFS_PRE_config >>>>>
2295 01:20:56.176334 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2296 01:20:56.179643 Exit from DVFS_PRE_config <<<<<
2297 01:20:56.183026 Enter into PICG configuration >>>>
2298 01:20:56.186140 Exit from PICG configuration <<<<
2299 01:20:56.189830 [RX_INPUT] configuration >>>>>
2300 01:20:56.189947 [RX_INPUT] configuration <<<<<
2301 01:20:56.196254 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2302 01:20:56.199721 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2303 01:20:56.206673 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2304 01:20:56.213015 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2305 01:20:56.220047 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2306 01:20:56.226542 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2307 01:20:56.229705 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2308 01:20:56.232870 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2309 01:20:56.239763 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2310 01:20:56.243025 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2311 01:20:56.246575 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2312 01:20:56.249611 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2313 01:20:56.253060 ===================================
2314 01:20:56.256237 LPDDR4 DRAM CONFIGURATION
2315 01:20:56.259980 ===================================
2316 01:20:56.263116 EX_ROW_EN[0] = 0x0
2317 01:20:56.263233 EX_ROW_EN[1] = 0x0
2318 01:20:56.266535 LP4Y_EN = 0x0
2319 01:20:56.266710 WORK_FSP = 0x0
2320 01:20:56.269776 WL = 0x4
2321 01:20:56.269889 RL = 0x4
2322 01:20:56.273126 BL = 0x2
2323 01:20:56.273241 RPST = 0x0
2324 01:20:56.276762 RD_PRE = 0x0
2325 01:20:56.276880 WR_PRE = 0x1
2326 01:20:56.279746 WR_PST = 0x0
2327 01:20:56.279862 DBI_WR = 0x0
2328 01:20:56.283520 DBI_RD = 0x0
2329 01:20:56.283638 OTF = 0x1
2330 01:20:56.286925 ===================================
2331 01:20:56.293438 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2332 01:20:56.297068 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2333 01:20:56.300021 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2334 01:20:56.303169 ===================================
2335 01:20:56.306690 LPDDR4 DRAM CONFIGURATION
2336 01:20:56.310254 ===================================
2337 01:20:56.310422 EX_ROW_EN[0] = 0x10
2338 01:20:56.313389 EX_ROW_EN[1] = 0x0
2339 01:20:56.316650 LP4Y_EN = 0x0
2340 01:20:56.316779 WORK_FSP = 0x0
2341 01:20:56.319859 WL = 0x4
2342 01:20:56.319987 RL = 0x4
2343 01:20:56.323779 BL = 0x2
2344 01:20:56.323903 RPST = 0x0
2345 01:20:56.326943 RD_PRE = 0x0
2346 01:20:56.327073 WR_PRE = 0x1
2347 01:20:56.330076 WR_PST = 0x0
2348 01:20:56.330203 DBI_WR = 0x0
2349 01:20:56.333848 DBI_RD = 0x0
2350 01:20:56.333976 OTF = 0x1
2351 01:20:56.337017 ===================================
2352 01:20:56.343452 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2353 01:20:56.343585 ==
2354 01:20:56.346712 Dram Type= 6, Freq= 0, CH_0, rank 0
2355 01:20:56.349994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2356 01:20:56.350148 ==
2357 01:20:56.353508 [Duty_Offset_Calibration]
2358 01:20:56.357183 B0:2 B1:1 CA:1
2359 01:20:56.357329
2360 01:20:56.359975 [DutyScan_Calibration_Flow] k_type=0
2361 01:20:56.368380
2362 01:20:56.368586 ==CLK 0==
2363 01:20:56.372422 Final CLK duty delay cell = 0
2364 01:20:56.374845 [0] MAX Duty = 5187%(X100), DQS PI = 24
2365 01:20:56.378083 [0] MIN Duty = 4875%(X100), DQS PI = 0
2366 01:20:56.378225 [0] AVG Duty = 5031%(X100)
2367 01:20:56.381309
2368 01:20:56.381445 CH0 CLK Duty spec in!! Max-Min= 312%
2369 01:20:56.388036 [DutyScan_Calibration_Flow] ====Done====
2370 01:20:56.388192
2371 01:20:56.391614 [DutyScan_Calibration_Flow] k_type=1
2372 01:20:56.406538
2373 01:20:56.406748 ==DQS 0 ==
2374 01:20:56.410034 Final DQS duty delay cell = -4
2375 01:20:56.413634 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2376 01:20:56.416727 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2377 01:20:56.420182 [-4] AVG Duty = 4937%(X100)
2378 01:20:56.420332
2379 01:20:56.420460 ==DQS 1 ==
2380 01:20:56.423125 Final DQS duty delay cell = 0
2381 01:20:56.426928 [0] MAX Duty = 5156%(X100), DQS PI = 62
2382 01:20:56.430118 [0] MIN Duty = 5000%(X100), DQS PI = 34
2383 01:20:56.433162 [0] AVG Duty = 5078%(X100)
2384 01:20:56.433311
2385 01:20:56.436528 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2386 01:20:56.436662
2387 01:20:56.440242 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2388 01:20:56.443442 [DutyScan_Calibration_Flow] ====Done====
2389 01:20:56.443575
2390 01:20:56.446550 [DutyScan_Calibration_Flow] k_type=3
2391 01:20:56.463711
2392 01:20:56.463854 ==DQM 0 ==
2393 01:20:56.467185 Final DQM duty delay cell = 0
2394 01:20:56.470192 [0] MAX Duty = 5156%(X100), DQS PI = 30
2395 01:20:56.473451 [0] MIN Duty = 4875%(X100), DQS PI = 58
2396 01:20:56.473542 [0] AVG Duty = 5015%(X100)
2397 01:20:56.476804
2398 01:20:56.476886 ==DQM 1 ==
2399 01:20:56.480480 Final DQM duty delay cell = 0
2400 01:20:56.483655 [0] MAX Duty = 5093%(X100), DQS PI = 0
2401 01:20:56.486830 [0] MIN Duty = 5031%(X100), DQS PI = 16
2402 01:20:56.486911 [0] AVG Duty = 5062%(X100)
2403 01:20:56.490344
2404 01:20:56.493666 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2405 01:20:56.493748
2406 01:20:56.496684 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2407 01:20:56.500532 [DutyScan_Calibration_Flow] ====Done====
2408 01:20:56.500613
2409 01:20:56.503372 [DutyScan_Calibration_Flow] k_type=2
2410 01:20:56.519829
2411 01:20:56.519924 ==DQ 0 ==
2412 01:20:56.523304 Final DQ duty delay cell = 0
2413 01:20:56.526696 [0] MAX Duty = 5031%(X100), DQS PI = 24
2414 01:20:56.530048 [0] MIN Duty = 4844%(X100), DQS PI = 62
2415 01:20:56.530185 [0] AVG Duty = 4937%(X100)
2416 01:20:56.530314
2417 01:20:56.533378 ==DQ 1 ==
2418 01:20:56.536524 Final DQ duty delay cell = 0
2419 01:20:56.540014 [0] MAX Duty = 5093%(X100), DQS PI = 8
2420 01:20:56.543073 [0] MIN Duty = 4938%(X100), DQS PI = 36
2421 01:20:56.543155 [0] AVG Duty = 5015%(X100)
2422 01:20:56.543220
2423 01:20:56.546467 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2424 01:20:56.546548
2425 01:20:56.550348 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2426 01:20:56.556682 [DutyScan_Calibration_Flow] ====Done====
2427 01:20:56.556817 ==
2428 01:20:56.559919 Dram Type= 6, Freq= 0, CH_1, rank 0
2429 01:20:56.563220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2430 01:20:56.563353 ==
2431 01:20:56.566458 [Duty_Offset_Calibration]
2432 01:20:56.566588 B0:1 B1:0 CA:0
2433 01:20:56.566707
2434 01:20:56.570017 [DutyScan_Calibration_Flow] k_type=0
2435 01:20:56.579104
2436 01:20:56.579191 ==CLK 0==
2437 01:20:56.582278 Final CLK duty delay cell = -4
2438 01:20:56.586276 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2439 01:20:56.589305 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2440 01:20:56.592595 [-4] AVG Duty = 4953%(X100)
2441 01:20:56.592676
2442 01:20:56.596338 CH1 CLK Duty spec in!! Max-Min= 156%
2443 01:20:56.599530 [DutyScan_Calibration_Flow] ====Done====
2444 01:20:56.599611
2445 01:20:56.602755 [DutyScan_Calibration_Flow] k_type=1
2446 01:20:56.618792
2447 01:20:56.618877 ==DQS 0 ==
2448 01:20:56.622039 Final DQS duty delay cell = 0
2449 01:20:56.626086 [0] MAX Duty = 5062%(X100), DQS PI = 10
2450 01:20:56.628769 [0] MIN Duty = 4875%(X100), DQS PI = 0
2451 01:20:56.628850 [0] AVG Duty = 4968%(X100)
2452 01:20:56.632553
2453 01:20:56.632635 ==DQS 1 ==
2454 01:20:56.635462 Final DQS duty delay cell = 0
2455 01:20:56.638827 [0] MAX Duty = 5187%(X100), DQS PI = 18
2456 01:20:56.642444 [0] MIN Duty = 4969%(X100), DQS PI = 10
2457 01:20:56.642526 [0] AVG Duty = 5078%(X100)
2458 01:20:56.645893
2459 01:20:56.649109 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2460 01:20:56.649191
2461 01:20:56.652220 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2462 01:20:56.655398 [DutyScan_Calibration_Flow] ====Done====
2463 01:20:56.655480
2464 01:20:56.658680 [DutyScan_Calibration_Flow] k_type=3
2465 01:20:56.675701
2466 01:20:56.675804 ==DQM 0 ==
2467 01:20:56.678791 Final DQM duty delay cell = 0
2468 01:20:56.682325 [0] MAX Duty = 5156%(X100), DQS PI = 8
2469 01:20:56.685444 [0] MIN Duty = 5000%(X100), DQS PI = 62
2470 01:20:56.685523 [0] AVG Duty = 5078%(X100)
2471 01:20:56.685586
2472 01:20:56.689298 ==DQM 1 ==
2473 01:20:56.692514 Final DQM duty delay cell = 0
2474 01:20:56.695654 [0] MAX Duty = 5031%(X100), DQS PI = 16
2475 01:20:56.698836 [0] MIN Duty = 4907%(X100), DQS PI = 36
2476 01:20:56.698916 [0] AVG Duty = 4969%(X100)
2477 01:20:56.701916
2478 01:20:56.705206 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2479 01:20:56.705287
2480 01:20:56.709201 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2481 01:20:56.712401 [DutyScan_Calibration_Flow] ====Done====
2482 01:20:56.712481
2483 01:20:56.715423 [DutyScan_Calibration_Flow] k_type=2
2484 01:20:56.731316
2485 01:20:56.731407 ==DQ 0 ==
2486 01:20:56.734439 Final DQ duty delay cell = -4
2487 01:20:56.737726 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2488 01:20:56.741351 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2489 01:20:56.744331 [-4] AVG Duty = 4984%(X100)
2490 01:20:56.744412
2491 01:20:56.744475 ==DQ 1 ==
2492 01:20:56.747558 Final DQ duty delay cell = 0
2493 01:20:56.751061 [0] MAX Duty = 5125%(X100), DQS PI = 20
2494 01:20:56.754567 [0] MIN Duty = 4969%(X100), DQS PI = 12
2495 01:20:56.757491 [0] AVG Duty = 5047%(X100)
2496 01:20:56.757571
2497 01:20:56.761055 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2498 01:20:56.761136
2499 01:20:56.764607 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2500 01:20:56.767855 [DutyScan_Calibration_Flow] ====Done====
2501 01:20:56.771122 nWR fixed to 30
2502 01:20:56.771203 [ModeRegInit_LP4] CH0 RK0
2503 01:20:56.774702 [ModeRegInit_LP4] CH0 RK1
2504 01:20:56.777858 [ModeRegInit_LP4] CH1 RK0
2505 01:20:56.781482 [ModeRegInit_LP4] CH1 RK1
2506 01:20:56.781563 match AC timing 7
2507 01:20:56.784427 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2508 01:20:56.788014 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2509 01:20:56.794643 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2510 01:20:56.797822 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2511 01:20:56.804625 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2512 01:20:56.804732 ==
2513 01:20:56.807816 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 01:20:56.811121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2515 01:20:56.811224 ==
2516 01:20:56.817854 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2517 01:20:56.824277 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2518 01:20:56.831190 [CA 0] Center 39 (8~70) winsize 63
2519 01:20:56.834868 [CA 1] Center 39 (8~70) winsize 63
2520 01:20:56.838027 [CA 2] Center 35 (5~66) winsize 62
2521 01:20:56.841169 [CA 3] Center 34 (4~65) winsize 62
2522 01:20:56.845050 [CA 4] Center 33 (3~64) winsize 62
2523 01:20:56.848364 [CA 5] Center 32 (3~62) winsize 60
2524 01:20:56.848468
2525 01:20:56.851483 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2526 01:20:56.851587
2527 01:20:56.854663 [CATrainingPosCal] consider 1 rank data
2528 01:20:56.858243 u2DelayCellTimex100 = 270/100 ps
2529 01:20:56.861475 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2530 01:20:56.864464 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2531 01:20:56.871404 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2532 01:20:56.874983 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2533 01:20:56.878468 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2534 01:20:56.881764 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2535 01:20:56.881865
2536 01:20:56.885278 CA PerBit enable=1, Macro0, CA PI delay=32
2537 01:20:56.885384
2538 01:20:56.888307 [CBTSetCACLKResult] CA Dly = 32
2539 01:20:56.888410 CS Dly: 6 (0~37)
2540 01:20:56.888494 ==
2541 01:20:56.891314 Dram Type= 6, Freq= 0, CH_0, rank 1
2542 01:20:56.897915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2543 01:20:56.898021 ==
2544 01:20:56.901160 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2545 01:20:56.907893 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2546 01:20:56.917369 [CA 0] Center 38 (8~69) winsize 62
2547 01:20:56.920600 [CA 1] Center 38 (8~69) winsize 62
2548 01:20:56.923868 [CA 2] Center 35 (4~66) winsize 63
2549 01:20:56.926963 [CA 3] Center 34 (4~65) winsize 62
2550 01:20:56.930898 [CA 4] Center 33 (3~64) winsize 62
2551 01:20:56.933990 [CA 5] Center 32 (3~62) winsize 60
2552 01:20:56.934097
2553 01:20:56.937211 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2554 01:20:56.937315
2555 01:20:56.940403 [CATrainingPosCal] consider 2 rank data
2556 01:20:56.944246 u2DelayCellTimex100 = 270/100 ps
2557 01:20:56.947461 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2558 01:20:56.950475 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2559 01:20:56.957368 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2560 01:20:56.960742 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2561 01:20:56.963857 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2562 01:20:56.967636 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2563 01:20:56.967745
2564 01:20:56.970703 CA PerBit enable=1, Macro0, CA PI delay=32
2565 01:20:56.970808
2566 01:20:56.973602 [CBTSetCACLKResult] CA Dly = 32
2567 01:20:56.973707 CS Dly: 6 (0~38)
2568 01:20:56.973799
2569 01:20:56.977428 ----->DramcWriteLeveling(PI) begin...
2570 01:20:56.981012 ==
2571 01:20:56.983776 Dram Type= 6, Freq= 0, CH_0, rank 0
2572 01:20:56.986983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2573 01:20:56.987083 ==
2574 01:20:56.990637 Write leveling (Byte 0): 33 => 33
2575 01:20:56.993599 Write leveling (Byte 1): 30 => 30
2576 01:20:56.997363 DramcWriteLeveling(PI) end<-----
2577 01:20:56.997468
2578 01:20:56.997559 ==
2579 01:20:57.000323 Dram Type= 6, Freq= 0, CH_0, rank 0
2580 01:20:57.003619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2581 01:20:57.003723 ==
2582 01:20:57.006932 [Gating] SW mode calibration
2583 01:20:57.013763 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2584 01:20:57.016981 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2585 01:20:57.023614 0 15 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
2586 01:20:57.027435 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2587 01:20:57.030322 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 01:20:57.037075 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 01:20:57.040337 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 01:20:57.044135 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 01:20:57.050848 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2592 01:20:57.054020 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2593 01:20:57.057358 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
2594 01:20:57.063714 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2595 01:20:57.067478 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 01:20:57.070638 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 01:20:57.077579 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 01:20:57.080395 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 01:20:57.084003 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2600 01:20:57.087327 1 0 28 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2601 01:20:57.094255 1 1 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
2602 01:20:57.097449 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 01:20:57.101239 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 01:20:57.107813 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 01:20:57.110973 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 01:20:57.113778 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 01:20:57.120872 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 01:20:57.124099 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2609 01:20:57.127323 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2610 01:20:57.134154 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 01:20:57.137420 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 01:20:57.140877 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 01:20:57.147535 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 01:20:57.150684 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 01:20:57.154006 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 01:20:57.160529 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 01:20:57.164126 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 01:20:57.167535 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 01:20:57.174515 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 01:20:57.177365 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 01:20:57.180594 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 01:20:57.184657 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 01:20:57.190934 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2624 01:20:57.194097 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2625 01:20:57.197808 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2626 01:20:57.200913 Total UI for P1: 0, mck2ui 16
2627 01:20:57.203928 best dqsien dly found for B0: ( 1, 3, 26)
2628 01:20:57.211017 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2629 01:20:57.213835 Total UI for P1: 0, mck2ui 16
2630 01:20:57.217537 best dqsien dly found for B1: ( 1, 3, 30)
2631 01:20:57.220909 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2632 01:20:57.223983 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2633 01:20:57.224093
2634 01:20:57.227308 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2635 01:20:57.230814 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2636 01:20:57.233942 [Gating] SW calibration Done
2637 01:20:57.234023 ==
2638 01:20:57.237690 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 01:20:57.240812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 01:20:57.240894 ==
2641 01:20:57.244110 RX Vref Scan: 0
2642 01:20:57.244190
2643 01:20:57.244253 RX Vref 0 -> 0, step: 1
2644 01:20:57.244313
2645 01:20:57.247286 RX Delay -40 -> 252, step: 8
2646 01:20:57.254025 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2647 01:20:57.257610 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2648 01:20:57.260574 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2649 01:20:57.263803 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2650 01:20:57.267640 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2651 01:20:57.270416 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2652 01:20:57.277503 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2653 01:20:57.280434 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2654 01:20:57.284298 iDelay=200, Bit 8, Center 99 (40 ~ 159) 120
2655 01:20:57.287403 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2656 01:20:57.290399 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2657 01:20:57.297023 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2658 01:20:57.300766 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2659 01:20:57.303795 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2660 01:20:57.307495 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2661 01:20:57.310672 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2662 01:20:57.313898 ==
2663 01:20:57.317064 Dram Type= 6, Freq= 0, CH_0, rank 0
2664 01:20:57.320683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2665 01:20:57.320767 ==
2666 01:20:57.320831 DQS Delay:
2667 01:20:57.324221 DQS0 = 0, DQS1 = 0
2668 01:20:57.324305 DQM Delay:
2669 01:20:57.327023 DQM0 = 121, DQM1 = 113
2670 01:20:57.327105 DQ Delay:
2671 01:20:57.330485 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2672 01:20:57.334227 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2673 01:20:57.337458 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2674 01:20:57.340377 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2675 01:20:57.340487
2676 01:20:57.340578
2677 01:20:57.340639 ==
2678 01:20:57.343972 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 01:20:57.350847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 01:20:57.350942 ==
2681 01:20:57.351007
2682 01:20:57.351066
2683 01:20:57.351123 TX Vref Scan disable
2684 01:20:57.353955 == TX Byte 0 ==
2685 01:20:57.357822 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2686 01:20:57.360921 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2687 01:20:57.363997 == TX Byte 1 ==
2688 01:20:57.367767 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2689 01:20:57.370912 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2690 01:20:57.374029 ==
2691 01:20:57.377704 Dram Type= 6, Freq= 0, CH_0, rank 0
2692 01:20:57.380607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2693 01:20:57.380693 ==
2694 01:20:57.391963 TX Vref=22, minBit 10, minWin=24, winSum=405
2695 01:20:57.395883 TX Vref=24, minBit 10, minWin=25, winSum=417
2696 01:20:57.398991 TX Vref=26, minBit 3, minWin=25, winSum=413
2697 01:20:57.401986 TX Vref=28, minBit 0, minWin=26, winSum=422
2698 01:20:57.405713 TX Vref=30, minBit 0, minWin=26, winSum=422
2699 01:20:57.411867 TX Vref=32, minBit 12, minWin=25, winSum=418
2700 01:20:57.416027 [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 28
2701 01:20:57.416116
2702 01:20:57.418784 Final TX Range 1 Vref 28
2703 01:20:57.418866
2704 01:20:57.418929 ==
2705 01:20:57.422012 Dram Type= 6, Freq= 0, CH_0, rank 0
2706 01:20:57.425913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2707 01:20:57.425998 ==
2708 01:20:57.426062
2709 01:20:57.428817
2710 01:20:57.428923 TX Vref Scan disable
2711 01:20:57.432572 == TX Byte 0 ==
2712 01:20:57.435467 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2713 01:20:57.438775 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2714 01:20:57.442226 == TX Byte 1 ==
2715 01:20:57.445450 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2716 01:20:57.449301 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2717 01:20:57.449387
2718 01:20:57.452288 [DATLAT]
2719 01:20:57.452370 Freq=1200, CH0 RK0
2720 01:20:57.452435
2721 01:20:57.455928 DATLAT Default: 0xd
2722 01:20:57.456010 0, 0xFFFF, sum = 0
2723 01:20:57.459073 1, 0xFFFF, sum = 0
2724 01:20:57.459158 2, 0xFFFF, sum = 0
2725 01:20:57.462255 3, 0xFFFF, sum = 0
2726 01:20:57.462390 4, 0xFFFF, sum = 0
2727 01:20:57.465655 5, 0xFFFF, sum = 0
2728 01:20:57.465739 6, 0xFFFF, sum = 0
2729 01:20:57.468706 7, 0xFFFF, sum = 0
2730 01:20:57.468791 8, 0xFFFF, sum = 0
2731 01:20:57.472329 9, 0xFFFF, sum = 0
2732 01:20:57.475585 10, 0xFFFF, sum = 0
2733 01:20:57.475670 11, 0xFFFF, sum = 0
2734 01:20:57.479412 12, 0x0, sum = 1
2735 01:20:57.479496 13, 0x0, sum = 2
2736 01:20:57.479562 14, 0x0, sum = 3
2737 01:20:57.482730 15, 0x0, sum = 4
2738 01:20:57.482813 best_step = 13
2739 01:20:57.482878
2740 01:20:57.485876 ==
2741 01:20:57.485962 Dram Type= 6, Freq= 0, CH_0, rank 0
2742 01:20:57.492712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2743 01:20:57.492797 ==
2744 01:20:57.492862 RX Vref Scan: 1
2745 01:20:57.492922
2746 01:20:57.495719 Set Vref Range= 32 -> 127
2747 01:20:57.495801
2748 01:20:57.499642 RX Vref 32 -> 127, step: 1
2749 01:20:57.499739
2750 01:20:57.502764 RX Delay -5 -> 252, step: 4
2751 01:20:57.502846
2752 01:20:57.505915 Set Vref, RX VrefLevel [Byte0]: 32
2753 01:20:57.505996 [Byte1]: 32
2754 01:20:57.510487
2755 01:20:57.510617 Set Vref, RX VrefLevel [Byte0]: 33
2756 01:20:57.513823 [Byte1]: 33
2757 01:20:57.518316
2758 01:20:57.518431 Set Vref, RX VrefLevel [Byte0]: 34
2759 01:20:57.521714 [Byte1]: 34
2760 01:20:57.526104
2761 01:20:57.526187 Set Vref, RX VrefLevel [Byte0]: 35
2762 01:20:57.529291 [Byte1]: 35
2763 01:20:57.534455
2764 01:20:57.534574 Set Vref, RX VrefLevel [Byte0]: 36
2765 01:20:57.537570 [Byte1]: 36
2766 01:20:57.541959
2767 01:20:57.542042 Set Vref, RX VrefLevel [Byte0]: 37
2768 01:20:57.544886 [Byte1]: 37
2769 01:20:57.549776
2770 01:20:57.549859 Set Vref, RX VrefLevel [Byte0]: 38
2771 01:20:57.552865 [Byte1]: 38
2772 01:20:57.557367
2773 01:20:57.557449 Set Vref, RX VrefLevel [Byte0]: 39
2774 01:20:57.561185 [Byte1]: 39
2775 01:20:57.565546
2776 01:20:57.565630 Set Vref, RX VrefLevel [Byte0]: 40
2777 01:20:57.568493 [Byte1]: 40
2778 01:20:57.573129
2779 01:20:57.573211 Set Vref, RX VrefLevel [Byte0]: 41
2780 01:20:57.576503 [Byte1]: 41
2781 01:20:57.581188
2782 01:20:57.581273 Set Vref, RX VrefLevel [Byte0]: 42
2783 01:20:57.584549 [Byte1]: 42
2784 01:20:57.589071
2785 01:20:57.589154 Set Vref, RX VrefLevel [Byte0]: 43
2786 01:20:57.592264 [Byte1]: 43
2787 01:20:57.596928
2788 01:20:57.597011 Set Vref, RX VrefLevel [Byte0]: 44
2789 01:20:57.600016 [Byte1]: 44
2790 01:20:57.604685
2791 01:20:57.604769 Set Vref, RX VrefLevel [Byte0]: 45
2792 01:20:57.608300 [Byte1]: 45
2793 01:20:57.612591
2794 01:20:57.612683 Set Vref, RX VrefLevel [Byte0]: 46
2795 01:20:57.615941 [Byte1]: 46
2796 01:20:57.620444
2797 01:20:57.620527 Set Vref, RX VrefLevel [Byte0]: 47
2798 01:20:57.623786 [Byte1]: 47
2799 01:20:57.628150
2800 01:20:57.628231 Set Vref, RX VrefLevel [Byte0]: 48
2801 01:20:57.631758 [Byte1]: 48
2802 01:20:57.636212
2803 01:20:57.636313 Set Vref, RX VrefLevel [Byte0]: 49
2804 01:20:57.639352 [Byte1]: 49
2805 01:20:57.643812
2806 01:20:57.643902 Set Vref, RX VrefLevel [Byte0]: 50
2807 01:20:57.647028 [Byte1]: 50
2808 01:20:57.651573
2809 01:20:57.651669 Set Vref, RX VrefLevel [Byte0]: 51
2810 01:20:57.655129 [Byte1]: 51
2811 01:20:57.659660
2812 01:20:57.659751 Set Vref, RX VrefLevel [Byte0]: 52
2813 01:20:57.662972 [Byte1]: 52
2814 01:20:57.667754
2815 01:20:57.667857 Set Vref, RX VrefLevel [Byte0]: 53
2816 01:20:57.670912 [Byte1]: 53
2817 01:20:57.675537
2818 01:20:57.675619 Set Vref, RX VrefLevel [Byte0]: 54
2819 01:20:57.678627 [Byte1]: 54
2820 01:20:57.683414
2821 01:20:57.683494 Set Vref, RX VrefLevel [Byte0]: 55
2822 01:20:57.686480 [Byte1]: 55
2823 01:20:57.690756
2824 01:20:57.690837 Set Vref, RX VrefLevel [Byte0]: 56
2825 01:20:57.694183 [Byte1]: 56
2826 01:20:57.698736
2827 01:20:57.698868 Set Vref, RX VrefLevel [Byte0]: 57
2828 01:20:57.702487 [Byte1]: 57
2829 01:20:57.706428
2830 01:20:57.706555 Set Vref, RX VrefLevel [Byte0]: 58
2831 01:20:57.710267 [Byte1]: 58
2832 01:20:57.714708
2833 01:20:57.714803 Set Vref, RX VrefLevel [Byte0]: 59
2834 01:20:57.717888 [Byte1]: 59
2835 01:20:57.722517
2836 01:20:57.722613 Set Vref, RX VrefLevel [Byte0]: 60
2837 01:20:57.725661 [Byte1]: 60
2838 01:20:57.730488
2839 01:20:57.730589 Set Vref, RX VrefLevel [Byte0]: 61
2840 01:20:57.733341 [Byte1]: 61
2841 01:20:57.738195
2842 01:20:57.738363 Set Vref, RX VrefLevel [Byte0]: 62
2843 01:20:57.741417 [Byte1]: 62
2844 01:20:57.746031
2845 01:20:57.746141 Set Vref, RX VrefLevel [Byte0]: 63
2846 01:20:57.749204 [Byte1]: 63
2847 01:20:57.753790
2848 01:20:57.753894 Set Vref, RX VrefLevel [Byte0]: 64
2849 01:20:57.757053 [Byte1]: 64
2850 01:20:57.761966
2851 01:20:57.762106 Set Vref, RX VrefLevel [Byte0]: 65
2852 01:20:57.765148 [Byte1]: 65
2853 01:20:57.769797
2854 01:20:57.769897 Set Vref, RX VrefLevel [Byte0]: 66
2855 01:20:57.772706 [Byte1]: 66
2856 01:20:57.777599
2857 01:20:57.777706 Set Vref, RX VrefLevel [Byte0]: 67
2858 01:20:57.780655 [Byte1]: 67
2859 01:20:57.785613
2860 01:20:57.785697 Set Vref, RX VrefLevel [Byte0]: 68
2861 01:20:57.788568 [Byte1]: 68
2862 01:20:57.792984
2863 01:20:57.793078 Set Vref, RX VrefLevel [Byte0]: 69
2864 01:20:57.796716 [Byte1]: 69
2865 01:20:57.801069
2866 01:20:57.801174 Set Vref, RX VrefLevel [Byte0]: 70
2867 01:20:57.804647 [Byte1]: 70
2868 01:20:57.808936
2869 01:20:57.809035 Final RX Vref Byte 0 = 53 to rank0
2870 01:20:57.812398 Final RX Vref Byte 1 = 54 to rank0
2871 01:20:57.815278 Final RX Vref Byte 0 = 53 to rank1
2872 01:20:57.818951 Final RX Vref Byte 1 = 54 to rank1==
2873 01:20:57.822178 Dram Type= 6, Freq= 0, CH_0, rank 0
2874 01:20:57.829031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2875 01:20:57.829189 ==
2876 01:20:57.829286 DQS Delay:
2877 01:20:57.829374 DQS0 = 0, DQS1 = 0
2878 01:20:57.831774 DQM Delay:
2879 01:20:57.831858 DQM0 = 120, DQM1 = 112
2880 01:20:57.835509 DQ Delay:
2881 01:20:57.838490 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2882 01:20:57.842232 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2883 01:20:57.845342 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
2884 01:20:57.848913 DQ12 =118, DQ13 =118, DQ14 =124, DQ15 =120
2885 01:20:57.849004
2886 01:20:57.849132
2887 01:20:57.855701 [DQSOSCAuto] RK0, (LSB)MR18= 0x110a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 403 ps
2888 01:20:57.858694 CH0 RK0: MR19=404, MR18=110A
2889 01:20:57.865685 CH0_RK0: MR19=0x404, MR18=0x110A, DQSOSC=403, MR23=63, INC=40, DEC=26
2890 01:20:57.865804
2891 01:20:57.868868 ----->DramcWriteLeveling(PI) begin...
2892 01:20:57.868951 ==
2893 01:20:57.872083 Dram Type= 6, Freq= 0, CH_0, rank 1
2894 01:20:57.875792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2895 01:20:57.875874 ==
2896 01:20:57.879161 Write leveling (Byte 0): 32 => 32
2897 01:20:57.882941 Write leveling (Byte 1): 30 => 30
2898 01:20:57.886023 DramcWriteLeveling(PI) end<-----
2899 01:20:57.886104
2900 01:20:57.886168 ==
2901 01:20:57.889090 Dram Type= 6, Freq= 0, CH_0, rank 1
2902 01:20:57.895860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2903 01:20:57.895943 ==
2904 01:20:57.896006 [Gating] SW mode calibration
2905 01:20:57.905695 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2906 01:20:57.909319 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2907 01:20:57.912300 0 15 0 | B1->B0 | 3131 2e2e | 0 0 | (0 0) (0 0)
2908 01:20:57.919273 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 01:20:57.922881 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 01:20:57.925980 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2911 01:20:57.932538 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2912 01:20:57.935562 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2913 01:20:57.938828 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2914 01:20:57.945554 0 15 28 | B1->B0 | 2e2e 2e2e | 0 0 | (0 1) (0 1)
2915 01:20:57.949396 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 01:20:57.952719 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 01:20:57.959065 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 01:20:57.962341 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2919 01:20:57.965869 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2920 01:20:57.972054 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2921 01:20:57.975943 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2922 01:20:57.978981 1 0 28 | B1->B0 | 3c3c 3737 | 0 1 | (0 0) (0 0)
2923 01:20:57.985579 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 01:20:57.988580 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 01:20:57.992336 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 01:20:57.999078 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 01:20:58.002064 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 01:20:58.005717 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2929 01:20:58.012374 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2930 01:20:58.015212 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2931 01:20:58.019024 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 01:20:58.022184 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 01:20:58.028723 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 01:20:58.031782 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 01:20:58.035575 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 01:20:58.042179 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 01:20:58.045491 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 01:20:58.048718 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 01:20:58.055318 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 01:20:58.059053 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 01:20:58.062260 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 01:20:58.068681 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 01:20:58.072091 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 01:20:58.075776 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 01:20:58.082664 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 01:20:58.085454 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2947 01:20:58.088883 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2948 01:20:58.092689 Total UI for P1: 0, mck2ui 16
2949 01:20:58.095518 best dqsien dly found for B0: ( 1, 3, 28)
2950 01:20:58.099269 Total UI for P1: 0, mck2ui 16
2951 01:20:58.102414 best dqsien dly found for B1: ( 1, 3, 28)
2952 01:20:58.105895 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2953 01:20:58.108986 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2954 01:20:58.109069
2955 01:20:58.112446 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2956 01:20:58.115596 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2957 01:20:58.119202 [Gating] SW calibration Done
2958 01:20:58.119284 ==
2959 01:20:58.122406 Dram Type= 6, Freq= 0, CH_0, rank 1
2960 01:20:58.126220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2961 01:20:58.129261 ==
2962 01:20:58.129344 RX Vref Scan: 0
2963 01:20:58.129408
2964 01:20:58.132420 RX Vref 0 -> 0, step: 1
2965 01:20:58.132502
2966 01:20:58.135854 RX Delay -40 -> 252, step: 8
2967 01:20:58.139634 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2968 01:20:58.142446 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2969 01:20:58.145831 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2970 01:20:58.149552 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2971 01:20:58.155875 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2972 01:20:58.158897 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2973 01:20:58.162769 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
2974 01:20:58.165935 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2975 01:20:58.169181 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
2976 01:20:58.175947 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2977 01:20:58.179336 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2978 01:20:58.182263 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2979 01:20:58.185814 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2980 01:20:58.188958 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2981 01:20:58.196214 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2982 01:20:58.199509 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2983 01:20:58.199596 ==
2984 01:20:58.202664 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 01:20:58.206091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 01:20:58.206174 ==
2987 01:20:58.206238 DQS Delay:
2988 01:20:58.209277 DQS0 = 0, DQS1 = 0
2989 01:20:58.209359 DQM Delay:
2990 01:20:58.212865 DQM0 = 121, DQM1 = 114
2991 01:20:58.212947 DQ Delay:
2992 01:20:58.216046 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2993 01:20:58.219201 DQ4 =127, DQ5 =115, DQ6 =123, DQ7 =127
2994 01:20:58.222702 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =107
2995 01:20:58.229541 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2996 01:20:58.229643
2997 01:20:58.229731
2998 01:20:58.229813 ==
2999 01:20:58.232516 Dram Type= 6, Freq= 0, CH_0, rank 1
3000 01:20:58.235767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3001 01:20:58.235849 ==
3002 01:20:58.235913
3003 01:20:58.235973
3004 01:20:58.239499 TX Vref Scan disable
3005 01:20:58.239581 == TX Byte 0 ==
3006 01:20:58.246233 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3007 01:20:58.249213 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3008 01:20:58.249295 == TX Byte 1 ==
3009 01:20:58.256427 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3010 01:20:58.259384 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3011 01:20:58.259466 ==
3012 01:20:58.262826 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 01:20:58.265962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 01:20:58.266051 ==
3015 01:20:58.278850 TX Vref=22, minBit 1, minWin=25, winSum=416
3016 01:20:58.281589 TX Vref=24, minBit 0, minWin=25, winSum=420
3017 01:20:58.285179 TX Vref=26, minBit 0, minWin=26, winSum=427
3018 01:20:58.288315 TX Vref=28, minBit 1, minWin=26, winSum=431
3019 01:20:58.292022 TX Vref=30, minBit 1, minWin=26, winSum=431
3020 01:20:58.294979 TX Vref=32, minBit 1, minWin=26, winSum=428
3021 01:20:58.302236 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 28
3022 01:20:58.302345
3023 01:20:58.305247 Final TX Range 1 Vref 28
3024 01:20:58.305327
3025 01:20:58.305391 ==
3026 01:20:58.308271 Dram Type= 6, Freq= 0, CH_0, rank 1
3027 01:20:58.312133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3028 01:20:58.312215 ==
3029 01:20:58.312278
3030 01:20:58.314893
3031 01:20:58.314973 TX Vref Scan disable
3032 01:20:58.318228 == TX Byte 0 ==
3033 01:20:58.322086 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3034 01:20:58.324981 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3035 01:20:58.328766 == TX Byte 1 ==
3036 01:20:58.332008 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3037 01:20:58.335381 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3038 01:20:58.335472
3039 01:20:58.338835 [DATLAT]
3040 01:20:58.338917 Freq=1200, CH0 RK1
3041 01:20:58.338982
3042 01:20:58.341790 DATLAT Default: 0xd
3043 01:20:58.341871 0, 0xFFFF, sum = 0
3044 01:20:58.344927 1, 0xFFFF, sum = 0
3045 01:20:58.345009 2, 0xFFFF, sum = 0
3046 01:20:58.348551 3, 0xFFFF, sum = 0
3047 01:20:58.348634 4, 0xFFFF, sum = 0
3048 01:20:58.351875 5, 0xFFFF, sum = 0
3049 01:20:58.351958 6, 0xFFFF, sum = 0
3050 01:20:58.355655 7, 0xFFFF, sum = 0
3051 01:20:58.355736 8, 0xFFFF, sum = 0
3052 01:20:58.358810 9, 0xFFFF, sum = 0
3053 01:20:58.362415 10, 0xFFFF, sum = 0
3054 01:20:58.362496 11, 0xFFFF, sum = 0
3055 01:20:58.365460 12, 0x0, sum = 1
3056 01:20:58.365545 13, 0x0, sum = 2
3057 01:20:58.365618 14, 0x0, sum = 3
3058 01:20:58.368598 15, 0x0, sum = 4
3059 01:20:58.368679 best_step = 13
3060 01:20:58.368741
3061 01:20:58.368799 ==
3062 01:20:58.372181 Dram Type= 6, Freq= 0, CH_0, rank 1
3063 01:20:58.378399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3064 01:20:58.378479 ==
3065 01:20:58.378542 RX Vref Scan: 0
3066 01:20:58.378603
3067 01:20:58.382064 RX Vref 0 -> 0, step: 1
3068 01:20:58.382143
3069 01:20:58.385188 RX Delay -13 -> 252, step: 4
3070 01:20:58.388418 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3071 01:20:58.391965 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3072 01:20:58.398724 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3073 01:20:58.401815 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3074 01:20:58.405591 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3075 01:20:58.408609 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3076 01:20:58.411624 iDelay=195, Bit 6, Center 126 (63 ~ 190) 128
3077 01:20:58.418340 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3078 01:20:58.421885 iDelay=195, Bit 8, Center 102 (35 ~ 170) 136
3079 01:20:58.425343 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3080 01:20:58.428601 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3081 01:20:58.431796 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3082 01:20:58.438474 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3083 01:20:58.442133 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3084 01:20:58.445297 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3085 01:20:58.448936 iDelay=195, Bit 15, Center 120 (59 ~ 182) 124
3086 01:20:58.449017 ==
3087 01:20:58.452032 Dram Type= 6, Freq= 0, CH_0, rank 1
3088 01:20:58.458561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3089 01:20:58.458641 ==
3090 01:20:58.458704 DQS Delay:
3091 01:20:58.458763 DQS0 = 0, DQS1 = 0
3092 01:20:58.461510 DQM Delay:
3093 01:20:58.461604 DQM0 = 121, DQM1 = 111
3094 01:20:58.465289 DQ Delay:
3095 01:20:58.468613 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =118
3096 01:20:58.471911 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =128
3097 01:20:58.475047 DQ8 =102, DQ9 =100, DQ10 =112, DQ11 =104
3098 01:20:58.478565 DQ12 =116, DQ13 =118, DQ14 =122, DQ15 =120
3099 01:20:58.478645
3100 01:20:58.478708
3101 01:20:58.485409 [DQSOSCAuto] RK1, (LSB)MR18= 0xeee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 404 ps
3102 01:20:58.488733 CH0 RK1: MR19=403, MR18=EEE
3103 01:20:58.495035 CH0_RK1: MR19=0x403, MR18=0xEEE, DQSOSC=404, MR23=63, INC=40, DEC=26
3104 01:20:58.498848 [RxdqsGatingPostProcess] freq 1200
3105 01:20:58.505044 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3106 01:20:58.508802 best DQS0 dly(2T, 0.5T) = (0, 11)
3107 01:20:58.508884 best DQS1 dly(2T, 0.5T) = (0, 11)
3108 01:20:58.511945 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3109 01:20:58.515032 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3110 01:20:58.518837 best DQS0 dly(2T, 0.5T) = (0, 11)
3111 01:20:58.521944 best DQS1 dly(2T, 0.5T) = (0, 11)
3112 01:20:58.525025 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3113 01:20:58.528573 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3114 01:20:58.532036 Pre-setting of DQS Precalculation
3115 01:20:58.538734 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3116 01:20:58.538817 ==
3117 01:20:58.542266 Dram Type= 6, Freq= 0, CH_1, rank 0
3118 01:20:58.545198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3119 01:20:58.545279 ==
3120 01:20:58.552247 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3121 01:20:58.555543 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3122 01:20:58.564698 [CA 0] Center 37 (7~68) winsize 62
3123 01:20:58.568194 [CA 1] Center 37 (7~68) winsize 62
3124 01:20:58.571701 [CA 2] Center 35 (5~65) winsize 61
3125 01:20:58.574997 [CA 3] Center 34 (4~64) winsize 61
3126 01:20:58.578265 [CA 4] Center 34 (4~64) winsize 61
3127 01:20:58.581742 [CA 5] Center 33 (3~63) winsize 61
3128 01:20:58.581822
3129 01:20:58.584997 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3130 01:20:58.585078
3131 01:20:58.588372 [CATrainingPosCal] consider 1 rank data
3132 01:20:58.591229 u2DelayCellTimex100 = 270/100 ps
3133 01:20:58.594862 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3134 01:20:58.598261 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3135 01:20:58.604907 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3136 01:20:58.608255 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3137 01:20:58.611294 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3138 01:20:58.614408 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3139 01:20:58.614488
3140 01:20:58.618101 CA PerBit enable=1, Macro0, CA PI delay=33
3141 01:20:58.618181
3142 01:20:58.621435 [CBTSetCACLKResult] CA Dly = 33
3143 01:20:58.621515 CS Dly: 8 (0~39)
3144 01:20:58.624993 ==
3145 01:20:58.625073 Dram Type= 6, Freq= 0, CH_1, rank 1
3146 01:20:58.631260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3147 01:20:58.631341 ==
3148 01:20:58.634548 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3149 01:20:58.641022 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3150 01:20:58.650252 [CA 0] Center 37 (7~68) winsize 62
3151 01:20:58.653465 [CA 1] Center 38 (7~69) winsize 63
3152 01:20:58.657352 [CA 2] Center 35 (5~65) winsize 61
3153 01:20:58.660477 [CA 3] Center 34 (4~65) winsize 62
3154 01:20:58.663687 [CA 4] Center 34 (4~65) winsize 62
3155 01:20:58.667305 [CA 5] Center 33 (4~63) winsize 60
3156 01:20:58.667385
3157 01:20:58.670333 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3158 01:20:58.670427
3159 01:20:58.673899 [CATrainingPosCal] consider 2 rank data
3160 01:20:58.677220 u2DelayCellTimex100 = 270/100 ps
3161 01:20:58.680517 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3162 01:20:58.683805 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3163 01:20:58.687686 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3164 01:20:58.694036 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3165 01:20:58.696974 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3166 01:20:58.700353 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3167 01:20:58.700427
3168 01:20:58.703941 CA PerBit enable=1, Macro0, CA PI delay=33
3169 01:20:58.704038
3170 01:20:58.706940 [CBTSetCACLKResult] CA Dly = 33
3171 01:20:58.707039 CS Dly: 9 (0~41)
3172 01:20:58.707117
3173 01:20:58.710537 ----->DramcWriteLeveling(PI) begin...
3174 01:20:58.710619 ==
3175 01:20:58.713937 Dram Type= 6, Freq= 0, CH_1, rank 0
3176 01:20:58.720325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3177 01:20:58.720416 ==
3178 01:20:58.723891 Write leveling (Byte 0): 24 => 24
3179 01:20:58.727158 Write leveling (Byte 1): 27 => 27
3180 01:20:58.730184 DramcWriteLeveling(PI) end<-----
3181 01:20:58.730293
3182 01:20:58.730385 ==
3183 01:20:58.734112 Dram Type= 6, Freq= 0, CH_1, rank 0
3184 01:20:58.737367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3185 01:20:58.737501 ==
3186 01:20:58.740417 [Gating] SW mode calibration
3187 01:20:58.747125 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3188 01:20:58.750194 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3189 01:20:58.757474 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 01:20:58.760608 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 01:20:58.763749 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 01:20:58.770185 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3193 01:20:58.774083 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3194 01:20:58.777229 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3195 01:20:58.783561 0 15 24 | B1->B0 | 3333 2c2c | 0 0 | (0 1) (0 1)
3196 01:20:58.787262 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
3197 01:20:58.790540 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 01:20:58.796882 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 01:20:58.800562 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 01:20:58.803891 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 01:20:58.810277 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3202 01:20:58.813433 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3203 01:20:58.816702 1 0 24 | B1->B0 | 3a3a 4343 | 0 0 | (1 1) (0 0)
3204 01:20:58.823425 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 01:20:58.826714 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 01:20:58.830089 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 01:20:58.837054 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 01:20:58.839968 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 01:20:58.843213 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 01:20:58.850237 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 01:20:58.853414 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3212 01:20:58.857133 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3213 01:20:58.860099 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 01:20:58.866930 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 01:20:58.869915 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 01:20:58.873563 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 01:20:58.880526 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 01:20:58.883303 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 01:20:58.887151 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 01:20:58.893353 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 01:20:58.896951 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 01:20:58.900071 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 01:20:58.906716 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 01:20:58.910267 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 01:20:58.913723 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 01:20:58.920671 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 01:20:58.923836 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3228 01:20:58.927024 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3229 01:20:58.930235 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3230 01:20:58.933877 Total UI for P1: 0, mck2ui 16
3231 01:20:58.937083 best dqsien dly found for B0: ( 1, 3, 26)
3232 01:20:58.940163 Total UI for P1: 0, mck2ui 16
3233 01:20:58.943461 best dqsien dly found for B1: ( 1, 3, 26)
3234 01:20:58.947273 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3235 01:20:58.950502 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3236 01:20:58.953929
3237 01:20:58.957231 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3238 01:20:58.960140 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3239 01:20:58.963733 [Gating] SW calibration Done
3240 01:20:58.963819 ==
3241 01:20:58.967413 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 01:20:58.970608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 01:20:58.970756 ==
3244 01:20:58.970855 RX Vref Scan: 0
3245 01:20:58.970951
3246 01:20:58.973753 RX Vref 0 -> 0, step: 1
3247 01:20:58.973863
3248 01:20:58.977253 RX Delay -40 -> 252, step: 8
3249 01:20:58.980627 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3250 01:20:58.983756 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3251 01:20:58.990724 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3252 01:20:58.993848 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3253 01:20:58.997323 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3254 01:20:59.000784 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3255 01:20:59.003962 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3256 01:20:59.007160 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3257 01:20:59.014086 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3258 01:20:59.016920 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3259 01:20:59.020548 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3260 01:20:59.023919 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3261 01:20:59.027047 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3262 01:20:59.033980 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3263 01:20:59.037245 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3264 01:20:59.040439 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3265 01:20:59.040557 ==
3266 01:20:59.043765 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 01:20:59.047580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 01:20:59.050759 ==
3269 01:20:59.050873 DQS Delay:
3270 01:20:59.050970 DQS0 = 0, DQS1 = 0
3271 01:20:59.053945 DQM Delay:
3272 01:20:59.054055 DQM0 = 119, DQM1 = 116
3273 01:20:59.057150 DQ Delay:
3274 01:20:59.060961 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3275 01:20:59.064352 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3276 01:20:59.067265 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3277 01:20:59.070481 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3278 01:20:59.070564
3279 01:20:59.070628
3280 01:20:59.070688 ==
3281 01:20:59.074217 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 01:20:59.077375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 01:20:59.077459 ==
3284 01:20:59.077523
3285 01:20:59.077583
3286 01:20:59.080700 TX Vref Scan disable
3287 01:20:59.083811 == TX Byte 0 ==
3288 01:20:59.088456 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3289 01:20:59.090756 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3290 01:20:59.094211 == TX Byte 1 ==
3291 01:20:59.097696 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3292 01:20:59.100419 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3293 01:20:59.100503 ==
3294 01:20:59.104122 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 01:20:59.107067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 01:20:59.110254 ==
3297 01:20:59.120831 TX Vref=22, minBit 1, minWin=25, winSum=411
3298 01:20:59.124019 TX Vref=24, minBit 1, minWin=25, winSum=419
3299 01:20:59.127301 TX Vref=26, minBit 1, minWin=26, winSum=423
3300 01:20:59.130666 TX Vref=28, minBit 2, minWin=26, winSum=428
3301 01:20:59.133978 TX Vref=30, minBit 9, minWin=26, winSum=428
3302 01:20:59.137216 TX Vref=32, minBit 9, minWin=26, winSum=433
3303 01:20:59.144063 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 32
3304 01:20:59.144154
3305 01:20:59.147500 Final TX Range 1 Vref 32
3306 01:20:59.147583
3307 01:20:59.147648 ==
3308 01:20:59.150590 Dram Type= 6, Freq= 0, CH_1, rank 0
3309 01:20:59.154486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3310 01:20:59.154569 ==
3311 01:20:59.154634
3312 01:20:59.154694
3313 01:20:59.157694 TX Vref Scan disable
3314 01:20:59.160893 == TX Byte 0 ==
3315 01:20:59.164074 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3316 01:20:59.167401 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3317 01:20:59.171101 == TX Byte 1 ==
3318 01:20:59.174241 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3319 01:20:59.177384 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3320 01:20:59.177466
3321 01:20:59.180739 [DATLAT]
3322 01:20:59.180821 Freq=1200, CH1 RK0
3323 01:20:59.180886
3324 01:20:59.183839 DATLAT Default: 0xd
3325 01:20:59.183920 0, 0xFFFF, sum = 0
3326 01:20:59.187792 1, 0xFFFF, sum = 0
3327 01:20:59.187875 2, 0xFFFF, sum = 0
3328 01:20:59.190822 3, 0xFFFF, sum = 0
3329 01:20:59.190905 4, 0xFFFF, sum = 0
3330 01:20:59.194073 5, 0xFFFF, sum = 0
3331 01:20:59.194156 6, 0xFFFF, sum = 0
3332 01:20:59.197745 7, 0xFFFF, sum = 0
3333 01:20:59.197827 8, 0xFFFF, sum = 0
3334 01:20:59.201126 9, 0xFFFF, sum = 0
3335 01:20:59.201210 10, 0xFFFF, sum = 0
3336 01:20:59.204015 11, 0xFFFF, sum = 0
3337 01:20:59.204097 12, 0x0, sum = 1
3338 01:20:59.207534 13, 0x0, sum = 2
3339 01:20:59.207616 14, 0x0, sum = 3
3340 01:20:59.210846 15, 0x0, sum = 4
3341 01:20:59.210943 best_step = 13
3342 01:20:59.211008
3343 01:20:59.211068 ==
3344 01:20:59.214066 Dram Type= 6, Freq= 0, CH_1, rank 0
3345 01:20:59.220968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3346 01:20:59.221064 ==
3347 01:20:59.221129 RX Vref Scan: 1
3348 01:20:59.221189
3349 01:20:59.224158 Set Vref Range= 32 -> 127
3350 01:20:59.224240
3351 01:20:59.227373 RX Vref 32 -> 127, step: 1
3352 01:20:59.227455
3353 01:20:59.227518 RX Delay -5 -> 252, step: 4
3354 01:20:59.231038
3355 01:20:59.231119 Set Vref, RX VrefLevel [Byte0]: 32
3356 01:20:59.234333 [Byte1]: 32
3357 01:20:59.238633
3358 01:20:59.238716 Set Vref, RX VrefLevel [Byte0]: 33
3359 01:20:59.242217 [Byte1]: 33
3360 01:20:59.247080
3361 01:20:59.247176 Set Vref, RX VrefLevel [Byte0]: 34
3362 01:20:59.250135 [Byte1]: 34
3363 01:20:59.254672
3364 01:20:59.254772 Set Vref, RX VrefLevel [Byte0]: 35
3365 01:20:59.258024 [Byte1]: 35
3366 01:20:59.262259
3367 01:20:59.262388 Set Vref, RX VrefLevel [Byte0]: 36
3368 01:20:59.265871 [Byte1]: 36
3369 01:20:59.270025
3370 01:20:59.270132 Set Vref, RX VrefLevel [Byte0]: 37
3371 01:20:59.273425 [Byte1]: 37
3372 01:20:59.277916
3373 01:20:59.278019 Set Vref, RX VrefLevel [Byte0]: 38
3374 01:20:59.281471 [Byte1]: 38
3375 01:20:59.285854
3376 01:20:59.285960 Set Vref, RX VrefLevel [Byte0]: 39
3377 01:20:59.289186 [Byte1]: 39
3378 01:20:59.293499
3379 01:20:59.293598 Set Vref, RX VrefLevel [Byte0]: 40
3380 01:20:59.296812 [Byte1]: 40
3381 01:20:59.301613
3382 01:20:59.301687 Set Vref, RX VrefLevel [Byte0]: 41
3383 01:20:59.304754 [Byte1]: 41
3384 01:20:59.309213
3385 01:20:59.309290 Set Vref, RX VrefLevel [Byte0]: 42
3386 01:20:59.312671 [Byte1]: 42
3387 01:20:59.317272
3388 01:20:59.317374 Set Vref, RX VrefLevel [Byte0]: 43
3389 01:20:59.320682 [Byte1]: 43
3390 01:20:59.324975
3391 01:20:59.325076 Set Vref, RX VrefLevel [Byte0]: 44
3392 01:20:59.328717 [Byte1]: 44
3393 01:20:59.333250
3394 01:20:59.333357 Set Vref, RX VrefLevel [Byte0]: 45
3395 01:20:59.336322 [Byte1]: 45
3396 01:20:59.341281
3397 01:20:59.341398 Set Vref, RX VrefLevel [Byte0]: 46
3398 01:20:59.344439 [Byte1]: 46
3399 01:20:59.348888
3400 01:20:59.348990 Set Vref, RX VrefLevel [Byte0]: 47
3401 01:20:59.352171 [Byte1]: 47
3402 01:20:59.356665
3403 01:20:59.356781 Set Vref, RX VrefLevel [Byte0]: 48
3404 01:20:59.359630 [Byte1]: 48
3405 01:20:59.364381
3406 01:20:59.364501 Set Vref, RX VrefLevel [Byte0]: 49
3407 01:20:59.367730 [Byte1]: 49
3408 01:20:59.372209
3409 01:20:59.372309 Set Vref, RX VrefLevel [Byte0]: 50
3410 01:20:59.375863 [Byte1]: 50
3411 01:20:59.380090
3412 01:20:59.380191 Set Vref, RX VrefLevel [Byte0]: 51
3413 01:20:59.383613 [Byte1]: 51
3414 01:20:59.387836
3415 01:20:59.387917 Set Vref, RX VrefLevel [Byte0]: 52
3416 01:20:59.391375 [Byte1]: 52
3417 01:20:59.395594
3418 01:20:59.395698 Set Vref, RX VrefLevel [Byte0]: 53
3419 01:20:59.399570 [Byte1]: 53
3420 01:20:59.403869
3421 01:20:59.403943 Set Vref, RX VrefLevel [Byte0]: 54
3422 01:20:59.406979 [Byte1]: 54
3423 01:20:59.411549
3424 01:20:59.411624 Set Vref, RX VrefLevel [Byte0]: 55
3425 01:20:59.415077 [Byte1]: 55
3426 01:20:59.419295
3427 01:20:59.419382 Set Vref, RX VrefLevel [Byte0]: 56
3428 01:20:59.422467 [Byte1]: 56
3429 01:20:59.427163
3430 01:20:59.427239 Set Vref, RX VrefLevel [Byte0]: 57
3431 01:20:59.430516 [Byte1]: 57
3432 01:20:59.435007
3433 01:20:59.435109 Set Vref, RX VrefLevel [Byte0]: 58
3434 01:20:59.438143 [Byte1]: 58
3435 01:20:59.442995
3436 01:20:59.443077 Set Vref, RX VrefLevel [Byte0]: 59
3437 01:20:59.446268 [Byte1]: 59
3438 01:20:59.450676
3439 01:20:59.450758 Set Vref, RX VrefLevel [Byte0]: 60
3440 01:20:59.454040 [Byte1]: 60
3441 01:20:59.458468
3442 01:20:59.458549 Set Vref, RX VrefLevel [Byte0]: 61
3443 01:20:59.461587 [Byte1]: 61
3444 01:20:59.466566
3445 01:20:59.466658 Set Vref, RX VrefLevel [Byte0]: 62
3446 01:20:59.469661 [Byte1]: 62
3447 01:20:59.474140
3448 01:20:59.474221 Set Vref, RX VrefLevel [Byte0]: 63
3449 01:20:59.477897 [Byte1]: 63
3450 01:20:59.482344
3451 01:20:59.482425 Set Vref, RX VrefLevel [Byte0]: 64
3452 01:20:59.485485 [Byte1]: 64
3453 01:20:59.489844
3454 01:20:59.489925 Set Vref, RX VrefLevel [Byte0]: 65
3455 01:20:59.493628 [Byte1]: 65
3456 01:20:59.498000
3457 01:20:59.498098 Set Vref, RX VrefLevel [Byte0]: 66
3458 01:20:59.501073 [Byte1]: 66
3459 01:20:59.505480
3460 01:20:59.505579 Set Vref, RX VrefLevel [Byte0]: 67
3461 01:20:59.509242 [Byte1]: 67
3462 01:20:59.513291
3463 01:20:59.513372 Final RX Vref Byte 0 = 54 to rank0
3464 01:20:59.516934 Final RX Vref Byte 1 = 48 to rank0
3465 01:20:59.520205 Final RX Vref Byte 0 = 54 to rank1
3466 01:20:59.523561 Final RX Vref Byte 1 = 48 to rank1==
3467 01:20:59.527297 Dram Type= 6, Freq= 0, CH_1, rank 0
3468 01:20:59.533643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3469 01:20:59.533726 ==
3470 01:20:59.533791 DQS Delay:
3471 01:20:59.533851 DQS0 = 0, DQS1 = 0
3472 01:20:59.537051 DQM Delay:
3473 01:20:59.537170 DQM0 = 120, DQM1 = 116
3474 01:20:59.540445 DQ Delay:
3475 01:20:59.543853 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3476 01:20:59.547098 DQ4 =120, DQ5 =128, DQ6 =130, DQ7 =120
3477 01:20:59.550229 DQ8 =102, DQ9 =106, DQ10 =118, DQ11 =108
3478 01:20:59.553607 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3479 01:20:59.553712
3480 01:20:59.553806
3481 01:20:59.560242 [DQSOSCAuto] RK0, (LSB)MR18= 0xfc0f, (MSB)MR19= 0x304, tDQSOscB0 = 404 ps tDQSOscB1 = 411 ps
3482 01:20:59.563986 CH1 RK0: MR19=304, MR18=FC0F
3483 01:20:59.570463 CH1_RK0: MR19=0x304, MR18=0xFC0F, DQSOSC=404, MR23=63, INC=40, DEC=26
3484 01:20:59.570568
3485 01:20:59.573557 ----->DramcWriteLeveling(PI) begin...
3486 01:20:59.573663 ==
3487 01:20:59.577134 Dram Type= 6, Freq= 0, CH_1, rank 1
3488 01:20:59.580087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3489 01:20:59.583291 ==
3490 01:20:59.583366 Write leveling (Byte 0): 27 => 27
3491 01:20:59.587052 Write leveling (Byte 1): 29 => 29
3492 01:20:59.590102 DramcWriteLeveling(PI) end<-----
3493 01:20:59.590198
3494 01:20:59.590289 ==
3495 01:20:59.593299 Dram Type= 6, Freq= 0, CH_1, rank 1
3496 01:20:59.600210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3497 01:20:59.600340 ==
3498 01:20:59.600458 [Gating] SW mode calibration
3499 01:20:59.610281 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3500 01:20:59.613430 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3501 01:20:59.616685 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 01:20:59.623787 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 01:20:59.626824 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3504 01:20:59.629959 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3505 01:20:59.636861 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3506 01:20:59.640378 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3507 01:20:59.643314 0 15 24 | B1->B0 | 2c2c 3434 | 0 1 | (1 0) (1 0)
3508 01:20:59.649951 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3509 01:20:59.653760 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 01:20:59.656574 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 01:20:59.663241 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3512 01:20:59.666541 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3513 01:20:59.669841 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3514 01:20:59.676747 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3515 01:20:59.679814 1 0 24 | B1->B0 | 4141 2626 | 0 0 | (0 0) (0 0)
3516 01:20:59.683624 1 0 28 | B1->B0 | 4646 4545 | 0 1 | (0 0) (0 0)
3517 01:20:59.689787 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 01:20:59.693409 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 01:20:59.696792 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 01:20:59.703157 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 01:20:59.706838 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 01:20:59.709833 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3523 01:20:59.716285 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3524 01:20:59.719631 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 01:20:59.723058 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 01:20:59.729511 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 01:20:59.733313 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 01:20:59.736422 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 01:20:59.743437 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 01:20:59.746213 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 01:20:59.750012 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 01:20:59.756356 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 01:20:59.759756 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 01:20:59.763269 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 01:20:59.766015 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 01:20:59.773085 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 01:20:59.776341 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 01:20:59.779291 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3539 01:20:59.786050 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3540 01:20:59.789292 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3541 01:20:59.793327 Total UI for P1: 0, mck2ui 16
3542 01:20:59.796282 best dqsien dly found for B1: ( 1, 3, 22)
3543 01:20:59.799749 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3544 01:20:59.803128 Total UI for P1: 0, mck2ui 16
3545 01:20:59.806010 best dqsien dly found for B0: ( 1, 3, 26)
3546 01:20:59.809735 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3547 01:20:59.813086 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3548 01:20:59.813183
3549 01:20:59.819802 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3550 01:20:59.823009 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3551 01:20:59.825887 [Gating] SW calibration Done
3552 01:20:59.825969 ==
3553 01:20:59.829357 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 01:20:59.833045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 01:20:59.833128 ==
3556 01:20:59.833194 RX Vref Scan: 0
3557 01:20:59.833256
3558 01:20:59.836086 RX Vref 0 -> 0, step: 1
3559 01:20:59.836169
3560 01:20:59.839198 RX Delay -40 -> 252, step: 8
3561 01:20:59.842356 iDelay=200, Bit 0, Center 127 (64 ~ 191) 128
3562 01:20:59.846098 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3563 01:20:59.852317 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3564 01:20:59.855814 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3565 01:20:59.859220 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3566 01:20:59.862274 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3567 01:20:59.865622 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3568 01:20:59.872316 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3569 01:20:59.875853 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3570 01:20:59.879545 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3571 01:20:59.882308 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3572 01:20:59.885668 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3573 01:20:59.892697 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3574 01:20:59.895466 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3575 01:20:59.899163 iDelay=200, Bit 14, Center 119 (56 ~ 183) 128
3576 01:20:59.902673 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3577 01:20:59.902758 ==
3578 01:20:59.905549 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 01:20:59.912228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 01:20:59.912317 ==
3581 01:20:59.912382 DQS Delay:
3582 01:20:59.915921 DQS0 = 0, DQS1 = 0
3583 01:20:59.916004 DQM Delay:
3584 01:20:59.916070 DQM0 = 120, DQM1 = 118
3585 01:20:59.918868 DQ Delay:
3586 01:20:59.922188 DQ0 =127, DQ1 =115, DQ2 =107, DQ3 =115
3587 01:20:59.925668 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3588 01:20:59.928938 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115
3589 01:20:59.931889 DQ12 =127, DQ13 =127, DQ14 =119, DQ15 =127
3590 01:20:59.931973
3591 01:20:59.932037
3592 01:20:59.932096 ==
3593 01:20:59.935855 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 01:20:59.941974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 01:20:59.942131 ==
3596 01:20:59.942226
3597 01:20:59.942323
3598 01:20:59.942396 TX Vref Scan disable
3599 01:20:59.945525 == TX Byte 0 ==
3600 01:20:59.948548 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3601 01:20:59.952277 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3602 01:20:59.955635 == TX Byte 1 ==
3603 01:20:59.958672 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3604 01:20:59.962225 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3605 01:20:59.965395 ==
3606 01:20:59.968474 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 01:20:59.971667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 01:20:59.971749 ==
3609 01:20:59.983196 TX Vref=22, minBit 0, minWin=26, winSum=420
3610 01:20:59.986002 TX Vref=24, minBit 1, minWin=26, winSum=423
3611 01:20:59.989786 TX Vref=26, minBit 10, minWin=25, winSum=426
3612 01:20:59.992731 TX Vref=28, minBit 10, minWin=26, winSum=433
3613 01:20:59.996043 TX Vref=30, minBit 9, minWin=26, winSum=432
3614 01:21:00.002770 TX Vref=32, minBit 9, minWin=26, winSum=436
3615 01:21:00.005833 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 32
3616 01:21:00.005935
3617 01:21:00.009558 Final TX Range 1 Vref 32
3618 01:21:00.009640
3619 01:21:00.009703 ==
3620 01:21:00.012594 Dram Type= 6, Freq= 0, CH_1, rank 1
3621 01:21:00.016343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3622 01:21:00.019339 ==
3623 01:21:00.019421
3624 01:21:00.019484
3625 01:21:00.019542 TX Vref Scan disable
3626 01:21:00.023170 == TX Byte 0 ==
3627 01:21:00.026426 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3628 01:21:00.032610 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3629 01:21:00.032722 == TX Byte 1 ==
3630 01:21:00.036321 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3631 01:21:00.042571 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3632 01:21:00.042691
3633 01:21:00.042783 [DATLAT]
3634 01:21:00.042871 Freq=1200, CH1 RK1
3635 01:21:00.042957
3636 01:21:00.045966 DATLAT Default: 0xd
3637 01:21:00.046047 0, 0xFFFF, sum = 0
3638 01:21:00.049185 1, 0xFFFF, sum = 0
3639 01:21:00.052653 2, 0xFFFF, sum = 0
3640 01:21:00.052741 3, 0xFFFF, sum = 0
3641 01:21:00.055953 4, 0xFFFF, sum = 0
3642 01:21:00.056091 5, 0xFFFF, sum = 0
3643 01:21:00.059438 6, 0xFFFF, sum = 0
3644 01:21:00.059523 7, 0xFFFF, sum = 0
3645 01:21:00.062490 8, 0xFFFF, sum = 0
3646 01:21:00.062578 9, 0xFFFF, sum = 0
3647 01:21:00.065693 10, 0xFFFF, sum = 0
3648 01:21:00.065779 11, 0xFFFF, sum = 0
3649 01:21:00.069195 12, 0x0, sum = 1
3650 01:21:00.069285 13, 0x0, sum = 2
3651 01:21:00.072393 14, 0x0, sum = 3
3652 01:21:00.072482 15, 0x0, sum = 4
3653 01:21:00.076610 best_step = 13
3654 01:21:00.076692
3655 01:21:00.076755 ==
3656 01:21:00.079121 Dram Type= 6, Freq= 0, CH_1, rank 1
3657 01:21:00.082412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3658 01:21:00.082495 ==
3659 01:21:00.082559 RX Vref Scan: 0
3660 01:21:00.086161
3661 01:21:00.086270 RX Vref 0 -> 0, step: 1
3662 01:21:00.086387
3663 01:21:00.089228 RX Delay -5 -> 252, step: 4
3664 01:21:00.092353 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3665 01:21:00.099185 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3666 01:21:00.102153 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3667 01:21:00.105901 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3668 01:21:00.108950 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3669 01:21:00.112097 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3670 01:21:00.119020 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3671 01:21:00.122460 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3672 01:21:00.125442 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3673 01:21:00.128725 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3674 01:21:00.132608 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3675 01:21:00.139169 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3676 01:21:00.142246 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3677 01:21:00.145359 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3678 01:21:00.148894 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3679 01:21:00.155877 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3680 01:21:00.155959 ==
3681 01:21:00.158968 Dram Type= 6, Freq= 0, CH_1, rank 1
3682 01:21:00.162230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3683 01:21:00.162398 ==
3684 01:21:00.162480 DQS Delay:
3685 01:21:00.165635 DQS0 = 0, DQS1 = 0
3686 01:21:00.165717 DQM Delay:
3687 01:21:00.168891 DQM0 = 120, DQM1 = 116
3688 01:21:00.168973 DQ Delay:
3689 01:21:00.172352 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3690 01:21:00.175253 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3691 01:21:00.178548 DQ8 =106, DQ9 =106, DQ10 =116, DQ11 =110
3692 01:21:00.182121 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124
3693 01:21:00.182227
3694 01:21:00.182343
3695 01:21:00.191934 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3696 01:21:00.194959 CH1 RK1: MR19=403, MR18=10ED
3697 01:21:00.198845 CH1_RK1: MR19=0x403, MR18=0x10ED, DQSOSC=403, MR23=63, INC=40, DEC=26
3698 01:21:00.201756 [RxdqsGatingPostProcess] freq 1200
3699 01:21:00.208619 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3700 01:21:00.211819 best DQS0 dly(2T, 0.5T) = (0, 11)
3701 01:21:00.214845 best DQS1 dly(2T, 0.5T) = (0, 11)
3702 01:21:00.218043 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3703 01:21:00.221798 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3704 01:21:00.225111 best DQS0 dly(2T, 0.5T) = (0, 11)
3705 01:21:00.228100 best DQS1 dly(2T, 0.5T) = (0, 11)
3706 01:21:00.231645 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3707 01:21:00.235290 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3708 01:21:00.238498 Pre-setting of DQS Precalculation
3709 01:21:00.241556 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3710 01:21:00.248334 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3711 01:21:00.254892 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3712 01:21:00.258468
3713 01:21:00.258548
3714 01:21:00.258614 [Calibration Summary] 2400 Mbps
3715 01:21:00.261458 CH 0, Rank 0
3716 01:21:00.261539 SW Impedance : PASS
3717 01:21:00.264922 DUTY Scan : NO K
3718 01:21:00.268052 ZQ Calibration : PASS
3719 01:21:00.268132 Jitter Meter : NO K
3720 01:21:00.271627 CBT Training : PASS
3721 01:21:00.274703 Write leveling : PASS
3722 01:21:00.274784 RX DQS gating : PASS
3723 01:21:00.277837 RX DQ/DQS(RDDQC) : PASS
3724 01:21:00.281349 TX DQ/DQS : PASS
3725 01:21:00.281430 RX DATLAT : PASS
3726 01:21:00.284408 RX DQ/DQS(Engine): PASS
3727 01:21:00.288601 TX OE : NO K
3728 01:21:00.288682 All Pass.
3729 01:21:00.288745
3730 01:21:00.288805 CH 0, Rank 1
3731 01:21:00.291629 SW Impedance : PASS
3732 01:21:00.294462 DUTY Scan : NO K
3733 01:21:00.294542 ZQ Calibration : PASS
3734 01:21:00.297771 Jitter Meter : NO K
3735 01:21:00.301235 CBT Training : PASS
3736 01:21:00.301316 Write leveling : PASS
3737 01:21:00.305178 RX DQS gating : PASS
3738 01:21:00.305258 RX DQ/DQS(RDDQC) : PASS
3739 01:21:00.308035 TX DQ/DQS : PASS
3740 01:21:00.311526 RX DATLAT : PASS
3741 01:21:00.311607 RX DQ/DQS(Engine): PASS
3742 01:21:00.314406 TX OE : NO K
3743 01:21:00.314486 All Pass.
3744 01:21:00.314550
3745 01:21:00.317927 CH 1, Rank 0
3746 01:21:00.318007 SW Impedance : PASS
3747 01:21:00.321409 DUTY Scan : NO K
3748 01:21:00.324688 ZQ Calibration : PASS
3749 01:21:00.324769 Jitter Meter : NO K
3750 01:21:00.327870 CBT Training : PASS
3751 01:21:00.331215 Write leveling : PASS
3752 01:21:00.331295 RX DQS gating : PASS
3753 01:21:00.334356 RX DQ/DQS(RDDQC) : PASS
3754 01:21:00.337906 TX DQ/DQS : PASS
3755 01:21:00.337987 RX DATLAT : PASS
3756 01:21:00.341475 RX DQ/DQS(Engine): PASS
3757 01:21:00.344632 TX OE : NO K
3758 01:21:00.344713 All Pass.
3759 01:21:00.344777
3760 01:21:00.344836 CH 1, Rank 1
3761 01:21:00.347733 SW Impedance : PASS
3762 01:21:00.351486 DUTY Scan : NO K
3763 01:21:00.351566 ZQ Calibration : PASS
3764 01:21:00.354761 Jitter Meter : NO K
3765 01:21:00.357963 CBT Training : PASS
3766 01:21:00.358043 Write leveling : PASS
3767 01:21:00.361062 RX DQS gating : PASS
3768 01:21:00.361142 RX DQ/DQS(RDDQC) : PASS
3769 01:21:00.364375 TX DQ/DQS : PASS
3770 01:21:00.367861 RX DATLAT : PASS
3771 01:21:00.367942 RX DQ/DQS(Engine): PASS
3772 01:21:00.371125 TX OE : NO K
3773 01:21:00.371206 All Pass.
3774 01:21:00.371270
3775 01:21:00.374329 DramC Write-DBI off
3776 01:21:00.377438 PER_BANK_REFRESH: Hybrid Mode
3777 01:21:00.377519 TX_TRACKING: ON
3778 01:21:00.387640 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3779 01:21:00.391054 [FAST_K] Save calibration result to emmc
3780 01:21:00.394572 dramc_set_vcore_voltage set vcore to 650000
3781 01:21:00.397667 Read voltage for 600, 5
3782 01:21:00.397748 Vio18 = 0
3783 01:21:00.397813 Vcore = 650000
3784 01:21:00.400841 Vdram = 0
3785 01:21:00.400921 Vddq = 0
3786 01:21:00.400984 Vmddr = 0
3787 01:21:00.407793 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3788 01:21:00.410787 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3789 01:21:00.414107 MEM_TYPE=3, freq_sel=19
3790 01:21:00.417188 sv_algorithm_assistance_LP4_1600
3791 01:21:00.420519 ============ PULL DRAM RESETB DOWN ============
3792 01:21:00.427446 ========== PULL DRAM RESETB DOWN end =========
3793 01:21:00.430419 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3794 01:21:00.434055 ===================================
3795 01:21:00.437209 LPDDR4 DRAM CONFIGURATION
3796 01:21:00.440476 ===================================
3797 01:21:00.440573 EX_ROW_EN[0] = 0x0
3798 01:21:00.444257 EX_ROW_EN[1] = 0x0
3799 01:21:00.444338 LP4Y_EN = 0x0
3800 01:21:00.447349 WORK_FSP = 0x0
3801 01:21:00.447430 WL = 0x2
3802 01:21:00.450447 RL = 0x2
3803 01:21:00.450528 BL = 0x2
3804 01:21:00.453963 RPST = 0x0
3805 01:21:00.454043 RD_PRE = 0x0
3806 01:21:00.457667 WR_PRE = 0x1
3807 01:21:00.460702 WR_PST = 0x0
3808 01:21:00.460782 DBI_WR = 0x0
3809 01:21:00.463962 DBI_RD = 0x0
3810 01:21:00.464042 OTF = 0x1
3811 01:21:00.467353 ===================================
3812 01:21:00.470284 ===================================
3813 01:21:00.470401 ANA top config
3814 01:21:00.473813 ===================================
3815 01:21:00.476806 DLL_ASYNC_EN = 0
3816 01:21:00.480671 ALL_SLAVE_EN = 1
3817 01:21:00.483736 NEW_RANK_MODE = 1
3818 01:21:00.486998 DLL_IDLE_MODE = 1
3819 01:21:00.487079 LP45_APHY_COMB_EN = 1
3820 01:21:00.490183 TX_ODT_DIS = 1
3821 01:21:00.493608 NEW_8X_MODE = 1
3822 01:21:00.496927 ===================================
3823 01:21:00.500051 ===================================
3824 01:21:00.503653 data_rate = 1200
3825 01:21:00.506853 CKR = 1
3826 01:21:00.506933 DQ_P2S_RATIO = 8
3827 01:21:00.510018 ===================================
3828 01:21:00.513244 CA_P2S_RATIO = 8
3829 01:21:00.516668 DQ_CA_OPEN = 0
3830 01:21:00.520728 DQ_SEMI_OPEN = 0
3831 01:21:00.523413 CA_SEMI_OPEN = 0
3832 01:21:00.526825 CA_FULL_RATE = 0
3833 01:21:00.526906 DQ_CKDIV4_EN = 1
3834 01:21:00.530066 CA_CKDIV4_EN = 1
3835 01:21:00.533123 CA_PREDIV_EN = 0
3836 01:21:00.536347 PH8_DLY = 0
3837 01:21:00.540069 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3838 01:21:00.543259 DQ_AAMCK_DIV = 4
3839 01:21:00.543340 CA_AAMCK_DIV = 4
3840 01:21:00.546760 CA_ADMCK_DIV = 4
3841 01:21:00.549838 DQ_TRACK_CA_EN = 0
3842 01:21:00.553559 CA_PICK = 600
3843 01:21:00.556402 CA_MCKIO = 600
3844 01:21:00.559850 MCKIO_SEMI = 0
3845 01:21:00.563507 PLL_FREQ = 2288
3846 01:21:00.563587 DQ_UI_PI_RATIO = 32
3847 01:21:00.566762 CA_UI_PI_RATIO = 0
3848 01:21:00.569919 ===================================
3849 01:21:00.573125 ===================================
3850 01:21:00.576285 memory_type:LPDDR4
3851 01:21:00.580098 GP_NUM : 10
3852 01:21:00.580179 SRAM_EN : 1
3853 01:21:00.582868 MD32_EN : 0
3854 01:21:00.586631 ===================================
3855 01:21:00.589817 [ANA_INIT] >>>>>>>>>>>>>>
3856 01:21:00.589898 <<<<<< [CONFIGURE PHASE]: ANA_TX
3857 01:21:00.592951 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3858 01:21:00.596174 ===================================
3859 01:21:00.599805 data_rate = 1200,PCW = 0X5800
3860 01:21:00.603037 ===================================
3861 01:21:00.606638 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3862 01:21:00.612847 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3863 01:21:00.619691 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3864 01:21:00.622747 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3865 01:21:00.626719 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3866 01:21:00.629816 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3867 01:21:00.632904 [ANA_INIT] flow start
3868 01:21:00.632985 [ANA_INIT] PLL >>>>>>>>
3869 01:21:00.636472 [ANA_INIT] PLL <<<<<<<<
3870 01:21:00.639406 [ANA_INIT] MIDPI >>>>>>>>
3871 01:21:00.639503 [ANA_INIT] MIDPI <<<<<<<<
3872 01:21:00.642915 [ANA_INIT] DLL >>>>>>>>
3873 01:21:00.645915 [ANA_INIT] flow end
3874 01:21:00.649428 ============ LP4 DIFF to SE enter ============
3875 01:21:00.652788 ============ LP4 DIFF to SE exit ============
3876 01:21:00.655957 [ANA_INIT] <<<<<<<<<<<<<
3877 01:21:00.659147 [Flow] Enable top DCM control >>>>>
3878 01:21:00.662643 [Flow] Enable top DCM control <<<<<
3879 01:21:00.665901 Enable DLL master slave shuffle
3880 01:21:00.672532 ==============================================================
3881 01:21:00.672614 Gating Mode config
3882 01:21:00.678989 ==============================================================
3883 01:21:00.679071 Config description:
3884 01:21:00.688824 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3885 01:21:00.695778 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3886 01:21:00.702191 SELPH_MODE 0: By rank 1: By Phase
3887 01:21:00.705391 ==============================================================
3888 01:21:00.708651 GAT_TRACK_EN = 1
3889 01:21:00.712313 RX_GATING_MODE = 2
3890 01:21:00.715630 RX_GATING_TRACK_MODE = 2
3891 01:21:00.718645 SELPH_MODE = 1
3892 01:21:00.721902 PICG_EARLY_EN = 1
3893 01:21:00.725657 VALID_LAT_VALUE = 1
3894 01:21:00.731911 ==============================================================
3895 01:21:00.735537 Enter into Gating configuration >>>>
3896 01:21:00.738689 Exit from Gating configuration <<<<
3897 01:21:00.738770 Enter into DVFS_PRE_config >>>>>
3898 01:21:00.752055 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3899 01:21:00.755075 Exit from DVFS_PRE_config <<<<<
3900 01:21:00.758823 Enter into PICG configuration >>>>
3901 01:21:00.762027 Exit from PICG configuration <<<<
3902 01:21:00.762108 [RX_INPUT] configuration >>>>>
3903 01:21:00.765102 [RX_INPUT] configuration <<<<<
3904 01:21:00.772107 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3905 01:21:00.775067 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3906 01:21:00.781668 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3907 01:21:00.788161 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3908 01:21:00.795041 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3909 01:21:00.801790 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3910 01:21:00.804917 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3911 01:21:00.808291 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3912 01:21:00.814802 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3913 01:21:00.817908 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3914 01:21:00.821638 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3915 01:21:00.824653 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3916 01:21:00.828294 ===================================
3917 01:21:00.831373 LPDDR4 DRAM CONFIGURATION
3918 01:21:00.835037 ===================================
3919 01:21:00.838138 EX_ROW_EN[0] = 0x0
3920 01:21:00.838218 EX_ROW_EN[1] = 0x0
3921 01:21:00.841287 LP4Y_EN = 0x0
3922 01:21:00.841368 WORK_FSP = 0x0
3923 01:21:00.844513 WL = 0x2
3924 01:21:00.844597 RL = 0x2
3925 01:21:00.848288 BL = 0x2
3926 01:21:00.848368 RPST = 0x0
3927 01:21:00.851269 RD_PRE = 0x0
3928 01:21:00.854346 WR_PRE = 0x1
3929 01:21:00.854427 WR_PST = 0x0
3930 01:21:00.857828 DBI_WR = 0x0
3931 01:21:00.857908 DBI_RD = 0x0
3932 01:21:00.861462 OTF = 0x1
3933 01:21:00.864633 ===================================
3934 01:21:00.867716 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3935 01:21:00.871334 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3936 01:21:00.874503 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3937 01:21:00.877618 ===================================
3938 01:21:00.880802 LPDDR4 DRAM CONFIGURATION
3939 01:21:00.884256 ===================================
3940 01:21:00.887669 EX_ROW_EN[0] = 0x10
3941 01:21:00.887749 EX_ROW_EN[1] = 0x0
3942 01:21:00.890916 LP4Y_EN = 0x0
3943 01:21:00.890996 WORK_FSP = 0x0
3944 01:21:00.894265 WL = 0x2
3945 01:21:00.894384 RL = 0x2
3946 01:21:00.897717 BL = 0x2
3947 01:21:00.897797 RPST = 0x0
3948 01:21:00.900980 RD_PRE = 0x0
3949 01:21:00.904465 WR_PRE = 0x1
3950 01:21:00.904545 WR_PST = 0x0
3951 01:21:00.907686 DBI_WR = 0x0
3952 01:21:00.907767 DBI_RD = 0x0
3953 01:21:00.910650 OTF = 0x1
3954 01:21:00.914087 ===================================
3955 01:21:00.917249 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3956 01:21:00.922874 nWR fixed to 30
3957 01:21:00.926588 [ModeRegInit_LP4] CH0 RK0
3958 01:21:00.926669 [ModeRegInit_LP4] CH0 RK1
3959 01:21:00.929648 [ModeRegInit_LP4] CH1 RK0
3960 01:21:00.932551 [ModeRegInit_LP4] CH1 RK1
3961 01:21:00.932631 match AC timing 17
3962 01:21:00.939336 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3963 01:21:00.942560 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3964 01:21:00.946513 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3965 01:21:00.952577 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3966 01:21:00.956424 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3967 01:21:00.956506 ==
3968 01:21:00.959786 Dram Type= 6, Freq= 0, CH_0, rank 0
3969 01:21:00.963152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3970 01:21:00.963233 ==
3971 01:21:00.969282 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3972 01:21:00.976138 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3973 01:21:00.979451 [CA 0] Center 35 (5~66) winsize 62
3974 01:21:00.982631 [CA 1] Center 35 (5~66) winsize 62
3975 01:21:00.985891 [CA 2] Center 33 (3~64) winsize 62
3976 01:21:00.989680 [CA 3] Center 33 (2~64) winsize 63
3977 01:21:00.992641 [CA 4] Center 33 (2~64) winsize 63
3978 01:21:00.995929 [CA 5] Center 32 (2~63) winsize 62
3979 01:21:00.996009
3980 01:21:00.999007 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3981 01:21:00.999087
3982 01:21:01.002805 [CATrainingPosCal] consider 1 rank data
3983 01:21:01.005909 u2DelayCellTimex100 = 270/100 ps
3984 01:21:01.009358 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3985 01:21:01.012439 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3986 01:21:01.015737 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3987 01:21:01.019550 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3988 01:21:01.022748 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3989 01:21:01.025836 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3990 01:21:01.029306
3991 01:21:01.032902 CA PerBit enable=1, Macro0, CA PI delay=32
3992 01:21:01.032983
3993 01:21:01.036005 [CBTSetCACLKResult] CA Dly = 32
3994 01:21:01.036086 CS Dly: 4 (0~35)
3995 01:21:01.036150 ==
3996 01:21:01.039029 Dram Type= 6, Freq= 0, CH_0, rank 1
3997 01:21:01.042505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3998 01:21:01.042587 ==
3999 01:21:01.048779 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4000 01:21:01.055846 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4001 01:21:01.059224 [CA 0] Center 35 (5~66) winsize 62
4002 01:21:01.062240 [CA 1] Center 35 (5~66) winsize 62
4003 01:21:01.065622 [CA 2] Center 34 (3~65) winsize 63
4004 01:21:01.068835 [CA 3] Center 33 (3~64) winsize 62
4005 01:21:01.072071 [CA 4] Center 32 (2~63) winsize 62
4006 01:21:01.075487 [CA 5] Center 32 (2~63) winsize 62
4007 01:21:01.075567
4008 01:21:01.078924 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4009 01:21:01.079004
4010 01:21:01.082773 [CATrainingPosCal] consider 2 rank data
4011 01:21:01.085790 u2DelayCellTimex100 = 270/100 ps
4012 01:21:01.088825 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4013 01:21:01.092094 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4014 01:21:01.095261 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4015 01:21:01.099068 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4016 01:21:01.102015 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4017 01:21:01.108869 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4018 01:21:01.108951
4019 01:21:01.112145 CA PerBit enable=1, Macro0, CA PI delay=32
4020 01:21:01.112225
4021 01:21:01.115788 [CBTSetCACLKResult] CA Dly = 32
4022 01:21:01.115867 CS Dly: 4 (0~36)
4023 01:21:01.115930
4024 01:21:01.118741 ----->DramcWriteLeveling(PI) begin...
4025 01:21:01.118822 ==
4026 01:21:01.122182 Dram Type= 6, Freq= 0, CH_0, rank 0
4027 01:21:01.128660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4028 01:21:01.128745 ==
4029 01:21:01.132061 Write leveling (Byte 0): 36 => 36
4030 01:21:01.132153 Write leveling (Byte 1): 32 => 32
4031 01:21:01.135220 DramcWriteLeveling(PI) end<-----
4032 01:21:01.135300
4033 01:21:01.135377 ==
4034 01:21:01.139032 Dram Type= 6, Freq= 0, CH_0, rank 0
4035 01:21:01.145247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4036 01:21:01.145329 ==
4037 01:21:01.148676 [Gating] SW mode calibration
4038 01:21:01.155131 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4039 01:21:01.158531 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4040 01:21:01.165191 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4041 01:21:01.168431 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4042 01:21:01.172291 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4043 01:21:01.175440 0 9 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
4044 01:21:01.181888 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4045 01:21:01.185405 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 01:21:01.188875 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 01:21:01.195561 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 01:21:01.198633 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 01:21:01.202476 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 01:21:01.208845 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 01:21:01.211961 0 10 12 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
4052 01:21:01.215941 0 10 16 | B1->B0 | 2f2f 4646 | 1 0 | (0 0) (0 0)
4053 01:21:01.222172 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 01:21:01.225286 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 01:21:01.228740 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 01:21:01.235257 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 01:21:01.238833 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 01:21:01.242055 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 01:21:01.249211 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4060 01:21:01.252343 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4061 01:21:01.255376 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 01:21:01.262141 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 01:21:01.265451 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 01:21:01.268702 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 01:21:01.272066 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 01:21:01.278647 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 01:21:01.282677 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 01:21:01.285842 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 01:21:01.292463 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 01:21:01.295460 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 01:21:01.298561 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 01:21:01.305204 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 01:21:01.308423 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 01:21:01.311834 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 01:21:01.318405 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4076 01:21:01.322507 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4077 01:21:01.325478 Total UI for P1: 0, mck2ui 16
4078 01:21:01.328746 best dqsien dly found for B0: ( 0, 13, 12)
4079 01:21:01.331836 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4080 01:21:01.335522 Total UI for P1: 0, mck2ui 16
4081 01:21:01.338477 best dqsien dly found for B1: ( 0, 13, 16)
4082 01:21:01.342194 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4083 01:21:01.344917 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4084 01:21:01.344999
4085 01:21:01.351965 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4086 01:21:01.355213 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4087 01:21:01.358961 [Gating] SW calibration Done
4088 01:21:01.359043 ==
4089 01:21:01.362060 Dram Type= 6, Freq= 0, CH_0, rank 0
4090 01:21:01.365115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4091 01:21:01.365198 ==
4092 01:21:01.365262 RX Vref Scan: 0
4093 01:21:01.365322
4094 01:21:01.368436 RX Vref 0 -> 0, step: 1
4095 01:21:01.368517
4096 01:21:01.371633 RX Delay -230 -> 252, step: 16
4097 01:21:01.375062 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4098 01:21:01.378306 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4099 01:21:01.385017 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4100 01:21:01.388393 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4101 01:21:01.391582 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4102 01:21:01.395223 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4103 01:21:01.401538 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4104 01:21:01.404609 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4105 01:21:01.408269 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4106 01:21:01.411526 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4107 01:21:01.414906 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4108 01:21:01.421430 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4109 01:21:01.424770 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4110 01:21:01.427883 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4111 01:21:01.431126 iDelay=218, Bit 14, Center 65 (-86 ~ 217) 304
4112 01:21:01.437985 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4113 01:21:01.438097 ==
4114 01:21:01.441451 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 01:21:01.444495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 01:21:01.444603 ==
4117 01:21:01.444695 DQS Delay:
4118 01:21:01.447453 DQS0 = 0, DQS1 = 0
4119 01:21:01.447557 DQM Delay:
4120 01:21:01.451394 DQM0 = 50, DQM1 = 45
4121 01:21:01.451503 DQ Delay:
4122 01:21:01.454532 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4123 01:21:01.457741 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4124 01:21:01.460804 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4125 01:21:01.464081 DQ12 =49, DQ13 =49, DQ14 =65, DQ15 =49
4126 01:21:01.464192
4127 01:21:01.464284
4128 01:21:01.464370 ==
4129 01:21:01.467893 Dram Type= 6, Freq= 0, CH_0, rank 0
4130 01:21:01.471007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4131 01:21:01.474213 ==
4132 01:21:01.474339
4133 01:21:01.474445
4134 01:21:01.474534 TX Vref Scan disable
4135 01:21:01.477285 == TX Byte 0 ==
4136 01:21:01.480707 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4137 01:21:01.487487 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4138 01:21:01.487598 == TX Byte 1 ==
4139 01:21:01.491033 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4140 01:21:01.497286 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4141 01:21:01.497396 ==
4142 01:21:01.500719 Dram Type= 6, Freq= 0, CH_0, rank 0
4143 01:21:01.504536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 01:21:01.504645 ==
4145 01:21:01.504739
4146 01:21:01.504829
4147 01:21:01.507314 TX Vref Scan disable
4148 01:21:01.507420 == TX Byte 0 ==
4149 01:21:01.514040 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4150 01:21:01.517215 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4151 01:21:01.517325 == TX Byte 1 ==
4152 01:21:01.523949 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4153 01:21:01.527488 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4154 01:21:01.527570
4155 01:21:01.527634 [DATLAT]
4156 01:21:01.530900 Freq=600, CH0 RK0
4157 01:21:01.530982
4158 01:21:01.531086 DATLAT Default: 0x9
4159 01:21:01.534279 0, 0xFFFF, sum = 0
4160 01:21:01.537116 1, 0xFFFF, sum = 0
4161 01:21:01.537200 2, 0xFFFF, sum = 0
4162 01:21:01.540802 3, 0xFFFF, sum = 0
4163 01:21:01.540885 4, 0xFFFF, sum = 0
4164 01:21:01.543995 5, 0xFFFF, sum = 0
4165 01:21:01.544078 6, 0xFFFF, sum = 0
4166 01:21:01.546996 7, 0xFFFF, sum = 0
4167 01:21:01.547079 8, 0x0, sum = 1
4168 01:21:01.550757 9, 0x0, sum = 2
4169 01:21:01.550840 10, 0x0, sum = 3
4170 01:21:01.550906 11, 0x0, sum = 4
4171 01:21:01.554112 best_step = 9
4172 01:21:01.554193
4173 01:21:01.554256 ==
4174 01:21:01.557434 Dram Type= 6, Freq= 0, CH_0, rank 0
4175 01:21:01.560632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 01:21:01.560714 ==
4177 01:21:01.563910 RX Vref Scan: 1
4178 01:21:01.563991
4179 01:21:01.564055 RX Vref 0 -> 0, step: 1
4180 01:21:01.564115
4181 01:21:01.567032 RX Delay -163 -> 252, step: 8
4182 01:21:01.567113
4183 01:21:01.570626 Set Vref, RX VrefLevel [Byte0]: 53
4184 01:21:01.573671 [Byte1]: 54
4185 01:21:01.578159
4186 01:21:01.578240 Final RX Vref Byte 0 = 53 to rank0
4187 01:21:01.581356 Final RX Vref Byte 1 = 54 to rank0
4188 01:21:01.584516 Final RX Vref Byte 0 = 53 to rank1
4189 01:21:01.587690 Final RX Vref Byte 1 = 54 to rank1==
4190 01:21:01.590973 Dram Type= 6, Freq= 0, CH_0, rank 0
4191 01:21:01.597765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4192 01:21:01.597847 ==
4193 01:21:01.597910 DQS Delay:
4194 01:21:01.597969 DQS0 = 0, DQS1 = 0
4195 01:21:01.600911 DQM Delay:
4196 01:21:01.600992 DQM0 = 52, DQM1 = 46
4197 01:21:01.604695 DQ Delay:
4198 01:21:01.607728 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =48
4199 01:21:01.611413 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4200 01:21:01.611494 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =36
4201 01:21:01.617922 DQ12 =56, DQ13 =52, DQ14 =56, DQ15 =52
4202 01:21:01.618004
4203 01:21:01.618067
4204 01:21:01.624595 [DQSOSCAuto] RK0, (LSB)MR18= 0x6c5f, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4205 01:21:01.628082 CH0 RK0: MR19=808, MR18=6C5F
4206 01:21:01.634154 CH0_RK0: MR19=0x808, MR18=0x6C5F, DQSOSC=389, MR23=63, INC=173, DEC=115
4207 01:21:01.634269
4208 01:21:01.637756 ----->DramcWriteLeveling(PI) begin...
4209 01:21:01.637867 ==
4210 01:21:01.640927 Dram Type= 6, Freq= 0, CH_0, rank 1
4211 01:21:01.644351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4212 01:21:01.644460 ==
4213 01:21:01.647717 Write leveling (Byte 0): 35 => 35
4214 01:21:01.650672 Write leveling (Byte 1): 31 => 31
4215 01:21:01.654270 DramcWriteLeveling(PI) end<-----
4216 01:21:01.654397
4217 01:21:01.654491 ==
4218 01:21:01.657385 Dram Type= 6, Freq= 0, CH_0, rank 1
4219 01:21:01.660966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4220 01:21:01.661074 ==
4221 01:21:01.664192 [Gating] SW mode calibration
4222 01:21:01.670957 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4223 01:21:01.677196 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4224 01:21:01.680965 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4225 01:21:01.687374 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4226 01:21:01.690687 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4227 01:21:01.693791 0 9 12 | B1->B0 | 3434 3434 | 0 0 | (0 1) (0 0)
4228 01:21:01.700542 0 9 16 | B1->B0 | 2c2c 2727 | 0 0 | (0 0) (0 0)
4229 01:21:01.703622 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 01:21:01.707299 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 01:21:01.713615 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 01:21:01.716782 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 01:21:01.720822 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 01:21:01.727295 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 01:21:01.730035 0 10 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4236 01:21:01.733660 0 10 16 | B1->B0 | 3737 3d3d | 0 0 | (0 0) (1 1)
4237 01:21:01.737024 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 01:21:01.743937 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 01:21:01.747022 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 01:21:01.750418 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 01:21:01.756919 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 01:21:01.759826 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 01:21:01.763098 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 01:21:01.769960 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4245 01:21:01.773510 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 01:21:01.776795 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 01:21:01.783328 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 01:21:01.786708 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 01:21:01.790093 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 01:21:01.796339 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 01:21:01.799633 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 01:21:01.803089 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 01:21:01.810053 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 01:21:01.813006 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 01:21:01.816512 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 01:21:01.822713 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 01:21:01.825966 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 01:21:01.829719 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 01:21:01.836491 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 01:21:01.839631 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4261 01:21:01.842952 Total UI for P1: 0, mck2ui 16
4262 01:21:01.845968 best dqsien dly found for B0: ( 0, 13, 14)
4263 01:21:01.849430 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 01:21:01.852809 Total UI for P1: 0, mck2ui 16
4265 01:21:01.856654 best dqsien dly found for B1: ( 0, 13, 16)
4266 01:21:01.859773 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4267 01:21:01.862877 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4268 01:21:01.862959
4269 01:21:01.869870 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4270 01:21:01.872807 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4271 01:21:01.872891 [Gating] SW calibration Done
4272 01:21:01.876468 ==
4273 01:21:01.879621 Dram Type= 6, Freq= 0, CH_0, rank 1
4274 01:21:01.882707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4275 01:21:01.882819 ==
4276 01:21:01.882913 RX Vref Scan: 0
4277 01:21:01.883004
4278 01:21:01.886259 RX Vref 0 -> 0, step: 1
4279 01:21:01.886389
4280 01:21:01.889689 RX Delay -230 -> 252, step: 16
4281 01:21:01.892711 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4282 01:21:01.895850 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4283 01:21:01.902835 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4284 01:21:01.906048 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4285 01:21:01.909134 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4286 01:21:01.912905 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4287 01:21:01.919073 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4288 01:21:01.922654 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4289 01:21:01.925696 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4290 01:21:01.929034 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4291 01:21:01.932857 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4292 01:21:01.939002 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4293 01:21:01.942504 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4294 01:21:01.945969 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4295 01:21:01.949001 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4296 01:21:01.955635 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4297 01:21:01.955721 ==
4298 01:21:01.959409 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 01:21:01.962641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 01:21:01.962726 ==
4301 01:21:01.962811 DQS Delay:
4302 01:21:01.965884 DQS0 = 0, DQS1 = 0
4303 01:21:01.965969 DQM Delay:
4304 01:21:01.968999 DQM0 = 48, DQM1 = 42
4305 01:21:01.969083 DQ Delay:
4306 01:21:01.972853 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4307 01:21:01.976080 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4308 01:21:01.979148 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4309 01:21:01.982239 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4310 01:21:01.982363
4311 01:21:01.982447
4312 01:21:01.982525 ==
4313 01:21:01.985905 Dram Type= 6, Freq= 0, CH_0, rank 1
4314 01:21:01.988904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4315 01:21:01.988989 ==
4316 01:21:01.989074
4317 01:21:01.992616
4318 01:21:01.992699 TX Vref Scan disable
4319 01:21:01.995802 == TX Byte 0 ==
4320 01:21:01.999152 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4321 01:21:02.002330 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4322 01:21:02.005692 == TX Byte 1 ==
4323 01:21:02.009722 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4324 01:21:02.012938 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4325 01:21:02.013021 ==
4326 01:21:02.015520 Dram Type= 6, Freq= 0, CH_0, rank 1
4327 01:21:02.022409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4328 01:21:02.022519 ==
4329 01:21:02.022621
4330 01:21:02.022719
4331 01:21:02.022821 TX Vref Scan disable
4332 01:21:02.026836 == TX Byte 0 ==
4333 01:21:02.030319 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4334 01:21:02.036730 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4335 01:21:02.036838 == TX Byte 1 ==
4336 01:21:02.040001 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4337 01:21:02.046764 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4338 01:21:02.046876
4339 01:21:02.046966 [DATLAT]
4340 01:21:02.047054 Freq=600, CH0 RK1
4341 01:21:02.047140
4342 01:21:02.050045 DATLAT Default: 0x9
4343 01:21:02.050146 0, 0xFFFF, sum = 0
4344 01:21:02.053599 1, 0xFFFF, sum = 0
4345 01:21:02.053705 2, 0xFFFF, sum = 0
4346 01:21:02.056874 3, 0xFFFF, sum = 0
4347 01:21:02.059912 4, 0xFFFF, sum = 0
4348 01:21:02.060017 5, 0xFFFF, sum = 0
4349 01:21:02.063667 6, 0xFFFF, sum = 0
4350 01:21:02.063774 7, 0xFFFF, sum = 0
4351 01:21:02.066800 8, 0x0, sum = 1
4352 01:21:02.066905 9, 0x0, sum = 2
4353 01:21:02.066996 10, 0x0, sum = 3
4354 01:21:02.070438 11, 0x0, sum = 4
4355 01:21:02.070543 best_step = 9
4356 01:21:02.070633
4357 01:21:02.070719 ==
4358 01:21:02.073362 Dram Type= 6, Freq= 0, CH_0, rank 1
4359 01:21:02.079838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4360 01:21:02.079946 ==
4361 01:21:02.080034 RX Vref Scan: 0
4362 01:21:02.080118
4363 01:21:02.083668 RX Vref 0 -> 0, step: 1
4364 01:21:02.083770
4365 01:21:02.087072 RX Delay -179 -> 252, step: 8
4366 01:21:02.090189 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4367 01:21:02.096791 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4368 01:21:02.099857 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4369 01:21:02.103723 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4370 01:21:02.106917 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4371 01:21:02.110159 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4372 01:21:02.117081 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4373 01:21:02.120072 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4374 01:21:02.123711 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4375 01:21:02.126470 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4376 01:21:02.129903 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4377 01:21:02.136641 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4378 01:21:02.139754 iDelay=197, Bit 12, Center 52 (-91 ~ 196) 288
4379 01:21:02.143120 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4380 01:21:02.146296 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4381 01:21:02.149995 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4382 01:21:02.152824 ==
4383 01:21:02.156400 Dram Type= 6, Freq= 0, CH_0, rank 1
4384 01:21:02.159438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 01:21:02.159542 ==
4386 01:21:02.159632 DQS Delay:
4387 01:21:02.163156 DQS0 = 0, DQS1 = 0
4388 01:21:02.163258 DQM Delay:
4389 01:21:02.166281 DQM0 = 53, DQM1 = 46
4390 01:21:02.166420 DQ Delay:
4391 01:21:02.169998 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4392 01:21:02.173250 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =60
4393 01:21:02.176334 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4394 01:21:02.179893 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4395 01:21:02.179996
4396 01:21:02.180084
4397 01:21:02.186609 [DQSOSCAuto] RK1, (LSB)MR18= 0x6324, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4398 01:21:02.189832 CH0 RK1: MR19=808, MR18=6324
4399 01:21:02.196246 CH0_RK1: MR19=0x808, MR18=0x6324, DQSOSC=391, MR23=63, INC=171, DEC=114
4400 01:21:02.199487 [RxdqsGatingPostProcess] freq 600
4401 01:21:02.206510 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4402 01:21:02.209684 Pre-setting of DQS Precalculation
4403 01:21:02.212764 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4404 01:21:02.212868 ==
4405 01:21:02.216447 Dram Type= 6, Freq= 0, CH_1, rank 0
4406 01:21:02.219443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4407 01:21:02.219546 ==
4408 01:21:02.226044 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4409 01:21:02.232895 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4410 01:21:02.235959 [CA 0] Center 36 (5~67) winsize 63
4411 01:21:02.239307 [CA 1] Center 36 (5~67) winsize 63
4412 01:21:02.242642 [CA 2] Center 34 (4~65) winsize 62
4413 01:21:02.246104 [CA 3] Center 34 (4~65) winsize 62
4414 01:21:02.249258 [CA 4] Center 34 (4~65) winsize 62
4415 01:21:02.252500 [CA 5] Center 34 (3~65) winsize 63
4416 01:21:02.252604
4417 01:21:02.256195 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4418 01:21:02.256299
4419 01:21:02.259510 [CATrainingPosCal] consider 1 rank data
4420 01:21:02.262764 u2DelayCellTimex100 = 270/100 ps
4421 01:21:02.265952 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4422 01:21:02.269023 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4423 01:21:02.272497 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4424 01:21:02.275732 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4425 01:21:02.278946 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4426 01:21:02.282291 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4427 01:21:02.285914
4428 01:21:02.289682 CA PerBit enable=1, Macro0, CA PI delay=34
4429 01:21:02.289788
4430 01:21:02.292851 [CBTSetCACLKResult] CA Dly = 34
4431 01:21:02.292955 CS Dly: 5 (0~36)
4432 01:21:02.293046 ==
4433 01:21:02.296055 Dram Type= 6, Freq= 0, CH_1, rank 1
4434 01:21:02.299228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4435 01:21:02.299333 ==
4436 01:21:02.305455 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4437 01:21:02.312278 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4438 01:21:02.316113 [CA 0] Center 36 (5~67) winsize 63
4439 01:21:02.319296 [CA 1] Center 36 (5~67) winsize 63
4440 01:21:02.322223 [CA 2] Center 34 (4~65) winsize 62
4441 01:21:02.325877 [CA 3] Center 34 (4~65) winsize 62
4442 01:21:02.329246 [CA 4] Center 34 (4~65) winsize 62
4443 01:21:02.332368 [CA 5] Center 34 (4~65) winsize 62
4444 01:21:02.332452
4445 01:21:02.335578 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4446 01:21:02.335662
4447 01:21:02.338807 [CATrainingPosCal] consider 2 rank data
4448 01:21:02.342480 u2DelayCellTimex100 = 270/100 ps
4449 01:21:02.345442 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4450 01:21:02.348766 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4451 01:21:02.352293 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4452 01:21:02.355668 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4453 01:21:02.362292 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4454 01:21:02.365519 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4455 01:21:02.365603
4456 01:21:02.368671 CA PerBit enable=1, Macro0, CA PI delay=34
4457 01:21:02.368755
4458 01:21:02.371867 [CBTSetCACLKResult] CA Dly = 34
4459 01:21:02.371950 CS Dly: 6 (0~38)
4460 01:21:02.372035
4461 01:21:02.375312 ----->DramcWriteLeveling(PI) begin...
4462 01:21:02.375397 ==
4463 01:21:02.378763 Dram Type= 6, Freq= 0, CH_1, rank 0
4464 01:21:02.385572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4465 01:21:02.385657 ==
4466 01:21:02.388499 Write leveling (Byte 0): 33 => 33
4467 01:21:02.391725 Write leveling (Byte 1): 30 => 30
4468 01:21:02.391809 DramcWriteLeveling(PI) end<-----
4469 01:21:02.391893
4470 01:21:02.395303 ==
4471 01:21:02.398642 Dram Type= 6, Freq= 0, CH_1, rank 0
4472 01:21:02.401681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4473 01:21:02.401762 ==
4474 01:21:02.405246 [Gating] SW mode calibration
4475 01:21:02.411663 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4476 01:21:02.415322 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4477 01:21:02.421270 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4478 01:21:02.424986 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4479 01:21:02.428137 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
4480 01:21:02.435182 0 9 12 | B1->B0 | 2f2f 2d2d | 0 0 | (0 0) (0 0)
4481 01:21:02.438401 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 01:21:02.441521 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 01:21:02.447971 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 01:21:02.451333 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 01:21:02.454766 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 01:21:02.461051 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 01:21:02.464508 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4488 01:21:02.467923 0 10 12 | B1->B0 | 3838 3838 | 0 0 | (0 0) (0 0)
4489 01:21:02.474664 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 01:21:02.477969 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 01:21:02.481494 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 01:21:02.487832 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 01:21:02.491213 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 01:21:02.494203 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 01:21:02.500895 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 01:21:02.504260 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4497 01:21:02.507421 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 01:21:02.514277 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 01:21:02.517554 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 01:21:02.520696 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 01:21:02.527695 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 01:21:02.531030 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 01:21:02.534488 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 01:21:02.541167 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 01:21:02.544461 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 01:21:02.547687 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 01:21:02.551325 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 01:21:02.557801 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 01:21:02.560791 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 01:21:02.564434 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 01:21:02.570676 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 01:21:02.574222 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4513 01:21:02.577294 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4514 01:21:02.580316 Total UI for P1: 0, mck2ui 16
4515 01:21:02.583996 best dqsien dly found for B0: ( 0, 13, 12)
4516 01:21:02.587315 Total UI for P1: 0, mck2ui 16
4517 01:21:02.590280 best dqsien dly found for B1: ( 0, 13, 14)
4518 01:21:02.593656 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4519 01:21:02.600319 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4520 01:21:02.600400
4521 01:21:02.604184 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4522 01:21:02.607230 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4523 01:21:02.610678 [Gating] SW calibration Done
4524 01:21:02.610759 ==
4525 01:21:02.613878 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 01:21:02.617156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 01:21:02.617237 ==
4528 01:21:02.620241 RX Vref Scan: 0
4529 01:21:02.620321
4530 01:21:02.620384 RX Vref 0 -> 0, step: 1
4531 01:21:02.620443
4532 01:21:02.623473 RX Delay -230 -> 252, step: 16
4533 01:21:02.627231 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4534 01:21:02.633606 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4535 01:21:02.636889 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4536 01:21:02.640522 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4537 01:21:02.643386 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4538 01:21:02.647009 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4539 01:21:02.653514 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4540 01:21:02.657318 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4541 01:21:02.660227 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4542 01:21:02.663316 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4543 01:21:02.670156 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4544 01:21:02.673376 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4545 01:21:02.676570 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4546 01:21:02.680010 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4547 01:21:02.686451 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4548 01:21:02.690048 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4549 01:21:02.690154 ==
4550 01:21:02.693760 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 01:21:02.696691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 01:21:02.696796 ==
4553 01:21:02.700035 DQS Delay:
4554 01:21:02.700137 DQS0 = 0, DQS1 = 0
4555 01:21:02.700227 DQM Delay:
4556 01:21:02.703363 DQM0 = 47, DQM1 = 45
4557 01:21:02.703467 DQ Delay:
4558 01:21:02.706992 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4559 01:21:02.710092 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4560 01:21:02.713432 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4561 01:21:02.716943 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4562 01:21:02.717048
4563 01:21:02.717143
4564 01:21:02.717232 ==
4565 01:21:02.720468 Dram Type= 6, Freq= 0, CH_1, rank 0
4566 01:21:02.726629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 01:21:02.726735 ==
4568 01:21:02.726825
4569 01:21:02.726911
4570 01:21:02.726995 TX Vref Scan disable
4571 01:21:02.729951 == TX Byte 0 ==
4572 01:21:02.733685 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4573 01:21:02.740064 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4574 01:21:02.740170 == TX Byte 1 ==
4575 01:21:02.743088 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4576 01:21:02.749757 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4577 01:21:02.749865 ==
4578 01:21:02.753713 Dram Type= 6, Freq= 0, CH_1, rank 0
4579 01:21:02.756578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 01:21:02.756683 ==
4581 01:21:02.756774
4582 01:21:02.756862
4583 01:21:02.759908 TX Vref Scan disable
4584 01:21:02.763303 == TX Byte 0 ==
4585 01:21:02.766567 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4586 01:21:02.769614 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4587 01:21:02.773414 == TX Byte 1 ==
4588 01:21:02.776281 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4589 01:21:02.779575 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4590 01:21:02.779695
4591 01:21:02.779786 [DATLAT]
4592 01:21:02.783114 Freq=600, CH1 RK0
4593 01:21:02.783217
4594 01:21:02.786456 DATLAT Default: 0x9
4595 01:21:02.786559 0, 0xFFFF, sum = 0
4596 01:21:02.789614 1, 0xFFFF, sum = 0
4597 01:21:02.789719 2, 0xFFFF, sum = 0
4598 01:21:02.792910 3, 0xFFFF, sum = 0
4599 01:21:02.793014 4, 0xFFFF, sum = 0
4600 01:21:02.796646 5, 0xFFFF, sum = 0
4601 01:21:02.796752 6, 0xFFFF, sum = 0
4602 01:21:02.799417 7, 0xFFFF, sum = 0
4603 01:21:02.799522 8, 0x0, sum = 1
4604 01:21:02.802712 9, 0x0, sum = 2
4605 01:21:02.802818 10, 0x0, sum = 3
4606 01:21:02.806001 11, 0x0, sum = 4
4607 01:21:02.806107 best_step = 9
4608 01:21:02.806195
4609 01:21:02.806276 ==
4610 01:21:02.809755 Dram Type= 6, Freq= 0, CH_1, rank 0
4611 01:21:02.812969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4612 01:21:02.813073 ==
4613 01:21:02.816149 RX Vref Scan: 1
4614 01:21:02.816252
4615 01:21:02.819880 RX Vref 0 -> 0, step: 1
4616 01:21:02.819983
4617 01:21:02.820073 RX Delay -163 -> 252, step: 8
4618 01:21:02.820160
4619 01:21:02.822791 Set Vref, RX VrefLevel [Byte0]: 54
4620 01:21:02.825947 [Byte1]: 48
4621 01:21:02.830449
4622 01:21:02.830551 Final RX Vref Byte 0 = 54 to rank0
4623 01:21:02.833628 Final RX Vref Byte 1 = 48 to rank0
4624 01:21:02.837418 Final RX Vref Byte 0 = 54 to rank1
4625 01:21:02.840769 Final RX Vref Byte 1 = 48 to rank1==
4626 01:21:02.843964 Dram Type= 6, Freq= 0, CH_1, rank 0
4627 01:21:02.850756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4628 01:21:02.850861 ==
4629 01:21:02.850950 DQS Delay:
4630 01:21:02.851036 DQS0 = 0, DQS1 = 0
4631 01:21:02.853744 DQM Delay:
4632 01:21:02.853846 DQM0 = 48, DQM1 = 46
4633 01:21:02.857332 DQ Delay:
4634 01:21:02.860497 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4635 01:21:02.863717 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4636 01:21:02.863821 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4637 01:21:02.870975 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4638 01:21:02.871080
4639 01:21:02.871170
4640 01:21:02.877170 [DQSOSCAuto] RK0, (LSB)MR18= 0x4267, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
4641 01:21:02.880319 CH1 RK0: MR19=808, MR18=4267
4642 01:21:02.887325 CH1_RK0: MR19=0x808, MR18=0x4267, DQSOSC=390, MR23=63, INC=172, DEC=114
4643 01:21:02.887431
4644 01:21:02.890787 ----->DramcWriteLeveling(PI) begin...
4645 01:21:02.890890 ==
4646 01:21:02.893512 Dram Type= 6, Freq= 0, CH_1, rank 1
4647 01:21:02.897227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 01:21:02.897331 ==
4649 01:21:02.900224 Write leveling (Byte 0): 31 => 31
4650 01:21:02.903383 Write leveling (Byte 1): 31 => 31
4651 01:21:02.907222 DramcWriteLeveling(PI) end<-----
4652 01:21:02.907325
4653 01:21:02.907414 ==
4654 01:21:02.910095 Dram Type= 6, Freq= 0, CH_1, rank 1
4655 01:21:02.913884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4656 01:21:02.913988 ==
4657 01:21:02.916885 [Gating] SW mode calibration
4658 01:21:02.923655 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4659 01:21:02.930739 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4660 01:21:02.933298 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4661 01:21:02.936834 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4662 01:21:02.943453 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4663 01:21:02.946710 0 9 12 | B1->B0 | 3030 3030 | 0 0 | (0 0) (1 1)
4664 01:21:02.951019 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4665 01:21:02.956791 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 01:21:02.959861 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4667 01:21:02.963376 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4668 01:21:02.969827 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4669 01:21:02.973507 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 01:21:02.976726 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4671 01:21:02.983532 0 10 12 | B1->B0 | 3b3b 3838 | 0 1 | (0 0) (1 1)
4672 01:21:02.986972 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 01:21:02.989804 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 01:21:02.996797 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 01:21:02.999760 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 01:21:03.003319 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 01:21:03.009636 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 01:21:03.012824 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 01:21:03.016808 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4680 01:21:03.022927 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 01:21:03.026861 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 01:21:03.029852 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 01:21:03.036067 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 01:21:03.039292 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 01:21:03.042857 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 01:21:03.049638 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 01:21:03.052951 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 01:21:03.056171 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 01:21:03.063066 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 01:21:03.065989 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 01:21:03.069283 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 01:21:03.076447 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 01:21:03.079655 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 01:21:03.082841 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4695 01:21:03.089429 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4696 01:21:03.089534 Total UI for P1: 0, mck2ui 16
4697 01:21:03.096029 best dqsien dly found for B0: ( 0, 13, 8)
4698 01:21:03.099424 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4699 01:21:03.102542 Total UI for P1: 0, mck2ui 16
4700 01:21:03.105958 best dqsien dly found for B1: ( 0, 13, 10)
4701 01:21:03.109308 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4702 01:21:03.112673 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4703 01:21:03.112758
4704 01:21:03.115968 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4705 01:21:03.119108 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4706 01:21:03.122401 [Gating] SW calibration Done
4707 01:21:03.122481 ==
4708 01:21:03.126034 Dram Type= 6, Freq= 0, CH_1, rank 1
4709 01:21:03.129292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4710 01:21:03.129373 ==
4711 01:21:03.132411 RX Vref Scan: 0
4712 01:21:03.132492
4713 01:21:03.135621 RX Vref 0 -> 0, step: 1
4714 01:21:03.135701
4715 01:21:03.135764 RX Delay -230 -> 252, step: 16
4716 01:21:03.142189 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4717 01:21:03.146021 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4718 01:21:03.149030 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4719 01:21:03.152252 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4720 01:21:03.159445 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4721 01:21:03.162447 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4722 01:21:03.165831 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4723 01:21:03.169308 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4724 01:21:03.172293 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4725 01:21:03.179402 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4726 01:21:03.182265 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4727 01:21:03.185828 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4728 01:21:03.189110 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4729 01:21:03.195874 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4730 01:21:03.198767 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4731 01:21:03.202260 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4732 01:21:03.202368 ==
4733 01:21:03.205698 Dram Type= 6, Freq= 0, CH_1, rank 1
4734 01:21:03.209270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4735 01:21:03.212738 ==
4736 01:21:03.212819 DQS Delay:
4737 01:21:03.212883 DQS0 = 0, DQS1 = 0
4738 01:21:03.215703 DQM Delay:
4739 01:21:03.215784 DQM0 = 49, DQM1 = 47
4740 01:21:03.215848 DQ Delay:
4741 01:21:03.219042 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =49
4742 01:21:03.222186 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4743 01:21:03.225408 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4744 01:21:03.229211 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4745 01:21:03.229292
4746 01:21:03.229354
4747 01:21:03.232499 ==
4748 01:21:03.235566 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 01:21:03.239250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 01:21:03.239331 ==
4751 01:21:03.239394
4752 01:21:03.239452
4753 01:21:03.242514 TX Vref Scan disable
4754 01:21:03.242594 == TX Byte 0 ==
4755 01:21:03.248738 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4756 01:21:03.251996 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4757 01:21:03.252081 == TX Byte 1 ==
4758 01:21:03.258827 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4759 01:21:03.262088 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4760 01:21:03.262168 ==
4761 01:21:03.265286 Dram Type= 6, Freq= 0, CH_1, rank 1
4762 01:21:03.268495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4763 01:21:03.268576 ==
4764 01:21:03.268640
4765 01:21:03.268699
4766 01:21:03.272401 TX Vref Scan disable
4767 01:21:03.275672 == TX Byte 0 ==
4768 01:21:03.278738 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4769 01:21:03.281842 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4770 01:21:03.285599 == TX Byte 1 ==
4771 01:21:03.288780 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4772 01:21:03.292021 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4773 01:21:03.292106
4774 01:21:03.295419 [DATLAT]
4775 01:21:03.295499 Freq=600, CH1 RK1
4776 01:21:03.295562
4777 01:21:03.298708 DATLAT Default: 0x9
4778 01:21:03.298788 0, 0xFFFF, sum = 0
4779 01:21:03.302168 1, 0xFFFF, sum = 0
4780 01:21:03.302250 2, 0xFFFF, sum = 0
4781 01:21:03.305379 3, 0xFFFF, sum = 0
4782 01:21:03.305460 4, 0xFFFF, sum = 0
4783 01:21:03.308716 5, 0xFFFF, sum = 0
4784 01:21:03.308798 6, 0xFFFF, sum = 0
4785 01:21:03.311950 7, 0xFFFF, sum = 0
4786 01:21:03.312031 8, 0x0, sum = 1
4787 01:21:03.315277 9, 0x0, sum = 2
4788 01:21:03.315359 10, 0x0, sum = 3
4789 01:21:03.318479 11, 0x0, sum = 4
4790 01:21:03.318587 best_step = 9
4791 01:21:03.318677
4792 01:21:03.318764 ==
4793 01:21:03.321852 Dram Type= 6, Freq= 0, CH_1, rank 1
4794 01:21:03.325462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4795 01:21:03.328824 ==
4796 01:21:03.328926 RX Vref Scan: 0
4797 01:21:03.329015
4798 01:21:03.331662 RX Vref 0 -> 0, step: 1
4799 01:21:03.331762
4800 01:21:03.334955 RX Delay -163 -> 252, step: 8
4801 01:21:03.338482 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4802 01:21:03.341589 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4803 01:21:03.348178 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4804 01:21:03.351605 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4805 01:21:03.354735 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4806 01:21:03.358231 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4807 01:21:03.361839 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4808 01:21:03.368160 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4809 01:21:03.371265 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4810 01:21:03.374642 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4811 01:21:03.378410 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4812 01:21:03.381469 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4813 01:21:03.388218 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4814 01:21:03.391482 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4815 01:21:03.394651 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4816 01:21:03.398530 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4817 01:21:03.398611 ==
4818 01:21:03.401517 Dram Type= 6, Freq= 0, CH_1, rank 1
4819 01:21:03.408645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4820 01:21:03.408727 ==
4821 01:21:03.408790 DQS Delay:
4822 01:21:03.411671 DQS0 = 0, DQS1 = 0
4823 01:21:03.411751 DQM Delay:
4824 01:21:03.411814 DQM0 = 48, DQM1 = 45
4825 01:21:03.414782 DQ Delay:
4826 01:21:03.418018 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4827 01:21:03.421508 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4828 01:21:03.424609 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4829 01:21:03.428190 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =52
4830 01:21:03.428270
4831 01:21:03.428333
4832 01:21:03.434535 [DQSOSCAuto] RK1, (LSB)MR18= 0x6820, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 390 ps
4833 01:21:03.437801 CH1 RK1: MR19=808, MR18=6820
4834 01:21:03.444431 CH1_RK1: MR19=0x808, MR18=0x6820, DQSOSC=390, MR23=63, INC=172, DEC=114
4835 01:21:03.448203 [RxdqsGatingPostProcess] freq 600
4836 01:21:03.451641 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4837 01:21:03.454423 Pre-setting of DQS Precalculation
4838 01:21:03.461026 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4839 01:21:03.467929 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4840 01:21:03.474147 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4841 01:21:03.474228
4842 01:21:03.474291
4843 01:21:03.477595 [Calibration Summary] 1200 Mbps
4844 01:21:03.480932 CH 0, Rank 0
4845 01:21:03.481013 SW Impedance : PASS
4846 01:21:03.484374 DUTY Scan : NO K
4847 01:21:03.484455 ZQ Calibration : PASS
4848 01:21:03.487421 Jitter Meter : NO K
4849 01:21:03.490838 CBT Training : PASS
4850 01:21:03.490918 Write leveling : PASS
4851 01:21:03.494054 RX DQS gating : PASS
4852 01:21:03.497365 RX DQ/DQS(RDDQC) : PASS
4853 01:21:03.497446 TX DQ/DQS : PASS
4854 01:21:03.500760 RX DATLAT : PASS
4855 01:21:03.503886 RX DQ/DQS(Engine): PASS
4856 01:21:03.503966 TX OE : NO K
4857 01:21:03.507620 All Pass.
4858 01:21:03.507700
4859 01:21:03.507764 CH 0, Rank 1
4860 01:21:03.510728 SW Impedance : PASS
4861 01:21:03.510808 DUTY Scan : NO K
4862 01:21:03.514085 ZQ Calibration : PASS
4863 01:21:03.517212 Jitter Meter : NO K
4864 01:21:03.517293 CBT Training : PASS
4865 01:21:03.520733 Write leveling : PASS
4866 01:21:03.524148 RX DQS gating : PASS
4867 01:21:03.524228 RX DQ/DQS(RDDQC) : PASS
4868 01:21:03.527560 TX DQ/DQS : PASS
4869 01:21:03.530792 RX DATLAT : PASS
4870 01:21:03.530873 RX DQ/DQS(Engine): PASS
4871 01:21:03.533833 TX OE : NO K
4872 01:21:03.533913 All Pass.
4873 01:21:03.533977
4874 01:21:03.537057 CH 1, Rank 0
4875 01:21:03.537137 SW Impedance : PASS
4876 01:21:03.540309 DUTY Scan : NO K
4877 01:21:03.544111 ZQ Calibration : PASS
4878 01:21:03.544194 Jitter Meter : NO K
4879 01:21:03.547471 CBT Training : PASS
4880 01:21:03.547551 Write leveling : PASS
4881 01:21:03.550502 RX DQS gating : PASS
4882 01:21:03.553587 RX DQ/DQS(RDDQC) : PASS
4883 01:21:03.553667 TX DQ/DQS : PASS
4884 01:21:03.557254 RX DATLAT : PASS
4885 01:21:03.560272 RX DQ/DQS(Engine): PASS
4886 01:21:03.560352 TX OE : NO K
4887 01:21:03.564012 All Pass.
4888 01:21:03.564099
4889 01:21:03.564161 CH 1, Rank 1
4890 01:21:03.567023 SW Impedance : PASS
4891 01:21:03.567103 DUTY Scan : NO K
4892 01:21:03.570439 ZQ Calibration : PASS
4893 01:21:03.573350 Jitter Meter : NO K
4894 01:21:03.573430 CBT Training : PASS
4895 01:21:03.577203 Write leveling : PASS
4896 01:21:03.580289 RX DQS gating : PASS
4897 01:21:03.580369 RX DQ/DQS(RDDQC) : PASS
4898 01:21:03.583369 TX DQ/DQS : PASS
4899 01:21:03.586857 RX DATLAT : PASS
4900 01:21:03.586936 RX DQ/DQS(Engine): PASS
4901 01:21:03.590084 TX OE : NO K
4902 01:21:03.590194 All Pass.
4903 01:21:03.590285
4904 01:21:03.593178 DramC Write-DBI off
4905 01:21:03.596637 PER_BANK_REFRESH: Hybrid Mode
4906 01:21:03.596744 TX_TRACKING: ON
4907 01:21:03.606789 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4908 01:21:03.609962 [FAST_K] Save calibration result to emmc
4909 01:21:03.613307 dramc_set_vcore_voltage set vcore to 662500
4910 01:21:03.616397 Read voltage for 933, 3
4911 01:21:03.616477 Vio18 = 0
4912 01:21:03.616539 Vcore = 662500
4913 01:21:03.619800 Vdram = 0
4914 01:21:03.619883 Vddq = 0
4915 01:21:03.619946 Vmddr = 0
4916 01:21:03.626585 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4917 01:21:03.629779 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4918 01:21:03.633272 MEM_TYPE=3, freq_sel=17
4919 01:21:03.636695 sv_algorithm_assistance_LP4_1600
4920 01:21:03.639760 ============ PULL DRAM RESETB DOWN ============
4921 01:21:03.643539 ========== PULL DRAM RESETB DOWN end =========
4922 01:21:03.650003 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4923 01:21:03.653334 ===================================
4924 01:21:03.653414 LPDDR4 DRAM CONFIGURATION
4925 01:21:03.656277 ===================================
4926 01:21:03.660084 EX_ROW_EN[0] = 0x0
4927 01:21:03.663348 EX_ROW_EN[1] = 0x0
4928 01:21:03.663428 LP4Y_EN = 0x0
4929 01:21:03.666569 WORK_FSP = 0x0
4930 01:21:03.666649 WL = 0x3
4931 01:21:03.669495 RL = 0x3
4932 01:21:03.669574 BL = 0x2
4933 01:21:03.673387 RPST = 0x0
4934 01:21:03.673467 RD_PRE = 0x0
4935 01:21:03.676461 WR_PRE = 0x1
4936 01:21:03.676540 WR_PST = 0x0
4937 01:21:03.679672 DBI_WR = 0x0
4938 01:21:03.679756 DBI_RD = 0x0
4939 01:21:03.682778 OTF = 0x1
4940 01:21:03.686229 ===================================
4941 01:21:03.689433 ===================================
4942 01:21:03.689514 ANA top config
4943 01:21:03.693401 ===================================
4944 01:21:03.696130 DLL_ASYNC_EN = 0
4945 01:21:03.699221 ALL_SLAVE_EN = 1
4946 01:21:03.703060 NEW_RANK_MODE = 1
4947 01:21:03.703141 DLL_IDLE_MODE = 1
4948 01:21:03.706290 LP45_APHY_COMB_EN = 1
4949 01:21:03.709431 TX_ODT_DIS = 1
4950 01:21:03.712625 NEW_8X_MODE = 1
4951 01:21:03.716481 ===================================
4952 01:21:03.719210 ===================================
4953 01:21:03.722651 data_rate = 1866
4954 01:21:03.722731 CKR = 1
4955 01:21:03.726084 DQ_P2S_RATIO = 8
4956 01:21:03.729334 ===================================
4957 01:21:03.732339 CA_P2S_RATIO = 8
4958 01:21:03.736158 DQ_CA_OPEN = 0
4959 01:21:03.739431 DQ_SEMI_OPEN = 0
4960 01:21:03.742292 CA_SEMI_OPEN = 0
4961 01:21:03.742413 CA_FULL_RATE = 0
4962 01:21:03.745362 DQ_CKDIV4_EN = 1
4963 01:21:03.749117 CA_CKDIV4_EN = 1
4964 01:21:03.752348 CA_PREDIV_EN = 0
4965 01:21:03.755374 PH8_DLY = 0
4966 01:21:03.759029 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4967 01:21:03.759109 DQ_AAMCK_DIV = 4
4968 01:21:03.762431 CA_AAMCK_DIV = 4
4969 01:21:03.765799 CA_ADMCK_DIV = 4
4970 01:21:03.768909 DQ_TRACK_CA_EN = 0
4971 01:21:03.772431 CA_PICK = 933
4972 01:21:03.775427 CA_MCKIO = 933
4973 01:21:03.778884 MCKIO_SEMI = 0
4974 01:21:03.778963 PLL_FREQ = 3732
4975 01:21:03.782148 DQ_UI_PI_RATIO = 32
4976 01:21:03.785395 CA_UI_PI_RATIO = 0
4977 01:21:03.789116 ===================================
4978 01:21:03.792339 ===================================
4979 01:21:03.795606 memory_type:LPDDR4
4980 01:21:03.795686 GP_NUM : 10
4981 01:21:03.798758 SRAM_EN : 1
4982 01:21:03.801890 MD32_EN : 0
4983 01:21:03.805021 ===================================
4984 01:21:03.805111 [ANA_INIT] >>>>>>>>>>>>>>
4985 01:21:03.808702 <<<<<< [CONFIGURE PHASE]: ANA_TX
4986 01:21:03.811799 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4987 01:21:03.815002 ===================================
4988 01:21:03.818201 data_rate = 1866,PCW = 0X8f00
4989 01:21:03.821961 ===================================
4990 01:21:03.825137 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4991 01:21:03.831805 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4992 01:21:03.838149 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4993 01:21:03.841473 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4994 01:21:03.844639 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4995 01:21:03.848406 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4996 01:21:03.851249 [ANA_INIT] flow start
4997 01:21:03.851329 [ANA_INIT] PLL >>>>>>>>
4998 01:21:03.854954 [ANA_INIT] PLL <<<<<<<<
4999 01:21:03.858142 [ANA_INIT] MIDPI >>>>>>>>
5000 01:21:03.858222 [ANA_INIT] MIDPI <<<<<<<<
5001 01:21:03.861314 [ANA_INIT] DLL >>>>>>>>
5002 01:21:03.864652 [ANA_INIT] flow end
5003 01:21:03.868000 ============ LP4 DIFF to SE enter ============
5004 01:21:03.871308 ============ LP4 DIFF to SE exit ============
5005 01:21:03.874506 [ANA_INIT] <<<<<<<<<<<<<
5006 01:21:03.878226 [Flow] Enable top DCM control >>>>>
5007 01:21:03.881052 [Flow] Enable top DCM control <<<<<
5008 01:21:03.884415 Enable DLL master slave shuffle
5009 01:21:03.887899 ==============================================================
5010 01:21:03.890932 Gating Mode config
5011 01:21:03.897656 ==============================================================
5012 01:21:03.897736 Config description:
5013 01:21:03.907692 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5014 01:21:03.914622 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5015 01:21:03.920956 SELPH_MODE 0: By rank 1: By Phase
5016 01:21:03.924127 ==============================================================
5017 01:21:03.927367 GAT_TRACK_EN = 1
5018 01:21:03.931049 RX_GATING_MODE = 2
5019 01:21:03.934319 RX_GATING_TRACK_MODE = 2
5020 01:21:03.937495 SELPH_MODE = 1
5021 01:21:03.940765 PICG_EARLY_EN = 1
5022 01:21:03.944276 VALID_LAT_VALUE = 1
5023 01:21:03.948109 ==============================================================
5024 01:21:03.951380 Enter into Gating configuration >>>>
5025 01:21:03.954515 Exit from Gating configuration <<<<
5026 01:21:03.957620 Enter into DVFS_PRE_config >>>>>
5027 01:21:03.970560 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5028 01:21:03.973960 Exit from DVFS_PRE_config <<<<<
5029 01:21:03.977708 Enter into PICG configuration >>>>
5030 01:21:03.977789 Exit from PICG configuration <<<<
5031 01:21:03.980930 [RX_INPUT] configuration >>>>>
5032 01:21:03.984076 [RX_INPUT] configuration <<<<<
5033 01:21:03.990433 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5034 01:21:03.993638 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5035 01:21:04.000887 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5036 01:21:04.007074 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5037 01:21:04.013854 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5038 01:21:04.020243 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5039 01:21:04.023764 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5040 01:21:04.027342 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5041 01:21:04.033567 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5042 01:21:04.036791 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5043 01:21:04.040224 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5044 01:21:04.043531 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5045 01:21:04.047320 ===================================
5046 01:21:04.050036 LPDDR4 DRAM CONFIGURATION
5047 01:21:04.053510 ===================================
5048 01:21:04.057617 EX_ROW_EN[0] = 0x0
5049 01:21:04.057723 EX_ROW_EN[1] = 0x0
5050 01:21:04.059950 LP4Y_EN = 0x0
5051 01:21:04.060029 WORK_FSP = 0x0
5052 01:21:04.063778 WL = 0x3
5053 01:21:04.063859 RL = 0x3
5054 01:21:04.066870 BL = 0x2
5055 01:21:04.066950 RPST = 0x0
5056 01:21:04.070112 RD_PRE = 0x0
5057 01:21:04.070192 WR_PRE = 0x1
5058 01:21:04.073255 WR_PST = 0x0
5059 01:21:04.073336 DBI_WR = 0x0
5060 01:21:04.076979 DBI_RD = 0x0
5061 01:21:04.077060 OTF = 0x1
5062 01:21:04.080087 ===================================
5063 01:21:04.087201 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5064 01:21:04.090228 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5065 01:21:04.093644 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5066 01:21:04.096809 ===================================
5067 01:21:04.099959 LPDDR4 DRAM CONFIGURATION
5068 01:21:04.103409 ===================================
5069 01:21:04.106461 EX_ROW_EN[0] = 0x10
5070 01:21:04.106542 EX_ROW_EN[1] = 0x0
5071 01:21:04.110067 LP4Y_EN = 0x0
5072 01:21:04.110147 WORK_FSP = 0x0
5073 01:21:04.113155 WL = 0x3
5074 01:21:04.113235 RL = 0x3
5075 01:21:04.116922 BL = 0x2
5076 01:21:04.117003 RPST = 0x0
5077 01:21:04.119894 RD_PRE = 0x0
5078 01:21:04.119974 WR_PRE = 0x1
5079 01:21:04.123431 WR_PST = 0x0
5080 01:21:04.123512 DBI_WR = 0x0
5081 01:21:04.126603 DBI_RD = 0x0
5082 01:21:04.126683 OTF = 0x1
5083 01:21:04.129850 ===================================
5084 01:21:04.136239 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5085 01:21:04.141084 nWR fixed to 30
5086 01:21:04.144357 [ModeRegInit_LP4] CH0 RK0
5087 01:21:04.144463 [ModeRegInit_LP4] CH0 RK1
5088 01:21:04.148209 [ModeRegInit_LP4] CH1 RK0
5089 01:21:04.151146 [ModeRegInit_LP4] CH1 RK1
5090 01:21:04.151226 match AC timing 9
5091 01:21:04.157862 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5092 01:21:04.161383 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5093 01:21:04.164286 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5094 01:21:04.170667 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5095 01:21:04.174196 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5096 01:21:04.174308 ==
5097 01:21:04.177695 Dram Type= 6, Freq= 0, CH_0, rank 0
5098 01:21:04.180912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5099 01:21:04.180992 ==
5100 01:21:04.187540 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5101 01:21:04.194205 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5102 01:21:04.197364 [CA 0] Center 37 (6~68) winsize 63
5103 01:21:04.200579 [CA 1] Center 37 (7~68) winsize 62
5104 01:21:04.203740 [CA 2] Center 34 (4~65) winsize 62
5105 01:21:04.207565 [CA 3] Center 34 (3~65) winsize 63
5106 01:21:04.210720 [CA 4] Center 33 (3~64) winsize 62
5107 01:21:04.214192 [CA 5] Center 32 (2~62) winsize 61
5108 01:21:04.214298
5109 01:21:04.216981 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5110 01:21:04.217060
5111 01:21:04.220678 [CATrainingPosCal] consider 1 rank data
5112 01:21:04.223914 u2DelayCellTimex100 = 270/100 ps
5113 01:21:04.226867 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5114 01:21:04.230340 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5115 01:21:04.233936 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5116 01:21:04.237060 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5117 01:21:04.243557 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5118 01:21:04.247304 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5119 01:21:04.247385
5120 01:21:04.250205 CA PerBit enable=1, Macro0, CA PI delay=32
5121 01:21:04.250292
5122 01:21:04.253625 [CBTSetCACLKResult] CA Dly = 32
5123 01:21:04.253706 CS Dly: 5 (0~36)
5124 01:21:04.253770 ==
5125 01:21:04.256880 Dram Type= 6, Freq= 0, CH_0, rank 1
5126 01:21:04.263804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5127 01:21:04.263885 ==
5128 01:21:04.266835 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5129 01:21:04.273734 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5130 01:21:04.276943 [CA 0] Center 37 (7~68) winsize 62
5131 01:21:04.280085 [CA 1] Center 37 (7~68) winsize 62
5132 01:21:04.283684 [CA 2] Center 34 (4~65) winsize 62
5133 01:21:04.287234 [CA 3] Center 34 (4~65) winsize 62
5134 01:21:04.290171 [CA 4] Center 32 (2~63) winsize 62
5135 01:21:04.293567 [CA 5] Center 32 (2~62) winsize 61
5136 01:21:04.293648
5137 01:21:04.297047 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5138 01:21:04.297127
5139 01:21:04.300125 [CATrainingPosCal] consider 2 rank data
5140 01:21:04.303319 u2DelayCellTimex100 = 270/100 ps
5141 01:21:04.306977 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5142 01:21:04.309787 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5143 01:21:04.313127 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5144 01:21:04.320104 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5145 01:21:04.323230 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5146 01:21:04.326801 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5147 01:21:04.326883
5148 01:21:04.330015 CA PerBit enable=1, Macro0, CA PI delay=32
5149 01:21:04.330097
5150 01:21:04.333192 [CBTSetCACLKResult] CA Dly = 32
5151 01:21:04.333273 CS Dly: 5 (0~37)
5152 01:21:04.333337
5153 01:21:04.336791 ----->DramcWriteLeveling(PI) begin...
5154 01:21:04.339691 ==
5155 01:21:04.339772 Dram Type= 6, Freq= 0, CH_0, rank 0
5156 01:21:04.346666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5157 01:21:04.346771 ==
5158 01:21:04.349675 Write leveling (Byte 0): 32 => 32
5159 01:21:04.352931 Write leveling (Byte 1): 30 => 30
5160 01:21:04.356669 DramcWriteLeveling(PI) end<-----
5161 01:21:04.356750
5162 01:21:04.356815 ==
5163 01:21:04.359842 Dram Type= 6, Freq= 0, CH_0, rank 0
5164 01:21:04.363059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5165 01:21:04.363141 ==
5166 01:21:04.366210 [Gating] SW mode calibration
5167 01:21:04.373172 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5168 01:21:04.379865 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5169 01:21:04.383012 0 14 0 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
5170 01:21:04.386136 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 01:21:04.392727 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5172 01:21:04.395884 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5173 01:21:04.399717 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 01:21:04.402869 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5175 01:21:04.409593 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5176 01:21:04.412783 0 14 28 | B1->B0 | 3434 2525 | 1 1 | (1 1) (1 0)
5177 01:21:04.415850 0 15 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
5178 01:21:04.422942 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 01:21:04.425852 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 01:21:04.429304 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 01:21:04.435504 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 01:21:04.438783 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 01:21:04.442193 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5184 01:21:04.448808 0 15 28 | B1->B0 | 2424 3e3e | 0 0 | (0 0) (0 0)
5185 01:21:04.452390 1 0 0 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
5186 01:21:04.455480 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 01:21:04.461957 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 01:21:04.465388 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 01:21:04.468541 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 01:21:04.475525 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 01:21:04.478897 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 01:21:04.481896 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5193 01:21:04.488408 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5194 01:21:04.492116 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 01:21:04.495349 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 01:21:04.501806 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 01:21:04.505074 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 01:21:04.508151 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 01:21:04.515024 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 01:21:04.518111 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 01:21:04.521828 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 01:21:04.528354 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 01:21:04.531470 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 01:21:04.534642 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 01:21:04.541777 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 01:21:04.544940 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 01:21:04.548233 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5208 01:21:04.555090 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5209 01:21:04.555172 Total UI for P1: 0, mck2ui 16
5210 01:21:04.561271 best dqsien dly found for B0: ( 1, 2, 24)
5211 01:21:04.564932 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5212 01:21:04.567836 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5213 01:21:04.571308 Total UI for P1: 0, mck2ui 16
5214 01:21:04.574823 best dqsien dly found for B1: ( 1, 3, 0)
5215 01:21:04.577930 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5216 01:21:04.581690 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5217 01:21:04.581770
5218 01:21:04.584842 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5219 01:21:04.591832 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5220 01:21:04.591914 [Gating] SW calibration Done
5221 01:21:04.591977 ==
5222 01:21:04.594453 Dram Type= 6, Freq= 0, CH_0, rank 0
5223 01:21:04.601403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5224 01:21:04.601485 ==
5225 01:21:04.601549 RX Vref Scan: 0
5226 01:21:04.601609
5227 01:21:04.604589 RX Vref 0 -> 0, step: 1
5228 01:21:04.604671
5229 01:21:04.608447 RX Delay -80 -> 252, step: 8
5230 01:21:04.611516 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5231 01:21:04.614867 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5232 01:21:04.617820 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5233 01:21:04.624498 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5234 01:21:04.628102 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5235 01:21:04.631387 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5236 01:21:04.634509 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5237 01:21:04.637844 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5238 01:21:04.641672 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5239 01:21:04.648142 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5240 01:21:04.651296 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5241 01:21:04.654680 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5242 01:21:04.657850 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5243 01:21:04.661035 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5244 01:21:04.664367 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5245 01:21:04.671122 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5246 01:21:04.671204 ==
5247 01:21:04.674141 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 01:21:04.677967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 01:21:04.678048 ==
5250 01:21:04.678113 DQS Delay:
5251 01:21:04.681200 DQS0 = 0, DQS1 = 0
5252 01:21:04.681281 DQM Delay:
5253 01:21:04.684073 DQM0 = 105, DQM1 = 94
5254 01:21:04.684154 DQ Delay:
5255 01:21:04.687934 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5256 01:21:04.691130 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5257 01:21:04.694396 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5258 01:21:04.697781 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5259 01:21:04.697862
5260 01:21:04.697926
5261 01:21:04.697985 ==
5262 01:21:04.700832 Dram Type= 6, Freq= 0, CH_0, rank 0
5263 01:21:04.707546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 01:21:04.707628 ==
5265 01:21:04.707692
5266 01:21:04.707750
5267 01:21:04.707806 TX Vref Scan disable
5268 01:21:04.710564 == TX Byte 0 ==
5269 01:21:04.714034 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5270 01:21:04.720690 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5271 01:21:04.720771 == TX Byte 1 ==
5272 01:21:04.723997 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5273 01:21:04.730343 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5274 01:21:04.730425 ==
5275 01:21:04.733450 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 01:21:04.736839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 01:21:04.736920 ==
5278 01:21:04.736984
5279 01:21:04.737048
5280 01:21:04.740421 TX Vref Scan disable
5281 01:21:04.740502 == TX Byte 0 ==
5282 01:21:04.746743 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5283 01:21:04.750474 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5284 01:21:04.750557 == TX Byte 1 ==
5285 01:21:04.757393 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5286 01:21:04.760132 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5287 01:21:04.760214
5288 01:21:04.760278 [DATLAT]
5289 01:21:04.763442 Freq=933, CH0 RK0
5290 01:21:04.763524
5291 01:21:04.763588 DATLAT Default: 0xd
5292 01:21:04.767092 0, 0xFFFF, sum = 0
5293 01:21:04.767175 1, 0xFFFF, sum = 0
5294 01:21:04.770289 2, 0xFFFF, sum = 0
5295 01:21:04.773307 3, 0xFFFF, sum = 0
5296 01:21:04.773389 4, 0xFFFF, sum = 0
5297 01:21:04.776670 5, 0xFFFF, sum = 0
5298 01:21:04.776764 6, 0xFFFF, sum = 0
5299 01:21:04.780028 7, 0xFFFF, sum = 0
5300 01:21:04.780111 8, 0xFFFF, sum = 0
5301 01:21:04.783225 9, 0xFFFF, sum = 0
5302 01:21:04.783308 10, 0x0, sum = 1
5303 01:21:04.786447 11, 0x0, sum = 2
5304 01:21:04.786546 12, 0x0, sum = 3
5305 01:21:04.790288 13, 0x0, sum = 4
5306 01:21:04.790395 best_step = 11
5307 01:21:04.790459
5308 01:21:04.790518 ==
5309 01:21:04.793928 Dram Type= 6, Freq= 0, CH_0, rank 0
5310 01:21:04.796687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 01:21:04.796769 ==
5312 01:21:04.799763 RX Vref Scan: 1
5313 01:21:04.799844
5314 01:21:04.802923 RX Vref 0 -> 0, step: 1
5315 01:21:04.803005
5316 01:21:04.803078 RX Delay -45 -> 252, step: 4
5317 01:21:04.803140
5318 01:21:04.806811 Set Vref, RX VrefLevel [Byte0]: 53
5319 01:21:04.809771 [Byte1]: 54
5320 01:21:04.814656
5321 01:21:04.814737 Final RX Vref Byte 0 = 53 to rank0
5322 01:21:04.817860 Final RX Vref Byte 1 = 54 to rank0
5323 01:21:04.820889 Final RX Vref Byte 0 = 53 to rank1
5324 01:21:04.824859 Final RX Vref Byte 1 = 54 to rank1==
5325 01:21:04.827982 Dram Type= 6, Freq= 0, CH_0, rank 0
5326 01:21:04.834289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5327 01:21:04.834392 ==
5328 01:21:04.834456 DQS Delay:
5329 01:21:04.834518 DQS0 = 0, DQS1 = 0
5330 01:21:04.837547 DQM Delay:
5331 01:21:04.837627 DQM0 = 104, DQM1 = 95
5332 01:21:04.841229 DQ Delay:
5333 01:21:04.844105 DQ0 =106, DQ1 =104, DQ2 =102, DQ3 =104
5334 01:21:04.847524 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5335 01:21:04.851066 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =90
5336 01:21:04.854416 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =102
5337 01:21:04.854498
5338 01:21:04.854561
5339 01:21:04.861057 [DQSOSCAuto] RK0, (LSB)MR18= 0x322a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5340 01:21:04.864068 CH0 RK0: MR19=505, MR18=322A
5341 01:21:04.870614 CH0_RK0: MR19=0x505, MR18=0x322A, DQSOSC=406, MR23=63, INC=65, DEC=43
5342 01:21:04.870746
5343 01:21:04.874029 ----->DramcWriteLeveling(PI) begin...
5344 01:21:04.874111 ==
5345 01:21:04.877598 Dram Type= 6, Freq= 0, CH_0, rank 1
5346 01:21:04.880799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5347 01:21:04.880879 ==
5348 01:21:04.884383 Write leveling (Byte 0): 34 => 34
5349 01:21:04.887235 Write leveling (Byte 1): 29 => 29
5350 01:21:04.890656 DramcWriteLeveling(PI) end<-----
5351 01:21:04.890767
5352 01:21:04.890834 ==
5353 01:21:04.893807 Dram Type= 6, Freq= 0, CH_0, rank 1
5354 01:21:04.900855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5355 01:21:04.900935 ==
5356 01:21:04.900998 [Gating] SW mode calibration
5357 01:21:04.910492 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5358 01:21:04.914085 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5359 01:21:04.920332 0 14 0 | B1->B0 | 3131 2f2f | 1 0 | (0 0) (0 0)
5360 01:21:04.923923 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 01:21:04.926883 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 01:21:04.930250 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 01:21:04.937184 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 01:21:04.940346 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 01:21:04.943571 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5366 01:21:04.950392 0 14 28 | B1->B0 | 2e2e 2f2f | 1 1 | (1 1) (1 0)
5367 01:21:04.953900 0 15 0 | B1->B0 | 2626 2424 | 0 0 | (0 0) (1 1)
5368 01:21:04.957428 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 01:21:04.964142 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 01:21:04.967298 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 01:21:04.970602 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 01:21:04.977367 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 01:21:04.980592 0 15 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5374 01:21:04.983812 0 15 28 | B1->B0 | 3939 3a3a | 1 0 | (0 0) (0 0)
5375 01:21:04.990195 1 0 0 | B1->B0 | 4444 4545 | 0 0 | (0 0) (0 0)
5376 01:21:04.993454 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 01:21:04.996922 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 01:21:05.003425 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 01:21:05.006623 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 01:21:05.010062 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 01:21:05.016637 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5382 01:21:05.020154 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5383 01:21:05.023675 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5384 01:21:05.030140 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 01:21:05.033714 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 01:21:05.036912 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 01:21:05.043185 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 01:21:05.046458 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 01:21:05.050237 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 01:21:05.056656 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 01:21:05.059730 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 01:21:05.063246 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 01:21:05.066367 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 01:21:05.073593 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 01:21:05.076783 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 01:21:05.079967 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 01:21:05.086279 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 01:21:05.089970 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5399 01:21:05.093229 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 01:21:05.096679 Total UI for P1: 0, mck2ui 16
5401 01:21:05.099784 best dqsien dly found for B0: ( 1, 2, 28)
5402 01:21:05.103155 Total UI for P1: 0, mck2ui 16
5403 01:21:05.106296 best dqsien dly found for B1: ( 1, 2, 28)
5404 01:21:05.109345 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5405 01:21:05.116276 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5406 01:21:05.116355
5407 01:21:05.119323 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5408 01:21:05.122971 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5409 01:21:05.126763 [Gating] SW calibration Done
5410 01:21:05.126864 ==
5411 01:21:05.129540 Dram Type= 6, Freq= 0, CH_0, rank 1
5412 01:21:05.132884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5413 01:21:05.133004 ==
5414 01:21:05.133069 RX Vref Scan: 0
5415 01:21:05.136100
5416 01:21:05.136180 RX Vref 0 -> 0, step: 1
5417 01:21:05.136245
5418 01:21:05.139496 RX Delay -80 -> 252, step: 8
5419 01:21:05.142678 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5420 01:21:05.146375 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5421 01:21:05.152504 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5422 01:21:05.156037 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5423 01:21:05.159295 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5424 01:21:05.162775 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5425 01:21:05.165923 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5426 01:21:05.169762 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5427 01:21:05.176116 iDelay=208, Bit 8, Center 91 (8 ~ 175) 168
5428 01:21:05.179202 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5429 01:21:05.182432 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5430 01:21:05.185995 iDelay=208, Bit 11, Center 91 (8 ~ 175) 168
5431 01:21:05.189237 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5432 01:21:05.192557 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5433 01:21:05.199214 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5434 01:21:05.202284 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5435 01:21:05.202372 ==
5436 01:21:05.206136 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 01:21:05.209305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 01:21:05.209385 ==
5439 01:21:05.212418 DQS Delay:
5440 01:21:05.212497 DQS0 = 0, DQS1 = 0
5441 01:21:05.212561 DQM Delay:
5442 01:21:05.215686 DQM0 = 104, DQM1 = 96
5443 01:21:05.215766 DQ Delay:
5444 01:21:05.219457 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5445 01:21:05.222621 DQ4 =107, DQ5 =99, DQ6 =107, DQ7 =111
5446 01:21:05.225842 DQ8 =91, DQ9 =87, DQ10 =95, DQ11 =91
5447 01:21:05.228861 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =103
5448 01:21:05.228941
5449 01:21:05.229004
5450 01:21:05.232121 ==
5451 01:21:05.236055 Dram Type= 6, Freq= 0, CH_0, rank 1
5452 01:21:05.239260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5453 01:21:05.239340 ==
5454 01:21:05.239403
5455 01:21:05.239461
5456 01:21:05.242381 TX Vref Scan disable
5457 01:21:05.242462 == TX Byte 0 ==
5458 01:21:05.249177 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5459 01:21:05.252272 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5460 01:21:05.252354 == TX Byte 1 ==
5461 01:21:05.258824 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5462 01:21:05.261969 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5463 01:21:05.262050 ==
5464 01:21:05.265844 Dram Type= 6, Freq= 0, CH_0, rank 1
5465 01:21:05.268598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5466 01:21:05.268680 ==
5467 01:21:05.268745
5468 01:21:05.268804
5469 01:21:05.272039 TX Vref Scan disable
5470 01:21:05.275727 == TX Byte 0 ==
5471 01:21:05.278967 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5472 01:21:05.281946 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5473 01:21:05.285003 == TX Byte 1 ==
5474 01:21:05.289273 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5475 01:21:05.292319 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5476 01:21:05.292401
5477 01:21:05.295238 [DATLAT]
5478 01:21:05.295320 Freq=933, CH0 RK1
5479 01:21:05.295385
5480 01:21:05.298463 DATLAT Default: 0xb
5481 01:21:05.298545 0, 0xFFFF, sum = 0
5482 01:21:05.301753 1, 0xFFFF, sum = 0
5483 01:21:05.301835 2, 0xFFFF, sum = 0
5484 01:21:05.304951 3, 0xFFFF, sum = 0
5485 01:21:05.305034 4, 0xFFFF, sum = 0
5486 01:21:05.308776 5, 0xFFFF, sum = 0
5487 01:21:05.308859 6, 0xFFFF, sum = 0
5488 01:21:05.312332 7, 0xFFFF, sum = 0
5489 01:21:05.312415 8, 0xFFFF, sum = 0
5490 01:21:05.315613 9, 0xFFFF, sum = 0
5491 01:21:05.315695 10, 0x0, sum = 1
5492 01:21:05.318889 11, 0x0, sum = 2
5493 01:21:05.318971 12, 0x0, sum = 3
5494 01:21:05.322057 13, 0x0, sum = 4
5495 01:21:05.322139 best_step = 11
5496 01:21:05.322203
5497 01:21:05.322262 ==
5498 01:21:05.324973 Dram Type= 6, Freq= 0, CH_0, rank 1
5499 01:21:05.331884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5500 01:21:05.331966 ==
5501 01:21:05.332031 RX Vref Scan: 0
5502 01:21:05.332090
5503 01:21:05.335126 RX Vref 0 -> 0, step: 1
5504 01:21:05.335208
5505 01:21:05.338276 RX Delay -45 -> 252, step: 4
5506 01:21:05.342277 iDelay=195, Bit 0, Center 102 (15 ~ 190) 176
5507 01:21:05.345244 iDelay=195, Bit 1, Center 108 (23 ~ 194) 172
5508 01:21:05.351654 iDelay=195, Bit 2, Center 102 (15 ~ 190) 176
5509 01:21:05.354786 iDelay=195, Bit 3, Center 102 (15 ~ 190) 176
5510 01:21:05.358281 iDelay=195, Bit 4, Center 106 (19 ~ 194) 176
5511 01:21:05.361835 iDelay=195, Bit 5, Center 98 (11 ~ 186) 176
5512 01:21:05.365121 iDelay=195, Bit 6, Center 110 (27 ~ 194) 168
5513 01:21:05.371637 iDelay=195, Bit 7, Center 110 (27 ~ 194) 168
5514 01:21:05.374926 iDelay=195, Bit 8, Center 86 (3 ~ 170) 168
5515 01:21:05.378058 iDelay=195, Bit 9, Center 86 (3 ~ 170) 168
5516 01:21:05.381880 iDelay=195, Bit 10, Center 94 (11 ~ 178) 168
5517 01:21:05.385110 iDelay=195, Bit 11, Center 88 (7 ~ 170) 164
5518 01:21:05.388170 iDelay=195, Bit 12, Center 100 (19 ~ 182) 164
5519 01:21:05.394994 iDelay=195, Bit 13, Center 102 (19 ~ 186) 168
5520 01:21:05.398700 iDelay=195, Bit 14, Center 104 (19 ~ 190) 172
5521 01:21:05.402048 iDelay=195, Bit 15, Center 102 (19 ~ 186) 168
5522 01:21:05.402130 ==
5523 01:21:05.405057 Dram Type= 6, Freq= 0, CH_0, rank 1
5524 01:21:05.408775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5525 01:21:05.408857 ==
5526 01:21:05.411951 DQS Delay:
5527 01:21:05.412032 DQS0 = 0, DQS1 = 0
5528 01:21:05.414854 DQM Delay:
5529 01:21:05.414951 DQM0 = 104, DQM1 = 95
5530 01:21:05.415048 DQ Delay:
5531 01:21:05.418328 DQ0 =102, DQ1 =108, DQ2 =102, DQ3 =102
5532 01:21:05.421747 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =110
5533 01:21:05.424930 DQ8 =86, DQ9 =86, DQ10 =94, DQ11 =88
5534 01:21:05.431498 DQ12 =100, DQ13 =102, DQ14 =104, DQ15 =102
5535 01:21:05.431579
5536 01:21:05.431642
5537 01:21:05.438517 [DQSOSCAuto] RK1, (LSB)MR18= 0x2903, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5538 01:21:05.441520 CH0 RK1: MR19=505, MR18=2903
5539 01:21:05.448555 CH0_RK1: MR19=0x505, MR18=0x2903, DQSOSC=408, MR23=63, INC=65, DEC=43
5540 01:21:05.451291 [RxdqsGatingPostProcess] freq 933
5541 01:21:05.454797 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5542 01:21:05.457634 best DQS0 dly(2T, 0.5T) = (0, 10)
5543 01:21:05.461241 best DQS1 dly(2T, 0.5T) = (0, 11)
5544 01:21:05.464389 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5545 01:21:05.467458 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5546 01:21:05.470681 best DQS0 dly(2T, 0.5T) = (0, 10)
5547 01:21:05.474434 best DQS1 dly(2T, 0.5T) = (0, 10)
5548 01:21:05.477634 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5549 01:21:05.480859 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5550 01:21:05.484126 Pre-setting of DQS Precalculation
5551 01:21:05.490596 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5552 01:21:05.490706 ==
5553 01:21:05.494378 Dram Type= 6, Freq= 0, CH_1, rank 0
5554 01:21:05.497650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5555 01:21:05.497755 ==
5556 01:21:05.504612 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5557 01:21:05.507079 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5558 01:21:05.510975 [CA 0] Center 36 (6~67) winsize 62
5559 01:21:05.514299 [CA 1] Center 37 (6~68) winsize 63
5560 01:21:05.517978 [CA 2] Center 35 (5~65) winsize 61
5561 01:21:05.521097 [CA 3] Center 34 (4~65) winsize 62
5562 01:21:05.524241 [CA 4] Center 34 (4~65) winsize 62
5563 01:21:05.527399 [CA 5] Center 33 (3~64) winsize 62
5564 01:21:05.527481
5565 01:21:05.531140 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5566 01:21:05.531222
5567 01:21:05.534316 [CATrainingPosCal] consider 1 rank data
5568 01:21:05.537324 u2DelayCellTimex100 = 270/100 ps
5569 01:21:05.541000 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5570 01:21:05.547827 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5571 01:21:05.550767 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5572 01:21:05.554314 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5573 01:21:05.557712 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5574 01:21:05.560759 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5575 01:21:05.560870
5576 01:21:05.564563 CA PerBit enable=1, Macro0, CA PI delay=33
5577 01:21:05.564669
5578 01:21:05.567316 [CBTSetCACLKResult] CA Dly = 33
5579 01:21:05.570932 CS Dly: 6 (0~37)
5580 01:21:05.571013 ==
5581 01:21:05.573926 Dram Type= 6, Freq= 0, CH_1, rank 1
5582 01:21:05.577218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5583 01:21:05.577299 ==
5584 01:21:05.583766 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5585 01:21:05.586946 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5586 01:21:05.591152 [CA 0] Center 36 (6~67) winsize 62
5587 01:21:05.594529 [CA 1] Center 37 (6~68) winsize 63
5588 01:21:05.597745 [CA 2] Center 35 (5~66) winsize 62
5589 01:21:05.601243 [CA 3] Center 34 (4~65) winsize 62
5590 01:21:05.604450 [CA 4] Center 34 (4~65) winsize 62
5591 01:21:05.608082 [CA 5] Center 33 (3~64) winsize 62
5592 01:21:05.608212
5593 01:21:05.611153 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5594 01:21:05.611277
5595 01:21:05.614562 [CATrainingPosCal] consider 2 rank data
5596 01:21:05.617707 u2DelayCellTimex100 = 270/100 ps
5597 01:21:05.621598 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5598 01:21:05.624788 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5599 01:21:05.631178 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5600 01:21:05.634767 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5601 01:21:05.637961 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5602 01:21:05.640978 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5603 01:21:05.641090
5604 01:21:05.644664 CA PerBit enable=1, Macro0, CA PI delay=33
5605 01:21:05.644773
5606 01:21:05.647677 [CBTSetCACLKResult] CA Dly = 33
5607 01:21:05.647786 CS Dly: 7 (0~40)
5608 01:21:05.650819
5609 01:21:05.654962 ----->DramcWriteLeveling(PI) begin...
5610 01:21:05.655076 ==
5611 01:21:05.657865 Dram Type= 6, Freq= 0, CH_1, rank 0
5612 01:21:05.660978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5613 01:21:05.661087 ==
5614 01:21:05.664164 Write leveling (Byte 0): 26 => 26
5615 01:21:05.667665 Write leveling (Byte 1): 27 => 27
5616 01:21:05.670973 DramcWriteLeveling(PI) end<-----
5617 01:21:05.671099
5618 01:21:05.671195 ==
5619 01:21:05.674076 Dram Type= 6, Freq= 0, CH_1, rank 0
5620 01:21:05.677481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5621 01:21:05.677590 ==
5622 01:21:05.680647 [Gating] SW mode calibration
5623 01:21:05.687527 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5624 01:21:05.694572 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5625 01:21:05.697409 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 01:21:05.700669 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 01:21:05.707700 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 01:21:05.710931 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 01:21:05.713947 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5630 01:21:05.720889 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5631 01:21:05.724016 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
5632 01:21:05.727534 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5633 01:21:05.734188 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 01:21:05.737368 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 01:21:05.740389 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 01:21:05.744210 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 01:21:05.750359 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5638 01:21:05.754077 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5639 01:21:05.760314 0 15 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5640 01:21:05.763600 0 15 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5641 01:21:05.767523 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 01:21:05.770667 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 01:21:05.777163 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 01:21:05.780227 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 01:21:05.783474 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 01:21:05.790255 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 01:21:05.793382 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 01:21:05.797061 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5649 01:21:05.803464 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 01:21:05.806712 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 01:21:05.810228 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 01:21:05.816437 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 01:21:05.820385 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 01:21:05.823544 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 01:21:05.830195 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 01:21:05.833644 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 01:21:05.836749 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 01:21:05.843385 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 01:21:05.846642 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 01:21:05.850411 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 01:21:05.856511 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 01:21:05.859665 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 01:21:05.863179 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 01:21:05.869575 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5665 01:21:05.869745 Total UI for P1: 0, mck2ui 16
5666 01:21:05.876530 best dqsien dly found for B0: ( 1, 2, 26)
5667 01:21:05.876707 Total UI for P1: 0, mck2ui 16
5668 01:21:05.882888 best dqsien dly found for B1: ( 1, 2, 26)
5669 01:21:05.886062 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5670 01:21:05.889887 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5671 01:21:05.890017
5672 01:21:05.893129 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5673 01:21:05.896530 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5674 01:21:05.899712 [Gating] SW calibration Done
5675 01:21:05.899849 ==
5676 01:21:05.902776 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 01:21:05.906070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 01:21:05.906196 ==
5679 01:21:05.909215 RX Vref Scan: 0
5680 01:21:05.909358
5681 01:21:05.909457 RX Vref 0 -> 0, step: 1
5682 01:21:05.909551
5683 01:21:05.912446 RX Delay -80 -> 252, step: 8
5684 01:21:05.919779 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5685 01:21:05.922827 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5686 01:21:05.926124 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5687 01:21:05.929402 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5688 01:21:05.932630 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5689 01:21:05.935800 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5690 01:21:05.942580 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5691 01:21:05.945830 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5692 01:21:05.949464 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5693 01:21:05.952432 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5694 01:21:05.955627 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5695 01:21:05.959456 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5696 01:21:05.965700 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5697 01:21:05.969109 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5698 01:21:05.972271 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5699 01:21:05.975324 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5700 01:21:05.975447 ==
5701 01:21:05.978751 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 01:21:05.985511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 01:21:05.985648 ==
5704 01:21:05.985746 DQS Delay:
5705 01:21:05.985837 DQS0 = 0, DQS1 = 0
5706 01:21:05.988842 DQM Delay:
5707 01:21:05.988948 DQM0 = 102, DQM1 = 98
5708 01:21:05.992333 DQ Delay:
5709 01:21:05.995428 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5710 01:21:05.998926 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5711 01:21:06.001881 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5712 01:21:06.005165 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5713 01:21:06.005279
5714 01:21:06.005373
5715 01:21:06.005461 ==
5716 01:21:06.008674 Dram Type= 6, Freq= 0, CH_1, rank 0
5717 01:21:06.011913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5718 01:21:06.012023 ==
5719 01:21:06.012117
5720 01:21:06.012229
5721 01:21:06.015490 TX Vref Scan disable
5722 01:21:06.018711 == TX Byte 0 ==
5723 01:21:06.021966 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5724 01:21:06.025065 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5725 01:21:06.028296 == TX Byte 1 ==
5726 01:21:06.031948 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5727 01:21:06.035422 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5728 01:21:06.035536 ==
5729 01:21:06.038027 Dram Type= 6, Freq= 0, CH_1, rank 0
5730 01:21:06.044931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 01:21:06.045053 ==
5732 01:21:06.045144
5733 01:21:06.045238
5734 01:21:06.045330 TX Vref Scan disable
5735 01:21:06.048763 == TX Byte 0 ==
5736 01:21:06.052255 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5737 01:21:06.055737 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5738 01:21:06.058724 == TX Byte 1 ==
5739 01:21:06.061919 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5740 01:21:06.068908 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5741 01:21:06.069046
5742 01:21:06.069147 [DATLAT]
5743 01:21:06.069240 Freq=933, CH1 RK0
5744 01:21:06.069333
5745 01:21:06.072086 DATLAT Default: 0xd
5746 01:21:06.072197 0, 0xFFFF, sum = 0
5747 01:21:06.075218 1, 0xFFFF, sum = 0
5748 01:21:06.075332 2, 0xFFFF, sum = 0
5749 01:21:06.078499 3, 0xFFFF, sum = 0
5750 01:21:06.082159 4, 0xFFFF, sum = 0
5751 01:21:06.082277 5, 0xFFFF, sum = 0
5752 01:21:06.085080 6, 0xFFFF, sum = 0
5753 01:21:06.085194 7, 0xFFFF, sum = 0
5754 01:21:06.088799 8, 0xFFFF, sum = 0
5755 01:21:06.088909 9, 0xFFFF, sum = 0
5756 01:21:06.092053 10, 0x0, sum = 1
5757 01:21:06.092164 11, 0x0, sum = 2
5758 01:21:06.095342 12, 0x0, sum = 3
5759 01:21:06.095447 13, 0x0, sum = 4
5760 01:21:06.095540 best_step = 11
5761 01:21:06.095629
5762 01:21:06.098908 ==
5763 01:21:06.101669 Dram Type= 6, Freq= 0, CH_1, rank 0
5764 01:21:06.105286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 01:21:06.105400 ==
5766 01:21:06.105495 RX Vref Scan: 1
5767 01:21:06.105586
5768 01:21:06.108350 RX Vref 0 -> 0, step: 1
5769 01:21:06.108457
5770 01:21:06.112236 RX Delay -45 -> 252, step: 4
5771 01:21:06.112347
5772 01:21:06.115172 Set Vref, RX VrefLevel [Byte0]: 54
5773 01:21:06.118659 [Byte1]: 48
5774 01:21:06.118770
5775 01:21:06.121857 Final RX Vref Byte 0 = 54 to rank0
5776 01:21:06.125240 Final RX Vref Byte 1 = 48 to rank0
5777 01:21:06.128537 Final RX Vref Byte 0 = 54 to rank1
5778 01:21:06.131869 Final RX Vref Byte 1 = 48 to rank1==
5779 01:21:06.135126 Dram Type= 6, Freq= 0, CH_1, rank 0
5780 01:21:06.138309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5781 01:21:06.138434 ==
5782 01:21:06.141918 DQS Delay:
5783 01:21:06.142035 DQS0 = 0, DQS1 = 0
5784 01:21:06.145425 DQM Delay:
5785 01:21:06.145539 DQM0 = 103, DQM1 = 99
5786 01:21:06.145635 DQ Delay:
5787 01:21:06.148912 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5788 01:21:06.151847 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =102
5789 01:21:06.155156 DQ8 =90, DQ9 =90, DQ10 =100, DQ11 =96
5790 01:21:06.162196 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =108
5791 01:21:06.162379
5792 01:21:06.162480
5793 01:21:06.168927 [DQSOSCAuto] RK0, (LSB)MR18= 0x172f, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5794 01:21:06.171648 CH1 RK0: MR19=505, MR18=172F
5795 01:21:06.178803 CH1_RK0: MR19=0x505, MR18=0x172F, DQSOSC=407, MR23=63, INC=65, DEC=43
5796 01:21:06.178937
5797 01:21:06.181851 ----->DramcWriteLeveling(PI) begin...
5798 01:21:06.181963 ==
5799 01:21:06.185117 Dram Type= 6, Freq= 0, CH_1, rank 1
5800 01:21:06.188321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5801 01:21:06.188437 ==
5802 01:21:06.191805 Write leveling (Byte 0): 26 => 26
5803 01:21:06.194926 Write leveling (Byte 1): 27 => 27
5804 01:21:06.198194 DramcWriteLeveling(PI) end<-----
5805 01:21:06.198312
5806 01:21:06.198408 ==
5807 01:21:06.201476 Dram Type= 6, Freq= 0, CH_1, rank 1
5808 01:21:06.205283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5809 01:21:06.205394 ==
5810 01:21:06.208484 [Gating] SW mode calibration
5811 01:21:06.214804 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5812 01:21:06.221290 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5813 01:21:06.224625 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 01:21:06.231716 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 01:21:06.234656 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 01:21:06.238060 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 01:21:06.244714 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 01:21:06.247691 0 14 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5819 01:21:06.251030 0 14 24 | B1->B0 | 2f2f 3131 | 1 0 | (1 1) (0 0)
5820 01:21:06.257666 0 14 28 | B1->B0 | 2323 2626 | 0 0 | (1 0) (1 0)
5821 01:21:06.261219 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 01:21:06.264538 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 01:21:06.271180 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 01:21:06.274297 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 01:21:06.277497 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 01:21:06.284742 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5827 01:21:06.287664 0 15 24 | B1->B0 | 3434 2727 | 0 0 | (0 0) (0 0)
5828 01:21:06.290855 0 15 28 | B1->B0 | 4646 4040 | 0 0 | (0 0) (1 1)
5829 01:21:06.294562 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 01:21:06.301290 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 01:21:06.304667 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 01:21:06.307836 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 01:21:06.314278 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 01:21:06.317535 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 01:21:06.320764 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5836 01:21:06.327485 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5837 01:21:06.330884 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 01:21:06.334096 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 01:21:06.341129 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 01:21:06.344534 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 01:21:06.347282 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 01:21:06.353902 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 01:21:06.357712 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 01:21:06.360854 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 01:21:06.367377 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 01:21:06.370829 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 01:21:06.374238 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 01:21:06.380529 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 01:21:06.383831 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 01:21:06.386979 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 01:21:06.393737 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5852 01:21:06.396930 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5853 01:21:06.400519 Total UI for P1: 0, mck2ui 16
5854 01:21:06.403894 best dqsien dly found for B0: ( 1, 2, 24)
5855 01:21:06.406803 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5856 01:21:06.410242 Total UI for P1: 0, mck2ui 16
5857 01:21:06.413400 best dqsien dly found for B1: ( 1, 2, 26)
5858 01:21:06.416955 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5859 01:21:06.420490 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5860 01:21:06.420583
5861 01:21:06.426658 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5862 01:21:06.430558 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5863 01:21:06.430653 [Gating] SW calibration Done
5864 01:21:06.433363 ==
5865 01:21:06.436584 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 01:21:06.439821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 01:21:06.439909 ==
5868 01:21:06.439974 RX Vref Scan: 0
5869 01:21:06.440032
5870 01:21:06.443085 RX Vref 0 -> 0, step: 1
5871 01:21:06.443168
5872 01:21:06.446918 RX Delay -80 -> 252, step: 8
5873 01:21:06.449990 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5874 01:21:06.453109 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5875 01:21:06.456381 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5876 01:21:06.463318 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5877 01:21:06.466604 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5878 01:21:06.469732 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5879 01:21:06.473028 iDelay=208, Bit 6, Center 119 (32 ~ 207) 176
5880 01:21:06.476264 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5881 01:21:06.479633 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5882 01:21:06.486627 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5883 01:21:06.489816 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5884 01:21:06.492882 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5885 01:21:06.496202 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5886 01:21:06.499765 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5887 01:21:06.506374 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5888 01:21:06.509603 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5889 01:21:06.509695 ==
5890 01:21:06.512917 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 01:21:06.516128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 01:21:06.516214 ==
5893 01:21:06.519717 DQS Delay:
5894 01:21:06.519803 DQS0 = 0, DQS1 = 0
5895 01:21:06.519868 DQM Delay:
5896 01:21:06.522735 DQM0 = 103, DQM1 = 97
5897 01:21:06.522841 DQ Delay:
5898 01:21:06.526035 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5899 01:21:06.529233 DQ4 =95, DQ5 =119, DQ6 =119, DQ7 =99
5900 01:21:06.532777 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5901 01:21:06.535905 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =107
5902 01:21:06.535993
5903 01:21:06.536057
5904 01:21:06.539370 ==
5905 01:21:06.542614 Dram Type= 6, Freq= 0, CH_1, rank 1
5906 01:21:06.545922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5907 01:21:06.546011 ==
5908 01:21:06.546075
5909 01:21:06.546134
5910 01:21:06.549732 TX Vref Scan disable
5911 01:21:06.549852 == TX Byte 0 ==
5912 01:21:06.552671 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5913 01:21:06.559106 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5914 01:21:06.559209 == TX Byte 1 ==
5915 01:21:06.562820 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5916 01:21:06.568990 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5917 01:21:06.569094 ==
5918 01:21:06.572864 Dram Type= 6, Freq= 0, CH_1, rank 1
5919 01:21:06.575978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5920 01:21:06.576065 ==
5921 01:21:06.576129
5922 01:21:06.576188
5923 01:21:06.579132 TX Vref Scan disable
5924 01:21:06.582437 == TX Byte 0 ==
5925 01:21:06.585462 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5926 01:21:06.588708 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5927 01:21:06.592515 == TX Byte 1 ==
5928 01:21:06.595697 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5929 01:21:06.599086 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5930 01:21:06.599174
5931 01:21:06.602162 [DATLAT]
5932 01:21:06.602244 Freq=933, CH1 RK1
5933 01:21:06.602332
5934 01:21:06.605334 DATLAT Default: 0xb
5935 01:21:06.605415 0, 0xFFFF, sum = 0
5936 01:21:06.608977 1, 0xFFFF, sum = 0
5937 01:21:06.609062 2, 0xFFFF, sum = 0
5938 01:21:06.612124 3, 0xFFFF, sum = 0
5939 01:21:06.612208 4, 0xFFFF, sum = 0
5940 01:21:06.615173 5, 0xFFFF, sum = 0
5941 01:21:06.615258 6, 0xFFFF, sum = 0
5942 01:21:06.619038 7, 0xFFFF, sum = 0
5943 01:21:06.619141 8, 0xFFFF, sum = 0
5944 01:21:06.621999 9, 0xFFFF, sum = 0
5945 01:21:06.622082 10, 0x0, sum = 1
5946 01:21:06.625123 11, 0x0, sum = 2
5947 01:21:06.625208 12, 0x0, sum = 3
5948 01:21:06.628830 13, 0x0, sum = 4
5949 01:21:06.628916 best_step = 11
5950 01:21:06.628980
5951 01:21:06.629039 ==
5952 01:21:06.632163 Dram Type= 6, Freq= 0, CH_1, rank 1
5953 01:21:06.638334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5954 01:21:06.638428 ==
5955 01:21:06.638496 RX Vref Scan: 0
5956 01:21:06.638555
5957 01:21:06.641808 RX Vref 0 -> 0, step: 1
5958 01:21:06.641892
5959 01:21:06.644997 RX Delay -45 -> 252, step: 4
5960 01:21:06.648793 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5961 01:21:06.651838 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5962 01:21:06.658446 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5963 01:21:06.662327 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5964 01:21:06.664928 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5965 01:21:06.668295 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5966 01:21:06.671868 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5967 01:21:06.678833 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5968 01:21:06.681693 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5969 01:21:06.684963 iDelay=203, Bit 9, Center 90 (7 ~ 174) 168
5970 01:21:06.688190 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5971 01:21:06.691691 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5972 01:21:06.694993 iDelay=203, Bit 12, Center 106 (19 ~ 194) 176
5973 01:21:06.701526 iDelay=203, Bit 13, Center 102 (19 ~ 186) 168
5974 01:21:06.705366 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5975 01:21:06.708641 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5976 01:21:06.708730 ==
5977 01:21:06.711726 Dram Type= 6, Freq= 0, CH_1, rank 1
5978 01:21:06.715111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5979 01:21:06.715198 ==
5980 01:21:06.718675 DQS Delay:
5981 01:21:06.718760 DQS0 = 0, DQS1 = 0
5982 01:21:06.721945 DQM Delay:
5983 01:21:06.722027 DQM0 = 105, DQM1 = 99
5984 01:21:06.722091 DQ Delay:
5985 01:21:06.725077 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5986 01:21:06.731894 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5987 01:21:06.735010 DQ8 =90, DQ9 =90, DQ10 =102, DQ11 =94
5988 01:21:06.738790 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =108
5989 01:21:06.738877
5990 01:21:06.738941
5991 01:21:06.744921 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d01, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5992 01:21:06.748627 CH1 RK1: MR19=505, MR18=2D01
5993 01:21:06.755277 CH1_RK1: MR19=0x505, MR18=0x2D01, DQSOSC=407, MR23=63, INC=65, DEC=43
5994 01:21:06.758033 [RxdqsGatingPostProcess] freq 933
5995 01:21:06.761844 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5996 01:21:06.765029 best DQS0 dly(2T, 0.5T) = (0, 10)
5997 01:21:06.768125 best DQS1 dly(2T, 0.5T) = (0, 10)
5998 01:21:06.771107 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5999 01:21:06.774723 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6000 01:21:06.778056 best DQS0 dly(2T, 0.5T) = (0, 10)
6001 01:21:06.781156 best DQS1 dly(2T, 0.5T) = (0, 10)
6002 01:21:06.784896 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6003 01:21:06.787723 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6004 01:21:06.791124 Pre-setting of DQS Precalculation
6005 01:21:06.797826 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6006 01:21:06.804771 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6007 01:21:06.811029 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6008 01:21:06.811143
6009 01:21:06.811210
6010 01:21:06.814756 [Calibration Summary] 1866 Mbps
6011 01:21:06.814844 CH 0, Rank 0
6012 01:21:06.817500 SW Impedance : PASS
6013 01:21:06.821284 DUTY Scan : NO K
6014 01:21:06.821370 ZQ Calibration : PASS
6015 01:21:06.824624 Jitter Meter : NO K
6016 01:21:06.824708 CBT Training : PASS
6017 01:21:06.827777 Write leveling : PASS
6018 01:21:06.830749 RX DQS gating : PASS
6019 01:21:06.830833 RX DQ/DQS(RDDQC) : PASS
6020 01:21:06.834265 TX DQ/DQS : PASS
6021 01:21:06.837446 RX DATLAT : PASS
6022 01:21:06.837532 RX DQ/DQS(Engine): PASS
6023 01:21:06.841077 TX OE : NO K
6024 01:21:06.841162 All Pass.
6025 01:21:06.841226
6026 01:21:06.844394 CH 0, Rank 1
6027 01:21:06.844477 SW Impedance : PASS
6028 01:21:06.847536 DUTY Scan : NO K
6029 01:21:06.850560 ZQ Calibration : PASS
6030 01:21:06.850663 Jitter Meter : NO K
6031 01:21:06.854201 CBT Training : PASS
6032 01:21:06.857355 Write leveling : PASS
6033 01:21:06.857440 RX DQS gating : PASS
6034 01:21:06.860579 RX DQ/DQS(RDDQC) : PASS
6035 01:21:06.863788 TX DQ/DQS : PASS
6036 01:21:06.863871 RX DATLAT : PASS
6037 01:21:06.867610 RX DQ/DQS(Engine): PASS
6038 01:21:06.870717 TX OE : NO K
6039 01:21:06.870801 All Pass.
6040 01:21:06.870866
6041 01:21:06.870924 CH 1, Rank 0
6042 01:21:06.873874 SW Impedance : PASS
6043 01:21:06.877046 DUTY Scan : NO K
6044 01:21:06.877129 ZQ Calibration : PASS
6045 01:21:06.880468 Jitter Meter : NO K
6046 01:21:06.880552 CBT Training : PASS
6047 01:21:06.884004 Write leveling : PASS
6048 01:21:06.887261 RX DQS gating : PASS
6049 01:21:06.887346 RX DQ/DQS(RDDQC) : PASS
6050 01:21:06.890372 TX DQ/DQS : PASS
6051 01:21:06.894284 RX DATLAT : PASS
6052 01:21:06.894416 RX DQ/DQS(Engine): PASS
6053 01:21:06.897222 TX OE : NO K
6054 01:21:06.897314 All Pass.
6055 01:21:06.897378
6056 01:21:06.900206 CH 1, Rank 1
6057 01:21:06.900288 SW Impedance : PASS
6058 01:21:06.903731 DUTY Scan : NO K
6059 01:21:06.907148 ZQ Calibration : PASS
6060 01:21:06.907233 Jitter Meter : NO K
6061 01:21:06.910168 CBT Training : PASS
6062 01:21:06.913892 Write leveling : PASS
6063 01:21:06.913980 RX DQS gating : PASS
6064 01:21:06.917043 RX DQ/DQS(RDDQC) : PASS
6065 01:21:06.920210 TX DQ/DQS : PASS
6066 01:21:06.920296 RX DATLAT : PASS
6067 01:21:06.923784 RX DQ/DQS(Engine): PASS
6068 01:21:06.926915 TX OE : NO K
6069 01:21:06.927001 All Pass.
6070 01:21:06.927065
6071 01:21:06.927123 DramC Write-DBI off
6072 01:21:06.930340 PER_BANK_REFRESH: Hybrid Mode
6073 01:21:06.933570 TX_TRACKING: ON
6074 01:21:06.940181 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6075 01:21:06.943787 [FAST_K] Save calibration result to emmc
6076 01:21:06.949997 dramc_set_vcore_voltage set vcore to 650000
6077 01:21:06.950166 Read voltage for 400, 6
6078 01:21:06.953787 Vio18 = 0
6079 01:21:06.953884 Vcore = 650000
6080 01:21:06.953952 Vdram = 0
6081 01:21:06.956712 Vddq = 0
6082 01:21:06.956797 Vmddr = 0
6083 01:21:06.960334 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6084 01:21:06.967015 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6085 01:21:06.970227 MEM_TYPE=3, freq_sel=20
6086 01:21:06.970381 sv_algorithm_assistance_LP4_800
6087 01:21:06.977132 ============ PULL DRAM RESETB DOWN ============
6088 01:21:06.980194 ========== PULL DRAM RESETB DOWN end =========
6089 01:21:06.983347 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6090 01:21:06.986990 ===================================
6091 01:21:06.990098 LPDDR4 DRAM CONFIGURATION
6092 01:21:06.993334 ===================================
6093 01:21:06.997087 EX_ROW_EN[0] = 0x0
6094 01:21:06.997177 EX_ROW_EN[1] = 0x0
6095 01:21:07.000300 LP4Y_EN = 0x0
6096 01:21:07.000390 WORK_FSP = 0x0
6097 01:21:07.003252 WL = 0x2
6098 01:21:07.003337 RL = 0x2
6099 01:21:07.007131 BL = 0x2
6100 01:21:07.007226 RPST = 0x0
6101 01:21:07.010140 RD_PRE = 0x0
6102 01:21:07.010229 WR_PRE = 0x1
6103 01:21:07.013492 WR_PST = 0x0
6104 01:21:07.013579 DBI_WR = 0x0
6105 01:21:07.016760 DBI_RD = 0x0
6106 01:21:07.016843 OTF = 0x1
6107 01:21:07.019800 ===================================
6108 01:21:07.023050 ===================================
6109 01:21:07.026899 ANA top config
6110 01:21:07.030022 ===================================
6111 01:21:07.033196 DLL_ASYNC_EN = 0
6112 01:21:07.033284 ALL_SLAVE_EN = 1
6113 01:21:07.036393 NEW_RANK_MODE = 1
6114 01:21:07.039674 DLL_IDLE_MODE = 1
6115 01:21:07.043105 LP45_APHY_COMB_EN = 1
6116 01:21:07.043192 TX_ODT_DIS = 1
6117 01:21:07.046876 NEW_8X_MODE = 1
6118 01:21:07.049971 ===================================
6119 01:21:07.053115 ===================================
6120 01:21:07.056677 data_rate = 800
6121 01:21:07.059772 CKR = 1
6122 01:21:07.063246 DQ_P2S_RATIO = 4
6123 01:21:07.066453 ===================================
6124 01:21:07.069535 CA_P2S_RATIO = 4
6125 01:21:07.069622 DQ_CA_OPEN = 0
6126 01:21:07.072982 DQ_SEMI_OPEN = 1
6127 01:21:07.076338 CA_SEMI_OPEN = 1
6128 01:21:07.079479 CA_FULL_RATE = 0
6129 01:21:07.083014 DQ_CKDIV4_EN = 0
6130 01:21:07.086554 CA_CKDIV4_EN = 1
6131 01:21:07.086649 CA_PREDIV_EN = 0
6132 01:21:07.089529 PH8_DLY = 0
6133 01:21:07.092884 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6134 01:21:07.096150 DQ_AAMCK_DIV = 0
6135 01:21:07.099721 CA_AAMCK_DIV = 0
6136 01:21:07.103052 CA_ADMCK_DIV = 4
6137 01:21:07.103142 DQ_TRACK_CA_EN = 0
6138 01:21:07.106186 CA_PICK = 800
6139 01:21:07.109366 CA_MCKIO = 400
6140 01:21:07.113259 MCKIO_SEMI = 400
6141 01:21:07.116332 PLL_FREQ = 3016
6142 01:21:07.119634 DQ_UI_PI_RATIO = 32
6143 01:21:07.122939 CA_UI_PI_RATIO = 32
6144 01:21:07.126112 ===================================
6145 01:21:07.129247 ===================================
6146 01:21:07.129334 memory_type:LPDDR4
6147 01:21:07.132607 GP_NUM : 10
6148 01:21:07.136472 SRAM_EN : 1
6149 01:21:07.136564 MD32_EN : 0
6150 01:21:07.139616 ===================================
6151 01:21:07.142740 [ANA_INIT] >>>>>>>>>>>>>>
6152 01:21:07.146196 <<<<<< [CONFIGURE PHASE]: ANA_TX
6153 01:21:07.149807 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6154 01:21:07.152471 ===================================
6155 01:21:07.155710 data_rate = 800,PCW = 0X7400
6156 01:21:07.159534 ===================================
6157 01:21:07.162142 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6158 01:21:07.165963 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6159 01:21:07.179103 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6160 01:21:07.182280 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6161 01:21:07.185339 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6162 01:21:07.188851 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6163 01:21:07.192264 [ANA_INIT] flow start
6164 01:21:07.195459 [ANA_INIT] PLL >>>>>>>>
6165 01:21:07.195555 [ANA_INIT] PLL <<<<<<<<
6166 01:21:07.198883 [ANA_INIT] MIDPI >>>>>>>>
6167 01:21:07.202283 [ANA_INIT] MIDPI <<<<<<<<
6168 01:21:07.202394 [ANA_INIT] DLL >>>>>>>>
6169 01:21:07.205169 [ANA_INIT] flow end
6170 01:21:07.208508 ============ LP4 DIFF to SE enter ============
6171 01:21:07.215405 ============ LP4 DIFF to SE exit ============
6172 01:21:07.215510 [ANA_INIT] <<<<<<<<<<<<<
6173 01:21:07.218671 [Flow] Enable top DCM control >>>>>
6174 01:21:07.221897 [Flow] Enable top DCM control <<<<<
6175 01:21:07.225590 Enable DLL master slave shuffle
6176 01:21:07.232150 ==============================================================
6177 01:21:07.232297 Gating Mode config
6178 01:21:07.238353 ==============================================================
6179 01:21:07.241803 Config description:
6180 01:21:07.248278 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6181 01:21:07.255269 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6182 01:21:07.261530 SELPH_MODE 0: By rank 1: By Phase
6183 01:21:07.267858 ==============================================================
6184 01:21:07.271094 GAT_TRACK_EN = 0
6185 01:21:07.271201 RX_GATING_MODE = 2
6186 01:21:07.274926 RX_GATING_TRACK_MODE = 2
6187 01:21:07.278109 SELPH_MODE = 1
6188 01:21:07.281170 PICG_EARLY_EN = 1
6189 01:21:07.284362 VALID_LAT_VALUE = 1
6190 01:21:07.291774 ==============================================================
6191 01:21:07.294426 Enter into Gating configuration >>>>
6192 01:21:07.298116 Exit from Gating configuration <<<<
6193 01:21:07.301043 Enter into DVFS_PRE_config >>>>>
6194 01:21:07.310998 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6195 01:21:07.314771 Exit from DVFS_PRE_config <<<<<
6196 01:21:07.317770 Enter into PICG configuration >>>>
6197 01:21:07.321359 Exit from PICG configuration <<<<
6198 01:21:07.324273 [RX_INPUT] configuration >>>>>
6199 01:21:07.327854 [RX_INPUT] configuration <<<<<
6200 01:21:07.331139 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6201 01:21:07.338049 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6202 01:21:07.344458 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6203 01:21:07.351124 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6204 01:21:07.354173 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6205 01:21:07.360843 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6206 01:21:07.364213 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6207 01:21:07.370809 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6208 01:21:07.373925 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6209 01:21:07.377234 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6210 01:21:07.381004 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6211 01:21:07.387473 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6212 01:21:07.390494 ===================================
6213 01:21:07.390587 LPDDR4 DRAM CONFIGURATION
6214 01:21:07.393716 ===================================
6215 01:21:07.397353 EX_ROW_EN[0] = 0x0
6216 01:21:07.400348 EX_ROW_EN[1] = 0x0
6217 01:21:07.400439 LP4Y_EN = 0x0
6218 01:21:07.404009 WORK_FSP = 0x0
6219 01:21:07.404096 WL = 0x2
6220 01:21:07.407460 RL = 0x2
6221 01:21:07.407551 BL = 0x2
6222 01:21:07.410482 RPST = 0x0
6223 01:21:07.410570 RD_PRE = 0x0
6224 01:21:07.414215 WR_PRE = 0x1
6225 01:21:07.414392 WR_PST = 0x0
6226 01:21:07.417254 DBI_WR = 0x0
6227 01:21:07.417357 DBI_RD = 0x0
6228 01:21:07.420299 OTF = 0x1
6229 01:21:07.424065 ===================================
6230 01:21:07.427083 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6231 01:21:07.430976 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6232 01:21:07.436990 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6233 01:21:07.440596 ===================================
6234 01:21:07.440702 LPDDR4 DRAM CONFIGURATION
6235 01:21:07.443809 ===================================
6236 01:21:07.447007 EX_ROW_EN[0] = 0x10
6237 01:21:07.450149 EX_ROW_EN[1] = 0x0
6238 01:21:07.450239 LP4Y_EN = 0x0
6239 01:21:07.453542 WORK_FSP = 0x0
6240 01:21:07.453637 WL = 0x2
6241 01:21:07.457201 RL = 0x2
6242 01:21:07.457293 BL = 0x2
6243 01:21:07.460169 RPST = 0x0
6244 01:21:07.460255 RD_PRE = 0x0
6245 01:21:07.463426 WR_PRE = 0x1
6246 01:21:07.463513 WR_PST = 0x0
6247 01:21:07.467078 DBI_WR = 0x0
6248 01:21:07.467169 DBI_RD = 0x0
6249 01:21:07.470422 OTF = 0x1
6250 01:21:07.473692 ===================================
6251 01:21:07.479890 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6252 01:21:07.483250 nWR fixed to 30
6253 01:21:07.486411 [ModeRegInit_LP4] CH0 RK0
6254 01:21:07.486511 [ModeRegInit_LP4] CH0 RK1
6255 01:21:07.489876 [ModeRegInit_LP4] CH1 RK0
6256 01:21:07.493182 [ModeRegInit_LP4] CH1 RK1
6257 01:21:07.493279 match AC timing 19
6258 01:21:07.500645 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6259 01:21:07.503054 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6260 01:21:07.506968 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6261 01:21:07.512991 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6262 01:21:07.516459 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6263 01:21:07.516574 ==
6264 01:21:07.519644 Dram Type= 6, Freq= 0, CH_0, rank 0
6265 01:21:07.522996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6266 01:21:07.523137 ==
6267 01:21:07.529747 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6268 01:21:07.536743 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6269 01:21:07.539846 [CA 0] Center 36 (8~64) winsize 57
6270 01:21:07.539953 [CA 1] Center 36 (8~64) winsize 57
6271 01:21:07.543204 [CA 2] Center 36 (8~64) winsize 57
6272 01:21:07.546243 [CA 3] Center 36 (8~64) winsize 57
6273 01:21:07.550207 [CA 4] Center 36 (8~64) winsize 57
6274 01:21:07.553376 [CA 5] Center 36 (8~64) winsize 57
6275 01:21:07.553480
6276 01:21:07.556663 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6277 01:21:07.556753
6278 01:21:07.562939 [CATrainingPosCal] consider 1 rank data
6279 01:21:07.563042 u2DelayCellTimex100 = 270/100 ps
6280 01:21:07.569742 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 01:21:07.572769 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 01:21:07.576179 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 01:21:07.579415 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 01:21:07.583218 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 01:21:07.586505 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 01:21:07.586637
6287 01:21:07.589412 CA PerBit enable=1, Macro0, CA PI delay=36
6288 01:21:07.589496
6289 01:21:07.593205 [CBTSetCACLKResult] CA Dly = 36
6290 01:21:07.596746 CS Dly: 1 (0~32)
6291 01:21:07.596838 ==
6292 01:21:07.599916 Dram Type= 6, Freq= 0, CH_0, rank 1
6293 01:21:07.603004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6294 01:21:07.603094 ==
6295 01:21:07.606263 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6296 01:21:07.612725 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6297 01:21:07.616728 [CA 0] Center 36 (8~64) winsize 57
6298 01:21:07.619879 [CA 1] Center 36 (8~64) winsize 57
6299 01:21:07.623136 [CA 2] Center 36 (8~64) winsize 57
6300 01:21:07.626104 [CA 3] Center 36 (8~64) winsize 57
6301 01:21:07.629411 [CA 4] Center 36 (8~64) winsize 57
6302 01:21:07.633344 [CA 5] Center 36 (8~64) winsize 57
6303 01:21:07.633445
6304 01:21:07.636284 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6305 01:21:07.636370
6306 01:21:07.639884 [CATrainingPosCal] consider 2 rank data
6307 01:21:07.642695 u2DelayCellTimex100 = 270/100 ps
6308 01:21:07.646263 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 01:21:07.650017 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 01:21:07.652878 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 01:21:07.656007 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 01:21:07.662887 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 01:21:07.665991 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 01:21:07.666092
6315 01:21:07.669283 CA PerBit enable=1, Macro0, CA PI delay=36
6316 01:21:07.669370
6317 01:21:07.672432 [CBTSetCACLKResult] CA Dly = 36
6318 01:21:07.672537 CS Dly: 1 (0~32)
6319 01:21:07.672616
6320 01:21:07.676133 ----->DramcWriteLeveling(PI) begin...
6321 01:21:07.676223 ==
6322 01:21:07.679229 Dram Type= 6, Freq= 0, CH_0, rank 0
6323 01:21:07.686216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6324 01:21:07.686373 ==
6325 01:21:07.688972 Write leveling (Byte 0): 40 => 8
6326 01:21:07.692598 Write leveling (Byte 1): 40 => 8
6327 01:21:07.692688 DramcWriteLeveling(PI) end<-----
6328 01:21:07.692791
6329 01:21:07.695767 ==
6330 01:21:07.699087 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 01:21:07.702314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 01:21:07.702420 ==
6333 01:21:07.705541 [Gating] SW mode calibration
6334 01:21:07.712552 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6335 01:21:07.715720 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6336 01:21:07.722180 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6337 01:21:07.725928 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6338 01:21:07.729282 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6339 01:21:07.735864 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6340 01:21:07.739262 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6341 01:21:07.742288 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6342 01:21:07.748665 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6343 01:21:07.752078 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6344 01:21:07.755768 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6345 01:21:07.759437 Total UI for P1: 0, mck2ui 16
6346 01:21:07.761934 best dqsien dly found for B0: ( 0, 14, 24)
6347 01:21:07.765373 Total UI for P1: 0, mck2ui 16
6348 01:21:07.769001 best dqsien dly found for B1: ( 0, 14, 24)
6349 01:21:07.772283 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6350 01:21:07.775472 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6351 01:21:07.775578
6352 01:21:07.778896 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6353 01:21:07.785435 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6354 01:21:07.785577 [Gating] SW calibration Done
6355 01:21:07.789192 ==
6356 01:21:07.789293 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 01:21:07.795660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 01:21:07.795810 ==
6359 01:21:07.795892 RX Vref Scan: 0
6360 01:21:07.795952
6361 01:21:07.799108 RX Vref 0 -> 0, step: 1
6362 01:21:07.799196
6363 01:21:07.802525 RX Delay -410 -> 252, step: 16
6364 01:21:07.805288 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6365 01:21:07.809390 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6366 01:21:07.815644 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6367 01:21:07.818850 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6368 01:21:07.821928 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6369 01:21:07.825181 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6370 01:21:07.832048 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6371 01:21:07.835415 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6372 01:21:07.838424 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6373 01:21:07.841854 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6374 01:21:07.848359 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6375 01:21:07.852104 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6376 01:21:07.854907 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6377 01:21:07.858068 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6378 01:21:07.864878 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6379 01:21:07.868655 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6380 01:21:07.868769 ==
6381 01:21:07.871590 Dram Type= 6, Freq= 0, CH_0, rank 0
6382 01:21:07.874856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6383 01:21:07.874952 ==
6384 01:21:07.878268 DQS Delay:
6385 01:21:07.878400 DQS0 = 27, DQS1 = 35
6386 01:21:07.881587 DQM Delay:
6387 01:21:07.881676 DQM0 = 10, DQM1 = 11
6388 01:21:07.881741 DQ Delay:
6389 01:21:07.884665 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6390 01:21:07.887929 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6391 01:21:07.891632 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6392 01:21:07.894972 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6393 01:21:07.895071
6394 01:21:07.895137
6395 01:21:07.895196 ==
6396 01:21:07.898556 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 01:21:07.904718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 01:21:07.904834 ==
6399 01:21:07.904899
6400 01:21:07.904962
6401 01:21:07.905019 TX Vref Scan disable
6402 01:21:07.908203 == TX Byte 0 ==
6403 01:21:07.911740 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6404 01:21:07.915018 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6405 01:21:07.918214 == TX Byte 1 ==
6406 01:21:07.921637 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6407 01:21:07.924743 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6408 01:21:07.924848 ==
6409 01:21:07.928466 Dram Type= 6, Freq= 0, CH_0, rank 0
6410 01:21:07.934994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 01:21:07.935114 ==
6412 01:21:07.935180
6413 01:21:07.935248
6414 01:21:07.935313 TX Vref Scan disable
6415 01:21:07.938078 == TX Byte 0 ==
6416 01:21:07.941330 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6417 01:21:07.945209 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6418 01:21:07.948089 == TX Byte 1 ==
6419 01:21:07.951470 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6420 01:21:07.954891 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6421 01:21:07.955001
6422 01:21:07.957858 [DATLAT]
6423 01:21:07.957951 Freq=400, CH0 RK0
6424 01:21:07.958016
6425 01:21:07.961759 DATLAT Default: 0xf
6426 01:21:07.961844 0, 0xFFFF, sum = 0
6427 01:21:07.964932 1, 0xFFFF, sum = 0
6428 01:21:07.965016 2, 0xFFFF, sum = 0
6429 01:21:07.967846 3, 0xFFFF, sum = 0
6430 01:21:07.967929 4, 0xFFFF, sum = 0
6431 01:21:07.971440 5, 0xFFFF, sum = 0
6432 01:21:07.971534 6, 0xFFFF, sum = 0
6433 01:21:07.974655 7, 0xFFFF, sum = 0
6434 01:21:07.974742 8, 0xFFFF, sum = 0
6435 01:21:07.977719 9, 0xFFFF, sum = 0
6436 01:21:07.980983 10, 0xFFFF, sum = 0
6437 01:21:07.981076 11, 0xFFFF, sum = 0
6438 01:21:07.984799 12, 0xFFFF, sum = 0
6439 01:21:07.984891 13, 0x0, sum = 1
6440 01:21:07.987699 14, 0x0, sum = 2
6441 01:21:07.987819 15, 0x0, sum = 3
6442 01:21:07.987883 16, 0x0, sum = 4
6443 01:21:07.991317 best_step = 14
6444 01:21:07.991408
6445 01:21:07.991478 ==
6446 01:21:07.994574 Dram Type= 6, Freq= 0, CH_0, rank 0
6447 01:21:07.997793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 01:21:07.997884 ==
6449 01:21:08.001385 RX Vref Scan: 1
6450 01:21:08.001473
6451 01:21:08.001585 RX Vref 0 -> 0, step: 1
6452 01:21:08.004462
6453 01:21:08.004544 RX Delay -311 -> 252, step: 8
6454 01:21:08.004608
6455 01:21:08.007699 Set Vref, RX VrefLevel [Byte0]: 53
6456 01:21:08.011329 [Byte1]: 54
6457 01:21:08.016954
6458 01:21:08.017064 Final RX Vref Byte 0 = 53 to rank0
6459 01:21:08.019452 Final RX Vref Byte 1 = 54 to rank0
6460 01:21:08.022880 Final RX Vref Byte 0 = 53 to rank1
6461 01:21:08.026469 Final RX Vref Byte 1 = 54 to rank1==
6462 01:21:08.029724 Dram Type= 6, Freq= 0, CH_0, rank 0
6463 01:21:08.036125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 01:21:08.036286 ==
6465 01:21:08.036401 DQS Delay:
6466 01:21:08.039391 DQS0 = 28, DQS1 = 36
6467 01:21:08.039522 DQM Delay:
6468 01:21:08.039651 DQM0 = 11, DQM1 = 12
6469 01:21:08.042639 DQ Delay:
6470 01:21:08.045944 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6471 01:21:08.046076 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6472 01:21:08.049700 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6473 01:21:08.053074 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6474 01:21:08.056203
6475 01:21:08.056335
6476 01:21:08.062486 [DQSOSCAuto] RK0, (LSB)MR18= 0xc8b6, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6477 01:21:08.066229 CH0 RK0: MR19=C0C, MR18=C8B6
6478 01:21:08.073086 CH0_RK0: MR19=0xC0C, MR18=0xC8B6, DQSOSC=385, MR23=63, INC=398, DEC=265
6479 01:21:08.073260 ==
6480 01:21:08.075966 Dram Type= 6, Freq= 0, CH_0, rank 1
6481 01:21:08.079272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 01:21:08.079401 ==
6483 01:21:08.082540 [Gating] SW mode calibration
6484 01:21:08.089742 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6485 01:21:08.096418 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6486 01:21:08.099087 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6487 01:21:08.102926 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6488 01:21:08.106475 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6489 01:21:08.112502 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6490 01:21:08.116026 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 01:21:08.119002 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 01:21:08.125759 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6493 01:21:08.129551 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6494 01:21:08.132684 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6495 01:21:08.136031 Total UI for P1: 0, mck2ui 16
6496 01:21:08.139269 best dqsien dly found for B0: ( 0, 14, 24)
6497 01:21:08.142254 Total UI for P1: 0, mck2ui 16
6498 01:21:08.145825 best dqsien dly found for B1: ( 0, 14, 24)
6499 01:21:08.148879 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6500 01:21:08.155735 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6501 01:21:08.155953
6502 01:21:08.159168 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6503 01:21:08.162056 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6504 01:21:08.165628 [Gating] SW calibration Done
6505 01:21:08.165784 ==
6506 01:21:08.168733 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 01:21:08.172625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 01:21:08.172816 ==
6509 01:21:08.175346 RX Vref Scan: 0
6510 01:21:08.175504
6511 01:21:08.175627 RX Vref 0 -> 0, step: 1
6512 01:21:08.175754
6513 01:21:08.178723 RX Delay -410 -> 252, step: 16
6514 01:21:08.182331 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6515 01:21:08.189070 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6516 01:21:08.192306 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6517 01:21:08.195669 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6518 01:21:08.198711 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6519 01:21:08.205435 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6520 01:21:08.208603 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6521 01:21:08.211797 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6522 01:21:08.215589 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6523 01:21:08.221762 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6524 01:21:08.225458 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6525 01:21:08.228469 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6526 01:21:08.231857 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6527 01:21:08.238468 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6528 01:21:08.241624 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6529 01:21:08.244971 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6530 01:21:08.245102 ==
6531 01:21:08.248618 Dram Type= 6, Freq= 0, CH_0, rank 1
6532 01:21:08.255093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6533 01:21:08.255260 ==
6534 01:21:08.255377 DQS Delay:
6535 01:21:08.258456 DQS0 = 27, DQS1 = 35
6536 01:21:08.258580 DQM Delay:
6537 01:21:08.258692 DQM0 = 12, DQM1 = 10
6538 01:21:08.261592 DQ Delay:
6539 01:21:08.264695 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6540 01:21:08.268450 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6541 01:21:08.268587 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6542 01:21:08.271616 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6543 01:21:08.274974
6544 01:21:08.275101
6545 01:21:08.275210 ==
6546 01:21:08.278367 Dram Type= 6, Freq= 0, CH_0, rank 1
6547 01:21:08.281672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6548 01:21:08.281806 ==
6549 01:21:08.281915
6550 01:21:08.282018
6551 01:21:08.284506 TX Vref Scan disable
6552 01:21:08.284701 == TX Byte 0 ==
6553 01:21:08.287838 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6554 01:21:08.294587 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6555 01:21:08.294750 == TX Byte 1 ==
6556 01:21:08.297801 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6557 01:21:08.304816 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6558 01:21:08.304995 ==
6559 01:21:08.307801 Dram Type= 6, Freq= 0, CH_0, rank 1
6560 01:21:08.311151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6561 01:21:08.311285 ==
6562 01:21:08.311393
6563 01:21:08.311497
6564 01:21:08.314718 TX Vref Scan disable
6565 01:21:08.314851 == TX Byte 0 ==
6566 01:21:08.317952 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6567 01:21:08.324692 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6568 01:21:08.324865 == TX Byte 1 ==
6569 01:21:08.327898 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6570 01:21:08.334560 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6571 01:21:08.334767
6572 01:21:08.334900 [DATLAT]
6573 01:21:08.337390 Freq=400, CH0 RK1
6574 01:21:08.337523
6575 01:21:08.337646 DATLAT Default: 0xe
6576 01:21:08.340897 0, 0xFFFF, sum = 0
6577 01:21:08.341075 1, 0xFFFF, sum = 0
6578 01:21:08.344080 2, 0xFFFF, sum = 0
6579 01:21:08.344261 3, 0xFFFF, sum = 0
6580 01:21:08.347981 4, 0xFFFF, sum = 0
6581 01:21:08.348148 5, 0xFFFF, sum = 0
6582 01:21:08.351024 6, 0xFFFF, sum = 0
6583 01:21:08.351191 7, 0xFFFF, sum = 0
6584 01:21:08.354281 8, 0xFFFF, sum = 0
6585 01:21:08.354478 9, 0xFFFF, sum = 0
6586 01:21:08.357353 10, 0xFFFF, sum = 0
6587 01:21:08.357517 11, 0xFFFF, sum = 0
6588 01:21:08.360588 12, 0xFFFF, sum = 0
6589 01:21:08.360742 13, 0x0, sum = 1
6590 01:21:08.364419 14, 0x0, sum = 2
6591 01:21:08.364582 15, 0x0, sum = 3
6592 01:21:08.367421 16, 0x0, sum = 4
6593 01:21:08.367567 best_step = 14
6594 01:21:08.367698
6595 01:21:08.367808 ==
6596 01:21:08.371399 Dram Type= 6, Freq= 0, CH_0, rank 1
6597 01:21:08.377835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6598 01:21:08.378023 ==
6599 01:21:08.378153 RX Vref Scan: 0
6600 01:21:08.378270
6601 01:21:08.380890 RX Vref 0 -> 0, step: 1
6602 01:21:08.381026
6603 01:21:08.384067 RX Delay -311 -> 252, step: 8
6604 01:21:08.390676 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6605 01:21:08.394341 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6606 01:21:08.397564 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6607 01:21:08.400641 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6608 01:21:08.407404 iDelay=217, Bit 4, Center -12 (-239 ~ 216) 456
6609 01:21:08.410567 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6610 01:21:08.414025 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6611 01:21:08.417212 iDelay=217, Bit 7, Center -4 (-223 ~ 216) 440
6612 01:21:08.423849 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6613 01:21:08.427559 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6614 01:21:08.430294 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6615 01:21:08.433718 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6616 01:21:08.440533 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6617 01:21:08.443725 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6618 01:21:08.447005 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6619 01:21:08.450509 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6620 01:21:08.453517 ==
6621 01:21:08.456936 Dram Type= 6, Freq= 0, CH_0, rank 1
6622 01:21:08.460221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6623 01:21:08.460326 ==
6624 01:21:08.460391 DQS Delay:
6625 01:21:08.463786 DQS0 = 24, DQS1 = 32
6626 01:21:08.463879 DQM Delay:
6627 01:21:08.466990 DQM0 = 9, DQM1 = 9
6628 01:21:08.467078 DQ Delay:
6629 01:21:08.470215 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6630 01:21:08.473869 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =20
6631 01:21:08.476999 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6632 01:21:08.480252 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6633 01:21:08.480348
6634 01:21:08.480412
6635 01:21:08.486782 [DQSOSCAuto] RK1, (LSB)MR18= 0xb95a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6636 01:21:08.490016 CH0 RK1: MR19=C0C, MR18=B95A
6637 01:21:08.496986 CH0_RK1: MR19=0xC0C, MR18=0xB95A, DQSOSC=386, MR23=63, INC=396, DEC=264
6638 01:21:08.500180 [RxdqsGatingPostProcess] freq 400
6639 01:21:08.503437 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6640 01:21:08.506608 best DQS0 dly(2T, 0.5T) = (0, 10)
6641 01:21:08.510427 best DQS1 dly(2T, 0.5T) = (0, 10)
6642 01:21:08.513478 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6643 01:21:08.517019 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6644 01:21:08.520140 best DQS0 dly(2T, 0.5T) = (0, 10)
6645 01:21:08.523376 best DQS1 dly(2T, 0.5T) = (0, 10)
6646 01:21:08.526498 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6647 01:21:08.530263 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6648 01:21:08.532986 Pre-setting of DQS Precalculation
6649 01:21:08.536733 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6650 01:21:08.536833 ==
6651 01:21:08.539788 Dram Type= 6, Freq= 0, CH_1, rank 0
6652 01:21:08.546556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 01:21:08.546711 ==
6654 01:21:08.550051 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6655 01:21:08.556321 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6656 01:21:08.559846 [CA 0] Center 36 (8~64) winsize 57
6657 01:21:08.563247 [CA 1] Center 36 (8~64) winsize 57
6658 01:21:08.566513 [CA 2] Center 36 (8~64) winsize 57
6659 01:21:08.569851 [CA 3] Center 36 (8~64) winsize 57
6660 01:21:08.573480 [CA 4] Center 36 (8~64) winsize 57
6661 01:21:08.576484 [CA 5] Center 36 (8~64) winsize 57
6662 01:21:08.576574
6663 01:21:08.579657 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6664 01:21:08.579743
6665 01:21:08.583207 [CATrainingPosCal] consider 1 rank data
6666 01:21:08.586273 u2DelayCellTimex100 = 270/100 ps
6667 01:21:08.589661 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 01:21:08.592970 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 01:21:08.596129 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 01:21:08.599618 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 01:21:08.603193 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 01:21:08.609638 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 01:21:08.609746
6674 01:21:08.612825 CA PerBit enable=1, Macro0, CA PI delay=36
6675 01:21:08.612909
6676 01:21:08.616108 [CBTSetCACLKResult] CA Dly = 36
6677 01:21:08.616189 CS Dly: 1 (0~32)
6678 01:21:08.616251 ==
6679 01:21:08.619182 Dram Type= 6, Freq= 0, CH_1, rank 1
6680 01:21:08.622717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6681 01:21:08.625865 ==
6682 01:21:08.629676 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6683 01:21:08.635861 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6684 01:21:08.639715 [CA 0] Center 36 (8~64) winsize 57
6685 01:21:08.642937 [CA 1] Center 36 (8~64) winsize 57
6686 01:21:08.646036 [CA 2] Center 36 (8~64) winsize 57
6687 01:21:08.649532 [CA 3] Center 36 (8~64) winsize 57
6688 01:21:08.652717 [CA 4] Center 36 (8~64) winsize 57
6689 01:21:08.655900 [CA 5] Center 36 (8~64) winsize 57
6690 01:21:08.656027
6691 01:21:08.659171 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6692 01:21:08.659262
6693 01:21:08.663026 [CATrainingPosCal] consider 2 rank data
6694 01:21:08.666082 u2DelayCellTimex100 = 270/100 ps
6695 01:21:08.669625 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 01:21:08.672709 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 01:21:08.675902 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 01:21:08.679627 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 01:21:08.682737 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 01:21:08.685678 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 01:21:08.685792
6702 01:21:08.689480 CA PerBit enable=1, Macro0, CA PI delay=36
6703 01:21:08.689565
6704 01:21:08.692707 [CBTSetCACLKResult] CA Dly = 36
6705 01:21:08.696075 CS Dly: 1 (0~32)
6706 01:21:08.696164
6707 01:21:08.698993 ----->DramcWriteLeveling(PI) begin...
6708 01:21:08.699133 ==
6709 01:21:08.702434 Dram Type= 6, Freq= 0, CH_1, rank 0
6710 01:21:08.705729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6711 01:21:08.705836 ==
6712 01:21:08.708946 Write leveling (Byte 0): 40 => 8
6713 01:21:08.712163 Write leveling (Byte 1): 40 => 8
6714 01:21:08.715817 DramcWriteLeveling(PI) end<-----
6715 01:21:08.715912
6716 01:21:08.715977 ==
6717 01:21:08.719644 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 01:21:08.722227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 01:21:08.722337 ==
6720 01:21:08.725655 [Gating] SW mode calibration
6721 01:21:08.732333 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6722 01:21:08.739047 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6723 01:21:08.742236 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6724 01:21:08.748674 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6725 01:21:08.752338 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6726 01:21:08.755793 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6727 01:21:08.762234 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6728 01:21:08.765650 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6729 01:21:08.768707 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6730 01:21:08.772164 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6731 01:21:08.778794 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6732 01:21:08.782019 Total UI for P1: 0, mck2ui 16
6733 01:21:08.785231 best dqsien dly found for B0: ( 0, 14, 24)
6734 01:21:08.788958 Total UI for P1: 0, mck2ui 16
6735 01:21:08.792123 best dqsien dly found for B1: ( 0, 14, 24)
6736 01:21:08.795249 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6737 01:21:08.799097 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6738 01:21:08.799193
6739 01:21:08.802220 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6740 01:21:08.805516 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6741 01:21:08.808794 [Gating] SW calibration Done
6742 01:21:08.808887 ==
6743 01:21:08.812432 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 01:21:08.815573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 01:21:08.815666 ==
6746 01:21:08.818729 RX Vref Scan: 0
6747 01:21:08.818816
6748 01:21:08.821797 RX Vref 0 -> 0, step: 1
6749 01:21:08.821888
6750 01:21:08.821957 RX Delay -410 -> 252, step: 16
6751 01:21:08.828829 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6752 01:21:08.832128 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6753 01:21:08.835040 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6754 01:21:08.841870 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6755 01:21:08.845081 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6756 01:21:08.848634 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6757 01:21:08.851727 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6758 01:21:08.855061 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6759 01:21:08.861876 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6760 01:21:08.865111 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6761 01:21:08.868480 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6762 01:21:08.871817 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6763 01:21:08.878266 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6764 01:21:08.881703 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6765 01:21:08.884833 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6766 01:21:08.891915 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6767 01:21:08.892038 ==
6768 01:21:08.895166 Dram Type= 6, Freq= 0, CH_1, rank 0
6769 01:21:08.898316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6770 01:21:08.898435 ==
6771 01:21:08.898500 DQS Delay:
6772 01:21:08.901461 DQS0 = 35, DQS1 = 35
6773 01:21:08.901545 DQM Delay:
6774 01:21:08.904724 DQM0 = 17, DQM1 = 13
6775 01:21:08.904810 DQ Delay:
6776 01:21:08.907998 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6777 01:21:08.911816 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6778 01:21:08.914872 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6779 01:21:08.918274 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6780 01:21:08.918406
6781 01:21:08.918472
6782 01:21:08.918533 ==
6783 01:21:08.921655 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 01:21:08.924704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 01:21:08.924802 ==
6786 01:21:08.924875
6787 01:21:08.924936
6788 01:21:08.928512 TX Vref Scan disable
6789 01:21:08.931535 == TX Byte 0 ==
6790 01:21:08.934437 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6791 01:21:08.937954 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6792 01:21:08.941303 == TX Byte 1 ==
6793 01:21:08.944524 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6794 01:21:08.947905 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6795 01:21:08.948007 ==
6796 01:21:08.951061 Dram Type= 6, Freq= 0, CH_1, rank 0
6797 01:21:08.954936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 01:21:08.955083 ==
6799 01:21:08.955177
6800 01:21:08.955259
6801 01:21:08.958071 TX Vref Scan disable
6802 01:21:08.961232 == TX Byte 0 ==
6803 01:21:08.964933 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6804 01:21:08.968462 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6805 01:21:08.971348 == TX Byte 1 ==
6806 01:21:08.974628 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6807 01:21:08.977920 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6808 01:21:08.978027
6809 01:21:08.978092 [DATLAT]
6810 01:21:08.981611 Freq=400, CH1 RK0
6811 01:21:08.981704
6812 01:21:08.981769 DATLAT Default: 0xf
6813 01:21:08.984589 0, 0xFFFF, sum = 0
6814 01:21:08.984683 1, 0xFFFF, sum = 0
6815 01:21:08.987907 2, 0xFFFF, sum = 0
6816 01:21:08.988002 3, 0xFFFF, sum = 0
6817 01:21:08.991163 4, 0xFFFF, sum = 0
6818 01:21:08.994606 5, 0xFFFF, sum = 0
6819 01:21:08.994709 6, 0xFFFF, sum = 0
6820 01:21:08.997976 7, 0xFFFF, sum = 0
6821 01:21:08.998068 8, 0xFFFF, sum = 0
6822 01:21:09.001205 9, 0xFFFF, sum = 0
6823 01:21:09.001299 10, 0xFFFF, sum = 0
6824 01:21:09.004289 11, 0xFFFF, sum = 0
6825 01:21:09.004382 12, 0xFFFF, sum = 0
6826 01:21:09.007576 13, 0x0, sum = 1
6827 01:21:09.007666 14, 0x0, sum = 2
6828 01:21:09.011082 15, 0x0, sum = 3
6829 01:21:09.011177 16, 0x0, sum = 4
6830 01:21:09.014532 best_step = 14
6831 01:21:09.014633
6832 01:21:09.014697 ==
6833 01:21:09.018136 Dram Type= 6, Freq= 0, CH_1, rank 0
6834 01:21:09.021372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 01:21:09.021495 ==
6836 01:21:09.021588 RX Vref Scan: 1
6837 01:21:09.021674
6838 01:21:09.024523 RX Vref 0 -> 0, step: 1
6839 01:21:09.024611
6840 01:21:09.027438 RX Delay -311 -> 252, step: 8
6841 01:21:09.027523
6842 01:21:09.031375 Set Vref, RX VrefLevel [Byte0]: 54
6843 01:21:09.034612 [Byte1]: 48
6844 01:21:09.038590
6845 01:21:09.038695 Final RX Vref Byte 0 = 54 to rank0
6846 01:21:09.041400 Final RX Vref Byte 1 = 48 to rank0
6847 01:21:09.044974 Final RX Vref Byte 0 = 54 to rank1
6848 01:21:09.048101 Final RX Vref Byte 1 = 48 to rank1==
6849 01:21:09.051366 Dram Type= 6, Freq= 0, CH_1, rank 0
6850 01:21:09.058204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 01:21:09.058395 ==
6852 01:21:09.058467 DQS Delay:
6853 01:21:09.061381 DQS0 = 24, DQS1 = 32
6854 01:21:09.061470 DQM Delay:
6855 01:21:09.061535 DQM0 = 7, DQM1 = 12
6856 01:21:09.065217 DQ Delay:
6857 01:21:09.065308 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6858 01:21:09.068307 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6859 01:21:09.071357 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6860 01:21:09.075045 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
6861 01:21:09.075147
6862 01:21:09.075212
6863 01:21:09.084538 [DQSOSCAuto] RK0, (LSB)MR18= 0x87c0, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 392 ps
6864 01:21:09.088128 CH1 RK0: MR19=C0C, MR18=87C0
6865 01:21:09.094592 CH1_RK0: MR19=0xC0C, MR18=0x87C0, DQSOSC=386, MR23=63, INC=396, DEC=264
6866 01:21:09.094736 ==
6867 01:21:09.097850 Dram Type= 6, Freq= 0, CH_1, rank 1
6868 01:21:09.101037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 01:21:09.101136 ==
6870 01:21:09.105245 [Gating] SW mode calibration
6871 01:21:09.110905 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6872 01:21:09.114374 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6873 01:21:09.121029 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6874 01:21:09.124249 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6875 01:21:09.127893 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6876 01:21:09.134265 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6877 01:21:09.137782 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6878 01:21:09.140881 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6879 01:21:09.147724 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6880 01:21:09.151129 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6881 01:21:09.154143 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6882 01:21:09.157759 Total UI for P1: 0, mck2ui 16
6883 01:21:09.161282 best dqsien dly found for B0: ( 0, 14, 24)
6884 01:21:09.164535 Total UI for P1: 0, mck2ui 16
6885 01:21:09.167872 best dqsien dly found for B1: ( 0, 14, 24)
6886 01:21:09.171061 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6887 01:21:09.173964 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6888 01:21:09.177683
6889 01:21:09.180679 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6890 01:21:09.184236 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6891 01:21:09.187848 [Gating] SW calibration Done
6892 01:21:09.187952 ==
6893 01:21:09.190962 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 01:21:09.194037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 01:21:09.194134 ==
6896 01:21:09.194200 RX Vref Scan: 0
6897 01:21:09.194259
6898 01:21:09.197674 RX Vref 0 -> 0, step: 1
6899 01:21:09.197765
6900 01:21:09.200645 RX Delay -410 -> 252, step: 16
6901 01:21:09.203876 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6902 01:21:09.210703 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6903 01:21:09.214032 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6904 01:21:09.217363 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6905 01:21:09.220345 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6906 01:21:09.227429 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6907 01:21:09.230579 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6908 01:21:09.233722 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6909 01:21:09.237361 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6910 01:21:09.243844 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6911 01:21:09.247079 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6912 01:21:09.250582 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6913 01:21:09.253775 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6914 01:21:09.260727 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6915 01:21:09.263734 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6916 01:21:09.266995 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6917 01:21:09.267100 ==
6918 01:21:09.270376 Dram Type= 6, Freq= 0, CH_1, rank 1
6919 01:21:09.276903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6920 01:21:09.277036 ==
6921 01:21:09.277106 DQS Delay:
6922 01:21:09.279898 DQS0 = 35, DQS1 = 35
6923 01:21:09.279987 DQM Delay:
6924 01:21:09.280079 DQM0 = 18, DQM1 = 13
6925 01:21:09.283191 DQ Delay:
6926 01:21:09.286870 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6927 01:21:09.290115 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6928 01:21:09.290258 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6929 01:21:09.296852 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6930 01:21:09.296977
6931 01:21:09.297045
6932 01:21:09.297105 ==
6933 01:21:09.300234 Dram Type= 6, Freq= 0, CH_1, rank 1
6934 01:21:09.303173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6935 01:21:09.303264 ==
6936 01:21:09.303330
6937 01:21:09.303389
6938 01:21:09.306772 TX Vref Scan disable
6939 01:21:09.306859 == TX Byte 0 ==
6940 01:21:09.309742 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6941 01:21:09.316757 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6942 01:21:09.316882 == TX Byte 1 ==
6943 01:21:09.319826 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6944 01:21:09.326308 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6945 01:21:09.326446 ==
6946 01:21:09.329572 Dram Type= 6, Freq= 0, CH_1, rank 1
6947 01:21:09.333407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6948 01:21:09.333510 ==
6949 01:21:09.333576
6950 01:21:09.333635
6951 01:21:09.336493 TX Vref Scan disable
6952 01:21:09.336580 == TX Byte 0 ==
6953 01:21:09.342886 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6954 01:21:09.346524 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6955 01:21:09.346631 == TX Byte 1 ==
6956 01:21:09.349585 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6957 01:21:09.356326 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6958 01:21:09.356456
6959 01:21:09.356524 [DATLAT]
6960 01:21:09.360051 Freq=400, CH1 RK1
6961 01:21:09.360146
6962 01:21:09.360211 DATLAT Default: 0xe
6963 01:21:09.363225 0, 0xFFFF, sum = 0
6964 01:21:09.363314 1, 0xFFFF, sum = 0
6965 01:21:09.366388 2, 0xFFFF, sum = 0
6966 01:21:09.366475 3, 0xFFFF, sum = 0
6967 01:21:09.369472 4, 0xFFFF, sum = 0
6968 01:21:09.369562 5, 0xFFFF, sum = 0
6969 01:21:09.373216 6, 0xFFFF, sum = 0
6970 01:21:09.373312 7, 0xFFFF, sum = 0
6971 01:21:09.376296 8, 0xFFFF, sum = 0
6972 01:21:09.376390 9, 0xFFFF, sum = 0
6973 01:21:09.379271 10, 0xFFFF, sum = 0
6974 01:21:09.379363 11, 0xFFFF, sum = 0
6975 01:21:09.383063 12, 0xFFFF, sum = 0
6976 01:21:09.383192 13, 0x0, sum = 1
6977 01:21:09.386420 14, 0x0, sum = 2
6978 01:21:09.386517 15, 0x0, sum = 3
6979 01:21:09.389288 16, 0x0, sum = 4
6980 01:21:09.389378 best_step = 14
6981 01:21:09.389444
6982 01:21:09.389504 ==
6983 01:21:09.392987 Dram Type= 6, Freq= 0, CH_1, rank 1
6984 01:21:09.399552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6985 01:21:09.399668 ==
6986 01:21:09.399759 RX Vref Scan: 0
6987 01:21:09.399833
6988 01:21:09.402632 RX Vref 0 -> 0, step: 1
6989 01:21:09.402730
6990 01:21:09.406065 RX Delay -311 -> 252, step: 8
6991 01:21:09.412491 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6992 01:21:09.415957 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6993 01:21:09.419081 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6994 01:21:09.422675 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6995 01:21:09.429788 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6996 01:21:09.433015 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6997 01:21:09.435864 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6998 01:21:09.439096 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6999 01:21:09.445872 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
7000 01:21:09.448979 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7001 01:21:09.452673 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
7002 01:21:09.455933 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
7003 01:21:09.462605 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
7004 01:21:09.466163 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7005 01:21:09.469435 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7006 01:21:09.472543 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
7007 01:21:09.472648 ==
7008 01:21:09.476317 Dram Type= 6, Freq= 0, CH_1, rank 1
7009 01:21:09.482811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7010 01:21:09.482942 ==
7011 01:21:09.483013 DQS Delay:
7012 01:21:09.486096 DQS0 = 28, DQS1 = 32
7013 01:21:09.486210 DQM Delay:
7014 01:21:09.489655 DQM0 = 11, DQM1 = 11
7015 01:21:09.489748 DQ Delay:
7016 01:21:09.492662 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7017 01:21:09.495703 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
7018 01:21:09.495799 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
7019 01:21:09.502876 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
7020 01:21:09.503004
7021 01:21:09.503069
7022 01:21:09.509163 [DQSOSCAuto] RK1, (LSB)MR18= 0xbd4f, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 386 ps
7023 01:21:09.512763 CH1 RK1: MR19=C0C, MR18=BD4F
7024 01:21:09.519318 CH1_RK1: MR19=0xC0C, MR18=0xBD4F, DQSOSC=386, MR23=63, INC=396, DEC=264
7025 01:21:09.522282 [RxdqsGatingPostProcess] freq 400
7026 01:21:09.525907 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7027 01:21:09.529033 best DQS0 dly(2T, 0.5T) = (0, 10)
7028 01:21:09.532395 best DQS1 dly(2T, 0.5T) = (0, 10)
7029 01:21:09.535618 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7030 01:21:09.539261 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7031 01:21:09.542087 best DQS0 dly(2T, 0.5T) = (0, 10)
7032 01:21:09.545245 best DQS1 dly(2T, 0.5T) = (0, 10)
7033 01:21:09.549118 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7034 01:21:09.552113 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7035 01:21:09.555418 Pre-setting of DQS Precalculation
7036 01:21:09.558960 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7037 01:21:09.568801 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7038 01:21:09.575628 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7039 01:21:09.575765
7040 01:21:09.575836
7041 01:21:09.578692 [Calibration Summary] 800 Mbps
7042 01:21:09.578874 CH 0, Rank 0
7043 01:21:09.581892 SW Impedance : PASS
7044 01:21:09.582057 DUTY Scan : NO K
7045 01:21:09.585805 ZQ Calibration : PASS
7046 01:21:09.589038 Jitter Meter : NO K
7047 01:21:09.589209 CBT Training : PASS
7048 01:21:09.592215 Write leveling : PASS
7049 01:21:09.595263 RX DQS gating : PASS
7050 01:21:09.595425 RX DQ/DQS(RDDQC) : PASS
7051 01:21:09.598798 TX DQ/DQS : PASS
7052 01:21:09.598961 RX DATLAT : PASS
7053 01:21:09.601861 RX DQ/DQS(Engine): PASS
7054 01:21:09.605859 TX OE : NO K
7055 01:21:09.606044 All Pass.
7056 01:21:09.606193
7057 01:21:09.606356 CH 0, Rank 1
7058 01:21:09.608900 SW Impedance : PASS
7059 01:21:09.612078 DUTY Scan : NO K
7060 01:21:09.612248 ZQ Calibration : PASS
7061 01:21:09.615183 Jitter Meter : NO K
7062 01:21:09.618866 CBT Training : PASS
7063 01:21:09.619042 Write leveling : NO K
7064 01:21:09.621812 RX DQS gating : PASS
7065 01:21:09.625271 RX DQ/DQS(RDDQC) : PASS
7066 01:21:09.625374 TX DQ/DQS : PASS
7067 01:21:09.628738 RX DATLAT : PASS
7068 01:21:09.632088 RX DQ/DQS(Engine): PASS
7069 01:21:09.632193 TX OE : NO K
7070 01:21:09.635218 All Pass.
7071 01:21:09.635309
7072 01:21:09.635373 CH 1, Rank 0
7073 01:21:09.638450 SW Impedance : PASS
7074 01:21:09.638538 DUTY Scan : NO K
7075 01:21:09.641724 ZQ Calibration : PASS
7076 01:21:09.645200 Jitter Meter : NO K
7077 01:21:09.645298 CBT Training : PASS
7078 01:21:09.648656 Write leveling : PASS
7079 01:21:09.651726 RX DQS gating : PASS
7080 01:21:09.651818 RX DQ/DQS(RDDQC) : PASS
7081 01:21:09.655416 TX DQ/DQS : PASS
7082 01:21:09.655554 RX DATLAT : PASS
7083 01:21:09.658658 RX DQ/DQS(Engine): PASS
7084 01:21:09.661771 TX OE : NO K
7085 01:21:09.661867 All Pass.
7086 01:21:09.661931
7087 01:21:09.665359 CH 1, Rank 1
7088 01:21:09.665449 SW Impedance : PASS
7089 01:21:09.668243 DUTY Scan : NO K
7090 01:21:09.668331 ZQ Calibration : PASS
7091 01:21:09.671825 Jitter Meter : NO K
7092 01:21:09.675109 CBT Training : PASS
7093 01:21:09.675203 Write leveling : NO K
7094 01:21:09.678195 RX DQS gating : PASS
7095 01:21:09.681369 RX DQ/DQS(RDDQC) : PASS
7096 01:21:09.681462 TX DQ/DQS : PASS
7097 01:21:09.685440 RX DATLAT : PASS
7098 01:21:09.688133 RX DQ/DQS(Engine): PASS
7099 01:21:09.688224 TX OE : NO K
7100 01:21:09.691383 All Pass.
7101 01:21:09.691469
7102 01:21:09.691534 DramC Write-DBI off
7103 01:21:09.694839 PER_BANK_REFRESH: Hybrid Mode
7104 01:21:09.694925 TX_TRACKING: ON
7105 01:21:09.704892 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7106 01:21:09.708039 [FAST_K] Save calibration result to emmc
7107 01:21:09.711181 dramc_set_vcore_voltage set vcore to 725000
7108 01:21:09.714584 Read voltage for 1600, 0
7109 01:21:09.714688 Vio18 = 0
7110 01:21:09.717664 Vcore = 725000
7111 01:21:09.717749 Vdram = 0
7112 01:21:09.717813 Vddq = 0
7113 01:21:09.721145 Vmddr = 0
7114 01:21:09.724931 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7115 01:21:09.731050 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7116 01:21:09.731204 MEM_TYPE=3, freq_sel=13
7117 01:21:09.734375 sv_algorithm_assistance_LP4_3733
7118 01:21:09.741707 ============ PULL DRAM RESETB DOWN ============
7119 01:21:09.744884 ========== PULL DRAM RESETB DOWN end =========
7120 01:21:09.747908 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7121 01:21:09.751117 ===================================
7122 01:21:09.754469 LPDDR4 DRAM CONFIGURATION
7123 01:21:09.757689 ===================================
7124 01:21:09.757797 EX_ROW_EN[0] = 0x0
7125 01:21:09.761240 EX_ROW_EN[1] = 0x0
7126 01:21:09.764539 LP4Y_EN = 0x0
7127 01:21:09.764641 WORK_FSP = 0x1
7128 01:21:09.767710 WL = 0x5
7129 01:21:09.767797 RL = 0x5
7130 01:21:09.771019 BL = 0x2
7131 01:21:09.771104 RPST = 0x0
7132 01:21:09.774530 RD_PRE = 0x0
7133 01:21:09.774615 WR_PRE = 0x1
7134 01:21:09.777610 WR_PST = 0x1
7135 01:21:09.777696 DBI_WR = 0x0
7136 01:21:09.781037 DBI_RD = 0x0
7137 01:21:09.781123 OTF = 0x1
7138 01:21:09.783958 ===================================
7139 01:21:09.787548 ===================================
7140 01:21:09.791100 ANA top config
7141 01:21:09.794215 ===================================
7142 01:21:09.794369 DLL_ASYNC_EN = 0
7143 01:21:09.797442 ALL_SLAVE_EN = 0
7144 01:21:09.800564 NEW_RANK_MODE = 1
7145 01:21:09.804144 DLL_IDLE_MODE = 1
7146 01:21:09.807510 LP45_APHY_COMB_EN = 1
7147 01:21:09.807611 TX_ODT_DIS = 0
7148 01:21:09.810690 NEW_8X_MODE = 1
7149 01:21:09.814181 ===================================
7150 01:21:09.817666 ===================================
7151 01:21:09.821021 data_rate = 3200
7152 01:21:09.823941 CKR = 1
7153 01:21:09.827516 DQ_P2S_RATIO = 8
7154 01:21:09.830732 ===================================
7155 01:21:09.830834 CA_P2S_RATIO = 8
7156 01:21:09.834191 DQ_CA_OPEN = 0
7157 01:21:09.837602 DQ_SEMI_OPEN = 0
7158 01:21:09.840635 CA_SEMI_OPEN = 0
7159 01:21:09.844213 CA_FULL_RATE = 0
7160 01:21:09.847194 DQ_CKDIV4_EN = 0
7161 01:21:09.847288 CA_CKDIV4_EN = 0
7162 01:21:09.850470 CA_PREDIV_EN = 0
7163 01:21:09.854230 PH8_DLY = 12
7164 01:21:09.857231 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7165 01:21:09.860947 DQ_AAMCK_DIV = 4
7166 01:21:09.864048 CA_AAMCK_DIV = 4
7167 01:21:09.864144 CA_ADMCK_DIV = 4
7168 01:21:09.867268 DQ_TRACK_CA_EN = 0
7169 01:21:09.870514 CA_PICK = 1600
7170 01:21:09.873775 CA_MCKIO = 1600
7171 01:21:09.876928 MCKIO_SEMI = 0
7172 01:21:09.880703 PLL_FREQ = 3068
7173 01:21:09.883794 DQ_UI_PI_RATIO = 32
7174 01:21:09.886821 CA_UI_PI_RATIO = 0
7175 01:21:09.890708 ===================================
7176 01:21:09.893666 ===================================
7177 01:21:09.893761 memory_type:LPDDR4
7178 01:21:09.897309 GP_NUM : 10
7179 01:21:09.900207 SRAM_EN : 1
7180 01:21:09.900301 MD32_EN : 0
7181 01:21:09.903448 ===================================
7182 01:21:09.907289 [ANA_INIT] >>>>>>>>>>>>>>
7183 01:21:09.910203 <<<<<< [CONFIGURE PHASE]: ANA_TX
7184 01:21:09.913377 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7185 01:21:09.917065 ===================================
7186 01:21:09.920268 data_rate = 3200,PCW = 0X7600
7187 01:21:09.923542 ===================================
7188 01:21:09.926625 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7189 01:21:09.930295 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7190 01:21:09.936865 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7191 01:21:09.939926 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7192 01:21:09.943619 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7193 01:21:09.946705 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7194 01:21:09.949706 [ANA_INIT] flow start
7195 01:21:09.953145 [ANA_INIT] PLL >>>>>>>>
7196 01:21:09.953317 [ANA_INIT] PLL <<<<<<<<
7197 01:21:09.956962 [ANA_INIT] MIDPI >>>>>>>>
7198 01:21:09.959538 [ANA_INIT] MIDPI <<<<<<<<
7199 01:21:09.963055 [ANA_INIT] DLL >>>>>>>>
7200 01:21:09.963152 [ANA_INIT] DLL <<<<<<<<
7201 01:21:09.966347 [ANA_INIT] flow end
7202 01:21:09.969892 ============ LP4 DIFF to SE enter ============
7203 01:21:09.973196 ============ LP4 DIFF to SE exit ============
7204 01:21:09.976229 [ANA_INIT] <<<<<<<<<<<<<
7205 01:21:09.980185 [Flow] Enable top DCM control >>>>>
7206 01:21:09.983277 [Flow] Enable top DCM control <<<<<
7207 01:21:09.986555 Enable DLL master slave shuffle
7208 01:21:09.992758 ==============================================================
7209 01:21:09.992879 Gating Mode config
7210 01:21:09.999816 ==============================================================
7211 01:21:09.999941 Config description:
7212 01:21:10.009472 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7213 01:21:10.015870 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7214 01:21:10.022915 SELPH_MODE 0: By rank 1: By Phase
7215 01:21:10.026310 ==============================================================
7216 01:21:10.029505 GAT_TRACK_EN = 1
7217 01:21:10.032895 RX_GATING_MODE = 2
7218 01:21:10.035948 RX_GATING_TRACK_MODE = 2
7219 01:21:10.039184 SELPH_MODE = 1
7220 01:21:10.042800 PICG_EARLY_EN = 1
7221 01:21:10.046172 VALID_LAT_VALUE = 1
7222 01:21:10.049702 ==============================================================
7223 01:21:10.053072 Enter into Gating configuration >>>>
7224 01:21:10.056370 Exit from Gating configuration <<<<
7225 01:21:10.059582 Enter into DVFS_PRE_config >>>>>
7226 01:21:10.073182 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7227 01:21:10.076063 Exit from DVFS_PRE_config <<<<<
7228 01:21:10.079511 Enter into PICG configuration >>>>
7229 01:21:10.079626 Exit from PICG configuration <<<<
7230 01:21:10.083089 [RX_INPUT] configuration >>>>>
7231 01:21:10.086558 [RX_INPUT] configuration <<<<<
7232 01:21:10.092696 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7233 01:21:10.096046 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7234 01:21:10.102264 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7235 01:21:10.108823 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7236 01:21:10.115972 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7237 01:21:10.122103 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7238 01:21:10.125855 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7239 01:21:10.129031 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7240 01:21:10.135382 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7241 01:21:10.138737 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7242 01:21:10.142570 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7243 01:21:10.145758 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7244 01:21:10.148951 ===================================
7245 01:21:10.152144 LPDDR4 DRAM CONFIGURATION
7246 01:21:10.155313 ===================================
7247 01:21:10.158881 EX_ROW_EN[0] = 0x0
7248 01:21:10.158989 EX_ROW_EN[1] = 0x0
7249 01:21:10.162282 LP4Y_EN = 0x0
7250 01:21:10.162396 WORK_FSP = 0x1
7251 01:21:10.165929 WL = 0x5
7252 01:21:10.166016 RL = 0x5
7253 01:21:10.169011 BL = 0x2
7254 01:21:10.169099 RPST = 0x0
7255 01:21:10.172182 RD_PRE = 0x0
7256 01:21:10.172270 WR_PRE = 0x1
7257 01:21:10.175270 WR_PST = 0x1
7258 01:21:10.175356 DBI_WR = 0x0
7259 01:21:10.178489 DBI_RD = 0x0
7260 01:21:10.182456 OTF = 0x1
7261 01:21:10.182550 ===================================
7262 01:21:10.188796 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7263 01:21:10.192297 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7264 01:21:10.195271 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7265 01:21:10.198495 ===================================
7266 01:21:10.201812 LPDDR4 DRAM CONFIGURATION
7267 01:21:10.205322 ===================================
7268 01:21:10.208553 EX_ROW_EN[0] = 0x10
7269 01:21:10.208646 EX_ROW_EN[1] = 0x0
7270 01:21:10.211762 LP4Y_EN = 0x0
7271 01:21:10.211848 WORK_FSP = 0x1
7272 01:21:10.215238 WL = 0x5
7273 01:21:10.215323 RL = 0x5
7274 01:21:10.218501 BL = 0x2
7275 01:21:10.218586 RPST = 0x0
7276 01:21:10.222031 RD_PRE = 0x0
7277 01:21:10.222116 WR_PRE = 0x1
7278 01:21:10.225034 WR_PST = 0x1
7279 01:21:10.225123 DBI_WR = 0x0
7280 01:21:10.228660 DBI_RD = 0x0
7281 01:21:10.228750 OTF = 0x1
7282 01:21:10.231566 ===================================
7283 01:21:10.238159 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7284 01:21:10.238274 ==
7285 01:21:10.242199 Dram Type= 6, Freq= 0, CH_0, rank 0
7286 01:21:10.248616 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7287 01:21:10.248740 ==
7288 01:21:10.248807 [Duty_Offset_Calibration]
7289 01:21:10.251846 B0:2 B1:1 CA:1
7290 01:21:10.251957
7291 01:21:10.255018 [DutyScan_Calibration_Flow] k_type=0
7292 01:21:10.264490
7293 01:21:10.264632 ==CLK 0==
7294 01:21:10.267394 Final CLK duty delay cell = 0
7295 01:21:10.270896 [0] MAX Duty = 5156%(X100), DQS PI = 22
7296 01:21:10.274488 [0] MIN Duty = 4876%(X100), DQS PI = 48
7297 01:21:10.277819 [0] AVG Duty = 5016%(X100)
7298 01:21:10.277921
7299 01:21:10.280713 CH0 CLK Duty spec in!! Max-Min= 280%
7300 01:21:10.284043 [DutyScan_Calibration_Flow] ====Done====
7301 01:21:10.284142
7302 01:21:10.287197 [DutyScan_Calibration_Flow] k_type=1
7303 01:21:10.303827
7304 01:21:10.303966 ==DQS 0 ==
7305 01:21:10.306960 Final DQS duty delay cell = -4
7306 01:21:10.310129 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7307 01:21:10.313397 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7308 01:21:10.316589 [-4] AVG Duty = 4891%(X100)
7309 01:21:10.316683
7310 01:21:10.316756 ==DQS 1 ==
7311 01:21:10.320298 Final DQS duty delay cell = 0
7312 01:21:10.323683 [0] MAX Duty = 5187%(X100), DQS PI = 10
7313 01:21:10.326700 [0] MIN Duty = 5031%(X100), DQS PI = 52
7314 01:21:10.329908 [0] AVG Duty = 5109%(X100)
7315 01:21:10.330029
7316 01:21:10.333382 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7317 01:21:10.333468
7318 01:21:10.336821 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7319 01:21:10.340283 [DutyScan_Calibration_Flow] ====Done====
7320 01:21:10.340376
7321 01:21:10.343306 [DutyScan_Calibration_Flow] k_type=3
7322 01:21:10.360242
7323 01:21:10.360395 ==DQM 0 ==
7324 01:21:10.363511 Final DQM duty delay cell = 0
7325 01:21:10.366873 [0] MAX Duty = 5218%(X100), DQS PI = 34
7326 01:21:10.369867 [0] MIN Duty = 4907%(X100), DQS PI = 0
7327 01:21:10.373406 [0] AVG Duty = 5062%(X100)
7328 01:21:10.373534
7329 01:21:10.373678 ==DQM 1 ==
7330 01:21:10.376887 Final DQM duty delay cell = -4
7331 01:21:10.380004 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7332 01:21:10.383133 [-4] MIN Duty = 4813%(X100), DQS PI = 12
7333 01:21:10.386817 [-4] AVG Duty = 4891%(X100)
7334 01:21:10.386937
7335 01:21:10.389710 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7336 01:21:10.389819
7337 01:21:10.393305 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7338 01:21:10.396713 [DutyScan_Calibration_Flow] ====Done====
7339 01:21:10.396835
7340 01:21:10.399935 [DutyScan_Calibration_Flow] k_type=2
7341 01:21:10.417550
7342 01:21:10.417738 ==DQ 0 ==
7343 01:21:10.421429 Final DQ duty delay cell = 0
7344 01:21:10.424667 [0] MAX Duty = 5062%(X100), DQS PI = 26
7345 01:21:10.427850 [0] MIN Duty = 4907%(X100), DQS PI = 0
7346 01:21:10.427966 [0] AVG Duty = 4984%(X100)
7347 01:21:10.428060
7348 01:21:10.431172 ==DQ 1 ==
7349 01:21:10.434203 Final DQ duty delay cell = 0
7350 01:21:10.437904 [0] MAX Duty = 5125%(X100), DQS PI = 6
7351 01:21:10.440934 [0] MIN Duty = 4938%(X100), DQS PI = 36
7352 01:21:10.441055 [0] AVG Duty = 5031%(X100)
7353 01:21:10.441147
7354 01:21:10.444619 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7355 01:21:10.444731
7356 01:21:10.447805 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7357 01:21:10.454236 [DutyScan_Calibration_Flow] ====Done====
7358 01:21:10.454416 ==
7359 01:21:10.457362 Dram Type= 6, Freq= 0, CH_1, rank 0
7360 01:21:10.460913 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7361 01:21:10.461059 ==
7362 01:21:10.464072 [Duty_Offset_Calibration]
7363 01:21:10.464186 B0:1 B1:0 CA:0
7364 01:21:10.464286
7365 01:21:10.467614 [DutyScan_Calibration_Flow] k_type=0
7366 01:21:10.477232
7367 01:21:10.477405 ==CLK 0==
7368 01:21:10.480753 Final CLK duty delay cell = -4
7369 01:21:10.483709 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7370 01:21:10.486800 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7371 01:21:10.489929 [-4] AVG Duty = 4906%(X100)
7372 01:21:10.490049
7373 01:21:10.493396 CH1 CLK Duty spec in!! Max-Min= 125%
7374 01:21:10.497196 [DutyScan_Calibration_Flow] ====Done====
7375 01:21:10.497327
7376 01:21:10.500176 [DutyScan_Calibration_Flow] k_type=1
7377 01:21:10.517438
7378 01:21:10.517627 ==DQS 0 ==
7379 01:21:10.520232 Final DQS duty delay cell = 0
7380 01:21:10.523997 [0] MAX Duty = 5094%(X100), DQS PI = 32
7381 01:21:10.527244 [0] MIN Duty = 4844%(X100), DQS PI = 46
7382 01:21:10.530501 [0] AVG Duty = 4969%(X100)
7383 01:21:10.530628
7384 01:21:10.530727 ==DQS 1 ==
7385 01:21:10.533607 Final DQS duty delay cell = 0
7386 01:21:10.536884 [0] MAX Duty = 5249%(X100), DQS PI = 16
7387 01:21:10.540583 [0] MIN Duty = 4938%(X100), DQS PI = 8
7388 01:21:10.543787 [0] AVG Duty = 5093%(X100)
7389 01:21:10.543907
7390 01:21:10.546577 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7391 01:21:10.546694
7392 01:21:10.550243 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7393 01:21:10.553442 [DutyScan_Calibration_Flow] ====Done====
7394 01:21:10.553561
7395 01:21:10.556621 [DutyScan_Calibration_Flow] k_type=3
7396 01:21:10.574204
7397 01:21:10.574440 ==DQM 0 ==
7398 01:21:10.577075 Final DQM duty delay cell = 0
7399 01:21:10.580169 [0] MAX Duty = 5218%(X100), DQS PI = 18
7400 01:21:10.583990 [0] MIN Duty = 4969%(X100), DQS PI = 48
7401 01:21:10.587102 [0] AVG Duty = 5093%(X100)
7402 01:21:10.587225
7403 01:21:10.587324 ==DQM 1 ==
7404 01:21:10.590245 Final DQM duty delay cell = 0
7405 01:21:10.593630 [0] MAX Duty = 5093%(X100), DQS PI = 16
7406 01:21:10.596898 [0] MIN Duty = 4907%(X100), DQS PI = 52
7407 01:21:10.600229 [0] AVG Duty = 5000%(X100)
7408 01:21:10.600351
7409 01:21:10.603960 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7410 01:21:10.604082
7411 01:21:10.607041 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7412 01:21:10.610679 [DutyScan_Calibration_Flow] ====Done====
7413 01:21:10.610803
7414 01:21:10.613559 [DutyScan_Calibration_Flow] k_type=2
7415 01:21:10.629918
7416 01:21:10.630111 ==DQ 0 ==
7417 01:21:10.633330 Final DQ duty delay cell = -4
7418 01:21:10.636709 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7419 01:21:10.639829 [-4] MIN Duty = 4844%(X100), DQS PI = 46
7420 01:21:10.643680 [-4] AVG Duty = 4937%(X100)
7421 01:21:10.643812
7422 01:21:10.643910 ==DQ 1 ==
7423 01:21:10.646901 Final DQ duty delay cell = 0
7424 01:21:10.649988 [0] MAX Duty = 5124%(X100), DQS PI = 18
7425 01:21:10.653422 [0] MIN Duty = 4938%(X100), DQS PI = 8
7426 01:21:10.656494 [0] AVG Duty = 5031%(X100)
7427 01:21:10.656621
7428 01:21:10.660332 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7429 01:21:10.660465
7430 01:21:10.663621 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7431 01:21:10.666507 [DutyScan_Calibration_Flow] ====Done====
7432 01:21:10.669798 nWR fixed to 30
7433 01:21:10.669916 [ModeRegInit_LP4] CH0 RK0
7434 01:21:10.673358 [ModeRegInit_LP4] CH0 RK1
7435 01:21:10.676625 [ModeRegInit_LP4] CH1 RK0
7436 01:21:10.679757 [ModeRegInit_LP4] CH1 RK1
7437 01:21:10.679892 match AC timing 5
7438 01:21:10.686642 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7439 01:21:10.689768 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7440 01:21:10.693027 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7441 01:21:10.699668 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7442 01:21:10.703273 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7443 01:21:10.703403 [MiockJmeterHQA]
7444 01:21:10.703495
7445 01:21:10.706270 [DramcMiockJmeter] u1RxGatingPI = 0
7446 01:21:10.710017 0 : 4252, 4027
7447 01:21:10.710141 4 : 4362, 4137
7448 01:21:10.713583 8 : 4255, 4029
7449 01:21:10.713702 12 : 4252, 4026
7450 01:21:10.713800 16 : 4253, 4026
7451 01:21:10.716181 20 : 4252, 4027
7452 01:21:10.716291 24 : 4363, 4137
7453 01:21:10.719677 28 : 4252, 4027
7454 01:21:10.719791 32 : 4363, 4137
7455 01:21:10.723235 36 : 4252, 4027
7456 01:21:10.723350 40 : 4252, 4027
7457 01:21:10.726619 44 : 4252, 4027
7458 01:21:10.726732 48 : 4254, 4029
7459 01:21:10.726825 52 : 4252, 4027
7460 01:21:10.729786 56 : 4250, 4027
7461 01:21:10.729895 60 : 4363, 4140
7462 01:21:10.732963 64 : 4250, 4026
7463 01:21:10.733078 68 : 4252, 4030
7464 01:21:10.736019 72 : 4250, 4026
7465 01:21:10.736130 76 : 4361, 4137
7466 01:21:10.739434 80 : 4250, 4027
7467 01:21:10.739546 84 : 4361, 4136
7468 01:21:10.739640 88 : 4250, 105
7469 01:21:10.742695 92 : 4253, 0
7470 01:21:10.742806 96 : 4253, 0
7471 01:21:10.742900 100 : 4253, 0
7472 01:21:10.746265 104 : 4250, 0
7473 01:21:10.746419 108 : 4361, 0
7474 01:21:10.749664 112 : 4361, 0
7475 01:21:10.749775 116 : 4250, 0
7476 01:21:10.749869 120 : 4250, 0
7477 01:21:10.752957 124 : 4250, 0
7478 01:21:10.753068 128 : 4252, 0
7479 01:21:10.755936 132 : 4250, 0
7480 01:21:10.756046 136 : 4250, 0
7481 01:21:10.756140 140 : 4252, 0
7482 01:21:10.759673 144 : 4250, 0
7483 01:21:10.759796 148 : 4250, 0
7484 01:21:10.763239 152 : 4252, 0
7485 01:21:10.763378 156 : 4250, 0
7486 01:21:10.763476 160 : 4360, 0
7487 01:21:10.766009 164 : 4249, 0
7488 01:21:10.766128 168 : 4250, 0
7489 01:21:10.766226 172 : 4250, 0
7490 01:21:10.769950 176 : 4363, 0
7491 01:21:10.770066 180 : 4250, 0
7492 01:21:10.773017 184 : 4253, 0
7493 01:21:10.773127 188 : 4250, 0
7494 01:21:10.773222 192 : 4252, 0
7495 01:21:10.776300 196 : 4250, 0
7496 01:21:10.776408 200 : 4250, 0
7497 01:21:10.780414 204 : 4252, 1191
7498 01:21:10.780537 208 : 4250, 3932
7499 01:21:10.782683 212 : 4250, 4026
7500 01:21:10.782792 216 : 4361, 4137
7501 01:21:10.786033 220 : 4250, 4027
7502 01:21:10.786153 224 : 4250, 4027
7503 01:21:10.786247 228 : 4361, 4137
7504 01:21:10.789551 232 : 4361, 4137
7505 01:21:10.789667 236 : 4250, 4027
7506 01:21:10.793240 240 : 4360, 4138
7507 01:21:10.793355 244 : 4361, 4137
7508 01:21:10.796309 248 : 4253, 4029
7509 01:21:10.796421 252 : 4250, 4027
7510 01:21:10.799445 256 : 4252, 4030
7511 01:21:10.799557 260 : 4250, 4027
7512 01:21:10.802571 264 : 4250, 4026
7513 01:21:10.802681 268 : 4250, 4027
7514 01:21:10.806409 272 : 4250, 4027
7515 01:21:10.806519 276 : 4250, 4027
7516 01:21:10.806612 280 : 4361, 4137
7517 01:21:10.809559 284 : 4361, 4137
7518 01:21:10.809666 288 : 4250, 4027
7519 01:21:10.813069 292 : 4363, 4140
7520 01:21:10.813185 296 : 4252, 4029
7521 01:21:10.815968 300 : 4250, 4026
7522 01:21:10.816080 304 : 4250, 4027
7523 01:21:10.819189 308 : 4252, 3958
7524 01:21:10.819301 312 : 4250, 2039
7525 01:21:10.819394
7526 01:21:10.823002 MIOCK jitter meter ch=0
7527 01:21:10.823114
7528 01:21:10.826036 1T = (312-88) = 224 dly cells
7529 01:21:10.832757 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7530 01:21:10.832904 ==
7531 01:21:10.836131 Dram Type= 6, Freq= 0, CH_0, rank 0
7532 01:21:10.839369 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 01:21:10.839487 ==
7534 01:21:10.846163 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7535 01:21:10.849771 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7536 01:21:10.852580 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7537 01:21:10.859470 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7538 01:21:10.867942 [CA 0] Center 42 (12~73) winsize 62
7539 01:21:10.870910 [CA 1] Center 42 (12~73) winsize 62
7540 01:21:10.874403 [CA 2] Center 38 (8~68) winsize 61
7541 01:21:10.877682 [CA 3] Center 37 (8~67) winsize 60
7542 01:21:10.881204 [CA 4] Center 36 (6~66) winsize 61
7543 01:21:10.884225 [CA 5] Center 35 (6~64) winsize 59
7544 01:21:10.884354
7545 01:21:10.887855 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7546 01:21:10.887971
7547 01:21:10.890851 [CATrainingPosCal] consider 1 rank data
7548 01:21:10.894209 u2DelayCellTimex100 = 290/100 ps
7549 01:21:10.897250 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7550 01:21:10.903921 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7551 01:21:10.907478 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7552 01:21:10.910664 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7553 01:21:10.913830 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7554 01:21:10.917413 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7555 01:21:10.917532
7556 01:21:10.920661 CA PerBit enable=1, Macro0, CA PI delay=35
7557 01:21:10.920774
7558 01:21:10.924659 [CBTSetCACLKResult] CA Dly = 35
7559 01:21:10.927544 CS Dly: 9 (0~40)
7560 01:21:10.930545 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7561 01:21:10.934076 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7562 01:21:10.934212 ==
7563 01:21:10.937680 Dram Type= 6, Freq= 0, CH_0, rank 1
7564 01:21:10.940266 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7565 01:21:10.944044 ==
7566 01:21:10.946736 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7567 01:21:10.950311 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7568 01:21:10.957059 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7569 01:21:10.963479 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7570 01:21:10.970926 [CA 0] Center 42 (12~73) winsize 62
7571 01:21:10.974290 [CA 1] Center 42 (12~73) winsize 62
7572 01:21:10.977397 [CA 2] Center 38 (8~68) winsize 61
7573 01:21:10.981329 [CA 3] Center 37 (8~67) winsize 60
7574 01:21:10.984341 [CA 4] Center 36 (6~66) winsize 61
7575 01:21:10.987401 [CA 5] Center 35 (5~65) winsize 61
7576 01:21:10.987520
7577 01:21:10.991301 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7578 01:21:10.991425
7579 01:21:10.994199 [CATrainingPosCal] consider 2 rank data
7580 01:21:10.997477 u2DelayCellTimex100 = 290/100 ps
7581 01:21:11.001320 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7582 01:21:11.007517 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7583 01:21:11.011049 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7584 01:21:11.014232 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7585 01:21:11.017716 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7586 01:21:11.020666 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7587 01:21:11.020787
7588 01:21:11.024428 CA PerBit enable=1, Macro0, CA PI delay=35
7589 01:21:11.024542
7590 01:21:11.027295 [CBTSetCACLKResult] CA Dly = 35
7591 01:21:11.031053 CS Dly: 10 (0~42)
7592 01:21:11.034272 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7593 01:21:11.037382 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7594 01:21:11.037501
7595 01:21:11.040984 ----->DramcWriteLeveling(PI) begin...
7596 01:21:11.041097 ==
7597 01:21:11.044242 Dram Type= 6, Freq= 0, CH_0, rank 0
7598 01:21:11.050462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7599 01:21:11.050601 ==
7600 01:21:11.054218 Write leveling (Byte 0): 36 => 36
7601 01:21:11.054370 Write leveling (Byte 1): 27 => 27
7602 01:21:11.057336 DramcWriteLeveling(PI) end<-----
7603 01:21:11.057443
7604 01:21:11.057533 ==
7605 01:21:11.060325 Dram Type= 6, Freq= 0, CH_0, rank 0
7606 01:21:11.066958 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7607 01:21:11.067104 ==
7608 01:21:11.070741 [Gating] SW mode calibration
7609 01:21:11.076827 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7610 01:21:11.080502 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7611 01:21:11.086790 1 4 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7612 01:21:11.090155 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7613 01:21:11.093875 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7614 01:21:11.100302 1 4 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (1 1)
7615 01:21:11.103569 1 4 16 | B1->B0 | 2322 3635 | 1 1 | (0 0) (0 0)
7616 01:21:11.106783 1 4 20 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7617 01:21:11.113422 1 4 24 | B1->B0 | 3434 3a39 | 1 1 | (1 1) (1 1)
7618 01:21:11.116768 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
7619 01:21:11.119951 1 5 0 | B1->B0 | 3434 3939 | 1 1 | (1 1) (1 1)
7620 01:21:11.126723 1 5 4 | B1->B0 | 3434 3838 | 1 1 | (1 1) (1 1)
7621 01:21:11.129890 1 5 8 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 0)
7622 01:21:11.132986 1 5 12 | B1->B0 | 3434 2625 | 1 1 | (1 1) (1 0)
7623 01:21:11.140108 1 5 16 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 0)
7624 01:21:11.143635 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7625 01:21:11.146909 1 5 24 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7626 01:21:11.153159 1 5 28 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7627 01:21:11.156562 1 6 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7628 01:21:11.159839 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7629 01:21:11.166158 1 6 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7630 01:21:11.169967 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7631 01:21:11.172996 1 6 16 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
7632 01:21:11.179570 1 6 20 | B1->B0 | 4444 4645 | 0 1 | (0 0) (0 0)
7633 01:21:11.183183 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7634 01:21:11.186152 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7635 01:21:11.189650 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 01:21:11.196538 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7637 01:21:11.199729 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7638 01:21:11.202837 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7639 01:21:11.209896 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7640 01:21:11.212571 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7641 01:21:11.216295 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 01:21:11.222455 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 01:21:11.226153 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 01:21:11.229153 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 01:21:11.235786 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 01:21:11.239591 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 01:21:11.242703 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 01:21:11.248969 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 01:21:11.252551 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 01:21:11.255755 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 01:21:11.262133 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 01:21:11.266090 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 01:21:11.268845 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 01:21:11.275671 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7655 01:21:11.275794 Total UI for P1: 0, mck2ui 16
7656 01:21:11.282331 best dqsien dly found for B0: ( 1, 9, 10)
7657 01:21:11.285863 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7658 01:21:11.289219 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7659 01:21:11.292443 Total UI for P1: 0, mck2ui 16
7660 01:21:11.295573 best dqsien dly found for B1: ( 1, 9, 18)
7661 01:21:11.298735 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7662 01:21:11.302529 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7663 01:21:11.302623
7664 01:21:11.308981 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7665 01:21:11.312203 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7666 01:21:11.315362 [Gating] SW calibration Done
7667 01:21:11.315452 ==
7668 01:21:11.318608 Dram Type= 6, Freq= 0, CH_0, rank 0
7669 01:21:11.321770 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7670 01:21:11.321867 ==
7671 01:21:11.321936 RX Vref Scan: 0
7672 01:21:11.324967
7673 01:21:11.325051 RX Vref 0 -> 0, step: 1
7674 01:21:11.325116
7675 01:21:11.328664 RX Delay 0 -> 252, step: 8
7676 01:21:11.331591 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7677 01:21:11.335100 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7678 01:21:11.341869 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7679 01:21:11.345041 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7680 01:21:11.348191 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7681 01:21:11.351365 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7682 01:21:11.355305 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7683 01:21:11.361684 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7684 01:21:11.365067 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7685 01:21:11.368610 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7686 01:21:11.371519 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7687 01:21:11.374907 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7688 01:21:11.381584 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7689 01:21:11.384937 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7690 01:21:11.387750 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7691 01:21:11.391268 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7692 01:21:11.391364 ==
7693 01:21:11.394591 Dram Type= 6, Freq= 0, CH_0, rank 0
7694 01:21:11.401169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7695 01:21:11.401279 ==
7696 01:21:11.401347 DQS Delay:
7697 01:21:11.404607 DQS0 = 0, DQS1 = 0
7698 01:21:11.404697 DQM Delay:
7699 01:21:11.404763 DQM0 = 136, DQM1 = 131
7700 01:21:11.407645 DQ Delay:
7701 01:21:11.411061 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7702 01:21:11.414620 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7703 01:21:11.417695 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7704 01:21:11.421010 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =135
7705 01:21:11.421101
7706 01:21:11.421166
7707 01:21:11.421225 ==
7708 01:21:11.424309 Dram Type= 6, Freq= 0, CH_0, rank 0
7709 01:21:11.430952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7710 01:21:11.431059 ==
7711 01:21:11.431125
7712 01:21:11.431185
7713 01:21:11.431242 TX Vref Scan disable
7714 01:21:11.434143 == TX Byte 0 ==
7715 01:21:11.437584 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7716 01:21:11.444380 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7717 01:21:11.444496 == TX Byte 1 ==
7718 01:21:11.447241 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7719 01:21:11.454290 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7720 01:21:11.454434 ==
7721 01:21:11.457720 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 01:21:11.460779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 01:21:11.460904 ==
7724 01:21:11.473094
7725 01:21:11.476194 TX Vref early break, caculate TX vref
7726 01:21:11.479760 TX Vref=16, minBit 3, minWin=22, winSum=377
7727 01:21:11.482752 TX Vref=18, minBit 1, minWin=23, winSum=385
7728 01:21:11.486099 TX Vref=20, minBit 3, minWin=23, winSum=399
7729 01:21:11.489305 TX Vref=22, minBit 3, minWin=24, winSum=404
7730 01:21:11.492403 TX Vref=24, minBit 0, minWin=25, winSum=417
7731 01:21:11.499417 TX Vref=26, minBit 6, minWin=25, winSum=425
7732 01:21:11.502256 TX Vref=28, minBit 1, minWin=25, winSum=425
7733 01:21:11.506116 TX Vref=30, minBit 7, minWin=24, winSum=415
7734 01:21:11.509326 TX Vref=32, minBit 6, minWin=23, winSum=400
7735 01:21:11.515792 [TxChooseVref] Worse bit 6, Min win 25, Win sum 425, Final Vref 26
7736 01:21:11.515907
7737 01:21:11.519277 Final TX Range 0 Vref 26
7738 01:21:11.519367
7739 01:21:11.519432 ==
7740 01:21:11.522283 Dram Type= 6, Freq= 0, CH_0, rank 0
7741 01:21:11.525722 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7742 01:21:11.525814 ==
7743 01:21:11.525879
7744 01:21:11.525938
7745 01:21:11.529373 TX Vref Scan disable
7746 01:21:11.532508 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7747 01:21:11.535839 == TX Byte 0 ==
7748 01:21:11.539508 u2DelayCellOfst[0]=10 cells (3 PI)
7749 01:21:11.543075 u2DelayCellOfst[1]=13 cells (4 PI)
7750 01:21:11.545627 u2DelayCellOfst[2]=10 cells (3 PI)
7751 01:21:11.548832 u2DelayCellOfst[3]=6 cells (2 PI)
7752 01:21:11.552600 u2DelayCellOfst[4]=6 cells (2 PI)
7753 01:21:11.552702 u2DelayCellOfst[5]=0 cells (0 PI)
7754 01:21:11.555512 u2DelayCellOfst[6]=16 cells (5 PI)
7755 01:21:11.558916 u2DelayCellOfst[7]=16 cells (5 PI)
7756 01:21:11.565707 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7757 01:21:11.568897 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7758 01:21:11.568994 == TX Byte 1 ==
7759 01:21:11.572088 u2DelayCellOfst[8]=0 cells (0 PI)
7760 01:21:11.575385 u2DelayCellOfst[9]=0 cells (0 PI)
7761 01:21:11.579185 u2DelayCellOfst[10]=6 cells (2 PI)
7762 01:21:11.582210 u2DelayCellOfst[11]=0 cells (0 PI)
7763 01:21:11.585313 u2DelayCellOfst[12]=6 cells (2 PI)
7764 01:21:11.589078 u2DelayCellOfst[13]=10 cells (3 PI)
7765 01:21:11.592090 u2DelayCellOfst[14]=13 cells (4 PI)
7766 01:21:11.595494 u2DelayCellOfst[15]=10 cells (3 PI)
7767 01:21:11.599007 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7768 01:21:11.602073 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7769 01:21:11.605280 DramC Write-DBI on
7770 01:21:11.605369 ==
7771 01:21:11.608663 Dram Type= 6, Freq= 0, CH_0, rank 0
7772 01:21:11.612347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7773 01:21:11.612445 ==
7774 01:21:11.612512
7775 01:21:11.612572
7776 01:21:11.615167 TX Vref Scan disable
7777 01:21:11.618939 == TX Byte 0 ==
7778 01:21:11.622227 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7779 01:21:11.625274 == TX Byte 1 ==
7780 01:21:11.628943 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7781 01:21:11.629036 DramC Write-DBI off
7782 01:21:11.629102
7783 01:21:11.631816 [DATLAT]
7784 01:21:11.631900 Freq=1600, CH0 RK0
7785 01:21:11.631966
7786 01:21:11.635761 DATLAT Default: 0xf
7787 01:21:11.635850 0, 0xFFFF, sum = 0
7788 01:21:11.638913 1, 0xFFFF, sum = 0
7789 01:21:11.639001 2, 0xFFFF, sum = 0
7790 01:21:11.642224 3, 0xFFFF, sum = 0
7791 01:21:11.642322 4, 0xFFFF, sum = 0
7792 01:21:11.645251 5, 0xFFFF, sum = 0
7793 01:21:11.645339 6, 0xFFFF, sum = 0
7794 01:21:11.648661 7, 0xFFFF, sum = 0
7795 01:21:11.648750 8, 0xFFFF, sum = 0
7796 01:21:11.651686 9, 0xFFFF, sum = 0
7797 01:21:11.655061 10, 0xFFFF, sum = 0
7798 01:21:11.655156 11, 0xFFFF, sum = 0
7799 01:21:11.658778 12, 0xFFFF, sum = 0
7800 01:21:11.658867 13, 0xFFFF, sum = 0
7801 01:21:11.661808 14, 0x0, sum = 1
7802 01:21:11.661901 15, 0x0, sum = 2
7803 01:21:11.665144 16, 0x0, sum = 3
7804 01:21:11.665234 17, 0x0, sum = 4
7805 01:21:11.665301 best_step = 15
7806 01:21:11.668613
7807 01:21:11.668699 ==
7808 01:21:11.671904 Dram Type= 6, Freq= 0, CH_0, rank 0
7809 01:21:11.675069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7810 01:21:11.675158 ==
7811 01:21:11.675224 RX Vref Scan: 1
7812 01:21:11.675285
7813 01:21:11.678794 Set Vref Range= 24 -> 127
7814 01:21:11.678879
7815 01:21:11.681857 RX Vref 24 -> 127, step: 1
7816 01:21:11.681989
7817 01:21:11.685087 RX Delay 27 -> 252, step: 4
7818 01:21:11.685175
7819 01:21:11.688704 Set Vref, RX VrefLevel [Byte0]: 24
7820 01:21:11.691911 [Byte1]: 24
7821 01:21:11.692001
7822 01:21:11.694917 Set Vref, RX VrefLevel [Byte0]: 25
7823 01:21:11.698567 [Byte1]: 25
7824 01:21:11.698659
7825 01:21:11.701812 Set Vref, RX VrefLevel [Byte0]: 26
7826 01:21:11.705103 [Byte1]: 26
7827 01:21:11.708293
7828 01:21:11.708377 Set Vref, RX VrefLevel [Byte0]: 27
7829 01:21:11.711501 [Byte1]: 27
7830 01:21:11.716237
7831 01:21:11.716331 Set Vref, RX VrefLevel [Byte0]: 28
7832 01:21:11.719364 [Byte1]: 28
7833 01:21:11.723649
7834 01:21:11.723751 Set Vref, RX VrefLevel [Byte0]: 29
7835 01:21:11.727009 [Byte1]: 29
7836 01:21:11.730717
7837 01:21:11.730812 Set Vref, RX VrefLevel [Byte0]: 30
7838 01:21:11.734534 [Byte1]: 30
7839 01:21:11.738628
7840 01:21:11.738777 Set Vref, RX VrefLevel [Byte0]: 31
7841 01:21:11.741642 [Byte1]: 31
7842 01:21:11.746088
7843 01:21:11.746215 Set Vref, RX VrefLevel [Byte0]: 32
7844 01:21:11.749670 [Byte1]: 32
7845 01:21:11.753418
7846 01:21:11.753544 Set Vref, RX VrefLevel [Byte0]: 33
7847 01:21:11.757049 [Byte1]: 33
7848 01:21:11.761365
7849 01:21:11.761500 Set Vref, RX VrefLevel [Byte0]: 34
7850 01:21:11.764504 [Byte1]: 34
7851 01:21:11.768849
7852 01:21:11.768976 Set Vref, RX VrefLevel [Byte0]: 35
7853 01:21:11.771698 [Byte1]: 35
7854 01:21:11.776166
7855 01:21:11.776293 Set Vref, RX VrefLevel [Byte0]: 36
7856 01:21:11.779380 [Byte1]: 36
7857 01:21:11.783857
7858 01:21:11.783980 Set Vref, RX VrefLevel [Byte0]: 37
7859 01:21:11.787072 [Byte1]: 37
7860 01:21:11.791336
7861 01:21:11.791461 Set Vref, RX VrefLevel [Byte0]: 38
7862 01:21:11.794419 [Byte1]: 38
7863 01:21:11.798793
7864 01:21:11.798901 Set Vref, RX VrefLevel [Byte0]: 39
7865 01:21:11.801895 [Byte1]: 39
7866 01:21:11.806358
7867 01:21:11.806458 Set Vref, RX VrefLevel [Byte0]: 40
7868 01:21:11.809596 [Byte1]: 40
7869 01:21:11.814075
7870 01:21:11.814176 Set Vref, RX VrefLevel [Byte0]: 41
7871 01:21:11.817213 [Byte1]: 41
7872 01:21:11.821823
7873 01:21:11.821934 Set Vref, RX VrefLevel [Byte0]: 42
7874 01:21:11.824823 [Byte1]: 42
7875 01:21:11.828983
7876 01:21:11.829122 Set Vref, RX VrefLevel [Byte0]: 43
7877 01:21:11.832747 [Byte1]: 43
7878 01:21:11.836276
7879 01:21:11.836407 Set Vref, RX VrefLevel [Byte0]: 44
7880 01:21:11.839703 [Byte1]: 44
7881 01:21:11.844292
7882 01:21:11.844415 Set Vref, RX VrefLevel [Byte0]: 45
7883 01:21:11.847415 [Byte1]: 45
7884 01:21:11.851687
7885 01:21:11.851811 Set Vref, RX VrefLevel [Byte0]: 46
7886 01:21:11.854885 [Byte1]: 46
7887 01:21:11.858973
7888 01:21:11.859085 Set Vref, RX VrefLevel [Byte0]: 47
7889 01:21:11.862106 [Byte1]: 47
7890 01:21:11.866491
7891 01:21:11.866608 Set Vref, RX VrefLevel [Byte0]: 48
7892 01:21:11.870007 [Byte1]: 48
7893 01:21:11.874279
7894 01:21:11.874421 Set Vref, RX VrefLevel [Byte0]: 49
7895 01:21:11.877456 [Byte1]: 49
7896 01:21:11.881538
7897 01:21:11.881655 Set Vref, RX VrefLevel [Byte0]: 50
7898 01:21:11.884879 [Byte1]: 50
7899 01:21:11.889245
7900 01:21:11.889458 Set Vref, RX VrefLevel [Byte0]: 51
7901 01:21:11.892920 [Byte1]: 51
7902 01:21:11.896690
7903 01:21:11.896802 Set Vref, RX VrefLevel [Byte0]: 52
7904 01:21:11.899730 [Byte1]: 52
7905 01:21:11.904034
7906 01:21:11.904163 Set Vref, RX VrefLevel [Byte0]: 53
7907 01:21:11.907852 [Byte1]: 53
7908 01:21:11.911628
7909 01:21:11.911737 Set Vref, RX VrefLevel [Byte0]: 54
7910 01:21:11.914879 [Byte1]: 54
7911 01:21:11.919288
7912 01:21:11.919406 Set Vref, RX VrefLevel [Byte0]: 55
7913 01:21:11.922665 [Byte1]: 55
7914 01:21:11.927199
7915 01:21:11.927312 Set Vref, RX VrefLevel [Byte0]: 56
7916 01:21:11.930233 [Byte1]: 56
7917 01:21:11.934597
7918 01:21:11.934725 Set Vref, RX VrefLevel [Byte0]: 57
7919 01:21:11.937852 [Byte1]: 57
7920 01:21:11.942132
7921 01:21:11.942275 Set Vref, RX VrefLevel [Byte0]: 58
7922 01:21:11.945490 [Byte1]: 58
7923 01:21:11.949273
7924 01:21:11.949406 Set Vref, RX VrefLevel [Byte0]: 59
7925 01:21:11.952809 [Byte1]: 59
7926 01:21:11.957041
7927 01:21:11.957156 Set Vref, RX VrefLevel [Byte0]: 60
7928 01:21:11.960243 [Byte1]: 60
7929 01:21:11.964664
7930 01:21:11.964809 Set Vref, RX VrefLevel [Byte0]: 61
7931 01:21:11.967888 [Byte1]: 61
7932 01:21:11.972274
7933 01:21:11.972401 Set Vref, RX VrefLevel [Byte0]: 62
7934 01:21:11.975375 [Byte1]: 62
7935 01:21:11.979584
7936 01:21:11.979717 Set Vref, RX VrefLevel [Byte0]: 63
7937 01:21:11.983221 [Byte1]: 63
7938 01:21:11.987336
7939 01:21:11.987456 Set Vref, RX VrefLevel [Byte0]: 64
7940 01:21:11.990196 [Byte1]: 64
7941 01:21:11.994404
7942 01:21:11.994540 Set Vref, RX VrefLevel [Byte0]: 65
7943 01:21:11.997771 [Byte1]: 65
7944 01:21:12.002054
7945 01:21:12.002189 Set Vref, RX VrefLevel [Byte0]: 66
7946 01:21:12.005438 [Byte1]: 66
7947 01:21:12.009464
7948 01:21:12.009617 Set Vref, RX VrefLevel [Byte0]: 67
7949 01:21:12.012872 [Byte1]: 67
7950 01:21:12.017206
7951 01:21:12.017338 Set Vref, RX VrefLevel [Byte0]: 68
7952 01:21:12.020413 [Byte1]: 68
7953 01:21:12.024944
7954 01:21:12.025078 Set Vref, RX VrefLevel [Byte0]: 69
7955 01:21:12.028094 [Byte1]: 69
7956 01:21:12.032741
7957 01:21:12.032878 Set Vref, RX VrefLevel [Byte0]: 70
7958 01:21:12.035799 [Byte1]: 70
7959 01:21:12.040175
7960 01:21:12.040304 Set Vref, RX VrefLevel [Byte0]: 71
7961 01:21:12.043140 [Byte1]: 71
7962 01:21:12.047323
7963 01:21:12.047455 Set Vref, RX VrefLevel [Byte0]: 72
7964 01:21:12.050625 [Byte1]: 72
7965 01:21:12.055158
7966 01:21:12.055285 Set Vref, RX VrefLevel [Byte0]: 73
7967 01:21:12.058471 [Byte1]: 73
7968 01:21:12.062219
7969 01:21:12.062399 Set Vref, RX VrefLevel [Byte0]: 74
7970 01:21:12.065952 [Byte1]: 74
7971 01:21:12.070419
7972 01:21:12.070571 Final RX Vref Byte 0 = 59 to rank0
7973 01:21:12.073331 Final RX Vref Byte 1 = 64 to rank0
7974 01:21:12.076805 Final RX Vref Byte 0 = 59 to rank1
7975 01:21:12.079717 Final RX Vref Byte 1 = 64 to rank1==
7976 01:21:12.083312 Dram Type= 6, Freq= 0, CH_0, rank 0
7977 01:21:12.090215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7978 01:21:12.090422 ==
7979 01:21:12.090522 DQS Delay:
7980 01:21:12.090610 DQS0 = 0, DQS1 = 0
7981 01:21:12.093083 DQM Delay:
7982 01:21:12.093204 DQM0 = 134, DQM1 = 128
7983 01:21:12.096373 DQ Delay:
7984 01:21:12.100074 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7985 01:21:12.103102 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7986 01:21:12.106265 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122
7987 01:21:12.110107 DQ12 =132, DQ13 =132, DQ14 =140, DQ15 =136
7988 01:21:12.110247
7989 01:21:12.110351
7990 01:21:12.110430
7991 01:21:12.113088 [DramC_TX_OE_Calibration] TA2
7992 01:21:12.116419 Original DQ_B0 (3 6) =30, OEN = 27
7993 01:21:12.119837 Original DQ_B1 (3 6) =30, OEN = 27
7994 01:21:12.122776 24, 0x0, End_B0=24 End_B1=24
7995 01:21:12.122899 25, 0x0, End_B0=25 End_B1=25
7996 01:21:12.126292 26, 0x0, End_B0=26 End_B1=26
7997 01:21:12.129708 27, 0x0, End_B0=27 End_B1=27
7998 01:21:12.132864 28, 0x0, End_B0=28 End_B1=28
7999 01:21:12.136025 29, 0x0, End_B0=29 End_B1=29
8000 01:21:12.136157 30, 0x0, End_B0=30 End_B1=30
8001 01:21:12.139311 31, 0x4545, End_B0=30 End_B1=30
8002 01:21:12.143109 Byte0 end_step=30 best_step=27
8003 01:21:12.146279 Byte1 end_step=30 best_step=27
8004 01:21:12.149482 Byte0 TX OE(2T, 0.5T) = (3, 3)
8005 01:21:12.152716 Byte1 TX OE(2T, 0.5T) = (3, 3)
8006 01:21:12.152830
8007 01:21:12.152898
8008 01:21:12.159605 [DQSOSCAuto] RK0, (LSB)MR18= 0x221e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 392 ps
8009 01:21:12.162723 CH0 RK0: MR19=303, MR18=221E
8010 01:21:12.169576 CH0_RK0: MR19=0x303, MR18=0x221E, DQSOSC=392, MR23=63, INC=24, DEC=16
8011 01:21:12.169731
8012 01:21:12.172758 ----->DramcWriteLeveling(PI) begin...
8013 01:21:12.172883 ==
8014 01:21:12.176013 Dram Type= 6, Freq= 0, CH_0, rank 1
8015 01:21:12.179656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8016 01:21:12.179821 ==
8017 01:21:12.182507 Write leveling (Byte 0): 36 => 36
8018 01:21:12.186168 Write leveling (Byte 1): 26 => 26
8019 01:21:12.189030 DramcWriteLeveling(PI) end<-----
8020 01:21:12.189161
8021 01:21:12.189231 ==
8022 01:21:12.192885 Dram Type= 6, Freq= 0, CH_0, rank 1
8023 01:21:12.196129 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8024 01:21:12.196269 ==
8025 01:21:12.199197 [Gating] SW mode calibration
8026 01:21:12.205677 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8027 01:21:12.212149 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8028 01:21:12.215776 1 4 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8029 01:21:12.222228 1 4 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8030 01:21:12.225357 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8031 01:21:12.228791 1 4 12 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
8032 01:21:12.235528 1 4 16 | B1->B0 | 2c2c 3535 | 0 0 | (0 0) (0 0)
8033 01:21:12.238565 1 4 20 | B1->B0 | 3434 3736 | 1 1 | (1 1) (1 1)
8034 01:21:12.242133 1 4 24 | B1->B0 | 3434 3a3a | 1 1 | (1 1) (1 1)
8035 01:21:12.248720 1 4 28 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
8036 01:21:12.251948 1 5 0 | B1->B0 | 3434 3939 | 1 0 | (1 1) (0 0)
8037 01:21:12.255300 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
8038 01:21:12.261843 1 5 8 | B1->B0 | 3434 3838 | 1 1 | (1 1) (1 0)
8039 01:21:12.265196 1 5 12 | B1->B0 | 3434 3534 | 1 1 | (1 0) (1 0)
8040 01:21:12.268478 1 5 16 | B1->B0 | 2c2c 2b2a | 1 1 | (1 0) (0 1)
8041 01:21:12.275140 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8042 01:21:12.278318 1 5 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8043 01:21:12.282204 1 5 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8044 01:21:12.285464 1 6 0 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
8045 01:21:12.291842 1 6 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
8046 01:21:12.294835 1 6 8 | B1->B0 | 2323 2625 | 0 1 | (0 0) (1 1)
8047 01:21:12.298294 1 6 12 | B1->B0 | 2323 3534 | 0 1 | (0 0) (0 0)
8048 01:21:12.304980 1 6 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
8049 01:21:12.308139 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8050 01:21:12.311318 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8051 01:21:12.318491 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8052 01:21:12.321469 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 01:21:12.324773 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 01:21:12.331506 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 01:21:12.334696 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8056 01:21:12.338191 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8057 01:21:12.344859 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 01:21:12.348174 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 01:21:12.351380 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 01:21:12.358160 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 01:21:12.361041 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 01:21:12.364523 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 01:21:12.371353 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 01:21:12.374728 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 01:21:12.378223 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 01:21:12.384318 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 01:21:12.387809 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 01:21:12.391385 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 01:21:12.397991 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 01:21:12.400881 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 01:21:12.404385 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8072 01:21:12.411227 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8073 01:21:12.411362 Total UI for P1: 0, mck2ui 16
8074 01:21:12.417732 best dqsien dly found for B0: ( 1, 9, 12)
8075 01:21:12.421021 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 01:21:12.424142 Total UI for P1: 0, mck2ui 16
8077 01:21:12.427397 best dqsien dly found for B1: ( 1, 9, 14)
8078 01:21:12.431313 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8079 01:21:12.434580 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8080 01:21:12.434707
8081 01:21:12.437592 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8082 01:21:12.440809 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8083 01:21:12.444140 [Gating] SW calibration Done
8084 01:21:12.444260 ==
8085 01:21:12.447265 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 01:21:12.450874 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 01:21:12.454438 ==
8088 01:21:12.454557 RX Vref Scan: 0
8089 01:21:12.454625
8090 01:21:12.457179 RX Vref 0 -> 0, step: 1
8091 01:21:12.457273
8092 01:21:12.457339 RX Delay 0 -> 252, step: 8
8093 01:21:12.463888 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8094 01:21:12.467285 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8095 01:21:12.470567 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8096 01:21:12.474549 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8097 01:21:12.480819 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8098 01:21:12.483806 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8099 01:21:12.487297 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8100 01:21:12.491214 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8101 01:21:12.494241 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8102 01:21:12.500100 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8103 01:21:12.503643 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8104 01:21:12.506802 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8105 01:21:12.510200 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8106 01:21:12.514335 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8107 01:21:12.520366 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8108 01:21:12.523427 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8109 01:21:12.523554 ==
8110 01:21:12.527351 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 01:21:12.530547 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 01:21:12.530664 ==
8113 01:21:12.533810 DQS Delay:
8114 01:21:12.533914 DQS0 = 0, DQS1 = 0
8115 01:21:12.533981 DQM Delay:
8116 01:21:12.537003 DQM0 = 137, DQM1 = 130
8117 01:21:12.537119 DQ Delay:
8118 01:21:12.540254 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8119 01:21:12.543542 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8120 01:21:12.546736 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8121 01:21:12.553275 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8122 01:21:12.553420
8123 01:21:12.553488
8124 01:21:12.553548 ==
8125 01:21:12.556973 Dram Type= 6, Freq= 0, CH_0, rank 1
8126 01:21:12.560163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8127 01:21:12.560275 ==
8128 01:21:12.560340
8129 01:21:12.560401
8130 01:21:12.563567 TX Vref Scan disable
8131 01:21:12.563681 == TX Byte 0 ==
8132 01:21:12.569841 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8133 01:21:12.573235 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8134 01:21:12.576457 == TX Byte 1 ==
8135 01:21:12.579990 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8136 01:21:12.582850 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8137 01:21:12.582968 ==
8138 01:21:12.586921 Dram Type= 6, Freq= 0, CH_0, rank 1
8139 01:21:12.590058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8140 01:21:12.590169 ==
8141 01:21:12.605278
8142 01:21:12.608304 TX Vref early break, caculate TX vref
8143 01:21:12.611794 TX Vref=16, minBit 0, minWin=23, winSum=383
8144 01:21:12.615418 TX Vref=18, minBit 0, minWin=24, winSum=396
8145 01:21:12.618506 TX Vref=20, minBit 1, minWin=23, winSum=401
8146 01:21:12.621704 TX Vref=22, minBit 3, minWin=24, winSum=409
8147 01:21:12.624718 TX Vref=24, minBit 3, minWin=24, winSum=417
8148 01:21:12.631780 TX Vref=26, minBit 3, minWin=25, winSum=426
8149 01:21:12.634815 TX Vref=28, minBit 3, minWin=25, winSum=425
8150 01:21:12.638031 TX Vref=30, minBit 6, minWin=25, winSum=417
8151 01:21:12.641481 TX Vref=32, minBit 0, minWin=25, winSum=411
8152 01:21:12.644806 TX Vref=34, minBit 0, minWin=24, winSum=401
8153 01:21:12.651556 [TxChooseVref] Worse bit 3, Min win 25, Win sum 426, Final Vref 26
8154 01:21:12.651700
8155 01:21:12.654679 Final TX Range 0 Vref 26
8156 01:21:12.654799
8157 01:21:12.654867 ==
8158 01:21:12.657903 Dram Type= 6, Freq= 0, CH_0, rank 1
8159 01:21:12.661568 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8160 01:21:12.661681 ==
8161 01:21:12.661748
8162 01:21:12.661809
8163 01:21:12.664869 TX Vref Scan disable
8164 01:21:12.671175 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8165 01:21:12.671311 == TX Byte 0 ==
8166 01:21:12.674513 u2DelayCellOfst[0]=10 cells (3 PI)
8167 01:21:12.678061 u2DelayCellOfst[1]=13 cells (4 PI)
8168 01:21:12.681149 u2DelayCellOfst[2]=10 cells (3 PI)
8169 01:21:12.684513 u2DelayCellOfst[3]=10 cells (3 PI)
8170 01:21:12.688052 u2DelayCellOfst[4]=6 cells (2 PI)
8171 01:21:12.691031 u2DelayCellOfst[5]=0 cells (0 PI)
8172 01:21:12.694790 u2DelayCellOfst[6]=13 cells (4 PI)
8173 01:21:12.697761 u2DelayCellOfst[7]=13 cells (4 PI)
8174 01:21:12.701255 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8175 01:21:12.704370 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8176 01:21:12.708085 == TX Byte 1 ==
8177 01:21:12.711396 u2DelayCellOfst[8]=0 cells (0 PI)
8178 01:21:12.711514 u2DelayCellOfst[9]=0 cells (0 PI)
8179 01:21:12.714433 u2DelayCellOfst[10]=3 cells (1 PI)
8180 01:21:12.717650 u2DelayCellOfst[11]=3 cells (1 PI)
8181 01:21:12.721344 u2DelayCellOfst[12]=6 cells (2 PI)
8182 01:21:12.724599 u2DelayCellOfst[13]=10 cells (3 PI)
8183 01:21:12.727859 u2DelayCellOfst[14]=13 cells (4 PI)
8184 01:21:12.731036 u2DelayCellOfst[15]=6 cells (2 PI)
8185 01:21:12.734292 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8186 01:21:12.741229 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8187 01:21:12.741370 DramC Write-DBI on
8188 01:21:12.741439 ==
8189 01:21:12.744132 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 01:21:12.747628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 01:21:12.751306 ==
8192 01:21:12.751426
8193 01:21:12.751496
8194 01:21:12.751555 TX Vref Scan disable
8195 01:21:12.754871 == TX Byte 0 ==
8196 01:21:12.757922 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8197 01:21:12.761169 == TX Byte 1 ==
8198 01:21:12.764726 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8199 01:21:12.768351 DramC Write-DBI off
8200 01:21:12.768469
8201 01:21:12.768539 [DATLAT]
8202 01:21:12.768655 Freq=1600, CH0 RK1
8203 01:21:12.768715
8204 01:21:12.770872 DATLAT Default: 0xf
8205 01:21:12.770964 0, 0xFFFF, sum = 0
8206 01:21:12.774715 1, 0xFFFF, sum = 0
8207 01:21:12.777871 2, 0xFFFF, sum = 0
8208 01:21:12.777983 3, 0xFFFF, sum = 0
8209 01:21:12.780949 4, 0xFFFF, sum = 0
8210 01:21:12.781052 5, 0xFFFF, sum = 0
8211 01:21:12.784507 6, 0xFFFF, sum = 0
8212 01:21:12.784622 7, 0xFFFF, sum = 0
8213 01:21:12.787884 8, 0xFFFF, sum = 0
8214 01:21:12.787987 9, 0xFFFF, sum = 0
8215 01:21:12.791444 10, 0xFFFF, sum = 0
8216 01:21:12.791555 11, 0xFFFF, sum = 0
8217 01:21:12.794699 12, 0xFFFF, sum = 0
8218 01:21:12.794790 13, 0xFFFF, sum = 0
8219 01:21:12.797783 14, 0x0, sum = 1
8220 01:21:12.797871 15, 0x0, sum = 2
8221 01:21:12.801042 16, 0x0, sum = 3
8222 01:21:12.801133 17, 0x0, sum = 4
8223 01:21:12.804194 best_step = 15
8224 01:21:12.804281
8225 01:21:12.804345 ==
8226 01:21:12.807838 Dram Type= 6, Freq= 0, CH_0, rank 1
8227 01:21:12.810746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8228 01:21:12.810835 ==
8229 01:21:12.814113 RX Vref Scan: 0
8230 01:21:12.814199
8231 01:21:12.814265 RX Vref 0 -> 0, step: 1
8232 01:21:12.814353
8233 01:21:12.817379 RX Delay 19 -> 252, step: 4
8234 01:21:12.820982 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8235 01:21:12.827947 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8236 01:21:12.831293 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8237 01:21:12.834481 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8238 01:21:12.837649 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8239 01:21:12.840776 iDelay=191, Bit 5, Center 126 (71 ~ 182) 112
8240 01:21:12.847314 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8241 01:21:12.851008 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8242 01:21:12.854027 iDelay=191, Bit 8, Center 120 (71 ~ 170) 100
8243 01:21:12.857282 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8244 01:21:12.861099 iDelay=191, Bit 10, Center 128 (79 ~ 178) 100
8245 01:21:12.867757 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8246 01:21:12.870753 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8247 01:21:12.873893 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8248 01:21:12.877447 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8249 01:21:12.880584 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8250 01:21:12.883756 ==
8251 01:21:12.887607 Dram Type= 6, Freq= 0, CH_0, rank 1
8252 01:21:12.890829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8253 01:21:12.890928 ==
8254 01:21:12.890994 DQS Delay:
8255 01:21:12.893901 DQS0 = 0, DQS1 = 0
8256 01:21:12.893987 DQM Delay:
8257 01:21:12.897588 DQM0 = 134, DQM1 = 127
8258 01:21:12.897678 DQ Delay:
8259 01:21:12.900614 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8260 01:21:12.904439 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =140
8261 01:21:12.907720 DQ8 =120, DQ9 =116, DQ10 =128, DQ11 =118
8262 01:21:12.910867 DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =134
8263 01:21:12.910981
8264 01:21:12.911045
8265 01:21:12.911105
8266 01:21:12.913994 [DramC_TX_OE_Calibration] TA2
8267 01:21:12.917232 Original DQ_B0 (3 6) =30, OEN = 27
8268 01:21:12.920907 Original DQ_B1 (3 6) =30, OEN = 27
8269 01:21:12.924129 24, 0x0, End_B0=24 End_B1=24
8270 01:21:12.927232 25, 0x0, End_B0=25 End_B1=25
8271 01:21:12.927350 26, 0x0, End_B0=26 End_B1=26
8272 01:21:12.930768 27, 0x0, End_B0=27 End_B1=27
8273 01:21:12.933775 28, 0x0, End_B0=28 End_B1=28
8274 01:21:12.936876 29, 0x0, End_B0=29 End_B1=29
8275 01:21:12.940415 30, 0x0, End_B0=30 End_B1=30
8276 01:21:12.940571 31, 0x4141, End_B0=30 End_B1=30
8277 01:21:12.943868 Byte0 end_step=30 best_step=27
8278 01:21:12.947038 Byte1 end_step=30 best_step=27
8279 01:21:12.950169 Byte0 TX OE(2T, 0.5T) = (3, 3)
8280 01:21:12.953956 Byte1 TX OE(2T, 0.5T) = (3, 3)
8281 01:21:12.954076
8282 01:21:12.954145
8283 01:21:12.960096 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps
8284 01:21:12.964156 CH0 RK1: MR19=303, MR18=1E07
8285 01:21:12.970594 CH0_RK1: MR19=0x303, MR18=0x1E07, DQSOSC=394, MR23=63, INC=23, DEC=15
8286 01:21:12.973828 [RxdqsGatingPostProcess] freq 1600
8287 01:21:12.980115 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8288 01:21:12.980258 best DQS0 dly(2T, 0.5T) = (1, 1)
8289 01:21:12.984091 best DQS1 dly(2T, 0.5T) = (1, 1)
8290 01:21:12.987176 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8291 01:21:12.990604 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8292 01:21:12.993741 best DQS0 dly(2T, 0.5T) = (1, 1)
8293 01:21:12.997269 best DQS1 dly(2T, 0.5T) = (1, 1)
8294 01:21:13.000530 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8295 01:21:13.003810 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8296 01:21:13.006765 Pre-setting of DQS Precalculation
8297 01:21:13.010326 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8298 01:21:13.010461 ==
8299 01:21:13.014022 Dram Type= 6, Freq= 0, CH_1, rank 0
8300 01:21:13.020283 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8301 01:21:13.020406 ==
8302 01:21:13.023363 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8303 01:21:13.029980 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8304 01:21:13.033035 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8305 01:21:13.039968 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8306 01:21:13.047467 [CA 0] Center 42 (13~72) winsize 60
8307 01:21:13.050967 [CA 1] Center 42 (12~72) winsize 61
8308 01:21:13.053924 [CA 2] Center 38 (9~68) winsize 60
8309 01:21:13.057369 [CA 3] Center 38 (9~67) winsize 59
8310 01:21:13.060622 [CA 4] Center 38 (9~68) winsize 60
8311 01:21:13.063882 [CA 5] Center 37 (8~67) winsize 60
8312 01:21:13.063990
8313 01:21:13.067448 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8314 01:21:13.067541
8315 01:21:13.070971 [CATrainingPosCal] consider 1 rank data
8316 01:21:13.074167 u2DelayCellTimex100 = 290/100 ps
8317 01:21:13.077440 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8318 01:21:13.084333 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8319 01:21:13.087648 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8320 01:21:13.090742 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8321 01:21:13.094297 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8322 01:21:13.097278 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8323 01:21:13.097376
8324 01:21:13.101073 CA PerBit enable=1, Macro0, CA PI delay=37
8325 01:21:13.101167
8326 01:21:13.104242 [CBTSetCACLKResult] CA Dly = 37
8327 01:21:13.107693 CS Dly: 10 (0~41)
8328 01:21:13.110722 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8329 01:21:13.113845 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8330 01:21:13.113938 ==
8331 01:21:13.117402 Dram Type= 6, Freq= 0, CH_1, rank 1
8332 01:21:13.120914 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8333 01:21:13.121009 ==
8334 01:21:13.127203 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8335 01:21:13.130989 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8336 01:21:13.137491 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8337 01:21:13.140600 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8338 01:21:13.150777 [CA 0] Center 42 (12~72) winsize 61
8339 01:21:13.154096 [CA 1] Center 42 (12~72) winsize 61
8340 01:21:13.157823 [CA 2] Center 38 (9~68) winsize 60
8341 01:21:13.160869 [CA 3] Center 38 (8~68) winsize 61
8342 01:21:13.164115 [CA 4] Center 38 (8~69) winsize 62
8343 01:21:13.167538 [CA 5] Center 37 (8~66) winsize 59
8344 01:21:13.167642
8345 01:21:13.170421 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8346 01:21:13.170511
8347 01:21:13.174025 [CATrainingPosCal] consider 2 rank data
8348 01:21:13.177462 u2DelayCellTimex100 = 290/100 ps
8349 01:21:13.180660 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8350 01:21:13.187423 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8351 01:21:13.190784 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8352 01:21:13.193754 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8353 01:21:13.197464 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8354 01:21:13.200442 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8355 01:21:13.200539
8356 01:21:13.204055 CA PerBit enable=1, Macro0, CA PI delay=37
8357 01:21:13.204152
8358 01:21:13.206851 [CBTSetCACLKResult] CA Dly = 37
8359 01:21:13.210550 CS Dly: 11 (0~44)
8360 01:21:13.213755 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8361 01:21:13.216922 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8362 01:21:13.217020
8363 01:21:13.220240 ----->DramcWriteLeveling(PI) begin...
8364 01:21:13.220331 ==
8365 01:21:13.223752 Dram Type= 6, Freq= 0, CH_1, rank 0
8366 01:21:13.230282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8367 01:21:13.230504 ==
8368 01:21:13.233374 Write leveling (Byte 0): 24 => 24
8369 01:21:13.233466 Write leveling (Byte 1): 26 => 26
8370 01:21:13.237119 DramcWriteLeveling(PI) end<-----
8371 01:21:13.237207
8372 01:21:13.237271 ==
8373 01:21:13.240546 Dram Type= 6, Freq= 0, CH_1, rank 0
8374 01:21:13.246859 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8375 01:21:13.246996 ==
8376 01:21:13.250099 [Gating] SW mode calibration
8377 01:21:13.257223 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8378 01:21:13.260336 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8379 01:21:13.266889 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 01:21:13.270282 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 01:21:13.273662 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
8382 01:21:13.280629 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8383 01:21:13.283918 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 01:21:13.287145 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8385 01:21:13.293448 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 01:21:13.296967 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 01:21:13.299812 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 01:21:13.303260 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8389 01:21:13.310266 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
8390 01:21:13.313477 1 5 12 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (1 0)
8391 01:21:13.319759 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 01:21:13.323199 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 01:21:13.326252 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 01:21:13.329845 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 01:21:13.336344 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 01:21:13.339912 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 01:21:13.342828 1 6 8 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
8398 01:21:13.349810 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8399 01:21:13.353017 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 01:21:13.356202 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8401 01:21:13.363379 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 01:21:13.365978 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 01:21:13.369649 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 01:21:13.376488 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 01:21:13.379983 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8406 01:21:13.382657 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8407 01:21:13.389876 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8408 01:21:13.392639 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 01:21:13.396481 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 01:21:13.402817 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 01:21:13.405774 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 01:21:13.409568 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 01:21:13.415909 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 01:21:13.419344 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 01:21:13.422696 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 01:21:13.429132 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 01:21:13.432616 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 01:21:13.435958 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 01:21:13.442405 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 01:21:13.445833 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 01:21:13.449527 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 01:21:13.456073 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8423 01:21:13.459188 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8424 01:21:13.462018 Total UI for P1: 0, mck2ui 16
8425 01:21:13.465653 best dqsien dly found for B0: ( 1, 9, 12)
8426 01:21:13.468875 Total UI for P1: 0, mck2ui 16
8427 01:21:13.472670 best dqsien dly found for B1: ( 1, 9, 12)
8428 01:21:13.475921 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8429 01:21:13.479039 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8430 01:21:13.479143
8431 01:21:13.482270 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8432 01:21:13.485617 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8433 01:21:13.488761 [Gating] SW calibration Done
8434 01:21:13.488860 ==
8435 01:21:13.492532 Dram Type= 6, Freq= 0, CH_1, rank 0
8436 01:21:13.495296 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8437 01:21:13.499116 ==
8438 01:21:13.499226 RX Vref Scan: 0
8439 01:21:13.499294
8440 01:21:13.502503 RX Vref 0 -> 0, step: 1
8441 01:21:13.502614
8442 01:21:13.502683 RX Delay 0 -> 252, step: 8
8443 01:21:13.508789 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8444 01:21:13.511925 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8445 01:21:13.515466 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8446 01:21:13.518580 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8447 01:21:13.521717 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8448 01:21:13.528886 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8449 01:21:13.532151 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8450 01:21:13.535336 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8451 01:21:13.538523 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8452 01:21:13.541777 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8453 01:21:13.548891 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8454 01:21:13.552103 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8455 01:21:13.555129 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8456 01:21:13.558733 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8457 01:21:13.565507 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8458 01:21:13.568804 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8459 01:21:13.568924 ==
8460 01:21:13.572080 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 01:21:13.575015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 01:21:13.575119 ==
8463 01:21:13.575186 DQS Delay:
8464 01:21:13.578434 DQS0 = 0, DQS1 = 0
8465 01:21:13.578532 DQM Delay:
8466 01:21:13.581834 DQM0 = 136, DQM1 = 132
8467 01:21:13.581936 DQ Delay:
8468 01:21:13.585095 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8469 01:21:13.588506 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8470 01:21:13.591902 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8471 01:21:13.595060 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8472 01:21:13.598212
8473 01:21:13.598381
8474 01:21:13.598485 ==
8475 01:21:13.601693 Dram Type= 6, Freq= 0, CH_1, rank 0
8476 01:21:13.605269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8477 01:21:13.605383 ==
8478 01:21:13.605450
8479 01:21:13.605511
8480 01:21:13.608800 TX Vref Scan disable
8481 01:21:13.608893 == TX Byte 0 ==
8482 01:21:13.615313 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8483 01:21:13.618502 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8484 01:21:13.618607 == TX Byte 1 ==
8485 01:21:13.624960 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8486 01:21:13.628246 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8487 01:21:13.628398 ==
8488 01:21:13.631495 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 01:21:13.634766 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 01:21:13.634923 ==
8491 01:21:13.648551
8492 01:21:13.651568 TX Vref early break, caculate TX vref
8493 01:21:13.654649 TX Vref=16, minBit 6, minWin=22, winSum=380
8494 01:21:13.658316 TX Vref=18, minBit 0, minWin=23, winSum=391
8495 01:21:13.661464 TX Vref=20, minBit 3, minWin=24, winSum=403
8496 01:21:13.664748 TX Vref=22, minBit 0, minWin=25, winSum=412
8497 01:21:13.667880 TX Vref=24, minBit 6, minWin=24, winSum=413
8498 01:21:13.674467 TX Vref=26, minBit 0, minWin=25, winSum=425
8499 01:21:13.677717 TX Vref=28, minBit 1, minWin=24, winSum=429
8500 01:21:13.681355 TX Vref=30, minBit 2, minWin=25, winSum=423
8501 01:21:13.684515 TX Vref=32, minBit 0, minWin=24, winSum=416
8502 01:21:13.688117 TX Vref=34, minBit 0, minWin=24, winSum=403
8503 01:21:13.694392 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 26
8504 01:21:13.694543
8505 01:21:13.697688 Final TX Range 0 Vref 26
8506 01:21:13.697801
8507 01:21:13.697870 ==
8508 01:21:13.701462 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 01:21:13.704476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 01:21:13.704600 ==
8511 01:21:13.704669
8512 01:21:13.704729
8513 01:21:13.708008 TX Vref Scan disable
8514 01:21:13.715008 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8515 01:21:13.715165 == TX Byte 0 ==
8516 01:21:13.718182 u2DelayCellOfst[0]=16 cells (5 PI)
8517 01:21:13.721448 u2DelayCellOfst[1]=10 cells (3 PI)
8518 01:21:13.724761 u2DelayCellOfst[2]=0 cells (0 PI)
8519 01:21:13.727868 u2DelayCellOfst[3]=3 cells (1 PI)
8520 01:21:13.731095 u2DelayCellOfst[4]=6 cells (2 PI)
8521 01:21:13.734827 u2DelayCellOfst[5]=16 cells (5 PI)
8522 01:21:13.737584 u2DelayCellOfst[6]=16 cells (5 PI)
8523 01:21:13.737693 u2DelayCellOfst[7]=6 cells (2 PI)
8524 01:21:13.744471 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8525 01:21:13.747398 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8526 01:21:13.747496 == TX Byte 1 ==
8527 01:21:13.750809 u2DelayCellOfst[8]=0 cells (0 PI)
8528 01:21:13.754032 u2DelayCellOfst[9]=3 cells (1 PI)
8529 01:21:13.757910 u2DelayCellOfst[10]=13 cells (4 PI)
8530 01:21:13.760947 u2DelayCellOfst[11]=3 cells (1 PI)
8531 01:21:13.763830 u2DelayCellOfst[12]=13 cells (4 PI)
8532 01:21:13.767682 u2DelayCellOfst[13]=16 cells (5 PI)
8533 01:21:13.770788 u2DelayCellOfst[14]=16 cells (5 PI)
8534 01:21:13.773914 u2DelayCellOfst[15]=16 cells (5 PI)
8535 01:21:13.777472 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8536 01:21:13.783717 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8537 01:21:13.783882 DramC Write-DBI on
8538 01:21:13.783980 ==
8539 01:21:13.787478 Dram Type= 6, Freq= 0, CH_1, rank 0
8540 01:21:13.790625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8541 01:21:13.793722 ==
8542 01:21:13.793847
8543 01:21:13.793940
8544 01:21:13.794034 TX Vref Scan disable
8545 01:21:13.797619 == TX Byte 0 ==
8546 01:21:13.800703 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8547 01:21:13.803879 == TX Byte 1 ==
8548 01:21:13.806982 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8549 01:21:13.810688 DramC Write-DBI off
8550 01:21:13.810815
8551 01:21:13.810909 [DATLAT]
8552 01:21:13.810997 Freq=1600, CH1 RK0
8553 01:21:13.811080
8554 01:21:13.813917 DATLAT Default: 0xf
8555 01:21:13.814024 0, 0xFFFF, sum = 0
8556 01:21:13.817104 1, 0xFFFF, sum = 0
8557 01:21:13.817223 2, 0xFFFF, sum = 0
8558 01:21:13.820567 3, 0xFFFF, sum = 0
8559 01:21:13.824136 4, 0xFFFF, sum = 0
8560 01:21:13.824304 5, 0xFFFF, sum = 0
8561 01:21:13.827053 6, 0xFFFF, sum = 0
8562 01:21:13.827160 7, 0xFFFF, sum = 0
8563 01:21:13.830530 8, 0xFFFF, sum = 0
8564 01:21:13.830631 9, 0xFFFF, sum = 0
8565 01:21:13.834058 10, 0xFFFF, sum = 0
8566 01:21:13.834149 11, 0xFFFF, sum = 0
8567 01:21:13.837218 12, 0xFFFF, sum = 0
8568 01:21:13.837307 13, 0xFFFF, sum = 0
8569 01:21:13.840559 14, 0x0, sum = 1
8570 01:21:13.840687 15, 0x0, sum = 2
8571 01:21:13.843655 16, 0x0, sum = 3
8572 01:21:13.843746 17, 0x0, sum = 4
8573 01:21:13.847407 best_step = 15
8574 01:21:13.847501
8575 01:21:13.847588 ==
8576 01:21:13.850703 Dram Type= 6, Freq= 0, CH_1, rank 0
8577 01:21:13.853609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8578 01:21:13.853702 ==
8579 01:21:13.853787 RX Vref Scan: 1
8580 01:21:13.857233
8581 01:21:13.857320 Set Vref Range= 24 -> 127
8582 01:21:13.857406
8583 01:21:13.860302 RX Vref 24 -> 127, step: 1
8584 01:21:13.860391
8585 01:21:13.864028 RX Delay 27 -> 252, step: 4
8586 01:21:13.864164
8587 01:21:13.867604 Set Vref, RX VrefLevel [Byte0]: 24
8588 01:21:13.870760 [Byte1]: 24
8589 01:21:13.870911
8590 01:21:13.873760 Set Vref, RX VrefLevel [Byte0]: 25
8591 01:21:13.877005 [Byte1]: 25
8592 01:21:13.877099
8593 01:21:13.880443 Set Vref, RX VrefLevel [Byte0]: 26
8594 01:21:13.883644 [Byte1]: 26
8595 01:21:13.887198
8596 01:21:13.887302 Set Vref, RX VrefLevel [Byte0]: 27
8597 01:21:13.890566 [Byte1]: 27
8598 01:21:13.894925
8599 01:21:13.895027 Set Vref, RX VrefLevel [Byte0]: 28
8600 01:21:13.898095 [Byte1]: 28
8601 01:21:13.902461
8602 01:21:13.902578 Set Vref, RX VrefLevel [Byte0]: 29
8603 01:21:13.906141 [Byte1]: 29
8604 01:21:13.909995
8605 01:21:13.910093 Set Vref, RX VrefLevel [Byte0]: 30
8606 01:21:13.913164 [Byte1]: 30
8607 01:21:13.917893
8608 01:21:13.917993 Set Vref, RX VrefLevel [Byte0]: 31
8609 01:21:13.921056 [Byte1]: 31
8610 01:21:13.925338
8611 01:21:13.925439 Set Vref, RX VrefLevel [Byte0]: 32
8612 01:21:13.928258 [Byte1]: 32
8613 01:21:13.932848
8614 01:21:13.932950 Set Vref, RX VrefLevel [Byte0]: 33
8615 01:21:13.935896 [Byte1]: 33
8616 01:21:13.939940
8617 01:21:13.940042 Set Vref, RX VrefLevel [Byte0]: 34
8618 01:21:13.943837 [Byte1]: 34
8619 01:21:13.947641
8620 01:21:13.947744 Set Vref, RX VrefLevel [Byte0]: 35
8621 01:21:13.950761 [Byte1]: 35
8622 01:21:13.955046
8623 01:21:13.955147 Set Vref, RX VrefLevel [Byte0]: 36
8624 01:21:13.958537 [Byte1]: 36
8625 01:21:13.962823
8626 01:21:13.962925 Set Vref, RX VrefLevel [Byte0]: 37
8627 01:21:13.966504 [Byte1]: 37
8628 01:21:13.970125
8629 01:21:13.970254 Set Vref, RX VrefLevel [Byte0]: 38
8630 01:21:13.973656 [Byte1]: 38
8631 01:21:13.977898
8632 01:21:13.978004 Set Vref, RX VrefLevel [Byte0]: 39
8633 01:21:13.981282 [Byte1]: 39
8634 01:21:13.985700
8635 01:21:13.985807 Set Vref, RX VrefLevel [Byte0]: 40
8636 01:21:13.988888 [Byte1]: 40
8637 01:21:13.992944
8638 01:21:13.993049 Set Vref, RX VrefLevel [Byte0]: 41
8639 01:21:13.996190 [Byte1]: 41
8640 01:21:14.000312
8641 01:21:14.000414 Set Vref, RX VrefLevel [Byte0]: 42
8642 01:21:14.003959 [Byte1]: 42
8643 01:21:14.008319
8644 01:21:14.008434 Set Vref, RX VrefLevel [Byte0]: 43
8645 01:21:14.010978 [Byte1]: 43
8646 01:21:14.015627
8647 01:21:14.015730 Set Vref, RX VrefLevel [Byte0]: 44
8648 01:21:14.018772 [Byte1]: 44
8649 01:21:14.023338
8650 01:21:14.023445 Set Vref, RX VrefLevel [Byte0]: 45
8651 01:21:14.026558 [Byte1]: 45
8652 01:21:14.030568
8653 01:21:14.030666 Set Vref, RX VrefLevel [Byte0]: 46
8654 01:21:14.033527 [Byte1]: 46
8655 01:21:14.038106
8656 01:21:14.038221 Set Vref, RX VrefLevel [Byte0]: 47
8657 01:21:14.041561 [Byte1]: 47
8658 01:21:14.045652
8659 01:21:14.045755 Set Vref, RX VrefLevel [Byte0]: 48
8660 01:21:14.048975 [Byte1]: 48
8661 01:21:14.053311
8662 01:21:14.053415 Set Vref, RX VrefLevel [Byte0]: 49
8663 01:21:14.056298 [Byte1]: 49
8664 01:21:14.061029
8665 01:21:14.061141 Set Vref, RX VrefLevel [Byte0]: 50
8666 01:21:14.063687 [Byte1]: 50
8667 01:21:14.068404
8668 01:21:14.068523 Set Vref, RX VrefLevel [Byte0]: 51
8669 01:21:14.071740 [Byte1]: 51
8670 01:21:14.076383
8671 01:21:14.076496 Set Vref, RX VrefLevel [Byte0]: 52
8672 01:21:14.078903 [Byte1]: 52
8673 01:21:14.083046
8674 01:21:14.083155 Set Vref, RX VrefLevel [Byte0]: 53
8675 01:21:14.086714 [Byte1]: 53
8676 01:21:14.090731
8677 01:21:14.090839 Set Vref, RX VrefLevel [Byte0]: 54
8678 01:21:14.094530 [Byte1]: 54
8679 01:21:14.098332
8680 01:21:14.098447 Set Vref, RX VrefLevel [Byte0]: 55
8681 01:21:14.101903 [Byte1]: 55
8682 01:21:14.105892
8683 01:21:14.105992 Set Vref, RX VrefLevel [Byte0]: 56
8684 01:21:14.109239 [Byte1]: 56
8685 01:21:14.113604
8686 01:21:14.113720 Set Vref, RX VrefLevel [Byte0]: 57
8687 01:21:14.116580 [Byte1]: 57
8688 01:21:14.121065
8689 01:21:14.121169 Set Vref, RX VrefLevel [Byte0]: 58
8690 01:21:14.124431 [Byte1]: 58
8691 01:21:14.128932
8692 01:21:14.129034 Set Vref, RX VrefLevel [Byte0]: 59
8693 01:21:14.131796 [Byte1]: 59
8694 01:21:14.136277
8695 01:21:14.136381 Set Vref, RX VrefLevel [Byte0]: 60
8696 01:21:14.139356 [Byte1]: 60
8697 01:21:14.143966
8698 01:21:14.144081 Set Vref, RX VrefLevel [Byte0]: 61
8699 01:21:14.147073 [Byte1]: 61
8700 01:21:14.151009
8701 01:21:14.151145 Set Vref, RX VrefLevel [Byte0]: 62
8702 01:21:14.154631 [Byte1]: 62
8703 01:21:14.158601
8704 01:21:14.158707 Set Vref, RX VrefLevel [Byte0]: 63
8705 01:21:14.162164 [Byte1]: 63
8706 01:21:14.166109
8707 01:21:14.166225 Set Vref, RX VrefLevel [Byte0]: 64
8708 01:21:14.169768 [Byte1]: 64
8709 01:21:14.173954
8710 01:21:14.174061 Set Vref, RX VrefLevel [Byte0]: 65
8711 01:21:14.177066 [Byte1]: 65
8712 01:21:14.181133
8713 01:21:14.181330 Set Vref, RX VrefLevel [Byte0]: 66
8714 01:21:14.184499 [Byte1]: 66
8715 01:21:14.188488
8716 01:21:14.188589 Set Vref, RX VrefLevel [Byte0]: 67
8717 01:21:14.191808 [Byte1]: 67
8718 01:21:14.196248
8719 01:21:14.196353 Set Vref, RX VrefLevel [Byte0]: 68
8720 01:21:14.199681 [Byte1]: 68
8721 01:21:14.203676
8722 01:21:14.203776 Set Vref, RX VrefLevel [Byte0]: 69
8723 01:21:14.207035 [Byte1]: 69
8724 01:21:14.211203
8725 01:21:14.211337 Set Vref, RX VrefLevel [Byte0]: 70
8726 01:21:14.214488 [Byte1]: 70
8727 01:21:14.218941
8728 01:21:14.219040 Set Vref, RX VrefLevel [Byte0]: 71
8729 01:21:14.221973 [Byte1]: 71
8730 01:21:14.226444
8731 01:21:14.226556 Set Vref, RX VrefLevel [Byte0]: 72
8732 01:21:14.229476 [Byte1]: 72
8733 01:21:14.233837
8734 01:21:14.233940 Set Vref, RX VrefLevel [Byte0]: 73
8735 01:21:14.237576 [Byte1]: 73
8736 01:21:14.241790
8737 01:21:14.241894 Set Vref, RX VrefLevel [Byte0]: 74
8738 01:21:14.245075 [Byte1]: 74
8739 01:21:14.249101
8740 01:21:14.249201 Set Vref, RX VrefLevel [Byte0]: 75
8741 01:21:14.252210 [Byte1]: 75
8742 01:21:14.256325
8743 01:21:14.256427 Set Vref, RX VrefLevel [Byte0]: 76
8744 01:21:14.259822 [Byte1]: 76
8745 01:21:14.264339
8746 01:21:14.264448 Set Vref, RX VrefLevel [Byte0]: 77
8747 01:21:14.267394 [Byte1]: 77
8748 01:21:14.271576
8749 01:21:14.271683 Final RX Vref Byte 0 = 60 to rank0
8750 01:21:14.274833 Final RX Vref Byte 1 = 56 to rank0
8751 01:21:14.278571 Final RX Vref Byte 0 = 60 to rank1
8752 01:21:14.281801 Final RX Vref Byte 1 = 56 to rank1==
8753 01:21:14.284727 Dram Type= 6, Freq= 0, CH_1, rank 0
8754 01:21:14.291290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8755 01:21:14.291423 ==
8756 01:21:14.291529 DQS Delay:
8757 01:21:14.291591 DQS0 = 0, DQS1 = 0
8758 01:21:14.294770 DQM Delay:
8759 01:21:14.294859 DQM0 = 134, DQM1 = 131
8760 01:21:14.297821 DQ Delay:
8761 01:21:14.301570 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8762 01:21:14.304733 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =134
8763 01:21:14.308120 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
8764 01:21:14.311741 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8765 01:21:14.311841
8766 01:21:14.311908
8767 01:21:14.311968
8768 01:21:14.314745 [DramC_TX_OE_Calibration] TA2
8769 01:21:14.318047 Original DQ_B0 (3 6) =30, OEN = 27
8770 01:21:14.321248 Original DQ_B1 (3 6) =30, OEN = 27
8771 01:21:14.324837 24, 0x0, End_B0=24 End_B1=24
8772 01:21:14.324943 25, 0x0, End_B0=25 End_B1=25
8773 01:21:14.328074 26, 0x0, End_B0=26 End_B1=26
8774 01:21:14.331089 27, 0x0, End_B0=27 End_B1=27
8775 01:21:14.334668 28, 0x0, End_B0=28 End_B1=28
8776 01:21:14.337995 29, 0x0, End_B0=29 End_B1=29
8777 01:21:14.338091 30, 0x0, End_B0=30 End_B1=30
8778 01:21:14.340999 31, 0x4545, End_B0=30 End_B1=30
8779 01:21:14.344765 Byte0 end_step=30 best_step=27
8780 01:21:14.347903 Byte1 end_step=30 best_step=27
8781 01:21:14.351204 Byte0 TX OE(2T, 0.5T) = (3, 3)
8782 01:21:14.354272 Byte1 TX OE(2T, 0.5T) = (3, 3)
8783 01:21:14.354398
8784 01:21:14.354465
8785 01:21:14.361348 [DQSOSCAuto] RK0, (LSB)MR18= 0x1825, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
8786 01:21:14.364440 CH1 RK0: MR19=303, MR18=1825
8787 01:21:14.370848 CH1_RK0: MR19=0x303, MR18=0x1825, DQSOSC=391, MR23=63, INC=24, DEC=16
8788 01:21:14.370992
8789 01:21:14.374687 ----->DramcWriteLeveling(PI) begin...
8790 01:21:14.374784 ==
8791 01:21:14.377856 Dram Type= 6, Freq= 0, CH_1, rank 1
8792 01:21:14.380892 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8793 01:21:14.380990 ==
8794 01:21:14.384503 Write leveling (Byte 0): 26 => 26
8795 01:21:14.387790 Write leveling (Byte 1): 28 => 28
8796 01:21:14.390978 DramcWriteLeveling(PI) end<-----
8797 01:21:14.391081
8798 01:21:14.391146 ==
8799 01:21:14.394044 Dram Type= 6, Freq= 0, CH_1, rank 1
8800 01:21:14.397815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8801 01:21:14.397916 ==
8802 01:21:14.400804 [Gating] SW mode calibration
8803 01:21:14.407491 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8804 01:21:14.413957 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8805 01:21:14.417337 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 01:21:14.423857 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 01:21:14.427233 1 4 8 | B1->B0 | 2828 2323 | 1 0 | (0 0) (0 0)
8808 01:21:14.430747 1 4 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
8809 01:21:14.437110 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8810 01:21:14.440747 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8811 01:21:14.444161 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8812 01:21:14.450397 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8813 01:21:14.453984 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8814 01:21:14.457023 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8815 01:21:14.463513 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8816 01:21:14.467278 1 5 12 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
8817 01:21:14.470542 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8818 01:21:14.473428 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8819 01:21:14.480258 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8820 01:21:14.483635 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8821 01:21:14.487241 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 01:21:14.493552 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 01:21:14.496765 1 6 8 | B1->B0 | 3838 2323 | 1 0 | (0 0) (0 0)
8824 01:21:14.500180 1 6 12 | B1->B0 | 4545 3f3f | 0 0 | (0 0) (1 1)
8825 01:21:14.506774 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8826 01:21:14.509924 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 01:21:14.513050 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8828 01:21:14.519946 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8829 01:21:14.523282 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 01:21:14.526558 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8831 01:21:14.533459 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8832 01:21:14.536587 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8833 01:21:14.539598 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8834 01:21:14.546188 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 01:21:14.549793 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 01:21:14.553138 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 01:21:14.559801 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 01:21:14.563066 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 01:21:14.566526 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 01:21:14.572828 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 01:21:14.576779 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 01:21:14.579693 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 01:21:14.586143 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 01:21:14.589933 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 01:21:14.593060 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 01:21:14.599417 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8847 01:21:14.602999 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8848 01:21:14.606243 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8849 01:21:14.609611 Total UI for P1: 0, mck2ui 16
8850 01:21:14.613247 best dqsien dly found for B1: ( 1, 9, 6)
8851 01:21:14.616438 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 01:21:14.619591 Total UI for P1: 0, mck2ui 16
8853 01:21:14.622737 best dqsien dly found for B0: ( 1, 9, 12)
8854 01:21:14.626544 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8855 01:21:14.633017 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8856 01:21:14.633145
8857 01:21:14.636347 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8858 01:21:14.639899 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8859 01:21:14.642594 [Gating] SW calibration Done
8860 01:21:14.642692 ==
8861 01:21:14.646160 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 01:21:14.649434 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 01:21:14.649531 ==
8864 01:21:14.652801 RX Vref Scan: 0
8865 01:21:14.652888
8866 01:21:14.652954 RX Vref 0 -> 0, step: 1
8867 01:21:14.653014
8868 01:21:14.656543 RX Delay 0 -> 252, step: 8
8869 01:21:14.659432 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8870 01:21:14.662874 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8871 01:21:14.669253 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8872 01:21:14.672670 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8873 01:21:14.676032 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8874 01:21:14.679214 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8875 01:21:14.683249 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8876 01:21:14.689445 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8877 01:21:14.692865 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8878 01:21:14.696077 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8879 01:21:14.699164 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8880 01:21:14.702297 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8881 01:21:14.709391 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8882 01:21:14.712592 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8883 01:21:14.715670 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8884 01:21:14.719385 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8885 01:21:14.719507 ==
8886 01:21:14.722318 Dram Type= 6, Freq= 0, CH_1, rank 1
8887 01:21:14.728811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8888 01:21:14.728958 ==
8889 01:21:14.729050 DQS Delay:
8890 01:21:14.732444 DQS0 = 0, DQS1 = 0
8891 01:21:14.732551 DQM Delay:
8892 01:21:14.735667 DQM0 = 136, DQM1 = 133
8893 01:21:14.735774 DQ Delay:
8894 01:21:14.738853 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8895 01:21:14.742021 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8896 01:21:14.745550 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8897 01:21:14.748976 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8898 01:21:14.749092
8899 01:21:14.749181
8900 01:21:14.749269 ==
8901 01:21:14.752554 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 01:21:14.758787 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 01:21:14.758934 ==
8904 01:21:14.759028
8905 01:21:14.759116
8906 01:21:14.759199 TX Vref Scan disable
8907 01:21:14.762157 == TX Byte 0 ==
8908 01:21:14.765332 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8909 01:21:14.768620 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8910 01:21:14.772418 == TX Byte 1 ==
8911 01:21:14.775566 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8912 01:21:14.778646 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8913 01:21:14.782230 ==
8914 01:21:14.785546 Dram Type= 6, Freq= 0, CH_1, rank 1
8915 01:21:14.788900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8916 01:21:14.789022 ==
8917 01:21:14.800711
8918 01:21:14.804215 TX Vref early break, caculate TX vref
8919 01:21:14.807372 TX Vref=16, minBit 0, minWin=23, winSum=382
8920 01:21:14.810801 TX Vref=18, minBit 6, minWin=23, winSum=392
8921 01:21:14.813902 TX Vref=20, minBit 0, minWin=23, winSum=400
8922 01:21:14.817261 TX Vref=22, minBit 1, minWin=24, winSum=412
8923 01:21:14.820983 TX Vref=24, minBit 0, minWin=25, winSum=416
8924 01:21:14.827929 TX Vref=26, minBit 0, minWin=25, winSum=422
8925 01:21:14.830558 TX Vref=28, minBit 0, minWin=24, winSum=427
8926 01:21:14.833910 TX Vref=30, minBit 1, minWin=25, winSum=423
8927 01:21:14.837120 TX Vref=32, minBit 6, minWin=24, winSum=412
8928 01:21:14.840898 TX Vref=34, minBit 0, minWin=24, winSum=403
8929 01:21:14.847040 [TxChooseVref] Worse bit 1, Min win 25, Win sum 423, Final Vref 30
8930 01:21:14.847150
8931 01:21:14.850859 Final TX Range 0 Vref 30
8932 01:21:14.850949
8933 01:21:14.851013 ==
8934 01:21:14.853941 Dram Type= 6, Freq= 0, CH_1, rank 1
8935 01:21:14.857411 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8936 01:21:14.857497 ==
8937 01:21:14.857562
8938 01:21:14.857621
8939 01:21:14.860806 TX Vref Scan disable
8940 01:21:14.867301 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8941 01:21:14.867423 == TX Byte 0 ==
8942 01:21:14.870241 u2DelayCellOfst[0]=20 cells (6 PI)
8943 01:21:14.874062 u2DelayCellOfst[1]=13 cells (4 PI)
8944 01:21:14.877359 u2DelayCellOfst[2]=0 cells (0 PI)
8945 01:21:14.880621 u2DelayCellOfst[3]=6 cells (2 PI)
8946 01:21:14.883785 u2DelayCellOfst[4]=10 cells (3 PI)
8947 01:21:14.887110 u2DelayCellOfst[5]=16 cells (5 PI)
8948 01:21:14.890260 u2DelayCellOfst[6]=16 cells (5 PI)
8949 01:21:14.893555 u2DelayCellOfst[7]=6 cells (2 PI)
8950 01:21:14.896870 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8951 01:21:14.900410 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8952 01:21:14.903443 == TX Byte 1 ==
8953 01:21:14.903561 u2DelayCellOfst[8]=0 cells (0 PI)
8954 01:21:14.906615 u2DelayCellOfst[9]=3 cells (1 PI)
8955 01:21:14.910186 u2DelayCellOfst[10]=10 cells (3 PI)
8956 01:21:14.913571 u2DelayCellOfst[11]=6 cells (2 PI)
8957 01:21:14.917015 u2DelayCellOfst[12]=13 cells (4 PI)
8958 01:21:14.920233 u2DelayCellOfst[13]=16 cells (5 PI)
8959 01:21:14.923239 u2DelayCellOfst[14]=13 cells (4 PI)
8960 01:21:14.926781 u2DelayCellOfst[15]=16 cells (5 PI)
8961 01:21:14.930011 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8962 01:21:14.936399 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8963 01:21:14.936527 DramC Write-DBI on
8964 01:21:14.936598 ==
8965 01:21:14.940087 Dram Type= 6, Freq= 0, CH_1, rank 1
8966 01:21:14.943114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8967 01:21:14.946625 ==
8968 01:21:14.946753
8969 01:21:14.946833
8970 01:21:14.946894 TX Vref Scan disable
8971 01:21:14.950037 == TX Byte 0 ==
8972 01:21:14.953345 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8973 01:21:14.957221 == TX Byte 1 ==
8974 01:21:14.960285 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8975 01:21:14.963625 DramC Write-DBI off
8976 01:21:14.963724
8977 01:21:14.963794 [DATLAT]
8978 01:21:14.963886 Freq=1600, CH1 RK1
8979 01:21:14.963944
8980 01:21:14.966719 DATLAT Default: 0xf
8981 01:21:14.966806 0, 0xFFFF, sum = 0
8982 01:21:14.969832 1, 0xFFFF, sum = 0
8983 01:21:14.973264 2, 0xFFFF, sum = 0
8984 01:21:14.973363 3, 0xFFFF, sum = 0
8985 01:21:14.976494 4, 0xFFFF, sum = 0
8986 01:21:14.976584 5, 0xFFFF, sum = 0
8987 01:21:14.980076 6, 0xFFFF, sum = 0
8988 01:21:14.980166 7, 0xFFFF, sum = 0
8989 01:21:14.983246 8, 0xFFFF, sum = 0
8990 01:21:14.983335 9, 0xFFFF, sum = 0
8991 01:21:14.986748 10, 0xFFFF, sum = 0
8992 01:21:14.986844 11, 0xFFFF, sum = 0
8993 01:21:14.990004 12, 0xFFFF, sum = 0
8994 01:21:14.990093 13, 0xFFFF, sum = 0
8995 01:21:14.993318 14, 0x0, sum = 1
8996 01:21:14.993411 15, 0x0, sum = 2
8997 01:21:14.996560 16, 0x0, sum = 3
8998 01:21:14.996651 17, 0x0, sum = 4
8999 01:21:14.999826 best_step = 15
9000 01:21:14.999914
9001 01:21:14.999979 ==
9002 01:21:15.003684 Dram Type= 6, Freq= 0, CH_1, rank 1
9003 01:21:15.006767 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9004 01:21:15.006861 ==
9005 01:21:15.006928 RX Vref Scan: 0
9006 01:21:15.009838
9007 01:21:15.009926 RX Vref 0 -> 0, step: 1
9008 01:21:15.009992
9009 01:21:15.013711 RX Delay 19 -> 252, step: 4
9010 01:21:15.016884 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9011 01:21:15.023680 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
9012 01:21:15.026842 iDelay=195, Bit 2, Center 122 (75 ~ 170) 96
9013 01:21:15.029958 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9014 01:21:15.033245 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9015 01:21:15.036510 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9016 01:21:15.039717 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9017 01:21:15.046426 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9018 01:21:15.049640 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9019 01:21:15.052850 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9020 01:21:15.056321 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9021 01:21:15.060285 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9022 01:21:15.066329 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9023 01:21:15.069745 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9024 01:21:15.073188 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9025 01:21:15.076403 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9026 01:21:15.076502 ==
9027 01:21:15.079516 Dram Type= 6, Freq= 0, CH_1, rank 1
9028 01:21:15.086759 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9029 01:21:15.086893 ==
9030 01:21:15.086960 DQS Delay:
9031 01:21:15.089989 DQS0 = 0, DQS1 = 0
9032 01:21:15.090081 DQM Delay:
9033 01:21:15.093050 DQM0 = 134, DQM1 = 130
9034 01:21:15.093140 DQ Delay:
9035 01:21:15.096424 DQ0 =138, DQ1 =132, DQ2 =122, DQ3 =130
9036 01:21:15.099712 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9037 01:21:15.103294 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
9038 01:21:15.106605 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
9039 01:21:15.106703
9040 01:21:15.106770
9041 01:21:15.106829
9042 01:21:15.109740 [DramC_TX_OE_Calibration] TA2
9043 01:21:15.112922 Original DQ_B0 (3 6) =30, OEN = 27
9044 01:21:15.116620 Original DQ_B1 (3 6) =30, OEN = 27
9045 01:21:15.119895 24, 0x0, End_B0=24 End_B1=24
9046 01:21:15.119992 25, 0x0, End_B0=25 End_B1=25
9047 01:21:15.123039 26, 0x0, End_B0=26 End_B1=26
9048 01:21:15.126124 27, 0x0, End_B0=27 End_B1=27
9049 01:21:15.129888 28, 0x0, End_B0=28 End_B1=28
9050 01:21:15.133007 29, 0x0, End_B0=29 End_B1=29
9051 01:21:15.133110 30, 0x0, End_B0=30 End_B1=30
9052 01:21:15.136339 31, 0x4141, End_B0=30 End_B1=30
9053 01:21:15.139384 Byte0 end_step=30 best_step=27
9054 01:21:15.143239 Byte1 end_step=30 best_step=27
9055 01:21:15.146501 Byte0 TX OE(2T, 0.5T) = (3, 3)
9056 01:21:15.149573 Byte1 TX OE(2T, 0.5T) = (3, 3)
9057 01:21:15.149693
9058 01:21:15.149760
9059 01:21:15.155967 [DQSOSCAuto] RK1, (LSB)MR18= 0x2005, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
9060 01:21:15.159592 CH1 RK1: MR19=303, MR18=2005
9061 01:21:15.166232 CH1_RK1: MR19=0x303, MR18=0x2005, DQSOSC=393, MR23=63, INC=23, DEC=15
9062 01:21:15.169207 [RxdqsGatingPostProcess] freq 1600
9063 01:21:15.172864 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9064 01:21:15.176402 best DQS0 dly(2T, 0.5T) = (1, 1)
9065 01:21:15.179468 best DQS1 dly(2T, 0.5T) = (1, 1)
9066 01:21:15.182495 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9067 01:21:15.185883 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9068 01:21:15.189323 best DQS0 dly(2T, 0.5T) = (1, 1)
9069 01:21:15.192426 best DQS1 dly(2T, 0.5T) = (1, 1)
9070 01:21:15.195815 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9071 01:21:15.199230 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9072 01:21:15.202916 Pre-setting of DQS Precalculation
9073 01:21:15.206089 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9074 01:21:15.212794 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9075 01:21:15.222721 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9076 01:21:15.222864
9077 01:21:15.222934
9078 01:21:15.225494 [Calibration Summary] 3200 Mbps
9079 01:21:15.225686 CH 0, Rank 0
9080 01:21:15.229431 SW Impedance : PASS
9081 01:21:15.229559 DUTY Scan : NO K
9082 01:21:15.232645 ZQ Calibration : PASS
9083 01:21:15.232762 Jitter Meter : NO K
9084 01:21:15.235646 CBT Training : PASS
9085 01:21:15.239568 Write leveling : PASS
9086 01:21:15.239703 RX DQS gating : PASS
9087 01:21:15.242058 RX DQ/DQS(RDDQC) : PASS
9088 01:21:15.246011 TX DQ/DQS : PASS
9089 01:21:15.246139 RX DATLAT : PASS
9090 01:21:15.249080 RX DQ/DQS(Engine): PASS
9091 01:21:15.252160 TX OE : PASS
9092 01:21:15.252285 All Pass.
9093 01:21:15.252378
9094 01:21:15.252466 CH 0, Rank 1
9095 01:21:15.255458 SW Impedance : PASS
9096 01:21:15.258794 DUTY Scan : NO K
9097 01:21:15.258913 ZQ Calibration : PASS
9098 01:21:15.261856 Jitter Meter : NO K
9099 01:21:15.265618 CBT Training : PASS
9100 01:21:15.265750 Write leveling : PASS
9101 01:21:15.268540 RX DQS gating : PASS
9102 01:21:15.271891 RX DQ/DQS(RDDQC) : PASS
9103 01:21:15.272023 TX DQ/DQS : PASS
9104 01:21:15.275239 RX DATLAT : PASS
9105 01:21:15.278921 RX DQ/DQS(Engine): PASS
9106 01:21:15.279044 TX OE : PASS
9107 01:21:15.281856 All Pass.
9108 01:21:15.281959
9109 01:21:15.282048 CH 1, Rank 0
9110 01:21:15.285490 SW Impedance : PASS
9111 01:21:15.285604 DUTY Scan : NO K
9112 01:21:15.288804 ZQ Calibration : PASS
9113 01:21:15.292001 Jitter Meter : NO K
9114 01:21:15.292116 CBT Training : PASS
9115 01:21:15.295136 Write leveling : PASS
9116 01:21:15.295246 RX DQS gating : PASS
9117 01:21:15.298296 RX DQ/DQS(RDDQC) : PASS
9118 01:21:15.301990 TX DQ/DQS : PASS
9119 01:21:15.302110 RX DATLAT : PASS
9120 01:21:15.304918 RX DQ/DQS(Engine): PASS
9121 01:21:15.308514 TX OE : PASS
9122 01:21:15.308639 All Pass.
9123 01:21:15.308730
9124 01:21:15.308813 CH 1, Rank 1
9125 01:21:15.311845 SW Impedance : PASS
9126 01:21:15.315443 DUTY Scan : NO K
9127 01:21:15.315546 ZQ Calibration : PASS
9128 01:21:15.318618 Jitter Meter : NO K
9129 01:21:15.321698 CBT Training : PASS
9130 01:21:15.321793 Write leveling : PASS
9131 01:21:15.325193 RX DQS gating : PASS
9132 01:21:15.328445 RX DQ/DQS(RDDQC) : PASS
9133 01:21:15.328541 TX DQ/DQS : PASS
9134 01:21:15.331847 RX DATLAT : PASS
9135 01:21:15.335007 RX DQ/DQS(Engine): PASS
9136 01:21:15.335101 TX OE : PASS
9137 01:21:15.335168 All Pass.
9138 01:21:15.338151
9139 01:21:15.338237 DramC Write-DBI on
9140 01:21:15.341554 PER_BANK_REFRESH: Hybrid Mode
9141 01:21:15.341647 TX_TRACKING: ON
9142 01:21:15.351446 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9143 01:21:15.358684 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9144 01:21:15.368462 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9145 01:21:15.371239 [FAST_K] Save calibration result to emmc
9146 01:21:15.374876 sync common calibartion params.
9147 01:21:15.374992 sync cbt_mode0:1, 1:1
9148 01:21:15.378322 dram_init: ddr_geometry: 2
9149 01:21:15.381336 dram_init: ddr_geometry: 2
9150 01:21:15.381440 dram_init: ddr_geometry: 2
9151 01:21:15.384497 0:dram_rank_size:100000000
9152 01:21:15.387656 1:dram_rank_size:100000000
9153 01:21:15.394416 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9154 01:21:15.394553 DFS_SHUFFLE_HW_MODE: ON
9155 01:21:15.397639 dramc_set_vcore_voltage set vcore to 725000
9156 01:21:15.401453 Read voltage for 1600, 0
9157 01:21:15.401561 Vio18 = 0
9158 01:21:15.404597 Vcore = 725000
9159 01:21:15.404692 Vdram = 0
9160 01:21:15.404759 Vddq = 0
9161 01:21:15.407779 Vmddr = 0
9162 01:21:15.407870 switch to 3200 Mbps bootup
9163 01:21:15.411554 [DramcRunTimeConfig]
9164 01:21:15.411650 PHYPLL
9165 01:21:15.414254 DPM_CONTROL_AFTERK: ON
9166 01:21:15.414369 PER_BANK_REFRESH: ON
9167 01:21:15.417688 REFRESH_OVERHEAD_REDUCTION: ON
9168 01:21:15.421079 CMD_PICG_NEW_MODE: OFF
9169 01:21:15.421193 XRTWTW_NEW_MODE: ON
9170 01:21:15.424594 XRTRTR_NEW_MODE: ON
9171 01:21:15.424706 TX_TRACKING: ON
9172 01:21:15.427737 RDSEL_TRACKING: OFF
9173 01:21:15.430942 DQS Precalculation for DVFS: ON
9174 01:21:15.431049 RX_TRACKING: OFF
9175 01:21:15.434549 HW_GATING DBG: ON
9176 01:21:15.434672 ZQCS_ENABLE_LP4: ON
9177 01:21:15.437883 RX_PICG_NEW_MODE: ON
9178 01:21:15.438028 TX_PICG_NEW_MODE: ON
9179 01:21:15.441038 ENABLE_RX_DCM_DPHY: ON
9180 01:21:15.444161 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9181 01:21:15.447341 DUMMY_READ_FOR_TRACKING: OFF
9182 01:21:15.447464 !!! SPM_CONTROL_AFTERK: OFF
9183 01:21:15.450924 !!! SPM could not control APHY
9184 01:21:15.454156 IMPEDANCE_TRACKING: ON
9185 01:21:15.454314 TEMP_SENSOR: ON
9186 01:21:15.457497 HW_SAVE_FOR_SR: OFF
9187 01:21:15.460863 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9188 01:21:15.464033 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9189 01:21:15.464137 Read ODT Tracking: ON
9190 01:21:15.467348 Refresh Rate DeBounce: ON
9191 01:21:15.470874 DFS_NO_QUEUE_FLUSH: ON
9192 01:21:15.474424 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9193 01:21:15.477105 ENABLE_DFS_RUNTIME_MRW: OFF
9194 01:21:15.477208 DDR_RESERVE_NEW_MODE: ON
9195 01:21:15.480892 MR_CBT_SWITCH_FREQ: ON
9196 01:21:15.483781 =========================
9197 01:21:15.501456 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9198 01:21:15.504652 dram_init: ddr_geometry: 2
9199 01:21:15.523194 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9200 01:21:15.525969 dram_init: dram init end (result: 0)
9201 01:21:15.532405 DRAM-K: Full calibration passed in 24438 msecs
9202 01:21:15.536041 MRC: failed to locate region type 0.
9203 01:21:15.536168 DRAM rank0 size:0x100000000,
9204 01:21:15.539125 DRAM rank1 size=0x100000000
9205 01:21:15.549603 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9206 01:21:15.556142 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9207 01:21:15.562586 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9208 01:21:15.569035 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9209 01:21:15.572764 DRAM rank0 size:0x100000000,
9210 01:21:15.575602 DRAM rank1 size=0x100000000
9211 01:21:15.575714 CBMEM:
9212 01:21:15.579163 IMD: root @ 0xfffff000 254 entries.
9213 01:21:15.582598 IMD: root @ 0xffffec00 62 entries.
9214 01:21:15.585672 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9215 01:21:15.589147 WARNING: RO_VPD is uninitialized or empty.
9216 01:21:15.595929 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9217 01:21:15.602815 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9218 01:21:15.615586 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9219 01:21:15.626955 BS: romstage times (exec / console): total (unknown) / 23974 ms
9220 01:21:15.627106
9221 01:21:15.627173
9222 01:21:15.637190 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9223 01:21:15.640015 ARM64: Exception handlers installed.
9224 01:21:15.643455 ARM64: Testing exception
9225 01:21:15.646735 ARM64: Done test exception
9226 01:21:15.646868 Enumerating buses...
9227 01:21:15.649908 Show all devs... Before device enumeration.
9228 01:21:15.653855 Root Device: enabled 1
9229 01:21:15.656953 CPU_CLUSTER: 0: enabled 1
9230 01:21:15.657065 CPU: 00: enabled 1
9231 01:21:15.660130 Compare with tree...
9232 01:21:15.660235 Root Device: enabled 1
9233 01:21:15.663335 CPU_CLUSTER: 0: enabled 1
9234 01:21:15.666634 CPU: 00: enabled 1
9235 01:21:15.666756 Root Device scanning...
9236 01:21:15.669954 scan_static_bus for Root Device
9237 01:21:15.673610 CPU_CLUSTER: 0 enabled
9238 01:21:15.676818 scan_static_bus for Root Device done
9239 01:21:15.679982 scan_bus: bus Root Device finished in 8 msecs
9240 01:21:15.680097 done
9241 01:21:15.686945 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9242 01:21:15.690504 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9243 01:21:15.696431 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9244 01:21:15.700325 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9245 01:21:15.703104 Allocating resources...
9246 01:21:15.706725 Reading resources...
9247 01:21:15.710245 Root Device read_resources bus 0 link: 0
9248 01:21:15.710428 DRAM rank0 size:0x100000000,
9249 01:21:15.713461 DRAM rank1 size=0x100000000
9250 01:21:15.717105 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9251 01:21:15.719881 CPU: 00 missing read_resources
9252 01:21:15.723473 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9253 01:21:15.729919 Root Device read_resources bus 0 link: 0 done
9254 01:21:15.730064 Done reading resources.
9255 01:21:15.736993 Show resources in subtree (Root Device)...After reading.
9256 01:21:15.739678 Root Device child on link 0 CPU_CLUSTER: 0
9257 01:21:15.743215 CPU_CLUSTER: 0 child on link 0 CPU: 00
9258 01:21:15.752984 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9259 01:21:15.753136 CPU: 00
9260 01:21:15.756501 Root Device assign_resources, bus 0 link: 0
9261 01:21:15.759684 CPU_CLUSTER: 0 missing set_resources
9262 01:21:15.762929 Root Device assign_resources, bus 0 link: 0 done
9263 01:21:15.766267 Done setting resources.
9264 01:21:15.773319 Show resources in subtree (Root Device)...After assigning values.
9265 01:21:15.776461 Root Device child on link 0 CPU_CLUSTER: 0
9266 01:21:15.779542 CPU_CLUSTER: 0 child on link 0 CPU: 00
9267 01:21:15.789653 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9268 01:21:15.789854 CPU: 00
9269 01:21:15.792734 Done allocating resources.
9270 01:21:15.796198 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9271 01:21:15.799454 Enabling resources...
9272 01:21:15.799607 done.
9273 01:21:15.806294 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9274 01:21:15.806517 Initializing devices...
9275 01:21:15.809515 Root Device init
9276 01:21:15.809644 init hardware done!
9277 01:21:15.813101 0x00000018: ctrlr->caps
9278 01:21:15.816244 52.000 MHz: ctrlr->f_max
9279 01:21:15.816397 0.400 MHz: ctrlr->f_min
9280 01:21:15.819253 0x40ff8080: ctrlr->voltages
9281 01:21:15.819388 sclk: 390625
9282 01:21:15.822502 Bus Width = 1
9283 01:21:15.822627 sclk: 390625
9284 01:21:15.826231 Bus Width = 1
9285 01:21:15.826377 Early init status = 3
9286 01:21:15.832602 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9287 01:21:15.836209 in-header: 03 fc 00 00 01 00 00 00
9288 01:21:15.836361 in-data: 00
9289 01:21:15.842605 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9290 01:21:15.845891 in-header: 03 fd 00 00 00 00 00 00
9291 01:21:15.848884 in-data:
9292 01:21:15.852081 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9293 01:21:15.856636 in-header: 03 fc 00 00 01 00 00 00
9294 01:21:15.859510 in-data: 00
9295 01:21:15.862940 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9296 01:21:15.868259 in-header: 03 fd 00 00 00 00 00 00
9297 01:21:15.871686 in-data:
9298 01:21:15.875370 [SSUSB] Setting up USB HOST controller...
9299 01:21:15.878634 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9300 01:21:15.881779 [SSUSB] phy power-on done.
9301 01:21:15.884811 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9302 01:21:15.891618 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9303 01:21:15.895432 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9304 01:21:15.901746 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9305 01:21:15.908509 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9306 01:21:15.914856 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9307 01:21:15.921612 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9308 01:21:15.928357 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9309 01:21:15.931745 SPM: binary array size = 0x9dc
9310 01:21:15.934912 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9311 01:21:15.941216 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9312 01:21:15.948159 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9313 01:21:15.951194 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9314 01:21:15.957905 configure_display: Starting display init
9315 01:21:15.991901 anx7625_power_on_init: Init interface.
9316 01:21:15.994802 anx7625_disable_pd_protocol: Disabled PD feature.
9317 01:21:15.998075 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9318 01:21:16.026079 anx7625_start_dp_work: Secure OCM version=00
9319 01:21:16.029073 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9320 01:21:16.044471 sp_tx_get_edid_block: EDID Block = 1
9321 01:21:16.146763 Extracted contents:
9322 01:21:16.150111 header: 00 ff ff ff ff ff ff 00
9323 01:21:16.153173 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9324 01:21:16.156881 version: 01 04
9325 01:21:16.160364 basic params: 95 1f 11 78 0a
9326 01:21:16.163483 chroma info: 76 90 94 55 54 90 27 21 50 54
9327 01:21:16.167144 established: 00 00 00
9328 01:21:16.173547 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9329 01:21:16.176692 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9330 01:21:16.183025 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9331 01:21:16.190075 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9332 01:21:16.196575 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9333 01:21:16.199745 extensions: 00
9334 01:21:16.199868 checksum: fb
9335 01:21:16.199942
9336 01:21:16.203114 Manufacturer: IVO Model 57d Serial Number 0
9337 01:21:16.206669 Made week 0 of 2020
9338 01:21:16.206813 EDID version: 1.4
9339 01:21:16.209824 Digital display
9340 01:21:16.213342 6 bits per primary color channel
9341 01:21:16.213464 DisplayPort interface
9342 01:21:16.216816 Maximum image size: 31 cm x 17 cm
9343 01:21:16.219836 Gamma: 220%
9344 01:21:16.219946 Check DPMS levels
9345 01:21:16.223134 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9346 01:21:16.226363 First detailed timing is preferred timing
9347 01:21:16.229415 Established timings supported:
9348 01:21:16.233262 Standard timings supported:
9349 01:21:16.236568 Detailed timings
9350 01:21:16.239670 Hex of detail: 383680a07038204018303c0035ae10000019
9351 01:21:16.243167 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9352 01:21:16.249485 0780 0798 07c8 0820 hborder 0
9353 01:21:16.253180 0438 043b 0447 0458 vborder 0
9354 01:21:16.256438 -hsync -vsync
9355 01:21:16.256568 Did detailed timing
9356 01:21:16.262960 Hex of detail: 000000000000000000000000000000000000
9357 01:21:16.263105 Manufacturer-specified data, tag 0
9358 01:21:16.269516 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9359 01:21:16.272862 ASCII string: InfoVision
9360 01:21:16.276298 Hex of detail: 000000fe00523134304e574635205248200a
9361 01:21:16.279606 ASCII string: R140NWF5 RH
9362 01:21:16.279734 Checksum
9363 01:21:16.282532 Checksum: 0xfb (valid)
9364 01:21:16.285900 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9365 01:21:16.289331 DSI data_rate: 832800000 bps
9366 01:21:16.296108 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9367 01:21:16.299514 anx7625_parse_edid: pixelclock(138800).
9368 01:21:16.302669 hactive(1920), hsync(48), hfp(24), hbp(88)
9369 01:21:16.305835 vactive(1080), vsync(12), vfp(3), vbp(17)
9370 01:21:16.308960 anx7625_dsi_config: config dsi.
9371 01:21:16.315671 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9372 01:21:16.328828 anx7625_dsi_config: success to config DSI
9373 01:21:16.332125 anx7625_dp_start: MIPI phy setup OK.
9374 01:21:16.335146 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9375 01:21:16.339128 mtk_ddp_mode_set invalid vrefresh 60
9376 01:21:16.342182 main_disp_path_setup
9377 01:21:16.342313 ovl_layer_smi_id_en
9378 01:21:16.345405 ovl_layer_smi_id_en
9379 01:21:16.345513 ccorr_config
9380 01:21:16.345580 aal_config
9381 01:21:16.348569 gamma_config
9382 01:21:16.348668 postmask_config
9383 01:21:16.351697 dither_config
9384 01:21:16.355655 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9385 01:21:16.361804 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9386 01:21:16.365256 Root Device init finished in 552 msecs
9387 01:21:16.365372 CPU_CLUSTER: 0 init
9388 01:21:16.375291 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9389 01:21:16.378493 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9390 01:21:16.381739 APU_MBOX 0x190000b0 = 0x10001
9391 01:21:16.385245 APU_MBOX 0x190001b0 = 0x10001
9392 01:21:16.388831 APU_MBOX 0x190005b0 = 0x10001
9393 01:21:16.391900 APU_MBOX 0x190006b0 = 0x10001
9394 01:21:16.395347 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9395 01:21:16.407598 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9396 01:21:16.420212 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9397 01:21:16.426856 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9398 01:21:16.438538 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9399 01:21:16.447588 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9400 01:21:16.450754 CPU_CLUSTER: 0 init finished in 81 msecs
9401 01:21:16.454073 Devices initialized
9402 01:21:16.457772 Show all devs... After init.
9403 01:21:16.457898 Root Device: enabled 1
9404 01:21:16.460900 CPU_CLUSTER: 0: enabled 1
9405 01:21:16.464519 CPU: 00: enabled 1
9406 01:21:16.467673 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9407 01:21:16.470674 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9408 01:21:16.474488 ELOG: NV offset 0x57f000 size 0x1000
9409 01:21:16.481209 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9410 01:21:16.487349 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9411 01:21:16.490973 ELOG: Event(17) added with size 13 at 2024-04-23 01:17:05 UTC
9412 01:21:16.494029 out: cmd=0x121: 03 db 21 01 00 00 00 00
9413 01:21:16.497793 in-header: 03 f0 00 00 2c 00 00 00
9414 01:21:16.511075 in-data: 6f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9415 01:21:16.517855 ELOG: Event(A1) added with size 10 at 2024-04-23 01:17:05 UTC
9416 01:21:16.524564 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9417 01:21:16.530527 ELOG: Event(A0) added with size 9 at 2024-04-23 01:17:05 UTC
9418 01:21:16.534205 elog_add_boot_reason: Logged dev mode boot
9419 01:21:16.537130 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9420 01:21:16.540338 Finalize devices...
9421 01:21:16.540460 Devices finalized
9422 01:21:16.547022 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9423 01:21:16.550159 Writing coreboot table at 0xffe64000
9424 01:21:16.553721 0. 000000000010a000-0000000000113fff: RAMSTAGE
9425 01:21:16.557200 1. 0000000040000000-00000000400fffff: RAM
9426 01:21:16.563683 2. 0000000040100000-000000004032afff: RAMSTAGE
9427 01:21:16.567447 3. 000000004032b000-00000000545fffff: RAM
9428 01:21:16.570565 4. 0000000054600000-000000005465ffff: BL31
9429 01:21:16.573858 5. 0000000054660000-00000000ffe63fff: RAM
9430 01:21:16.580770 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9431 01:21:16.584012 7. 0000000100000000-000000023fffffff: RAM
9432 01:21:16.587187 Passing 5 GPIOs to payload:
9433 01:21:16.590369 NAME | PORT | POLARITY | VALUE
9434 01:21:16.593352 EC in RW | 0x000000aa | low | undefined
9435 01:21:16.600344 EC interrupt | 0x00000005 | low | undefined
9436 01:21:16.603442 TPM interrupt | 0x000000ab | high | undefined
9437 01:21:16.610527 SD card detect | 0x00000011 | high | undefined
9438 01:21:16.613431 speaker enable | 0x00000093 | high | undefined
9439 01:21:16.617317 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9440 01:21:16.620018 in-header: 03 f9 00 00 02 00 00 00
9441 01:21:16.623716 in-data: 02 00
9442 01:21:16.623844 ADC[4]: Raw value=903988 ID=7
9443 01:21:16.626885 ADC[3]: Raw value=213810 ID=1
9444 01:21:16.629902 RAM Code: 0x71
9445 01:21:16.630014 ADC[6]: Raw value=75701 ID=0
9446 01:21:16.633644 ADC[5]: Raw value=212703 ID=1
9447 01:21:16.636989 SKU Code: 0x1
9448 01:21:16.640196 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum cac8
9449 01:21:16.643208 coreboot table: 964 bytes.
9450 01:21:16.646487 IMD ROOT 0. 0xfffff000 0x00001000
9451 01:21:16.650295 IMD SMALL 1. 0xffffe000 0x00001000
9452 01:21:16.653480 RO MCACHE 2. 0xffffc000 0x00001104
9453 01:21:16.656873 CONSOLE 3. 0xfff7c000 0x00080000
9454 01:21:16.660364 FMAP 4. 0xfff7b000 0x00000452
9455 01:21:16.663631 TIME STAMP 5. 0xfff7a000 0x00000910
9456 01:21:16.666884 VBOOT WORK 6. 0xfff66000 0x00014000
9457 01:21:16.670009 RAMOOPS 7. 0xffe66000 0x00100000
9458 01:21:16.673458 COREBOOT 8. 0xffe64000 0x00002000
9459 01:21:16.673592 IMD small region:
9460 01:21:16.677008 IMD ROOT 0. 0xffffec00 0x00000400
9461 01:21:16.680242 VPD 1. 0xffffeb80 0x0000006c
9462 01:21:16.683439 MMC STATUS 2. 0xffffeb60 0x00000004
9463 01:21:16.689988 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9464 01:21:16.693336 Probing TPM: done!
9465 01:21:16.696590 Connected to device vid:did:rid of 1ae0:0028:00
9466 01:21:16.707168 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9467 01:21:16.709917 Initialized TPM device CR50 revision 0
9468 01:21:16.713793 Checking cr50 for pending updates
9469 01:21:16.717405 Reading cr50 TPM mode
9470 01:21:16.725636 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9471 01:21:16.732454 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9472 01:21:16.772728 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9473 01:21:16.775769 Checking segment from ROM address 0x40100000
9474 01:21:16.779391 Checking segment from ROM address 0x4010001c
9475 01:21:16.785687 Loading segment from ROM address 0x40100000
9476 01:21:16.785838 code (compression=0)
9477 01:21:16.795623 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9478 01:21:16.802557 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9479 01:21:16.802711 it's not compressed!
9480 01:21:16.808972 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9481 01:21:16.812684 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9482 01:21:16.832765 Loading segment from ROM address 0x4010001c
9483 01:21:16.832920 Entry Point 0x80000000
9484 01:21:16.836359 Loaded segments
9485 01:21:16.839366 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9486 01:21:16.846368 Jumping to boot code at 0x80000000(0xffe64000)
9487 01:21:16.853005 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9488 01:21:16.859332 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9489 01:21:16.867524 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9490 01:21:16.870612 Checking segment from ROM address 0x40100000
9491 01:21:16.874187 Checking segment from ROM address 0x4010001c
9492 01:21:16.881049 Loading segment from ROM address 0x40100000
9493 01:21:16.881202 code (compression=1)
9494 01:21:16.887291 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9495 01:21:16.897228 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9496 01:21:16.897385 using LZMA
9497 01:21:16.905618 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9498 01:21:16.912414 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9499 01:21:16.916092 Loading segment from ROM address 0x4010001c
9500 01:21:16.916228 Entry Point 0x54601000
9501 01:21:16.919096 Loaded segments
9502 01:21:16.922628 NOTICE: MT8192 bl31_setup
9503 01:21:16.929336 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9504 01:21:16.932870 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9505 01:21:16.935958 WARNING: region 0:
9506 01:21:16.939621 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9507 01:21:16.939750 WARNING: region 1:
9508 01:21:16.946156 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9509 01:21:16.949302 WARNING: region 2:
9510 01:21:16.952564 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9511 01:21:16.956380 WARNING: region 3:
9512 01:21:16.959376 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9513 01:21:16.962880 WARNING: region 4:
9514 01:21:16.969070 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9515 01:21:16.969220 WARNING: region 5:
9516 01:21:16.972938 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9517 01:21:16.976141 WARNING: region 6:
9518 01:21:16.979699 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9519 01:21:16.982752 WARNING: region 7:
9520 01:21:16.985766 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9521 01:21:16.992567 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9522 01:21:16.995802 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9523 01:21:16.999647 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9524 01:21:17.006232 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9525 01:21:17.009423 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9526 01:21:17.013029 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9527 01:21:17.019199 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9528 01:21:17.022611 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9529 01:21:17.029119 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9530 01:21:17.032989 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9531 01:21:17.036079 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9532 01:21:17.042561 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9533 01:21:17.046006 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9534 01:21:17.049458 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9535 01:21:17.056027 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9536 01:21:17.059050 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9537 01:21:17.066111 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9538 01:21:17.069341 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9539 01:21:17.072579 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9540 01:21:17.079034 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9541 01:21:17.082805 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9542 01:21:17.085818 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9543 01:21:17.092875 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9544 01:21:17.096009 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9545 01:21:17.102828 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9546 01:21:17.106034 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9547 01:21:17.109118 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9548 01:21:17.115903 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9549 01:21:17.119097 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9550 01:21:17.123058 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9551 01:21:17.129407 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9552 01:21:17.132523 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9553 01:21:17.139200 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9554 01:21:17.142594 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9555 01:21:17.145828 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9556 01:21:17.149346 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9557 01:21:17.156060 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9558 01:21:17.159279 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9559 01:21:17.162934 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9560 01:21:17.166223 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9561 01:21:17.169454 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9562 01:21:17.176516 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9563 01:21:17.179753 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9564 01:21:17.183288 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9565 01:21:17.186435 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9566 01:21:17.193067 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9567 01:21:17.196460 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9568 01:21:17.199632 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9569 01:21:17.206708 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9570 01:21:17.209700 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9571 01:21:17.213318 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9572 01:21:17.219591 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9573 01:21:17.223229 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9574 01:21:17.229561 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9575 01:21:17.232829 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9576 01:21:17.239729 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9577 01:21:17.242857 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9578 01:21:17.246634 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9579 01:21:17.253253 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9580 01:21:17.256643 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9581 01:21:17.262824 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9582 01:21:17.266431 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9583 01:21:17.273320 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9584 01:21:17.276573 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9585 01:21:17.280155 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9586 01:21:17.286150 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9587 01:21:17.289823 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9588 01:21:17.296950 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9589 01:21:17.300222 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9590 01:21:17.306504 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9591 01:21:17.309620 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9592 01:21:17.313375 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9593 01:21:17.319526 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9594 01:21:17.323217 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9595 01:21:17.330131 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9596 01:21:17.333313 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9597 01:21:17.339704 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9598 01:21:17.343008 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9599 01:21:17.349778 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9600 01:21:17.352849 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9601 01:21:17.356170 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9602 01:21:17.362849 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9603 01:21:17.366120 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9604 01:21:17.372810 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9605 01:21:17.376067 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9606 01:21:17.382810 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9607 01:21:17.386100 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9608 01:21:17.389343 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9609 01:21:17.396313 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9610 01:21:17.399995 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9611 01:21:17.406046 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9612 01:21:17.409585 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9613 01:21:17.416187 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9614 01:21:17.419862 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9615 01:21:17.423514 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9616 01:21:17.429417 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9617 01:21:17.432697 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9618 01:21:17.436310 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9619 01:21:17.442773 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9620 01:21:17.445926 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9621 01:21:17.449963 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9622 01:21:17.456075 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9623 01:21:17.459818 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9624 01:21:17.462970 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9625 01:21:17.469689 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9626 01:21:17.473047 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9627 01:21:17.479423 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9628 01:21:17.483001 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9629 01:21:17.486342 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9630 01:21:17.493150 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9631 01:21:17.496163 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9632 01:21:17.499995 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9633 01:21:17.506459 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9634 01:21:17.509654 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9635 01:21:17.516408 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9636 01:21:17.519776 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9637 01:21:17.523354 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9638 01:21:17.529796 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9639 01:21:17.533011 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9640 01:21:17.536940 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9641 01:21:17.539830 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9642 01:21:17.546672 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9643 01:21:17.549858 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9644 01:21:17.553448 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9645 01:21:17.559699 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9646 01:21:17.563036 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9647 01:21:17.566827 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9648 01:21:17.573615 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9649 01:21:17.576679 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9650 01:21:17.579848 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9651 01:21:17.586242 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9652 01:21:17.590023 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9653 01:21:17.596637 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9654 01:21:17.600287 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9655 01:21:17.603039 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9656 01:21:17.609893 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9657 01:21:17.613152 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9658 01:21:17.616382 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9659 01:21:17.623470 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9660 01:21:17.626895 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9661 01:21:17.633525 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9662 01:21:17.636691 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9663 01:21:17.640410 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9664 01:21:17.646798 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9665 01:21:17.649803 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9666 01:21:17.656657 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9667 01:21:17.659838 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9668 01:21:17.663357 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9669 01:21:17.669970 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9670 01:21:17.673332 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9671 01:21:17.676684 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9672 01:21:17.683455 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9673 01:21:17.687189 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9674 01:21:17.693556 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9675 01:21:17.696898 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9676 01:21:17.700139 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9677 01:21:17.706905 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9678 01:21:17.710613 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9679 01:21:17.713534 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9680 01:21:17.720202 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9681 01:21:17.723400 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9682 01:21:17.730456 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9683 01:21:17.733334 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9684 01:21:17.740231 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9685 01:21:17.743211 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9686 01:21:17.746632 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9687 01:21:17.753743 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9688 01:21:17.756744 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9689 01:21:17.760072 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9690 01:21:17.766509 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9691 01:21:17.769527 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9692 01:21:17.776321 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9693 01:21:17.779723 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9694 01:21:17.782635 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9695 01:21:17.789356 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9696 01:21:17.792756 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9697 01:21:17.799162 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9698 01:21:17.803080 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9699 01:21:17.806079 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9700 01:21:17.812402 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9701 01:21:17.815746 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9702 01:21:17.822533 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9703 01:21:17.825595 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9704 01:21:17.829427 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9705 01:21:17.835804 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9706 01:21:17.839410 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9707 01:21:17.845969 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9708 01:21:17.849091 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9709 01:21:17.852097 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9710 01:21:17.858919 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9711 01:21:17.862164 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9712 01:21:17.868601 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9713 01:21:17.871964 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9714 01:21:17.879010 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9715 01:21:17.882132 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9716 01:21:17.885160 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9717 01:21:17.892257 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9718 01:21:17.895284 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9719 01:21:17.902281 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9720 01:21:17.905280 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9721 01:21:17.908914 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9722 01:21:17.915848 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9723 01:21:17.918701 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9724 01:21:17.925345 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9725 01:21:17.928588 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9726 01:21:17.935579 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9727 01:21:17.938652 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9728 01:21:17.941749 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9729 01:21:17.948589 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9730 01:21:17.951954 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9731 01:21:17.958650 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9732 01:21:17.962009 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9733 01:21:17.965575 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9734 01:21:17.972157 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9735 01:21:17.975163 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9736 01:21:17.981751 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9737 01:21:17.984804 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9738 01:21:17.991915 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9739 01:21:17.995132 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9740 01:21:17.998360 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9741 01:21:18.004782 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9742 01:21:18.007931 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9743 01:21:18.014634 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9744 01:21:18.017770 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9745 01:21:18.024723 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9746 01:21:18.027825 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9747 01:21:18.031463 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9748 01:21:18.037661 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9749 01:21:18.041232 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9750 01:21:18.044616 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9751 01:21:18.051288 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9752 01:21:18.054588 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9753 01:21:18.058216 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9754 01:21:18.060902 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9755 01:21:18.067783 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9756 01:21:18.070926 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9757 01:21:18.077779 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9758 01:21:18.080949 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9759 01:21:18.084309 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9760 01:21:18.091113 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9761 01:21:18.094263 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9762 01:21:18.097520 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9763 01:21:18.103859 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9764 01:21:18.107782 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9765 01:21:18.110869 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9766 01:21:18.117883 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9767 01:21:18.120767 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9768 01:21:18.127564 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9769 01:21:18.130862 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9770 01:21:18.134014 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9771 01:21:18.141039 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9772 01:21:18.144147 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9773 01:21:18.147585 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9774 01:21:18.153543 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9775 01:21:18.157312 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9776 01:21:18.160765 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9777 01:21:18.167055 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9778 01:21:18.170911 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9779 01:21:18.173654 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9780 01:21:18.180279 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9781 01:21:18.183984 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9782 01:21:18.190202 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9783 01:21:18.193925 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9784 01:21:18.196939 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9785 01:21:18.203590 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9786 01:21:18.206898 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9787 01:21:18.210694 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9788 01:21:18.216841 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9789 01:21:18.220112 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9790 01:21:18.223319 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9791 01:21:18.230268 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9792 01:21:18.233683 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9793 01:21:18.236790 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9794 01:21:18.239971 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9795 01:21:18.243254 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9796 01:21:18.250244 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9797 01:21:18.253208 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9798 01:21:18.256905 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9799 01:21:18.259791 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9800 01:21:18.266919 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9801 01:21:18.270251 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9802 01:21:18.273344 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9803 01:21:18.280071 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9804 01:21:18.282966 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9805 01:21:18.289740 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9806 01:21:18.293158 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9807 01:21:18.299980 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9808 01:21:18.302838 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9809 01:21:18.306680 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9810 01:21:18.313025 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9811 01:21:18.316480 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9812 01:21:18.322896 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9813 01:21:18.325990 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9814 01:21:18.329399 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9815 01:21:18.336314 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9816 01:21:18.339338 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9817 01:21:18.346490 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9818 01:21:18.349381 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9819 01:21:18.352815 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9820 01:21:18.360032 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9821 01:21:18.362890 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9822 01:21:18.369604 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9823 01:21:18.373439 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9824 01:21:18.379393 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9825 01:21:18.382498 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9826 01:21:18.386258 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9827 01:21:18.393046 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9828 01:21:18.395909 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9829 01:21:18.399228 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9830 01:21:18.405864 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9831 01:21:18.409797 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9832 01:21:18.416170 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9833 01:21:18.419426 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9834 01:21:18.422571 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9835 01:21:18.429373 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9836 01:21:18.432678 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9837 01:21:18.439495 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9838 01:21:18.442386 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9839 01:21:18.449019 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9840 01:21:18.452349 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9841 01:21:18.455464 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9842 01:21:18.462657 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9843 01:21:18.465800 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9844 01:21:18.471986 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9845 01:21:18.475921 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9846 01:21:18.478971 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9847 01:21:18.485291 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9848 01:21:18.488719 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9849 01:21:18.495578 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9850 01:21:18.499030 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9851 01:21:18.501913 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9852 01:21:18.508679 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9853 01:21:18.511730 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9854 01:21:18.518260 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9855 01:21:18.522271 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9856 01:21:18.528568 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9857 01:21:18.532106 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9858 01:21:18.535307 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9859 01:21:18.541575 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9860 01:21:18.545416 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9861 01:21:18.551788 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9862 01:21:18.554932 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9863 01:21:18.558634 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9864 01:21:18.564933 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9865 01:21:18.568215 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9866 01:21:18.574991 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9867 01:21:18.578197 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9868 01:21:18.581594 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9869 01:21:18.588591 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9870 01:21:18.591555 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9871 01:21:18.598060 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9872 01:21:18.601467 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9873 01:21:18.608466 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9874 01:21:18.611738 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9875 01:21:18.614842 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9876 01:21:18.621615 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9877 01:21:18.625006 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9878 01:21:18.631526 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9879 01:21:18.634806 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9880 01:21:18.641244 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9881 01:21:18.644529 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9882 01:21:18.648014 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9883 01:21:18.654524 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9884 01:21:18.657603 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9885 01:21:18.664516 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9886 01:21:18.667683 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9887 01:21:18.673876 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9888 01:21:18.677234 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9889 01:21:18.683889 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9890 01:21:18.687174 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9891 01:21:18.690483 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9892 01:21:18.697294 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9893 01:21:18.700467 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9894 01:21:18.707374 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9895 01:21:18.710673 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9896 01:21:18.716912 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9897 01:21:18.720740 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9898 01:21:18.723950 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9899 01:21:18.730061 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9900 01:21:18.733846 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9901 01:21:18.740560 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9902 01:21:18.743828 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9903 01:21:18.749954 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9904 01:21:18.753708 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9905 01:21:18.759997 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9906 01:21:18.763822 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9907 01:21:18.766747 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9908 01:21:18.773220 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9909 01:21:18.777109 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9910 01:21:18.783450 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9911 01:21:18.786611 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9912 01:21:18.793087 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9913 01:21:18.797064 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9914 01:21:18.800032 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9915 01:21:18.806551 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9916 01:21:18.809904 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9917 01:21:18.816472 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9918 01:21:18.820000 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9919 01:21:18.826448 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9920 01:21:18.829925 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9921 01:21:18.836630 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9922 01:21:18.840163 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9923 01:21:18.843167 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9924 01:21:18.849492 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9925 01:21:18.852665 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9926 01:21:18.859750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9927 01:21:18.862791 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9928 01:21:18.869543 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9929 01:21:18.872631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9930 01:21:18.879287 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9931 01:21:18.882862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9932 01:21:18.889362 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9933 01:21:18.892429 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9934 01:21:18.899359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9935 01:21:18.902731 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9936 01:21:18.905907 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9937 01:21:18.912604 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9938 01:21:18.915714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9939 01:21:18.922339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9940 01:21:18.925695 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9941 01:21:18.932098 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9942 01:21:18.935645 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9943 01:21:18.942449 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9944 01:21:18.945279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9945 01:21:18.952037 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9946 01:21:18.955700 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9947 01:21:18.962155 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9948 01:21:18.965376 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9949 01:21:18.972265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9950 01:21:18.975925 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9951 01:21:18.982398 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9952 01:21:18.985226 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9953 01:21:18.991990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9954 01:21:18.995414 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9955 01:21:19.001872 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9956 01:21:19.002021 INFO: [APUAPC] vio 0
9957 01:21:19.009054 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9958 01:21:19.012300 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9959 01:21:19.015799 INFO: [APUAPC] D0_APC_0: 0x400510
9960 01:21:19.019069 INFO: [APUAPC] D0_APC_1: 0x0
9961 01:21:19.022068 INFO: [APUAPC] D0_APC_2: 0x1540
9962 01:21:19.025604 INFO: [APUAPC] D0_APC_3: 0x0
9963 01:21:19.029252 INFO: [APUAPC] D1_APC_0: 0xffffffff
9964 01:21:19.032459 INFO: [APUAPC] D1_APC_1: 0xffffffff
9965 01:21:19.035765 INFO: [APUAPC] D1_APC_2: 0x3fffff
9966 01:21:19.038918 INFO: [APUAPC] D1_APC_3: 0x0
9967 01:21:19.042667 INFO: [APUAPC] D2_APC_0: 0xffffffff
9968 01:21:19.045731 INFO: [APUAPC] D2_APC_1: 0xffffffff
9969 01:21:19.049104 INFO: [APUAPC] D2_APC_2: 0x3fffff
9970 01:21:19.052415 INFO: [APUAPC] D2_APC_3: 0x0
9971 01:21:19.055615 INFO: [APUAPC] D3_APC_0: 0xffffffff
9972 01:21:19.058908 INFO: [APUAPC] D3_APC_1: 0xffffffff
9973 01:21:19.062594 INFO: [APUAPC] D3_APC_2: 0x3fffff
9974 01:21:19.065456 INFO: [APUAPC] D3_APC_3: 0x0
9975 01:21:19.069008 INFO: [APUAPC] D4_APC_0: 0xffffffff
9976 01:21:19.072246 INFO: [APUAPC] D4_APC_1: 0xffffffff
9977 01:21:19.075722 INFO: [APUAPC] D4_APC_2: 0x3fffff
9978 01:21:19.075870 INFO: [APUAPC] D4_APC_3: 0x0
9979 01:21:19.078845 INFO: [APUAPC] D5_APC_0: 0xffffffff
9980 01:21:19.085753 INFO: [APUAPC] D5_APC_1: 0xffffffff
9981 01:21:19.085941 INFO: [APUAPC] D5_APC_2: 0x3fffff
9982 01:21:19.088975 INFO: [APUAPC] D5_APC_3: 0x0
9983 01:21:19.092173 INFO: [APUAPC] D6_APC_0: 0xffffffff
9984 01:21:19.095150 INFO: [APUAPC] D6_APC_1: 0xffffffff
9985 01:21:19.099044 INFO: [APUAPC] D6_APC_2: 0x3fffff
9986 01:21:19.102293 INFO: [APUAPC] D6_APC_3: 0x0
9987 01:21:19.105409 INFO: [APUAPC] D7_APC_0: 0xffffffff
9988 01:21:19.108724 INFO: [APUAPC] D7_APC_1: 0xffffffff
9989 01:21:19.112145 INFO: [APUAPC] D7_APC_2: 0x3fffff
9990 01:21:19.115172 INFO: [APUAPC] D7_APC_3: 0x0
9991 01:21:19.118483 INFO: [APUAPC] D8_APC_0: 0xffffffff
9992 01:21:19.121806 INFO: [APUAPC] D8_APC_1: 0xffffffff
9993 01:21:19.125422 INFO: [APUAPC] D8_APC_2: 0x3fffff
9994 01:21:19.128596 INFO: [APUAPC] D8_APC_3: 0x0
9995 01:21:19.131555 INFO: [APUAPC] D9_APC_0: 0xffffffff
9996 01:21:19.135277 INFO: [APUAPC] D9_APC_1: 0xffffffff
9997 01:21:19.138509 INFO: [APUAPC] D9_APC_2: 0x3fffff
9998 01:21:19.141687 INFO: [APUAPC] D9_APC_3: 0x0
9999 01:21:19.144968 INFO: [APUAPC] D10_APC_0: 0xffffffff
10000 01:21:19.148293 INFO: [APUAPC] D10_APC_1: 0xffffffff
10001 01:21:19.151666 INFO: [APUAPC] D10_APC_2: 0x3fffff
10002 01:21:19.155327 INFO: [APUAPC] D10_APC_3: 0x0
10003 01:21:19.158624 INFO: [APUAPC] D11_APC_0: 0xffffffff
10004 01:21:19.161807 INFO: [APUAPC] D11_APC_1: 0xffffffff
10005 01:21:19.165379 INFO: [APUAPC] D11_APC_2: 0x3fffff
10006 01:21:19.168512 INFO: [APUAPC] D11_APC_3: 0x0
10007 01:21:19.172037 INFO: [APUAPC] D12_APC_0: 0xffffffff
10008 01:21:19.174706 INFO: [APUAPC] D12_APC_1: 0xffffffff
10009 01:21:19.178022 INFO: [APUAPC] D12_APC_2: 0x3fffff
10010 01:21:19.181530 INFO: [APUAPC] D12_APC_3: 0x0
10011 01:21:19.184757 INFO: [APUAPC] D13_APC_0: 0xffffffff
10012 01:21:19.188439 INFO: [APUAPC] D13_APC_1: 0xffffffff
10013 01:21:19.191481 INFO: [APUAPC] D13_APC_2: 0x3fffff
10014 01:21:19.194724 INFO: [APUAPC] D13_APC_3: 0x0
10015 01:21:19.198430 INFO: [APUAPC] D14_APC_0: 0xffffffff
10016 01:21:19.201554 INFO: [APUAPC] D14_APC_1: 0xffffffff
10017 01:21:19.204805 INFO: [APUAPC] D14_APC_2: 0x3fffff
10018 01:21:19.208185 INFO: [APUAPC] D14_APC_3: 0x0
10019 01:21:19.211683 INFO: [APUAPC] D15_APC_0: 0xffffffff
10020 01:21:19.214901 INFO: [APUAPC] D15_APC_1: 0xffffffff
10021 01:21:19.218344 INFO: [APUAPC] D15_APC_2: 0x3fffff
10022 01:21:19.221589 INFO: [APUAPC] D15_APC_3: 0x0
10023 01:21:19.224597 INFO: [APUAPC] APC_CON: 0x4
10024 01:21:19.228190 INFO: [NOCDAPC] D0_APC_0: 0x0
10025 01:21:19.231547 INFO: [NOCDAPC] D0_APC_1: 0x0
10026 01:21:19.234617 INFO: [NOCDAPC] D1_APC_0: 0x0
10027 01:21:19.238537 INFO: [NOCDAPC] D1_APC_1: 0xfff
10028 01:21:19.238669 INFO: [NOCDAPC] D2_APC_0: 0x0
10029 01:21:19.241300 INFO: [NOCDAPC] D2_APC_1: 0xfff
10030 01:21:19.244963 INFO: [NOCDAPC] D3_APC_0: 0x0
10031 01:21:19.248036 INFO: [NOCDAPC] D3_APC_1: 0xfff
10032 01:21:19.251289 INFO: [NOCDAPC] D4_APC_0: 0x0
10033 01:21:19.254531 INFO: [NOCDAPC] D4_APC_1: 0xfff
10034 01:21:19.257829 INFO: [NOCDAPC] D5_APC_0: 0x0
10035 01:21:19.261747 INFO: [NOCDAPC] D5_APC_1: 0xfff
10036 01:21:19.264610 INFO: [NOCDAPC] D6_APC_0: 0x0
10037 01:21:19.267836 INFO: [NOCDAPC] D6_APC_1: 0xfff
10038 01:21:19.271370 INFO: [NOCDAPC] D7_APC_0: 0x0
10039 01:21:19.274516 INFO: [NOCDAPC] D7_APC_1: 0xfff
10040 01:21:19.274642 INFO: [NOCDAPC] D8_APC_0: 0x0
10041 01:21:19.278323 INFO: [NOCDAPC] D8_APC_1: 0xfff
10042 01:21:19.281542 INFO: [NOCDAPC] D9_APC_0: 0x0
10043 01:21:19.284610 INFO: [NOCDAPC] D9_APC_1: 0xfff
10044 01:21:19.287724 INFO: [NOCDAPC] D10_APC_0: 0x0
10045 01:21:19.290989 INFO: [NOCDAPC] D10_APC_1: 0xfff
10046 01:21:19.294780 INFO: [NOCDAPC] D11_APC_0: 0x0
10047 01:21:19.297892 INFO: [NOCDAPC] D11_APC_1: 0xfff
10048 01:21:19.301127 INFO: [NOCDAPC] D12_APC_0: 0x0
10049 01:21:19.304488 INFO: [NOCDAPC] D12_APC_1: 0xfff
10050 01:21:19.307522 INFO: [NOCDAPC] D13_APC_0: 0x0
10051 01:21:19.311237 INFO: [NOCDAPC] D13_APC_1: 0xfff
10052 01:21:19.314061 INFO: [NOCDAPC] D14_APC_0: 0x0
10053 01:21:19.317798 INFO: [NOCDAPC] D14_APC_1: 0xfff
10054 01:21:19.317923 INFO: [NOCDAPC] D15_APC_0: 0x0
10055 01:21:19.321104 INFO: [NOCDAPC] D15_APC_1: 0xfff
10056 01:21:19.323991 INFO: [NOCDAPC] APC_CON: 0x4
10057 01:21:19.327318 INFO: [APUAPC] set_apusys_apc done
10058 01:21:19.331479 INFO: [DEVAPC] devapc_init done
10059 01:21:19.334471 INFO: GICv3 without legacy support detected.
10060 01:21:19.340615 INFO: ARM GICv3 driver initialized in EL3
10061 01:21:19.344095 INFO: Maximum SPI INTID supported: 639
10062 01:21:19.347611 INFO: BL31: Initializing runtime services
10063 01:21:19.354171 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10064 01:21:19.357168 INFO: SPM: enable CPC mode
10065 01:21:19.360815 INFO: mcdi ready for mcusys-off-idle and system suspend
10066 01:21:19.367192 INFO: BL31: Preparing for EL3 exit to normal world
10067 01:21:19.370730 INFO: Entry point address = 0x80000000
10068 01:21:19.370873 INFO: SPSR = 0x8
10069 01:21:19.377446
10070 01:21:19.377609
10071 01:21:19.377706
10072 01:21:19.380748 Starting depthcharge on Spherion...
10073 01:21:19.380858
10074 01:21:19.380947 Wipe memory regions:
10075 01:21:19.381032
10076 01:21:19.381834 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10077 01:21:19.381966 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10078 01:21:19.382075 Setting prompt string to ['asurada:']
10079 01:21:19.382186 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10080 01:21:19.383995 [0x00000040000000, 0x00000054600000)
10081 01:21:19.506274
10082 01:21:19.506490 [0x00000054660000, 0x00000080000000)
10083 01:21:19.766866
10084 01:21:19.767031 [0x000000821a7280, 0x000000ffe64000)
10085 01:21:20.511581
10086 01:21:20.511736 [0x00000100000000, 0x00000240000000)
10087 01:21:22.402048
10088 01:21:22.405075 Initializing XHCI USB controller at 0x11200000.
10089 01:21:23.444279
10090 01:21:23.447434 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10091 01:21:23.447530
10092 01:21:23.447594
10093 01:21:23.447653
10094 01:21:23.447935 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10096 01:21:23.548331 asurada: tftpboot 192.168.201.1 13468747/tftp-deploy-8daeronz/kernel/image.itb 13468747/tftp-deploy-8daeronz/kernel/cmdline
10097 01:21:23.548514 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10098 01:21:23.548637 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10099 01:21:23.553151 tftpboot 192.168.201.1 13468747/tftp-deploy-8daeronz/kernel/image.itp-deploy-8daeronz/kernel/cmdline
10100 01:21:23.553240
10101 01:21:23.553304 Waiting for link
10102 01:21:23.713575
10103 01:21:23.713734 R8152: Initializing
10104 01:21:23.713800
10105 01:21:23.717177 Version 9 (ocp_data = 6010)
10106 01:21:23.717260
10107 01:21:23.720211 R8152: Done initializing
10108 01:21:23.720292
10109 01:21:23.720355 Adding net device
10110 01:21:25.592458
10111 01:21:25.592610 done.
10112 01:21:25.592679
10113 01:21:25.592738 MAC: 00:e0:4c:78:7a:aa
10114 01:21:25.592798
10115 01:21:25.596048 Sending DHCP discover... done.
10116 01:21:25.596131
10117 01:21:29.624230 Waiting for reply... done.
10118 01:21:29.624638
10119 01:21:29.624891 Sending DHCP request... done.
10120 01:21:29.626437
10121 01:21:29.636269 Waiting for reply... done.
10122 01:21:29.636434
10123 01:21:29.636522 My ip is 192.168.201.12
10124 01:21:29.636591
10125 01:21:29.639704 The DHCP server ip is 192.168.201.1
10126 01:21:29.639876
10127 01:21:29.646730 TFTP server IP predefined by user: 192.168.201.1
10128 01:21:29.646916
10129 01:21:29.653329 Bootfile predefined by user: 13468747/tftp-deploy-8daeronz/kernel/image.itb
10130 01:21:29.653520
10131 01:21:29.653614 Sending tftp read request... done.
10132 01:21:29.655955
10133 01:21:29.659927 Waiting for the transfer...
10134 01:21:29.660063
10135 01:21:29.951998 00000000 ################################################################
10136 01:21:29.952146
10137 01:21:30.231911 00080000 ################################################################
10138 01:21:30.232055
10139 01:21:30.517340 00100000 ################################################################
10140 01:21:30.517481
10141 01:21:30.808893 00180000 ################################################################
10142 01:21:30.809040
10143 01:21:31.067144 00200000 ################################################################
10144 01:21:31.067288
10145 01:21:31.311066 00280000 ################################################################
10146 01:21:31.311268
10147 01:21:31.554765 00300000 ################################################################
10148 01:21:31.554938
10149 01:21:31.798556 00380000 ################################################################
10150 01:21:31.798718
10151 01:21:32.042253 00400000 ################################################################
10152 01:21:32.042413
10153 01:21:32.285610 00480000 ################################################################
10154 01:21:32.285773
10155 01:21:32.530921 00500000 ################################################################
10156 01:21:32.531057
10157 01:21:32.781237 00580000 ################################################################
10158 01:21:32.781395
10159 01:21:33.029196 00600000 ################################################################
10160 01:21:33.029344
10161 01:21:33.280284 00680000 ################################################################
10162 01:21:33.280430
10163 01:21:33.526286 00700000 ################################################################
10164 01:21:33.526422
10165 01:21:33.771225 00780000 ################################################################
10166 01:21:33.771360
10167 01:21:34.015094 00800000 ################################################################
10168 01:21:34.015239
10169 01:21:34.256552 00880000 ################################################################
10170 01:21:34.256700
10171 01:21:34.501004 00900000 ################################################################
10172 01:21:34.501142
10173 01:21:34.746681 00980000 ################################################################
10174 01:21:34.746820
10175 01:21:34.988886 00a00000 ################################################################
10176 01:21:34.989026
10177 01:21:35.233034 00a80000 ################################################################
10178 01:21:35.233164
10179 01:21:35.476193 00b00000 ################################################################
10180 01:21:35.476332
10181 01:21:35.719779 00b80000 ################################################################
10182 01:21:35.719913
10183 01:21:35.963040 00c00000 ################################################################
10184 01:21:35.963176
10185 01:21:36.213747 00c80000 ################################################################
10186 01:21:36.213882
10187 01:21:36.457954 00d00000 ################################################################
10188 01:21:36.458096
10189 01:21:36.702504 00d80000 ################################################################
10190 01:21:36.702637
10191 01:21:36.946675 00e00000 ################################################################
10192 01:21:36.946810
10193 01:21:37.190715 00e80000 ################################################################
10194 01:21:37.190851
10195 01:21:37.435158 00f00000 ################################################################
10196 01:21:37.435293
10197 01:21:37.685530 00f80000 ################################################################
10198 01:21:37.685668
10199 01:21:37.939349 01000000 ################################################################
10200 01:21:37.939510
10201 01:21:38.190687 01080000 ################################################################
10202 01:21:38.190853
10203 01:21:38.432531 01100000 ################################################################
10204 01:21:38.432670
10205 01:21:38.674672 01180000 ################################################################
10206 01:21:38.674805
10207 01:21:38.919382 01200000 ################################################################
10208 01:21:38.919518
10209 01:21:39.165423 01280000 ################################################################
10210 01:21:39.165583
10211 01:21:39.398679 01300000 ################################################################
10212 01:21:39.398831
10213 01:21:39.627281 01380000 ################################################################
10214 01:21:39.627430
10215 01:21:39.868759 01400000 ################################################################
10216 01:21:39.868920
10217 01:21:40.108644 01480000 ################################################################
10218 01:21:40.108780
10219 01:21:40.348165 01500000 ################################################################
10220 01:21:40.348304
10221 01:21:40.588426 01580000 ################################################################
10222 01:21:40.588581
10223 01:21:40.830535 01600000 ################################################################
10224 01:21:40.830678
10225 01:21:41.072694 01680000 ################################################################
10226 01:21:41.072832
10227 01:21:41.312408 01700000 ################################################################
10228 01:21:41.312542
10229 01:21:41.551656 01780000 ################################################################
10230 01:21:41.551794
10231 01:21:41.792779 01800000 ################################################################
10232 01:21:41.792944
10233 01:21:42.040890 01880000 ################################################################
10234 01:21:42.041027
10235 01:21:42.283298 01900000 ################################################################
10236 01:21:42.283435
10237 01:21:42.526729 01980000 ################################################################
10238 01:21:42.526904
10239 01:21:42.769352 01a00000 ################################################################
10240 01:21:42.769490
10241 01:21:43.013922 01a80000 ################################################################
10242 01:21:43.014080
10243 01:21:43.257710 01b00000 ################################################################
10244 01:21:43.257842
10245 01:21:43.499851 01b80000 ################################################################
10246 01:21:43.500011
10247 01:21:43.739888 01c00000 ################################################################
10248 01:21:43.740060
10249 01:21:43.994812 01c80000 ################################################################
10250 01:21:43.994962
10251 01:21:44.238852 01d00000 ################################################################
10252 01:21:44.239010
10253 01:21:44.478970 01d80000 ################################################################
10254 01:21:44.479146
10255 01:21:44.607141 01e00000 ################################### done.
10256 01:21:44.607275
10257 01:21:44.610667 The bootfile was 31736746 bytes long.
10258 01:21:44.610750
10259 01:21:44.613244 Sending tftp read request... done.
10260 01:21:44.613322
10261 01:21:44.617138 Waiting for the transfer...
10262 01:21:44.617244
10263 01:21:44.617346 00000000 # done.
10264 01:21:44.617439
10265 01:21:44.623545 Command line loaded dynamically from TFTP file: 13468747/tftp-deploy-8daeronz/kernel/cmdline
10266 01:21:44.623633
10267 01:21:44.646369 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13468747/extract-nfsrootfs-v5xyip58,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10268 01:21:44.646488
10269 01:21:44.646561 Loading FIT.
10270 01:21:44.646623
10271 01:21:44.649821 Image ramdisk-1 has 18777429 bytes.
10272 01:21:44.649896
10273 01:21:44.653593 Image fdt-1 has 47230 bytes.
10274 01:21:44.653676
10275 01:21:44.656587 Image kernel-1 has 12910050 bytes.
10276 01:21:44.656663
10277 01:21:44.666637 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10278 01:21:44.666720
10279 01:21:44.683234 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10280 01:21:44.683424
10281 01:21:44.689991 Choosing best match conf-1 for compat google,spherion-rev2.
10282 01:21:44.690105
10283 01:21:44.697854 Connected to device vid:did:rid of 1ae0:0028:00
10284 01:21:44.705425
10285 01:21:44.708781 tpm_get_response: command 0x17b, return code 0x0
10286 01:21:44.708982
10287 01:21:44.715439 ec_init: CrosEC protocol v3 supported (256, 248)
10288 01:21:44.715590
10289 01:21:44.718900 tpm_cleanup: add release locality here.
10290 01:21:44.719009
10291 01:21:44.722265 Shutting down all USB controllers.
10292 01:21:44.722390
10293 01:21:44.725457 Removing current net device
10294 01:21:44.725569
10295 01:21:44.728962 Exiting depthcharge with code 4 at timestamp: 54606832
10296 01:21:44.729082
10297 01:21:44.732166 LZMA decompressing kernel-1 to 0x821a6718
10298 01:21:44.732268
10299 01:21:44.735472 LZMA decompressing kernel-1 to 0x40000000
10300 01:21:46.331202
10301 01:21:46.331341 jumping to kernel
10302 01:21:46.331809 end: 2.2.4 bootloader-commands (duration 00:00:27) [common]
10303 01:21:46.331914 start: 2.2.5 auto-login-action (timeout 00:03:58) [common]
10304 01:21:46.332003 Setting prompt string to ['Linux version [0-9]']
10305 01:21:46.332075 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10306 01:21:46.332148 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10307 01:21:46.413525
10308 01:21:46.416824 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10309 01:21:46.420399 start: 2.2.5.1 login-action (timeout 00:03:58) [common]
10310 01:21:46.420519 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10311 01:21:46.420615 Setting prompt string to []
10312 01:21:46.420705 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10313 01:21:46.420784 Using line separator: #'\n'#
10314 01:21:46.420842 No login prompt set.
10315 01:21:46.420909 Parsing kernel messages
10316 01:21:46.420977 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10317 01:21:46.421108 [login-action] Waiting for messages, (timeout 00:03:58)
10318 01:21:46.421184 Waiting using forced prompt support (timeout 00:01:59)
10319 01:21:46.439961 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j174389-arm64-gcc-10-defconfig-arm64-chromebook-96m9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024
10320 01:21:46.443221 [ 0.000000] random: crng init done
10321 01:21:46.449823 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10322 01:21:46.453111 [ 0.000000] efi: UEFI not found.
10323 01:21:46.459559 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10324 01:21:46.466121 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10325 01:21:46.476126 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10326 01:21:46.486085 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10327 01:21:46.492561 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10328 01:21:46.499275 [ 0.000000] printk: bootconsole [mtk8250] enabled
10329 01:21:46.506222 [ 0.000000] NUMA: No NUMA configuration found
10330 01:21:46.512326 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10331 01:21:46.515790 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10332 01:21:46.519052 [ 0.000000] Zone ranges:
10333 01:21:46.525729 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10334 01:21:46.528683 [ 0.000000] DMA32 empty
10335 01:21:46.535685 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10336 01:21:46.539097 [ 0.000000] Movable zone start for each node
10337 01:21:46.542228 [ 0.000000] Early memory node ranges
10338 01:21:46.548782 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10339 01:21:46.555430 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10340 01:21:46.562473 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10341 01:21:46.568410 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10342 01:21:46.571975 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10343 01:21:46.582038 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10344 01:21:46.638014 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10345 01:21:46.644623 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10346 01:21:46.651079 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10347 01:21:46.654494 [ 0.000000] psci: probing for conduit method from DT.
10348 01:21:46.661222 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10349 01:21:46.664421 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10350 01:21:46.670883 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10351 01:21:46.674206 [ 0.000000] psci: SMC Calling Convention v1.2
10352 01:21:46.680733 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10353 01:21:46.684041 [ 0.000000] Detected VIPT I-cache on CPU0
10354 01:21:46.690641 [ 0.000000] CPU features: detected: GIC system register CPU interface
10355 01:21:46.697275 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10356 01:21:46.703812 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10357 01:21:46.710337 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10358 01:21:46.720613 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10359 01:21:46.727087 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10360 01:21:46.730366 [ 0.000000] alternatives: applying boot alternatives
10361 01:21:46.736989 [ 0.000000] Fallback order for Node 0: 0
10362 01:21:46.743387 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10363 01:21:46.746731 [ 0.000000] Policy zone: Normal
10364 01:21:46.770025 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13468747/extract-nfsrootfs-v5xyip58,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10365 01:21:46.780000 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10366 01:21:46.790974 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10367 01:21:46.800589 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10368 01:21:46.807448 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10369 01:21:46.810856 <6>[ 0.000000] software IO TLB: area num 8.
10370 01:21:46.867591 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10371 01:21:47.017087 <6>[ 0.000000] Memory: 7946172K/8385536K available (18048K kernel code, 4118K rwdata, 22292K rodata, 8448K init, 616K bss, 406596K reserved, 32768K cma-reserved)
10372 01:21:47.023630 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10373 01:21:47.030428 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10374 01:21:47.033512 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10375 01:21:47.039936 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10376 01:21:47.047064 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10377 01:21:47.050193 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10378 01:21:47.059994 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10379 01:21:47.066941 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10380 01:21:47.073022 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10381 01:21:47.076877 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10382 01:21:47.083309 <6>[ 0.000000] GICv3: 608 SPIs implemented
10383 01:21:47.086476 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10384 01:21:47.089766 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10385 01:21:47.096612 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10386 01:21:47.103464 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10387 01:21:47.116080 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10388 01:21:47.125995 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10389 01:21:47.135865 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10390 01:21:47.143730 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10391 01:21:47.156831 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10392 01:21:47.163611 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10393 01:21:47.169901 <6>[ 0.009185] Console: colour dummy device 80x25
10394 01:21:47.179874 <6>[ 0.013913] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10395 01:21:47.186752 <6>[ 0.024420] pid_max: default: 32768 minimum: 301
10396 01:21:47.189778 <6>[ 0.029292] LSM: Security Framework initializing
10397 01:21:47.196358 <6>[ 0.034230] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10398 01:21:47.206417 <6>[ 0.042044] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10399 01:21:47.213163 <6>[ 0.051455] cblist_init_generic: Setting adjustable number of callback queues.
10400 01:21:47.219773 <6>[ 0.058898] cblist_init_generic: Setting shift to 3 and lim to 1.
10401 01:21:47.229559 <6>[ 0.065238] cblist_init_generic: Setting adjustable number of callback queues.
10402 01:21:47.236122 <6>[ 0.072664] cblist_init_generic: Setting shift to 3 and lim to 1.
10403 01:21:47.239387 <6>[ 0.079105] rcu: Hierarchical SRCU implementation.
10404 01:21:47.246086 <6>[ 0.084120] rcu: Max phase no-delay instances is 1000.
10405 01:21:47.252963 <6>[ 0.091151] EFI services will not be available.
10406 01:21:47.255987 <6>[ 0.096109] smp: Bringing up secondary CPUs ...
10407 01:21:47.264037 <6>[ 0.101187] Detected VIPT I-cache on CPU1
10408 01:21:47.270732 <6>[ 0.101258] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10409 01:21:47.277702 <6>[ 0.101290] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10410 01:21:47.280956 <6>[ 0.101620] Detected VIPT I-cache on CPU2
10411 01:21:47.287641 <6>[ 0.101666] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10412 01:21:47.294376 <6>[ 0.101682] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10413 01:21:47.300899 <6>[ 0.101938] Detected VIPT I-cache on CPU3
10414 01:21:47.307375 <6>[ 0.101984] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10415 01:21:47.313789 <6>[ 0.101998] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10416 01:21:47.317440 <6>[ 0.102301] CPU features: detected: Spectre-v4
10417 01:21:47.324045 <6>[ 0.102307] CPU features: detected: Spectre-BHB
10418 01:21:47.327276 <6>[ 0.102312] Detected PIPT I-cache on CPU4
10419 01:21:47.334283 <6>[ 0.102370] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10420 01:21:47.340930 <6>[ 0.102387] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10421 01:21:47.347666 <6>[ 0.102685] Detected PIPT I-cache on CPU5
10422 01:21:47.353809 <6>[ 0.102747] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10423 01:21:47.360648 <6>[ 0.102763] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10424 01:21:47.363625 <6>[ 0.103045] Detected PIPT I-cache on CPU6
10425 01:21:47.370418 <6>[ 0.103112] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10426 01:21:47.377229 <6>[ 0.103128] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10427 01:21:47.383677 <6>[ 0.103421] Detected PIPT I-cache on CPU7
10428 01:21:47.390429 <6>[ 0.103485] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10429 01:21:47.397154 <6>[ 0.103501] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10430 01:21:47.399834 <6>[ 0.103548] smp: Brought up 1 node, 8 CPUs
10431 01:21:47.406606 <6>[ 0.244816] SMP: Total of 8 processors activated.
10432 01:21:47.409940 <6>[ 0.249768] CPU features: detected: 32-bit EL0 Support
10433 01:21:47.419808 <6>[ 0.255131] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10434 01:21:47.426476 <6>[ 0.263931] CPU features: detected: Common not Private translations
10435 01:21:47.430067 <6>[ 0.270408] CPU features: detected: CRC32 instructions
10436 01:21:47.436806 <6>[ 0.275759] CPU features: detected: RCpc load-acquire (LDAPR)
10437 01:21:47.443413 <6>[ 0.281756] CPU features: detected: LSE atomic instructions
10438 01:21:47.450181 <6>[ 0.287537] CPU features: detected: Privileged Access Never
10439 01:21:47.453175 <6>[ 0.293317] CPU features: detected: RAS Extension Support
10440 01:21:47.463249 <6>[ 0.298925] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10441 01:21:47.466500 <6>[ 0.306147] CPU: All CPU(s) started at EL2
10442 01:21:47.473089 <6>[ 0.310464] alternatives: applying system-wide alternatives
10443 01:21:47.481668 <6>[ 0.321252] devtmpfs: initialized
10444 01:21:47.494715 <6>[ 0.330272] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10445 01:21:47.504622 <6>[ 0.340233] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10446 01:21:47.511136 <6>[ 0.348475] pinctrl core: initialized pinctrl subsystem
10447 01:21:47.514505 <6>[ 0.355115] DMI not present or invalid.
10448 01:21:47.521267 <6>[ 0.359526] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10449 01:21:47.531203 <6>[ 0.366421] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10450 01:21:47.537445 <6>[ 0.374005] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10451 01:21:47.547258 <6>[ 0.382239] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10452 01:21:47.550540 <6>[ 0.390482] audit: initializing netlink subsys (disabled)
10453 01:21:47.560568 <5>[ 0.396178] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10454 01:21:47.567215 <6>[ 0.396884] thermal_sys: Registered thermal governor 'step_wise'
10455 01:21:47.574032 <6>[ 0.404144] thermal_sys: Registered thermal governor 'power_allocator'
10456 01:21:47.577474 <6>[ 0.410397] cpuidle: using governor menu
10457 01:21:47.583644 <6>[ 0.421357] NET: Registered PF_QIPCRTR protocol family
10458 01:21:47.590352 <6>[ 0.426862] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10459 01:21:47.596818 <6>[ 0.433964] ASID allocator initialised with 32768 entries
10460 01:21:47.600009 <6>[ 0.440539] Serial: AMBA PL011 UART driver
10461 01:21:47.610218 <4>[ 0.449311] Trying to register duplicate clock ID: 134
10462 01:21:47.666507 <6>[ 0.509144] KASLR enabled
10463 01:21:47.681003 <6>[ 0.516848] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10464 01:21:47.687454 <6>[ 0.523863] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10465 01:21:47.694414 <6>[ 0.530349] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10466 01:21:47.700852 <6>[ 0.537357] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10467 01:21:47.707638 <6>[ 0.543843] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10468 01:21:47.714103 <6>[ 0.550848] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10469 01:21:47.721082 <6>[ 0.557338] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10470 01:21:47.727791 <6>[ 0.564342] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10471 01:21:47.730489 <6>[ 0.571817] ACPI: Interpreter disabled.
10472 01:21:47.739371 <6>[ 0.578236] iommu: Default domain type: Translated
10473 01:21:47.745928 <6>[ 0.583381] iommu: DMA domain TLB invalidation policy: strict mode
10474 01:21:47.748642 <5>[ 0.590039] SCSI subsystem initialized
10475 01:21:47.755764 <6>[ 0.594289] usbcore: registered new interface driver usbfs
10476 01:21:47.762211 <6>[ 0.600016] usbcore: registered new interface driver hub
10477 01:21:47.765409 <6>[ 0.605571] usbcore: registered new device driver usb
10478 01:21:47.772734 <6>[ 0.611688] pps_core: LinuxPPS API ver. 1 registered
10479 01:21:47.782153 <6>[ 0.616878] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10480 01:21:47.785519 <6>[ 0.626217] PTP clock support registered
10481 01:21:47.789511 <6>[ 0.630456] EDAC MC: Ver: 3.0.0
10482 01:21:47.796369 <6>[ 0.635641] FPGA manager framework
10483 01:21:47.800048 <6>[ 0.639315] Advanced Linux Sound Architecture Driver Initialized.
10484 01:21:47.803666 <6>[ 0.646092] vgaarb: loaded
10485 01:21:47.810628 <6>[ 0.649262] clocksource: Switched to clocksource arch_sys_counter
10486 01:21:47.816512 <5>[ 0.655706] VFS: Disk quotas dquot_6.6.0
10487 01:21:47.823146 <6>[ 0.659894] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10488 01:21:47.826402 <6>[ 0.667086] pnp: PnP ACPI: disabled
10489 01:21:47.834178 <6>[ 0.673758] NET: Registered PF_INET protocol family
10490 01:21:47.843990 <6>[ 0.679350] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10491 01:21:47.855393 <6>[ 0.691694] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10492 01:21:47.865941 <6>[ 0.700508] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10493 01:21:47.872550 <6>[ 0.708479] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10494 01:21:47.879354 <6>[ 0.717185] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10495 01:21:47.891098 <6>[ 0.726931] TCP: Hash tables configured (established 65536 bind 65536)
10496 01:21:47.897670 <6>[ 0.733798] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10497 01:21:47.904212 <6>[ 0.740996] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10498 01:21:47.910473 <6>[ 0.748702] NET: Registered PF_UNIX/PF_LOCAL protocol family
10499 01:21:47.917785 <6>[ 0.754846] RPC: Registered named UNIX socket transport module.
10500 01:21:47.920995 <6>[ 0.760997] RPC: Registered udp transport module.
10501 01:21:47.927691 <6>[ 0.765929] RPC: Registered tcp transport module.
10502 01:21:47.933770 <6>[ 0.770865] RPC: Registered tcp NFSv4.1 backchannel transport module.
10503 01:21:47.937149 <6>[ 0.777527] PCI: CLS 0 bytes, default 64
10504 01:21:47.940435 <6>[ 0.781866] Unpacking initramfs...
10505 01:21:47.965343 <6>[ 0.801354] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10506 01:21:47.975093 <6>[ 0.810007] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10507 01:21:47.978615 <6>[ 0.818861] kvm [1]: IPA Size Limit: 40 bits
10508 01:21:47.985066 <6>[ 0.823392] kvm [1]: GICv3: no GICV resource entry
10509 01:21:47.988445 <6>[ 0.828411] kvm [1]: disabling GICv2 emulation
10510 01:21:47.995461 <6>[ 0.833097] kvm [1]: GIC system register CPU interface enabled
10511 01:21:47.998782 <6>[ 0.839261] kvm [1]: vgic interrupt IRQ18
10512 01:21:48.005101 <6>[ 0.843620] kvm [1]: VHE mode initialized successfully
10513 01:21:48.011779 <5>[ 0.850179] Initialise system trusted keyrings
10514 01:21:48.018108 <6>[ 0.855014] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10515 01:21:48.025721 <6>[ 0.865085] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10516 01:21:48.032447 <5>[ 0.871429] NFS: Registering the id_resolver key type
10517 01:21:48.035785 <5>[ 0.876729] Key type id_resolver registered
10518 01:21:48.042425 <5>[ 0.881145] Key type id_legacy registered
10519 01:21:48.049167 <6>[ 0.885421] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10520 01:21:48.055662 <6>[ 0.892342] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10521 01:21:48.061819 <6>[ 0.900053] 9p: Installing v9fs 9p2000 file system support
10522 01:21:48.098804 <5>[ 0.937841] Key type asymmetric registered
10523 01:21:48.102089 <5>[ 0.942172] Asymmetric key parser 'x509' registered
10524 01:21:48.112075 <6>[ 0.947305] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10525 01:21:48.115293 <6>[ 0.954919] io scheduler mq-deadline registered
10526 01:21:48.118595 <6>[ 0.959677] io scheduler kyber registered
10527 01:21:48.137422 <6>[ 0.976542] EINJ: ACPI disabled.
10528 01:21:48.169346 <4>[ 1.002137] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10529 01:21:48.179332 <4>[ 1.012752] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10530 01:21:48.193959 <6>[ 1.033457] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10531 01:21:48.202363 <6>[ 1.041462] printk: console [ttyS0] disabled
10532 01:21:48.229843 <6>[ 1.066086] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10533 01:21:48.236583 <6>[ 1.075555] printk: console [ttyS0] enabled
10534 01:21:48.239750 <6>[ 1.075555] printk: console [ttyS0] enabled
10535 01:21:48.246619 <6>[ 1.084447] printk: bootconsole [mtk8250] disabled
10536 01:21:48.249801 <6>[ 1.084447] printk: bootconsole [mtk8250] disabled
10537 01:21:48.256453 <6>[ 1.095473] SuperH (H)SCI(F) driver initialized
10538 01:21:48.259670 <6>[ 1.100757] msm_serial: driver initialized
10539 01:21:48.273726 <6>[ 1.109620] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10540 01:21:48.283421 <6>[ 1.118163] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10541 01:21:48.290068 <6>[ 1.126706] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10542 01:21:48.300332 <6>[ 1.135334] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10543 01:21:48.306611 <6>[ 1.144039] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10544 01:21:48.316655 <6>[ 1.152752] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10545 01:21:48.326486 <6>[ 1.161301] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10546 01:21:48.333477 <6>[ 1.170098] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10547 01:21:48.343095 <6>[ 1.178640] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10548 01:21:48.354783 <6>[ 1.194239] loop: module loaded
10549 01:21:48.361453 <6>[ 1.200133] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10550 01:21:48.383569 <4>[ 1.223154] mtk-pmic-keys: Failed to locate of_node [id: -1]
10551 01:21:48.390852 <6>[ 1.229986] megasas: 07.719.03.00-rc1
10552 01:21:48.400092 <6>[ 1.239653] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10553 01:21:48.409407 <6>[ 1.248667] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10554 01:21:48.425822 <6>[ 1.265435] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10555 01:21:48.483133 <6>[ 1.315700] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10556 01:21:48.735504 <6>[ 1.574978] Freeing initrd memory: 18332K
10557 01:21:48.747216 <6>[ 1.586549] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10558 01:21:48.758771 <6>[ 1.597681] tun: Universal TUN/TAP device driver, 1.6
10559 01:21:48.761736 <6>[ 1.603750] thunder_xcv, ver 1.0
10560 01:21:48.764851 <6>[ 1.607260] thunder_bgx, ver 1.0
10561 01:21:48.768486 <6>[ 1.610755] nicpf, ver 1.0
10562 01:21:48.778656 <6>[ 1.614779] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10563 01:21:48.782037 <6>[ 1.622255] hns3: Copyright (c) 2017 Huawei Corporation.
10564 01:21:48.785439 <6>[ 1.627845] hclge is initializing
10565 01:21:48.792167 <6>[ 1.631425] e1000: Intel(R) PRO/1000 Network Driver
10566 01:21:48.798788 <6>[ 1.636554] e1000: Copyright (c) 1999-2006 Intel Corporation.
10567 01:21:48.802144 <6>[ 1.642567] e1000e: Intel(R) PRO/1000 Network Driver
10568 01:21:48.808817 <6>[ 1.647783] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10569 01:21:48.815292 <6>[ 1.653969] igb: Intel(R) Gigabit Ethernet Network Driver
10570 01:21:48.821947 <6>[ 1.659618] igb: Copyright (c) 2007-2014 Intel Corporation.
10571 01:21:48.828439 <6>[ 1.665457] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10572 01:21:48.834873 <6>[ 1.671976] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10573 01:21:48.838602 <6>[ 1.678439] sky2: driver version 1.30
10574 01:21:48.845282 <6>[ 1.683433] VFIO - User Level meta-driver version: 0.3
10575 01:21:48.852198 <6>[ 1.691697] usbcore: registered new interface driver usb-storage
10576 01:21:48.859010 <6>[ 1.698145] usbcore: registered new device driver onboard-usb-hub
10577 01:21:48.867795 <6>[ 1.707332] mt6397-rtc mt6359-rtc: registered as rtc0
10578 01:21:48.877845 <6>[ 1.712794] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-23T01:17:37 UTC (1713835057)
10579 01:21:48.881505 <6>[ 1.722364] i2c_dev: i2c /dev entries driver
10580 01:21:48.898219 <6>[ 1.734218] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10581 01:21:48.904873 <4>[ 1.742953] cpu cpu0: supply cpu not found, using dummy regulator
10582 01:21:48.911471 <4>[ 1.749385] cpu cpu1: supply cpu not found, using dummy regulator
10583 01:21:48.918141 <4>[ 1.755792] cpu cpu2: supply cpu not found, using dummy regulator
10584 01:21:48.924600 <4>[ 1.762208] cpu cpu3: supply cpu not found, using dummy regulator
10585 01:21:48.931847 <4>[ 1.768607] cpu cpu4: supply cpu not found, using dummy regulator
10586 01:21:48.937865 <4>[ 1.775002] cpu cpu5: supply cpu not found, using dummy regulator
10587 01:21:48.944479 <4>[ 1.781405] cpu cpu6: supply cpu not found, using dummy regulator
10588 01:21:48.951620 <4>[ 1.787800] cpu cpu7: supply cpu not found, using dummy regulator
10589 01:21:48.969687 <6>[ 1.809427] cpu cpu0: EM: created perf domain
10590 01:21:48.972965 <6>[ 1.814377] cpu cpu4: EM: created perf domain
10591 01:21:48.980401 <6>[ 1.819993] sdhci: Secure Digital Host Controller Interface driver
10592 01:21:48.987473 <6>[ 1.826424] sdhci: Copyright(c) Pierre Ossman
10593 01:21:48.994060 <6>[ 1.831384] Synopsys Designware Multimedia Card Interface Driver
10594 01:21:49.000374 <6>[ 1.838025] sdhci-pltfm: SDHCI platform and OF driver helper
10595 01:21:49.003788 <6>[ 1.838027] mmc0: CQHCI version 5.10
10596 01:21:49.010472 <6>[ 1.848279] ledtrig-cpu: registered to indicate activity on CPUs
10597 01:21:49.017022 <6>[ 1.855423] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10598 01:21:49.023699 <6>[ 1.862487] usbcore: registered new interface driver usbhid
10599 01:21:49.027022 <6>[ 1.868311] usbhid: USB HID core driver
10600 01:21:49.033776 <6>[ 1.872524] spi_master spi0: will run message pump with realtime priority
10601 01:21:49.076937 <6>[ 1.909349] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10602 01:21:49.091423 <6>[ 1.924236] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10603 01:21:49.099921 <6>[ 1.939267] cros-ec-spi spi0.0: Chrome EC device registered
10604 01:21:49.106634 <6>[ 1.945249] mmc0: Command Queue Engine enabled
10605 01:21:49.113289 <6>[ 1.950018] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10606 01:21:49.116858 <6>[ 1.957756] mmcblk0: mmc0:0001 DA4128 116 GiB
10607 01:21:49.129286 <6>[ 1.968523] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10608 01:21:49.136423 <6>[ 1.975988] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10609 01:21:49.146957 <6>[ 1.979819] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10610 01:21:49.149618 <6>[ 1.981989] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10611 01:21:49.156803 <6>[ 1.991946] NET: Registered PF_PACKET protocol family
10612 01:21:49.163294 <6>[ 1.996518] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10613 01:21:49.166687 <6>[ 2.001128] 9pnet: Installing 9P2000 support
10614 01:21:49.172870 <5>[ 2.012151] Key type dns_resolver registered
10615 01:21:49.176169 <6>[ 2.017123] registered taskstats version 1
10616 01:21:49.182756 <5>[ 2.021505] Loading compiled-in X.509 certificates
10617 01:21:49.212035 <4>[ 2.044580] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10618 01:21:49.221867 <4>[ 2.055331] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10619 01:21:49.228646 <3>[ 2.065886] debugfs: File 'uA_load' in directory '/' already present!
10620 01:21:49.235666 <3>[ 2.072643] debugfs: File 'min_uV' in directory '/' already present!
10621 01:21:49.242083 <3>[ 2.079270] debugfs: File 'max_uV' in directory '/' already present!
10622 01:21:49.248686 <3>[ 2.085893] debugfs: File 'constraint_flags' in directory '/' already present!
10623 01:21:49.259442 <3>[ 2.095586] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10624 01:21:49.269765 <6>[ 2.109151] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10625 01:21:49.276366 <6>[ 2.115912] xhci-mtk 11200000.usb: xHCI Host Controller
10626 01:21:49.283041 <6>[ 2.121411] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10627 01:21:49.292922 <6>[ 2.129246] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10628 01:21:49.299565 <6>[ 2.138681] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10629 01:21:49.306211 <6>[ 2.144728] xhci-mtk 11200000.usb: xHCI Host Controller
10630 01:21:49.313271 <6>[ 2.150206] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10631 01:21:49.320092 <6>[ 2.157854] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10632 01:21:49.326230 <6>[ 2.165549] hub 1-0:1.0: USB hub found
10633 01:21:49.329574 <6>[ 2.169561] hub 1-0:1.0: 1 port detected
10634 01:21:49.336384 <6>[ 2.173825] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10635 01:21:49.343014 <6>[ 2.182381] hub 2-0:1.0: USB hub found
10636 01:21:49.346483 <6>[ 2.186388] hub 2-0:1.0: 1 port detected
10637 01:21:49.355015 <6>[ 2.194311] mtk-msdc 11f70000.mmc: Got CD GPIO
10638 01:21:49.365197 <6>[ 2.201349] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10639 01:21:49.371755 <6>[ 2.209375] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10640 01:21:49.381701 <4>[ 2.217279] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10641 01:21:49.391704 <6>[ 2.226803] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10642 01:21:49.398245 <6>[ 2.234880] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10643 01:21:49.404985 <6>[ 2.242995] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10644 01:21:49.415095 <6>[ 2.251023] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10645 01:21:49.421925 <6>[ 2.258843] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10646 01:21:49.431398 <6>[ 2.266671] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10647 01:21:49.441743 <6>[ 2.277324] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10648 01:21:49.448231 <6>[ 2.285720] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10649 01:21:49.458173 <6>[ 2.294063] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10650 01:21:49.464633 <6>[ 2.302413] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10651 01:21:49.474650 <6>[ 2.310751] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10652 01:21:49.484233 <6>[ 2.319100] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10653 01:21:49.491092 <6>[ 2.327443] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10654 01:21:49.500867 <6>[ 2.335793] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10655 01:21:49.507505 <6>[ 2.344132] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10656 01:21:49.517495 <6>[ 2.352479] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10657 01:21:49.524232 <6>[ 2.360818] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10658 01:21:49.534410 <6>[ 2.369156] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10659 01:21:49.540989 <6>[ 2.377494] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10660 01:21:49.550916 <6>[ 2.385831] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10661 01:21:49.557423 <6>[ 2.394169] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10662 01:21:49.563812 <6>[ 2.402964] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10663 01:21:49.570546 <6>[ 2.410200] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10664 01:21:49.577507 <6>[ 2.416975] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10665 01:21:49.587398 <6>[ 2.423732] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10666 01:21:49.593853 <6>[ 2.430659] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10667 01:21:49.600759 <6>[ 2.437534] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10668 01:21:49.610892 <6>[ 2.446663] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10669 01:21:49.620795 <6>[ 2.455783] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10670 01:21:49.630954 <6>[ 2.465097] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10671 01:21:49.640883 <6>[ 2.474571] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10672 01:21:49.647372 <6>[ 2.484038] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10673 01:21:49.657154 <6>[ 2.493161] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10674 01:21:49.667176 <6>[ 2.502629] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10675 01:21:49.676841 <6>[ 2.511749] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10676 01:21:49.687046 <6>[ 2.521043] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10677 01:21:49.696674 <6>[ 2.531204] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10678 01:21:49.707023 <6>[ 2.543213] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10679 01:21:49.713422 <6>[ 2.552833] Trying to probe devices needed for running init ...
10680 01:21:49.737483 <6>[ 2.573597] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10681 01:21:49.765464 <6>[ 2.604955] hub 2-1:1.0: USB hub found
10682 01:21:49.768928 <6>[ 2.609441] hub 2-1:1.0: 3 ports detected
10683 01:21:49.777417 <6>[ 2.616925] hub 2-1:1.0: USB hub found
10684 01:21:49.780772 <6>[ 2.621253] hub 2-1:1.0: 3 ports detected
10685 01:21:49.889419 <6>[ 2.725474] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10686 01:21:50.043727 <6>[ 2.883406] hub 1-1:1.0: USB hub found
10687 01:21:50.046949 <6>[ 2.887891] hub 1-1:1.0: 4 ports detected
10688 01:21:50.057047 <6>[ 2.896383] hub 1-1:1.0: USB hub found
10689 01:21:50.059968 <6>[ 2.900799] hub 1-1:1.0: 4 ports detected
10690 01:21:50.129795 <6>[ 2.965835] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10691 01:21:50.380995 <6>[ 3.217546] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10692 01:21:50.513916 <6>[ 3.353158] hub 1-1.4:1.0: USB hub found
10693 01:21:50.516680 <6>[ 3.357840] hub 1-1.4:1.0: 2 ports detected
10694 01:21:50.526694 <6>[ 3.366087] hub 1-1.4:1.0: USB hub found
10695 01:21:50.530091 <6>[ 3.370632] hub 1-1.4:1.0: 2 ports detected
10696 01:21:50.825499 <6>[ 3.661563] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10697 01:21:51.017427 <6>[ 3.853558] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10698 01:22:01.987013 <6>[ 14.830769] ALSA device list:
10699 01:22:01.993495 <6>[ 14.834229] No soundcards found.
10700 01:22:02.000444 <6>[ 14.841528] Freeing unused kernel memory: 8448K
10701 01:22:02.003876 <6>[ 14.846505] Run /init as init process
10702 01:22:02.012710 Loading, please wait...
10703 01:22:02.038961 Starting systemd-udevd version 252.22-1~deb12u1
10704 01:22:02.039045
10705 01:22:02.260536 <6>[ 15.098195] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10706 01:22:02.290667 <6>[ 15.131679] remoteproc remoteproc0: scp is available
10707 01:22:02.297310 <6>[ 15.133986] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10708 01:22:02.304040 <6>[ 15.137160] remoteproc remoteproc0: powering up scp
10709 01:22:02.310768 <6>[ 15.145359] usbcore: registered new device driver r8152-cfgselector
10710 01:22:02.320941 <6>[ 15.146266] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10711 01:22:02.327593 <6>[ 15.146285] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10712 01:22:02.336886 <6>[ 15.149772] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10713 01:22:02.344009 <3>[ 15.157349] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 01:22:02.350716 <6>[ 15.162299] mc: Linux media interface: v0.10
10715 01:22:02.353903 <6>[ 15.165020] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10716 01:22:02.363333 <3>[ 15.173688] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10717 01:22:02.370432 <6>[ 15.182609] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10718 01:22:02.379953 <3>[ 15.190216] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 01:22:02.386625 <3>[ 15.190305] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10720 01:22:02.393190 <6>[ 15.192257] videodev: Linux video capture interface: v2.00
10721 01:22:02.400268 <4>[ 15.192370] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10722 01:22:02.406514 <4>[ 15.192474] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10723 01:22:02.416618 <3>[ 15.253365] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 01:22:02.422980 <3>[ 15.261790] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10725 01:22:02.433410 <3>[ 15.270013] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 01:22:02.440074 <6>[ 15.270706] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10727 01:22:02.446786 <3>[ 15.278155] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10728 01:22:02.456268 <3>[ 15.278276] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 01:22:02.459929 <6>[ 15.285947] pci_bus 0000:00: root bus resource [bus 00-ff]
10730 01:22:02.470186 <3>[ 15.294057] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10731 01:22:02.476537 <4>[ 15.298009] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10732 01:22:02.483018 <4>[ 15.298009] Fallback method does not support PEC.
10733 01:22:02.490476 <6>[ 15.301344] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10734 01:22:02.497235 <3>[ 15.307052] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 01:22:02.503903 <6>[ 15.307381] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10736 01:22:02.513319 <6>[ 15.307414] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10737 01:22:02.520398 <6>[ 15.307422] remoteproc remoteproc0: remote processor scp is now up
10738 01:22:02.530017 <6>[ 15.309857] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10739 01:22:02.539800 <6>[ 15.315125] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10740 01:22:02.546755 <3>[ 15.315384] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10741 01:22:02.556707 <6>[ 15.316095] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10742 01:22:02.563348 <6>[ 15.317131] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10743 01:22:02.573299 <3>[ 15.328756] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10744 01:22:02.579895 <6>[ 15.335923] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10745 01:22:02.586158 <6>[ 15.335938] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10746 01:22:02.589868 <6>[ 15.335999] pci 0000:00:00.0: supports D1 D2
10747 01:22:02.599555 <6>[ 15.337731] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10748 01:22:02.609279 <3>[ 15.338441] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10749 01:22:02.616024 <3>[ 15.344083] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10750 01:22:02.623021 <6>[ 15.351061] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10751 01:22:02.629748 <3>[ 15.359569] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10752 01:22:02.639235 <3>[ 15.359572] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10753 01:22:02.649103 <6>[ 15.360387] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10754 01:22:02.659404 <6>[ 15.360866] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10755 01:22:02.666231 <4>[ 15.360890] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10756 01:22:02.676115 <4>[ 15.360897] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10757 01:22:02.682996 <6>[ 15.367411] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10758 01:22:02.692555 <3>[ 15.375301] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 01:22:02.699048 <3>[ 15.375306] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10760 01:22:02.709129 <3>[ 15.375333] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10761 01:22:02.715283 <6>[ 15.385396] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10762 01:22:02.718608 <6>[ 15.394615] Bluetooth: Core ver 2.22
10763 01:22:02.725537 <6>[ 15.402280] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10764 01:22:02.732432 <6>[ 15.403445] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10765 01:22:02.745678 <6>[ 15.404607] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10766 01:22:02.752428 <6>[ 15.404731] usbcore: registered new interface driver uvcvideo
10767 01:22:02.755460 <6>[ 15.410596] NET: Registered PF_BLUETOOTH protocol family
10768 01:22:02.765344 <6>[ 15.418604] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10769 01:22:02.771914 <6>[ 15.424866] Bluetooth: HCI device and connection manager initialized
10770 01:22:02.778413 <6>[ 15.432332] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10771 01:22:02.781735 <6>[ 15.436854] Bluetooth: HCI socket layer initialized
10772 01:22:02.788443 <6>[ 15.445297] pci 0000:01:00.0: supports D1 D2
10773 01:22:02.791647 <6>[ 15.445427] r8152 2-1.3:1.0 eth0: v1.12.13
10774 01:22:02.798354 <6>[ 15.445529] usbcore: registered new interface driver r8152
10775 01:22:02.801513 <6>[ 15.453951] Bluetooth: L2CAP socket layer initialized
10776 01:22:02.808107 <6>[ 15.454439] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10777 01:22:02.818193 <6>[ 15.462024] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10778 01:22:02.821712 <6>[ 15.468894] Bluetooth: SCO socket layer initialized
10779 01:22:02.828029 <6>[ 15.477300] usbcore: registered new interface driver cdc_ether
10780 01:22:02.834449 <6>[ 15.485587] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10781 01:22:02.841250 <6>[ 15.513551] usbcore: registered new interface driver r8153_ecm
10782 01:22:02.847602 <6>[ 15.521309] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10783 01:22:02.858259 <6>[ 15.521315] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10784 01:22:02.864754 <6>[ 15.521331] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10785 01:22:02.874735 <6>[ 15.521345] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10786 01:22:02.880889 <6>[ 15.521359] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10787 01:22:02.887810 <6>[ 15.521374] pci 0000:00:00.0: PCI bridge to [bus 01]
10788 01:22:02.894612 <6>[ 15.521381] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10789 01:22:02.901004 <6>[ 15.521669] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10790 01:22:02.907790 <6>[ 15.560631] usbcore: registered new interface driver btusb
10791 01:22:02.917462 <4>[ 15.561401] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10792 01:22:02.923605 <3>[ 15.561410] Bluetooth: hci0: Failed to load firmware file (-2)
10793 01:22:02.927510 <3>[ 15.561412] Bluetooth: hci0: Failed to set up firmware (-2)
10794 01:22:02.940581 <4>[ 15.561415] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10795 01:22:02.943788 <6>[ 15.564474] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10796 01:22:02.950631 <6>[ 15.564483] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10797 01:22:02.956807 <6>[ 15.564685] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10798 01:22:03.005331 <5>[ 15.843057] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10799 01:22:03.027845 <5>[ 15.865354] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10800 01:22:03.034440 <5>[ 15.872912] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10801 01:22:03.044399 <4>[ 15.881415] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10802 01:22:03.050997 <6>[ 15.890315] cfg80211: failed to load regulatory.db
10803 01:22:03.098185 <6>[ 15.935875] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10804 01:22:03.104789 <6>[ 15.943400] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10805 01:22:03.129069 <6>[ 15.970193] mt7921e 0000:01:00.0: ASIC revision: 79610010
10806 01:22:03.231941 <6>[ 16.069757] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10807 01:22:03.235530 <6>[ 16.069757]
10808 01:22:03.253306 Begin: Loading essential drivers ... done.
10809 01:22:03.256904 Begin: Running /scripts/init-premount ... done.
10810 01:22:03.263318 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10811 01:22:03.273313 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10812 01:22:03.276726 Device /sys/class/net/enx00e04c787aaa found
10813 01:22:03.276807 done.
10814 01:22:03.282518 Begin: Waiting up to 180 secs for any network device to become available ... done.
10815 01:22:03.331759 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10816 01:22:03.502166 <6>[ 16.339749] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10817 01:22:04.129554 <6>[ 16.970289] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10818 01:22:04.356295 <6>[ 17.197455] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10819 01:22:04.372044 IP-Config: no response after 2 secs - giving up
10820 01:22:04.404076 IP-Config: wlp1s0 hardware address d8:f3:bc:78:17:6f mtu 1500 DHCP
10821 01:22:05.055763 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10822 01:22:05.059233 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10823 01:22:05.065828 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10824 01:22:05.072484 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10825 01:22:05.079264 host : mt8192-asurada-spherion-r0-cbg-0
10826 01:22:05.085902 domain : lava-rack
10827 01:22:05.088770 rootserver: 192.168.201.1 rootpath:
10828 01:22:05.091890 filename :
10829 01:22:05.242022 done.
10830 01:22:05.245585 Begin: Running /scripts/nfs-bottom ... done.
10831 01:22:05.262907 Begin: Running /scripts/init-bottom ... done.
10832 01:22:06.559609 <6>[ 19.401233] NET: Registered PF_INET6 protocol family
10833 01:22:06.567487 <6>[ 19.409029] Segment Routing with IPv6
10834 01:22:06.570884 <6>[ 19.412994] In-situ OAM (IOAM) with IPv6
10835 01:22:06.741862 <30>[ 19.556680] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10836 01:22:06.748157 <30>[ 19.589828] systemd[1]: Detected architecture arm64.
10837 01:22:06.754977
10838 01:22:06.758151 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10839 01:22:06.758234
10840 01:22:06.758344
10841 01:22:06.784650 <30>[ 19.625929] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10842 01:22:07.700507 <30>[ 20.538655] systemd[1]: Queued start job for default target graphical.target.
10843 01:22:07.740085 <30>[ 20.578093] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10844 01:22:07.746482 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10845 01:22:07.746573
10846 01:22:07.769568 <30>[ 20.607331] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10847 01:22:07.778960 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10848 01:22:07.779042
10849 01:22:07.797471 <30>[ 20.635317] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10850 01:22:07.807152 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10851 01:22:07.807230
10852 01:22:07.825649 <30>[ 20.663745] systemd[1]: Created slice user.slice - User and Session Slice.
10853 01:22:07.832533 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10854 01:22:07.832641
10855 01:22:07.855449 <30>[ 20.690423] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10856 01:22:07.862457 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10857 01:22:07.865245
10858 01:22:07.883020 <30>[ 20.717784] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10859 01:22:07.889425 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10860 01:22:07.889508
10861 01:22:07.918180 <30>[ 20.746102] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10862 01:22:07.927927 <30>[ 20.766024] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10863 01:22:07.934391 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10864 01:22:07.934473
10865 01:22:07.951522 <30>[ 20.789940] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10866 01:22:07.958375 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10867 01:22:07.961660
10868 01:22:07.979430 <30>[ 20.817670] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10869 01:22:07.989148 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10870 01:22:07.989231
10871 01:22:08.004470 <30>[ 20.846091] systemd[1]: Reached target paths.target - Path Units.
10872 01:22:08.011392 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10873 01:22:08.014701
10874 01:22:08.031853 <30>[ 20.870016] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10875 01:22:08.038722 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10876 01:22:08.038805
10877 01:22:08.052151 <30>[ 20.893555] systemd[1]: Reached target slices.target - Slice Units.
10878 01:22:08.062124 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10879 01:22:08.062235
10880 01:22:08.076111 <30>[ 20.917616] systemd[1]: Reached target swap.target - Swaps.
10881 01:22:08.082207 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10882 01:22:08.082338
10883 01:22:08.103538 <30>[ 20.941654] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10884 01:22:08.113420 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10885 01:22:08.113522
10886 01:22:08.132318 <30>[ 20.970474] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10887 01:22:08.142520 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10888 01:22:08.142603
10889 01:22:08.161982 <30>[ 21.000248] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10890 01:22:08.172157 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10891 01:22:08.172242
10892 01:22:08.188676 <30>[ 21.026932] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10893 01:22:08.198463 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10894 01:22:08.198546
10895 01:22:08.215815 <30>[ 21.054170] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10896 01:22:08.222426 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10897 01:22:08.222519
10898 01:22:08.240624 <30>[ 21.078906] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10899 01:22:08.250840 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10900 01:22:08.250922
10901 01:22:08.270211 <30>[ 21.108183] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10902 01:22:08.280108 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10903 01:22:08.280245
10904 01:22:08.296714 <30>[ 21.134646] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10905 01:22:08.305918 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10906 01:22:08.306018
10907 01:22:08.347505 <30>[ 21.185636] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10908 01:22:08.353851 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10909 01:22:08.353959
10910 01:22:08.376026 <30>[ 21.214237] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10911 01:22:08.382376 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10912 01:22:08.382459
10913 01:22:08.408352 <30>[ 21.246381] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10914 01:22:08.414696 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10915 01:22:08.414778
10916 01:22:08.442484 <30>[ 21.274195] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10917 01:22:08.480188 <30>[ 21.318153] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10918 01:22:08.489433 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10919 01:22:08.489520
10920 01:22:08.512736 <30>[ 21.351079] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10921 01:22:08.519324 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10922 01:22:08.519435
10923 01:22:08.559787 <30>[ 21.397837] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10924 01:22:08.565790 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10925 01:22:08.565898
10926 01:22:08.592655 <30>[ 21.430909] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10927 01:22:08.602593 Starting [0;1;39mmodpr<6>[ 21.440807] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10928 01:22:08.608904 obe@drm.service[0m - Load Kernel Module drm...
10929 01:22:08.609008
10930 01:22:08.630208 <30>[ 21.468639] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10931 01:22:08.636913 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10932 01:22:08.640043
10933 01:22:08.658602 <30>[ 21.496574] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10934 01:22:08.665249 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10935 01:22:08.665351
10936 01:22:08.689122 <6>[ 21.530588] fuse: init (API version 7.37)
10937 01:22:08.720330 <30>[ 21.558324] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10938 01:22:08.726692 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10939 01:22:08.726780
10940 01:22:08.757438 <30>[ 21.595380] systemd[1]: Starting systemd-journald.service - Journal Service...
10941 01:22:08.764013 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10942 01:22:08.764096
10943 01:22:08.793916 <30>[ 21.632197] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10944 01:22:08.800343 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10945 01:22:08.800429
10946 01:22:08.828957 <30>[ 21.663823] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10947 01:22:08.835460 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10948 01:22:08.835545
10949 01:22:08.898922 <3>[ 21.737456] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 01:22:08.909221 <30>[ 21.742075] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10951 01:22:08.915805 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10952 01:22:08.915905
10953 01:22:08.939994 <3>[ 21.777769] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 01:22:08.949823 <30>[ 21.778602] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10955 01:22:08.956376 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10956 01:22:08.956461
10957 01:22:08.981708 <30>[ 21.819834] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10958 01:22:08.995654 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File S<3>[ 21.833880] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 01:22:08.998882 ystem.
10960 01:22:08.998963
10961 01:22:09.015325 <30>[ 21.853855] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10962 01:22:09.022854 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10963 01:22:09.022961
10964 01:22:09.032934 <3>[ 21.870667] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 01:22:09.043836 <30>[ 21.882061] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10966 01:22:09.050503 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10967 01:22:09.050584
10968 01:22:09.061736 <3>[ 21.900215] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 01:22:09.072349 <30>[ 21.910607] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10970 01:22:09.082339 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10971 01:22:09.082445
10972 01:22:09.092249 <3>[ 21.929932] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10973 01:22:09.102922 <30>[ 21.941233] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10974 01:22:09.109746 <30>[ 21.949523] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10975 01:22:09.120405 [[0;32m OK [<3>[ 21.959473] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10976 01:22:09.127175 0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10977 01:22:09.130332
10978 01:22:09.149326 <30>[ 21.987018] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10979 01:22:09.155832 <3>[ 21.989580] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10980 01:22:09.165680 <30>[ 21.995194] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10981 01:22:09.172161 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10982 01:22:09.172241
10983 01:22:09.188431 <3>[ 22.026840] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10984 01:22:09.199353 <30>[ 22.037498] systemd[1]: modprobe@drm.service: Deactivated successfully.
10985 01:22:09.205925 <30>[ 22.045486] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10986 01:22:09.215831 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10987 01:22:09.215935
10988 01:22:09.232057 <3>[ 22.070675] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10989 01:22:09.243332 <30>[ 22.081659] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10990 01:22:09.253476 <30>[ 22.090388] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10991 01:22:09.259793 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10992 01:22:09.259897
10993 01:22:09.283935 <30>[ 22.122618] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10994 01:22:09.291061 <30>[ 22.130254] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10995 01:22:09.300954 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10996 01:22:09.301036
10997 01:22:09.321186 <30>[ 22.159162] systemd[1]: modprobe@loop.service: Deactivated successfully.
10998 01:22:09.327913 <30>[ 22.166673] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10999 01:22:09.344675 [[0;32m OK [0m] Finished [0<4>[ 22.177220] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11000 01:22:09.354578 <3>[ 22.193146] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11001 01:22:09.358504 ;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11002 01:22:09.358597
11003 01:22:09.378052 <30>[ 22.216055] systemd[1]: Started systemd-journald.service - Journal Service.
11004 01:22:09.384485 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11005 01:22:09.384569
11006 01:22:09.408408 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11007 01:22:09.408493
11008 01:22:09.432667 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11009 01:22:09.432752
11010 01:22:09.452462 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11011 01:22:09.452549
11012 01:22:09.472467 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11013 01:22:09.472572
11014 01:22:09.494023 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11015 01:22:09.494133
11016 01:22:09.547566 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11017 01:22:09.547656
11018 01:22:09.572359 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11019 01:22:09.572447
11020 01:22:09.596922 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11021 01:22:09.597008
11022 01:22:09.622445 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11023 01:22:09.622530
11024 01:22:09.647831 Startin<46>[ 22.486702] systemd-journald[301]: Received client request to flush runtime journal.
11025 01:22:09.654625 g [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11026 01:22:09.654708
11027 01:22:09.676874 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11028 01:22:09.676959
11029 01:22:09.969337 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11030 01:22:09.969485
11031 01:22:09.987647 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11032 01:22:09.987731
11033 01:22:10.004552 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11034 01:22:10.004635
11035 01:22:10.420241 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11036 01:22:10.420385
11037 01:22:10.756398 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11038 01:22:10.756549
11039 01:22:10.804153 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11040 01:22:10.804253
11041 01:22:11.048935 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11042 01:22:11.049082
11043 01:22:11.137407 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11044 01:22:11.137531
11045 01:22:11.155736 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11046 01:22:11.155856
11047 01:22:11.171599 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11048 01:22:11.171688
11049 01:22:11.228485 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11050 01:22:11.228586
11051 01:22:11.251316 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11052 01:22:11.251439
11053 01:22:11.428275 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11054 01:22:11.428440
11055 01:22:11.481156 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11056 01:22:11.481256
11057 01:22:11.505980 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11058 01:22:11.506066
11059 01:22:11.554531 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11060 01:22:11.554626
11061 01:22:11.760933 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11062 01:22:11.761062
11063 01:22:11.786249 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11064 01:22:11.786382
11065 01:22:11.900585 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11066 01:22:11.900718
11067 01:22:11.937164 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11068 01:22:11.937259
11069 01:22:12.004948 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11070 01:22:12.005064
11071 01:22:12.040403 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11072 01:22:12.040528
11073 01:22:12.069035 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11074 01:22:12.069159
11075 01:22:12.092868 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11076 01:22:12.092962
11077 01:22:12.112432 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11078 01:22:12.112534
11079 01:22:12.131729 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11080 01:22:12.131812
11081 01:22:12.168134 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11082 01:22:12.168227
11083 01:22:12.187522 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11084 01:22:12.187611
11085 01:22:12.203420 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11086 01:22:12.203506
11087 01:22:12.218882 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11088 01:22:12.218965
11089 01:22:12.239182 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11090 01:22:12.239266
11091 01:22:12.257632 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11092 01:22:12.257714
11093 01:22:12.275469 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11094 01:22:12.275562
11095 01:22:12.293934 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11096 01:22:12.294020
11097 01:22:12.314043 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11098 01:22:12.314133
11099 01:22:12.330783 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11100 01:22:12.330863
11101 01:22:12.372118 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11102 01:22:12.372221
11103 01:22:12.390509 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11104 01:22:12.390594
11105 01:22:12.406730 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11106 01:22:12.406814
11107 01:22:12.442733 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11108 01:22:12.442848
11109 01:22:12.474703 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11110 01:22:12.474798
11111 01:22:12.589843 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11112 01:22:12.589965
11113 01:22:12.613551 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11114 01:22:12.613666
11115 01:22:12.637299 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11116 01:22:12.637405
11117 01:22:12.740523 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11118 01:22:12.740644
11119 01:22:12.774433 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11120 01:22:12.774538
11121 01:22:12.794015 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11122 01:22:12.794107
11123 01:22:12.816625 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11124 01:22:12.816711
11125 01:22:12.833485 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11126 01:22:12.833570
11127 01:22:12.855637 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11128 01:22:12.855723
11129 01:22:12.888747 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11130 01:22:12.888841
11131 01:22:12.916191 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11132 01:22:12.916304
11133 01:22:12.962039 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11134 01:22:12.962195
11135 01:22:12.980178 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11136 01:22:12.980263
11137 01:22:13.035260 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11138 01:22:13.035358
11139 01:22:13.060237 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11140 01:22:13.060340
11141 01:22:13.103255 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11142 01:22:13.103361
11143 01:22:13.131498 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11144 01:22:13.131586
11145 01:22:13.205752
11146 01:22:13.205900
11147 01:22:13.209018 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11148 01:22:13.209100
11149 01:22:13.212452 debian-bookworm-arm64 login: root (automatic login)
11150 01:22:13.212534
11151 01:22:13.212598
11152 01:22:13.478612 Linux debian-bookworm-arm64 6.1.86-cip19 #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024 aarch64
11153 01:22:13.478765
11154 01:22:13.485293 The programs included with the Debian GNU/Linux system are free software;
11155 01:22:13.491853 the exact distribution terms for each program are described in the
11156 01:22:13.495061 individual files in /usr/share/doc/*/copyright.
11157 01:22:13.495142
11158 01:22:13.502014 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11159 01:22:13.505353 permitted by applicable law.
11160 01:22:14.353129 Matched prompt #10: / #
11162 01:22:14.353401 Setting prompt string to ['/ #']
11163 01:22:14.353497 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11165 01:22:14.353693 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11166 01:22:14.353783 start: 2.2.6 expect-shell-connection (timeout 00:03:30) [common]
11167 01:22:14.353855 Setting prompt string to ['/ #']
11168 01:22:14.353916 Forcing a shell prompt, looking for ['/ #']
11170 01:22:14.404105 / #
11171 01:22:14.404228 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11172 01:22:14.404307 Waiting using forced prompt support (timeout 00:02:30)
11173 01:22:14.409048
11174 01:22:14.409311 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11175 01:22:14.409402 start: 2.2.7 export-device-env (timeout 00:03:30) [common]
11177 01:22:14.509682 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13468747/extract-nfsrootfs-v5xyip58'
11178 01:22:14.514660 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13468747/extract-nfsrootfs-v5xyip58'
11180 01:22:14.615127 / # export NFS_SERVER_IP='192.168.201.1'
11181 01:22:14.620128 export NFS_SERVER_IP='192.168.201.1'
11182 01:22:14.620410 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11183 01:22:14.620510 end: 2.2 depthcharge-retry (duration 00:01:30) [common]
11184 01:22:14.620599 end: 2 depthcharge-action (duration 00:01:30) [common]
11185 01:22:14.620692 start: 3 lava-test-retry (timeout 00:07:53) [common]
11186 01:22:14.620782 start: 3.1 lava-test-shell (timeout 00:07:53) [common]
11187 01:22:14.620859 Using namespace: common
11189 01:22:14.721136 / # #
11190 01:22:14.721264 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11191 01:22:14.726078 #
11192 01:22:14.726362 Using /lava-13468747
11194 01:22:14.826630 / # export SHELL=/bin/bash
11195 01:22:14.831457 export SHELL=/bin/bash
11197 01:22:14.931917 / # . /lava-13468747/environment
11198 01:22:14.937143 . /lava-13468747/environment
11200 01:22:15.042189 / # /lava-13468747/bin/lava-test-runner /lava-13468747/0
11201 01:22:15.042315 Test shell timeout: 10s (minimum of the action and connection timeout)
11202 01:22:15.047336 /lava-13468747/bin/lava-test-runner /lava-13468747/0
11203 01:22:15.264612 + export TESTRUN_ID=0_timesync-off
11204 01:22:15.267929 + TESTRUN_ID=0_timesync-off
11205 01:22:15.271593 + cd /lava-13468747/0/tests/0_timesync-off
11206 01:22:15.274619 ++ cat uuid
11207 01:22:15.277921 + UUID=13468747_1.6.2.3.1
11208 01:22:15.277996 + set +x
11209 01:22:15.281313 <LAVA_SIGNAL_STARTRUN 0_timesync-off 13468747_1.6.2.3.1>
11210 01:22:15.281571 Received signal: <STARTRUN> 0_timesync-off 13468747_1.6.2.3.1
11211 01:22:15.281644 Starting test lava.0_timesync-off (13468747_1.6.2.3.1)
11212 01:22:15.281737 Skipping test definition patterns.
11213 01:22:15.284655 + systemctl stop systemd-timesyncd
11214 01:22:15.360618 + set +x
11215 01:22:15.363754 <LAVA_SIGNAL_ENDRUN 0_timesync-off 13468747_1.6.2.3.1>
11216 01:22:15.364037 Received signal: <ENDRUN> 0_timesync-off 13468747_1.6.2.3.1
11217 01:22:15.364125 Ending use of test pattern.
11218 01:22:15.364189 Ending test lava.0_timesync-off (13468747_1.6.2.3.1), duration 0.08
11220 01:22:15.412480 + export TESTRUN_ID=1_kselftest-dt
11221 01:22:15.416159 + TESTRUN_ID=1_kselftest-dt
11222 01:22:15.418942 + cd /lava-13468747/0/tests/1_kselftest-dt
11223 01:22:15.422680 ++ cat uuid
11224 01:22:15.422780 + UUID=13468747_1.6.2.3.5
11225 01:22:15.425948 + set +x
11226 01:22:15.429336 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 13468747_1.6.2.3.5>
11227 01:22:15.429584 Received signal: <STARTRUN> 1_kselftest-dt 13468747_1.6.2.3.5
11228 01:22:15.429655 Starting test lava.1_kselftest-dt (13468747_1.6.2.3.5)
11229 01:22:15.429732 Skipping test definition patterns.
11230 01:22:15.432671 + cd ./automated/linux/kselftest/
11231 01:22:15.458727 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11232 01:22:15.482415 INFO: install_deps skipped
11233 01:22:15.966421 --2024-04-23 01:18:04-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11234 01:22:15.975648 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11235 01:22:16.102455 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11236 01:22:16.230723 HTTP request sent, awaiting response... 200 OK
11237 01:22:16.234009 Length: 1651524 (1.6M) [application/octet-stream]
11238 01:22:16.237369 Saving to: 'kselftest_armhf.tar.gz'
11239 01:22:16.237448
11240 01:22:16.237512
11241 01:22:16.483179 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11242 01:22:16.736618 kselftest_armhf.tar 2%[ ] 47.81K 186KB/s
11243 01:22:17.018045 kselftest_armhf.tar 13%[=> ] 218.91K 425KB/s
11244 01:22:17.152306 kselftest_armhf.tar 40%[=======> ] 658.68K 821KB/s
11245 01:22:17.158877 kselftest_armhf.tar 100%[===================>] 1.57M 1.68MB/s in 0.9s
11246 01:22:17.158979
11247 01:22:17.303522 2024-04-23 01:18:05 (1.68 MB/s) - 'kselftest_armhf.tar.gz' saved [1651524/1651524]
11248 01:22:17.303676
11249 01:22:20.694857 skiplist:
11250 01:22:20.698277 ========================================
11251 01:22:20.701793 ========================================
11252 01:22:20.755149 ============== Tests to run ===============
11253 01:22:20.759096 ===========End Tests to run ===============
11254 01:22:20.761674 shardfile-dt fail
11255 01:22:20.780122 ./kselftest.sh: 131: cannot open /lava-13468747/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11256 01:22:20.783271 + ../../utils/send-to-lava.sh ./output/result.txt
11257 01:22:20.825948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11258 01:22:20.826079 + set +x
11259 01:22:20.826356 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11261 01:22:20.832847 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 13468747_1.6.2.3.5>
11262 01:22:20.832926 <LAVA_TEST_RUNNER EXIT>
11263 01:22:20.833160 Received signal: <ENDRUN> 1_kselftest-dt 13468747_1.6.2.3.5
11264 01:22:20.833231 Ending use of test pattern.
11265 01:22:20.833291 Ending test lava.1_kselftest-dt (13468747_1.6.2.3.5), duration 5.40
11267 01:22:20.833512 ok: lava_test_shell seems to have completed
11268 01:22:20.833609 shardfile-dt: fail
11269 01:22:20.833705 end: 3.1 lava-test-shell (duration 00:00:06) [common]
11270 01:22:20.833823 end: 3 lava-test-retry (duration 00:00:06) [common]
11271 01:22:20.833920 start: 4 finalize (timeout 00:07:46) [common]
11272 01:22:20.834016 start: 4.1 power-off (timeout 00:00:30) [common]
11273 01:22:20.834316 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11274 01:22:20.912350 >> Command sent successfully.
11275 01:22:20.915151 Returned 0 in 0 seconds
11276 01:22:21.015598 end: 4.1 power-off (duration 00:00:00) [common]
11278 01:22:21.015924 start: 4.2 read-feedback (timeout 00:07:46) [common]
11279 01:22:21.016183 Listened to connection for namespace 'common' for up to 1s
11280 01:22:21.016503 Listened to connection for namespace 'common' for up to 1s
11281 01:22:22.017108 Finalising connection for namespace 'common'
11282 01:22:22.017299 Disconnecting from shell: Finalise
11283 01:22:22.017381 / #
11284 01:22:22.117697 end: 4.2 read-feedback (duration 00:00:01) [common]
11285 01:22:22.117861 end: 4 finalize (duration 00:00:01) [common]
11286 01:22:22.117995 Cleaning after the job
11287 01:22:22.118111 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468747/tftp-deploy-8daeronz/ramdisk
11288 01:22:22.120346 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468747/tftp-deploy-8daeronz/kernel
11289 01:22:22.131451 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468747/tftp-deploy-8daeronz/dtb
11290 01:22:22.131721 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468747/tftp-deploy-8daeronz/nfsrootfs
11291 01:22:22.196207 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468747/tftp-deploy-8daeronz/modules
11292 01:22:22.202220 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13468747
11293 01:22:22.765841 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13468747
11294 01:22:22.766020 Job finished correctly