Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 25
- Errors: 0
- Kernel Errors: 36
- Boot result: PASS
1 01:19:13.752521 lava-dispatcher, installed at version: 2024.01
2 01:19:13.752732 start: 0 validate
3 01:19:13.752858 Start time: 2024-04-23 01:19:13.752849+00:00 (UTC)
4 01:19:13.752976 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:19:13.753105 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:19:14.009544 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:19:14.010316 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:19:14.267967 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:19:14.268716 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:19:14.527141 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:19:14.527903 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:19:14.785007 Using caching service: 'http://localhost/cache/?uri=%s'
13 01:19:14.785763 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 01:19:15.054285 validate duration: 1.30
16 01:19:15.055566 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:19:15.056091 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:19:15.056561 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:19:15.057166 Not decompressing ramdisk as can be used compressed.
20 01:19:15.057631 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 01:19:15.057986 saving as /var/lib/lava/dispatcher/tmp/13468762/tftp-deploy-p9xkn4mi/ramdisk/initrd.cpio.gz
22 01:19:15.058410 total size: 5628169 (5 MB)
23 01:19:15.063762 progress 0 % (0 MB)
24 01:19:15.073300 progress 5 % (0 MB)
25 01:19:15.081190 progress 10 % (0 MB)
26 01:19:15.085964 progress 15 % (0 MB)
27 01:19:15.090211 progress 20 % (1 MB)
28 01:19:15.093523 progress 25 % (1 MB)
29 01:19:15.096678 progress 30 % (1 MB)
30 01:19:15.099534 progress 35 % (1 MB)
31 01:19:15.101752 progress 40 % (2 MB)
32 01:19:15.104244 progress 45 % (2 MB)
33 01:19:15.106211 progress 50 % (2 MB)
34 01:19:15.108379 progress 55 % (2 MB)
35 01:19:15.110397 progress 60 % (3 MB)
36 01:19:15.112119 progress 65 % (3 MB)
37 01:19:15.114063 progress 70 % (3 MB)
38 01:19:15.115609 progress 75 % (4 MB)
39 01:19:15.117348 progress 80 % (4 MB)
40 01:19:15.118922 progress 85 % (4 MB)
41 01:19:15.120543 progress 90 % (4 MB)
42 01:19:15.122136 progress 95 % (5 MB)
43 01:19:15.123567 progress 100 % (5 MB)
44 01:19:15.123779 5 MB downloaded in 0.07 s (82.07 MB/s)
45 01:19:15.123938 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:19:15.124192 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:19:15.124275 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:19:15.124357 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:19:15.124484 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 01:19:15.124555 saving as /var/lib/lava/dispatcher/tmp/13468762/tftp-deploy-p9xkn4mi/kernel/Image
52 01:19:15.124614 total size: 54352384 (51 MB)
53 01:19:15.124675 No compression specified
54 01:19:15.125738 progress 0 % (0 MB)
55 01:19:15.139466 progress 5 % (2 MB)
56 01:19:15.153329 progress 10 % (5 MB)
57 01:19:15.167086 progress 15 % (7 MB)
58 01:19:15.180621 progress 20 % (10 MB)
59 01:19:15.194067 progress 25 % (12 MB)
60 01:19:15.207553 progress 30 % (15 MB)
61 01:19:15.220823 progress 35 % (18 MB)
62 01:19:15.234333 progress 40 % (20 MB)
63 01:19:15.248191 progress 45 % (23 MB)
64 01:19:15.261841 progress 50 % (25 MB)
65 01:19:15.275538 progress 55 % (28 MB)
66 01:19:15.289145 progress 60 % (31 MB)
67 01:19:15.302913 progress 65 % (33 MB)
68 01:19:15.316570 progress 70 % (36 MB)
69 01:19:15.330178 progress 75 % (38 MB)
70 01:19:15.343654 progress 80 % (41 MB)
71 01:19:15.357862 progress 85 % (44 MB)
72 01:19:15.371993 progress 90 % (46 MB)
73 01:19:15.385657 progress 95 % (49 MB)
74 01:19:15.399334 progress 100 % (51 MB)
75 01:19:15.399549 51 MB downloaded in 0.27 s (188.54 MB/s)
76 01:19:15.399769 end: 1.2.1 http-download (duration 00:00:00) [common]
78 01:19:15.400089 end: 1.2 download-retry (duration 00:00:00) [common]
79 01:19:15.400232 start: 1.3 download-retry (timeout 00:10:00) [common]
80 01:19:15.400331 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 01:19:15.400462 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 01:19:15.400531 saving as /var/lib/lava/dispatcher/tmp/13468762/tftp-deploy-p9xkn4mi/dtb/mt8192-asurada-spherion-r0.dtb
83 01:19:15.400591 total size: 47230 (0 MB)
84 01:19:15.400653 No compression specified
85 01:19:15.401738 progress 69 % (0 MB)
86 01:19:15.402001 progress 100 % (0 MB)
87 01:19:15.402197 0 MB downloaded in 0.00 s (28.08 MB/s)
88 01:19:15.402316 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:19:15.402533 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:19:15.402614 start: 1.4 download-retry (timeout 00:10:00) [common]
92 01:19:15.402694 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 01:19:15.402801 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 01:19:15.402867 saving as /var/lib/lava/dispatcher/tmp/13468762/tftp-deploy-p9xkn4mi/nfsrootfs/full.rootfs.tar
95 01:19:15.402926 total size: 120894716 (115 MB)
96 01:19:15.402986 Using unxz to decompress xz
97 01:19:15.406904 progress 0 % (0 MB)
98 01:19:15.744251 progress 5 % (5 MB)
99 01:19:16.092928 progress 10 % (11 MB)
100 01:19:16.434612 progress 15 % (17 MB)
101 01:19:16.757200 progress 20 % (23 MB)
102 01:19:17.045411 progress 25 % (28 MB)
103 01:19:17.396388 progress 30 % (34 MB)
104 01:19:17.730138 progress 35 % (40 MB)
105 01:19:17.892749 progress 40 % (46 MB)
106 01:19:18.067051 progress 45 % (51 MB)
107 01:19:18.368631 progress 50 % (57 MB)
108 01:19:18.740469 progress 55 % (63 MB)
109 01:19:19.076734 progress 60 % (69 MB)
110 01:19:19.410245 progress 65 % (74 MB)
111 01:19:19.751407 progress 70 % (80 MB)
112 01:19:20.106301 progress 75 % (86 MB)
113 01:19:20.442084 progress 80 % (92 MB)
114 01:19:20.773811 progress 85 % (98 MB)
115 01:19:21.126475 progress 90 % (103 MB)
116 01:19:21.444445 progress 95 % (109 MB)
117 01:19:21.791787 progress 100 % (115 MB)
118 01:19:21.796940 115 MB downloaded in 6.39 s (18.03 MB/s)
119 01:19:21.797212 end: 1.4.1 http-download (duration 00:00:06) [common]
121 01:19:21.797479 end: 1.4 download-retry (duration 00:00:06) [common]
122 01:19:21.797568 start: 1.5 download-retry (timeout 00:09:53) [common]
123 01:19:21.797655 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 01:19:21.797806 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 01:19:21.797878 saving as /var/lib/lava/dispatcher/tmp/13468762/tftp-deploy-p9xkn4mi/modules/modules.tar
126 01:19:21.797939 total size: 8638160 (8 MB)
127 01:19:21.798003 Using unxz to decompress xz
128 01:19:21.801993 progress 0 % (0 MB)
129 01:19:21.820550 progress 5 % (0 MB)
130 01:19:21.844412 progress 10 % (0 MB)
131 01:19:21.868028 progress 15 % (1 MB)
132 01:19:21.890831 progress 20 % (1 MB)
133 01:19:21.914655 progress 25 % (2 MB)
134 01:19:21.939527 progress 30 % (2 MB)
135 01:19:21.963029 progress 35 % (2 MB)
136 01:19:21.987701 progress 40 % (3 MB)
137 01:19:22.011059 progress 45 % (3 MB)
138 01:19:22.035340 progress 50 % (4 MB)
139 01:19:22.059817 progress 55 % (4 MB)
140 01:19:22.087943 progress 60 % (4 MB)
141 01:19:22.112602 progress 65 % (5 MB)
142 01:19:22.137054 progress 70 % (5 MB)
143 01:19:22.160977 progress 75 % (6 MB)
144 01:19:22.185649 progress 80 % (6 MB)
145 01:19:22.212925 progress 85 % (7 MB)
146 01:19:22.238431 progress 90 % (7 MB)
147 01:19:22.266902 progress 95 % (7 MB)
148 01:19:22.292733 progress 100 % (8 MB)
149 01:19:22.298432 8 MB downloaded in 0.50 s (16.46 MB/s)
150 01:19:22.298690 end: 1.5.1 http-download (duration 00:00:01) [common]
152 01:19:22.298964 end: 1.5 download-retry (duration 00:00:01) [common]
153 01:19:22.299059 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 01:19:22.299155 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 01:19:25.681878 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13468762/extract-nfsrootfs-yac1dttm
156 01:19:25.682143 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 01:19:25.682247 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 01:19:25.682412 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s
159 01:19:25.682540 makedir: /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin
160 01:19:25.682639 makedir: /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/tests
161 01:19:25.682738 makedir: /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/results
162 01:19:25.682840 Creating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-add-keys
163 01:19:25.682981 Creating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-add-sources
164 01:19:25.683108 Creating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-background-process-start
165 01:19:25.683233 Creating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-background-process-stop
166 01:19:25.683358 Creating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-common-functions
167 01:19:25.683480 Creating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-echo-ipv4
168 01:19:25.683603 Creating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-install-packages
169 01:19:25.683726 Creating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-installed-packages
170 01:19:25.683848 Creating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-os-build
171 01:19:25.683969 Creating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-probe-channel
172 01:19:25.684090 Creating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-probe-ip
173 01:19:25.684211 Creating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-target-ip
174 01:19:25.684335 Creating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-target-mac
175 01:19:25.684456 Creating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-target-storage
176 01:19:25.684580 Creating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-test-case
177 01:19:25.684704 Creating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-test-event
178 01:19:25.684827 Creating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-test-feedback
179 01:19:25.684949 Creating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-test-raise
180 01:19:25.685070 Creating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-test-reference
181 01:19:25.685191 Creating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-test-runner
182 01:19:25.685317 Creating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-test-set
183 01:19:25.685439 Creating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-test-shell
184 01:19:25.687052 Updating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-add-keys (debian)
185 01:19:25.688105 Updating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-add-sources (debian)
186 01:19:25.688472 Updating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-install-packages (debian)
187 01:19:25.688700 Updating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-installed-packages (debian)
188 01:19:25.688996 Updating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/bin/lava-os-build (debian)
189 01:19:25.689253 Creating /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/environment
190 01:19:25.689353 LAVA metadata
191 01:19:25.689424 - LAVA_JOB_ID=13468762
192 01:19:25.689487 - LAVA_DISPATCHER_IP=192.168.201.1
193 01:19:25.689585 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 01:19:25.689650 skipped lava-vland-overlay
195 01:19:25.689724 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 01:19:25.689801 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 01:19:25.689860 skipped lava-multinode-overlay
198 01:19:25.689930 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 01:19:25.690007 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 01:19:25.690232 Loading test definitions
201 01:19:25.690320 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 01:19:25.690390 Using /lava-13468762 at stage 0
203 01:19:25.690665 uuid=13468762_1.6.2.3.1 testdef=None
204 01:19:25.690752 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 01:19:25.690835 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 01:19:25.691276 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 01:19:25.691492 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 01:19:25.692032 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 01:19:25.692257 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 01:19:25.692775 runner path: /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/0/tests/0_timesync-off test_uuid 13468762_1.6.2.3.1
213 01:19:25.692929 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 01:19:25.693150 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 01:19:25.693221 Using /lava-13468762 at stage 0
217 01:19:25.693314 Fetching tests from https://github.com/kernelci/test-definitions.git
218 01:19:25.693399 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/0/tests/1_kselftest-rtc'
219 01:19:29.245073 Running '/usr/bin/git checkout kernelci.org
220 01:19:29.389735 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 01:19:29.390633 uuid=13468762_1.6.2.3.5 testdef=None
222 01:19:29.390789 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 01:19:29.391039 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 01:19:29.391775 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 01:19:29.392042 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 01:19:29.393022 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 01:19:29.393259 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 01:19:29.394226 runner path: /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/0/tests/1_kselftest-rtc test_uuid 13468762_1.6.2.3.5
232 01:19:29.394316 BOARD='mt8192-asurada-spherion-r0'
233 01:19:29.394382 BRANCH='cip'
234 01:19:29.394442 SKIPFILE='/dev/null'
235 01:19:29.394500 SKIP_INSTALL='True'
236 01:19:29.394560 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 01:19:29.394618 TST_CASENAME=''
238 01:19:29.394673 TST_CMDFILES='rtc'
239 01:19:29.394813 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 01:19:29.395020 Creating lava-test-runner.conf files
242 01:19:29.395083 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13468762/lava-overlay-04fh9f9s/lava-13468762/0 for stage 0
243 01:19:29.395175 - 0_timesync-off
244 01:19:29.395243 - 1_kselftest-rtc
245 01:19:29.395337 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 01:19:29.395424 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 01:19:36.755993 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 01:19:36.756151 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 01:19:36.756246 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 01:19:36.756342 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 01:19:36.756430 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 01:19:36.916952 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 01:19:36.917342 start: 1.6.4 extract-modules (timeout 00:09:38) [common]
254 01:19:36.917518 extracting modules file /var/lib/lava/dispatcher/tmp/13468762/tftp-deploy-p9xkn4mi/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13468762/extract-nfsrootfs-yac1dttm
255 01:19:37.128283 extracting modules file /var/lib/lava/dispatcher/tmp/13468762/tftp-deploy-p9xkn4mi/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13468762/extract-overlay-ramdisk-ervojmug/ramdisk
256 01:19:37.344033 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 01:19:37.344208 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 01:19:37.344303 [common] Applying overlay to NFS
259 01:19:37.344376 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13468762/compress-overlay-7833d9ts/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13468762/extract-nfsrootfs-yac1dttm
260 01:19:38.247583 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 01:19:38.247746 start: 1.6.6 configure-preseed-file (timeout 00:09:37) [common]
262 01:19:38.247844 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 01:19:38.247930 start: 1.6.7 compress-ramdisk (timeout 00:09:37) [common]
264 01:19:38.248010 Building ramdisk /var/lib/lava/dispatcher/tmp/13468762/extract-overlay-ramdisk-ervojmug/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13468762/extract-overlay-ramdisk-ervojmug/ramdisk
265 01:19:38.591260 >> 130624 blocks
266 01:19:40.602226 rename /var/lib/lava/dispatcher/tmp/13468762/extract-overlay-ramdisk-ervojmug/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13468762/tftp-deploy-p9xkn4mi/ramdisk/ramdisk.cpio.gz
267 01:19:40.602681 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 01:19:40.602799 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 01:19:40.602899 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 01:19:40.603004 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13468762/tftp-deploy-p9xkn4mi/kernel/Image'
271 01:19:53.212424 Returned 0 in 12 seconds
272 01:19:53.313431 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13468762/tftp-deploy-p9xkn4mi/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13468762/tftp-deploy-p9xkn4mi/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13468762/tftp-deploy-p9xkn4mi/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13468762/tftp-deploy-p9xkn4mi/kernel/image.itb
273 01:19:53.687862 output: FIT description: Kernel Image image with one or more FDT blobs
274 01:19:53.688243 output: Created: Tue Apr 23 02:19:53 2024
275 01:19:53.688321 output: Image 0 (kernel-1)
276 01:19:53.688388 output: Description:
277 01:19:53.688450 output: Created: Tue Apr 23 02:19:53 2024
278 01:19:53.688508 output: Type: Kernel Image
279 01:19:53.688570 output: Compression: lzma compressed
280 01:19:53.688627 output: Data Size: 12910050 Bytes = 12607.47 KiB = 12.31 MiB
281 01:19:53.688687 output: Architecture: AArch64
282 01:19:53.688746 output: OS: Linux
283 01:19:53.688803 output: Load Address: 0x00000000
284 01:19:53.688860 output: Entry Point: 0x00000000
285 01:19:53.688943 output: Hash algo: crc32
286 01:19:53.689055 output: Hash value: 1126c3f9
287 01:19:53.689119 output: Image 1 (fdt-1)
288 01:19:53.689177 output: Description: mt8192-asurada-spherion-r0
289 01:19:53.689233 output: Created: Tue Apr 23 02:19:53 2024
290 01:19:53.689286 output: Type: Flat Device Tree
291 01:19:53.689339 output: Compression: uncompressed
292 01:19:53.689392 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
293 01:19:53.689444 output: Architecture: AArch64
294 01:19:53.689497 output: Hash algo: crc32
295 01:19:53.689548 output: Hash value: 4bf0d1ac
296 01:19:53.689600 output: Image 2 (ramdisk-1)
297 01:19:53.689652 output: Description: unavailable
298 01:19:53.689704 output: Created: Tue Apr 23 02:19:53 2024
299 01:19:53.689756 output: Type: RAMDisk Image
300 01:19:53.689808 output: Compression: Unknown Compression
301 01:19:53.689860 output: Data Size: 18775754 Bytes = 18335.70 KiB = 17.91 MiB
302 01:19:53.689912 output: Architecture: AArch64
303 01:19:53.689963 output: OS: Linux
304 01:19:53.690015 output: Load Address: unavailable
305 01:19:53.690098 output: Entry Point: unavailable
306 01:19:53.690163 output: Hash algo: crc32
307 01:19:53.690214 output: Hash value: ff919966
308 01:19:53.690266 output: Default Configuration: 'conf-1'
309 01:19:53.690318 output: Configuration 0 (conf-1)
310 01:19:53.690369 output: Description: mt8192-asurada-spherion-r0
311 01:19:53.690421 output: Kernel: kernel-1
312 01:19:53.690472 output: Init Ramdisk: ramdisk-1
313 01:19:53.690524 output: FDT: fdt-1
314 01:19:53.690575 output: Loadables: kernel-1
315 01:19:53.690627 output:
316 01:19:53.690826 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 01:19:53.690921 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 01:19:53.691021 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 01:19:53.691112 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 01:19:53.691195 No LXC device requested
321 01:19:53.691272 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 01:19:53.691357 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 01:19:53.691432 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 01:19:53.691497 Checking files for TFTP limit of 4294967296 bytes.
325 01:19:53.691983 end: 1 tftp-deploy (duration 00:00:39) [common]
326 01:19:53.692089 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 01:19:53.692179 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 01:19:53.692305 substitutions:
329 01:19:53.692371 - {DTB}: 13468762/tftp-deploy-p9xkn4mi/dtb/mt8192-asurada-spherion-r0.dtb
330 01:19:53.692436 - {INITRD}: 13468762/tftp-deploy-p9xkn4mi/ramdisk/ramdisk.cpio.gz
331 01:19:53.692495 - {KERNEL}: 13468762/tftp-deploy-p9xkn4mi/kernel/Image
332 01:19:53.692552 - {LAVA_MAC}: None
333 01:19:53.692607 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13468762/extract-nfsrootfs-yac1dttm
334 01:19:53.692662 - {NFS_SERVER_IP}: 192.168.201.1
335 01:19:53.692716 - {PRESEED_CONFIG}: None
336 01:19:53.692770 - {PRESEED_LOCAL}: None
337 01:19:53.692823 - {RAMDISK}: 13468762/tftp-deploy-p9xkn4mi/ramdisk/ramdisk.cpio.gz
338 01:19:53.692875 - {ROOT_PART}: None
339 01:19:53.692946 - {ROOT}: None
340 01:19:53.693000 - {SERVER_IP}: 192.168.201.1
341 01:19:53.693066 - {TEE}: None
342 01:19:53.693128 Parsed boot commands:
343 01:19:53.693188 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 01:19:53.693366 Parsed boot commands: tftpboot 192.168.201.1 13468762/tftp-deploy-p9xkn4mi/kernel/image.itb 13468762/tftp-deploy-p9xkn4mi/kernel/cmdline
345 01:19:53.693454 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 01:19:53.693538 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 01:19:53.693629 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 01:19:53.693713 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 01:19:53.693791 Not connected, no need to disconnect.
350 01:19:53.693864 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 01:19:53.693944 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 01:19:53.694010 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 01:19:53.697922 Setting prompt string to ['lava-test: # ']
354 01:19:53.698311 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 01:19:53.698416 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 01:19:53.698510 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 01:19:53.698649 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 01:19:53.698894 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
359 01:19:58.844455 >> Command sent successfully.
360 01:19:58.855549 Returned 0 in 5 seconds
361 01:19:58.956929 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 01:19:58.958588 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 01:19:58.959153 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 01:19:58.959628 Setting prompt string to 'Starting depthcharge on Spherion...'
366 01:19:58.960043 Changing prompt to 'Starting depthcharge on Spherion...'
367 01:19:58.960432 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 01:19:58.961790 [Enter `^Ec?' for help]
369 01:19:59.126092
370 01:19:59.126698
371 01:19:59.127129 F0: 102B 0000
372 01:19:59.127540
373 01:19:59.127914 F3: 1001 0000 [0200]
374 01:19:59.128470
375 01:19:59.129452 F3: 1001 0000
376 01:19:59.129886
377 01:19:59.130396 F7: 102D 0000
378 01:19:59.130760
379 01:19:59.131097 F1: 0000 0000
380 01:19:59.131429
381 01:19:59.133771 V0: 0000 0000 [0001]
382 01:19:59.134300
383 01:19:59.134685 00: 0007 8000
384 01:19:59.135072
385 01:19:59.137253 01: 0000 0000
386 01:19:59.137863
387 01:19:59.138327 BP: 0C00 0209 [0000]
388 01:19:59.138695
389 01:19:59.140896 G0: 1182 0000
390 01:19:59.141376
391 01:19:59.141804 EC: 0000 0021 [4000]
392 01:19:59.142214
393 01:19:59.144536 S7: 0000 0000 [0000]
394 01:19:59.145015
395 01:19:59.145396 CC: 0000 0000 [0001]
396 01:19:59.145755
397 01:19:59.147693 T0: 0000 0040 [010F]
398 01:19:59.148353
399 01:19:59.149012 Jump to BL
400 01:19:59.149399
401 01:19:59.172836
402 01:19:59.173416
403 01:19:59.173799
404 01:19:59.180230 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 01:19:59.183837 ARM64: Exception handlers installed.
406 01:19:59.187701 ARM64: Testing exception
407 01:19:59.191611 ARM64: Done test exception
408 01:19:59.198420 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 01:19:59.206007 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 01:19:59.212784 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 01:19:59.223970 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 01:19:59.229995 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 01:19:59.240978 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 01:19:59.250875 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 01:19:59.257487 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 01:19:59.276075 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 01:19:59.279213 WDT: Last reset was cold boot
418 01:19:59.282307 SPI1(PAD0) initialized at 2873684 Hz
419 01:19:59.285820 SPI5(PAD0) initialized at 992727 Hz
420 01:19:59.288702 VBOOT: Loading verstage.
421 01:19:59.295995 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 01:19:59.298734 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 01:19:59.302300 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 01:19:59.305631 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 01:19:59.313108 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 01:19:59.319807 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 01:19:59.331048 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 01:19:59.331640
429 01:19:59.332028
430 01:19:59.340877 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 01:19:59.343627 ARM64: Exception handlers installed.
432 01:19:59.347149 ARM64: Testing exception
433 01:19:59.347734 ARM64: Done test exception
434 01:19:59.353593 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 01:19:59.357152 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 01:19:59.371586 Probing TPM: . done!
437 01:19:59.372185 TPM ready after 0 ms
438 01:19:59.378604 Connected to device vid:did:rid of 1ae0:0028:00
439 01:19:59.385404 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
440 01:19:59.436250 Initialized TPM device CR50 revision 0
441 01:19:59.439319 tlcl_send_startup: Startup return code is 0
442 01:19:59.448544 TPM: setup succeeded
443 01:19:59.459529 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 01:19:59.468420 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 01:19:59.477715 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 01:19:59.486652 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 01:19:59.490189 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 01:19:59.493361 in-header: 03 07 00 00 08 00 00 00
449 01:19:59.496529 in-data: aa e4 47 04 13 02 00 00
450 01:19:59.499997 Chrome EC: UHEPI supported
451 01:19:59.506486 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 01:19:59.510423 in-header: 03 95 00 00 08 00 00 00
453 01:19:59.513821 in-data: 18 20 20 08 00 00 00 00
454 01:19:59.514447 Phase 1
455 01:19:59.517205 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 01:19:59.524424 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 01:19:59.531689 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 01:19:59.532168 Recovery requested (1009000e)
459 01:19:59.541467 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 01:19:59.546539 tlcl_extend: response is 0
461 01:19:59.556183 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 01:19:59.561720 tlcl_extend: response is 0
463 01:19:59.568938 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 01:19:59.589293 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 01:19:59.595964 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 01:19:59.596531
467 01:19:59.596989
468 01:19:59.603930 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 01:19:59.607626 ARM64: Exception handlers installed.
470 01:19:59.610947 ARM64: Testing exception
471 01:19:59.615026 ARM64: Done test exception
472 01:19:59.633950 pmic_efuse_setting: Set efuses in 11 msecs
473 01:19:59.637565 pmwrap_interface_init: Select PMIF_VLD_RDY
474 01:19:59.644093 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 01:19:59.647331 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 01:19:59.654009 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 01:19:59.657417 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 01:19:59.664021 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 01:19:59.667234 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 01:19:59.673797 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 01:19:59.677579 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 01:19:59.680958 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 01:19:59.687098 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 01:19:59.690733 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 01:19:59.697385 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 01:19:59.700377 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 01:19:59.707419 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 01:19:59.710806 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 01:19:59.718132 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 01:19:59.725537 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 01:19:59.729013 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 01:19:59.736713 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 01:19:59.740149 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 01:19:59.747227 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 01:19:59.751038 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 01:19:59.758638 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 01:19:59.762379 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 01:19:59.769542 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 01:19:59.772873 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 01:19:59.780203 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 01:19:59.784397 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 01:19:59.787551 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 01:19:59.791536 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 01:19:59.798798 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 01:19:59.802490 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 01:19:59.809560 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 01:19:59.813415 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 01:19:59.816896 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 01:19:59.824017 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 01:19:59.827943 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 01:19:59.831215 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 01:19:59.838848 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 01:19:59.842330 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 01:19:59.846065 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 01:19:59.849435 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 01:19:59.856650 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 01:19:59.860326 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 01:19:59.863956 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 01:19:59.867270 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 01:19:59.871176 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 01:19:59.878140 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 01:19:59.881592 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 01:19:59.885169 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 01:19:59.888703 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 01:19:59.896706 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 01:19:59.903631 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 01:19:59.911129 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 01:19:59.918257 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 01:19:59.925411 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 01:19:59.932845 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 01:19:59.936579 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 01:19:59.939704 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 01:19:59.947156 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x13
534 01:19:59.954351 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 01:19:59.957955 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 01:19:59.961087 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 01:19:59.971487 [RTC]rtc_get_frequency_meter,154: input=15, output=764
538 01:19:59.981409 [RTC]rtc_get_frequency_meter,154: input=23, output=949
539 01:19:59.990622 [RTC]rtc_get_frequency_meter,154: input=19, output=857
540 01:19:59.999833 [RTC]rtc_get_frequency_meter,154: input=17, output=811
541 01:20:00.009902 [RTC]rtc_get_frequency_meter,154: input=16, output=787
542 01:20:00.019368 [RTC]rtc_get_frequency_meter,154: input=16, output=786
543 01:20:00.029086 [RTC]rtc_get_frequency_meter,154: input=17, output=809
544 01:20:00.033041 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 01:20:00.037005 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 01:20:00.040845 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 01:20:00.047821 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 01:20:00.051585 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 01:20:00.055163 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 01:20:00.058768 ADC[4]: Raw value=670432 ID=5
551 01:20:00.059243 ADC[3]: Raw value=212917 ID=1
552 01:20:00.062152 RAM Code: 0x51
553 01:20:00.066469 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 01:20:00.069815 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 01:20:00.076891 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
556 01:20:00.084304 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
557 01:20:00.087352 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 01:20:00.091486 in-header: 03 07 00 00 08 00 00 00
559 01:20:00.095006 in-data: aa e4 47 04 13 02 00 00
560 01:20:00.098467 Chrome EC: UHEPI supported
561 01:20:00.106185 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 01:20:00.109765 in-header: 03 95 00 00 08 00 00 00
563 01:20:00.110439 in-data: 18 20 20 08 00 00 00 00
564 01:20:00.113540 MRC: failed to locate region type 0.
565 01:20:00.121432 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 01:20:00.124693 DRAM-K: Running full calibration
567 01:20:00.131663 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
568 01:20:00.132259 header.status = 0x0
569 01:20:00.135195 header.version = 0x6 (expected: 0x6)
570 01:20:00.139272 header.size = 0xd00 (expected: 0xd00)
571 01:20:00.139751 header.flags = 0x0
572 01:20:00.146246 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 01:20:00.164558 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 01:20:00.172064 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 01:20:00.175503 dram_init: ddr_geometry: 0
576 01:20:00.175982 [EMI] MDL number = 0
577 01:20:00.179264 [EMI] Get MDL freq = 0
578 01:20:00.179745 dram_init: ddr_type: 0
579 01:20:00.182732 is_discrete_lpddr4: 1
580 01:20:00.186508 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 01:20:00.186991
582 01:20:00.187372
583 01:20:00.187725 [Bian_co] ETT version 0.0.0.1
584 01:20:00.194265 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
585 01:20:00.194879
586 01:20:00.198002 dramc_set_vcore_voltage set vcore to 650000
587 01:20:00.198680 Read voltage for 800, 4
588 01:20:00.201431 Vio18 = 0
589 01:20:00.201927 Vcore = 650000
590 01:20:00.202373 Vdram = 0
591 01:20:00.202759 Vddq = 0
592 01:20:00.205219 Vmddr = 0
593 01:20:00.205826 dram_init: config_dvfs: 1
594 01:20:00.212477 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 01:20:00.216438 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 01:20:00.220346 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 01:20:00.223900 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 01:20:00.227754 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 01:20:00.231178 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 01:20:00.235188 MEM_TYPE=3, freq_sel=18
601 01:20:00.238679 sv_algorithm_assistance_LP4_1600
602 01:20:00.242117 ============ PULL DRAM RESETB DOWN ============
603 01:20:00.245959 ========== PULL DRAM RESETB DOWN end =========
604 01:20:00.249795 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 01:20:00.253165 ===================================
606 01:20:00.256856 LPDDR4 DRAM CONFIGURATION
607 01:20:00.260917 ===================================
608 01:20:00.261403 EX_ROW_EN[0] = 0x0
609 01:20:00.264611 EX_ROW_EN[1] = 0x0
610 01:20:00.265232 LP4Y_EN = 0x0
611 01:20:00.268279 WORK_FSP = 0x0
612 01:20:00.268914 WL = 0x2
613 01:20:00.269309 RL = 0x2
614 01:20:00.271847 BL = 0x2
615 01:20:00.272444 RPST = 0x0
616 01:20:00.275549 RD_PRE = 0x0
617 01:20:00.276022 WR_PRE = 0x1
618 01:20:00.279690 WR_PST = 0x0
619 01:20:00.280263 DBI_WR = 0x0
620 01:20:00.282883 DBI_RD = 0x0
621 01:20:00.283354 OTF = 0x1
622 01:20:00.286907 ===================================
623 01:20:00.290395 ===================================
624 01:20:00.291150 ANA top config
625 01:20:00.294154 ===================================
626 01:20:00.297856 DLL_ASYNC_EN = 0
627 01:20:00.301609 ALL_SLAVE_EN = 1
628 01:20:00.302124 NEW_RANK_MODE = 1
629 01:20:00.305095 DLL_IDLE_MODE = 1
630 01:20:00.309084 LP45_APHY_COMB_EN = 1
631 01:20:00.309713 TX_ODT_DIS = 1
632 01:20:00.312638 NEW_8X_MODE = 1
633 01:20:00.315786 ===================================
634 01:20:00.319958 ===================================
635 01:20:00.322491 data_rate = 1600
636 01:20:00.325745 CKR = 1
637 01:20:00.329130 DQ_P2S_RATIO = 8
638 01:20:00.332133 ===================================
639 01:20:00.336129 CA_P2S_RATIO = 8
640 01:20:00.336735 DQ_CA_OPEN = 0
641 01:20:00.339347 DQ_SEMI_OPEN = 0
642 01:20:00.343036 CA_SEMI_OPEN = 0
643 01:20:00.347116 CA_FULL_RATE = 0
644 01:20:00.347724 DQ_CKDIV4_EN = 1
645 01:20:00.350599 CA_CKDIV4_EN = 1
646 01:20:00.354285 CA_PREDIV_EN = 0
647 01:20:00.357439 PH8_DLY = 0
648 01:20:00.357939 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 01:20:00.360556 DQ_AAMCK_DIV = 4
650 01:20:00.364244 CA_AAMCK_DIV = 4
651 01:20:00.367706 CA_ADMCK_DIV = 4
652 01:20:00.370902 DQ_TRACK_CA_EN = 0
653 01:20:00.374368 CA_PICK = 800
654 01:20:00.374871 CA_MCKIO = 800
655 01:20:00.377483 MCKIO_SEMI = 0
656 01:20:00.381204 PLL_FREQ = 3068
657 01:20:00.384293 DQ_UI_PI_RATIO = 32
658 01:20:00.387396 CA_UI_PI_RATIO = 0
659 01:20:00.390998 ===================================
660 01:20:00.394507 ===================================
661 01:20:00.394989 memory_type:LPDDR4
662 01:20:00.398124 GP_NUM : 10
663 01:20:00.401845 SRAM_EN : 1
664 01:20:00.402500 MD32_EN : 0
665 01:20:00.405440 ===================================
666 01:20:00.409249 [ANA_INIT] >>>>>>>>>>>>>>
667 01:20:00.409834 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 01:20:00.412629 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 01:20:00.416592 ===================================
670 01:20:00.420500 data_rate = 1600,PCW = 0X7600
671 01:20:00.423601 ===================================
672 01:20:00.427250 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 01:20:00.430754 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 01:20:00.437658 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 01:20:00.441052 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 01:20:00.447629 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 01:20:00.451382 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 01:20:00.451967 [ANA_INIT] flow start
679 01:20:00.454114 [ANA_INIT] PLL >>>>>>>>
680 01:20:00.457684 [ANA_INIT] PLL <<<<<<<<
681 01:20:00.458208 [ANA_INIT] MIDPI >>>>>>>>
682 01:20:00.460995 [ANA_INIT] MIDPI <<<<<<<<
683 01:20:00.464026 [ANA_INIT] DLL >>>>>>>>
684 01:20:00.464512 [ANA_INIT] flow end
685 01:20:00.470998 ============ LP4 DIFF to SE enter ============
686 01:20:00.473937 ============ LP4 DIFF to SE exit ============
687 01:20:00.474570 [ANA_INIT] <<<<<<<<<<<<<
688 01:20:00.477392 [Flow] Enable top DCM control >>>>>
689 01:20:00.480805 [Flow] Enable top DCM control <<<<<
690 01:20:00.484195 Enable DLL master slave shuffle
691 01:20:00.490632 ==============================================================
692 01:20:00.491216 Gating Mode config
693 01:20:00.497242 ==============================================================
694 01:20:00.500570 Config description:
695 01:20:00.510765 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 01:20:00.517204 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 01:20:00.520773 SELPH_MODE 0: By rank 1: By Phase
698 01:20:00.526956 ==============================================================
699 01:20:00.530661 GAT_TRACK_EN = 1
700 01:20:00.533690 RX_GATING_MODE = 2
701 01:20:00.536955 RX_GATING_TRACK_MODE = 2
702 01:20:00.537533 SELPH_MODE = 1
703 01:20:00.540267 PICG_EARLY_EN = 1
704 01:20:00.543714 VALID_LAT_VALUE = 1
705 01:20:00.550285 ==============================================================
706 01:20:00.553217 Enter into Gating configuration >>>>
707 01:20:00.556811 Exit from Gating configuration <<<<
708 01:20:00.560150 Enter into DVFS_PRE_config >>>>>
709 01:20:00.570250 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 01:20:00.573697 Exit from DVFS_PRE_config <<<<<
711 01:20:00.577402 Enter into PICG configuration >>>>
712 01:20:00.579948 Exit from PICG configuration <<<<
713 01:20:00.583539 [RX_INPUT] configuration >>>>>
714 01:20:00.586424 [RX_INPUT] configuration <<<<<
715 01:20:00.590166 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 01:20:00.596657 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 01:20:00.603409 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 01:20:00.610266 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 01:20:00.613514 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 01:20:00.620049 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 01:20:00.623190 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 01:20:00.630210 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 01:20:00.633401 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 01:20:00.636419 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 01:20:00.639712 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 01:20:00.646602 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 01:20:00.649923 ===================================
728 01:20:00.653077 LPDDR4 DRAM CONFIGURATION
729 01:20:00.653560 ===================================
730 01:20:00.656725 EX_ROW_EN[0] = 0x0
731 01:20:00.659894 EX_ROW_EN[1] = 0x0
732 01:20:00.660373 LP4Y_EN = 0x0
733 01:20:00.663551 WORK_FSP = 0x0
734 01:20:00.664138 WL = 0x2
735 01:20:00.666537 RL = 0x2
736 01:20:00.667017 BL = 0x2
737 01:20:00.669956 RPST = 0x0
738 01:20:00.670595 RD_PRE = 0x0
739 01:20:00.673290 WR_PRE = 0x1
740 01:20:00.673884 WR_PST = 0x0
741 01:20:00.676825 DBI_WR = 0x0
742 01:20:00.677410 DBI_RD = 0x0
743 01:20:00.680006 OTF = 0x1
744 01:20:00.683386 ===================================
745 01:20:00.686711 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 01:20:00.690000 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 01:20:00.696526 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 01:20:00.699579 ===================================
749 01:20:00.700066 LPDDR4 DRAM CONFIGURATION
750 01:20:00.703348 ===================================
751 01:20:00.706922 EX_ROW_EN[0] = 0x10
752 01:20:00.709893 EX_ROW_EN[1] = 0x0
753 01:20:00.710518 LP4Y_EN = 0x0
754 01:20:00.713225 WORK_FSP = 0x0
755 01:20:00.713813 WL = 0x2
756 01:20:00.716717 RL = 0x2
757 01:20:00.717196 BL = 0x2
758 01:20:00.719690 RPST = 0x0
759 01:20:00.720170 RD_PRE = 0x0
760 01:20:00.723126 WR_PRE = 0x1
761 01:20:00.723721 WR_PST = 0x0
762 01:20:00.726642 DBI_WR = 0x0
763 01:20:00.727121 DBI_RD = 0x0
764 01:20:00.729868 OTF = 0x1
765 01:20:00.732919 ===================================
766 01:20:00.739739 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 01:20:00.743016 nWR fixed to 40
768 01:20:00.743595 [ModeRegInit_LP4] CH0 RK0
769 01:20:00.746156 [ModeRegInit_LP4] CH0 RK1
770 01:20:00.749961 [ModeRegInit_LP4] CH1 RK0
771 01:20:00.753182 [ModeRegInit_LP4] CH1 RK1
772 01:20:00.753756 match AC timing 12
773 01:20:00.756491 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
774 01:20:00.763131 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 01:20:00.766251 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 01:20:00.769945 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 01:20:00.776638 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 01:20:00.777220 [EMI DOE] emi_dcm 0
779 01:20:00.783050 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 01:20:00.783624 ==
781 01:20:00.786594 Dram Type= 6, Freq= 0, CH_0, rank 0
782 01:20:00.789702 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
783 01:20:00.790241 ==
784 01:20:00.796128 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 01:20:00.799398 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 01:20:00.810079 [CA 0] Center 37 (7~68) winsize 62
787 01:20:00.812992 [CA 1] Center 37 (7~68) winsize 62
788 01:20:00.816303 [CA 2] Center 35 (5~66) winsize 62
789 01:20:00.819426 [CA 3] Center 35 (4~66) winsize 63
790 01:20:00.823006 [CA 4] Center 34 (3~65) winsize 63
791 01:20:00.825983 [CA 5] Center 33 (3~64) winsize 62
792 01:20:00.826507
793 01:20:00.829496 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 01:20:00.829968
795 01:20:00.832717 [CATrainingPosCal] consider 1 rank data
796 01:20:00.835979 u2DelayCellTimex100 = 270/100 ps
797 01:20:00.839518 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 01:20:00.845821 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
799 01:20:00.849430 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
800 01:20:00.852599 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
801 01:20:00.855852 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
802 01:20:00.859197 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 01:20:00.859773
804 01:20:00.862598 CA PerBit enable=1, Macro0, CA PI delay=33
805 01:20:00.863074
806 01:20:00.865783 [CBTSetCACLKResult] CA Dly = 33
807 01:20:00.866309 CS Dly: 5 (0~36)
808 01:20:00.869659 ==
809 01:20:00.872488 Dram Type= 6, Freq= 0, CH_0, rank 1
810 01:20:00.876095 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
811 01:20:00.876571 ==
812 01:20:00.879427 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 01:20:00.886075 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 01:20:00.895700 [CA 0] Center 37 (7~68) winsize 62
815 01:20:00.898892 [CA 1] Center 37 (6~68) winsize 63
816 01:20:00.902148 [CA 2] Center 35 (5~66) winsize 62
817 01:20:00.905656 [CA 3] Center 35 (5~66) winsize 62
818 01:20:00.908981 [CA 4] Center 34 (3~65) winsize 63
819 01:20:00.912529 [CA 5] Center 34 (3~65) winsize 63
820 01:20:00.913159
821 01:20:00.915560 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 01:20:00.916038
823 01:20:00.919033 [CATrainingPosCal] consider 2 rank data
824 01:20:00.922711 u2DelayCellTimex100 = 270/100 ps
825 01:20:00.925777 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 01:20:00.929147 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 01:20:00.932370 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
828 01:20:00.939442 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
829 01:20:00.942820 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
830 01:20:00.945911 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 01:20:00.946391
832 01:20:00.949305 CA PerBit enable=1, Macro0, CA PI delay=33
833 01:20:00.949739
834 01:20:00.952712 [CBTSetCACLKResult] CA Dly = 33
835 01:20:00.953278 CS Dly: 5 (0~37)
836 01:20:00.953641
837 01:20:00.955922 ----->DramcWriteLeveling(PI) begin...
838 01:20:00.956363 ==
839 01:20:00.958848 Dram Type= 6, Freq= 0, CH_0, rank 0
840 01:20:00.965736 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
841 01:20:00.966203 ==
842 01:20:00.969056 Write leveling (Byte 0): 31 => 31
843 01:20:00.972917 Write leveling (Byte 1): 28 => 28
844 01:20:00.973466 DramcWriteLeveling(PI) end<-----
845 01:20:00.973818
846 01:20:00.976225 ==
847 01:20:00.976707 Dram Type= 6, Freq= 0, CH_0, rank 0
848 01:20:00.983840 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
849 01:20:00.984279 ==
850 01:20:00.984628 [Gating] SW mode calibration
851 01:20:00.990337 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 01:20:00.996899 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 01:20:01.000686 0 6 0 | B1->B0 | 3232 3030 | 1 1 | (1 0) (1 0)
854 01:20:01.004123 0 6 4 | B1->B0 | 2929 2525 | 0 0 | (0 0) (0 0)
855 01:20:01.010813 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 01:20:01.013890 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 01:20:01.017403 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 01:20:01.024326 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 01:20:01.027654 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 01:20:01.030972 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 01:20:01.037647 0 7 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
862 01:20:01.040862 0 7 4 | B1->B0 | 3939 3c3c | 1 1 | (0 0) (0 0)
863 01:20:01.044214 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 01:20:01.050723 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 01:20:01.054447 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 01:20:01.057882 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 01:20:01.064490 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 01:20:01.067868 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 01:20:01.070710 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
870 01:20:01.077459 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
871 01:20:01.081339 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 01:20:01.084870 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 01:20:01.090770 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 01:20:01.094134 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 01:20:01.097530 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 01:20:01.104252 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 01:20:01.107578 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 01:20:01.110764 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 01:20:01.114433 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 01:20:01.120817 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 01:20:01.124187 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 01:20:01.127310 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 01:20:01.134271 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 01:20:01.137664 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 01:20:01.141082 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
886 01:20:01.147629 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 01:20:01.151023 Total UI for P1: 0, mck2ui 16
888 01:20:01.154486 best dqsien dly found for B0: ( 0, 10, 2)
889 01:20:01.155277 Total UI for P1: 0, mck2ui 16
890 01:20:01.160670 best dqsien dly found for B1: ( 0, 10, 0)
891 01:20:01.164149 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
892 01:20:01.167507 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
893 01:20:01.168079
894 01:20:01.171154 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
895 01:20:01.173902 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
896 01:20:01.177468 [Gating] SW calibration Done
897 01:20:01.177944 ==
898 01:20:01.180881 Dram Type= 6, Freq= 0, CH_0, rank 0
899 01:20:01.184355 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 01:20:01.184950 ==
901 01:20:01.187452 RX Vref Scan: 0
902 01:20:01.187927
903 01:20:01.188303 RX Vref 0 -> 0, step: 1
904 01:20:01.188661
905 01:20:01.191008 RX Delay -130 -> 252, step: 16
906 01:20:01.194389 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
907 01:20:01.200717 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
908 01:20:01.204285 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
909 01:20:01.207625 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
910 01:20:01.210638 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
911 01:20:01.214200 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
912 01:20:01.221126 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
913 01:20:01.223778 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
914 01:20:01.227404 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
915 01:20:01.230864 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
916 01:20:01.234189 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
917 01:20:01.240839 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
918 01:20:01.244169 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
919 01:20:01.247927 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
920 01:20:01.250550 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
921 01:20:01.254044 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
922 01:20:01.257558 ==
923 01:20:01.260595 Dram Type= 6, Freq= 0, CH_0, rank 0
924 01:20:01.264138 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
925 01:20:01.264727 ==
926 01:20:01.265114 DQS Delay:
927 01:20:01.267212 DQS0 = 0, DQS1 = 0
928 01:20:01.267688 DQM Delay:
929 01:20:01.270551 DQM0 = 82, DQM1 = 75
930 01:20:01.271027 DQ Delay:
931 01:20:01.273913 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
932 01:20:01.277323 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
933 01:20:01.280698 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
934 01:20:01.283849 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
935 01:20:01.284330
936 01:20:01.284709
937 01:20:01.285061 ==
938 01:20:01.287250 Dram Type= 6, Freq= 0, CH_0, rank 0
939 01:20:01.290717 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
940 01:20:01.291194 ==
941 01:20:01.291575
942 01:20:01.291926
943 01:20:01.293741 TX Vref Scan disable
944 01:20:01.297107 == TX Byte 0 ==
945 01:20:01.300517 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
946 01:20:01.304148 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
947 01:20:01.308053 == TX Byte 1 ==
948 01:20:01.310612 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
949 01:20:01.314077 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
950 01:20:01.314561 ==
951 01:20:01.317152 Dram Type= 6, Freq= 0, CH_0, rank 0
952 01:20:01.320818 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
953 01:20:01.323787 ==
954 01:20:01.335191 TX Vref=22, minBit 4, minWin=27, winSum=450
955 01:20:01.339000 TX Vref=24, minBit 0, minWin=28, winSum=453
956 01:20:01.342306 TX Vref=26, minBit 11, minWin=27, winSum=450
957 01:20:01.345328 TX Vref=28, minBit 0, minWin=28, winSum=455
958 01:20:01.348709 TX Vref=30, minBit 0, minWin=28, winSum=457
959 01:20:01.355252 TX Vref=32, minBit 8, minWin=27, winSum=452
960 01:20:01.358359 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
961 01:20:01.358905
962 01:20:01.361677 Final TX Range 1 Vref 30
963 01:20:01.362379
964 01:20:01.362781 ==
965 01:20:01.365092 Dram Type= 6, Freq= 0, CH_0, rank 0
966 01:20:01.368821 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
967 01:20:01.369398 ==
968 01:20:01.372094
969 01:20:01.372663
970 01:20:01.373040 TX Vref Scan disable
971 01:20:01.375398 == TX Byte 0 ==
972 01:20:01.378924 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
973 01:20:01.382285 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
974 01:20:01.385457 == TX Byte 1 ==
975 01:20:01.389223 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
976 01:20:01.392020 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
977 01:20:01.395282
978 01:20:01.395754 [DATLAT]
979 01:20:01.396135 Freq=800, CH0 RK0
980 01:20:01.396493
981 01:20:01.398547 DATLAT Default: 0xa
982 01:20:01.399020 0, 0xFFFF, sum = 0
983 01:20:01.401809 1, 0xFFFF, sum = 0
984 01:20:01.402355 2, 0xFFFF, sum = 0
985 01:20:01.405224 3, 0xFFFF, sum = 0
986 01:20:01.405658 4, 0xFFFF, sum = 0
987 01:20:01.408535 5, 0xFFFF, sum = 0
988 01:20:01.412065 6, 0xFFFF, sum = 0
989 01:20:01.412702 7, 0xFFFF, sum = 0
990 01:20:01.413065 8, 0x0, sum = 1
991 01:20:01.415409 9, 0x0, sum = 2
992 01:20:01.415939 10, 0x0, sum = 3
993 01:20:01.418927 11, 0x0, sum = 4
994 01:20:01.419482 best_step = 9
995 01:20:01.419836
996 01:20:01.420158 ==
997 01:20:01.422219 Dram Type= 6, Freq= 0, CH_0, rank 0
998 01:20:01.429133 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
999 01:20:01.429661 ==
1000 01:20:01.430008 RX Vref Scan: 1
1001 01:20:01.430449
1002 01:20:01.431993 Set Vref Range= 32 -> 127
1003 01:20:01.432484
1004 01:20:01.435172 RX Vref 32 -> 127, step: 1
1005 01:20:01.435604
1006 01:20:01.435944 RX Delay -111 -> 252, step: 8
1007 01:20:01.438931
1008 01:20:01.439455 Set Vref, RX VrefLevel [Byte0]: 32
1009 01:20:01.442276 [Byte1]: 32
1010 01:20:01.446503
1011 01:20:01.447032 Set Vref, RX VrefLevel [Byte0]: 33
1012 01:20:01.449551 [Byte1]: 33
1013 01:20:01.453944
1014 01:20:01.457217 Set Vref, RX VrefLevel [Byte0]: 34
1015 01:20:01.460366 [Byte1]: 34
1016 01:20:01.460870
1017 01:20:01.463564 Set Vref, RX VrefLevel [Byte0]: 35
1018 01:20:01.467215 [Byte1]: 35
1019 01:20:01.467775
1020 01:20:01.470510 Set Vref, RX VrefLevel [Byte0]: 36
1021 01:20:01.474189 [Byte1]: 36
1022 01:20:01.474947
1023 01:20:01.477000 Set Vref, RX VrefLevel [Byte0]: 37
1024 01:20:01.480711 [Byte1]: 37
1025 01:20:01.485087
1026 01:20:01.485656 Set Vref, RX VrefLevel [Byte0]: 38
1027 01:20:01.487717 [Byte1]: 38
1028 01:20:01.492452
1029 01:20:01.493006 Set Vref, RX VrefLevel [Byte0]: 39
1030 01:20:01.495586 [Byte1]: 39
1031 01:20:01.499918
1032 01:20:01.500383 Set Vref, RX VrefLevel [Byte0]: 40
1033 01:20:01.503112 [Byte1]: 40
1034 01:20:01.507549
1035 01:20:01.508102 Set Vref, RX VrefLevel [Byte0]: 41
1036 01:20:01.511058 [Byte1]: 41
1037 01:20:01.514999
1038 01:20:01.515561 Set Vref, RX VrefLevel [Byte0]: 42
1039 01:20:01.518794 [Byte1]: 42
1040 01:20:01.523247
1041 01:20:01.523810 Set Vref, RX VrefLevel [Byte0]: 43
1042 01:20:01.526112 [Byte1]: 43
1043 01:20:01.530505
1044 01:20:01.531057 Set Vref, RX VrefLevel [Byte0]: 44
1045 01:20:01.533671 [Byte1]: 44
1046 01:20:01.538195
1047 01:20:01.538805 Set Vref, RX VrefLevel [Byte0]: 45
1048 01:20:01.541409 [Byte1]: 45
1049 01:20:01.545935
1050 01:20:01.546526 Set Vref, RX VrefLevel [Byte0]: 46
1051 01:20:01.549207 [Byte1]: 46
1052 01:20:01.553416
1053 01:20:01.553978 Set Vref, RX VrefLevel [Byte0]: 47
1054 01:20:01.556753 [Byte1]: 47
1055 01:20:01.560986
1056 01:20:01.561451 Set Vref, RX VrefLevel [Byte0]: 48
1057 01:20:01.564038 [Byte1]: 48
1058 01:20:01.569047
1059 01:20:01.569607 Set Vref, RX VrefLevel [Byte0]: 49
1060 01:20:01.571843 [Byte1]: 49
1061 01:20:01.576126
1062 01:20:01.576673 Set Vref, RX VrefLevel [Byte0]: 50
1063 01:20:01.579360 [Byte1]: 50
1064 01:20:01.583763
1065 01:20:01.584231 Set Vref, RX VrefLevel [Byte0]: 51
1066 01:20:01.587313 [Byte1]: 51
1067 01:20:01.591983
1068 01:20:01.592554 Set Vref, RX VrefLevel [Byte0]: 52
1069 01:20:01.594855 [Byte1]: 52
1070 01:20:01.599232
1071 01:20:01.599700 Set Vref, RX VrefLevel [Byte0]: 53
1072 01:20:01.602921 [Byte1]: 53
1073 01:20:01.606947
1074 01:20:01.607665 Set Vref, RX VrefLevel [Byte0]: 54
1075 01:20:01.610575 [Byte1]: 54
1076 01:20:01.614463
1077 01:20:01.614889 Set Vref, RX VrefLevel [Byte0]: 55
1078 01:20:01.617610 [Byte1]: 55
1079 01:20:01.622268
1080 01:20:01.622834 Set Vref, RX VrefLevel [Byte0]: 56
1081 01:20:01.625589 [Byte1]: 56
1082 01:20:01.630206
1083 01:20:01.630773 Set Vref, RX VrefLevel [Byte0]: 57
1084 01:20:01.633304 [Byte1]: 57
1085 01:20:01.637787
1086 01:20:01.638423 Set Vref, RX VrefLevel [Byte0]: 58
1087 01:20:01.641223 [Byte1]: 58
1088 01:20:01.645547
1089 01:20:01.646171 Set Vref, RX VrefLevel [Byte0]: 59
1090 01:20:01.648878 [Byte1]: 59
1091 01:20:01.653281
1092 01:20:01.653868 Set Vref, RX VrefLevel [Byte0]: 60
1093 01:20:01.656272 [Byte1]: 60
1094 01:20:01.660598
1095 01:20:01.661066 Set Vref, RX VrefLevel [Byte0]: 61
1096 01:20:01.664335 [Byte1]: 61
1097 01:20:01.668129
1098 01:20:01.668704 Set Vref, RX VrefLevel [Byte0]: 62
1099 01:20:01.671587 [Byte1]: 62
1100 01:20:01.675729
1101 01:20:01.676231 Set Vref, RX VrefLevel [Byte0]: 63
1102 01:20:01.678649 [Byte1]: 63
1103 01:20:01.683038
1104 01:20:01.683462 Set Vref, RX VrefLevel [Byte0]: 64
1105 01:20:01.686695 [Byte1]: 64
1106 01:20:01.690921
1107 01:20:01.691390 Set Vref, RX VrefLevel [Byte0]: 65
1108 01:20:01.694448 [Byte1]: 65
1109 01:20:01.698685
1110 01:20:01.699250 Set Vref, RX VrefLevel [Byte0]: 66
1111 01:20:01.701940 [Byte1]: 66
1112 01:20:01.706288
1113 01:20:01.706849 Set Vref, RX VrefLevel [Byte0]: 67
1114 01:20:01.709711 [Byte1]: 67
1115 01:20:01.714178
1116 01:20:01.714737 Set Vref, RX VrefLevel [Byte0]: 68
1117 01:20:01.717082 [Byte1]: 68
1118 01:20:01.721697
1119 01:20:01.722200 Set Vref, RX VrefLevel [Byte0]: 69
1120 01:20:01.725059 [Byte1]: 69
1121 01:20:01.728966
1122 01:20:01.729436 Set Vref, RX VrefLevel [Byte0]: 70
1123 01:20:01.732883 [Byte1]: 70
1124 01:20:01.737122
1125 01:20:01.737695 Set Vref, RX VrefLevel [Byte0]: 71
1126 01:20:01.740071 [Byte1]: 71
1127 01:20:01.744667
1128 01:20:01.745232 Set Vref, RX VrefLevel [Byte0]: 72
1129 01:20:01.747836 [Byte1]: 72
1130 01:20:01.752075
1131 01:20:01.752644 Set Vref, RX VrefLevel [Byte0]: 73
1132 01:20:01.755349 [Byte1]: 73
1133 01:20:01.759836
1134 01:20:01.760429 Final RX Vref Byte 0 = 54 to rank0
1135 01:20:01.762975 Final RX Vref Byte 1 = 54 to rank0
1136 01:20:01.766318 Final RX Vref Byte 0 = 54 to rank1
1137 01:20:01.769983 Final RX Vref Byte 1 = 54 to rank1==
1138 01:20:01.773221 Dram Type= 6, Freq= 0, CH_0, rank 0
1139 01:20:01.776656 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1140 01:20:01.779849 ==
1141 01:20:01.780324 DQS Delay:
1142 01:20:01.780700 DQS0 = 0, DQS1 = 0
1143 01:20:01.783278 DQM Delay:
1144 01:20:01.783841 DQM0 = 83, DQM1 = 73
1145 01:20:01.786547 DQ Delay:
1146 01:20:01.790278 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1147 01:20:01.790854 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1148 01:20:01.793348 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1149 01:20:01.799486 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1150 01:20:01.800039
1151 01:20:01.800413
1152 01:20:01.806685 [DQSOSCAuto] RK0, (LSB)MR18= 0x3737, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1153 01:20:01.809837 CH0 RK0: MR19=606, MR18=3737
1154 01:20:01.816441 CH0_RK0: MR19=0x606, MR18=0x3737, DQSOSC=395, MR23=63, INC=94, DEC=63
1155 01:20:01.816993
1156 01:20:01.819826 ----->DramcWriteLeveling(PI) begin...
1157 01:20:01.820446 ==
1158 01:20:01.822819 Dram Type= 6, Freq= 0, CH_0, rank 1
1159 01:20:01.826574 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1160 01:20:01.827144 ==
1161 01:20:01.829738 Write leveling (Byte 0): 28 => 28
1162 01:20:01.832997 Write leveling (Byte 1): 26 => 26
1163 01:20:01.836486 DramcWriteLeveling(PI) end<-----
1164 01:20:01.837047
1165 01:20:01.837420 ==
1166 01:20:01.839713 Dram Type= 6, Freq= 0, CH_0, rank 1
1167 01:20:01.842860 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1168 01:20:01.843332 ==
1169 01:20:01.846209 [Gating] SW mode calibration
1170 01:20:01.853299 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1171 01:20:01.859989 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1172 01:20:01.863057 0 6 0 | B1->B0 | 3434 3030 | 0 0 | (0 1) (0 0)
1173 01:20:01.866335 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 01:20:01.873362 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 01:20:01.876160 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 01:20:01.879698 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 01:20:01.886182 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 01:20:01.889948 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 01:20:01.893262 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 01:20:01.900015 0 7 0 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
1181 01:20:01.903107 0 7 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1182 01:20:01.906413 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1183 01:20:01.913278 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1184 01:20:01.916340 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 01:20:01.920081 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 01:20:01.926141 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 01:20:01.930113 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1188 01:20:01.933039 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1189 01:20:01.936568 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1190 01:20:01.943161 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1191 01:20:01.946471 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 01:20:01.949468 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 01:20:01.956387 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 01:20:01.959513 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 01:20:01.962579 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 01:20:01.969727 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 01:20:01.972812 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 01:20:01.976206 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 01:20:01.982710 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 01:20:01.986071 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 01:20:01.989500 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 01:20:01.996331 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 01:20:01.999848 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 01:20:02.002765 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1205 01:20:02.009899 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1206 01:20:02.010525 Total UI for P1: 0, mck2ui 16
1207 01:20:02.016251 best dqsien dly found for B1: ( 0, 10, 0)
1208 01:20:02.019549 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 01:20:02.022808 Total UI for P1: 0, mck2ui 16
1210 01:20:02.026099 best dqsien dly found for B0: ( 0, 10, 2)
1211 01:20:02.029715 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1212 01:20:02.033113 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1213 01:20:02.033680
1214 01:20:02.036524 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1215 01:20:02.039362 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1216 01:20:02.042947 [Gating] SW calibration Done
1217 01:20:02.043574 ==
1218 01:20:02.046004 Dram Type= 6, Freq= 0, CH_0, rank 1
1219 01:20:02.049527 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1220 01:20:02.050143 ==
1221 01:20:02.093949 RX Vref Scan: 0
1222 01:20:02.094581
1223 01:20:02.094961 RX Vref 0 -> 0, step: 1
1224 01:20:02.095312
1225 01:20:02.095646 RX Delay -130 -> 252, step: 16
1226 01:20:02.095977 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1227 01:20:02.096300 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1228 01:20:02.096987 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1229 01:20:02.097340 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1230 01:20:02.097662 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1231 01:20:02.097978 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1232 01:20:02.098346 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1233 01:20:02.098711 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1234 01:20:02.099040 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1235 01:20:02.122861 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1236 01:20:02.123808 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1237 01:20:02.124236 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1238 01:20:02.124599 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1239 01:20:02.125004 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1240 01:20:02.125345 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1241 01:20:02.125705 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1242 01:20:02.126097 ==
1243 01:20:02.127014 Dram Type= 6, Freq= 0, CH_0, rank 1
1244 01:20:02.130196 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1245 01:20:02.130991 ==
1246 01:20:02.131622 DQS Delay:
1247 01:20:02.133489 DQS0 = 0, DQS1 = 0
1248 01:20:02.134075 DQM Delay:
1249 01:20:02.136881 DQM0 = 83, DQM1 = 75
1250 01:20:02.137606 DQ Delay:
1251 01:20:02.140169 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1252 01:20:02.143406 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1253 01:20:02.146720 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1254 01:20:02.150680 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1255 01:20:02.151247
1256 01:20:02.151621
1257 01:20:02.151972 ==
1258 01:20:02.153758 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 01:20:02.156889 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1260 01:20:02.157455 ==
1261 01:20:02.157835
1262 01:20:02.158249
1263 01:20:02.160763 TX Vref Scan disable
1264 01:20:02.163421 == TX Byte 0 ==
1265 01:20:02.166755 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1266 01:20:02.169986 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1267 01:20:02.173380 == TX Byte 1 ==
1268 01:20:02.176689 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1269 01:20:02.180046 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1270 01:20:02.180519 ==
1271 01:20:02.183351 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 01:20:02.187228 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1273 01:20:02.187793 ==
1274 01:20:02.201421 TX Vref=22, minBit 0, minWin=27, winSum=438
1275 01:20:02.204655 TX Vref=24, minBit 0, minWin=27, winSum=445
1276 01:20:02.207632 TX Vref=26, minBit 2, minWin=28, winSum=454
1277 01:20:02.211278 TX Vref=28, minBit 4, minWin=28, winSum=456
1278 01:20:02.214983 TX Vref=30, minBit 2, minWin=28, winSum=456
1279 01:20:02.218259 TX Vref=32, minBit 0, minWin=28, winSum=456
1280 01:20:02.225063 [TxChooseVref] Worse bit 4, Min win 28, Win sum 456, Final Vref 28
1281 01:20:02.225628
1282 01:20:02.228789 Final TX Range 1 Vref 28
1283 01:20:02.229348
1284 01:20:02.229722 ==
1285 01:20:02.232442 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 01:20:02.235931 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1287 01:20:02.236406 ==
1288 01:20:02.236782
1289 01:20:02.237311
1290 01:20:02.238948 TX Vref Scan disable
1291 01:20:02.242630 == TX Byte 0 ==
1292 01:20:02.246350 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1293 01:20:02.249733 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1294 01:20:02.250254 == TX Byte 1 ==
1295 01:20:02.256725 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1296 01:20:02.259811 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1297 01:20:02.260376
1298 01:20:02.260755 [DATLAT]
1299 01:20:02.262850 Freq=800, CH0 RK1
1300 01:20:02.263341
1301 01:20:02.263717 DATLAT Default: 0x9
1302 01:20:02.266131 0, 0xFFFF, sum = 0
1303 01:20:02.266612 1, 0xFFFF, sum = 0
1304 01:20:02.269508 2, 0xFFFF, sum = 0
1305 01:20:02.269983 3, 0xFFFF, sum = 0
1306 01:20:02.272761 4, 0xFFFF, sum = 0
1307 01:20:02.273236 5, 0xFFFF, sum = 0
1308 01:20:02.276422 6, 0xFFFF, sum = 0
1309 01:20:02.277000 7, 0xFFFF, sum = 0
1310 01:20:02.279776 8, 0x0, sum = 1
1311 01:20:02.280372 9, 0x0, sum = 2
1312 01:20:02.282835 10, 0x0, sum = 3
1313 01:20:02.283328 11, 0x0, sum = 4
1314 01:20:02.286324 best_step = 9
1315 01:20:02.286791
1316 01:20:02.287164 ==
1317 01:20:02.289522 Dram Type= 6, Freq= 0, CH_0, rank 1
1318 01:20:02.292805 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1319 01:20:02.293276 ==
1320 01:20:02.296227 RX Vref Scan: 0
1321 01:20:02.296795
1322 01:20:02.297170 RX Vref 0 -> 0, step: 1
1323 01:20:02.297522
1324 01:20:02.299364 RX Delay -95 -> 252, step: 8
1325 01:20:02.306307 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1326 01:20:02.309982 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1327 01:20:02.312837 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1328 01:20:02.316173 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1329 01:20:02.319709 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1330 01:20:02.325944 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1331 01:20:02.329401 iDelay=217, Bit 6, Center 96 (-23 ~ 216) 240
1332 01:20:02.332928 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1333 01:20:02.335935 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1334 01:20:02.339069 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1335 01:20:02.346178 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1336 01:20:02.349861 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1337 01:20:02.352752 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1338 01:20:02.356111 iDelay=217, Bit 13, Center 76 (-39 ~ 192) 232
1339 01:20:02.359444 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1340 01:20:02.365914 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1341 01:20:02.366438 ==
1342 01:20:02.369325 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 01:20:02.372912 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1344 01:20:02.373531 ==
1345 01:20:02.373920 DQS Delay:
1346 01:20:02.375958 DQS0 = 0, DQS1 = 0
1347 01:20:02.376429 DQM Delay:
1348 01:20:02.379503 DQM0 = 86, DQM1 = 73
1349 01:20:02.380093 DQ Delay:
1350 01:20:02.382664 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =80
1351 01:20:02.386655 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1352 01:20:02.389873 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1353 01:20:02.392932 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1354 01:20:02.393403
1355 01:20:02.393776
1356 01:20:02.399803 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f3f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1357 01:20:02.402764 CH0 RK1: MR19=606, MR18=3F3F
1358 01:20:02.409152 CH0_RK1: MR19=0x606, MR18=0x3F3F, DQSOSC=393, MR23=63, INC=95, DEC=63
1359 01:20:02.413002 [RxdqsGatingPostProcess] freq 800
1360 01:20:02.419084 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1361 01:20:02.422306 Pre-setting of DQS Precalculation
1362 01:20:02.425523 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1363 01:20:02.425982 ==
1364 01:20:02.428748 Dram Type= 6, Freq= 0, CH_1, rank 0
1365 01:20:02.432473 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1366 01:20:02.432932 ==
1367 01:20:02.438949 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1368 01:20:02.445566 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1369 01:20:02.454011 [CA 0] Center 37 (6~68) winsize 63
1370 01:20:02.457075 [CA 1] Center 37 (6~68) winsize 63
1371 01:20:02.460751 [CA 2] Center 34 (4~65) winsize 62
1372 01:20:02.463551 [CA 3] Center 34 (4~65) winsize 62
1373 01:20:02.466959 [CA 4] Center 33 (2~64) winsize 63
1374 01:20:02.470467 [CA 5] Center 33 (3~64) winsize 62
1375 01:20:02.470788
1376 01:20:02.474122 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1377 01:20:02.474637
1378 01:20:02.477094 [CATrainingPosCal] consider 1 rank data
1379 01:20:02.480297 u2DelayCellTimex100 = 270/100 ps
1380 01:20:02.484044 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1381 01:20:02.486834 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1382 01:20:02.493897 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1383 01:20:02.497022 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1384 01:20:02.500467 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
1385 01:20:02.503670 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1386 01:20:02.504150
1387 01:20:02.506842 CA PerBit enable=1, Macro0, CA PI delay=33
1388 01:20:02.507304
1389 01:20:02.510470 [CBTSetCACLKResult] CA Dly = 33
1390 01:20:02.511026 CS Dly: 4 (0~35)
1391 01:20:02.513974 ==
1392 01:20:02.514596 Dram Type= 6, Freq= 0, CH_1, rank 1
1393 01:20:02.520503 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1394 01:20:02.521062 ==
1395 01:20:02.523626 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1396 01:20:02.530109 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1397 01:20:02.539773 [CA 0] Center 37 (6~68) winsize 63
1398 01:20:02.542718 [CA 1] Center 37 (6~68) winsize 63
1399 01:20:02.546914 [CA 2] Center 34 (4~65) winsize 62
1400 01:20:02.549644 [CA 3] Center 34 (4~65) winsize 62
1401 01:20:02.553234 [CA 4] Center 33 (3~64) winsize 62
1402 01:20:02.556598 [CA 5] Center 33 (3~64) winsize 62
1403 01:20:02.557157
1404 01:20:02.559550 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1405 01:20:02.560011
1406 01:20:02.563114 [CATrainingPosCal] consider 2 rank data
1407 01:20:02.566425 u2DelayCellTimex100 = 270/100 ps
1408 01:20:02.569379 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1409 01:20:02.573025 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1410 01:20:02.579960 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1411 01:20:02.582583 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1412 01:20:02.586602 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1413 01:20:02.589728 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1414 01:20:02.590334
1415 01:20:02.593171 CA PerBit enable=1, Macro0, CA PI delay=33
1416 01:20:02.593731
1417 01:20:02.596281 [CBTSetCACLKResult] CA Dly = 33
1418 01:20:02.596875 CS Dly: 4 (0~36)
1419 01:20:02.597252
1420 01:20:02.599717 ----->DramcWriteLeveling(PI) begin...
1421 01:20:02.602990 ==
1422 01:20:02.606301 Dram Type= 6, Freq= 0, CH_1, rank 0
1423 01:20:02.609372 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1424 01:20:02.609838 ==
1425 01:20:02.613159 Write leveling (Byte 0): 25 => 25
1426 01:20:02.616226 Write leveling (Byte 1): 25 => 25
1427 01:20:02.619759 DramcWriteLeveling(PI) end<-----
1428 01:20:02.620319
1429 01:20:02.620684 ==
1430 01:20:02.622749 Dram Type= 6, Freq= 0, CH_1, rank 0
1431 01:20:02.626077 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1432 01:20:02.626650 ==
1433 01:20:02.629840 [Gating] SW mode calibration
1434 01:20:02.635900 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1435 01:20:02.639460 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1436 01:20:02.646299 0 6 0 | B1->B0 | 3030 2424 | 0 0 | (0 1) (0 0)
1437 01:20:02.649330 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1438 01:20:02.652567 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1439 01:20:02.659206 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1440 01:20:02.662684 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 01:20:02.665970 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 01:20:02.672640 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 01:20:02.676194 0 6 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1444 01:20:02.679674 0 7 0 | B1->B0 | 2a2a 3a3a | 0 0 | (0 0) (0 0)
1445 01:20:02.686182 0 7 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1446 01:20:02.689164 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1447 01:20:02.692656 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1448 01:20:02.699261 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1449 01:20:02.702961 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1450 01:20:02.705882 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1451 01:20:02.713145 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1452 01:20:02.716408 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1453 01:20:02.719447 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1454 01:20:02.726130 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1455 01:20:02.729701 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1456 01:20:02.732717 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1457 01:20:02.736354 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1458 01:20:02.742883 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1459 01:20:02.746111 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 01:20:02.749047 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 01:20:02.755860 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 01:20:02.759269 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 01:20:02.762254 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1464 01:20:02.768937 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1465 01:20:02.772547 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1466 01:20:02.775540 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1467 01:20:02.782761 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1468 01:20:02.785986 Total UI for P1: 0, mck2ui 16
1469 01:20:02.789044 best dqsien dly found for B0: ( 0, 9, 26)
1470 01:20:02.792724 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1471 01:20:02.795777 Total UI for P1: 0, mck2ui 16
1472 01:20:02.798959 best dqsien dly found for B1: ( 0, 9, 28)
1473 01:20:02.802218 best DQS0 dly(MCK, UI, PI) = (0, 9, 26)
1474 01:20:02.805700 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
1475 01:20:02.806308
1476 01:20:02.809043 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26)
1477 01:20:02.812276 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
1478 01:20:02.815587 [Gating] SW calibration Done
1479 01:20:02.816149 ==
1480 01:20:02.818965 Dram Type= 6, Freq= 0, CH_1, rank 0
1481 01:20:02.825511 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1482 01:20:02.826121 ==
1483 01:20:02.826504 RX Vref Scan: 0
1484 01:20:02.826907
1485 01:20:02.829005 RX Vref 0 -> 0, step: 1
1486 01:20:02.829466
1487 01:20:02.832361 RX Delay -130 -> 252, step: 16
1488 01:20:02.835553 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1489 01:20:02.838703 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1490 01:20:02.842319 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1491 01:20:02.845397 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1492 01:20:02.852256 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1493 01:20:02.855341 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1494 01:20:02.858945 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1495 01:20:02.862124 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1496 01:20:02.865123 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1497 01:20:02.872182 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1498 01:20:02.875206 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1499 01:20:02.878976 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1500 01:20:02.882397 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1501 01:20:02.885977 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1502 01:20:02.889635 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1503 01:20:02.897364 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1504 01:20:02.897936 ==
1505 01:20:02.900876 Dram Type= 6, Freq= 0, CH_1, rank 0
1506 01:20:02.904444 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1507 01:20:02.904978 ==
1508 01:20:02.905472 DQS Delay:
1509 01:20:02.905832 DQS0 = 0, DQS1 = 0
1510 01:20:02.908629 DQM Delay:
1511 01:20:02.909279 DQM0 = 80, DQM1 = 72
1512 01:20:02.909902 DQ Delay:
1513 01:20:02.912463 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1514 01:20:02.915948 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1515 01:20:02.919301 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1516 01:20:02.922468 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =85
1517 01:20:02.922933
1518 01:20:02.923300
1519 01:20:02.923640 ==
1520 01:20:02.925893 Dram Type= 6, Freq= 0, CH_1, rank 0
1521 01:20:02.929411 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1522 01:20:02.932919 ==
1523 01:20:02.933479
1524 01:20:02.933845
1525 01:20:02.934229 TX Vref Scan disable
1526 01:20:02.936141 == TX Byte 0 ==
1527 01:20:02.939595 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1528 01:20:02.942602 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1529 01:20:02.946131 == TX Byte 1 ==
1530 01:20:02.949192 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1531 01:20:02.952562 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1532 01:20:02.955980 ==
1533 01:20:02.956544 Dram Type= 6, Freq= 0, CH_1, rank 0
1534 01:20:02.962193 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1535 01:20:02.962661 ==
1536 01:20:02.974493 TX Vref=22, minBit 3, minWin=27, winSum=449
1537 01:20:02.977577 TX Vref=24, minBit 3, minWin=27, winSum=449
1538 01:20:02.980933 TX Vref=26, minBit 0, minWin=28, winSum=455
1539 01:20:02.984242 TX Vref=28, minBit 0, minWin=28, winSum=459
1540 01:20:02.987445 TX Vref=30, minBit 0, minWin=28, winSum=459
1541 01:20:02.994127 TX Vref=32, minBit 0, minWin=28, winSum=457
1542 01:20:02.997791 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 28
1543 01:20:02.998407
1544 01:20:03.001371 Final TX Range 1 Vref 28
1545 01:20:03.001951
1546 01:20:03.002380 ==
1547 01:20:03.004125 Dram Type= 6, Freq= 0, CH_1, rank 0
1548 01:20:03.007505 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1549 01:20:03.011001 ==
1550 01:20:03.011564
1551 01:20:03.011930
1552 01:20:03.012270 TX Vref Scan disable
1553 01:20:03.014821 == TX Byte 0 ==
1554 01:20:03.017620 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1555 01:20:03.024698 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1556 01:20:03.025264 == TX Byte 1 ==
1557 01:20:03.027345 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1558 01:20:03.034383 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1559 01:20:03.034963
1560 01:20:03.035332 [DATLAT]
1561 01:20:03.035672 Freq=800, CH1 RK0
1562 01:20:03.036017
1563 01:20:03.037877 DATLAT Default: 0xa
1564 01:20:03.038467 0, 0xFFFF, sum = 0
1565 01:20:03.040925 1, 0xFFFF, sum = 0
1566 01:20:03.041386 2, 0xFFFF, sum = 0
1567 01:20:03.044359 3, 0xFFFF, sum = 0
1568 01:20:03.047799 4, 0xFFFF, sum = 0
1569 01:20:03.048371 5, 0xFFFF, sum = 0
1570 01:20:03.050997 6, 0xFFFF, sum = 0
1571 01:20:03.051461 7, 0xFFFF, sum = 0
1572 01:20:03.054577 8, 0x0, sum = 1
1573 01:20:03.055149 9, 0x0, sum = 2
1574 01:20:03.055525 10, 0x0, sum = 3
1575 01:20:03.057709 11, 0x0, sum = 4
1576 01:20:03.058216 best_step = 9
1577 01:20:03.058588
1578 01:20:03.058928 ==
1579 01:20:03.060620 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 01:20:03.067377 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1581 01:20:03.067847 ==
1582 01:20:03.068219 RX Vref Scan: 1
1583 01:20:03.068565
1584 01:20:03.070745 Set Vref Range= 32 -> 127
1585 01:20:03.071205
1586 01:20:03.073948 RX Vref 32 -> 127, step: 1
1587 01:20:03.074446
1588 01:20:03.077574 RX Delay -111 -> 252, step: 8
1589 01:20:03.078078
1590 01:20:03.081203 Set Vref, RX VrefLevel [Byte0]: 32
1591 01:20:03.084002 [Byte1]: 32
1592 01:20:03.084463
1593 01:20:03.087588 Set Vref, RX VrefLevel [Byte0]: 33
1594 01:20:03.090892 [Byte1]: 33
1595 01:20:03.091352
1596 01:20:03.094354 Set Vref, RX VrefLevel [Byte0]: 34
1597 01:20:03.097664 [Byte1]: 34
1598 01:20:03.100911
1599 01:20:03.101471 Set Vref, RX VrefLevel [Byte0]: 35
1600 01:20:03.103998 [Byte1]: 35
1601 01:20:03.108440
1602 01:20:03.109015 Set Vref, RX VrefLevel [Byte0]: 36
1603 01:20:03.111478 [Byte1]: 36
1604 01:20:03.116273
1605 01:20:03.116833 Set Vref, RX VrefLevel [Byte0]: 37
1606 01:20:03.119474 [Byte1]: 37
1607 01:20:03.123561
1608 01:20:03.124122 Set Vref, RX VrefLevel [Byte0]: 38
1609 01:20:03.126755 [Byte1]: 38
1610 01:20:03.131373
1611 01:20:03.131928 Set Vref, RX VrefLevel [Byte0]: 39
1612 01:20:03.134560 [Byte1]: 39
1613 01:20:03.139143
1614 01:20:03.139705 Set Vref, RX VrefLevel [Byte0]: 40
1615 01:20:03.142270 [Byte1]: 40
1616 01:20:03.146925
1617 01:20:03.147497 Set Vref, RX VrefLevel [Byte0]: 41
1618 01:20:03.150268 [Byte1]: 41
1619 01:20:03.154406
1620 01:20:03.154964 Set Vref, RX VrefLevel [Byte0]: 42
1621 01:20:03.157612 [Byte1]: 42
1622 01:20:03.161946
1623 01:20:03.162552 Set Vref, RX VrefLevel [Byte0]: 43
1624 01:20:03.164921 [Byte1]: 43
1625 01:20:03.169557
1626 01:20:03.170068 Set Vref, RX VrefLevel [Byte0]: 44
1627 01:20:03.173023 [Byte1]: 44
1628 01:20:03.177097
1629 01:20:03.177661 Set Vref, RX VrefLevel [Byte0]: 45
1630 01:20:03.180732 [Byte1]: 45
1631 01:20:03.184668
1632 01:20:03.185228 Set Vref, RX VrefLevel [Byte0]: 46
1633 01:20:03.187865 [Byte1]: 46
1634 01:20:03.192666
1635 01:20:03.193232 Set Vref, RX VrefLevel [Byte0]: 47
1636 01:20:03.195668 [Byte1]: 47
1637 01:20:03.200168
1638 01:20:03.200742 Set Vref, RX VrefLevel [Byte0]: 48
1639 01:20:03.203212 [Byte1]: 48
1640 01:20:03.207767
1641 01:20:03.208326 Set Vref, RX VrefLevel [Byte0]: 49
1642 01:20:03.211254 [Byte1]: 49
1643 01:20:03.215196
1644 01:20:03.215653 Set Vref, RX VrefLevel [Byte0]: 50
1645 01:20:03.218599 [Byte1]: 50
1646 01:20:03.222939
1647 01:20:03.223396 Set Vref, RX VrefLevel [Byte0]: 51
1648 01:20:03.226145 [Byte1]: 51
1649 01:20:03.230582
1650 01:20:03.231044 Set Vref, RX VrefLevel [Byte0]: 52
1651 01:20:03.234131 [Byte1]: 52
1652 01:20:03.238338
1653 01:20:03.238801 Set Vref, RX VrefLevel [Byte0]: 53
1654 01:20:03.241529 [Byte1]: 53
1655 01:20:03.245866
1656 01:20:03.246362 Set Vref, RX VrefLevel [Byte0]: 54
1657 01:20:03.249767 [Byte1]: 54
1658 01:20:03.253499
1659 01:20:03.253962 Set Vref, RX VrefLevel [Byte0]: 55
1660 01:20:03.257012 [Byte1]: 55
1661 01:20:03.261155
1662 01:20:03.261617 Set Vref, RX VrefLevel [Byte0]: 56
1663 01:20:03.264294 [Byte1]: 56
1664 01:20:03.269319
1665 01:20:03.269891 Set Vref, RX VrefLevel [Byte0]: 57
1666 01:20:03.272044 [Byte1]: 57
1667 01:20:03.276624
1668 01:20:03.277264 Set Vref, RX VrefLevel [Byte0]: 58
1669 01:20:03.279693 [Byte1]: 58
1670 01:20:03.284122
1671 01:20:03.284679 Set Vref, RX VrefLevel [Byte0]: 59
1672 01:20:03.287562 [Byte1]: 59
1673 01:20:03.291867
1674 01:20:03.292429 Set Vref, RX VrefLevel [Byte0]: 60
1675 01:20:03.295226 [Byte1]: 60
1676 01:20:03.299204
1677 01:20:03.299704 Set Vref, RX VrefLevel [Byte0]: 61
1678 01:20:03.302642 [Byte1]: 61
1679 01:20:03.307032
1680 01:20:03.307649 Set Vref, RX VrefLevel [Byte0]: 62
1681 01:20:03.310390 [Byte1]: 62
1682 01:20:03.314596
1683 01:20:03.315058 Set Vref, RX VrefLevel [Byte0]: 63
1684 01:20:03.318389 [Byte1]: 63
1685 01:20:03.322638
1686 01:20:03.323129 Set Vref, RX VrefLevel [Byte0]: 64
1687 01:20:03.325950 [Byte1]: 64
1688 01:20:03.330085
1689 01:20:03.330553 Set Vref, RX VrefLevel [Byte0]: 65
1690 01:20:03.333479 [Byte1]: 65
1691 01:20:03.337883
1692 01:20:03.338500 Set Vref, RX VrefLevel [Byte0]: 66
1693 01:20:03.341074 [Byte1]: 66
1694 01:20:03.345269
1695 01:20:03.345733 Set Vref, RX VrefLevel [Byte0]: 67
1696 01:20:03.349052 [Byte1]: 67
1697 01:20:03.353037
1698 01:20:03.353590 Set Vref, RX VrefLevel [Byte0]: 68
1699 01:20:03.356484 [Byte1]: 68
1700 01:20:03.361203
1701 01:20:03.361775 Set Vref, RX VrefLevel [Byte0]: 69
1702 01:20:03.363933 [Byte1]: 69
1703 01:20:03.368331
1704 01:20:03.368894 Set Vref, RX VrefLevel [Byte0]: 70
1705 01:20:03.371529 [Byte1]: 70
1706 01:20:03.376041
1707 01:20:03.376597 Set Vref, RX VrefLevel [Byte0]: 71
1708 01:20:03.379023 [Byte1]: 71
1709 01:20:03.384179
1710 01:20:03.384736 Set Vref, RX VrefLevel [Byte0]: 72
1711 01:20:03.386743 [Byte1]: 72
1712 01:20:03.391532
1713 01:20:03.392143 Set Vref, RX VrefLevel [Byte0]: 73
1714 01:20:03.394686 [Byte1]: 73
1715 01:20:03.399365
1716 01:20:03.399924 Set Vref, RX VrefLevel [Byte0]: 74
1717 01:20:03.402091 [Byte1]: 74
1718 01:20:03.406688
1719 01:20:03.407247 Final RX Vref Byte 0 = 58 to rank0
1720 01:20:03.409615 Final RX Vref Byte 1 = 56 to rank0
1721 01:20:03.413303 Final RX Vref Byte 0 = 58 to rank1
1722 01:20:03.416463 Final RX Vref Byte 1 = 56 to rank1==
1723 01:20:03.420187 Dram Type= 6, Freq= 0, CH_1, rank 0
1724 01:20:03.426495 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1725 01:20:03.427063 ==
1726 01:20:03.427439 DQS Delay:
1727 01:20:03.429820 DQS0 = 0, DQS1 = 0
1728 01:20:03.430428 DQM Delay:
1729 01:20:03.430805 DQM0 = 81, DQM1 = 74
1730 01:20:03.433108 DQ Delay:
1731 01:20:03.436362 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =80
1732 01:20:03.439506 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1733 01:20:03.442869 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
1734 01:20:03.446496 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1735 01:20:03.446961
1736 01:20:03.447329
1737 01:20:03.453176 [DQSOSCAuto] RK0, (LSB)MR18= 0x5050, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1738 01:20:03.456402 CH1 RK0: MR19=606, MR18=5050
1739 01:20:03.463629 CH1_RK0: MR19=0x606, MR18=0x5050, DQSOSC=389, MR23=63, INC=97, DEC=65
1740 01:20:03.464181
1741 01:20:03.466800 ----->DramcWriteLeveling(PI) begin...
1742 01:20:03.467461 ==
1743 01:20:03.470162 Dram Type= 6, Freq= 0, CH_1, rank 1
1744 01:20:03.473628 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1745 01:20:03.474141 ==
1746 01:20:03.476883 Write leveling (Byte 0): 25 => 25
1747 01:20:03.480436 Write leveling (Byte 1): 25 => 25
1748 01:20:03.483500 DramcWriteLeveling(PI) end<-----
1749 01:20:03.483964
1750 01:20:03.484331 ==
1751 01:20:03.487201 Dram Type= 6, Freq= 0, CH_1, rank 1
1752 01:20:03.490815 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1753 01:20:03.491281 ==
1754 01:20:03.493375 [Gating] SW mode calibration
1755 01:20:03.500587 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1756 01:20:03.506843 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1757 01:20:03.510087 0 6 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
1758 01:20:03.513414 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1759 01:20:03.520195 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1760 01:20:03.523503 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1761 01:20:03.526719 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1762 01:20:03.533463 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1763 01:20:03.536991 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1764 01:20:03.540143 0 6 28 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1765 01:20:03.546939 0 7 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
1766 01:20:03.549776 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1767 01:20:03.553559 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1768 01:20:03.556841 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1769 01:20:03.563466 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1770 01:20:03.566739 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1771 01:20:03.569884 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1772 01:20:03.576583 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1773 01:20:03.580146 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1774 01:20:03.583382 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1775 01:20:03.589949 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1776 01:20:03.592998 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1777 01:20:03.596650 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1778 01:20:03.603334 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1779 01:20:03.606225 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1780 01:20:03.609718 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1781 01:20:03.616623 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1782 01:20:03.619799 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1783 01:20:03.623225 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1784 01:20:03.629563 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1785 01:20:03.632848 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1786 01:20:03.636534 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1787 01:20:03.643177 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1788 01:20:03.646548 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1789 01:20:03.649723 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1790 01:20:03.653397 Total UI for P1: 0, mck2ui 16
1791 01:20:03.656401 best dqsien dly found for B0: ( 0, 9, 28)
1792 01:20:03.660212 Total UI for P1: 0, mck2ui 16
1793 01:20:03.663068 best dqsien dly found for B1: ( 0, 9, 28)
1794 01:20:03.666240 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1795 01:20:03.669592 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
1796 01:20:03.670078
1797 01:20:03.673249 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1798 01:20:03.679802 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
1799 01:20:03.680367 [Gating] SW calibration Done
1800 01:20:03.680740 ==
1801 01:20:03.683265 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 01:20:03.689703 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1803 01:20:03.690316 ==
1804 01:20:03.690694 RX Vref Scan: 0
1805 01:20:03.691044
1806 01:20:03.692938 RX Vref 0 -> 0, step: 1
1807 01:20:03.693403
1808 01:20:03.696236 RX Delay -130 -> 252, step: 16
1809 01:20:03.699625 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1810 01:20:03.702942 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1811 01:20:03.706225 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1812 01:20:03.713416 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1813 01:20:03.716812 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1814 01:20:03.719695 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1815 01:20:03.723243 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1816 01:20:03.726586 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1817 01:20:03.733114 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1818 01:20:03.736532 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1819 01:20:03.739393 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1820 01:20:03.743467 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1821 01:20:03.745986 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1822 01:20:03.752728 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1823 01:20:03.756012 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1824 01:20:03.759888 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1825 01:20:03.760521 ==
1826 01:20:03.762871 Dram Type= 6, Freq= 0, CH_1, rank 1
1827 01:20:03.766192 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1828 01:20:03.766667 ==
1829 01:20:03.769599 DQS Delay:
1830 01:20:03.770246 DQS0 = 0, DQS1 = 0
1831 01:20:03.772687 DQM Delay:
1832 01:20:03.773195 DQM0 = 85, DQM1 = 73
1833 01:20:03.776029 DQ Delay:
1834 01:20:03.776494 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1835 01:20:03.779485 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1836 01:20:03.782610 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =69
1837 01:20:03.786102 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1838 01:20:03.786729
1839 01:20:03.789154
1840 01:20:03.789613 ==
1841 01:20:03.792749 Dram Type= 6, Freq= 0, CH_1, rank 1
1842 01:20:03.796077 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1843 01:20:03.796549 ==
1844 01:20:03.796921
1845 01:20:03.797266
1846 01:20:03.799515 TX Vref Scan disable
1847 01:20:03.800073 == TX Byte 0 ==
1848 01:20:03.805714 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1849 01:20:03.809557 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1850 01:20:03.810155 == TX Byte 1 ==
1851 01:20:03.816088 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1852 01:20:03.819270 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1853 01:20:03.819833 ==
1854 01:20:03.822480 Dram Type= 6, Freq= 0, CH_1, rank 1
1855 01:20:03.825866 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1856 01:20:03.826472 ==
1857 01:20:03.839400 TX Vref=22, minBit 0, minWin=27, winSum=449
1858 01:20:03.842254 TX Vref=24, minBit 8, minWin=27, winSum=451
1859 01:20:03.846299 TX Vref=26, minBit 0, minWin=28, winSum=455
1860 01:20:03.849126 TX Vref=28, minBit 9, minWin=27, winSum=454
1861 01:20:03.852555 TX Vref=30, minBit 0, minWin=28, winSum=458
1862 01:20:03.855961 TX Vref=32, minBit 0, minWin=28, winSum=454
1863 01:20:03.862915 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 30
1864 01:20:03.863482
1865 01:20:03.865544 Final TX Range 1 Vref 30
1866 01:20:03.866010
1867 01:20:03.866461 ==
1868 01:20:03.868993 Dram Type= 6, Freq= 0, CH_1, rank 1
1869 01:20:03.872283 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1870 01:20:03.872796 ==
1871 01:20:03.873420
1872 01:20:03.875599
1873 01:20:03.876061 TX Vref Scan disable
1874 01:20:03.879048 == TX Byte 0 ==
1875 01:20:03.882427 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1876 01:20:03.885846 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1877 01:20:03.889219 == TX Byte 1 ==
1878 01:20:03.892641 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1879 01:20:03.895680 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1880 01:20:03.899189
1881 01:20:03.899654 [DATLAT]
1882 01:20:03.900024 Freq=800, CH1 RK1
1883 01:20:03.900372
1884 01:20:03.902675 DATLAT Default: 0x9
1885 01:20:03.903236 0, 0xFFFF, sum = 0
1886 01:20:03.905862 1, 0xFFFF, sum = 0
1887 01:20:03.906356 2, 0xFFFF, sum = 0
1888 01:20:03.909253 3, 0xFFFF, sum = 0
1889 01:20:03.909990 4, 0xFFFF, sum = 0
1890 01:20:03.912828 5, 0xFFFF, sum = 0
1891 01:20:03.915905 6, 0xFFFF, sum = 0
1892 01:20:03.916468 7, 0xFFFF, sum = 0
1893 01:20:03.916844 8, 0x0, sum = 1
1894 01:20:03.919247 9, 0x0, sum = 2
1895 01:20:03.919813 10, 0x0, sum = 3
1896 01:20:03.922458 11, 0x0, sum = 4
1897 01:20:03.923023 best_step = 9
1898 01:20:03.923392
1899 01:20:03.923766 ==
1900 01:20:03.926014 Dram Type= 6, Freq= 0, CH_1, rank 1
1901 01:20:03.932283 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1902 01:20:03.932765 ==
1903 01:20:03.933138 RX Vref Scan: 0
1904 01:20:03.933484
1905 01:20:03.935925 RX Vref 0 -> 0, step: 1
1906 01:20:03.936483
1907 01:20:03.938958 RX Delay -111 -> 252, step: 8
1908 01:20:03.942081 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
1909 01:20:03.944945 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1910 01:20:03.951975 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1911 01:20:03.955381 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1912 01:20:03.958762 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1913 01:20:03.961941 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1914 01:20:03.965926 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1915 01:20:03.972344 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1916 01:20:03.975392 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1917 01:20:03.978493 iDelay=217, Bit 9, Center 64 (-55 ~ 184) 240
1918 01:20:03.981695 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1919 01:20:03.985326 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1920 01:20:03.992019 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1921 01:20:03.994940 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1922 01:20:03.998517 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1923 01:20:04.001671 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1924 01:20:04.001830 ==
1925 01:20:04.005089 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 01:20:04.012127 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1927 01:20:04.012588 ==
1928 01:20:04.012959 DQS Delay:
1929 01:20:04.013303 DQS0 = 0, DQS1 = 0
1930 01:20:04.015250 DQM Delay:
1931 01:20:04.015817 DQM0 = 84, DQM1 = 74
1932 01:20:04.018870 DQ Delay:
1933 01:20:04.021708 DQ0 =88, DQ1 =76, DQ2 =76, DQ3 =80
1934 01:20:04.022056 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =80
1935 01:20:04.025464 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1936 01:20:04.031744 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1937 01:20:04.032009
1938 01:20:04.032228
1939 01:20:04.038660 [DQSOSCAuto] RK1, (LSB)MR18= 0x3535, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1940 01:20:04.041884 CH1 RK1: MR19=606, MR18=3535
1941 01:20:04.048553 CH1_RK1: MR19=0x606, MR18=0x3535, DQSOSC=396, MR23=63, INC=94, DEC=62
1942 01:20:04.051835 [RxdqsGatingPostProcess] freq 800
1943 01:20:04.055069 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1944 01:20:04.058458 Pre-setting of DQS Precalculation
1945 01:20:04.065657 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1946 01:20:04.072112 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1947 01:20:04.078487 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1948 01:20:04.078857
1949 01:20:04.079117
1950 01:20:04.081877 [Calibration Summary] 1600 Mbps
1951 01:20:04.082247 CH 0, Rank 0
1952 01:20:04.085251 SW Impedance : PASS
1953 01:20:04.085770 DUTY Scan : NO K
1954 01:20:04.088963 ZQ Calibration : PASS
1955 01:20:04.092267 Jitter Meter : NO K
1956 01:20:04.092824 CBT Training : PASS
1957 01:20:04.095207 Write leveling : PASS
1958 01:20:04.098702 RX DQS gating : PASS
1959 01:20:04.099164 RX DQ/DQS(RDDQC) : PASS
1960 01:20:04.102007 TX DQ/DQS : PASS
1961 01:20:04.105407 RX DATLAT : PASS
1962 01:20:04.105987 RX DQ/DQS(Engine): PASS
1963 01:20:04.108702 TX OE : NO K
1964 01:20:04.109258 All Pass.
1965 01:20:04.109631
1966 01:20:04.112291 CH 0, Rank 1
1967 01:20:04.112912 SW Impedance : PASS
1968 01:20:04.115387 DUTY Scan : NO K
1969 01:20:04.118827 ZQ Calibration : PASS
1970 01:20:04.119382 Jitter Meter : NO K
1971 01:20:04.121991 CBT Training : PASS
1972 01:20:04.125608 Write leveling : PASS
1973 01:20:04.126212 RX DQS gating : PASS
1974 01:20:04.128496 RX DQ/DQS(RDDQC) : PASS
1975 01:20:04.128961 TX DQ/DQS : PASS
1976 01:20:04.132157 RX DATLAT : PASS
1977 01:20:04.135742 RX DQ/DQS(Engine): PASS
1978 01:20:04.136302 TX OE : NO K
1979 01:20:04.138611 All Pass.
1980 01:20:04.139070
1981 01:20:04.139436 CH 1, Rank 0
1982 01:20:04.142216 SW Impedance : PASS
1983 01:20:04.142793 DUTY Scan : NO K
1984 01:20:04.145369 ZQ Calibration : PASS
1985 01:20:04.149040 Jitter Meter : NO K
1986 01:20:04.149606 CBT Training : PASS
1987 01:20:04.152149 Write leveling : PASS
1988 01:20:04.155750 RX DQS gating : PASS
1989 01:20:04.156314 RX DQ/DQS(RDDQC) : PASS
1990 01:20:04.159026 TX DQ/DQS : PASS
1991 01:20:04.162469 RX DATLAT : PASS
1992 01:20:04.163035 RX DQ/DQS(Engine): PASS
1993 01:20:04.165187 TX OE : NO K
1994 01:20:04.165650 All Pass.
1995 01:20:04.166021
1996 01:20:04.168542 CH 1, Rank 1
1997 01:20:04.169006 SW Impedance : PASS
1998 01:20:04.172357 DUTY Scan : NO K
1999 01:20:04.175175 ZQ Calibration : PASS
2000 01:20:04.175640 Jitter Meter : NO K
2001 01:20:04.178589 CBT Training : PASS
2002 01:20:04.179056 Write leveling : PASS
2003 01:20:04.181817 RX DQS gating : PASS
2004 01:20:04.185393 RX DQ/DQS(RDDQC) : PASS
2005 01:20:04.185956 TX DQ/DQS : PASS
2006 01:20:04.188693 RX DATLAT : PASS
2007 01:20:04.191966 RX DQ/DQS(Engine): PASS
2008 01:20:04.192524 TX OE : NO K
2009 01:20:04.194963 All Pass.
2010 01:20:04.195425
2011 01:20:04.195791 DramC Write-DBI off
2012 01:20:04.198585 PER_BANK_REFRESH: Hybrid Mode
2013 01:20:04.201354 TX_TRACKING: ON
2014 01:20:04.205063 [GetDramInforAfterCalByMRR] Vendor 6.
2015 01:20:04.208162 [GetDramInforAfterCalByMRR] Revision 606.
2016 01:20:04.211485 [GetDramInforAfterCalByMRR] Revision 2 0.
2017 01:20:04.212046 MR0 0x3939
2018 01:20:04.212430 MR8 0x1111
2019 01:20:04.218147 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2020 01:20:04.218705
2021 01:20:04.219081 MR0 0x3939
2022 01:20:04.219428 MR8 0x1111
2023 01:20:04.221747 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2024 01:20:04.222343
2025 01:20:04.231188 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2026 01:20:04.234843 [FAST_K] Save calibration result to emmc
2027 01:20:04.238202 [FAST_K] Save calibration result to emmc
2028 01:20:04.241234 dram_init: config_dvfs: 1
2029 01:20:04.244858 dramc_set_vcore_voltage set vcore to 662500
2030 01:20:04.248266 Read voltage for 1200, 2
2031 01:20:04.248880 Vio18 = 0
2032 01:20:04.251035 Vcore = 662500
2033 01:20:04.251497 Vdram = 0
2034 01:20:04.251866 Vddq = 0
2035 01:20:04.252213 Vmddr = 0
2036 01:20:04.257813 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2037 01:20:04.260960 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2038 01:20:04.264345 MEM_TYPE=3, freq_sel=15
2039 01:20:04.267362 sv_algorithm_assistance_LP4_1600
2040 01:20:04.270956 ============ PULL DRAM RESETB DOWN ============
2041 01:20:04.277578 ========== PULL DRAM RESETB DOWN end =========
2042 01:20:04.281139 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2043 01:20:04.284441 ===================================
2044 01:20:04.288127 LPDDR4 DRAM CONFIGURATION
2045 01:20:04.291010 ===================================
2046 01:20:04.291562 EX_ROW_EN[0] = 0x0
2047 01:20:04.294278 EX_ROW_EN[1] = 0x0
2048 01:20:04.294741 LP4Y_EN = 0x0
2049 01:20:04.297627 WORK_FSP = 0x0
2050 01:20:04.298113 WL = 0x4
2051 01:20:04.300908 RL = 0x4
2052 01:20:04.301465 BL = 0x2
2053 01:20:04.304304 RPST = 0x0
2054 01:20:04.304861 RD_PRE = 0x0
2055 01:20:04.307720 WR_PRE = 0x1
2056 01:20:04.310815 WR_PST = 0x0
2057 01:20:04.311312 DBI_WR = 0x0
2058 01:20:04.314379 DBI_RD = 0x0
2059 01:20:04.314938 OTF = 0x1
2060 01:20:04.317548 ===================================
2061 01:20:04.320693 ===================================
2062 01:20:04.321257 ANA top config
2063 01:20:04.324107 ===================================
2064 01:20:04.327511 DLL_ASYNC_EN = 0
2065 01:20:04.331010 ALL_SLAVE_EN = 0
2066 01:20:04.334313 NEW_RANK_MODE = 1
2067 01:20:04.337284 DLL_IDLE_MODE = 1
2068 01:20:04.337905 LP45_APHY_COMB_EN = 1
2069 01:20:04.340742 TX_ODT_DIS = 1
2070 01:20:04.343958 NEW_8X_MODE = 1
2071 01:20:04.347332 ===================================
2072 01:20:04.350688 ===================================
2073 01:20:04.354512 data_rate = 2400
2074 01:20:04.357683 CKR = 1
2075 01:20:04.358463 DQ_P2S_RATIO = 8
2076 01:20:04.360503 ===================================
2077 01:20:04.364029 CA_P2S_RATIO = 8
2078 01:20:04.367201 DQ_CA_OPEN = 0
2079 01:20:04.370722 DQ_SEMI_OPEN = 0
2080 01:20:04.374062 CA_SEMI_OPEN = 0
2081 01:20:04.377716 CA_FULL_RATE = 0
2082 01:20:04.378219 DQ_CKDIV4_EN = 0
2083 01:20:04.380485 CA_CKDIV4_EN = 0
2084 01:20:04.383720 CA_PREDIV_EN = 0
2085 01:20:04.387106 PH8_DLY = 17
2086 01:20:04.390639 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2087 01:20:04.393857 DQ_AAMCK_DIV = 4
2088 01:20:04.394368 CA_AAMCK_DIV = 4
2089 01:20:04.397176 CA_ADMCK_DIV = 4
2090 01:20:04.400446 DQ_TRACK_CA_EN = 0
2091 01:20:04.403692 CA_PICK = 1200
2092 01:20:04.407537 CA_MCKIO = 1200
2093 01:20:04.410546 MCKIO_SEMI = 0
2094 01:20:04.413965 PLL_FREQ = 2366
2095 01:20:04.414531 DQ_UI_PI_RATIO = 32
2096 01:20:04.417291 CA_UI_PI_RATIO = 0
2097 01:20:04.420488 ===================================
2098 01:20:04.424237 ===================================
2099 01:20:04.427124 memory_type:LPDDR4
2100 01:20:04.430880 GP_NUM : 10
2101 01:20:04.431399 SRAM_EN : 1
2102 01:20:04.433755 MD32_EN : 0
2103 01:20:04.437486 ===================================
2104 01:20:04.438009 [ANA_INIT] >>>>>>>>>>>>>>
2105 01:20:04.441099 <<<<<< [CONFIGURE PHASE]: ANA_TX
2106 01:20:04.443953 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2107 01:20:04.447449 ===================================
2108 01:20:04.450970 data_rate = 2400,PCW = 0X5b00
2109 01:20:04.454008 ===================================
2110 01:20:04.457445 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2111 01:20:04.464442 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2112 01:20:04.470719 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2113 01:20:04.474007 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2114 01:20:04.477543 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2115 01:20:04.480739 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2116 01:20:04.484506 [ANA_INIT] flow start
2117 01:20:04.485032 [ANA_INIT] PLL >>>>>>>>
2118 01:20:04.487499 [ANA_INIT] PLL <<<<<<<<
2119 01:20:04.490883 [ANA_INIT] MIDPI >>>>>>>>
2120 01:20:04.491404 [ANA_INIT] MIDPI <<<<<<<<
2121 01:20:04.493807 [ANA_INIT] DLL >>>>>>>>
2122 01:20:04.497297 [ANA_INIT] DLL <<<<<<<<
2123 01:20:04.497717 [ANA_INIT] flow end
2124 01:20:04.503798 ============ LP4 DIFF to SE enter ============
2125 01:20:04.507222 ============ LP4 DIFF to SE exit ============
2126 01:20:04.507747 [ANA_INIT] <<<<<<<<<<<<<
2127 01:20:04.510775 [Flow] Enable top DCM control >>>>>
2128 01:20:04.514006 [Flow] Enable top DCM control <<<<<
2129 01:20:04.517532 Enable DLL master slave shuffle
2130 01:20:04.523728 ==============================================================
2131 01:20:04.527274 Gating Mode config
2132 01:20:04.530840 ==============================================================
2133 01:20:04.533807 Config description:
2134 01:20:04.543901 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2135 01:20:04.550521 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2136 01:20:04.553942 SELPH_MODE 0: By rank 1: By Phase
2137 01:20:04.560514 ==============================================================
2138 01:20:04.563988 GAT_TRACK_EN = 1
2139 01:20:04.567312 RX_GATING_MODE = 2
2140 01:20:04.570561 RX_GATING_TRACK_MODE = 2
2141 01:20:04.571020 SELPH_MODE = 1
2142 01:20:04.573462 PICG_EARLY_EN = 1
2143 01:20:04.577198 VALID_LAT_VALUE = 1
2144 01:20:04.583796 ==============================================================
2145 01:20:04.586915 Enter into Gating configuration >>>>
2146 01:20:04.590789 Exit from Gating configuration <<<<
2147 01:20:04.593967 Enter into DVFS_PRE_config >>>>>
2148 01:20:04.603886 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2149 01:20:04.606949 Exit from DVFS_PRE_config <<<<<
2150 01:20:04.610514 Enter into PICG configuration >>>>
2151 01:20:04.613747 Exit from PICG configuration <<<<
2152 01:20:04.617316 [RX_INPUT] configuration >>>>>
2153 01:20:04.620721 [RX_INPUT] configuration <<<<<
2154 01:20:04.623876 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2155 01:20:04.630418 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2156 01:20:04.637869 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2157 01:20:04.643848 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2158 01:20:04.646779 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2159 01:20:04.653525 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2160 01:20:04.656865 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2161 01:20:04.664224 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2162 01:20:04.666957 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2163 01:20:04.670603 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2164 01:20:04.673794 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2165 01:20:04.680503 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2166 01:20:04.683436 ===================================
2167 01:20:04.683901 LPDDR4 DRAM CONFIGURATION
2168 01:20:04.686887 ===================================
2169 01:20:04.690254 EX_ROW_EN[0] = 0x0
2170 01:20:04.693728 EX_ROW_EN[1] = 0x0
2171 01:20:04.694363 LP4Y_EN = 0x0
2172 01:20:04.696921 WORK_FSP = 0x0
2173 01:20:04.697397 WL = 0x4
2174 01:20:04.700364 RL = 0x4
2175 01:20:04.700931 BL = 0x2
2176 01:20:04.703386 RPST = 0x0
2177 01:20:04.703848 RD_PRE = 0x0
2178 01:20:04.706919 WR_PRE = 0x1
2179 01:20:04.707489 WR_PST = 0x0
2180 01:20:04.710216 DBI_WR = 0x0
2181 01:20:04.710785 DBI_RD = 0x0
2182 01:20:04.713410 OTF = 0x1
2183 01:20:04.716987 ===================================
2184 01:20:04.720117 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2185 01:20:04.723485 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2186 01:20:04.730121 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2187 01:20:04.733499 ===================================
2188 01:20:04.734100 LPDDR4 DRAM CONFIGURATION
2189 01:20:04.736867 ===================================
2190 01:20:04.740460 EX_ROW_EN[0] = 0x10
2191 01:20:04.741085 EX_ROW_EN[1] = 0x0
2192 01:20:04.743514 LP4Y_EN = 0x0
2193 01:20:04.746811 WORK_FSP = 0x0
2194 01:20:04.747381 WL = 0x4
2195 01:20:04.750484 RL = 0x4
2196 01:20:04.751048 BL = 0x2
2197 01:20:04.753581 RPST = 0x0
2198 01:20:04.754187 RD_PRE = 0x0
2199 01:20:04.756873 WR_PRE = 0x1
2200 01:20:04.757434 WR_PST = 0x0
2201 01:20:04.760598 DBI_WR = 0x0
2202 01:20:04.761199 DBI_RD = 0x0
2203 01:20:04.763255 OTF = 0x1
2204 01:20:04.766677 ===================================
2205 01:20:04.773582 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2206 01:20:04.774183 ==
2207 01:20:04.776575 Dram Type= 6, Freq= 0, CH_0, rank 0
2208 01:20:04.779962 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2209 01:20:04.780426 ==
2210 01:20:04.783300 [Duty_Offset_Calibration]
2211 01:20:04.783760 B0:0 B1:2 CA:1
2212 01:20:04.784127
2213 01:20:04.786439 [DutyScan_Calibration_Flow] k_type=0
2214 01:20:04.796276
2215 01:20:04.796836 ==CLK 0==
2216 01:20:04.799727 Final CLK duty delay cell = 0
2217 01:20:04.803043 [0] MAX Duty = 5093%(X100), DQS PI = 12
2218 01:20:04.806250 [0] MIN Duty = 4938%(X100), DQS PI = 54
2219 01:20:04.806715 [0] AVG Duty = 5015%(X100)
2220 01:20:04.809745
2221 01:20:04.813280 CH0 CLK Duty spec in!! Max-Min= 155%
2222 01:20:04.816595 [DutyScan_Calibration_Flow] ====Done====
2223 01:20:04.817154
2224 01:20:04.820392 [DutyScan_Calibration_Flow] k_type=1
2225 01:20:04.835942
2226 01:20:04.836584 ==DQS 0 ==
2227 01:20:04.838916 Final DQS duty delay cell = 0
2228 01:20:04.842508 [0] MAX Duty = 5125%(X100), DQS PI = 30
2229 01:20:04.845615 [0] MIN Duty = 5031%(X100), DQS PI = 4
2230 01:20:04.846216 [0] AVG Duty = 5078%(X100)
2231 01:20:04.849363
2232 01:20:04.849928 ==DQS 1 ==
2233 01:20:04.852945 Final DQS duty delay cell = 0
2234 01:20:04.855778 [0] MAX Duty = 5031%(X100), DQS PI = 54
2235 01:20:04.859263 [0] MIN Duty = 4906%(X100), DQS PI = 16
2236 01:20:04.859830 [0] AVG Duty = 4968%(X100)
2237 01:20:04.862629
2238 01:20:04.865801 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2239 01:20:04.866409
2240 01:20:04.868970 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2241 01:20:04.872416 [DutyScan_Calibration_Flow] ====Done====
2242 01:20:04.872991
2243 01:20:04.875711 [DutyScan_Calibration_Flow] k_type=3
2244 01:20:04.893514
2245 01:20:04.894140 ==DQM 0 ==
2246 01:20:04.896323 Final DQM duty delay cell = 0
2247 01:20:04.899339 [0] MAX Duty = 5187%(X100), DQS PI = 22
2248 01:20:04.902642 [0] MIN Duty = 4969%(X100), DQS PI = 40
2249 01:20:04.903107 [0] AVG Duty = 5078%(X100)
2250 01:20:04.906806
2251 01:20:04.907372 ==DQM 1 ==
2252 01:20:04.909629 Final DQM duty delay cell = 4
2253 01:20:04.912910 [4] MAX Duty = 5156%(X100), DQS PI = 52
2254 01:20:04.916380 [4] MIN Duty = 5000%(X100), DQS PI = 16
2255 01:20:04.919397 [4] AVG Duty = 5078%(X100)
2256 01:20:04.919966
2257 01:20:04.923024 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2258 01:20:04.923592
2259 01:20:04.926075 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2260 01:20:04.929803 [DutyScan_Calibration_Flow] ====Done====
2261 01:20:04.930427
2262 01:20:04.932750 [DutyScan_Calibration_Flow] k_type=2
2263 01:20:04.947703
2264 01:20:04.948269 ==DQ 0 ==
2265 01:20:04.951002 Final DQ duty delay cell = -4
2266 01:20:04.954524 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2267 01:20:04.957983 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2268 01:20:04.961022 [-4] AVG Duty = 4937%(X100)
2269 01:20:04.961632
2270 01:20:04.962015 ==DQ 1 ==
2271 01:20:04.964559 Final DQ duty delay cell = -4
2272 01:20:04.968032 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2273 01:20:04.971142 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2274 01:20:04.974339 [-4] AVG Duty = 4969%(X100)
2275 01:20:04.974917
2276 01:20:04.977821 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2277 01:20:04.978450
2278 01:20:04.981254 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2279 01:20:04.984220 [DutyScan_Calibration_Flow] ====Done====
2280 01:20:04.984680 ==
2281 01:20:04.987536 Dram Type= 6, Freq= 0, CH_1, rank 0
2282 01:20:04.990856 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2283 01:20:04.991318 ==
2284 01:20:04.994207 [Duty_Offset_Calibration]
2285 01:20:04.994669 B0:0 B1:5 CA:-5
2286 01:20:04.995031
2287 01:20:04.997676 [DutyScan_Calibration_Flow] k_type=0
2288 01:20:05.008846
2289 01:20:05.009442 ==CLK 0==
2290 01:20:05.011595 Final CLK duty delay cell = 0
2291 01:20:05.015458 [0] MAX Duty = 5094%(X100), DQS PI = 24
2292 01:20:05.018481 [0] MIN Duty = 4907%(X100), DQS PI = 44
2293 01:20:05.019045 [0] AVG Duty = 5000%(X100)
2294 01:20:05.021962
2295 01:20:05.022568 CH1 CLK Duty spec in!! Max-Min= 187%
2296 01:20:05.028501 [DutyScan_Calibration_Flow] ====Done====
2297 01:20:05.029064
2298 01:20:05.031419 [DutyScan_Calibration_Flow] k_type=1
2299 01:20:05.046991
2300 01:20:05.047562 ==DQS 0 ==
2301 01:20:05.050513 Final DQS duty delay cell = 0
2302 01:20:05.053520 [0] MAX Duty = 5125%(X100), DQS PI = 16
2303 01:20:05.056903 [0] MIN Duty = 4875%(X100), DQS PI = 40
2304 01:20:05.059870 [0] AVG Duty = 5000%(X100)
2305 01:20:05.060336
2306 01:20:05.060706 ==DQS 1 ==
2307 01:20:05.063481 Final DQS duty delay cell = -4
2308 01:20:05.066759 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2309 01:20:05.069918 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2310 01:20:05.073231 [-4] AVG Duty = 4953%(X100)
2311 01:20:05.073693
2312 01:20:05.076816 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2313 01:20:05.077383
2314 01:20:05.079731 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2315 01:20:05.083270 [DutyScan_Calibration_Flow] ====Done====
2316 01:20:05.083915
2317 01:20:05.086425 [DutyScan_Calibration_Flow] k_type=3
2318 01:20:05.102127
2319 01:20:05.102688 ==DQM 0 ==
2320 01:20:05.105977 Final DQM duty delay cell = -4
2321 01:20:05.108713 [-4] MAX Duty = 5093%(X100), DQS PI = 32
2322 01:20:05.112139 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2323 01:20:05.115601 [-4] AVG Duty = 4968%(X100)
2324 01:20:05.116169
2325 01:20:05.116541 ==DQM 1 ==
2326 01:20:05.118669 Final DQM duty delay cell = -4
2327 01:20:05.122206 [-4] MAX Duty = 5094%(X100), DQS PI = 22
2328 01:20:05.125725 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2329 01:20:05.129444 [-4] AVG Duty = 5000%(X100)
2330 01:20:05.129980
2331 01:20:05.132240 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2332 01:20:05.132706
2333 01:20:05.135451 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2334 01:20:05.139029 [DutyScan_Calibration_Flow] ====Done====
2335 01:20:05.139604
2336 01:20:05.141984 [DutyScan_Calibration_Flow] k_type=2
2337 01:20:05.159796
2338 01:20:05.160359 ==DQ 0 ==
2339 01:20:05.162588 Final DQ duty delay cell = 0
2340 01:20:05.165998 [0] MAX Duty = 5062%(X100), DQS PI = 0
2341 01:20:05.169780 [0] MIN Duty = 4938%(X100), DQS PI = 44
2342 01:20:05.170296 [0] AVG Duty = 5000%(X100)
2343 01:20:05.170673
2344 01:20:05.172710 ==DQ 1 ==
2345 01:20:05.175978 Final DQ duty delay cell = 0
2346 01:20:05.179227 [0] MAX Duty = 5000%(X100), DQS PI = 6
2347 01:20:05.182525 [0] MIN Duty = 4907%(X100), DQS PI = 0
2348 01:20:05.182991 [0] AVG Duty = 4953%(X100)
2349 01:20:05.183365
2350 01:20:05.185932 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2351 01:20:05.186435
2352 01:20:05.189489 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2353 01:20:05.196558 [DutyScan_Calibration_Flow] ====Done====
2354 01:20:05.198988 nWR fixed to 30
2355 01:20:05.199458 [ModeRegInit_LP4] CH0 RK0
2356 01:20:05.203363 [ModeRegInit_LP4] CH0 RK1
2357 01:20:05.205841 [ModeRegInit_LP4] CH1 RK0
2358 01:20:05.206386 [ModeRegInit_LP4] CH1 RK1
2359 01:20:05.209139 match AC timing 6
2360 01:20:05.212468 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2361 01:20:05.215683 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2362 01:20:05.222634 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2363 01:20:05.225828 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2364 01:20:05.232359 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2365 01:20:05.232819 ==
2366 01:20:05.236045 Dram Type= 6, Freq= 0, CH_0, rank 0
2367 01:20:05.239028 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2368 01:20:05.239526 ==
2369 01:20:05.245811 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2370 01:20:05.249529 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2371 01:20:05.258808 [CA 0] Center 39 (9~70) winsize 62
2372 01:20:05.262605 [CA 1] Center 39 (8~70) winsize 63
2373 01:20:05.265372 [CA 2] Center 36 (5~67) winsize 63
2374 01:20:05.268694 [CA 3] Center 35 (4~66) winsize 63
2375 01:20:05.272027 [CA 4] Center 34 (3~65) winsize 63
2376 01:20:05.275951 [CA 5] Center 33 (3~64) winsize 62
2377 01:20:05.276550
2378 01:20:05.279249 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2379 01:20:05.279714
2380 01:20:05.282244 [CATrainingPosCal] consider 1 rank data
2381 01:20:05.285796 u2DelayCellTimex100 = 270/100 ps
2382 01:20:05.288890 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2383 01:20:05.292189 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2384 01:20:05.298745 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2385 01:20:05.302308 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2386 01:20:05.305879 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2387 01:20:05.308861 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2388 01:20:05.309423
2389 01:20:05.312440 CA PerBit enable=1, Macro0, CA PI delay=33
2390 01:20:05.313002
2391 01:20:05.315437 [CBTSetCACLKResult] CA Dly = 33
2392 01:20:05.315996 CS Dly: 7 (0~38)
2393 01:20:05.318603 ==
2394 01:20:05.319075 Dram Type= 6, Freq= 0, CH_0, rank 1
2395 01:20:05.325765 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2396 01:20:05.326381 ==
2397 01:20:05.328689 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2398 01:20:05.335193 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2399 01:20:05.345056 [CA 0] Center 39 (8~70) winsize 63
2400 01:20:05.348223 [CA 1] Center 39 (8~70) winsize 63
2401 01:20:05.350835 [CA 2] Center 36 (5~67) winsize 63
2402 01:20:05.354483 [CA 3] Center 35 (4~66) winsize 63
2403 01:20:05.357791 [CA 4] Center 33 (3~64) winsize 62
2404 01:20:05.361132 [CA 5] Center 34 (3~65) winsize 63
2405 01:20:05.361693
2406 01:20:05.364420 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2407 01:20:05.364979
2408 01:20:05.367561 [CATrainingPosCal] consider 2 rank data
2409 01:20:05.370949 u2DelayCellTimex100 = 270/100 ps
2410 01:20:05.374475 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2411 01:20:05.377688 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2412 01:20:05.384147 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2413 01:20:05.387471 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2414 01:20:05.390783 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2415 01:20:05.394005 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2416 01:20:05.394501
2417 01:20:05.397743 CA PerBit enable=1, Macro0, CA PI delay=33
2418 01:20:05.398444
2419 01:20:05.400899 [CBTSetCACLKResult] CA Dly = 33
2420 01:20:05.401477 CS Dly: 7 (0~39)
2421 01:20:05.404434
2422 01:20:05.407485 ----->DramcWriteLeveling(PI) begin...
2423 01:20:05.408051 ==
2424 01:20:05.410527 Dram Type= 6, Freq= 0, CH_0, rank 0
2425 01:20:05.413996 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2426 01:20:05.414591 ==
2427 01:20:05.417724 Write leveling (Byte 0): 26 => 26
2428 01:20:05.421049 Write leveling (Byte 1): 25 => 25
2429 01:20:05.424544 DramcWriteLeveling(PI) end<-----
2430 01:20:05.425110
2431 01:20:05.425492 ==
2432 01:20:05.427092 Dram Type= 6, Freq= 0, CH_0, rank 0
2433 01:20:05.430452 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2434 01:20:05.430911 ==
2435 01:20:05.434240 [Gating] SW mode calibration
2436 01:20:05.440879 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2437 01:20:05.447088 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2438 01:20:05.450701 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2439 01:20:05.453789 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2440 01:20:05.460761 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2441 01:20:05.463780 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2442 01:20:05.467666 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2443 01:20:05.470399 0 11 20 | B1->B0 | 3131 2c2c | 0 1 | (0 1) (1 0)
2444 01:20:05.477258 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2445 01:20:05.480444 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2446 01:20:05.483814 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2447 01:20:05.490705 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2448 01:20:05.493804 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2449 01:20:05.497219 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2450 01:20:05.504064 0 12 16 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
2451 01:20:05.507567 0 12 20 | B1->B0 | 3232 3c3c | 1 0 | (0 0) (0 0)
2452 01:20:05.510293 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2453 01:20:05.517283 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2454 01:20:05.520659 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2455 01:20:05.524104 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2456 01:20:05.530962 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2457 01:20:05.533879 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2458 01:20:05.537603 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2459 01:20:05.544008 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2460 01:20:05.546959 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2461 01:20:05.550341 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2462 01:20:05.557478 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2463 01:20:05.560269 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2464 01:20:05.563428 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2465 01:20:05.570558 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2466 01:20:05.573389 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2467 01:20:05.576708 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2468 01:20:05.583517 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2469 01:20:05.587032 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2470 01:20:05.590206 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2471 01:20:05.596967 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2472 01:20:05.600207 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2473 01:20:05.603802 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2474 01:20:05.610400 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2475 01:20:05.613588 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2476 01:20:05.616929 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2477 01:20:05.620255 Total UI for P1: 0, mck2ui 16
2478 01:20:05.623735 best dqsien dly found for B0: ( 0, 15, 20)
2479 01:20:05.627067 Total UI for P1: 0, mck2ui 16
2480 01:20:05.630182 best dqsien dly found for B1: ( 0, 15, 20)
2481 01:20:05.633403 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2482 01:20:05.636972 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2483 01:20:05.637538
2484 01:20:05.640418 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2485 01:20:05.646877 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2486 01:20:05.647521 [Gating] SW calibration Done
2487 01:20:05.647897 ==
2488 01:20:05.650330 Dram Type= 6, Freq= 0, CH_0, rank 0
2489 01:20:05.656439 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2490 01:20:05.656897 ==
2491 01:20:05.657259 RX Vref Scan: 0
2492 01:20:05.657597
2493 01:20:05.660187 RX Vref 0 -> 0, step: 1
2494 01:20:05.660747
2495 01:20:05.663463 RX Delay -40 -> 252, step: 8
2496 01:20:05.666905 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2497 01:20:05.669998 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2498 01:20:05.673199 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2499 01:20:05.680168 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2500 01:20:05.683126 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2501 01:20:05.686732 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2502 01:20:05.689896 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2503 01:20:05.693269 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2504 01:20:05.696822 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2505 01:20:05.703392 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2506 01:20:05.706597 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2507 01:20:05.710089 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2508 01:20:05.713250 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2509 01:20:05.719552 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2510 01:20:05.723299 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2511 01:20:05.726643 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2512 01:20:05.727212 ==
2513 01:20:05.729643 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 01:20:05.733168 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2515 01:20:05.733742 ==
2516 01:20:05.736308 DQS Delay:
2517 01:20:05.736893 DQS0 = 0, DQS1 = 0
2518 01:20:05.739803 DQM Delay:
2519 01:20:05.740397 DQM0 = 115, DQM1 = 106
2520 01:20:05.740893 DQ Delay:
2521 01:20:05.742632 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2522 01:20:05.749713 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2523 01:20:05.752909 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2524 01:20:05.756233 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2525 01:20:05.756714
2526 01:20:05.757195
2527 01:20:05.757646 ==
2528 01:20:05.759147 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 01:20:05.762850 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2530 01:20:05.763389 ==
2531 01:20:05.763872
2532 01:20:05.764328
2533 01:20:05.766001 TX Vref Scan disable
2534 01:20:05.769414 == TX Byte 0 ==
2535 01:20:05.772875 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2536 01:20:05.776374 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2537 01:20:05.779395 == TX Byte 1 ==
2538 01:20:05.782583 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2539 01:20:05.785595 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2540 01:20:05.786092 ==
2541 01:20:05.789220 Dram Type= 6, Freq= 0, CH_0, rank 0
2542 01:20:05.792714 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2543 01:20:05.795569 ==
2544 01:20:05.806119 TX Vref=22, minBit 5, minWin=24, winSum=412
2545 01:20:05.809662 TX Vref=24, minBit 10, minWin=24, winSum=413
2546 01:20:05.812744 TX Vref=26, minBit 8, minWin=25, winSum=426
2547 01:20:05.815737 TX Vref=28, minBit 9, minWin=25, winSum=423
2548 01:20:05.818778 TX Vref=30, minBit 9, minWin=26, winSum=430
2549 01:20:05.825557 TX Vref=32, minBit 5, minWin=26, winSum=431
2550 01:20:05.828814 [TxChooseVref] Worse bit 5, Min win 26, Win sum 431, Final Vref 32
2551 01:20:05.829282
2552 01:20:05.832214 Final TX Range 1 Vref 32
2553 01:20:05.832788
2554 01:20:05.833241 ==
2555 01:20:05.835360 Dram Type= 6, Freq= 0, CH_0, rank 0
2556 01:20:05.838715 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2557 01:20:05.842194 ==
2558 01:20:05.842752
2559 01:20:05.843162
2560 01:20:05.843512 TX Vref Scan disable
2561 01:20:05.845496 == TX Byte 0 ==
2562 01:20:05.848911 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2563 01:20:05.852533 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2564 01:20:05.855695 == TX Byte 1 ==
2565 01:20:05.858910 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2566 01:20:05.865590 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2567 01:20:05.866177
2568 01:20:05.866546 [DATLAT]
2569 01:20:05.866890 Freq=1200, CH0 RK0
2570 01:20:05.867220
2571 01:20:05.868814 DATLAT Default: 0xd
2572 01:20:05.869272 0, 0xFFFF, sum = 0
2573 01:20:05.872391 1, 0xFFFF, sum = 0
2574 01:20:05.872963 2, 0xFFFF, sum = 0
2575 01:20:05.875257 3, 0xFFFF, sum = 0
2576 01:20:05.879038 4, 0xFFFF, sum = 0
2577 01:20:05.879605 5, 0xFFFF, sum = 0
2578 01:20:05.881953 6, 0xFFFF, sum = 0
2579 01:20:05.882710 7, 0xFFFF, sum = 0
2580 01:20:05.885270 8, 0xFFFF, sum = 0
2581 01:20:05.885740 9, 0xFFFF, sum = 0
2582 01:20:05.888980 10, 0xFFFF, sum = 0
2583 01:20:05.889639 11, 0x0, sum = 1
2584 01:20:05.892429 12, 0x0, sum = 2
2585 01:20:05.893006 13, 0x0, sum = 3
2586 01:20:05.895645 14, 0x0, sum = 4
2587 01:20:05.896213 best_step = 12
2588 01:20:05.896584
2589 01:20:05.896929 ==
2590 01:20:05.899052 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 01:20:05.901857 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2592 01:20:05.902360 ==
2593 01:20:05.905642 RX Vref Scan: 1
2594 01:20:05.906248
2595 01:20:05.909168 Set Vref Range= 32 -> 127
2596 01:20:05.909727
2597 01:20:05.910151 RX Vref 32 -> 127, step: 1
2598 01:20:05.910505
2599 01:20:05.911952 RX Delay -21 -> 252, step: 4
2600 01:20:05.912412
2601 01:20:05.915756 Set Vref, RX VrefLevel [Byte0]: 32
2602 01:20:05.918637 [Byte1]: 32
2603 01:20:05.922478
2604 01:20:05.923115 Set Vref, RX VrefLevel [Byte0]: 33
2605 01:20:05.925750 [Byte1]: 33
2606 01:20:05.930202
2607 01:20:05.930754 Set Vref, RX VrefLevel [Byte0]: 34
2608 01:20:05.933499 [Byte1]: 34
2609 01:20:05.937877
2610 01:20:05.938375 Set Vref, RX VrefLevel [Byte0]: 35
2611 01:20:05.941350 [Byte1]: 35
2612 01:20:05.946210
2613 01:20:05.946764 Set Vref, RX VrefLevel [Byte0]: 36
2614 01:20:05.949173 [Byte1]: 36
2615 01:20:05.954273
2616 01:20:05.954835 Set Vref, RX VrefLevel [Byte0]: 37
2617 01:20:05.957612 [Byte1]: 37
2618 01:20:05.962235
2619 01:20:05.962793 Set Vref, RX VrefLevel [Byte0]: 38
2620 01:20:05.964976 [Byte1]: 38
2621 01:20:05.970184
2622 01:20:05.970742 Set Vref, RX VrefLevel [Byte0]: 39
2623 01:20:05.973183 [Byte1]: 39
2624 01:20:05.977840
2625 01:20:05.978346 Set Vref, RX VrefLevel [Byte0]: 40
2626 01:20:05.981327 [Byte1]: 40
2627 01:20:05.985409
2628 01:20:05.985867 Set Vref, RX VrefLevel [Byte0]: 41
2629 01:20:05.988711 [Byte1]: 41
2630 01:20:05.993350
2631 01:20:05.993807 Set Vref, RX VrefLevel [Byte0]: 42
2632 01:20:05.996651 [Byte1]: 42
2633 01:20:06.001305
2634 01:20:06.001762 Set Vref, RX VrefLevel [Byte0]: 43
2635 01:20:06.005048 [Byte1]: 43
2636 01:20:06.009756
2637 01:20:06.010370 Set Vref, RX VrefLevel [Byte0]: 44
2638 01:20:06.012791 [Byte1]: 44
2639 01:20:06.017479
2640 01:20:06.018070 Set Vref, RX VrefLevel [Byte0]: 45
2641 01:20:06.021011 [Byte1]: 45
2642 01:20:06.025345
2643 01:20:06.025909 Set Vref, RX VrefLevel [Byte0]: 46
2644 01:20:06.028243 [Byte1]: 46
2645 01:20:06.033164
2646 01:20:06.033856 Set Vref, RX VrefLevel [Byte0]: 47
2647 01:20:06.036261 [Byte1]: 47
2648 01:20:06.041329
2649 01:20:06.041894 Set Vref, RX VrefLevel [Byte0]: 48
2650 01:20:06.044246 [Byte1]: 48
2651 01:20:06.049378
2652 01:20:06.049944 Set Vref, RX VrefLevel [Byte0]: 49
2653 01:20:06.052758 [Byte1]: 49
2654 01:20:06.057233
2655 01:20:06.057794 Set Vref, RX VrefLevel [Byte0]: 50
2656 01:20:06.060407 [Byte1]: 50
2657 01:20:06.065100
2658 01:20:06.065674 Set Vref, RX VrefLevel [Byte0]: 51
2659 01:20:06.067876 [Byte1]: 51
2660 01:20:06.072937
2661 01:20:06.073499 Set Vref, RX VrefLevel [Byte0]: 52
2662 01:20:06.076094 [Byte1]: 52
2663 01:20:06.080752
2664 01:20:06.081313 Set Vref, RX VrefLevel [Byte0]: 53
2665 01:20:06.084173 [Byte1]: 53
2666 01:20:06.088336
2667 01:20:06.088796 Set Vref, RX VrefLevel [Byte0]: 54
2668 01:20:06.091613 [Byte1]: 54
2669 01:20:06.096492
2670 01:20:06.097055 Set Vref, RX VrefLevel [Byte0]: 55
2671 01:20:06.099886 [Byte1]: 55
2672 01:20:06.104435
2673 01:20:06.105005 Set Vref, RX VrefLevel [Byte0]: 56
2674 01:20:06.107687 [Byte1]: 56
2675 01:20:06.112376
2676 01:20:06.112939 Set Vref, RX VrefLevel [Byte0]: 57
2677 01:20:06.115658 [Byte1]: 57
2678 01:20:06.120342
2679 01:20:06.120904 Set Vref, RX VrefLevel [Byte0]: 58
2680 01:20:06.123722 [Byte1]: 58
2681 01:20:06.128205
2682 01:20:06.128764 Set Vref, RX VrefLevel [Byte0]: 59
2683 01:20:06.131747 [Byte1]: 59
2684 01:20:06.136315
2685 01:20:06.136876 Set Vref, RX VrefLevel [Byte0]: 60
2686 01:20:06.140014 [Byte1]: 60
2687 01:20:06.144400
2688 01:20:06.145081 Set Vref, RX VrefLevel [Byte0]: 61
2689 01:20:06.147141 [Byte1]: 61
2690 01:20:06.152387
2691 01:20:06.152973 Set Vref, RX VrefLevel [Byte0]: 62
2692 01:20:06.155169 [Byte1]: 62
2693 01:20:06.159919
2694 01:20:06.160494 Set Vref, RX VrefLevel [Byte0]: 63
2695 01:20:06.163422 [Byte1]: 63
2696 01:20:06.167899
2697 01:20:06.168466 Set Vref, RX VrefLevel [Byte0]: 64
2698 01:20:06.171121 [Byte1]: 64
2699 01:20:06.175689
2700 01:20:06.176243 Set Vref, RX VrefLevel [Byte0]: 65
2701 01:20:06.179369 [Byte1]: 65
2702 01:20:06.183577
2703 01:20:06.184346 Set Vref, RX VrefLevel [Byte0]: 66
2704 01:20:06.186934 [Byte1]: 66
2705 01:20:06.191608
2706 01:20:06.192064 Final RX Vref Byte 0 = 45 to rank0
2707 01:20:06.194592 Final RX Vref Byte 1 = 48 to rank0
2708 01:20:06.198167 Final RX Vref Byte 0 = 45 to rank1
2709 01:20:06.201835 Final RX Vref Byte 1 = 48 to rank1==
2710 01:20:06.204805 Dram Type= 6, Freq= 0, CH_0, rank 0
2711 01:20:06.211331 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2712 01:20:06.211883 ==
2713 01:20:06.212256 DQS Delay:
2714 01:20:06.212597 DQS0 = 0, DQS1 = 0
2715 01:20:06.214758 DQM Delay:
2716 01:20:06.215213 DQM0 = 114, DQM1 = 105
2717 01:20:06.217908 DQ Delay:
2718 01:20:06.221569 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2719 01:20:06.224743 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =120
2720 01:20:06.228169 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =96
2721 01:20:06.231301 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =114
2722 01:20:06.231863
2723 01:20:06.232233
2724 01:20:06.237977 [DQSOSCAuto] RK0, (LSB)MR18= 0x404, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
2725 01:20:06.241471 CH0 RK0: MR19=404, MR18=404
2726 01:20:06.248390 CH0_RK0: MR19=0x404, MR18=0x404, DQSOSC=408, MR23=63, INC=39, DEC=26
2727 01:20:06.249065
2728 01:20:06.251341 ----->DramcWriteLeveling(PI) begin...
2729 01:20:06.251809 ==
2730 01:20:06.254657 Dram Type= 6, Freq= 0, CH_0, rank 1
2731 01:20:06.258564 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2732 01:20:06.261225 ==
2733 01:20:06.261788 Write leveling (Byte 0): 27 => 27
2734 01:20:06.264479 Write leveling (Byte 1): 26 => 26
2735 01:20:06.267990 DramcWriteLeveling(PI) end<-----
2736 01:20:06.268554
2737 01:20:06.268923 ==
2738 01:20:06.271229 Dram Type= 6, Freq= 0, CH_0, rank 1
2739 01:20:06.277730 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2740 01:20:06.278346 ==
2741 01:20:06.278724 [Gating] SW mode calibration
2742 01:20:06.287413 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2743 01:20:06.290685 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2744 01:20:06.297867 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2745 01:20:06.301075 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2746 01:20:06.304285 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2747 01:20:06.307671 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2748 01:20:06.314218 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2749 01:20:06.317559 0 11 20 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
2750 01:20:06.321014 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2751 01:20:06.327581 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2752 01:20:06.330759 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2753 01:20:06.333982 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2754 01:20:06.341051 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2755 01:20:06.344521 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2756 01:20:06.347711 0 12 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2757 01:20:06.354543 0 12 20 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2758 01:20:06.357570 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2759 01:20:06.361056 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2760 01:20:06.367839 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2761 01:20:06.371245 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2762 01:20:06.374655 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2763 01:20:06.381087 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2764 01:20:06.384192 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2765 01:20:06.387527 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2766 01:20:06.394062 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2767 01:20:06.397637 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2768 01:20:06.401014 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2769 01:20:06.407242 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2770 01:20:06.410675 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2771 01:20:06.414235 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2772 01:20:06.417510 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2773 01:20:06.424109 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2774 01:20:06.427216 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2775 01:20:06.431040 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2776 01:20:06.437371 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2777 01:20:06.441000 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2778 01:20:06.444092 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2779 01:20:06.450876 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2780 01:20:06.454192 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2781 01:20:06.457192 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2782 01:20:06.464322 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2783 01:20:06.464953 Total UI for P1: 0, mck2ui 16
2784 01:20:06.470822 best dqsien dly found for B0: ( 0, 15, 18)
2785 01:20:06.471390 Total UI for P1: 0, mck2ui 16
2786 01:20:06.477492 best dqsien dly found for B1: ( 0, 15, 18)
2787 01:20:06.480752 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2788 01:20:06.484145 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2789 01:20:06.484738
2790 01:20:06.487399 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2791 01:20:06.491125 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2792 01:20:06.493868 [Gating] SW calibration Done
2793 01:20:06.494534 ==
2794 01:20:06.497272 Dram Type= 6, Freq= 0, CH_0, rank 1
2795 01:20:06.501124 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2796 01:20:06.501733 ==
2797 01:20:06.504321 RX Vref Scan: 0
2798 01:20:06.504884
2799 01:20:06.505252 RX Vref 0 -> 0, step: 1
2800 01:20:06.505598
2801 01:20:06.507269 RX Delay -40 -> 252, step: 8
2802 01:20:06.510710 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2803 01:20:06.517381 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2804 01:20:06.520774 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2805 01:20:06.524263 iDelay=200, Bit 3, Center 107 (40 ~ 175) 136
2806 01:20:06.527350 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2807 01:20:06.530526 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2808 01:20:06.537242 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
2809 01:20:06.540391 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2810 01:20:06.543943 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2811 01:20:06.547379 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2812 01:20:06.550788 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2813 01:20:06.554337 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2814 01:20:06.560962 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2815 01:20:06.563956 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2816 01:20:06.567852 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2817 01:20:06.570837 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2818 01:20:06.571259 ==
2819 01:20:06.573857 Dram Type= 6, Freq= 0, CH_0, rank 1
2820 01:20:06.580647 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2821 01:20:06.581173 ==
2822 01:20:06.581511 DQS Delay:
2823 01:20:06.583866 DQS0 = 0, DQS1 = 0
2824 01:20:06.584509 DQM Delay:
2825 01:20:06.586965 DQM0 = 114, DQM1 = 107
2826 01:20:06.587411 DQ Delay:
2827 01:20:06.590503 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =107
2828 01:20:06.593791 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2829 01:20:06.596888 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2830 01:20:06.600840 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2831 01:20:06.601291
2832 01:20:06.601730
2833 01:20:06.602287 ==
2834 01:20:06.603775 Dram Type= 6, Freq= 0, CH_0, rank 1
2835 01:20:06.607477 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2836 01:20:06.611263 ==
2837 01:20:06.611811
2838 01:20:06.612266
2839 01:20:06.612685 TX Vref Scan disable
2840 01:20:06.613699 == TX Byte 0 ==
2841 01:20:06.617318 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2842 01:20:06.620355 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2843 01:20:06.623915 == TX Byte 1 ==
2844 01:20:06.627087 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2845 01:20:06.630787 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2846 01:20:06.634504 ==
2847 01:20:06.635052 Dram Type= 6, Freq= 0, CH_0, rank 1
2848 01:20:06.640683 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2849 01:20:06.641255 ==
2850 01:20:06.651524 TX Vref=22, minBit 8, minWin=25, winSum=416
2851 01:20:06.654813 TX Vref=24, minBit 1, minWin=26, winSum=424
2852 01:20:06.658012 TX Vref=26, minBit 10, minWin=25, winSum=429
2853 01:20:06.661198 TX Vref=28, minBit 9, minWin=26, winSum=434
2854 01:20:06.664824 TX Vref=30, minBit 8, minWin=26, winSum=432
2855 01:20:06.671741 TX Vref=32, minBit 8, minWin=26, winSum=435
2856 01:20:06.674484 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 32
2857 01:20:06.674969
2858 01:20:06.677627 Final TX Range 1 Vref 32
2859 01:20:06.678158
2860 01:20:06.678646 ==
2861 01:20:06.681407 Dram Type= 6, Freq= 0, CH_0, rank 1
2862 01:20:06.684774 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2863 01:20:06.687536 ==
2864 01:20:06.688005
2865 01:20:06.688377
2866 01:20:06.688715 TX Vref Scan disable
2867 01:20:06.692054 == TX Byte 0 ==
2868 01:20:06.694285 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2869 01:20:06.701154 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2870 01:20:06.701723 == TX Byte 1 ==
2871 01:20:06.704644 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2872 01:20:06.708032 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2873 01:20:06.711690
2874 01:20:06.712257 [DATLAT]
2875 01:20:06.712653 Freq=1200, CH0 RK1
2876 01:20:06.713041
2877 01:20:06.714531 DATLAT Default: 0xc
2878 01:20:06.714993 0, 0xFFFF, sum = 0
2879 01:20:06.717909 1, 0xFFFF, sum = 0
2880 01:20:06.718531 2, 0xFFFF, sum = 0
2881 01:20:06.721538 3, 0xFFFF, sum = 0
2882 01:20:06.722167 4, 0xFFFF, sum = 0
2883 01:20:06.724638 5, 0xFFFF, sum = 0
2884 01:20:06.727930 6, 0xFFFF, sum = 0
2885 01:20:06.728504 7, 0xFFFF, sum = 0
2886 01:20:06.731099 8, 0xFFFF, sum = 0
2887 01:20:06.731571 9, 0xFFFF, sum = 0
2888 01:20:06.734343 10, 0xFFFF, sum = 0
2889 01:20:06.734828 11, 0x0, sum = 1
2890 01:20:06.737732 12, 0x0, sum = 2
2891 01:20:06.738352 13, 0x0, sum = 3
2892 01:20:06.741046 14, 0x0, sum = 4
2893 01:20:06.741624 best_step = 12
2894 01:20:06.741996
2895 01:20:06.742408 ==
2896 01:20:06.744549 Dram Type= 6, Freq= 0, CH_0, rank 1
2897 01:20:06.747840 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2898 01:20:06.748305 ==
2899 01:20:06.751198 RX Vref Scan: 0
2900 01:20:06.751659
2901 01:20:06.754166 RX Vref 0 -> 0, step: 1
2902 01:20:06.754632
2903 01:20:06.755002 RX Delay -21 -> 252, step: 4
2904 01:20:06.761893 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2905 01:20:06.765372 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2906 01:20:06.768543 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2907 01:20:06.771512 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2908 01:20:06.775356 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2909 01:20:06.782008 iDelay=195, Bit 5, Center 108 (39 ~ 178) 140
2910 01:20:06.785068 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2911 01:20:06.788125 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
2912 01:20:06.791295 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
2913 01:20:06.794955 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2914 01:20:06.801841 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2915 01:20:06.805017 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2916 01:20:06.808041 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
2917 01:20:06.811557 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2918 01:20:06.818200 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
2919 01:20:06.821623 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2920 01:20:06.822237 ==
2921 01:20:06.824743 Dram Type= 6, Freq= 0, CH_0, rank 1
2922 01:20:06.828063 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2923 01:20:06.828631 ==
2924 01:20:06.829167 DQS Delay:
2925 01:20:06.831142 DQS0 = 0, DQS1 = 0
2926 01:20:06.831603 DQM Delay:
2927 01:20:06.834847 DQM0 = 114, DQM1 = 105
2928 01:20:06.835410 DQ Delay:
2929 01:20:06.837694 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2930 01:20:06.841114 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =122
2931 01:20:06.845089 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2932 01:20:06.847884 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2933 01:20:06.848417
2934 01:20:06.850922
2935 01:20:06.857994 [DQSOSCAuto] RK1, (LSB)MR18= 0xd0d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2936 01:20:06.861622 CH0 RK1: MR19=404, MR18=D0D
2937 01:20:06.864771 CH0_RK1: MR19=0x404, MR18=0xD0D, DQSOSC=405, MR23=63, INC=39, DEC=26
2938 01:20:06.867980 [RxdqsGatingPostProcess] freq 1200
2939 01:20:06.874176 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2940 01:20:06.877758 Pre-setting of DQS Precalculation
2941 01:20:06.881339 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2942 01:20:06.884695 ==
2943 01:20:06.887498 Dram Type= 6, Freq= 0, CH_1, rank 0
2944 01:20:06.891539 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2945 01:20:06.892015 ==
2946 01:20:06.894560 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2947 01:20:06.900647 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2948 01:20:06.910191 [CA 0] Center 37 (7~68) winsize 62
2949 01:20:06.913405 [CA 1] Center 37 (7~68) winsize 62
2950 01:20:06.916709 [CA 2] Center 34 (4~65) winsize 62
2951 01:20:06.920352 [CA 3] Center 33 (3~64) winsize 62
2952 01:20:06.923331 [CA 4] Center 32 (2~63) winsize 62
2953 01:20:06.926740 [CA 5] Center 32 (2~63) winsize 62
2954 01:20:06.927312
2955 01:20:06.930336 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2956 01:20:06.930907
2957 01:20:06.933808 [CATrainingPosCal] consider 1 rank data
2958 01:20:06.936561 u2DelayCellTimex100 = 270/100 ps
2959 01:20:06.939669 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2960 01:20:06.943565 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2961 01:20:06.950163 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2962 01:20:06.953194 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2963 01:20:06.956512 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2964 01:20:06.959843 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2965 01:20:06.960415
2966 01:20:06.963417 CA PerBit enable=1, Macro0, CA PI delay=32
2967 01:20:06.963994
2968 01:20:06.966575 [CBTSetCACLKResult] CA Dly = 32
2969 01:20:06.967045 CS Dly: 6 (0~37)
2970 01:20:06.969929 ==
2971 01:20:06.970559 Dram Type= 6, Freq= 0, CH_1, rank 1
2972 01:20:06.976353 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2973 01:20:06.976931 ==
2974 01:20:06.979772 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2975 01:20:06.986286 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2976 01:20:06.995329 [CA 0] Center 37 (7~68) winsize 62
2977 01:20:06.998690 [CA 1] Center 37 (7~68) winsize 62
2978 01:20:07.002148 [CA 2] Center 33 (3~64) winsize 62
2979 01:20:07.005234 [CA 3] Center 33 (3~64) winsize 62
2980 01:20:07.008556 [CA 4] Center 32 (2~63) winsize 62
2981 01:20:07.012087 [CA 5] Center 32 (1~63) winsize 63
2982 01:20:07.012662
2983 01:20:07.015319 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2984 01:20:07.015787
2985 01:20:07.018613 [CATrainingPosCal] consider 2 rank data
2986 01:20:07.021786 u2DelayCellTimex100 = 270/100 ps
2987 01:20:07.025149 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2988 01:20:07.028609 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2989 01:20:07.035318 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
2990 01:20:07.038816 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2991 01:20:07.041745 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2992 01:20:07.045703 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2993 01:20:07.046318
2994 01:20:07.048812 CA PerBit enable=1, Macro0, CA PI delay=32
2995 01:20:07.049386
2996 01:20:07.051979 [CBTSetCACLKResult] CA Dly = 32
2997 01:20:07.052603 CS Dly: 6 (0~38)
2998 01:20:07.052996
2999 01:20:07.055181 ----->DramcWriteLeveling(PI) begin...
3000 01:20:07.058506 ==
3001 01:20:07.062167 Dram Type= 6, Freq= 0, CH_1, rank 0
3002 01:20:07.064892 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3003 01:20:07.065365 ==
3004 01:20:07.068233 Write leveling (Byte 0): 21 => 21
3005 01:20:07.072095 Write leveling (Byte 1): 22 => 22
3006 01:20:07.075345 DramcWriteLeveling(PI) end<-----
3007 01:20:07.075919
3008 01:20:07.076294 ==
3009 01:20:07.078662 Dram Type= 6, Freq= 0, CH_1, rank 0
3010 01:20:07.082310 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3011 01:20:07.082885 ==
3012 01:20:07.085971 [Gating] SW mode calibration
3013 01:20:07.092050 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3014 01:20:07.095013 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3015 01:20:07.102283 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3016 01:20:07.105529 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3017 01:20:07.108536 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3018 01:20:07.115119 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
3019 01:20:07.118146 0 11 16 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (1 0)
3020 01:20:07.121659 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3021 01:20:07.128381 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3022 01:20:07.131506 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3023 01:20:07.134836 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3024 01:20:07.141731 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3025 01:20:07.144921 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3026 01:20:07.148110 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3027 01:20:07.154996 0 12 16 | B1->B0 | 3333 4545 | 0 0 | (0 0) (0 0)
3028 01:20:07.158191 0 12 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3029 01:20:07.161493 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3030 01:20:07.168373 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3031 01:20:07.171488 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3032 01:20:07.175016 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3033 01:20:07.181634 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3034 01:20:07.184762 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3035 01:20:07.187935 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3036 01:20:07.194617 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3037 01:20:07.197815 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3038 01:20:07.201496 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3039 01:20:07.208486 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3040 01:20:07.211368 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3041 01:20:07.214736 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3042 01:20:07.221498 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3043 01:20:07.225021 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3044 01:20:07.228201 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3045 01:20:07.231141 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3046 01:20:07.237961 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3047 01:20:07.241434 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3048 01:20:07.244579 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3049 01:20:07.251488 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3050 01:20:07.254915 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3051 01:20:07.258314 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3052 01:20:07.264574 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3053 01:20:07.267631 Total UI for P1: 0, mck2ui 16
3054 01:20:07.270986 best dqsien dly found for B0: ( 0, 15, 16)
3055 01:20:07.274380 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3056 01:20:07.277775 Total UI for P1: 0, mck2ui 16
3057 01:20:07.281304 best dqsien dly found for B1: ( 0, 15, 18)
3058 01:20:07.284793 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3059 01:20:07.287945 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3060 01:20:07.288418
3061 01:20:07.291022 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3062 01:20:07.295248 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3063 01:20:07.297750 [Gating] SW calibration Done
3064 01:20:07.298269 ==
3065 01:20:07.301365 Dram Type= 6, Freq= 0, CH_1, rank 0
3066 01:20:07.304403 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3067 01:20:07.308076 ==
3068 01:20:07.308646 RX Vref Scan: 0
3069 01:20:07.309023
3070 01:20:07.311307 RX Vref 0 -> 0, step: 1
3071 01:20:07.311889
3072 01:20:07.314389 RX Delay -40 -> 252, step: 8
3073 01:20:07.317992 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3074 01:20:07.321416 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3075 01:20:07.324507 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3076 01:20:07.328100 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3077 01:20:07.334610 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3078 01:20:07.337934 iDelay=208, Bit 5, Center 123 (40 ~ 207) 168
3079 01:20:07.341163 iDelay=208, Bit 6, Center 119 (40 ~ 199) 160
3080 01:20:07.344946 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3081 01:20:07.348375 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3082 01:20:07.354498 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3083 01:20:07.357960 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3084 01:20:07.361115 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3085 01:20:07.364612 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3086 01:20:07.367569 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3087 01:20:07.374441 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3088 01:20:07.377584 iDelay=208, Bit 15, Center 115 (40 ~ 191) 152
3089 01:20:07.378095 ==
3090 01:20:07.380967 Dram Type= 6, Freq= 0, CH_1, rank 0
3091 01:20:07.384611 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3092 01:20:07.385189 ==
3093 01:20:07.387555 DQS Delay:
3094 01:20:07.388016 DQS0 = 0, DQS1 = 0
3095 01:20:07.388389 DQM Delay:
3096 01:20:07.391036 DQM0 = 115, DQM1 = 107
3097 01:20:07.391502 DQ Delay:
3098 01:20:07.394222 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3099 01:20:07.398122 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =115
3100 01:20:07.401285 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =103
3101 01:20:07.407636 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3102 01:20:07.408204
3103 01:20:07.408576
3104 01:20:07.408918 ==
3105 01:20:07.410885 Dram Type= 6, Freq= 0, CH_1, rank 0
3106 01:20:07.414571 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3107 01:20:07.415139 ==
3108 01:20:07.415575
3109 01:20:07.415930
3110 01:20:07.417263 TX Vref Scan disable
3111 01:20:07.417723 == TX Byte 0 ==
3112 01:20:07.424721 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3113 01:20:07.427811 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3114 01:20:07.428388 == TX Byte 1 ==
3115 01:20:07.434111 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3116 01:20:07.437441 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3117 01:20:07.438005 ==
3118 01:20:07.440513 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 01:20:07.444138 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3120 01:20:07.444710 ==
3121 01:20:07.456640 TX Vref=22, minBit 9, minWin=25, winSum=412
3122 01:20:07.459601 TX Vref=24, minBit 3, minWin=25, winSum=416
3123 01:20:07.463128 TX Vref=26, minBit 9, minWin=25, winSum=424
3124 01:20:07.466458 TX Vref=28, minBit 0, minWin=26, winSum=427
3125 01:20:07.469716 TX Vref=30, minBit 9, minWin=25, winSum=426
3126 01:20:07.476804 TX Vref=32, minBit 9, minWin=26, winSum=431
3127 01:20:07.479877 [TxChooseVref] Worse bit 9, Min win 26, Win sum 431, Final Vref 32
3128 01:20:07.480448
3129 01:20:07.483260 Final TX Range 1 Vref 32
3130 01:20:07.483829
3131 01:20:07.484201 ==
3132 01:20:07.486685 Dram Type= 6, Freq= 0, CH_1, rank 0
3133 01:20:07.489801 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3134 01:20:07.490309 ==
3135 01:20:07.490694
3136 01:20:07.493078
3137 01:20:07.493550 TX Vref Scan disable
3138 01:20:07.496207 == TX Byte 0 ==
3139 01:20:07.499800 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3140 01:20:07.502949 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3141 01:20:07.506396 == TX Byte 1 ==
3142 01:20:07.509719 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3143 01:20:07.513126 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3144 01:20:07.513701
3145 01:20:07.516410 [DATLAT]
3146 01:20:07.516980 Freq=1200, CH1 RK0
3147 01:20:07.517359
3148 01:20:07.519755 DATLAT Default: 0xd
3149 01:20:07.520343 0, 0xFFFF, sum = 0
3150 01:20:07.523017 1, 0xFFFF, sum = 0
3151 01:20:07.523595 2, 0xFFFF, sum = 0
3152 01:20:07.526517 3, 0xFFFF, sum = 0
3153 01:20:07.527095 4, 0xFFFF, sum = 0
3154 01:20:07.529854 5, 0xFFFF, sum = 0
3155 01:20:07.530474 6, 0xFFFF, sum = 0
3156 01:20:07.533064 7, 0xFFFF, sum = 0
3157 01:20:07.535987 8, 0xFFFF, sum = 0
3158 01:20:07.536463 9, 0xFFFF, sum = 0
3159 01:20:07.539310 10, 0xFFFF, sum = 0
3160 01:20:07.539783 11, 0x0, sum = 1
3161 01:20:07.543237 12, 0x0, sum = 2
3162 01:20:07.543816 13, 0x0, sum = 3
3163 01:20:07.544199 14, 0x0, sum = 4
3164 01:20:07.546324 best_step = 12
3165 01:20:07.546789
3166 01:20:07.547160 ==
3167 01:20:07.549708 Dram Type= 6, Freq= 0, CH_1, rank 0
3168 01:20:07.552751 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3169 01:20:07.553242 ==
3170 01:20:07.556274 RX Vref Scan: 1
3171 01:20:07.556846
3172 01:20:07.559308 Set Vref Range= 32 -> 127
3173 01:20:07.559777
3174 01:20:07.560151 RX Vref 32 -> 127, step: 1
3175 01:20:07.560502
3176 01:20:07.562774 RX Delay -29 -> 252, step: 4
3177 01:20:07.563242
3178 01:20:07.566211 Set Vref, RX VrefLevel [Byte0]: 32
3179 01:20:07.569471 [Byte1]: 32
3180 01:20:07.573023
3181 01:20:07.573623 Set Vref, RX VrefLevel [Byte0]: 33
3182 01:20:07.576108 [Byte1]: 33
3183 01:20:07.580908
3184 01:20:07.581494 Set Vref, RX VrefLevel [Byte0]: 34
3185 01:20:07.584188 [Byte1]: 34
3186 01:20:07.588883
3187 01:20:07.589350 Set Vref, RX VrefLevel [Byte0]: 35
3188 01:20:07.592211 [Byte1]: 35
3189 01:20:07.597142
3190 01:20:07.597779 Set Vref, RX VrefLevel [Byte0]: 36
3191 01:20:07.600009 [Byte1]: 36
3192 01:20:07.604794
3193 01:20:07.605262 Set Vref, RX VrefLevel [Byte0]: 37
3194 01:20:07.607944 [Byte1]: 37
3195 01:20:07.612611
3196 01:20:07.613076 Set Vref, RX VrefLevel [Byte0]: 38
3197 01:20:07.616275 [Byte1]: 38
3198 01:20:07.620750
3199 01:20:07.621323 Set Vref, RX VrefLevel [Byte0]: 39
3200 01:20:07.623827 [Byte1]: 39
3201 01:20:07.628412
3202 01:20:07.628879 Set Vref, RX VrefLevel [Byte0]: 40
3203 01:20:07.631858 [Byte1]: 40
3204 01:20:07.636607
3205 01:20:07.637220 Set Vref, RX VrefLevel [Byte0]: 41
3206 01:20:07.640061 [Byte1]: 41
3207 01:20:07.644344
3208 01:20:07.644806 Set Vref, RX VrefLevel [Byte0]: 42
3209 01:20:07.647958 [Byte1]: 42
3210 01:20:07.652342
3211 01:20:07.652808 Set Vref, RX VrefLevel [Byte0]: 43
3212 01:20:07.655680 [Byte1]: 43
3213 01:20:07.660231
3214 01:20:07.661121 Set Vref, RX VrefLevel [Byte0]: 44
3215 01:20:07.663418 [Byte1]: 44
3216 01:20:07.668164
3217 01:20:07.669001 Set Vref, RX VrefLevel [Byte0]: 45
3218 01:20:07.672033 [Byte1]: 45
3219 01:20:07.676210
3220 01:20:07.677030 Set Vref, RX VrefLevel [Byte0]: 46
3221 01:20:07.679740 [Byte1]: 46
3222 01:20:07.684360
3223 01:20:07.684699 Set Vref, RX VrefLevel [Byte0]: 47
3224 01:20:07.687574 [Byte1]: 47
3225 01:20:07.692107
3226 01:20:07.692739 Set Vref, RX VrefLevel [Byte0]: 48
3227 01:20:07.695486 [Byte1]: 48
3228 01:20:07.700495
3229 01:20:07.700969 Set Vref, RX VrefLevel [Byte0]: 49
3230 01:20:07.703596 [Byte1]: 49
3231 01:20:07.707972
3232 01:20:07.708441 Set Vref, RX VrefLevel [Byte0]: 50
3233 01:20:07.711245 [Byte1]: 50
3234 01:20:07.716080
3235 01:20:07.716547 Set Vref, RX VrefLevel [Byte0]: 51
3236 01:20:07.719197 [Byte1]: 51
3237 01:20:07.723908
3238 01:20:07.724329 Set Vref, RX VrefLevel [Byte0]: 52
3239 01:20:07.727275 [Byte1]: 52
3240 01:20:07.731890
3241 01:20:07.731972 Set Vref, RX VrefLevel [Byte0]: 53
3242 01:20:07.734905 [Byte1]: 53
3243 01:20:07.739795
3244 01:20:07.739876 Set Vref, RX VrefLevel [Byte0]: 54
3245 01:20:07.742730 [Byte1]: 54
3246 01:20:07.747313
3247 01:20:07.747436 Set Vref, RX VrefLevel [Byte0]: 55
3248 01:20:07.750734 [Byte1]: 55
3249 01:20:07.755609
3250 01:20:07.755691 Set Vref, RX VrefLevel [Byte0]: 56
3251 01:20:07.759114 [Byte1]: 56
3252 01:20:07.763357
3253 01:20:07.763451 Set Vref, RX VrefLevel [Byte0]: 57
3254 01:20:07.767155 [Byte1]: 57
3255 01:20:07.771902
3256 01:20:07.772504 Set Vref, RX VrefLevel [Byte0]: 58
3257 01:20:07.775248 [Byte1]: 58
3258 01:20:07.779711
3259 01:20:07.780182 Set Vref, RX VrefLevel [Byte0]: 59
3260 01:20:07.782502 [Byte1]: 59
3261 01:20:07.788237
3262 01:20:07.788857 Set Vref, RX VrefLevel [Byte0]: 60
3263 01:20:07.791402 [Byte1]: 60
3264 01:20:07.795563
3265 01:20:07.796033 Set Vref, RX VrefLevel [Byte0]: 61
3266 01:20:07.798883 [Byte1]: 61
3267 01:20:07.803070
3268 01:20:07.803151 Set Vref, RX VrefLevel [Byte0]: 62
3269 01:20:07.806594 [Byte1]: 62
3270 01:20:07.811431
3271 01:20:07.811528 Set Vref, RX VrefLevel [Byte0]: 63
3272 01:20:07.814421 [Byte1]: 63
3273 01:20:07.819093
3274 01:20:07.819277 Set Vref, RX VrefLevel [Byte0]: 64
3275 01:20:07.822808 [Byte1]: 64
3276 01:20:07.827344
3277 01:20:07.827550 Set Vref, RX VrefLevel [Byte0]: 65
3278 01:20:07.830535 [Byte1]: 65
3279 01:20:07.835403
3280 01:20:07.835628 Set Vref, RX VrefLevel [Byte0]: 66
3281 01:20:07.838393 [Byte1]: 66
3282 01:20:07.843327
3283 01:20:07.843597 Final RX Vref Byte 0 = 54 to rank0
3284 01:20:07.847205 Final RX Vref Byte 1 = 50 to rank0
3285 01:20:07.849995 Final RX Vref Byte 0 = 54 to rank1
3286 01:20:07.853394 Final RX Vref Byte 1 = 50 to rank1==
3287 01:20:07.857364 Dram Type= 6, Freq= 0, CH_1, rank 0
3288 01:20:07.864204 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3289 01:20:07.864748 ==
3290 01:20:07.865093 DQS Delay:
3291 01:20:07.865413 DQS0 = 0, DQS1 = 0
3292 01:20:07.866530 DQM Delay:
3293 01:20:07.866951 DQM0 = 115, DQM1 = 106
3294 01:20:07.870510 DQ Delay:
3295 01:20:07.873751 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3296 01:20:07.876758 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3297 01:20:07.880251 DQ8 =86, DQ9 =94, DQ10 =110, DQ11 =96
3298 01:20:07.883668 DQ12 =114, DQ13 =116, DQ14 =116, DQ15 =116
3299 01:20:07.884243
3300 01:20:07.884618
3301 01:20:07.889850 [DQSOSCAuto] RK0, (LSB)MR18= 0x1919, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3302 01:20:07.893241 CH1 RK0: MR19=404, MR18=1919
3303 01:20:07.900507 CH1_RK0: MR19=0x404, MR18=0x1919, DQSOSC=400, MR23=63, INC=40, DEC=27
3304 01:20:07.901075
3305 01:20:07.903358 ----->DramcWriteLeveling(PI) begin...
3306 01:20:07.903852 ==
3307 01:20:07.906536 Dram Type= 6, Freq= 0, CH_1, rank 1
3308 01:20:07.910169 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3309 01:20:07.910752 ==
3310 01:20:07.913165 Write leveling (Byte 0): 21 => 21
3311 01:20:07.917149 Write leveling (Byte 1): 21 => 21
3312 01:20:07.920072 DramcWriteLeveling(PI) end<-----
3313 01:20:07.920539
3314 01:20:07.920913 ==
3315 01:20:07.923585 Dram Type= 6, Freq= 0, CH_1, rank 1
3316 01:20:07.929983 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3317 01:20:07.930563 ==
3318 01:20:07.930981 [Gating] SW mode calibration
3319 01:20:07.940284 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3320 01:20:07.943956 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3321 01:20:07.946321 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3322 01:20:07.953441 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3323 01:20:07.956945 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3324 01:20:07.960013 0 11 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
3325 01:20:07.966775 0 11 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
3326 01:20:07.970270 0 11 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3327 01:20:07.973183 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3328 01:20:07.980634 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3329 01:20:07.983082 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3330 01:20:07.986421 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3331 01:20:07.994138 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3332 01:20:07.996392 0 12 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
3333 01:20:07.999878 0 12 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
3334 01:20:08.006753 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3335 01:20:08.010080 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3336 01:20:08.013040 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3337 01:20:08.020117 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3338 01:20:08.022943 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3339 01:20:08.026306 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3340 01:20:08.032892 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3341 01:20:08.036622 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3342 01:20:08.039600 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3343 01:20:08.046308 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3344 01:20:08.049345 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3345 01:20:08.052997 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3346 01:20:08.059363 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3347 01:20:08.062914 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3348 01:20:08.066250 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3349 01:20:08.073019 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3350 01:20:08.076277 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3351 01:20:08.079784 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3352 01:20:08.082647 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3353 01:20:08.089805 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3354 01:20:08.092889 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3355 01:20:08.096009 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3356 01:20:08.102624 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3357 01:20:08.106097 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3358 01:20:08.109492 Total UI for P1: 0, mck2ui 16
3359 01:20:08.112502 best dqsien dly found for B0: ( 0, 15, 12)
3360 01:20:08.115914 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3361 01:20:08.119206 Total UI for P1: 0, mck2ui 16
3362 01:20:08.122708 best dqsien dly found for B1: ( 0, 15, 14)
3363 01:20:08.126127 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3364 01:20:08.129160 best DQS1 dly(MCK, UI, PI) = (0, 15, 14)
3365 01:20:08.132664
3366 01:20:08.136021 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3367 01:20:08.139221 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 14)
3368 01:20:08.142898 [Gating] SW calibration Done
3369 01:20:08.143465 ==
3370 01:20:08.146260 Dram Type= 6, Freq= 0, CH_1, rank 1
3371 01:20:08.149623 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3372 01:20:08.150241 ==
3373 01:20:08.150624 RX Vref Scan: 0
3374 01:20:08.151057
3375 01:20:08.152721 RX Vref 0 -> 0, step: 1
3376 01:20:08.153276
3377 01:20:08.156284 RX Delay -40 -> 252, step: 8
3378 01:20:08.159208 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3379 01:20:08.162846 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3380 01:20:08.169404 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3381 01:20:08.172474 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3382 01:20:08.175949 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3383 01:20:08.179025 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3384 01:20:08.182563 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3385 01:20:08.188965 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3386 01:20:08.192540 iDelay=208, Bit 8, Center 91 (16 ~ 167) 152
3387 01:20:08.195671 iDelay=208, Bit 9, Center 91 (16 ~ 167) 152
3388 01:20:08.199313 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3389 01:20:08.202599 iDelay=208, Bit 11, Center 99 (24 ~ 175) 152
3390 01:20:08.209382 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3391 01:20:08.212753 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3392 01:20:08.215879 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3393 01:20:08.219160 iDelay=208, Bit 15, Center 111 (40 ~ 183) 144
3394 01:20:08.219716 ==
3395 01:20:08.222937 Dram Type= 6, Freq= 0, CH_1, rank 1
3396 01:20:08.226191 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3397 01:20:08.229519 ==
3398 01:20:08.230134 DQS Delay:
3399 01:20:08.230517 DQS0 = 0, DQS1 = 0
3400 01:20:08.232492 DQM Delay:
3401 01:20:08.233054 DQM0 = 117, DQM1 = 106
3402 01:20:08.235890 DQ Delay:
3403 01:20:08.239104 DQ0 =119, DQ1 =115, DQ2 =111, DQ3 =115
3404 01:20:08.242599 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3405 01:20:08.245802 DQ8 =91, DQ9 =91, DQ10 =111, DQ11 =99
3406 01:20:08.249682 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3407 01:20:08.250287
3408 01:20:08.250667
3409 01:20:08.251016 ==
3410 01:20:08.252333 Dram Type= 6, Freq= 0, CH_1, rank 1
3411 01:20:08.255613 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3412 01:20:08.256081 ==
3413 01:20:08.256451
3414 01:20:08.256791
3415 01:20:08.258957 TX Vref Scan disable
3416 01:20:08.262614 == TX Byte 0 ==
3417 01:20:08.266184 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3418 01:20:08.268772 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3419 01:20:08.272222 == TX Byte 1 ==
3420 01:20:08.276109 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3421 01:20:08.278836 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3422 01:20:08.279308 ==
3423 01:20:08.282464 Dram Type= 6, Freq= 0, CH_1, rank 1
3424 01:20:08.288549 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3425 01:20:08.289109 ==
3426 01:20:08.298779 TX Vref=22, minBit 0, minWin=25, winSum=421
3427 01:20:08.302111 TX Vref=24, minBit 9, minWin=25, winSum=422
3428 01:20:08.305649 TX Vref=26, minBit 8, minWin=26, winSum=430
3429 01:20:08.309165 TX Vref=28, minBit 8, minWin=26, winSum=433
3430 01:20:08.312491 TX Vref=30, minBit 3, minWin=26, winSum=431
3431 01:20:08.315389 TX Vref=32, minBit 0, minWin=26, winSum=429
3432 01:20:08.322301 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 28
3433 01:20:08.322880
3434 01:20:08.325816 Final TX Range 1 Vref 28
3435 01:20:08.326435
3436 01:20:08.326808 ==
3437 01:20:08.329172 Dram Type= 6, Freq= 0, CH_1, rank 1
3438 01:20:08.332529 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3439 01:20:08.333105 ==
3440 01:20:08.335690
3441 01:20:08.336258
3442 01:20:08.336629 TX Vref Scan disable
3443 01:20:08.338626 == TX Byte 0 ==
3444 01:20:08.342102 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3445 01:20:08.345412 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3446 01:20:08.349113 == TX Byte 1 ==
3447 01:20:08.352184 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3448 01:20:08.355246 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3449 01:20:08.355729
3450 01:20:08.359157 [DATLAT]
3451 01:20:08.359724 Freq=1200, CH1 RK1
3452 01:20:08.360104
3453 01:20:08.362314 DATLAT Default: 0xc
3454 01:20:08.362881 0, 0xFFFF, sum = 0
3455 01:20:08.365921 1, 0xFFFF, sum = 0
3456 01:20:08.366546 2, 0xFFFF, sum = 0
3457 01:20:08.369048 3, 0xFFFF, sum = 0
3458 01:20:08.369623 4, 0xFFFF, sum = 0
3459 01:20:08.372562 5, 0xFFFF, sum = 0
3460 01:20:08.373131 6, 0xFFFF, sum = 0
3461 01:20:08.375770 7, 0xFFFF, sum = 0
3462 01:20:08.379265 8, 0xFFFF, sum = 0
3463 01:20:08.379834 9, 0xFFFF, sum = 0
3464 01:20:08.382538 10, 0xFFFF, sum = 0
3465 01:20:08.383011 11, 0x0, sum = 1
3466 01:20:08.385468 12, 0x0, sum = 2
3467 01:20:08.386089 13, 0x0, sum = 3
3468 01:20:08.386488 14, 0x0, sum = 4
3469 01:20:08.388869 best_step = 12
3470 01:20:08.389329
3471 01:20:08.389696 ==
3472 01:20:08.392065 Dram Type= 6, Freq= 0, CH_1, rank 1
3473 01:20:08.395158 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3474 01:20:08.395622 ==
3475 01:20:08.398454 RX Vref Scan: 0
3476 01:20:08.398916
3477 01:20:08.399280 RX Vref 0 -> 0, step: 1
3478 01:20:08.401818
3479 01:20:08.402314 RX Delay -29 -> 252, step: 4
3480 01:20:08.409086 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3481 01:20:08.412452 iDelay=199, Bit 1, Center 112 (43 ~ 182) 140
3482 01:20:08.415641 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3483 01:20:08.418970 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3484 01:20:08.422692 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3485 01:20:08.429111 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3486 01:20:08.432623 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3487 01:20:08.435775 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3488 01:20:08.438948 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3489 01:20:08.442390 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3490 01:20:08.449163 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3491 01:20:08.452346 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3492 01:20:08.455486 iDelay=199, Bit 12, Center 114 (43 ~ 186) 144
3493 01:20:08.458991 iDelay=199, Bit 13, Center 110 (43 ~ 178) 136
3494 01:20:08.462559 iDelay=199, Bit 14, Center 116 (47 ~ 186) 140
3495 01:20:08.469288 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3496 01:20:08.469859 ==
3497 01:20:08.472755 Dram Type= 6, Freq= 0, CH_1, rank 1
3498 01:20:08.475605 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3499 01:20:08.476078 ==
3500 01:20:08.476448 DQS Delay:
3501 01:20:08.478747 DQS0 = 0, DQS1 = 0
3502 01:20:08.479361 DQM Delay:
3503 01:20:08.482064 DQM0 = 115, DQM1 = 104
3504 01:20:08.482534 DQ Delay:
3505 01:20:08.485610 DQ0 =116, DQ1 =112, DQ2 =108, DQ3 =112
3506 01:20:08.488719 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3507 01:20:08.492394 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3508 01:20:08.495398 DQ12 =114, DQ13 =110, DQ14 =116, DQ15 =110
3509 01:20:08.495869
3510 01:20:08.496238
3511 01:20:08.505513 [DQSOSCAuto] RK1, (LSB)MR18= 0x606, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
3512 01:20:08.509194 CH1 RK1: MR19=404, MR18=606
3513 01:20:08.512613 CH1_RK1: MR19=0x404, MR18=0x606, DQSOSC=407, MR23=63, INC=39, DEC=26
3514 01:20:08.515663 [RxdqsGatingPostProcess] freq 1200
3515 01:20:08.522334 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3516 01:20:08.525556 Pre-setting of DQS Precalculation
3517 01:20:08.528803 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3518 01:20:08.538557 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3519 01:20:08.545401 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3520 01:20:08.545976
3521 01:20:08.546414
3522 01:20:08.548876 [Calibration Summary] 2400 Mbps
3523 01:20:08.549448 CH 0, Rank 0
3524 01:20:08.551708 SW Impedance : PASS
3525 01:20:08.552180 DUTY Scan : NO K
3526 01:20:08.555342 ZQ Calibration : PASS
3527 01:20:08.558785 Jitter Meter : NO K
3528 01:20:08.559255 CBT Training : PASS
3529 01:20:08.562169 Write leveling : PASS
3530 01:20:08.565395 RX DQS gating : PASS
3531 01:20:08.565954 RX DQ/DQS(RDDQC) : PASS
3532 01:20:08.568823 TX DQ/DQS : PASS
3533 01:20:08.572282 RX DATLAT : PASS
3534 01:20:08.572844 RX DQ/DQS(Engine): PASS
3535 01:20:08.575103 TX OE : NO K
3536 01:20:08.575586 All Pass.
3537 01:20:08.575958
3538 01:20:08.578371 CH 0, Rank 1
3539 01:20:08.578843 SW Impedance : PASS
3540 01:20:08.582211 DUTY Scan : NO K
3541 01:20:08.585240 ZQ Calibration : PASS
3542 01:20:08.585803 Jitter Meter : NO K
3543 01:20:08.588615 CBT Training : PASS
3544 01:20:08.589177 Write leveling : PASS
3545 01:20:08.591886 RX DQS gating : PASS
3546 01:20:08.595358 RX DQ/DQS(RDDQC) : PASS
3547 01:20:08.595826 TX DQ/DQS : PASS
3548 01:20:08.598971 RX DATLAT : PASS
3549 01:20:08.601896 RX DQ/DQS(Engine): PASS
3550 01:20:08.602457 TX OE : NO K
3551 01:20:08.605210 All Pass.
3552 01:20:08.605685
3553 01:20:08.606271 CH 1, Rank 0
3554 01:20:08.608868 SW Impedance : PASS
3555 01:20:08.609351 DUTY Scan : NO K
3556 01:20:08.612036 ZQ Calibration : PASS
3557 01:20:08.615299 Jitter Meter : NO K
3558 01:20:08.615770 CBT Training : PASS
3559 01:20:08.618382 Write leveling : PASS
3560 01:20:08.622286 RX DQS gating : PASS
3561 01:20:08.622846 RX DQ/DQS(RDDQC) : PASS
3562 01:20:08.625536 TX DQ/DQS : PASS
3563 01:20:08.628824 RX DATLAT : PASS
3564 01:20:08.629385 RX DQ/DQS(Engine): PASS
3565 01:20:08.632287 TX OE : NO K
3566 01:20:08.632851 All Pass.
3567 01:20:08.633227
3568 01:20:08.633576 CH 1, Rank 1
3569 01:20:08.635060 SW Impedance : PASS
3570 01:20:08.638678 DUTY Scan : NO K
3571 01:20:08.639264 ZQ Calibration : PASS
3572 01:20:08.642400 Jitter Meter : NO K
3573 01:20:08.645549 CBT Training : PASS
3574 01:20:08.646165 Write leveling : PASS
3575 01:20:08.648638 RX DQS gating : PASS
3576 01:20:08.652091 RX DQ/DQS(RDDQC) : PASS
3577 01:20:08.652560 TX DQ/DQS : PASS
3578 01:20:08.655132 RX DATLAT : PASS
3579 01:20:08.658595 RX DQ/DQS(Engine): PASS
3580 01:20:08.659158 TX OE : NO K
3581 01:20:08.661834 All Pass.
3582 01:20:08.662380
3583 01:20:08.662759 DramC Write-DBI off
3584 01:20:08.665552 PER_BANK_REFRESH: Hybrid Mode
3585 01:20:08.666167 TX_TRACKING: ON
3586 01:20:08.675215 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3587 01:20:08.678567 [FAST_K] Save calibration result to emmc
3588 01:20:08.681840 dramc_set_vcore_voltage set vcore to 650000
3589 01:20:08.685209 Read voltage for 600, 5
3590 01:20:08.685769 Vio18 = 0
3591 01:20:08.688812 Vcore = 650000
3592 01:20:08.689373 Vdram = 0
3593 01:20:08.689741 Vddq = 0
3594 01:20:08.690129 Vmddr = 0
3595 01:20:08.695726 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3596 01:20:08.702204 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3597 01:20:08.702765 MEM_TYPE=3, freq_sel=19
3598 01:20:08.705236 sv_algorithm_assistance_LP4_1600
3599 01:20:08.708602 ============ PULL DRAM RESETB DOWN ============
3600 01:20:08.715039 ========== PULL DRAM RESETB DOWN end =========
3601 01:20:08.718836 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3602 01:20:08.721674 ===================================
3603 01:20:08.725314 LPDDR4 DRAM CONFIGURATION
3604 01:20:08.728542 ===================================
3605 01:20:08.729004 EX_ROW_EN[0] = 0x0
3606 01:20:08.731579 EX_ROW_EN[1] = 0x0
3607 01:20:08.732042 LP4Y_EN = 0x0
3608 01:20:08.735211 WORK_FSP = 0x0
3609 01:20:08.735719 WL = 0x2
3610 01:20:08.738449 RL = 0x2
3611 01:20:08.738867 BL = 0x2
3612 01:20:08.741827 RPST = 0x0
3613 01:20:08.742421 RD_PRE = 0x0
3614 01:20:08.745517 WR_PRE = 0x1
3615 01:20:08.748616 WR_PST = 0x0
3616 01:20:08.749256 DBI_WR = 0x0
3617 01:20:08.751744 DBI_RD = 0x0
3618 01:20:08.752172 OTF = 0x1
3619 01:20:08.755040 ===================================
3620 01:20:08.758366 ===================================
3621 01:20:08.758785 ANA top config
3622 01:20:08.761856 ===================================
3623 01:20:08.765087 DLL_ASYNC_EN = 0
3624 01:20:08.768235 ALL_SLAVE_EN = 1
3625 01:20:08.771584 NEW_RANK_MODE = 1
3626 01:20:08.774862 DLL_IDLE_MODE = 1
3627 01:20:08.775280 LP45_APHY_COMB_EN = 1
3628 01:20:08.778362 TX_ODT_DIS = 1
3629 01:20:08.781528 NEW_8X_MODE = 1
3630 01:20:08.784991 ===================================
3631 01:20:08.788038 ===================================
3632 01:20:08.791467 data_rate = 1200
3633 01:20:08.795139 CKR = 1
3634 01:20:08.798460 DQ_P2S_RATIO = 8
3635 01:20:08.801736 ===================================
3636 01:20:08.802317 CA_P2S_RATIO = 8
3637 01:20:08.804939 DQ_CA_OPEN = 0
3638 01:20:08.807980 DQ_SEMI_OPEN = 0
3639 01:20:08.811472 CA_SEMI_OPEN = 0
3640 01:20:08.815207 CA_FULL_RATE = 0
3641 01:20:08.817926 DQ_CKDIV4_EN = 1
3642 01:20:08.818393 CA_CKDIV4_EN = 1
3643 01:20:08.820988 CA_PREDIV_EN = 0
3644 01:20:08.824780 PH8_DLY = 0
3645 01:20:08.827806 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3646 01:20:08.831690 DQ_AAMCK_DIV = 4
3647 01:20:08.834490 CA_AAMCK_DIV = 4
3648 01:20:08.834951 CA_ADMCK_DIV = 4
3649 01:20:08.838104 DQ_TRACK_CA_EN = 0
3650 01:20:08.841182 CA_PICK = 600
3651 01:20:08.844569 CA_MCKIO = 600
3652 01:20:08.847727 MCKIO_SEMI = 0
3653 01:20:08.850863 PLL_FREQ = 2288
3654 01:20:08.854577 DQ_UI_PI_RATIO = 32
3655 01:20:08.855194 CA_UI_PI_RATIO = 0
3656 01:20:08.857345 ===================================
3657 01:20:08.860968 ===================================
3658 01:20:08.864314 memory_type:LPDDR4
3659 01:20:08.867463 GP_NUM : 10
3660 01:20:08.868022 SRAM_EN : 1
3661 01:20:08.871125 MD32_EN : 0
3662 01:20:08.874292 ===================================
3663 01:20:08.877577 [ANA_INIT] >>>>>>>>>>>>>>
3664 01:20:08.880654 <<<<<< [CONFIGURE PHASE]: ANA_TX
3665 01:20:08.884123 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3666 01:20:08.887099 ===================================
3667 01:20:08.887576 data_rate = 1200,PCW = 0X5800
3668 01:20:08.890961 ===================================
3669 01:20:08.897215 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3670 01:20:08.900601 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3671 01:20:08.906949 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3672 01:20:08.910046 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3673 01:20:08.913570 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3674 01:20:08.916925 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3675 01:20:08.920116 [ANA_INIT] flow start
3676 01:20:08.923465 [ANA_INIT] PLL >>>>>>>>
3677 01:20:08.924032 [ANA_INIT] PLL <<<<<<<<
3678 01:20:08.926605 [ANA_INIT] MIDPI >>>>>>>>
3679 01:20:08.930362 [ANA_INIT] MIDPI <<<<<<<<
3680 01:20:08.930828 [ANA_INIT] DLL >>>>>>>>
3681 01:20:08.933329 [ANA_INIT] flow end
3682 01:20:08.937003 ============ LP4 DIFF to SE enter ============
3683 01:20:08.943291 ============ LP4 DIFF to SE exit ============
3684 01:20:08.943869 [ANA_INIT] <<<<<<<<<<<<<
3685 01:20:08.946697 [Flow] Enable top DCM control >>>>>
3686 01:20:08.950050 [Flow] Enable top DCM control <<<<<
3687 01:20:08.953196 Enable DLL master slave shuffle
3688 01:20:08.960017 ==============================================================
3689 01:20:08.960596 Gating Mode config
3690 01:20:08.966434 ==============================================================
3691 01:20:08.969775 Config description:
3692 01:20:08.979752 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3693 01:20:08.986163 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3694 01:20:08.989835 SELPH_MODE 0: By rank 1: By Phase
3695 01:20:08.996204 ==============================================================
3696 01:20:08.999265 GAT_TRACK_EN = 1
3697 01:20:08.999980 RX_GATING_MODE = 2
3698 01:20:09.002524 RX_GATING_TRACK_MODE = 2
3699 01:20:09.005860 SELPH_MODE = 1
3700 01:20:09.008951 PICG_EARLY_EN = 1
3701 01:20:09.012698 VALID_LAT_VALUE = 1
3702 01:20:09.018864 ==============================================================
3703 01:20:09.022686 Enter into Gating configuration >>>>
3704 01:20:09.025656 Exit from Gating configuration <<<<
3705 01:20:09.029419 Enter into DVFS_PRE_config >>>>>
3706 01:20:09.038681 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3707 01:20:09.042623 Exit from DVFS_PRE_config <<<<<
3708 01:20:09.045923 Enter into PICG configuration >>>>
3709 01:20:09.048811 Exit from PICG configuration <<<<
3710 01:20:09.052109 [RX_INPUT] configuration >>>>>
3711 01:20:09.055339 [RX_INPUT] configuration <<<<<
3712 01:20:09.058499 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3713 01:20:09.065200 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3714 01:20:09.071694 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3715 01:20:09.078083 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3716 01:20:09.085017 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3717 01:20:09.087916 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3718 01:20:09.094596 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3719 01:20:09.097728 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3720 01:20:09.101078 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3721 01:20:09.104490 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3722 01:20:09.110981 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3723 01:20:09.113999 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3724 01:20:09.117617 ===================================
3725 01:20:09.120912 LPDDR4 DRAM CONFIGURATION
3726 01:20:09.123929 ===================================
3727 01:20:09.124066 EX_ROW_EN[0] = 0x0
3728 01:20:09.127398 EX_ROW_EN[1] = 0x0
3729 01:20:09.127535 LP4Y_EN = 0x0
3730 01:20:09.130664 WORK_FSP = 0x0
3731 01:20:09.130800 WL = 0x2
3732 01:20:09.133860 RL = 0x2
3733 01:20:09.134049 BL = 0x2
3734 01:20:09.137732 RPST = 0x0
3735 01:20:09.140464 RD_PRE = 0x0
3736 01:20:09.140600 WR_PRE = 0x1
3737 01:20:09.144057 WR_PST = 0x0
3738 01:20:09.144191 DBI_WR = 0x0
3739 01:20:09.147686 DBI_RD = 0x0
3740 01:20:09.147836 OTF = 0x1
3741 01:20:09.150331 ===================================
3742 01:20:09.153489 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3743 01:20:09.160497 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3744 01:20:09.163610 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3745 01:20:09.166940 ===================================
3746 01:20:09.170306 LPDDR4 DRAM CONFIGURATION
3747 01:20:09.173261 ===================================
3748 01:20:09.173435 EX_ROW_EN[0] = 0x10
3749 01:20:09.176611 EX_ROW_EN[1] = 0x0
3750 01:20:09.176785 LP4Y_EN = 0x0
3751 01:20:09.180067 WORK_FSP = 0x0
3752 01:20:09.180241 WL = 0x2
3753 01:20:09.183343 RL = 0x2
3754 01:20:09.186597 BL = 0x2
3755 01:20:09.186770 RPST = 0x0
3756 01:20:09.190052 RD_PRE = 0x0
3757 01:20:09.190224 WR_PRE = 0x1
3758 01:20:09.193123 WR_PST = 0x0
3759 01:20:09.193295 DBI_WR = 0x0
3760 01:20:09.196470 DBI_RD = 0x0
3761 01:20:09.196642 OTF = 0x1
3762 01:20:09.199836 ===================================
3763 01:20:09.206602 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3764 01:20:09.210679 nWR fixed to 30
3765 01:20:09.213704 [ModeRegInit_LP4] CH0 RK0
3766 01:20:09.213876 [ModeRegInit_LP4] CH0 RK1
3767 01:20:09.217097 [ModeRegInit_LP4] CH1 RK0
3768 01:20:09.220262 [ModeRegInit_LP4] CH1 RK1
3769 01:20:09.220436 match AC timing 16
3770 01:20:09.227365 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3771 01:20:09.230673 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3772 01:20:09.233710 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3773 01:20:09.240302 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3774 01:20:09.244057 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3775 01:20:09.244233 ==
3776 01:20:09.247135 Dram Type= 6, Freq= 0, CH_0, rank 0
3777 01:20:09.250183 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3778 01:20:09.250363 ==
3779 01:20:09.256801 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3780 01:20:09.263508 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3781 01:20:09.266982 [CA 0] Center 35 (5~66) winsize 62
3782 01:20:09.269948 [CA 1] Center 35 (5~66) winsize 62
3783 01:20:09.274020 [CA 2] Center 34 (4~65) winsize 62
3784 01:20:09.276881 [CA 3] Center 34 (4~65) winsize 62
3785 01:20:09.280166 [CA 4] Center 33 (3~64) winsize 62
3786 01:20:09.283215 [CA 5] Center 33 (3~64) winsize 62
3787 01:20:09.283510
3788 01:20:09.286833 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3789 01:20:09.287207
3790 01:20:09.290088 [CATrainingPosCal] consider 1 rank data
3791 01:20:09.293336 u2DelayCellTimex100 = 270/100 ps
3792 01:20:09.296856 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3793 01:20:09.299911 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3794 01:20:09.303334 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3795 01:20:09.306419 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3796 01:20:09.313306 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3797 01:20:09.316577 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3798 01:20:09.317163
3799 01:20:09.319697 CA PerBit enable=1, Macro0, CA PI delay=33
3800 01:20:09.320254
3801 01:20:09.323276 [CBTSetCACLKResult] CA Dly = 33
3802 01:20:09.323850 CS Dly: 4 (0~35)
3803 01:20:09.324226 ==
3804 01:20:09.326432 Dram Type= 6, Freq= 0, CH_0, rank 1
3805 01:20:09.333226 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3806 01:20:09.333697 ==
3807 01:20:09.336069 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3808 01:20:09.343062 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3809 01:20:09.346120 [CA 0] Center 35 (5~66) winsize 62
3810 01:20:09.349578 [CA 1] Center 35 (5~66) winsize 62
3811 01:20:09.352670 [CA 2] Center 34 (4~65) winsize 62
3812 01:20:09.356050 [CA 3] Center 34 (3~65) winsize 63
3813 01:20:09.359175 [CA 4] Center 33 (3~64) winsize 62
3814 01:20:09.362662 [CA 5] Center 33 (3~64) winsize 62
3815 01:20:09.363203
3816 01:20:09.365844 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3817 01:20:09.366355
3818 01:20:09.369063 [CATrainingPosCal] consider 2 rank data
3819 01:20:09.372662 u2DelayCellTimex100 = 270/100 ps
3820 01:20:09.375851 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3821 01:20:09.382672 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3822 01:20:09.386172 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3823 01:20:09.389040 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3824 01:20:09.392565 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3825 01:20:09.395832 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3826 01:20:09.396421
3827 01:20:09.399164 CA PerBit enable=1, Macro0, CA PI delay=33
3828 01:20:09.399632
3829 01:20:09.402094 [CBTSetCACLKResult] CA Dly = 33
3830 01:20:09.405911 CS Dly: 4 (0~36)
3831 01:20:09.406521
3832 01:20:09.409271 ----->DramcWriteLeveling(PI) begin...
3833 01:20:09.409841 ==
3834 01:20:09.412347 Dram Type= 6, Freq= 0, CH_0, rank 0
3835 01:20:09.415408 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3836 01:20:09.415878 ==
3837 01:20:09.418704 Write leveling (Byte 0): 30 => 30
3838 01:20:09.422420 Write leveling (Byte 1): 30 => 30
3839 01:20:09.425460 DramcWriteLeveling(PI) end<-----
3840 01:20:09.426017
3841 01:20:09.426432 ==
3842 01:20:09.428744 Dram Type= 6, Freq= 0, CH_0, rank 0
3843 01:20:09.432069 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3844 01:20:09.432635 ==
3845 01:20:09.435047 [Gating] SW mode calibration
3846 01:20:09.442374 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3847 01:20:09.448569 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3848 01:20:09.451727 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3849 01:20:09.455270 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3850 01:20:09.462067 0 5 8 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 0)
3851 01:20:09.465044 0 5 12 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
3852 01:20:09.468563 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3853 01:20:09.474897 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3854 01:20:09.478571 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3855 01:20:09.481579 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3856 01:20:09.488144 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3857 01:20:09.491397 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3858 01:20:09.494640 0 6 8 | B1->B0 | 2f2f 3434 | 0 0 | (0 0) (0 0)
3859 01:20:09.501275 0 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3860 01:20:09.505136 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3861 01:20:09.508407 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3862 01:20:09.515005 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3863 01:20:09.518351 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3864 01:20:09.521592 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3865 01:20:09.528052 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3866 01:20:09.531229 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3867 01:20:09.534610 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3868 01:20:09.541309 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3869 01:20:09.544079 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3870 01:20:09.548059 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3871 01:20:09.554367 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3872 01:20:09.557678 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3873 01:20:09.560873 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3874 01:20:09.567628 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3875 01:20:09.570793 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3876 01:20:09.573718 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3877 01:20:09.580705 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3878 01:20:09.584181 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3879 01:20:09.587285 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3880 01:20:09.594135 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3881 01:20:09.597228 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3882 01:20:09.600644 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3883 01:20:09.607451 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3884 01:20:09.608018 Total UI for P1: 0, mck2ui 16
3885 01:20:09.613848 best dqsien dly found for B0: ( 0, 9, 10)
3886 01:20:09.614454 Total UI for P1: 0, mck2ui 16
3887 01:20:09.617157 best dqsien dly found for B1: ( 0, 9, 10)
3888 01:20:09.624267 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
3889 01:20:09.626711 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3890 01:20:09.627172
3891 01:20:09.630257 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
3892 01:20:09.633669 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3893 01:20:09.637083 [Gating] SW calibration Done
3894 01:20:09.637540 ==
3895 01:20:09.640374 Dram Type= 6, Freq= 0, CH_0, rank 0
3896 01:20:09.643322 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3897 01:20:09.643789 ==
3898 01:20:09.646723 RX Vref Scan: 0
3899 01:20:09.647291
3900 01:20:09.647664 RX Vref 0 -> 0, step: 1
3901 01:20:09.648012
3902 01:20:09.649806 RX Delay -230 -> 252, step: 16
3903 01:20:09.656660 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3904 01:20:09.660276 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3905 01:20:09.663688 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3906 01:20:09.666788 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3907 01:20:09.669966 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3908 01:20:09.676866 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3909 01:20:09.679794 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3910 01:20:09.683136 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3911 01:20:09.686470 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3912 01:20:09.692744 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3913 01:20:09.696449 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3914 01:20:09.699564 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3915 01:20:09.702971 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3916 01:20:09.709728 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3917 01:20:09.712884 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3918 01:20:09.716197 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3919 01:20:09.716661 ==
3920 01:20:09.719798 Dram Type= 6, Freq= 0, CH_0, rank 0
3921 01:20:09.722781 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3922 01:20:09.726569 ==
3923 01:20:09.727124 DQS Delay:
3924 01:20:09.727496 DQS0 = 0, DQS1 = 0
3925 01:20:09.729519 DQM Delay:
3926 01:20:09.730118 DQM0 = 38, DQM1 = 33
3927 01:20:09.732852 DQ Delay:
3928 01:20:09.733400 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3929 01:20:09.735936 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3930 01:20:09.739460 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3931 01:20:09.742728 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3932 01:20:09.743290
3933 01:20:09.746586
3934 01:20:09.747137 ==
3935 01:20:09.749115 Dram Type= 6, Freq= 0, CH_0, rank 0
3936 01:20:09.752372 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3937 01:20:09.752934 ==
3938 01:20:09.753309
3939 01:20:09.753651
3940 01:20:09.756126 TX Vref Scan disable
3941 01:20:09.756690 == TX Byte 0 ==
3942 01:20:09.762616 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3943 01:20:09.765610 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3944 01:20:09.766214 == TX Byte 1 ==
3945 01:20:09.772194 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3946 01:20:09.775603 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3947 01:20:09.776160 ==
3948 01:20:09.779313 Dram Type= 6, Freq= 0, CH_0, rank 0
3949 01:20:09.782301 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3950 01:20:09.782769 ==
3951 01:20:09.783138
3952 01:20:09.783480
3953 01:20:09.785597 TX Vref Scan disable
3954 01:20:09.788836 == TX Byte 0 ==
3955 01:20:09.791992 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3956 01:20:09.795444 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3957 01:20:09.798974 == TX Byte 1 ==
3958 01:20:09.802020 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3959 01:20:09.805361 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3960 01:20:09.808592
3961 01:20:09.809046 [DATLAT]
3962 01:20:09.809412 Freq=600, CH0 RK0
3963 01:20:09.809757
3964 01:20:09.811682 DATLAT Default: 0x9
3965 01:20:09.812160 0, 0xFFFF, sum = 0
3966 01:20:09.815013 1, 0xFFFF, sum = 0
3967 01:20:09.815478 2, 0xFFFF, sum = 0
3968 01:20:09.818459 3, 0xFFFF, sum = 0
3969 01:20:09.818954 4, 0xFFFF, sum = 0
3970 01:20:09.821677 5, 0xFFFF, sum = 0
3971 01:20:09.825229 6, 0xFFFF, sum = 0
3972 01:20:09.825784 7, 0x0, sum = 1
3973 01:20:09.826218 8, 0x0, sum = 2
3974 01:20:09.828650 9, 0x0, sum = 3
3975 01:20:09.829143 10, 0x0, sum = 4
3976 01:20:09.831493 best_step = 8
3977 01:20:09.831950
3978 01:20:09.832374 ==
3979 01:20:09.835076 Dram Type= 6, Freq= 0, CH_0, rank 0
3980 01:20:09.838898 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3981 01:20:09.839381 ==
3982 01:20:09.841748 RX Vref Scan: 1
3983 01:20:09.842366
3984 01:20:09.842739 RX Vref 0 -> 0, step: 1
3985 01:20:09.843087
3986 01:20:09.845136 RX Delay -195 -> 252, step: 8
3987 01:20:09.845595
3988 01:20:09.848347 Set Vref, RX VrefLevel [Byte0]: 45
3989 01:20:09.851558 [Byte1]: 48
3990 01:20:09.855480
3991 01:20:09.855936 Final RX Vref Byte 0 = 45 to rank0
3992 01:20:09.859022 Final RX Vref Byte 1 = 48 to rank0
3993 01:20:09.862116 Final RX Vref Byte 0 = 45 to rank1
3994 01:20:09.865413 Final RX Vref Byte 1 = 48 to rank1==
3995 01:20:09.868583 Dram Type= 6, Freq= 0, CH_0, rank 0
3996 01:20:09.875170 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3997 01:20:09.875594 ==
3998 01:20:09.875924 DQS Delay:
3999 01:20:09.878907 DQS0 = 0, DQS1 = 0
4000 01:20:09.879321 DQM Delay:
4001 01:20:09.879654 DQM0 = 40, DQM1 = 29
4002 01:20:09.882020 DQ Delay:
4003 01:20:09.885242 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =36
4004 01:20:09.888413 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4005 01:20:09.891915 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4006 01:20:09.894827 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40
4007 01:20:09.895246
4008 01:20:09.895576
4009 01:20:09.901938 [DQSOSCAuto] RK0, (LSB)MR18= 0x5252, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
4010 01:20:09.904871 CH0 RK0: MR19=808, MR18=5252
4011 01:20:09.911793 CH0_RK0: MR19=0x808, MR18=0x5252, DQSOSC=394, MR23=63, INC=168, DEC=112
4012 01:20:09.912226
4013 01:20:09.914864 ----->DramcWriteLeveling(PI) begin...
4014 01:20:09.915286 ==
4015 01:20:09.918346 Dram Type= 6, Freq= 0, CH_0, rank 1
4016 01:20:09.921566 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4017 01:20:09.921984 ==
4018 01:20:09.925013 Write leveling (Byte 0): 32 => 32
4019 01:20:09.928012 Write leveling (Byte 1): 31 => 31
4020 01:20:09.931778 DramcWriteLeveling(PI) end<-----
4021 01:20:09.932296
4022 01:20:09.932630 ==
4023 01:20:09.934785 Dram Type= 6, Freq= 0, CH_0, rank 1
4024 01:20:09.938314 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4025 01:20:09.941850 ==
4026 01:20:09.942430 [Gating] SW mode calibration
4027 01:20:09.948323 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4028 01:20:09.954833 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4029 01:20:09.958094 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4030 01:20:09.964725 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4031 01:20:09.968205 0 5 8 | B1->B0 | 3333 3131 | 1 0 | (0 0) (0 0)
4032 01:20:09.971263 0 5 12 | B1->B0 | 2c2c 2525 | 0 0 | (0 0) (0 0)
4033 01:20:09.977665 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 01:20:09.981212 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 01:20:09.984509 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 01:20:09.990836 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 01:20:09.994406 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 01:20:09.997787 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 01:20:10.004096 0 6 8 | B1->B0 | 2c2c 3333 | 0 1 | (0 0) (0 0)
4040 01:20:10.007543 0 6 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
4041 01:20:10.011180 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 01:20:10.017496 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 01:20:10.021106 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 01:20:10.024099 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 01:20:10.031125 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 01:20:10.034149 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 01:20:10.037373 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4048 01:20:10.043957 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 01:20:10.047267 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 01:20:10.050943 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 01:20:10.057041 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 01:20:10.060560 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 01:20:10.063605 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 01:20:10.070448 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 01:20:10.073828 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 01:20:10.076940 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 01:20:10.083672 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 01:20:10.086848 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 01:20:10.090160 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 01:20:10.096897 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 01:20:10.099930 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 01:20:10.103190 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4063 01:20:10.109838 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 01:20:10.110464 Total UI for P1: 0, mck2ui 16
4065 01:20:10.116456 best dqsien dly found for B0: ( 0, 9, 6)
4066 01:20:10.117024 Total UI for P1: 0, mck2ui 16
4067 01:20:10.123170 best dqsien dly found for B1: ( 0, 9, 4)
4068 01:20:10.126317 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4069 01:20:10.129577 best DQS1 dly(MCK, UI, PI) = (0, 9, 4)
4070 01:20:10.130196
4071 01:20:10.133090 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4072 01:20:10.136304 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 4)
4073 01:20:10.139825 [Gating] SW calibration Done
4074 01:20:10.140425 ==
4075 01:20:10.142780 Dram Type= 6, Freq= 0, CH_0, rank 1
4076 01:20:10.146634 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4077 01:20:10.147197 ==
4078 01:20:10.149582 RX Vref Scan: 0
4079 01:20:10.150187
4080 01:20:10.150565 RX Vref 0 -> 0, step: 1
4081 01:20:10.150910
4082 01:20:10.152853 RX Delay -230 -> 252, step: 16
4083 01:20:10.156245 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4084 01:20:10.162759 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4085 01:20:10.166222 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4086 01:20:10.169769 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4087 01:20:10.172612 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4088 01:20:10.179114 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4089 01:20:10.182347 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4090 01:20:10.185946 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4091 01:20:10.188992 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4092 01:20:10.195425 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4093 01:20:10.198784 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4094 01:20:10.202081 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4095 01:20:10.205746 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4096 01:20:10.211992 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4097 01:20:10.215568 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4098 01:20:10.218517 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4099 01:20:10.219023 ==
4100 01:20:10.222007 Dram Type= 6, Freq= 0, CH_0, rank 1
4101 01:20:10.225620 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4102 01:20:10.226232 ==
4103 01:20:10.228876 DQS Delay:
4104 01:20:10.229430 DQS0 = 0, DQS1 = 0
4105 01:20:10.232037 DQM Delay:
4106 01:20:10.232591 DQM0 = 45, DQM1 = 34
4107 01:20:10.232963 DQ Delay:
4108 01:20:10.235224 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4109 01:20:10.238454 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =57
4110 01:20:10.241836 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4111 01:20:10.245321 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4112 01:20:10.245878
4113 01:20:10.246316
4114 01:20:10.248553 ==
4115 01:20:10.251803 Dram Type= 6, Freq= 0, CH_0, rank 1
4116 01:20:10.254934 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4117 01:20:10.255397 ==
4118 01:20:10.255762
4119 01:20:10.256104
4120 01:20:10.258290 TX Vref Scan disable
4121 01:20:10.258781 == TX Byte 0 ==
4122 01:20:10.265015 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4123 01:20:10.268621 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4124 01:20:10.269240 == TX Byte 1 ==
4125 01:20:10.274885 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4126 01:20:10.278403 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4127 01:20:10.278881 ==
4128 01:20:10.281743 Dram Type= 6, Freq= 0, CH_0, rank 1
4129 01:20:10.284912 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4130 01:20:10.285372 ==
4131 01:20:10.285739
4132 01:20:10.286126
4133 01:20:10.288183 TX Vref Scan disable
4134 01:20:10.291229 == TX Byte 0 ==
4135 01:20:10.294694 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4136 01:20:10.298207 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4137 01:20:10.301906 == TX Byte 1 ==
4138 01:20:10.304670 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4139 01:20:10.307920 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4140 01:20:10.308380
4141 01:20:10.311271 [DATLAT]
4142 01:20:10.311838 Freq=600, CH0 RK1
4143 01:20:10.312214
4144 01:20:10.314345 DATLAT Default: 0x8
4145 01:20:10.314806 0, 0xFFFF, sum = 0
4146 01:20:10.317691 1, 0xFFFF, sum = 0
4147 01:20:10.318201 2, 0xFFFF, sum = 0
4148 01:20:10.321074 3, 0xFFFF, sum = 0
4149 01:20:10.321541 4, 0xFFFF, sum = 0
4150 01:20:10.324571 5, 0xFFFF, sum = 0
4151 01:20:10.327962 6, 0xFFFF, sum = 0
4152 01:20:10.328528 7, 0x0, sum = 1
4153 01:20:10.328908 8, 0x0, sum = 2
4154 01:20:10.330952 9, 0x0, sum = 3
4155 01:20:10.331421 10, 0x0, sum = 4
4156 01:20:10.334528 best_step = 8
4157 01:20:10.334983
4158 01:20:10.335344 ==
4159 01:20:10.337455 Dram Type= 6, Freq= 0, CH_0, rank 1
4160 01:20:10.341163 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4161 01:20:10.341728 ==
4162 01:20:10.344789 RX Vref Scan: 0
4163 01:20:10.345352
4164 01:20:10.345718 RX Vref 0 -> 0, step: 1
4165 01:20:10.346100
4166 01:20:10.347397 RX Delay -179 -> 252, step: 8
4167 01:20:10.354541 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4168 01:20:10.357856 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4169 01:20:10.361675 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4170 01:20:10.364520 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4171 01:20:10.371393 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4172 01:20:10.374430 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4173 01:20:10.378004 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4174 01:20:10.381559 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4175 01:20:10.384652 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4176 01:20:10.391532 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4177 01:20:10.394456 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4178 01:20:10.397722 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4179 01:20:10.401213 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4180 01:20:10.407747 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4181 01:20:10.411286 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4182 01:20:10.414183 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4183 01:20:10.414649 ==
4184 01:20:10.417441 Dram Type= 6, Freq= 0, CH_0, rank 1
4185 01:20:10.420850 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4186 01:20:10.424581 ==
4187 01:20:10.425147 DQS Delay:
4188 01:20:10.425514 DQS0 = 0, DQS1 = 0
4189 01:20:10.427748 DQM Delay:
4190 01:20:10.428315 DQM0 = 40, DQM1 = 32
4191 01:20:10.430782 DQ Delay:
4192 01:20:10.434426 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4193 01:20:10.434887 DQ4 =44, DQ5 =32, DQ6 =44, DQ7 =52
4194 01:20:10.437633 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4195 01:20:10.440958 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4196 01:20:10.444151
4197 01:20:10.444606
4198 01:20:10.450907 [DQSOSCAuto] RK1, (LSB)MR18= 0x6161, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4199 01:20:10.454405 CH0 RK1: MR19=808, MR18=6161
4200 01:20:10.460566 CH0_RK1: MR19=0x808, MR18=0x6161, DQSOSC=391, MR23=63, INC=171, DEC=114
4201 01:20:10.464116 [RxdqsGatingPostProcess] freq 600
4202 01:20:10.467842 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4203 01:20:10.470549 Pre-setting of DQS Precalculation
4204 01:20:10.477097 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4205 01:20:10.477663 ==
4206 01:20:10.480581 Dram Type= 6, Freq= 0, CH_1, rank 0
4207 01:20:10.483919 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4208 01:20:10.484571 ==
4209 01:20:10.490583 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4210 01:20:10.493761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4211 01:20:10.498085 [CA 0] Center 35 (5~66) winsize 62
4212 01:20:10.501574 [CA 1] Center 35 (5~66) winsize 62
4213 01:20:10.504893 [CA 2] Center 33 (3~64) winsize 62
4214 01:20:10.508023 [CA 3] Center 33 (3~64) winsize 62
4215 01:20:10.511321 [CA 4] Center 32 (2~63) winsize 62
4216 01:20:10.514599 [CA 5] Center 32 (2~63) winsize 62
4217 01:20:10.515059
4218 01:20:10.517968 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4219 01:20:10.518467
4220 01:20:10.521545 [CATrainingPosCal] consider 1 rank data
4221 01:20:10.524579 u2DelayCellTimex100 = 270/100 ps
4222 01:20:10.528034 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4223 01:20:10.534438 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4224 01:20:10.538169 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4225 01:20:10.541224 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4226 01:20:10.544332 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4227 01:20:10.547886 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4228 01:20:10.548441
4229 01:20:10.551525 CA PerBit enable=1, Macro0, CA PI delay=32
4230 01:20:10.552081
4231 01:20:10.554371 [CBTSetCACLKResult] CA Dly = 32
4232 01:20:10.554932 CS Dly: 4 (0~35)
4233 01:20:10.557662 ==
4234 01:20:10.560823 Dram Type= 6, Freq= 0, CH_1, rank 1
4235 01:20:10.564581 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4236 01:20:10.565148 ==
4237 01:20:10.568030 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4238 01:20:10.574397 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4239 01:20:10.578238 [CA 0] Center 35 (5~66) winsize 62
4240 01:20:10.581524 [CA 1] Center 34 (4~65) winsize 62
4241 01:20:10.584666 [CA 2] Center 33 (3~64) winsize 62
4242 01:20:10.588524 [CA 3] Center 33 (3~64) winsize 62
4243 01:20:10.591472 [CA 4] Center 32 (2~63) winsize 62
4244 01:20:10.594886 [CA 5] Center 32 (2~63) winsize 62
4245 01:20:10.595503
4246 01:20:10.598130 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4247 01:20:10.598594
4248 01:20:10.601481 [CATrainingPosCal] consider 2 rank data
4249 01:20:10.604781 u2DelayCellTimex100 = 270/100 ps
4250 01:20:10.607660 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4251 01:20:10.614495 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4252 01:20:10.617761 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4253 01:20:10.621067 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4254 01:20:10.624643 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4255 01:20:10.627880 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4256 01:20:10.628444
4257 01:20:10.630944 CA PerBit enable=1, Macro0, CA PI delay=32
4258 01:20:10.631503
4259 01:20:10.634747 [CBTSetCACLKResult] CA Dly = 32
4260 01:20:10.635305 CS Dly: 4 (0~36)
4261 01:20:10.637827
4262 01:20:10.641087 ----->DramcWriteLeveling(PI) begin...
4263 01:20:10.641656 ==
4264 01:20:10.644320 Dram Type= 6, Freq= 0, CH_1, rank 0
4265 01:20:10.647728 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4266 01:20:10.648193 ==
4267 01:20:10.651056 Write leveling (Byte 0): 28 => 28
4268 01:20:10.654488 Write leveling (Byte 1): 28 => 28
4269 01:20:10.657968 DramcWriteLeveling(PI) end<-----
4270 01:20:10.658574
4271 01:20:10.658949 ==
4272 01:20:10.660874 Dram Type= 6, Freq= 0, CH_1, rank 0
4273 01:20:10.664340 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4274 01:20:10.664909 ==
4275 01:20:10.667586 [Gating] SW mode calibration
4276 01:20:10.674133 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4277 01:20:10.680821 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4278 01:20:10.684175 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4279 01:20:10.687266 0 5 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
4280 01:20:10.694401 0 5 8 | B1->B0 | 2f2f 2828 | 1 0 | (1 1) (0 0)
4281 01:20:10.697140 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4282 01:20:10.700909 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4283 01:20:10.707271 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4284 01:20:10.710211 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4285 01:20:10.713840 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4286 01:20:10.720349 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4287 01:20:10.723448 0 6 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
4288 01:20:10.726899 0 6 8 | B1->B0 | 3434 3e3e | 1 0 | (0 0) (0 0)
4289 01:20:10.733628 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4290 01:20:10.737031 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4291 01:20:10.740337 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4292 01:20:10.746690 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4293 01:20:10.749851 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4294 01:20:10.753375 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4295 01:20:10.759983 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4296 01:20:10.763327 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4297 01:20:10.766230 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 01:20:10.772808 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 01:20:10.776361 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 01:20:10.779288 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 01:20:10.786568 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 01:20:10.789686 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 01:20:10.792858 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 01:20:10.799615 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 01:20:10.802795 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 01:20:10.806319 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 01:20:10.812928 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 01:20:10.816257 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 01:20:10.819422 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 01:20:10.825804 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 01:20:10.829257 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 01:20:10.832657 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4313 01:20:10.835679 Total UI for P1: 0, mck2ui 16
4314 01:20:10.838908 best dqsien dly found for B0: ( 0, 9, 6)
4315 01:20:10.842632 Total UI for P1: 0, mck2ui 16
4316 01:20:10.845382 best dqsien dly found for B1: ( 0, 9, 6)
4317 01:20:10.848461 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4318 01:20:10.852206 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4319 01:20:10.852773
4320 01:20:10.858846 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4321 01:20:10.861870 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4322 01:20:10.862380 [Gating] SW calibration Done
4323 01:20:10.865448 ==
4324 01:20:10.868700 Dram Type= 6, Freq= 0, CH_1, rank 0
4325 01:20:10.871769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4326 01:20:10.872336 ==
4327 01:20:10.872706 RX Vref Scan: 0
4328 01:20:10.873046
4329 01:20:10.875443 RX Vref 0 -> 0, step: 1
4330 01:20:10.876005
4331 01:20:10.878284 RX Delay -230 -> 252, step: 16
4332 01:20:10.881798 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4333 01:20:10.885119 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4334 01:20:10.892055 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4335 01:20:10.894876 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4336 01:20:10.898338 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4337 01:20:10.901643 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4338 01:20:10.908836 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4339 01:20:10.911200 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4340 01:20:10.914766 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4341 01:20:10.917880 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4342 01:20:10.921609 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4343 01:20:10.927700 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4344 01:20:10.931184 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4345 01:20:10.934520 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4346 01:20:10.941533 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4347 01:20:10.944414 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4348 01:20:10.945045 ==
4349 01:20:10.947589 Dram Type= 6, Freq= 0, CH_1, rank 0
4350 01:20:10.951139 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4351 01:20:10.951705 ==
4352 01:20:10.952075 DQS Delay:
4353 01:20:10.954165 DQS0 = 0, DQS1 = 0
4354 01:20:10.954623 DQM Delay:
4355 01:20:10.957860 DQM0 = 38, DQM1 = 32
4356 01:20:10.958352 DQ Delay:
4357 01:20:10.960989 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4358 01:20:10.965178 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4359 01:20:10.967615 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4360 01:20:10.970952 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =49
4361 01:20:10.971415
4362 01:20:10.971779
4363 01:20:10.972124 ==
4364 01:20:10.974321 Dram Type= 6, Freq= 0, CH_1, rank 0
4365 01:20:10.977573 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4366 01:20:10.980505 ==
4367 01:20:10.980924
4368 01:20:10.981256
4369 01:20:10.981567 TX Vref Scan disable
4370 01:20:10.983882 == TX Byte 0 ==
4371 01:20:10.987194 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4372 01:20:10.993847 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4373 01:20:10.994354 == TX Byte 1 ==
4374 01:20:10.997309 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4375 01:20:11.003612 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4376 01:20:11.004125 ==
4377 01:20:11.007081 Dram Type= 6, Freq= 0, CH_1, rank 0
4378 01:20:11.010246 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4379 01:20:11.010889 ==
4380 01:20:11.011240
4381 01:20:11.011549
4382 01:20:11.013686 TX Vref Scan disable
4383 01:20:11.017004 == TX Byte 0 ==
4384 01:20:11.020263 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4385 01:20:11.023599 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4386 01:20:11.027026 == TX Byte 1 ==
4387 01:20:11.030581 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4388 01:20:11.033579 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4389 01:20:11.034113
4390 01:20:11.034505 [DATLAT]
4391 01:20:11.037346 Freq=600, CH1 RK0
4392 01:20:11.038085
4393 01:20:11.040125 DATLAT Default: 0x9
4394 01:20:11.040535 0, 0xFFFF, sum = 0
4395 01:20:11.043244 1, 0xFFFF, sum = 0
4396 01:20:11.043659 2, 0xFFFF, sum = 0
4397 01:20:11.046791 3, 0xFFFF, sum = 0
4398 01:20:11.047206 4, 0xFFFF, sum = 0
4399 01:20:11.050218 5, 0xFFFF, sum = 0
4400 01:20:11.050834 6, 0xFFFF, sum = 0
4401 01:20:11.053391 7, 0x0, sum = 1
4402 01:20:11.053806 8, 0x0, sum = 2
4403 01:20:11.057037 9, 0x0, sum = 3
4404 01:20:11.057458 10, 0x0, sum = 4
4405 01:20:11.057827 best_step = 8
4406 01:20:11.058278
4407 01:20:11.059831 ==
4408 01:20:11.063343 Dram Type= 6, Freq= 0, CH_1, rank 0
4409 01:20:11.066485 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4410 01:20:11.066902 ==
4411 01:20:11.067236 RX Vref Scan: 1
4412 01:20:11.067546
4413 01:20:11.069886 RX Vref 0 -> 0, step: 1
4414 01:20:11.070452
4415 01:20:11.073022 RX Delay -195 -> 252, step: 8
4416 01:20:11.073435
4417 01:20:11.076489 Set Vref, RX VrefLevel [Byte0]: 54
4418 01:20:11.080020 [Byte1]: 50
4419 01:20:11.080444
4420 01:20:11.082877 Final RX Vref Byte 0 = 54 to rank0
4421 01:20:11.086084 Final RX Vref Byte 1 = 50 to rank0
4422 01:20:11.089817 Final RX Vref Byte 0 = 54 to rank1
4423 01:20:11.092929 Final RX Vref Byte 1 = 50 to rank1==
4424 01:20:11.096207 Dram Type= 6, Freq= 0, CH_1, rank 0
4425 01:20:11.099658 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4426 01:20:11.102860 ==
4427 01:20:11.103384 DQS Delay:
4428 01:20:11.103829 DQS0 = 0, DQS1 = 0
4429 01:20:11.106385 DQM Delay:
4430 01:20:11.106799 DQM0 = 36, DQM1 = 30
4431 01:20:11.109812 DQ Delay:
4432 01:20:11.112537 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4433 01:20:11.113017 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4434 01:20:11.116341 DQ8 =12, DQ9 =16, DQ10 =32, DQ11 =24
4435 01:20:11.122742 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4436 01:20:11.123158
4437 01:20:11.123489
4438 01:20:11.129191 [DQSOSCAuto] RK0, (LSB)MR18= 0x6c6c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4439 01:20:11.132965 CH1 RK0: MR19=808, MR18=6C6C
4440 01:20:11.139369 CH1_RK0: MR19=0x808, MR18=0x6C6C, DQSOSC=389, MR23=63, INC=173, DEC=115
4441 01:20:11.139891
4442 01:20:11.142923 ----->DramcWriteLeveling(PI) begin...
4443 01:20:11.143484 ==
4444 01:20:11.146136 Dram Type= 6, Freq= 0, CH_1, rank 1
4445 01:20:11.149528 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4446 01:20:11.149948 ==
4447 01:20:11.152783 Write leveling (Byte 0): 27 => 27
4448 01:20:11.156452 Write leveling (Byte 1): 27 => 27
4449 01:20:11.159405 DramcWriteLeveling(PI) end<-----
4450 01:20:11.159921
4451 01:20:11.160253 ==
4452 01:20:11.162534 Dram Type= 6, Freq= 0, CH_1, rank 1
4453 01:20:11.165977 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4454 01:20:11.166579 ==
4455 01:20:11.169347 [Gating] SW mode calibration
4456 01:20:11.175820 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4457 01:20:11.182596 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4458 01:20:11.185823 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4459 01:20:11.192149 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
4460 01:20:11.195440 0 5 8 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (0 0)
4461 01:20:11.198718 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 01:20:11.205725 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 01:20:11.208801 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 01:20:11.211827 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 01:20:11.218408 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 01:20:11.221722 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 01:20:11.225341 0 6 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
4468 01:20:11.232178 0 6 8 | B1->B0 | 3232 4040 | 0 0 | (0 0) (0 0)
4469 01:20:11.235471 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 01:20:11.238365 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 01:20:11.244985 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 01:20:11.248573 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 01:20:11.251516 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 01:20:11.258294 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 01:20:11.261630 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4476 01:20:11.265010 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4477 01:20:11.268684 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 01:20:11.274873 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 01:20:11.278202 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 01:20:11.284827 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 01:20:11.287996 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 01:20:11.291290 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 01:20:11.294887 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 01:20:11.301020 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 01:20:11.304504 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 01:20:11.307767 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 01:20:11.314266 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 01:20:11.317895 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 01:20:11.321185 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 01:20:11.327648 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 01:20:11.331017 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4492 01:20:11.333975 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 01:20:11.337706 Total UI for P1: 0, mck2ui 16
4494 01:20:11.341047 best dqsien dly found for B0: ( 0, 9, 4)
4495 01:20:11.344339 Total UI for P1: 0, mck2ui 16
4496 01:20:11.347655 best dqsien dly found for B1: ( 0, 9, 4)
4497 01:20:11.350898 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4498 01:20:11.354166 best DQS1 dly(MCK, UI, PI) = (0, 9, 4)
4499 01:20:11.354632
4500 01:20:11.360829 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4501 01:20:11.363681 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 4)
4502 01:20:11.367100 [Gating] SW calibration Done
4503 01:20:11.367558 ==
4504 01:20:11.370130 Dram Type= 6, Freq= 0, CH_1, rank 1
4505 01:20:11.374001 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4506 01:20:11.374664 ==
4507 01:20:11.375051 RX Vref Scan: 0
4508 01:20:11.377315
4509 01:20:11.377874 RX Vref 0 -> 0, step: 1
4510 01:20:11.378288
4511 01:20:11.380228 RX Delay -230 -> 252, step: 16
4512 01:20:11.383755 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4513 01:20:11.390373 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4514 01:20:11.393718 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4515 01:20:11.396632 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4516 01:20:11.400147 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4517 01:20:11.406945 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4518 01:20:11.410068 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4519 01:20:11.413475 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4520 01:20:11.416477 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4521 01:20:11.420099 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4522 01:20:11.426408 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4523 01:20:11.429604 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4524 01:20:11.433230 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4525 01:20:11.436637 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4526 01:20:11.443316 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4527 01:20:11.446480 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4528 01:20:11.447042 ==
4529 01:20:11.449761 Dram Type= 6, Freq= 0, CH_1, rank 1
4530 01:20:11.452994 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4531 01:20:11.453562 ==
4532 01:20:11.456305 DQS Delay:
4533 01:20:11.456868 DQS0 = 0, DQS1 = 0
4534 01:20:11.459186 DQM Delay:
4535 01:20:11.459643 DQM0 = 40, DQM1 = 32
4536 01:20:11.460006 DQ Delay:
4537 01:20:11.462617 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4538 01:20:11.466100 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4539 01:20:11.469283 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4540 01:20:11.472686 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4541 01:20:11.473250
4542 01:20:11.473626
4543 01:20:11.476096 ==
4544 01:20:11.476654 Dram Type= 6, Freq= 0, CH_1, rank 1
4545 01:20:11.482532 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4546 01:20:11.483082 ==
4547 01:20:11.483452
4548 01:20:11.483796
4549 01:20:11.485949 TX Vref Scan disable
4550 01:20:11.486586 == TX Byte 0 ==
4551 01:20:11.492649 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4552 01:20:11.495937 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4553 01:20:11.496509 == TX Byte 1 ==
4554 01:20:11.502622 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4555 01:20:11.505629 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4556 01:20:11.506234 ==
4557 01:20:11.509234 Dram Type= 6, Freq= 0, CH_1, rank 1
4558 01:20:11.512142 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4559 01:20:11.512689 ==
4560 01:20:11.513233
4561 01:20:11.513591
4562 01:20:11.515638 TX Vref Scan disable
4563 01:20:11.519190 == TX Byte 0 ==
4564 01:20:11.522405 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4565 01:20:11.525667 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4566 01:20:11.528790 == TX Byte 1 ==
4567 01:20:11.532364 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4568 01:20:11.535814 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4569 01:20:11.536398
4570 01:20:11.538766 [DATLAT]
4571 01:20:11.539320 Freq=600, CH1 RK1
4572 01:20:11.539697
4573 01:20:11.541913 DATLAT Default: 0x8
4574 01:20:11.542445 0, 0xFFFF, sum = 0
4575 01:20:11.545239 1, 0xFFFF, sum = 0
4576 01:20:11.545712 2, 0xFFFF, sum = 0
4577 01:20:11.548902 3, 0xFFFF, sum = 0
4578 01:20:11.549471 4, 0xFFFF, sum = 0
4579 01:20:11.552424 5, 0xFFFF, sum = 0
4580 01:20:11.552991 6, 0xFFFF, sum = 0
4581 01:20:11.555152 7, 0x0, sum = 1
4582 01:20:11.555627 8, 0x0, sum = 2
4583 01:20:11.558488 9, 0x0, sum = 3
4584 01:20:11.558962 10, 0x0, sum = 4
4585 01:20:11.562018 best_step = 8
4586 01:20:11.562673
4587 01:20:11.563231 ==
4588 01:20:11.565268 Dram Type= 6, Freq= 0, CH_1, rank 1
4589 01:20:11.568336 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4590 01:20:11.568884 ==
4591 01:20:11.572054 RX Vref Scan: 0
4592 01:20:11.572661
4593 01:20:11.573229 RX Vref 0 -> 0, step: 1
4594 01:20:11.573602
4595 01:20:11.575066 RX Delay -195 -> 252, step: 8
4596 01:20:11.581757 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4597 01:20:11.585069 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4598 01:20:11.588758 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4599 01:20:11.591774 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4600 01:20:11.598522 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4601 01:20:11.601363 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4602 01:20:11.605229 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4603 01:20:11.608578 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4604 01:20:11.614624 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4605 01:20:11.618308 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4606 01:20:11.622019 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4607 01:20:11.624647 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4608 01:20:11.631298 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4609 01:20:11.634932 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4610 01:20:11.638274 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4611 01:20:11.641434 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4612 01:20:11.642000 ==
4613 01:20:11.644463 Dram Type= 6, Freq= 0, CH_1, rank 1
4614 01:20:11.651370 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4615 01:20:11.651953 ==
4616 01:20:11.652331 DQS Delay:
4617 01:20:11.654265 DQS0 = 0, DQS1 = 0
4618 01:20:11.654733 DQM Delay:
4619 01:20:11.655108 DQM0 = 36, DQM1 = 29
4620 01:20:11.658229 DQ Delay:
4621 01:20:11.660943 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4622 01:20:11.664579 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4623 01:20:11.667501 DQ8 =16, DQ9 =20, DQ10 =28, DQ11 =20
4624 01:20:11.670780 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4625 01:20:11.671378
4626 01:20:11.671933
4627 01:20:11.677676 [DQSOSCAuto] RK1, (LSB)MR18= 0x5454, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4628 01:20:11.680806 CH1 RK1: MR19=808, MR18=5454
4629 01:20:11.687597 CH1_RK1: MR19=0x808, MR18=0x5454, DQSOSC=393, MR23=63, INC=169, DEC=113
4630 01:20:11.690772 [RxdqsGatingPostProcess] freq 600
4631 01:20:11.694000 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4632 01:20:11.697362 Pre-setting of DQS Precalculation
4633 01:20:11.704329 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4634 01:20:11.710732 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4635 01:20:11.717002 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4636 01:20:11.717491
4637 01:20:11.717869
4638 01:20:11.720329 [Calibration Summary] 1200 Mbps
4639 01:20:11.723873 CH 0, Rank 0
4640 01:20:11.724436 SW Impedance : PASS
4641 01:20:11.727499 DUTY Scan : NO K
4642 01:20:11.728061 ZQ Calibration : PASS
4643 01:20:11.730254 Jitter Meter : NO K
4644 01:20:11.734147 CBT Training : PASS
4645 01:20:11.734706 Write leveling : PASS
4646 01:20:11.737269 RX DQS gating : PASS
4647 01:20:11.740389 RX DQ/DQS(RDDQC) : PASS
4648 01:20:11.740949 TX DQ/DQS : PASS
4649 01:20:11.743863 RX DATLAT : PASS
4650 01:20:11.746878 RX DQ/DQS(Engine): PASS
4651 01:20:11.747342 TX OE : NO K
4652 01:20:11.750741 All Pass.
4653 01:20:11.751300
4654 01:20:11.751713 CH 0, Rank 1
4655 01:20:11.753251 SW Impedance : PASS
4656 01:20:11.753710 DUTY Scan : NO K
4657 01:20:11.756757 ZQ Calibration : PASS
4658 01:20:11.760003 Jitter Meter : NO K
4659 01:20:11.760482 CBT Training : PASS
4660 01:20:11.763421 Write leveling : PASS
4661 01:20:11.766932 RX DQS gating : PASS
4662 01:20:11.767493 RX DQ/DQS(RDDQC) : PASS
4663 01:20:11.770459 TX DQ/DQS : PASS
4664 01:20:11.773016 RX DATLAT : PASS
4665 01:20:11.773483 RX DQ/DQS(Engine): PASS
4666 01:20:11.776317 TX OE : NO K
4667 01:20:11.776783 All Pass.
4668 01:20:11.777147
4669 01:20:11.779714 CH 1, Rank 0
4670 01:20:11.780235 SW Impedance : PASS
4671 01:20:11.783565 DUTY Scan : NO K
4672 01:20:11.786542 ZQ Calibration : PASS
4673 01:20:11.787101 Jitter Meter : NO K
4674 01:20:11.789804 CBT Training : PASS
4675 01:20:11.792915 Write leveling : PASS
4676 01:20:11.793381 RX DQS gating : PASS
4677 01:20:11.796383 RX DQ/DQS(RDDQC) : PASS
4678 01:20:11.796846 TX DQ/DQS : PASS
4679 01:20:11.799630 RX DATLAT : PASS
4680 01:20:11.802959 RX DQ/DQS(Engine): PASS
4681 01:20:11.803471 TX OE : NO K
4682 01:20:11.806252 All Pass.
4683 01:20:11.806712
4684 01:20:11.807074 CH 1, Rank 1
4685 01:20:11.809755 SW Impedance : PASS
4686 01:20:11.810363 DUTY Scan : NO K
4687 01:20:11.812709 ZQ Calibration : PASS
4688 01:20:11.815904 Jitter Meter : NO K
4689 01:20:11.816366 CBT Training : PASS
4690 01:20:11.819318 Write leveling : PASS
4691 01:20:11.822736 RX DQS gating : PASS
4692 01:20:11.823204 RX DQ/DQS(RDDQC) : PASS
4693 01:20:11.826362 TX DQ/DQS : PASS
4694 01:20:11.829162 RX DATLAT : PASS
4695 01:20:11.829583 RX DQ/DQS(Engine): PASS
4696 01:20:11.832738 TX OE : NO K
4697 01:20:11.833260 All Pass.
4698 01:20:11.833596
4699 01:20:11.835862 DramC Write-DBI off
4700 01:20:11.839473 PER_BANK_REFRESH: Hybrid Mode
4701 01:20:11.840030 TX_TRACKING: ON
4702 01:20:11.849081 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4703 01:20:11.852855 [FAST_K] Save calibration result to emmc
4704 01:20:11.855833 dramc_set_vcore_voltage set vcore to 662500
4705 01:20:11.858998 Read voltage for 933, 3
4706 01:20:11.859558 Vio18 = 0
4707 01:20:11.859930 Vcore = 662500
4708 01:20:11.862345 Vdram = 0
4709 01:20:11.862838 Vddq = 0
4710 01:20:11.863212 Vmddr = 0
4711 01:20:11.869088 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4712 01:20:11.872198 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4713 01:20:11.876026 MEM_TYPE=3, freq_sel=17
4714 01:20:11.879169 sv_algorithm_assistance_LP4_1600
4715 01:20:11.881967 ============ PULL DRAM RESETB DOWN ============
4716 01:20:11.885573 ========== PULL DRAM RESETB DOWN end =========
4717 01:20:11.892356 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4718 01:20:11.895286 ===================================
4719 01:20:11.898528 LPDDR4 DRAM CONFIGURATION
4720 01:20:11.902410 ===================================
4721 01:20:11.902978 EX_ROW_EN[0] = 0x0
4722 01:20:11.905368 EX_ROW_EN[1] = 0x0
4723 01:20:11.905926 LP4Y_EN = 0x0
4724 01:20:11.908757 WORK_FSP = 0x0
4725 01:20:11.909314 WL = 0x3
4726 01:20:11.911765 RL = 0x3
4727 01:20:11.912226 BL = 0x2
4728 01:20:11.915140 RPST = 0x0
4729 01:20:11.915703 RD_PRE = 0x0
4730 01:20:11.918448 WR_PRE = 0x1
4731 01:20:11.921486 WR_PST = 0x0
4732 01:20:11.921947 DBI_WR = 0x0
4733 01:20:11.925346 DBI_RD = 0x0
4734 01:20:11.925906 OTF = 0x1
4735 01:20:11.928279 ===================================
4736 01:20:11.931774 ===================================
4737 01:20:11.932238 ANA top config
4738 01:20:11.935079 ===================================
4739 01:20:11.938425 DLL_ASYNC_EN = 0
4740 01:20:11.941881 ALL_SLAVE_EN = 1
4741 01:20:11.944882 NEW_RANK_MODE = 1
4742 01:20:11.948236 DLL_IDLE_MODE = 1
4743 01:20:11.948799 LP45_APHY_COMB_EN = 1
4744 01:20:11.951673 TX_ODT_DIS = 1
4745 01:20:11.954705 NEW_8X_MODE = 1
4746 01:20:11.958281 ===================================
4747 01:20:11.961171 ===================================
4748 01:20:11.964505 data_rate = 1866
4749 01:20:11.967876 CKR = 1
4750 01:20:11.971382 DQ_P2S_RATIO = 8
4751 01:20:11.974582 ===================================
4752 01:20:11.975141 CA_P2S_RATIO = 8
4753 01:20:11.977622 DQ_CA_OPEN = 0
4754 01:20:11.981681 DQ_SEMI_OPEN = 0
4755 01:20:11.984366 CA_SEMI_OPEN = 0
4756 01:20:11.987590 CA_FULL_RATE = 0
4757 01:20:11.991145 DQ_CKDIV4_EN = 1
4758 01:20:11.991705 CA_CKDIV4_EN = 1
4759 01:20:11.994294 CA_PREDIV_EN = 0
4760 01:20:11.997704 PH8_DLY = 0
4761 01:20:12.000867 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4762 01:20:12.004470 DQ_AAMCK_DIV = 4
4763 01:20:12.007391 CA_AAMCK_DIV = 4
4764 01:20:12.007850 CA_ADMCK_DIV = 4
4765 01:20:12.010684 DQ_TRACK_CA_EN = 0
4766 01:20:12.013995 CA_PICK = 933
4767 01:20:12.017384 CA_MCKIO = 933
4768 01:20:12.020547 MCKIO_SEMI = 0
4769 01:20:12.023851 PLL_FREQ = 3732
4770 01:20:12.027364 DQ_UI_PI_RATIO = 32
4771 01:20:12.027931 CA_UI_PI_RATIO = 0
4772 01:20:12.030620 ===================================
4773 01:20:12.033771 ===================================
4774 01:20:12.036973 memory_type:LPDDR4
4775 01:20:12.040360 GP_NUM : 10
4776 01:20:12.040921 SRAM_EN : 1
4777 01:20:12.043937 MD32_EN : 0
4778 01:20:12.046867 ===================================
4779 01:20:12.050703 [ANA_INIT] >>>>>>>>>>>>>>
4780 01:20:12.053457 <<<<<< [CONFIGURE PHASE]: ANA_TX
4781 01:20:12.057100 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4782 01:20:12.060197 ===================================
4783 01:20:12.060662 data_rate = 1866,PCW = 0X8f00
4784 01:20:12.063561 ===================================
4785 01:20:12.066941 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4786 01:20:12.073694 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4787 01:20:12.080447 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4788 01:20:12.083318 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4789 01:20:12.086693 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4790 01:20:12.090389 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4791 01:20:12.093382 [ANA_INIT] flow start
4792 01:20:12.097014 [ANA_INIT] PLL >>>>>>>>
4793 01:20:12.097581 [ANA_INIT] PLL <<<<<<<<
4794 01:20:12.099783 [ANA_INIT] MIDPI >>>>>>>>
4795 01:20:12.103355 [ANA_INIT] MIDPI <<<<<<<<
4796 01:20:12.103917 [ANA_INIT] DLL >>>>>>>>
4797 01:20:12.106502 [ANA_INIT] flow end
4798 01:20:12.109711 ============ LP4 DIFF to SE enter ============
4799 01:20:12.113573 ============ LP4 DIFF to SE exit ============
4800 01:20:12.116398 [ANA_INIT] <<<<<<<<<<<<<
4801 01:20:12.119471 [Flow] Enable top DCM control >>>>>
4802 01:20:12.122688 [Flow] Enable top DCM control <<<<<
4803 01:20:12.126237 Enable DLL master slave shuffle
4804 01:20:12.132850 ==============================================================
4805 01:20:12.133570 Gating Mode config
4806 01:20:12.139746 ==============================================================
4807 01:20:12.142725 Config description:
4808 01:20:12.149612 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4809 01:20:12.156472 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4810 01:20:12.162667 SELPH_MODE 0: By rank 1: By Phase
4811 01:20:12.169384 ==============================================================
4812 01:20:12.172482 GAT_TRACK_EN = 1
4813 01:20:12.172948 RX_GATING_MODE = 2
4814 01:20:12.175589 RX_GATING_TRACK_MODE = 2
4815 01:20:12.179652 SELPH_MODE = 1
4816 01:20:12.182728 PICG_EARLY_EN = 1
4817 01:20:12.185975 VALID_LAT_VALUE = 1
4818 01:20:12.192257 ==============================================================
4819 01:20:12.195733 Enter into Gating configuration >>>>
4820 01:20:12.199108 Exit from Gating configuration <<<<
4821 01:20:12.202131 Enter into DVFS_PRE_config >>>>>
4822 01:20:12.212249 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4823 01:20:12.215245 Exit from DVFS_PRE_config <<<<<
4824 01:20:12.218649 Enter into PICG configuration >>>>
4825 01:20:12.221943 Exit from PICG configuration <<<<
4826 01:20:12.225925 [RX_INPUT] configuration >>>>>
4827 01:20:12.228343 [RX_INPUT] configuration <<<<<
4828 01:20:12.231715 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4829 01:20:12.238356 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4830 01:20:12.244834 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4831 01:20:12.251464 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4832 01:20:12.258484 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4833 01:20:12.261719 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4834 01:20:12.267959 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4835 01:20:12.271411 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4836 01:20:12.274819 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4837 01:20:12.278114 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4838 01:20:12.284682 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4839 01:20:12.287621 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4840 01:20:12.291002 ===================================
4841 01:20:12.294546 LPDDR4 DRAM CONFIGURATION
4842 01:20:12.297761 ===================================
4843 01:20:12.298404 EX_ROW_EN[0] = 0x0
4844 01:20:12.300934 EX_ROW_EN[1] = 0x0
4845 01:20:12.301507 LP4Y_EN = 0x0
4846 01:20:12.304579 WORK_FSP = 0x0
4847 01:20:12.305156 WL = 0x3
4848 01:20:12.307700 RL = 0x3
4849 01:20:12.308273 BL = 0x2
4850 01:20:12.310652 RPST = 0x0
4851 01:20:12.314491 RD_PRE = 0x0
4852 01:20:12.315068 WR_PRE = 0x1
4853 01:20:12.317614 WR_PST = 0x0
4854 01:20:12.318140 DBI_WR = 0x0
4855 01:20:12.320955 DBI_RD = 0x0
4856 01:20:12.321521 OTF = 0x1
4857 01:20:12.323953 ===================================
4858 01:20:12.327496 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4859 01:20:12.333979 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4860 01:20:12.337409 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4861 01:20:12.340749 ===================================
4862 01:20:12.343750 LPDDR4 DRAM CONFIGURATION
4863 01:20:12.347361 ===================================
4864 01:20:12.347926 EX_ROW_EN[0] = 0x10
4865 01:20:12.350481 EX_ROW_EN[1] = 0x0
4866 01:20:12.351037 LP4Y_EN = 0x0
4867 01:20:12.353935 WORK_FSP = 0x0
4868 01:20:12.354560 WL = 0x3
4869 01:20:12.356714 RL = 0x3
4870 01:20:12.359930 BL = 0x2
4871 01:20:12.360553 RPST = 0x0
4872 01:20:12.363276 RD_PRE = 0x0
4873 01:20:12.363743 WR_PRE = 0x1
4874 01:20:12.366887 WR_PST = 0x0
4875 01:20:12.367589 DBI_WR = 0x0
4876 01:20:12.370322 DBI_RD = 0x0
4877 01:20:12.370788 OTF = 0x1
4878 01:20:12.373014 ===================================
4879 01:20:12.380210 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4880 01:20:12.383763 nWR fixed to 30
4881 01:20:12.387534 [ModeRegInit_LP4] CH0 RK0
4882 01:20:12.388097 [ModeRegInit_LP4] CH0 RK1
4883 01:20:12.390891 [ModeRegInit_LP4] CH1 RK0
4884 01:20:12.394123 [ModeRegInit_LP4] CH1 RK1
4885 01:20:12.394686 match AC timing 8
4886 01:20:12.400199 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4887 01:20:12.404338 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4888 01:20:12.407053 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4889 01:20:12.413993 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4890 01:20:12.417418 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4891 01:20:12.418288 ==
4892 01:20:12.420221 Dram Type= 6, Freq= 0, CH_0, rank 0
4893 01:20:12.423267 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4894 01:20:12.423739 ==
4895 01:20:12.430223 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4896 01:20:12.436845 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4897 01:20:12.439993 [CA 0] Center 38 (8~69) winsize 62
4898 01:20:12.443026 [CA 1] Center 38 (8~69) winsize 62
4899 01:20:12.446184 [CA 2] Center 36 (6~67) winsize 62
4900 01:20:12.449661 [CA 3] Center 35 (5~66) winsize 62
4901 01:20:12.452699 [CA 4] Center 34 (4~65) winsize 62
4902 01:20:12.456088 [CA 5] Center 34 (4~64) winsize 61
4903 01:20:12.456619
4904 01:20:12.459293 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4905 01:20:12.459763
4906 01:20:12.462647 [CATrainingPosCal] consider 1 rank data
4907 01:20:12.466157 u2DelayCellTimex100 = 270/100 ps
4908 01:20:12.469375 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4909 01:20:12.472720 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4910 01:20:12.476512 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4911 01:20:12.482574 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4912 01:20:12.485640 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4913 01:20:12.489203 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4914 01:20:12.489766
4915 01:20:12.492089 CA PerBit enable=1, Macro0, CA PI delay=34
4916 01:20:12.492666
4917 01:20:12.495527 [CBTSetCACLKResult] CA Dly = 34
4918 01:20:12.495997 CS Dly: 7 (0~38)
4919 01:20:12.499101 ==
4920 01:20:12.499694 Dram Type= 6, Freq= 0, CH_0, rank 1
4921 01:20:12.505758 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4922 01:20:12.506370 ==
4923 01:20:12.508874 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4924 01:20:12.515133 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4925 01:20:12.518963 [CA 0] Center 38 (8~69) winsize 62
4926 01:20:12.522147 [CA 1] Center 38 (8~69) winsize 62
4927 01:20:12.526064 [CA 2] Center 35 (5~66) winsize 62
4928 01:20:12.529224 [CA 3] Center 35 (5~66) winsize 62
4929 01:20:12.532189 [CA 4] Center 34 (4~65) winsize 62
4930 01:20:12.535588 [CA 5] Center 34 (4~65) winsize 62
4931 01:20:12.536163
4932 01:20:12.538900 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4933 01:20:12.539463
4934 01:20:12.542294 [CATrainingPosCal] consider 2 rank data
4935 01:20:12.545541 u2DelayCellTimex100 = 270/100 ps
4936 01:20:12.549027 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4937 01:20:12.555492 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4938 01:20:12.558905 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
4939 01:20:12.562193 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4940 01:20:12.565282 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4941 01:20:12.568355 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4942 01:20:12.568823
4943 01:20:12.572071 CA PerBit enable=1, Macro0, CA PI delay=34
4944 01:20:12.572678
4945 01:20:12.575306 [CBTSetCACLKResult] CA Dly = 34
4946 01:20:12.578481 CS Dly: 7 (0~39)
4947 01:20:12.578996
4948 01:20:12.582021 ----->DramcWriteLeveling(PI) begin...
4949 01:20:12.582670 ==
4950 01:20:12.585146 Dram Type= 6, Freq= 0, CH_0, rank 0
4951 01:20:12.588275 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4952 01:20:12.588767 ==
4953 01:20:12.591790 Write leveling (Byte 0): 27 => 27
4954 01:20:12.595361 Write leveling (Byte 1): 26 => 26
4955 01:20:12.598465 DramcWriteLeveling(PI) end<-----
4956 01:20:12.599023
4957 01:20:12.599398 ==
4958 01:20:12.601825 Dram Type= 6, Freq= 0, CH_0, rank 0
4959 01:20:12.605539 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4960 01:20:12.606156 ==
4961 01:20:12.608232 [Gating] SW mode calibration
4962 01:20:12.614872 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4963 01:20:12.621286 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4964 01:20:12.625018 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4965 01:20:12.628460 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4966 01:20:12.634604 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4967 01:20:12.637804 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4968 01:20:12.641213 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4969 01:20:12.647986 0 10 20 | B1->B0 | 3232 2e2e | 0 0 | (0 0) (0 0)
4970 01:20:12.651095 0 10 24 | B1->B0 | 2f2f 2929 | 0 0 | (1 1) (1 1)
4971 01:20:12.654968 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4972 01:20:12.661249 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4973 01:20:12.664380 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4974 01:20:12.667828 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4975 01:20:12.674385 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4976 01:20:12.677436 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4977 01:20:12.680791 0 11 20 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
4978 01:20:12.687874 0 11 24 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
4979 01:20:12.690895 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4980 01:20:12.694015 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4981 01:20:12.700986 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4982 01:20:12.704120 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4983 01:20:12.707239 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4984 01:20:12.714144 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4985 01:20:12.717037 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4986 01:20:12.720718 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4987 01:20:12.727422 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4988 01:20:12.731139 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4989 01:20:12.734136 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4990 01:20:12.740600 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4991 01:20:12.743905 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4992 01:20:12.747121 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4993 01:20:12.754054 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4994 01:20:12.757247 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4995 01:20:12.760700 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4996 01:20:12.767162 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4997 01:20:12.770450 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4998 01:20:12.773690 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4999 01:20:12.780284 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5000 01:20:12.783287 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5001 01:20:12.786952 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5002 01:20:12.793840 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5003 01:20:12.794480 Total UI for P1: 0, mck2ui 16
5004 01:20:12.799788 best dqsien dly found for B0: ( 0, 14, 20)
5005 01:20:12.803281 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5006 01:20:12.806750 Total UI for P1: 0, mck2ui 16
5007 01:20:12.810091 best dqsien dly found for B1: ( 0, 14, 22)
5008 01:20:12.813259 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5009 01:20:12.816563 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5010 01:20:12.817165
5011 01:20:12.819823 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5012 01:20:12.823146 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5013 01:20:12.826489 [Gating] SW calibration Done
5014 01:20:12.826967 ==
5015 01:20:12.829971 Dram Type= 6, Freq= 0, CH_0, rank 0
5016 01:20:12.833384 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5017 01:20:12.836455 ==
5018 01:20:12.837043 RX Vref Scan: 0
5019 01:20:12.837535
5020 01:20:12.839616 RX Vref 0 -> 0, step: 1
5021 01:20:12.840146
5022 01:20:12.842667 RX Delay -80 -> 252, step: 8
5023 01:20:12.846477 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5024 01:20:12.849482 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5025 01:20:12.853163 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5026 01:20:12.856539 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5027 01:20:12.859498 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5028 01:20:12.866156 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5029 01:20:12.870140 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5030 01:20:12.872845 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5031 01:20:12.876265 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5032 01:20:12.879513 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5033 01:20:12.886318 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5034 01:20:12.889476 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5035 01:20:12.892610 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5036 01:20:12.895852 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5037 01:20:12.899064 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5038 01:20:12.906229 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5039 01:20:12.906808 ==
5040 01:20:12.909204 Dram Type= 6, Freq= 0, CH_0, rank 0
5041 01:20:12.912582 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5042 01:20:12.913158 ==
5043 01:20:12.913654 DQS Delay:
5044 01:20:12.915537 DQS0 = 0, DQS1 = 0
5045 01:20:12.916018 DQM Delay:
5046 01:20:12.918948 DQM0 = 95, DQM1 = 83
5047 01:20:12.919418 DQ Delay:
5048 01:20:12.922142 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5049 01:20:12.925664 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5050 01:20:12.929364 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =79
5051 01:20:12.932294 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5052 01:20:12.932849
5053 01:20:12.933220
5054 01:20:12.933562 ==
5055 01:20:12.935705 Dram Type= 6, Freq= 0, CH_0, rank 0
5056 01:20:12.938794 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5057 01:20:12.939261 ==
5058 01:20:12.942204
5059 01:20:12.942755
5060 01:20:12.943124 TX Vref Scan disable
5061 01:20:12.945655 == TX Byte 0 ==
5062 01:20:12.948677 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5063 01:20:12.951804 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5064 01:20:12.955499 == TX Byte 1 ==
5065 01:20:12.958575 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5066 01:20:12.961964 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5067 01:20:12.965675 ==
5068 01:20:12.966290 Dram Type= 6, Freq= 0, CH_0, rank 0
5069 01:20:12.971873 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5070 01:20:12.972443 ==
5071 01:20:12.972881
5072 01:20:12.973232
5073 01:20:12.975199 TX Vref Scan disable
5074 01:20:12.975760 == TX Byte 0 ==
5075 01:20:12.981712 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5076 01:20:12.985246 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5077 01:20:12.985712 == TX Byte 1 ==
5078 01:20:12.991802 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5079 01:20:12.994716 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5080 01:20:12.995182
5081 01:20:12.995551 [DATLAT]
5082 01:20:12.998392 Freq=933, CH0 RK0
5083 01:20:12.998957
5084 01:20:12.999330 DATLAT Default: 0xd
5085 01:20:13.001621 0, 0xFFFF, sum = 0
5086 01:20:13.002237 1, 0xFFFF, sum = 0
5087 01:20:13.004832 2, 0xFFFF, sum = 0
5088 01:20:13.005398 3, 0xFFFF, sum = 0
5089 01:20:13.008101 4, 0xFFFF, sum = 0
5090 01:20:13.008572 5, 0xFFFF, sum = 0
5091 01:20:13.011521 6, 0xFFFF, sum = 0
5092 01:20:13.012092 7, 0xFFFF, sum = 0
5093 01:20:13.014734 8, 0xFFFF, sum = 0
5094 01:20:13.018219 9, 0xFFFF, sum = 0
5095 01:20:13.018782 10, 0x0, sum = 1
5096 01:20:13.019227 11, 0x0, sum = 2
5097 01:20:13.021493 12, 0x0, sum = 3
5098 01:20:13.022241 13, 0x0, sum = 4
5099 01:20:13.024556 best_step = 11
5100 01:20:13.025021
5101 01:20:13.025429 ==
5102 01:20:13.027996 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 01:20:13.031468 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5104 01:20:13.032029 ==
5105 01:20:13.034572 RX Vref Scan: 1
5106 01:20:13.035034
5107 01:20:13.035402 RX Vref 0 -> 0, step: 1
5108 01:20:13.035748
5109 01:20:13.038412 RX Delay -77 -> 252, step: 4
5110 01:20:13.038973
5111 01:20:13.041510 Set Vref, RX VrefLevel [Byte0]: 45
5112 01:20:13.044735 [Byte1]: 48
5113 01:20:13.049155
5114 01:20:13.049715 Final RX Vref Byte 0 = 45 to rank0
5115 01:20:13.052172 Final RX Vref Byte 1 = 48 to rank0
5116 01:20:13.055580 Final RX Vref Byte 0 = 45 to rank1
5117 01:20:13.059116 Final RX Vref Byte 1 = 48 to rank1==
5118 01:20:13.062605 Dram Type= 6, Freq= 0, CH_0, rank 0
5119 01:20:13.069071 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5120 01:20:13.069638 ==
5121 01:20:13.070046 DQS Delay:
5122 01:20:13.072112 DQS0 = 0, DQS1 = 0
5123 01:20:13.072671 DQM Delay:
5124 01:20:13.073044 DQM0 = 96, DQM1 = 87
5125 01:20:13.075079 DQ Delay:
5126 01:20:13.078625 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =92
5127 01:20:13.082005 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =104
5128 01:20:13.085280 DQ8 =78, DQ9 =70, DQ10 =88, DQ11 =78
5129 01:20:13.088452 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =98
5130 01:20:13.088922
5131 01:20:13.089289
5132 01:20:13.095587 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5133 01:20:13.098397 CH0 RK0: MR19=505, MR18=1F1F
5134 01:20:13.105286 CH0_RK0: MR19=0x505, MR18=0x1F1F, DQSOSC=412, MR23=63, INC=63, DEC=42
5135 01:20:13.106127
5136 01:20:13.108343 ----->DramcWriteLeveling(PI) begin...
5137 01:20:13.108931 ==
5138 01:20:13.111847 Dram Type= 6, Freq= 0, CH_0, rank 1
5139 01:20:13.115055 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5140 01:20:13.115630 ==
5141 01:20:13.118289 Write leveling (Byte 0): 30 => 30
5142 01:20:13.121381 Write leveling (Byte 1): 28 => 28
5143 01:20:13.124578 DramcWriteLeveling(PI) end<-----
5144 01:20:13.125078
5145 01:20:13.125451 ==
5146 01:20:13.128113 Dram Type= 6, Freq= 0, CH_0, rank 1
5147 01:20:13.131619 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5148 01:20:13.134584 ==
5149 01:20:13.135048 [Gating] SW mode calibration
5150 01:20:13.144952 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5151 01:20:13.147670 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5152 01:20:13.151211 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 01:20:13.157731 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 01:20:13.161240 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 01:20:13.164581 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 01:20:13.170930 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 01:20:13.174320 0 10 20 | B1->B0 | 2f2f 2f2f | 1 1 | (1 1) (1 1)
5158 01:20:13.177905 0 10 24 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
5159 01:20:13.184545 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 01:20:13.187625 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 01:20:13.191035 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 01:20:13.197347 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 01:20:13.200677 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 01:20:13.204169 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 01:20:13.211261 0 11 20 | B1->B0 | 2b2b 3a3a | 0 0 | (0 0) (0 0)
5166 01:20:13.213979 0 11 24 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
5167 01:20:13.217350 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 01:20:13.223729 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 01:20:13.227468 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 01:20:13.230570 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 01:20:13.237226 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 01:20:13.240468 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 01:20:13.243511 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5174 01:20:13.250125 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5175 01:20:13.253506 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 01:20:13.256848 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 01:20:13.263865 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 01:20:13.267075 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 01:20:13.270240 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 01:20:13.276965 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 01:20:13.279934 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 01:20:13.283312 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 01:20:13.289545 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 01:20:13.293403 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 01:20:13.296470 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 01:20:13.303148 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 01:20:13.306350 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 01:20:13.309846 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 01:20:13.316193 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5190 01:20:13.319485 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5191 01:20:13.322662 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 01:20:13.326065 Total UI for P1: 0, mck2ui 16
5193 01:20:13.329249 best dqsien dly found for B0: ( 0, 14, 22)
5194 01:20:13.333018 Total UI for P1: 0, mck2ui 16
5195 01:20:13.336175 best dqsien dly found for B1: ( 0, 14, 24)
5196 01:20:13.339126 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5197 01:20:13.342757 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
5198 01:20:13.343226
5199 01:20:13.349103 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5200 01:20:13.352531 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 24)
5201 01:20:13.356028 [Gating] SW calibration Done
5202 01:20:13.356550 ==
5203 01:20:13.359147 Dram Type= 6, Freq= 0, CH_0, rank 1
5204 01:20:13.362644 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5205 01:20:13.363221 ==
5206 01:20:13.363815 RX Vref Scan: 0
5207 01:20:13.364197
5208 01:20:13.365911 RX Vref 0 -> 0, step: 1
5209 01:20:13.366407
5210 01:20:13.369301 RX Delay -80 -> 252, step: 8
5211 01:20:13.372240 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5212 01:20:13.375816 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5213 01:20:13.382407 iDelay=200, Bit 2, Center 99 (8 ~ 191) 184
5214 01:20:13.385769 iDelay=200, Bit 3, Center 91 (0 ~ 183) 184
5215 01:20:13.388980 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5216 01:20:13.392307 iDelay=200, Bit 5, Center 83 (-16 ~ 183) 200
5217 01:20:13.395750 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5218 01:20:13.398899 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5219 01:20:13.405459 iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184
5220 01:20:13.409019 iDelay=200, Bit 9, Center 67 (-32 ~ 167) 200
5221 01:20:13.412130 iDelay=200, Bit 10, Center 83 (-16 ~ 183) 200
5222 01:20:13.415317 iDelay=200, Bit 11, Center 75 (-24 ~ 175) 200
5223 01:20:13.418604 iDelay=200, Bit 12, Center 87 (-8 ~ 183) 192
5224 01:20:13.425341 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5225 01:20:13.428692 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5226 01:20:13.431944 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5227 01:20:13.432506 ==
5228 01:20:13.435166 Dram Type= 6, Freq= 0, CH_0, rank 1
5229 01:20:13.438844 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5230 01:20:13.439335 ==
5231 01:20:13.442222 DQS Delay:
5232 01:20:13.442780 DQS0 = 0, DQS1 = 0
5233 01:20:13.445251 DQM Delay:
5234 01:20:13.445798 DQM0 = 96, DQM1 = 83
5235 01:20:13.446236 DQ Delay:
5236 01:20:13.448445 DQ0 =95, DQ1 =99, DQ2 =99, DQ3 =91
5237 01:20:13.451648 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =103
5238 01:20:13.454666 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5239 01:20:13.458153 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =91
5240 01:20:13.458628
5241 01:20:13.458995
5242 01:20:13.461616 ==
5243 01:20:13.464510 Dram Type= 6, Freq= 0, CH_0, rank 1
5244 01:20:13.468207 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5245 01:20:13.468765 ==
5246 01:20:13.469139
5247 01:20:13.469479
5248 01:20:13.471576 TX Vref Scan disable
5249 01:20:13.472096 == TX Byte 0 ==
5250 01:20:13.474793 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5251 01:20:13.481348 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5252 01:20:13.481862 == TX Byte 1 ==
5253 01:20:13.484519 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5254 01:20:13.491874 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5255 01:20:13.492441 ==
5256 01:20:13.494394 Dram Type= 6, Freq= 0, CH_0, rank 1
5257 01:20:13.498001 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5258 01:20:13.498484 ==
5259 01:20:13.498861
5260 01:20:13.499199
5261 01:20:13.501147 TX Vref Scan disable
5262 01:20:13.504648 == TX Byte 0 ==
5263 01:20:13.508175 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5264 01:20:13.511196 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5265 01:20:13.514345 == TX Byte 1 ==
5266 01:20:13.517820 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5267 01:20:13.520953 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5268 01:20:13.521413
5269 01:20:13.524612 [DATLAT]
5270 01:20:13.525297 Freq=933, CH0 RK1
5271 01:20:13.525682
5272 01:20:13.528152 DATLAT Default: 0xb
5273 01:20:13.528609 0, 0xFFFF, sum = 0
5274 01:20:13.530947 1, 0xFFFF, sum = 0
5275 01:20:13.531416 2, 0xFFFF, sum = 0
5276 01:20:13.534219 3, 0xFFFF, sum = 0
5277 01:20:13.534683 4, 0xFFFF, sum = 0
5278 01:20:13.537655 5, 0xFFFF, sum = 0
5279 01:20:13.538145 6, 0xFFFF, sum = 0
5280 01:20:13.540872 7, 0xFFFF, sum = 0
5281 01:20:13.541337 8, 0xFFFF, sum = 0
5282 01:20:13.544403 9, 0xFFFF, sum = 0
5283 01:20:13.544975 10, 0x0, sum = 1
5284 01:20:13.547392 11, 0x0, sum = 2
5285 01:20:13.547872 12, 0x0, sum = 3
5286 01:20:13.550708 13, 0x0, sum = 4
5287 01:20:13.551176 best_step = 11
5288 01:20:13.551564
5289 01:20:13.551932 ==
5290 01:20:13.553905 Dram Type= 6, Freq= 0, CH_0, rank 1
5291 01:20:13.560878 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5292 01:20:13.561445 ==
5293 01:20:13.561861 RX Vref Scan: 0
5294 01:20:13.562277
5295 01:20:13.563948 RX Vref 0 -> 0, step: 1
5296 01:20:13.564405
5297 01:20:13.567312 RX Delay -77 -> 252, step: 4
5298 01:20:13.570664 iDelay=199, Bit 0, Center 94 (7 ~ 182) 176
5299 01:20:13.574196 iDelay=199, Bit 1, Center 100 (7 ~ 194) 188
5300 01:20:13.580548 iDelay=199, Bit 2, Center 96 (7 ~ 186) 180
5301 01:20:13.583793 iDelay=199, Bit 3, Center 92 (7 ~ 178) 172
5302 01:20:13.587077 iDelay=199, Bit 4, Center 100 (11 ~ 190) 180
5303 01:20:13.590868 iDelay=199, Bit 5, Center 92 (-1 ~ 186) 188
5304 01:20:13.593715 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5305 01:20:13.599987 iDelay=199, Bit 7, Center 108 (19 ~ 198) 180
5306 01:20:13.603553 iDelay=199, Bit 8, Center 74 (-13 ~ 162) 176
5307 01:20:13.606663 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5308 01:20:13.610185 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5309 01:20:13.613773 iDelay=199, Bit 11, Center 76 (-9 ~ 162) 172
5310 01:20:13.616878 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5311 01:20:13.623493 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5312 01:20:13.626595 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5313 01:20:13.629980 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5314 01:20:13.630492 ==
5315 01:20:13.633266 Dram Type= 6, Freq= 0, CH_0, rank 1
5316 01:20:13.636909 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5317 01:20:13.637475 ==
5318 01:20:13.640063 DQS Delay:
5319 01:20:13.640633 DQS0 = 0, DQS1 = 0
5320 01:20:13.643579 DQM Delay:
5321 01:20:13.644155 DQM0 = 98, DQM1 = 85
5322 01:20:13.644527 DQ Delay:
5323 01:20:13.646554 DQ0 =94, DQ1 =100, DQ2 =96, DQ3 =92
5324 01:20:13.649746 DQ4 =100, DQ5 =92, DQ6 =104, DQ7 =108
5325 01:20:13.653233 DQ8 =74, DQ9 =72, DQ10 =88, DQ11 =76
5326 01:20:13.659816 DQ12 =94, DQ13 =90, DQ14 =96, DQ15 =96
5327 01:20:13.660378
5328 01:20:13.660744
5329 01:20:13.666331 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c2c, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5330 01:20:13.669655 CH0 RK1: MR19=505, MR18=2C2C
5331 01:20:13.676134 CH0_RK1: MR19=0x505, MR18=0x2C2C, DQSOSC=408, MR23=63, INC=65, DEC=43
5332 01:20:13.679375 [RxdqsGatingPostProcess] freq 933
5333 01:20:13.682777 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5334 01:20:13.685669 Pre-setting of DQS Precalculation
5335 01:20:13.692880 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5336 01:20:13.693454 ==
5337 01:20:13.696248 Dram Type= 6, Freq= 0, CH_1, rank 0
5338 01:20:13.699160 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5339 01:20:13.699687 ==
5340 01:20:13.706215 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5341 01:20:13.712772 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5342 01:20:13.715588 [CA 0] Center 37 (7~68) winsize 62
5343 01:20:13.719060 [CA 1] Center 37 (6~68) winsize 63
5344 01:20:13.722638 [CA 2] Center 34 (4~65) winsize 62
5345 01:20:13.725461 [CA 3] Center 34 (4~65) winsize 62
5346 01:20:13.729074 [CA 4] Center 32 (2~63) winsize 62
5347 01:20:13.732277 [CA 5] Center 33 (3~63) winsize 61
5348 01:20:13.732837
5349 01:20:13.735702 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5350 01:20:13.736263
5351 01:20:13.738554 [CATrainingPosCal] consider 1 rank data
5352 01:20:13.742274 u2DelayCellTimex100 = 270/100 ps
5353 01:20:13.745371 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5354 01:20:13.748822 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5355 01:20:13.752184 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5356 01:20:13.755555 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5357 01:20:13.758852 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5358 01:20:13.762194 CA5 delay=33 (3~63),Diff = 1 PI (6 cell)
5359 01:20:13.762753
5360 01:20:13.768204 CA PerBit enable=1, Macro0, CA PI delay=32
5361 01:20:13.768678
5362 01:20:13.772161 [CBTSetCACLKResult] CA Dly = 32
5363 01:20:13.772617 CS Dly: 5 (0~36)
5364 01:20:13.772979 ==
5365 01:20:13.775039 Dram Type= 6, Freq= 0, CH_1, rank 1
5366 01:20:13.778388 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5367 01:20:13.778867 ==
5368 01:20:13.784719 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5369 01:20:13.791576 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5370 01:20:13.795087 [CA 0] Center 37 (6~68) winsize 63
5371 01:20:13.798301 [CA 1] Center 37 (6~68) winsize 63
5372 01:20:13.801468 [CA 2] Center 34 (4~65) winsize 62
5373 01:20:13.805311 [CA 3] Center 34 (3~65) winsize 63
5374 01:20:13.808732 [CA 4] Center 33 (3~64) winsize 62
5375 01:20:13.811681 [CA 5] Center 33 (3~64) winsize 62
5376 01:20:13.812241
5377 01:20:13.814684 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5378 01:20:13.815141
5379 01:20:13.818167 [CATrainingPosCal] consider 2 rank data
5380 01:20:13.821884 u2DelayCellTimex100 = 270/100 ps
5381 01:20:13.824685 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5382 01:20:13.827788 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5383 01:20:13.831219 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5384 01:20:13.834244 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5385 01:20:13.840964 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5386 01:20:13.844782 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5387 01:20:13.845351
5388 01:20:13.847690 CA PerBit enable=1, Macro0, CA PI delay=33
5389 01:20:13.848145
5390 01:20:13.850851 [CBTSetCACLKResult] CA Dly = 33
5391 01:20:13.851306 CS Dly: 5 (0~37)
5392 01:20:13.851667
5393 01:20:13.854566 ----->DramcWriteLeveling(PI) begin...
5394 01:20:13.855131 ==
5395 01:20:13.857790 Dram Type= 6, Freq= 0, CH_1, rank 0
5396 01:20:13.864539 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5397 01:20:13.865101 ==
5398 01:20:13.867383 Write leveling (Byte 0): 25 => 25
5399 01:20:13.870948 Write leveling (Byte 1): 24 => 24
5400 01:20:13.871506 DramcWriteLeveling(PI) end<-----
5401 01:20:13.871881
5402 01:20:13.874160 ==
5403 01:20:13.877480 Dram Type= 6, Freq= 0, CH_1, rank 0
5404 01:20:13.881005 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5405 01:20:13.881567 ==
5406 01:20:13.883997 [Gating] SW mode calibration
5407 01:20:13.890716 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5408 01:20:13.893871 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5409 01:20:13.900353 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5410 01:20:13.903649 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5411 01:20:13.906818 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5412 01:20:13.913582 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5413 01:20:13.916885 0 10 16 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
5414 01:20:13.920304 0 10 20 | B1->B0 | 3131 2323 | 1 0 | (1 1) (0 0)
5415 01:20:13.926732 0 10 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5416 01:20:13.929953 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5417 01:20:13.933473 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5418 01:20:13.940031 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5419 01:20:13.943385 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5420 01:20:13.946527 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5421 01:20:13.953423 0 11 16 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5422 01:20:13.956746 0 11 20 | B1->B0 | 2828 4545 | 1 0 | (0 0) (0 0)
5423 01:20:13.959650 0 11 24 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5424 01:20:13.966636 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5425 01:20:13.970090 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5426 01:20:13.972951 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5427 01:20:13.979649 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5428 01:20:13.982902 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5429 01:20:13.986257 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5430 01:20:13.992895 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5431 01:20:13.996131 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 01:20:13.999617 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 01:20:14.005804 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 01:20:14.009198 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 01:20:14.012545 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 01:20:14.018964 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 01:20:14.022437 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 01:20:14.025476 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 01:20:14.032421 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 01:20:14.035682 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 01:20:14.038692 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 01:20:14.045582 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 01:20:14.048465 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 01:20:14.052087 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5445 01:20:14.059243 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5446 01:20:14.061919 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5447 01:20:14.065273 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5448 01:20:14.068388 Total UI for P1: 0, mck2ui 16
5449 01:20:14.072087 best dqsien dly found for B0: ( 0, 14, 18)
5450 01:20:14.078642 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5451 01:20:14.081667 Total UI for P1: 0, mck2ui 16
5452 01:20:14.085416 best dqsien dly found for B1: ( 0, 14, 22)
5453 01:20:14.088236 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5454 01:20:14.091585 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5455 01:20:14.092147
5456 01:20:14.095036 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5457 01:20:14.098237 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5458 01:20:14.101443 [Gating] SW calibration Done
5459 01:20:14.102001 ==
5460 01:20:14.104649 Dram Type= 6, Freq= 0, CH_1, rank 0
5461 01:20:14.108392 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5462 01:20:14.108981 ==
5463 01:20:14.111404 RX Vref Scan: 0
5464 01:20:14.111960
5465 01:20:14.114880 RX Vref 0 -> 0, step: 1
5466 01:20:14.115441
5467 01:20:14.115807 RX Delay -80 -> 252, step: 8
5468 01:20:14.121599 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5469 01:20:14.124585 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5470 01:20:14.127847 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5471 01:20:14.130911 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5472 01:20:14.134563 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5473 01:20:14.137694 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5474 01:20:14.144546 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5475 01:20:14.147796 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5476 01:20:14.151217 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5477 01:20:14.154428 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5478 01:20:14.157455 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5479 01:20:14.164182 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5480 01:20:14.167488 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5481 01:20:14.170915 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5482 01:20:14.174552 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5483 01:20:14.177507 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5484 01:20:14.178253 ==
5485 01:20:14.180933 Dram Type= 6, Freq= 0, CH_1, rank 0
5486 01:20:14.187365 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5487 01:20:14.187982 ==
5488 01:20:14.188378 DQS Delay:
5489 01:20:14.190750 DQS0 = 0, DQS1 = 0
5490 01:20:14.191205 DQM Delay:
5491 01:20:14.191571 DQM0 = 96, DQM1 = 87
5492 01:20:14.194001 DQ Delay:
5493 01:20:14.197276 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =95
5494 01:20:14.200552 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5495 01:20:14.203718 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =75
5496 01:20:14.207048 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5497 01:20:14.207610
5498 01:20:14.207977
5499 01:20:14.208318 ==
5500 01:20:14.210603 Dram Type= 6, Freq= 0, CH_1, rank 0
5501 01:20:14.214206 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5502 01:20:14.214771 ==
5503 01:20:14.215141
5504 01:20:14.215481
5505 01:20:14.217113 TX Vref Scan disable
5506 01:20:14.220359 == TX Byte 0 ==
5507 01:20:14.223759 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5508 01:20:14.227628 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5509 01:20:14.229915 == TX Byte 1 ==
5510 01:20:14.233634 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5511 01:20:14.236809 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5512 01:20:14.237369 ==
5513 01:20:14.240023 Dram Type= 6, Freq= 0, CH_1, rank 0
5514 01:20:14.243328 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5515 01:20:14.246562 ==
5516 01:20:14.247120
5517 01:20:14.247488
5518 01:20:14.247830 TX Vref Scan disable
5519 01:20:14.250098 == TX Byte 0 ==
5520 01:20:14.253671 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5521 01:20:14.259999 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5522 01:20:14.260466 == TX Byte 1 ==
5523 01:20:14.263679 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5524 01:20:14.269933 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5525 01:20:14.270520
5526 01:20:14.270894 [DATLAT]
5527 01:20:14.271240 Freq=933, CH1 RK0
5528 01:20:14.271571
5529 01:20:14.273430 DATLAT Default: 0xd
5530 01:20:14.273984 0, 0xFFFF, sum = 0
5531 01:20:14.276717 1, 0xFFFF, sum = 0
5532 01:20:14.279736 2, 0xFFFF, sum = 0
5533 01:20:14.280225 3, 0xFFFF, sum = 0
5534 01:20:14.283244 4, 0xFFFF, sum = 0
5535 01:20:14.283813 5, 0xFFFF, sum = 0
5536 01:20:14.286664 6, 0xFFFF, sum = 0
5537 01:20:14.287143 7, 0xFFFF, sum = 0
5538 01:20:14.289773 8, 0xFFFF, sum = 0
5539 01:20:14.290383 9, 0xFFFF, sum = 0
5540 01:20:14.293443 10, 0x0, sum = 1
5541 01:20:14.294013 11, 0x0, sum = 2
5542 01:20:14.296449 12, 0x0, sum = 3
5543 01:20:14.297021 13, 0x0, sum = 4
5544 01:20:14.300066 best_step = 11
5545 01:20:14.300676
5546 01:20:14.301241 ==
5547 01:20:14.303036 Dram Type= 6, Freq= 0, CH_1, rank 0
5548 01:20:14.305994 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5549 01:20:14.306493 ==
5550 01:20:14.306861 RX Vref Scan: 1
5551 01:20:14.307205
5552 01:20:14.309544 RX Vref 0 -> 0, step: 1
5553 01:20:14.310146
5554 01:20:14.313251 RX Delay -69 -> 252, step: 4
5555 01:20:14.313812
5556 01:20:14.315978 Set Vref, RX VrefLevel [Byte0]: 54
5557 01:20:14.319598 [Byte1]: 50
5558 01:20:14.322958
5559 01:20:14.323515 Final RX Vref Byte 0 = 54 to rank0
5560 01:20:14.326202 Final RX Vref Byte 1 = 50 to rank0
5561 01:20:14.329196 Final RX Vref Byte 0 = 54 to rank1
5562 01:20:14.332836 Final RX Vref Byte 1 = 50 to rank1==
5563 01:20:14.335986 Dram Type= 6, Freq= 0, CH_1, rank 0
5564 01:20:14.342702 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5565 01:20:14.343269 ==
5566 01:20:14.343640 DQS Delay:
5567 01:20:14.345789 DQS0 = 0, DQS1 = 0
5568 01:20:14.346301 DQM Delay:
5569 01:20:14.346677 DQM0 = 94, DQM1 = 88
5570 01:20:14.349008 DQ Delay:
5571 01:20:14.352204 DQ0 =96, DQ1 =88, DQ2 =86, DQ3 =92
5572 01:20:14.355439 DQ4 =94, DQ5 =104, DQ6 =102, DQ7 =90
5573 01:20:14.358830 DQ8 =72, DQ9 =76, DQ10 =90, DQ11 =80
5574 01:20:14.362757 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =96
5575 01:20:14.363229
5576 01:20:14.363599
5577 01:20:14.368821 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e2e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5578 01:20:14.372519 CH1 RK0: MR19=505, MR18=2E2E
5579 01:20:14.378627 CH1_RK0: MR19=0x505, MR18=0x2E2E, DQSOSC=407, MR23=63, INC=65, DEC=43
5580 01:20:14.379180
5581 01:20:14.381988 ----->DramcWriteLeveling(PI) begin...
5582 01:20:14.382501 ==
5583 01:20:14.385427 Dram Type= 6, Freq= 0, CH_1, rank 1
5584 01:20:14.388531 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5585 01:20:14.389005 ==
5586 01:20:14.392100 Write leveling (Byte 0): 26 => 26
5587 01:20:14.395573 Write leveling (Byte 1): 26 => 26
5588 01:20:14.398653 DramcWriteLeveling(PI) end<-----
5589 01:20:14.399126
5590 01:20:14.399511 ==
5591 01:20:14.401881 Dram Type= 6, Freq= 0, CH_1, rank 1
5592 01:20:14.405081 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5593 01:20:14.408653 ==
5594 01:20:14.409228 [Gating] SW mode calibration
5595 01:20:14.418207 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5596 01:20:14.421737 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5597 01:20:14.424907 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 01:20:14.431892 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 01:20:14.434649 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 01:20:14.438182 0 10 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5601 01:20:14.444768 0 10 16 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
5602 01:20:14.448670 0 10 20 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
5603 01:20:14.451790 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 01:20:14.458302 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 01:20:14.461527 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 01:20:14.464603 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 01:20:14.471151 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 01:20:14.474648 0 11 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5609 01:20:14.477806 0 11 16 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (1 1)
5610 01:20:14.484792 0 11 20 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
5611 01:20:14.487881 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 01:20:14.491445 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 01:20:14.497986 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 01:20:14.501150 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 01:20:14.504869 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 01:20:14.511188 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 01:20:14.514591 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5618 01:20:14.517702 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5619 01:20:14.524306 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 01:20:14.527547 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 01:20:14.530978 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 01:20:14.538177 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 01:20:14.540978 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 01:20:14.544368 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 01:20:14.550534 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 01:20:14.554260 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 01:20:14.557150 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 01:20:14.564336 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 01:20:14.567091 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 01:20:14.570537 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 01:20:14.577609 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 01:20:14.580555 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5633 01:20:14.584339 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 01:20:14.590501 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5635 01:20:14.591082 Total UI for P1: 0, mck2ui 16
5636 01:20:14.593579 best dqsien dly found for B0: ( 0, 14, 18)
5637 01:20:14.600550 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 01:20:14.604306 Total UI for P1: 0, mck2ui 16
5639 01:20:14.606988 best dqsien dly found for B1: ( 0, 14, 20)
5640 01:20:14.610645 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5641 01:20:14.613871 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5642 01:20:14.614494
5643 01:20:14.617134 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5644 01:20:14.620207 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5645 01:20:14.623590 [Gating] SW calibration Done
5646 01:20:14.624162 ==
5647 01:20:14.626780 Dram Type= 6, Freq= 0, CH_1, rank 1
5648 01:20:14.630007 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5649 01:20:14.633648 ==
5650 01:20:14.634274 RX Vref Scan: 0
5651 01:20:14.634658
5652 01:20:14.636938 RX Vref 0 -> 0, step: 1
5653 01:20:14.637508
5654 01:20:14.640153 RX Delay -80 -> 252, step: 8
5655 01:20:14.643504 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5656 01:20:14.646610 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5657 01:20:14.649825 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5658 01:20:14.653255 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5659 01:20:14.656515 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5660 01:20:14.663130 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5661 01:20:14.666696 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5662 01:20:14.669516 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5663 01:20:14.672994 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5664 01:20:14.676552 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5665 01:20:14.682655 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5666 01:20:14.686538 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5667 01:20:14.689310 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5668 01:20:14.692955 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5669 01:20:14.696255 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5670 01:20:14.699499 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5671 01:20:14.702859 ==
5672 01:20:14.706232 Dram Type= 6, Freq= 0, CH_1, rank 1
5673 01:20:14.709512 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5674 01:20:14.710106 ==
5675 01:20:14.710484 DQS Delay:
5676 01:20:14.712860 DQS0 = 0, DQS1 = 0
5677 01:20:14.713418 DQM Delay:
5678 01:20:14.716124 DQM0 = 95, DQM1 = 89
5679 01:20:14.716683 DQ Delay:
5680 01:20:14.719286 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =91
5681 01:20:14.722501 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5682 01:20:14.725957 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5683 01:20:14.729183 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =95
5684 01:20:14.729753
5685 01:20:14.730187
5686 01:20:14.730543 ==
5687 01:20:14.732465 Dram Type= 6, Freq= 0, CH_1, rank 1
5688 01:20:14.736078 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5689 01:20:14.736656 ==
5690 01:20:14.737031
5691 01:20:14.737381
5692 01:20:14.739086 TX Vref Scan disable
5693 01:20:14.742331 == TX Byte 0 ==
5694 01:20:14.746115 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5695 01:20:14.749894 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5696 01:20:14.752838 == TX Byte 1 ==
5697 01:20:14.755738 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5698 01:20:14.759356 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5699 01:20:14.759933 ==
5700 01:20:14.762345 Dram Type= 6, Freq= 0, CH_1, rank 1
5701 01:20:14.769436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5702 01:20:14.770162 ==
5703 01:20:14.770641
5704 01:20:14.770997
5705 01:20:14.771331 TX Vref Scan disable
5706 01:20:14.772862 == TX Byte 0 ==
5707 01:20:14.776202 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5708 01:20:14.782851 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5709 01:20:14.783433 == TX Byte 1 ==
5710 01:20:14.785994 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5711 01:20:14.793005 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5712 01:20:14.793631
5713 01:20:14.794051 [DATLAT]
5714 01:20:14.794413 Freq=933, CH1 RK1
5715 01:20:14.794756
5716 01:20:14.795713 DATLAT Default: 0xb
5717 01:20:14.799409 0, 0xFFFF, sum = 0
5718 01:20:14.799981 1, 0xFFFF, sum = 0
5719 01:20:14.803119 2, 0xFFFF, sum = 0
5720 01:20:14.803685 3, 0xFFFF, sum = 0
5721 01:20:14.805792 4, 0xFFFF, sum = 0
5722 01:20:14.806328 5, 0xFFFF, sum = 0
5723 01:20:14.809245 6, 0xFFFF, sum = 0
5724 01:20:14.809894 7, 0xFFFF, sum = 0
5725 01:20:14.812606 8, 0xFFFF, sum = 0
5726 01:20:14.813182 9, 0xFFFF, sum = 0
5727 01:20:14.816364 10, 0x0, sum = 1
5728 01:20:14.816836 11, 0x0, sum = 2
5729 01:20:14.819235 12, 0x0, sum = 3
5730 01:20:14.819705 13, 0x0, sum = 4
5731 01:20:14.822387 best_step = 11
5732 01:20:14.822957
5733 01:20:14.823336 ==
5734 01:20:14.825674 Dram Type= 6, Freq= 0, CH_1, rank 1
5735 01:20:14.828851 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5736 01:20:14.829418 ==
5737 01:20:14.829795 RX Vref Scan: 0
5738 01:20:14.830207
5739 01:20:14.831992 RX Vref 0 -> 0, step: 1
5740 01:20:14.832999
5741 01:20:14.835829 RX Delay -61 -> 252, step: 4
5742 01:20:14.842483 iDelay=203, Bit 0, Center 96 (3 ~ 190) 188
5743 01:20:14.845607 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188
5744 01:20:14.849550 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5745 01:20:14.852150 iDelay=203, Bit 3, Center 94 (3 ~ 186) 184
5746 01:20:14.855038 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5747 01:20:14.858584 iDelay=203, Bit 5, Center 108 (15 ~ 202) 188
5748 01:20:14.865222 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5749 01:20:14.868351 iDelay=203, Bit 7, Center 92 (-1 ~ 186) 188
5750 01:20:14.871997 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5751 01:20:14.875121 iDelay=203, Bit 9, Center 78 (-13 ~ 170) 184
5752 01:20:14.878413 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5753 01:20:14.885763 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5754 01:20:14.888056 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5755 01:20:14.891789 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5756 01:20:14.894802 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5757 01:20:14.898270 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5758 01:20:14.898739 ==
5759 01:20:14.901778 Dram Type= 6, Freq= 0, CH_1, rank 1
5760 01:20:14.908150 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5761 01:20:14.908715 ==
5762 01:20:14.909092 DQS Delay:
5763 01:20:14.911218 DQS0 = 0, DQS1 = 0
5764 01:20:14.911686 DQM Delay:
5765 01:20:14.914638 DQM0 = 96, DQM1 = 87
5766 01:20:14.915120 DQ Delay:
5767 01:20:14.917885 DQ0 =96, DQ1 =92, DQ2 =88, DQ3 =94
5768 01:20:14.921351 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =92
5769 01:20:14.924873 DQ8 =74, DQ9 =78, DQ10 =88, DQ11 =80
5770 01:20:14.928232 DQ12 =96, DQ13 =96, DQ14 =94, DQ15 =96
5771 01:20:14.928798
5772 01:20:14.929171
5773 01:20:14.934695 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5774 01:20:14.937933 CH1 RK1: MR19=505, MR18=1D1D
5775 01:20:14.944669 CH1_RK1: MR19=0x505, MR18=0x1D1D, DQSOSC=412, MR23=63, INC=63, DEC=42
5776 01:20:14.947661 [RxdqsGatingPostProcess] freq 933
5777 01:20:14.954894 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5778 01:20:14.955466 Pre-setting of DQS Precalculation
5779 01:20:14.960637 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5780 01:20:14.967312 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5781 01:20:14.974393 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5782 01:20:14.974964
5783 01:20:14.975389
5784 01:20:14.977460 [Calibration Summary] 1866 Mbps
5785 01:20:14.980524 CH 0, Rank 0
5786 01:20:14.980983 SW Impedance : PASS
5787 01:20:14.983904 DUTY Scan : NO K
5788 01:20:14.987640 ZQ Calibration : PASS
5789 01:20:14.988310 Jitter Meter : NO K
5790 01:20:14.990725 CBT Training : PASS
5791 01:20:14.994134 Write leveling : PASS
5792 01:20:14.994707 RX DQS gating : PASS
5793 01:20:14.997528 RX DQ/DQS(RDDQC) : PASS
5794 01:20:15.000878 TX DQ/DQS : PASS
5795 01:20:15.001499 RX DATLAT : PASS
5796 01:20:15.004168 RX DQ/DQS(Engine): PASS
5797 01:20:15.004751 TX OE : NO K
5798 01:20:15.007144 All Pass.
5799 01:20:15.007611
5800 01:20:15.007980 CH 0, Rank 1
5801 01:20:15.010506 SW Impedance : PASS
5802 01:20:15.010975 DUTY Scan : NO K
5803 01:20:15.014118 ZQ Calibration : PASS
5804 01:20:15.016857 Jitter Meter : NO K
5805 01:20:15.017326 CBT Training : PASS
5806 01:20:15.020339 Write leveling : PASS
5807 01:20:15.023549 RX DQS gating : PASS
5808 01:20:15.024016 RX DQ/DQS(RDDQC) : PASS
5809 01:20:15.026926 TX DQ/DQS : PASS
5810 01:20:15.030610 RX DATLAT : PASS
5811 01:20:15.031185 RX DQ/DQS(Engine): PASS
5812 01:20:15.034153 TX OE : NO K
5813 01:20:15.034645 All Pass.
5814 01:20:15.035024
5815 01:20:15.037185 CH 1, Rank 0
5816 01:20:15.037754 SW Impedance : PASS
5817 01:20:15.040378 DUTY Scan : NO K
5818 01:20:15.043919 ZQ Calibration : PASS
5819 01:20:15.044495 Jitter Meter : NO K
5820 01:20:15.046849 CBT Training : PASS
5821 01:20:15.050192 Write leveling : PASS
5822 01:20:15.050731 RX DQS gating : PASS
5823 01:20:15.053650 RX DQ/DQS(RDDQC) : PASS
5824 01:20:15.056944 TX DQ/DQS : PASS
5825 01:20:15.057416 RX DATLAT : PASS
5826 01:20:15.060689 RX DQ/DQS(Engine): PASS
5827 01:20:15.063500 TX OE : NO K
5828 01:20:15.064074 All Pass.
5829 01:20:15.064452
5830 01:20:15.064797 CH 1, Rank 1
5831 01:20:15.066481 SW Impedance : PASS
5832 01:20:15.070138 DUTY Scan : NO K
5833 01:20:15.070729 ZQ Calibration : PASS
5834 01:20:15.073692 Jitter Meter : NO K
5835 01:20:15.074312 CBT Training : PASS
5836 01:20:15.077288 Write leveling : PASS
5837 01:20:15.080275 RX DQS gating : PASS
5838 01:20:15.080847 RX DQ/DQS(RDDQC) : PASS
5839 01:20:15.083322 TX DQ/DQS : PASS
5840 01:20:15.086714 RX DATLAT : PASS
5841 01:20:15.087286 RX DQ/DQS(Engine): PASS
5842 01:20:15.089876 TX OE : NO K
5843 01:20:15.090384 All Pass.
5844 01:20:15.090758
5845 01:20:15.093235 DramC Write-DBI off
5846 01:20:15.097277 PER_BANK_REFRESH: Hybrid Mode
5847 01:20:15.097839 TX_TRACKING: ON
5848 01:20:15.106237 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5849 01:20:15.109854 [FAST_K] Save calibration result to emmc
5850 01:20:15.113071 dramc_set_vcore_voltage set vcore to 650000
5851 01:20:15.116548 Read voltage for 400, 6
5852 01:20:15.117123 Vio18 = 0
5853 01:20:15.119659 Vcore = 650000
5854 01:20:15.120239 Vdram = 0
5855 01:20:15.120615 Vddq = 0
5856 01:20:15.120954 Vmddr = 0
5857 01:20:15.125889 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5858 01:20:15.132700 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5859 01:20:15.133161 MEM_TYPE=3, freq_sel=20
5860 01:20:15.135810 sv_algorithm_assistance_LP4_800
5861 01:20:15.139400 ============ PULL DRAM RESETB DOWN ============
5862 01:20:15.146189 ========== PULL DRAM RESETB DOWN end =========
5863 01:20:15.149104 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5864 01:20:15.152742 ===================================
5865 01:20:15.155738 LPDDR4 DRAM CONFIGURATION
5866 01:20:15.159541 ===================================
5867 01:20:15.160127 EX_ROW_EN[0] = 0x0
5868 01:20:15.162380 EX_ROW_EN[1] = 0x0
5869 01:20:15.162866 LP4Y_EN = 0x0
5870 01:20:15.165900 WORK_FSP = 0x0
5871 01:20:15.166532 WL = 0x2
5872 01:20:15.169238 RL = 0x2
5873 01:20:15.169736 BL = 0x2
5874 01:20:15.172500 RPST = 0x0
5875 01:20:15.173078 RD_PRE = 0x0
5876 01:20:15.176169 WR_PRE = 0x1
5877 01:20:15.179058 WR_PST = 0x0
5878 01:20:15.179634 DBI_WR = 0x0
5879 01:20:15.183093 DBI_RD = 0x0
5880 01:20:15.183669 OTF = 0x1
5881 01:20:15.186139 ===================================
5882 01:20:15.188921 ===================================
5883 01:20:15.189411 ANA top config
5884 01:20:15.192722 ===================================
5885 01:20:15.195764 DLL_ASYNC_EN = 0
5886 01:20:15.199054 ALL_SLAVE_EN = 1
5887 01:20:15.202348 NEW_RANK_MODE = 1
5888 01:20:15.206291 DLL_IDLE_MODE = 1
5889 01:20:15.206882 LP45_APHY_COMB_EN = 1
5890 01:20:15.208713 TX_ODT_DIS = 1
5891 01:20:15.212223 NEW_8X_MODE = 1
5892 01:20:15.215311 ===================================
5893 01:20:15.218584 ===================================
5894 01:20:15.221994 data_rate = 800
5895 01:20:15.225063 CKR = 1
5896 01:20:15.228566 DQ_P2S_RATIO = 4
5897 01:20:15.231955 ===================================
5898 01:20:15.232534 CA_P2S_RATIO = 4
5899 01:20:15.235074 DQ_CA_OPEN = 0
5900 01:20:15.238543 DQ_SEMI_OPEN = 1
5901 01:20:15.241789 CA_SEMI_OPEN = 1
5902 01:20:15.245226 CA_FULL_RATE = 0
5903 01:20:15.248573 DQ_CKDIV4_EN = 0
5904 01:20:15.249198 CA_CKDIV4_EN = 1
5905 01:20:15.252100 CA_PREDIV_EN = 0
5906 01:20:15.255018 PH8_DLY = 0
5907 01:20:15.258296 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5908 01:20:15.261778 DQ_AAMCK_DIV = 0
5909 01:20:15.264922 CA_AAMCK_DIV = 0
5910 01:20:15.265573 CA_ADMCK_DIV = 4
5911 01:20:15.268320 DQ_TRACK_CA_EN = 0
5912 01:20:15.271425 CA_PICK = 800
5913 01:20:15.274956 CA_MCKIO = 400
5914 01:20:15.278126 MCKIO_SEMI = 400
5915 01:20:15.281692 PLL_FREQ = 3016
5916 01:20:15.284912 DQ_UI_PI_RATIO = 32
5917 01:20:15.288136 CA_UI_PI_RATIO = 32
5918 01:20:15.291432 ===================================
5919 01:20:15.291938 ===================================
5920 01:20:15.294941 memory_type:LPDDR4
5921 01:20:15.298230 GP_NUM : 10
5922 01:20:15.298798 SRAM_EN : 1
5923 01:20:15.301425 MD32_EN : 0
5924 01:20:15.304364 ===================================
5925 01:20:15.307916 [ANA_INIT] >>>>>>>>>>>>>>
5926 01:20:15.311252 <<<<<< [CONFIGURE PHASE]: ANA_TX
5927 01:20:15.314409 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5928 01:20:15.317775 ===================================
5929 01:20:15.321360 data_rate = 800,PCW = 0X7400
5930 01:20:15.324235 ===================================
5931 01:20:15.327982 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5932 01:20:15.330865 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5933 01:20:15.344227 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5934 01:20:15.347545 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5935 01:20:15.350729 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5936 01:20:15.353985 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5937 01:20:15.357687 [ANA_INIT] flow start
5938 01:20:15.358303 [ANA_INIT] PLL >>>>>>>>
5939 01:20:15.360684 [ANA_INIT] PLL <<<<<<<<
5940 01:20:15.364120 [ANA_INIT] MIDPI >>>>>>>>
5941 01:20:15.367394 [ANA_INIT] MIDPI <<<<<<<<
5942 01:20:15.367972 [ANA_INIT] DLL >>>>>>>>
5943 01:20:15.370682 [ANA_INIT] flow end
5944 01:20:15.374273 ============ LP4 DIFF to SE enter ============
5945 01:20:15.377369 ============ LP4 DIFF to SE exit ============
5946 01:20:15.380846 [ANA_INIT] <<<<<<<<<<<<<
5947 01:20:15.384044 [Flow] Enable top DCM control >>>>>
5948 01:20:15.387186 [Flow] Enable top DCM control <<<<<
5949 01:20:15.390771 Enable DLL master slave shuffle
5950 01:20:15.397122 ==============================================================
5951 01:20:15.397687 Gating Mode config
5952 01:20:15.403761 ==============================================================
5953 01:20:15.404326 Config description:
5954 01:20:15.413888 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5955 01:20:15.420258 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5956 01:20:15.427125 SELPH_MODE 0: By rank 1: By Phase
5957 01:20:15.430203 ==============================================================
5958 01:20:15.433415 GAT_TRACK_EN = 0
5959 01:20:15.436594 RX_GATING_MODE = 2
5960 01:20:15.440294 RX_GATING_TRACK_MODE = 2
5961 01:20:15.443698 SELPH_MODE = 1
5962 01:20:15.446614 PICG_EARLY_EN = 1
5963 01:20:15.449674 VALID_LAT_VALUE = 1
5964 01:20:15.456810 ==============================================================
5965 01:20:15.460273 Enter into Gating configuration >>>>
5966 01:20:15.463009 Exit from Gating configuration <<<<
5967 01:20:15.466314 Enter into DVFS_PRE_config >>>>>
5968 01:20:15.476486 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5969 01:20:15.479926 Exit from DVFS_PRE_config <<<<<
5970 01:20:15.482945 Enter into PICG configuration >>>>
5971 01:20:15.486706 Exit from PICG configuration <<<<
5972 01:20:15.489407 [RX_INPUT] configuration >>>>>
5973 01:20:15.489869 [RX_INPUT] configuration <<<<<
5974 01:20:15.496135 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5975 01:20:15.502723 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5976 01:20:15.506458 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5977 01:20:15.512781 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5978 01:20:15.519292 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5979 01:20:15.525828 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5980 01:20:15.529090 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5981 01:20:15.532493 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5982 01:20:15.540027 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5983 01:20:15.543092 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5984 01:20:15.545929 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5985 01:20:15.552666 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5986 01:20:15.556187 ===================================
5987 01:20:15.556806 LPDDR4 DRAM CONFIGURATION
5988 01:20:15.559101 ===================================
5989 01:20:15.562319 EX_ROW_EN[0] = 0x0
5990 01:20:15.562996 EX_ROW_EN[1] = 0x0
5991 01:20:15.565727 LP4Y_EN = 0x0
5992 01:20:15.566221 WORK_FSP = 0x0
5993 01:20:15.569361 WL = 0x2
5994 01:20:15.572252 RL = 0x2
5995 01:20:15.572758 BL = 0x2
5996 01:20:15.576052 RPST = 0x0
5997 01:20:15.576605 RD_PRE = 0x0
5998 01:20:15.578898 WR_PRE = 0x1
5999 01:20:15.579354 WR_PST = 0x0
6000 01:20:15.582246 DBI_WR = 0x0
6001 01:20:15.582725 DBI_RD = 0x0
6002 01:20:15.585603 OTF = 0x1
6003 01:20:15.588832 ===================================
6004 01:20:15.592453 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6005 01:20:15.595433 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6006 01:20:15.602346 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6007 01:20:15.605564 ===================================
6008 01:20:15.606175 LPDDR4 DRAM CONFIGURATION
6009 01:20:15.608563 ===================================
6010 01:20:15.612099 EX_ROW_EN[0] = 0x10
6011 01:20:15.612662 EX_ROW_EN[1] = 0x0
6012 01:20:15.615242 LP4Y_EN = 0x0
6013 01:20:15.618864 WORK_FSP = 0x0
6014 01:20:15.619431 WL = 0x2
6015 01:20:15.622180 RL = 0x2
6016 01:20:15.622749 BL = 0x2
6017 01:20:15.625427 RPST = 0x0
6018 01:20:15.625982 RD_PRE = 0x0
6019 01:20:15.628292 WR_PRE = 0x1
6020 01:20:15.628750 WR_PST = 0x0
6021 01:20:15.631843 DBI_WR = 0x0
6022 01:20:15.632301 DBI_RD = 0x0
6023 01:20:15.635108 OTF = 0x1
6024 01:20:15.638401 ===================================
6025 01:20:15.645152 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6026 01:20:15.648395 nWR fixed to 30
6027 01:20:15.648957 [ModeRegInit_LP4] CH0 RK0
6028 01:20:15.651670 [ModeRegInit_LP4] CH0 RK1
6029 01:20:15.655110 [ModeRegInit_LP4] CH1 RK0
6030 01:20:15.657963 [ModeRegInit_LP4] CH1 RK1
6031 01:20:15.658469 match AC timing 18
6032 01:20:15.661518 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6033 01:20:15.668047 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6034 01:20:15.671196 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6035 01:20:15.677990 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6036 01:20:15.681679 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6037 01:20:15.682286 ==
6038 01:20:15.684821 Dram Type= 6, Freq= 0, CH_0, rank 0
6039 01:20:15.687949 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6040 01:20:15.688440 ==
6041 01:20:15.694616 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6042 01:20:15.701012 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6043 01:20:15.704793 [CA 0] Center 36 (8~64) winsize 57
6044 01:20:15.707693 [CA 1] Center 36 (8~64) winsize 57
6045 01:20:15.708260 [CA 2] Center 36 (8~64) winsize 57
6046 01:20:15.711381 [CA 3] Center 36 (8~64) winsize 57
6047 01:20:15.714195 [CA 4] Center 36 (8~64) winsize 57
6048 01:20:15.717177 [CA 5] Center 36 (8~64) winsize 57
6049 01:20:15.717639
6050 01:20:15.720411 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6051 01:20:15.724079
6052 01:20:15.727417 [CATrainingPosCal] consider 1 rank data
6053 01:20:15.730549 u2DelayCellTimex100 = 270/100 ps
6054 01:20:15.734117 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6055 01:20:15.737218 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6056 01:20:15.740361 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6057 01:20:15.743900 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6058 01:20:15.747177 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6059 01:20:15.750400 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6060 01:20:15.750857
6061 01:20:15.753787 CA PerBit enable=1, Macro0, CA PI delay=36
6062 01:20:15.754434
6063 01:20:15.757287 [CBTSetCACLKResult] CA Dly = 36
6064 01:20:15.760592 CS Dly: 1 (0~32)
6065 01:20:15.761163 ==
6066 01:20:15.763705 Dram Type= 6, Freq= 0, CH_0, rank 1
6067 01:20:15.766917 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6068 01:20:15.767385 ==
6069 01:20:15.773524 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6070 01:20:15.780024 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6071 01:20:15.780595 [CA 0] Center 36 (8~64) winsize 57
6072 01:20:15.783382 [CA 1] Center 36 (8~64) winsize 57
6073 01:20:15.786954 [CA 2] Center 36 (8~64) winsize 57
6074 01:20:15.790174 [CA 3] Center 36 (8~64) winsize 57
6075 01:20:15.793946 [CA 4] Center 36 (8~64) winsize 57
6076 01:20:15.796663 [CA 5] Center 36 (8~64) winsize 57
6077 01:20:15.797266
6078 01:20:15.799936 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6079 01:20:15.800586
6080 01:20:15.803069 [CATrainingPosCal] consider 2 rank data
6081 01:20:15.806581 u2DelayCellTimex100 = 270/100 ps
6082 01:20:15.809862 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6083 01:20:15.816801 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6084 01:20:15.819689 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6085 01:20:15.822896 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6086 01:20:15.826426 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6087 01:20:15.829708 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6088 01:20:15.830211
6089 01:20:15.833027 CA PerBit enable=1, Macro0, CA PI delay=36
6090 01:20:15.833595
6091 01:20:15.836376 [CBTSetCACLKResult] CA Dly = 36
6092 01:20:15.836956 CS Dly: 1 (0~32)
6093 01:20:15.839429
6094 01:20:15.843188 ----->DramcWriteLeveling(PI) begin...
6095 01:20:15.843761 ==
6096 01:20:15.845955 Dram Type= 6, Freq= 0, CH_0, rank 0
6097 01:20:15.849731 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6098 01:20:15.850352 ==
6099 01:20:15.853107 Write leveling (Byte 0): 32 => 0
6100 01:20:15.856330 Write leveling (Byte 1): 32 => 0
6101 01:20:15.859475 DramcWriteLeveling(PI) end<-----
6102 01:20:15.860047
6103 01:20:15.860422 ==
6104 01:20:15.862779 Dram Type= 6, Freq= 0, CH_0, rank 0
6105 01:20:15.866113 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6106 01:20:15.866699 ==
6107 01:20:15.869413 [Gating] SW mode calibration
6108 01:20:15.875838 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6109 01:20:15.882611 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6110 01:20:15.885866 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6111 01:20:15.889342 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6112 01:20:15.895798 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6113 01:20:15.898955 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6114 01:20:15.902183 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6115 01:20:15.909100 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6116 01:20:15.912405 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6117 01:20:15.915867 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6118 01:20:15.922253 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6119 01:20:15.922824 Total UI for P1: 0, mck2ui 16
6120 01:20:15.928907 best dqsien dly found for B0: ( 0, 10, 16)
6121 01:20:15.929482 Total UI for P1: 0, mck2ui 16
6122 01:20:15.932205 best dqsien dly found for B1: ( 0, 10, 24)
6123 01:20:15.938580 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6124 01:20:15.941725 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6125 01:20:15.942229
6126 01:20:15.945387 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6127 01:20:15.948651 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6128 01:20:15.951922 [Gating] SW calibration Done
6129 01:20:15.952486 ==
6130 01:20:15.954827 Dram Type= 6, Freq= 0, CH_0, rank 0
6131 01:20:15.958384 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6132 01:20:15.958956 ==
6133 01:20:15.961609 RX Vref Scan: 0
6134 01:20:15.962116
6135 01:20:15.962501 RX Vref 0 -> 0, step: 1
6136 01:20:15.965417
6137 01:20:15.965975 RX Delay -410 -> 252, step: 16
6138 01:20:15.971479 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6139 01:20:15.974690 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6140 01:20:15.978172 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6141 01:20:15.981675 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6142 01:20:15.988051 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6143 01:20:15.991044 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6144 01:20:15.994618 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6145 01:20:16.001357 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6146 01:20:16.004192 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6147 01:20:16.007824 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6148 01:20:16.010927 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6149 01:20:16.018000 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6150 01:20:16.021248 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6151 01:20:16.024357 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6152 01:20:16.027543 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6153 01:20:16.034460 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6154 01:20:16.035021 ==
6155 01:20:16.037349 Dram Type= 6, Freq= 0, CH_0, rank 0
6156 01:20:16.040797 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6157 01:20:16.041259 ==
6158 01:20:16.041623 DQS Delay:
6159 01:20:16.044298 DQS0 = 43, DQS1 = 59
6160 01:20:16.044894 DQM Delay:
6161 01:20:16.047561 DQM0 = 5, DQM1 = 13
6162 01:20:16.048126 DQ Delay:
6163 01:20:16.050702 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6164 01:20:16.054112 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6165 01:20:16.057460 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6166 01:20:16.061003 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6167 01:20:16.061565
6168 01:20:16.061931
6169 01:20:16.062338 ==
6170 01:20:16.063990 Dram Type= 6, Freq= 0, CH_0, rank 0
6171 01:20:16.067362 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6172 01:20:16.067924 ==
6173 01:20:16.068297
6174 01:20:16.068637
6175 01:20:16.070404 TX Vref Scan disable
6176 01:20:16.073798 == TX Byte 0 ==
6177 01:20:16.076939 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6178 01:20:16.080393 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6179 01:20:16.083775 == TX Byte 1 ==
6180 01:20:16.087436 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6181 01:20:16.090706 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6182 01:20:16.091275 ==
6183 01:20:16.093832 Dram Type= 6, Freq= 0, CH_0, rank 0
6184 01:20:16.096934 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6185 01:20:16.100562 ==
6186 01:20:16.101134
6187 01:20:16.101502
6188 01:20:16.101846 TX Vref Scan disable
6189 01:20:16.103943 == TX Byte 0 ==
6190 01:20:16.106856 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6191 01:20:16.110007 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6192 01:20:16.113438 == TX Byte 1 ==
6193 01:20:16.117063 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6194 01:20:16.120113 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6195 01:20:16.120837
6196 01:20:16.123149 [DATLAT]
6197 01:20:16.123608 Freq=400, CH0 RK0
6198 01:20:16.123977
6199 01:20:16.126617 DATLAT Default: 0xf
6200 01:20:16.127079 0, 0xFFFF, sum = 0
6201 01:20:16.129971 1, 0xFFFF, sum = 0
6202 01:20:16.130592 2, 0xFFFF, sum = 0
6203 01:20:16.133018 3, 0xFFFF, sum = 0
6204 01:20:16.133485 4, 0xFFFF, sum = 0
6205 01:20:16.136514 5, 0xFFFF, sum = 0
6206 01:20:16.137090 6, 0xFFFF, sum = 0
6207 01:20:16.139656 7, 0xFFFF, sum = 0
6208 01:20:16.140324 8, 0xFFFF, sum = 0
6209 01:20:16.143130 9, 0xFFFF, sum = 0
6210 01:20:16.146547 10, 0xFFFF, sum = 0
6211 01:20:16.147018 11, 0xFFFF, sum = 0
6212 01:20:16.149524 12, 0x0, sum = 1
6213 01:20:16.149993 13, 0x0, sum = 2
6214 01:20:16.150416 14, 0x0, sum = 3
6215 01:20:16.153076 15, 0x0, sum = 4
6216 01:20:16.153650 best_step = 13
6217 01:20:16.154068
6218 01:20:16.156104 ==
6219 01:20:16.159258 Dram Type= 6, Freq= 0, CH_0, rank 0
6220 01:20:16.162683 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6221 01:20:16.163150 ==
6222 01:20:16.163519 RX Vref Scan: 1
6223 01:20:16.163868
6224 01:20:16.166051 RX Vref 0 -> 0, step: 1
6225 01:20:16.166522
6226 01:20:16.169344 RX Delay -359 -> 252, step: 8
6227 01:20:16.169807
6228 01:20:16.173215 Set Vref, RX VrefLevel [Byte0]: 45
6229 01:20:16.176207 [Byte1]: 48
6230 01:20:16.179916
6231 01:20:16.180474 Final RX Vref Byte 0 = 45 to rank0
6232 01:20:16.183254 Final RX Vref Byte 1 = 48 to rank0
6233 01:20:16.186699 Final RX Vref Byte 0 = 45 to rank1
6234 01:20:16.190011 Final RX Vref Byte 1 = 48 to rank1==
6235 01:20:16.193219 Dram Type= 6, Freq= 0, CH_0, rank 0
6236 01:20:16.199630 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6237 01:20:16.200200 ==
6238 01:20:16.200618 DQS Delay:
6239 01:20:16.203297 DQS0 = 52, DQS1 = 68
6240 01:20:16.203755 DQM Delay:
6241 01:20:16.204119 DQM0 = 9, DQM1 = 17
6242 01:20:16.206323 DQ Delay:
6243 01:20:16.209634 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6244 01:20:16.210134 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6245 01:20:16.213040 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6246 01:20:16.216182 DQ12 =24, DQ13 =28, DQ14 =28, DQ15 =28
6247 01:20:16.216745
6248 01:20:16.217117
6249 01:20:16.226099 [DQSOSCAuto] RK0, (LSB)MR18= 0xa5a5, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6250 01:20:16.229526 CH0 RK0: MR19=C0C, MR18=A5A5
6251 01:20:16.235892 CH0_RK0: MR19=0xC0C, MR18=0xA5A5, DQSOSC=389, MR23=63, INC=390, DEC=260
6252 01:20:16.236459 ==
6253 01:20:16.239383 Dram Type= 6, Freq= 0, CH_0, rank 1
6254 01:20:16.242608 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6255 01:20:16.243077 ==
6256 01:20:16.245806 [Gating] SW mode calibration
6257 01:20:16.252680 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6258 01:20:16.258996 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6259 01:20:16.262500 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6260 01:20:16.265823 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6261 01:20:16.272148 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6262 01:20:16.275733 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6263 01:20:16.278827 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6264 01:20:16.285914 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6265 01:20:16.288939 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6266 01:20:16.292211 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6267 01:20:16.298684 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6268 01:20:16.299231 Total UI for P1: 0, mck2ui 16
6269 01:20:16.302157 best dqsien dly found for B0: ( 0, 10, 16)
6270 01:20:16.305114 Total UI for P1: 0, mck2ui 16
6271 01:20:16.308646 best dqsien dly found for B1: ( 0, 10, 24)
6272 01:20:16.315350 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6273 01:20:16.318572 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6274 01:20:16.319121
6275 01:20:16.322181 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6276 01:20:16.324940 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6277 01:20:16.328126 [Gating] SW calibration Done
6278 01:20:16.328619 ==
6279 01:20:16.331591 Dram Type= 6, Freq= 0, CH_0, rank 1
6280 01:20:16.335101 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6281 01:20:16.335662 ==
6282 01:20:16.338570 RX Vref Scan: 0
6283 01:20:16.339126
6284 01:20:16.339500 RX Vref 0 -> 0, step: 1
6285 01:20:16.339846
6286 01:20:16.341441 RX Delay -410 -> 252, step: 16
6287 01:20:16.348458 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6288 01:20:16.351713 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6289 01:20:16.354762 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6290 01:20:16.357820 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6291 01:20:16.364969 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6292 01:20:16.368316 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6293 01:20:16.371244 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6294 01:20:16.374724 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6295 01:20:16.381437 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6296 01:20:16.384551 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6297 01:20:16.387982 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6298 01:20:16.394144 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6299 01:20:16.397843 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6300 01:20:16.400828 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6301 01:20:16.404549 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6302 01:20:16.410789 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6303 01:20:16.411359 ==
6304 01:20:16.414121 Dram Type= 6, Freq= 0, CH_0, rank 1
6305 01:20:16.417435 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6306 01:20:16.417998 ==
6307 01:20:16.418410 DQS Delay:
6308 01:20:16.420659 DQS0 = 43, DQS1 = 59
6309 01:20:16.421121 DQM Delay:
6310 01:20:16.424145 DQM0 = 7, DQM1 = 14
6311 01:20:16.424725 DQ Delay:
6312 01:20:16.427231 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6313 01:20:16.430407 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6314 01:20:16.434149 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6315 01:20:16.437183 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6316 01:20:16.437744
6317 01:20:16.438166
6318 01:20:16.438516 ==
6319 01:20:16.440262 Dram Type= 6, Freq= 0, CH_0, rank 1
6320 01:20:16.443481 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6321 01:20:16.443946 ==
6322 01:20:16.444315
6323 01:20:16.444653
6324 01:20:16.446965 TX Vref Scan disable
6325 01:20:16.450193 == TX Byte 0 ==
6326 01:20:16.453391 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6327 01:20:16.456958 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6328 01:20:16.460130 == TX Byte 1 ==
6329 01:20:16.463689 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6330 01:20:16.466995 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6331 01:20:16.467539 ==
6332 01:20:16.469825 Dram Type= 6, Freq= 0, CH_0, rank 1
6333 01:20:16.473214 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6334 01:20:16.476345 ==
6335 01:20:16.476808
6336 01:20:16.477166
6337 01:20:16.477503 TX Vref Scan disable
6338 01:20:16.479691 == TX Byte 0 ==
6339 01:20:16.482921 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6340 01:20:16.486560 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6341 01:20:16.490091 == TX Byte 1 ==
6342 01:20:16.493206 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6343 01:20:16.496438 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6344 01:20:16.497034
6345 01:20:16.497410 [DATLAT]
6346 01:20:16.499871 Freq=400, CH0 RK1
6347 01:20:16.500434
6348 01:20:16.502948 DATLAT Default: 0xd
6349 01:20:16.503506 0, 0xFFFF, sum = 0
6350 01:20:16.506388 1, 0xFFFF, sum = 0
6351 01:20:16.507010 2, 0xFFFF, sum = 0
6352 01:20:16.509509 3, 0xFFFF, sum = 0
6353 01:20:16.509975 4, 0xFFFF, sum = 0
6354 01:20:16.513129 5, 0xFFFF, sum = 0
6355 01:20:16.513701 6, 0xFFFF, sum = 0
6356 01:20:16.515992 7, 0xFFFF, sum = 0
6357 01:20:16.516457 8, 0xFFFF, sum = 0
6358 01:20:16.519533 9, 0xFFFF, sum = 0
6359 01:20:16.520101 10, 0xFFFF, sum = 0
6360 01:20:16.522566 11, 0xFFFF, sum = 0
6361 01:20:16.523084 12, 0x0, sum = 1
6362 01:20:16.526387 13, 0x0, sum = 2
6363 01:20:16.526905 14, 0x0, sum = 3
6364 01:20:16.529145 15, 0x0, sum = 4
6365 01:20:16.529607 best_step = 13
6366 01:20:16.529969
6367 01:20:16.530348 ==
6368 01:20:16.532364 Dram Type= 6, Freq= 0, CH_0, rank 1
6369 01:20:16.539500 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6370 01:20:16.539957 ==
6371 01:20:16.540323 RX Vref Scan: 0
6372 01:20:16.540665
6373 01:20:16.542669 RX Vref 0 -> 0, step: 1
6374 01:20:16.543128
6375 01:20:16.545621 RX Delay -359 -> 252, step: 8
6376 01:20:16.552458 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6377 01:20:16.555929 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6378 01:20:16.558869 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6379 01:20:16.562271 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6380 01:20:16.569271 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6381 01:20:16.571935 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6382 01:20:16.575212 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6383 01:20:16.578703 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6384 01:20:16.585560 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6385 01:20:16.589187 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6386 01:20:16.592368 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6387 01:20:16.595250 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6388 01:20:16.602122 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6389 01:20:16.605256 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6390 01:20:16.608483 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6391 01:20:16.615409 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6392 01:20:16.616108 ==
6393 01:20:16.618782 Dram Type= 6, Freq= 0, CH_0, rank 1
6394 01:20:16.622141 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6395 01:20:16.622698 ==
6396 01:20:16.623069 DQS Delay:
6397 01:20:16.625492 DQS0 = 52, DQS1 = 64
6398 01:20:16.626362 DQM Delay:
6399 01:20:16.628351 DQM0 = 10, DQM1 = 14
6400 01:20:16.628814 DQ Delay:
6401 01:20:16.631851 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6402 01:20:16.635478 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6403 01:20:16.638561 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6404 01:20:16.642288 DQ12 =20, DQ13 =24, DQ14 =24, DQ15 =24
6405 01:20:16.643202
6406 01:20:16.643608
6407 01:20:16.648171 [DQSOSCAuto] RK1, (LSB)MR18= 0xb5b5, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6408 01:20:16.651504 CH0 RK1: MR19=C0C, MR18=B5B5
6409 01:20:16.658534 CH0_RK1: MR19=0xC0C, MR18=0xB5B5, DQSOSC=387, MR23=63, INC=394, DEC=262
6410 01:20:16.661657 [RxdqsGatingPostProcess] freq 400
6411 01:20:16.668596 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6412 01:20:16.669156 Pre-setting of DQS Precalculation
6413 01:20:16.674952 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6414 01:20:16.675507 ==
6415 01:20:16.678228 Dram Type= 6, Freq= 0, CH_1, rank 0
6416 01:20:16.681315 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6417 01:20:16.681775 ==
6418 01:20:16.688351 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6419 01:20:16.694890 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6420 01:20:16.698343 [CA 0] Center 36 (8~64) winsize 57
6421 01:20:16.701412 [CA 1] Center 36 (8~64) winsize 57
6422 01:20:16.704747 [CA 2] Center 36 (8~64) winsize 57
6423 01:20:16.708142 [CA 3] Center 36 (8~64) winsize 57
6424 01:20:16.711111 [CA 4] Center 36 (8~64) winsize 57
6425 01:20:16.711638 [CA 5] Center 36 (8~64) winsize 57
6426 01:20:16.712019
6427 01:20:16.717639 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6428 01:20:16.718229
6429 01:20:16.721328 [CATrainingPosCal] consider 1 rank data
6430 01:20:16.724644 u2DelayCellTimex100 = 270/100 ps
6431 01:20:16.727791 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6432 01:20:16.730833 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6433 01:20:16.733923 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6434 01:20:16.737402 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6435 01:20:16.740981 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6436 01:20:16.744084 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6437 01:20:16.744547
6438 01:20:16.747404 CA PerBit enable=1, Macro0, CA PI delay=36
6439 01:20:16.747974
6440 01:20:16.751016 [CBTSetCACLKResult] CA Dly = 36
6441 01:20:16.754127 CS Dly: 1 (0~32)
6442 01:20:16.754688 ==
6443 01:20:16.757240 Dram Type= 6, Freq= 0, CH_1, rank 1
6444 01:20:16.760687 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6445 01:20:16.761257 ==
6446 01:20:16.767117 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6447 01:20:16.773681 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6448 01:20:16.777114 [CA 0] Center 36 (8~64) winsize 57
6449 01:20:16.780673 [CA 1] Center 36 (8~64) winsize 57
6450 01:20:16.781233 [CA 2] Center 36 (8~64) winsize 57
6451 01:20:16.783576 [CA 3] Center 36 (8~64) winsize 57
6452 01:20:16.787105 [CA 4] Center 36 (8~64) winsize 57
6453 01:20:16.790908 [CA 5] Center 36 (8~64) winsize 57
6454 01:20:16.791477
6455 01:20:16.794181 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6456 01:20:16.796972
6457 01:20:16.800731 [CATrainingPosCal] consider 2 rank data
6458 01:20:16.801293 u2DelayCellTimex100 = 270/100 ps
6459 01:20:16.807217 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6460 01:20:16.810463 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6461 01:20:16.813486 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6462 01:20:16.816647 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6463 01:20:16.820271 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6464 01:20:16.823367 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6465 01:20:16.823930
6466 01:20:16.826881 CA PerBit enable=1, Macro0, CA PI delay=36
6467 01:20:16.827343
6468 01:20:16.830251 [CBTSetCACLKResult] CA Dly = 36
6469 01:20:16.833151 CS Dly: 1 (0~32)
6470 01:20:16.833619
6471 01:20:16.836402 ----->DramcWriteLeveling(PI) begin...
6472 01:20:16.836868 ==
6473 01:20:16.840089 Dram Type= 6, Freq= 0, CH_1, rank 0
6474 01:20:16.843135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6475 01:20:16.843899 ==
6476 01:20:16.846306 Write leveling (Byte 0): 32 => 0
6477 01:20:16.849860 Write leveling (Byte 1): 32 => 0
6478 01:20:16.853084 DramcWriteLeveling(PI) end<-----
6479 01:20:16.853553
6480 01:20:16.853920 ==
6481 01:20:16.857098 Dram Type= 6, Freq= 0, CH_1, rank 0
6482 01:20:16.859588 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6483 01:20:16.860057 ==
6484 01:20:16.863021 [Gating] SW mode calibration
6485 01:20:16.869780 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6486 01:20:16.876099 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6487 01:20:16.879706 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6488 01:20:16.882690 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6489 01:20:16.889831 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6490 01:20:16.892892 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6491 01:20:16.896076 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 01:20:16.902657 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6493 01:20:16.906142 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6494 01:20:16.909766 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6495 01:20:16.916074 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6496 01:20:16.919270 Total UI for P1: 0, mck2ui 16
6497 01:20:16.922920 best dqsien dly found for B0: ( 0, 10, 16)
6498 01:20:16.923482 Total UI for P1: 0, mck2ui 16
6499 01:20:16.929318 best dqsien dly found for B1: ( 0, 10, 16)
6500 01:20:16.932206 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6501 01:20:16.935654 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6502 01:20:16.936119
6503 01:20:16.939200 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6504 01:20:16.942434 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6505 01:20:16.945434 [Gating] SW calibration Done
6506 01:20:16.945897 ==
6507 01:20:16.948712 Dram Type= 6, Freq= 0, CH_1, rank 0
6508 01:20:16.952285 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6509 01:20:16.952854 ==
6510 01:20:16.955520 RX Vref Scan: 0
6511 01:20:16.955980
6512 01:20:16.958689 RX Vref 0 -> 0, step: 1
6513 01:20:16.959151
6514 01:20:16.959514 RX Delay -410 -> 252, step: 16
6515 01:20:16.965386 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6516 01:20:16.969036 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6517 01:20:16.972313 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6518 01:20:16.975636 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6519 01:20:16.982296 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6520 01:20:16.985787 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6521 01:20:16.989127 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6522 01:20:16.995445 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6523 01:20:16.998885 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6524 01:20:17.002428 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6525 01:20:17.005178 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6526 01:20:17.012002 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6527 01:20:17.015402 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6528 01:20:17.018623 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6529 01:20:17.021738 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6530 01:20:17.028762 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6531 01:20:17.029335 ==
6532 01:20:17.031659 Dram Type= 6, Freq= 0, CH_1, rank 0
6533 01:20:17.034852 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6534 01:20:17.035315 ==
6535 01:20:17.035688 DQS Delay:
6536 01:20:17.038073 DQS0 = 43, DQS1 = 59
6537 01:20:17.038534 DQM Delay:
6538 01:20:17.041712 DQM0 = 6, DQM1 = 15
6539 01:20:17.042342 DQ Delay:
6540 01:20:17.044796 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6541 01:20:17.047906 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6542 01:20:17.051465 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6543 01:20:17.054960 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6544 01:20:17.055425
6545 01:20:17.055790
6546 01:20:17.056130 ==
6547 01:20:17.057809 Dram Type= 6, Freq= 0, CH_1, rank 0
6548 01:20:17.061600 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6549 01:20:17.062214 ==
6550 01:20:17.062591
6551 01:20:17.062931
6552 01:20:17.064818 TX Vref Scan disable
6553 01:20:17.068017 == TX Byte 0 ==
6554 01:20:17.071380 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6555 01:20:17.074405 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6556 01:20:17.077593 == TX Byte 1 ==
6557 01:20:17.081221 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6558 01:20:17.084319 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6559 01:20:17.084889 ==
6560 01:20:17.087683 Dram Type= 6, Freq= 0, CH_1, rank 0
6561 01:20:17.090843 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6562 01:20:17.094344 ==
6563 01:20:17.094912
6564 01:20:17.095281
6565 01:20:17.095624 TX Vref Scan disable
6566 01:20:17.097800 == TX Byte 0 ==
6567 01:20:17.101020 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6568 01:20:17.104422 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6569 01:20:17.107490 == TX Byte 1 ==
6570 01:20:17.111103 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6571 01:20:17.114181 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6572 01:20:17.114742
6573 01:20:17.117577 [DATLAT]
6574 01:20:17.118174 Freq=400, CH1 RK0
6575 01:20:17.118556
6576 01:20:17.120949 DATLAT Default: 0xf
6577 01:20:17.121419 0, 0xFFFF, sum = 0
6578 01:20:17.124299 1, 0xFFFF, sum = 0
6579 01:20:17.124798 2, 0xFFFF, sum = 0
6580 01:20:17.127059 3, 0xFFFF, sum = 0
6581 01:20:17.127569 4, 0xFFFF, sum = 0
6582 01:20:17.130471 5, 0xFFFF, sum = 0
6583 01:20:17.130937 6, 0xFFFF, sum = 0
6584 01:20:17.134203 7, 0xFFFF, sum = 0
6585 01:20:17.134769 8, 0xFFFF, sum = 0
6586 01:20:17.137263 9, 0xFFFF, sum = 0
6587 01:20:17.140766 10, 0xFFFF, sum = 0
6588 01:20:17.141337 11, 0xFFFF, sum = 0
6589 01:20:17.144296 12, 0x0, sum = 1
6590 01:20:17.144923 13, 0x0, sum = 2
6591 01:20:17.147173 14, 0x0, sum = 3
6592 01:20:17.147640 15, 0x0, sum = 4
6593 01:20:17.148014 best_step = 13
6594 01:20:17.148356
6595 01:20:17.150316 ==
6596 01:20:17.153973 Dram Type= 6, Freq= 0, CH_1, rank 0
6597 01:20:17.157198 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6598 01:20:17.157758 ==
6599 01:20:17.158184 RX Vref Scan: 1
6600 01:20:17.158536
6601 01:20:17.160674 RX Vref 0 -> 0, step: 1
6602 01:20:17.161255
6603 01:20:17.164137 RX Delay -359 -> 252, step: 8
6604 01:20:17.164698
6605 01:20:17.167086 Set Vref, RX VrefLevel [Byte0]: 54
6606 01:20:17.170455 [Byte1]: 50
6607 01:20:17.174202
6608 01:20:17.174758 Final RX Vref Byte 0 = 54 to rank0
6609 01:20:17.177298 Final RX Vref Byte 1 = 50 to rank0
6610 01:20:17.180415 Final RX Vref Byte 0 = 54 to rank1
6611 01:20:17.183953 Final RX Vref Byte 1 = 50 to rank1==
6612 01:20:17.187105 Dram Type= 6, Freq= 0, CH_1, rank 0
6613 01:20:17.194097 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6614 01:20:17.194671 ==
6615 01:20:17.195046 DQS Delay:
6616 01:20:17.197020 DQS0 = 48, DQS1 = 64
6617 01:20:17.197571 DQM Delay:
6618 01:20:17.197939 DQM0 = 8, DQM1 = 17
6619 01:20:17.200223 DQ Delay:
6620 01:20:17.203713 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6621 01:20:17.204263 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6622 01:20:17.206870 DQ8 =0, DQ9 =8, DQ10 =20, DQ11 =8
6623 01:20:17.210372 DQ12 =24, DQ13 =28, DQ14 =24, DQ15 =24
6624 01:20:17.211010
6625 01:20:17.211475
6626 01:20:17.220214 [DQSOSCAuto] RK0, (LSB)MR18= 0xcaca, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6627 01:20:17.223521 CH1 RK0: MR19=C0C, MR18=CACA
6628 01:20:17.230171 CH1_RK0: MR19=0xC0C, MR18=0xCACA, DQSOSC=384, MR23=63, INC=400, DEC=267
6629 01:20:17.230738 ==
6630 01:20:17.233444 Dram Type= 6, Freq= 0, CH_1, rank 1
6631 01:20:17.237170 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6632 01:20:17.237765 ==
6633 01:20:17.240211 [Gating] SW mode calibration
6634 01:20:17.246896 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6635 01:20:17.253406 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6636 01:20:17.257064 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6637 01:20:17.259997 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6638 01:20:17.263143 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6639 01:20:17.270361 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6640 01:20:17.273396 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6641 01:20:17.276807 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6642 01:20:17.283365 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6643 01:20:17.287048 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6644 01:20:17.289919 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6645 01:20:17.293388 Total UI for P1: 0, mck2ui 16
6646 01:20:17.296815 best dqsien dly found for B0: ( 0, 10, 16)
6647 01:20:17.299857 Total UI for P1: 0, mck2ui 16
6648 01:20:17.303074 best dqsien dly found for B1: ( 0, 10, 16)
6649 01:20:17.306705 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6650 01:20:17.313012 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6651 01:20:17.313476
6652 01:20:17.316249 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6653 01:20:17.319407 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6654 01:20:17.322968 [Gating] SW calibration Done
6655 01:20:17.323546 ==
6656 01:20:17.326245 Dram Type= 6, Freq= 0, CH_1, rank 1
6657 01:20:17.329573 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6658 01:20:17.330089 ==
6659 01:20:17.332933 RX Vref Scan: 0
6660 01:20:17.333387
6661 01:20:17.333753 RX Vref 0 -> 0, step: 1
6662 01:20:17.334143
6663 01:20:17.336489 RX Delay -410 -> 252, step: 16
6664 01:20:17.342858 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6665 01:20:17.346789 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6666 01:20:17.349314 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6667 01:20:17.352393 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6668 01:20:17.359258 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6669 01:20:17.362748 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6670 01:20:17.366118 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6671 01:20:17.369232 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6672 01:20:17.375819 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6673 01:20:17.379090 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6674 01:20:17.382470 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6675 01:20:17.386073 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6676 01:20:17.392649 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6677 01:20:17.395478 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6678 01:20:17.398919 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6679 01:20:17.402174 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6680 01:20:17.405874 ==
6681 01:20:17.406493 Dram Type= 6, Freq= 0, CH_1, rank 1
6682 01:20:17.412173 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6683 01:20:17.412637 ==
6684 01:20:17.413005 DQS Delay:
6685 01:20:17.415371 DQS0 = 43, DQS1 = 59
6686 01:20:17.415829 DQM Delay:
6687 01:20:17.418806 DQM0 = 9, DQM1 = 18
6688 01:20:17.419364 DQ Delay:
6689 01:20:17.422223 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6690 01:20:17.425479 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6691 01:20:17.428471 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6692 01:20:17.432116 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6693 01:20:17.432685
6694 01:20:17.433055
6695 01:20:17.433395 ==
6696 01:20:17.435689 Dram Type= 6, Freq= 0, CH_1, rank 1
6697 01:20:17.439069 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6698 01:20:17.439632 ==
6699 01:20:17.440004
6700 01:20:17.440346
6701 01:20:17.442183 TX Vref Scan disable
6702 01:20:17.442871 == TX Byte 0 ==
6703 01:20:17.445225 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6704 01:20:17.452324 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6705 01:20:17.452895 == TX Byte 1 ==
6706 01:20:17.456090 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6707 01:20:17.461879 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6708 01:20:17.462530 ==
6709 01:20:17.465999 Dram Type= 6, Freq= 0, CH_1, rank 1
6710 01:20:17.468786 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6711 01:20:17.469356 ==
6712 01:20:17.469730
6713 01:20:17.470124
6714 01:20:17.471523 TX Vref Scan disable
6715 01:20:17.471990 == TX Byte 0 ==
6716 01:20:17.478489 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6717 01:20:17.481872 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6718 01:20:17.482486 == TX Byte 1 ==
6719 01:20:17.488419 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6720 01:20:17.491754 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6721 01:20:17.492323
6722 01:20:17.492693 [DATLAT]
6723 01:20:17.494676 Freq=400, CH1 RK1
6724 01:20:17.495137
6725 01:20:17.495508 DATLAT Default: 0xd
6726 01:20:17.498397 0, 0xFFFF, sum = 0
6727 01:20:17.498979 1, 0xFFFF, sum = 0
6728 01:20:17.501778 2, 0xFFFF, sum = 0
6729 01:20:17.502288 3, 0xFFFF, sum = 0
6730 01:20:17.505135 4, 0xFFFF, sum = 0
6731 01:20:17.505710 5, 0xFFFF, sum = 0
6732 01:20:17.508191 6, 0xFFFF, sum = 0
6733 01:20:17.508664 7, 0xFFFF, sum = 0
6734 01:20:17.511595 8, 0xFFFF, sum = 0
6735 01:20:17.512068 9, 0xFFFF, sum = 0
6736 01:20:17.514547 10, 0xFFFF, sum = 0
6737 01:20:17.515021 11, 0xFFFF, sum = 0
6738 01:20:17.517952 12, 0x0, sum = 1
6739 01:20:17.518447 13, 0x0, sum = 2
6740 01:20:17.521909 14, 0x0, sum = 3
6741 01:20:17.522527 15, 0x0, sum = 4
6742 01:20:17.525092 best_step = 13
6743 01:20:17.525665
6744 01:20:17.526077 ==
6745 01:20:17.528137 Dram Type= 6, Freq= 0, CH_1, rank 1
6746 01:20:17.531852 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6747 01:20:17.532442 ==
6748 01:20:17.534808 RX Vref Scan: 0
6749 01:20:17.535276
6750 01:20:17.535667 RX Vref 0 -> 0, step: 1
6751 01:20:17.536028
6752 01:20:17.538444 RX Delay -359 -> 252, step: 8
6753 01:20:17.546511 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6754 01:20:17.549401 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6755 01:20:17.552910 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6756 01:20:17.556053 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6757 01:20:17.562585 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6758 01:20:17.566168 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6759 01:20:17.569628 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6760 01:20:17.572938 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6761 01:20:17.579488 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6762 01:20:17.582664 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6763 01:20:17.586104 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6764 01:20:17.593012 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6765 01:20:17.595711 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6766 01:20:17.599427 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6767 01:20:17.602218 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6768 01:20:17.608947 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6769 01:20:17.609507 ==
6770 01:20:17.612719 Dram Type= 6, Freq= 0, CH_1, rank 1
6771 01:20:17.615546 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6772 01:20:17.616017 ==
6773 01:20:17.616463 DQS Delay:
6774 01:20:17.618872 DQS0 = 48, DQS1 = 64
6775 01:20:17.619343 DQM Delay:
6776 01:20:17.622476 DQM0 = 9, DQM1 = 15
6777 01:20:17.623045 DQ Delay:
6778 01:20:17.625643 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6779 01:20:17.628959 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6780 01:20:17.632094 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6781 01:20:17.635383 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6782 01:20:17.635852
6783 01:20:17.636225
6784 01:20:17.642616 [DQSOSCAuto] RK1, (LSB)MR18= 0xadad, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6785 01:20:17.645152 CH1 RK1: MR19=C0C, MR18=ADAD
6786 01:20:17.652014 CH1_RK1: MR19=0xC0C, MR18=0xADAD, DQSOSC=388, MR23=63, INC=392, DEC=261
6787 01:20:17.655326 [RxdqsGatingPostProcess] freq 400
6788 01:20:17.661782 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6789 01:20:17.665187 Pre-setting of DQS Precalculation
6790 01:20:17.668863 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6791 01:20:17.674984 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6792 01:20:17.681578 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6793 01:20:17.684946
6794 01:20:17.685421
6795 01:20:17.685790 [Calibration Summary] 800 Mbps
6796 01:20:17.687980 CH 0, Rank 0
6797 01:20:17.688442 SW Impedance : PASS
6798 01:20:17.691338 DUTY Scan : NO K
6799 01:20:17.694665 ZQ Calibration : PASS
6800 01:20:17.695129 Jitter Meter : NO K
6801 01:20:17.698606 CBT Training : PASS
6802 01:20:17.701324 Write leveling : PASS
6803 01:20:17.701951 RX DQS gating : PASS
6804 01:20:17.704888 RX DQ/DQS(RDDQC) : PASS
6805 01:20:17.708172 TX DQ/DQS : PASS
6806 01:20:17.708881 RX DATLAT : PASS
6807 01:20:17.711099 RX DQ/DQS(Engine): PASS
6808 01:20:17.714392 TX OE : NO K
6809 01:20:17.714864 All Pass.
6810 01:20:17.715237
6811 01:20:17.715581 CH 0, Rank 1
6812 01:20:17.717795 SW Impedance : PASS
6813 01:20:17.721337 DUTY Scan : NO K
6814 01:20:17.721905 ZQ Calibration : PASS
6815 01:20:17.724574 Jitter Meter : NO K
6816 01:20:17.728091 CBT Training : PASS
6817 01:20:17.728658 Write leveling : NO K
6818 01:20:17.730933 RX DQS gating : PASS
6819 01:20:17.734631 RX DQ/DQS(RDDQC) : PASS
6820 01:20:17.735203 TX DQ/DQS : PASS
6821 01:20:17.737626 RX DATLAT : PASS
6822 01:20:17.738125 RX DQ/DQS(Engine): PASS
6823 01:20:17.740979 TX OE : NO K
6824 01:20:17.741577 All Pass.
6825 01:20:17.741958
6826 01:20:17.744255 CH 1, Rank 0
6827 01:20:17.747432 SW Impedance : PASS
6828 01:20:17.747892 DUTY Scan : NO K
6829 01:20:17.750853 ZQ Calibration : PASS
6830 01:20:17.751337 Jitter Meter : NO K
6831 01:20:17.753997 CBT Training : PASS
6832 01:20:17.757323 Write leveling : PASS
6833 01:20:17.757787 RX DQS gating : PASS
6834 01:20:17.761108 RX DQ/DQS(RDDQC) : PASS
6835 01:20:17.764372 TX DQ/DQS : PASS
6836 01:20:17.764966 RX DATLAT : PASS
6837 01:20:17.767555 RX DQ/DQS(Engine): PASS
6838 01:20:17.770715 TX OE : NO K
6839 01:20:17.771204 All Pass.
6840 01:20:17.771577
6841 01:20:17.771919 CH 1, Rank 1
6842 01:20:17.774075 SW Impedance : PASS
6843 01:20:17.777366 DUTY Scan : NO K
6844 01:20:17.777983 ZQ Calibration : PASS
6845 01:20:17.780968 Jitter Meter : NO K
6846 01:20:17.784145 CBT Training : PASS
6847 01:20:17.784716 Write leveling : NO K
6848 01:20:17.787266 RX DQS gating : PASS
6849 01:20:17.790497 RX DQ/DQS(RDDQC) : PASS
6850 01:20:17.790961 TX DQ/DQS : PASS
6851 01:20:17.794155 RX DATLAT : PASS
6852 01:20:17.797214 RX DQ/DQS(Engine): PASS
6853 01:20:17.797851 TX OE : NO K
6854 01:20:17.798364 All Pass.
6855 01:20:17.800914
6856 01:20:17.801484 DramC Write-DBI off
6857 01:20:17.803905 PER_BANK_REFRESH: Hybrid Mode
6858 01:20:17.804380 TX_TRACKING: ON
6859 01:20:17.813754 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6860 01:20:17.817089 [FAST_K] Save calibration result to emmc
6861 01:20:17.820894 dramc_set_vcore_voltage set vcore to 725000
6862 01:20:17.823665 Read voltage for 1600, 0
6863 01:20:17.824243 Vio18 = 0
6864 01:20:17.826780 Vcore = 725000
6865 01:20:17.827343 Vdram = 0
6866 01:20:17.827746 Vddq = 0
6867 01:20:17.830270 Vmddr = 0
6868 01:20:17.833364 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6869 01:20:17.840833 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6870 01:20:17.841393 MEM_TYPE=3, freq_sel=13
6871 01:20:17.843341 sv_algorithm_assistance_LP4_3733
6872 01:20:17.849939 ============ PULL DRAM RESETB DOWN ============
6873 01:20:17.853197 ========== PULL DRAM RESETB DOWN end =========
6874 01:20:17.856770 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6875 01:20:17.860069 ===================================
6876 01:20:17.862993 LPDDR4 DRAM CONFIGURATION
6877 01:20:17.866556 ===================================
6878 01:20:17.867031 EX_ROW_EN[0] = 0x0
6879 01:20:17.869595 EX_ROW_EN[1] = 0x0
6880 01:20:17.873293 LP4Y_EN = 0x0
6881 01:20:17.873891 WORK_FSP = 0x1
6882 01:20:17.876232 WL = 0x5
6883 01:20:17.876693 RL = 0x5
6884 01:20:17.879946 BL = 0x2
6885 01:20:17.880500 RPST = 0x0
6886 01:20:17.883030 RD_PRE = 0x0
6887 01:20:17.883542 WR_PRE = 0x1
6888 01:20:17.886139 WR_PST = 0x1
6889 01:20:17.886600 DBI_WR = 0x0
6890 01:20:17.889405 DBI_RD = 0x0
6891 01:20:17.889867 OTF = 0x1
6892 01:20:17.892943 ===================================
6893 01:20:17.896464 ===================================
6894 01:20:17.899707 ANA top config
6895 01:20:17.902547 ===================================
6896 01:20:17.906246 DLL_ASYNC_EN = 0
6897 01:20:17.906800 ALL_SLAVE_EN = 0
6898 01:20:17.909297 NEW_RANK_MODE = 1
6899 01:20:17.912714 DLL_IDLE_MODE = 1
6900 01:20:17.916044 LP45_APHY_COMB_EN = 1
6901 01:20:17.916608 TX_ODT_DIS = 0
6902 01:20:17.919424 NEW_8X_MODE = 1
6903 01:20:17.922666 ===================================
6904 01:20:17.925914 ===================================
6905 01:20:17.929288 data_rate = 3200
6906 01:20:17.932607 CKR = 1
6907 01:20:17.935714 DQ_P2S_RATIO = 8
6908 01:20:17.938958 ===================================
6909 01:20:17.942568 CA_P2S_RATIO = 8
6910 01:20:17.943125 DQ_CA_OPEN = 0
6911 01:20:17.945682 DQ_SEMI_OPEN = 0
6912 01:20:17.948876 CA_SEMI_OPEN = 0
6913 01:20:17.952565 CA_FULL_RATE = 0
6914 01:20:17.955928 DQ_CKDIV4_EN = 0
6915 01:20:17.958668 CA_CKDIV4_EN = 0
6916 01:20:17.959127 CA_PREDIV_EN = 0
6917 01:20:17.962375 PH8_DLY = 12
6918 01:20:17.965349 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6919 01:20:17.968579 DQ_AAMCK_DIV = 4
6920 01:20:17.972189 CA_AAMCK_DIV = 4
6921 01:20:17.975333 CA_ADMCK_DIV = 4
6922 01:20:17.975902 DQ_TRACK_CA_EN = 0
6923 01:20:17.978656 CA_PICK = 1600
6924 01:20:17.982344 CA_MCKIO = 1600
6925 01:20:17.985699 MCKIO_SEMI = 0
6926 01:20:17.988899 PLL_FREQ = 3068
6927 01:20:17.992108 DQ_UI_PI_RATIO = 32
6928 01:20:17.995470 CA_UI_PI_RATIO = 0
6929 01:20:17.998639 ===================================
6930 01:20:18.002197 ===================================
6931 01:20:18.002768 memory_type:LPDDR4
6932 01:20:18.005650 GP_NUM : 10
6933 01:20:18.008677 SRAM_EN : 1
6934 01:20:18.009249 MD32_EN : 0
6935 01:20:18.012007 ===================================
6936 01:20:18.015089 [ANA_INIT] >>>>>>>>>>>>>>
6937 01:20:18.018637 <<<<<< [CONFIGURE PHASE]: ANA_TX
6938 01:20:18.021817 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6939 01:20:18.025176 ===================================
6940 01:20:18.028533 data_rate = 3200,PCW = 0X7600
6941 01:20:18.031587 ===================================
6942 01:20:18.034756 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6943 01:20:18.038294 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6944 01:20:18.045304 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6945 01:20:18.051379 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6946 01:20:18.054609 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6947 01:20:18.058331 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6948 01:20:18.058886 [ANA_INIT] flow start
6949 01:20:18.061415 [ANA_INIT] PLL >>>>>>>>
6950 01:20:18.064891 [ANA_INIT] PLL <<<<<<<<
6951 01:20:18.065475 [ANA_INIT] MIDPI >>>>>>>>
6952 01:20:18.067954 [ANA_INIT] MIDPI <<<<<<<<
6953 01:20:18.071548 [ANA_INIT] DLL >>>>>>>>
6954 01:20:18.072110 [ANA_INIT] DLL <<<<<<<<
6955 01:20:18.074252 [ANA_INIT] flow end
6956 01:20:18.077700 ============ LP4 DIFF to SE enter ============
6957 01:20:18.081011 ============ LP4 DIFF to SE exit ============
6958 01:20:18.084555 [ANA_INIT] <<<<<<<<<<<<<
6959 01:20:18.087685 [Flow] Enable top DCM control >>>>>
6960 01:20:18.090920 [Flow] Enable top DCM control <<<<<
6961 01:20:18.094626 Enable DLL master slave shuffle
6962 01:20:18.101164 ==============================================================
6963 01:20:18.101723 Gating Mode config
6964 01:20:18.107597 ==============================================================
6965 01:20:18.110646 Config description:
6966 01:20:18.117981 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6967 01:20:18.124101 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6968 01:20:18.130662 SELPH_MODE 0: By rank 1: By Phase
6969 01:20:18.137473 ==============================================================
6970 01:20:18.140540 GAT_TRACK_EN = 1
6971 01:20:18.141123 RX_GATING_MODE = 2
6972 01:20:18.143903 RX_GATING_TRACK_MODE = 2
6973 01:20:18.147250 SELPH_MODE = 1
6974 01:20:18.150541 PICG_EARLY_EN = 1
6975 01:20:18.153761 VALID_LAT_VALUE = 1
6976 01:20:18.160455 ==============================================================
6977 01:20:18.163381 Enter into Gating configuration >>>>
6978 01:20:18.166641 Exit from Gating configuration <<<<
6979 01:20:18.170137 Enter into DVFS_PRE_config >>>>>
6980 01:20:18.180975 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6981 01:20:18.183653 Exit from DVFS_PRE_config <<<<<
6982 01:20:18.186862 Enter into PICG configuration >>>>
6983 01:20:18.190372 Exit from PICG configuration <<<<
6984 01:20:18.193372 [RX_INPUT] configuration >>>>>
6985 01:20:18.197342 [RX_INPUT] configuration <<<<<
6986 01:20:18.200381 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6987 01:20:18.206681 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6988 01:20:18.213403 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6989 01:20:18.216746 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6990 01:20:18.223470 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6991 01:20:18.230345 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6992 01:20:18.233789 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6993 01:20:18.239936 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6994 01:20:18.243271 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6995 01:20:18.246561 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6996 01:20:18.250083 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6997 01:20:18.256204 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6998 01:20:18.260003 ===================================
6999 01:20:18.260572 LPDDR4 DRAM CONFIGURATION
7000 01:20:18.262733 ===================================
7001 01:20:18.266371 EX_ROW_EN[0] = 0x0
7002 01:20:18.269946 EX_ROW_EN[1] = 0x0
7003 01:20:18.270559 LP4Y_EN = 0x0
7004 01:20:18.272795 WORK_FSP = 0x1
7005 01:20:18.273394 WL = 0x5
7006 01:20:18.276164 RL = 0x5
7007 01:20:18.276747 BL = 0x2
7008 01:20:18.279384 RPST = 0x0
7009 01:20:18.280037 RD_PRE = 0x0
7010 01:20:18.282698 WR_PRE = 0x1
7011 01:20:18.283163 WR_PST = 0x1
7012 01:20:18.286148 DBI_WR = 0x0
7013 01:20:18.286724 DBI_RD = 0x0
7014 01:20:18.289408 OTF = 0x1
7015 01:20:18.292859 ===================================
7016 01:20:18.296166 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7017 01:20:18.299642 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7018 01:20:18.306084 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7019 01:20:18.309649 ===================================
7020 01:20:18.310268 LPDDR4 DRAM CONFIGURATION
7021 01:20:18.312468 ===================================
7022 01:20:18.315715 EX_ROW_EN[0] = 0x10
7023 01:20:18.319086 EX_ROW_EN[1] = 0x0
7024 01:20:18.319639 LP4Y_EN = 0x0
7025 01:20:18.322217 WORK_FSP = 0x1
7026 01:20:18.322712 WL = 0x5
7027 01:20:18.325889 RL = 0x5
7028 01:20:18.326493 BL = 0x2
7029 01:20:18.328982 RPST = 0x0
7030 01:20:18.329440 RD_PRE = 0x0
7031 01:20:18.332154 WR_PRE = 0x1
7032 01:20:18.332612 WR_PST = 0x1
7033 01:20:18.335680 DBI_WR = 0x0
7034 01:20:18.336140 DBI_RD = 0x0
7035 01:20:18.339350 OTF = 0x1
7036 01:20:18.342461 ===================================
7037 01:20:18.349273 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7038 01:20:18.349839 ==
7039 01:20:18.352329 Dram Type= 6, Freq= 0, CH_0, rank 0
7040 01:20:18.355608 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7041 01:20:18.356175 ==
7042 01:20:18.359192 [Duty_Offset_Calibration]
7043 01:20:18.359756 B0:0 B1:2 CA:1
7044 01:20:18.360126
7045 01:20:18.361825 [DutyScan_Calibration_Flow] k_type=0
7046 01:20:18.373372
7047 01:20:18.373969 ==CLK 0==
7048 01:20:18.376082 Final CLK duty delay cell = 0
7049 01:20:18.379733 [0] MAX Duty = 5156%(X100), DQS PI = 22
7050 01:20:18.382966 [0] MIN Duty = 4938%(X100), DQS PI = 52
7051 01:20:18.386752 [0] AVG Duty = 5047%(X100)
7052 01:20:18.387329
7053 01:20:18.389416 CH0 CLK Duty spec in!! Max-Min= 218%
7054 01:20:18.393188 [DutyScan_Calibration_Flow] ====Done====
7055 01:20:18.393752
7056 01:20:18.396409 [DutyScan_Calibration_Flow] k_type=1
7057 01:20:18.413157
7058 01:20:18.413717 ==DQS 0 ==
7059 01:20:18.416674 Final DQS duty delay cell = 0
7060 01:20:18.419288 [0] MAX Duty = 5125%(X100), DQS PI = 2
7061 01:20:18.422847 [0] MIN Duty = 5031%(X100), DQS PI = 8
7062 01:20:18.426232 [0] AVG Duty = 5078%(X100)
7063 01:20:18.426789
7064 01:20:18.427162 ==DQS 1 ==
7065 01:20:18.429566 Final DQS duty delay cell = 0
7066 01:20:18.432500 [0] MAX Duty = 5031%(X100), DQS PI = 6
7067 01:20:18.435996 [0] MIN Duty = 4876%(X100), DQS PI = 18
7068 01:20:18.439483 [0] AVG Duty = 4953%(X100)
7069 01:20:18.440059
7070 01:20:18.442841 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7071 01:20:18.443413
7072 01:20:18.446174 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7073 01:20:18.449629 [DutyScan_Calibration_Flow] ====Done====
7074 01:20:18.450250
7075 01:20:18.452190 [DutyScan_Calibration_Flow] k_type=3
7076 01:20:18.469923
7077 01:20:18.470530 ==DQM 0 ==
7078 01:20:18.473503 Final DQM duty delay cell = 0
7079 01:20:18.476809 [0] MAX Duty = 5187%(X100), DQS PI = 22
7080 01:20:18.479939 [0] MIN Duty = 4907%(X100), DQS PI = 56
7081 01:20:18.482833 [0] AVG Duty = 5047%(X100)
7082 01:20:18.483302
7083 01:20:18.483673 ==DQM 1 ==
7084 01:20:18.486589 Final DQM duty delay cell = 0
7085 01:20:18.489977 [0] MAX Duty = 5000%(X100), DQS PI = 4
7086 01:20:18.493146 [0] MIN Duty = 4782%(X100), DQS PI = 12
7087 01:20:18.496158 [0] AVG Duty = 4891%(X100)
7088 01:20:18.496637
7089 01:20:18.499829 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7090 01:20:18.500392
7091 01:20:18.502802 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7092 01:20:18.506134 [DutyScan_Calibration_Flow] ====Done====
7093 01:20:18.506607
7094 01:20:18.509685 [DutyScan_Calibration_Flow] k_type=2
7095 01:20:18.526481
7096 01:20:18.527050 ==DQ 0 ==
7097 01:20:18.529409 Final DQ duty delay cell = 0
7098 01:20:18.532638 [0] MAX Duty = 5218%(X100), DQS PI = 18
7099 01:20:18.536037 [0] MIN Duty = 4938%(X100), DQS PI = 56
7100 01:20:18.539391 [0] AVG Duty = 5078%(X100)
7101 01:20:18.539858
7102 01:20:18.540234 ==DQ 1 ==
7103 01:20:18.542677 Final DQ duty delay cell = -4
7104 01:20:18.546202 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7105 01:20:18.549296 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7106 01:20:18.552436 [-4] AVG Duty = 4953%(X100)
7107 01:20:18.552905
7108 01:20:18.555869 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7109 01:20:18.556447
7110 01:20:18.559037 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7111 01:20:18.562523 [DutyScan_Calibration_Flow] ====Done====
7112 01:20:18.563080 ==
7113 01:20:18.565587 Dram Type= 6, Freq= 0, CH_1, rank 0
7114 01:20:18.569039 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7115 01:20:18.569611 ==
7116 01:20:18.573118 [Duty_Offset_Calibration]
7117 01:20:18.573678 B0:0 B1:4 CA:-5
7118 01:20:18.574106
7119 01:20:18.575660 [DutyScan_Calibration_Flow] k_type=0
7120 01:20:18.586858
7121 01:20:18.587417 ==CLK 0==
7122 01:20:18.590407 Final CLK duty delay cell = 0
7123 01:20:18.593429 [0] MAX Duty = 5156%(X100), DQS PI = 20
7124 01:20:18.596941 [0] MIN Duty = 4906%(X100), DQS PI = 50
7125 01:20:18.600087 [0] AVG Duty = 5031%(X100)
7126 01:20:18.600554
7127 01:20:18.603492 CH1 CLK Duty spec in!! Max-Min= 250%
7128 01:20:18.606911 [DutyScan_Calibration_Flow] ====Done====
7129 01:20:18.607479
7130 01:20:18.610002 [DutyScan_Calibration_Flow] k_type=1
7131 01:20:18.625864
7132 01:20:18.626502 ==DQS 0 ==
7133 01:20:18.629151 Final DQS duty delay cell = 0
7134 01:20:18.632191 [0] MAX Duty = 5187%(X100), DQS PI = 20
7135 01:20:18.635633 [0] MIN Duty = 4876%(X100), DQS PI = 42
7136 01:20:18.638984 [0] AVG Duty = 5031%(X100)
7137 01:20:18.639551
7138 01:20:18.639925 ==DQS 1 ==
7139 01:20:18.642277 Final DQS duty delay cell = -4
7140 01:20:18.645503 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7141 01:20:18.649022 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7142 01:20:18.652034 [-4] AVG Duty = 4922%(X100)
7143 01:20:18.652594
7144 01:20:18.655186 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7145 01:20:18.655657
7146 01:20:18.658433 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7147 01:20:18.661985 [DutyScan_Calibration_Flow] ====Done====
7148 01:20:18.662486
7149 01:20:18.665188 [DutyScan_Calibration_Flow] k_type=3
7150 01:20:18.681623
7151 01:20:18.682220 ==DQM 0 ==
7152 01:20:18.684494 Final DQM duty delay cell = -4
7153 01:20:18.687901 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7154 01:20:18.691257 [-4] MIN Duty = 4782%(X100), DQS PI = 46
7155 01:20:18.694639 [-4] AVG Duty = 4922%(X100)
7156 01:20:18.695200
7157 01:20:18.695572 ==DQM 1 ==
7158 01:20:18.698014 Final DQM duty delay cell = -4
7159 01:20:18.701065 [-4] MAX Duty = 5062%(X100), DQS PI = 16
7160 01:20:18.704464 [-4] MIN Duty = 4907%(X100), DQS PI = 36
7161 01:20:18.707504 [-4] AVG Duty = 4984%(X100)
7162 01:20:18.708065
7163 01:20:18.710945 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7164 01:20:18.711464
7165 01:20:18.714211 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7166 01:20:18.717658 [DutyScan_Calibration_Flow] ====Done====
7167 01:20:18.718096
7168 01:20:18.721084 [DutyScan_Calibration_Flow] k_type=2
7169 01:20:18.738940
7170 01:20:18.739529 ==DQ 0 ==
7171 01:20:18.742454 Final DQ duty delay cell = 0
7172 01:20:18.745700 [0] MAX Duty = 5093%(X100), DQS PI = 18
7173 01:20:18.749375 [0] MIN Duty = 4938%(X100), DQS PI = 46
7174 01:20:18.749938 [0] AVG Duty = 5015%(X100)
7175 01:20:18.752561
7176 01:20:18.753024 ==DQ 1 ==
7177 01:20:18.755439 Final DQ duty delay cell = 0
7178 01:20:18.758812 [0] MAX Duty = 5031%(X100), DQS PI = 4
7179 01:20:18.762090 [0] MIN Duty = 4876%(X100), DQS PI = 28
7180 01:20:18.762558 [0] AVG Duty = 4953%(X100)
7181 01:20:18.762934
7182 01:20:18.768541 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7183 01:20:18.769010
7184 01:20:18.772348 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7185 01:20:18.775417 [DutyScan_Calibration_Flow] ====Done====
7186 01:20:18.778665 nWR fixed to 30
7187 01:20:18.779233 [ModeRegInit_LP4] CH0 RK0
7188 01:20:18.782312 [ModeRegInit_LP4] CH0 RK1
7189 01:20:18.785498 [ModeRegInit_LP4] CH1 RK0
7190 01:20:18.788914 [ModeRegInit_LP4] CH1 RK1
7191 01:20:18.789479 match AC timing 4
7192 01:20:18.795467 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7193 01:20:18.798932 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7194 01:20:18.801432 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7195 01:20:18.808281 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7196 01:20:18.811367 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7197 01:20:18.811836 [MiockJmeterHQA]
7198 01:20:18.812285
7199 01:20:18.814858 [DramcMiockJmeter] u1RxGatingPI = 0
7200 01:20:18.818352 0 : 4260, 4031
7201 01:20:18.818924 4 : 4255, 4030
7202 01:20:18.821324 8 : 4253, 4026
7203 01:20:18.821791 12 : 4363, 4138
7204 01:20:18.824516 16 : 4255, 4029
7205 01:20:18.824991 20 : 4252, 4027
7206 01:20:18.825362 24 : 4253, 4026
7207 01:20:18.827855 28 : 4361, 4138
7208 01:20:18.828460 32 : 4360, 4137
7209 01:20:18.830988 36 : 4250, 4027
7210 01:20:18.831456 40 : 4252, 4027
7211 01:20:18.834695 44 : 4253, 4026
7212 01:20:18.835177 48 : 4252, 4027
7213 01:20:18.838153 52 : 4255, 4029
7214 01:20:18.838625 56 : 4363, 4138
7215 01:20:18.839002 60 : 4250, 4027
7216 01:20:18.841882 64 : 4252, 4027
7217 01:20:18.842549 68 : 4252, 4027
7218 01:20:18.844291 72 : 4252, 4029
7219 01:20:18.844764 76 : 4250, 4026
7220 01:20:18.847996 80 : 4361, 4138
7221 01:20:18.848578 84 : 4360, 4137
7222 01:20:18.850919 88 : 4250, 4027
7223 01:20:18.851403 92 : 4250, 4027
7224 01:20:18.851815 96 : 4250, 4027
7225 01:20:18.854297 100 : 4250, 1532
7226 01:20:18.854768 104 : 4250, 0
7227 01:20:18.857541 108 : 4252, 0
7228 01:20:18.858053 112 : 4361, 0
7229 01:20:18.858850 116 : 4250, 0
7230 01:20:18.860917 120 : 4250, 0
7231 01:20:18.861400 124 : 4250, 0
7232 01:20:18.864521 128 : 4252, 0
7233 01:20:18.865240 132 : 4363, 0
7234 01:20:18.865843 136 : 4361, 0
7235 01:20:18.867408 140 : 4363, 0
7236 01:20:18.867893 144 : 4250, 0
7237 01:20:18.871667 148 : 4360, 0
7238 01:20:18.872277 152 : 4361, 0
7239 01:20:18.872797 156 : 4250, 0
7240 01:20:18.874568 160 : 4250, 0
7241 01:20:18.875054 164 : 4250, 0
7242 01:20:18.877791 168 : 4252, 0
7243 01:20:18.878327 172 : 4249, 0
7244 01:20:18.878822 176 : 4250, 0
7245 01:20:18.880814 180 : 4252, 0
7246 01:20:18.881506 184 : 4361, 0
7247 01:20:18.882157 188 : 4250, 0
7248 01:20:18.883929 192 : 4250, 0
7249 01:20:18.884401 196 : 4360, 0
7250 01:20:18.887483 200 : 4250, 0
7251 01:20:18.888056 204 : 4250, 0
7252 01:20:18.888436 208 : 4250, 0
7253 01:20:18.891575 212 : 4250, 0
7254 01:20:18.892081 216 : 4250, 0
7255 01:20:18.894248 220 : 4252, 1020
7256 01:20:18.894718 224 : 4250, 4024
7257 01:20:18.897453 228 : 4363, 4140
7258 01:20:18.898055 232 : 4250, 4027
7259 01:20:18.901037 236 : 4250, 4027
7260 01:20:18.901761 240 : 4363, 4140
7261 01:20:18.902199 244 : 4250, 4027
7262 01:20:18.904164 248 : 4250, 4027
7263 01:20:18.904634 252 : 4250, 4027
7264 01:20:18.907311 256 : 4252, 4029
7265 01:20:18.907785 260 : 4250, 4027
7266 01:20:18.910793 264 : 4250, 4027
7267 01:20:18.911276 268 : 4361, 4138
7268 01:20:18.913971 272 : 4250, 4027
7269 01:20:18.914621 276 : 4250, 4027
7270 01:20:18.917322 280 : 4361, 4137
7271 01:20:18.917792 284 : 4252, 4027
7272 01:20:18.920424 288 : 4250, 4026
7273 01:20:18.920892 292 : 4360, 4137
7274 01:20:18.923811 296 : 4250, 4027
7275 01:20:18.924378 300 : 4250, 4027
7276 01:20:18.927115 304 : 4250, 4027
7277 01:20:18.927583 308 : 4253, 4029
7278 01:20:18.927955 312 : 4250, 4027
7279 01:20:18.930718 316 : 4250, 4027
7280 01:20:18.931290 320 : 4361, 4138
7281 01:20:18.933501 324 : 4250, 4027
7282 01:20:18.933980 328 : 4250, 4027
7283 01:20:18.936901 332 : 4361, 4137
7284 01:20:18.937369 336 : 4250, 3608
7285 01:20:18.940207 340 : 4250, 1385
7286 01:20:18.940671
7287 01:20:18.941038 MIOCK jitter meter ch=0
7288 01:20:18.943945
7289 01:20:18.944536 1T = (340-100) = 240 dly cells
7290 01:20:18.950174 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7291 01:20:18.950783 ==
7292 01:20:18.953848 Dram Type= 6, Freq= 0, CH_0, rank 0
7293 01:20:18.956579 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7294 01:20:18.960097 ==
7295 01:20:18.963362 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7296 01:20:18.966936 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7297 01:20:18.973751 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7298 01:20:18.979587 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7299 01:20:18.986411 [CA 0] Center 41 (11~72) winsize 62
7300 01:20:18.989492 [CA 1] Center 41 (11~72) winsize 62
7301 01:20:18.993116 [CA 2] Center 37 (7~68) winsize 62
7302 01:20:18.996448 [CA 3] Center 37 (7~67) winsize 61
7303 01:20:18.999387 [CA 4] Center 35 (5~66) winsize 62
7304 01:20:19.003014 [CA 5] Center 35 (5~65) winsize 61
7305 01:20:19.003576
7306 01:20:19.006077 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7307 01:20:19.006649
7308 01:20:19.009145 [CATrainingPosCal] consider 1 rank data
7309 01:20:19.012653 u2DelayCellTimex100 = 271/100 ps
7310 01:20:19.015949 CA0 delay=41 (11~72),Diff = 6 PI (21 cell)
7311 01:20:19.022502 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7312 01:20:19.026229 CA2 delay=37 (7~68),Diff = 2 PI (7 cell)
7313 01:20:19.029664 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7314 01:20:19.032654 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7315 01:20:19.035910 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7316 01:20:19.036376
7317 01:20:19.039613 CA PerBit enable=1, Macro0, CA PI delay=35
7318 01:20:19.040223
7319 01:20:19.042489 [CBTSetCACLKResult] CA Dly = 35
7320 01:20:19.045809 CS Dly: 11 (0~42)
7321 01:20:19.049169 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7322 01:20:19.052868 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7323 01:20:19.053428 ==
7324 01:20:19.055626 Dram Type= 6, Freq= 0, CH_0, rank 1
7325 01:20:19.062360 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7326 01:20:19.063002 ==
7327 01:20:19.065385 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7328 01:20:19.069031 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7329 01:20:19.075507 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7330 01:20:19.081718 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7331 01:20:19.089099 [CA 0] Center 42 (12~73) winsize 62
7332 01:20:19.092240 [CA 1] Center 41 (11~72) winsize 62
7333 01:20:19.095821 [CA 2] Center 38 (8~68) winsize 61
7334 01:20:19.098855 [CA 3] Center 37 (7~67) winsize 61
7335 01:20:19.102209 [CA 4] Center 35 (5~65) winsize 61
7336 01:20:19.105457 [CA 5] Center 35 (5~66) winsize 62
7337 01:20:19.106055
7338 01:20:19.109099 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7339 01:20:19.109662
7340 01:20:19.112300 [CATrainingPosCal] consider 2 rank data
7341 01:20:19.115174 u2DelayCellTimex100 = 271/100 ps
7342 01:20:19.121859 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7343 01:20:19.125318 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7344 01:20:19.128410 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7345 01:20:19.132081 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7346 01:20:19.134948 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
7347 01:20:19.138491 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7348 01:20:19.138953
7349 01:20:19.142191 CA PerBit enable=1, Macro0, CA PI delay=35
7350 01:20:19.142766
7351 01:20:19.145224 [CBTSetCACLKResult] CA Dly = 35
7352 01:20:19.148631 CS Dly: 11 (0~43)
7353 01:20:19.151751 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7354 01:20:19.154725 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7355 01:20:19.155196
7356 01:20:19.158170 ----->DramcWriteLeveling(PI) begin...
7357 01:20:19.158642 ==
7358 01:20:19.161393 Dram Type= 6, Freq= 0, CH_0, rank 0
7359 01:20:19.168007 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7360 01:20:19.168473 ==
7361 01:20:19.171206 Write leveling (Byte 0): 30 => 30
7362 01:20:19.174493 Write leveling (Byte 1): 23 => 23
7363 01:20:19.174951 DramcWriteLeveling(PI) end<-----
7364 01:20:19.175313
7365 01:20:19.178325 ==
7366 01:20:19.181355 Dram Type= 6, Freq= 0, CH_0, rank 0
7367 01:20:19.184581 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7368 01:20:19.185043 ==
7369 01:20:19.187745 [Gating] SW mode calibration
7370 01:20:19.194955 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7371 01:20:19.197965 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7372 01:20:19.204567 0 12 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7373 01:20:19.207887 0 12 4 | B1->B0 | 2424 3333 | 1 1 | (1 1) (0 0)
7374 01:20:19.210832 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7375 01:20:19.217630 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7376 01:20:19.220876 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7377 01:20:19.224250 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7378 01:20:19.231341 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7379 01:20:19.233932 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7380 01:20:19.237558 0 13 0 | B1->B0 | 3434 2d2d | 1 1 | (1 0) (1 0)
7381 01:20:19.244277 0 13 4 | B1->B0 | 3232 2525 | 1 0 | (1 0) (0 1)
7382 01:20:19.247563 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7383 01:20:19.250735 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7384 01:20:19.257952 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7385 01:20:19.260456 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7386 01:20:19.263825 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7387 01:20:19.270910 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7388 01:20:19.273919 0 14 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (1 1)
7389 01:20:19.277062 0 14 4 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
7390 01:20:19.283676 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7391 01:20:19.286586 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7392 01:20:19.290124 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7393 01:20:19.297144 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7394 01:20:19.299987 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7395 01:20:19.303468 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7396 01:20:19.310122 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7397 01:20:19.313363 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7398 01:20:19.316610 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7399 01:20:19.323783 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7400 01:20:19.326858 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7401 01:20:19.329672 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7402 01:20:19.336099 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7403 01:20:19.339911 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7404 01:20:19.342905 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7405 01:20:19.349685 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7406 01:20:19.352590 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7407 01:20:19.356027 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7408 01:20:19.362507 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7409 01:20:19.365955 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7410 01:20:19.369253 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7411 01:20:19.375611 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7412 01:20:19.379165 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7413 01:20:19.382432 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7414 01:20:19.389001 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7415 01:20:19.392209 Total UI for P1: 0, mck2ui 16
7416 01:20:19.395740 best dqsien dly found for B0: ( 1, 1, 4)
7417 01:20:19.398978 Total UI for P1: 0, mck2ui 16
7418 01:20:19.402576 best dqsien dly found for B1: ( 1, 1, 4)
7419 01:20:19.405626 best DQS0 dly(MCK, UI, PI) = (1, 1, 4)
7420 01:20:19.408797 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7421 01:20:19.409393
7422 01:20:19.412075 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 4)
7423 01:20:19.415286 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7424 01:20:19.418657 [Gating] SW calibration Done
7425 01:20:19.419222 ==
7426 01:20:19.422165 Dram Type= 6, Freq= 0, CH_0, rank 0
7427 01:20:19.425679 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7428 01:20:19.426293 ==
7429 01:20:19.428680 RX Vref Scan: 0
7430 01:20:19.429234
7431 01:20:19.429612 RX Vref 0 -> 0, step: 1
7432 01:20:19.429958
7433 01:20:19.432182 RX Delay 0 -> 252, step: 8
7434 01:20:19.435146 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7435 01:20:19.441780 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7436 01:20:19.445229 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7437 01:20:19.448511 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7438 01:20:19.451684 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7439 01:20:19.455422 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7440 01:20:19.461815 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7441 01:20:19.464931 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7442 01:20:19.468218 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7443 01:20:19.471850 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7444 01:20:19.475085 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7445 01:20:19.481430 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7446 01:20:19.485111 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7447 01:20:19.487947 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7448 01:20:19.491174 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7449 01:20:19.498245 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7450 01:20:19.498806 ==
7451 01:20:19.501558 Dram Type= 6, Freq= 0, CH_0, rank 0
7452 01:20:19.504690 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7453 01:20:19.505250 ==
7454 01:20:19.505619 DQS Delay:
7455 01:20:19.508191 DQS0 = 0, DQS1 = 0
7456 01:20:19.508751 DQM Delay:
7457 01:20:19.510933 DQM0 = 130, DQM1 = 123
7458 01:20:19.511397 DQ Delay:
7459 01:20:19.514455 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7460 01:20:19.517605 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7461 01:20:19.521037 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
7462 01:20:19.524556 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7463 01:20:19.525130
7464 01:20:19.527429
7465 01:20:19.527909 ==
7466 01:20:19.530959 Dram Type= 6, Freq= 0, CH_0, rank 0
7467 01:20:19.534252 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7468 01:20:19.534832 ==
7469 01:20:19.535333
7470 01:20:19.535788
7471 01:20:19.537498 TX Vref Scan disable
7472 01:20:19.537978 == TX Byte 0 ==
7473 01:20:19.544196 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7474 01:20:19.547393 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7475 01:20:19.547973 == TX Byte 1 ==
7476 01:20:19.554113 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7477 01:20:19.557667 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
7478 01:20:19.558286 ==
7479 01:20:19.560387 Dram Type= 6, Freq= 0, CH_0, rank 0
7480 01:20:19.563927 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7481 01:20:19.564497 ==
7482 01:20:19.578093
7483 01:20:19.581449 TX Vref early break, caculate TX vref
7484 01:20:19.584710 TX Vref=16, minBit 10, minWin=21, winSum=370
7485 01:20:19.588108 TX Vref=18, minBit 7, minWin=23, winSum=383
7486 01:20:19.591185 TX Vref=20, minBit 4, minWin=24, winSum=394
7487 01:20:19.594396 TX Vref=22, minBit 8, minWin=24, winSum=399
7488 01:20:19.601231 TX Vref=24, minBit 0, minWin=25, winSum=410
7489 01:20:19.604696 TX Vref=26, minBit 4, minWin=25, winSum=415
7490 01:20:19.608165 TX Vref=28, minBit 8, minWin=24, winSum=415
7491 01:20:19.610740 TX Vref=30, minBit 0, minWin=25, winSum=413
7492 01:20:19.613922 TX Vref=32, minBit 1, minWin=24, winSum=403
7493 01:20:19.617728 TX Vref=34, minBit 0, minWin=24, winSum=393
7494 01:20:19.624433 [TxChooseVref] Worse bit 4, Min win 25, Win sum 415, Final Vref 26
7495 01:20:19.625030
7496 01:20:19.627631 Final TX Range 0 Vref 26
7497 01:20:19.628203
7498 01:20:19.628695 ==
7499 01:20:19.630486 Dram Type= 6, Freq= 0, CH_0, rank 0
7500 01:20:19.634364 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7501 01:20:19.634974 ==
7502 01:20:19.635466
7503 01:20:19.635920
7504 01:20:19.637229 TX Vref Scan disable
7505 01:20:19.644120 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7506 01:20:19.644688 == TX Byte 0 ==
7507 01:20:19.647606 u2DelayCellOfst[0]=10 cells (3 PI)
7508 01:20:19.650777 u2DelayCellOfst[1]=18 cells (5 PI)
7509 01:20:19.654178 u2DelayCellOfst[2]=10 cells (3 PI)
7510 01:20:19.657143 u2DelayCellOfst[3]=10 cells (3 PI)
7511 01:20:19.660753 u2DelayCellOfst[4]=10 cells (3 PI)
7512 01:20:19.663864 u2DelayCellOfst[5]=0 cells (0 PI)
7513 01:20:19.667355 u2DelayCellOfst[6]=18 cells (5 PI)
7514 01:20:19.670291 u2DelayCellOfst[7]=18 cells (5 PI)
7515 01:20:19.673453 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7516 01:20:19.677038 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7517 01:20:19.680435 == TX Byte 1 ==
7518 01:20:19.684104 u2DelayCellOfst[8]=3 cells (1 PI)
7519 01:20:19.686798 u2DelayCellOfst[9]=0 cells (0 PI)
7520 01:20:19.690265 u2DelayCellOfst[10]=7 cells (2 PI)
7521 01:20:19.690842 u2DelayCellOfst[11]=3 cells (1 PI)
7522 01:20:19.693579 u2DelayCellOfst[12]=14 cells (4 PI)
7523 01:20:19.696984 u2DelayCellOfst[13]=14 cells (4 PI)
7524 01:20:19.700464 u2DelayCellOfst[14]=18 cells (5 PI)
7525 01:20:19.703519 u2DelayCellOfst[15]=14 cells (4 PI)
7526 01:20:19.710000 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
7527 01:20:19.713077 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
7528 01:20:19.713559 DramC Write-DBI on
7529 01:20:19.716759 ==
7530 01:20:19.717368 Dram Type= 6, Freq= 0, CH_0, rank 0
7531 01:20:19.723534 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7532 01:20:19.724100 ==
7533 01:20:19.724480
7534 01:20:19.724825
7535 01:20:19.726212 TX Vref Scan disable
7536 01:20:19.726690 == TX Byte 0 ==
7537 01:20:19.733296 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7538 01:20:19.733861 == TX Byte 1 ==
7539 01:20:19.736138 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
7540 01:20:19.739565 DramC Write-DBI off
7541 01:20:19.740045
7542 01:20:19.740416 [DATLAT]
7543 01:20:19.743230 Freq=1600, CH0 RK0
7544 01:20:19.743790
7545 01:20:19.744166 DATLAT Default: 0xf
7546 01:20:19.746306 0, 0xFFFF, sum = 0
7547 01:20:19.746776 1, 0xFFFF, sum = 0
7548 01:20:19.749713 2, 0xFFFF, sum = 0
7549 01:20:19.750340 3, 0xFFFF, sum = 0
7550 01:20:19.752937 4, 0xFFFF, sum = 0
7551 01:20:19.753527 5, 0xFFFF, sum = 0
7552 01:20:19.756434 6, 0xFFFF, sum = 0
7553 01:20:19.759401 7, 0xFFFF, sum = 0
7554 01:20:19.759886 8, 0xFFFF, sum = 0
7555 01:20:19.762577 9, 0xFFFF, sum = 0
7556 01:20:19.763048 10, 0xFFFF, sum = 0
7557 01:20:19.765856 11, 0xFFFF, sum = 0
7558 01:20:19.766366 12, 0x8FFF, sum = 0
7559 01:20:19.769242 13, 0x0, sum = 1
7560 01:20:19.769730 14, 0x0, sum = 2
7561 01:20:19.772865 15, 0x0, sum = 3
7562 01:20:19.773435 16, 0x0, sum = 4
7563 01:20:19.773815 best_step = 14
7564 01:20:19.776109
7565 01:20:19.776663 ==
7566 01:20:19.779453 Dram Type= 6, Freq= 0, CH_0, rank 0
7567 01:20:19.782474 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7568 01:20:19.782941 ==
7569 01:20:19.783314 RX Vref Scan: 1
7570 01:20:19.783663
7571 01:20:19.786089 Set Vref Range= 24 -> 127
7572 01:20:19.786552
7573 01:20:19.789526 RX Vref 24 -> 127, step: 1
7574 01:20:19.790140
7575 01:20:19.792577 RX Delay 11 -> 252, step: 4
7576 01:20:19.793054
7577 01:20:19.796277 Set Vref, RX VrefLevel [Byte0]: 24
7578 01:20:19.799276 [Byte1]: 24
7579 01:20:19.799836
7580 01:20:19.802440 Set Vref, RX VrefLevel [Byte0]: 25
7581 01:20:19.806088 [Byte1]: 25
7582 01:20:19.806663
7583 01:20:19.809223 Set Vref, RX VrefLevel [Byte0]: 26
7584 01:20:19.812260 [Byte1]: 26
7585 01:20:19.816337
7586 01:20:19.816895 Set Vref, RX VrefLevel [Byte0]: 27
7587 01:20:19.819921 [Byte1]: 27
7588 01:20:19.823870
7589 01:20:19.824434 Set Vref, RX VrefLevel [Byte0]: 28
7590 01:20:19.826975 [Byte1]: 28
7591 01:20:19.831508
7592 01:20:19.832069 Set Vref, RX VrefLevel [Byte0]: 29
7593 01:20:19.834648 [Byte1]: 29
7594 01:20:19.839029
7595 01:20:19.839592 Set Vref, RX VrefLevel [Byte0]: 30
7596 01:20:19.842601 [Byte1]: 30
7597 01:20:19.846843
7598 01:20:19.847409 Set Vref, RX VrefLevel [Byte0]: 31
7599 01:20:19.849885 [Byte1]: 31
7600 01:20:19.854468
7601 01:20:19.855025 Set Vref, RX VrefLevel [Byte0]: 32
7602 01:20:19.858171 [Byte1]: 32
7603 01:20:19.861758
7604 01:20:19.862372 Set Vref, RX VrefLevel [Byte0]: 33
7605 01:20:19.865247 [Byte1]: 33
7606 01:20:19.869490
7607 01:20:19.869962 Set Vref, RX VrefLevel [Byte0]: 34
7608 01:20:19.872766 [Byte1]: 34
7609 01:20:19.877485
7610 01:20:19.878104 Set Vref, RX VrefLevel [Byte0]: 35
7611 01:20:19.880469 [Byte1]: 35
7612 01:20:19.884847
7613 01:20:19.885420 Set Vref, RX VrefLevel [Byte0]: 36
7614 01:20:19.888195 [Byte1]: 36
7615 01:20:19.892180
7616 01:20:19.892709 Set Vref, RX VrefLevel [Byte0]: 37
7617 01:20:19.895677 [Byte1]: 37
7618 01:20:19.899786
7619 01:20:19.900256 Set Vref, RX VrefLevel [Byte0]: 38
7620 01:20:19.906600 [Byte1]: 38
7621 01:20:19.907187
7622 01:20:19.909634 Set Vref, RX VrefLevel [Byte0]: 39
7623 01:20:19.913055 [Byte1]: 39
7624 01:20:19.913524
7625 01:20:19.916010 Set Vref, RX VrefLevel [Byte0]: 40
7626 01:20:19.919686 [Byte1]: 40
7627 01:20:19.920267
7628 01:20:19.922918 Set Vref, RX VrefLevel [Byte0]: 41
7629 01:20:19.926483 [Byte1]: 41
7630 01:20:19.930291
7631 01:20:19.930755 Set Vref, RX VrefLevel [Byte0]: 42
7632 01:20:19.933630 [Byte1]: 42
7633 01:20:19.937910
7634 01:20:19.938471 Set Vref, RX VrefLevel [Byte0]: 43
7635 01:20:19.941513 [Byte1]: 43
7636 01:20:19.945364
7637 01:20:19.945830 Set Vref, RX VrefLevel [Byte0]: 44
7638 01:20:19.949039 [Byte1]: 44
7639 01:20:19.953725
7640 01:20:19.954363 Set Vref, RX VrefLevel [Byte0]: 45
7641 01:20:19.956734 [Byte1]: 45
7642 01:20:19.960756
7643 01:20:19.961243 Set Vref, RX VrefLevel [Byte0]: 46
7644 01:20:19.963893 [Byte1]: 46
7645 01:20:19.968517
7646 01:20:19.969110 Set Vref, RX VrefLevel [Byte0]: 47
7647 01:20:19.971637 [Byte1]: 47
7648 01:20:19.975927
7649 01:20:19.976390 Set Vref, RX VrefLevel [Byte0]: 48
7650 01:20:19.979447 [Byte1]: 48
7651 01:20:19.983544
7652 01:20:19.983955 Set Vref, RX VrefLevel [Byte0]: 49
7653 01:20:19.986964 [Byte1]: 49
7654 01:20:19.991340
7655 01:20:19.991935 Set Vref, RX VrefLevel [Byte0]: 50
7656 01:20:19.994473 [Byte1]: 50
7657 01:20:19.998696
7658 01:20:19.999184 Set Vref, RX VrefLevel [Byte0]: 51
7659 01:20:20.005398 [Byte1]: 51
7660 01:20:20.005957
7661 01:20:20.008467 Set Vref, RX VrefLevel [Byte0]: 52
7662 01:20:20.011971 [Byte1]: 52
7663 01:20:20.012436
7664 01:20:20.015308 Set Vref, RX VrefLevel [Byte0]: 53
7665 01:20:20.018554 [Byte1]: 53
7666 01:20:20.021512
7667 01:20:20.021970 Set Vref, RX VrefLevel [Byte0]: 54
7668 01:20:20.025359 [Byte1]: 54
7669 01:20:20.029555
7670 01:20:20.030156 Set Vref, RX VrefLevel [Byte0]: 55
7671 01:20:20.032674 [Byte1]: 55
7672 01:20:20.036821
7673 01:20:20.037285 Set Vref, RX VrefLevel [Byte0]: 56
7674 01:20:20.040243 [Byte1]: 56
7675 01:20:20.044725
7676 01:20:20.045295 Set Vref, RX VrefLevel [Byte0]: 57
7677 01:20:20.047768 [Byte1]: 57
7678 01:20:20.052214
7679 01:20:20.052676 Set Vref, RX VrefLevel [Byte0]: 58
7680 01:20:20.055347 [Byte1]: 58
7681 01:20:20.059917
7682 01:20:20.060375 Set Vref, RX VrefLevel [Byte0]: 59
7683 01:20:20.062843 [Byte1]: 59
7684 01:20:20.067136
7685 01:20:20.067611 Set Vref, RX VrefLevel [Byte0]: 60
7686 01:20:20.070673 [Byte1]: 60
7687 01:20:20.074847
7688 01:20:20.075322 Set Vref, RX VrefLevel [Byte0]: 61
7689 01:20:20.078397 [Byte1]: 61
7690 01:20:20.082723
7691 01:20:20.083217 Set Vref, RX VrefLevel [Byte0]: 62
7692 01:20:20.085795 [Byte1]: 62
7693 01:20:20.090235
7694 01:20:20.090711 Set Vref, RX VrefLevel [Byte0]: 63
7695 01:20:20.093476 [Byte1]: 63
7696 01:20:20.097972
7697 01:20:20.098581 Set Vref, RX VrefLevel [Byte0]: 64
7698 01:20:20.101034 [Byte1]: 64
7699 01:20:20.105340
7700 01:20:20.105812 Set Vref, RX VrefLevel [Byte0]: 65
7701 01:20:20.109146 [Byte1]: 65
7702 01:20:20.113023
7703 01:20:20.113589 Set Vref, RX VrefLevel [Byte0]: 66
7704 01:20:20.116324 [Byte1]: 66
7705 01:20:20.120635
7706 01:20:20.121254 Set Vref, RX VrefLevel [Byte0]: 67
7707 01:20:20.124393 [Byte1]: 67
7708 01:20:20.128241
7709 01:20:20.128720 Set Vref, RX VrefLevel [Byte0]: 68
7710 01:20:20.131688 [Byte1]: 68
7711 01:20:20.135829
7712 01:20:20.136317 Set Vref, RX VrefLevel [Byte0]: 69
7713 01:20:20.139254 [Byte1]: 69
7714 01:20:20.143336
7715 01:20:20.143819 Set Vref, RX VrefLevel [Byte0]: 70
7716 01:20:20.146639 [Byte1]: 70
7717 01:20:20.150836
7718 01:20:20.151312 Final RX Vref Byte 0 = 50 to rank0
7719 01:20:20.154721 Final RX Vref Byte 1 = 55 to rank0
7720 01:20:20.157486 Final RX Vref Byte 0 = 50 to rank1
7721 01:20:20.161500 Final RX Vref Byte 1 = 55 to rank1==
7722 01:20:20.164203 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 01:20:20.170831 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7724 01:20:20.171404 ==
7725 01:20:20.171898 DQS Delay:
7726 01:20:20.172348 DQS0 = 0, DQS1 = 0
7727 01:20:20.174130 DQM Delay:
7728 01:20:20.174607 DQM0 = 127, DQM1 = 120
7729 01:20:20.177650 DQ Delay:
7730 01:20:20.181241 DQ0 =124, DQ1 =128, DQ2 =124, DQ3 =124
7731 01:20:20.184342 DQ4 =130, DQ5 =116, DQ6 =136, DQ7 =134
7732 01:20:20.187337 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
7733 01:20:20.191167 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7734 01:20:20.191733
7735 01:20:20.192125
7736 01:20:20.192475
7737 01:20:20.193998 [DramC_TX_OE_Calibration] TA2
7738 01:20:20.197439 Original DQ_B0 (3 6) =30, OEN = 27
7739 01:20:20.200827 Original DQ_B1 (3 6) =30, OEN = 27
7740 01:20:20.204138 24, 0x0, End_B0=24 End_B1=24
7741 01:20:20.204717 25, 0x0, End_B0=25 End_B1=25
7742 01:20:20.207746 26, 0x0, End_B0=26 End_B1=26
7743 01:20:20.210553 27, 0x0, End_B0=27 End_B1=27
7744 01:20:20.213853 28, 0x0, End_B0=28 End_B1=28
7745 01:20:20.217388 29, 0x0, End_B0=29 End_B1=29
7746 01:20:20.217955 30, 0x0, End_B0=30 End_B1=30
7747 01:20:20.220812 31, 0x4545, End_B0=30 End_B1=30
7748 01:20:20.224133 Byte0 end_step=30 best_step=27
7749 01:20:20.227733 Byte1 end_step=30 best_step=27
7750 01:20:20.230647 Byte0 TX OE(2T, 0.5T) = (3, 3)
7751 01:20:20.233835 Byte1 TX OE(2T, 0.5T) = (3, 3)
7752 01:20:20.234452
7753 01:20:20.234832
7754 01:20:20.240832 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
7755 01:20:20.244022 CH0 RK0: MR19=303, MR18=1B1B
7756 01:20:20.250552 CH0_RK0: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
7757 01:20:20.251142
7758 01:20:20.253534 ----->DramcWriteLeveling(PI) begin...
7759 01:20:20.254167 ==
7760 01:20:20.257455 Dram Type= 6, Freq= 0, CH_0, rank 1
7761 01:20:20.260039 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7762 01:20:20.260526 ==
7763 01:20:20.263372 Write leveling (Byte 0): 28 => 28
7764 01:20:20.266686 Write leveling (Byte 1): 24 => 24
7765 01:20:20.270009 DramcWriteLeveling(PI) end<-----
7766 01:20:20.270647
7767 01:20:20.271020 ==
7768 01:20:20.273252 Dram Type= 6, Freq= 0, CH_0, rank 1
7769 01:20:20.276849 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7770 01:20:20.280394 ==
7771 01:20:20.280964 [Gating] SW mode calibration
7772 01:20:20.286720 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7773 01:20:20.293165 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7774 01:20:20.296695 0 12 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7775 01:20:20.303103 0 12 4 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
7776 01:20:20.306628 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7777 01:20:20.309600 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7778 01:20:20.316527 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7779 01:20:20.320317 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7780 01:20:20.322937 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7781 01:20:20.329923 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7782 01:20:20.333085 0 13 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
7783 01:20:20.336348 0 13 4 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (1 0)
7784 01:20:20.342963 0 13 8 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
7785 01:20:20.346275 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7786 01:20:20.349659 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7787 01:20:20.356474 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7788 01:20:20.359706 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7789 01:20:20.362674 0 13 28 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
7790 01:20:20.369475 0 14 0 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
7791 01:20:20.372781 0 14 4 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
7792 01:20:20.376046 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7793 01:20:20.382844 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7794 01:20:20.386356 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7795 01:20:20.389654 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7796 01:20:20.395641 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7797 01:20:20.399084 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7798 01:20:20.402508 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7799 01:20:20.408867 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7800 01:20:20.412495 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7801 01:20:20.415592 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7802 01:20:20.422252 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7803 01:20:20.425460 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7804 01:20:20.429157 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7805 01:20:20.435473 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7806 01:20:20.438677 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7807 01:20:20.441796 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7808 01:20:20.448783 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7809 01:20:20.452487 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7810 01:20:20.455261 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7811 01:20:20.461991 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7812 01:20:20.464938 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7813 01:20:20.468610 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7814 01:20:20.475462 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7815 01:20:20.478347 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7816 01:20:20.481776 Total UI for P1: 0, mck2ui 16
7817 01:20:20.484824 best dqsien dly found for B0: ( 1, 0, 30)
7818 01:20:20.488283 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7819 01:20:20.491395 Total UI for P1: 0, mck2ui 16
7820 01:20:20.494944 best dqsien dly found for B1: ( 1, 1, 4)
7821 01:20:20.498426 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7822 01:20:20.501664 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7823 01:20:20.502275
7824 01:20:20.505020 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7825 01:20:20.508203 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7826 01:20:20.511638 [Gating] SW calibration Done
7827 01:20:20.512201 ==
7828 01:20:20.514587 Dram Type= 6, Freq= 0, CH_0, rank 1
7829 01:20:20.521622 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7830 01:20:20.522235 ==
7831 01:20:20.522612 RX Vref Scan: 0
7832 01:20:20.522953
7833 01:20:20.524730 RX Vref 0 -> 0, step: 1
7834 01:20:20.525295
7835 01:20:20.528208 RX Delay 0 -> 252, step: 8
7836 01:20:20.531481 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7837 01:20:20.534968 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7838 01:20:20.537848 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7839 01:20:20.541310 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7840 01:20:20.548470 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7841 01:20:20.551226 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7842 01:20:20.554450 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7843 01:20:20.557876 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7844 01:20:20.561176 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7845 01:20:20.567917 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7846 01:20:20.570619 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7847 01:20:20.574202 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7848 01:20:20.577934 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7849 01:20:20.584116 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7850 01:20:20.587911 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7851 01:20:20.590547 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7852 01:20:20.591012 ==
7853 01:20:20.594227 Dram Type= 6, Freq= 0, CH_0, rank 1
7854 01:20:20.597491 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7855 01:20:20.598118 ==
7856 01:20:20.600738 DQS Delay:
7857 01:20:20.601302 DQS0 = 0, DQS1 = 0
7858 01:20:20.603658 DQM Delay:
7859 01:20:20.604180 DQM0 = 130, DQM1 = 123
7860 01:20:20.606970 DQ Delay:
7861 01:20:20.610450 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =123
7862 01:20:20.613836 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7863 01:20:20.617037 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =115
7864 01:20:20.620115 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7865 01:20:20.620582
7866 01:20:20.620948
7867 01:20:20.621285 ==
7868 01:20:20.623449 Dram Type= 6, Freq= 0, CH_0, rank 1
7869 01:20:20.627344 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7870 01:20:20.628023 ==
7871 01:20:20.628408
7872 01:20:20.630254
7873 01:20:20.630711 TX Vref Scan disable
7874 01:20:20.633590 == TX Byte 0 ==
7875 01:20:20.636518 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7876 01:20:20.639871 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7877 01:20:20.643269 == TX Byte 1 ==
7878 01:20:20.646937 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7879 01:20:20.650281 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7880 01:20:20.650848 ==
7881 01:20:20.653314 Dram Type= 6, Freq= 0, CH_0, rank 1
7882 01:20:20.660091 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7883 01:20:20.660670 ==
7884 01:20:20.673232
7885 01:20:20.676152 TX Vref early break, caculate TX vref
7886 01:20:20.679512 TX Vref=16, minBit 1, minWin=22, winSum=374
7887 01:20:20.683023 TX Vref=18, minBit 1, minWin=23, winSum=381
7888 01:20:20.686565 TX Vref=20, minBit 8, minWin=23, winSum=393
7889 01:20:20.690402 TX Vref=22, minBit 8, minWin=24, winSum=400
7890 01:20:20.692917 TX Vref=24, minBit 1, minWin=24, winSum=402
7891 01:20:20.699539 TX Vref=26, minBit 8, minWin=25, winSum=417
7892 01:20:20.703131 TX Vref=28, minBit 6, minWin=25, winSum=416
7893 01:20:20.706227 TX Vref=30, minBit 4, minWin=25, winSum=412
7894 01:20:20.709815 TX Vref=32, minBit 7, minWin=24, winSum=403
7895 01:20:20.713060 TX Vref=34, minBit 3, minWin=24, winSum=397
7896 01:20:20.715659 TX Vref=36, minBit 8, minWin=23, winSum=389
7897 01:20:20.722555 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 26
7898 01:20:20.723166
7899 01:20:20.725707 Final TX Range 0 Vref 26
7900 01:20:20.726315
7901 01:20:20.726688 ==
7902 01:20:20.729398 Dram Type= 6, Freq= 0, CH_0, rank 1
7903 01:20:20.732501 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7904 01:20:20.733086 ==
7905 01:20:20.735821
7906 01:20:20.736282
7907 01:20:20.736649 TX Vref Scan disable
7908 01:20:20.742184 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7909 01:20:20.742752 == TX Byte 0 ==
7910 01:20:20.746011 u2DelayCellOfst[0]=10 cells (3 PI)
7911 01:20:20.748978 u2DelayCellOfst[1]=18 cells (5 PI)
7912 01:20:20.752323 u2DelayCellOfst[2]=10 cells (3 PI)
7913 01:20:20.755750 u2DelayCellOfst[3]=10 cells (3 PI)
7914 01:20:20.758935 u2DelayCellOfst[4]=10 cells (3 PI)
7915 01:20:20.762477 u2DelayCellOfst[5]=0 cells (0 PI)
7916 01:20:20.765159 u2DelayCellOfst[6]=18 cells (5 PI)
7917 01:20:20.768533 u2DelayCellOfst[7]=18 cells (5 PI)
7918 01:20:20.771732 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7919 01:20:20.775049 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7920 01:20:20.778611 == TX Byte 1 ==
7921 01:20:20.781859 u2DelayCellOfst[8]=3 cells (1 PI)
7922 01:20:20.784948 u2DelayCellOfst[9]=0 cells (0 PI)
7923 01:20:20.788319 u2DelayCellOfst[10]=14 cells (4 PI)
7924 01:20:20.791773 u2DelayCellOfst[11]=7 cells (2 PI)
7925 01:20:20.794908 u2DelayCellOfst[12]=18 cells (5 PI)
7926 01:20:20.798258 u2DelayCellOfst[13]=18 cells (5 PI)
7927 01:20:20.801731 u2DelayCellOfst[14]=21 cells (6 PI)
7928 01:20:20.805000 u2DelayCellOfst[15]=18 cells (5 PI)
7929 01:20:20.808627 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
7930 01:20:20.811591 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7931 01:20:20.814740 DramC Write-DBI on
7932 01:20:20.815204 ==
7933 01:20:20.818368 Dram Type= 6, Freq= 0, CH_0, rank 1
7934 01:20:20.821644 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7935 01:20:20.822253 ==
7936 01:20:20.822630
7937 01:20:20.822977
7938 01:20:20.824828 TX Vref Scan disable
7939 01:20:20.825290 == TX Byte 0 ==
7940 01:20:20.831421 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7941 01:20:20.832008 == TX Byte 1 ==
7942 01:20:20.834805 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
7943 01:20:20.837905 DramC Write-DBI off
7944 01:20:20.838416
7945 01:20:20.838784 [DATLAT]
7946 01:20:20.841261 Freq=1600, CH0 RK1
7947 01:20:20.841735
7948 01:20:20.842144 DATLAT Default: 0xe
7949 01:20:20.844662 0, 0xFFFF, sum = 0
7950 01:20:20.845126 1, 0xFFFF, sum = 0
7951 01:20:20.848566 2, 0xFFFF, sum = 0
7952 01:20:20.851470 3, 0xFFFF, sum = 0
7953 01:20:20.852040 4, 0xFFFF, sum = 0
7954 01:20:20.854690 5, 0xFFFF, sum = 0
7955 01:20:20.855263 6, 0xFFFF, sum = 0
7956 01:20:20.858134 7, 0xFFFF, sum = 0
7957 01:20:20.858708 8, 0xFFFF, sum = 0
7958 01:20:20.861237 9, 0xFFFF, sum = 0
7959 01:20:20.861810 10, 0xFFFF, sum = 0
7960 01:20:20.864360 11, 0xFFFF, sum = 0
7961 01:20:20.864829 12, 0x8FFF, sum = 0
7962 01:20:20.867697 13, 0x0, sum = 1
7963 01:20:20.868168 14, 0x0, sum = 2
7964 01:20:20.871410 15, 0x0, sum = 3
7965 01:20:20.871881 16, 0x0, sum = 4
7966 01:20:20.874218 best_step = 14
7967 01:20:20.874679
7968 01:20:20.875042 ==
7969 01:20:20.877487 Dram Type= 6, Freq= 0, CH_0, rank 1
7970 01:20:20.881285 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7971 01:20:20.881864 ==
7972 01:20:20.884226 RX Vref Scan: 0
7973 01:20:20.884688
7974 01:20:20.885055 RX Vref 0 -> 0, step: 1
7975 01:20:20.885495
7976 01:20:20.888159 RX Delay 11 -> 252, step: 4
7977 01:20:20.890734 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7978 01:20:20.897525 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
7979 01:20:20.900697 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7980 01:20:20.904428 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7981 01:20:20.907488 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7982 01:20:20.914204 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7983 01:20:20.917522 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
7984 01:20:20.920647 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7985 01:20:20.923584 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7986 01:20:20.927197 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7987 01:20:20.933910 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7988 01:20:20.937028 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7989 01:20:20.940053 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7990 01:20:20.943696 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7991 01:20:20.947185 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
7992 01:20:20.954207 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7993 01:20:20.954764 ==
7994 01:20:20.956843 Dram Type= 6, Freq= 0, CH_0, rank 1
7995 01:20:20.960056 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7996 01:20:20.960624 ==
7997 01:20:20.960998 DQS Delay:
7998 01:20:20.963338 DQS0 = 0, DQS1 = 0
7999 01:20:20.963797 DQM Delay:
8000 01:20:20.966729 DQM0 = 127, DQM1 = 120
8001 01:20:20.967304 DQ Delay:
8002 01:20:20.970273 DQ0 =122, DQ1 =130, DQ2 =126, DQ3 =122
8003 01:20:20.973417 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =138
8004 01:20:20.976950 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
8005 01:20:20.983132 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
8006 01:20:20.983681
8007 01:20:20.984047
8008 01:20:20.984388
8009 01:20:20.984712 [DramC_TX_OE_Calibration] TA2
8010 01:20:20.986710 Original DQ_B0 (3 6) =30, OEN = 27
8011 01:20:20.990082 Original DQ_B1 (3 6) =30, OEN = 27
8012 01:20:20.992940 24, 0x0, End_B0=24 End_B1=24
8013 01:20:20.996580 25, 0x0, End_B0=25 End_B1=25
8014 01:20:20.999505 26, 0x0, End_B0=26 End_B1=26
8015 01:20:21.003122 27, 0x0, End_B0=27 End_B1=27
8016 01:20:21.003695 28, 0x0, End_B0=28 End_B1=28
8017 01:20:21.006058 29, 0x0, End_B0=29 End_B1=29
8018 01:20:21.009637 30, 0x0, End_B0=30 End_B1=30
8019 01:20:21.012839 31, 0x5151, End_B0=30 End_B1=30
8020 01:20:21.016503 Byte0 end_step=30 best_step=27
8021 01:20:21.017067 Byte1 end_step=30 best_step=27
8022 01:20:21.019716 Byte0 TX OE(2T, 0.5T) = (3, 3)
8023 01:20:21.022789 Byte1 TX OE(2T, 0.5T) = (3, 3)
8024 01:20:21.023248
8025 01:20:21.023611
8026 01:20:21.032594 [DQSOSCAuto] RK1, (LSB)MR18= 0x2323, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
8027 01:20:21.033166 CH0 RK1: MR19=303, MR18=2323
8028 01:20:21.039180 CH0_RK1: MR19=0x303, MR18=0x2323, DQSOSC=392, MR23=63, INC=24, DEC=16
8029 01:20:21.042632 [RxdqsGatingPostProcess] freq 1600
8030 01:20:21.049325 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8031 01:20:21.052475 Pre-setting of DQS Precalculation
8032 01:20:21.056177 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8033 01:20:21.056747 ==
8034 01:20:21.058821 Dram Type= 6, Freq= 0, CH_1, rank 0
8035 01:20:21.065704 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8036 01:20:21.066422 ==
8037 01:20:21.069029 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8038 01:20:21.075576 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8039 01:20:21.078716 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8040 01:20:21.085493 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8041 01:20:21.092479 [CA 0] Center 41 (11~72) winsize 62
8042 01:20:21.096079 [CA 1] Center 41 (11~72) winsize 62
8043 01:20:21.099105 [CA 2] Center 37 (8~67) winsize 60
8044 01:20:21.102616 [CA 3] Center 36 (7~66) winsize 60
8045 01:20:21.105900 [CA 4] Center 34 (4~64) winsize 61
8046 01:20:21.108951 [CA 5] Center 34 (5~64) winsize 60
8047 01:20:21.109518
8048 01:20:21.112376 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8049 01:20:21.112945
8050 01:20:21.115533 [CATrainingPosCal] consider 1 rank data
8051 01:20:21.118870 u2DelayCellTimex100 = 271/100 ps
8052 01:20:21.122142 CA0 delay=41 (11~72),Diff = 7 PI (25 cell)
8053 01:20:21.129102 CA1 delay=41 (11~72),Diff = 7 PI (25 cell)
8054 01:20:21.132196 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
8055 01:20:21.135589 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8056 01:20:21.138583 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8057 01:20:21.142450 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8058 01:20:21.143014
8059 01:20:21.145731 CA PerBit enable=1, Macro0, CA PI delay=34
8060 01:20:21.146347
8061 01:20:21.148946 [CBTSetCACLKResult] CA Dly = 34
8062 01:20:21.152278 CS Dly: 8 (0~39)
8063 01:20:21.155371 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8064 01:20:21.158841 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8065 01:20:21.159439 ==
8066 01:20:21.162323 Dram Type= 6, Freq= 0, CH_1, rank 1
8067 01:20:21.168846 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8068 01:20:21.169499 ==
8069 01:20:21.171744 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8070 01:20:21.178060 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8071 01:20:21.181956 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8072 01:20:21.188080 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8073 01:20:21.195193 [CA 0] Center 41 (11~71) winsize 61
8074 01:20:21.198008 [CA 1] Center 41 (10~72) winsize 63
8075 01:20:21.201337 [CA 2] Center 36 (7~66) winsize 60
8076 01:20:21.204967 [CA 3] Center 36 (7~65) winsize 59
8077 01:20:21.208134 [CA 4] Center 34 (5~64) winsize 60
8078 01:20:21.211878 [CA 5] Center 34 (5~64) winsize 60
8079 01:20:21.212445
8080 01:20:21.214821 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8081 01:20:21.215316
8082 01:20:21.218348 [CATrainingPosCal] consider 2 rank data
8083 01:20:21.221436 u2DelayCellTimex100 = 271/100 ps
8084 01:20:21.225003 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8085 01:20:21.231570 CA1 delay=41 (11~72),Diff = 7 PI (25 cell)
8086 01:20:21.235247 CA2 delay=37 (8~66),Diff = 3 PI (10 cell)
8087 01:20:21.238106 CA3 delay=36 (7~65),Diff = 2 PI (7 cell)
8088 01:20:21.241219 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
8089 01:20:21.245030 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8090 01:20:21.245497
8091 01:20:21.247885 CA PerBit enable=1, Macro0, CA PI delay=34
8092 01:20:21.248354
8093 01:20:21.251146 [CBTSetCACLKResult] CA Dly = 34
8094 01:20:21.254364 CS Dly: 8 (0~40)
8095 01:20:21.257841 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8096 01:20:21.261440 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8097 01:20:21.262014
8098 01:20:21.264385 ----->DramcWriteLeveling(PI) begin...
8099 01:20:21.264865 ==
8100 01:20:21.268102 Dram Type= 6, Freq= 0, CH_1, rank 0
8101 01:20:21.274494 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8102 01:20:21.274970 ==
8103 01:20:21.277546 Write leveling (Byte 0): 21 => 21
8104 01:20:21.278011 Write leveling (Byte 1): 21 => 21
8105 01:20:21.281040 DramcWriteLeveling(PI) end<-----
8106 01:20:21.281509
8107 01:20:21.284108 ==
8108 01:20:21.284577 Dram Type= 6, Freq= 0, CH_1, rank 0
8109 01:20:21.291052 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8110 01:20:21.291552 ==
8111 01:20:21.294184 [Gating] SW mode calibration
8112 01:20:21.300830 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8113 01:20:21.304214 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8114 01:20:21.310733 0 12 0 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
8115 01:20:21.314395 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8116 01:20:21.317431 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8117 01:20:21.323643 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8118 01:20:21.326982 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8119 01:20:21.330925 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8120 01:20:21.337475 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8121 01:20:21.340498 0 12 28 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 0)
8122 01:20:21.343770 0 13 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (1 0)
8123 01:20:21.350245 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8124 01:20:21.354335 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8125 01:20:21.357080 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8126 01:20:21.363345 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8127 01:20:21.367008 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8128 01:20:21.370213 0 13 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8129 01:20:21.376783 0 13 28 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
8130 01:20:21.380419 0 14 0 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
8131 01:20:21.383482 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8132 01:20:21.390264 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8133 01:20:21.393470 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8134 01:20:21.397178 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8135 01:20:21.403301 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8136 01:20:21.406651 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8137 01:20:21.409942 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8138 01:20:21.416320 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8139 01:20:21.419779 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8140 01:20:21.423268 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8141 01:20:21.429807 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8142 01:20:21.432983 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8143 01:20:21.436422 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8144 01:20:21.442848 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8145 01:20:21.446247 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8146 01:20:21.449581 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8147 01:20:21.456277 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 01:20:21.459131 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8149 01:20:21.462509 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 01:20:21.469282 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8151 01:20:21.472631 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8152 01:20:21.475688 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8153 01:20:21.482345 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8154 01:20:21.485732 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8155 01:20:21.489274 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8156 01:20:21.492454 Total UI for P1: 0, mck2ui 16
8157 01:20:21.495837 best dqsien dly found for B0: ( 1, 0, 28)
8158 01:20:21.502860 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8159 01:20:21.503431 Total UI for P1: 0, mck2ui 16
8160 01:20:21.505869 best dqsien dly found for B1: ( 1, 1, 4)
8161 01:20:21.512408 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
8162 01:20:21.515733 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
8163 01:20:21.516201
8164 01:20:21.518928 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
8165 01:20:21.522413 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
8166 01:20:21.525721 [Gating] SW calibration Done
8167 01:20:21.526240 ==
8168 01:20:21.528845 Dram Type= 6, Freq= 0, CH_1, rank 0
8169 01:20:21.532150 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8170 01:20:21.532709 ==
8171 01:20:21.536028 RX Vref Scan: 0
8172 01:20:21.536587
8173 01:20:21.536965 RX Vref 0 -> 0, step: 1
8174 01:20:21.537315
8175 01:20:21.538595 RX Delay 0 -> 252, step: 8
8176 01:20:21.541965 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8177 01:20:21.545351 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8178 01:20:21.552424 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8179 01:20:21.555338 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8180 01:20:21.558337 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8181 01:20:21.561724 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8182 01:20:21.565002 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8183 01:20:21.571525 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8184 01:20:21.574776 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8185 01:20:21.578488 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8186 01:20:21.581572 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8187 01:20:21.585021 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8188 01:20:21.591724 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8189 01:20:21.594827 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8190 01:20:21.598241 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8191 01:20:21.601944 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8192 01:20:21.604843 ==
8193 01:20:21.605406 Dram Type= 6, Freq= 0, CH_1, rank 0
8194 01:20:21.611057 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8195 01:20:21.611610 ==
8196 01:20:21.611982 DQS Delay:
8197 01:20:21.614434 DQS0 = 0, DQS1 = 0
8198 01:20:21.614897 DQM Delay:
8199 01:20:21.618369 DQM0 = 129, DQM1 = 125
8200 01:20:21.618927 DQ Delay:
8201 01:20:21.621484 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =127
8202 01:20:21.624787 DQ4 =127, DQ5 =139, DQ6 =135, DQ7 =127
8203 01:20:21.628125 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8204 01:20:21.631673 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8205 01:20:21.632284
8206 01:20:21.632673
8207 01:20:21.633022 ==
8208 01:20:21.634406 Dram Type= 6, Freq= 0, CH_1, rank 0
8209 01:20:21.641279 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8210 01:20:21.641843 ==
8211 01:20:21.642334
8212 01:20:21.642693
8213 01:20:21.643027 TX Vref Scan disable
8214 01:20:21.644937 == TX Byte 0 ==
8215 01:20:21.648152 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8216 01:20:21.654667 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8217 01:20:21.655230 == TX Byte 1 ==
8218 01:20:21.658065 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8219 01:20:21.664597 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8220 01:20:21.665081 ==
8221 01:20:21.667815 Dram Type= 6, Freq= 0, CH_1, rank 0
8222 01:20:21.671197 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8223 01:20:21.671936 ==
8224 01:20:21.684279
8225 01:20:21.687301 TX Vref early break, caculate TX vref
8226 01:20:21.690860 TX Vref=16, minBit 0, minWin=22, winSum=370
8227 01:20:21.694222 TX Vref=18, minBit 3, minWin=22, winSum=382
8228 01:20:21.697287 TX Vref=20, minBit 3, minWin=22, winSum=386
8229 01:20:21.700666 TX Vref=22, minBit 3, minWin=22, winSum=394
8230 01:20:21.703633 TX Vref=24, minBit 1, minWin=24, winSum=406
8231 01:20:21.710485 TX Vref=26, minBit 1, minWin=24, winSum=412
8232 01:20:21.714260 TX Vref=28, minBit 3, minWin=24, winSum=410
8233 01:20:21.716861 TX Vref=30, minBit 3, minWin=24, winSum=409
8234 01:20:21.720228 TX Vref=32, minBit 3, minWin=23, winSum=399
8235 01:20:21.723548 TX Vref=34, minBit 1, minWin=23, winSum=392
8236 01:20:21.730246 TX Vref=36, minBit 1, minWin=22, winSum=382
8237 01:20:21.733484 [TxChooseVref] Worse bit 1, Min win 24, Win sum 412, Final Vref 26
8238 01:20:21.734088
8239 01:20:21.737111 Final TX Range 0 Vref 26
8240 01:20:21.737668
8241 01:20:21.738082 ==
8242 01:20:21.740338 Dram Type= 6, Freq= 0, CH_1, rank 0
8243 01:20:21.743449 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8244 01:20:21.746569 ==
8245 01:20:21.747031
8246 01:20:21.747394
8247 01:20:21.747733 TX Vref Scan disable
8248 01:20:21.753400 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8249 01:20:21.753970 == TX Byte 0 ==
8250 01:20:21.757055 u2DelayCellOfst[0]=18 cells (5 PI)
8251 01:20:21.759792 u2DelayCellOfst[1]=10 cells (3 PI)
8252 01:20:21.763649 u2DelayCellOfst[2]=0 cells (0 PI)
8253 01:20:21.766415 u2DelayCellOfst[3]=7 cells (2 PI)
8254 01:20:21.770209 u2DelayCellOfst[4]=10 cells (3 PI)
8255 01:20:21.773207 u2DelayCellOfst[5]=18 cells (5 PI)
8256 01:20:21.776434 u2DelayCellOfst[6]=18 cells (5 PI)
8257 01:20:21.779823 u2DelayCellOfst[7]=7 cells (2 PI)
8258 01:20:21.782788 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8259 01:20:21.786666 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8260 01:20:21.789488 == TX Byte 1 ==
8261 01:20:21.792947 u2DelayCellOfst[8]=0 cells (0 PI)
8262 01:20:21.796035 u2DelayCellOfst[9]=3 cells (1 PI)
8263 01:20:21.799606 u2DelayCellOfst[10]=7 cells (2 PI)
8264 01:20:21.802810 u2DelayCellOfst[11]=3 cells (1 PI)
8265 01:20:21.806238 u2DelayCellOfst[12]=14 cells (4 PI)
8266 01:20:21.809337 u2DelayCellOfst[13]=18 cells (5 PI)
8267 01:20:21.809896 u2DelayCellOfst[14]=18 cells (5 PI)
8268 01:20:21.812659 u2DelayCellOfst[15]=18 cells (5 PI)
8269 01:20:21.819388 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8270 01:20:21.822901 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8271 01:20:21.825836 DramC Write-DBI on
8272 01:20:21.826470 ==
8273 01:20:21.829103 Dram Type= 6, Freq= 0, CH_1, rank 0
8274 01:20:21.833017 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8275 01:20:21.833583 ==
8276 01:20:21.833961
8277 01:20:21.834427
8278 01:20:21.835631 TX Vref Scan disable
8279 01:20:21.836101 == TX Byte 0 ==
8280 01:20:21.842490 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8281 01:20:21.843071 == TX Byte 1 ==
8282 01:20:21.846138 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8283 01:20:21.849124 DramC Write-DBI off
8284 01:20:21.849684
8285 01:20:21.850113 [DATLAT]
8286 01:20:21.852503 Freq=1600, CH1 RK0
8287 01:20:21.853083
8288 01:20:21.853464 DATLAT Default: 0xf
8289 01:20:21.855668 0, 0xFFFF, sum = 0
8290 01:20:21.856145 1, 0xFFFF, sum = 0
8291 01:20:21.859222 2, 0xFFFF, sum = 0
8292 01:20:21.859792 3, 0xFFFF, sum = 0
8293 01:20:21.862118 4, 0xFFFF, sum = 0
8294 01:20:21.866123 5, 0xFFFF, sum = 0
8295 01:20:21.866691 6, 0xFFFF, sum = 0
8296 01:20:21.869077 7, 0xFFFF, sum = 0
8297 01:20:21.869646 8, 0xFFFF, sum = 0
8298 01:20:21.872063 9, 0xFFFF, sum = 0
8299 01:20:21.872541 10, 0xFFFF, sum = 0
8300 01:20:21.875385 11, 0xFFFF, sum = 0
8301 01:20:21.875900 12, 0xFFF, sum = 0
8302 01:20:21.878507 13, 0x0, sum = 1
8303 01:20:21.878979 14, 0x0, sum = 2
8304 01:20:21.882251 15, 0x0, sum = 3
8305 01:20:21.882727 16, 0x0, sum = 4
8306 01:20:21.885459 best_step = 14
8307 01:20:21.886015
8308 01:20:21.886427 ==
8309 01:20:21.888500 Dram Type= 6, Freq= 0, CH_1, rank 0
8310 01:20:21.891994 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8311 01:20:21.892557 ==
8312 01:20:21.892933 RX Vref Scan: 1
8313 01:20:21.895116
8314 01:20:21.895581 Set Vref Range= 24 -> 127
8315 01:20:21.895953
8316 01:20:21.898382 RX Vref 24 -> 127, step: 1
8317 01:20:21.898849
8318 01:20:21.901716 RX Delay 3 -> 252, step: 4
8319 01:20:21.902212
8320 01:20:21.905227 Set Vref, RX VrefLevel [Byte0]: 24
8321 01:20:21.908457 [Byte1]: 24
8322 01:20:21.909017
8323 01:20:21.912129 Set Vref, RX VrefLevel [Byte0]: 25
8324 01:20:21.915187 [Byte1]: 25
8325 01:20:21.915749
8326 01:20:21.918250 Set Vref, RX VrefLevel [Byte0]: 26
8327 01:20:21.921191 [Byte1]: 26
8328 01:20:21.925630
8329 01:20:21.926228 Set Vref, RX VrefLevel [Byte0]: 27
8330 01:20:21.929461 [Byte1]: 27
8331 01:20:21.933463
8332 01:20:21.934020 Set Vref, RX VrefLevel [Byte0]: 28
8333 01:20:21.936519 [Byte1]: 28
8334 01:20:21.941124
8335 01:20:21.941681 Set Vref, RX VrefLevel [Byte0]: 29
8336 01:20:21.944491 [Byte1]: 29
8337 01:20:21.948769
8338 01:20:21.949323 Set Vref, RX VrefLevel [Byte0]: 30
8339 01:20:21.951712 [Byte1]: 30
8340 01:20:21.957078
8341 01:20:21.957635 Set Vref, RX VrefLevel [Byte0]: 31
8342 01:20:21.960080 [Byte1]: 31
8343 01:20:21.964394
8344 01:20:21.964957 Set Vref, RX VrefLevel [Byte0]: 32
8345 01:20:21.967567 [Byte1]: 32
8346 01:20:21.972076
8347 01:20:21.972744 Set Vref, RX VrefLevel [Byte0]: 33
8348 01:20:21.974743 [Byte1]: 33
8349 01:20:21.979460
8350 01:20:21.980017 Set Vref, RX VrefLevel [Byte0]: 34
8351 01:20:21.982732 [Byte1]: 34
8352 01:20:21.986855
8353 01:20:21.987419 Set Vref, RX VrefLevel [Byte0]: 35
8354 01:20:21.990136 [Byte1]: 35
8355 01:20:21.994629
8356 01:20:21.995185 Set Vref, RX VrefLevel [Byte0]: 36
8357 01:20:21.997903 [Byte1]: 36
8358 01:20:22.002237
8359 01:20:22.002831 Set Vref, RX VrefLevel [Byte0]: 37
8360 01:20:22.005310 [Byte1]: 37
8361 01:20:22.009731
8362 01:20:22.010218 Set Vref, RX VrefLevel [Byte0]: 38
8363 01:20:22.013111 [Byte1]: 38
8364 01:20:22.017403
8365 01:20:22.017914 Set Vref, RX VrefLevel [Byte0]: 39
8366 01:20:22.020668 [Byte1]: 39
8367 01:20:22.025117
8368 01:20:22.025572 Set Vref, RX VrefLevel [Byte0]: 40
8369 01:20:22.028823 [Byte1]: 40
8370 01:20:22.032781
8371 01:20:22.033340 Set Vref, RX VrefLevel [Byte0]: 41
8372 01:20:22.036201 [Byte1]: 41
8373 01:20:22.040595
8374 01:20:22.041149 Set Vref, RX VrefLevel [Byte0]: 42
8375 01:20:22.043912 [Byte1]: 42
8376 01:20:22.048249
8377 01:20:22.048803 Set Vref, RX VrefLevel [Byte0]: 43
8378 01:20:22.051685 [Byte1]: 43
8379 01:20:22.056118
8380 01:20:22.056673 Set Vref, RX VrefLevel [Byte0]: 44
8381 01:20:22.059187 [Byte1]: 44
8382 01:20:22.063660
8383 01:20:22.064211 Set Vref, RX VrefLevel [Byte0]: 45
8384 01:20:22.066477 [Byte1]: 45
8385 01:20:22.071100
8386 01:20:22.071654 Set Vref, RX VrefLevel [Byte0]: 46
8387 01:20:22.074448 [Byte1]: 46
8388 01:20:22.078577
8389 01:20:22.079047 Set Vref, RX VrefLevel [Byte0]: 47
8390 01:20:22.081944 [Byte1]: 47
8391 01:20:22.086493
8392 01:20:22.087053 Set Vref, RX VrefLevel [Byte0]: 48
8393 01:20:22.089657 [Byte1]: 48
8394 01:20:22.094150
8395 01:20:22.094704 Set Vref, RX VrefLevel [Byte0]: 49
8396 01:20:22.097312 [Byte1]: 49
8397 01:20:22.101673
8398 01:20:22.102273 Set Vref, RX VrefLevel [Byte0]: 50
8399 01:20:22.105017 [Byte1]: 50
8400 01:20:22.109347
8401 01:20:22.109897 Set Vref, RX VrefLevel [Byte0]: 51
8402 01:20:22.112968 [Byte1]: 51
8403 01:20:22.116769
8404 01:20:22.117229 Set Vref, RX VrefLevel [Byte0]: 52
8405 01:20:22.120193 [Byte1]: 52
8406 01:20:22.124570
8407 01:20:22.125129 Set Vref, RX VrefLevel [Byte0]: 53
8408 01:20:22.128001 [Byte1]: 53
8409 01:20:22.132471
8410 01:20:22.133021 Set Vref, RX VrefLevel [Byte0]: 54
8411 01:20:22.135686 [Byte1]: 54
8412 01:20:22.140127
8413 01:20:22.140715 Set Vref, RX VrefLevel [Byte0]: 55
8414 01:20:22.143225 [Byte1]: 55
8415 01:20:22.147771
8416 01:20:22.148321 Set Vref, RX VrefLevel [Byte0]: 56
8417 01:20:22.154164 [Byte1]: 56
8418 01:20:22.154712
8419 01:20:22.157699 Set Vref, RX VrefLevel [Byte0]: 57
8420 01:20:22.160841 [Byte1]: 57
8421 01:20:22.161401
8422 01:20:22.164303 Set Vref, RX VrefLevel [Byte0]: 58
8423 01:20:22.166895 [Byte1]: 58
8424 01:20:22.170879
8425 01:20:22.171435 Set Vref, RX VrefLevel [Byte0]: 59
8426 01:20:22.174488 [Byte1]: 59
8427 01:20:22.178399
8428 01:20:22.178955 Set Vref, RX VrefLevel [Byte0]: 60
8429 01:20:22.181619 [Byte1]: 60
8430 01:20:22.185854
8431 01:20:22.186462 Set Vref, RX VrefLevel [Byte0]: 61
8432 01:20:22.189131 [Byte1]: 61
8433 01:20:22.193368
8434 01:20:22.193929 Set Vref, RX VrefLevel [Byte0]: 62
8435 01:20:22.196983 [Byte1]: 62
8436 01:20:22.201157
8437 01:20:22.201710 Set Vref, RX VrefLevel [Byte0]: 63
8438 01:20:22.204557 [Byte1]: 63
8439 01:20:22.208789
8440 01:20:22.209352 Set Vref, RX VrefLevel [Byte0]: 64
8441 01:20:22.215072 [Byte1]: 64
8442 01:20:22.215620
8443 01:20:22.218684 Set Vref, RX VrefLevel [Byte0]: 65
8444 01:20:22.221914 [Byte1]: 65
8445 01:20:22.222527
8446 01:20:22.224878 Set Vref, RX VrefLevel [Byte0]: 66
8447 01:20:22.228516 [Byte1]: 66
8448 01:20:22.231833
8449 01:20:22.232394 Set Vref, RX VrefLevel [Byte0]: 67
8450 01:20:22.235143 [Byte1]: 67
8451 01:20:22.239646
8452 01:20:22.240285 Set Vref, RX VrefLevel [Byte0]: 68
8453 01:20:22.242591 [Byte1]: 68
8454 01:20:22.246992
8455 01:20:22.247553 Set Vref, RX VrefLevel [Byte0]: 69
8456 01:20:22.250436 [Byte1]: 69
8457 01:20:22.254686
8458 01:20:22.255240 Set Vref, RX VrefLevel [Byte0]: 70
8459 01:20:22.258393 [Byte1]: 70
8460 01:20:22.262468
8461 01:20:22.263026 Set Vref, RX VrefLevel [Byte0]: 71
8462 01:20:22.265693 [Byte1]: 71
8463 01:20:22.270148
8464 01:20:22.270697 Set Vref, RX VrefLevel [Byte0]: 72
8465 01:20:22.273252 [Byte1]: 72
8466 01:20:22.277782
8467 01:20:22.278397 Set Vref, RX VrefLevel [Byte0]: 73
8468 01:20:22.281090 [Byte1]: 73
8469 01:20:22.285800
8470 01:20:22.286416 Set Vref, RX VrefLevel [Byte0]: 74
8471 01:20:22.288664 [Byte1]: 74
8472 01:20:22.293232
8473 01:20:22.293791 Set Vref, RX VrefLevel [Byte0]: 75
8474 01:20:22.297319 [Byte1]: 75
8475 01:20:22.300680
8476 01:20:22.301362 Final RX Vref Byte 0 = 60 to rank0
8477 01:20:22.303795 Final RX Vref Byte 1 = 54 to rank0
8478 01:20:22.307095 Final RX Vref Byte 0 = 60 to rank1
8479 01:20:22.310580 Final RX Vref Byte 1 = 54 to rank1==
8480 01:20:22.313735 Dram Type= 6, Freq= 0, CH_1, rank 0
8481 01:20:22.320562 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8482 01:20:22.321029 ==
8483 01:20:22.321442 DQS Delay:
8484 01:20:22.323445 DQS0 = 0, DQS1 = 0
8485 01:20:22.323913 DQM Delay:
8486 01:20:22.324289 DQM0 = 128, DQM1 = 123
8487 01:20:22.327090 DQ Delay:
8488 01:20:22.330400 DQ0 =132, DQ1 =124, DQ2 =116, DQ3 =126
8489 01:20:22.333555 DQ4 =128, DQ5 =138, DQ6 =136, DQ7 =124
8490 01:20:22.336894 DQ8 =106, DQ9 =114, DQ10 =124, DQ11 =114
8491 01:20:22.340142 DQ12 =130, DQ13 =134, DQ14 =134, DQ15 =134
8492 01:20:22.340647
8493 01:20:22.341014
8494 01:20:22.341357
8495 01:20:22.343449 [DramC_TX_OE_Calibration] TA2
8496 01:20:22.346711 Original DQ_B0 (3 6) =30, OEN = 27
8497 01:20:22.350074 Original DQ_B1 (3 6) =30, OEN = 27
8498 01:20:22.353230 24, 0x0, End_B0=24 End_B1=24
8499 01:20:22.356418 25, 0x0, End_B0=25 End_B1=25
8500 01:20:22.356887 26, 0x0, End_B0=26 End_B1=26
8501 01:20:22.360069 27, 0x0, End_B0=27 End_B1=27
8502 01:20:22.363070 28, 0x0, End_B0=28 End_B1=28
8503 01:20:22.366345 29, 0x0, End_B0=29 End_B1=29
8504 01:20:22.366860 30, 0x0, End_B0=30 End_B1=30
8505 01:20:22.369594 31, 0x4141, End_B0=30 End_B1=30
8506 01:20:22.372870 Byte0 end_step=30 best_step=27
8507 01:20:22.376223 Byte1 end_step=30 best_step=27
8508 01:20:22.379538 Byte0 TX OE(2T, 0.5T) = (3, 3)
8509 01:20:22.383016 Byte1 TX OE(2T, 0.5T) = (3, 3)
8510 01:20:22.383540
8511 01:20:22.383906
8512 01:20:22.389711 [DQSOSCAuto] RK0, (LSB)MR18= 0x2929, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
8513 01:20:22.392986 CH1 RK0: MR19=303, MR18=2929
8514 01:20:22.399689 CH1_RK0: MR19=0x303, MR18=0x2929, DQSOSC=389, MR23=63, INC=24, DEC=16
8515 01:20:22.400257
8516 01:20:22.403417 ----->DramcWriteLeveling(PI) begin...
8517 01:20:22.403940 ==
8518 01:20:22.406113 Dram Type= 6, Freq= 0, CH_1, rank 1
8519 01:20:22.409484 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8520 01:20:22.409948 ==
8521 01:20:22.412840 Write leveling (Byte 0): 22 => 22
8522 01:20:22.417045 Write leveling (Byte 1): 22 => 22
8523 01:20:22.419619 DramcWriteLeveling(PI) end<-----
8524 01:20:22.420084
8525 01:20:22.420456 ==
8526 01:20:22.423172 Dram Type= 6, Freq= 0, CH_1, rank 1
8527 01:20:22.425841 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8528 01:20:22.429524 ==
8529 01:20:22.430134 [Gating] SW mode calibration
8530 01:20:22.439157 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8531 01:20:22.442651 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8532 01:20:22.446155 0 12 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8533 01:20:22.452258 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8534 01:20:22.455810 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8535 01:20:22.458941 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8536 01:20:22.465401 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8537 01:20:22.468879 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8538 01:20:22.472517 0 12 24 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
8539 01:20:22.478634 0 12 28 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8540 01:20:22.482292 0 13 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8541 01:20:22.485466 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8542 01:20:22.491968 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8543 01:20:22.495276 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8544 01:20:22.498582 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8545 01:20:22.505438 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8546 01:20:22.508586 0 13 24 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
8547 01:20:22.512114 0 13 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8548 01:20:22.518522 0 14 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8549 01:20:22.521884 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8550 01:20:22.525063 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8551 01:20:22.531852 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8552 01:20:22.534950 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8553 01:20:22.538254 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8554 01:20:22.544918 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8555 01:20:22.548204 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8556 01:20:22.551505 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8557 01:20:22.558258 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8558 01:20:22.561610 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8559 01:20:22.564533 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8560 01:20:22.571200 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8561 01:20:22.574598 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8562 01:20:22.577678 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8563 01:20:22.584271 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8564 01:20:22.587888 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8565 01:20:22.591210 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8566 01:20:22.597729 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8567 01:20:22.601080 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8568 01:20:22.604008 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8569 01:20:22.611057 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8570 01:20:22.613942 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8571 01:20:22.617570 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8572 01:20:22.621248 Total UI for P1: 0, mck2ui 16
8573 01:20:22.624176 best dqsien dly found for B0: ( 1, 0, 24)
8574 01:20:22.631022 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8575 01:20:22.634180 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8576 01:20:22.637499 Total UI for P1: 0, mck2ui 16
8577 01:20:22.640963 best dqsien dly found for B1: ( 1, 0, 30)
8578 01:20:22.643514 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8579 01:20:22.647157 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8580 01:20:22.647713
8581 01:20:22.650803 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8582 01:20:22.653838 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8583 01:20:22.657057 [Gating] SW calibration Done
8584 01:20:22.657608 ==
8585 01:20:22.660925 Dram Type= 6, Freq= 0, CH_1, rank 1
8586 01:20:22.666924 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8587 01:20:22.667481 ==
8588 01:20:22.667855 RX Vref Scan: 0
8589 01:20:22.668207
8590 01:20:22.670220 RX Vref 0 -> 0, step: 1
8591 01:20:22.670779
8592 01:20:22.673567 RX Delay 0 -> 252, step: 8
8593 01:20:22.677283 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8594 01:20:22.680036 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8595 01:20:22.683960 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8596 01:20:22.686837 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8597 01:20:22.693533 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8598 01:20:22.697109 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8599 01:20:22.700161 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8600 01:20:22.703212 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8601 01:20:22.706568 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8602 01:20:22.713119 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8603 01:20:22.716598 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8604 01:20:22.719742 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8605 01:20:22.722813 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8606 01:20:22.726710 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8607 01:20:22.733021 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8608 01:20:22.736238 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8609 01:20:22.736804 ==
8610 01:20:22.739557 Dram Type= 6, Freq= 0, CH_1, rank 1
8611 01:20:22.742855 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8612 01:20:22.743322 ==
8613 01:20:22.746416 DQS Delay:
8614 01:20:22.746991 DQS0 = 0, DQS1 = 0
8615 01:20:22.749889 DQM Delay:
8616 01:20:22.750524 DQM0 = 131, DQM1 = 125
8617 01:20:22.750902 DQ Delay:
8618 01:20:22.752709 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8619 01:20:22.759391 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8620 01:20:22.762998 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8621 01:20:22.766188 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8622 01:20:22.766890
8623 01:20:22.767348
8624 01:20:22.767699 ==
8625 01:20:22.769107 Dram Type= 6, Freq= 0, CH_1, rank 1
8626 01:20:22.772751 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8627 01:20:22.773316 ==
8628 01:20:22.773690
8629 01:20:22.774085
8630 01:20:22.775964 TX Vref Scan disable
8631 01:20:22.779084 == TX Byte 0 ==
8632 01:20:22.782580 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8633 01:20:22.786178 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8634 01:20:22.789050 == TX Byte 1 ==
8635 01:20:22.792760 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8636 01:20:22.795626 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8637 01:20:22.796122 ==
8638 01:20:22.798834 Dram Type= 6, Freq= 0, CH_1, rank 1
8639 01:20:22.802508 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8640 01:20:22.805619 ==
8641 01:20:22.816351
8642 01:20:22.819427 TX Vref early break, caculate TX vref
8643 01:20:22.822910 TX Vref=16, minBit 0, minWin=22, winSum=373
8644 01:20:22.826411 TX Vref=18, minBit 0, minWin=23, winSum=385
8645 01:20:22.829586 TX Vref=20, minBit 0, minWin=23, winSum=394
8646 01:20:22.832884 TX Vref=22, minBit 2, minWin=24, winSum=403
8647 01:20:22.835936 TX Vref=24, minBit 0, minWin=25, winSum=412
8648 01:20:22.842456 TX Vref=26, minBit 0, minWin=25, winSum=418
8649 01:20:22.846085 TX Vref=28, minBit 0, minWin=24, winSum=415
8650 01:20:22.849327 TX Vref=30, minBit 0, minWin=24, winSum=413
8651 01:20:22.852593 TX Vref=32, minBit 0, minWin=24, winSum=404
8652 01:20:22.855956 TX Vref=34, minBit 0, minWin=23, winSum=392
8653 01:20:22.862844 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 26
8654 01:20:22.863408
8655 01:20:22.865545 Final TX Range 0 Vref 26
8656 01:20:22.866006
8657 01:20:22.866422 ==
8658 01:20:22.869163 Dram Type= 6, Freq= 0, CH_1, rank 1
8659 01:20:22.872476 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8660 01:20:22.873043 ==
8661 01:20:22.873416
8662 01:20:22.873761
8663 01:20:22.875773 TX Vref Scan disable
8664 01:20:22.882283 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8665 01:20:22.882754 == TX Byte 0 ==
8666 01:20:22.885483 u2DelayCellOfst[0]=18 cells (5 PI)
8667 01:20:22.888876 u2DelayCellOfst[1]=10 cells (3 PI)
8668 01:20:22.892119 u2DelayCellOfst[2]=0 cells (0 PI)
8669 01:20:22.895111 u2DelayCellOfst[3]=7 cells (2 PI)
8670 01:20:22.898861 u2DelayCellOfst[4]=7 cells (2 PI)
8671 01:20:22.902100 u2DelayCellOfst[5]=18 cells (5 PI)
8672 01:20:22.905309 u2DelayCellOfst[6]=18 cells (5 PI)
8673 01:20:22.908681 u2DelayCellOfst[7]=7 cells (2 PI)
8674 01:20:22.912206 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8675 01:20:22.914963 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8676 01:20:22.918941 == TX Byte 1 ==
8677 01:20:22.922000 u2DelayCellOfst[8]=0 cells (0 PI)
8678 01:20:22.925310 u2DelayCellOfst[9]=3 cells (1 PI)
8679 01:20:22.928451 u2DelayCellOfst[10]=10 cells (3 PI)
8680 01:20:22.928915 u2DelayCellOfst[11]=3 cells (1 PI)
8681 01:20:22.931382 u2DelayCellOfst[12]=14 cells (4 PI)
8682 01:20:22.934751 u2DelayCellOfst[13]=18 cells (5 PI)
8683 01:20:22.938188 u2DelayCellOfst[14]=18 cells (5 PI)
8684 01:20:22.941562 u2DelayCellOfst[15]=18 cells (5 PI)
8685 01:20:22.948135 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8686 01:20:22.951856 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8687 01:20:22.952434 DramC Write-DBI on
8688 01:20:22.952804 ==
8689 01:20:22.955301 Dram Type= 6, Freq= 0, CH_1, rank 1
8690 01:20:22.961777 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8691 01:20:22.962392 ==
8692 01:20:22.962764
8693 01:20:22.963112
8694 01:20:22.963441 TX Vref Scan disable
8695 01:20:22.965545 == TX Byte 0 ==
8696 01:20:22.968902 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8697 01:20:22.971913 == TX Byte 1 ==
8698 01:20:22.975292 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8699 01:20:22.978309 DramC Write-DBI off
8700 01:20:22.978935
8701 01:20:22.979378 [DATLAT]
8702 01:20:22.979731 Freq=1600, CH1 RK1
8703 01:20:22.980093
8704 01:20:22.981756 DATLAT Default: 0xe
8705 01:20:22.985546 0, 0xFFFF, sum = 0
8706 01:20:22.986173 1, 0xFFFF, sum = 0
8707 01:20:22.988545 2, 0xFFFF, sum = 0
8708 01:20:22.989111 3, 0xFFFF, sum = 0
8709 01:20:22.992165 4, 0xFFFF, sum = 0
8710 01:20:22.992730 5, 0xFFFF, sum = 0
8711 01:20:22.995337 6, 0xFFFF, sum = 0
8712 01:20:22.996005 7, 0xFFFF, sum = 0
8713 01:20:22.998276 8, 0xFFFF, sum = 0
8714 01:20:22.998755 9, 0xFFFF, sum = 0
8715 01:20:23.001785 10, 0xFFFF, sum = 0
8716 01:20:23.002305 11, 0xFFFF, sum = 0
8717 01:20:23.005643 12, 0xF7F, sum = 0
8718 01:20:23.006151 13, 0x0, sum = 1
8719 01:20:23.008499 14, 0x0, sum = 2
8720 01:20:23.009061 15, 0x0, sum = 3
8721 01:20:23.012229 16, 0x0, sum = 4
8722 01:20:23.012831 best_step = 14
8723 01:20:23.013206
8724 01:20:23.013549 ==
8725 01:20:23.015039 Dram Type= 6, Freq= 0, CH_1, rank 1
8726 01:20:23.022115 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8727 01:20:23.022685 ==
8728 01:20:23.023059 RX Vref Scan: 0
8729 01:20:23.023409
8730 01:20:23.024781 RX Vref 0 -> 0, step: 1
8731 01:20:23.025243
8732 01:20:23.027801 RX Delay 3 -> 252, step: 4
8733 01:20:23.031365 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8734 01:20:23.034724 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8735 01:20:23.038212 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8736 01:20:23.044576 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8737 01:20:23.047734 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8738 01:20:23.051600 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8739 01:20:23.054624 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8740 01:20:23.057853 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8741 01:20:23.064364 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
8742 01:20:23.067546 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8743 01:20:23.070884 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8744 01:20:23.074621 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8745 01:20:23.081316 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8746 01:20:23.084394 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8747 01:20:23.087503 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8748 01:20:23.090697 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8749 01:20:23.091171 ==
8750 01:20:23.093921 Dram Type= 6, Freq= 0, CH_1, rank 1
8751 01:20:23.100754 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8752 01:20:23.101322 ==
8753 01:20:23.101700 DQS Delay:
8754 01:20:23.102112 DQS0 = 0, DQS1 = 0
8755 01:20:23.104072 DQM Delay:
8756 01:20:23.104671 DQM0 = 127, DQM1 = 123
8757 01:20:23.107582 DQ Delay:
8758 01:20:23.110764 DQ0 =128, DQ1 =124, DQ2 =118, DQ3 =124
8759 01:20:23.113913 DQ4 =126, DQ5 =138, DQ6 =134, DQ7 =126
8760 01:20:23.117188 DQ8 =108, DQ9 =110, DQ10 =124, DQ11 =114
8761 01:20:23.120973 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132
8762 01:20:23.121547
8763 01:20:23.121922
8764 01:20:23.122319
8765 01:20:23.124332 [DramC_TX_OE_Calibration] TA2
8766 01:20:23.127007 Original DQ_B0 (3 6) =30, OEN = 27
8767 01:20:23.130338 Original DQ_B1 (3 6) =30, OEN = 27
8768 01:20:23.134207 24, 0x0, End_B0=24 End_B1=24
8769 01:20:23.134776 25, 0x0, End_B0=25 End_B1=25
8770 01:20:23.137265 26, 0x0, End_B0=26 End_B1=26
8771 01:20:23.140426 27, 0x0, End_B0=27 End_B1=27
8772 01:20:23.143862 28, 0x0, End_B0=28 End_B1=28
8773 01:20:23.144332 29, 0x0, End_B0=29 End_B1=29
8774 01:20:23.147185 30, 0x0, End_B0=30 End_B1=30
8775 01:20:23.150518 31, 0x4141, End_B0=30 End_B1=30
8776 01:20:23.154593 Byte0 end_step=30 best_step=27
8777 01:20:23.157718 Byte1 end_step=30 best_step=27
8778 01:20:23.160752 Byte0 TX OE(2T, 0.5T) = (3, 3)
8779 01:20:23.161269 Byte1 TX OE(2T, 0.5T) = (3, 3)
8780 01:20:23.163649
8781 01:20:23.164109
8782 01:20:23.170762 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8783 01:20:23.173470 CH1 RK1: MR19=303, MR18=1E1E
8784 01:20:23.180299 CH1_RK1: MR19=0x303, MR18=0x1E1E, DQSOSC=394, MR23=63, INC=23, DEC=15
8785 01:20:23.183599 [RxdqsGatingPostProcess] freq 1600
8786 01:20:23.187228 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8787 01:20:23.190120 Pre-setting of DQS Precalculation
8788 01:20:23.197001 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8789 01:20:23.203594 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8790 01:20:23.210078 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8791 01:20:23.210655
8792 01:20:23.211024
8793 01:20:23.213468 [Calibration Summary] 3200 Mbps
8794 01:20:23.214064 CH 0, Rank 0
8795 01:20:23.216443 SW Impedance : PASS
8796 01:20:23.219823 DUTY Scan : NO K
8797 01:20:23.220281 ZQ Calibration : PASS
8798 01:20:23.223023 Jitter Meter : NO K
8799 01:20:23.226642 CBT Training : PASS
8800 01:20:23.227223 Write leveling : PASS
8801 01:20:23.229875 RX DQS gating : PASS
8802 01:20:23.233079 RX DQ/DQS(RDDQC) : PASS
8803 01:20:23.233636 TX DQ/DQS : PASS
8804 01:20:23.236317 RX DATLAT : PASS
8805 01:20:23.239948 RX DQ/DQS(Engine): PASS
8806 01:20:23.240515 TX OE : PASS
8807 01:20:23.243153 All Pass.
8808 01:20:23.243643
8809 01:20:23.244013 CH 0, Rank 1
8810 01:20:23.246344 SW Impedance : PASS
8811 01:20:23.246806 DUTY Scan : NO K
8812 01:20:23.249736 ZQ Calibration : PASS
8813 01:20:23.253125 Jitter Meter : NO K
8814 01:20:23.253691 CBT Training : PASS
8815 01:20:23.256247 Write leveling : PASS
8816 01:20:23.259567 RX DQS gating : PASS
8817 01:20:23.260133 RX DQ/DQS(RDDQC) : PASS
8818 01:20:23.262871 TX DQ/DQS : PASS
8819 01:20:23.263443 RX DATLAT : PASS
8820 01:20:23.266251 RX DQ/DQS(Engine): PASS
8821 01:20:23.269503 TX OE : PASS
8822 01:20:23.270102 All Pass.
8823 01:20:23.270482
8824 01:20:23.272662 CH 1, Rank 0
8825 01:20:23.273125 SW Impedance : PASS
8826 01:20:23.276046 DUTY Scan : NO K
8827 01:20:23.276586 ZQ Calibration : PASS
8828 01:20:23.279185 Jitter Meter : NO K
8829 01:20:23.282520 CBT Training : PASS
8830 01:20:23.282984 Write leveling : PASS
8831 01:20:23.285777 RX DQS gating : PASS
8832 01:20:23.289026 RX DQ/DQS(RDDQC) : PASS
8833 01:20:23.289595 TX DQ/DQS : PASS
8834 01:20:23.292456 RX DATLAT : PASS
8835 01:20:23.295818 RX DQ/DQS(Engine): PASS
8836 01:20:23.296383 TX OE : PASS
8837 01:20:23.298972 All Pass.
8838 01:20:23.299432
8839 01:20:23.299796 CH 1, Rank 1
8840 01:20:23.302513 SW Impedance : PASS
8841 01:20:23.303083 DUTY Scan : NO K
8842 01:20:23.305905 ZQ Calibration : PASS
8843 01:20:23.309248 Jitter Meter : NO K
8844 01:20:23.309816 CBT Training : PASS
8845 01:20:23.312266 Write leveling : PASS
8846 01:20:23.315362 RX DQS gating : PASS
8847 01:20:23.315826 RX DQ/DQS(RDDQC) : PASS
8848 01:20:23.318947 TX DQ/DQS : PASS
8849 01:20:23.321922 RX DATLAT : PASS
8850 01:20:23.322416 RX DQ/DQS(Engine): PASS
8851 01:20:23.325509 TX OE : PASS
8852 01:20:23.326139 All Pass.
8853 01:20:23.326522
8854 01:20:23.329143 DramC Write-DBI on
8855 01:20:23.332164 PER_BANK_REFRESH: Hybrid Mode
8856 01:20:23.332733 TX_TRACKING: ON
8857 01:20:23.341892 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8858 01:20:23.348533 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8859 01:20:23.355619 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8860 01:20:23.358556 [FAST_K] Save calibration result to emmc
8861 01:20:23.362007 sync common calibartion params.
8862 01:20:23.365072 sync cbt_mode0:0, 1:0
8863 01:20:23.368587 dram_init: ddr_geometry: 0
8864 01:20:23.369158 dram_init: ddr_geometry: 0
8865 01:20:23.371827 dram_init: ddr_geometry: 0
8866 01:20:23.374823 0:dram_rank_size:80000000
8867 01:20:23.375297 1:dram_rank_size:80000000
8868 01:20:23.381372 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8869 01:20:23.384844 DFS_SHUFFLE_HW_MODE: ON
8870 01:20:23.388392 dramc_set_vcore_voltage set vcore to 725000
8871 01:20:23.391562 Read voltage for 1600, 0
8872 01:20:23.392026 Vio18 = 0
8873 01:20:23.392393 Vcore = 725000
8874 01:20:23.394654 Vdram = 0
8875 01:20:23.395115 Vddq = 0
8876 01:20:23.395483 Vmddr = 0
8877 01:20:23.398162 switch to 3200 Mbps bootup
8878 01:20:23.398630 [DramcRunTimeConfig]
8879 01:20:23.401606 PHYPLL
8880 01:20:23.402217 DPM_CONTROL_AFTERK: ON
8881 01:20:23.404686 PER_BANK_REFRESH: ON
8882 01:20:23.407966 REFRESH_OVERHEAD_REDUCTION: ON
8883 01:20:23.408534 CMD_PICG_NEW_MODE: OFF
8884 01:20:23.411239 XRTWTW_NEW_MODE: ON
8885 01:20:23.411702 XRTRTR_NEW_MODE: ON
8886 01:20:23.414557 TX_TRACKING: ON
8887 01:20:23.415139 RDSEL_TRACKING: OFF
8888 01:20:23.417661 DQS Precalculation for DVFS: ON
8889 01:20:23.421015 RX_TRACKING: OFF
8890 01:20:23.421473 HW_GATING DBG: ON
8891 01:20:23.424258 ZQCS_ENABLE_LP4: ON
8892 01:20:23.424716 RX_PICG_NEW_MODE: ON
8893 01:20:23.427643 TX_PICG_NEW_MODE: ON
8894 01:20:23.431311 ENABLE_RX_DCM_DPHY: ON
8895 01:20:23.434759 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8896 01:20:23.435319 DUMMY_READ_FOR_TRACKING: OFF
8897 01:20:23.437571 !!! SPM_CONTROL_AFTERK: OFF
8898 01:20:23.441068 !!! SPM could not control APHY
8899 01:20:23.443879 IMPEDANCE_TRACKING: ON
8900 01:20:23.444337 TEMP_SENSOR: ON
8901 01:20:23.447241 HW_SAVE_FOR_SR: OFF
8902 01:20:23.447697 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8903 01:20:23.454058 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8904 01:20:23.454741 Read ODT Tracking: ON
8905 01:20:23.457383 Refresh Rate DeBounce: ON
8906 01:20:23.460525 DFS_NO_QUEUE_FLUSH: ON
8907 01:20:23.461043 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8908 01:20:23.463680 ENABLE_DFS_RUNTIME_MRW: OFF
8909 01:20:23.466879 DDR_RESERVE_NEW_MODE: ON
8910 01:20:23.470133 MR_CBT_SWITCH_FREQ: ON
8911 01:20:23.470755 =========================
8912 01:20:23.490164 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8913 01:20:23.493318 dram_init: ddr_geometry: 0
8914 01:20:23.511401 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8915 01:20:23.514434 dram_init: dram init end (result: 0)
8916 01:20:23.521543 DRAM-K: Full calibration passed in 23385 msecs
8917 01:20:23.524370 MRC: failed to locate region type 0.
8918 01:20:23.524832 DRAM rank0 size:0x80000000,
8919 01:20:23.528011 DRAM rank1 size=0x80000000
8920 01:20:23.538072 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8921 01:20:23.544479 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8922 01:20:23.551238 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8923 01:20:23.557796 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8924 01:20:23.561510 DRAM rank0 size:0x80000000,
8925 01:20:23.564357 DRAM rank1 size=0x80000000
8926 01:20:23.564918 CBMEM:
8927 01:20:23.567636 IMD: root @ 0xfffff000 254 entries.
8928 01:20:23.570980 IMD: root @ 0xffffec00 62 entries.
8929 01:20:23.574541 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8930 01:20:23.577691 WARNING: RO_VPD is uninitialized or empty.
8931 01:20:23.584116 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8932 01:20:23.590962 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8933 01:20:23.603832 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8934 01:20:23.615709 BS: romstage times (exec / console): total (unknown) / 22928 ms
8935 01:20:23.616314
8936 01:20:23.616683
8937 01:20:23.625089 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8938 01:20:23.628073 ARM64: Exception handlers installed.
8939 01:20:23.631752 ARM64: Testing exception
8940 01:20:23.634943 ARM64: Done test exception
8941 01:20:23.635510 Enumerating buses...
8942 01:20:23.638374 Show all devs... Before device enumeration.
8943 01:20:23.641771 Root Device: enabled 1
8944 01:20:23.644991 CPU_CLUSTER: 0: enabled 1
8945 01:20:23.645555 CPU: 00: enabled 1
8946 01:20:23.648409 Compare with tree...
8947 01:20:23.648987 Root Device: enabled 1
8948 01:20:23.651923 CPU_CLUSTER: 0: enabled 1
8949 01:20:23.654742 CPU: 00: enabled 1
8950 01:20:23.655203 Root Device scanning...
8951 01:20:23.658533 scan_static_bus for Root Device
8952 01:20:23.661464 CPU_CLUSTER: 0 enabled
8953 01:20:23.664876 scan_static_bus for Root Device done
8954 01:20:23.668290 scan_bus: bus Root Device finished in 8 msecs
8955 01:20:23.668864 done
8956 01:20:23.674742 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8957 01:20:23.677877 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8958 01:20:23.684679 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8959 01:20:23.687868 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8960 01:20:23.691388 Allocating resources...
8961 01:20:23.694719 Reading resources...
8962 01:20:23.697933 Root Device read_resources bus 0 link: 0
8963 01:20:23.698568 DRAM rank0 size:0x80000000,
8964 01:20:23.701286 DRAM rank1 size=0x80000000
8965 01:20:23.704930 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8966 01:20:23.707812 CPU: 00 missing read_resources
8967 01:20:23.714253 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8968 01:20:23.717485 Root Device read_resources bus 0 link: 0 done
8969 01:20:23.717949 Done reading resources.
8970 01:20:23.724602 Show resources in subtree (Root Device)...After reading.
8971 01:20:23.727326 Root Device child on link 0 CPU_CLUSTER: 0
8972 01:20:23.730730 CPU_CLUSTER: 0 child on link 0 CPU: 00
8973 01:20:23.741080 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8974 01:20:23.741674 CPU: 00
8975 01:20:23.744161 Root Device assign_resources, bus 0 link: 0
8976 01:20:23.747387 CPU_CLUSTER: 0 missing set_resources
8977 01:20:23.754197 Root Device assign_resources, bus 0 link: 0 done
8978 01:20:23.754776 Done setting resources.
8979 01:20:23.761004 Show resources in subtree (Root Device)...After assigning values.
8980 01:20:23.763927 Root Device child on link 0 CPU_CLUSTER: 0
8981 01:20:23.767261 CPU_CLUSTER: 0 child on link 0 CPU: 00
8982 01:20:23.777248 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8983 01:20:23.777835 CPU: 00
8984 01:20:23.780461 Done allocating resources.
8985 01:20:23.787303 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8986 01:20:23.787898 Enabling resources...
8987 01:20:23.788393 done.
8988 01:20:23.793463 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8989 01:20:23.793949 Initializing devices...
8990 01:20:23.797518 Root Device init
8991 01:20:23.798138 init hardware done!
8992 01:20:23.800227 0x00000018: ctrlr->caps
8993 01:20:23.803509 52.000 MHz: ctrlr->f_max
8994 01:20:23.804000 0.400 MHz: ctrlr->f_min
8995 01:20:23.806844 0x40ff8080: ctrlr->voltages
8996 01:20:23.810551 sclk: 390625
8997 01:20:23.811128 Bus Width = 1
8998 01:20:23.811616 sclk: 390625
8999 01:20:23.813636 Bus Width = 1
9000 01:20:23.814257 Early init status = 3
9001 01:20:23.819843 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9002 01:20:23.823541 in-header: 03 fc 00 00 01 00 00 00
9003 01:20:23.826610 in-data: 00
9004 01:20:23.829868 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9005 01:20:23.834390 in-header: 03 fd 00 00 00 00 00 00
9006 01:20:23.837562 in-data:
9007 01:20:23.841050 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9008 01:20:23.844725 in-header: 03 fc 00 00 01 00 00 00
9009 01:20:23.847971 in-data: 00
9010 01:20:23.851466 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9011 01:20:23.856899 in-header: 03 fd 00 00 00 00 00 00
9012 01:20:23.859951 in-data:
9013 01:20:23.863466 [SSUSB] Setting up USB HOST controller...
9014 01:20:23.866354 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9015 01:20:23.869969 [SSUSB] phy power-on done.
9016 01:20:23.873288 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9017 01:20:23.879822 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9018 01:20:23.883324 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9019 01:20:23.889602 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9020 01:20:23.896704 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9021 01:20:23.903142 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9022 01:20:23.909606 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9023 01:20:23.916155 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9024 01:20:23.919340 SPM: binary array size = 0x9dc
9025 01:20:23.922797 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9026 01:20:23.929509 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9027 01:20:23.936092 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9028 01:20:23.942892 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9029 01:20:23.945913 configure_display: Starting display init
9030 01:20:23.979709 anx7625_power_on_init: Init interface.
9031 01:20:23.983235 anx7625_disable_pd_protocol: Disabled PD feature.
9032 01:20:23.986601 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9033 01:20:24.014635 anx7625_start_dp_work: Secure OCM version=00
9034 01:20:24.017522 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9035 01:20:24.032484 sp_tx_get_edid_block: EDID Block = 1
9036 01:20:24.135073 Extracted contents:
9037 01:20:24.138629 header: 00 ff ff ff ff ff ff 00
9038 01:20:24.142446 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9039 01:20:24.144853 version: 01 04
9040 01:20:24.148928 basic params: 95 1f 11 78 0a
9041 01:20:24.151895 chroma info: 76 90 94 55 54 90 27 21 50 54
9042 01:20:24.155199 established: 00 00 00
9043 01:20:24.161442 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9044 01:20:24.168052 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9045 01:20:24.171339 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9046 01:20:24.177898 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9047 01:20:24.184189 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9048 01:20:24.187659 extensions: 00
9049 01:20:24.188160 checksum: fb
9050 01:20:24.188528
9051 01:20:24.193984 Manufacturer: IVO Model 57d Serial Number 0
9052 01:20:24.194494 Made week 0 of 2020
9053 01:20:24.197524 EDID version: 1.4
9054 01:20:24.198139 Digital display
9055 01:20:24.200748 6 bits per primary color channel
9056 01:20:24.201213 DisplayPort interface
9057 01:20:24.204046 Maximum image size: 31 cm x 17 cm
9058 01:20:24.207406 Gamma: 220%
9059 01:20:24.207875 Check DPMS levels
9060 01:20:24.214526 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9061 01:20:24.217943 First detailed timing is preferred timing
9062 01:20:24.218558 Established timings supported:
9063 01:20:24.220875 Standard timings supported:
9064 01:20:24.224436 Detailed timings
9065 01:20:24.227305 Hex of detail: 383680a07038204018303c0035ae10000019
9066 01:20:24.233988 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9067 01:20:24.237365 0780 0798 07c8 0820 hborder 0
9068 01:20:24.240649 0438 043b 0447 0458 vborder 0
9069 01:20:24.243721 -hsync -vsync
9070 01:20:24.244183 Did detailed timing
9071 01:20:24.250804 Hex of detail: 000000000000000000000000000000000000
9072 01:20:24.254089 Manufacturer-specified data, tag 0
9073 01:20:24.257721 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9074 01:20:24.260421 ASCII string: InfoVision
9075 01:20:24.263787 Hex of detail: 000000fe00523134304e574635205248200a
9076 01:20:24.266926 ASCII string: R140NWF5 RH
9077 01:20:24.267392 Checksum
9078 01:20:24.270635 Checksum: 0xfb (valid)
9079 01:20:24.273866 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9080 01:20:24.277224 DSI data_rate: 832800000 bps
9081 01:20:24.283814 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9082 01:20:24.286943 anx7625_parse_edid: pixelclock(138800).
9083 01:20:24.290211 hactive(1920), hsync(48), hfp(24), hbp(88)
9084 01:20:24.293462 vactive(1080), vsync(12), vfp(3), vbp(17)
9085 01:20:24.296944 anx7625_dsi_config: config dsi.
9086 01:20:24.303201 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9087 01:20:24.317115 anx7625_dsi_config: success to config DSI
9088 01:20:24.320510 anx7625_dp_start: MIPI phy setup OK.
9089 01:20:24.323580 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9090 01:20:24.326791 mtk_ddp_mode_set invalid vrefresh 60
9091 01:20:24.330063 main_disp_path_setup
9092 01:20:24.330655 ovl_layer_smi_id_en
9093 01:20:24.333649 ovl_layer_smi_id_en
9094 01:20:24.334271 ccorr_config
9095 01:20:24.334653 aal_config
9096 01:20:24.337467 gamma_config
9097 01:20:24.338083 postmask_config
9098 01:20:24.340186 dither_config
9099 01:20:24.343280 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9100 01:20:24.350074 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9101 01:20:24.353597 Root Device init finished in 553 msecs
9102 01:20:24.356605 CPU_CLUSTER: 0 init
9103 01:20:24.363753 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9104 01:20:24.369866 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9105 01:20:24.370486 APU_MBOX 0x190000b0 = 0x10001
9106 01:20:24.373295 APU_MBOX 0x190001b0 = 0x10001
9107 01:20:24.376425 APU_MBOX 0x190005b0 = 0x10001
9108 01:20:24.379447 APU_MBOX 0x190006b0 = 0x10001
9109 01:20:24.386215 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9110 01:20:24.395966 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9111 01:20:24.408465 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9112 01:20:24.414995 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9113 01:20:24.426531 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9114 01:20:24.435657 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9115 01:20:24.439132 CPU_CLUSTER: 0 init finished in 81 msecs
9116 01:20:24.442281 Devices initialized
9117 01:20:24.445753 Show all devs... After init.
9118 01:20:24.446394 Root Device: enabled 1
9119 01:20:24.449006 CPU_CLUSTER: 0: enabled 1
9120 01:20:24.452279 CPU: 00: enabled 1
9121 01:20:24.455677 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9122 01:20:24.459139 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9123 01:20:24.462172 ELOG: NV offset 0x57f000 size 0x1000
9124 01:20:24.468754 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9125 01:20:24.475434 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9126 01:20:24.478916 ELOG: Event(17) added with size 13 at 2024-04-23 01:20:23 UTC
9127 01:20:24.485463 out: cmd=0x121: 03 db 21 01 00 00 00 00
9128 01:20:24.488670 in-header: 03 14 00 00 2c 00 00 00
9129 01:20:24.501873 in-data: 4f 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9130 01:20:24.505198 ELOG: Event(A1) added with size 10 at 2024-04-23 01:20:23 UTC
9131 01:20:24.511718 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9132 01:20:24.518780 ELOG: Event(A0) added with size 9 at 2024-04-23 01:20:23 UTC
9133 01:20:24.521781 elog_add_boot_reason: Logged dev mode boot
9134 01:20:24.528274 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9135 01:20:24.528846 Finalize devices...
9136 01:20:24.531269 Devices finalized
9137 01:20:24.534787 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9138 01:20:24.537967 Writing coreboot table at 0xffe64000
9139 01:20:24.544394 0. 000000000010a000-0000000000113fff: RAMSTAGE
9140 01:20:24.547764 1. 0000000040000000-00000000400fffff: RAM
9141 01:20:24.551362 2. 0000000040100000-000000004032afff: RAMSTAGE
9142 01:20:24.554868 3. 000000004032b000-00000000545fffff: RAM
9143 01:20:24.557845 4. 0000000054600000-000000005465ffff: BL31
9144 01:20:24.564339 5. 0000000054660000-00000000ffe63fff: RAM
9145 01:20:24.568084 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9146 01:20:24.571382 7. 0000000100000000-000000013fffffff: RAM
9147 01:20:24.574411 Passing 5 GPIOs to payload:
9148 01:20:24.577523 NAME | PORT | POLARITY | VALUE
9149 01:20:24.584034 EC in RW | 0x000000aa | low | undefined
9150 01:20:24.587732 EC interrupt | 0x00000005 | low | undefined
9151 01:20:24.593903 TPM interrupt | 0x000000ab | high | undefined
9152 01:20:24.597500 SD card detect | 0x00000011 | high | undefined
9153 01:20:24.600616 speaker enable | 0x00000093 | high | undefined
9154 01:20:24.608008 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9155 01:20:24.610679 in-header: 03 f8 00 00 02 00 00 00
9156 01:20:24.611150 in-data: 03 00
9157 01:20:24.614132 ADC[4]: Raw value=669327 ID=5
9158 01:20:24.617181 ADC[3]: Raw value=212549 ID=1
9159 01:20:24.617649 RAM Code: 0x51
9160 01:20:24.620448 ADC[6]: Raw value=74410 ID=0
9161 01:20:24.623685 ADC[5]: Raw value=211444 ID=1
9162 01:20:24.624154 SKU Code: 0x1
9163 01:20:24.630347 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum dd9a
9164 01:20:24.633566 coreboot table: 964 bytes.
9165 01:20:24.637199 IMD ROOT 0. 0xfffff000 0x00001000
9166 01:20:24.640571 IMD SMALL 1. 0xffffe000 0x00001000
9167 01:20:24.644034 RO MCACHE 2. 0xffffc000 0x00001104
9168 01:20:24.646815 CONSOLE 3. 0xfff7c000 0x00080000
9169 01:20:24.650511 FMAP 4. 0xfff7b000 0x00000452
9170 01:20:24.651066 TIME STAMP 5. 0xfff7a000 0x00000910
9171 01:20:24.653535 VBOOT WORK 6. 0xfff66000 0x00014000
9172 01:20:24.657236 RAMOOPS 7. 0xffe66000 0x00100000
9173 01:20:24.660563 COREBOOT 8. 0xffe64000 0x00002000
9174 01:20:24.663564 IMD small region:
9175 01:20:24.667070 IMD ROOT 0. 0xffffec00 0x00000400
9176 01:20:24.670344 VPD 1. 0xffffeb80 0x0000006c
9177 01:20:24.673639 MMC STATUS 2. 0xffffeb60 0x00000004
9178 01:20:24.680358 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9179 01:20:24.680827 Probing TPM: done!
9180 01:20:24.686785 Connected to device vid:did:rid of 1ae0:0028:00
9181 01:20:24.693437 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9182 01:20:24.696978 Initialized TPM device CR50 revision 0
9183 01:20:24.700537 Checking cr50 for pending updates
9184 01:20:24.706642 Reading cr50 TPM mode
9185 01:20:24.714905 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9186 01:20:24.721305 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9187 01:20:24.761460 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9188 01:20:24.764710 Checking segment from ROM address 0x40100000
9189 01:20:24.767900 Checking segment from ROM address 0x4010001c
9190 01:20:24.774475 Loading segment from ROM address 0x40100000
9191 01:20:24.775024 code (compression=0)
9192 01:20:24.784747 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9193 01:20:24.791358 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9194 01:20:24.791931 it's not compressed!
9195 01:20:24.798007 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9196 01:20:24.801501 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9197 01:20:24.821991 Loading segment from ROM address 0x4010001c
9198 01:20:24.822619 Entry Point 0x80000000
9199 01:20:24.824987 Loaded segments
9200 01:20:24.828718 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9201 01:20:24.835071 Jumping to boot code at 0x80000000(0xffe64000)
9202 01:20:24.842095 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9203 01:20:24.848323 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9204 01:20:24.856411 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9205 01:20:24.859598 Checking segment from ROM address 0x40100000
9206 01:20:24.862913 Checking segment from ROM address 0x4010001c
9207 01:20:24.869857 Loading segment from ROM address 0x40100000
9208 01:20:24.870482 code (compression=1)
9209 01:20:24.876359 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9210 01:20:24.885945 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9211 01:20:24.886556 using LZMA
9212 01:20:24.894393 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9213 01:20:24.901684 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9214 01:20:24.904607 Loading segment from ROM address 0x4010001c
9215 01:20:24.905181 Entry Point 0x54601000
9216 01:20:24.907913 Loaded segments
9217 01:20:24.911511 NOTICE: MT8192 bl31_setup
9218 01:20:24.918513 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9219 01:20:24.921449 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9220 01:20:24.924503 WARNING: region 0:
9221 01:20:24.928007 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9222 01:20:24.928484 WARNING: region 1:
9223 01:20:24.934590 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9224 01:20:24.938199 WARNING: region 2:
9225 01:20:24.941592 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9226 01:20:24.944510 WARNING: region 3:
9227 01:20:24.947874 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9228 01:20:24.951630 WARNING: region 4:
9229 01:20:24.957979 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9230 01:20:24.958598 WARNING: region 5:
9231 01:20:24.961451 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9232 01:20:24.965089 WARNING: region 6:
9233 01:20:24.967986 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9234 01:20:24.971242 WARNING: region 7:
9235 01:20:24.974662 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9236 01:20:24.981146 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9237 01:20:24.984837 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9238 01:20:24.987887 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9239 01:20:24.994445 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9240 01:20:24.998092 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9241 01:20:25.001259 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9242 01:20:25.008198 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9243 01:20:25.011789 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9244 01:20:25.018198 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9245 01:20:25.021299 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9246 01:20:25.024737 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9247 01:20:25.031331 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9248 01:20:25.034809 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9249 01:20:25.038139 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9250 01:20:25.044676 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9251 01:20:25.048069 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9252 01:20:25.054727 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9253 01:20:25.057883 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9254 01:20:25.061301 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9255 01:20:25.068267 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9256 01:20:25.071129 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9257 01:20:25.074463 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9258 01:20:25.081083 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9259 01:20:25.084276 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9260 01:20:25.090877 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9261 01:20:25.093967 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9262 01:20:25.101390 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9263 01:20:25.104430 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9264 01:20:25.107558 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9265 01:20:25.114263 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9266 01:20:25.117311 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9267 01:20:25.121120 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9268 01:20:25.127451 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9269 01:20:25.130768 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9270 01:20:25.134243 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9271 01:20:25.137681 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9272 01:20:25.144170 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9273 01:20:25.147844 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9274 01:20:25.150956 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9275 01:20:25.154398 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9276 01:20:25.161344 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9277 01:20:25.164771 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9278 01:20:25.167848 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9279 01:20:25.171361 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9280 01:20:25.177947 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9281 01:20:25.180855 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9282 01:20:25.184170 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9283 01:20:25.187574 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9284 01:20:25.194219 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9285 01:20:25.198280 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9286 01:20:25.204432 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9287 01:20:25.207882 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9288 01:20:25.214163 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9289 01:20:25.217610 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9290 01:20:25.220824 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9291 01:20:25.227389 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9292 01:20:25.230774 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9293 01:20:25.237349 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9294 01:20:25.240852 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9295 01:20:25.247242 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9296 01:20:25.250947 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9297 01:20:25.257539 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9298 01:20:25.261018 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9299 01:20:25.264321 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9300 01:20:25.270898 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9301 01:20:25.274178 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9302 01:20:25.280726 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9303 01:20:25.284358 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9304 01:20:25.290635 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9305 01:20:25.294109 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9306 01:20:25.297733 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9307 01:20:25.304082 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9308 01:20:25.307725 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9309 01:20:25.314329 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9310 01:20:25.317333 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9311 01:20:25.323951 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9312 01:20:25.327282 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9313 01:20:25.330907 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9314 01:20:25.337146 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9315 01:20:25.340826 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9316 01:20:25.347491 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9317 01:20:25.350658 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9318 01:20:25.357436 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9319 01:20:25.360598 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9320 01:20:25.364166 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9321 01:20:25.370725 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9322 01:20:25.373859 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9323 01:20:25.380666 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9324 01:20:25.383903 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9325 01:20:25.390585 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9326 01:20:25.393739 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9327 01:20:25.400699 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9328 01:20:25.403638 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9329 01:20:25.407285 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9330 01:20:25.413809 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9331 01:20:25.417197 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9332 01:20:25.423658 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9333 01:20:25.427153 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9334 01:20:25.431026 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9335 01:20:25.434246 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9336 01:20:25.440609 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9337 01:20:25.443760 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9338 01:20:25.447203 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9339 01:20:25.453694 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9340 01:20:25.457185 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9341 01:20:25.464053 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9342 01:20:25.466927 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9343 01:20:25.470284 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9344 01:20:25.477067 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9345 01:20:25.480437 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9346 01:20:25.487089 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9347 01:20:25.490227 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9348 01:20:25.493554 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9349 01:20:25.500567 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9350 01:20:25.503814 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9351 01:20:25.510541 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9352 01:20:25.513774 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9353 01:20:25.516898 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9354 01:20:25.520384 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9355 01:20:25.527144 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9356 01:20:25.530165 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9357 01:20:25.533187 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9358 01:20:25.536984 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9359 01:20:25.543109 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9360 01:20:25.546578 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9361 01:20:25.549884 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9362 01:20:25.556672 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9363 01:20:25.559837 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9364 01:20:25.566795 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9365 01:20:25.570057 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9366 01:20:25.573308 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9367 01:20:25.580160 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9368 01:20:25.583127 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9369 01:20:25.590050 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9370 01:20:25.593295 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9371 01:20:25.596453 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9372 01:20:25.603215 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9373 01:20:25.606311 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9374 01:20:25.610126 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9375 01:20:25.616853 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9376 01:20:25.620640 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9377 01:20:25.626838 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9378 01:20:25.630138 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9379 01:20:25.633177 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9380 01:20:25.640297 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9381 01:20:25.643424 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9382 01:20:25.650186 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9383 01:20:25.653350 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9384 01:20:25.656908 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9385 01:20:25.663268 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9386 01:20:25.666492 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9387 01:20:25.670100 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9388 01:20:25.676793 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9389 01:20:25.680002 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9390 01:20:25.686807 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9391 01:20:25.690085 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9392 01:20:25.693445 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9393 01:20:25.700062 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9394 01:20:25.703258 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9395 01:20:25.709915 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9396 01:20:25.713011 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9397 01:20:25.716536 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9398 01:20:25.723543 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9399 01:20:25.726357 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9400 01:20:25.732948 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9401 01:20:25.736321 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9402 01:20:25.739667 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9403 01:20:25.746611 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9404 01:20:25.749695 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9405 01:20:25.753004 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9406 01:20:25.759773 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9407 01:20:25.763669 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9408 01:20:25.769900 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9409 01:20:25.773021 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9410 01:20:25.776332 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9411 01:20:25.783075 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9412 01:20:25.786513 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9413 01:20:25.793286 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9414 01:20:25.796082 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9415 01:20:25.799914 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9416 01:20:25.805834 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9417 01:20:25.809532 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9418 01:20:25.816036 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9419 01:20:25.818960 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9420 01:20:25.822728 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9421 01:20:25.828986 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9422 01:20:25.832719 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9423 01:20:25.839018 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9424 01:20:25.842308 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9425 01:20:25.848697 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9426 01:20:25.852386 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9427 01:20:25.855682 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9428 01:20:25.862175 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9429 01:20:25.865542 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9430 01:20:25.871836 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9431 01:20:25.875649 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9432 01:20:25.878720 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9433 01:20:25.885350 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9434 01:20:25.888526 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9435 01:20:25.895235 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9436 01:20:25.898651 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9437 01:20:25.905467 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9438 01:20:25.908874 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9439 01:20:25.912142 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9440 01:20:25.918775 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9441 01:20:25.921895 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9442 01:20:25.928877 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9443 01:20:25.931805 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9444 01:20:25.934999 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9445 01:20:25.941416 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9446 01:20:25.945076 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9447 01:20:25.951786 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9448 01:20:25.954855 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9449 01:20:25.961626 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9450 01:20:25.965592 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9451 01:20:25.969095 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9452 01:20:25.974788 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9453 01:20:25.978212 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9454 01:20:25.984537 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9455 01:20:25.988083 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9456 01:20:25.994783 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9457 01:20:25.997721 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9458 01:20:26.001296 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9459 01:20:26.007921 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9460 01:20:26.011004 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9461 01:20:26.017871 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9462 01:20:26.021150 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9463 01:20:26.027640 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9464 01:20:26.030909 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9465 01:20:26.034641 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9466 01:20:26.037511 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9467 01:20:26.044853 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9468 01:20:26.047187 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9469 01:20:26.050927 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9470 01:20:26.054159 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9471 01:20:26.060774 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9472 01:20:26.064022 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9473 01:20:26.070420 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9474 01:20:26.073838 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9475 01:20:26.077389 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9476 01:20:26.083799 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9477 01:20:26.087249 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9478 01:20:26.090993 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9479 01:20:26.096951 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9480 01:20:26.100553 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9481 01:20:26.107251 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9482 01:20:26.110120 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9483 01:20:26.113365 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9484 01:20:26.120494 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9485 01:20:26.123579 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9486 01:20:26.126857 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9487 01:20:26.133778 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9488 01:20:26.136783 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9489 01:20:26.140335 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9490 01:20:26.147433 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9491 01:20:26.150140 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9492 01:20:26.156560 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9493 01:20:26.160056 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9494 01:20:26.163499 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9495 01:20:26.169968 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9496 01:20:26.173646 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9497 01:20:26.176777 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9498 01:20:26.183184 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9499 01:20:26.186240 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9500 01:20:26.193070 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9501 01:20:26.196207 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9502 01:20:26.199775 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9503 01:20:26.206149 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9504 01:20:26.209528 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9505 01:20:26.212856 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9506 01:20:26.216509 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9507 01:20:26.222903 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9508 01:20:26.225969 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9509 01:20:26.229067 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9510 01:20:26.232908 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9511 01:20:26.239238 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9512 01:20:26.242877 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9513 01:20:26.245899 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9514 01:20:26.249158 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9515 01:20:26.256039 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9516 01:20:26.259116 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9517 01:20:26.262544 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9518 01:20:26.269635 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9519 01:20:26.273011 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9520 01:20:26.279139 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9521 01:20:26.282281 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9522 01:20:26.286021 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9523 01:20:26.291895 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9524 01:20:26.295665 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9525 01:20:26.302195 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9526 01:20:26.305914 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9527 01:20:26.308971 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9528 01:20:26.315788 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9529 01:20:26.318729 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9530 01:20:26.325728 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9531 01:20:26.328595 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9532 01:20:26.335190 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9533 01:20:26.338713 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9534 01:20:26.341773 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9535 01:20:26.348650 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9536 01:20:26.351877 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9537 01:20:26.358786 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9538 01:20:26.361951 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9539 01:20:26.365782 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9540 01:20:26.372044 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9541 01:20:26.375002 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9542 01:20:26.382066 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9543 01:20:26.385308 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9544 01:20:26.388901 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9545 01:20:26.394941 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9546 01:20:26.398541 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9547 01:20:26.405222 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9548 01:20:26.408335 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9549 01:20:26.411569 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9550 01:20:26.418148 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9551 01:20:26.421870 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9552 01:20:26.427979 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9553 01:20:26.431212 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9554 01:20:26.438176 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9555 01:20:26.441640 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9556 01:20:26.444954 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9557 01:20:26.451545 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9558 01:20:26.454688 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9559 01:20:26.461360 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9560 01:20:26.464452 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9561 01:20:26.468112 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9562 01:20:26.474826 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9563 01:20:26.477746 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9564 01:20:26.484190 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9565 01:20:26.487698 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9566 01:20:26.491370 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9567 01:20:26.497445 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9568 01:20:26.501099 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9569 01:20:26.507574 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9570 01:20:26.510593 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9571 01:20:26.517651 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9572 01:20:26.520561 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9573 01:20:26.524032 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9574 01:20:26.530412 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9575 01:20:26.533853 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9576 01:20:26.540521 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9577 01:20:26.543818 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9578 01:20:26.550404 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9579 01:20:26.553919 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9580 01:20:26.557201 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9581 01:20:26.563669 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9582 01:20:26.567048 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9583 01:20:26.570723 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9584 01:20:26.577027 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9585 01:20:26.580143 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9586 01:20:26.586801 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9587 01:20:26.590393 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9588 01:20:26.596902 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9589 01:20:26.599984 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9590 01:20:26.603853 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9591 01:20:26.609923 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9592 01:20:26.613503 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9593 01:20:26.619887 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9594 01:20:26.623574 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9595 01:20:26.629702 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9596 01:20:26.633394 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9597 01:20:26.636653 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9598 01:20:26.643305 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9599 01:20:26.646406 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9600 01:20:26.652938 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9601 01:20:26.656468 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9602 01:20:26.663121 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9603 01:20:26.665973 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9604 01:20:26.672831 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9605 01:20:26.675997 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9606 01:20:26.679173 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9607 01:20:26.686178 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9608 01:20:26.689395 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9609 01:20:26.696170 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9610 01:20:26.698990 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9611 01:20:26.705983 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9612 01:20:26.709394 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9613 01:20:26.712506 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9614 01:20:26.719443 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9615 01:20:26.722270 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9616 01:20:26.728692 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9617 01:20:26.732477 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9618 01:20:26.738604 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9619 01:20:26.741949 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9620 01:20:26.748983 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9621 01:20:26.751901 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9622 01:20:26.755460 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9623 01:20:26.762015 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9624 01:20:26.765287 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9625 01:20:26.772077 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9626 01:20:26.774988 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9627 01:20:26.781664 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9628 01:20:26.785290 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9629 01:20:26.791501 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9630 01:20:26.794947 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9631 01:20:26.798224 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9632 01:20:26.804806 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9633 01:20:26.808195 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9634 01:20:26.814752 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9635 01:20:26.818061 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9636 01:20:26.824622 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9637 01:20:26.828013 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9638 01:20:26.830981 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9639 01:20:26.837804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9640 01:20:26.841386 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9641 01:20:26.847923 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9642 01:20:26.850934 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9643 01:20:26.857788 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9644 01:20:26.861145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9645 01:20:26.867499 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9646 01:20:26.870960 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9647 01:20:26.877378 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9648 01:20:26.880662 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9649 01:20:26.887406 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9650 01:20:26.890663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9651 01:20:26.897391 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9652 01:20:26.900637 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9653 01:20:26.907411 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9654 01:20:26.910548 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9655 01:20:26.917329 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9656 01:20:26.920789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9657 01:20:26.927096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9658 01:20:26.930189 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9659 01:20:26.937051 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9660 01:20:26.940454 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9661 01:20:26.947054 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9662 01:20:26.950258 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9663 01:20:26.956878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9664 01:20:26.960703 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9665 01:20:26.966841 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9666 01:20:26.970158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9667 01:20:26.976525 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9668 01:20:26.979907 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9669 01:20:26.986335 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9670 01:20:26.990171 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9671 01:20:26.992884 INFO: [APUAPC] vio 0
9672 01:20:26.996500 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9673 01:20:27.002589 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9674 01:20:27.006405 INFO: [APUAPC] D0_APC_0: 0x400510
9675 01:20:27.007018 INFO: [APUAPC] D0_APC_1: 0x0
9676 01:20:27.009587 INFO: [APUAPC] D0_APC_2: 0x1540
9677 01:20:27.012933 INFO: [APUAPC] D0_APC_3: 0x0
9678 01:20:27.015954 INFO: [APUAPC] D1_APC_0: 0xffffffff
9679 01:20:27.019503 INFO: [APUAPC] D1_APC_1: 0xffffffff
9680 01:20:27.022738 INFO: [APUAPC] D1_APC_2: 0x3fffff
9681 01:20:27.025996 INFO: [APUAPC] D1_APC_3: 0x0
9682 01:20:27.029573 INFO: [APUAPC] D2_APC_0: 0xffffffff
9683 01:20:27.032669 INFO: [APUAPC] D2_APC_1: 0xffffffff
9684 01:20:27.036241 INFO: [APUAPC] D2_APC_2: 0x3fffff
9685 01:20:27.039342 INFO: [APUAPC] D2_APC_3: 0x0
9686 01:20:27.042684 INFO: [APUAPC] D3_APC_0: 0xffffffff
9687 01:20:27.045788 INFO: [APUAPC] D3_APC_1: 0xffffffff
9688 01:20:27.049295 INFO: [APUAPC] D3_APC_2: 0x3fffff
9689 01:20:27.052591 INFO: [APUAPC] D3_APC_3: 0x0
9690 01:20:27.055938 INFO: [APUAPC] D4_APC_0: 0xffffffff
9691 01:20:27.059202 INFO: [APUAPC] D4_APC_1: 0xffffffff
9692 01:20:27.062651 INFO: [APUAPC] D4_APC_2: 0x3fffff
9693 01:20:27.065403 INFO: [APUAPC] D4_APC_3: 0x0
9694 01:20:27.069177 INFO: [APUAPC] D5_APC_0: 0xffffffff
9695 01:20:27.072254 INFO: [APUAPC] D5_APC_1: 0xffffffff
9696 01:20:27.075340 INFO: [APUAPC] D5_APC_2: 0x3fffff
9697 01:20:27.079119 INFO: [APUAPC] D5_APC_3: 0x0
9698 01:20:27.082147 INFO: [APUAPC] D6_APC_0: 0xffffffff
9699 01:20:27.085372 INFO: [APUAPC] D6_APC_1: 0xffffffff
9700 01:20:27.088706 INFO: [APUAPC] D6_APC_2: 0x3fffff
9701 01:20:27.092514 INFO: [APUAPC] D6_APC_3: 0x0
9702 01:20:27.095537 INFO: [APUAPC] D7_APC_0: 0xffffffff
9703 01:20:27.098732 INFO: [APUAPC] D7_APC_1: 0xffffffff
9704 01:20:27.101662 INFO: [APUAPC] D7_APC_2: 0x3fffff
9705 01:20:27.105528 INFO: [APUAPC] D7_APC_3: 0x0
9706 01:20:27.108840 INFO: [APUAPC] D8_APC_0: 0xffffffff
9707 01:20:27.111916 INFO: [APUAPC] D8_APC_1: 0xffffffff
9708 01:20:27.115409 INFO: [APUAPC] D8_APC_2: 0x3fffff
9709 01:20:27.118582 INFO: [APUAPC] D8_APC_3: 0x0
9710 01:20:27.121473 INFO: [APUAPC] D9_APC_0: 0xffffffff
9711 01:20:27.125281 INFO: [APUAPC] D9_APC_1: 0xffffffff
9712 01:20:27.128245 INFO: [APUAPC] D9_APC_2: 0x3fffff
9713 01:20:27.131487 INFO: [APUAPC] D9_APC_3: 0x0
9714 01:20:27.134857 INFO: [APUAPC] D10_APC_0: 0xffffffff
9715 01:20:27.138618 INFO: [APUAPC] D10_APC_1: 0xffffffff
9716 01:20:27.141257 INFO: [APUAPC] D10_APC_2: 0x3fffff
9717 01:20:27.144774 INFO: [APUAPC] D10_APC_3: 0x0
9718 01:20:27.148231 INFO: [APUAPC] D11_APC_0: 0xffffffff
9719 01:20:27.151795 INFO: [APUAPC] D11_APC_1: 0xffffffff
9720 01:20:27.154656 INFO: [APUAPC] D11_APC_2: 0x3fffff
9721 01:20:27.158172 INFO: [APUAPC] D11_APC_3: 0x0
9722 01:20:27.161459 INFO: [APUAPC] D12_APC_0: 0xffffffff
9723 01:20:27.164718 INFO: [APUAPC] D12_APC_1: 0xffffffff
9724 01:20:27.168314 INFO: [APUAPC] D12_APC_2: 0x3fffff
9725 01:20:27.171203 INFO: [APUAPC] D12_APC_3: 0x0
9726 01:20:27.174835 INFO: [APUAPC] D13_APC_0: 0xffffffff
9727 01:20:27.178056 INFO: [APUAPC] D13_APC_1: 0xffffffff
9728 01:20:27.181237 INFO: [APUAPC] D13_APC_2: 0x3fffff
9729 01:20:27.184492 INFO: [APUAPC] D13_APC_3: 0x0
9730 01:20:27.187454 INFO: [APUAPC] D14_APC_0: 0xffffffff
9731 01:20:27.191267 INFO: [APUAPC] D14_APC_1: 0xffffffff
9732 01:20:27.194307 INFO: [APUAPC] D14_APC_2: 0x3fffff
9733 01:20:27.197885 INFO: [APUAPC] D14_APC_3: 0x0
9734 01:20:27.200773 INFO: [APUAPC] D15_APC_0: 0xffffffff
9735 01:20:27.204450 INFO: [APUAPC] D15_APC_1: 0xffffffff
9736 01:20:27.207605 INFO: [APUAPC] D15_APC_2: 0x3fffff
9737 01:20:27.210969 INFO: [APUAPC] D15_APC_3: 0x0
9738 01:20:27.214442 INFO: [APUAPC] APC_CON: 0x4
9739 01:20:27.217910 INFO: [NOCDAPC] D0_APC_0: 0x0
9740 01:20:27.220991 INFO: [NOCDAPC] D0_APC_1: 0x0
9741 01:20:27.221464 INFO: [NOCDAPC] D1_APC_0: 0x0
9742 01:20:27.224107 INFO: [NOCDAPC] D1_APC_1: 0xfff
9743 01:20:27.227559 INFO: [NOCDAPC] D2_APC_0: 0x0
9744 01:20:27.231077 INFO: [NOCDAPC] D2_APC_1: 0xfff
9745 01:20:27.234072 INFO: [NOCDAPC] D3_APC_0: 0x0
9746 01:20:27.237779 INFO: [NOCDAPC] D3_APC_1: 0xfff
9747 01:20:27.240753 INFO: [NOCDAPC] D4_APC_0: 0x0
9748 01:20:27.244049 INFO: [NOCDAPC] D4_APC_1: 0xfff
9749 01:20:27.247347 INFO: [NOCDAPC] D5_APC_0: 0x0
9750 01:20:27.250651 INFO: [NOCDAPC] D5_APC_1: 0xfff
9751 01:20:27.253790 INFO: [NOCDAPC] D6_APC_0: 0x0
9752 01:20:27.257422 INFO: [NOCDAPC] D6_APC_1: 0xfff
9753 01:20:27.257984 INFO: [NOCDAPC] D7_APC_0: 0x0
9754 01:20:27.260664 INFO: [NOCDAPC] D7_APC_1: 0xfff
9755 01:20:27.263892 INFO: [NOCDAPC] D8_APC_0: 0x0
9756 01:20:27.267427 INFO: [NOCDAPC] D8_APC_1: 0xfff
9757 01:20:27.270471 INFO: [NOCDAPC] D9_APC_0: 0x0
9758 01:20:27.273523 INFO: [NOCDAPC] D9_APC_1: 0xfff
9759 01:20:27.277102 INFO: [NOCDAPC] D10_APC_0: 0x0
9760 01:20:27.280371 INFO: [NOCDAPC] D10_APC_1: 0xfff
9761 01:20:27.283734 INFO: [NOCDAPC] D11_APC_0: 0x0
9762 01:20:27.286821 INFO: [NOCDAPC] D11_APC_1: 0xfff
9763 01:20:27.290591 INFO: [NOCDAPC] D12_APC_0: 0x0
9764 01:20:27.293675 INFO: [NOCDAPC] D12_APC_1: 0xfff
9765 01:20:27.296881 INFO: [NOCDAPC] D13_APC_0: 0x0
9766 01:20:27.299906 INFO: [NOCDAPC] D13_APC_1: 0xfff
9767 01:20:27.300434 INFO: [NOCDAPC] D14_APC_0: 0x0
9768 01:20:27.303366 INFO: [NOCDAPC] D14_APC_1: 0xfff
9769 01:20:27.306970 INFO: [NOCDAPC] D15_APC_0: 0x0
9770 01:20:27.310075 INFO: [NOCDAPC] D15_APC_1: 0xfff
9771 01:20:27.313362 INFO: [NOCDAPC] APC_CON: 0x4
9772 01:20:27.316640 INFO: [APUAPC] set_apusys_apc done
9773 01:20:27.319677 INFO: [DEVAPC] devapc_init done
9774 01:20:27.323456 INFO: GICv3 without legacy support detected.
9775 01:20:27.329528 INFO: ARM GICv3 driver initialized in EL3
9776 01:20:27.332920 INFO: Maximum SPI INTID supported: 639
9777 01:20:27.336626 INFO: BL31: Initializing runtime services
9778 01:20:27.343022 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9779 01:20:27.346411 INFO: SPM: enable CPC mode
9780 01:20:27.349614 INFO: mcdi ready for mcusys-off-idle and system suspend
9781 01:20:27.356698 INFO: BL31: Preparing for EL3 exit to normal world
9782 01:20:27.359595 INFO: Entry point address = 0x80000000
9783 01:20:27.360158 INFO: SPSR = 0x8
9784 01:20:27.366185
9785 01:20:27.366748
9786 01:20:27.367122
9787 01:20:27.369424 Starting depthcharge on Spherion...
9788 01:20:27.369991
9789 01:20:27.370405 Wipe memory regions:
9790 01:20:27.370759
9791 01:20:27.373270 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9792 01:20:27.373815 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9793 01:20:27.374307 Setting prompt string to ['asurada:']
9794 01:20:27.374776 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9795 01:20:27.375513 [0x00000040000000, 0x00000054600000)
9796 01:20:27.494743
9797 01:20:27.495303 [0x00000054660000, 0x00000080000000)
9798 01:20:27.754744
9799 01:20:27.757932 [0x000000821a7280, 0x000000ffe64000)
9800 01:20:28.498516
9801 01:20:28.499074 [0x00000100000000, 0x00000140000000)
9802 01:20:28.877920
9803 01:20:28.881148 Initializing XHCI USB controller at 0x11200000.
9804 01:20:29.918696
9805 01:20:29.922324 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9806 01:20:29.922889
9807 01:20:29.923264
9808 01:20:29.923615
9809 01:20:29.924434 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9811 01:20:30.025762 asurada: tftpboot 192.168.201.1 13468762/tftp-deploy-p9xkn4mi/kernel/image.itb 13468762/tftp-deploy-p9xkn4mi/kernel/cmdline
9812 01:20:30.026526 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9813 01:20:30.027087 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9814 01:20:30.031425 tftpboot 192.168.201.1 13468762/tftp-deploy-p9xkn4mi/kernel/image.ittp-deploy-p9xkn4mi/kernel/cmdline
9815 01:20:30.031995
9816 01:20:30.032369 Waiting for link
9817 01:20:30.192113
9818 01:20:30.192670 R8152: Initializing
9819 01:20:30.193046
9820 01:20:30.195056 Version 9 (ocp_data = 6010)
9821 01:20:30.195518
9822 01:20:30.199069 R8152: Done initializing
9823 01:20:30.199694
9824 01:20:30.200096 Adding net device
9825 01:20:32.206417
9826 01:20:32.207036 done.
9827 01:20:32.207467
9828 01:20:32.207828 MAC: 00:e0:4c:68:03:bd
9829 01:20:32.208165
9830 01:20:32.209763 Sending DHCP discover... done.
9831 01:20:32.210271
9832 01:20:32.212933 Waiting for reply... done.
9833 01:20:32.213463
9834 01:20:32.216022 Sending DHCP request... done.
9835 01:20:32.216481
9836 01:20:32.219374 Waiting for reply... done.
9837 01:20:32.219834
9838 01:20:32.220200 My ip is 192.168.201.16
9839 01:20:32.220539
9840 01:20:32.222667 The DHCP server ip is 192.168.201.1
9841 01:20:32.223130
9842 01:20:32.229578 TFTP server IP predefined by user: 192.168.201.1
9843 01:20:32.230196
9844 01:20:32.236118 Bootfile predefined by user: 13468762/tftp-deploy-p9xkn4mi/kernel/image.itb
9845 01:20:32.236582
9846 01:20:32.238969 Sending tftp read request... done.
9847 01:20:32.239434
9848 01:20:32.245447 Waiting for the transfer...
9849 01:20:32.245909
9850 01:20:32.532245 00000000 ################################################################
9851 01:20:32.532467
9852 01:20:32.818222 00080000 ################################################################
9853 01:20:32.818395
9854 01:20:33.114987 00100000 ################################################################
9855 01:20:33.115130
9856 01:20:33.409883 00180000 ################################################################
9857 01:20:33.410026
9858 01:20:33.705350 00200000 ################################################################
9859 01:20:33.705494
9860 01:20:33.991093 00280000 ################################################################
9861 01:20:33.991230
9862 01:20:34.280137 00300000 ################################################################
9863 01:20:34.280273
9864 01:20:34.556699 00380000 ################################################################
9865 01:20:34.556863
9866 01:20:34.833056 00400000 ################################################################
9867 01:20:34.833198
9868 01:20:35.095121 00480000 ################################################################
9869 01:20:35.095259
9870 01:20:35.382309 00500000 ################################################################
9871 01:20:35.382446
9872 01:20:35.648121 00580000 ################################################################
9873 01:20:35.648258
9874 01:20:35.931688 00600000 ################################################################
9875 01:20:35.931852
9876 01:20:36.206455 00680000 ################################################################
9877 01:20:36.206591
9878 01:20:36.462994 00700000 ################################################################
9879 01:20:36.463131
9880 01:20:36.715963 00780000 ################################################################
9881 01:20:36.716096
9882 01:20:36.987954 00800000 ################################################################
9883 01:20:36.988097
9884 01:20:37.268712 00880000 ################################################################
9885 01:20:37.268856
9886 01:20:37.565638 00900000 ################################################################
9887 01:20:37.565781
9888 01:20:37.861604 00980000 ################################################################
9889 01:20:37.861742
9890 01:20:38.155358 00a00000 ################################################################
9891 01:20:38.155504
9892 01:20:38.445404 00a80000 ################################################################
9893 01:20:38.445548
9894 01:20:38.719594 00b00000 ################################################################
9895 01:20:38.719730
9896 01:20:39.014295 00b80000 ################################################################
9897 01:20:39.014434
9898 01:20:39.304962 00c00000 ################################################################
9899 01:20:39.305117
9900 01:20:39.597956 00c80000 ################################################################
9901 01:20:39.598104
9902 01:20:39.874192 00d00000 ################################################################
9903 01:20:39.874328
9904 01:20:40.170072 00d80000 ################################################################
9905 01:20:40.170209
9906 01:20:40.463394 00e00000 ################################################################
9907 01:20:40.463536
9908 01:20:40.749462 00e80000 ################################################################
9909 01:20:40.749603
9910 01:20:41.017828 00f00000 ################################################################
9911 01:20:41.017974
9912 01:20:41.312757 00f80000 ################################################################
9913 01:20:41.312903
9914 01:20:41.604589 01000000 ################################################################
9915 01:20:41.604730
9916 01:20:41.900157 01080000 ################################################################
9917 01:20:41.900298
9918 01:20:42.197395 01100000 ################################################################
9919 01:20:42.197531
9920 01:20:42.491499 01180000 ################################################################
9921 01:20:42.491638
9922 01:20:42.765222 01200000 ################################################################
9923 01:20:42.765369
9924 01:20:43.015386 01280000 ################################################################
9925 01:20:43.015535
9926 01:20:43.268015 01300000 ################################################################
9927 01:20:43.268151
9928 01:20:43.562804 01380000 ################################################################
9929 01:20:43.562935
9930 01:20:43.853500 01400000 ################################################################
9931 01:20:43.853643
9932 01:20:44.149366 01480000 ################################################################
9933 01:20:44.149504
9934 01:20:44.435040 01500000 ################################################################
9935 01:20:44.435178
9936 01:20:44.717778 01580000 ################################################################
9937 01:20:44.717915
9938 01:20:44.997093 01600000 ################################################################
9939 01:20:44.997235
9940 01:20:45.283106 01680000 ################################################################
9941 01:20:45.283244
9942 01:20:45.569608 01700000 ################################################################
9943 01:20:45.569743
9944 01:20:45.865298 01780000 ################################################################
9945 01:20:45.865437
9946 01:20:46.135087 01800000 ################################################################
9947 01:20:46.135254
9948 01:20:46.388909 01880000 ################################################################
9949 01:20:46.389072
9950 01:20:46.654885 01900000 ################################################################
9951 01:20:46.655043
9952 01:20:46.948055 01980000 ################################################################
9953 01:20:46.948188
9954 01:20:47.202911 01a00000 ################################################################
9955 01:20:47.203055
9956 01:20:47.484048 01a80000 ################################################################
9957 01:20:47.484188
9958 01:20:47.770393 01b00000 ################################################################
9959 01:20:47.770533
9960 01:20:48.067811 01b80000 ################################################################
9961 01:20:48.067957
9962 01:20:48.350312 01c00000 ################################################################
9963 01:20:48.350483
9964 01:20:48.642841 01c80000 ################################################################
9965 01:20:48.642986
9966 01:20:48.921907 01d00000 ################################################################
9967 01:20:48.922050
9968 01:20:49.197169 01d80000 ################################################################
9969 01:20:49.197305
9970 01:20:49.354734 01e00000 ################################## done.
9971 01:20:49.354860
9972 01:20:49.358032 The bootfile was 31735070 bytes long.
9973 01:20:49.358155
9974 01:20:49.361331 Sending tftp read request... done.
9975 01:20:49.361427
9976 01:20:49.361502 Waiting for the transfer...
9977 01:20:49.361573
9978 01:20:49.364762 00000000 # done.
9979 01:20:49.364868
9980 01:20:49.371392 Command line loaded dynamically from TFTP file: 13468762/tftp-deploy-p9xkn4mi/kernel/cmdline
9981 01:20:49.371587
9982 01:20:49.394692 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13468762/extract-nfsrootfs-yac1dttm,tcp,hard ip=dhcp tftpserverip=192.168.201.1
9983 01:20:49.395003
9984 01:20:49.395181 Loading FIT.
9985 01:20:49.395341
9986 01:20:49.398069 Image ramdisk-1 has 18775754 bytes.
9987 01:20:49.398361
9988 01:20:49.401101 Image fdt-1 has 47230 bytes.
9989 01:20:49.401351
9990 01:20:49.404852 Image kernel-1 has 12910050 bytes.
9991 01:20:49.405268
9992 01:20:49.414767 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
9993 01:20:49.415347
9994 01:20:49.431120 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
9995 01:20:49.431716
9996 01:20:49.437507 Choosing best match conf-1 for compat google,spherion-rev3.
9997 01:20:49.437978
9998 01:20:49.445783 Connected to device vid:did:rid of 1ae0:0028:00
9999 01:20:49.453806
10000 01:20:49.456897 tpm_get_response: command 0x17b, return code 0x0
10001 01:20:49.457383
10002 01:20:49.460151 ec_init: CrosEC protocol v3 supported (256, 248)
10003 01:20:49.465375
10004 01:20:49.468314 tpm_cleanup: add release locality here.
10005 01:20:49.468784
10006 01:20:49.469156 Shutting down all USB controllers.
10007 01:20:49.471548
10008 01:20:49.472011 Removing current net device
10009 01:20:49.472384
10010 01:20:49.478376 Exiting depthcharge with code 4 at timestamp: 50302258
10011 01:20:49.478855
10012 01:20:49.481881 LZMA decompressing kernel-1 to 0x821a6718
10013 01:20:49.482396
10014 01:20:49.485147 LZMA decompressing kernel-1 to 0x40000000
10015 01:20:51.078839
10016 01:20:51.079410 jumping to kernel
10017 01:20:51.081265 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10018 01:20:51.081878 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10019 01:20:51.082403 Setting prompt string to ['Linux version [0-9]']
10020 01:20:51.082878 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10021 01:20:51.083347 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10022 01:20:51.128959
10023 01:20:51.132757 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10024 01:20:51.135997 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10025 01:20:51.136335 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10026 01:20:51.136587 Setting prompt string to []
10027 01:20:51.136860 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10028 01:20:51.137101 Using line separator: #'\n'#
10029 01:20:51.137304 No login prompt set.
10030 01:20:51.137533 Parsing kernel messages
10031 01:20:51.137796 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10032 01:20:51.138234 [login-action] Waiting for messages, (timeout 00:04:03)
10033 01:20:51.138547 Waiting using forced prompt support (timeout 00:02:01)
10034 01:20:51.155688 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j174389-arm64-gcc-10-defconfig-arm64-chromebook-96m9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024
10035 01:20:51.158949 [ 0.000000] random: crng init done
10036 01:20:51.165302 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10037 01:20:51.168869 [ 0.000000] efi: UEFI not found.
10038 01:20:51.175473 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10039 01:20:51.182306 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10040 01:20:51.191590 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10041 01:20:51.201473 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10042 01:20:51.208639 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10043 01:20:51.215264 [ 0.000000] printk: bootconsole [mtk8250] enabled
10044 01:20:51.221534 [ 0.000000] NUMA: No NUMA configuration found
10045 01:20:51.228385 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10046 01:20:51.231445 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10047 01:20:51.234930 [ 0.000000] Zone ranges:
10048 01:20:51.241481 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10049 01:20:51.244776 [ 0.000000] DMA32 empty
10050 01:20:51.251347 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10051 01:20:51.254655 [ 0.000000] Movable zone start for each node
10052 01:20:51.257632 [ 0.000000] Early memory node ranges
10053 01:20:51.264545 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10054 01:20:51.270707 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10055 01:20:51.277924 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10056 01:20:51.283964 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10057 01:20:51.290547 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10058 01:20:51.297149 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10059 01:20:51.327991 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10060 01:20:51.334877 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10061 01:20:51.341277 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10062 01:20:51.344473 [ 0.000000] psci: probing for conduit method from DT.
10063 01:20:51.351327 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10064 01:20:51.354206 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10065 01:20:51.360888 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10066 01:20:51.364267 [ 0.000000] psci: SMC Calling Convention v1.2
10067 01:20:51.371083 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10068 01:20:51.374190 [ 0.000000] Detected VIPT I-cache on CPU0
10069 01:20:51.380566 [ 0.000000] CPU features: detected: GIC system register CPU interface
10070 01:20:51.387095 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10071 01:20:51.393508 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10072 01:20:51.400257 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10073 01:20:51.410127 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10074 01:20:51.416718 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10075 01:20:51.419671 [ 0.000000] alternatives: applying boot alternatives
10076 01:20:51.426513 [ 0.000000] Fallback order for Node 0: 0
10077 01:20:51.433622 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10078 01:20:51.436863 [ 0.000000] Policy zone: Normal
10079 01:20:51.459719 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13468762/extract-nfsrootfs-yac1dttm,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10080 01:20:51.469710 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10081 01:20:51.479533 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10082 01:20:51.489034 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10083 01:20:51.495671 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10084 01:20:51.498954 <6>[ 0.000000] software IO TLB: area num 8.
10085 01:20:51.554565 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10086 01:20:51.635787 <6>[ 0.000000] Memory: 3831760K/4191232K available (18048K kernel code, 4118K rwdata, 22292K rodata, 8448K init, 616K bss, 326704K reserved, 32768K cma-reserved)
10087 01:20:51.642261 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10088 01:20:51.648940 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10089 01:20:51.652170 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10090 01:20:51.658736 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10091 01:20:51.665438 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10092 01:20:51.669045 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10093 01:20:51.678694 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10094 01:20:51.685018 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10095 01:20:51.691750 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10096 01:20:51.698299 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10097 01:20:51.702007 <6>[ 0.000000] GICv3: 608 SPIs implemented
10098 01:20:51.704634 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10099 01:20:51.711508 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10100 01:20:51.714747 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10101 01:20:51.721372 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10102 01:20:51.734569 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10103 01:20:51.747826 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10104 01:20:51.754125 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10105 01:20:51.762114 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10106 01:20:51.775269 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10107 01:20:51.782123 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10108 01:20:51.788613 <6>[ 0.009181] Console: colour dummy device 80x25
10109 01:20:51.798280 <6>[ 0.013910] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10110 01:20:51.805322 <6>[ 0.024352] pid_max: default: 32768 minimum: 301
10111 01:20:51.808287 <6>[ 0.029223] LSM: Security Framework initializing
10112 01:20:51.814968 <6>[ 0.034136] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10113 01:20:51.824739 <6>[ 0.041743] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10114 01:20:51.831333 <6>[ 0.050972] cblist_init_generic: Setting adjustable number of callback queues.
10115 01:20:51.838201 <6>[ 0.058415] cblist_init_generic: Setting shift to 3 and lim to 1.
10116 01:20:51.847880 <6>[ 0.064755] cblist_init_generic: Setting adjustable number of callback queues.
10117 01:20:51.854494 <6>[ 0.072181] cblist_init_generic: Setting shift to 3 and lim to 1.
10118 01:20:51.858119 <6>[ 0.078620] rcu: Hierarchical SRCU implementation.
10119 01:20:51.864373 <6>[ 0.083666] rcu: Max phase no-delay instances is 1000.
10120 01:20:51.870541 <6>[ 0.090699] EFI services will not be available.
10121 01:20:51.873994 <6>[ 0.095656] smp: Bringing up secondary CPUs ...
10122 01:20:51.882576 <6>[ 0.100702] Detected VIPT I-cache on CPU1
10123 01:20:51.889178 <6>[ 0.100771] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10124 01:20:51.895734 <6>[ 0.100801] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10125 01:20:51.899143 <6>[ 0.101131] Detected VIPT I-cache on CPU2
10126 01:20:51.909281 <6>[ 0.101177] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10127 01:20:51.915275 <6>[ 0.101193] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10128 01:20:51.918510 <6>[ 0.101451] Detected VIPT I-cache on CPU3
10129 01:20:51.925490 <6>[ 0.101493] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10130 01:20:51.931797 <6>[ 0.101507] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10131 01:20:51.938779 <6>[ 0.101793] CPU features: detected: Spectre-v4
10132 01:20:51.941608 <6>[ 0.101798] CPU features: detected: Spectre-BHB
10133 01:20:51.944785 <6>[ 0.101803] Detected PIPT I-cache on CPU4
10134 01:20:51.951979 <6>[ 0.101853] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10135 01:20:51.958310 <6>[ 0.101868] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10136 01:20:51.964774 <6>[ 0.102157] Detected PIPT I-cache on CPU5
10137 01:20:51.971329 <6>[ 0.102219] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10138 01:20:51.978206 <6>[ 0.102235] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10139 01:20:51.981438 <6>[ 0.102514] Detected PIPT I-cache on CPU6
10140 01:20:51.991310 <6>[ 0.102577] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10141 01:20:51.997773 <6>[ 0.102593] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10142 01:20:52.001041 <6>[ 0.102891] Detected PIPT I-cache on CPU7
10143 01:20:52.007681 <6>[ 0.102956] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10144 01:20:52.014135 <6>[ 0.102973] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10145 01:20:52.017261 <6>[ 0.103019] smp: Brought up 1 node, 8 CPUs
10146 01:20:52.024006 <6>[ 0.244477] SMP: Total of 8 processors activated.
10147 01:20:52.030321 <6>[ 0.249429] CPU features: detected: 32-bit EL0 Support
10148 01:20:52.037156 <6>[ 0.254792] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10149 01:20:52.043701 <6>[ 0.263593] CPU features: detected: Common not Private translations
10150 01:20:52.050305 <6>[ 0.270109] CPU features: detected: CRC32 instructions
10151 01:20:52.057070 <6>[ 0.275460] CPU features: detected: RCpc load-acquire (LDAPR)
10152 01:20:52.060447 <6>[ 0.281420] CPU features: detected: LSE atomic instructions
10153 01:20:52.066767 <6>[ 0.287202] CPU features: detected: Privileged Access Never
10154 01:20:52.073157 <6>[ 0.293018] CPU features: detected: RAS Extension Support
10155 01:20:52.080045 <6>[ 0.298626] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10156 01:20:52.083256 <6>[ 0.305847] CPU: All CPU(s) started at EL2
10157 01:20:52.089701 <6>[ 0.310164] alternatives: applying system-wide alternatives
10158 01:20:52.099419 <6>[ 0.320166] devtmpfs: initialized
10159 01:20:52.114717 <6>[ 0.328406] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10160 01:20:52.121122 <6>[ 0.338367] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10161 01:20:52.127507 <6>[ 0.346613] pinctrl core: initialized pinctrl subsystem
10162 01:20:52.130958 <6>[ 0.353221] DMI not present or invalid.
10163 01:20:52.137380 <6>[ 0.357625] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10164 01:20:52.147395 <6>[ 0.364495] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10165 01:20:52.154247 <6>[ 0.371944] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10166 01:20:52.163868 <6>[ 0.380039] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10167 01:20:52.167510 <6>[ 0.388194] audit: initializing netlink subsys (disabled)
10168 01:20:52.177082 <5>[ 0.393894] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10169 01:20:52.183514 <6>[ 0.394585] thermal_sys: Registered thermal governor 'step_wise'
10170 01:20:52.190318 <6>[ 0.401861] thermal_sys: Registered thermal governor 'power_allocator'
10171 01:20:52.193492 <6>[ 0.408115] cpuidle: using governor menu
10172 01:20:52.200315 <6>[ 0.419071] NET: Registered PF_QIPCRTR protocol family
10173 01:20:52.206904 <6>[ 0.424571] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10174 01:20:52.213320 <6>[ 0.431675] ASID allocator initialised with 32768 entries
10175 01:20:52.216472 <6>[ 0.438219] Serial: AMBA PL011 UART driver
10176 01:20:52.226415 <4>[ 0.446962] Trying to register duplicate clock ID: 134
10177 01:20:52.280321 <6>[ 0.504221] KASLR enabled
10178 01:20:52.294684 <6>[ 0.511877] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10179 01:20:52.301256 <6>[ 0.518892] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10180 01:20:52.307734 <6>[ 0.525382] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10181 01:20:52.314665 <6>[ 0.532389] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10182 01:20:52.321107 <6>[ 0.538876] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10183 01:20:52.327204 <6>[ 0.545878] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10184 01:20:52.334122 <6>[ 0.552364] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10185 01:20:52.341280 <6>[ 0.559371] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10186 01:20:52.343694 <6>[ 0.566814] ACPI: Interpreter disabled.
10187 01:20:52.352820 <6>[ 0.573210] iommu: Default domain type: Translated
10188 01:20:52.359413 <6>[ 0.578358] iommu: DMA domain TLB invalidation policy: strict mode
10189 01:20:52.362511 <5>[ 0.585015] SCSI subsystem initialized
10190 01:20:52.369267 <6>[ 0.589261] usbcore: registered new interface driver usbfs
10191 01:20:52.375704 <6>[ 0.594987] usbcore: registered new interface driver hub
10192 01:20:52.379028 <6>[ 0.600540] usbcore: registered new device driver usb
10193 01:20:52.385943 <6>[ 0.606649] pps_core: LinuxPPS API ver. 1 registered
10194 01:20:52.395955 <6>[ 0.611840] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10195 01:20:52.399121 <6>[ 0.621187] PTP clock support registered
10196 01:20:52.402304 <6>[ 0.625424] EDAC MC: Ver: 3.0.0
10197 01:20:52.409979 <6>[ 0.630599] FPGA manager framework
10198 01:20:52.416602 <6>[ 0.634275] Advanced Linux Sound Architecture Driver Initialized.
10199 01:20:52.420165 <6>[ 0.641044] vgaarb: loaded
10200 01:20:52.426428 <6>[ 0.644215] clocksource: Switched to clocksource arch_sys_counter
10201 01:20:52.429848 <5>[ 0.650662] VFS: Disk quotas dquot_6.6.0
10202 01:20:52.436707 <6>[ 0.654844] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10203 01:20:52.439869 <6>[ 0.662037] pnp: PnP ACPI: disabled
10204 01:20:52.448660 <6>[ 0.668691] NET: Registered PF_INET protocol family
10205 01:20:52.454675 <6>[ 0.674072] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10206 01:20:52.466900 <6>[ 0.684080] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10207 01:20:52.476451 <6>[ 0.692862] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10208 01:20:52.483502 <6>[ 0.700828] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10209 01:20:52.489887 <6>[ 0.709231] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10210 01:20:52.500510 <6>[ 0.717888] TCP: Hash tables configured (established 32768 bind 32768)
10211 01:20:52.507173 <6>[ 0.724741] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10212 01:20:52.513876 <6>[ 0.731762] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10213 01:20:52.520484 <6>[ 0.739288] NET: Registered PF_UNIX/PF_LOCAL protocol family
10214 01:20:52.527139 <6>[ 0.745424] RPC: Registered named UNIX socket transport module.
10215 01:20:52.530002 <6>[ 0.751575] RPC: Registered udp transport module.
10216 01:20:52.536918 <6>[ 0.756507] RPC: Registered tcp transport module.
10217 01:20:52.543209 <6>[ 0.761439] RPC: Registered tcp NFSv4.1 backchannel transport module.
10218 01:20:52.546895 <6>[ 0.768102] PCI: CLS 0 bytes, default 64
10219 01:20:52.550073 <6>[ 0.772451] Unpacking initramfs...
10220 01:20:52.559973 <6>[ 0.776167] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10221 01:20:52.566403 <6>[ 0.784788] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10222 01:20:52.573036 <6>[ 0.793575] kvm [1]: IPA Size Limit: 40 bits
10223 01:20:52.576771 <6>[ 0.798101] kvm [1]: GICv3: no GICV resource entry
10224 01:20:52.582582 <6>[ 0.803122] kvm [1]: disabling GICv2 emulation
10225 01:20:52.589394 <6>[ 0.807803] kvm [1]: GIC system register CPU interface enabled
10226 01:20:52.592891 <6>[ 0.813955] kvm [1]: vgic interrupt IRQ18
10227 01:20:52.599183 <6>[ 0.818315] kvm [1]: VHE mode initialized successfully
10228 01:20:52.602589 <5>[ 0.824708] Initialise system trusted keyrings
10229 01:20:52.609301 <6>[ 0.829532] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10230 01:20:52.619226 <6>[ 0.839468] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10231 01:20:52.625717 <5>[ 0.845845] NFS: Registering the id_resolver key type
10232 01:20:52.628681 <5>[ 0.851140] Key type id_resolver registered
10233 01:20:52.635390 <5>[ 0.855553] Key type id_legacy registered
10234 01:20:52.641725 <6>[ 0.859831] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10235 01:20:52.648449 <6>[ 0.866753] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10236 01:20:52.654962 <6>[ 0.874481] 9p: Installing v9fs 9p2000 file system support
10237 01:20:52.691488 <5>[ 0.912169] Key type asymmetric registered
10238 01:20:52.695215 <5>[ 0.916502] Asymmetric key parser 'x509' registered
10239 01:20:52.704748 <6>[ 0.921665] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10240 01:20:52.708262 <6>[ 0.929284] io scheduler mq-deadline registered
10241 01:20:52.711073 <6>[ 0.934043] io scheduler kyber registered
10242 01:20:52.730545 <6>[ 0.951038] EINJ: ACPI disabled.
10243 01:20:52.762632 <4>[ 0.976494] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10244 01:20:52.772423 <4>[ 0.987105] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10245 01:20:52.786639 <6>[ 1.007705] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10246 01:20:52.794746 <6>[ 1.015761] printk: console [ttyS0] disabled
10247 01:20:52.822697 <6>[ 1.040394] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10248 01:20:52.829346 <6>[ 1.049859] printk: console [ttyS0] enabled
10249 01:20:52.832795 <6>[ 1.049859] printk: console [ttyS0] enabled
10250 01:20:52.839305 <6>[ 1.058754] printk: bootconsole [mtk8250] disabled
10251 01:20:52.842747 <6>[ 1.058754] printk: bootconsole [mtk8250] disabled
10252 01:20:52.849282 <6>[ 1.069791] SuperH (H)SCI(F) driver initialized
10253 01:20:52.853226 <6>[ 1.075060] msm_serial: driver initialized
10254 01:20:52.866459 <6>[ 1.083946] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10255 01:20:52.876335 <6>[ 1.092493] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10256 01:20:52.883395 <6>[ 1.101037] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10257 01:20:52.893031 <6>[ 1.109665] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10258 01:20:52.903154 <6>[ 1.118372] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10259 01:20:52.909580 <6>[ 1.127092] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10260 01:20:52.919682 <6>[ 1.135634] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10261 01:20:52.926332 <6>[ 1.144427] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10262 01:20:52.936281 <6>[ 1.152970] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10263 01:20:52.947985 <6>[ 1.168488] loop: module loaded
10264 01:20:52.954428 <6>[ 1.174293] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10265 01:20:52.976605 <4>[ 1.197575] mtk-pmic-keys: Failed to locate of_node [id: -1]
10266 01:20:52.983764 <6>[ 1.204370] megasas: 07.719.03.00-rc1
10267 01:20:52.993325 <6>[ 1.214011] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10268 01:20:53.003311 <6>[ 1.223664] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10269 01:20:53.019301 <6>[ 1.239600] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10270 01:20:53.074635 <6>[ 1.288829] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10271 01:20:53.343579 <6>[ 1.563849] Freeing initrd memory: 18332K
10272 01:20:53.354654 <6>[ 1.575455] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10273 01:20:53.366355 <6>[ 1.586526] tun: Universal TUN/TAP device driver, 1.6
10274 01:20:53.369444 <6>[ 1.592611] thunder_xcv, ver 1.0
10275 01:20:53.372191 <6>[ 1.596109] thunder_bgx, ver 1.0
10276 01:20:53.375902 <6>[ 1.599608] nicpf, ver 1.0
10277 01:20:53.386317 <6>[ 1.603652] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10278 01:20:53.389524 <6>[ 1.611127] hns3: Copyright (c) 2017 Huawei Corporation.
10279 01:20:53.396494 <6>[ 1.616719] hclge is initializing
10280 01:20:53.399573 <6>[ 1.620302] e1000: Intel(R) PRO/1000 Network Driver
10281 01:20:53.406192 <6>[ 1.625432] e1000: Copyright (c) 1999-2006 Intel Corporation.
10282 01:20:53.409452 <6>[ 1.631444] e1000e: Intel(R) PRO/1000 Network Driver
10283 01:20:53.416021 <6>[ 1.636659] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10284 01:20:53.422430 <6>[ 1.642846] igb: Intel(R) Gigabit Ethernet Network Driver
10285 01:20:53.429088 <6>[ 1.648496] igb: Copyright (c) 2007-2014 Intel Corporation.
10286 01:20:53.435732 <6>[ 1.654333] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10287 01:20:53.442587 <6>[ 1.660850] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10288 01:20:53.446116 <6>[ 1.667327] sky2: driver version 1.30
10289 01:20:53.452288 <6>[ 1.672328] VFIO - User Level meta-driver version: 0.3
10290 01:20:53.460008 <6>[ 1.680586] usbcore: registered new interface driver usb-storage
10291 01:20:53.466412 <6>[ 1.687034] usbcore: registered new device driver onboard-usb-hub
10292 01:20:53.475613 <6>[ 1.696180] mt6397-rtc mt6359-rtc: registered as rtc0
10293 01:20:53.485329 <6>[ 1.701651] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-23T01:20:52 UTC (1713835252)
10294 01:20:53.488946 <6>[ 1.711210] i2c_dev: i2c /dev entries driver
10295 01:20:53.505642 <6>[ 1.722999] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10296 01:20:53.512254 <4>[ 1.731720] cpu cpu0: supply cpu not found, using dummy regulator
10297 01:20:53.519179 <4>[ 1.738141] cpu cpu1: supply cpu not found, using dummy regulator
10298 01:20:53.525670 <4>[ 1.744547] cpu cpu2: supply cpu not found, using dummy regulator
10299 01:20:53.532255 <4>[ 1.750949] cpu cpu3: supply cpu not found, using dummy regulator
10300 01:20:53.538581 <4>[ 1.757366] cpu cpu4: supply cpu not found, using dummy regulator
10301 01:20:53.545250 <4>[ 1.763765] cpu cpu5: supply cpu not found, using dummy regulator
10302 01:20:53.552322 <4>[ 1.770161] cpu cpu6: supply cpu not found, using dummy regulator
10303 01:20:53.558858 <4>[ 1.776558] cpu cpu7: supply cpu not found, using dummy regulator
10304 01:20:53.577587 <6>[ 1.798184] cpu cpu0: EM: created perf domain
10305 01:20:53.580750 <6>[ 1.803109] cpu cpu4: EM: created perf domain
10306 01:20:53.587893 <6>[ 1.808665] sdhci: Secure Digital Host Controller Interface driver
10307 01:20:53.594361 <6>[ 1.815096] sdhci: Copyright(c) Pierre Ossman
10308 01:20:53.601141 <6>[ 1.820019] Synopsys Designware Multimedia Card Interface Driver
10309 01:20:53.608039 <6>[ 1.826621] sdhci-pltfm: SDHCI platform and OF driver helper
10310 01:20:53.611179 <6>[ 1.826778] mmc0: CQHCI version 5.10
10311 01:20:53.618262 <6>[ 1.836985] ledtrig-cpu: registered to indicate activity on CPUs
10312 01:20:53.624721 <6>[ 1.844059] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10313 01:20:53.631216 <6>[ 1.851095] usbcore: registered new interface driver usbhid
10314 01:20:53.634543 <6>[ 1.856919] usbhid: USB HID core driver
10315 01:20:53.641553 <6>[ 1.861110] spi_master spi0: will run message pump with realtime priority
10316 01:20:53.685157 <6>[ 1.899145] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10317 01:20:53.704276 <6>[ 1.914984] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10318 01:20:53.707945 <6>[ 1.928491] mmc0: Command Queue Engine enabled
10319 01:20:53.714629 <6>[ 1.933232] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10320 01:20:53.721267 <6>[ 1.940149] cros-ec-spi spi0.0: Chrome EC device registered
10321 01:20:53.724642 <6>[ 1.940432] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10322 01:20:53.734578 <6>[ 1.955347] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10323 01:20:53.742122 <6>[ 1.962548] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10324 01:20:53.748487 <6>[ 1.968435] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10325 01:20:53.755297 <6>[ 1.974282] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10326 01:20:53.764979 <6>[ 1.979445] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10327 01:20:53.771789 <6>[ 1.991412] NET: Registered PF_PACKET protocol family
10328 01:20:53.774833 <6>[ 1.996802] 9pnet: Installing 9P2000 support
10329 01:20:53.781602 <5>[ 2.001365] Key type dns_resolver registered
10330 01:20:53.785027 <6>[ 2.006328] registered taskstats version 1
10331 01:20:53.791917 <5>[ 2.010706] Loading compiled-in X.509 certificates
10332 01:20:53.819470 <4>[ 2.033229] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10333 01:20:53.829290 <4>[ 2.043968] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10334 01:20:53.835536 <3>[ 2.054552] debugfs: File 'uA_load' in directory '/' already present!
10335 01:20:53.842463 <3>[ 2.061264] debugfs: File 'min_uV' in directory '/' already present!
10336 01:20:53.849001 <3>[ 2.067885] debugfs: File 'max_uV' in directory '/' already present!
10337 01:20:53.855647 <3>[ 2.074496] debugfs: File 'constraint_flags' in directory '/' already present!
10338 01:20:53.867017 <3>[ 2.084648] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10339 01:20:53.879508 <6>[ 2.100475] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10340 01:20:53.887239 <6>[ 2.107481] xhci-mtk 11200000.usb: xHCI Host Controller
10341 01:20:53.893406 <6>[ 2.112986] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10342 01:20:53.903377 <6>[ 2.120821] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10343 01:20:53.910570 <6>[ 2.130242] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10344 01:20:53.917002 <6>[ 2.136316] xhci-mtk 11200000.usb: xHCI Host Controller
10345 01:20:53.923460 <6>[ 2.141791] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10346 01:20:53.930164 <6>[ 2.149435] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10347 01:20:53.936383 <6>[ 2.157014] hub 1-0:1.0: USB hub found
10348 01:20:53.940130 <6>[ 2.161023] hub 1-0:1.0: 1 port detected
10349 01:20:53.946603 <6>[ 2.165274] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10350 01:20:53.953108 <6>[ 2.173759] hub 2-0:1.0: USB hub found
10351 01:20:53.956140 <6>[ 2.177762] hub 2-0:1.0: 1 port detected
10352 01:20:53.963612 <6>[ 2.184435] mtk-msdc 11f70000.mmc: Got CD GPIO
10353 01:20:53.973911 <6>[ 2.191477] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10354 01:20:53.980599 <6>[ 2.199501] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10355 01:20:53.990705 <4>[ 2.207389] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10356 01:20:54.000214 <6>[ 2.216909] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10357 01:20:54.007008 <6>[ 2.224985] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10358 01:20:54.013747 <6>[ 2.233072] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10359 01:20:54.023930 <6>[ 2.240999] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10360 01:20:54.030112 <6>[ 2.248815] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10361 01:20:54.040012 <6>[ 2.256630] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10362 01:20:54.049993 <6>[ 2.267027] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10363 01:20:54.057103 <6>[ 2.275409] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10364 01:20:54.066282 <6>[ 2.283750] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10365 01:20:54.073409 <6>[ 2.292088] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10366 01:20:54.082913 <6>[ 2.300425] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10367 01:20:54.089478 <6>[ 2.308764] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10368 01:20:54.099613 <6>[ 2.317101] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10369 01:20:54.109640 <6>[ 2.325439] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10370 01:20:54.116151 <6>[ 2.333776] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10371 01:20:54.126434 <6>[ 2.342113] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10372 01:20:54.132322 <6>[ 2.350450] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10373 01:20:54.142584 <6>[ 2.358787] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10374 01:20:54.149217 <6>[ 2.367136] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10375 01:20:54.159082 <6>[ 2.375474] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10376 01:20:54.166054 <6>[ 2.383810] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10377 01:20:54.172135 <6>[ 2.392568] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10378 01:20:54.179022 <6>[ 2.399708] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10379 01:20:54.185426 <6>[ 2.406443] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10380 01:20:54.195788 <6>[ 2.413179] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10381 01:20:54.202350 <6>[ 2.420081] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10382 01:20:54.209097 <6>[ 2.426918] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10383 01:20:54.218727 <6>[ 2.436050] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10384 01:20:54.228937 <6>[ 2.445169] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10385 01:20:54.238907 <6>[ 2.454461] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10386 01:20:54.248808 <6>[ 2.463928] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10387 01:20:54.255364 <6>[ 2.473393] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10388 01:20:54.265160 <6>[ 2.482511] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10389 01:20:54.275129 <6>[ 2.491980] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10390 01:20:54.284786 <6>[ 2.501120] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10391 01:20:54.294669 <6>[ 2.510415] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10392 01:20:54.304359 <6>[ 2.520574] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10393 01:20:54.314659 <6>[ 2.532001] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10394 01:20:54.321208 <6>[ 2.541533] Trying to probe devices needed for running init ...
10395 01:20:54.346960 <6>[ 2.564557] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10396 01:20:54.375084 <6>[ 2.595970] hub 2-1:1.0: USB hub found
10397 01:20:54.379029 <6>[ 2.600427] hub 2-1:1.0: 3 ports detected
10398 01:20:54.386757 <6>[ 2.607656] hub 2-1:1.0: USB hub found
10399 01:20:54.390187 <6>[ 2.611995] hub 2-1:1.0: 3 ports detected
10400 01:20:54.498850 <6>[ 2.716471] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10401 01:20:54.653733 <6>[ 2.874432] hub 1-1:1.0: USB hub found
10402 01:20:54.656950 <6>[ 2.878920] hub 1-1:1.0: 4 ports detected
10403 01:20:54.666671 <6>[ 2.887451] hub 1-1:1.0: USB hub found
10404 01:20:54.669963 <6>[ 2.891797] hub 1-1:1.0: 4 ports detected
10405 01:20:54.739112 <6>[ 2.956680] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10406 01:20:54.990879 <6>[ 3.208529] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10407 01:20:55.123643 <6>[ 3.344406] hub 1-1.4:1.0: USB hub found
10408 01:20:55.126895 <6>[ 3.349082] hub 1-1.4:1.0: 2 ports detected
10409 01:20:55.136425 <6>[ 3.357197] hub 1-1.4:1.0: USB hub found
10410 01:20:55.139434 <6>[ 3.361802] hub 1-1.4:1.0: 2 ports detected
10411 01:20:55.435248 <6>[ 3.652529] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10412 01:20:55.627066 <6>[ 3.844524] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10413 01:21:06.604336 <6>[ 14.829864] ALSA device list:
10414 01:21:06.610990 <6>[ 14.833153] No soundcards found.
10415 01:21:06.618435 <6>[ 14.840498] Freeing unused kernel memory: 8448K
10416 01:21:06.622062 <6>[ 14.845490] Run /init as init process
10417 01:21:06.631620 Loading, please wait...
10418 01:21:06.657850 Starting systemd-udevd version 252.22-1~deb12u1
10419 01:21:06.658499
10420 01:21:06.861791 <6>[ 15.080520] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10421 01:21:06.870503 <6>[ 15.092638] remoteproc remoteproc0: scp is available
10422 01:21:06.877092 <6>[ 15.098140] remoteproc remoteproc0: powering up scp
10423 01:21:06.884249 <6>[ 15.103289] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10424 01:21:06.893577 <3>[ 15.107124] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10425 01:21:06.896920 <6>[ 15.111806] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10426 01:21:06.906636 <3>[ 15.119968] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10427 01:21:06.913101 <3>[ 15.133557] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10428 01:21:06.924328 <4>[ 15.143091] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10429 01:21:06.930707 <6>[ 15.143476] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10430 01:21:06.940717 <6>[ 15.158076] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10431 01:21:06.947545 <3>[ 15.158088] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10432 01:21:06.953691 <4>[ 15.158163] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10433 01:21:06.960952 <6>[ 15.158878] usbcore: registered new device driver r8152-cfgselector
10434 01:21:06.970301 <6>[ 15.164842] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10435 01:21:06.977464 <6>[ 15.166811] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10436 01:21:06.983957 <6>[ 15.171462] mc: Linux media interface: v0.10
10437 01:21:06.990206 <3>[ 15.174870] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10438 01:21:06.996985 <6>[ 15.189834] videodev: Linux video capture interface: v2.00
10439 01:21:07.003576 <3>[ 15.196332] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10440 01:21:07.014165 <3>[ 15.196354] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10441 01:21:07.021001 <3>[ 15.196360] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10442 01:21:07.027137 <3>[ 15.197123] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10443 01:21:07.037468 <4>[ 15.214056] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10444 01:21:07.043996 <4>[ 15.214056] Fallback method does not support PEC.
10445 01:21:07.050603 <3>[ 15.218081] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10446 01:21:07.060501 <3>[ 15.239722] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10447 01:21:07.066949 <3>[ 15.240018] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10448 01:21:07.073582 <6>[ 15.250892] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10449 01:21:07.083606 <6>[ 15.250922] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10450 01:21:07.090077 <6>[ 15.250929] remoteproc remoteproc0: remote processor scp is now up
10451 01:21:07.097110 <3>[ 15.256031] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10452 01:21:07.106903 <3>[ 15.256113] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10453 01:21:07.113675 <3>[ 15.256117] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10454 01:21:07.123195 <3>[ 15.256119] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10455 01:21:07.129778 <3>[ 15.256125] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10456 01:21:07.139840 <3>[ 15.256128] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10457 01:21:07.146392 <3>[ 15.256146] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10458 01:21:07.152903 <6>[ 15.301934] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10459 01:21:07.163013 <6>[ 15.305759] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10460 01:21:07.166510 <6>[ 15.305767] pci_bus 0000:00: root bus resource [bus 00-ff]
10461 01:21:07.172777 <6>[ 15.305777] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10462 01:21:07.182500 <6>[ 15.305782] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10463 01:21:07.189564 <6>[ 15.305822] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10464 01:21:07.199236 <6>[ 15.305848] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10465 01:21:07.202636 <6>[ 15.305950] pci 0000:00:00.0: supports D1 D2
10466 01:21:07.209365 <6>[ 15.305954] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10467 01:21:07.219037 <6>[ 15.307542] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10468 01:21:07.222622 <6>[ 15.307653] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10469 01:21:07.232393 <6>[ 15.307683] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10470 01:21:07.239148 <6>[ 15.307703] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10471 01:21:07.245618 <6>[ 15.307722] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10472 01:21:07.252890 <6>[ 15.307834] pci 0000:01:00.0: supports D1 D2
10473 01:21:07.256355 <6>[ 15.307837] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10474 01:21:07.265899 <6>[ 15.312066] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10475 01:21:07.275922 <6>[ 15.312490] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10476 01:21:07.282710 <6>[ 15.317028] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10477 01:21:07.292700 <6>[ 15.325651] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10478 01:21:07.302264 <6>[ 15.326563] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10479 01:21:07.309029 <6>[ 15.333095] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10480 01:21:07.318938 <4>[ 15.353105] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10481 01:21:07.325310 <6>[ 15.357389] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10482 01:21:07.335401 <6>[ 15.359791] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10483 01:21:07.341976 <4>[ 15.365461] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10484 01:21:07.351911 <6>[ 15.373536] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10485 01:21:07.355399 <6>[ 15.382373] Bluetooth: Core ver 2.22
10486 01:21:07.361462 <6>[ 15.388748] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10487 01:21:07.368509 <6>[ 15.411577] NET: Registered PF_BLUETOOTH protocol family
10488 01:21:07.374764 <6>[ 15.417775] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10489 01:21:07.381852 <6>[ 15.425232] Bluetooth: HCI device and connection manager initialized
10490 01:21:07.388158 <6>[ 15.425257] Bluetooth: HCI socket layer initialized
10491 01:21:07.391426 <6>[ 15.429769] pci 0000:00:00.0: PCI bridge to [bus 01]
10492 01:21:07.401226 <6>[ 15.430642] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10493 01:21:07.411290 <6>[ 15.431908] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10494 01:21:07.417933 <6>[ 15.432093] usbcore: registered new interface driver uvcvideo
10495 01:21:07.424386 <6>[ 15.436621] Bluetooth: L2CAP socket layer initialized
10496 01:21:07.428046 <6>[ 15.440360] r8152 2-1.3:1.0 eth0: v1.12.13
10497 01:21:07.434359 <6>[ 15.440426] usbcore: registered new interface driver r8152
10498 01:21:07.441035 <6>[ 15.444873] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10499 01:21:07.447508 <6>[ 15.451129] Bluetooth: SCO socket layer initialized
10500 01:21:07.454202 <6>[ 15.458766] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10501 01:21:07.461266 <6>[ 15.466819] usbcore: registered new interface driver cdc_ether
10502 01:21:07.464102 <6>[ 15.474599] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10503 01:21:07.470480 <6>[ 15.474700] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10504 01:21:07.480592 <3>[ 15.480443] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10505 01:21:07.487028 <6>[ 15.485392] usbcore: registered new interface driver r8153_ecm
10506 01:21:07.493949 <6>[ 15.485879] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10507 01:21:07.500561 <5>[ 15.497565] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10508 01:21:07.507220 <6>[ 15.511807] usbcore: registered new interface driver btusb
10509 01:21:07.513931 <6>[ 15.512848] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10510 01:21:07.523601 <4>[ 15.512859] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10511 01:21:07.530073 <3>[ 15.512874] Bluetooth: hci0: Failed to load firmware file (-2)
10512 01:21:07.533664 <3>[ 15.512882] Bluetooth: hci0: Failed to set up firmware (-2)
10513 01:21:07.546728 <4>[ 15.512888] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10514 01:21:07.553301 <5>[ 15.534688] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10515 01:21:07.560201 <5>[ 15.779678] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10516 01:21:07.570795 <4>[ 15.788126] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10517 01:21:07.573056 <6>[ 15.797003] cfg80211: failed to load regulatory.db
10518 01:21:07.614394 <6>[ 15.833439] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10519 01:21:07.621127 <6>[ 15.840932] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10520 01:21:07.645113 <6>[ 15.867592] mt7921e 0000:01:00.0: ASIC revision: 79610010
10521 01:21:07.748677 <6>[ 15.967728] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10522 01:21:07.751676 <6>[ 15.967728]
10523 01:21:07.760735 Begin: Loading essential drivers ... done.
10524 01:21:07.763935 Begin: Running /scripts/init-premount ... done.
10525 01:21:07.770761 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10526 01:21:07.780344 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10527 01:21:07.783184 Device /sys/class/net/enx00e04c6803bd found
10528 01:21:07.783670 done.
10529 01:21:07.789845 Begin: Waiting up to 180 secs for any network device to become available ... done.
10530 01:21:07.845512 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10531 01:21:08.018596 <6>[ 16.237917] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10532 01:21:08.804022 <6>[ 17.026522] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10533 01:21:08.881867 <6>[ 17.104425] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10534 01:21:08.979144 IP-Config: no response after 2 secs - giving up
10535 01:21:09.017319 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10536 01:21:09.030381 IP-Config: wlp1s0 hardware address 74:4c:a1:92:35:3b mtu 1500 DHCP
10537 01:21:09.711403 IP-Config: enx00e04c6803bd complete (dhcp from 192.168.201.1):
10538 01:21:09.718077 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10539 01:21:09.724949 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10540 01:21:09.731052 host : mt8192-asurada-spherion-r0-cbg-4
10541 01:21:09.738055 domain : lava-rack
10542 01:21:09.744116 rootserver: 192.168.201.1 rootpath:
10543 01:21:09.744618 filename :
10544 01:21:09.805373 done.
10545 01:21:09.814018 Begin: Running /scripts/nfs-bottom ... done.
10546 01:21:09.835705 Begin: Running /scripts/init-bottom ... done.
10547 01:21:11.190297 <6>[ 19.413023] NET: Registered PF_INET6 protocol family
10548 01:21:11.198004 <6>[ 19.420693] Segment Routing with IPv6
10549 01:21:11.200939 <6>[ 19.424695] In-situ OAM (IOAM) with IPv6
10550 01:21:11.377331 <30>[ 19.573417] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10551 01:21:11.383832 <30>[ 19.606581] systemd[1]: Detected architecture arm64.
10552 01:21:11.393154
10553 01:21:11.396239 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10554 01:21:11.396806
10555 01:21:11.397180
10556 01:21:11.419458 <30>[ 19.642458] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10557 01:21:12.571125 <30>[ 20.790830] systemd[1]: Queued start job for default target graphical.target.
10558 01:21:12.618234 <30>[ 20.837509] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10559 01:21:12.624272 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10560 01:21:12.624839
10561 01:21:12.646642 <30>[ 20.866274] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10562 01:21:12.656804 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10563 01:21:12.657381
10564 01:21:12.674900 <30>[ 20.894304] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10565 01:21:12.685159 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10566 01:21:12.685731
10567 01:21:12.702148 <30>[ 20.921918] systemd[1]: Created slice user.slice - User and Session Slice.
10568 01:21:12.708851 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10569 01:21:12.709413
10570 01:21:12.732598 <30>[ 20.948852] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10571 01:21:12.739299 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10572 01:21:12.739868
10573 01:21:12.760357 <30>[ 20.976766] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10574 01:21:12.767151 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10575 01:21:12.767720
10576 01:21:12.794984 <30>[ 21.004701] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10577 01:21:12.805088 <30>[ 21.024516] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10578 01:21:12.811076 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10579 01:21:12.811544
10580 01:21:12.828987 <30>[ 21.048502] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10581 01:21:12.835615 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10582 01:21:12.836481
10583 01:21:12.853154 <30>[ 21.072558] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10584 01:21:12.862628 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10585 01:21:12.863195
10586 01:21:12.877738 <30>[ 21.100594] systemd[1]: Reached target paths.target - Path Units.
10587 01:21:12.884480 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10588 01:21:12.885043
10589 01:21:12.906118 <30>[ 21.124942] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10590 01:21:12.912214 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10591 01:21:12.912780
10592 01:21:12.925565 <30>[ 21.148502] systemd[1]: Reached target slices.target - Slice Units.
10593 01:21:12.935478 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10594 01:21:12.936030
10595 01:21:12.950184 <30>[ 21.173011] systemd[1]: Reached target swap.target - Swaps.
10596 01:21:12.956982 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10597 01:21:12.957542
10598 01:21:12.977722 <30>[ 21.197002] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10599 01:21:12.987055 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10600 01:21:12.987622
10601 01:21:13.005358 <30>[ 21.224998] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10602 01:21:13.015126 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10603 01:21:13.015781
10604 01:21:13.036365 <30>[ 21.255909] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10605 01:21:13.045861 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10606 01:21:13.046468
10607 01:21:13.062642 <30>[ 21.281991] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10608 01:21:13.071965 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10609 01:21:13.072540
10610 01:21:13.089574 <30>[ 21.309163] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10611 01:21:13.095868 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10612 01:21:13.096463
10613 01:21:13.114875 <30>[ 21.334093] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10614 01:21:13.124502 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10615 01:21:13.125073
10616 01:21:13.144267 <30>[ 21.363575] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10617 01:21:13.154051 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10618 01:21:13.154643
10619 01:21:13.169396 <30>[ 21.388972] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10620 01:21:13.179281 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10621 01:21:13.179853
10622 01:21:13.220975 <30>[ 21.440576] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10623 01:21:13.227529 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10624 01:21:13.228000
10625 01:21:13.249778 <30>[ 21.469359] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10626 01:21:13.256072 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10627 01:21:13.256627
10628 01:21:13.304758 <30>[ 21.524954] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10629 01:21:13.311503 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10630 01:21:13.311651
10631 01:21:13.340153 <30>[ 21.553189] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10632 01:21:13.355653 <30>[ 21.575303] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10633 01:21:13.365388 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10634 01:21:13.365960
10635 01:21:13.386243 <30>[ 21.605953] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10636 01:21:13.393091 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10637 01:21:13.393565
10638 01:21:13.419120 <30>[ 21.638367] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10639 01:21:13.425230 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10640 01:21:13.425763
10641 01:21:13.450581 <30>[ 21.670411] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10642 01:21:13.460697 Starting [0;1;39mmodpr<6>[ 21.680555] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10643 01:21:13.466898 obe@drm.service[0m - Load Kernel Module drm...
10644 01:21:13.467370
10645 01:21:13.513794 <30>[ 21.733412] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10646 01:21:13.523301 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10647 01:21:13.523785
10648 01:21:13.546471 <30>[ 21.766176] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10649 01:21:13.553030 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10650 01:21:13.553504
10651 01:21:13.579336 <30>[ 21.799290] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10652 01:21:13.589481 Starting [0;1;39mmodprobe@loop.ser…e<6>[ 21.812274] fuse: init (API version 7.37)
10653 01:21:13.592955 [0m - Load Kernel Module loop...
10654 01:21:13.593518
10655 01:21:13.657685 <30>[ 21.877356] systemd[1]: Starting systemd-journald.service - Journal Service...
10656 01:21:13.664393 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10657 01:21:13.665011
10658 01:21:13.697934 <30>[ 21.917951] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10659 01:21:13.704795 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10660 01:21:13.705286
10661 01:21:13.733705 <30>[ 21.950211] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10662 01:21:13.740234 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10663 01:21:13.740715
10664 01:21:13.765939 <30>[ 21.986386] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10665 01:21:13.776190 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10666 01:21:13.776298
10667 01:21:13.797639 <30>[ 22.017788] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10668 01:21:13.804154 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10669 01:21:13.804364
10670 01:21:13.834777 <30>[ 22.054575] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10671 01:21:13.841911 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10672 01:21:13.842475
10673 01:21:13.851597 <3>[ 22.071362] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10674 01:21:13.861101 <30>[ 22.081395] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10675 01:21:13.868379 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10676 01:21:13.868463
10677 01:21:13.889033 <30>[ 22.108912] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10678 01:21:13.895555 <3>[ 22.111276] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10679 01:21:13.906003 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10680 01:21:13.906153
10681 01:21:13.926400 <30>[ 22.145662] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10682 01:21:13.936861 <3>[ 22.152183] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10683 01:21:13.943179 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10684 01:21:13.943372
10685 01:21:13.962384 <30>[ 22.181976] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10686 01:21:13.969349 <3>[ 22.186244] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10687 01:21:13.979188 <30>[ 22.189835] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10688 01:21:13.985759 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10689 01:21:13.986300
10690 01:21:13.999391 <3>[ 22.219280] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10691 01:21:14.009779 <30>[ 22.229756] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10692 01:21:14.016923 <30>[ 22.237690] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10693 01:21:14.033827 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Mo<3>[ 22.251750] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10694 01:21:14.034467 dule dm_mod.
10695 01:21:14.034843
10696 01:21:14.051074 <30>[ 22.273796] systemd[1]: modprobe@drm.service: Deactivated successfully.
10697 01:21:14.061716 <30>[ 22.281321] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10698 01:21:14.068568 <3>[ 22.283655] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10699 01:21:14.078550 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10700 01:21:14.079115
10701 01:21:14.099127 <30>[ 22.318578] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10702 01:21:14.105778 <3>[ 22.322535] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10703 01:21:14.115926 <30>[ 22.326872] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10704 01:21:14.125680 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10705 01:21:14.126392
10706 01:21:14.141951 <30>[ 22.361486] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10707 01:21:14.148668 <3>[ 22.368273] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10708 01:21:14.158674 <30>[ 22.369252] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10709 01:21:14.165445 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10710 01:21:14.166013
10711 01:21:14.186076 <30>[ 22.405540] systemd[1]: modprobe@loop.service: Deactivated successfully.
10712 01:21:14.193324 <30>[ 22.413098] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10713 01:21:14.206720 [[0;32m OK [0m] Finished [0;1;39mmodprobe@l<3>[ 22.424138] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10714 01:21:14.223316 <4>[ 22.425146] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10715 01:21:14.230453 <3>[ 22.449678] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10716 01:21:14.233484 oop.service[0m - Load Kernel Module loop.
10717 01:21:14.234105
10718 01:21:14.252761 <30>[ 22.471970] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10719 01:21:14.259237 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10720 01:21:14.259792
10721 01:21:14.285080 <30>[ 22.501543] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10722 01:21:14.291511 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10723 01:21:14.292085
10724 01:21:14.309113 <30>[ 22.528969] systemd[1]: Started systemd-journald.service - Journal Service.
10725 01:21:14.316071 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10726 01:21:14.316654
10727 01:21:14.337338 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10728 01:21:14.337933
10729 01:21:14.354413 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10730 01:21:14.354986
10731 01:21:14.375689 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10732 01:21:14.376261
10733 01:21:14.433243 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10734 01:21:14.433833
10735 01:21:14.458083 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10736 01:21:14.458675
10737 01:21:14.482359 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10738 01:21:14.482939
10739 01:21:14.505758 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10740 01:21:14.505841
10741 01:21:14.541387 <46>[ 22.761887] systemd-journald[305]: Received client request to flush runtime journal.
10742 01:21:14.553578 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10743 01:21:14.553810
10744 01:21:14.580310 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10745 01:21:14.580823
10746 01:21:14.866705 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10747 01:21:14.866855
10748 01:21:14.889230 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10749 01:21:14.889315
10750 01:21:14.909394 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10751 01:21:14.909478
10752 01:21:15.317335 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10753 01:21:15.317483
10754 01:21:15.986735 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10755 01:21:15.986882
10756 01:21:16.010604 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10757 01:21:16.010793
10758 01:21:16.065846 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10759 01:21:16.066468
10760 01:21:16.155350 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10761 01:21:16.155933
10762 01:21:16.173304 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10763 01:21:16.173885
10764 01:21:16.192893 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10765 01:21:16.193474
10766 01:21:16.237412 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10767 01:21:16.237976
10768 01:21:16.268225 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10769 01:21:16.268698
10770 01:21:16.470872 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10771 01:21:16.471015
10772 01:21:16.526240 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10773 01:21:16.526687
10774 01:21:16.621647 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10775 01:21:16.621865
10776 01:21:16.852000 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10777 01:21:16.852493
10778 01:21:16.881542 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10779 01:21:16.881975
10780 01:21:16.926850 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10781 01:21:16.927295
10782 01:21:17.065357 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10783 01:21:17.065922
10784 01:21:17.076692 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10785 01:21:17.076857
10786 01:21:17.097697 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10787 01:21:17.097793
10788 01:21:17.153381 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10789 01:21:17.153523
10790 01:21:17.223086 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10791 01:21:17.223639
10792 01:21:17.238080 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10793 01:21:17.238620
10794 01:21:17.256702 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10795 01:21:17.257250
10796 01:21:17.273931 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10797 01:21:17.274563
10798 01:21:17.330119 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10799 01:21:17.330671
10800 01:21:17.352362 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10801 01:21:17.352814
10802 01:21:17.373104 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10803 01:21:17.373666
10804 01:21:17.392558 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10805 01:21:17.393135
10806 01:21:17.408351 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10807 01:21:17.408923
10808 01:21:17.432428 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10809 01:21:17.432984
10810 01:21:17.476078 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10811 01:21:17.476650
10812 01:21:17.492801 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10813 01:21:17.493378
10814 01:21:17.512666 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10815 01:21:17.513258
10816 01:21:17.532814 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10817 01:21:17.533389
10818 01:21:17.548734 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10819 01:21:17.549325
10820 01:21:17.568226 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10821 01:21:17.568804
10822 01:21:17.584361 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10823 01:21:17.584925
10824 01:21:17.600742 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10825 01:21:17.601323
10826 01:21:17.645976 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10827 01:21:17.646586
10828 01:21:17.679261 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10829 01:21:17.679737
10830 01:21:17.761085 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10831 01:21:17.761588
10832 01:21:17.786311 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10833 01:21:17.786424
10834 01:21:17.809982 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10835 01:21:17.810117
10836 01:21:17.976568 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10837 01:21:17.976722
10838 01:21:18.000498 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10839 01:21:18.000638
10840 01:21:18.065797 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10841 01:21:18.066314
10842 01:21:18.085307 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10843 01:21:18.085790
10844 01:21:18.104753 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10845 01:21:18.105556
10846 01:21:18.121093 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10847 01:21:18.121662
10848 01:21:18.153421 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10849 01:21:18.153994
10850 01:21:18.185005 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10851 01:21:18.185583
10852 01:21:18.201608 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10853 01:21:18.202561
10854 01:21:18.251352 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
10855 01:21:18.251910
10856 01:21:18.276714 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10857 01:21:18.277360
10858 01:21:18.332200 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10859 01:21:18.332797
10860 01:21:18.356170 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
10861 01:21:18.356730
10862 01:21:18.429586
10863 01:21:18.430191
10864 01:21:18.432939 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10865 01:21:18.433406
10866 01:21:18.436154 debian-bookworm-arm64 login: root (automatic login)
10867 01:21:18.436621
10868 01:21:18.437010
10869 01:21:18.737625 Linux debian-bookworm-arm64 6.1.86-cip19 #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024 aarch64
10870 01:21:18.738232
10871 01:21:18.744671 The programs included with the Debian GNU/Linux system are free software;
10872 01:21:18.751097 the exact distribution terms for each program are described in the
10873 01:21:18.754179 individual files in /usr/share/doc/*/copyright.
10874 01:21:18.754644
10875 01:21:18.760809 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10876 01:21:18.764083 permitted by applicable law.
10877 01:21:19.755128 Matched prompt #10: / #
10879 01:21:19.756392 Setting prompt string to ['/ #']
10880 01:21:19.756868 end: 2.2.5.1 login-action (duration 00:00:29) [common]
10882 01:21:19.757946 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
10883 01:21:19.758495 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
10884 01:21:19.758895 Setting prompt string to ['/ #']
10885 01:21:19.759241 Forcing a shell prompt, looking for ['/ #']
10887 01:21:19.809857 / #
10888 01:21:19.810290 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10889 01:21:19.810537 Waiting using forced prompt support (timeout 00:02:30)
10890 01:21:19.816106
10891 01:21:19.816901 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10892 01:21:19.817366 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
10894 01:21:19.918639 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13468762/extract-nfsrootfs-yac1dttm'
10895 01:21:19.925021 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13468762/extract-nfsrootfs-yac1dttm'
10897 01:21:20.026845 / # export NFS_SERVER_IP='192.168.201.1'
10898 01:21:20.033145 export NFS_SERVER_IP='192.168.201.1'
10899 01:21:20.034142 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10900 01:21:20.034688 end: 2.2 depthcharge-retry (duration 00:01:26) [common]
10901 01:21:20.035175 end: 2 depthcharge-action (duration 00:01:26) [common]
10902 01:21:20.035688 start: 3 lava-test-retry (timeout 00:07:55) [common]
10903 01:21:20.036183 start: 3.1 lava-test-shell (timeout 00:07:55) [common]
10904 01:21:20.036593 Using namespace: common
10906 01:21:20.137771 / # #
10907 01:21:20.138451 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10908 01:21:20.144626 #
10909 01:21:20.145510 Using /lava-13468762
10911 01:21:20.246851 / # export SHELL=/bin/bash
10912 01:21:20.253300 export SHELL=/bin/bash
10914 01:21:20.355055 / # . /lava-13468762/environment
10915 01:21:20.361740 . /lava-13468762/environment
10917 01:21:20.469230 / # /lava-13468762/bin/lava-test-runner /lava-13468762/0
10918 01:21:20.469866 Test shell timeout: 10s (minimum of the action and connection timeout)
10919 01:21:20.475715 /lava-13468762/bin/lava-test-runner /lava-13468762/0
10920 01:21:20.732000 + export TESTRUN_ID=0_timesync-off
10921 01:21:20.735211 + TESTRUN_ID=0_timesync-off
10922 01:21:20.738735 + cd /lava-13468762/0/tests/0_timesync-off
10923 01:21:20.742191 ++ cat uuid
10924 01:21:20.746785 + UUID=13468762_1.6.2.3.1
10925 01:21:20.747251 + set +x
10926 01:21:20.753638 <LAVA_SIGNAL_STARTRUN 0_timesync-off 13468762_1.6.2.3.1>
10927 01:21:20.754564 Received signal: <STARTRUN> 0_timesync-off 13468762_1.6.2.3.1
10928 01:21:20.754982 Starting test lava.0_timesync-off (13468762_1.6.2.3.1)
10929 01:21:20.755435 Skipping test definition patterns.
10930 01:21:20.756743 + systemctl stop systemd-timesyncd
10931 01:21:20.832105 + set +x
10932 01:21:20.835590 <LAVA_SIGNAL_ENDRUN 0_timesync-off 13468762_1.6.2.3.1>
10933 01:21:20.836321 Received signal: <ENDRUN> 0_timesync-off 13468762_1.6.2.3.1
10934 01:21:20.836782 Ending use of test pattern.
10935 01:21:20.837174 Ending test lava.0_timesync-off (13468762_1.6.2.3.1), duration 0.08
10937 01:21:20.900052 + export TESTRUN_ID=1_kselftest-rtc
10938 01:21:20.903125 + TESTRUN_ID=1_kselftest-rtc
10939 01:21:20.906301 + cd /lava-13468762/0/tests/1_kselftest-rtc
10940 01:21:20.909398 ++ cat uuid
10941 01:21:20.913972 + UUID=13468762_1.6.2.3.5
10942 01:21:20.914483 + set +x
10943 01:21:20.920412 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 13468762_1.6.2.3.5>
10944 01:21:20.921158 Received signal: <STARTRUN> 1_kselftest-rtc 13468762_1.6.2.3.5
10945 01:21:20.921576 Starting test lava.1_kselftest-rtc (13468762_1.6.2.3.5)
10946 01:21:20.921953 Skipping test definition patterns.
10947 01:21:20.923885 + cd ./automated/linux/kselftest/
10948 01:21:20.950218 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10949 01:21:20.991832 INFO: install_deps skipped
10950 01:21:21.497626 --2024-04-23 01:21:21-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10951 01:21:21.504371 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10952 01:21:21.628344 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10953 01:21:21.755591 HTTP request sent, awaiting response... 200 OK
10954 01:21:21.758620 Length: 1651524 (1.6M) [application/octet-stream]
10955 01:21:21.762267 Saving to: 'kselftest_armhf.tar.gz'
10956 01:21:21.762837
10957 01:21:21.763212
10958 01:21:22.009505 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
10959 01:21:22.264117 kselftest_armhf.tar 2%[ ] 47.81K 188KB/s
10960 01:21:22.564938 kselftest_armhf.tar 13%[=> ] 218.91K 431KB/s
10961 01:21:22.693264 kselftest_armhf.tar 49%[========> ] 804.33K 993KB/s
10962 01:21:22.699855 kselftest_armhf.tar 100%[===================>] 1.57M 1.68MB/s in 0.9s
10963 01:21:22.700326
10964 01:21:22.850680 2024-04-23 01:21:22 (1.68 MB/s) - 'kselftest_armhf.tar.gz' saved [1651524/1651524]
10965 01:21:22.851109
10966 01:21:27.396785 skiplist:
10967 01:21:27.400126 ========================================
10968 01:21:27.403765 ========================================
10969 01:21:27.451757 rtc:rtctest
10970 01:21:27.472757 ============== Tests to run ===============
10971 01:21:27.477020 rtc:rtctest
10972 01:21:27.480160 ===========End Tests to run ===============
10973 01:21:27.483825 shardfile-rtc pass
10974 01:21:27.586666 <12>[ 35.811479] kselftest: Running tests in rtc
10975 01:21:27.596913 TAP version 13
10976 01:21:27.612710 1..1
10977 01:21:27.643534 # selftests: rtc: rtctest
10978 01:21:28.099887 # TAP version 13
10979 01:21:28.100081 # 1..8
10980 01:21:28.103196 # # Starting 8 tests from 2 test cases.
10981 01:21:28.106572 # # RUN rtc.date_read ...
10982 01:21:28.112941 # # rtctest.c:49:date_read:Current RTC date/time is 23/04/2024 01:21:27.
10983 01:21:28.116678 # # OK rtc.date_read
10984 01:21:28.119514 # ok 1 rtc.date_read
10985 01:21:28.122912 # # RUN rtc.date_read_loop ...
10986 01:21:28.132841 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
10987 01:21:37.927255 <6>[ 46.156398] vpu: disabling
10988 01:21:37.930420 <6>[ 46.159493] vproc2: disabling
10989 01:21:37.933627 <6>[ 46.162813] vproc1: disabling
10990 01:21:37.937292 <6>[ 46.166371] vaud18: disabling
10991 01:21:37.944793 <6>[ 46.170201] vsram_others: disabling
10992 01:21:37.948012 <6>[ 46.174159] va09: disabling
10993 01:21:37.951331 <6>[ 46.177318] vsram_md: disabling
10994 01:21:37.954125 <6>[ 46.180904] Vgpu: disabling
10995 01:21:58.013725 # # rtctest.c:115:date_read_loop:Performed 2619 RTC time reads.
10996 01:21:58.017109 # # OK rtc.date_read_loop
10997 01:21:58.020003 # ok 2 rtc.date_read_loop
10998 01:21:58.023682 # # RUN rtc.uie_read ...
10999 01:22:00.993853 # # OK rtc.uie_read
11000 01:22:00.997256 # ok 3 rtc.uie_read
11001 01:22:01.000332 # # RUN rtc.uie_select ...
11002 01:22:03.993443 # # OK rtc.uie_select
11003 01:22:03.996785 # ok 4 rtc.uie_select
11004 01:22:03.999746 # # RUN rtc.alarm_alm_set ...
11005 01:22:04.006664 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 01:22:07.
11006 01:22:04.009888 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11007 01:22:04.016528 # # alarm_alm_set: Test terminated by assertion
11008 01:22:04.020190 # # FAIL rtc.alarm_alm_set
11009 01:22:04.022921 # not ok 5 rtc.alarm_alm_set
11010 01:22:04.026013 # # RUN rtc.alarm_wkalm_set ...
11011 01:22:04.032861 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 23/04/2024 01:22:07.
11012 01:22:06.995815 # # OK rtc.alarm_wkalm_set
11013 01:22:06.996375 # ok 6 rtc.alarm_wkalm_set
11014 01:22:07.002720 # # RUN rtc.alarm_alm_set_minute ...
11015 01:22:07.005617 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 01:23:00.
11016 01:22:07.013064 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11017 01:22:07.019353 # # alarm_alm_set_minute: Test terminated by assertion
11018 01:22:07.022432 # # FAIL rtc.alarm_alm_set_minute
11019 01:22:07.025631 # not ok 7 rtc.alarm_alm_set_minute
11020 01:22:07.029178 # # RUN rtc.alarm_wkalm_set_minute ...
11021 01:22:07.035773 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 23/04/2024 01:23:00.
11022 01:22:59.990091 # # OK rtc.alarm_wkalm_set_minute
11023 01:22:59.993033 # ok 8 rtc.alarm_wkalm_set_minute
11024 01:22:59.996447 # # FAILED: 6 / 8 tests passed.
11025 01:22:59.999810 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11026 01:23:00.003056 not ok 1 selftests: rtc: rtctest # exit=1
11027 01:23:01.511973 rtc_rtctest_rtc_date_read pass
11028 01:23:01.515064 rtc_rtctest_rtc_date_read_loop pass
11029 01:23:01.518569 rtc_rtctest_rtc_uie_read pass
11030 01:23:01.521761 rtc_rtctest_rtc_uie_select pass
11031 01:23:01.525326 rtc_rtctest_rtc_alarm_alm_set fail
11032 01:23:01.528497 rtc_rtctest_rtc_alarm_wkalm_set pass
11033 01:23:01.531888 rtc_rtctest_rtc_alarm_alm_set_minute fail
11034 01:23:01.535021 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11035 01:23:01.538378 rtc_rtctest fail
11036 01:23:01.587079 + ../../utils/send-to-lava.sh ./output/result.txt
11037 01:23:01.664281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11038 01:23:01.665080 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11040 01:23:01.721114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11041 01:23:01.721887 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11043 01:23:01.775877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11044 01:23:01.776659 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11046 01:23:01.819619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11047 01:23:01.820310 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11049 01:23:01.865235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11050 01:23:01.865927 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11052 01:23:01.922275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11053 01:23:01.922984 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11055 01:23:01.977997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11056 01:23:01.979035 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11058 01:23:02.029778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11059 01:23:02.030513 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11061 01:23:02.085058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11062 01:23:02.085881 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11064 01:23:02.131711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11065 01:23:02.132180 + set +x
11066 01:23:02.132814 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11068 01:23:02.138528 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 13468762_1.6.2.3.5>
11069 01:23:02.139259 Received signal: <ENDRUN> 1_kselftest-rtc 13468762_1.6.2.3.5
11070 01:23:02.139672 Ending use of test pattern.
11071 01:23:02.140025 Ending test lava.1_kselftest-rtc (13468762_1.6.2.3.5), duration 101.22
11073 01:23:02.141227 ok: lava_test_shell seems to have completed
11074 01:23:02.141970 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
11075 01:23:02.142459 end: 3.1 lava-test-shell (duration 00:01:42) [common]
11076 01:23:02.142924 end: 3 lava-test-retry (duration 00:01:42) [common]
11077 01:23:02.143401 start: 4 finalize (timeout 00:06:13) [common]
11078 01:23:02.143904 start: 4.1 power-off (timeout 00:00:30) [common]
11079 01:23:02.144733 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11080 01:23:02.267419 >> Command sent successfully.
11081 01:23:02.271392 Returned 0 in 0 seconds
11082 01:23:02.372228 end: 4.1 power-off (duration 00:00:00) [common]
11084 01:23:02.373792 start: 4.2 read-feedback (timeout 00:06:13) [common]
11086 01:23:02.376190 Listened to connection for namespace 'common' for up to 1s
11087 01:23:03.375918 Finalising connection for namespace 'common'
11088 01:23:03.376615 Disconnecting from shell: Finalise
11089 01:23:03.377073 / #
11090 01:23:03.478289 end: 4.2 read-feedback (duration 00:00:01) [common]
11091 01:23:03.478965 end: 4 finalize (duration 00:00:01) [common]
11092 01:23:03.479580 Cleaning after the job
11093 01:23:03.480122 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468762/tftp-deploy-p9xkn4mi/ramdisk
11094 01:23:03.490381 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468762/tftp-deploy-p9xkn4mi/kernel
11095 01:23:03.525612 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468762/tftp-deploy-p9xkn4mi/dtb
11096 01:23:03.525954 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468762/tftp-deploy-p9xkn4mi/nfsrootfs
11097 01:23:03.595540 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468762/tftp-deploy-p9xkn4mi/modules
11098 01:23:03.601191 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13468762
11099 01:23:04.146880 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13468762
11100 01:23:04.147062 Job finished correctly