Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 25
- Errors: 0
- Kernel Errors: 37
- Boot result: PASS
1 01:20:20.606403 lava-dispatcher, installed at version: 2024.01
2 01:20:20.606602 start: 0 validate
3 01:20:20.606731 Start time: 2024-04-23 01:20:20.606723+00:00 (UTC)
4 01:20:20.606858 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:20:20.606995 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:20:20.861720 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:20:20.861894 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:20:21.115458 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:20:21.115624 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:20:21.368733 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:20:21.368914 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:20:21.876070 Using caching service: 'http://localhost/cache/?uri=%s'
13 01:20:21.876251 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 01:20:22.136373 validate duration: 1.53
16 01:20:22.136626 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:20:22.136732 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:20:22.136821 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:20:22.136944 Not decompressing ramdisk as can be used compressed.
20 01:20:22.137030 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 01:20:22.137094 saving as /var/lib/lava/dispatcher/tmp/13468763/tftp-deploy-pagevbpx/ramdisk/initrd.cpio.gz
22 01:20:22.137160 total size: 5628169 (5 MB)
23 01:20:22.139036 progress 0 % (0 MB)
24 01:20:22.140818 progress 5 % (0 MB)
25 01:20:22.142612 progress 10 % (0 MB)
26 01:20:22.144125 progress 15 % (0 MB)
27 01:20:22.145722 progress 20 % (1 MB)
28 01:20:22.147195 progress 25 % (1 MB)
29 01:20:22.148783 progress 30 % (1 MB)
30 01:20:22.150383 progress 35 % (1 MB)
31 01:20:22.151762 progress 40 % (2 MB)
32 01:20:22.153343 progress 45 % (2 MB)
33 01:20:22.154763 progress 50 % (2 MB)
34 01:20:22.156278 progress 55 % (2 MB)
35 01:20:22.157874 progress 60 % (3 MB)
36 01:20:22.159283 progress 65 % (3 MB)
37 01:20:22.160951 progress 70 % (3 MB)
38 01:20:22.162342 progress 75 % (4 MB)
39 01:20:22.163851 progress 80 % (4 MB)
40 01:20:22.165235 progress 85 % (4 MB)
41 01:20:22.166816 progress 90 % (4 MB)
42 01:20:22.168327 progress 95 % (5 MB)
43 01:20:22.169786 progress 100 % (5 MB)
44 01:20:22.170071 5 MB downloaded in 0.03 s (163.09 MB/s)
45 01:20:22.170225 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:20:22.170503 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:20:22.170592 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:20:22.170678 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:20:22.170813 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 01:20:22.170886 saving as /var/lib/lava/dispatcher/tmp/13468763/tftp-deploy-pagevbpx/kernel/Image
52 01:20:22.170949 total size: 54352384 (51 MB)
53 01:20:22.171011 No compression specified
54 01:20:22.172204 progress 0 % (0 MB)
55 01:20:22.186614 progress 5 % (2 MB)
56 01:20:22.200522 progress 10 % (5 MB)
57 01:20:22.214363 progress 15 % (7 MB)
58 01:20:22.228092 progress 20 % (10 MB)
59 01:20:22.241849 progress 25 % (12 MB)
60 01:20:22.255635 progress 30 % (15 MB)
61 01:20:22.269433 progress 35 % (18 MB)
62 01:20:22.283428 progress 40 % (20 MB)
63 01:20:22.297386 progress 45 % (23 MB)
64 01:20:22.311215 progress 50 % (25 MB)
65 01:20:22.325128 progress 55 % (28 MB)
66 01:20:22.338969 progress 60 % (31 MB)
67 01:20:22.352744 progress 65 % (33 MB)
68 01:20:22.366664 progress 70 % (36 MB)
69 01:20:22.380528 progress 75 % (38 MB)
70 01:20:22.394211 progress 80 % (41 MB)
71 01:20:22.408240 progress 85 % (44 MB)
72 01:20:22.422166 progress 90 % (46 MB)
73 01:20:22.435782 progress 95 % (49 MB)
74 01:20:22.449221 progress 100 % (51 MB)
75 01:20:22.449479 51 MB downloaded in 0.28 s (186.10 MB/s)
76 01:20:22.449634 end: 1.2.1 http-download (duration 00:00:00) [common]
78 01:20:22.449876 end: 1.2 download-retry (duration 00:00:00) [common]
79 01:20:22.449964 start: 1.3 download-retry (timeout 00:10:00) [common]
80 01:20:22.450054 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 01:20:22.450190 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 01:20:22.450260 saving as /var/lib/lava/dispatcher/tmp/13468763/tftp-deploy-pagevbpx/dtb/mt8192-asurada-spherion-r0.dtb
83 01:20:22.450322 total size: 47230 (0 MB)
84 01:20:22.450384 No compression specified
85 01:20:22.451470 progress 69 % (0 MB)
86 01:20:22.451750 progress 100 % (0 MB)
87 01:20:22.451907 0 MB downloaded in 0.00 s (28.45 MB/s)
88 01:20:22.452031 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:20:22.452253 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:20:22.452339 start: 1.4 download-retry (timeout 00:10:00) [common]
92 01:20:22.452422 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 01:20:22.452532 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 01:20:22.452601 saving as /var/lib/lava/dispatcher/tmp/13468763/tftp-deploy-pagevbpx/nfsrootfs/full.rootfs.tar
95 01:20:22.452661 total size: 120894716 (115 MB)
96 01:20:22.452722 Using unxz to decompress xz
97 01:20:22.460565 progress 0 % (0 MB)
98 01:20:22.801969 progress 5 % (5 MB)
99 01:20:23.161245 progress 10 % (11 MB)
100 01:20:23.509557 progress 15 % (17 MB)
101 01:20:23.833708 progress 20 % (23 MB)
102 01:20:24.123689 progress 25 % (28 MB)
103 01:20:24.482318 progress 30 % (34 MB)
104 01:20:24.818628 progress 35 % (40 MB)
105 01:20:24.982077 progress 40 % (46 MB)
106 01:20:25.158766 progress 45 % (51 MB)
107 01:20:25.468585 progress 50 % (57 MB)
108 01:20:25.840875 progress 55 % (63 MB)
109 01:20:26.180738 progress 60 % (69 MB)
110 01:20:26.520144 progress 65 % (74 MB)
111 01:20:26.860428 progress 70 % (80 MB)
112 01:20:27.214785 progress 75 % (86 MB)
113 01:20:27.554103 progress 80 % (92 MB)
114 01:20:27.890234 progress 85 % (98 MB)
115 01:20:28.247431 progress 90 % (103 MB)
116 01:20:28.573339 progress 95 % (109 MB)
117 01:20:28.926260 progress 100 % (115 MB)
118 01:20:28.931526 115 MB downloaded in 6.48 s (17.80 MB/s)
119 01:20:28.931785 end: 1.4.1 http-download (duration 00:00:06) [common]
121 01:20:28.932088 end: 1.4 download-retry (duration 00:00:06) [common]
122 01:20:28.932192 start: 1.5 download-retry (timeout 00:09:53) [common]
123 01:20:28.932296 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 01:20:28.932463 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 01:20:28.932544 saving as /var/lib/lava/dispatcher/tmp/13468763/tftp-deploy-pagevbpx/modules/modules.tar
126 01:20:28.932627 total size: 8638160 (8 MB)
127 01:20:28.932732 Using unxz to decompress xz
128 01:20:28.937435 progress 0 % (0 MB)
129 01:20:28.956243 progress 5 % (0 MB)
130 01:20:28.980727 progress 10 % (0 MB)
131 01:20:29.004595 progress 15 % (1 MB)
132 01:20:29.027577 progress 20 % (1 MB)
133 01:20:29.051829 progress 25 % (2 MB)
134 01:20:29.077082 progress 30 % (2 MB)
135 01:20:29.100820 progress 35 % (2 MB)
136 01:20:29.125816 progress 40 % (3 MB)
137 01:20:29.149514 progress 45 % (3 MB)
138 01:20:29.174144 progress 50 % (4 MB)
139 01:20:29.198954 progress 55 % (4 MB)
140 01:20:29.227021 progress 60 % (4 MB)
141 01:20:29.252175 progress 65 % (5 MB)
142 01:20:29.277018 progress 70 % (5 MB)
143 01:20:29.300782 progress 75 % (6 MB)
144 01:20:29.325546 progress 80 % (6 MB)
145 01:20:29.353031 progress 85 % (7 MB)
146 01:20:29.378791 progress 90 % (7 MB)
147 01:20:29.407433 progress 95 % (7 MB)
148 01:20:29.433458 progress 100 % (8 MB)
149 01:20:29.439154 8 MB downloaded in 0.51 s (16.26 MB/s)
150 01:20:29.439400 end: 1.5.1 http-download (duration 00:00:01) [common]
152 01:20:29.439674 end: 1.5 download-retry (duration 00:00:01) [common]
153 01:20:29.439771 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 01:20:29.439866 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 01:20:33.244768 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13468763/extract-nfsrootfs-bow5lg9n
156 01:20:33.244957 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 01:20:33.245064 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 01:20:33.245235 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_
159 01:20:33.245709 makedir: /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin
160 01:20:33.245821 makedir: /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/tests
161 01:20:33.245923 makedir: /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/results
162 01:20:33.246026 Creating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-add-keys
163 01:20:33.246168 Creating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-add-sources
164 01:20:33.246301 Creating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-background-process-start
165 01:20:33.246429 Creating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-background-process-stop
166 01:20:33.246555 Creating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-common-functions
167 01:20:33.246678 Creating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-echo-ipv4
168 01:20:33.246808 Creating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-install-packages
169 01:20:33.246932 Creating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-installed-packages
170 01:20:33.247060 Creating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-os-build
171 01:20:33.247186 Creating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-probe-channel
172 01:20:33.247313 Creating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-probe-ip
173 01:20:33.247438 Creating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-target-ip
174 01:20:33.247562 Creating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-target-mac
175 01:20:33.247685 Creating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-target-storage
176 01:20:33.247812 Creating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-test-case
177 01:20:33.247942 Creating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-test-event
178 01:20:33.248065 Creating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-test-feedback
179 01:20:33.248188 Creating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-test-raise
180 01:20:33.248310 Creating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-test-reference
181 01:20:33.248440 Creating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-test-runner
182 01:20:33.248564 Creating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-test-set
183 01:20:33.248686 Creating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-test-shell
184 01:20:33.252242 Updating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-add-keys (debian)
185 01:20:33.252657 Updating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-add-sources (debian)
186 01:20:33.252996 Updating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-install-packages (debian)
187 01:20:33.253306 Updating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-installed-packages (debian)
188 01:20:33.253677 Updating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/bin/lava-os-build (debian)
189 01:20:33.254049 Creating /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/environment
190 01:20:33.254155 LAVA metadata
191 01:20:33.254227 - LAVA_JOB_ID=13468763
192 01:20:33.254293 - LAVA_DISPATCHER_IP=192.168.201.1
193 01:20:33.254397 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 01:20:33.254464 skipped lava-vland-overlay
195 01:20:33.254544 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 01:20:33.254624 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 01:20:33.254685 skipped lava-multinode-overlay
198 01:20:33.254757 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 01:20:33.254836 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 01:20:33.254910 Loading test definitions
201 01:20:33.254998 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 01:20:33.255076 Using /lava-13468763 at stage 0
203 01:20:33.255394 uuid=13468763_1.6.2.3.1 testdef=None
204 01:20:33.255483 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 01:20:33.255571 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 01:20:33.256022 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 01:20:33.256244 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 01:20:33.256799 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 01:20:33.257035 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 01:20:33.257613 runner path: /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/0/tests/0_timesync-off test_uuid 13468763_1.6.2.3.1
213 01:20:33.257771 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 01:20:33.257995 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 01:20:33.258071 Using /lava-13468763 at stage 0
217 01:20:33.258169 Fetching tests from https://github.com/kernelci/test-definitions.git
218 01:20:33.258256 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/0/tests/1_kselftest-tpm2'
219 01:20:36.861263 Running '/usr/bin/git checkout kernelci.org
220 01:20:37.020009 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 01:20:37.020976 uuid=13468763_1.6.2.3.5 testdef=None
222 01:20:37.021186 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 01:20:37.021485 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 01:20:37.022255 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 01:20:37.022496 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 01:20:37.023621 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 01:20:37.023872 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 01:20:37.024822 runner path: /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/0/tests/1_kselftest-tpm2 test_uuid 13468763_1.6.2.3.5
232 01:20:37.024917 BOARD='mt8192-asurada-spherion-r0'
233 01:20:37.024985 BRANCH='cip'
234 01:20:37.025046 SKIPFILE='/dev/null'
235 01:20:37.025106 SKIP_INSTALL='True'
236 01:20:37.025165 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 01:20:37.025225 TST_CASENAME=''
238 01:20:37.025281 TST_CMDFILES='tpm2'
239 01:20:37.025439 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 01:20:37.025653 Creating lava-test-runner.conf files
242 01:20:37.025727 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13468763/lava-overlay-jjrqc6y_/lava-13468763/0 for stage 0
243 01:20:37.025823 - 0_timesync-off
244 01:20:37.025908 - 1_kselftest-tpm2
245 01:20:37.026015 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 01:20:37.026129 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 01:20:44.639326 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 01:20:44.639481 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 01:20:44.639614 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 01:20:44.639744 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 01:20:44.639879 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 01:20:44.804589 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 01:20:44.805044 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 01:20:44.805200 extracting modules file /var/lib/lava/dispatcher/tmp/13468763/tftp-deploy-pagevbpx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13468763/extract-nfsrootfs-bow5lg9n
255 01:20:45.058012 extracting modules file /var/lib/lava/dispatcher/tmp/13468763/tftp-deploy-pagevbpx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13468763/extract-overlay-ramdisk-suefg8ge/ramdisk
256 01:20:45.279404 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 01:20:45.279573 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 01:20:45.279679 [common] Applying overlay to NFS
259 01:20:45.279752 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13468763/compress-overlay-wdu2kw3g/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13468763/extract-nfsrootfs-bow5lg9n
260 01:20:46.194682 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 01:20:46.194858 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 01:20:46.194958 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 01:20:46.195048 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 01:20:46.195138 Building ramdisk /var/lib/lava/dispatcher/tmp/13468763/extract-overlay-ramdisk-suefg8ge/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13468763/extract-overlay-ramdisk-suefg8ge/ramdisk
265 01:20:46.523969 >> 130624 blocks
266 01:20:48.506321 rename /var/lib/lava/dispatcher/tmp/13468763/extract-overlay-ramdisk-suefg8ge/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13468763/tftp-deploy-pagevbpx/ramdisk/ramdisk.cpio.gz
267 01:20:48.506776 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 01:20:48.506903 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 01:20:48.507011 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 01:20:48.507125 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13468763/tftp-deploy-pagevbpx/kernel/Image'
271 01:21:01.357895 Returned 0 in 12 seconds
272 01:21:01.458884 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13468763/tftp-deploy-pagevbpx/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13468763/tftp-deploy-pagevbpx/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13468763/tftp-deploy-pagevbpx/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13468763/tftp-deploy-pagevbpx/kernel/image.itb
273 01:21:01.809452 output: FIT description: Kernel Image image with one or more FDT blobs
274 01:21:01.809831 output: Created: Tue Apr 23 02:21:01 2024
275 01:21:01.809907 output: Image 0 (kernel-1)
276 01:21:01.809974 output: Description:
277 01:21:01.810040 output: Created: Tue Apr 23 02:21:01 2024
278 01:21:01.810099 output: Type: Kernel Image
279 01:21:01.810160 output: Compression: lzma compressed
280 01:21:01.810219 output: Data Size: 12910050 Bytes = 12607.47 KiB = 12.31 MiB
281 01:21:01.810280 output: Architecture: AArch64
282 01:21:01.810338 output: OS: Linux
283 01:21:01.810395 output: Load Address: 0x00000000
284 01:21:01.810456 output: Entry Point: 0x00000000
285 01:21:01.810515 output: Hash algo: crc32
286 01:21:01.810571 output: Hash value: 1126c3f9
287 01:21:01.810630 output: Image 1 (fdt-1)
288 01:21:01.810684 output: Description: mt8192-asurada-spherion-r0
289 01:21:01.810737 output: Created: Tue Apr 23 02:21:01 2024
290 01:21:01.810791 output: Type: Flat Device Tree
291 01:21:01.810845 output: Compression: uncompressed
292 01:21:01.810898 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
293 01:21:01.810951 output: Architecture: AArch64
294 01:21:01.811005 output: Hash algo: crc32
295 01:21:01.811058 output: Hash value: 4bf0d1ac
296 01:21:01.811111 output: Image 2 (ramdisk-1)
297 01:21:01.811164 output: Description: unavailable
298 01:21:01.811217 output: Created: Tue Apr 23 02:21:01 2024
299 01:21:01.811271 output: Type: RAMDisk Image
300 01:21:01.811324 output: Compression: Unknown Compression
301 01:21:01.811377 output: Data Size: 18777679 Bytes = 18337.58 KiB = 17.91 MiB
302 01:21:01.811431 output: Architecture: AArch64
303 01:21:01.811485 output: OS: Linux
304 01:21:01.811538 output: Load Address: unavailable
305 01:21:01.811591 output: Entry Point: unavailable
306 01:21:01.811644 output: Hash algo: crc32
307 01:21:01.811698 output: Hash value: 357415fb
308 01:21:01.811751 output: Default Configuration: 'conf-1'
309 01:21:01.811804 output: Configuration 0 (conf-1)
310 01:21:01.811856 output: Description: mt8192-asurada-spherion-r0
311 01:21:01.811909 output: Kernel: kernel-1
312 01:21:01.811962 output: Init Ramdisk: ramdisk-1
313 01:21:01.812015 output: FDT: fdt-1
314 01:21:01.812066 output: Loadables: kernel-1
315 01:21:01.812120 output:
316 01:21:01.812327 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 01:21:01.812426 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 01:21:01.812536 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 01:21:01.812626 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 01:21:01.812711 No LXC device requested
321 01:21:01.812792 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 01:21:01.812886 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 01:21:01.812965 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 01:21:01.813032 Checking files for TFTP limit of 4294967296 bytes.
325 01:21:01.813603 end: 1 tftp-deploy (duration 00:00:40) [common]
326 01:21:01.813713 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 01:21:01.813807 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 01:21:01.813938 substitutions:
329 01:21:01.814009 - {DTB}: 13468763/tftp-deploy-pagevbpx/dtb/mt8192-asurada-spherion-r0.dtb
330 01:21:01.814077 - {INITRD}: 13468763/tftp-deploy-pagevbpx/ramdisk/ramdisk.cpio.gz
331 01:21:01.814140 - {KERNEL}: 13468763/tftp-deploy-pagevbpx/kernel/Image
332 01:21:01.814199 - {LAVA_MAC}: None
333 01:21:01.814257 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13468763/extract-nfsrootfs-bow5lg9n
334 01:21:01.814314 - {NFS_SERVER_IP}: 192.168.201.1
335 01:21:01.814370 - {PRESEED_CONFIG}: None
336 01:21:01.814426 - {PRESEED_LOCAL}: None
337 01:21:01.814480 - {RAMDISK}: 13468763/tftp-deploy-pagevbpx/ramdisk/ramdisk.cpio.gz
338 01:21:01.814536 - {ROOT_PART}: None
339 01:21:01.814590 - {ROOT}: None
340 01:21:01.814645 - {SERVER_IP}: 192.168.201.1
341 01:21:01.814699 - {TEE}: None
342 01:21:01.814754 Parsed boot commands:
343 01:21:01.814807 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 01:21:01.814982 Parsed boot commands: tftpboot 192.168.201.1 13468763/tftp-deploy-pagevbpx/kernel/image.itb 13468763/tftp-deploy-pagevbpx/kernel/cmdline
345 01:21:01.815075 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 01:21:01.815160 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 01:21:01.815254 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 01:21:01.815343 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 01:21:01.815420 Not connected, no need to disconnect.
350 01:21:01.815495 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 01:21:01.815578 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 01:21:01.815648 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
353 01:21:01.819441 Setting prompt string to ['lava-test: # ']
354 01:21:01.819806 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 01:21:01.819915 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 01:21:01.820031 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 01:21:01.820159 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 01:21:01.820357 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
359 01:21:06.972545 >> Command sent successfully.
360 01:21:06.983732 Returned 0 in 5 seconds
361 01:21:07.085028 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 01:21:07.086655 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 01:21:07.087223 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 01:21:07.087893 Setting prompt string to 'Starting depthcharge on Spherion...'
366 01:21:07.088302 Changing prompt to 'Starting depthcharge on Spherion...'
367 01:21:07.088697 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 01:21:07.090039 [Enter `^Ec?' for help]
369 01:21:07.250842
370 01:21:07.251407
371 01:21:07.251813 F0: 102B 0000
372 01:21:07.252190
373 01:21:07.252528 F3: 1001 0000 [0200]
374 01:21:07.253709
375 01:21:07.254157 F3: 1001 0000
376 01:21:07.254507
377 01:21:07.254831 F7: 102D 0000
378 01:21:07.255143
379 01:21:07.256846 F1: 0000 0000
380 01:21:07.257286
381 01:21:07.257684 V0: 0000 0000 [0001]
382 01:21:07.258025
383 01:21:07.260219 00: 0007 8000
384 01:21:07.260673
385 01:21:07.261021 01: 0000 0000
386 01:21:07.261389
387 01:21:07.263371 BP: 0C00 0209 [0000]
388 01:21:07.263807
389 01:21:07.264214 G0: 1182 0000
390 01:21:07.264544
391 01:21:07.267320 EC: 0000 0021 [4000]
392 01:21:07.267871
393 01:21:07.268222 S7: 0000 0000 [0000]
394 01:21:07.268547
395 01:21:07.270451 CC: 0000 0000 [0001]
396 01:21:07.270889
397 01:21:07.271235 T0: 0000 0040 [010F]
398 01:21:07.271558
399 01:21:07.274267 Jump to BL
400 01:21:07.274703
401 01:21:07.297886
402 01:21:07.298429
403 01:21:07.298777
404 01:21:07.304004 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 01:21:07.307603 ARM64: Exception handlers installed.
406 01:21:07.310921 ARM64: Testing exception
407 01:21:07.313982 ARM64: Done test exception
408 01:21:07.321007 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 01:21:07.331159 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 01:21:07.337430 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 01:21:07.348523 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 01:21:07.355188 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 01:21:07.365448 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 01:21:07.375121 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 01:21:07.381826 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 01:21:07.400255 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 01:21:07.403388 WDT: Last reset was cold boot
418 01:21:07.406878 SPI1(PAD0) initialized at 2873684 Hz
419 01:21:07.410064 SPI5(PAD0) initialized at 992727 Hz
420 01:21:07.414053 VBOOT: Loading verstage.
421 01:21:07.420171 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 01:21:07.423427 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 01:21:07.426858 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 01:21:07.429897 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 01:21:07.438073 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 01:21:07.444200 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 01:21:07.455508 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 01:21:07.456110
429 01:21:07.456493
430 01:21:07.465256 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 01:21:07.468989 ARM64: Exception handlers installed.
432 01:21:07.471680 ARM64: Testing exception
433 01:21:07.472161 ARM64: Done test exception
434 01:21:07.478170 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 01:21:07.482067 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 01:21:07.496802 Probing TPM: . done!
437 01:21:07.497426 TPM ready after 0 ms
438 01:21:07.505484 Connected to device vid:did:rid of 1ae0:0028:00
439 01:21:07.511939 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 01:21:07.567205 Initialized TPM device CR50 revision 0
441 01:21:07.579797 tlcl_send_startup: Startup return code is 0
442 01:21:07.580389 TPM: setup succeeded
443 01:21:07.591192 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 01:21:07.600244 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 01:21:07.611766 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 01:21:07.621088 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 01:21:07.624607 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 01:21:07.630434 in-header: 03 07 00 00 08 00 00 00
449 01:21:07.634182 in-data: aa e4 47 04 13 02 00 00
450 01:21:07.637748 Chrome EC: UHEPI supported
451 01:21:07.645014 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 01:21:07.648009 in-header: 03 ad 00 00 08 00 00 00
453 01:21:07.651504 in-data: 00 20 20 08 00 00 00 00
454 01:21:07.652015 Phase 1
455 01:21:07.655614 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 01:21:07.662631 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 01:21:07.666360 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 01:21:07.670079 Recovery requested (1009000e)
459 01:21:07.679624 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 01:21:07.685398 tlcl_extend: response is 0
461 01:21:07.695257 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 01:21:07.700555 tlcl_extend: response is 0
463 01:21:07.707353 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 01:21:07.727397 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 01:21:07.733905 BS: bootblock times (exec / console): total (unknown) / 149 ms
466 01:21:07.734389
467 01:21:07.734783
468 01:21:07.744931 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 01:21:07.747943 ARM64: Exception handlers installed.
470 01:21:07.748482 ARM64: Testing exception
471 01:21:07.751286 ARM64: Done test exception
472 01:21:07.772499 pmic_efuse_setting: Set efuses in 11 msecs
473 01:21:07.776508 pmwrap_interface_init: Select PMIF_VLD_RDY
474 01:21:07.782575 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 01:21:07.786442 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 01:21:07.793065 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 01:21:07.796578 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 01:21:07.800368 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 01:21:07.807803 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 01:21:07.811187 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 01:21:07.814664 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 01:21:07.818462 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 01:21:07.826251 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 01:21:07.829399 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 01:21:07.833253 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 01:21:07.840280 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 01:21:07.843991 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 01:21:07.851770 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 01:21:07.855171 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 01:21:07.862339 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 01:21:07.869363 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 01:21:07.872833 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 01:21:07.880260 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 01:21:07.884514 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 01:21:07.891238 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 01:21:07.894942 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 01:21:07.902720 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 01:21:07.905602 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 01:21:07.912851 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 01:21:07.916594 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 01:21:07.923806 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 01:21:07.927428 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 01:21:07.930913 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 01:21:07.937863 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 01:21:07.941498 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 01:21:07.945055 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 01:21:07.952671 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 01:21:07.955934 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 01:21:07.963542 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 01:21:07.967348 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 01:21:07.970964 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 01:21:07.974778 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 01:21:07.981827 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 01:21:07.985608 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 01:21:07.989290 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 01:21:07.993093 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 01:21:07.996476 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 01:21:08.004314 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 01:21:08.007910 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 01:21:08.011863 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 01:21:08.014605 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 01:21:08.018275 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 01:21:08.021898 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 01:21:08.029459 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 01:21:08.036766 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 01:21:08.043844 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 01:21:08.047834 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 01:21:08.055083 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 01:21:08.065754 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 01:21:08.069686 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 01:21:08.073100 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 01:21:08.080467 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 01:21:08.087509 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0xf
534 01:21:08.091695 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 01:21:08.094689 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
536 01:21:08.101874 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 01:21:08.110444 [RTC]rtc_get_frequency_meter,154: input=15, output=833
538 01:21:08.119301 [RTC]rtc_get_frequency_meter,154: input=7, output=708
539 01:21:08.129268 [RTC]rtc_get_frequency_meter,154: input=11, output=771
540 01:21:08.138344 [RTC]rtc_get_frequency_meter,154: input=13, output=802
541 01:21:08.148376 [RTC]rtc_get_frequency_meter,154: input=12, output=786
542 01:21:08.157461 [RTC]rtc_get_frequency_meter,154: input=12, output=787
543 01:21:08.167498 [RTC]rtc_get_frequency_meter,154: input=13, output=803
544 01:21:08.171710 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
545 01:21:08.174847 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
546 01:21:08.182426 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 01:21:08.185976 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 01:21:08.189186 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 01:21:08.192738 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 01:21:08.196536 ADC[4]: Raw value=906357 ID=7
551 01:21:08.200644 ADC[3]: Raw value=214021 ID=1
552 01:21:08.201229 RAM Code: 0x71
553 01:21:08.204013 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 01:21:08.211310 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 01:21:08.218519 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 01:21:08.225861 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 01:21:08.229465 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 01:21:08.232908 in-header: 03 07 00 00 08 00 00 00
559 01:21:08.236448 in-data: aa e4 47 04 13 02 00 00
560 01:21:08.236893 Chrome EC: UHEPI supported
561 01:21:08.243675 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 01:21:08.247414 in-header: 03 ed 00 00 08 00 00 00
563 01:21:08.251018 in-data: 80 20 60 08 00 00 00 00
564 01:21:08.255007 MRC: failed to locate region type 0.
565 01:21:08.262572 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 01:21:08.265824 DRAM-K: Running full calibration
567 01:21:08.269753 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 01:21:08.272899 header.status = 0x0
569 01:21:08.276887 header.version = 0x6 (expected: 0x6)
570 01:21:08.280370 header.size = 0xd00 (expected: 0xd00)
571 01:21:08.280824 header.flags = 0x0
572 01:21:08.288178 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 01:21:08.305693 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 01:21:08.313192 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 01:21:08.316875 dram_init: ddr_geometry: 2
576 01:21:08.317312 [EMI] MDL number = 2
577 01:21:08.320317 [EMI] Get MDL freq = 0
578 01:21:08.320881 dram_init: ddr_type: 0
579 01:21:08.324137 is_discrete_lpddr4: 1
580 01:21:08.328451 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 01:21:08.329012
582 01:21:08.329406
583 01:21:08.329738 [Bian_co] ETT version 0.0.0.1
584 01:21:08.334847 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 01:21:08.335286
586 01:21:08.338429 dramc_set_vcore_voltage set vcore to 650000
587 01:21:08.338918 Read voltage for 800, 4
588 01:21:08.342088 Vio18 = 0
589 01:21:08.342529 Vcore = 650000
590 01:21:08.342875 Vdram = 0
591 01:21:08.346116 Vddq = 0
592 01:21:08.346556 Vmddr = 0
593 01:21:08.346907 dram_init: config_dvfs: 1
594 01:21:08.353849 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 01:21:08.356579 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 01:21:08.360468 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
597 01:21:08.363961 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
598 01:21:08.367885 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
599 01:21:08.371928 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
600 01:21:08.375138 MEM_TYPE=3, freq_sel=18
601 01:21:08.378594 sv_algorithm_assistance_LP4_1600
602 01:21:08.382723 ============ PULL DRAM RESETB DOWN ============
603 01:21:08.385684 ========== PULL DRAM RESETB DOWN end =========
604 01:21:08.392574 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 01:21:08.395730 ===================================
606 01:21:08.396312 LPDDR4 DRAM CONFIGURATION
607 01:21:08.399093 ===================================
608 01:21:08.402003 EX_ROW_EN[0] = 0x0
609 01:21:08.405451 EX_ROW_EN[1] = 0x0
610 01:21:08.405935 LP4Y_EN = 0x0
611 01:21:08.409898 WORK_FSP = 0x0
612 01:21:08.410479 WL = 0x2
613 01:21:08.412448 RL = 0x2
614 01:21:08.413026 BL = 0x2
615 01:21:08.415442 RPST = 0x0
616 01:21:08.415919 RD_PRE = 0x0
617 01:21:08.419153 WR_PRE = 0x1
618 01:21:08.419630 WR_PST = 0x0
619 01:21:08.422076 DBI_WR = 0x0
620 01:21:08.422509 DBI_RD = 0x0
621 01:21:08.425446 OTF = 0x1
622 01:21:08.428698 ===================================
623 01:21:08.432225 ===================================
624 01:21:08.432761 ANA top config
625 01:21:08.435260 ===================================
626 01:21:08.438807 DLL_ASYNC_EN = 0
627 01:21:08.441899 ALL_SLAVE_EN = 1
628 01:21:08.442332 NEW_RANK_MODE = 1
629 01:21:08.445363 DLL_IDLE_MODE = 1
630 01:21:08.448988 LP45_APHY_COMB_EN = 1
631 01:21:08.452171 TX_ODT_DIS = 1
632 01:21:08.455275 NEW_8X_MODE = 1
633 01:21:08.458440 ===================================
634 01:21:08.462071 ===================================
635 01:21:08.462571 data_rate = 1600
636 01:21:08.465013 CKR = 1
637 01:21:08.468871 DQ_P2S_RATIO = 8
638 01:21:08.472151 ===================================
639 01:21:08.475581 CA_P2S_RATIO = 8
640 01:21:08.478544 DQ_CA_OPEN = 0
641 01:21:08.482002 DQ_SEMI_OPEN = 0
642 01:21:08.482714 CA_SEMI_OPEN = 0
643 01:21:08.485223 CA_FULL_RATE = 0
644 01:21:08.488614 DQ_CKDIV4_EN = 1
645 01:21:08.491656 CA_CKDIV4_EN = 1
646 01:21:08.495019 CA_PREDIV_EN = 0
647 01:21:08.498423 PH8_DLY = 0
648 01:21:08.498904 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 01:21:08.501821 DQ_AAMCK_DIV = 4
650 01:21:08.505151 CA_AAMCK_DIV = 4
651 01:21:08.508311 CA_ADMCK_DIV = 4
652 01:21:08.511857 DQ_TRACK_CA_EN = 0
653 01:21:08.515142 CA_PICK = 800
654 01:21:08.518209 CA_MCKIO = 800
655 01:21:08.518706 MCKIO_SEMI = 0
656 01:21:08.522238 PLL_FREQ = 3068
657 01:21:08.525561 DQ_UI_PI_RATIO = 32
658 01:21:08.529406 CA_UI_PI_RATIO = 0
659 01:21:08.533117 ===================================
660 01:21:08.536468 ===================================
661 01:21:08.536949 memory_type:LPDDR4
662 01:21:08.540373 GP_NUM : 10
663 01:21:08.540849 SRAM_EN : 1
664 01:21:08.544151 MD32_EN : 0
665 01:21:08.548302 ===================================
666 01:21:08.548850 [ANA_INIT] >>>>>>>>>>>>>>
667 01:21:08.551547 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 01:21:08.555244 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 01:21:08.558865 ===================================
670 01:21:08.562066 data_rate = 1600,PCW = 0X7600
671 01:21:08.565856 ===================================
672 01:21:08.568466 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 01:21:08.571936 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 01:21:08.578438 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 01:21:08.585193 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 01:21:08.588459 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 01:21:08.592121 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 01:21:08.592704 [ANA_INIT] flow start
679 01:21:08.595669 [ANA_INIT] PLL >>>>>>>>
680 01:21:08.598604 [ANA_INIT] PLL <<<<<<<<
681 01:21:08.599108 [ANA_INIT] MIDPI >>>>>>>>
682 01:21:08.601372 [ANA_INIT] MIDPI <<<<<<<<
683 01:21:08.605440 [ANA_INIT] DLL >>>>>>>>
684 01:21:08.606027 [ANA_INIT] flow end
685 01:21:08.612128 ============ LP4 DIFF to SE enter ============
686 01:21:08.615238 ============ LP4 DIFF to SE exit ============
687 01:21:08.615736 [ANA_INIT] <<<<<<<<<<<<<
688 01:21:08.618301 [Flow] Enable top DCM control >>>>>
689 01:21:08.621796 [Flow] Enable top DCM control <<<<<
690 01:21:08.624953 Enable DLL master slave shuffle
691 01:21:08.631484 ==============================================================
692 01:21:08.634330 Gating Mode config
693 01:21:08.637636 ==============================================================
694 01:21:08.641181 Config description:
695 01:21:08.650845 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 01:21:08.657358 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 01:21:08.660790 SELPH_MODE 0: By rank 1: By Phase
698 01:21:08.667362 ==============================================================
699 01:21:08.670672 GAT_TRACK_EN = 1
700 01:21:08.674012 RX_GATING_MODE = 2
701 01:21:08.677537 RX_GATING_TRACK_MODE = 2
702 01:21:08.680527 SELPH_MODE = 1
703 01:21:08.684231 PICG_EARLY_EN = 1
704 01:21:08.684719 VALID_LAT_VALUE = 1
705 01:21:08.690130 ==============================================================
706 01:21:08.693606 Enter into Gating configuration >>>>
707 01:21:08.697533 Exit from Gating configuration <<<<
708 01:21:08.700403 Enter into DVFS_PRE_config >>>>>
709 01:21:08.713716 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 01:21:08.714311 Exit from DVFS_PRE_config <<<<<
711 01:21:08.717132 Enter into PICG configuration >>>>
712 01:21:08.720064 Exit from PICG configuration <<<<
713 01:21:08.723396 [RX_INPUT] configuration >>>>>
714 01:21:08.726708 [RX_INPUT] configuration <<<<<
715 01:21:08.733303 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 01:21:08.737027 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 01:21:08.743452 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 01:21:08.750402 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 01:21:08.756850 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 01:21:08.763208 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 01:21:08.766444 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 01:21:08.770056 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 01:21:08.773719 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 01:21:08.779976 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 01:21:08.783425 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 01:21:08.786657 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 01:21:08.790167 ===================================
728 01:21:08.793318 LPDDR4 DRAM CONFIGURATION
729 01:21:08.796705 ===================================
730 01:21:08.797246 EX_ROW_EN[0] = 0x0
731 01:21:08.799690 EX_ROW_EN[1] = 0x0
732 01:21:08.803275 LP4Y_EN = 0x0
733 01:21:08.803807 WORK_FSP = 0x0
734 01:21:08.806272 WL = 0x2
735 01:21:08.806714 RL = 0x2
736 01:21:08.809590 BL = 0x2
737 01:21:08.810026 RPST = 0x0
738 01:21:08.812768 RD_PRE = 0x0
739 01:21:08.813204 WR_PRE = 0x1
740 01:21:08.816542 WR_PST = 0x0
741 01:21:08.816981 DBI_WR = 0x0
742 01:21:08.819817 DBI_RD = 0x0
743 01:21:08.820432 OTF = 0x1
744 01:21:08.822923 ===================================
745 01:21:08.826423 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 01:21:08.833005 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 01:21:08.836228 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 01:21:08.839249 ===================================
749 01:21:08.842585 LPDDR4 DRAM CONFIGURATION
750 01:21:08.845833 ===================================
751 01:21:08.846427 EX_ROW_EN[0] = 0x10
752 01:21:08.849637 EX_ROW_EN[1] = 0x0
753 01:21:08.852702 LP4Y_EN = 0x0
754 01:21:08.853132 WORK_FSP = 0x0
755 01:21:08.855984 WL = 0x2
756 01:21:08.856510 RL = 0x2
757 01:21:08.859127 BL = 0x2
758 01:21:08.859559 RPST = 0x0
759 01:21:08.862436 RD_PRE = 0x0
760 01:21:08.862971 WR_PRE = 0x1
761 01:21:08.865279 WR_PST = 0x0
762 01:21:08.865699 DBI_WR = 0x0
763 01:21:08.869051 DBI_RD = 0x0
764 01:21:08.869614 OTF = 0x1
765 01:21:08.872449 ===================================
766 01:21:08.879014 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 01:21:08.883289 nWR fixed to 40
768 01:21:08.886827 [ModeRegInit_LP4] CH0 RK0
769 01:21:08.887261 [ModeRegInit_LP4] CH0 RK1
770 01:21:08.889928 [ModeRegInit_LP4] CH1 RK0
771 01:21:08.893538 [ModeRegInit_LP4] CH1 RK1
772 01:21:08.893980 match AC timing 13
773 01:21:08.899823 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 01:21:08.903346 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 01:21:08.906550 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 01:21:08.913176 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 01:21:08.916405 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 01:21:08.919937 [EMI DOE] emi_dcm 0
779 01:21:08.923222 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 01:21:08.923711 ==
781 01:21:08.926617 Dram Type= 6, Freq= 0, CH_0, rank 0
782 01:21:08.929812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 01:21:08.930261 ==
784 01:21:08.936362 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 01:21:08.942707 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 01:21:08.950842 [CA 0] Center 37 (7~68) winsize 62
787 01:21:08.954080 [CA 1] Center 37 (6~68) winsize 63
788 01:21:08.957506 [CA 2] Center 34 (4~65) winsize 62
789 01:21:08.960744 [CA 3] Center 34 (4~65) winsize 62
790 01:21:08.964107 [CA 4] Center 34 (4~64) winsize 61
791 01:21:08.967430 [CA 5] Center 33 (3~64) winsize 62
792 01:21:08.967918
793 01:21:08.970529 [CmdBusTrainingLP45] Vref(ca) range 1: 30
794 01:21:08.971011
795 01:21:08.973877 [CATrainingPosCal] consider 1 rank data
796 01:21:08.977570 u2DelayCellTimex100 = 270/100 ps
797 01:21:08.981062 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 01:21:08.987147 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 01:21:08.990554 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 01:21:08.993965 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 01:21:08.997207 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
802 01:21:09.000612 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 01:21:09.001212
804 01:21:09.003979 CA PerBit enable=1, Macro0, CA PI delay=33
805 01:21:09.004557
806 01:21:09.007261 [CBTSetCACLKResult] CA Dly = 33
807 01:21:09.010580 CS Dly: 6 (0~37)
808 01:21:09.011158 ==
809 01:21:09.013701 Dram Type= 6, Freq= 0, CH_0, rank 1
810 01:21:09.016971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 01:21:09.017619 ==
812 01:21:09.023252 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 01:21:09.027358 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 01:21:09.037387 [CA 0] Center 37 (6~68) winsize 63
815 01:21:09.040348 [CA 1] Center 37 (7~68) winsize 62
816 01:21:09.043888 [CA 2] Center 34 (4~65) winsize 62
817 01:21:09.047405 [CA 3] Center 34 (4~65) winsize 62
818 01:21:09.050201 [CA 4] Center 33 (3~64) winsize 62
819 01:21:09.053714 [CA 5] Center 33 (3~64) winsize 62
820 01:21:09.054311
821 01:21:09.057504 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 01:21:09.058081
823 01:21:09.060588 [CATrainingPosCal] consider 2 rank data
824 01:21:09.063754 u2DelayCellTimex100 = 270/100 ps
825 01:21:09.067238 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 01:21:09.073580 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 01:21:09.077033 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 01:21:09.079884 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 01:21:09.083026 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
830 01:21:09.086539 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 01:21:09.087043
832 01:21:09.089818 CA PerBit enable=1, Macro0, CA PI delay=33
833 01:21:09.090317
834 01:21:09.093287 [CBTSetCACLKResult] CA Dly = 33
835 01:21:09.093797 CS Dly: 7 (0~39)
836 01:21:09.096445
837 01:21:09.100080 ----->DramcWriteLeveling(PI) begin...
838 01:21:09.100672 ==
839 01:21:09.103409 Dram Type= 6, Freq= 0, CH_0, rank 0
840 01:21:09.107010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 01:21:09.107584 ==
842 01:21:09.110106 Write leveling (Byte 0): 30 => 30
843 01:21:09.113452 Write leveling (Byte 1): 29 => 29
844 01:21:09.117267 DramcWriteLeveling(PI) end<-----
845 01:21:09.117920
846 01:21:09.118303 ==
847 01:21:09.120565 Dram Type= 6, Freq= 0, CH_0, rank 0
848 01:21:09.124124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 01:21:09.124736 ==
850 01:21:09.126890 [Gating] SW mode calibration
851 01:21:09.134164 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 01:21:09.137448 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 01:21:09.144090 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 01:21:09.147771 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 01:21:09.150554 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
856 01:21:09.157506 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 01:21:09.161248 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 01:21:09.163828 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 01:21:09.170551 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 01:21:09.173901 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 01:21:09.177100 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 01:21:09.184007 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 01:21:09.186768 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 01:21:09.190254 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 01:21:09.196884 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 01:21:09.200710 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 01:21:09.203969 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 01:21:09.210330 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 01:21:09.213556 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 01:21:09.217071 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 01:21:09.223455 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
872 01:21:09.226618 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 01:21:09.230258 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 01:21:09.233970 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 01:21:09.240336 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 01:21:09.243793 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 01:21:09.247299 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 01:21:09.253520 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 01:21:09.256593 0 9 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
880 01:21:09.259743 0 9 12 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
881 01:21:09.267051 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 01:21:09.269889 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 01:21:09.273626 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 01:21:09.280438 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 01:21:09.283307 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 01:21:09.287200 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
887 01:21:09.293468 0 10 8 | B1->B0 | 3434 2828 | 1 0 | (1 0) (1 0)
888 01:21:09.296906 0 10 12 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
889 01:21:09.299840 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 01:21:09.306339 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 01:21:09.310296 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 01:21:09.313091 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 01:21:09.319891 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 01:21:09.323008 0 11 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
895 01:21:09.326618 0 11 8 | B1->B0 | 2828 3737 | 0 1 | (0 0) (0 0)
896 01:21:09.333489 0 11 12 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
897 01:21:09.335953 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 01:21:09.340235 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 01:21:09.346153 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 01:21:09.349639 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 01:21:09.353312 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 01:21:09.359388 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 01:21:09.362520 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 01:21:09.365880 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
905 01:21:09.372757 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 01:21:09.375922 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 01:21:09.379493 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 01:21:09.385644 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 01:21:09.389185 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 01:21:09.392246 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 01:21:09.399214 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 01:21:09.402102 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 01:21:09.405518 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 01:21:09.412266 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 01:21:09.415657 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 01:21:09.419242 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 01:21:09.425993 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 01:21:09.428855 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 01:21:09.432329 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
920 01:21:09.438926 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 01:21:09.439511 Total UI for P1: 0, mck2ui 16
922 01:21:09.442401 best dqsien dly found for B0: ( 0, 14, 8)
923 01:21:09.445793 Total UI for P1: 0, mck2ui 16
924 01:21:09.449195 best dqsien dly found for B1: ( 0, 14, 10)
925 01:21:09.452648 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
926 01:21:09.458944 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
927 01:21:09.459526
928 01:21:09.462152 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 01:21:09.465497 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 01:21:09.468755 [Gating] SW calibration Done
931 01:21:09.469240 ==
932 01:21:09.472019 Dram Type= 6, Freq= 0, CH_0, rank 0
933 01:21:09.475621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 01:21:09.476108 ==
935 01:21:09.476489 RX Vref Scan: 0
936 01:21:09.476844
937 01:21:09.478559 RX Vref 0 -> 0, step: 1
938 01:21:09.479041
939 01:21:09.482302 RX Delay -130 -> 252, step: 16
940 01:21:09.485906 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 01:21:09.488428 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 01:21:09.495078 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 01:21:09.498934 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 01:21:09.501831 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 01:21:09.505205 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 01:21:09.511907 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
947 01:21:09.515074 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
948 01:21:09.518222 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
949 01:21:09.521691 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
950 01:21:09.524794 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 01:21:09.531503 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 01:21:09.534665 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
953 01:21:09.538192 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 01:21:09.541776 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 01:21:09.544689 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
956 01:21:09.548880 ==
957 01:21:09.549506 Dram Type= 6, Freq= 0, CH_0, rank 0
958 01:21:09.555037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 01:21:09.555620 ==
960 01:21:09.555999 DQS Delay:
961 01:21:09.558840 DQS0 = 0, DQS1 = 0
962 01:21:09.559319 DQM Delay:
963 01:21:09.561799 DQM0 = 85, DQM1 = 73
964 01:21:09.562371 DQ Delay:
965 01:21:09.564678 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 01:21:09.568186 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
967 01:21:09.571437 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
968 01:21:09.574632 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =77
969 01:21:09.575209
970 01:21:09.575591
971 01:21:09.575943 ==
972 01:21:09.578658 Dram Type= 6, Freq= 0, CH_0, rank 0
973 01:21:09.581575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 01:21:09.582061 ==
975 01:21:09.582441
976 01:21:09.582786
977 01:21:09.585096 TX Vref Scan disable
978 01:21:09.588321 == TX Byte 0 ==
979 01:21:09.591239 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
980 01:21:09.594342 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
981 01:21:09.597839 == TX Byte 1 ==
982 01:21:09.601502 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
983 01:21:09.604452 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
984 01:21:09.605029 ==
985 01:21:09.607466 Dram Type= 6, Freq= 0, CH_0, rank 0
986 01:21:09.614798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 01:21:09.615382 ==
988 01:21:09.625444 TX Vref=22, minBit 5, minWin=27, winSum=441
989 01:21:09.628905 TX Vref=24, minBit 4, minWin=27, winSum=442
990 01:21:09.631763 TX Vref=26, minBit 5, minWin=27, winSum=444
991 01:21:09.635574 TX Vref=28, minBit 8, minWin=27, winSum=447
992 01:21:09.639221 TX Vref=30, minBit 4, minWin=27, winSum=445
993 01:21:09.645771 TX Vref=32, minBit 4, minWin=27, winSum=440
994 01:21:09.648952 [TxChooseVref] Worse bit 8, Min win 27, Win sum 447, Final Vref 28
995 01:21:09.649571
996 01:21:09.652497 Final TX Range 1 Vref 28
997 01:21:09.653100
998 01:21:09.653532 ==
999 01:21:09.655746 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 01:21:09.658775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 01:21:09.662026 ==
1002 01:21:09.662508
1003 01:21:09.662885
1004 01:21:09.663236 TX Vref Scan disable
1005 01:21:09.665560 == TX Byte 0 ==
1006 01:21:09.668737 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1007 01:21:09.675738 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1008 01:21:09.676312 == TX Byte 1 ==
1009 01:21:09.679024 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1010 01:21:09.685905 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1011 01:21:09.686491
1012 01:21:09.686873 [DATLAT]
1013 01:21:09.687230 Freq=800, CH0 RK0
1014 01:21:09.687575
1015 01:21:09.688713 DATLAT Default: 0xa
1016 01:21:09.689194 0, 0xFFFF, sum = 0
1017 01:21:09.692151 1, 0xFFFF, sum = 0
1018 01:21:09.695596 2, 0xFFFF, sum = 0
1019 01:21:09.696086 3, 0xFFFF, sum = 0
1020 01:21:09.698966 4, 0xFFFF, sum = 0
1021 01:21:09.699567 5, 0xFFFF, sum = 0
1022 01:21:09.701720 6, 0xFFFF, sum = 0
1023 01:21:09.702212 7, 0xFFFF, sum = 0
1024 01:21:09.705232 8, 0xFFFF, sum = 0
1025 01:21:09.705786 9, 0x0, sum = 1
1026 01:21:09.708323 10, 0x0, sum = 2
1027 01:21:09.708912 11, 0x0, sum = 3
1028 01:21:09.709295 12, 0x0, sum = 4
1029 01:21:09.712398 best_step = 10
1030 01:21:09.712972
1031 01:21:09.713396 ==
1032 01:21:09.714750 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 01:21:09.718374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 01:21:09.718854 ==
1035 01:21:09.721549 RX Vref Scan: 1
1036 01:21:09.722024
1037 01:21:09.724816 Set Vref Range= 32 -> 127
1038 01:21:09.725358
1039 01:21:09.725768 RX Vref 32 -> 127, step: 1
1040 01:21:09.726123
1041 01:21:09.728301 RX Delay -111 -> 252, step: 8
1042 01:21:09.728773
1043 01:21:09.731679 Set Vref, RX VrefLevel [Byte0]: 32
1044 01:21:09.734712 [Byte1]: 32
1045 01:21:09.738739
1046 01:21:09.739342 Set Vref, RX VrefLevel [Byte0]: 33
1047 01:21:09.741967 [Byte1]: 33
1048 01:21:09.746619
1049 01:21:09.747204 Set Vref, RX VrefLevel [Byte0]: 34
1050 01:21:09.749866 [Byte1]: 34
1051 01:21:09.753469
1052 01:21:09.753941 Set Vref, RX VrefLevel [Byte0]: 35
1053 01:21:09.756794 [Byte1]: 35
1054 01:21:09.761628
1055 01:21:09.762212 Set Vref, RX VrefLevel [Byte0]: 36
1056 01:21:09.764900 [Byte1]: 36
1057 01:21:09.768860
1058 01:21:09.769326 Set Vref, RX VrefLevel [Byte0]: 37
1059 01:21:09.772065 [Byte1]: 37
1060 01:21:09.776464
1061 01:21:09.777083 Set Vref, RX VrefLevel [Byte0]: 38
1062 01:21:09.780129 [Byte1]: 38
1063 01:21:09.784402
1064 01:21:09.784873 Set Vref, RX VrefLevel [Byte0]: 39
1065 01:21:09.787556 [Byte1]: 39
1066 01:21:09.791573
1067 01:21:09.795335 Set Vref, RX VrefLevel [Byte0]: 40
1068 01:21:09.795822 [Byte1]: 40
1069 01:21:09.800006
1070 01:21:09.800432 Set Vref, RX VrefLevel [Byte0]: 41
1071 01:21:09.803565 [Byte1]: 41
1072 01:21:09.807735
1073 01:21:09.808173 Set Vref, RX VrefLevel [Byte0]: 42
1074 01:21:09.811146 [Byte1]: 42
1075 01:21:09.815000
1076 01:21:09.815428 Set Vref, RX VrefLevel [Byte0]: 43
1077 01:21:09.818121 [Byte1]: 43
1078 01:21:09.822279
1079 01:21:09.822703 Set Vref, RX VrefLevel [Byte0]: 44
1080 01:21:09.825869 [Byte1]: 44
1081 01:21:09.830149
1082 01:21:09.830676 Set Vref, RX VrefLevel [Byte0]: 45
1083 01:21:09.833274 [Byte1]: 45
1084 01:21:09.838218
1085 01:21:09.838781 Set Vref, RX VrefLevel [Byte0]: 46
1086 01:21:09.841148 [Byte1]: 46
1087 01:21:09.845463
1088 01:21:09.845899 Set Vref, RX VrefLevel [Byte0]: 47
1089 01:21:09.848884 [Byte1]: 47
1090 01:21:09.853120
1091 01:21:09.853708 Set Vref, RX VrefLevel [Byte0]: 48
1092 01:21:09.859313 [Byte1]: 48
1093 01:21:09.859788
1094 01:21:09.863053 Set Vref, RX VrefLevel [Byte0]: 49
1095 01:21:09.865912 [Byte1]: 49
1096 01:21:09.866339
1097 01:21:09.869428 Set Vref, RX VrefLevel [Byte0]: 50
1098 01:21:09.872543 [Byte1]: 50
1099 01:21:09.875906
1100 01:21:09.876333 Set Vref, RX VrefLevel [Byte0]: 51
1101 01:21:09.879057 [Byte1]: 51
1102 01:21:09.883937
1103 01:21:09.884368 Set Vref, RX VrefLevel [Byte0]: 52
1104 01:21:09.887117 [Byte1]: 52
1105 01:21:09.891602
1106 01:21:09.892138 Set Vref, RX VrefLevel [Byte0]: 53
1107 01:21:09.894591 [Byte1]: 53
1108 01:21:09.898833
1109 01:21:09.899297 Set Vref, RX VrefLevel [Byte0]: 54
1110 01:21:09.902659 [Byte1]: 54
1111 01:21:09.906484
1112 01:21:09.906960 Set Vref, RX VrefLevel [Byte0]: 55
1113 01:21:09.909781 [Byte1]: 55
1114 01:21:09.914108
1115 01:21:09.914583 Set Vref, RX VrefLevel [Byte0]: 56
1116 01:21:09.917142 [Byte1]: 56
1117 01:21:09.921763
1118 01:21:09.922195 Set Vref, RX VrefLevel [Byte0]: 57
1119 01:21:09.925215 [Byte1]: 57
1120 01:21:09.929233
1121 01:21:09.929730 Set Vref, RX VrefLevel [Byte0]: 58
1122 01:21:09.932757 [Byte1]: 58
1123 01:21:09.937413
1124 01:21:09.937843 Set Vref, RX VrefLevel [Byte0]: 59
1125 01:21:09.940478 [Byte1]: 59
1126 01:21:09.944578
1127 01:21:09.945158 Set Vref, RX VrefLevel [Byte0]: 60
1128 01:21:09.947799 [Byte1]: 60
1129 01:21:09.952524
1130 01:21:09.952949 Set Vref, RX VrefLevel [Byte0]: 61
1131 01:21:09.958645 [Byte1]: 61
1132 01:21:09.959132
1133 01:21:09.962318 Set Vref, RX VrefLevel [Byte0]: 62
1134 01:21:09.965349 [Byte1]: 62
1135 01:21:09.965779
1136 01:21:09.968414 Set Vref, RX VrefLevel [Byte0]: 63
1137 01:21:09.971797 [Byte1]: 63
1138 01:21:09.975510
1139 01:21:09.975935 Set Vref, RX VrefLevel [Byte0]: 64
1140 01:21:09.978448 [Byte1]: 64
1141 01:21:09.983209
1142 01:21:09.983634 Set Vref, RX VrefLevel [Byte0]: 65
1143 01:21:09.986413 [Byte1]: 65
1144 01:21:09.990659
1145 01:21:09.991177 Set Vref, RX VrefLevel [Byte0]: 66
1146 01:21:09.993701 [Byte1]: 66
1147 01:21:09.998183
1148 01:21:09.998611 Set Vref, RX VrefLevel [Byte0]: 67
1149 01:21:10.001678 [Byte1]: 67
1150 01:21:10.005937
1151 01:21:10.006359 Set Vref, RX VrefLevel [Byte0]: 68
1152 01:21:10.008972 [Byte1]: 68
1153 01:21:10.013524
1154 01:21:10.014045 Set Vref, RX VrefLevel [Byte0]: 69
1155 01:21:10.016677 [Byte1]: 69
1156 01:21:10.020690
1157 01:21:10.024474 Set Vref, RX VrefLevel [Byte0]: 70
1158 01:21:10.027218 [Byte1]: 70
1159 01:21:10.027646
1160 01:21:10.030818 Set Vref, RX VrefLevel [Byte0]: 71
1161 01:21:10.034099 [Byte1]: 71
1162 01:21:10.034526
1163 01:21:10.037694 Set Vref, RX VrefLevel [Byte0]: 72
1164 01:21:10.040718 [Byte1]: 72
1165 01:21:10.044432
1166 01:21:10.044862 Set Vref, RX VrefLevel [Byte0]: 73
1167 01:21:10.047613 [Byte1]: 73
1168 01:21:10.051679
1169 01:21:10.052114 Set Vref, RX VrefLevel [Byte0]: 74
1170 01:21:10.055059 [Byte1]: 74
1171 01:21:10.059460
1172 01:21:10.059887 Set Vref, RX VrefLevel [Byte0]: 75
1173 01:21:10.063180 [Byte1]: 75
1174 01:21:10.067171
1175 01:21:10.067596 Set Vref, RX VrefLevel [Byte0]: 76
1176 01:21:10.070280 [Byte1]: 76
1177 01:21:10.074469
1178 01:21:10.074891 Set Vref, RX VrefLevel [Byte0]: 77
1179 01:21:10.077702 [Byte1]: 77
1180 01:21:10.082529
1181 01:21:10.083069 Set Vref, RX VrefLevel [Byte0]: 78
1182 01:21:10.085570 [Byte1]: 78
1183 01:21:10.090066
1184 01:21:10.090589 Set Vref, RX VrefLevel [Byte0]: 79
1185 01:21:10.093370 [Byte1]: 79
1186 01:21:10.097320
1187 01:21:10.097777 Set Vref, RX VrefLevel [Byte0]: 80
1188 01:21:10.100917 [Byte1]: 80
1189 01:21:10.105388
1190 01:21:10.105847 Set Vref, RX VrefLevel [Byte0]: 81
1191 01:21:10.108438 [Byte1]: 81
1192 01:21:10.113389
1193 01:21:10.113813 Final RX Vref Byte 0 = 60 to rank0
1194 01:21:10.115814 Final RX Vref Byte 1 = 56 to rank0
1195 01:21:10.119487 Final RX Vref Byte 0 = 60 to rank1
1196 01:21:10.122928 Final RX Vref Byte 1 = 56 to rank1==
1197 01:21:10.126121 Dram Type= 6, Freq= 0, CH_0, rank 0
1198 01:21:10.132474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1199 01:21:10.132978 ==
1200 01:21:10.133354 DQS Delay:
1201 01:21:10.133698 DQS0 = 0, DQS1 = 0
1202 01:21:10.136055 DQM Delay:
1203 01:21:10.136480 DQM0 = 86, DQM1 = 75
1204 01:21:10.139343 DQ Delay:
1205 01:21:10.142402 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =80
1206 01:21:10.146258 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1207 01:21:10.149160 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1208 01:21:10.152573 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1209 01:21:10.152999
1210 01:21:10.153370
1211 01:21:10.159225 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e20, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 394 ps
1212 01:21:10.162232 CH0 RK0: MR19=606, MR18=3E20
1213 01:21:10.210343 CH0_RK0: MR19=0x606, MR18=0x3E20, DQSOSC=394, MR23=63, INC=95, DEC=63
1214 01:21:10.211065
1215 01:21:10.211649 ----->DramcWriteLeveling(PI) begin...
1216 01:21:10.212126 ==
1217 01:21:10.212491 Dram Type= 6, Freq= 0, CH_0, rank 1
1218 01:21:10.213175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1219 01:21:10.213582 ==
1220 01:21:10.213922 Write leveling (Byte 0): 31 => 31
1221 01:21:10.214248 Write leveling (Byte 1): 28 => 28
1222 01:21:10.214563 DramcWriteLeveling(PI) end<-----
1223 01:21:10.214872
1224 01:21:10.215179 ==
1225 01:21:10.215487 Dram Type= 6, Freq= 0, CH_0, rank 1
1226 01:21:10.215793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1227 01:21:10.216103 ==
1228 01:21:10.216514 [Gating] SW mode calibration
1229 01:21:10.216911 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1230 01:21:10.229696 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1231 01:21:10.230316 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1232 01:21:10.230708 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1233 01:21:10.231056 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1234 01:21:10.233042 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 01:21:10.236596 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 01:21:10.240247 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 01:21:10.243255 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 01:21:10.246650 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 01:21:10.250085 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 01:21:10.256831 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 01:21:10.259910 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 01:21:10.266141 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 01:21:10.269517 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 01:21:10.272940 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 01:21:10.279719 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 01:21:10.282622 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 01:21:10.286221 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 01:21:10.293422 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1249 01:21:10.295850 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1250 01:21:10.299355 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1251 01:21:10.302598 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 01:21:10.308999 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 01:21:10.312904 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 01:21:10.315814 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 01:21:10.322276 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 01:21:10.325744 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 01:21:10.329072 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1258 01:21:10.335551 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1259 01:21:10.338953 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1260 01:21:10.342189 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1261 01:21:10.349158 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1262 01:21:10.352455 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1263 01:21:10.356092 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1264 01:21:10.363095 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1265 01:21:10.366854 0 10 8 | B1->B0 | 3030 2a2a | 1 0 | (1 1) (0 0)
1266 01:21:10.370127 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1267 01:21:10.373219 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1268 01:21:10.380050 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1269 01:21:10.383718 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1270 01:21:10.387135 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1271 01:21:10.390604 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1272 01:21:10.397072 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1273 01:21:10.400279 0 11 8 | B1->B0 | 2b2b 3d3d | 0 0 | (0 0) (0 0)
1274 01:21:10.403858 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1275 01:21:10.410323 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1276 01:21:10.413559 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1277 01:21:10.417256 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1278 01:21:10.423629 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1279 01:21:10.427070 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1280 01:21:10.430169 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1281 01:21:10.436712 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 01:21:10.440131 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 01:21:10.443141 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 01:21:10.450140 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 01:21:10.453240 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 01:21:10.456666 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 01:21:10.463411 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 01:21:10.466635 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 01:21:10.469542 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 01:21:10.476643 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 01:21:10.479977 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 01:21:10.483440 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 01:21:10.489819 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 01:21:10.493049 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1295 01:21:10.496184 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1296 01:21:10.502894 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1297 01:21:10.506421 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1298 01:21:10.509369 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1299 01:21:10.513063 Total UI for P1: 0, mck2ui 16
1300 01:21:10.515702 best dqsien dly found for B0: ( 0, 14, 8)
1301 01:21:10.519315 Total UI for P1: 0, mck2ui 16
1302 01:21:10.522559 best dqsien dly found for B1: ( 0, 14, 10)
1303 01:21:10.525802 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1304 01:21:10.529321 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1305 01:21:10.532553
1306 01:21:10.535942 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1307 01:21:10.539274 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1308 01:21:10.542565 [Gating] SW calibration Done
1309 01:21:10.543132 ==
1310 01:21:10.545538 Dram Type= 6, Freq= 0, CH_0, rank 1
1311 01:21:10.549398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1312 01:21:10.549873 ==
1313 01:21:10.550239 RX Vref Scan: 0
1314 01:21:10.550578
1315 01:21:10.552693 RX Vref 0 -> 0, step: 1
1316 01:21:10.553262
1317 01:21:10.555704 RX Delay -130 -> 252, step: 16
1318 01:21:10.558744 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1319 01:21:10.562284 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1320 01:21:10.569441 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1321 01:21:10.572332 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1322 01:21:10.575466 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1323 01:21:10.579014 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1324 01:21:10.582217 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1325 01:21:10.589230 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1326 01:21:10.592366 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1327 01:21:10.595962 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1328 01:21:10.599075 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1329 01:21:10.602205 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1330 01:21:10.608997 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1331 01:21:10.612249 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1332 01:21:10.615420 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1333 01:21:10.618734 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1334 01:21:10.619207 ==
1335 01:21:10.621777 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 01:21:10.628826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 01:21:10.629463 ==
1338 01:21:10.629849 DQS Delay:
1339 01:21:10.631748 DQS0 = 0, DQS1 = 0
1340 01:21:10.632216 DQM Delay:
1341 01:21:10.632591 DQM0 = 84, DQM1 = 77
1342 01:21:10.635398 DQ Delay:
1343 01:21:10.638502 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1344 01:21:10.642015 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1345 01:21:10.645914 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1346 01:21:10.648507 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1347 01:21:10.648972
1348 01:21:10.649376
1349 01:21:10.649731 ==
1350 01:21:10.652078 Dram Type= 6, Freq= 0, CH_0, rank 1
1351 01:21:10.655684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1352 01:21:10.656254 ==
1353 01:21:10.656627
1354 01:21:10.656967
1355 01:21:10.658180 TX Vref Scan disable
1356 01:21:10.662020 == TX Byte 0 ==
1357 01:21:10.664937 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1358 01:21:10.668451 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1359 01:21:10.671838 == TX Byte 1 ==
1360 01:21:10.674981 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1361 01:21:10.678034 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1362 01:21:10.678499 ==
1363 01:21:10.681272 Dram Type= 6, Freq= 0, CH_0, rank 1
1364 01:21:10.684675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1365 01:21:10.688083 ==
1366 01:21:10.699737 TX Vref=22, minBit 8, minWin=26, winSum=441
1367 01:21:10.702750 TX Vref=24, minBit 8, minWin=27, winSum=446
1368 01:21:10.706230 TX Vref=26, minBit 9, minWin=27, winSum=448
1369 01:21:10.709858 TX Vref=28, minBit 9, minWin=27, winSum=448
1370 01:21:10.712657 TX Vref=30, minBit 9, minWin=27, winSum=450
1371 01:21:10.719861 TX Vref=32, minBit 8, minWin=27, winSum=447
1372 01:21:10.722503 [TxChooseVref] Worse bit 9, Min win 27, Win sum 450, Final Vref 30
1373 01:21:10.722924
1374 01:21:10.725855 Final TX Range 1 Vref 30
1375 01:21:10.726388
1376 01:21:10.726721 ==
1377 01:21:10.729192 Dram Type= 6, Freq= 0, CH_0, rank 1
1378 01:21:10.732289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1379 01:21:10.736154 ==
1380 01:21:10.736698
1381 01:21:10.737032
1382 01:21:10.737361 TX Vref Scan disable
1383 01:21:10.739299 == TX Byte 0 ==
1384 01:21:10.742553 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1385 01:21:10.749171 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1386 01:21:10.749832 == TX Byte 1 ==
1387 01:21:10.752775 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1388 01:21:10.756065 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1389 01:21:10.759427
1390 01:21:10.759843 [DATLAT]
1391 01:21:10.760171 Freq=800, CH0 RK1
1392 01:21:10.760476
1393 01:21:10.762678 DATLAT Default: 0xa
1394 01:21:10.763097 0, 0xFFFF, sum = 0
1395 01:21:10.766108 1, 0xFFFF, sum = 0
1396 01:21:10.766531 2, 0xFFFF, sum = 0
1397 01:21:10.769401 3, 0xFFFF, sum = 0
1398 01:21:10.769932 4, 0xFFFF, sum = 0
1399 01:21:10.772789 5, 0xFFFF, sum = 0
1400 01:21:10.775984 6, 0xFFFF, sum = 0
1401 01:21:10.776409 7, 0xFFFF, sum = 0
1402 01:21:10.779258 8, 0xFFFF, sum = 0
1403 01:21:10.779690 9, 0x0, sum = 1
1404 01:21:10.780031 10, 0x0, sum = 2
1405 01:21:10.782955 11, 0x0, sum = 3
1406 01:21:10.783528 12, 0x0, sum = 4
1407 01:21:10.785888 best_step = 10
1408 01:21:10.786310
1409 01:21:10.786641 ==
1410 01:21:10.789615 Dram Type= 6, Freq= 0, CH_0, rank 1
1411 01:21:10.792593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1412 01:21:10.793020 ==
1413 01:21:10.796069 RX Vref Scan: 0
1414 01:21:10.796591
1415 01:21:10.796925 RX Vref 0 -> 0, step: 1
1416 01:21:10.797232
1417 01:21:10.799338 RX Delay -111 -> 252, step: 8
1418 01:21:10.806171 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1419 01:21:10.809670 iDelay=209, Bit 1, Center 88 (-31 ~ 208) 240
1420 01:21:10.813248 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1421 01:21:10.816616 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1422 01:21:10.819809 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1423 01:21:10.826284 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1424 01:21:10.829695 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1425 01:21:10.833301 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1426 01:21:10.836425 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1427 01:21:10.839377 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1428 01:21:10.845994 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
1429 01:21:10.848964 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1430 01:21:10.853042 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1431 01:21:10.855857 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1432 01:21:10.862482 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1433 01:21:10.865978 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1434 01:21:10.866464 ==
1435 01:21:10.869524 Dram Type= 6, Freq= 0, CH_0, rank 1
1436 01:21:10.872769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 01:21:10.873382 ==
1438 01:21:10.875656 DQS Delay:
1439 01:21:10.876275 DQS0 = 0, DQS1 = 0
1440 01:21:10.876724 DQM Delay:
1441 01:21:10.878784 DQM0 = 85, DQM1 = 77
1442 01:21:10.879246 DQ Delay:
1443 01:21:10.883022 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1444 01:21:10.885670 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1445 01:21:10.889269 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1446 01:21:10.892706 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1447 01:21:10.893267
1448 01:21:10.893692
1449 01:21:10.902283 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b03, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
1450 01:21:10.902844 CH0 RK1: MR19=606, MR18=3B03
1451 01:21:10.908939 CH0_RK1: MR19=0x606, MR18=0x3B03, DQSOSC=394, MR23=63, INC=95, DEC=63
1452 01:21:10.912670 [RxdqsGatingPostProcess] freq 800
1453 01:21:10.918668 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1454 01:21:10.922019 Pre-setting of DQS Precalculation
1455 01:21:10.925214 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1456 01:21:10.925825 ==
1457 01:21:10.928889 Dram Type= 6, Freq= 0, CH_1, rank 0
1458 01:21:10.934981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1459 01:21:10.935529 ==
1460 01:21:10.938998 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1461 01:21:10.945127 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1462 01:21:10.954662 [CA 0] Center 36 (6~67) winsize 62
1463 01:21:10.959058 [CA 1] Center 36 (6~67) winsize 62
1464 01:21:10.961695 [CA 2] Center 34 (4~65) winsize 62
1465 01:21:10.964575 [CA 3] Center 34 (3~65) winsize 63
1466 01:21:10.968355 [CA 4] Center 34 (4~65) winsize 62
1467 01:21:10.971339 [CA 5] Center 34 (3~65) winsize 63
1468 01:21:10.971903
1469 01:21:10.974290 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1470 01:21:10.974757
1471 01:21:10.977763 [CATrainingPosCal] consider 1 rank data
1472 01:21:10.981596 u2DelayCellTimex100 = 270/100 ps
1473 01:21:10.984414 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1474 01:21:10.987676 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1475 01:21:10.994443 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1476 01:21:10.997620 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1477 01:21:11.000743 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1478 01:21:11.004198 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1479 01:21:11.004660
1480 01:21:11.007655 CA PerBit enable=1, Macro0, CA PI delay=34
1481 01:21:11.008229
1482 01:21:11.010665 [CBTSetCACLKResult] CA Dly = 34
1483 01:21:11.011133 CS Dly: 4 (0~35)
1484 01:21:11.014509 ==
1485 01:21:11.017181 Dram Type= 6, Freq= 0, CH_1, rank 1
1486 01:21:11.021443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1487 01:21:11.022075 ==
1488 01:21:11.024511 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1489 01:21:11.031759 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1490 01:21:11.041209 [CA 0] Center 36 (6~67) winsize 62
1491 01:21:11.044998 [CA 1] Center 37 (6~68) winsize 63
1492 01:21:11.047778 [CA 2] Center 34 (4~65) winsize 62
1493 01:21:11.051446 [CA 3] Center 34 (4~65) winsize 62
1494 01:21:11.055207 [CA 4] Center 34 (4~65) winsize 62
1495 01:21:11.058807 [CA 5] Center 34 (4~64) winsize 61
1496 01:21:11.059231
1497 01:21:11.061569 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1498 01:21:11.061991
1499 01:21:11.065369 [CATrainingPosCal] consider 2 rank data
1500 01:21:11.068582 u2DelayCellTimex100 = 270/100 ps
1501 01:21:11.072124 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1502 01:21:11.075270 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1503 01:21:11.078644 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1504 01:21:11.082404 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1505 01:21:11.084681 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1506 01:21:11.091941 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1507 01:21:11.092466
1508 01:21:11.095050 CA PerBit enable=1, Macro0, CA PI delay=34
1509 01:21:11.095472
1510 01:21:11.098356 [CBTSetCACLKResult] CA Dly = 34
1511 01:21:11.098881 CS Dly: 5 (0~38)
1512 01:21:11.099218
1513 01:21:11.101660 ----->DramcWriteLeveling(PI) begin...
1514 01:21:11.102086 ==
1515 01:21:11.104424 Dram Type= 6, Freq= 0, CH_1, rank 0
1516 01:21:11.111283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1517 01:21:11.112065 ==
1518 01:21:11.114650 Write leveling (Byte 0): 28 => 28
1519 01:21:11.115076 Write leveling (Byte 1): 27 => 27
1520 01:21:11.117967 DramcWriteLeveling(PI) end<-----
1521 01:21:11.118397
1522 01:21:11.118729 ==
1523 01:21:11.121578 Dram Type= 6, Freq= 0, CH_1, rank 0
1524 01:21:11.127930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1525 01:21:11.128454 ==
1526 01:21:11.131259 [Gating] SW mode calibration
1527 01:21:11.137670 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1528 01:21:11.141107 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1529 01:21:11.147656 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1530 01:21:11.151124 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1531 01:21:11.154778 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1532 01:21:11.161231 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 01:21:11.164174 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 01:21:11.167546 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 01:21:11.174321 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 01:21:11.177293 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 01:21:11.181176 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 01:21:11.187324 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 01:21:11.190873 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 01:21:11.194125 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 01:21:11.200714 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 01:21:11.204270 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 01:21:11.207282 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 01:21:11.214007 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 01:21:11.217065 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 01:21:11.220389 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1547 01:21:11.223834 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 01:21:11.230405 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 01:21:11.233790 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 01:21:11.237100 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 01:21:11.243868 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 01:21:11.246671 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 01:21:11.249962 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 01:21:11.256777 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 01:21:11.260302 0 9 8 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
1556 01:21:11.263605 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1557 01:21:11.270055 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1558 01:21:11.273558 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1559 01:21:11.276897 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1560 01:21:11.283635 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1561 01:21:11.286872 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1562 01:21:11.289903 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 0) (0 0)
1563 01:21:11.296553 0 10 8 | B1->B0 | 2d2d 2424 | 0 0 | (0 0) (0 0)
1564 01:21:11.300115 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1565 01:21:11.303063 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1566 01:21:11.310146 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1567 01:21:11.313058 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1568 01:21:11.316245 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1569 01:21:11.323229 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1570 01:21:11.326523 0 11 4 | B1->B0 | 2424 2525 | 1 0 | (0 0) (0 0)
1571 01:21:11.329564 0 11 8 | B1->B0 | 3a3a 3e3d | 1 1 | (0 0) (0 0)
1572 01:21:11.336069 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1573 01:21:11.339620 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1574 01:21:11.343153 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1575 01:21:11.349310 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1576 01:21:11.353063 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1577 01:21:11.355798 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1578 01:21:11.362594 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1579 01:21:11.365795 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 01:21:11.369438 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 01:21:11.376159 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 01:21:11.379432 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 01:21:11.382449 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 01:21:11.388931 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 01:21:11.392258 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 01:21:11.395747 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 01:21:11.402210 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 01:21:11.405405 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 01:21:11.408570 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 01:21:11.415436 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 01:21:11.418256 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 01:21:11.422026 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1593 01:21:11.428278 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1594 01:21:11.431776 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1595 01:21:11.435007 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1596 01:21:11.438144 Total UI for P1: 0, mck2ui 16
1597 01:21:11.441627 best dqsien dly found for B0: ( 0, 14, 6)
1598 01:21:11.447880 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1599 01:21:11.448035 Total UI for P1: 0, mck2ui 16
1600 01:21:11.454914 best dqsien dly found for B1: ( 0, 14, 8)
1601 01:21:11.457924 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1602 01:21:11.461290 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1603 01:21:11.461459
1604 01:21:11.464390 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1605 01:21:11.468205 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1606 01:21:11.471372 [Gating] SW calibration Done
1607 01:21:11.471614 ==
1608 01:21:11.474898 Dram Type= 6, Freq= 0, CH_1, rank 0
1609 01:21:11.477994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1610 01:21:11.478197 ==
1611 01:21:11.481189 RX Vref Scan: 0
1612 01:21:11.481381
1613 01:21:11.481501 RX Vref 0 -> 0, step: 1
1614 01:21:11.481610
1615 01:21:11.484618 RX Delay -130 -> 252, step: 16
1616 01:21:11.490835 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1617 01:21:11.494244 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1618 01:21:11.497674 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1619 01:21:11.500983 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1620 01:21:11.504706 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1621 01:21:11.511389 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1622 01:21:11.513952 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1623 01:21:11.517461 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1624 01:21:11.520434 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1625 01:21:11.524036 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1626 01:21:11.530838 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1627 01:21:11.534219 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1628 01:21:11.537791 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1629 01:21:11.540890 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1630 01:21:11.544256 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1631 01:21:11.550850 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1632 01:21:11.551058 ==
1633 01:21:11.554159 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 01:21:11.557507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 01:21:11.557753 ==
1636 01:21:11.557886 DQS Delay:
1637 01:21:11.561010 DQS0 = 0, DQS1 = 0
1638 01:21:11.561270 DQM Delay:
1639 01:21:11.564593 DQM0 = 88, DQM1 = 78
1640 01:21:11.564863 DQ Delay:
1641 01:21:11.567681 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1642 01:21:11.570977 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1643 01:21:11.573732 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1644 01:21:11.577270 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1645 01:21:11.577786
1646 01:21:11.578157
1647 01:21:11.578495 ==
1648 01:21:11.581278 Dram Type= 6, Freq= 0, CH_1, rank 0
1649 01:21:11.587508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1650 01:21:11.588094 ==
1651 01:21:11.588466
1652 01:21:11.588802
1653 01:21:11.589139 TX Vref Scan disable
1654 01:21:11.590719 == TX Byte 0 ==
1655 01:21:11.593968 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1656 01:21:11.601029 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1657 01:21:11.601773 == TX Byte 1 ==
1658 01:21:11.604401 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1659 01:21:11.607907 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1660 01:21:11.608376 ==
1661 01:21:11.611414 Dram Type= 6, Freq= 0, CH_1, rank 0
1662 01:21:11.617893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1663 01:21:11.618586 ==
1664 01:21:11.630510 TX Vref=22, minBit 8, minWin=27, winSum=444
1665 01:21:11.633264 TX Vref=24, minBit 10, minWin=27, winSum=447
1666 01:21:11.636794 TX Vref=26, minBit 0, minWin=27, winSum=451
1667 01:21:11.639903 TX Vref=28, minBit 13, minWin=27, winSum=452
1668 01:21:11.643104 TX Vref=30, minBit 8, minWin=27, winSum=448
1669 01:21:11.649842 TX Vref=32, minBit 8, minWin=27, winSum=448
1670 01:21:11.653389 [TxChooseVref] Worse bit 13, Min win 27, Win sum 452, Final Vref 28
1671 01:21:11.653975
1672 01:21:11.656503 Final TX Range 1 Vref 28
1673 01:21:11.657064
1674 01:21:11.657477 ==
1675 01:21:11.660135 Dram Type= 6, Freq= 0, CH_1, rank 0
1676 01:21:11.662993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1677 01:21:11.666138 ==
1678 01:21:11.666542
1679 01:21:11.666891
1680 01:21:11.667221 TX Vref Scan disable
1681 01:21:11.669786 == TX Byte 0 ==
1682 01:21:11.673211 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1683 01:21:11.677029 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1684 01:21:11.680384 == TX Byte 1 ==
1685 01:21:11.683363 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1686 01:21:11.690245 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1687 01:21:11.690802
1688 01:21:11.691166 [DATLAT]
1689 01:21:11.691503 Freq=800, CH1 RK0
1690 01:21:11.691898
1691 01:21:11.692946 DATLAT Default: 0xa
1692 01:21:11.693462 0, 0xFFFF, sum = 0
1693 01:21:11.696604 1, 0xFFFF, sum = 0
1694 01:21:11.699668 2, 0xFFFF, sum = 0
1695 01:21:11.700321 3, 0xFFFF, sum = 0
1696 01:21:11.702796 4, 0xFFFF, sum = 0
1697 01:21:11.703271 5, 0xFFFF, sum = 0
1698 01:21:11.706389 6, 0xFFFF, sum = 0
1699 01:21:11.707090 7, 0xFFFF, sum = 0
1700 01:21:11.709408 8, 0xFFFF, sum = 0
1701 01:21:11.709900 9, 0x0, sum = 1
1702 01:21:11.712489 10, 0x0, sum = 2
1703 01:21:11.712967 11, 0x0, sum = 3
1704 01:21:11.716343 12, 0x0, sum = 4
1705 01:21:11.716825 best_step = 10
1706 01:21:11.717210
1707 01:21:11.717607 ==
1708 01:21:11.719681 Dram Type= 6, Freq= 0, CH_1, rank 0
1709 01:21:11.722741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1710 01:21:11.723217 ==
1711 01:21:11.725979 RX Vref Scan: 1
1712 01:21:11.726443
1713 01:21:11.729304 Set Vref Range= 32 -> 127
1714 01:21:11.729765
1715 01:21:11.730098 RX Vref 32 -> 127, step: 1
1716 01:21:11.730411
1717 01:21:11.732677 RX Delay -95 -> 252, step: 8
1718 01:21:11.733099
1719 01:21:11.735798 Set Vref, RX VrefLevel [Byte0]: 32
1720 01:21:11.739064 [Byte1]: 32
1721 01:21:11.742737
1722 01:21:11.743178 Set Vref, RX VrefLevel [Byte0]: 33
1723 01:21:11.746178 [Byte1]: 33
1724 01:21:11.750431
1725 01:21:11.750963 Set Vref, RX VrefLevel [Byte0]: 34
1726 01:21:11.753959 [Byte1]: 34
1727 01:21:11.758289
1728 01:21:11.758819 Set Vref, RX VrefLevel [Byte0]: 35
1729 01:21:11.761191 [Byte1]: 35
1730 01:21:11.765549
1731 01:21:11.766088 Set Vref, RX VrefLevel [Byte0]: 36
1732 01:21:11.769919 [Byte1]: 36
1733 01:21:11.773166
1734 01:21:11.773734 Set Vref, RX VrefLevel [Byte0]: 37
1735 01:21:11.776535 [Byte1]: 37
1736 01:21:11.780653
1737 01:21:11.781077 Set Vref, RX VrefLevel [Byte0]: 38
1738 01:21:11.784533 [Byte1]: 38
1739 01:21:11.788969
1740 01:21:11.789537 Set Vref, RX VrefLevel [Byte0]: 39
1741 01:21:11.791800 [Byte1]: 39
1742 01:21:11.795892
1743 01:21:11.796464 Set Vref, RX VrefLevel [Byte0]: 40
1744 01:21:11.799139 [Byte1]: 40
1745 01:21:11.803753
1746 01:21:11.804324 Set Vref, RX VrefLevel [Byte0]: 41
1747 01:21:11.806760 [Byte1]: 41
1748 01:21:11.811198
1749 01:21:11.811769 Set Vref, RX VrefLevel [Byte0]: 42
1750 01:21:11.814046 [Byte1]: 42
1751 01:21:11.818874
1752 01:21:11.819462 Set Vref, RX VrefLevel [Byte0]: 43
1753 01:21:11.821983 [Byte1]: 43
1754 01:21:11.826485
1755 01:21:11.827058 Set Vref, RX VrefLevel [Byte0]: 44
1756 01:21:11.829661 [Byte1]: 44
1757 01:21:11.834389
1758 01:21:11.835035 Set Vref, RX VrefLevel [Byte0]: 45
1759 01:21:11.837394 [Byte1]: 45
1760 01:21:11.841397
1761 01:21:11.841971 Set Vref, RX VrefLevel [Byte0]: 46
1762 01:21:11.845210 [Byte1]: 46
1763 01:21:11.849134
1764 01:21:11.849630 Set Vref, RX VrefLevel [Byte0]: 47
1765 01:21:11.852366 [Byte1]: 47
1766 01:21:11.856932
1767 01:21:11.857539 Set Vref, RX VrefLevel [Byte0]: 48
1768 01:21:11.859778 [Byte1]: 48
1769 01:21:11.864081
1770 01:21:11.864592 Set Vref, RX VrefLevel [Byte0]: 49
1771 01:21:11.867197 [Byte1]: 49
1772 01:21:11.871664
1773 01:21:11.872135 Set Vref, RX VrefLevel [Byte0]: 50
1774 01:21:11.874964 [Byte1]: 50
1775 01:21:11.879779
1776 01:21:11.880351 Set Vref, RX VrefLevel [Byte0]: 51
1777 01:21:11.882681 [Byte1]: 51
1778 01:21:11.887311
1779 01:21:11.887884 Set Vref, RX VrefLevel [Byte0]: 52
1780 01:21:11.890206 [Byte1]: 52
1781 01:21:11.894736
1782 01:21:11.895302 Set Vref, RX VrefLevel [Byte0]: 53
1783 01:21:11.897978 [Byte1]: 53
1784 01:21:11.902364
1785 01:21:11.902947 Set Vref, RX VrefLevel [Byte0]: 54
1786 01:21:11.905457 [Byte1]: 54
1787 01:21:11.910036
1788 01:21:11.910501 Set Vref, RX VrefLevel [Byte0]: 55
1789 01:21:11.913217 [Byte1]: 55
1790 01:21:11.917646
1791 01:21:11.918218 Set Vref, RX VrefLevel [Byte0]: 56
1792 01:21:11.920561 [Byte1]: 56
1793 01:21:11.925652
1794 01:21:11.926228 Set Vref, RX VrefLevel [Byte0]: 57
1795 01:21:11.928101 [Byte1]: 57
1796 01:21:11.932379
1797 01:21:11.932873 Set Vref, RX VrefLevel [Byte0]: 58
1798 01:21:11.936125 [Byte1]: 58
1799 01:21:11.940101
1800 01:21:11.940670 Set Vref, RX VrefLevel [Byte0]: 59
1801 01:21:11.943629 [Byte1]: 59
1802 01:21:11.948147
1803 01:21:11.948727 Set Vref, RX VrefLevel [Byte0]: 60
1804 01:21:11.951142 [Byte1]: 60
1805 01:21:11.955763
1806 01:21:11.956229 Set Vref, RX VrefLevel [Byte0]: 61
1807 01:21:11.958546 [Byte1]: 61
1808 01:21:11.963062
1809 01:21:11.963631 Set Vref, RX VrefLevel [Byte0]: 62
1810 01:21:11.966015 [Byte1]: 62
1811 01:21:11.970958
1812 01:21:11.971537 Set Vref, RX VrefLevel [Byte0]: 63
1813 01:21:11.974283 [Byte1]: 63
1814 01:21:11.978250
1815 01:21:11.978860 Set Vref, RX VrefLevel [Byte0]: 64
1816 01:21:11.981661 [Byte1]: 64
1817 01:21:11.986134
1818 01:21:11.986727 Set Vref, RX VrefLevel [Byte0]: 65
1819 01:21:11.988851 [Byte1]: 65
1820 01:21:11.993685
1821 01:21:11.994252 Set Vref, RX VrefLevel [Byte0]: 66
1822 01:21:11.996671 [Byte1]: 66
1823 01:21:12.000881
1824 01:21:12.001489 Set Vref, RX VrefLevel [Byte0]: 67
1825 01:21:12.004705 [Byte1]: 67
1826 01:21:12.008448
1827 01:21:12.008917 Set Vref, RX VrefLevel [Byte0]: 68
1828 01:21:12.012284 [Byte1]: 68
1829 01:21:12.016511
1830 01:21:12.017111 Set Vref, RX VrefLevel [Byte0]: 69
1831 01:21:12.019876 [Byte1]: 69
1832 01:21:12.024070
1833 01:21:12.024634 Set Vref, RX VrefLevel [Byte0]: 70
1834 01:21:12.027083 [Byte1]: 70
1835 01:21:12.031432
1836 01:21:12.031994 Set Vref, RX VrefLevel [Byte0]: 71
1837 01:21:12.034892 [Byte1]: 71
1838 01:21:12.039298
1839 01:21:12.039861 Set Vref, RX VrefLevel [Byte0]: 72
1840 01:21:12.042450 [Byte1]: 72
1841 01:21:12.046632
1842 01:21:12.047196 Set Vref, RX VrefLevel [Byte0]: 73
1843 01:21:12.049806 [Byte1]: 73
1844 01:21:12.054202
1845 01:21:12.054779 Final RX Vref Byte 0 = 52 to rank0
1846 01:21:12.057289 Final RX Vref Byte 1 = 62 to rank0
1847 01:21:12.060738 Final RX Vref Byte 0 = 52 to rank1
1848 01:21:12.064141 Final RX Vref Byte 1 = 62 to rank1==
1849 01:21:12.067758 Dram Type= 6, Freq= 0, CH_1, rank 0
1850 01:21:12.073898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1851 01:21:12.074487 ==
1852 01:21:12.074861 DQS Delay:
1853 01:21:12.077755 DQS0 = 0, DQS1 = 0
1854 01:21:12.078350 DQM Delay:
1855 01:21:12.078728 DQM0 = 86, DQM1 = 79
1856 01:21:12.080756 DQ Delay:
1857 01:21:12.084019 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
1858 01:21:12.087306 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1859 01:21:12.090791 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1860 01:21:12.093986 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1861 01:21:12.094459
1862 01:21:12.094827
1863 01:21:12.100744 [DQSOSCAuto] RK0, (LSB)MR18= 0x2815, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 399 ps
1864 01:21:12.103720 CH1 RK0: MR19=606, MR18=2815
1865 01:21:12.110157 CH1_RK0: MR19=0x606, MR18=0x2815, DQSOSC=399, MR23=63, INC=92, DEC=61
1866 01:21:12.110639
1867 01:21:12.113712 ----->DramcWriteLeveling(PI) begin...
1868 01:21:12.114294 ==
1869 01:21:12.117259 Dram Type= 6, Freq= 0, CH_1, rank 1
1870 01:21:12.120791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1871 01:21:12.121420 ==
1872 01:21:12.123562 Write leveling (Byte 0): 29 => 29
1873 01:21:12.126765 Write leveling (Byte 1): 29 => 29
1874 01:21:12.130411 DramcWriteLeveling(PI) end<-----
1875 01:21:12.130887
1876 01:21:12.131256 ==
1877 01:21:12.133547 Dram Type= 6, Freq= 0, CH_1, rank 1
1878 01:21:12.137225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1879 01:21:12.137860 ==
1880 01:21:12.139820 [Gating] SW mode calibration
1881 01:21:12.146772 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1882 01:21:12.153507 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1883 01:21:12.157049 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1884 01:21:12.163502 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1885 01:21:12.166522 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1886 01:21:12.170581 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 01:21:12.176226 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 01:21:12.180322 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 01:21:12.183496 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 01:21:12.189875 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 01:21:12.193029 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 01:21:12.196514 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 01:21:12.203485 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 01:21:12.206563 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 01:21:12.209552 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 01:21:12.213502 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 01:21:12.219830 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 01:21:12.222945 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 01:21:12.226177 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 01:21:12.232850 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1901 01:21:12.236621 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 01:21:12.239522 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 01:21:12.246029 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 01:21:12.249469 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 01:21:12.252945 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 01:21:12.259909 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 01:21:12.263094 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 01:21:12.265843 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 01:21:12.272670 0 9 8 | B1->B0 | 3131 2727 | 0 0 | (0 0) (0 0)
1910 01:21:12.275870 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 01:21:12.279164 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 01:21:12.285948 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 01:21:12.289226 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 01:21:12.292375 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1915 01:21:12.299546 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1916 01:21:12.302630 0 10 4 | B1->B0 | 3030 3232 | 1 1 | (1 1) (1 1)
1917 01:21:12.305467 0 10 8 | B1->B0 | 2424 2e2e | 0 1 | (0 0) (1 0)
1918 01:21:12.312430 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 01:21:12.315341 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 01:21:12.318919 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 01:21:12.325659 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 01:21:12.328926 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 01:21:12.332362 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 01:21:12.338410 0 11 4 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
1925 01:21:12.342037 0 11 8 | B1->B0 | 3e3e 3434 | 0 1 | (0 0) (1 1)
1926 01:21:12.344936 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 01:21:12.352095 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 01:21:12.355384 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 01:21:12.358459 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 01:21:12.365482 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 01:21:12.368007 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 01:21:12.372010 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 01:21:12.378316 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1934 01:21:12.381208 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 01:21:12.384718 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 01:21:12.391537 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 01:21:12.394738 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 01:21:12.397994 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 01:21:12.404555 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 01:21:12.407803 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 01:21:12.411383 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 01:21:12.417590 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 01:21:12.421168 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 01:21:12.424529 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 01:21:12.431165 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 01:21:12.434684 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 01:21:12.437844 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 01:21:12.444255 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1949 01:21:12.447976 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1950 01:21:12.450823 Total UI for P1: 0, mck2ui 16
1951 01:21:12.454035 best dqsien dly found for B1: ( 0, 14, 4)
1952 01:21:12.457254 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1953 01:21:12.460595 Total UI for P1: 0, mck2ui 16
1954 01:21:12.464277 best dqsien dly found for B0: ( 0, 14, 8)
1955 01:21:12.467162 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1956 01:21:12.470815 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1957 01:21:12.471241
1958 01:21:12.473933 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1959 01:21:12.481066 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1960 01:21:12.481702 [Gating] SW calibration Done
1961 01:21:12.483925 ==
1962 01:21:12.484494 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 01:21:12.490784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 01:21:12.491384 ==
1965 01:21:12.491770 RX Vref Scan: 0
1966 01:21:12.492118
1967 01:21:12.493997 RX Vref 0 -> 0, step: 1
1968 01:21:12.494558
1969 01:21:12.497732 RX Delay -130 -> 252, step: 16
1970 01:21:12.500842 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1971 01:21:12.503995 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1972 01:21:12.510500 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1973 01:21:12.513851 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1974 01:21:12.517517 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1975 01:21:12.520211 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1976 01:21:12.523677 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1977 01:21:12.530615 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1978 01:21:12.534164 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1979 01:21:12.537031 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1980 01:21:12.540390 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1981 01:21:12.543673 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1982 01:21:12.550823 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1983 01:21:28.469859 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1984 01:21:28.470389 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1985 01:21:28.470763 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1986 01:21:28.471110 ==
1987 01:21:28.471443 Dram Type= 6, Freq= 0, CH_1, rank 1
1988 01:21:28.471771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1989 01:21:28.472092 ==
1990 01:21:28.472407 DQS Delay:
1991 01:21:28.472715 DQS0 = 0, DQS1 = 0
1992 01:21:28.473023 DQM Delay:
1993 01:21:28.473359 DQM0 = 88, DQM1 = 79
1994 01:21:28.473676 DQ Delay:
1995 01:21:28.473982 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1996 01:21:28.474285 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1997 01:21:28.474588 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1998 01:21:28.474884 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1999 01:21:28.475181
2000 01:21:28.475476
2001 01:21:28.475776 ==
2002 01:21:28.476072 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 01:21:28.476374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 01:21:28.476727 ==
2005 01:21:28.477077
2006 01:21:28.477404
2007 01:21:28.477709 TX Vref Scan disable
2008 01:21:28.478012 == TX Byte 0 ==
2009 01:21:28.478310 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2010 01:21:28.478613 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2011 01:21:28.478911 == TX Byte 1 ==
2012 01:21:28.479209 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2013 01:21:28.479508 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2014 01:21:28.479808 ==
2015 01:21:28.480105 Dram Type= 6, Freq= 0, CH_1, rank 1
2016 01:21:28.480408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2017 01:21:28.480709 ==
2018 01:21:28.481008 TX Vref=22, minBit 9, minWin=26, winSum=444
2019 01:21:28.481307 TX Vref=24, minBit 9, minWin=26, winSum=444
2020 01:21:28.481632 TX Vref=26, minBit 8, minWin=27, winSum=447
2021 01:21:28.481933 TX Vref=28, minBit 13, minWin=27, winSum=452
2022 01:21:28.482234 TX Vref=30, minBit 8, minWin=27, winSum=450
2023 01:21:28.482530 TX Vref=32, minBit 8, minWin=27, winSum=454
2024 01:21:28.482830 [TxChooseVref] Worse bit 8, Min win 27, Win sum 454, Final Vref 32
2025 01:21:28.483130
2026 01:21:28.483428 Final TX Range 1 Vref 32
2027 01:21:28.483729
2028 01:21:28.484026 ==
2029 01:21:28.484325 Dram Type= 6, Freq= 0, CH_1, rank 1
2030 01:21:28.484624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2031 01:21:28.484925 ==
2032 01:21:28.485221
2033 01:21:28.485551
2034 01:21:28.485847 TX Vref Scan disable
2035 01:21:28.486147 == TX Byte 0 ==
2036 01:21:28.486446 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2037 01:21:28.486749 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2038 01:21:28.487267 == TX Byte 1 ==
2039 01:21:28.487861 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2040 01:21:28.488279 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2041 01:21:28.488604
2042 01:21:28.489012 [DATLAT]
2043 01:21:28.489357 Freq=800, CH1 RK1
2044 01:21:28.489695
2045 01:21:28.489997 DATLAT Default: 0xa
2046 01:21:28.490302 0, 0xFFFF, sum = 0
2047 01:21:28.490612 1, 0xFFFF, sum = 0
2048 01:21:28.490918 2, 0xFFFF, sum = 0
2049 01:21:28.491220 3, 0xFFFF, sum = 0
2050 01:21:28.491522 4, 0xFFFF, sum = 0
2051 01:21:28.491820 5, 0xFFFF, sum = 0
2052 01:21:28.492122 6, 0xFFFF, sum = 0
2053 01:21:28.492423 7, 0xFFFF, sum = 0
2054 01:21:28.492723 8, 0xFFFF, sum = 0
2055 01:21:28.493090 9, 0x0, sum = 1
2056 01:21:28.493440 10, 0x0, sum = 2
2057 01:21:28.493786 11, 0x0, sum = 3
2058 01:21:28.494148 12, 0x0, sum = 4
2059 01:21:28.494455 best_step = 10
2060 01:21:28.494755
2061 01:21:28.495279 ==
2062 01:21:28.495814 Dram Type= 6, Freq= 0, CH_1, rank 1
2063 01:21:28.496144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2064 01:21:28.496475 ==
2065 01:21:28.496805 RX Vref Scan: 0
2066 01:21:28.497131
2067 01:21:28.497474 RX Vref 0 -> 0, step: 1
2068 01:21:28.497769
2069 01:21:28.497989 RX Delay -95 -> 252, step: 8
2070 01:21:28.498205 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
2071 01:21:28.498423 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2072 01:21:28.498638 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2073 01:21:28.498851 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2074 01:21:28.499063 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2075 01:21:28.499274 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2076 01:21:28.499489 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2077 01:21:28.499703 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2078 01:21:28.499915 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2079 01:21:28.500127 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2080 01:21:28.500338 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2081 01:21:28.500549 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2082 01:21:28.500773 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2083 01:21:28.500990 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2084 01:21:28.501204 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2085 01:21:28.501457 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2086 01:21:28.501678 ==
2087 01:21:28.501893 Dram Type= 6, Freq= 0, CH_1, rank 1
2088 01:21:28.502111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2089 01:21:28.502328 ==
2090 01:21:28.502540 DQS Delay:
2091 01:21:28.502698 DQS0 = 0, DQS1 = 0
2092 01:21:28.502885 DQM Delay:
2093 01:21:28.503048 DQM0 = 86, DQM1 = 78
2094 01:21:28.503205 DQ Delay:
2095 01:21:28.503362 DQ0 =88, DQ1 =80, DQ2 =76, DQ3 =84
2096 01:21:28.503520 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2097 01:21:28.503679 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2098 01:21:28.503836 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2099 01:21:28.503994
2100 01:21:28.504151
2101 01:21:28.504309 [DQSOSCAuto] RK1, (LSB)MR18= 0x130c, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2102 01:21:28.504471 CH1 RK1: MR19=606, MR18=130C
2103 01:21:28.504629 CH1_RK1: MR19=0x606, MR18=0x130C, DQSOSC=405, MR23=63, INC=90, DEC=60
2104 01:21:28.504790 [RxdqsGatingPostProcess] freq 800
2105 01:21:28.504950 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2106 01:21:28.505108 Pre-setting of DQS Precalculation
2107 01:21:28.505282 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2108 01:21:28.505496 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2109 01:21:28.505666 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2110 01:21:28.505833
2111 01:21:28.506018
2112 01:21:28.506184 [Calibration Summary] 1600 Mbps
2113 01:21:28.506345 CH 0, Rank 0
2114 01:21:28.506505 SW Impedance : PASS
2115 01:21:28.506664 DUTY Scan : NO K
2116 01:21:28.506824 ZQ Calibration : PASS
2117 01:21:28.507096 Jitter Meter : NO K
2118 01:21:28.507378 CBT Training : PASS
2119 01:21:28.507625 Write leveling : PASS
2120 01:21:28.507820 RX DQS gating : PASS
2121 01:21:28.507959 RX DQ/DQS(RDDQC) : PASS
2122 01:21:28.508087 TX DQ/DQS : PASS
2123 01:21:28.508234 RX DATLAT : PASS
2124 01:21:28.508373 RX DQ/DQS(Engine): PASS
2125 01:21:28.508500 TX OE : NO K
2126 01:21:28.508626 All Pass.
2127 01:21:28.508753
2128 01:21:28.508878 CH 0, Rank 1
2129 01:21:28.509264 SW Impedance : PASS
2130 01:21:28.509449 DUTY Scan : NO K
2131 01:21:28.509588 ZQ Calibration : PASS
2132 01:21:28.509716 Jitter Meter : NO K
2133 01:21:28.509848 CBT Training : PASS
2134 01:21:28.509989 Write leveling : PASS
2135 01:21:28.510123 RX DQS gating : PASS
2136 01:21:28.510249 RX DQ/DQS(RDDQC) : PASS
2137 01:21:28.510375 TX DQ/DQS : PASS
2138 01:21:28.510503 RX DATLAT : PASS
2139 01:21:28.510630 RX DQ/DQS(Engine): PASS
2140 01:21:28.510755 TX OE : NO K
2141 01:21:28.510884 All Pass.
2142 01:21:28.511032
2143 01:21:28.511161 CH 1, Rank 0
2144 01:21:28.511287 SW Impedance : PASS
2145 01:21:28.511412 DUTY Scan : NO K
2146 01:21:28.511539 ZQ Calibration : PASS
2147 01:21:28.511664 Jitter Meter : NO K
2148 01:21:28.511789 CBT Training : PASS
2149 01:21:28.511912 Write leveling : PASS
2150 01:21:28.512092 RX DQS gating : PASS
2151 01:21:28.512310 RX DQ/DQS(RDDQC) : PASS
2152 01:21:28.512522 TX DQ/DQS : PASS
2153 01:21:28.512715 RX DATLAT : PASS
2154 01:21:28.512883 RX DQ/DQS(Engine): PASS
2155 01:21:28.513044 TX OE : NO K
2156 01:21:28.513223 All Pass.
2157 01:21:28.513401
2158 01:21:28.513563 CH 1, Rank 1
2159 01:21:28.513723 SW Impedance : PASS
2160 01:21:28.513883 DUTY Scan : NO K
2161 01:21:28.514043 ZQ Calibration : PASS
2162 01:21:28.514189 Jitter Meter : NO K
2163 01:21:28.514324 CBT Training : PASS
2164 01:21:28.514434 Write leveling : PASS
2165 01:21:28.514539 RX DQS gating : PASS
2166 01:21:28.514643 RX DQ/DQS(RDDQC) : PASS
2167 01:21:28.514754 TX DQ/DQS : PASS
2168 01:21:28.514884 RX DATLAT : PASS
2169 01:21:28.514990 RX DQ/DQS(Engine): PASS
2170 01:21:28.515095 TX OE : NO K
2171 01:21:28.515199 All Pass.
2172 01:21:28.515303
2173 01:21:28.515406 DramC Write-DBI off
2174 01:21:28.515511 PER_BANK_REFRESH: Hybrid Mode
2175 01:21:28.515615 TX_TRACKING: ON
2176 01:21:28.515720 [GetDramInforAfterCalByMRR] Vendor 6.
2177 01:21:28.515825 [GetDramInforAfterCalByMRR] Revision 606.
2178 01:21:28.515927 [GetDramInforAfterCalByMRR] Revision 2 0.
2179 01:21:28.516030 MR0 0x3b3b
2180 01:21:28.516132 MR8 0x5151
2181 01:21:28.516236 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2182 01:21:28.516338
2183 01:21:28.516441 MR0 0x3b3b
2184 01:21:28.516543 MR8 0x5151
2185 01:21:28.516645 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2186 01:21:28.516749
2187 01:21:28.516853 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2188 01:21:28.516994 [FAST_K] Save calibration result to emmc
2189 01:21:28.517175 [FAST_K] Save calibration result to emmc
2190 01:21:28.517360 dram_init: config_dvfs: 1
2191 01:21:28.517489 dramc_set_vcore_voltage set vcore to 662500
2192 01:21:28.517580 Read voltage for 1200, 2
2193 01:21:28.517668 Vio18 = 0
2194 01:21:28.517756 Vcore = 662500
2195 01:21:28.517843 Vdram = 0
2196 01:21:28.517932 Vddq = 0
2197 01:21:28.518020 Vmddr = 0
2198 01:21:28.518108 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2199 01:21:28.518197 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2200 01:21:28.518287 MEM_TYPE=3, freq_sel=15
2201 01:21:28.518376 sv_algorithm_assistance_LP4_1600
2202 01:21:28.518464 ============ PULL DRAM RESETB DOWN ============
2203 01:21:28.518553 ========== PULL DRAM RESETB DOWN end =========
2204 01:21:28.518642 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2205 01:21:28.518731 ===================================
2206 01:21:28.518821 LPDDR4 DRAM CONFIGURATION
2207 01:21:28.518908 ===================================
2208 01:21:28.518997 EX_ROW_EN[0] = 0x0
2209 01:21:28.519086 EX_ROW_EN[1] = 0x0
2210 01:21:28.519174 LP4Y_EN = 0x0
2211 01:21:28.519263 WORK_FSP = 0x0
2212 01:21:28.519350 WL = 0x4
2213 01:21:28.519438 RL = 0x4
2214 01:21:28.519526 BL = 0x2
2215 01:21:28.519614 RPST = 0x0
2216 01:21:28.519701 RD_PRE = 0x0
2217 01:21:28.519790 WR_PRE = 0x1
2218 01:21:28.519876 WR_PST = 0x0
2219 01:21:28.519964 DBI_WR = 0x0
2220 01:21:28.520051 DBI_RD = 0x0
2221 01:21:28.520138 OTF = 0x1
2222 01:21:28.520226 ===================================
2223 01:21:28.520315 ===================================
2224 01:21:28.520402 ANA top config
2225 01:21:28.520489 ===================================
2226 01:21:28.520578 DLL_ASYNC_EN = 0
2227 01:21:28.520666 ALL_SLAVE_EN = 0
2228 01:21:28.520753 NEW_RANK_MODE = 1
2229 01:21:28.520842 DLL_IDLE_MODE = 1
2230 01:21:28.520930 LP45_APHY_COMB_EN = 1
2231 01:21:28.521018 TX_ODT_DIS = 1
2232 01:21:28.521107 NEW_8X_MODE = 1
2233 01:21:28.521196 ===================================
2234 01:21:28.521284 ===================================
2235 01:21:28.521389 data_rate = 2400
2236 01:21:28.521480 CKR = 1
2237 01:21:28.521569 DQ_P2S_RATIO = 8
2238 01:21:28.521658 ===================================
2239 01:21:28.521746 CA_P2S_RATIO = 8
2240 01:21:28.521834 DQ_CA_OPEN = 0
2241 01:21:28.521922 DQ_SEMI_OPEN = 0
2242 01:21:28.522009 CA_SEMI_OPEN = 0
2243 01:21:28.522096 CA_FULL_RATE = 0
2244 01:21:28.522185 DQ_CKDIV4_EN = 0
2245 01:21:28.522273 CA_CKDIV4_EN = 0
2246 01:21:28.522360 CA_PREDIV_EN = 0
2247 01:21:28.522449 PH8_DLY = 17
2248 01:21:28.522546 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2249 01:21:28.522623 DQ_AAMCK_DIV = 4
2250 01:21:28.522698 CA_AAMCK_DIV = 4
2251 01:21:28.522775 CA_ADMCK_DIV = 4
2252 01:21:28.522851 DQ_TRACK_CA_EN = 0
2253 01:21:28.522928 CA_PICK = 1200
2254 01:21:28.523005 CA_MCKIO = 1200
2255 01:21:28.523082 MCKIO_SEMI = 0
2256 01:21:28.523159 PLL_FREQ = 2366
2257 01:21:28.523235 DQ_UI_PI_RATIO = 32
2258 01:21:28.523312 CA_UI_PI_RATIO = 0
2259 01:21:28.523389 ===================================
2260 01:21:28.523466 ===================================
2261 01:21:28.523542 memory_type:LPDDR4
2262 01:21:28.523619 GP_NUM : 10
2263 01:21:28.523695 SRAM_EN : 1
2264 01:21:28.523772 MD32_EN : 0
2265 01:21:28.523852 ===================================
2266 01:21:28.523930 [ANA_INIT] >>>>>>>>>>>>>>
2267 01:21:28.524009 <<<<<< [CONFIGURE PHASE]: ANA_TX
2268 01:21:28.524088 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2269 01:21:28.524165 ===================================
2270 01:21:28.524243 data_rate = 2400,PCW = 0X5b00
2271 01:21:28.524319 ===================================
2272 01:21:28.524397 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2273 01:21:28.524683 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2274 01:21:28.524772 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2275 01:21:28.524852 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2276 01:21:28.524930 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2277 01:21:28.525008 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2278 01:21:28.525086 [ANA_INIT] flow start
2279 01:21:28.525162 [ANA_INIT] PLL >>>>>>>>
2280 01:21:28.525239 [ANA_INIT] PLL <<<<<<<<
2281 01:21:28.525316 [ANA_INIT] MIDPI >>>>>>>>
2282 01:21:28.525408 [ANA_INIT] MIDPI <<<<<<<<
2283 01:21:28.525486 [ANA_INIT] DLL >>>>>>>>
2284 01:21:28.525563 [ANA_INIT] DLL <<<<<<<<
2285 01:21:28.525640 [ANA_INIT] flow end
2286 01:21:28.525717 ============ LP4 DIFF to SE enter ============
2287 01:21:28.525796 ============ LP4 DIFF to SE exit ============
2288 01:21:28.525874 [ANA_INIT] <<<<<<<<<<<<<
2289 01:21:28.525951 [Flow] Enable top DCM control >>>>>
2290 01:21:28.526029 [Flow] Enable top DCM control <<<<<
2291 01:21:28.526105 Enable DLL master slave shuffle
2292 01:21:28.526182 ==============================================================
2293 01:21:28.526260 Gating Mode config
2294 01:21:28.526337 ==============================================================
2295 01:21:28.526415 Config description:
2296 01:21:28.526492 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2297 01:21:28.526598 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2298 01:21:28.526681 SELPH_MODE 0: By rank 1: By Phase
2299 01:21:28.526763 ==============================================================
2300 01:21:28.526841 GAT_TRACK_EN = 1
2301 01:21:28.526920 RX_GATING_MODE = 2
2302 01:21:28.526996 RX_GATING_TRACK_MODE = 2
2303 01:21:28.527073 SELPH_MODE = 1
2304 01:21:28.527150 PICG_EARLY_EN = 1
2305 01:21:28.527226 VALID_LAT_VALUE = 1
2306 01:21:28.527304 ==============================================================
2307 01:21:28.527381 Enter into Gating configuration >>>>
2308 01:21:28.527458 Exit from Gating configuration <<<<
2309 01:21:28.527541 Enter into DVFS_PRE_config >>>>>
2310 01:21:28.527609 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2311 01:21:28.527679 Exit from DVFS_PRE_config <<<<<
2312 01:21:28.527747 Enter into PICG configuration >>>>
2313 01:21:28.527816 Exit from PICG configuration <<<<
2314 01:21:28.527884 [RX_INPUT] configuration >>>>>
2315 01:21:28.527952 [RX_INPUT] configuration <<<<<
2316 01:21:28.528020 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2317 01:21:28.528089 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2318 01:21:28.528158 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2319 01:21:28.528227 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2320 01:21:28.528296 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2321 01:21:28.528365 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2322 01:21:28.528433 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2323 01:21:28.528501 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2324 01:21:28.528569 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2325 01:21:28.528637 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2326 01:21:28.528706 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2327 01:21:28.528774 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2328 01:21:28.528842 ===================================
2329 01:21:28.528911 LPDDR4 DRAM CONFIGURATION
2330 01:21:28.529000 ===================================
2331 01:21:28.529120 EX_ROW_EN[0] = 0x0
2332 01:21:28.529197 EX_ROW_EN[1] = 0x0
2333 01:21:28.529267 LP4Y_EN = 0x0
2334 01:21:28.529346 WORK_FSP = 0x0
2335 01:21:28.529418 WL = 0x4
2336 01:21:28.529487 RL = 0x4
2337 01:21:28.529555 BL = 0x2
2338 01:21:28.529622 RPST = 0x0
2339 01:21:28.529691 RD_PRE = 0x0
2340 01:21:28.529759 WR_PRE = 0x1
2341 01:21:28.529827 WR_PST = 0x0
2342 01:21:28.529895 DBI_WR = 0x0
2343 01:21:28.529963 DBI_RD = 0x0
2344 01:21:28.530030 OTF = 0x1
2345 01:21:28.530099 ===================================
2346 01:21:28.530168 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2347 01:21:28.530237 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2348 01:21:28.530306 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2349 01:21:28.530374 ===================================
2350 01:21:28.530442 LPDDR4 DRAM CONFIGURATION
2351 01:21:28.530510 ===================================
2352 01:21:28.530578 EX_ROW_EN[0] = 0x10
2353 01:21:28.530646 EX_ROW_EN[1] = 0x0
2354 01:21:28.530714 LP4Y_EN = 0x0
2355 01:21:28.530781 WORK_FSP = 0x0
2356 01:21:28.530849 WL = 0x4
2357 01:21:28.530917 RL = 0x4
2358 01:21:28.530985 BL = 0x2
2359 01:21:28.531053 RPST = 0x0
2360 01:21:28.531120 RD_PRE = 0x0
2361 01:21:28.531188 WR_PRE = 0x1
2362 01:21:28.531255 WR_PST = 0x0
2363 01:21:28.531338 DBI_WR = 0x0
2364 01:21:28.531409 DBI_RD = 0x0
2365 01:21:28.531476 OTF = 0x1
2366 01:21:28.531544 ===================================
2367 01:21:28.531612 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2368 01:21:28.531680 ==
2369 01:21:28.531747 Dram Type= 6, Freq= 0, CH_0, rank 0
2370 01:21:28.531815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2371 01:21:28.531883 ==
2372 01:21:28.531950 [Duty_Offset_Calibration]
2373 01:21:28.532017 B0:1 B1:-1 CA:0
2374 01:21:28.532085
2375 01:21:28.532151 [DutyScan_Calibration_Flow] k_type=0
2376 01:21:28.532219
2377 01:21:28.532286 ==CLK 0==
2378 01:21:28.532354 Final CLK duty delay cell = 0
2379 01:21:28.532422 [0] MAX Duty = 5125%(X100), DQS PI = 24
2380 01:21:28.532502 [0] MIN Duty = 4875%(X100), DQS PI = 8
2381 01:21:28.532563 [0] AVG Duty = 5000%(X100)
2382 01:21:28.532623
2383 01:21:28.532683 CH0 CLK Duty spec in!! Max-Min= 250%
2384 01:21:28.532743 [DutyScan_Calibration_Flow] ====Done====
2385 01:21:28.532803
2386 01:21:28.532863 [DutyScan_Calibration_Flow] k_type=1
2387 01:21:28.532924
2388 01:21:28.532983 ==DQS 0 ==
2389 01:21:28.533043 Final DQS duty delay cell = -4
2390 01:21:28.533302 [-4] MAX Duty = 5062%(X100), DQS PI = 18
2391 01:21:28.533388 [-4] MIN Duty = 4875%(X100), DQS PI = 8
2392 01:21:28.533452 [-4] AVG Duty = 4968%(X100)
2393 01:21:28.533514
2394 01:21:28.533574 ==DQS 1 ==
2395 01:21:28.533636 Final DQS duty delay cell = 0
2396 01:21:28.533697 [0] MAX Duty = 5125%(X100), DQS PI = 56
2397 01:21:28.533758 [0] MIN Duty = 5000%(X100), DQS PI = 20
2398 01:21:28.533818 [0] AVG Duty = 5062%(X100)
2399 01:21:28.533879
2400 01:21:28.533939 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2401 01:21:28.534000
2402 01:21:28.534060 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2403 01:21:28.534121 [DutyScan_Calibration_Flow] ====Done====
2404 01:21:28.534184
2405 01:21:28.534245 [DutyScan_Calibration_Flow] k_type=3
2406 01:21:28.534306
2407 01:21:28.534366 ==DQM 0 ==
2408 01:21:28.534427 Final DQM duty delay cell = 0
2409 01:21:28.534488 [0] MAX Duty = 5062%(X100), DQS PI = 22
2410 01:21:28.534549 [0] MIN Duty = 4844%(X100), DQS PI = 8
2411 01:21:28.534609 [0] AVG Duty = 4953%(X100)
2412 01:21:28.534670
2413 01:21:28.534730 ==DQM 1 ==
2414 01:21:28.534790 Final DQM duty delay cell = 4
2415 01:21:28.534851 [4] MAX Duty = 5187%(X100), DQS PI = 14
2416 01:21:28.534912 [4] MIN Duty = 5000%(X100), DQS PI = 22
2417 01:21:28.534979 [4] AVG Duty = 5093%(X100)
2418 01:21:28.535040
2419 01:21:28.535101 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2420 01:21:28.535162
2421 01:21:28.535222 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2422 01:21:28.535282 [DutyScan_Calibration_Flow] ====Done====
2423 01:21:28.535342
2424 01:21:28.535402 [DutyScan_Calibration_Flow] k_type=2
2425 01:21:28.535463
2426 01:21:28.535523 ==DQ 0 ==
2427 01:21:28.535587 Final DQ duty delay cell = -4
2428 01:21:28.535648 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2429 01:21:28.535709 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2430 01:21:28.535769 [-4] AVG Duty = 4953%(X100)
2431 01:21:28.535829
2432 01:21:28.535889 ==DQ 1 ==
2433 01:21:28.535950 Final DQ duty delay cell = -4
2434 01:21:28.536011 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2435 01:21:28.536071 [-4] MIN Duty = 4876%(X100), DQS PI = 14
2436 01:21:28.536132 [-4] AVG Duty = 4922%(X100)
2437 01:21:28.536192
2438 01:21:28.536251 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2439 01:21:28.536311
2440 01:21:28.536370 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2441 01:21:28.536431 [DutyScan_Calibration_Flow] ====Done====
2442 01:21:28.536490 ==
2443 01:21:28.536551 Dram Type= 6, Freq= 0, CH_1, rank 0
2444 01:21:28.536611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2445 01:21:28.536673 ==
2446 01:21:28.536734 [Duty_Offset_Calibration]
2447 01:21:28.536795 B0:-1 B1:1 CA:1
2448 01:21:28.536856
2449 01:21:28.536916 [DutyScan_Calibration_Flow] k_type=0
2450 01:21:28.536982
2451 01:21:28.537043 ==CLK 0==
2452 01:21:28.537104 Final CLK duty delay cell = 0
2453 01:21:28.537164 [0] MAX Duty = 5187%(X100), DQS PI = 22
2454 01:21:28.537224 [0] MIN Duty = 4969%(X100), DQS PI = 60
2455 01:21:28.537284 [0] AVG Duty = 5078%(X100)
2456 01:21:28.537353
2457 01:21:28.537416 CH1 CLK Duty spec in!! Max-Min= 218%
2458 01:21:28.537476 [DutyScan_Calibration_Flow] ====Done====
2459 01:21:28.537549
2460 01:21:28.537603 [DutyScan_Calibration_Flow] k_type=1
2461 01:21:28.537658
2462 01:21:28.537711 ==DQS 0 ==
2463 01:21:28.537767 Final DQS duty delay cell = 0
2464 01:21:28.537822 [0] MAX Duty = 5125%(X100), DQS PI = 18
2465 01:21:28.537878 [0] MIN Duty = 4875%(X100), DQS PI = 6
2466 01:21:28.537933 [0] AVG Duty = 5000%(X100)
2467 01:21:28.537987
2468 01:21:28.538042 ==DQS 1 ==
2469 01:21:28.538096 Final DQS duty delay cell = 0
2470 01:21:28.538151 [0] MAX Duty = 5062%(X100), DQS PI = 10
2471 01:21:28.538211 [0] MIN Duty = 4969%(X100), DQS PI = 56
2472 01:21:28.538266 [0] AVG Duty = 5015%(X100)
2473 01:21:28.538320
2474 01:21:28.538377 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2475 01:21:28.538433
2476 01:21:28.538488 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2477 01:21:28.538542 [DutyScan_Calibration_Flow] ====Done====
2478 01:21:28.538597
2479 01:21:28.538651 [DutyScan_Calibration_Flow] k_type=3
2480 01:21:28.538708
2481 01:21:28.538764 ==DQM 0 ==
2482 01:21:28.538825 Final DQM duty delay cell = -4
2483 01:21:28.538880 [-4] MAX Duty = 5062%(X100), DQS PI = 36
2484 01:21:28.538940 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2485 01:21:28.538999 [-4] AVG Duty = 4953%(X100)
2486 01:21:28.539055
2487 01:21:28.539110 ==DQM 1 ==
2488 01:21:28.539164 Final DQM duty delay cell = 0
2489 01:21:28.539221 [0] MAX Duty = 5156%(X100), DQS PI = 6
2490 01:21:28.539277 [0] MIN Duty = 4969%(X100), DQS PI = 28
2491 01:21:28.539332 [0] AVG Duty = 5062%(X100)
2492 01:21:28.539387
2493 01:21:28.539441 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2494 01:21:28.539496
2495 01:21:28.539550 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2496 01:21:28.539605 [DutyScan_Calibration_Flow] ====Done====
2497 01:21:28.539660
2498 01:21:28.539714 [DutyScan_Calibration_Flow] k_type=2
2499 01:21:28.539769
2500 01:21:28.539822 ==DQ 0 ==
2501 01:21:28.539878 Final DQ duty delay cell = 0
2502 01:21:28.539933 [0] MAX Duty = 5187%(X100), DQS PI = 32
2503 01:21:28.539988 [0] MIN Duty = 4876%(X100), DQS PI = 8
2504 01:21:28.540043 [0] AVG Duty = 5031%(X100)
2505 01:21:28.540097
2506 01:21:28.540151 ==DQ 1 ==
2507 01:21:28.540206 Final DQ duty delay cell = 0
2508 01:21:28.540261 [0] MAX Duty = 5124%(X100), DQS PI = 10
2509 01:21:28.540316 [0] MIN Duty = 4969%(X100), DQS PI = 58
2510 01:21:28.540371 [0] AVG Duty = 5046%(X100)
2511 01:21:28.540426
2512 01:21:28.540480 CH1 DQ 0 Duty spec in!! Max-Min= 311%
2513 01:21:28.540535
2514 01:21:28.540589 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2515 01:21:28.540644 [DutyScan_Calibration_Flow] ====Done====
2516 01:21:28.540698 nWR fixed to 30
2517 01:21:28.540753 [ModeRegInit_LP4] CH0 RK0
2518 01:21:28.540807 [ModeRegInit_LP4] CH0 RK1
2519 01:21:28.540861 [ModeRegInit_LP4] CH1 RK0
2520 01:21:28.540924 [ModeRegInit_LP4] CH1 RK1
2521 01:21:28.541019 match AC timing 7
2522 01:21:28.541081 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2523 01:21:28.541137 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2524 01:21:28.541192 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2525 01:21:28.541247 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2526 01:21:28.541303 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2527 01:21:28.541368 ==
2528 01:21:28.541425 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 01:21:28.541480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2530 01:21:28.541536 ==
2531 01:21:28.541592 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2532 01:21:28.541647 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2533 01:21:28.541703 [CA 0] Center 39 (9~70) winsize 62
2534 01:21:28.541758 [CA 1] Center 39 (9~69) winsize 61
2535 01:21:28.541813 [CA 2] Center 35 (5~66) winsize 62
2536 01:21:28.541868 [CA 3] Center 35 (5~66) winsize 62
2537 01:21:28.541927 [CA 4] Center 33 (4~63) winsize 60
2538 01:21:28.541982 [CA 5] Center 33 (3~63) winsize 61
2539 01:21:28.542036
2540 01:21:28.542091 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2541 01:21:28.542149
2542 01:21:28.542408 [CATrainingPosCal] consider 1 rank data
2543 01:21:28.542477 u2DelayCellTimex100 = 270/100 ps
2544 01:21:28.542550 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2545 01:21:28.542608 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2546 01:21:28.542662 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2547 01:21:28.542715 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2548 01:21:28.542767 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2549 01:21:28.542819 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2550 01:21:28.542871
2551 01:21:28.542924 CA PerBit enable=1, Macro0, CA PI delay=33
2552 01:21:28.542976
2553 01:21:28.543028 [CBTSetCACLKResult] CA Dly = 33
2554 01:21:28.543081 CS Dly: 8 (0~39)
2555 01:21:28.543133 ==
2556 01:21:28.543187 Dram Type= 6, Freq= 0, CH_0, rank 1
2557 01:21:28.543239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2558 01:21:28.543293 ==
2559 01:21:28.543346 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2560 01:21:28.543399 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2561 01:21:28.543452 [CA 0] Center 39 (8~70) winsize 63
2562 01:21:28.543504 [CA 1] Center 39 (9~70) winsize 62
2563 01:21:28.543556 [CA 2] Center 35 (5~66) winsize 62
2564 01:21:28.543608 [CA 3] Center 34 (4~65) winsize 62
2565 01:21:28.543660 [CA 4] Center 33 (3~64) winsize 62
2566 01:21:28.543712 [CA 5] Center 33 (3~63) winsize 61
2567 01:21:28.543764
2568 01:21:28.543817 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2569 01:21:28.543870
2570 01:21:28.543923 [CATrainingPosCal] consider 2 rank data
2571 01:21:28.543976 u2DelayCellTimex100 = 270/100 ps
2572 01:21:28.544028 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2573 01:21:28.544081 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2574 01:21:28.544133 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2575 01:21:28.544186 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2576 01:21:28.544238 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2577 01:21:28.544291 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2578 01:21:28.544343
2579 01:21:28.544396 CA PerBit enable=1, Macro0, CA PI delay=33
2580 01:21:28.544449
2581 01:21:28.544501 [CBTSetCACLKResult] CA Dly = 33
2582 01:21:28.544553 CS Dly: 9 (0~41)
2583 01:21:28.544605
2584 01:21:28.544657 ----->DramcWriteLeveling(PI) begin...
2585 01:21:28.544711 ==
2586 01:21:28.544764 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 01:21:28.544816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 01:21:28.544869 ==
2589 01:21:28.544921 Write leveling (Byte 0): 31 => 31
2590 01:21:28.545010 Write leveling (Byte 1): 28 => 28
2591 01:21:28.545098 DramcWriteLeveling(PI) end<-----
2592 01:21:28.545175
2593 01:21:28.545228 ==
2594 01:21:28.545281 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 01:21:28.545356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 01:21:28.545412 ==
2597 01:21:28.545465 [Gating] SW mode calibration
2598 01:21:28.545518 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2599 01:21:28.545572 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2600 01:21:28.545625 0 15 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2601 01:21:28.545678 0 15 4 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2602 01:21:28.545731 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2603 01:21:28.545784 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2604 01:21:28.545837 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2605 01:21:28.545890 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2606 01:21:28.545942 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2607 01:21:28.545995 0 15 28 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 1)
2608 01:21:28.546049 1 0 0 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
2609 01:21:28.546102 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 01:21:28.546154 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 01:21:28.546207 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 01:21:28.546260 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2613 01:21:28.546312 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 01:21:28.546365 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2615 01:21:28.546417 1 0 28 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
2616 01:21:28.546469 1 1 0 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
2617 01:21:28.546522 1 1 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2618 01:21:28.546575 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 01:21:28.546627 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 01:21:28.546679 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 01:21:28.546732 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 01:21:28.546785 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 01:21:28.546838 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2624 01:21:28.546891 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2625 01:21:28.546943 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2626 01:21:28.546996 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 01:21:28.547049 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 01:21:28.547101 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 01:21:28.547154 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 01:21:28.547206 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 01:21:28.547259 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 01:21:28.547312 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 01:21:28.547365 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 01:21:28.547417 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 01:21:28.547470 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 01:21:28.547541 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 01:21:28.547596 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 01:21:28.547664 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 01:21:28.547739 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2640 01:21:28.547822 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2641 01:21:28.547905 Total UI for P1: 0, mck2ui 16
2642 01:21:28.547982 best dqsien dly found for B0: ( 1, 3, 28)
2643 01:21:28.548043 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2644 01:21:28.548127 Total UI for P1: 0, mck2ui 16
2645 01:21:28.548410 best dqsien dly found for B1: ( 1, 4, 0)
2646 01:21:28.548499 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2647 01:21:28.548583 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2648 01:21:28.548665
2649 01:21:28.548750 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2650 01:21:28.548839 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2651 01:21:28.548922 [Gating] SW calibration Done
2652 01:21:28.549003 ==
2653 01:21:28.549086 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 01:21:28.549169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 01:21:28.549251 ==
2656 01:21:28.549341 RX Vref Scan: 0
2657 01:21:28.549437
2658 01:21:28.549491 RX Vref 0 -> 0, step: 1
2659 01:21:28.549544
2660 01:21:28.549597 RX Delay -40 -> 252, step: 8
2661 01:21:28.549650 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2662 01:21:28.549702 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2663 01:21:28.549772 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2664 01:21:28.549826 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2665 01:21:28.549887 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2666 01:21:28.549952 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2667 01:21:28.550007 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2668 01:21:28.550060 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2669 01:21:28.550112 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2670 01:21:28.550165 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2671 01:21:28.550218 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2672 01:21:28.550270 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2673 01:21:28.550322 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2674 01:21:28.550383 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2675 01:21:28.550449 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2676 01:21:28.550504 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2677 01:21:28.550557 ==
2678 01:21:28.550610 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 01:21:28.550663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 01:21:28.550717 ==
2681 01:21:28.550770 DQS Delay:
2682 01:21:28.550823 DQS0 = 0, DQS1 = 0
2683 01:21:28.550876 DQM Delay:
2684 01:21:28.550929 DQM0 = 119, DQM1 = 106
2685 01:21:28.550982 DQ Delay:
2686 01:21:28.551035 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2687 01:21:28.551088 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2688 01:21:28.551141 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2689 01:21:28.551194 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2690 01:21:28.551246
2691 01:21:28.551298
2692 01:21:28.551350 ==
2693 01:21:28.551403 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 01:21:28.551455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 01:21:28.551508 ==
2696 01:21:28.551561
2697 01:21:28.551613
2698 01:21:28.551664 TX Vref Scan disable
2699 01:21:28.551717 == TX Byte 0 ==
2700 01:21:28.551770 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2701 01:21:28.551823 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2702 01:21:28.551876 == TX Byte 1 ==
2703 01:21:28.551928 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2704 01:21:28.551981 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2705 01:21:28.552033 ==
2706 01:21:28.552087 Dram Type= 6, Freq= 0, CH_0, rank 0
2707 01:21:28.552139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2708 01:21:28.552192 ==
2709 01:21:28.552244 TX Vref=22, minBit 4, minWin=25, winSum=415
2710 01:21:28.552298 TX Vref=24, minBit 0, minWin=26, winSum=419
2711 01:21:28.552350 TX Vref=26, minBit 1, minWin=25, winSum=422
2712 01:21:28.552403 TX Vref=28, minBit 13, minWin=25, winSum=427
2713 01:21:28.552455 TX Vref=30, minBit 1, minWin=26, winSum=428
2714 01:21:28.552508 TX Vref=32, minBit 5, minWin=26, winSum=429
2715 01:21:28.552560 [TxChooseVref] Worse bit 5, Min win 26, Win sum 429, Final Vref 32
2716 01:21:28.552613
2717 01:21:28.552665 Final TX Range 1 Vref 32
2718 01:21:28.552718
2719 01:21:28.552770 ==
2720 01:21:28.552822 Dram Type= 6, Freq= 0, CH_0, rank 0
2721 01:21:28.552875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2722 01:21:28.552928 ==
2723 01:21:28.552981
2724 01:21:28.553032
2725 01:21:28.553085 TX Vref Scan disable
2726 01:21:28.553137 == TX Byte 0 ==
2727 01:21:28.553189 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2728 01:21:28.553242 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2729 01:21:28.553295 == TX Byte 1 ==
2730 01:21:28.553376 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2731 01:21:28.553445 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2732 01:21:28.553498
2733 01:21:28.553550 [DATLAT]
2734 01:21:28.553602 Freq=1200, CH0 RK0
2735 01:21:28.553655
2736 01:21:28.553707 DATLAT Default: 0xd
2737 01:21:28.553760 0, 0xFFFF, sum = 0
2738 01:21:28.553814 1, 0xFFFF, sum = 0
2739 01:21:28.553867 2, 0xFFFF, sum = 0
2740 01:21:28.553920 3, 0xFFFF, sum = 0
2741 01:21:28.553973 4, 0xFFFF, sum = 0
2742 01:21:28.554026 5, 0xFFFF, sum = 0
2743 01:21:28.554080 6, 0xFFFF, sum = 0
2744 01:21:28.554133 7, 0xFFFF, sum = 0
2745 01:21:28.554186 8, 0xFFFF, sum = 0
2746 01:21:28.554239 9, 0xFFFF, sum = 0
2747 01:21:28.554292 10, 0xFFFF, sum = 0
2748 01:21:28.554345 11, 0xFFFF, sum = 0
2749 01:21:28.554398 12, 0x0, sum = 1
2750 01:21:28.554451 13, 0x0, sum = 2
2751 01:21:28.554504 14, 0x0, sum = 3
2752 01:21:28.554557 15, 0x0, sum = 4
2753 01:21:28.554610 best_step = 13
2754 01:21:28.554662
2755 01:21:28.554714 ==
2756 01:21:28.554767 Dram Type= 6, Freq= 0, CH_0, rank 0
2757 01:21:28.554820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2758 01:21:28.554873 ==
2759 01:21:28.554926 RX Vref Scan: 1
2760 01:21:28.554978
2761 01:21:28.555030 Set Vref Range= 32 -> 127
2762 01:21:28.555083
2763 01:21:28.555135 RX Vref 32 -> 127, step: 1
2764 01:21:28.555187
2765 01:21:28.555239 RX Delay -21 -> 252, step: 4
2766 01:21:28.555292
2767 01:21:28.555344 Set Vref, RX VrefLevel [Byte0]: 32
2768 01:21:28.555397 [Byte1]: 32
2769 01:21:28.555450
2770 01:21:28.555501 Set Vref, RX VrefLevel [Byte0]: 33
2771 01:21:28.555554 [Byte1]: 33
2772 01:21:28.555606
2773 01:21:28.555658 Set Vref, RX VrefLevel [Byte0]: 34
2774 01:21:28.555709 [Byte1]: 34
2775 01:21:28.555761
2776 01:21:28.555813 Set Vref, RX VrefLevel [Byte0]: 35
2777 01:21:28.555866 [Byte1]: 35
2778 01:21:28.555918
2779 01:21:28.555970 Set Vref, RX VrefLevel [Byte0]: 36
2780 01:21:28.556033 [Byte1]: 36
2781 01:21:28.556089
2782 01:21:28.556142 Set Vref, RX VrefLevel [Byte0]: 37
2783 01:21:28.556213 [Byte1]: 37
2784 01:21:28.556273
2785 01:21:28.556336 Set Vref, RX VrefLevel [Byte0]: 38
2786 01:21:28.556419 [Byte1]: 38
2787 01:21:28.556501
2788 01:21:28.556583 Set Vref, RX VrefLevel [Byte0]: 39
2789 01:21:28.556671 [Byte1]: 39
2790 01:21:28.556761
2791 01:21:28.556851 Set Vref, RX VrefLevel [Byte0]: 40
2792 01:21:28.556934 [Byte1]: 40
2793 01:21:28.557020
2794 01:21:28.557104 Set Vref, RX VrefLevel [Byte0]: 41
2795 01:21:28.557187 [Byte1]: 41
2796 01:21:28.557268
2797 01:21:28.557373 Set Vref, RX VrefLevel [Byte0]: 42
2798 01:21:28.557444 [Byte1]: 42
2799 01:21:28.557497
2800 01:21:28.557549 Set Vref, RX VrefLevel [Byte0]: 43
2801 01:21:28.557795 [Byte1]: 43
2802 01:21:28.557855
2803 01:21:28.557909 Set Vref, RX VrefLevel [Byte0]: 44
2804 01:21:28.557963 [Byte1]: 44
2805 01:21:28.558016
2806 01:21:28.558068 Set Vref, RX VrefLevel [Byte0]: 45
2807 01:21:28.558122 [Byte1]: 45
2808 01:21:28.558175
2809 01:21:28.558227 Set Vref, RX VrefLevel [Byte0]: 46
2810 01:21:28.558279 [Byte1]: 46
2811 01:21:28.558332
2812 01:21:28.558384 Set Vref, RX VrefLevel [Byte0]: 47
2813 01:21:28.558436 [Byte1]: 47
2814 01:21:28.558489
2815 01:21:28.558540 Set Vref, RX VrefLevel [Byte0]: 48
2816 01:21:28.558593 [Byte1]: 48
2817 01:21:28.558645
2818 01:21:28.558697 Set Vref, RX VrefLevel [Byte0]: 49
2819 01:21:28.558750 [Byte1]: 49
2820 01:21:28.558802
2821 01:21:28.558854 Set Vref, RX VrefLevel [Byte0]: 50
2822 01:21:28.558907 [Byte1]: 50
2823 01:21:28.558959
2824 01:21:28.559011 Set Vref, RX VrefLevel [Byte0]: 51
2825 01:21:28.559063 [Byte1]: 51
2826 01:21:28.559115
2827 01:21:28.559168 Set Vref, RX VrefLevel [Byte0]: 52
2828 01:21:28.559220 [Byte1]: 52
2829 01:21:28.559272
2830 01:21:28.559324 Set Vref, RX VrefLevel [Byte0]: 53
2831 01:21:28.559377 [Byte1]: 53
2832 01:21:28.559429
2833 01:21:28.559486 Set Vref, RX VrefLevel [Byte0]: 54
2834 01:21:28.559543 [Byte1]: 54
2835 01:21:28.559599
2836 01:21:28.559652 Set Vref, RX VrefLevel [Byte0]: 55
2837 01:21:28.559705 [Byte1]: 55
2838 01:21:28.559757
2839 01:21:28.559809 Set Vref, RX VrefLevel [Byte0]: 56
2840 01:21:28.559862 [Byte1]: 56
2841 01:21:28.559914
2842 01:21:28.559971 Set Vref, RX VrefLevel [Byte0]: 57
2843 01:21:28.560028 [Byte1]: 57
2844 01:21:28.560083
2845 01:21:28.560139 Set Vref, RX VrefLevel [Byte0]: 58
2846 01:21:28.560193 [Byte1]: 58
2847 01:21:28.560245
2848 01:21:28.560298 Set Vref, RX VrefLevel [Byte0]: 59
2849 01:21:28.560350 [Byte1]: 59
2850 01:21:28.560404
2851 01:21:28.560456 Set Vref, RX VrefLevel [Byte0]: 60
2852 01:21:28.560508 [Byte1]: 60
2853 01:21:28.560561
2854 01:21:28.560613 Set Vref, RX VrefLevel [Byte0]: 61
2855 01:21:28.560665 [Byte1]: 61
2856 01:21:28.560716
2857 01:21:28.560768 Set Vref, RX VrefLevel [Byte0]: 62
2858 01:21:28.560820 [Byte1]: 62
2859 01:21:28.560873
2860 01:21:28.560924 Set Vref, RX VrefLevel [Byte0]: 63
2861 01:21:28.560976 [Byte1]: 63
2862 01:21:28.561029
2863 01:21:28.561081 Set Vref, RX VrefLevel [Byte0]: 64
2864 01:21:28.561132 [Byte1]: 64
2865 01:21:28.561184
2866 01:21:28.561236 Set Vref, RX VrefLevel [Byte0]: 65
2867 01:21:28.561288 [Byte1]: 65
2868 01:21:28.561369
2869 01:21:28.561437 Set Vref, RX VrefLevel [Byte0]: 66
2870 01:21:28.561489 [Byte1]: 66
2871 01:21:28.561542
2872 01:21:28.561594 Set Vref, RX VrefLevel [Byte0]: 67
2873 01:21:28.561646 [Byte1]: 67
2874 01:21:28.561698
2875 01:21:28.561750 Set Vref, RX VrefLevel [Byte0]: 68
2876 01:21:28.561803 [Byte1]: 68
2877 01:21:28.561855
2878 01:21:28.561907 Set Vref, RX VrefLevel [Byte0]: 69
2879 01:21:28.561959 [Byte1]: 69
2880 01:21:28.562011
2881 01:21:28.562063 Set Vref, RX VrefLevel [Byte0]: 70
2882 01:21:28.562115 [Byte1]: 70
2883 01:21:28.562167
2884 01:21:28.562219 Set Vref, RX VrefLevel [Byte0]: 71
2885 01:21:28.562271 [Byte1]: 71
2886 01:21:28.562324
2887 01:21:28.562375 Set Vref, RX VrefLevel [Byte0]: 72
2888 01:21:28.562428 [Byte1]: 72
2889 01:21:28.562481
2890 01:21:28.562533 Set Vref, RX VrefLevel [Byte0]: 73
2891 01:21:28.562585 [Byte1]: 73
2892 01:21:28.562638
2893 01:21:28.562690 Set Vref, RX VrefLevel [Byte0]: 74
2894 01:21:28.562742 [Byte1]: 74
2895 01:21:28.562794
2896 01:21:28.562846 Set Vref, RX VrefLevel [Byte0]: 75
2897 01:21:28.562898 [Byte1]: 75
2898 01:21:28.562951
2899 01:21:28.563003 Set Vref, RX VrefLevel [Byte0]: 76
2900 01:21:28.563054 [Byte1]: 76
2901 01:21:28.563106
2902 01:21:28.563158 Set Vref, RX VrefLevel [Byte0]: 77
2903 01:21:28.563211 [Byte1]: 77
2904 01:21:28.563263
2905 01:21:28.563315 Set Vref, RX VrefLevel [Byte0]: 78
2906 01:21:28.563367 [Byte1]: 78
2907 01:21:28.563422
2908 01:21:28.563474 Set Vref, RX VrefLevel [Byte0]: 79
2909 01:21:28.563526 [Byte1]: 79
2910 01:21:28.563578
2911 01:21:28.563630 Final RX Vref Byte 0 = 57 to rank0
2912 01:21:28.563683 Final RX Vref Byte 1 = 49 to rank0
2913 01:21:28.563736 Final RX Vref Byte 0 = 57 to rank1
2914 01:21:28.563788 Final RX Vref Byte 1 = 49 to rank1==
2915 01:21:28.563840 Dram Type= 6, Freq= 0, CH_0, rank 0
2916 01:21:28.563893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2917 01:21:28.563946 ==
2918 01:21:28.563998 DQS Delay:
2919 01:21:28.564050 DQS0 = 0, DQS1 = 0
2920 01:21:28.564102 DQM Delay:
2921 01:21:28.564154 DQM0 = 118, DQM1 = 106
2922 01:21:28.564207 DQ Delay:
2923 01:21:28.564259 DQ0 =118, DQ1 =120, DQ2 =116, DQ3 =114
2924 01:21:28.564311 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =126
2925 01:21:28.564364 DQ8 =96, DQ9 =92, DQ10 =108, DQ11 =98
2926 01:21:28.564416 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =116
2927 01:21:28.564469
2928 01:21:28.564520
2929 01:21:28.564572 [DQSOSCAuto] RK0, (LSB)MR18= 0xffb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 404 ps
2930 01:21:28.564625 CH0 RK0: MR19=403, MR18=FFB
2931 01:21:28.564678 CH0_RK0: MR19=0x403, MR18=0xFFB, DQSOSC=404, MR23=63, INC=40, DEC=26
2932 01:21:28.564731
2933 01:21:28.564783 ----->DramcWriteLeveling(PI) begin...
2934 01:21:28.564836 ==
2935 01:21:28.564888 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 01:21:28.564941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 01:21:28.564994 ==
2938 01:21:28.565046 Write leveling (Byte 0): 34 => 34
2939 01:21:28.565099 Write leveling (Byte 1): 31 => 31
2940 01:21:28.565151 DramcWriteLeveling(PI) end<-----
2941 01:21:28.565204
2942 01:21:28.565255 ==
2943 01:21:28.565307 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 01:21:28.565408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 01:21:28.565463 ==
2946 01:21:28.565515 [Gating] SW mode calibration
2947 01:21:28.565568 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2948 01:21:28.565622 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2949 01:21:28.565676 0 15 0 | B1->B0 | 2323 3333 | 1 1 | (0 0) (1 1)
2950 01:21:28.565730 0 15 4 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
2951 01:21:28.565972 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2952 01:21:28.566033 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2953 01:21:28.566088 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2954 01:21:28.566141 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2955 01:21:28.566194 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2956 01:21:28.566247 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2957 01:21:28.566300 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2958 01:21:28.566352 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2959 01:21:28.566405 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2960 01:21:28.566457 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2961 01:21:28.566510 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2962 01:21:28.566562 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2963 01:21:28.566615 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2964 01:21:28.566668 1 0 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2965 01:21:28.566720 1 1 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
2966 01:21:28.566773 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 01:21:28.566825 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2968 01:21:28.566878 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2969 01:21:28.566932 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2970 01:21:28.566985 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2971 01:21:28.567037 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2972 01:21:28.567090 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2973 01:21:28.567142 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 01:21:28.567194 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 01:21:28.567247 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 01:21:28.567299 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 01:21:28.567352 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 01:21:28.567404 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 01:21:28.567456 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 01:21:28.567509 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 01:21:28.567561 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 01:21:28.567614 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 01:21:28.567666 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 01:21:28.567718 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 01:21:28.567771 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 01:21:28.567823 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 01:21:28.567876 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 01:21:28.567928 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2989 01:21:28.567980 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2990 01:21:28.568033 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2991 01:21:28.568085 Total UI for P1: 0, mck2ui 16
2992 01:21:28.568138 best dqsien dly found for B0: ( 1, 3, 30)
2993 01:21:28.568191 Total UI for P1: 0, mck2ui 16
2994 01:21:28.568244 best dqsien dly found for B1: ( 1, 4, 0)
2995 01:21:28.568297 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2996 01:21:28.568349 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2997 01:21:28.568402
2998 01:21:28.568454 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2999 01:21:28.568507 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3000 01:21:28.568559 [Gating] SW calibration Done
3001 01:21:28.568612 ==
3002 01:21:28.568664 Dram Type= 6, Freq= 0, CH_0, rank 1
3003 01:21:28.568731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3004 01:21:29.207354 ==
3005 01:21:29.207887 RX Vref Scan: 0
3006 01:21:29.208263
3007 01:21:29.208608 RX Vref 0 -> 0, step: 1
3008 01:21:29.208946
3009 01:21:29.209267 RX Delay -40 -> 252, step: 8
3010 01:21:29.209646 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
3011 01:21:29.209969 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3012 01:21:29.210280 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3013 01:21:29.210591 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3014 01:21:29.210894 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3015 01:21:29.211201 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3016 01:21:29.211507 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3017 01:21:29.211814 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
3018 01:21:29.212117 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3019 01:21:29.212418 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3020 01:21:29.212718 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3021 01:21:29.213017 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3022 01:21:29.213315 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3023 01:21:29.213664 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3024 01:21:29.213967 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3025 01:21:29.214269 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3026 01:21:29.214568 ==
3027 01:21:29.214871 Dram Type= 6, Freq= 0, CH_0, rank 1
3028 01:21:29.215176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3029 01:21:29.215479 ==
3030 01:21:29.215780 DQS Delay:
3031 01:21:29.216080 DQS0 = 0, DQS1 = 0
3032 01:21:29.216379 DQM Delay:
3033 01:21:29.216677 DQM0 = 118, DQM1 = 108
3034 01:21:29.216976 DQ Delay:
3035 01:21:29.217276 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
3036 01:21:29.217623 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =127
3037 01:21:29.217925 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3038 01:21:29.218225 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
3039 01:21:29.218526
3040 01:21:29.218823
3041 01:21:29.219117 ==
3042 01:21:29.219416 Dram Type= 6, Freq= 0, CH_0, rank 1
3043 01:21:29.219713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 01:21:29.220015 ==
3045 01:21:29.220313
3046 01:21:29.220608
3047 01:21:29.220905 TX Vref Scan disable
3048 01:21:29.221206 == TX Byte 0 ==
3049 01:21:29.221564 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3050 01:21:29.221872 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3051 01:21:29.222175 == TX Byte 1 ==
3052 01:21:29.222474 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3053 01:21:29.222776 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3054 01:21:29.223077 ==
3055 01:21:29.223376 Dram Type= 6, Freq= 0, CH_0, rank 1
3056 01:21:29.223676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3057 01:21:29.223979 ==
3058 01:21:29.224682 TX Vref=22, minBit 1, minWin=25, winSum=417
3059 01:21:29.225035 TX Vref=24, minBit 8, minWin=25, winSum=425
3060 01:21:29.225399 TX Vref=26, minBit 1, minWin=26, winSum=429
3061 01:21:29.225719 TX Vref=28, minBit 1, minWin=26, winSum=429
3062 01:21:29.226025 TX Vref=30, minBit 4, minWin=26, winSum=432
3063 01:21:29.226326 TX Vref=32, minBit 14, minWin=26, winSum=431
3064 01:21:29.226629 [TxChooseVref] Worse bit 4, Min win 26, Win sum 432, Final Vref 30
3065 01:21:29.226931
3066 01:21:29.227273 Final TX Range 1 Vref 30
3067 01:21:29.227590
3068 01:21:29.227890 ==
3069 01:21:29.228185 Dram Type= 6, Freq= 0, CH_0, rank 1
3070 01:21:29.228592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 01:21:29.228908 ==
3072 01:21:29.229209
3073 01:21:29.229557
3074 01:21:29.229859 TX Vref Scan disable
3075 01:21:29.230160 == TX Byte 0 ==
3076 01:21:29.230462 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3077 01:21:29.230755 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3078 01:21:29.231028 == TX Byte 1 ==
3079 01:21:29.231421 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3080 01:21:29.231822 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3081 01:21:29.232112
3082 01:21:29.232387 [DATLAT]
3083 01:21:29.232635 Freq=1200, CH0 RK1
3084 01:21:29.232832
3085 01:21:29.233027 DATLAT Default: 0xd
3086 01:21:29.233222 0, 0xFFFF, sum = 0
3087 01:21:29.233457 1, 0xFFFF, sum = 0
3088 01:21:29.233662 2, 0xFFFF, sum = 0
3089 01:21:29.233860 3, 0xFFFF, sum = 0
3090 01:21:29.234059 4, 0xFFFF, sum = 0
3091 01:21:29.234257 5, 0xFFFF, sum = 0
3092 01:21:29.234454 6, 0xFFFF, sum = 0
3093 01:21:29.234653 7, 0xFFFF, sum = 0
3094 01:21:29.234850 8, 0xFFFF, sum = 0
3095 01:21:29.235048 9, 0xFFFF, sum = 0
3096 01:21:29.235244 10, 0xFFFF, sum = 0
3097 01:21:29.235442 11, 0xFFFF, sum = 0
3098 01:21:29.235638 12, 0x0, sum = 1
3099 01:21:29.235838 13, 0x0, sum = 2
3100 01:21:29.236035 14, 0x0, sum = 3
3101 01:21:29.236235 15, 0x0, sum = 4
3102 01:21:29.236433 best_step = 13
3103 01:21:29.236624
3104 01:21:29.236817 ==
3105 01:21:29.237012 Dram Type= 6, Freq= 0, CH_0, rank 1
3106 01:21:29.237208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 01:21:29.237430 ==
3108 01:21:29.237612 RX Vref Scan: 0
3109 01:21:29.237761
3110 01:21:29.237909 RX Vref 0 -> 0, step: 1
3111 01:21:29.238058
3112 01:21:29.238205 RX Delay -21 -> 252, step: 4
3113 01:21:29.238353 iDelay=199, Bit 0, Center 114 (51 ~ 178) 128
3114 01:21:29.238501 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3115 01:21:29.238650 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3116 01:21:29.238798 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3117 01:21:29.238947 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3118 01:21:29.239095 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3119 01:21:29.239243 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3120 01:21:29.239391 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3121 01:21:29.239539 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3122 01:21:29.239687 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3123 01:21:29.239835 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3124 01:21:29.239983 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3125 01:21:29.240131 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
3126 01:21:29.240279 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3127 01:21:29.240426 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3128 01:21:29.240572 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3129 01:21:29.240719 ==
3130 01:21:29.240868 Dram Type= 6, Freq= 0, CH_0, rank 1
3131 01:21:29.241017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 01:21:29.241167 ==
3133 01:21:29.241314 DQS Delay:
3134 01:21:29.241476 DQS0 = 0, DQS1 = 0
3135 01:21:29.241626 DQM Delay:
3136 01:21:29.241774 DQM0 = 116, DQM1 = 107
3137 01:21:29.241922 DQ Delay:
3138 01:21:29.242069 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =112
3139 01:21:29.242218 DQ4 =116, DQ5 =110, DQ6 =128, DQ7 =124
3140 01:21:29.242366 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3141 01:21:29.242518 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =116
3142 01:21:29.242636
3143 01:21:29.242754
3144 01:21:29.242872 [DQSOSCAuto] RK1, (LSB)MR18= 0xce6, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps
3145 01:21:29.242994 CH0 RK1: MR19=403, MR18=CE6
3146 01:21:29.243115 CH0_RK1: MR19=0x403, MR18=0xCE6, DQSOSC=405, MR23=63, INC=39, DEC=26
3147 01:21:29.243237 [RxdqsGatingPostProcess] freq 1200
3148 01:21:29.243356 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3149 01:21:29.243476 best DQS0 dly(2T, 0.5T) = (0, 11)
3150 01:21:29.243596 best DQS1 dly(2T, 0.5T) = (0, 12)
3151 01:21:29.243714 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3152 01:21:29.243833 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3153 01:21:29.243953 best DQS0 dly(2T, 0.5T) = (0, 11)
3154 01:21:29.244070 best DQS1 dly(2T, 0.5T) = (0, 12)
3155 01:21:29.244189 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3156 01:21:29.244309 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3157 01:21:29.244429 Pre-setting of DQS Precalculation
3158 01:21:29.244548 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3159 01:21:29.244668 ==
3160 01:21:29.244788 Dram Type= 6, Freq= 0, CH_1, rank 0
3161 01:21:29.244907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3162 01:21:29.245026 ==
3163 01:21:29.245147 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3164 01:21:29.245266 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3165 01:21:29.245397 [CA 0] Center 37 (7~68) winsize 62
3166 01:21:29.245516 [CA 1] Center 37 (7~68) winsize 62
3167 01:21:29.245634 [CA 2] Center 34 (4~64) winsize 61
3168 01:21:29.245754 [CA 3] Center 33 (3~64) winsize 62
3169 01:21:29.245873 [CA 4] Center 34 (5~64) winsize 60
3170 01:21:29.245991 [CA 5] Center 33 (3~64) winsize 62
3171 01:21:29.246109
3172 01:21:29.246227 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3173 01:21:29.246345
3174 01:21:29.246463 [CATrainingPosCal] consider 1 rank data
3175 01:21:29.246581 u2DelayCellTimex100 = 270/100 ps
3176 01:21:29.246700 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3177 01:21:29.246819 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3178 01:21:29.246939 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3179 01:21:29.247057 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3180 01:21:29.247176 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3181 01:21:29.247294 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3182 01:21:29.247413
3183 01:21:29.247542 CA PerBit enable=1, Macro0, CA PI delay=33
3184 01:21:29.247642
3185 01:21:29.247740 [CBTSetCACLKResult] CA Dly = 33
3186 01:21:29.247840 CS Dly: 6 (0~37)
3187 01:21:29.247938 ==
3188 01:21:29.248037 Dram Type= 6, Freq= 0, CH_1, rank 1
3189 01:21:29.248136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 01:21:29.248236 ==
3191 01:21:29.248333 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3192 01:21:29.248660 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3193 01:21:29.248775 [CA 0] Center 37 (7~68) winsize 62
3194 01:21:29.248876 [CA 1] Center 38 (8~68) winsize 61
3195 01:21:29.248977 [CA 2] Center 34 (4~65) winsize 62
3196 01:21:29.249078 [CA 3] Center 33 (3~64) winsize 62
3197 01:21:29.249177 [CA 4] Center 34 (4~65) winsize 62
3198 01:21:29.249276 [CA 5] Center 33 (3~64) winsize 62
3199 01:21:29.249387
3200 01:21:29.249487 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3201 01:21:29.249587
3202 01:21:29.249686 [CATrainingPosCal] consider 2 rank data
3203 01:21:29.249785 u2DelayCellTimex100 = 270/100 ps
3204 01:21:29.249884 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3205 01:21:29.249982 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3206 01:21:29.250082 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3207 01:21:29.250180 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3208 01:21:29.250278 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3209 01:21:29.250391 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3210 01:21:29.250508
3211 01:21:29.250608 CA PerBit enable=1, Macro0, CA PI delay=33
3212 01:21:29.250707
3213 01:21:29.250805 [CBTSetCACLKResult] CA Dly = 33
3214 01:21:29.250904 CS Dly: 7 (0~40)
3215 01:21:29.251003
3216 01:21:29.251102 ----->DramcWriteLeveling(PI) begin...
3217 01:21:29.251203 ==
3218 01:21:29.251302 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 01:21:29.251401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 01:21:29.251501 ==
3221 01:21:29.251601 Write leveling (Byte 0): 26 => 26
3222 01:21:29.251700 Write leveling (Byte 1): 26 => 26
3223 01:21:29.251799 DramcWriteLeveling(PI) end<-----
3224 01:21:29.251899
3225 01:21:29.251998 ==
3226 01:21:29.252096 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 01:21:29.252195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 01:21:29.252294 ==
3229 01:21:29.252393 [Gating] SW mode calibration
3230 01:21:29.252505 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3231 01:21:29.252592 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3232 01:21:29.252677 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3233 01:21:29.252763 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3234 01:21:29.252849 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3235 01:21:29.252935 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3236 01:21:29.253021 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3237 01:21:29.253106 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3238 01:21:29.253191 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
3239 01:21:29.253276 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
3240 01:21:29.253370 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3241 01:21:29.253457 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3242 01:21:29.253543 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3243 01:21:29.253628 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3244 01:21:29.253714 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3245 01:21:29.253798 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3246 01:21:29.253884 1 0 24 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
3247 01:21:29.253969 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3248 01:21:29.254054 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3249 01:21:29.254140 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3250 01:21:29.254225 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3251 01:21:29.254310 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3252 01:21:29.254395 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3253 01:21:29.254479 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3254 01:21:29.254564 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3255 01:21:29.254649 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3256 01:21:29.254734 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3257 01:21:29.254819 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3258 01:21:29.254904 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3259 01:21:29.254988 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3260 01:21:29.255073 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3261 01:21:29.255161 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3262 01:21:29.255259 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3263 01:21:29.255345 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3264 01:21:29.255431 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3265 01:21:29.255516 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3266 01:21:29.255602 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3267 01:21:29.255688 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3268 01:21:29.255774 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3269 01:21:29.255858 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3270 01:21:29.255942 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3271 01:21:29.256027 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3272 01:21:29.256112 Total UI for P1: 0, mck2ui 16
3273 01:21:29.256198 best dqsien dly found for B0: ( 1, 3, 24)
3274 01:21:29.256284 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3275 01:21:29.256369 Total UI for P1: 0, mck2ui 16
3276 01:21:29.256455 best dqsien dly found for B1: ( 1, 3, 26)
3277 01:21:29.256541 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3278 01:21:29.256626 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3279 01:21:29.256711
3280 01:21:29.256796 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3281 01:21:29.256880 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3282 01:21:29.256964 [Gating] SW calibration Done
3283 01:21:29.257049 ==
3284 01:21:29.257134 Dram Type= 6, Freq= 0, CH_1, rank 0
3285 01:21:29.257219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3286 01:21:29.257306 ==
3287 01:21:29.257426 RX Vref Scan: 0
3288 01:21:29.257526
3289 01:21:29.257600 RX Vref 0 -> 0, step: 1
3290 01:21:29.257676
3291 01:21:29.257751 RX Delay -40 -> 252, step: 8
3292 01:21:29.257825 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3293 01:21:29.257900 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3294 01:21:29.257974 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3295 01:21:29.258048 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3296 01:21:29.258123 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3297 01:21:29.258404 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3298 01:21:29.258488 iDelay=208, Bit 6, Center 127 (56 ~ 199) 144
3299 01:21:29.258566 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3300 01:21:29.258663 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3301 01:21:29.258741 iDelay=208, Bit 9, Center 103 (32 ~ 175) 144
3302 01:21:29.258817 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3303 01:21:29.258892 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3304 01:21:29.258967 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3305 01:21:29.259041 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3306 01:21:29.259116 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3307 01:21:29.259191 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3308 01:21:29.259265 ==
3309 01:21:29.259351 Dram Type= 6, Freq= 0, CH_1, rank 0
3310 01:21:29.259428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3311 01:21:29.259503 ==
3312 01:21:29.259578 DQS Delay:
3313 01:21:29.259653 DQS0 = 0, DQS1 = 0
3314 01:21:29.259727 DQM Delay:
3315 01:21:29.259802 DQM0 = 118, DQM1 = 109
3316 01:21:29.259877 DQ Delay:
3317 01:21:29.259951 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3318 01:21:29.260025 DQ4 =111, DQ5 =131, DQ6 =127, DQ7 =115
3319 01:21:29.260101 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =95
3320 01:21:29.260189 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3321 01:21:29.260265
3322 01:21:29.260338
3323 01:21:29.260412 ==
3324 01:21:29.260486 Dram Type= 6, Freq= 0, CH_1, rank 0
3325 01:21:29.260561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3326 01:21:29.260635 ==
3327 01:21:29.260710
3328 01:21:29.260783
3329 01:21:29.260857 TX Vref Scan disable
3330 01:21:29.260931 == TX Byte 0 ==
3331 01:21:29.261005 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3332 01:21:29.261081 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3333 01:21:29.261155 == TX Byte 1 ==
3334 01:21:29.261230 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3335 01:21:29.261304 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3336 01:21:29.261394 ==
3337 01:21:29.261470 Dram Type= 6, Freq= 0, CH_1, rank 0
3338 01:21:29.261544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3339 01:21:29.261620 ==
3340 01:21:29.261695 TX Vref=22, minBit 9, minWin=25, winSum=416
3341 01:21:29.261770 TX Vref=24, minBit 10, minWin=25, winSum=423
3342 01:21:29.261846 TX Vref=26, minBit 10, minWin=25, winSum=429
3343 01:21:29.261920 TX Vref=28, minBit 9, minWin=26, winSum=430
3344 01:21:29.261995 TX Vref=30, minBit 9, minWin=26, winSum=429
3345 01:21:29.262071 TX Vref=32, minBit 1, minWin=26, winSum=428
3346 01:21:29.262147 [TxChooseVref] Worse bit 9, Min win 26, Win sum 430, Final Vref 28
3347 01:21:29.262222
3348 01:21:29.262297 Final TX Range 1 Vref 28
3349 01:21:29.262372
3350 01:21:29.262446 ==
3351 01:21:29.262529 Dram Type= 6, Freq= 0, CH_1, rank 0
3352 01:21:29.262596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3353 01:21:29.262662 ==
3354 01:21:29.262728
3355 01:21:29.262792
3356 01:21:29.262858 TX Vref Scan disable
3357 01:21:29.262925 == TX Byte 0 ==
3358 01:21:29.262991 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3359 01:21:29.263058 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3360 01:21:29.263125 == TX Byte 1 ==
3361 01:21:29.263191 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3362 01:21:29.263257 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3363 01:21:29.263323
3364 01:21:29.263401 [DATLAT]
3365 01:21:29.263468 Freq=1200, CH1 RK0
3366 01:21:29.263534
3367 01:21:29.263599 DATLAT Default: 0xd
3368 01:21:29.263665 0, 0xFFFF, sum = 0
3369 01:21:29.263732 1, 0xFFFF, sum = 0
3370 01:21:29.263798 2, 0xFFFF, sum = 0
3371 01:21:29.263864 3, 0xFFFF, sum = 0
3372 01:21:29.263930 4, 0xFFFF, sum = 0
3373 01:21:29.263996 5, 0xFFFF, sum = 0
3374 01:21:29.264062 6, 0xFFFF, sum = 0
3375 01:21:29.264127 7, 0xFFFF, sum = 0
3376 01:21:29.264193 8, 0xFFFF, sum = 0
3377 01:21:29.264260 9, 0xFFFF, sum = 0
3378 01:21:29.264325 10, 0xFFFF, sum = 0
3379 01:21:29.264392 11, 0xFFFF, sum = 0
3380 01:21:29.264459 12, 0x0, sum = 1
3381 01:21:29.264525 13, 0x0, sum = 2
3382 01:21:29.264592 14, 0x0, sum = 3
3383 01:21:29.264657 15, 0x0, sum = 4
3384 01:21:29.264724 best_step = 13
3385 01:21:29.264788
3386 01:21:29.264857 ==
3387 01:21:29.264923 Dram Type= 6, Freq= 0, CH_1, rank 0
3388 01:21:29.264988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3389 01:21:29.265054 ==
3390 01:21:29.265120 RX Vref Scan: 1
3391 01:21:29.265184
3392 01:21:29.265249 Set Vref Range= 32 -> 127
3393 01:21:29.265314
3394 01:21:29.265394 RX Vref 32 -> 127, step: 1
3395 01:21:29.265461
3396 01:21:29.265526 RX Delay -21 -> 252, step: 4
3397 01:21:29.265592
3398 01:21:29.265657 Set Vref, RX VrefLevel [Byte0]: 32
3399 01:21:29.265723 [Byte1]: 32
3400 01:21:29.265789
3401 01:21:29.265854 Set Vref, RX VrefLevel [Byte0]: 33
3402 01:21:29.265920 [Byte1]: 33
3403 01:21:29.265985
3404 01:21:29.266050 Set Vref, RX VrefLevel [Byte0]: 34
3405 01:21:29.266115 [Byte1]: 34
3406 01:21:29.266182
3407 01:21:29.266247 Set Vref, RX VrefLevel [Byte0]: 35
3408 01:21:29.266312 [Byte1]: 35
3409 01:21:29.266377
3410 01:21:29.266442 Set Vref, RX VrefLevel [Byte0]: 36
3411 01:21:29.266508 [Byte1]: 36
3412 01:21:29.266573
3413 01:21:29.266637 Set Vref, RX VrefLevel [Byte0]: 37
3414 01:21:29.266703 [Byte1]: 37
3415 01:21:29.266768
3416 01:21:29.266833 Set Vref, RX VrefLevel [Byte0]: 38
3417 01:21:29.266898 [Byte1]: 38
3418 01:21:29.266963
3419 01:21:29.267028 Set Vref, RX VrefLevel [Byte0]: 39
3420 01:21:29.267094 [Byte1]: 39
3421 01:21:29.267159
3422 01:21:29.267224 Set Vref, RX VrefLevel [Byte0]: 40
3423 01:21:29.267289 [Byte1]: 40
3424 01:21:29.267354
3425 01:21:29.267423 Set Vref, RX VrefLevel [Byte0]: 41
3426 01:21:29.267490 [Byte1]: 41
3427 01:21:29.267565
3428 01:21:29.267623 Set Vref, RX VrefLevel [Byte0]: 42
3429 01:21:29.267683 [Byte1]: 42
3430 01:21:29.267742
3431 01:21:29.267800 Set Vref, RX VrefLevel [Byte0]: 43
3432 01:21:29.267859 [Byte1]: 43
3433 01:21:29.267919
3434 01:21:29.267978 Set Vref, RX VrefLevel [Byte0]: 44
3435 01:21:29.268036 [Byte1]: 44
3436 01:21:29.268094
3437 01:21:29.268153 Set Vref, RX VrefLevel [Byte0]: 45
3438 01:21:29.268212 [Byte1]: 45
3439 01:21:29.268271
3440 01:21:29.268329 Set Vref, RX VrefLevel [Byte0]: 46
3441 01:21:29.268388 [Byte1]: 46
3442 01:21:29.268447
3443 01:21:29.268505 Set Vref, RX VrefLevel [Byte0]: 47
3444 01:21:29.268563 [Byte1]: 47
3445 01:21:29.268622
3446 01:21:29.268681 Set Vref, RX VrefLevel [Byte0]: 48
3447 01:21:29.268740 [Byte1]: 48
3448 01:21:29.268799
3449 01:21:29.268857 Set Vref, RX VrefLevel [Byte0]: 49
3450 01:21:29.268916 [Byte1]: 49
3451 01:21:29.268975
3452 01:21:29.269034 Set Vref, RX VrefLevel [Byte0]: 50
3453 01:21:29.269093 [Byte1]: 50
3454 01:21:29.269152
3455 01:21:29.269210 Set Vref, RX VrefLevel [Byte0]: 51
3456 01:21:29.269469 [Byte1]: 51
3457 01:21:29.269544
3458 01:21:29.269606 Set Vref, RX VrefLevel [Byte0]: 52
3459 01:21:29.269667 [Byte1]: 52
3460 01:21:29.269727
3461 01:21:29.269787 Set Vref, RX VrefLevel [Byte0]: 53
3462 01:21:29.269847 [Byte1]: 53
3463 01:21:29.269906
3464 01:21:29.269980 Set Vref, RX VrefLevel [Byte0]: 54
3465 01:21:29.270042 [Byte1]: 54
3466 01:21:29.270101
3467 01:21:29.270160 Set Vref, RX VrefLevel [Byte0]: 55
3468 01:21:29.270220 [Byte1]: 55
3469 01:21:29.270279
3470 01:21:29.270338 Set Vref, RX VrefLevel [Byte0]: 56
3471 01:21:29.270396 [Byte1]: 56
3472 01:21:29.270455
3473 01:21:29.270514 Set Vref, RX VrefLevel [Byte0]: 57
3474 01:21:29.270573 [Byte1]: 57
3475 01:21:29.270632
3476 01:21:29.270691 Set Vref, RX VrefLevel [Byte0]: 58
3477 01:21:29.270750 [Byte1]: 58
3478 01:21:29.270809
3479 01:21:29.270868 Set Vref, RX VrefLevel [Byte0]: 59
3480 01:21:29.270926 [Byte1]: 59
3481 01:21:29.270985
3482 01:21:29.271043 Set Vref, RX VrefLevel [Byte0]: 60
3483 01:21:29.271102 [Byte1]: 60
3484 01:21:29.271161
3485 01:21:29.271219 Set Vref, RX VrefLevel [Byte0]: 61
3486 01:21:29.271278 [Byte1]: 61
3487 01:21:29.271336
3488 01:21:29.271418 Set Vref, RX VrefLevel [Byte0]: 62
3489 01:21:29.271520 [Byte1]: 62
3490 01:21:29.271586
3491 01:21:29.271647 Set Vref, RX VrefLevel [Byte0]: 63
3492 01:21:29.271706 [Byte1]: 63
3493 01:21:29.271765
3494 01:21:29.271824 Set Vref, RX VrefLevel [Byte0]: 64
3495 01:21:29.271884 [Byte1]: 64
3496 01:21:29.271943
3497 01:21:29.272001 Set Vref, RX VrefLevel [Byte0]: 65
3498 01:21:29.272061 [Byte1]: 65
3499 01:21:29.272120
3500 01:21:29.272178 Set Vref, RX VrefLevel [Byte0]: 66
3501 01:21:29.272237 [Byte1]: 66
3502 01:21:29.272296
3503 01:21:29.272355 Set Vref, RX VrefLevel [Byte0]: 67
3504 01:21:29.272414 [Byte1]: 67
3505 01:21:29.272472
3506 01:21:29.272542 Set Vref, RX VrefLevel [Byte0]: 68
3507 01:21:29.272596 [Byte1]: 68
3508 01:21:29.272650
3509 01:21:29.272703 Final RX Vref Byte 0 = 51 to rank0
3510 01:21:29.272756 Final RX Vref Byte 1 = 59 to rank0
3511 01:21:29.272811 Final RX Vref Byte 0 = 51 to rank1
3512 01:21:29.272865 Final RX Vref Byte 1 = 59 to rank1==
3513 01:21:29.272919 Dram Type= 6, Freq= 0, CH_1, rank 0
3514 01:21:29.272973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 01:21:29.273027 ==
3516 01:21:29.273081 DQS Delay:
3517 01:21:29.273135 DQS0 = 0, DQS1 = 0
3518 01:21:29.273189 DQM Delay:
3519 01:21:29.273242 DQM0 = 116, DQM1 = 112
3520 01:21:29.273295 DQ Delay:
3521 01:21:29.273358 DQ0 =120, DQ1 =110, DQ2 =110, DQ3 =114
3522 01:21:29.273414 DQ4 =114, DQ5 =128, DQ6 =126, DQ7 =112
3523 01:21:29.273467 DQ8 =100, DQ9 =100, DQ10 =116, DQ11 =102
3524 01:21:29.273521 DQ12 =120, DQ13 =120, DQ14 =122, DQ15 =122
3525 01:21:29.273574
3526 01:21:29.273627
3527 01:21:29.273681 [DQSOSCAuto] RK0, (LSB)MR18= 0xf4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 410 ps
3528 01:21:29.273736 CH1 RK0: MR19=403, MR18=F4
3529 01:21:29.273790 CH1_RK0: MR19=0x403, MR18=0xF4, DQSOSC=410, MR23=63, INC=39, DEC=26
3530 01:21:29.273845
3531 01:21:29.273900 ----->DramcWriteLeveling(PI) begin...
3532 01:21:29.273955 ==
3533 01:21:29.274008 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 01:21:29.274062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 01:21:29.274116 ==
3536 01:21:29.274169 Write leveling (Byte 0): 24 => 24
3537 01:21:29.274223 Write leveling (Byte 1): 28 => 28
3538 01:21:29.274277 DramcWriteLeveling(PI) end<-----
3539 01:21:29.274330
3540 01:21:29.274383 ==
3541 01:21:29.274437 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 01:21:29.274491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 01:21:29.274544 ==
3544 01:21:29.274598 [Gating] SW mode calibration
3545 01:21:29.274652 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3546 01:21:29.274706 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3547 01:21:29.274760 0 15 0 | B1->B0 | 3333 3333 | 1 0 | (1 1) (0 0)
3548 01:21:29.274815 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3549 01:21:29.274869 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3550 01:21:29.274923 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3551 01:21:29.274977 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3552 01:21:29.275030 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3553 01:21:29.275085 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
3554 01:21:29.275138 0 15 28 | B1->B0 | 2525 2727 | 0 0 | (0 0) (0 1)
3555 01:21:29.275193 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3556 01:21:29.275247 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3557 01:21:29.275301 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3558 01:21:29.275373 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3559 01:21:29.275450 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3560 01:21:29.275528 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3561 01:21:29.275584 1 0 24 | B1->B0 | 3030 2424 | 0 0 | (0 0) (0 0)
3562 01:21:29.275638 1 0 28 | B1->B0 | 4545 4444 | 0 0 | (0 0) (0 0)
3563 01:21:29.275693 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3564 01:21:29.275746 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3565 01:21:29.275800 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3566 01:21:29.275853 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3567 01:21:29.275909 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3568 01:21:29.275962 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3569 01:21:29.276016 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3570 01:21:29.276069 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3571 01:21:29.276122 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 01:21:29.276176 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3573 01:21:29.276230 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3574 01:21:29.276283 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3575 01:21:29.276337 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3576 01:21:29.276390 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3577 01:21:29.276444 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3578 01:21:29.276690 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3579 01:21:29.276752 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3580 01:21:29.276807 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3581 01:21:29.276861 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3582 01:21:29.276915 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3583 01:21:29.276968 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3584 01:21:29.277022 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3585 01:21:29.277076 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3586 01:21:29.277130 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3587 01:21:29.277184 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3588 01:21:29.277237 Total UI for P1: 0, mck2ui 16
3589 01:21:29.277293 best dqsien dly found for B0: ( 1, 3, 28)
3590 01:21:29.277374 Total UI for P1: 0, mck2ui 16
3591 01:21:29.277430 best dqsien dly found for B1: ( 1, 3, 28)
3592 01:21:29.277485 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3593 01:21:29.277552 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3594 01:21:29.277604
3595 01:21:29.277657 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3596 01:21:29.277709 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3597 01:21:29.277761 [Gating] SW calibration Done
3598 01:21:29.277814 ==
3599 01:21:29.277866 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 01:21:29.277920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 01:21:29.277974 ==
3602 01:21:29.278026 RX Vref Scan: 0
3603 01:21:29.278080
3604 01:21:29.278132 RX Vref 0 -> 0, step: 1
3605 01:21:29.278185
3606 01:21:29.278237 RX Delay -40 -> 252, step: 8
3607 01:21:29.278289 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3608 01:21:29.278341 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3609 01:21:29.278393 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3610 01:21:29.278445 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3611 01:21:29.278497 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3612 01:21:29.278549 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3613 01:21:29.278600 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3614 01:21:29.278652 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3615 01:21:29.278703 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
3616 01:21:29.278755 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3617 01:21:29.278807 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3618 01:21:29.278860 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3619 01:21:29.278932 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3620 01:21:29.278986 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3621 01:21:29.279039 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3622 01:21:29.279091 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3623 01:21:29.279143 ==
3624 01:21:29.279195 Dram Type= 6, Freq= 0, CH_1, rank 1
3625 01:21:29.279248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3626 01:21:29.279301 ==
3627 01:21:29.279389 DQS Delay:
3628 01:21:29.279442 DQS0 = 0, DQS1 = 0
3629 01:21:29.279494 DQM Delay:
3630 01:21:29.279546 DQM0 = 116, DQM1 = 110
3631 01:21:29.279599 DQ Delay:
3632 01:21:29.279651 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3633 01:21:29.279703 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =115
3634 01:21:29.279756 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =103
3635 01:21:29.279808 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3636 01:21:29.279860
3637 01:21:29.279912
3638 01:21:29.279964 ==
3639 01:21:29.280016 Dram Type= 6, Freq= 0, CH_1, rank 1
3640 01:21:29.280069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3641 01:21:29.280121 ==
3642 01:21:29.280173
3643 01:21:29.280226
3644 01:21:29.280278 TX Vref Scan disable
3645 01:21:29.280330 == TX Byte 0 ==
3646 01:21:29.280382 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3647 01:21:29.280435 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3648 01:21:29.280487 == TX Byte 1 ==
3649 01:21:29.280539 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3650 01:21:29.280592 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3651 01:21:29.280644 ==
3652 01:21:29.280697 Dram Type= 6, Freq= 0, CH_1, rank 1
3653 01:21:29.280749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3654 01:21:29.280801 ==
3655 01:21:29.280854 TX Vref=22, minBit 8, minWin=25, winSum=424
3656 01:21:29.280907 TX Vref=24, minBit 8, minWin=25, winSum=427
3657 01:21:29.280960 TX Vref=26, minBit 8, minWin=26, winSum=432
3658 01:21:29.281012 TX Vref=28, minBit 8, minWin=26, winSum=434
3659 01:21:29.281065 TX Vref=30, minBit 8, minWin=26, winSum=437
3660 01:21:29.281117 TX Vref=32, minBit 9, minWin=25, winSum=432
3661 01:21:29.281170 [TxChooseVref] Worse bit 8, Min win 26, Win sum 437, Final Vref 30
3662 01:21:29.281223
3663 01:21:29.281275 Final TX Range 1 Vref 30
3664 01:21:29.281333
3665 01:21:29.281387 ==
3666 01:21:29.281440 Dram Type= 6, Freq= 0, CH_1, rank 1
3667 01:21:29.281492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3668 01:21:29.281545 ==
3669 01:21:29.281598
3670 01:21:29.281649
3671 01:21:29.281701 TX Vref Scan disable
3672 01:21:29.281754 == TX Byte 0 ==
3673 01:21:29.281806 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3674 01:21:29.281858 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3675 01:21:29.281911 == TX Byte 1 ==
3676 01:21:29.281964 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3677 01:21:29.282017 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3678 01:21:29.282069
3679 01:21:29.282121 [DATLAT]
3680 01:21:29.282173 Freq=1200, CH1 RK1
3681 01:21:29.282226
3682 01:21:29.282277 DATLAT Default: 0xd
3683 01:21:29.282330 0, 0xFFFF, sum = 0
3684 01:21:29.282383 1, 0xFFFF, sum = 0
3685 01:21:29.282437 2, 0xFFFF, sum = 0
3686 01:21:29.282491 3, 0xFFFF, sum = 0
3687 01:21:29.282544 4, 0xFFFF, sum = 0
3688 01:21:29.282596 5, 0xFFFF, sum = 0
3689 01:21:29.282649 6, 0xFFFF, sum = 0
3690 01:21:29.282702 7, 0xFFFF, sum = 0
3691 01:21:29.282754 8, 0xFFFF, sum = 0
3692 01:21:29.282807 9, 0xFFFF, sum = 0
3693 01:21:29.282860 10, 0xFFFF, sum = 0
3694 01:21:29.282913 11, 0xFFFF, sum = 0
3695 01:21:29.282966 12, 0x0, sum = 1
3696 01:21:29.283019 13, 0x0, sum = 2
3697 01:21:29.283073 14, 0x0, sum = 3
3698 01:21:29.283125 15, 0x0, sum = 4
3699 01:21:29.283178 best_step = 13
3700 01:21:29.283230
3701 01:21:29.283282 ==
3702 01:21:29.283334 Dram Type= 6, Freq= 0, CH_1, rank 1
3703 01:21:29.283387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3704 01:21:29.283440 ==
3705 01:21:29.283492 RX Vref Scan: 0
3706 01:21:29.283544
3707 01:21:29.283596 RX Vref 0 -> 0, step: 1
3708 01:21:29.283649
3709 01:21:29.283701 RX Delay -13 -> 252, step: 4
3710 01:21:29.283754 iDelay=199, Bit 0, Center 120 (51 ~ 190) 140
3711 01:21:29.283806 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3712 01:21:29.283859 iDelay=199, Bit 2, Center 108 (43 ~ 174) 132
3713 01:21:29.283911 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3714 01:21:29.283963 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3715 01:21:29.284015 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3716 01:21:29.284258 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3717 01:21:29.284320 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3718 01:21:29.284374 iDelay=199, Bit 8, Center 98 (35 ~ 162) 128
3719 01:21:29.284427 iDelay=199, Bit 9, Center 102 (39 ~ 166) 128
3720 01:21:29.284480 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3721 01:21:29.284533 iDelay=199, Bit 11, Center 102 (39 ~ 166) 128
3722 01:21:29.284586 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3723 01:21:29.284639 iDelay=199, Bit 13, Center 120 (55 ~ 186) 132
3724 01:21:29.284692 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3725 01:21:29.284744 iDelay=199, Bit 15, Center 120 (55 ~ 186) 132
3726 01:21:29.284798 ==
3727 01:21:29.284850 Dram Type= 6, Freq= 0, CH_1, rank 1
3728 01:21:29.284903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3729 01:21:29.284956 ==
3730 01:21:29.285009 DQS Delay:
3731 01:21:29.285061 DQS0 = 0, DQS1 = 0
3732 01:21:29.285113 DQM Delay:
3733 01:21:29.285166 DQM0 = 117, DQM1 = 111
3734 01:21:29.285219 DQ Delay:
3735 01:21:29.285270 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =112
3736 01:21:29.285322 DQ4 =116, DQ5 =126, DQ6 =130, DQ7 =116
3737 01:21:29.285422 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =102
3738 01:21:29.285475 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =120
3739 01:21:29.285527
3740 01:21:29.285578
3741 01:21:29.285631 [DQSOSCAuto] RK1, (LSB)MR18= 0xf3ee, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3742 01:21:29.285684 CH1 RK1: MR19=303, MR18=F3EE
3743 01:21:29.285737 CH1_RK1: MR19=0x303, MR18=0xF3EE, DQSOSC=415, MR23=63, INC=38, DEC=25
3744 01:21:29.285789 [RxdqsGatingPostProcess] freq 1200
3745 01:21:29.285842 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3746 01:21:29.285895 best DQS0 dly(2T, 0.5T) = (0, 11)
3747 01:21:29.285947 best DQS1 dly(2T, 0.5T) = (0, 11)
3748 01:21:29.285999 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3749 01:21:29.286052 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3750 01:21:29.286105 best DQS0 dly(2T, 0.5T) = (0, 11)
3751 01:21:29.286157 best DQS1 dly(2T, 0.5T) = (0, 11)
3752 01:21:29.286209 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3753 01:21:29.286262 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3754 01:21:29.286315 Pre-setting of DQS Precalculation
3755 01:21:29.286368 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3756 01:21:29.286421 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3757 01:21:29.286474 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3758 01:21:29.286527
3759 01:21:29.286579
3760 01:21:29.286631 [Calibration Summary] 2400 Mbps
3761 01:21:29.286683 CH 0, Rank 0
3762 01:21:29.286735 SW Impedance : PASS
3763 01:21:29.286787 DUTY Scan : NO K
3764 01:21:29.286839 ZQ Calibration : PASS
3765 01:21:29.286892 Jitter Meter : NO K
3766 01:21:29.286944 CBT Training : PASS
3767 01:21:29.286996 Write leveling : PASS
3768 01:21:29.287048 RX DQS gating : PASS
3769 01:21:29.287100 RX DQ/DQS(RDDQC) : PASS
3770 01:21:29.287151 TX DQ/DQS : PASS
3771 01:21:29.287203 RX DATLAT : PASS
3772 01:21:29.287254 RX DQ/DQS(Engine): PASS
3773 01:21:29.287306 TX OE : NO K
3774 01:21:29.287358 All Pass.
3775 01:21:29.287410
3776 01:21:29.287462 CH 0, Rank 1
3777 01:21:29.287514 SW Impedance : PASS
3778 01:21:29.287565 DUTY Scan : NO K
3779 01:21:29.287617 ZQ Calibration : PASS
3780 01:21:29.287668 Jitter Meter : NO K
3781 01:21:29.287720 CBT Training : PASS
3782 01:21:29.287772 Write leveling : PASS
3783 01:21:29.287824 RX DQS gating : PASS
3784 01:21:29.287876 RX DQ/DQS(RDDQC) : PASS
3785 01:21:29.287927 TX DQ/DQS : PASS
3786 01:21:29.287980 RX DATLAT : PASS
3787 01:21:29.288032 RX DQ/DQS(Engine): PASS
3788 01:21:29.288084 TX OE : NO K
3789 01:21:29.288136 All Pass.
3790 01:21:29.288188
3791 01:21:29.288239 CH 1, Rank 0
3792 01:21:29.288290 SW Impedance : PASS
3793 01:21:29.288342 DUTY Scan : NO K
3794 01:21:29.288395 ZQ Calibration : PASS
3795 01:21:29.288446 Jitter Meter : NO K
3796 01:21:29.288498 CBT Training : PASS
3797 01:21:29.288550 Write leveling : PASS
3798 01:21:29.288601 RX DQS gating : PASS
3799 01:21:29.288653 RX DQ/DQS(RDDQC) : PASS
3800 01:21:29.288704 TX DQ/DQS : PASS
3801 01:21:29.288756 RX DATLAT : PASS
3802 01:21:29.288808 RX DQ/DQS(Engine): PASS
3803 01:21:29.288861 TX OE : NO K
3804 01:21:29.288913 All Pass.
3805 01:21:29.288965
3806 01:21:29.289018 CH 1, Rank 1
3807 01:21:29.289070 SW Impedance : PASS
3808 01:21:29.289122 DUTY Scan : NO K
3809 01:21:29.289175 ZQ Calibration : PASS
3810 01:21:29.289227 Jitter Meter : NO K
3811 01:21:29.289279 CBT Training : PASS
3812 01:21:29.289335 Write leveling : PASS
3813 01:21:29.289424 RX DQS gating : PASS
3814 01:21:29.289476 RX DQ/DQS(RDDQC) : PASS
3815 01:21:29.289528 TX DQ/DQS : PASS
3816 01:21:29.289580 RX DATLAT : PASS
3817 01:21:29.289632 RX DQ/DQS(Engine): PASS
3818 01:21:29.289684 TX OE : NO K
3819 01:21:29.289736 All Pass.
3820 01:21:29.289789
3821 01:21:29.289841 DramC Write-DBI off
3822 01:21:29.289892 PER_BANK_REFRESH: Hybrid Mode
3823 01:21:29.289945 TX_TRACKING: ON
3824 01:21:29.289997 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3825 01:21:29.290051 [FAST_K] Save calibration result to emmc
3826 01:21:29.290103 dramc_set_vcore_voltage set vcore to 650000
3827 01:21:29.290156 Read voltage for 600, 5
3828 01:21:29.290208 Vio18 = 0
3829 01:21:29.290261 Vcore = 650000
3830 01:21:29.290312 Vdram = 0
3831 01:21:29.290364 Vddq = 0
3832 01:21:29.290416 Vmddr = 0
3833 01:21:29.290481 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3834 01:21:29.290536 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3835 01:21:29.290589 MEM_TYPE=3, freq_sel=19
3836 01:21:29.290642 sv_algorithm_assistance_LP4_1600
3837 01:21:29.290695 ============ PULL DRAM RESETB DOWN ============
3838 01:21:29.290748 ========== PULL DRAM RESETB DOWN end =========
3839 01:21:29.290800 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3840 01:21:29.290853 ===================================
3841 01:21:29.290906 LPDDR4 DRAM CONFIGURATION
3842 01:21:29.290958 ===================================
3843 01:21:29.291011 EX_ROW_EN[0] = 0x0
3844 01:21:29.291063 EX_ROW_EN[1] = 0x0
3845 01:21:29.291115 LP4Y_EN = 0x0
3846 01:21:29.291167 WORK_FSP = 0x0
3847 01:21:29.291219 WL = 0x2
3848 01:21:29.291271 RL = 0x2
3849 01:21:29.291323 BL = 0x2
3850 01:21:29.291376 RPST = 0x0
3851 01:21:29.291428 RD_PRE = 0x0
3852 01:21:29.291480 WR_PRE = 0x1
3853 01:21:29.291532 WR_PST = 0x0
3854 01:21:29.291584 DBI_WR = 0x0
3855 01:21:29.291636 DBI_RD = 0x0
3856 01:21:29.291687 OTF = 0x1
3857 01:21:29.291931 ===================================
3858 01:21:29.291993 ===================================
3859 01:21:29.292047 ANA top config
3860 01:21:29.292100 ===================================
3861 01:21:29.292153 DLL_ASYNC_EN = 0
3862 01:21:29.292206 ALL_SLAVE_EN = 1
3863 01:21:29.292259 NEW_RANK_MODE = 1
3864 01:21:29.292312 DLL_IDLE_MODE = 1
3865 01:21:29.292365 LP45_APHY_COMB_EN = 1
3866 01:21:29.292417 TX_ODT_DIS = 1
3867 01:21:29.292469 NEW_8X_MODE = 1
3868 01:21:29.292521 ===================================
3869 01:21:29.292574 ===================================
3870 01:21:29.292626 data_rate = 1200
3871 01:21:29.292679 CKR = 1
3872 01:21:29.292730 DQ_P2S_RATIO = 8
3873 01:21:29.292783 ===================================
3874 01:21:29.292835 CA_P2S_RATIO = 8
3875 01:21:29.292888 DQ_CA_OPEN = 0
3876 01:21:29.292939 DQ_SEMI_OPEN = 0
3877 01:21:29.292991 CA_SEMI_OPEN = 0
3878 01:21:29.293043 CA_FULL_RATE = 0
3879 01:21:29.293096 DQ_CKDIV4_EN = 1
3880 01:21:29.293148 CA_CKDIV4_EN = 1
3881 01:21:29.293200 CA_PREDIV_EN = 0
3882 01:21:29.293253 PH8_DLY = 0
3883 01:21:29.293305 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3884 01:21:29.293400 DQ_AAMCK_DIV = 4
3885 01:21:29.293454 CA_AAMCK_DIV = 4
3886 01:21:29.293506 CA_ADMCK_DIV = 4
3887 01:21:29.293559 DQ_TRACK_CA_EN = 0
3888 01:21:29.293611 CA_PICK = 600
3889 01:21:29.293663 CA_MCKIO = 600
3890 01:21:29.293716 MCKIO_SEMI = 0
3891 01:21:29.293769 PLL_FREQ = 2288
3892 01:21:29.293821 DQ_UI_PI_RATIO = 32
3893 01:21:29.293873 CA_UI_PI_RATIO = 0
3894 01:21:29.293925 ===================================
3895 01:21:29.293978 ===================================
3896 01:21:29.294031 memory_type:LPDDR4
3897 01:21:29.294084 GP_NUM : 10
3898 01:21:29.294136 SRAM_EN : 1
3899 01:21:29.294189 MD32_EN : 0
3900 01:21:29.294241 ===================================
3901 01:21:29.294294 [ANA_INIT] >>>>>>>>>>>>>>
3902 01:21:29.294346 <<<<<< [CONFIGURE PHASE]: ANA_TX
3903 01:21:29.294399 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3904 01:21:29.294452 ===================================
3905 01:21:29.294505 data_rate = 1200,PCW = 0X5800
3906 01:21:29.294557 ===================================
3907 01:21:29.294610 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3908 01:21:29.294662 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3909 01:21:29.294716 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3910 01:21:29.294769 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3911 01:21:29.294821 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3912 01:21:29.294874 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3913 01:21:29.294926 [ANA_INIT] flow start
3914 01:21:29.294978 [ANA_INIT] PLL >>>>>>>>
3915 01:21:29.295030 [ANA_INIT] PLL <<<<<<<<
3916 01:21:29.295082 [ANA_INIT] MIDPI >>>>>>>>
3917 01:21:29.295134 [ANA_INIT] MIDPI <<<<<<<<
3918 01:21:29.295186 [ANA_INIT] DLL >>>>>>>>
3919 01:21:29.295238 [ANA_INIT] flow end
3920 01:21:29.295290 ============ LP4 DIFF to SE enter ============
3921 01:21:29.295343 ============ LP4 DIFF to SE exit ============
3922 01:21:29.295396 [ANA_INIT] <<<<<<<<<<<<<
3923 01:21:29.295447 [Flow] Enable top DCM control >>>>>
3924 01:21:29.295499 [Flow] Enable top DCM control <<<<<
3925 01:21:29.295551 Enable DLL master slave shuffle
3926 01:21:29.295603 ==============================================================
3927 01:21:29.295667 Gating Mode config
3928 01:21:29.295726 ==============================================================
3929 01:21:29.295779 Config description:
3930 01:21:29.295832 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3931 01:21:29.295886 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3932 01:21:29.295939 SELPH_MODE 0: By rank 1: By Phase
3933 01:21:29.295992 ==============================================================
3934 01:21:29.296045 GAT_TRACK_EN = 1
3935 01:21:29.296097 RX_GATING_MODE = 2
3936 01:21:29.296150 RX_GATING_TRACK_MODE = 2
3937 01:21:29.296203 SELPH_MODE = 1
3938 01:21:29.296255 PICG_EARLY_EN = 1
3939 01:21:29.296307 VALID_LAT_VALUE = 1
3940 01:21:29.296359 ==============================================================
3941 01:21:29.296413 Enter into Gating configuration >>>>
3942 01:21:29.296465 Exit from Gating configuration <<<<
3943 01:21:29.296516 Enter into DVFS_PRE_config >>>>>
3944 01:21:29.296569 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3945 01:21:29.296623 Exit from DVFS_PRE_config <<<<<
3946 01:21:29.296675 Enter into PICG configuration >>>>
3947 01:21:29.296727 Exit from PICG configuration <<<<
3948 01:21:29.296779 [RX_INPUT] configuration >>>>>
3949 01:21:29.296831 [RX_INPUT] configuration <<<<<
3950 01:21:29.296883 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3951 01:21:29.296936 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3952 01:21:29.296988 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3953 01:21:29.297041 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3954 01:21:29.297093 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3955 01:21:29.297145 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3956 01:21:29.297198 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3957 01:21:29.297250 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3958 01:21:29.297303 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3959 01:21:29.297403 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3960 01:21:29.297663 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3961 01:21:29.297725 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3962 01:21:29.297780 ===================================
3963 01:21:29.297833 LPDDR4 DRAM CONFIGURATION
3964 01:21:29.297887 ===================================
3965 01:21:29.297940 EX_ROW_EN[0] = 0x0
3966 01:21:29.297993 EX_ROW_EN[1] = 0x0
3967 01:21:29.298045 LP4Y_EN = 0x0
3968 01:21:29.298098 WORK_FSP = 0x0
3969 01:21:29.298150 WL = 0x2
3970 01:21:29.298203 RL = 0x2
3971 01:21:29.298254 BL = 0x2
3972 01:21:29.298315 RPST = 0x0
3973 01:21:29.298370 RD_PRE = 0x0
3974 01:21:29.298422 WR_PRE = 0x1
3975 01:21:29.298474 WR_PST = 0x0
3976 01:21:29.298526 DBI_WR = 0x0
3977 01:21:29.298578 DBI_RD = 0x0
3978 01:21:29.298630 OTF = 0x1
3979 01:21:29.298683 ===================================
3980 01:21:29.298736 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3981 01:21:29.298789 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3982 01:21:29.298841 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3983 01:21:29.298894 ===================================
3984 01:21:29.298947 LPDDR4 DRAM CONFIGURATION
3985 01:21:29.299002 ===================================
3986 01:21:29.299055 EX_ROW_EN[0] = 0x10
3987 01:21:29.299108 EX_ROW_EN[1] = 0x0
3988 01:21:29.299160 LP4Y_EN = 0x0
3989 01:21:29.299211 WORK_FSP = 0x0
3990 01:21:29.299263 WL = 0x2
3991 01:21:29.299315 RL = 0x2
3992 01:21:29.299367 BL = 0x2
3993 01:21:29.299418 RPST = 0x0
3994 01:21:29.299470 RD_PRE = 0x0
3995 01:21:29.299522 WR_PRE = 0x1
3996 01:21:29.299575 WR_PST = 0x0
3997 01:21:29.299626 DBI_WR = 0x0
3998 01:21:29.299678 DBI_RD = 0x0
3999 01:21:29.299730 OTF = 0x1
4000 01:21:29.299782 ===================================
4001 01:21:29.299834 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4002 01:21:30.546787 nWR fixed to 30
4003 01:21:30.547327 [ModeRegInit_LP4] CH0 RK0
4004 01:21:30.547613 [ModeRegInit_LP4] CH0 RK1
4005 01:21:30.547674 [ModeRegInit_LP4] CH1 RK0
4006 01:21:30.547732 [ModeRegInit_LP4] CH1 RK1
4007 01:21:30.547789 match AC timing 17
4008 01:21:30.547845 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4009 01:21:30.547902 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4010 01:21:30.547957 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4011 01:21:30.548012 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4012 01:21:30.548067 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4013 01:21:30.548121 ==
4014 01:21:30.548175 Dram Type= 6, Freq= 0, CH_0, rank 0
4015 01:21:30.548230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4016 01:21:30.548284 ==
4017 01:21:30.548337 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4018 01:21:30.548390 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4019 01:21:30.548444 [CA 0] Center 36 (6~66) winsize 61
4020 01:21:30.548497 [CA 1] Center 35 (5~66) winsize 62
4021 01:21:30.548549 [CA 2] Center 34 (4~65) winsize 62
4022 01:21:30.548602 [CA 3] Center 34 (4~65) winsize 62
4023 01:21:30.548655 [CA 4] Center 33 (3~64) winsize 62
4024 01:21:30.548707 [CA 5] Center 33 (3~64) winsize 62
4025 01:21:30.548760
4026 01:21:30.548811 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4027 01:21:30.548864
4028 01:21:30.548916 [CATrainingPosCal] consider 1 rank data
4029 01:21:30.548969 u2DelayCellTimex100 = 270/100 ps
4030 01:21:30.549021 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4031 01:21:30.549074 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4032 01:21:30.549126 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4033 01:21:30.549179 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4034 01:21:30.549232 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4035 01:21:30.549284 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4036 01:21:30.549341
4037 01:21:30.549394 CA PerBit enable=1, Macro0, CA PI delay=33
4038 01:21:30.549447
4039 01:21:30.549498 [CBTSetCACLKResult] CA Dly = 33
4040 01:21:30.549551 CS Dly: 4 (0~35)
4041 01:21:30.549603 ==
4042 01:21:30.549658 Dram Type= 6, Freq= 0, CH_0, rank 1
4043 01:21:30.549740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4044 01:21:30.549825 ==
4045 01:21:30.549881 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4046 01:21:30.549936 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4047 01:21:30.549990 [CA 0] Center 35 (5~66) winsize 62
4048 01:21:30.550043 [CA 1] Center 36 (6~66) winsize 61
4049 01:21:30.550096 [CA 2] Center 34 (4~65) winsize 62
4050 01:21:30.550148 [CA 3] Center 34 (4~64) winsize 61
4051 01:21:30.550200 [CA 4] Center 33 (2~64) winsize 63
4052 01:21:30.550253 [CA 5] Center 33 (2~64) winsize 63
4053 01:21:30.550306
4054 01:21:30.550358 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4055 01:21:30.550410
4056 01:21:30.550463 [CATrainingPosCal] consider 2 rank data
4057 01:21:30.550516 u2DelayCellTimex100 = 270/100 ps
4058 01:21:30.550569 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4059 01:21:30.550621 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4060 01:21:30.550674 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4061 01:21:30.550726 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4062 01:21:30.550779 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4063 01:21:30.550832 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4064 01:21:30.550884
4065 01:21:30.550936 CA PerBit enable=1, Macro0, CA PI delay=33
4066 01:21:30.550989
4067 01:21:30.551041 [CBTSetCACLKResult] CA Dly = 33
4068 01:21:30.551094 CS Dly: 5 (0~37)
4069 01:21:30.551147
4070 01:21:30.551199 ----->DramcWriteLeveling(PI) begin...
4071 01:21:30.551253 ==
4072 01:21:30.551306 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 01:21:30.551359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 01:21:30.551413 ==
4075 01:21:30.551466 Write leveling (Byte 0): 32 => 32
4076 01:21:30.551518 Write leveling (Byte 1): 29 => 29
4077 01:21:30.551571 DramcWriteLeveling(PI) end<-----
4078 01:21:30.551623
4079 01:21:30.551674 ==
4080 01:21:30.551726 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 01:21:30.551779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 01:21:30.551833 ==
4083 01:21:30.551885 [Gating] SW mode calibration
4084 01:21:30.551938 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4085 01:21:30.551992 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4086 01:21:30.552045 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4087 01:21:30.552099 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4088 01:21:30.552151 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4089 01:21:30.552415 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
4090 01:21:30.552479 0 9 16 | B1->B0 | 3131 2d2d | 1 0 | (1 0) (0 0)
4091 01:21:30.552534 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4092 01:21:30.552589 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4093 01:21:30.552642 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4094 01:21:30.552696 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4095 01:21:30.552748 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4096 01:21:30.552801 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4097 01:21:30.552854 0 10 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4098 01:21:30.552906 0 10 16 | B1->B0 | 2f2f 4444 | 1 0 | (0 0) (0 0)
4099 01:21:30.552959 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4100 01:21:30.553012 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4101 01:21:30.553065 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4102 01:21:30.553117 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4103 01:21:30.553171 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4104 01:21:30.553224 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4105 01:21:30.553278 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4106 01:21:30.553339 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4107 01:21:30.553395 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 01:21:30.553448 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 01:21:30.553501 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 01:21:30.553554 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4111 01:21:30.553607 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4112 01:21:30.553660 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4113 01:21:30.553745 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4114 01:21:30.553798 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4115 01:21:30.553851 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4116 01:21:30.553904 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4117 01:21:30.553958 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4118 01:21:30.554011 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4119 01:21:30.554064 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4120 01:21:30.554116 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4121 01:21:30.554170 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4122 01:21:30.554223 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4123 01:21:30.554276 Total UI for P1: 0, mck2ui 16
4124 01:21:30.554329 best dqsien dly found for B0: ( 0, 13, 12)
4125 01:21:30.554383 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4126 01:21:30.554436 Total UI for P1: 0, mck2ui 16
4127 01:21:30.554490 best dqsien dly found for B1: ( 0, 13, 16)
4128 01:21:30.554560 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4129 01:21:30.554617 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4130 01:21:30.554671
4131 01:21:30.554724 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4132 01:21:30.554777 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4133 01:21:30.554830 [Gating] SW calibration Done
4134 01:21:30.554884 ==
4135 01:21:30.554937 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 01:21:30.554990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 01:21:30.555044 ==
4138 01:21:30.555098 RX Vref Scan: 0
4139 01:21:30.555151
4140 01:21:30.555204 RX Vref 0 -> 0, step: 1
4141 01:21:30.555257
4142 01:21:30.555311 RX Delay -230 -> 252, step: 16
4143 01:21:30.555364 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4144 01:21:30.555417 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4145 01:21:30.555470 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4146 01:21:30.555523 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4147 01:21:30.555576 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4148 01:21:30.555629 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4149 01:21:30.555682 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4150 01:21:30.555735 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4151 01:21:30.555788 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4152 01:21:30.555840 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4153 01:21:30.555894 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4154 01:21:30.555947 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4155 01:21:30.556000 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4156 01:21:30.556054 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4157 01:21:30.556107 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4158 01:21:30.556160 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4159 01:21:30.556213 ==
4160 01:21:30.556266 Dram Type= 6, Freq= 0, CH_0, rank 0
4161 01:21:30.556318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 01:21:30.556372 ==
4163 01:21:30.556425 DQS Delay:
4164 01:21:30.556477 DQS0 = 0, DQS1 = 0
4165 01:21:30.556530 DQM Delay:
4166 01:21:30.556583 DQM0 = 43, DQM1 = 30
4167 01:21:30.556637 DQ Delay:
4168 01:21:30.556690 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4169 01:21:30.556743 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4170 01:21:30.556796 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4171 01:21:30.556850 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4172 01:21:30.556903
4173 01:21:30.556955
4174 01:21:30.557008 ==
4175 01:21:30.557061 Dram Type= 6, Freq= 0, CH_0, rank 0
4176 01:21:30.557115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4177 01:21:30.557168 ==
4178 01:21:30.557222
4179 01:21:30.557275
4180 01:21:30.557332 TX Vref Scan disable
4181 01:21:30.557389 == TX Byte 0 ==
4182 01:21:30.557443 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4183 01:21:30.557497 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4184 01:21:30.557551 == TX Byte 1 ==
4185 01:21:30.557604 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4186 01:21:30.557658 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4187 01:21:30.557711 ==
4188 01:21:30.557764 Dram Type= 6, Freq= 0, CH_0, rank 0
4189 01:21:30.557817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4190 01:21:30.557871 ==
4191 01:21:30.557924
4192 01:21:30.557976
4193 01:21:30.558030 TX Vref Scan disable
4194 01:21:30.558082 == TX Byte 0 ==
4195 01:21:30.558135 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4196 01:21:30.558189 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4197 01:21:30.558242 == TX Byte 1 ==
4198 01:21:30.558295 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4199 01:21:30.558351 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4200 01:21:30.558411
4201 01:21:30.558464 [DATLAT]
4202 01:21:30.558517 Freq=600, CH0 RK0
4203 01:21:30.558571
4204 01:21:30.558814 DATLAT Default: 0x9
4205 01:21:30.558874 0, 0xFFFF, sum = 0
4206 01:21:30.558931 1, 0xFFFF, sum = 0
4207 01:21:30.558986 2, 0xFFFF, sum = 0
4208 01:21:30.559040 3, 0xFFFF, sum = 0
4209 01:21:30.559095 4, 0xFFFF, sum = 0
4210 01:21:30.559150 5, 0xFFFF, sum = 0
4211 01:21:30.559204 6, 0xFFFF, sum = 0
4212 01:21:30.559258 7, 0xFFFF, sum = 0
4213 01:21:30.559312 8, 0x0, sum = 1
4214 01:21:30.559366 9, 0x0, sum = 2
4215 01:21:30.559420 10, 0x0, sum = 3
4216 01:21:30.559474 11, 0x0, sum = 4
4217 01:21:30.559528 best_step = 9
4218 01:21:30.559582
4219 01:21:30.559635 ==
4220 01:21:30.559688 Dram Type= 6, Freq= 0, CH_0, rank 0
4221 01:21:30.559741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4222 01:21:30.559795 ==
4223 01:21:30.559847 RX Vref Scan: 1
4224 01:21:30.559900
4225 01:21:30.559953 RX Vref 0 -> 0, step: 1
4226 01:21:30.560005
4227 01:21:30.560058 RX Delay -195 -> 252, step: 8
4228 01:21:30.560110
4229 01:21:30.560163 Set Vref, RX VrefLevel [Byte0]: 57
4230 01:21:30.560216 [Byte1]: 49
4231 01:21:30.560269
4232 01:21:30.560322 Final RX Vref Byte 0 = 57 to rank0
4233 01:21:30.560375 Final RX Vref Byte 1 = 49 to rank0
4234 01:21:30.560429 Final RX Vref Byte 0 = 57 to rank1
4235 01:21:30.560482 Final RX Vref Byte 1 = 49 to rank1==
4236 01:21:30.560535 Dram Type= 6, Freq= 0, CH_0, rank 0
4237 01:21:30.560588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 01:21:30.560642 ==
4239 01:21:30.560695 DQS Delay:
4240 01:21:30.560747 DQS0 = 0, DQS1 = 0
4241 01:21:30.560800 DQM Delay:
4242 01:21:30.560853 DQM0 = 44, DQM1 = 33
4243 01:21:30.560906 DQ Delay:
4244 01:21:30.560959 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4245 01:21:30.561012 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =52
4246 01:21:30.561065 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4247 01:21:30.561117 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =44
4248 01:21:30.561170
4249 01:21:30.561222
4250 01:21:30.561275 [DQSOSCAuto] RK0, (LSB)MR18= 0x5b33, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
4251 01:21:30.561335 CH0 RK0: MR19=808, MR18=5B33
4252 01:21:30.561391 CH0_RK0: MR19=0x808, MR18=0x5B33, DQSOSC=392, MR23=63, INC=170, DEC=113
4253 01:21:30.561445
4254 01:21:30.561498 ----->DramcWriteLeveling(PI) begin...
4255 01:21:30.561552 ==
4256 01:21:30.561605 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 01:21:30.561658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 01:21:30.561712 ==
4259 01:21:30.561765 Write leveling (Byte 0): 34 => 34
4260 01:21:30.561818 Write leveling (Byte 1): 31 => 31
4261 01:21:30.561870 DramcWriteLeveling(PI) end<-----
4262 01:21:30.561922
4263 01:21:30.561975 ==
4264 01:21:30.562027 Dram Type= 6, Freq= 0, CH_0, rank 1
4265 01:21:30.562081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4266 01:21:30.562133 ==
4267 01:21:30.562186 [Gating] SW mode calibration
4268 01:21:30.562240 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4269 01:21:30.562294 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4270 01:21:30.562348 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4271 01:21:30.562402 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4272 01:21:30.562455 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4273 01:21:30.562509 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
4274 01:21:30.562561 0 9 16 | B1->B0 | 2f2f 2727 | 1 0 | (0 0) (0 0)
4275 01:21:30.562614 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4276 01:21:30.562667 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4277 01:21:30.562720 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4278 01:21:30.562786 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4279 01:21:30.562841 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4280 01:21:30.562894 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4281 01:21:30.562948 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4282 01:21:30.563001 0 10 16 | B1->B0 | 3939 3e3d | 0 1 | (1 1) (0 0)
4283 01:21:30.563055 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4284 01:21:30.563108 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4285 01:21:30.563161 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4286 01:21:30.563214 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4287 01:21:30.563267 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4288 01:21:30.563320 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4289 01:21:30.563373 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4290 01:21:30.563426 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 01:21:30.563479 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 01:21:30.563532 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 01:21:30.563586 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 01:21:30.563639 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 01:21:30.563692 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 01:21:30.563746 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 01:21:30.563799 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 01:21:30.563851 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 01:21:30.563904 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 01:21:30.563957 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 01:21:30.564010 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 01:21:30.564063 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 01:21:30.564117 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 01:21:30.564170 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 01:21:30.564223 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4306 01:21:30.564276 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4307 01:21:30.564329 Total UI for P1: 0, mck2ui 16
4308 01:21:30.564383 best dqsien dly found for B0: ( 0, 13, 12)
4309 01:21:30.564436 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4310 01:21:30.564489 Total UI for P1: 0, mck2ui 16
4311 01:21:30.564543 best dqsien dly found for B1: ( 0, 13, 14)
4312 01:21:30.564596 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4313 01:21:30.564650 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4314 01:21:30.564703
4315 01:21:30.564756 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4316 01:21:30.564809 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4317 01:21:30.564863 [Gating] SW calibration Done
4318 01:21:30.564916 ==
4319 01:21:30.564968 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 01:21:30.565021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 01:21:30.565075 ==
4322 01:21:30.565127 RX Vref Scan: 0
4323 01:21:30.565180
4324 01:21:30.565420 RX Vref 0 -> 0, step: 1
4325 01:21:30.565482
4326 01:21:30.565537 RX Delay -230 -> 252, step: 16
4327 01:21:30.565592 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4328 01:21:30.565646 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4329 01:21:30.565699 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4330 01:21:30.565752 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4331 01:21:30.565805 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4332 01:21:30.565859 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4333 01:21:30.565912 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4334 01:21:30.565965 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4335 01:21:30.566018 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4336 01:21:30.566071 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4337 01:21:30.566124 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4338 01:21:30.566178 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4339 01:21:30.566231 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4340 01:21:30.566284 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4341 01:21:30.566337 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4342 01:21:30.566390 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4343 01:21:30.566443 ==
4344 01:21:30.566496 Dram Type= 6, Freq= 0, CH_0, rank 1
4345 01:21:30.566550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4346 01:21:30.566604 ==
4347 01:21:30.566657 DQS Delay:
4348 01:21:30.566710 DQS0 = 0, DQS1 = 0
4349 01:21:30.566763 DQM Delay:
4350 01:21:30.566817 DQM0 = 41, DQM1 = 33
4351 01:21:30.566869 DQ Delay:
4352 01:21:30.566922 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4353 01:21:30.566976 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4354 01:21:30.567029 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4355 01:21:30.567082 DQ12 =33, DQ13 =49, DQ14 =49, DQ15 =33
4356 01:21:30.567135
4357 01:21:30.567187
4358 01:21:30.567240 ==
4359 01:21:30.567293 Dram Type= 6, Freq= 0, CH_0, rank 1
4360 01:21:30.567347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4361 01:21:30.567401 ==
4362 01:21:30.567453
4363 01:21:30.567505
4364 01:21:30.567557 TX Vref Scan disable
4365 01:21:30.567610 == TX Byte 0 ==
4366 01:21:30.567662 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4367 01:21:30.567715 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4368 01:21:30.567768 == TX Byte 1 ==
4369 01:21:30.567821 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4370 01:21:30.567873 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4371 01:21:30.567925 ==
4372 01:21:30.567977 Dram Type= 6, Freq= 0, CH_0, rank 1
4373 01:21:30.568029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 01:21:30.568082 ==
4375 01:21:30.568134
4376 01:21:30.568186
4377 01:21:30.568238 TX Vref Scan disable
4378 01:21:30.568290 == TX Byte 0 ==
4379 01:21:30.568343 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4380 01:21:30.568396 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4381 01:21:30.568449 == TX Byte 1 ==
4382 01:21:30.568501 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4383 01:21:30.568553 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4384 01:21:30.568605
4385 01:21:30.568657 [DATLAT]
4386 01:21:30.568710 Freq=600, CH0 RK1
4387 01:21:30.568762
4388 01:21:30.568814 DATLAT Default: 0x9
4389 01:21:30.568866 0, 0xFFFF, sum = 0
4390 01:21:30.568920 1, 0xFFFF, sum = 0
4391 01:21:30.568974 2, 0xFFFF, sum = 0
4392 01:21:30.569027 3, 0xFFFF, sum = 0
4393 01:21:30.569080 4, 0xFFFF, sum = 0
4394 01:21:30.569133 5, 0xFFFF, sum = 0
4395 01:21:30.569186 6, 0xFFFF, sum = 0
4396 01:21:30.569239 7, 0xFFFF, sum = 0
4397 01:21:30.569292 8, 0x0, sum = 1
4398 01:21:30.569373 9, 0x0, sum = 2
4399 01:21:30.569441 10, 0x0, sum = 3
4400 01:21:30.569495 11, 0x0, sum = 4
4401 01:21:30.569548 best_step = 9
4402 01:21:30.569600
4403 01:21:30.569652 ==
4404 01:21:30.569704 Dram Type= 6, Freq= 0, CH_0, rank 1
4405 01:21:30.569759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 01:21:30.569813 ==
4407 01:21:30.569866 RX Vref Scan: 0
4408 01:21:30.569918
4409 01:21:30.569970 RX Vref 0 -> 0, step: 1
4410 01:21:30.570022
4411 01:21:30.570074 RX Delay -195 -> 252, step: 8
4412 01:21:30.570126 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4413 01:21:30.570180 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4414 01:21:30.570232 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4415 01:21:30.570285 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4416 01:21:30.570337 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4417 01:21:30.570390 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4418 01:21:30.570442 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4419 01:21:30.570494 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4420 01:21:30.570547 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4421 01:21:30.570599 iDelay=205, Bit 9, Center 24 (-123 ~ 172) 296
4422 01:21:30.570651 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4423 01:21:30.570703 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4424 01:21:30.570756 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4425 01:21:30.570808 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4426 01:21:30.570860 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4427 01:21:30.570912 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4428 01:21:30.570964 ==
4429 01:21:30.571017 Dram Type= 6, Freq= 0, CH_0, rank 1
4430 01:21:30.571070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4431 01:21:30.571123 ==
4432 01:21:30.571175 DQS Delay:
4433 01:21:30.571228 DQS0 = 0, DQS1 = 0
4434 01:21:30.571280 DQM Delay:
4435 01:21:30.571333 DQM0 = 42, DQM1 = 37
4436 01:21:30.571385 DQ Delay:
4437 01:21:30.571437 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4438 01:21:30.571489 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4439 01:21:30.571542 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =28
4440 01:21:30.571594 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4441 01:21:30.571646
4442 01:21:30.571698
4443 01:21:30.571750 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e11, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
4444 01:21:30.571804 CH0 RK1: MR19=808, MR18=5E11
4445 01:21:30.571858 CH0_RK1: MR19=0x808, MR18=0x5E11, DQSOSC=392, MR23=63, INC=170, DEC=113
4446 01:21:30.571911 [RxdqsGatingPostProcess] freq 600
4447 01:21:30.571963 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4448 01:21:30.572016 Pre-setting of DQS Precalculation
4449 01:21:30.572068 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4450 01:21:30.572121 ==
4451 01:21:30.572174 Dram Type= 6, Freq= 0, CH_1, rank 0
4452 01:21:30.572227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4453 01:21:30.572280 ==
4454 01:21:30.572332 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4455 01:21:30.572385 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4456 01:21:30.572438 [CA 0] Center 35 (5~66) winsize 62
4457 01:21:30.572491 [CA 1] Center 35 (5~66) winsize 62
4458 01:21:30.572740 [CA 2] Center 34 (4~65) winsize 62
4459 01:21:30.572804 [CA 3] Center 33 (3~64) winsize 62
4460 01:21:30.572858 [CA 4] Center 34 (4~64) winsize 61
4461 01:21:30.572911 [CA 5] Center 33 (3~64) winsize 62
4462 01:21:30.572964
4463 01:21:30.573017 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4464 01:21:30.573069
4465 01:21:30.573121 [CATrainingPosCal] consider 1 rank data
4466 01:21:30.573174 u2DelayCellTimex100 = 270/100 ps
4467 01:21:30.573227 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4468 01:21:30.573280 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4469 01:21:30.573340 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4470 01:21:30.573429 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4471 01:21:30.573481 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4472 01:21:30.573533 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4473 01:21:30.573586
4474 01:21:30.573638 CA PerBit enable=1, Macro0, CA PI delay=33
4475 01:21:30.573691
4476 01:21:30.573743 [CBTSetCACLKResult] CA Dly = 33
4477 01:21:30.573796 CS Dly: 4 (0~35)
4478 01:21:30.573848 ==
4479 01:21:30.573901 Dram Type= 6, Freq= 0, CH_1, rank 1
4480 01:21:30.573953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4481 01:21:30.574006 ==
4482 01:21:30.574060 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4483 01:21:30.574113 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4484 01:21:30.574167 [CA 0] Center 35 (5~66) winsize 62
4485 01:21:30.574219 [CA 1] Center 36 (6~66) winsize 61
4486 01:21:30.574272 [CA 2] Center 34 (4~65) winsize 62
4487 01:21:30.574324 [CA 3] Center 34 (4~65) winsize 62
4488 01:21:30.574377 [CA 4] Center 34 (4~65) winsize 62
4489 01:21:30.574428 [CA 5] Center 34 (3~65) winsize 63
4490 01:21:30.574480
4491 01:21:30.574532 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4492 01:21:30.574584
4493 01:21:30.574637 [CATrainingPosCal] consider 2 rank data
4494 01:21:30.574689 u2DelayCellTimex100 = 270/100 ps
4495 01:21:30.574742 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4496 01:21:30.574795 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4497 01:21:30.574848 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4498 01:21:30.574899 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4499 01:21:30.574951 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4500 01:21:30.575003 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4501 01:21:30.575056
4502 01:21:30.575108 CA PerBit enable=1, Macro0, CA PI delay=33
4503 01:21:30.575160
4504 01:21:30.575211 [CBTSetCACLKResult] CA Dly = 33
4505 01:21:30.575264 CS Dly: 4 (0~36)
4506 01:21:30.575316
4507 01:21:30.575368 ----->DramcWriteLeveling(PI) begin...
4508 01:21:30.575422 ==
4509 01:21:30.575474 Dram Type= 6, Freq= 0, CH_1, rank 0
4510 01:21:30.575527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4511 01:21:30.575580 ==
4512 01:21:30.575633 Write leveling (Byte 0): 28 => 28
4513 01:21:30.575685 Write leveling (Byte 1): 30 => 30
4514 01:21:30.575738 DramcWriteLeveling(PI) end<-----
4515 01:21:30.575790
4516 01:21:30.575842 ==
4517 01:21:30.575895 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 01:21:30.575947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 01:21:30.576000 ==
4520 01:21:30.576052 [Gating] SW mode calibration
4521 01:21:30.576105 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4522 01:21:30.576159 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4523 01:21:30.576212 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4524 01:21:30.576265 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4525 01:21:30.576317 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4526 01:21:30.576370 0 9 12 | B1->B0 | 3131 2c2c | 0 0 | (0 0) (0 1)
4527 01:21:30.576423 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4528 01:21:30.576475 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4529 01:21:30.576527 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4530 01:21:30.576579 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4531 01:21:30.576631 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4532 01:21:30.576683 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4533 01:21:30.576735 0 10 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
4534 01:21:30.576787 0 10 12 | B1->B0 | 2c2c 3a3a | 1 0 | (0 0) (0 0)
4535 01:21:30.576840 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4536 01:21:30.576893 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4537 01:21:30.576945 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4538 01:21:30.576997 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4539 01:21:30.577050 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4540 01:21:30.577102 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4541 01:21:30.577155 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4542 01:21:30.577207 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4543 01:21:30.577260 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 01:21:30.577312 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 01:21:30.577406 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 01:21:30.577459 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 01:21:30.577512 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4548 01:21:30.577565 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4549 01:21:30.577617 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4550 01:21:30.577669 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4551 01:21:30.577721 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4552 01:21:30.577773 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4553 01:21:30.577825 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4554 01:21:30.577877 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4555 01:21:30.577930 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4556 01:21:30.577983 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4557 01:21:30.578036 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4558 01:21:30.578088 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4559 01:21:30.578140 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4560 01:21:30.578192 Total UI for P1: 0, mck2ui 16
4561 01:21:30.578245 best dqsien dly found for B0: ( 0, 13, 12)
4562 01:21:30.578299 Total UI for P1: 0, mck2ui 16
4563 01:21:30.578352 best dqsien dly found for B1: ( 0, 13, 14)
4564 01:21:30.578405 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4565 01:21:30.578646 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4566 01:21:30.578707
4567 01:21:30.578761 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4568 01:21:30.578814 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4569 01:21:30.578867 [Gating] SW calibration Done
4570 01:21:30.578919 ==
4571 01:21:30.578972 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 01:21:30.579024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 01:21:30.579078 ==
4574 01:21:30.579130 RX Vref Scan: 0
4575 01:21:30.579182
4576 01:21:30.579234 RX Vref 0 -> 0, step: 1
4577 01:21:30.579286
4578 01:21:30.579338 RX Delay -230 -> 252, step: 16
4579 01:21:30.579391 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4580 01:21:30.579445 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4581 01:21:30.579497 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4582 01:21:30.579549 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4583 01:21:30.579602 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4584 01:21:30.579654 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4585 01:21:30.579706 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4586 01:21:30.579759 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4587 01:21:30.579811 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4588 01:21:30.579863 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4589 01:21:30.579916 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4590 01:21:30.579968 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4591 01:21:30.580021 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4592 01:21:30.580075 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4593 01:21:30.580128 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4594 01:21:30.580180 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4595 01:21:30.580233 ==
4596 01:21:30.580286 Dram Type= 6, Freq= 0, CH_1, rank 0
4597 01:21:30.580339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4598 01:21:30.580391 ==
4599 01:21:30.580444 DQS Delay:
4600 01:21:30.580497 DQS0 = 0, DQS1 = 0
4601 01:21:30.580549 DQM Delay:
4602 01:21:30.580601 DQM0 = 44, DQM1 = 36
4603 01:21:30.580653 DQ Delay:
4604 01:21:30.580705 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4605 01:21:30.580757 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4606 01:21:30.580810 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4607 01:21:30.580862 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4608 01:21:30.580915
4609 01:21:30.580966
4610 01:21:30.581018 ==
4611 01:21:30.581070 Dram Type= 6, Freq= 0, CH_1, rank 0
4612 01:21:30.581122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 01:21:30.581175 ==
4614 01:21:30.581227
4615 01:21:30.581279
4616 01:21:30.581348 TX Vref Scan disable
4617 01:21:30.581407 == TX Byte 0 ==
4618 01:21:30.581460 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4619 01:21:30.581513 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4620 01:21:30.581566 == TX Byte 1 ==
4621 01:21:30.581619 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4622 01:21:30.581672 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4623 01:21:30.581724 ==
4624 01:21:30.581777 Dram Type= 6, Freq= 0, CH_1, rank 0
4625 01:21:30.581830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4626 01:21:30.581883 ==
4627 01:21:30.581935
4628 01:21:30.581987
4629 01:21:30.582039 TX Vref Scan disable
4630 01:21:30.582091 == TX Byte 0 ==
4631 01:21:30.582143 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4632 01:21:30.582195 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4633 01:21:30.582247 == TX Byte 1 ==
4634 01:21:30.582300 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4635 01:21:30.582353 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4636 01:21:30.582423
4637 01:21:30.582478 [DATLAT]
4638 01:21:30.582530 Freq=600, CH1 RK0
4639 01:21:30.582583
4640 01:21:30.582634 DATLAT Default: 0x9
4641 01:21:30.582687 0, 0xFFFF, sum = 0
4642 01:21:30.582741 1, 0xFFFF, sum = 0
4643 01:21:30.582794 2, 0xFFFF, sum = 0
4644 01:21:30.582847 3, 0xFFFF, sum = 0
4645 01:21:30.582900 4, 0xFFFF, sum = 0
4646 01:21:30.582952 5, 0xFFFF, sum = 0
4647 01:21:30.583005 6, 0xFFFF, sum = 0
4648 01:21:30.583058 7, 0xFFFF, sum = 0
4649 01:21:30.583111 8, 0x0, sum = 1
4650 01:21:30.583164 9, 0x0, sum = 2
4651 01:21:30.583217 10, 0x0, sum = 3
4652 01:21:30.583270 11, 0x0, sum = 4
4653 01:21:30.583323 best_step = 9
4654 01:21:30.583375
4655 01:21:30.583427 ==
4656 01:21:30.583479 Dram Type= 6, Freq= 0, CH_1, rank 0
4657 01:21:30.583531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 01:21:30.583622 ==
4659 01:21:30.583674 RX Vref Scan: 1
4660 01:21:30.583727
4661 01:21:30.583779 RX Vref 0 -> 0, step: 1
4662 01:21:30.583831
4663 01:21:30.583884 RX Delay -195 -> 252, step: 8
4664 01:21:30.583936
4665 01:21:30.583988 Set Vref, RX VrefLevel [Byte0]: 51
4666 01:21:30.584040 [Byte1]: 59
4667 01:21:30.584092
4668 01:21:30.584144 Final RX Vref Byte 0 = 51 to rank0
4669 01:21:30.584197 Final RX Vref Byte 1 = 59 to rank0
4670 01:21:30.584250 Final RX Vref Byte 0 = 51 to rank1
4671 01:21:30.584302 Final RX Vref Byte 1 = 59 to rank1==
4672 01:21:30.584355 Dram Type= 6, Freq= 0, CH_1, rank 0
4673 01:21:30.584407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 01:21:30.584460 ==
4675 01:21:30.584512 DQS Delay:
4676 01:21:30.584565 DQS0 = 0, DQS1 = 0
4677 01:21:30.584617 DQM Delay:
4678 01:21:30.584668 DQM0 = 45, DQM1 = 35
4679 01:21:30.584722 DQ Delay:
4680 01:21:30.584774 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =40
4681 01:21:30.584826 DQ4 =40, DQ5 =56, DQ6 =56, DQ7 =44
4682 01:21:30.584878 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4683 01:21:30.584931 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4684 01:21:30.584983
4685 01:21:30.585035
4686 01:21:30.585088 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a2f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4687 01:21:30.585141 CH1 RK0: MR19=808, MR18=4A2F
4688 01:21:30.585193 CH1_RK0: MR19=0x808, MR18=0x4A2F, DQSOSC=395, MR23=63, INC=168, DEC=112
4689 01:21:30.585246
4690 01:21:30.585298 ----->DramcWriteLeveling(PI) begin...
4691 01:21:30.585382 ==
4692 01:21:30.585448 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 01:21:30.585501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 01:21:30.585554 ==
4695 01:21:30.585644 Write leveling (Byte 0): 30 => 30
4696 01:21:30.585697 Write leveling (Byte 1): 29 => 29
4697 01:21:30.585749 DramcWriteLeveling(PI) end<-----
4698 01:21:30.585802
4699 01:21:30.585853 ==
4700 01:21:30.585905 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 01:21:30.585958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 01:21:30.586010 ==
4703 01:21:30.586063 [Gating] SW mode calibration
4704 01:21:30.586115 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4705 01:21:30.586169 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4706 01:21:30.586221 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4707 01:21:30.586274 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4708 01:21:30.586327 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4709 01:21:30.586379 0 9 12 | B1->B0 | 3131 3232 | 0 0 | (0 1) (0 1)
4710 01:21:30.586431 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4711 01:21:30.586672 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4712 01:21:30.586733 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4713 01:21:30.586787 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4714 01:21:30.586840 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4715 01:21:30.586892 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4716 01:21:30.586945 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4717 01:21:30.586998 0 10 12 | B1->B0 | 3333 2d2d | 0 0 | (0 0) (0 0)
4718 01:21:30.587051 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4719 01:21:30.587103 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4720 01:21:30.587156 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4721 01:21:30.587209 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4722 01:21:30.587262 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4723 01:21:30.587314 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4724 01:21:30.587366 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4725 01:21:30.587419 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4726 01:21:30.587471 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 01:21:30.587523 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 01:21:30.587576 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 01:21:30.587628 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 01:21:30.587680 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4731 01:21:30.587733 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4732 01:21:30.587785 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4733 01:21:30.587838 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4734 01:21:30.587890 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4735 01:21:30.587942 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4736 01:21:30.587994 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4737 01:21:30.588046 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4738 01:21:30.588098 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4739 01:21:30.588151 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4740 01:21:30.588203 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4741 01:21:30.588255 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4742 01:21:30.588307 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4743 01:21:30.588360 Total UI for P1: 0, mck2ui 16
4744 01:21:30.588412 best dqsien dly found for B0: ( 0, 13, 12)
4745 01:21:30.588465 Total UI for P1: 0, mck2ui 16
4746 01:21:30.588518 best dqsien dly found for B1: ( 0, 13, 12)
4747 01:21:30.588571 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4748 01:21:30.588623 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4749 01:21:30.588674
4750 01:21:30.588726 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4751 01:21:30.588779 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4752 01:21:30.588832 [Gating] SW calibration Done
4753 01:21:30.588884 ==
4754 01:21:30.588936 Dram Type= 6, Freq= 0, CH_1, rank 1
4755 01:21:30.588989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4756 01:21:30.589042 ==
4757 01:21:30.589094 RX Vref Scan: 0
4758 01:21:30.589146
4759 01:21:30.589198 RX Vref 0 -> 0, step: 1
4760 01:21:30.589250
4761 01:21:30.589302 RX Delay -230 -> 252, step: 16
4762 01:21:30.589399 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4763 01:21:30.589453 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4764 01:21:30.589505 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4765 01:21:30.589558 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4766 01:21:30.589610 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4767 01:21:30.589663 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4768 01:21:30.589715 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4769 01:21:30.589768 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4770 01:21:30.589820 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4771 01:21:30.589874 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4772 01:21:30.589926 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4773 01:21:30.589978 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4774 01:21:30.590030 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4775 01:21:30.590083 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4776 01:21:30.590135 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4777 01:21:30.590187 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4778 01:21:30.590239 ==
4779 01:21:30.590291 Dram Type= 6, Freq= 0, CH_1, rank 1
4780 01:21:30.590343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4781 01:21:30.590396 ==
4782 01:21:30.590448 DQS Delay:
4783 01:21:30.590500 DQS0 = 0, DQS1 = 0
4784 01:21:30.590552 DQM Delay:
4785 01:21:30.590604 DQM0 = 42, DQM1 = 34
4786 01:21:30.590657 DQ Delay:
4787 01:21:30.590709 DQ0 =57, DQ1 =33, DQ2 =25, DQ3 =41
4788 01:21:30.590762 DQ4 =33, DQ5 =57, DQ6 =57, DQ7 =33
4789 01:21:30.590815 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4790 01:21:30.590868 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4791 01:21:30.590921
4792 01:21:30.590973
4793 01:21:30.591025 ==
4794 01:21:30.591077 Dram Type= 6, Freq= 0, CH_1, rank 1
4795 01:21:30.591129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4796 01:21:30.591182 ==
4797 01:21:30.591234
4798 01:21:30.591285
4799 01:21:30.591337 TX Vref Scan disable
4800 01:21:30.591389 == TX Byte 0 ==
4801 01:21:30.591442 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4802 01:21:30.591495 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4803 01:21:30.591547 == TX Byte 1 ==
4804 01:21:30.591599 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4805 01:21:30.591652 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4806 01:21:30.591704 ==
4807 01:21:30.591757 Dram Type= 6, Freq= 0, CH_1, rank 1
4808 01:21:30.591810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4809 01:21:30.591862 ==
4810 01:21:30.591915
4811 01:21:30.591966
4812 01:21:30.592018 TX Vref Scan disable
4813 01:21:30.592070 == TX Byte 0 ==
4814 01:21:30.592122 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4815 01:21:30.592175 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4816 01:21:30.592227 == TX Byte 1 ==
4817 01:21:30.592278 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4818 01:21:30.592330 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4819 01:21:30.592382
4820 01:21:30.592433 [DATLAT]
4821 01:21:30.592485 Freq=600, CH1 RK1
4822 01:21:30.592537
4823 01:21:30.592589 DATLAT Default: 0x9
4824 01:21:30.592641 0, 0xFFFF, sum = 0
4825 01:21:30.592694 1, 0xFFFF, sum = 0
4826 01:21:30.592747 2, 0xFFFF, sum = 0
4827 01:21:30.592800 3, 0xFFFF, sum = 0
4828 01:21:30.592853 4, 0xFFFF, sum = 0
4829 01:21:30.593098 5, 0xFFFF, sum = 0
4830 01:21:30.593160 6, 0xFFFF, sum = 0
4831 01:21:30.593214 7, 0xFFFF, sum = 0
4832 01:21:30.593268 8, 0x0, sum = 1
4833 01:21:30.593322 9, 0x0, sum = 2
4834 01:21:30.593414 10, 0x0, sum = 3
4835 01:21:30.593468 11, 0x0, sum = 4
4836 01:21:30.593521 best_step = 9
4837 01:21:30.593574
4838 01:21:30.593627 ==
4839 01:21:30.593679 Dram Type= 6, Freq= 0, CH_1, rank 1
4840 01:21:30.593732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4841 01:21:30.593784 ==
4842 01:21:30.593837 RX Vref Scan: 0
4843 01:21:30.593889
4844 01:21:30.593942 RX Vref 0 -> 0, step: 1
4845 01:21:30.593994
4846 01:21:30.594046 RX Delay -195 -> 252, step: 8
4847 01:21:30.594100 iDelay=213, Bit 0, Center 44 (-107 ~ 196) 304
4848 01:21:30.594152 iDelay=213, Bit 1, Center 36 (-115 ~ 188) 304
4849 01:21:30.594205 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4850 01:21:30.594257 iDelay=213, Bit 3, Center 36 (-115 ~ 188) 304
4851 01:21:30.594310 iDelay=213, Bit 4, Center 40 (-115 ~ 196) 312
4852 01:21:30.594362 iDelay=213, Bit 5, Center 52 (-99 ~ 204) 304
4853 01:21:30.594414 iDelay=213, Bit 6, Center 56 (-99 ~ 212) 312
4854 01:21:30.594467 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4855 01:21:30.594519 iDelay=213, Bit 8, Center 20 (-139 ~ 180) 320
4856 01:21:30.594571 iDelay=213, Bit 9, Center 20 (-139 ~ 180) 320
4857 01:21:30.594624 iDelay=213, Bit 10, Center 36 (-123 ~ 196) 320
4858 01:21:30.594676 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4859 01:21:30.594728 iDelay=213, Bit 12, Center 44 (-115 ~ 204) 320
4860 01:21:30.594781 iDelay=213, Bit 13, Center 44 (-115 ~ 204) 320
4861 01:21:30.594834 iDelay=213, Bit 14, Center 40 (-115 ~ 196) 312
4862 01:21:30.594886 iDelay=213, Bit 15, Center 44 (-115 ~ 204) 320
4863 01:21:30.594939 ==
4864 01:21:30.594991 Dram Type= 6, Freq= 0, CH_1, rank 1
4865 01:21:30.595043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4866 01:21:30.595097 ==
4867 01:21:30.595149 DQS Delay:
4868 01:21:30.595201 DQS0 = 0, DQS1 = 0
4869 01:21:30.595253 DQM Delay:
4870 01:21:30.595305 DQM0 = 42, DQM1 = 34
4871 01:21:30.595357 DQ Delay:
4872 01:21:30.595409 DQ0 =44, DQ1 =36, DQ2 =32, DQ3 =36
4873 01:21:30.595461 DQ4 =40, DQ5 =52, DQ6 =56, DQ7 =40
4874 01:21:30.595515 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4875 01:21:30.595567 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =44
4876 01:21:30.595620
4877 01:21:30.595672
4878 01:21:30.595724 [DQSOSCAuto] RK1, (LSB)MR18= 0x241a, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
4879 01:21:30.595777 CH1 RK1: MR19=808, MR18=241A
4880 01:21:30.595830 CH1_RK1: MR19=0x808, MR18=0x241A, DQSOSC=403, MR23=63, INC=161, DEC=107
4881 01:21:30.595884 [RxdqsGatingPostProcess] freq 600
4882 01:21:30.595936 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4883 01:21:30.595989 Pre-setting of DQS Precalculation
4884 01:21:30.596042 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4885 01:21:30.596096 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4886 01:21:30.596150 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4887 01:21:30.596203
4888 01:21:30.596254
4889 01:21:30.596306 [Calibration Summary] 1200 Mbps
4890 01:21:30.596358 CH 0, Rank 0
4891 01:21:30.596411 SW Impedance : PASS
4892 01:21:30.596463 DUTY Scan : NO K
4893 01:21:30.596516 ZQ Calibration : PASS
4894 01:21:30.596568 Jitter Meter : NO K
4895 01:21:30.596620 CBT Training : PASS
4896 01:21:30.596672 Write leveling : PASS
4897 01:21:30.596724 RX DQS gating : PASS
4898 01:21:30.596777 RX DQ/DQS(RDDQC) : PASS
4899 01:21:30.596829 TX DQ/DQS : PASS
4900 01:21:30.596882 RX DATLAT : PASS
4901 01:21:30.596934 RX DQ/DQS(Engine): PASS
4902 01:21:30.596986 TX OE : NO K
4903 01:21:30.597039 All Pass.
4904 01:21:30.597092
4905 01:21:30.597144 CH 0, Rank 1
4906 01:21:30.597196 SW Impedance : PASS
4907 01:21:30.597248 DUTY Scan : NO K
4908 01:21:30.597300 ZQ Calibration : PASS
4909 01:21:30.597413 Jitter Meter : NO K
4910 01:21:30.597479 CBT Training : PASS
4911 01:21:30.597532 Write leveling : PASS
4912 01:21:30.597585 RX DQS gating : PASS
4913 01:21:30.597637 RX DQ/DQS(RDDQC) : PASS
4914 01:21:30.597707 TX DQ/DQS : PASS
4915 01:21:30.597774 RX DATLAT : PASS
4916 01:21:30.597826 RX DQ/DQS(Engine): PASS
4917 01:21:30.597879 TX OE : NO K
4918 01:21:30.597931 All Pass.
4919 01:21:30.597984
4920 01:21:30.598036 CH 1, Rank 0
4921 01:21:30.598088 SW Impedance : PASS
4922 01:21:30.598141 DUTY Scan : NO K
4923 01:21:30.598194 ZQ Calibration : PASS
4924 01:21:30.598246 Jitter Meter : NO K
4925 01:21:30.598299 CBT Training : PASS
4926 01:21:30.598351 Write leveling : PASS
4927 01:21:30.598403 RX DQS gating : PASS
4928 01:21:30.598455 RX DQ/DQS(RDDQC) : PASS
4929 01:21:30.598507 TX DQ/DQS : PASS
4930 01:21:30.598560 RX DATLAT : PASS
4931 01:21:30.598612 RX DQ/DQS(Engine): PASS
4932 01:21:30.598664 TX OE : NO K
4933 01:21:30.598716 All Pass.
4934 01:21:30.598773
4935 01:21:30.598837 CH 1, Rank 1
4936 01:21:30.598891 SW Impedance : PASS
4937 01:21:30.598944 DUTY Scan : NO K
4938 01:21:30.598997 ZQ Calibration : PASS
4939 01:21:30.599049 Jitter Meter : NO K
4940 01:21:30.599102 CBT Training : PASS
4941 01:21:30.599154 Write leveling : PASS
4942 01:21:30.599207 RX DQS gating : PASS
4943 01:21:30.599259 RX DQ/DQS(RDDQC) : PASS
4944 01:21:30.599311 TX DQ/DQS : PASS
4945 01:21:30.599364 RX DATLAT : PASS
4946 01:21:30.599417 RX DQ/DQS(Engine): PASS
4947 01:21:30.599469 TX OE : NO K
4948 01:21:30.599522 All Pass.
4949 01:21:30.599575
4950 01:21:30.599627 DramC Write-DBI off
4951 01:21:30.599679 PER_BANK_REFRESH: Hybrid Mode
4952 01:21:30.599732 TX_TRACKING: ON
4953 01:21:30.599785 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4954 01:21:30.599838 [FAST_K] Save calibration result to emmc
4955 01:21:30.599891 dramc_set_vcore_voltage set vcore to 662500
4956 01:21:30.599944 Read voltage for 933, 3
4957 01:21:30.599997 Vio18 = 0
4958 01:21:30.600050 Vcore = 662500
4959 01:21:30.600112 Vdram = 0
4960 01:21:30.600166 Vddq = 0
4961 01:21:30.600218 Vmddr = 0
4962 01:21:30.600270 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4963 01:21:30.600324 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4964 01:21:30.600377 MEM_TYPE=3, freq_sel=17
4965 01:21:30.600430 sv_algorithm_assistance_LP4_1600
4966 01:21:30.600483 ============ PULL DRAM RESETB DOWN ============
4967 01:21:30.600537 ========== PULL DRAM RESETB DOWN end =========
4968 01:21:30.600590 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4969 01:21:30.600643 ===================================
4970 01:21:30.600695 LPDDR4 DRAM CONFIGURATION
4971 01:21:30.600748 ===================================
4972 01:21:30.600991 EX_ROW_EN[0] = 0x0
4973 01:21:30.601051 EX_ROW_EN[1] = 0x0
4974 01:21:30.601147 LP4Y_EN = 0x0
4975 01:21:30.601199 WORK_FSP = 0x0
4976 01:21:30.601268 WL = 0x3
4977 01:21:30.601335 RL = 0x3
4978 01:21:30.601407 BL = 0x2
4979 01:21:30.601459 RPST = 0x0
4980 01:21:30.601511 RD_PRE = 0x0
4981 01:21:30.601564 WR_PRE = 0x1
4982 01:21:30.601615 WR_PST = 0x0
4983 01:21:30.601668 DBI_WR = 0x0
4984 01:21:30.601719 DBI_RD = 0x0
4985 01:21:30.601771 OTF = 0x1
4986 01:21:30.601823 ===================================
4987 01:21:30.601876 ===================================
4988 01:21:30.601928 ANA top config
4989 01:21:30.601980 ===================================
4990 01:21:30.602032 DLL_ASYNC_EN = 0
4991 01:21:30.602085 ALL_SLAVE_EN = 1
4992 01:21:30.602138 NEW_RANK_MODE = 1
4993 01:21:30.602190 DLL_IDLE_MODE = 1
4994 01:21:30.602243 LP45_APHY_COMB_EN = 1
4995 01:21:30.602295 TX_ODT_DIS = 1
4996 01:21:30.602348 NEW_8X_MODE = 1
4997 01:21:30.602400 ===================================
4998 01:21:31.331740 ===================================
4999 01:21:31.332368 data_rate = 1866
5000 01:21:31.332628 CKR = 1
5001 01:21:31.332702 DQ_P2S_RATIO = 8
5002 01:21:31.332760 ===================================
5003 01:21:31.332817 CA_P2S_RATIO = 8
5004 01:21:31.332872 DQ_CA_OPEN = 0
5005 01:21:31.332927 DQ_SEMI_OPEN = 0
5006 01:21:31.332981 CA_SEMI_OPEN = 0
5007 01:21:31.333034 CA_FULL_RATE = 0
5008 01:21:31.333087 DQ_CKDIV4_EN = 1
5009 01:21:31.333140 CA_CKDIV4_EN = 1
5010 01:21:31.333192 CA_PREDIV_EN = 0
5011 01:21:31.333244 PH8_DLY = 0
5012 01:21:31.333297 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5013 01:21:31.333379 DQ_AAMCK_DIV = 4
5014 01:21:31.333458 CA_AAMCK_DIV = 4
5015 01:21:31.333510 CA_ADMCK_DIV = 4
5016 01:21:31.333561 DQ_TRACK_CA_EN = 0
5017 01:21:31.333613 CA_PICK = 933
5018 01:21:31.333665 CA_MCKIO = 933
5019 01:21:31.333717 MCKIO_SEMI = 0
5020 01:21:31.333768 PLL_FREQ = 3732
5021 01:21:31.333820 DQ_UI_PI_RATIO = 32
5022 01:21:31.333872 CA_UI_PI_RATIO = 0
5023 01:21:31.333924 ===================================
5024 01:21:31.333976 ===================================
5025 01:21:31.334028 memory_type:LPDDR4
5026 01:21:31.334080 GP_NUM : 10
5027 01:21:31.334160 SRAM_EN : 1
5028 01:21:31.334212 MD32_EN : 0
5029 01:21:31.334264 ===================================
5030 01:21:31.334316 [ANA_INIT] >>>>>>>>>>>>>>
5031 01:21:31.334368 <<<<<< [CONFIGURE PHASE]: ANA_TX
5032 01:21:31.334420 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5033 01:21:31.334472 ===================================
5034 01:21:31.334525 data_rate = 1866,PCW = 0X8f00
5035 01:21:31.334577 ===================================
5036 01:21:31.334629 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5037 01:21:31.334715 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5038 01:21:31.334771 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5039 01:21:31.334853 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5040 01:21:31.334927 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5041 01:21:31.334982 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5042 01:21:31.335034 [ANA_INIT] flow start
5043 01:21:31.335087 [ANA_INIT] PLL >>>>>>>>
5044 01:21:31.335139 [ANA_INIT] PLL <<<<<<<<
5045 01:21:31.335191 [ANA_INIT] MIDPI >>>>>>>>
5046 01:21:31.335243 [ANA_INIT] MIDPI <<<<<<<<
5047 01:21:31.335294 [ANA_INIT] DLL >>>>>>>>
5048 01:21:31.335346 [ANA_INIT] flow end
5049 01:21:31.335397 ============ LP4 DIFF to SE enter ============
5050 01:21:31.335450 ============ LP4 DIFF to SE exit ============
5051 01:21:31.335502 [ANA_INIT] <<<<<<<<<<<<<
5052 01:21:31.335554 [Flow] Enable top DCM control >>>>>
5053 01:21:31.335605 [Flow] Enable top DCM control <<<<<
5054 01:21:31.335657 Enable DLL master slave shuffle
5055 01:21:31.335709 ==============================================================
5056 01:21:31.335762 Gating Mode config
5057 01:21:31.335814 ==============================================================
5058 01:21:31.335865 Config description:
5059 01:21:31.335918 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5060 01:21:31.335971 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5061 01:21:31.336024 SELPH_MODE 0: By rank 1: By Phase
5062 01:21:31.336076 ==============================================================
5063 01:21:31.336128 GAT_TRACK_EN = 1
5064 01:21:31.336180 RX_GATING_MODE = 2
5065 01:21:31.336232 RX_GATING_TRACK_MODE = 2
5066 01:21:31.336284 SELPH_MODE = 1
5067 01:21:31.336336 PICG_EARLY_EN = 1
5068 01:21:31.336387 VALID_LAT_VALUE = 1
5069 01:21:31.336438 ==============================================================
5070 01:21:31.336491 Enter into Gating configuration >>>>
5071 01:21:31.336543 Exit from Gating configuration <<<<
5072 01:21:31.336594 Enter into DVFS_PRE_config >>>>>
5073 01:21:31.336646 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5074 01:21:31.336699 Exit from DVFS_PRE_config <<<<<
5075 01:21:31.336751 Enter into PICG configuration >>>>
5076 01:21:31.336802 Exit from PICG configuration <<<<
5077 01:21:31.336854 [RX_INPUT] configuration >>>>>
5078 01:21:31.336905 [RX_INPUT] configuration <<<<<
5079 01:21:31.336956 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5080 01:21:31.337008 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5081 01:21:31.337060 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5082 01:21:31.337112 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5083 01:21:31.337427 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5084 01:21:31.337491 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5085 01:21:31.337547 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5086 01:21:31.337601 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5087 01:21:31.337655 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5088 01:21:31.337708 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5089 01:21:31.337761 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5090 01:21:31.337814 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5091 01:21:31.337880 ===================================
5092 01:21:31.337932 LPDDR4 DRAM CONFIGURATION
5093 01:21:31.337984 ===================================
5094 01:21:31.338037 EX_ROW_EN[0] = 0x0
5095 01:21:31.338089 EX_ROW_EN[1] = 0x0
5096 01:21:31.338142 LP4Y_EN = 0x0
5097 01:21:31.338194 WORK_FSP = 0x0
5098 01:21:31.338246 WL = 0x3
5099 01:21:31.338298 RL = 0x3
5100 01:21:31.338349 BL = 0x2
5101 01:21:31.338401 RPST = 0x0
5102 01:21:31.338452 RD_PRE = 0x0
5103 01:21:31.338504 WR_PRE = 0x1
5104 01:21:31.338556 WR_PST = 0x0
5105 01:21:31.338607 DBI_WR = 0x0
5106 01:21:31.338659 DBI_RD = 0x0
5107 01:21:31.338710 OTF = 0x1
5108 01:21:31.338763 ===================================
5109 01:21:31.338816 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5110 01:21:31.338868 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5111 01:21:31.338921 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5112 01:21:31.338973 ===================================
5113 01:21:31.339026 LPDDR4 DRAM CONFIGURATION
5114 01:21:31.339078 ===================================
5115 01:21:31.339130 EX_ROW_EN[0] = 0x10
5116 01:21:31.339183 EX_ROW_EN[1] = 0x0
5117 01:21:31.339235 LP4Y_EN = 0x0
5118 01:21:31.339288 WORK_FSP = 0x0
5119 01:21:31.339340 WL = 0x3
5120 01:21:31.339392 RL = 0x3
5121 01:21:31.339444 BL = 0x2
5122 01:21:31.339496 RPST = 0x0
5123 01:21:31.339596 RD_PRE = 0x0
5124 01:21:31.339653 WR_PRE = 0x1
5125 01:21:31.339705 WR_PST = 0x0
5126 01:21:31.339758 DBI_WR = 0x0
5127 01:21:31.339810 DBI_RD = 0x0
5128 01:21:31.339863 OTF = 0x1
5129 01:21:31.339916 ===================================
5130 01:21:31.339968 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5131 01:21:31.340022 nWR fixed to 30
5132 01:21:31.340076 [ModeRegInit_LP4] CH0 RK0
5133 01:21:31.340129 [ModeRegInit_LP4] CH0 RK1
5134 01:21:31.340182 [ModeRegInit_LP4] CH1 RK0
5135 01:21:31.340234 [ModeRegInit_LP4] CH1 RK1
5136 01:21:31.340287 match AC timing 9
5137 01:21:31.340339 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5138 01:21:31.340392 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5139 01:21:31.340445 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5140 01:21:31.340497 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5141 01:21:31.340550 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5142 01:21:31.340603 ==
5143 01:21:31.340656 Dram Type= 6, Freq= 0, CH_0, rank 0
5144 01:21:31.340709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5145 01:21:31.340762 ==
5146 01:21:31.340815 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5147 01:21:31.340868 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5148 01:21:31.340921 [CA 0] Center 37 (7~68) winsize 62
5149 01:21:31.340974 [CA 1] Center 37 (7~68) winsize 62
5150 01:21:31.341026 [CA 2] Center 34 (4~65) winsize 62
5151 01:21:31.341078 [CA 3] Center 35 (4~66) winsize 63
5152 01:21:31.341131 [CA 4] Center 33 (3~64) winsize 62
5153 01:21:31.341183 [CA 5] Center 34 (4~64) winsize 61
5154 01:21:31.341235
5155 01:21:31.341288 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5156 01:21:31.341368
5157 01:21:31.341435 [CATrainingPosCal] consider 1 rank data
5158 01:21:31.341488 u2DelayCellTimex100 = 270/100 ps
5159 01:21:31.341541 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5160 01:21:31.341594 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5161 01:21:31.341647 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5162 01:21:31.341700 CA3 delay=35 (4~66),Diff = 2 PI (12 cell)
5163 01:21:31.341752 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5164 01:21:31.341805 CA5 delay=34 (4~64),Diff = 1 PI (6 cell)
5165 01:21:31.341857
5166 01:21:31.341909 CA PerBit enable=1, Macro0, CA PI delay=33
5167 01:21:31.341962
5168 01:21:31.342013 [CBTSetCACLKResult] CA Dly = 33
5169 01:21:31.342066 CS Dly: 7 (0~38)
5170 01:21:31.342118 ==
5171 01:21:31.342170 Dram Type= 6, Freq= 0, CH_0, rank 1
5172 01:21:31.342223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 01:21:31.342276 ==
5174 01:21:31.342328 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5175 01:21:31.342381 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5176 01:21:31.342434 [CA 0] Center 37 (7~68) winsize 62
5177 01:21:31.342486 [CA 1] Center 37 (7~68) winsize 62
5178 01:21:31.342539 [CA 2] Center 34 (4~65) winsize 62
5179 01:21:31.342591 [CA 3] Center 34 (4~65) winsize 62
5180 01:21:31.342644 [CA 4] Center 33 (3~64) winsize 62
5181 01:21:31.342734 [CA 5] Center 33 (3~63) winsize 61
5182 01:21:31.342796
5183 01:21:31.342849 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5184 01:21:31.342901
5185 01:21:31.342953 [CATrainingPosCal] consider 2 rank data
5186 01:21:31.343005 u2DelayCellTimex100 = 270/100 ps
5187 01:21:31.343058 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5188 01:21:31.343110 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5189 01:21:31.343162 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5190 01:21:31.343214 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5191 01:21:31.343267 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5192 01:21:31.343319 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5193 01:21:31.343371
5194 01:21:31.343423 CA PerBit enable=1, Macro0, CA PI delay=33
5195 01:21:31.343476
5196 01:21:31.343528 [CBTSetCACLKResult] CA Dly = 33
5197 01:21:31.343580 CS Dly: 7 (0~39)
5198 01:21:31.343632
5199 01:21:31.343684 ----->DramcWriteLeveling(PI) begin...
5200 01:21:31.343737 ==
5201 01:21:31.343789 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 01:21:31.343842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 01:21:31.343894 ==
5204 01:21:31.343946 Write leveling (Byte 0): 32 => 32
5205 01:21:31.343999 Write leveling (Byte 1): 31 => 31
5206 01:21:31.344051 DramcWriteLeveling(PI) end<-----
5207 01:21:31.344104
5208 01:21:31.344155 ==
5209 01:21:31.344207 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 01:21:31.344259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 01:21:31.344312 ==
5212 01:21:31.344364 [Gating] SW mode calibration
5213 01:21:31.344606 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5214 01:21:31.344686 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5215 01:21:31.344741 0 14 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5216 01:21:31.344796 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5217 01:21:31.344868 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5218 01:21:31.344925 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5219 01:21:31.344979 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5220 01:21:31.345032 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5221 01:21:31.345086 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5222 01:21:31.345151 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5223 01:21:31.345204 0 15 0 | B1->B0 | 3030 2525 | 1 1 | (1 0) (1 0)
5224 01:21:31.345257 0 15 4 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
5225 01:21:31.345325 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5226 01:21:31.345433 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5227 01:21:31.345486 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5228 01:21:31.345538 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5229 01:21:31.345591 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5230 01:21:31.345643 0 15 28 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
5231 01:21:31.345696 1 0 0 | B1->B0 | 3333 4545 | 0 0 | (0 0) (0 0)
5232 01:21:31.345748 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5233 01:21:31.345801 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5234 01:21:31.345852 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5235 01:21:31.345905 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5236 01:21:31.345958 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5237 01:21:31.346010 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5238 01:21:31.346062 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5239 01:21:31.346113 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5240 01:21:31.346166 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 01:21:31.346218 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 01:21:31.346270 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5243 01:21:31.346322 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 01:21:31.346375 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5245 01:21:31.346428 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5246 01:21:31.346480 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5247 01:21:31.346532 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5248 01:21:31.346600 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5249 01:21:31.346688 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5250 01:21:31.346743 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5251 01:21:31.346796 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5252 01:21:31.346849 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5253 01:21:31.346901 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5254 01:21:31.346953 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5255 01:21:31.347006 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5256 01:21:31.347059 Total UI for P1: 0, mck2ui 16
5257 01:21:31.347112 best dqsien dly found for B0: ( 1, 2, 30)
5258 01:21:31.347165 Total UI for P1: 0, mck2ui 16
5259 01:21:31.347218 best dqsien dly found for B1: ( 1, 2, 30)
5260 01:21:31.347270 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5261 01:21:31.347323 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5262 01:21:31.347375
5263 01:21:31.347427 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5264 01:21:31.347479 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5265 01:21:31.347532 [Gating] SW calibration Done
5266 01:21:31.347584 ==
5267 01:21:31.347636 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 01:21:31.347689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 01:21:31.347741 ==
5270 01:21:31.347793 RX Vref Scan: 0
5271 01:21:31.347845
5272 01:21:31.347897 RX Vref 0 -> 0, step: 1
5273 01:21:31.347949
5274 01:21:31.348000 RX Delay -80 -> 252, step: 8
5275 01:21:31.348052 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5276 01:21:31.348105 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5277 01:21:31.348157 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5278 01:21:31.348210 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5279 01:21:31.348262 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5280 01:21:31.348314 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5281 01:21:31.348367 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5282 01:21:31.348419 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5283 01:21:31.348471 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5284 01:21:31.348523 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5285 01:21:31.348575 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5286 01:21:31.348628 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5287 01:21:31.348680 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5288 01:21:31.348732 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5289 01:21:31.348784 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5290 01:21:31.348836 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5291 01:21:31.348888 ==
5292 01:21:31.348940 Dram Type= 6, Freq= 0, CH_0, rank 0
5293 01:21:31.348992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 01:21:31.349045 ==
5295 01:21:31.349097 DQS Delay:
5296 01:21:31.349149 DQS0 = 0, DQS1 = 0
5297 01:21:31.349202 DQM Delay:
5298 01:21:31.349254 DQM0 = 96, DQM1 = 84
5299 01:21:31.349306 DQ Delay:
5300 01:21:31.349438 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5301 01:21:31.349494 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5302 01:21:31.349546 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =79
5303 01:21:31.349599 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5304 01:21:31.349651
5305 01:21:31.349702
5306 01:21:31.349754 ==
5307 01:21:31.349806 Dram Type= 6, Freq= 0, CH_0, rank 0
5308 01:21:31.349858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5309 01:21:31.349910 ==
5310 01:21:31.349963
5311 01:21:31.350014
5312 01:21:31.350081 TX Vref Scan disable
5313 01:21:31.350169 == TX Byte 0 ==
5314 01:21:31.350223 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5315 01:21:31.350276 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5316 01:21:31.350329 == TX Byte 1 ==
5317 01:21:31.350381 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5318 01:21:31.350623 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5319 01:21:31.350736 ==
5320 01:21:31.350791 Dram Type= 6, Freq= 0, CH_0, rank 0
5321 01:21:31.350845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5322 01:21:31.350899 ==
5323 01:21:31.350953
5324 01:21:31.351006
5325 01:21:31.351059 TX Vref Scan disable
5326 01:21:31.351112 == TX Byte 0 ==
5327 01:21:31.351178 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5328 01:21:31.351230 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5329 01:21:31.351282 == TX Byte 1 ==
5330 01:21:31.351334 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5331 01:21:31.351387 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5332 01:21:31.351439
5333 01:21:31.351491 [DATLAT]
5334 01:21:31.351543 Freq=933, CH0 RK0
5335 01:21:31.351595
5336 01:21:31.351647 DATLAT Default: 0xd
5337 01:21:31.351699 0, 0xFFFF, sum = 0
5338 01:21:31.351753 1, 0xFFFF, sum = 0
5339 01:21:31.351806 2, 0xFFFF, sum = 0
5340 01:21:31.351859 3, 0xFFFF, sum = 0
5341 01:21:31.351912 4, 0xFFFF, sum = 0
5342 01:21:31.351965 5, 0xFFFF, sum = 0
5343 01:21:31.352018 6, 0xFFFF, sum = 0
5344 01:21:31.352071 7, 0xFFFF, sum = 0
5345 01:21:31.352124 8, 0xFFFF, sum = 0
5346 01:21:31.352176 9, 0xFFFF, sum = 0
5347 01:21:31.352229 10, 0x0, sum = 1
5348 01:21:31.352282 11, 0x0, sum = 2
5349 01:21:31.352335 12, 0x0, sum = 3
5350 01:21:31.352387 13, 0x0, sum = 4
5351 01:21:31.352440 best_step = 11
5352 01:21:31.352507
5353 01:21:31.352571 ==
5354 01:21:31.352623 Dram Type= 6, Freq= 0, CH_0, rank 0
5355 01:21:31.352676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5356 01:21:31.352729 ==
5357 01:21:31.352781 RX Vref Scan: 1
5358 01:21:31.352833
5359 01:21:31.352885 RX Vref 0 -> 0, step: 1
5360 01:21:31.352937
5361 01:21:31.352988 RX Delay -69 -> 252, step: 4
5362 01:21:31.353040
5363 01:21:31.353091 Set Vref, RX VrefLevel [Byte0]: 57
5364 01:21:31.353143 [Byte1]: 49
5365 01:21:31.353194
5366 01:21:31.353246 Final RX Vref Byte 0 = 57 to rank0
5367 01:21:31.353297 Final RX Vref Byte 1 = 49 to rank0
5368 01:21:31.353376 Final RX Vref Byte 0 = 57 to rank1
5369 01:21:31.353454 Final RX Vref Byte 1 = 49 to rank1==
5370 01:21:31.353506 Dram Type= 6, Freq= 0, CH_0, rank 0
5371 01:21:31.353557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 01:21:31.353609 ==
5373 01:21:31.353661 DQS Delay:
5374 01:21:31.353712 DQS0 = 0, DQS1 = 0
5375 01:21:31.353764 DQM Delay:
5376 01:21:31.353815 DQM0 = 97, DQM1 = 85
5377 01:21:31.353867 DQ Delay:
5378 01:21:31.353918 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5379 01:21:31.353970 DQ4 =98, DQ5 =90, DQ6 =106, DQ7 =106
5380 01:21:31.354021 DQ8 =76, DQ9 =72, DQ10 =86, DQ11 =80
5381 01:21:31.354073 DQ12 =90, DQ13 =90, DQ14 =98, DQ15 =92
5382 01:21:31.354124
5383 01:21:31.354174
5384 01:21:31.354226 [DQSOSCAuto] RK0, (LSB)MR18= 0x260d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 409 ps
5385 01:21:31.354279 CH0 RK0: MR19=505, MR18=260D
5386 01:21:31.354331 CH0_RK0: MR19=0x505, MR18=0x260D, DQSOSC=409, MR23=63, INC=64, DEC=43
5387 01:21:31.354383
5388 01:21:31.354434 ----->DramcWriteLeveling(PI) begin...
5389 01:21:31.354501 ==
5390 01:21:31.354553 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 01:21:31.354639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 01:21:31.354695 ==
5393 01:21:31.354747 Write leveling (Byte 0): 30 => 30
5394 01:21:31.354801 Write leveling (Byte 1): 31 => 31
5395 01:21:31.354852 DramcWriteLeveling(PI) end<-----
5396 01:21:31.354904
5397 01:21:31.354955 ==
5398 01:21:31.355007 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 01:21:31.355059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 01:21:31.355111 ==
5401 01:21:31.355162 [Gating] SW mode calibration
5402 01:21:31.355214 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5403 01:21:31.355269 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5404 01:21:31.355321 0 14 0 | B1->B0 | 2d2d 3434 | 0 0 | (0 0) (0 0)
5405 01:21:31.355373 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5406 01:21:31.355425 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5407 01:21:31.355476 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5408 01:21:31.355528 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5409 01:21:31.355580 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5410 01:21:31.355631 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5411 01:21:31.355683 0 14 28 | B1->B0 | 3434 2e2e | 0 1 | (0 1) (1 1)
5412 01:21:31.355735 0 15 0 | B1->B0 | 2f2f 2727 | 1 1 | (1 0) (1 0)
5413 01:21:31.355786 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5414 01:21:31.355838 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5415 01:21:31.355890 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5416 01:21:31.355941 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5417 01:21:31.355993 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5418 01:21:31.356044 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5419 01:21:31.356096 0 15 28 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
5420 01:21:31.356147 1 0 0 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
5421 01:21:31.356199 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5422 01:21:31.356250 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5423 01:21:31.356302 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5424 01:21:31.356354 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5425 01:21:31.356405 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5426 01:21:31.356457 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5427 01:21:31.356530 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5428 01:21:31.356595 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5429 01:21:31.356647 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 01:21:31.356697 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 01:21:31.356749 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 01:21:31.356800 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 01:21:31.356852 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 01:21:31.356903 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 01:21:31.356954 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 01:21:31.357007 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 01:21:31.357059 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 01:21:31.357111 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 01:21:31.357163 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 01:21:31.357214 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 01:21:31.357265 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 01:21:31.357507 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 01:21:31.357649 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5444 01:21:31.357717 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5445 01:21:31.357770 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5446 01:21:31.357824 Total UI for P1: 0, mck2ui 16
5447 01:21:31.357878 best dqsien dly found for B0: ( 1, 2, 30)
5448 01:21:31.357941 Total UI for P1: 0, mck2ui 16
5449 01:21:31.358005 best dqsien dly found for B1: ( 1, 2, 30)
5450 01:21:31.358059 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5451 01:21:31.358112 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5452 01:21:31.358165
5453 01:21:31.358218 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5454 01:21:31.358270 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5455 01:21:31.358322 [Gating] SW calibration Done
5456 01:21:31.358374 ==
5457 01:21:31.358427 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 01:21:31.358480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 01:21:31.358532 ==
5460 01:21:31.358585 RX Vref Scan: 0
5461 01:21:31.358638
5462 01:21:31.358690 RX Vref 0 -> 0, step: 1
5463 01:21:31.358743
5464 01:21:31.358795 RX Delay -80 -> 252, step: 8
5465 01:21:31.358848 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5466 01:21:31.358901 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5467 01:21:31.358954 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5468 01:21:31.359006 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5469 01:21:31.359059 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5470 01:21:31.359112 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5471 01:21:31.359164 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5472 01:21:31.359217 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5473 01:21:31.359275 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5474 01:21:31.359329 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5475 01:21:31.359381 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5476 01:21:31.359434 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5477 01:21:31.359487 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5478 01:21:31.359539 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5479 01:21:31.359591 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5480 01:21:31.359643 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5481 01:21:31.359695 ==
5482 01:21:31.359748 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 01:21:31.359800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 01:21:31.359854 ==
5485 01:21:31.359906 DQS Delay:
5486 01:21:31.359958 DQS0 = 0, DQS1 = 0
5487 01:21:31.360011 DQM Delay:
5488 01:21:31.360062 DQM0 = 97, DQM1 = 87
5489 01:21:31.360124 DQ Delay:
5490 01:21:31.360180 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5491 01:21:31.360233 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5492 01:21:31.360286 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5493 01:21:31.360339 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5494 01:21:31.360391
5495 01:21:31.360443
5496 01:21:31.360495 ==
5497 01:21:31.360547 Dram Type= 6, Freq= 0, CH_0, rank 1
5498 01:21:31.360600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5499 01:21:31.360654 ==
5500 01:21:31.360706
5501 01:21:31.360758
5502 01:21:31.360810 TX Vref Scan disable
5503 01:21:31.360863 == TX Byte 0 ==
5504 01:21:31.360915 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5505 01:21:31.360968 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5506 01:21:31.361021 == TX Byte 1 ==
5507 01:21:31.361073 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5508 01:21:31.361126 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5509 01:21:31.361178 ==
5510 01:21:31.361230 Dram Type= 6, Freq= 0, CH_0, rank 1
5511 01:21:31.361283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5512 01:21:31.361361 ==
5513 01:21:31.361431
5514 01:21:31.361483
5515 01:21:31.361536 TX Vref Scan disable
5516 01:21:31.361588 == TX Byte 0 ==
5517 01:21:31.361640 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5518 01:21:31.361693 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5519 01:21:31.361745 == TX Byte 1 ==
5520 01:21:31.361798 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5521 01:21:31.361850 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5522 01:21:31.361902
5523 01:21:31.361954 [DATLAT]
5524 01:21:31.362006 Freq=933, CH0 RK1
5525 01:21:31.362059
5526 01:21:31.362112 DATLAT Default: 0xb
5527 01:21:31.362163 0, 0xFFFF, sum = 0
5528 01:21:31.362217 1, 0xFFFF, sum = 0
5529 01:21:31.362271 2, 0xFFFF, sum = 0
5530 01:21:31.362341 3, 0xFFFF, sum = 0
5531 01:21:31.362399 4, 0xFFFF, sum = 0
5532 01:21:31.362453 5, 0xFFFF, sum = 0
5533 01:21:31.362506 6, 0xFFFF, sum = 0
5534 01:21:31.362559 7, 0xFFFF, sum = 0
5535 01:21:31.362613 8, 0xFFFF, sum = 0
5536 01:21:31.362666 9, 0xFFFF, sum = 0
5537 01:21:31.362720 10, 0x0, sum = 1
5538 01:21:31.362773 11, 0x0, sum = 2
5539 01:21:31.362826 12, 0x0, sum = 3
5540 01:21:31.362880 13, 0x0, sum = 4
5541 01:21:31.362934 best_step = 11
5542 01:21:31.362986
5543 01:21:31.363038 ==
5544 01:21:31.363091 Dram Type= 6, Freq= 0, CH_0, rank 1
5545 01:21:31.363144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5546 01:21:31.363197 ==
5547 01:21:31.363250 RX Vref Scan: 0
5548 01:21:31.363302
5549 01:21:31.363354 RX Vref 0 -> 0, step: 1
5550 01:21:31.363407
5551 01:21:31.363458 RX Delay -61 -> 252, step: 4
5552 01:21:31.363510 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5553 01:21:31.363563 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5554 01:21:31.363615 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5555 01:21:31.363668 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5556 01:21:31.363720 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5557 01:21:31.363773 iDelay=203, Bit 5, Center 88 (-5 ~ 182) 188
5558 01:21:31.363826 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5559 01:21:31.363879 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5560 01:21:31.363931 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5561 01:21:31.363983 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5562 01:21:31.364035 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5563 01:21:31.364087 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5564 01:21:31.364139 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5565 01:21:31.364192 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5566 01:21:31.364244 iDelay=203, Bit 14, Center 94 (3 ~ 186) 184
5567 01:21:31.364297 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5568 01:21:31.364349 ==
5569 01:21:31.364401 Dram Type= 6, Freq= 0, CH_0, rank 1
5570 01:21:31.364453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 01:21:31.364506 ==
5572 01:21:31.364572 DQS Delay:
5573 01:21:31.364627 DQS0 = 0, DQS1 = 0
5574 01:21:31.364680 DQM Delay:
5575 01:21:31.364733 DQM0 = 96, DQM1 = 85
5576 01:21:31.364785 DQ Delay:
5577 01:21:31.364838 DQ0 =92, DQ1 =98, DQ2 =90, DQ3 =94
5578 01:21:31.364890 DQ4 =96, DQ5 =88, DQ6 =106, DQ7 =104
5579 01:21:31.364943 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5580 01:21:31.364996 DQ12 =92, DQ13 =92, DQ14 =94, DQ15 =92
5581 01:21:31.365048
5582 01:21:31.365099
5583 01:21:31.365349 [DQSOSCAuto] RK1, (LSB)MR18= 0x22f2, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 411 ps
5584 01:21:31.365470 CH0 RK1: MR19=504, MR18=22F2
5585 01:21:31.365529 CH0_RK1: MR19=0x504, MR18=0x22F2, DQSOSC=411, MR23=63, INC=64, DEC=42
5586 01:21:31.365596 [RxdqsGatingPostProcess] freq 933
5587 01:21:31.365649 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5588 01:21:31.365702 best DQS0 dly(2T, 0.5T) = (0, 10)
5589 01:21:31.365754 best DQS1 dly(2T, 0.5T) = (0, 10)
5590 01:21:31.365806 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5591 01:21:31.365858 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5592 01:21:31.365910 best DQS0 dly(2T, 0.5T) = (0, 10)
5593 01:21:31.365962 best DQS1 dly(2T, 0.5T) = (0, 10)
5594 01:21:31.366013 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5595 01:21:31.366065 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5596 01:21:31.366117 Pre-setting of DQS Precalculation
5597 01:21:31.366170 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5598 01:21:31.366222 ==
5599 01:21:31.366274 Dram Type= 6, Freq= 0, CH_1, rank 0
5600 01:21:31.366326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5601 01:21:31.366378 ==
5602 01:21:31.366430 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5603 01:21:31.366482 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5604 01:21:31.366534 [CA 0] Center 36 (6~67) winsize 62
5605 01:21:31.366586 [CA 1] Center 36 (6~67) winsize 62
5606 01:21:31.366638 [CA 2] Center 34 (4~65) winsize 62
5607 01:21:31.366689 [CA 3] Center 33 (3~64) winsize 62
5608 01:21:31.366741 [CA 4] Center 34 (4~64) winsize 61
5609 01:21:31.366792 [CA 5] Center 33 (3~64) winsize 62
5610 01:21:31.366844
5611 01:21:31.366895 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5612 01:21:31.366947
5613 01:21:31.366999 [CATrainingPosCal] consider 1 rank data
5614 01:21:31.367050 u2DelayCellTimex100 = 270/100 ps
5615 01:21:31.367101 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5616 01:21:31.367153 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5617 01:21:31.367205 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5618 01:21:31.367256 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5619 01:21:31.367308 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5620 01:21:31.367359 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5621 01:21:31.367410
5622 01:21:31.367462 CA PerBit enable=1, Macro0, CA PI delay=33
5623 01:21:31.367513
5624 01:21:31.367564 [CBTSetCACLKResult] CA Dly = 33
5625 01:21:31.367616 CS Dly: 6 (0~37)
5626 01:21:31.367668 ==
5627 01:21:31.367720 Dram Type= 6, Freq= 0, CH_1, rank 1
5628 01:21:31.367772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 01:21:31.367824 ==
5630 01:21:31.367876 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5631 01:21:31.367927 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5632 01:21:31.367980 [CA 0] Center 36 (6~67) winsize 62
5633 01:21:31.368031 [CA 1] Center 36 (6~67) winsize 62
5634 01:21:31.368083 [CA 2] Center 34 (3~65) winsize 63
5635 01:21:31.368135 [CA 3] Center 33 (3~64) winsize 62
5636 01:21:31.368187 [CA 4] Center 34 (3~65) winsize 63
5637 01:21:31.368238 [CA 5] Center 33 (3~64) winsize 62
5638 01:21:31.368290
5639 01:21:31.368340 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5640 01:21:31.368392
5641 01:21:31.368443 [CATrainingPosCal] consider 2 rank data
5642 01:21:31.368496 u2DelayCellTimex100 = 270/100 ps
5643 01:21:31.368547 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5644 01:21:31.368599 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5645 01:21:31.368651 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5646 01:21:31.368703 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5647 01:21:31.368755 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5648 01:21:31.368806 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5649 01:21:31.368858
5650 01:21:31.368909 CA PerBit enable=1, Macro0, CA PI delay=33
5651 01:21:31.368961
5652 01:21:31.369012 [CBTSetCACLKResult] CA Dly = 33
5653 01:21:31.369064 CS Dly: 7 (0~39)
5654 01:21:31.369115
5655 01:21:31.369166 ----->DramcWriteLeveling(PI) begin...
5656 01:21:31.369218 ==
5657 01:21:31.369270 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 01:21:31.369322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 01:21:31.369433 ==
5660 01:21:31.369486 Write leveling (Byte 0): 25 => 25
5661 01:21:31.369538 Write leveling (Byte 1): 27 => 27
5662 01:21:31.369589 DramcWriteLeveling(PI) end<-----
5663 01:21:31.369641
5664 01:21:31.369692 ==
5665 01:21:31.369743 Dram Type= 6, Freq= 0, CH_1, rank 0
5666 01:21:31.369795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5667 01:21:31.369847 ==
5668 01:21:31.369922 [Gating] SW mode calibration
5669 01:21:31.369977 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5670 01:21:31.370030 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5671 01:21:31.370083 0 14 0 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
5672 01:21:31.370135 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5673 01:21:31.370187 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5674 01:21:31.370239 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5675 01:21:31.370292 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5676 01:21:31.370344 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5677 01:21:31.370396 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5678 01:21:31.370447 0 14 28 | B1->B0 | 2f2f 2c2c | 1 0 | (1 0) (0 0)
5679 01:21:31.370499 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
5680 01:21:31.370550 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5681 01:21:31.370602 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5682 01:21:31.370653 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5683 01:21:31.370705 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5684 01:21:31.370757 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5685 01:21:31.370808 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5686 01:21:31.370860 0 15 28 | B1->B0 | 3231 3838 | 1 0 | (0 0) (0 0)
5687 01:21:31.370911 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5688 01:21:31.370963 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5689 01:21:31.371014 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5690 01:21:31.371066 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5691 01:21:31.371118 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5692 01:21:31.371169 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5693 01:21:31.371411 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5694 01:21:31.371499 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5695 01:21:31.371552 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5696 01:21:31.371604 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 01:21:31.371656 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 01:21:31.371708 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 01:21:31.371760 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 01:21:31.371812 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5701 01:21:31.371863 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5702 01:21:31.371915 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5703 01:21:31.371966 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5704 01:21:31.372018 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5705 01:21:31.372069 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5706 01:21:31.372121 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5707 01:21:31.372173 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5708 01:21:31.372240 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5709 01:21:31.372306 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5710 01:21:31.372357 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5711 01:21:31.372408 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5712 01:21:31.372460 Total UI for P1: 0, mck2ui 16
5713 01:21:31.372512 best dqsien dly found for B0: ( 1, 2, 24)
5714 01:21:31.372563 Total UI for P1: 0, mck2ui 16
5715 01:21:31.372644 best dqsien dly found for B1: ( 1, 2, 28)
5716 01:21:31.372696 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5717 01:21:31.372747 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5718 01:21:31.372821
5719 01:21:31.372875 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5720 01:21:31.372927 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5721 01:21:31.372979 [Gating] SW calibration Done
5722 01:21:31.373031 ==
5723 01:21:31.373083 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 01:21:31.373135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 01:21:31.373187 ==
5726 01:21:31.373239 RX Vref Scan: 0
5727 01:21:31.373291
5728 01:21:31.373374 RX Vref 0 -> 0, step: 1
5729 01:21:31.373454
5730 01:21:31.373505 RX Delay -80 -> 252, step: 8
5731 01:21:31.373558 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5732 01:21:31.373610 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5733 01:21:31.373662 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5734 01:21:31.373713 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5735 01:21:31.373765 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5736 01:21:31.373816 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5737 01:21:31.373868 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5738 01:21:31.373919 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5739 01:21:31.373970 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5740 01:21:31.374022 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5741 01:21:31.374073 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5742 01:21:31.374124 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5743 01:21:31.374176 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5744 01:21:31.374227 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5745 01:21:31.374287 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5746 01:21:31.374343 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5747 01:21:31.374410 ==
5748 01:21:31.374475 Dram Type= 6, Freq= 0, CH_1, rank 0
5749 01:21:31.374526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 01:21:31.374578 ==
5751 01:21:31.374629 DQS Delay:
5752 01:21:31.374681 DQS0 = 0, DQS1 = 0
5753 01:21:31.374733 DQM Delay:
5754 01:21:31.374785 DQM0 = 103, DQM1 = 90
5755 01:21:31.374836 DQ Delay:
5756 01:21:31.374887 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =103
5757 01:21:31.374939 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5758 01:21:31.374991 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5759 01:21:31.375042 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5760 01:21:31.375094
5761 01:21:31.375145
5762 01:21:31.375195 ==
5763 01:21:31.375246 Dram Type= 6, Freq= 0, CH_1, rank 0
5764 01:21:31.375298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 01:21:31.375350 ==
5766 01:21:31.375402
5767 01:21:31.375453
5768 01:21:31.375504 TX Vref Scan disable
5769 01:21:31.375556 == TX Byte 0 ==
5770 01:21:31.375607 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5771 01:21:31.375659 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5772 01:21:31.375710 == TX Byte 1 ==
5773 01:21:31.375761 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5774 01:21:31.375813 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5775 01:21:31.375864 ==
5776 01:21:31.375916 Dram Type= 6, Freq= 0, CH_1, rank 0
5777 01:21:31.375968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5778 01:21:31.376019 ==
5779 01:21:31.376071
5780 01:21:31.376122
5781 01:21:31.376173 TX Vref Scan disable
5782 01:21:31.376224 == TX Byte 0 ==
5783 01:21:31.376276 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5784 01:21:31.376328 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5785 01:21:31.376380 == TX Byte 1 ==
5786 01:21:31.376431 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5787 01:21:31.376483 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5788 01:21:31.376535
5789 01:21:31.376627 [DATLAT]
5790 01:21:31.376678 Freq=933, CH1 RK0
5791 01:21:31.376729
5792 01:21:31.376781 DATLAT Default: 0xd
5793 01:21:31.376832 0, 0xFFFF, sum = 0
5794 01:21:31.376886 1, 0xFFFF, sum = 0
5795 01:21:31.376938 2, 0xFFFF, sum = 0
5796 01:21:31.376990 3, 0xFFFF, sum = 0
5797 01:21:31.377042 4, 0xFFFF, sum = 0
5798 01:21:31.377095 5, 0xFFFF, sum = 0
5799 01:21:31.377147 6, 0xFFFF, sum = 0
5800 01:21:31.377199 7, 0xFFFF, sum = 0
5801 01:21:31.377251 8, 0xFFFF, sum = 0
5802 01:21:31.377303 9, 0xFFFF, sum = 0
5803 01:21:31.377439 10, 0x0, sum = 1
5804 01:21:31.377503 11, 0x0, sum = 2
5805 01:21:31.377556 12, 0x0, sum = 3
5806 01:21:31.377608 13, 0x0, sum = 4
5807 01:21:31.377661 best_step = 11
5808 01:21:31.377712
5809 01:21:31.377763 ==
5810 01:21:31.377814 Dram Type= 6, Freq= 0, CH_1, rank 0
5811 01:21:31.377866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5812 01:21:31.377918 ==
5813 01:21:31.377970 RX Vref Scan: 1
5814 01:21:31.378021
5815 01:21:31.378072 RX Vref 0 -> 0, step: 1
5816 01:21:31.378124
5817 01:21:31.378175 RX Delay -69 -> 252, step: 4
5818 01:21:31.378227
5819 01:21:31.378278 Set Vref, RX VrefLevel [Byte0]: 51
5820 01:21:31.378329 [Byte1]: 59
5821 01:21:31.378392
5822 01:21:31.378445 Final RX Vref Byte 0 = 51 to rank0
5823 01:21:31.378497 Final RX Vref Byte 1 = 59 to rank0
5824 01:21:31.378584 Final RX Vref Byte 0 = 51 to rank1
5825 01:21:31.378637 Final RX Vref Byte 1 = 59 to rank1==
5826 01:21:31.378690 Dram Type= 6, Freq= 0, CH_1, rank 0
5827 01:21:31.378741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 01:21:31.378793 ==
5829 01:21:31.378844 DQS Delay:
5830 01:21:31.378896 DQS0 = 0, DQS1 = 0
5831 01:21:31.379135 DQM Delay:
5832 01:21:31.379194 DQM0 = 100, DQM1 = 93
5833 01:21:31.379248 DQ Delay:
5834 01:21:31.379300 DQ0 =104, DQ1 =96, DQ2 =92, DQ3 =96
5835 01:21:31.379352 DQ4 =98, DQ5 =110, DQ6 =112, DQ7 =96
5836 01:21:31.379403 DQ8 =82, DQ9 =84, DQ10 =92, DQ11 =84
5837 01:21:31.379455 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =102
5838 01:21:31.379507
5839 01:21:31.379558
5840 01:21:31.379609 [DQSOSCAuto] RK0, (LSB)MR18= 0x1606, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 414 ps
5841 01:21:31.379662 CH1 RK0: MR19=505, MR18=1606
5842 01:21:31.379713 CH1_RK0: MR19=0x505, MR18=0x1606, DQSOSC=414, MR23=63, INC=63, DEC=42
5843 01:21:31.379765
5844 01:21:31.379817 ----->DramcWriteLeveling(PI) begin...
5845 01:21:31.379869 ==
5846 01:21:31.379920 Dram Type= 6, Freq= 0, CH_1, rank 1
5847 01:21:31.379972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 01:21:31.380024 ==
5849 01:21:31.380076 Write leveling (Byte 0): 25 => 25
5850 01:21:31.380127 Write leveling (Byte 1): 27 => 27
5851 01:21:31.380179 DramcWriteLeveling(PI) end<-----
5852 01:21:31.380230
5853 01:21:31.380282 ==
5854 01:21:31.380334 Dram Type= 6, Freq= 0, CH_1, rank 1
5855 01:21:31.380385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5856 01:21:31.380437 ==
5857 01:21:31.380488 [Gating] SW mode calibration
5858 01:21:31.380540 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5859 01:21:31.380592 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5860 01:21:31.380644 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5861 01:21:31.380695 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5862 01:21:31.380747 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5863 01:21:31.380799 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5864 01:21:31.380851 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5865 01:21:31.380924 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5866 01:21:31.380978 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5867 01:21:31.381031 0 14 28 | B1->B0 | 2e2e 2f2f | 0 0 | (0 0) (1 0)
5868 01:21:31.381083 0 15 0 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
5869 01:21:31.381134 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5870 01:21:31.381186 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5871 01:21:31.381238 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5872 01:21:31.381290 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5873 01:21:31.381370 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5874 01:21:31.381437 0 15 24 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5875 01:21:31.381488 0 15 28 | B1->B0 | 3a3a 3131 | 0 1 | (0 0) (0 0)
5876 01:21:31.381540 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5877 01:21:31.381592 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5878 01:21:31.381644 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5879 01:21:31.381696 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5880 01:21:31.381748 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5881 01:21:31.381800 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5882 01:21:31.381851 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5883 01:21:31.381904 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5884 01:21:31.381955 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 01:21:31.382007 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 01:21:31.382059 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 01:21:31.382110 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 01:21:31.382162 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5889 01:21:31.382213 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5890 01:21:31.382265 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5891 01:21:31.382317 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5892 01:21:31.382368 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5893 01:21:31.382419 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5894 01:21:31.382471 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5895 01:21:31.382523 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5896 01:21:31.382615 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5897 01:21:31.382667 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5898 01:21:31.382718 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5899 01:21:31.382770 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5900 01:21:31.382822 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5901 01:21:31.382873 Total UI for P1: 0, mck2ui 16
5902 01:21:31.382925 best dqsien dly found for B0: ( 1, 2, 28)
5903 01:21:31.382977 Total UI for P1: 0, mck2ui 16
5904 01:21:31.383030 best dqsien dly found for B1: ( 1, 2, 26)
5905 01:21:31.383082 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5906 01:21:31.383134 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5907 01:21:31.383186
5908 01:21:31.383237 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5909 01:21:31.383290 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5910 01:21:31.383341 [Gating] SW calibration Done
5911 01:21:31.383393 ==
5912 01:21:31.383444 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 01:21:31.383496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 01:21:31.383547 ==
5915 01:21:31.383599 RX Vref Scan: 0
5916 01:21:31.383650
5917 01:21:31.383701 RX Vref 0 -> 0, step: 1
5918 01:21:31.383752
5919 01:21:31.383803 RX Delay -80 -> 252, step: 8
5920 01:21:31.383855 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5921 01:21:31.383907 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5922 01:21:31.383959 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5923 01:21:31.384011 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5924 01:21:31.384063 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5925 01:21:31.384115 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5926 01:21:31.384166 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5927 01:21:31.384218 iDelay=208, Bit 7, Center 99 (0 ~ 199) 200
5928 01:21:31.384270 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5929 01:21:31.384321 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5930 01:21:31.384373 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5931 01:21:31.384424 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5932 01:21:31.384680 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5933 01:21:31.384747 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5934 01:21:31.384803 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5935 01:21:31.384856 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5936 01:21:31.384909 ==
5937 01:21:31.384961 Dram Type= 6, Freq= 0, CH_1, rank 1
5938 01:21:31.385014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5939 01:21:31.385088 ==
5940 01:21:31.385144 DQS Delay:
5941 01:21:31.385197 DQS0 = 0, DQS1 = 0
5942 01:21:31.385250 DQM Delay:
5943 01:21:31.385302 DQM0 = 100, DQM1 = 93
5944 01:21:31.385384 DQ Delay:
5945 01:21:31.385449 DQ0 =103, DQ1 =99, DQ2 =87, DQ3 =99
5946 01:21:31.385501 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5947 01:21:31.385554 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =87
5948 01:21:31.385605 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5949 01:21:31.385656
5950 01:21:31.385707
5951 01:21:31.385759 ==
5952 01:21:31.385811 Dram Type= 6, Freq= 0, CH_1, rank 1
5953 01:21:31.385863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5954 01:21:31.385915 ==
5955 01:21:31.385968
5956 01:21:31.386019
5957 01:21:31.386071 TX Vref Scan disable
5958 01:21:31.386123 == TX Byte 0 ==
5959 01:21:31.386174 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5960 01:21:31.386227 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5961 01:21:31.386279 == TX Byte 1 ==
5962 01:21:31.386331 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5963 01:21:31.386383 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5964 01:21:31.386434 ==
5965 01:21:31.386486 Dram Type= 6, Freq= 0, CH_1, rank 1
5966 01:21:31.386538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5967 01:21:31.386609 ==
5968 01:21:31.386661
5969 01:21:31.386713
5970 01:21:31.386777 TX Vref Scan disable
5971 01:21:31.386829 == TX Byte 0 ==
5972 01:21:31.386881 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5973 01:21:31.386933 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5974 01:21:31.386985 == TX Byte 1 ==
5975 01:21:31.387036 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5976 01:21:31.387088 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5977 01:21:31.387139
5978 01:21:31.387191 [DATLAT]
5979 01:21:31.387242 Freq=933, CH1 RK1
5980 01:21:31.387293
5981 01:21:31.387344 DATLAT Default: 0xb
5982 01:21:31.387396 0, 0xFFFF, sum = 0
5983 01:21:31.387448 1, 0xFFFF, sum = 0
5984 01:21:31.387501 2, 0xFFFF, sum = 0
5985 01:21:31.387554 3, 0xFFFF, sum = 0
5986 01:21:31.387606 4, 0xFFFF, sum = 0
5987 01:21:31.921536 5, 0xFFFF, sum = 0
5988 01:21:31.922397 6, 0xFFFF, sum = 0
5989 01:21:31.922812 7, 0xFFFF, sum = 0
5990 01:21:31.923170 8, 0xFFFF, sum = 0
5991 01:21:31.923509 9, 0xFFFF, sum = 0
5992 01:21:31.923839 10, 0x0, sum = 1
5993 01:21:31.924164 11, 0x0, sum = 2
5994 01:21:31.924566 12, 0x0, sum = 3
5995 01:21:31.925231 13, 0x0, sum = 4
5996 01:21:31.925811 best_step = 11
5997 01:21:31.926159
5998 01:21:31.926479 ==
5999 01:21:31.926799 Dram Type= 6, Freq= 0, CH_1, rank 1
6000 01:21:31.927184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6001 01:21:31.927743 ==
6002 01:21:31.928170 RX Vref Scan: 0
6003 01:21:31.928846
6004 01:21:31.929442 RX Vref 0 -> 0, step: 1
6005 01:21:31.929792
6006 01:21:31.930112 RX Delay -61 -> 252, step: 4
6007 01:21:31.930619 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
6008 01:21:31.931214 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
6009 01:21:31.931601 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
6010 01:21:31.931951 iDelay=207, Bit 3, Center 98 (11 ~ 186) 176
6011 01:21:31.932263 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
6012 01:21:31.932571 iDelay=207, Bit 5, Center 112 (23 ~ 202) 180
6013 01:21:31.932877 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
6014 01:21:31.933178 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6015 01:21:31.933533 iDelay=207, Bit 8, Center 84 (-5 ~ 174) 180
6016 01:21:31.933843 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
6017 01:21:31.934143 iDelay=207, Bit 10, Center 92 (-1 ~ 186) 188
6018 01:21:31.934444 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6019 01:21:31.934742 iDelay=207, Bit 12, Center 104 (15 ~ 194) 180
6020 01:21:31.935043 iDelay=207, Bit 13, Center 104 (15 ~ 194) 180
6021 01:21:31.935343 iDelay=207, Bit 14, Center 98 (7 ~ 190) 184
6022 01:21:31.935645 iDelay=207, Bit 15, Center 104 (15 ~ 194) 180
6023 01:21:31.935944 ==
6024 01:21:31.936245 Dram Type= 6, Freq= 0, CH_1, rank 1
6025 01:21:31.936754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6026 01:21:31.937414 ==
6027 01:21:31.937994 DQS Delay:
6028 01:21:31.938336 DQS0 = 0, DQS1 = 0
6029 01:21:31.938683 DQM Delay:
6030 01:21:31.939039 DQM0 = 101, DQM1 = 94
6031 01:21:31.939353 DQ Delay:
6032 01:21:31.939683 DQ0 =104, DQ1 =94, DQ2 =90, DQ3 =98
6033 01:21:31.939995 DQ4 =98, DQ5 =112, DQ6 =114, DQ7 =98
6034 01:21:31.940296 DQ8 =84, DQ9 =84, DQ10 =92, DQ11 =84
6035 01:21:31.940598 DQ12 =104, DQ13 =104, DQ14 =98, DQ15 =104
6036 01:21:31.940901
6037 01:21:31.941201
6038 01:21:31.941570 [DQSOSCAuto] RK1, (LSB)MR18= 0x5fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 420 ps
6039 01:21:31.941859 CH1 RK1: MR19=504, MR18=5FE
6040 01:21:31.942136 CH1_RK1: MR19=0x504, MR18=0x5FE, DQSOSC=420, MR23=63, INC=61, DEC=40
6041 01:21:31.942417 [RxdqsGatingPostProcess] freq 933
6042 01:21:31.942696 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6043 01:21:31.943060 best DQS0 dly(2T, 0.5T) = (0, 10)
6044 01:21:31.943349 best DQS1 dly(2T, 0.5T) = (0, 10)
6045 01:21:31.943648 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6046 01:21:31.944081 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6047 01:21:31.944618 best DQS0 dly(2T, 0.5T) = (0, 10)
6048 01:21:31.944970 best DQS1 dly(2T, 0.5T) = (0, 10)
6049 01:21:31.945255 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6050 01:21:31.945594 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6051 01:21:31.945804 Pre-setting of DQS Precalculation
6052 01:21:31.946003 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6053 01:21:31.946203 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6054 01:21:31.946404 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6055 01:21:31.946602
6056 01:21:31.946795
6057 01:21:31.946988 [Calibration Summary] 1866 Mbps
6058 01:21:31.947186 CH 0, Rank 0
6059 01:21:31.947380 SW Impedance : PASS
6060 01:21:31.947576 DUTY Scan : NO K
6061 01:21:31.947772 ZQ Calibration : PASS
6062 01:21:31.947967 Jitter Meter : NO K
6063 01:21:31.948162 CBT Training : PASS
6064 01:21:31.948355 Write leveling : PASS
6065 01:21:31.948548 RX DQS gating : PASS
6066 01:21:31.948743 RX DQ/DQS(RDDQC) : PASS
6067 01:21:31.948936 TX DQ/DQS : PASS
6068 01:21:31.949131 RX DATLAT : PASS
6069 01:21:31.949323 RX DQ/DQS(Engine): PASS
6070 01:21:31.949753 TX OE : NO K
6071 01:21:31.950116 All Pass.
6072 01:21:31.950334
6073 01:21:31.950539 CH 0, Rank 1
6074 01:21:31.950687 SW Impedance : PASS
6075 01:21:31.950852 DUTY Scan : NO K
6076 01:21:31.951187 ZQ Calibration : PASS
6077 01:21:31.951471 Jitter Meter : NO K
6078 01:21:31.951976 CBT Training : PASS
6079 01:21:31.952232 Write leveling : PASS
6080 01:21:31.952468 RX DQS gating : PASS
6081 01:21:31.952700 RX DQ/DQS(RDDQC) : PASS
6082 01:21:31.952930 TX DQ/DQS : PASS
6083 01:21:31.953159 RX DATLAT : PASS
6084 01:21:31.953410 RX DQ/DQS(Engine): PASS
6085 01:21:31.953643 TX OE : NO K
6086 01:21:31.953872 All Pass.
6087 01:21:31.954099
6088 01:21:31.954325 CH 1, Rank 0
6089 01:21:31.954552 SW Impedance : PASS
6090 01:21:31.954780 DUTY Scan : NO K
6091 01:21:31.955005 ZQ Calibration : PASS
6092 01:21:31.955230 Jitter Meter : NO K
6093 01:21:31.955457 CBT Training : PASS
6094 01:21:31.955654 Write leveling : PASS
6095 01:21:31.955848 RX DQS gating : PASS
6096 01:21:31.956058 RX DQ/DQS(RDDQC) : PASS
6097 01:21:31.956191 TX DQ/DQS : PASS
6098 01:21:31.956312 RX DATLAT : PASS
6099 01:21:31.956433 RX DQ/DQS(Engine): PASS
6100 01:21:31.956560 TX OE : NO K
6101 01:21:31.956712 All Pass.
6102 01:21:31.956836
6103 01:21:31.956954 CH 1, Rank 1
6104 01:21:31.957074 SW Impedance : PASS
6105 01:21:31.957194 DUTY Scan : NO K
6106 01:21:31.957382 ZQ Calibration : PASS
6107 01:21:31.957582 Jitter Meter : NO K
6108 01:21:31.957772 CBT Training : PASS
6109 01:21:31.957967 Write leveling : PASS
6110 01:21:31.958178 RX DQS gating : PASS
6111 01:21:31.958386 RX DQ/DQS(RDDQC) : PASS
6112 01:21:31.958666 TX DQ/DQS : PASS
6113 01:21:31.958912 RX DATLAT : PASS
6114 01:21:31.959137 RX DQ/DQS(Engine): PASS
6115 01:21:31.959329 TX OE : NO K
6116 01:21:31.959516 All Pass.
6117 01:21:31.959700
6118 01:21:31.959883 DramC Write-DBI off
6119 01:21:31.960066 PER_BANK_REFRESH: Hybrid Mode
6120 01:21:31.960249 TX_TRACKING: ON
6121 01:21:31.960437 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6122 01:21:31.960622 [FAST_K] Save calibration result to emmc
6123 01:21:31.960777 dramc_set_vcore_voltage set vcore to 650000
6124 01:21:31.960930 Read voltage for 400, 6
6125 01:21:31.961083 Vio18 = 0
6126 01:21:31.961246 Vcore = 650000
6127 01:21:31.961393 Vdram = 0
6128 01:21:31.961497 Vddq = 0
6129 01:21:31.961597 Vmddr = 0
6130 01:21:31.961697 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6131 01:21:31.961799 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6132 01:21:31.961899 MEM_TYPE=3, freq_sel=20
6133 01:21:31.961999 sv_algorithm_assistance_LP4_800
6134 01:21:31.962117 ============ PULL DRAM RESETB DOWN ============
6135 01:21:31.962220 ========== PULL DRAM RESETB DOWN end =========
6136 01:21:31.962320 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6137 01:21:31.962421 ===================================
6138 01:21:31.962520 LPDDR4 DRAM CONFIGURATION
6139 01:21:31.962621 ===================================
6140 01:21:31.962721 EX_ROW_EN[0] = 0x0
6141 01:21:31.962821 EX_ROW_EN[1] = 0x0
6142 01:21:31.962920 LP4Y_EN = 0x0
6143 01:21:31.963019 WORK_FSP = 0x0
6144 01:21:31.963119 WL = 0x2
6145 01:21:31.963218 RL = 0x2
6146 01:21:31.963316 BL = 0x2
6147 01:21:31.963414 RPST = 0x0
6148 01:21:31.963513 RD_PRE = 0x0
6149 01:21:31.963611 WR_PRE = 0x1
6150 01:21:31.963709 WR_PST = 0x0
6151 01:21:31.963808 DBI_WR = 0x0
6152 01:21:31.963906 DBI_RD = 0x0
6153 01:21:31.964004 OTF = 0x1
6154 01:21:31.964120 ===================================
6155 01:21:31.964224 ===================================
6156 01:21:31.964324 ANA top config
6157 01:21:31.964423 ===================================
6158 01:21:31.964522 DLL_ASYNC_EN = 0
6159 01:21:31.964621 ALL_SLAVE_EN = 1
6160 01:21:31.964720 NEW_RANK_MODE = 1
6161 01:21:31.964820 DLL_IDLE_MODE = 1
6162 01:21:31.964919 LP45_APHY_COMB_EN = 1
6163 01:21:31.965018 TX_ODT_DIS = 1
6164 01:21:31.965116 NEW_8X_MODE = 1
6165 01:21:31.965216 ===================================
6166 01:21:31.965315 ===================================
6167 01:21:31.965434 data_rate = 800
6168 01:21:31.965539 CKR = 1
6169 01:21:31.965624 DQ_P2S_RATIO = 4
6170 01:21:31.965709 ===================================
6171 01:21:31.965794 CA_P2S_RATIO = 4
6172 01:21:31.965878 DQ_CA_OPEN = 0
6173 01:21:31.965963 DQ_SEMI_OPEN = 1
6174 01:21:31.966048 CA_SEMI_OPEN = 1
6175 01:21:31.966133 CA_FULL_RATE = 0
6176 01:21:31.966261 DQ_CKDIV4_EN = 0
6177 01:21:31.966388 CA_CKDIV4_EN = 1
6178 01:21:31.966477 CA_PREDIV_EN = 0
6179 01:21:31.966563 PH8_DLY = 0
6180 01:21:31.966648 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6181 01:21:31.966733 DQ_AAMCK_DIV = 0
6182 01:21:31.966818 CA_AAMCK_DIV = 0
6183 01:21:31.966904 CA_ADMCK_DIV = 4
6184 01:21:31.966988 DQ_TRACK_CA_EN = 0
6185 01:21:31.967073 CA_PICK = 800
6186 01:21:31.967159 CA_MCKIO = 400
6187 01:21:31.967244 MCKIO_SEMI = 400
6188 01:21:31.967329 PLL_FREQ = 3016
6189 01:21:31.967414 DQ_UI_PI_RATIO = 32
6190 01:21:31.967500 CA_UI_PI_RATIO = 32
6191 01:21:31.967583 ===================================
6192 01:21:31.967668 ===================================
6193 01:21:31.967753 memory_type:LPDDR4
6194 01:21:31.967839 GP_NUM : 10
6195 01:21:31.967924 SRAM_EN : 1
6196 01:21:31.968009 MD32_EN : 0
6197 01:21:31.968099 ===================================
6198 01:21:31.968185 [ANA_INIT] >>>>>>>>>>>>>>
6199 01:21:31.968270 <<<<<< [CONFIGURE PHASE]: ANA_TX
6200 01:21:31.968356 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6201 01:21:31.968441 ===================================
6202 01:21:31.968526 data_rate = 800,PCW = 0X7400
6203 01:21:31.968611 ===================================
6204 01:21:31.968696 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6205 01:21:31.968782 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6206 01:21:31.968869 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6207 01:21:31.968957 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6208 01:21:31.969043 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6209 01:21:31.969134 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6210 01:21:31.969268 [ANA_INIT] flow start
6211 01:21:31.969396 [ANA_INIT] PLL >>>>>>>>
6212 01:21:31.969486 [ANA_INIT] PLL <<<<<<<<
6213 01:21:31.969573 [ANA_INIT] MIDPI >>>>>>>>
6214 01:21:31.969658 [ANA_INIT] MIDPI <<<<<<<<
6215 01:21:31.969751 [ANA_INIT] DLL >>>>>>>>
6216 01:21:31.969841 [ANA_INIT] flow end
6217 01:21:31.970149 ============ LP4 DIFF to SE enter ============
6218 01:21:31.970250 ============ LP4 DIFF to SE exit ============
6219 01:21:31.970340 [ANA_INIT] <<<<<<<<<<<<<
6220 01:21:31.970427 [Flow] Enable top DCM control >>>>>
6221 01:21:31.970522 [Flow] Enable top DCM control <<<<<
6222 01:21:31.970598 Enable DLL master slave shuffle
6223 01:21:31.970673 ==============================================================
6224 01:21:31.970749 Gating Mode config
6225 01:21:31.970824 ==============================================================
6226 01:21:31.970900 Config description:
6227 01:21:31.970974 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6228 01:21:31.971051 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6229 01:21:31.971126 SELPH_MODE 0: By rank 1: By Phase
6230 01:21:31.971202 ==============================================================
6231 01:21:31.971277 GAT_TRACK_EN = 0
6232 01:21:31.971353 RX_GATING_MODE = 2
6233 01:21:31.971427 RX_GATING_TRACK_MODE = 2
6234 01:21:31.971502 SELPH_MODE = 1
6235 01:21:31.971576 PICG_EARLY_EN = 1
6236 01:21:31.971667 VALID_LAT_VALUE = 1
6237 01:21:31.971887 ==============================================================
6238 01:21:31.972032 Enter into Gating configuration >>>>
6239 01:21:31.972154 Exit from Gating configuration <<<<
6240 01:21:31.972271 Enter into DVFS_PRE_config >>>>>
6241 01:21:31.972391 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6242 01:21:31.972510 Exit from DVFS_PRE_config <<<<<
6243 01:21:31.972626 Enter into PICG configuration >>>>
6244 01:21:31.972741 Exit from PICG configuration <<<<
6245 01:21:31.972856 [RX_INPUT] configuration >>>>>
6246 01:21:31.972972 [RX_INPUT] configuration <<<<<
6247 01:21:31.973088 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6248 01:21:31.973205 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6249 01:21:31.973322 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6250 01:21:31.973413 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6251 01:21:31.973490 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6252 01:21:31.973565 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6253 01:21:31.973640 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6254 01:21:31.973715 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6255 01:21:31.973797 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6256 01:21:31.973874 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6257 01:21:31.973949 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6258 01:21:31.974024 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6259 01:21:31.974099 ===================================
6260 01:21:31.974174 LPDDR4 DRAM CONFIGURATION
6261 01:21:31.974249 ===================================
6262 01:21:31.974325 EX_ROW_EN[0] = 0x0
6263 01:21:31.974400 EX_ROW_EN[1] = 0x0
6264 01:21:31.974474 LP4Y_EN = 0x0
6265 01:21:31.974549 WORK_FSP = 0x0
6266 01:21:31.974623 WL = 0x2
6267 01:21:31.974697 RL = 0x2
6268 01:21:31.974770 BL = 0x2
6269 01:21:31.974844 RPST = 0x0
6270 01:21:31.974917 RD_PRE = 0x0
6271 01:21:31.974992 WR_PRE = 0x1
6272 01:21:31.975065 WR_PST = 0x0
6273 01:21:31.975139 DBI_WR = 0x0
6274 01:21:31.975212 DBI_RD = 0x0
6275 01:21:31.975286 OTF = 0x1
6276 01:21:31.975361 ===================================
6277 01:21:31.975436 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6278 01:21:31.975510 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6279 01:21:31.975590 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6280 01:21:31.975657 ===================================
6281 01:21:31.975723 LPDDR4 DRAM CONFIGURATION
6282 01:21:31.975789 ===================================
6283 01:21:31.975856 EX_ROW_EN[0] = 0x10
6284 01:21:31.975921 EX_ROW_EN[1] = 0x0
6285 01:21:31.975987 LP4Y_EN = 0x0
6286 01:21:31.976052 WORK_FSP = 0x0
6287 01:21:31.976118 WL = 0x2
6288 01:21:31.976184 RL = 0x2
6289 01:21:31.976249 BL = 0x2
6290 01:21:31.976315 RPST = 0x0
6291 01:21:31.976380 RD_PRE = 0x0
6292 01:21:31.976446 WR_PRE = 0x1
6293 01:21:31.976512 WR_PST = 0x0
6294 01:21:31.976577 DBI_WR = 0x0
6295 01:21:31.976642 DBI_RD = 0x0
6296 01:21:31.976707 OTF = 0x1
6297 01:21:31.976774 ===================================
6298 01:21:31.976840 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6299 01:21:31.976907 nWR fixed to 30
6300 01:21:31.976974 [ModeRegInit_LP4] CH0 RK0
6301 01:21:31.977039 [ModeRegInit_LP4] CH0 RK1
6302 01:21:31.977105 [ModeRegInit_LP4] CH1 RK0
6303 01:21:31.977170 [ModeRegInit_LP4] CH1 RK1
6304 01:21:31.977235 match AC timing 19
6305 01:21:31.977301 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6306 01:21:31.977398 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6307 01:21:31.977467 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6308 01:21:31.977535 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6309 01:21:31.977602 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6310 01:21:31.977668 ==
6311 01:21:31.977734 Dram Type= 6, Freq= 0, CH_0, rank 0
6312 01:21:31.977800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6313 01:21:31.977867 ==
6314 01:21:31.977934 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6315 01:21:31.978001 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6316 01:21:31.978068 [CA 0] Center 36 (8~64) winsize 57
6317 01:21:31.978134 [CA 1] Center 36 (8~64) winsize 57
6318 01:21:31.978200 [CA 2] Center 36 (8~64) winsize 57
6319 01:21:31.978265 [CA 3] Center 36 (8~64) winsize 57
6320 01:21:31.978344 [CA 4] Center 36 (8~64) winsize 57
6321 01:21:31.978412 [CA 5] Center 36 (8~64) winsize 57
6322 01:21:31.978478
6323 01:21:31.978544 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6324 01:21:31.978610
6325 01:21:31.978884 [CATrainingPosCal] consider 1 rank data
6326 01:21:31.978961 u2DelayCellTimex100 = 270/100 ps
6327 01:21:31.979029 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 01:21:31.979097 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 01:21:31.979164 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 01:21:31.979230 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 01:21:31.979297 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 01:21:31.979363 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 01:21:31.979429
6334 01:21:31.979496 CA PerBit enable=1, Macro0, CA PI delay=36
6335 01:21:31.979562
6336 01:21:31.979628 [CBTSetCACLKResult] CA Dly = 36
6337 01:21:31.979695 CS Dly: 1 (0~32)
6338 01:21:31.979773 ==
6339 01:21:31.979966 Dram Type= 6, Freq= 0, CH_0, rank 1
6340 01:21:31.980088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 01:21:31.980164 ==
6342 01:21:31.980232 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6343 01:21:31.980301 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6344 01:21:31.980369 [CA 0] Center 36 (8~64) winsize 57
6345 01:21:31.980436 [CA 1] Center 36 (8~64) winsize 57
6346 01:21:31.980515 [CA 2] Center 36 (8~64) winsize 57
6347 01:21:31.980575 [CA 3] Center 36 (8~64) winsize 57
6348 01:21:31.980634 [CA 4] Center 36 (8~64) winsize 57
6349 01:21:31.980694 [CA 5] Center 36 (8~64) winsize 57
6350 01:21:31.980753
6351 01:21:31.980812 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6352 01:21:31.980872
6353 01:21:31.980930 [CATrainingPosCal] consider 2 rank data
6354 01:21:31.980990 u2DelayCellTimex100 = 270/100 ps
6355 01:21:31.981049 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6356 01:21:31.981109 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6357 01:21:31.981169 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6358 01:21:31.981229 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6359 01:21:31.981288 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6360 01:21:31.981354 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6361 01:21:31.981416
6362 01:21:31.981474 CA PerBit enable=1, Macro0, CA PI delay=36
6363 01:21:31.981533
6364 01:21:31.981609 [CBTSetCACLKResult] CA Dly = 36
6365 01:21:31.981671 CS Dly: 1 (0~32)
6366 01:21:31.981754
6367 01:21:31.981816 ----->DramcWriteLeveling(PI) begin...
6368 01:21:31.981931 ==
6369 01:21:31.982083 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 01:21:31.982185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 01:21:31.982250 ==
6372 01:21:31.982327 Write leveling (Byte 0): 40 => 8
6373 01:21:31.982392 Write leveling (Byte 1): 32 => 0
6374 01:21:31.982452 DramcWriteLeveling(PI) end<-----
6375 01:21:31.982511
6376 01:21:31.982570 ==
6377 01:21:31.982629 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 01:21:31.982688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 01:21:31.982749 ==
6380 01:21:31.982808 [Gating] SW mode calibration
6381 01:21:31.982867 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6382 01:21:31.982928 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6383 01:21:31.982987 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6384 01:21:31.983047 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6385 01:21:31.983106 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6386 01:21:31.983165 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6387 01:21:31.983225 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6388 01:21:31.983284 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6389 01:21:31.983343 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6390 01:21:31.983401 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6391 01:21:31.983460 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6392 01:21:31.983519 Total UI for P1: 0, mck2ui 16
6393 01:21:31.983579 best dqsien dly found for B0: ( 0, 14, 24)
6394 01:21:31.983638 Total UI for P1: 0, mck2ui 16
6395 01:21:31.983697 best dqsien dly found for B1: ( 0, 14, 24)
6396 01:21:31.983756 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6397 01:21:31.983816 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6398 01:21:31.983874
6399 01:21:31.983933 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6400 01:21:31.983993 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6401 01:21:31.984052 [Gating] SW calibration Done
6402 01:21:31.984111 ==
6403 01:21:31.984170 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 01:21:31.984230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 01:21:31.984289 ==
6406 01:21:31.984348 RX Vref Scan: 0
6407 01:21:31.984406
6408 01:21:31.984465 RX Vref 0 -> 0, step: 1
6409 01:21:31.984523
6410 01:21:31.984581 RX Delay -410 -> 252, step: 16
6411 01:21:31.984640 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6412 01:21:31.984699 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6413 01:21:31.984758 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6414 01:21:31.984816 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6415 01:21:31.984875 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6416 01:21:31.984934 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6417 01:21:31.984993 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6418 01:21:31.985052 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6419 01:21:31.985110 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6420 01:21:31.985169 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6421 01:21:31.985228 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6422 01:21:31.985287 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6423 01:21:31.985357 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6424 01:21:31.985418 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6425 01:21:31.985477 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6426 01:21:31.985549 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6427 01:21:31.985603 ==
6428 01:21:31.985656 Dram Type= 6, Freq= 0, CH_0, rank 0
6429 01:21:31.985711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 01:21:31.985765 ==
6431 01:21:31.985823 DQS Delay:
6432 01:21:31.985880 DQS0 = 43, DQS1 = 59
6433 01:21:31.985935 DQM Delay:
6434 01:21:31.985989 DQM0 = 9, DQM1 = 11
6435 01:21:31.986042 DQ Delay:
6436 01:21:31.986097 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6437 01:21:31.986150 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6438 01:21:31.986204 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6439 01:21:31.986258 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6440 01:21:31.986312
6441 01:21:31.986365
6442 01:21:31.986417 ==
6443 01:21:31.986471 Dram Type= 6, Freq= 0, CH_0, rank 0
6444 01:21:31.986525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6445 01:21:31.986578 ==
6446 01:21:31.986631
6447 01:21:31.986684
6448 01:21:31.986738 TX Vref Scan disable
6449 01:21:31.986792 == TX Byte 0 ==
6450 01:21:31.986845 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6451 01:21:31.987091 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6452 01:21:31.987153 == TX Byte 1 ==
6453 01:21:31.987209 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6454 01:21:31.987264 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6455 01:21:31.987318 ==
6456 01:21:31.987372 Dram Type= 6, Freq= 0, CH_0, rank 0
6457 01:21:31.987426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6458 01:21:31.987480 ==
6459 01:21:31.987534
6460 01:21:31.987587
6461 01:21:31.987640 TX Vref Scan disable
6462 01:21:31.987693 == TX Byte 0 ==
6463 01:21:31.987747 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6464 01:21:31.987801 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6465 01:21:31.987855 == TX Byte 1 ==
6466 01:21:31.987926 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6467 01:21:31.987983 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6468 01:21:31.988060
6469 01:21:31.988141 [DATLAT]
6470 01:21:31.988259 Freq=400, CH0 RK0
6471 01:21:31.988395
6472 01:21:31.988498 DATLAT Default: 0xf
6473 01:21:31.988558 0, 0xFFFF, sum = 0
6474 01:21:31.988617 1, 0xFFFF, sum = 0
6475 01:21:31.988673 2, 0xFFFF, sum = 0
6476 01:21:31.988728 3, 0xFFFF, sum = 0
6477 01:21:31.988783 4, 0xFFFF, sum = 0
6478 01:21:31.988837 5, 0xFFFF, sum = 0
6479 01:21:31.988892 6, 0xFFFF, sum = 0
6480 01:21:31.988945 7, 0xFFFF, sum = 0
6481 01:21:31.989000 8, 0xFFFF, sum = 0
6482 01:21:31.989055 9, 0xFFFF, sum = 0
6483 01:21:31.989110 10, 0xFFFF, sum = 0
6484 01:21:31.989165 11, 0xFFFF, sum = 0
6485 01:21:31.989219 12, 0xFFFF, sum = 0
6486 01:21:31.989274 13, 0x0, sum = 1
6487 01:21:31.989335 14, 0x0, sum = 2
6488 01:21:31.989394 15, 0x0, sum = 3
6489 01:21:31.989449 16, 0x0, sum = 4
6490 01:21:31.989502 best_step = 14
6491 01:21:31.989556
6492 01:21:31.989609 ==
6493 01:21:31.989663 Dram Type= 6, Freq= 0, CH_0, rank 0
6494 01:21:31.989717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 01:21:31.989771 ==
6496 01:21:31.989825 RX Vref Scan: 1
6497 01:21:31.989879
6498 01:21:31.989932 RX Vref 0 -> 0, step: 1
6499 01:21:31.989985
6500 01:21:31.990038 RX Delay -359 -> 252, step: 8
6501 01:21:31.990092
6502 01:21:31.990146 Set Vref, RX VrefLevel [Byte0]: 57
6503 01:21:31.990200 [Byte1]: 49
6504 01:21:31.990254
6505 01:21:31.990307 Final RX Vref Byte 0 = 57 to rank0
6506 01:21:31.990361 Final RX Vref Byte 1 = 49 to rank0
6507 01:21:31.990416 Final RX Vref Byte 0 = 57 to rank1
6508 01:21:31.990469 Final RX Vref Byte 1 = 49 to rank1==
6509 01:21:31.990536 Dram Type= 6, Freq= 0, CH_0, rank 0
6510 01:21:31.990588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 01:21:31.990641 ==
6512 01:21:31.990694 DQS Delay:
6513 01:21:31.990746 DQS0 = 48, DQS1 = 60
6514 01:21:31.990799 DQM Delay:
6515 01:21:31.990851 DQM0 = 11, DQM1 = 12
6516 01:21:31.990903 DQ Delay:
6517 01:21:31.990955 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6518 01:21:31.991008 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6519 01:21:31.991061 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6520 01:21:31.991113 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6521 01:21:31.991166
6522 01:21:31.991218
6523 01:21:31.991271 [DQSOSCAuto] RK0, (LSB)MR18= 0xb77a, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 387 ps
6524 01:21:31.991324 CH0 RK0: MR19=C0C, MR18=B77A
6525 01:21:31.991377 CH0_RK0: MR19=0xC0C, MR18=0xB77A, DQSOSC=387, MR23=63, INC=394, DEC=262
6526 01:21:31.991431 ==
6527 01:21:31.991485 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 01:21:31.991537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 01:21:31.991590 ==
6530 01:21:31.991642 [Gating] SW mode calibration
6531 01:21:31.991695 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6532 01:21:31.991748 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6533 01:21:31.991801 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6534 01:21:31.991884 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6535 01:21:31.991937 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6536 01:21:31.991989 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6537 01:21:31.992041 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6538 01:21:31.992093 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6539 01:21:31.992146 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6540 01:21:31.992198 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6541 01:21:31.992250 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6542 01:21:31.992302 Total UI for P1: 0, mck2ui 16
6543 01:21:31.992355 best dqsien dly found for B0: ( 0, 14, 24)
6544 01:21:31.992407 Total UI for P1: 0, mck2ui 16
6545 01:21:31.992461 best dqsien dly found for B1: ( 0, 14, 24)
6546 01:21:31.992514 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6547 01:21:31.992566 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6548 01:21:31.992619
6549 01:21:31.992671 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6550 01:21:31.992724 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6551 01:21:31.992776 [Gating] SW calibration Done
6552 01:21:31.992828 ==
6553 01:21:31.992881 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 01:21:31.992933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 01:21:31.992986 ==
6556 01:21:31.993039 RX Vref Scan: 0
6557 01:21:31.993091
6558 01:21:31.993143 RX Vref 0 -> 0, step: 1
6559 01:21:31.993195
6560 01:21:31.993247 RX Delay -410 -> 252, step: 16
6561 01:21:31.993299 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6562 01:21:31.993360 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6563 01:21:31.993414 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6564 01:21:31.993467 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6565 01:21:31.993520 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6566 01:21:31.993573 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6567 01:21:31.993626 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6568 01:21:31.993678 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6569 01:21:31.993730 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6570 01:21:31.993783 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6571 01:21:31.993835 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6572 01:21:31.993888 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6573 01:21:31.993940 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6574 01:21:31.993992 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6575 01:21:31.994045 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6576 01:21:31.994097 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6577 01:21:31.994150 ==
6578 01:21:31.994203 Dram Type= 6, Freq= 0, CH_0, rank 1
6579 01:21:31.994255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 01:21:31.994308 ==
6581 01:21:31.994360 DQS Delay:
6582 01:21:31.994412 DQS0 = 35, DQS1 = 59
6583 01:21:31.994465 DQM Delay:
6584 01:21:31.994517 DQM0 = 4, DQM1 = 16
6585 01:21:31.994570 DQ Delay:
6586 01:21:31.994622 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6587 01:21:31.994674 DQ4 =0, DQ5 =0, DQ6 =8, DQ7 =16
6588 01:21:31.994919 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6589 01:21:31.994979 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6590 01:21:31.995033
6591 01:21:31.995086
6592 01:21:31.995137 ==
6593 01:21:31.995190 Dram Type= 6, Freq= 0, CH_0, rank 1
6594 01:21:31.995242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6595 01:21:31.995295 ==
6596 01:21:31.995347
6597 01:21:31.995400
6598 01:21:31.995452 TX Vref Scan disable
6599 01:21:31.995504 == TX Byte 0 ==
6600 01:21:31.995557 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6601 01:21:31.995610 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6602 01:21:31.995663 == TX Byte 1 ==
6603 01:21:31.995716 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6604 01:21:31.995770 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6605 01:21:31.995846 ==
6606 01:21:31.995914 Dram Type= 6, Freq= 0, CH_0, rank 1
6607 01:21:31.995967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6608 01:21:31.996020 ==
6609 01:21:31.996073
6610 01:21:31.996124
6611 01:21:31.996177 TX Vref Scan disable
6612 01:21:31.996230 == TX Byte 0 ==
6613 01:21:31.996282 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6614 01:21:31.996335 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6615 01:21:31.996387 == TX Byte 1 ==
6616 01:21:31.996440 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6617 01:21:31.996492 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6618 01:21:31.996544
6619 01:21:31.996596 [DATLAT]
6620 01:21:31.996648 Freq=400, CH0 RK1
6621 01:21:31.996701
6622 01:21:31.996752 DATLAT Default: 0xe
6623 01:21:31.996804 0, 0xFFFF, sum = 0
6624 01:21:31.996858 1, 0xFFFF, sum = 0
6625 01:21:31.996920 2, 0xFFFF, sum = 0
6626 01:21:31.996974 3, 0xFFFF, sum = 0
6627 01:21:31.997027 4, 0xFFFF, sum = 0
6628 01:21:31.997080 5, 0xFFFF, sum = 0
6629 01:21:31.997133 6, 0xFFFF, sum = 0
6630 01:21:31.997185 7, 0xFFFF, sum = 0
6631 01:21:31.997239 8, 0xFFFF, sum = 0
6632 01:21:31.997292 9, 0xFFFF, sum = 0
6633 01:21:31.997384 10, 0xFFFF, sum = 0
6634 01:21:31.997439 11, 0xFFFF, sum = 0
6635 01:21:31.997492 12, 0xFFFF, sum = 0
6636 01:21:31.997546 13, 0x0, sum = 1
6637 01:21:31.997600 14, 0x0, sum = 2
6638 01:21:31.997653 15, 0x0, sum = 3
6639 01:21:31.997706 16, 0x0, sum = 4
6640 01:21:31.997759 best_step = 14
6641 01:21:31.997811
6642 01:21:31.997863 ==
6643 01:21:31.997916 Dram Type= 6, Freq= 0, CH_0, rank 1
6644 01:21:31.997968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6645 01:21:31.998021 ==
6646 01:21:31.998073 RX Vref Scan: 0
6647 01:21:31.998126
6648 01:21:31.998179 RX Vref 0 -> 0, step: 1
6649 01:21:31.998232
6650 01:21:31.998283 RX Delay -359 -> 252, step: 8
6651 01:21:31.998335 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6652 01:21:31.998389 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6653 01:21:31.998442 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6654 01:21:31.998494 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6655 01:21:31.998546 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6656 01:21:31.998599 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6657 01:21:31.998651 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6658 01:21:31.998704 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6659 01:21:31.998756 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6660 01:21:31.998809 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6661 01:21:31.998869 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6662 01:21:31.999037 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6663 01:21:31.999138 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6664 01:21:31.999197 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6665 01:21:31.999251 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6666 01:21:31.999306 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6667 01:21:31.999359 ==
6668 01:21:31.999412 Dram Type= 6, Freq= 0, CH_0, rank 1
6669 01:21:31.999466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6670 01:21:31.999520 ==
6671 01:21:31.999573 DQS Delay:
6672 01:21:31.999625 DQS0 = 44, DQS1 = 60
6673 01:21:31.999678 DQM Delay:
6674 01:21:31.999730 DQM0 = 8, DQM1 = 14
6675 01:21:31.999783 DQ Delay:
6676 01:21:31.999835 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =8
6677 01:21:31.999888 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6678 01:21:31.999940 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6679 01:21:31.999993 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6680 01:21:32.000045
6681 01:21:32.000097
6682 01:21:32.000149 [DQSOSCAuto] RK1, (LSB)MR18= 0xa734, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
6683 01:21:32.000203 CH0 RK1: MR19=C0C, MR18=A734
6684 01:21:32.000256 CH0_RK1: MR19=0xC0C, MR18=0xA734, DQSOSC=389, MR23=63, INC=390, DEC=260
6685 01:21:32.000310 [RxdqsGatingPostProcess] freq 400
6686 01:21:32.000363 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6687 01:21:32.000416 best DQS0 dly(2T, 0.5T) = (0, 10)
6688 01:21:32.000469 best DQS1 dly(2T, 0.5T) = (0, 10)
6689 01:21:32.000521 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6690 01:21:32.000574 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6691 01:21:32.000626 best DQS0 dly(2T, 0.5T) = (0, 10)
6692 01:21:32.000678 best DQS1 dly(2T, 0.5T) = (0, 10)
6693 01:21:32.000730 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6694 01:21:32.000782 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6695 01:21:32.000834 Pre-setting of DQS Precalculation
6696 01:21:32.000887 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6697 01:21:32.000940 ==
6698 01:21:32.000992 Dram Type= 6, Freq= 0, CH_1, rank 0
6699 01:21:32.001045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6700 01:21:32.001097 ==
6701 01:21:32.001149 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6702 01:21:32.001203 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6703 01:21:32.001256 [CA 0] Center 36 (8~64) winsize 57
6704 01:21:32.001308 [CA 1] Center 36 (8~64) winsize 57
6705 01:21:32.001396 [CA 2] Center 36 (8~64) winsize 57
6706 01:21:32.001463 [CA 3] Center 36 (8~64) winsize 57
6707 01:21:32.001515 [CA 4] Center 36 (8~64) winsize 57
6708 01:21:32.001567 [CA 5] Center 36 (8~64) winsize 57
6709 01:21:32.001620
6710 01:21:32.001671 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6711 01:21:32.001724
6712 01:21:32.001776 [CATrainingPosCal] consider 1 rank data
6713 01:21:32.001839 u2DelayCellTimex100 = 270/100 ps
6714 01:21:32.001927 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 01:21:32.002021 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 01:21:32.002118 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 01:21:32.002208 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 01:21:32.002266 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 01:21:32.002320 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 01:21:32.002374
6721 01:21:32.002427 CA PerBit enable=1, Macro0, CA PI delay=36
6722 01:21:32.002479
6723 01:21:32.002531 [CBTSetCACLKResult] CA Dly = 36
6724 01:21:32.002586 CS Dly: 1 (0~32)
6725 01:21:32.002639 ==
6726 01:21:32.002691 Dram Type= 6, Freq= 0, CH_1, rank 1
6727 01:21:32.002937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 01:21:32.003000 ==
6729 01:21:32.003055 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6730 01:21:32.003108 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6731 01:21:32.003162 [CA 0] Center 36 (8~64) winsize 57
6732 01:21:32.003215 [CA 1] Center 36 (8~64) winsize 57
6733 01:21:32.003268 [CA 2] Center 36 (8~64) winsize 57
6734 01:21:32.003320 [CA 3] Center 36 (8~64) winsize 57
6735 01:21:32.003373 [CA 4] Center 36 (8~64) winsize 57
6736 01:21:32.003426 [CA 5] Center 36 (8~64) winsize 57
6737 01:21:32.003483
6738 01:21:32.003536 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6739 01:21:32.003603
6740 01:21:32.003657 [CATrainingPosCal] consider 2 rank data
6741 01:21:32.003710 u2DelayCellTimex100 = 270/100 ps
6742 01:21:32.003762 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6743 01:21:32.003815 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6744 01:21:32.003867 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6745 01:21:32.003924 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6746 01:21:32.003982 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6747 01:21:32.004035 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6748 01:21:32.004091
6749 01:21:32.004144 CA PerBit enable=1, Macro0, CA PI delay=36
6750 01:21:32.004219
6751 01:21:32.004395 [CBTSetCACLKResult] CA Dly = 36
6752 01:21:32.004494 CS Dly: 1 (0~32)
6753 01:21:32.004581
6754 01:21:32.004665 ----->DramcWriteLeveling(PI) begin...
6755 01:21:32.004752 ==
6756 01:21:32.004835 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 01:21:32.004920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 01:21:32.005003 ==
6759 01:21:32.005085 Write leveling (Byte 0): 40 => 8
6760 01:21:32.005166 Write leveling (Byte 1): 40 => 8
6761 01:21:32.005248 DramcWriteLeveling(PI) end<-----
6762 01:21:32.005337
6763 01:21:32.005429 ==
6764 01:21:32.005482 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 01:21:32.005536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 01:21:32.005590 ==
6767 01:21:32.005642 [Gating] SW mode calibration
6768 01:21:32.005694 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6769 01:21:32.005747 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6770 01:21:32.005800 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6771 01:21:32.005854 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6772 01:21:32.005906 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6773 01:21:32.005959 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6774 01:21:32.006011 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6775 01:21:32.006064 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6776 01:21:32.006116 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6777 01:21:32.006169 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6778 01:21:32.006221 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6779 01:21:32.006273 Total UI for P1: 0, mck2ui 16
6780 01:21:32.006326 best dqsien dly found for B0: ( 0, 14, 24)
6781 01:21:32.006379 Total UI for P1: 0, mck2ui 16
6782 01:21:32.006431 best dqsien dly found for B1: ( 0, 14, 24)
6783 01:21:32.006484 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6784 01:21:32.006536 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6785 01:21:32.006588
6786 01:21:32.006640 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6787 01:21:32.006716 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6788 01:21:32.006809 [Gating] SW calibration Done
6789 01:21:32.006931 ==
6790 01:21:32.007060 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 01:21:32.007149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 01:21:32.007208 ==
6793 01:21:32.007262 RX Vref Scan: 0
6794 01:21:32.007315
6795 01:21:32.007368 RX Vref 0 -> 0, step: 1
6796 01:21:32.007421
6797 01:21:32.007474 RX Delay -410 -> 252, step: 16
6798 01:21:32.007526 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6799 01:21:32.007579 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6800 01:21:32.007632 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6801 01:21:32.007684 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6802 01:21:32.007738 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6803 01:21:32.007790 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6804 01:21:32.007843 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6805 01:21:32.007896 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6806 01:21:32.007949 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6807 01:21:32.008001 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6808 01:21:32.008053 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6809 01:21:32.008105 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6810 01:21:32.008158 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6811 01:21:32.008210 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6812 01:21:32.008262 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6813 01:21:32.008315 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6814 01:21:32.008366 ==
6815 01:21:32.008419 Dram Type= 6, Freq= 0, CH_1, rank 0
6816 01:21:32.008471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 01:21:32.008524 ==
6818 01:21:32.008576 DQS Delay:
6819 01:21:32.008629 DQS0 = 43, DQS1 = 51
6820 01:21:32.008680 DQM Delay:
6821 01:21:32.008735 DQM0 = 12, DQM1 = 14
6822 01:21:32.008788 DQ Delay:
6823 01:21:32.008840 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6824 01:21:32.008915 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6825 01:21:32.009069 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6826 01:21:32.009180 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6827 01:21:32.009275
6828 01:21:32.009403
6829 01:21:32.009460 ==
6830 01:21:32.009514 Dram Type= 6, Freq= 0, CH_1, rank 0
6831 01:21:32.009568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6832 01:21:32.009622 ==
6833 01:21:32.009676
6834 01:21:32.009741
6835 01:21:32.009811 TX Vref Scan disable
6836 01:21:32.009870 == TX Byte 0 ==
6837 01:21:32.009944 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6838 01:21:32.010030 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6839 01:21:32.010113 == TX Byte 1 ==
6840 01:21:32.010196 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6841 01:21:32.010256 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6842 01:21:32.010346 ==
6843 01:21:32.010433 Dram Type= 6, Freq= 0, CH_1, rank 0
6844 01:21:32.010519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6845 01:21:32.010602 ==
6846 01:21:32.010684
6847 01:21:32.010766
6848 01:21:32.010847 TX Vref Scan disable
6849 01:21:32.010929 == TX Byte 0 ==
6850 01:21:32.011011 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6851 01:21:32.011095 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6852 01:21:32.011262 == TX Byte 1 ==
6853 01:21:32.011368 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6854 01:21:32.011655 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6855 01:21:32.011745
6856 01:21:32.011830 [DATLAT]
6857 01:21:32.011913 Freq=400, CH1 RK0
6858 01:21:32.011996
6859 01:21:32.012078 DATLAT Default: 0xf
6860 01:21:32.012160 0, 0xFFFF, sum = 0
6861 01:21:32.012244 1, 0xFFFF, sum = 0
6862 01:21:32.012328 2, 0xFFFF, sum = 0
6863 01:21:32.012411 3, 0xFFFF, sum = 0
6864 01:21:32.012495 4, 0xFFFF, sum = 0
6865 01:21:32.012578 5, 0xFFFF, sum = 0
6866 01:21:32.012661 6, 0xFFFF, sum = 0
6867 01:21:32.012744 7, 0xFFFF, sum = 0
6868 01:21:32.012828 8, 0xFFFF, sum = 0
6869 01:21:32.012911 9, 0xFFFF, sum = 0
6870 01:21:32.012994 10, 0xFFFF, sum = 0
6871 01:21:32.013078 11, 0xFFFF, sum = 0
6872 01:21:32.013164 12, 0xFFFF, sum = 0
6873 01:21:32.013248 13, 0x0, sum = 1
6874 01:21:32.013337 14, 0x0, sum = 2
6875 01:21:32.013428 15, 0x0, sum = 3
6876 01:21:32.013482 16, 0x0, sum = 4
6877 01:21:32.013535 best_step = 14
6878 01:21:32.013588
6879 01:21:32.013641 ==
6880 01:21:32.013693 Dram Type= 6, Freq= 0, CH_1, rank 0
6881 01:21:32.013747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 01:21:32.013800 ==
6883 01:21:32.013853 RX Vref Scan: 1
6884 01:21:32.013905
6885 01:21:32.013958 RX Vref 0 -> 0, step: 1
6886 01:21:32.014011
6887 01:21:32.014064 RX Delay -343 -> 252, step: 8
6888 01:21:32.014116
6889 01:21:32.014169 Set Vref, RX VrefLevel [Byte0]: 51
6890 01:21:32.014221 [Byte1]: 59
6891 01:21:32.014274
6892 01:21:32.014326 Final RX Vref Byte 0 = 51 to rank0
6893 01:21:32.014379 Final RX Vref Byte 1 = 59 to rank0
6894 01:21:32.014431 Final RX Vref Byte 0 = 51 to rank1
6895 01:21:32.014485 Final RX Vref Byte 1 = 59 to rank1==
6896 01:21:32.014537 Dram Type= 6, Freq= 0, CH_1, rank 0
6897 01:21:32.014590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 01:21:32.014644 ==
6899 01:21:32.014696 DQS Delay:
6900 01:21:32.014749 DQS0 = 44, DQS1 = 56
6901 01:21:32.014801 DQM Delay:
6902 01:21:32.014864 DQM0 = 7, DQM1 = 12
6903 01:21:32.014917 DQ Delay:
6904 01:21:32.014969 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6905 01:21:32.015022 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =0
6906 01:21:32.015075 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6907 01:21:32.015127 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =24
6908 01:21:32.015180
6909 01:21:32.015231
6910 01:21:32.015286 [DQSOSCAuto] RK0, (LSB)MR18= 0x8960, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 392 ps
6911 01:21:32.015340 CH1 RK0: MR19=C0C, MR18=8960
6912 01:21:32.015393 CH1_RK0: MR19=0xC0C, MR18=0x8960, DQSOSC=392, MR23=63, INC=384, DEC=256
6913 01:21:32.015446 ==
6914 01:21:32.015498 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 01:21:32.015551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 01:21:32.015604 ==
6917 01:21:32.015657 [Gating] SW mode calibration
6918 01:21:32.015709 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6919 01:21:32.015763 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6920 01:21:32.015815 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6921 01:21:32.015869 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6922 01:21:32.015921 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6923 01:21:32.015974 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6924 01:21:32.016026 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6925 01:21:32.016078 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6926 01:21:32.016132 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6927 01:21:32.016185 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6928 01:21:32.016237 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6929 01:21:32.016290 Total UI for P1: 0, mck2ui 16
6930 01:21:32.016343 best dqsien dly found for B0: ( 0, 14, 24)
6931 01:21:32.016396 Total UI for P1: 0, mck2ui 16
6932 01:21:32.016448 best dqsien dly found for B1: ( 0, 14, 24)
6933 01:21:32.016501 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6934 01:21:32.016554 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6935 01:21:32.016606
6936 01:21:32.016658 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6937 01:21:32.016711 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6938 01:21:32.016763 [Gating] SW calibration Done
6939 01:21:32.016816 ==
6940 01:21:32.016869 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 01:21:32.016921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 01:21:32.016974 ==
6943 01:21:32.017027 RX Vref Scan: 0
6944 01:21:32.017080
6945 01:21:32.017132 RX Vref 0 -> 0, step: 1
6946 01:21:32.017184
6947 01:21:32.017236 RX Delay -410 -> 252, step: 16
6948 01:21:32.017293 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6949 01:21:32.017429 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6950 01:21:32.017583 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6951 01:21:32.017701 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6952 01:21:32.017772 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6953 01:21:32.017838 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6954 01:21:32.017897 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6955 01:21:32.017951 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6956 01:21:32.018004 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6957 01:21:32.018058 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6958 01:21:32.018111 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6959 01:21:32.018164 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6960 01:21:32.018217 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6961 01:21:32.018275 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6962 01:21:32.018337 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6963 01:21:32.018391 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6964 01:21:32.018554 ==
6965 01:21:32.018675 Dram Type= 6, Freq= 0, CH_1, rank 1
6966 01:21:32.018771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6967 01:21:32.018864 ==
6968 01:21:32.018948 DQS Delay:
6969 01:21:32.019030 DQS0 = 51, DQS1 = 51
6970 01:21:32.019113 DQM Delay:
6971 01:21:32.019195 DQM0 = 19, DQM1 = 14
6972 01:21:32.019276 DQ Delay:
6973 01:21:32.019358 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6974 01:21:32.019440 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6975 01:21:32.019522 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6976 01:21:32.019604 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6977 01:21:32.019685
6978 01:21:32.019767
6979 01:21:32.019847 ==
6980 01:21:32.020002 Dram Type= 6, Freq= 0, CH_1, rank 1
6981 01:21:32.020124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6982 01:21:32.020217 ==
6983 01:21:32.020300
6984 01:21:32.020381
6985 01:21:32.020462 TX Vref Scan disable
6986 01:21:32.020544 == TX Byte 0 ==
6987 01:21:32.020627 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6988 01:21:32.020710 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6989 01:21:32.020792 == TX Byte 1 ==
6990 01:21:32.020874 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6991 01:21:32.020957 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6992 01:21:32.021038 ==
6993 01:21:32.021120 Dram Type= 6, Freq= 0, CH_1, rank 1
6994 01:21:32.021431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6995 01:21:32.021524 ==
6996 01:21:32.021608
6997 01:21:32.021690
6998 01:21:32.021772 TX Vref Scan disable
6999 01:21:32.021855 == TX Byte 0 ==
7000 01:21:32.021938 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
7001 01:21:32.022025 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
7002 01:21:32.022110 == TX Byte 1 ==
7003 01:21:32.022195 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
7004 01:21:32.022277 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
7005 01:21:32.929974
7006 01:21:32.930514 [DATLAT]
7007 01:21:32.930881 Freq=400, CH1 RK1
7008 01:21:32.931229
7009 01:21:32.931551 DATLAT Default: 0xe
7010 01:21:32.931645 0, 0xFFFF, sum = 0
7011 01:21:32.931760 1, 0xFFFF, sum = 0
7012 01:21:32.931816 2, 0xFFFF, sum = 0
7013 01:21:32.931870 3, 0xFFFF, sum = 0
7014 01:21:32.931925 4, 0xFFFF, sum = 0
7015 01:21:32.931978 5, 0xFFFF, sum = 0
7016 01:21:32.932032 6, 0xFFFF, sum = 0
7017 01:21:32.932084 7, 0xFFFF, sum = 0
7018 01:21:32.932137 8, 0xFFFF, sum = 0
7019 01:21:32.932189 9, 0xFFFF, sum = 0
7020 01:21:32.932241 10, 0xFFFF, sum = 0
7021 01:21:32.932293 11, 0xFFFF, sum = 0
7022 01:21:32.932345 12, 0xFFFF, sum = 0
7023 01:21:32.932397 13, 0x0, sum = 1
7024 01:21:32.932449 14, 0x0, sum = 2
7025 01:21:32.932501 15, 0x0, sum = 3
7026 01:21:32.932553 16, 0x0, sum = 4
7027 01:21:32.932605 best_step = 14
7028 01:21:32.932656
7029 01:21:32.932707 ==
7030 01:21:32.932758 Dram Type= 6, Freq= 0, CH_1, rank 1
7031 01:21:32.932810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7032 01:21:32.932862 ==
7033 01:21:32.932913 RX Vref Scan: 0
7034 01:21:32.932964
7035 01:21:32.933030 RX Vref 0 -> 0, step: 1
7036 01:21:32.933087
7037 01:21:32.933138 RX Delay -343 -> 252, step: 8
7038 01:21:32.933190 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
7039 01:21:32.933241 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7040 01:21:32.933293 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
7041 01:21:32.933371 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7042 01:21:32.933450 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7043 01:21:32.933501 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
7044 01:21:32.933552 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7045 01:21:32.933603 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
7046 01:21:32.933654 iDelay=225, Bit 8, Center -60 (-311 ~ 192) 504
7047 01:21:32.933705 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7048 01:21:32.933757 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7049 01:21:32.933837 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
7050 01:21:32.933888 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7051 01:21:32.933938 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7052 01:21:32.933989 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7053 01:21:32.934042 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7054 01:21:32.934093 ==
7055 01:21:32.934144 Dram Type= 6, Freq= 0, CH_1, rank 1
7056 01:21:32.934195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7057 01:21:32.934247 ==
7058 01:21:32.934298 DQS Delay:
7059 01:21:32.934349 DQS0 = 44, DQS1 = 60
7060 01:21:32.934400 DQM Delay:
7061 01:21:32.934451 DQM0 = 10, DQM1 = 14
7062 01:21:32.934502 DQ Delay:
7063 01:21:32.934552 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
7064 01:21:32.934603 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
7065 01:21:32.934654 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
7066 01:21:32.934706 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7067 01:21:32.934756
7068 01:21:32.934807
7069 01:21:32.934857 [DQSOSCAuto] RK1, (LSB)MR18= 0x5a49, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
7070 01:21:32.934909 CH1 RK1: MR19=C0C, MR18=5A49
7071 01:21:32.934960 CH1_RK1: MR19=0xC0C, MR18=0x5A49, DQSOSC=398, MR23=63, INC=372, DEC=248
7072 01:21:32.935012 [RxdqsGatingPostProcess] freq 400
7073 01:21:32.935063 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7074 01:21:32.935114 best DQS0 dly(2T, 0.5T) = (0, 10)
7075 01:21:32.935165 best DQS1 dly(2T, 0.5T) = (0, 10)
7076 01:21:32.935216 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7077 01:21:32.935267 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7078 01:21:32.935318 best DQS0 dly(2T, 0.5T) = (0, 10)
7079 01:21:32.935368 best DQS1 dly(2T, 0.5T) = (0, 10)
7080 01:21:32.935419 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7081 01:21:32.935470 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7082 01:21:32.935520 Pre-setting of DQS Precalculation
7083 01:21:32.935571 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7084 01:21:32.935622 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7085 01:21:32.935674 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7086 01:21:32.935726
7087 01:21:32.935777
7088 01:21:32.935827 [Calibration Summary] 800 Mbps
7089 01:21:32.935878 CH 0, Rank 0
7090 01:21:32.935928 SW Impedance : PASS
7091 01:21:32.935979 DUTY Scan : NO K
7092 01:21:32.936029 ZQ Calibration : PASS
7093 01:21:32.936080 Jitter Meter : NO K
7094 01:21:32.936131 CBT Training : PASS
7095 01:21:32.936182 Write leveling : PASS
7096 01:21:32.936233 RX DQS gating : PASS
7097 01:21:32.936283 RX DQ/DQS(RDDQC) : PASS
7098 01:21:32.936335 TX DQ/DQS : PASS
7099 01:21:32.936386 RX DATLAT : PASS
7100 01:21:32.936437 RX DQ/DQS(Engine): PASS
7101 01:21:32.936487 TX OE : NO K
7102 01:21:32.936538 All Pass.
7103 01:21:32.936589
7104 01:21:32.936640 CH 0, Rank 1
7105 01:21:32.936691 SW Impedance : PASS
7106 01:21:32.936742 DUTY Scan : NO K
7107 01:21:32.936792 ZQ Calibration : PASS
7108 01:21:32.936843 Jitter Meter : NO K
7109 01:21:32.936893 CBT Training : PASS
7110 01:21:32.936944 Write leveling : NO K
7111 01:21:32.936995 RX DQS gating : PASS
7112 01:21:32.937078 RX DQ/DQS(RDDQC) : PASS
7113 01:21:32.937181 TX DQ/DQS : PASS
7114 01:21:32.937232 RX DATLAT : PASS
7115 01:21:32.937283 RX DQ/DQS(Engine): PASS
7116 01:21:32.937358 TX OE : NO K
7117 01:21:32.937438 All Pass.
7118 01:21:32.937489
7119 01:21:32.937541 CH 1, Rank 0
7120 01:21:32.937592 SW Impedance : PASS
7121 01:21:32.937643 DUTY Scan : NO K
7122 01:21:32.937694 ZQ Calibration : PASS
7123 01:21:32.937745 Jitter Meter : NO K
7124 01:21:32.937796 CBT Training : PASS
7125 01:21:32.937847 Write leveling : PASS
7126 01:21:32.937898 RX DQS gating : PASS
7127 01:21:32.937949 RX DQ/DQS(RDDQC) : PASS
7128 01:21:32.937999 TX DQ/DQS : PASS
7129 01:21:32.938051 RX DATLAT : PASS
7130 01:21:32.938101 RX DQ/DQS(Engine): PASS
7131 01:21:32.938168 TX OE : NO K
7132 01:21:32.938220 All Pass.
7133 01:21:32.938303
7134 01:21:32.938367 CH 1, Rank 1
7135 01:21:32.938419 SW Impedance : PASS
7136 01:21:32.938470 DUTY Scan : NO K
7137 01:21:32.938521 ZQ Calibration : PASS
7138 01:21:32.938572 Jitter Meter : NO K
7139 01:21:32.938623 CBT Training : PASS
7140 01:21:32.938674 Write leveling : NO K
7141 01:21:32.938725 RX DQS gating : PASS
7142 01:21:32.938776 RX DQ/DQS(RDDQC) : PASS
7143 01:21:32.938827 TX DQ/DQS : PASS
7144 01:21:32.938878 RX DATLAT : PASS
7145 01:21:32.939151 RX DQ/DQS(Engine): PASS
7146 01:21:32.939214 TX OE : NO K
7147 01:21:32.939268 All Pass.
7148 01:21:32.939321
7149 01:21:32.939373 DramC Write-DBI off
7150 01:21:32.939425 PER_BANK_REFRESH: Hybrid Mode
7151 01:21:32.939478 TX_TRACKING: ON
7152 01:21:32.939532 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7153 01:21:32.939586 [FAST_K] Save calibration result to emmc
7154 01:21:32.939638 dramc_set_vcore_voltage set vcore to 725000
7155 01:21:32.939703 Read voltage for 1600, 0
7156 01:21:32.939755 Vio18 = 0
7157 01:21:32.939806 Vcore = 725000
7158 01:21:32.939858 Vdram = 0
7159 01:21:32.939909 Vddq = 0
7160 01:21:32.939960 Vmddr = 0
7161 01:21:32.940010 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7162 01:21:32.940062 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7163 01:21:32.940114 MEM_TYPE=3, freq_sel=13
7164 01:21:32.940166 sv_algorithm_assistance_LP4_3733
7165 01:21:32.940217 ============ PULL DRAM RESETB DOWN ============
7166 01:21:32.940269 ========== PULL DRAM RESETB DOWN end =========
7167 01:21:32.940320 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7168 01:21:32.940372 ===================================
7169 01:21:32.940424 LPDDR4 DRAM CONFIGURATION
7170 01:21:32.940475 ===================================
7171 01:21:32.940527 EX_ROW_EN[0] = 0x0
7172 01:21:32.940579 EX_ROW_EN[1] = 0x0
7173 01:21:32.940630 LP4Y_EN = 0x0
7174 01:21:32.940681 WORK_FSP = 0x1
7175 01:21:32.940733 WL = 0x5
7176 01:21:32.940784 RL = 0x5
7177 01:21:32.940835 BL = 0x2
7178 01:21:32.940886 RPST = 0x0
7179 01:21:32.940937 RD_PRE = 0x0
7180 01:21:32.941003 WR_PRE = 0x1
7181 01:21:32.941068 WR_PST = 0x1
7182 01:21:32.941119 DBI_WR = 0x0
7183 01:21:32.941170 DBI_RD = 0x0
7184 01:21:32.941220 OTF = 0x1
7185 01:21:32.941272 ===================================
7186 01:21:32.941323 ===================================
7187 01:21:32.941430 ANA top config
7188 01:21:32.941481 ===================================
7189 01:21:32.941533 DLL_ASYNC_EN = 0
7190 01:21:32.941584 ALL_SLAVE_EN = 0
7191 01:21:32.941635 NEW_RANK_MODE = 1
7192 01:21:32.941687 DLL_IDLE_MODE = 1
7193 01:21:32.941738 LP45_APHY_COMB_EN = 1
7194 01:21:32.941788 TX_ODT_DIS = 0
7195 01:21:32.941839 NEW_8X_MODE = 1
7196 01:21:32.941891 ===================================
7197 01:21:32.941942 ===================================
7198 01:21:32.941993 data_rate = 3200
7199 01:21:32.942045 CKR = 1
7200 01:21:32.942096 DQ_P2S_RATIO = 8
7201 01:21:32.942147 ===================================
7202 01:21:32.942198 CA_P2S_RATIO = 8
7203 01:21:32.942249 DQ_CA_OPEN = 0
7204 01:21:32.942300 DQ_SEMI_OPEN = 0
7205 01:21:32.942350 CA_SEMI_OPEN = 0
7206 01:21:32.942401 CA_FULL_RATE = 0
7207 01:21:32.942452 DQ_CKDIV4_EN = 0
7208 01:21:32.942503 CA_CKDIV4_EN = 0
7209 01:21:32.942555 CA_PREDIV_EN = 0
7210 01:21:32.942605 PH8_DLY = 12
7211 01:21:32.942656 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7212 01:21:32.942707 DQ_AAMCK_DIV = 4
7213 01:21:32.942757 CA_AAMCK_DIV = 4
7214 01:21:32.942809 CA_ADMCK_DIV = 4
7215 01:21:32.942860 DQ_TRACK_CA_EN = 0
7216 01:21:32.942911 CA_PICK = 1600
7217 01:21:32.942962 CA_MCKIO = 1600
7218 01:21:32.943013 MCKIO_SEMI = 0
7219 01:21:32.943115 PLL_FREQ = 3068
7220 01:21:32.943200 DQ_UI_PI_RATIO = 32
7221 01:21:32.943270 CA_UI_PI_RATIO = 0
7222 01:21:32.943323 ===================================
7223 01:21:32.943376 ===================================
7224 01:21:32.943428 memory_type:LPDDR4
7225 01:21:32.943479 GP_NUM : 10
7226 01:21:32.943531 SRAM_EN : 1
7227 01:21:32.943583 MD32_EN : 0
7228 01:21:32.943634 ===================================
7229 01:21:32.943686 [ANA_INIT] >>>>>>>>>>>>>>
7230 01:21:32.943737 <<<<<< [CONFIGURE PHASE]: ANA_TX
7231 01:21:32.943790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7232 01:21:32.943842 ===================================
7233 01:21:32.943893 data_rate = 3200,PCW = 0X7600
7234 01:21:32.943945 ===================================
7235 01:21:32.943996 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7236 01:21:32.944048 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7237 01:21:32.944100 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7238 01:21:32.944153 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7239 01:21:32.944205 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7240 01:21:32.944256 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7241 01:21:32.944307 [ANA_INIT] flow start
7242 01:21:32.944358 [ANA_INIT] PLL >>>>>>>>
7243 01:21:32.944409 [ANA_INIT] PLL <<<<<<<<
7244 01:21:32.944461 [ANA_INIT] MIDPI >>>>>>>>
7245 01:21:32.944511 [ANA_INIT] MIDPI <<<<<<<<
7246 01:21:32.944563 [ANA_INIT] DLL >>>>>>>>
7247 01:21:32.944615 [ANA_INIT] DLL <<<<<<<<
7248 01:21:32.944666 [ANA_INIT] flow end
7249 01:21:32.944717 ============ LP4 DIFF to SE enter ============
7250 01:21:32.944769 ============ LP4 DIFF to SE exit ============
7251 01:21:32.944821 [ANA_INIT] <<<<<<<<<<<<<
7252 01:21:32.944872 [Flow] Enable top DCM control >>>>>
7253 01:21:32.944923 [Flow] Enable top DCM control <<<<<
7254 01:21:32.944975 Enable DLL master slave shuffle
7255 01:21:32.945026 ==============================================================
7256 01:21:32.945078 Gating Mode config
7257 01:21:32.945130 ==============================================================
7258 01:21:32.945181 Config description:
7259 01:21:32.945232 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7260 01:21:32.945285 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7261 01:21:32.945363 SELPH_MODE 0: By rank 1: By Phase
7262 01:21:32.945432 ==============================================================
7263 01:21:32.945485 GAT_TRACK_EN = 1
7264 01:21:32.945536 RX_GATING_MODE = 2
7265 01:21:32.945587 RX_GATING_TRACK_MODE = 2
7266 01:21:32.945829 SELPH_MODE = 1
7267 01:21:32.945942 PICG_EARLY_EN = 1
7268 01:21:32.945996 VALID_LAT_VALUE = 1
7269 01:21:32.946048 ==============================================================
7270 01:21:32.946101 Enter into Gating configuration >>>>
7271 01:21:32.946153 Exit from Gating configuration <<<<
7272 01:21:32.946206 Enter into DVFS_PRE_config >>>>>
7273 01:21:32.946258 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7274 01:21:32.946312 Exit from DVFS_PRE_config <<<<<
7275 01:21:32.946365 Enter into PICG configuration >>>>
7276 01:21:32.946417 Exit from PICG configuration <<<<
7277 01:21:32.946469 [RX_INPUT] configuration >>>>>
7278 01:21:32.946534 [RX_INPUT] configuration <<<<<
7279 01:21:32.946585 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7280 01:21:32.946637 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7281 01:21:32.946689 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7282 01:21:32.946741 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7283 01:21:32.946793 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7284 01:21:32.946844 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7285 01:21:32.946896 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7286 01:21:32.946947 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7287 01:21:32.946999 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7288 01:21:32.947050 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7289 01:21:32.947102 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7290 01:21:32.947153 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7291 01:21:32.947204 ===================================
7292 01:21:32.947256 LPDDR4 DRAM CONFIGURATION
7293 01:21:32.947307 ===================================
7294 01:21:32.947358 EX_ROW_EN[0] = 0x0
7295 01:21:32.947410 EX_ROW_EN[1] = 0x0
7296 01:21:32.947461 LP4Y_EN = 0x0
7297 01:21:32.947513 WORK_FSP = 0x1
7298 01:21:32.947564 WL = 0x5
7299 01:21:32.947615 RL = 0x5
7300 01:21:32.947666 BL = 0x2
7301 01:21:32.947717 RPST = 0x0
7302 01:21:32.947768 RD_PRE = 0x0
7303 01:21:32.947818 WR_PRE = 0x1
7304 01:21:32.947869 WR_PST = 0x1
7305 01:21:32.947920 DBI_WR = 0x0
7306 01:21:32.947971 DBI_RD = 0x0
7307 01:21:32.948022 OTF = 0x1
7308 01:21:32.948074 ===================================
7309 01:21:32.948126 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7310 01:21:32.948178 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7311 01:21:32.948230 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7312 01:21:32.948282 ===================================
7313 01:21:32.948333 LPDDR4 DRAM CONFIGURATION
7314 01:21:32.948385 ===================================
7315 01:21:32.948436 EX_ROW_EN[0] = 0x10
7316 01:21:32.948488 EX_ROW_EN[1] = 0x0
7317 01:21:32.948539 LP4Y_EN = 0x0
7318 01:21:32.948590 WORK_FSP = 0x1
7319 01:21:32.948642 WL = 0x5
7320 01:21:32.948693 RL = 0x5
7321 01:21:32.948744 BL = 0x2
7322 01:21:32.948794 RPST = 0x0
7323 01:21:32.948846 RD_PRE = 0x0
7324 01:21:32.948897 WR_PRE = 0x1
7325 01:21:32.948947 WR_PST = 0x1
7326 01:21:32.948999 DBI_WR = 0x0
7327 01:21:32.949050 DBI_RD = 0x0
7328 01:21:32.949101 OTF = 0x1
7329 01:21:32.949152 ===================================
7330 01:21:32.949244 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7331 01:21:32.949325 ==
7332 01:21:32.949446 Dram Type= 6, Freq= 0, CH_0, rank 0
7333 01:21:32.949529 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7334 01:21:32.949615 ==
7335 01:21:32.949672 [Duty_Offset_Calibration]
7336 01:21:32.949724 B0:1 B1:-1 CA:0
7337 01:21:32.949776
7338 01:21:32.949828 [DutyScan_Calibration_Flow] k_type=0
7339 01:21:32.949879
7340 01:21:32.949930 ==CLK 0==
7341 01:21:32.949982 Final CLK duty delay cell = 0
7342 01:21:32.950034 [0] MAX Duty = 5093%(X100), DQS PI = 20
7343 01:21:32.950086 [0] MIN Duty = 4875%(X100), DQS PI = 10
7344 01:21:32.950138 [0] AVG Duty = 4984%(X100)
7345 01:21:32.950190
7346 01:21:32.950241 CH0 CLK Duty spec in!! Max-Min= 218%
7347 01:21:32.950293 [DutyScan_Calibration_Flow] ====Done====
7348 01:21:32.950345
7349 01:21:32.950396 [DutyScan_Calibration_Flow] k_type=1
7350 01:21:32.950447
7351 01:21:32.950498 ==DQS 0 ==
7352 01:21:32.950550 Final DQS duty delay cell = -4
7353 01:21:32.950602 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7354 01:21:32.950654 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7355 01:21:32.950706 [-4] AVG Duty = 4906%(X100)
7356 01:21:32.950757
7357 01:21:32.950809 ==DQS 1 ==
7358 01:21:32.950860 Final DQS duty delay cell = 0
7359 01:21:32.950911 [0] MAX Duty = 5156%(X100), DQS PI = 2
7360 01:21:32.950963 [0] MIN Duty = 5000%(X100), DQS PI = 20
7361 01:21:32.951014 [0] AVG Duty = 5078%(X100)
7362 01:21:32.951065
7363 01:21:32.951116 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7364 01:21:32.951166
7365 01:21:32.951217 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7366 01:21:32.951268 [DutyScan_Calibration_Flow] ====Done====
7367 01:21:32.951319
7368 01:21:32.951369 [DutyScan_Calibration_Flow] k_type=3
7369 01:21:32.951420
7370 01:21:32.951471 ==DQM 0 ==
7371 01:21:32.951522 Final DQM duty delay cell = 0
7372 01:21:32.951574 [0] MAX Duty = 5124%(X100), DQS PI = 22
7373 01:21:32.951624 [0] MIN Duty = 4875%(X100), DQS PI = 10
7374 01:21:32.951675 [0] AVG Duty = 4999%(X100)
7375 01:21:32.951725
7376 01:21:32.951776 ==DQM 1 ==
7377 01:21:32.951827 Final DQM duty delay cell = 0
7378 01:21:32.951878 [0] MAX Duty = 5000%(X100), DQS PI = 4
7379 01:21:32.951929 [0] MIN Duty = 4813%(X100), DQS PI = 20
7380 01:21:32.951980 [0] AVG Duty = 4906%(X100)
7381 01:21:32.952031
7382 01:21:32.952081 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7383 01:21:32.952132
7384 01:21:32.952182 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7385 01:21:32.952232 [DutyScan_Calibration_Flow] ====Done====
7386 01:21:32.952283
7387 01:21:32.952334 [DutyScan_Calibration_Flow] k_type=2
7388 01:21:32.952384
7389 01:21:32.952435 ==DQ 0 ==
7390 01:21:32.952486 Final DQ duty delay cell = -4
7391 01:21:32.952537 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7392 01:21:32.952588 [-4] MIN Duty = 4876%(X100), DQS PI = 50
7393 01:21:32.952639 [-4] AVG Duty = 4938%(X100)
7394 01:21:32.952689
7395 01:21:32.952740 ==DQ 1 ==
7396 01:21:32.952791 Final DQ duty delay cell = 0
7397 01:21:32.952842 [0] MAX Duty = 5125%(X100), DQS PI = 4
7398 01:21:32.952893 [0] MIN Duty = 5000%(X100), DQS PI = 34
7399 01:21:32.952943 [0] AVG Duty = 5062%(X100)
7400 01:21:32.952994
7401 01:21:32.953045 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7402 01:21:32.953095
7403 01:21:32.953374 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7404 01:21:32.953479 [DutyScan_Calibration_Flow] ====Done====
7405 01:21:32.953533 ==
7406 01:21:32.953585 Dram Type= 6, Freq= 0, CH_1, rank 0
7407 01:21:32.953636 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7408 01:21:32.953688 ==
7409 01:21:32.953740 [Duty_Offset_Calibration]
7410 01:21:32.953791 B0:-1 B1:1 CA:2
7411 01:21:32.953842
7412 01:21:32.953893 [DutyScan_Calibration_Flow] k_type=0
7413 01:21:32.953944
7414 01:21:32.953995 ==CLK 0==
7415 01:21:32.954046 Final CLK duty delay cell = 0
7416 01:21:32.954098 [0] MAX Duty = 5187%(X100), DQS PI = 24
7417 01:21:32.954149 [0] MIN Duty = 4969%(X100), DQS PI = 62
7418 01:21:32.954200 [0] AVG Duty = 5078%(X100)
7419 01:21:32.954251
7420 01:21:32.954301 CH1 CLK Duty spec in!! Max-Min= 218%
7421 01:21:32.954352 [DutyScan_Calibration_Flow] ====Done====
7422 01:21:32.954403
7423 01:21:32.954454 [DutyScan_Calibration_Flow] k_type=1
7424 01:21:32.954505
7425 01:21:32.954555 ==DQS 0 ==
7426 01:21:32.954605 Final DQS duty delay cell = 0
7427 01:21:32.954657 [0] MAX Duty = 5124%(X100), DQS PI = 18
7428 01:21:32.954707 [0] MIN Duty = 4907%(X100), DQS PI = 10
7429 01:21:32.954758 [0] AVG Duty = 5015%(X100)
7430 01:21:32.954808
7431 01:21:32.954858 ==DQS 1 ==
7432 01:21:32.954908 Final DQS duty delay cell = 0
7433 01:21:32.954959 [0] MAX Duty = 5093%(X100), DQS PI = 26
7434 01:21:32.955010 [0] MIN Duty = 4969%(X100), DQS PI = 54
7435 01:21:32.955060 [0] AVG Duty = 5031%(X100)
7436 01:21:32.955111
7437 01:21:32.955161 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7438 01:21:32.955212
7439 01:21:32.955262 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7440 01:21:32.955313 [DutyScan_Calibration_Flow] ====Done====
7441 01:21:32.955364
7442 01:21:32.955415 [DutyScan_Calibration_Flow] k_type=3
7443 01:21:32.955466
7444 01:21:32.955516 ==DQM 0 ==
7445 01:21:32.955567 Final DQM duty delay cell = -4
7446 01:21:32.955618 [-4] MAX Duty = 5031%(X100), DQS PI = 32
7447 01:21:32.955671 [-4] MIN Duty = 4782%(X100), DQS PI = 8
7448 01:21:32.955723 [-4] AVG Duty = 4906%(X100)
7449 01:21:32.955774
7450 01:21:32.955824 ==DQM 1 ==
7451 01:21:32.955875 Final DQM duty delay cell = 0
7452 01:21:32.955926 [0] MAX Duty = 5156%(X100), DQS PI = 6
7453 01:21:32.955977 [0] MIN Duty = 4938%(X100), DQS PI = 36
7454 01:21:32.956027 [0] AVG Duty = 5047%(X100)
7455 01:21:32.956077
7456 01:21:32.956127 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7457 01:21:32.956178
7458 01:21:32.956229 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7459 01:21:32.956279 [DutyScan_Calibration_Flow] ====Done====
7460 01:21:32.956330
7461 01:21:32.956380 [DutyScan_Calibration_Flow] k_type=2
7462 01:21:32.956431
7463 01:21:32.956481 ==DQ 0 ==
7464 01:21:32.956531 Final DQ duty delay cell = 0
7465 01:21:32.956582 [0] MAX Duty = 5156%(X100), DQS PI = 30
7466 01:21:32.956633 [0] MIN Duty = 4906%(X100), DQS PI = 10
7467 01:21:32.956685 [0] AVG Duty = 5031%(X100)
7468 01:21:32.956735
7469 01:21:32.956785 ==DQ 1 ==
7470 01:21:32.956835 Final DQ duty delay cell = 0
7471 01:21:32.956887 [0] MAX Duty = 5156%(X100), DQS PI = 8
7472 01:21:32.956938 [0] MIN Duty = 4969%(X100), DQS PI = 56
7473 01:21:32.956989 [0] AVG Duty = 5062%(X100)
7474 01:21:32.957039
7475 01:21:32.957089 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7476 01:21:32.957140
7477 01:21:32.957191 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7478 01:21:32.957241 [DutyScan_Calibration_Flow] ====Done====
7479 01:21:32.957291 nWR fixed to 30
7480 01:21:32.957371 [ModeRegInit_LP4] CH0 RK0
7481 01:21:32.957451 [ModeRegInit_LP4] CH0 RK1
7482 01:21:32.957502 [ModeRegInit_LP4] CH1 RK0
7483 01:21:32.957552 [ModeRegInit_LP4] CH1 RK1
7484 01:21:32.957602 match AC timing 5
7485 01:21:32.957653 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7486 01:21:32.957704 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7487 01:21:32.957755 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7488 01:21:32.957807 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7489 01:21:32.957859 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7490 01:21:32.957910 [MiockJmeterHQA]
7491 01:21:32.957961
7492 01:21:32.958011 [DramcMiockJmeter] u1RxGatingPI = 0
7493 01:21:32.958062 0 : 4368, 4140
7494 01:21:32.958114 4 : 4255, 4029
7495 01:21:32.958166 8 : 4363, 4137
7496 01:21:32.958217 12 : 4253, 4026
7497 01:21:32.958269 16 : 4252, 4027
7498 01:21:32.958321 20 : 4252, 4027
7499 01:21:32.958373 24 : 4253, 4027
7500 01:21:32.958424 28 : 4254, 4029
7501 01:21:32.958476 32 : 4252, 4027
7502 01:21:32.958527 36 : 4253, 4027
7503 01:21:32.958577 40 : 4252, 4027
7504 01:21:32.958629 44 : 4252, 4027
7505 01:21:32.958680 48 : 4252, 4026
7506 01:21:32.958731 52 : 4255, 4029
7507 01:21:32.958782 56 : 4252, 4027
7508 01:21:32.958834 60 : 4363, 4137
7509 01:21:32.958885 64 : 4363, 4137
7510 01:21:32.958937 68 : 4250, 4026
7511 01:21:32.958988 72 : 4253, 4026
7512 01:21:32.959039 76 : 4250, 4026
7513 01:21:32.959090 80 : 4250, 4027
7514 01:21:32.959142 84 : 4250, 4026
7515 01:21:32.959255 88 : 4253, 4026
7516 01:21:32.959353 92 : 4253, 311
7517 01:21:32.959436 96 : 4253, 0
7518 01:21:32.959540 100 : 4366, 0
7519 01:21:32.959594 104 : 4250, 0
7520 01:21:32.959646 108 : 4250, 0
7521 01:21:32.959698 112 : 4249, 0
7522 01:21:32.959750 116 : 4363, 0
7523 01:21:32.959802 120 : 4250, 0
7524 01:21:32.959853 124 : 4249, 0
7525 01:21:32.959905 128 : 4250, 0
7526 01:21:32.959956 132 : 4252, 0
7527 01:21:32.960008 136 : 4250, 0
7528 01:21:32.960058 140 : 4250, 0
7529 01:21:32.960110 144 : 4250, 0
7530 01:21:32.960161 148 : 4363, 0
7531 01:21:32.960212 152 : 4249, 0
7532 01:21:32.960263 156 : 4250, 0
7533 01:21:32.960315 160 : 4250, 0
7534 01:21:32.960366 164 : 4361, 0
7535 01:21:32.960418 168 : 4360, 0
7536 01:21:32.960469 172 : 4255, 0
7537 01:21:32.960520 176 : 4360, 0
7538 01:21:32.960589 180 : 4250, 0
7539 01:21:32.960643 184 : 4250, 0
7540 01:21:32.960695 188 : 4250, 0
7541 01:21:32.960747 192 : 4250, 0
7542 01:21:32.960798 196 : 4250, 0
7543 01:21:32.960850 200 : 4361, 0
7544 01:21:32.960902 204 : 4250, 0
7545 01:21:32.960954 208 : 4250, 0
7546 01:21:32.961005 212 : 4250, 0
7547 01:21:32.961057 216 : 4361, 0
7548 01:21:32.961108 220 : 4361, 0
7549 01:21:32.961159 224 : 4250, 60
7550 01:21:32.961211 228 : 4361, 2886
7551 01:21:32.961263 232 : 4363, 4140
7552 01:21:32.961314 236 : 4250, 4027
7553 01:21:32.961404 240 : 4252, 4029
7554 01:21:32.961457 244 : 4250, 4027
7555 01:21:32.961509 248 : 4250, 4027
7556 01:21:32.961560 252 : 4250, 4027
7557 01:21:32.961612 256 : 4252, 4029
7558 01:21:32.961663 260 : 4250, 4027
7559 01:21:32.961715 264 : 4250, 4026
7560 01:21:32.961766 268 : 4361, 4137
7561 01:21:32.961817 272 : 4250, 4027
7562 01:21:32.961869 276 : 4360, 4138
7563 01:21:32.961920 280 : 4250, 4027
7564 01:21:32.961971 284 : 4250, 4027
7565 01:21:32.962023 288 : 4250, 4026
7566 01:21:32.962074 292 : 4250, 4027
7567 01:21:32.962126 296 : 4250, 4027
7568 01:21:32.962177 300 : 4250, 4027
7569 01:21:32.962228 304 : 4250, 4027
7570 01:21:32.962280 308 : 4252, 4029
7571 01:21:32.962332 312 : 4250, 4027
7572 01:21:32.962383 316 : 4250, 4027
7573 01:21:32.962435 320 : 4361, 4137
7574 01:21:32.962486 324 : 4250, 4027
7575 01:21:32.962537 328 : 4360, 4138
7576 01:21:32.962588 332 : 4250, 4026
7577 01:21:32.962640 336 : 4250, 3884
7578 01:21:32.962692 340 : 4250, 1995
7579 01:21:32.962743
7580 01:21:32.962793 MIOCK jitter meter ch=0
7581 01:21:32.962845
7582 01:21:32.962896 1T = (340-92) = 248 dly cells
7583 01:21:32.962948 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7584 01:21:32.963000 ==
7585 01:21:32.963051 Dram Type= 6, Freq= 0, CH_0, rank 0
7586 01:21:32.963103 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7587 01:21:32.963154 ==
7588 01:21:32.963205 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7589 01:21:32.963454 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7590 01:21:32.963542 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7591 01:21:32.963595 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7592 01:21:32.963648 [CA 0] Center 43 (13~74) winsize 62
7593 01:21:32.963700 [CA 1] Center 43 (13~74) winsize 62
7594 01:21:32.963751 [CA 2] Center 39 (10~69) winsize 60
7595 01:21:32.963802 [CA 3] Center 39 (9~69) winsize 61
7596 01:21:32.963853 [CA 4] Center 37 (8~66) winsize 59
7597 01:21:32.963904 [CA 5] Center 36 (7~66) winsize 60
7598 01:21:32.963955
7599 01:21:32.964006 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7600 01:21:32.964057
7601 01:21:32.964108 [CATrainingPosCal] consider 1 rank data
7602 01:21:32.964159 u2DelayCellTimex100 = 262/100 ps
7603 01:21:32.964210 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7604 01:21:32.964261 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7605 01:21:32.964312 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7606 01:21:32.964362 CA3 delay=39 (9~69),Diff = 3 PI (11 cell)
7607 01:21:32.964413 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7608 01:21:32.964464 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7609 01:21:32.964544
7610 01:21:32.964595 CA PerBit enable=1, Macro0, CA PI delay=36
7611 01:21:32.964646
7612 01:21:32.964696 [CBTSetCACLKResult] CA Dly = 36
7613 01:21:32.964747 CS Dly: 12 (0~43)
7614 01:21:32.964798 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7615 01:21:32.964849 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7616 01:21:32.964900 ==
7617 01:21:32.964951 Dram Type= 6, Freq= 0, CH_0, rank 1
7618 01:21:32.965002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7619 01:21:32.965053 ==
7620 01:21:32.965106 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7621 01:21:32.965157 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7622 01:21:32.965208 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7623 01:21:32.965259 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7624 01:21:32.965310 [CA 0] Center 42 (12~73) winsize 62
7625 01:21:32.965426 [CA 1] Center 43 (13~73) winsize 61
7626 01:21:32.965479 [CA 2] Center 37 (8~67) winsize 60
7627 01:21:32.965530 [CA 3] Center 37 (8~67) winsize 60
7628 01:21:32.965581 [CA 4] Center 36 (6~66) winsize 61
7629 01:21:32.965632 [CA 5] Center 35 (5~65) winsize 61
7630 01:21:32.965683
7631 01:21:32.965735 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7632 01:21:32.965786
7633 01:21:32.965836 [CATrainingPosCal] consider 2 rank data
7634 01:21:32.965887 u2DelayCellTimex100 = 262/100 ps
7635 01:21:32.965938 CA0 delay=43 (13~73),Diff = 7 PI (26 cell)
7636 01:21:32.965989 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7637 01:21:32.966040 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7638 01:21:32.966091 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7639 01:21:32.966142 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7640 01:21:32.966193 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7641 01:21:32.966253
7642 01:21:32.966307 CA PerBit enable=1, Macro0, CA PI delay=36
7643 01:21:32.966359
7644 01:21:32.966410 [CBTSetCACLKResult] CA Dly = 36
7645 01:21:32.966461 CS Dly: 12 (0~43)
7646 01:21:32.966512 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7647 01:21:32.966563 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7648 01:21:32.966614
7649 01:21:32.966665 ----->DramcWriteLeveling(PI) begin...
7650 01:21:32.966717 ==
7651 01:21:32.966768 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 01:21:32.966819 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7653 01:21:32.966870 ==
7654 01:21:32.966921 Write leveling (Byte 0): 35 => 35
7655 01:21:32.966971 Write leveling (Byte 1): 26 => 26
7656 01:21:32.967022 DramcWriteLeveling(PI) end<-----
7657 01:21:32.967073
7658 01:21:32.967123 ==
7659 01:21:32.967174 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 01:21:32.967226 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 01:21:32.967278 ==
7662 01:21:32.967329 [Gating] SW mode calibration
7663 01:21:32.967381 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7664 01:21:32.967433 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7665 01:21:32.967485 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7666 01:21:32.967536 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7667 01:21:32.967588 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7668 01:21:32.967638 1 4 12 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7669 01:21:32.967690 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7670 01:21:32.967741 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7671 01:21:32.967791 1 4 24 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
7672 01:21:32.967842 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7673 01:21:32.967893 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7674 01:21:32.967944 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7675 01:21:32.967995 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7676 01:21:32.968046 1 5 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
7677 01:21:32.968117 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7678 01:21:32.968169 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7679 01:21:32.968220 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (0 1) (0 0)
7680 01:21:32.968271 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7681 01:21:32.968322 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7682 01:21:32.968372 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7683 01:21:32.968423 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7684 01:21:32.968474 1 6 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7685 01:21:32.968524 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7686 01:21:32.968576 1 6 20 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7687 01:21:32.968627 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7688 01:21:32.968678 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7689 01:21:32.968729 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7690 01:21:32.968780 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7691 01:21:32.968834 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7692 01:21:32.968885 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7693 01:21:32.968936 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7694 01:21:32.969213 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7695 01:21:32.969371 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7696 01:21:32.969512 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 01:21:32.969639 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7698 01:21:32.969764 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7699 01:21:32.969830 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7700 01:21:32.969884 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7701 01:21:32.969937 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7702 01:21:32.969989 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7703 01:21:32.970041 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7704 01:21:32.970093 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7705 01:21:32.970144 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7706 01:21:32.970195 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7707 01:21:32.970246 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7708 01:21:32.970297 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7709 01:21:32.970348 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7710 01:21:32.970400 Total UI for P1: 0, mck2ui 16
7711 01:21:32.970452 best dqsien dly found for B0: ( 1, 9, 10)
7712 01:21:32.970503 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7713 01:21:32.970554 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7714 01:21:32.970605 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7715 01:21:32.970656 Total UI for P1: 0, mck2ui 16
7716 01:21:32.970707 best dqsien dly found for B1: ( 1, 9, 22)
7717 01:21:32.970767 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7718 01:21:32.970863 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7719 01:21:32.970922
7720 01:21:32.970974 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7721 01:21:32.971026 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7722 01:21:32.971077 [Gating] SW calibration Done
7723 01:21:32.971129 ==
7724 01:21:32.971223 Dram Type= 6, Freq= 0, CH_0, rank 0
7725 01:21:32.971277 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7726 01:21:32.971329 ==
7727 01:21:32.971380 RX Vref Scan: 0
7728 01:21:32.971432
7729 01:21:32.971483 RX Vref 0 -> 0, step: 1
7730 01:21:32.971535
7731 01:21:32.971586 RX Delay 0 -> 252, step: 8
7732 01:21:32.971637 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7733 01:21:32.971689 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7734 01:21:32.971741 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7735 01:21:32.971792 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7736 01:21:32.971843 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7737 01:21:32.971894 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7738 01:21:32.971944 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7739 01:21:32.971995 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7740 01:21:32.972045 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7741 01:21:32.972096 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7742 01:21:32.972146 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7743 01:21:32.972197 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7744 01:21:32.972247 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7745 01:21:32.972298 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7746 01:21:32.972348 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7747 01:21:32.972399 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7748 01:21:32.972449 ==
7749 01:21:32.972500 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 01:21:32.972550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 01:21:32.972602 ==
7752 01:21:32.972653 DQS Delay:
7753 01:21:32.972703 DQS0 = 0, DQS1 = 0
7754 01:21:32.972754 DQM Delay:
7755 01:21:32.972805 DQM0 = 134, DQM1 = 127
7756 01:21:32.972855 DQ Delay:
7757 01:21:32.972906 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7758 01:21:32.972957 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =143
7759 01:21:32.973007 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7760 01:21:32.973058 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7761 01:21:32.973108
7762 01:21:32.973158
7763 01:21:32.973208 ==
7764 01:21:32.973259 Dram Type= 6, Freq= 0, CH_0, rank 0
7765 01:21:32.973310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7766 01:21:32.973390 ==
7767 01:21:32.973455
7768 01:21:32.973504
7769 01:21:32.973555 TX Vref Scan disable
7770 01:21:32.973605 == TX Byte 0 ==
7771 01:21:32.973657 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7772 01:21:32.973722 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7773 01:21:32.973776 == TX Byte 1 ==
7774 01:21:32.973827 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7775 01:21:32.973878 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7776 01:21:32.973930 ==
7777 01:21:32.973980 Dram Type= 6, Freq= 0, CH_0, rank 0
7778 01:21:32.974032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7779 01:21:32.974083 ==
7780 01:21:32.974134
7781 01:21:32.974185 TX Vref early break, caculate TX vref
7782 01:21:32.974236 TX Vref=16, minBit 4, minWin=22, winSum=370
7783 01:21:32.974287 TX Vref=18, minBit 0, minWin=23, winSum=376
7784 01:21:32.974373 TX Vref=20, minBit 3, minWin=23, winSum=390
7785 01:21:32.974424 TX Vref=22, minBit 1, minWin=24, winSum=397
7786 01:21:32.974476 TX Vref=24, minBit 0, minWin=24, winSum=402
7787 01:21:32.974526 TX Vref=26, minBit 3, minWin=24, winSum=414
7788 01:21:32.974577 TX Vref=28, minBit 4, minWin=25, winSum=419
7789 01:21:32.974629 TX Vref=30, minBit 7, minWin=24, winSum=410
7790 01:21:32.974680 TX Vref=32, minBit 0, minWin=24, winSum=403
7791 01:21:32.974730 TX Vref=34, minBit 8, minWin=23, winSum=390
7792 01:21:32.974781 [TxChooseVref] Worse bit 4, Min win 25, Win sum 419, Final Vref 28
7793 01:21:32.974833
7794 01:21:32.974884 Final TX Range 0 Vref 28
7795 01:21:32.974935
7796 01:21:32.974985 ==
7797 01:21:32.975036 Dram Type= 6, Freq= 0, CH_0, rank 0
7798 01:21:32.975087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7799 01:21:32.975193 ==
7800 01:21:32.975280
7801 01:21:32.975360
7802 01:21:32.975424 TX Vref Scan disable
7803 01:21:32.975476 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7804 01:21:32.975526 == TX Byte 0 ==
7805 01:21:32.975577 u2DelayCellOfst[0]=14 cells (4 PI)
7806 01:21:32.975629 u2DelayCellOfst[1]=14 cells (4 PI)
7807 01:21:32.975680 u2DelayCellOfst[2]=11 cells (3 PI)
7808 01:21:32.975731 u2DelayCellOfst[3]=11 cells (3 PI)
7809 01:21:32.975782 u2DelayCellOfst[4]=7 cells (2 PI)
7810 01:21:32.975833 u2DelayCellOfst[5]=0 cells (0 PI)
7811 01:21:32.975884 u2DelayCellOfst[6]=18 cells (5 PI)
7812 01:21:32.975935 u2DelayCellOfst[7]=18 cells (5 PI)
7813 01:21:32.976176 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7814 01:21:32.976237 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7815 01:21:32.976290 == TX Byte 1 ==
7816 01:21:32.976341 u2DelayCellOfst[8]=0 cells (0 PI)
7817 01:21:32.976393 u2DelayCellOfst[9]=3 cells (1 PI)
7818 01:21:32.976444 u2DelayCellOfst[10]=7 cells (2 PI)
7819 01:21:32.976495 u2DelayCellOfst[11]=3 cells (1 PI)
7820 01:21:32.976546 u2DelayCellOfst[12]=14 cells (4 PI)
7821 01:21:32.976596 u2DelayCellOfst[13]=14 cells (4 PI)
7822 01:21:32.976648 u2DelayCellOfst[14]=18 cells (5 PI)
7823 01:21:32.976699 u2DelayCellOfst[15]=14 cells (4 PI)
7824 01:21:32.976750 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7825 01:21:32.976801 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7826 01:21:32.976853 DramC Write-DBI on
7827 01:21:32.976904 ==
7828 01:21:32.976955 Dram Type= 6, Freq= 0, CH_0, rank 0
7829 01:21:32.977005 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7830 01:21:32.977056 ==
7831 01:21:32.977107
7832 01:21:32.977215
7833 01:21:32.977295 TX Vref Scan disable
7834 01:21:32.977417 == TX Byte 0 ==
7835 01:21:32.977484 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7836 01:21:32.977536 == TX Byte 1 ==
7837 01:21:32.977590 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7838 01:21:32.977643 DramC Write-DBI off
7839 01:21:32.977694
7840 01:21:32.977746 [DATLAT]
7841 01:21:32.977797 Freq=1600, CH0 RK0
7842 01:21:32.977848
7843 01:21:32.977898 DATLAT Default: 0xf
7844 01:21:32.977949 0, 0xFFFF, sum = 0
7845 01:21:32.978002 1, 0xFFFF, sum = 0
7846 01:21:32.978053 2, 0xFFFF, sum = 0
7847 01:21:32.978105 3, 0xFFFF, sum = 0
7848 01:21:32.978156 4, 0xFFFF, sum = 0
7849 01:21:32.978208 5, 0xFFFF, sum = 0
7850 01:21:32.978259 6, 0xFFFF, sum = 0
7851 01:21:32.978311 7, 0xFFFF, sum = 0
7852 01:21:32.978363 8, 0xFFFF, sum = 0
7853 01:21:32.978415 9, 0xFFFF, sum = 0
7854 01:21:32.978466 10, 0xFFFF, sum = 0
7855 01:21:32.978518 11, 0xFFFF, sum = 0
7856 01:21:32.978570 12, 0xFFFF, sum = 0
7857 01:21:32.978622 13, 0xFFFF, sum = 0
7858 01:21:32.978673 14, 0x0, sum = 1
7859 01:21:32.978725 15, 0x0, sum = 2
7860 01:21:32.978777 16, 0x0, sum = 3
7861 01:21:32.978828 17, 0x0, sum = 4
7862 01:21:32.978880 best_step = 15
7863 01:21:32.978931
7864 01:21:32.978982 ==
7865 01:21:32.979033 Dram Type= 6, Freq= 0, CH_0, rank 0
7866 01:21:32.979084 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7867 01:21:32.979136 ==
7868 01:21:32.979207 RX Vref Scan: 1
7869 01:21:32.979259
7870 01:21:32.979309 Set Vref Range= 24 -> 127
7871 01:21:32.979360
7872 01:21:32.979411 RX Vref 24 -> 127, step: 1
7873 01:21:32.979462
7874 01:21:32.979512 RX Delay 19 -> 252, step: 4
7875 01:21:32.979563
7876 01:21:32.979614 Set Vref, RX VrefLevel [Byte0]: 24
7877 01:21:32.979665 [Byte1]: 24
7878 01:21:32.979717
7879 01:21:32.979767 Set Vref, RX VrefLevel [Byte0]: 25
7880 01:21:32.979818 [Byte1]: 25
7881 01:21:32.979869
7882 01:21:32.979920 Set Vref, RX VrefLevel [Byte0]: 26
7883 01:21:32.979971 [Byte1]: 26
7884 01:21:32.980022
7885 01:21:32.980072 Set Vref, RX VrefLevel [Byte0]: 27
7886 01:21:32.980123 [Byte1]: 27
7887 01:21:32.980174
7888 01:21:32.980225 Set Vref, RX VrefLevel [Byte0]: 28
7889 01:21:32.980275 [Byte1]: 28
7890 01:21:32.980326
7891 01:21:32.980376 Set Vref, RX VrefLevel [Byte0]: 29
7892 01:21:32.980427 [Byte1]: 29
7893 01:21:32.980478
7894 01:21:32.980528 Set Vref, RX VrefLevel [Byte0]: 30
7895 01:21:32.980578 [Byte1]: 30
7896 01:21:32.980629
7897 01:21:32.980680 Set Vref, RX VrefLevel [Byte0]: 31
7898 01:21:32.980731 [Byte1]: 31
7899 01:21:32.980782
7900 01:21:32.980832 Set Vref, RX VrefLevel [Byte0]: 32
7901 01:21:32.980883 [Byte1]: 32
7902 01:21:32.980934
7903 01:21:32.980984 Set Vref, RX VrefLevel [Byte0]: 33
7904 01:21:32.981035 [Byte1]: 33
7905 01:21:32.981085
7906 01:21:32.981135 Set Vref, RX VrefLevel [Byte0]: 34
7907 01:21:32.981221 [Byte1]: 34
7908 01:21:32.981310
7909 01:21:32.981415 Set Vref, RX VrefLevel [Byte0]: 35
7910 01:21:32.981468 [Byte1]: 35
7911 01:21:32.981520
7912 01:21:32.981571 Set Vref, RX VrefLevel [Byte0]: 36
7913 01:21:32.981622 [Byte1]: 36
7914 01:21:32.981673
7915 01:21:32.981723 Set Vref, RX VrefLevel [Byte0]: 37
7916 01:21:32.981774 [Byte1]: 37
7917 01:21:32.981825
7918 01:21:32.981875 Set Vref, RX VrefLevel [Byte0]: 38
7919 01:21:32.981925 [Byte1]: 38
7920 01:21:32.981976
7921 01:21:32.982026 Set Vref, RX VrefLevel [Byte0]: 39
7922 01:21:32.982076 [Byte1]: 39
7923 01:21:32.982127
7924 01:21:32.982178 Set Vref, RX VrefLevel [Byte0]: 40
7925 01:21:32.982228 [Byte1]: 40
7926 01:21:32.982279
7927 01:21:32.982330 Set Vref, RX VrefLevel [Byte0]: 41
7928 01:21:32.982380 [Byte1]: 41
7929 01:21:32.982431
7930 01:21:32.982481 Set Vref, RX VrefLevel [Byte0]: 42
7931 01:21:32.982532 [Byte1]: 42
7932 01:21:32.982583
7933 01:21:32.982634 Set Vref, RX VrefLevel [Byte0]: 43
7934 01:21:32.982685 [Byte1]: 43
7935 01:21:32.982736
7936 01:21:32.982786 Set Vref, RX VrefLevel [Byte0]: 44
7937 01:21:32.982837 [Byte1]: 44
7938 01:21:32.982889
7939 01:21:32.982939 Set Vref, RX VrefLevel [Byte0]: 45
7940 01:21:32.982990 [Byte1]: 45
7941 01:21:32.983040
7942 01:21:32.983091 Set Vref, RX VrefLevel [Byte0]: 46
7943 01:21:32.983145 [Byte1]: 46
7944 01:21:32.983253
7945 01:21:32.983332 Set Vref, RX VrefLevel [Byte0]: 47
7946 01:21:32.983385 [Byte1]: 47
7947 01:21:32.983466
7948 01:21:32.983519 Set Vref, RX VrefLevel [Byte0]: 48
7949 01:21:32.983571 [Byte1]: 48
7950 01:21:32.983622
7951 01:21:32.983673 Set Vref, RX VrefLevel [Byte0]: 49
7952 01:21:32.983724 [Byte1]: 49
7953 01:21:32.983774
7954 01:21:32.983824 Set Vref, RX VrefLevel [Byte0]: 50
7955 01:21:32.983875 [Byte1]: 50
7956 01:21:32.983925
7957 01:21:32.983975 Set Vref, RX VrefLevel [Byte0]: 51
7958 01:21:32.984026 [Byte1]: 51
7959 01:21:32.984077
7960 01:21:32.984127 Set Vref, RX VrefLevel [Byte0]: 52
7961 01:21:32.984178 [Byte1]: 52
7962 01:21:32.984229
7963 01:21:32.984279 Set Vref, RX VrefLevel [Byte0]: 53
7964 01:21:32.984329 [Byte1]: 53
7965 01:21:32.984380
7966 01:21:32.984430 Set Vref, RX VrefLevel [Byte0]: 54
7967 01:21:32.984481 [Byte1]: 54
7968 01:21:32.984531
7969 01:21:32.984582 Set Vref, RX VrefLevel [Byte0]: 55
7970 01:21:32.984633 [Byte1]: 55
7971 01:21:32.984683
7972 01:21:32.984733 Set Vref, RX VrefLevel [Byte0]: 56
7973 01:21:32.984784 [Byte1]: 56
7974 01:21:32.984835
7975 01:21:32.984885 Set Vref, RX VrefLevel [Byte0]: 57
7976 01:21:32.984936 [Byte1]: 57
7977 01:21:32.984986
7978 01:21:32.985036 Set Vref, RX VrefLevel [Byte0]: 58
7979 01:21:32.985087 [Byte1]: 58
7980 01:21:32.985138
7981 01:21:32.985188 Set Vref, RX VrefLevel [Byte0]: 59
7982 01:21:32.985462 [Byte1]: 59
7983 01:21:32.985594
7984 01:21:32.985743 Set Vref, RX VrefLevel [Byte0]: 60
7985 01:21:32.985883 [Byte1]: 60
7986 01:21:32.986007
7987 01:21:32.986133 Set Vref, RX VrefLevel [Byte0]: 61
7988 01:21:32.986256 [Byte1]: 61
7989 01:21:32.986379
7990 01:21:32.986504 Set Vref, RX VrefLevel [Byte0]: 62
7991 01:21:32.986615 [Byte1]: 62
7992 01:21:32.986671
7993 01:21:32.986723 Set Vref, RX VrefLevel [Byte0]: 63
7994 01:21:32.986775 [Byte1]: 63
7995 01:21:32.986827
7996 01:21:32.986877 Set Vref, RX VrefLevel [Byte0]: 64
7997 01:21:32.986929 [Byte1]: 64
7998 01:21:32.986979
7999 01:21:32.987029 Set Vref, RX VrefLevel [Byte0]: 65
8000 01:21:32.987080 [Byte1]: 65
8001 01:21:32.987131
8002 01:21:32.987181 Set Vref, RX VrefLevel [Byte0]: 66
8003 01:21:32.987232 [Byte1]: 66
8004 01:21:32.987282
8005 01:21:32.987333 Set Vref, RX VrefLevel [Byte0]: 67
8006 01:21:32.987384 [Byte1]: 67
8007 01:21:32.987435
8008 01:21:32.987485 Set Vref, RX VrefLevel [Byte0]: 68
8009 01:21:32.987535 [Byte1]: 68
8010 01:21:32.987586
8011 01:21:32.987636 Set Vref, RX VrefLevel [Byte0]: 69
8012 01:21:32.987687 [Byte1]: 69
8013 01:21:32.987737
8014 01:21:32.987787 Set Vref, RX VrefLevel [Byte0]: 70
8015 01:21:32.987838 [Byte1]: 70
8016 01:21:32.987889
8017 01:21:32.987939 Set Vref, RX VrefLevel [Byte0]: 71
8018 01:21:32.987990 [Byte1]: 71
8019 01:21:32.988041
8020 01:21:32.988091 Set Vref, RX VrefLevel [Byte0]: 72
8021 01:21:32.988142 [Byte1]: 72
8022 01:21:33.292985
8023 01:21:33.293571 Set Vref, RX VrefLevel [Byte0]: 73
8024 01:21:33.293953 [Byte1]: 73
8025 01:21:33.294301
8026 01:21:33.294629 Set Vref, RX VrefLevel [Byte0]: 74
8027 01:21:33.294954 [Byte1]: 74
8028 01:21:33.295274
8029 01:21:33.295585 Set Vref, RX VrefLevel [Byte0]: 75
8030 01:21:33.295893 [Byte1]: 75
8031 01:21:33.296201
8032 01:21:33.296506 Set Vref, RX VrefLevel [Byte0]: 76
8033 01:21:33.296810 [Byte1]: 76
8034 01:21:33.297113
8035 01:21:33.297462 Set Vref, RX VrefLevel [Byte0]: 77
8036 01:21:33.297780 [Byte1]: 77
8037 01:21:33.298085
8038 01:21:33.298387 Set Vref, RX VrefLevel [Byte0]: 78
8039 01:21:33.298687 [Byte1]: 78
8040 01:21:33.298987
8041 01:21:33.299283 Set Vref, RX VrefLevel [Byte0]: 79
8042 01:21:33.299583 [Byte1]: 79
8043 01:21:33.299881
8044 01:21:33.300176 Final RX Vref Byte 0 = 69 to rank0
8045 01:21:33.300479 Final RX Vref Byte 1 = 61 to rank0
8046 01:21:33.300779 Final RX Vref Byte 0 = 69 to rank1
8047 01:21:33.301079 Final RX Vref Byte 1 = 61 to rank1==
8048 01:21:33.301434 Dram Type= 6, Freq= 0, CH_0, rank 0
8049 01:21:33.301753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 01:21:33.302060 ==
8051 01:21:33.302365 DQS Delay:
8052 01:21:33.302665 DQS0 = 0, DQS1 = 0
8053 01:21:33.302968 DQM Delay:
8054 01:21:33.303266 DQM0 = 133, DQM1 = 123
8055 01:21:33.303567 DQ Delay:
8056 01:21:33.303864 DQ0 =130, DQ1 =136, DQ2 =130, DQ3 =132
8057 01:21:33.304164 DQ4 =134, DQ5 =120, DQ6 =142, DQ7 =140
8058 01:21:33.304465 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8059 01:21:33.304763 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =130
8060 01:21:33.305062
8061 01:21:33.305413
8062 01:21:33.305774
8063 01:21:33.306077 [DramC_TX_OE_Calibration] TA2
8064 01:21:33.306382 Original DQ_B0 (3 6) =30, OEN = 27
8065 01:21:33.306684 Original DQ_B1 (3 6) =30, OEN = 27
8066 01:21:33.306989 24, 0x0, End_B0=24 End_B1=24
8067 01:21:33.307294 25, 0x0, End_B0=25 End_B1=25
8068 01:21:33.307598 26, 0x0, End_B0=26 End_B1=26
8069 01:21:33.307900 27, 0x0, End_B0=27 End_B1=27
8070 01:21:33.308203 28, 0x0, End_B0=28 End_B1=28
8071 01:21:33.308506 29, 0x0, End_B0=29 End_B1=29
8072 01:21:33.308808 30, 0x0, End_B0=30 End_B1=30
8073 01:21:33.309112 31, 0x5151, End_B0=30 End_B1=30
8074 01:21:33.309479 Byte0 end_step=30 best_step=27
8075 01:21:33.309794 Byte1 end_step=30 best_step=27
8076 01:21:33.310093 Byte0 TX OE(2T, 0.5T) = (3, 3)
8077 01:21:33.310393 Byte1 TX OE(2T, 0.5T) = (3, 3)
8078 01:21:33.310702
8079 01:21:33.311064
8080 01:21:33.311368 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 395 ps
8081 01:21:33.311673 CH0 RK0: MR19=303, MR18=1D0F
8082 01:21:33.311949 CH0_RK0: MR19=0x303, MR18=0x1D0F, DQSOSC=395, MR23=63, INC=23, DEC=15
8083 01:21:33.312226
8084 01:21:33.312494 ----->DramcWriteLeveling(PI) begin...
8085 01:21:33.312810 ==
8086 01:21:33.313098 Dram Type= 6, Freq= 0, CH_0, rank 1
8087 01:21:33.313425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8088 01:21:33.313717 ==
8089 01:21:33.313994 Write leveling (Byte 0): 35 => 35
8090 01:21:33.314269 Write leveling (Byte 1): 27 => 27
8091 01:21:33.314542 DramcWriteLeveling(PI) end<-----
8092 01:21:33.314814
8093 01:21:33.315160 ==
8094 01:21:33.315440 Dram Type= 6, Freq= 0, CH_0, rank 1
8095 01:21:33.315714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8096 01:21:33.315991 ==
8097 01:21:33.316263 [Gating] SW mode calibration
8098 01:21:33.316536 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8099 01:21:33.316814 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8100 01:21:33.317089 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8101 01:21:33.317425 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8102 01:21:33.317835 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8103 01:21:33.318211 1 4 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
8104 01:21:33.318500 1 4 16 | B1->B0 | 2524 3131 | 1 1 | (0 0) (1 1)
8105 01:21:33.318779 1 4 20 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
8106 01:21:33.319089 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8107 01:21:33.319367 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8108 01:21:33.319639 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8109 01:21:33.319916 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8110 01:21:33.320190 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8111 01:21:33.320487 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 1)
8112 01:21:33.320682 1 5 16 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
8113 01:21:33.320909 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
8114 01:21:33.321113 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8115 01:21:33.321309 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8116 01:21:33.321545 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8117 01:21:33.322059 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8118 01:21:33.322289 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8119 01:21:33.322490 1 6 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8120 01:21:33.322688 1 6 16 | B1->B0 | 2424 4040 | 0 0 | (1 1) (0 0)
8121 01:21:33.322913 1 6 20 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
8122 01:21:33.323115 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8123 01:21:33.323313 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8124 01:21:33.323509 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8125 01:21:33.323708 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8126 01:21:33.323903 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8127 01:21:33.324098 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8128 01:21:33.324292 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8129 01:21:33.324486 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8130 01:21:33.324681 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8131 01:21:33.324902 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 01:21:33.325102 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8133 01:21:33.325300 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8134 01:21:33.325539 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8135 01:21:33.325689 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8136 01:21:33.325837 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8137 01:21:33.325987 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8138 01:21:33.326136 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8139 01:21:33.326285 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8140 01:21:33.326430 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8141 01:21:33.326579 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8142 01:21:33.326729 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8143 01:21:33.326950 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8144 01:21:33.327166 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8145 01:21:33.327322 Total UI for P1: 0, mck2ui 16
8146 01:21:33.327477 best dqsien dly found for B0: ( 1, 9, 12)
8147 01:21:33.327629 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8148 01:21:33.327780 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8149 01:21:33.327929 Total UI for P1: 0, mck2ui 16
8150 01:21:33.328081 best dqsien dly found for B1: ( 1, 9, 20)
8151 01:21:33.328231 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8152 01:21:33.328381 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8153 01:21:33.328530
8154 01:21:33.328678 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8155 01:21:33.328828 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8156 01:21:33.328978 [Gating] SW calibration Done
8157 01:21:33.329128 ==
8158 01:21:33.329277 Dram Type= 6, Freq= 0, CH_0, rank 1
8159 01:21:33.329461 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8160 01:21:33.329616 ==
8161 01:21:33.329765 RX Vref Scan: 0
8162 01:21:33.329913
8163 01:21:33.330061 RX Vref 0 -> 0, step: 1
8164 01:21:33.330209
8165 01:21:33.330357 RX Delay 0 -> 252, step: 8
8166 01:21:33.330515 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8167 01:21:33.330634 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8168 01:21:33.330753 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8169 01:21:33.330872 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8170 01:21:33.330990 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8171 01:21:33.331108 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8172 01:21:33.331226 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8173 01:21:33.331344 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8174 01:21:33.331463 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8175 01:21:33.331581 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8176 01:21:33.331699 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8177 01:21:33.331819 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8178 01:21:33.331937 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8179 01:21:33.332055 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8180 01:21:33.332174 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8181 01:21:33.332292 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8182 01:21:33.332410 ==
8183 01:21:33.332528 Dram Type= 6, Freq= 0, CH_0, rank 1
8184 01:21:33.332647 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8185 01:21:33.332767 ==
8186 01:21:33.332885 DQS Delay:
8187 01:21:33.333004 DQS0 = 0, DQS1 = 0
8188 01:21:33.333124 DQM Delay:
8189 01:21:33.333242 DQM0 = 132, DQM1 = 127
8190 01:21:33.333375 DQ Delay:
8191 01:21:33.333498 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8192 01:21:33.333617 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8193 01:21:33.333736 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8194 01:21:33.333854 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8195 01:21:33.333972
8196 01:21:33.334090
8197 01:21:33.334207 ==
8198 01:21:33.334353 Dram Type= 6, Freq= 0, CH_0, rank 1
8199 01:21:33.334478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8200 01:21:33.334598 ==
8201 01:21:33.334716
8202 01:21:33.334848
8203 01:21:33.334972 TX Vref Scan disable
8204 01:21:33.335092 == TX Byte 0 ==
8205 01:21:33.335212 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8206 01:21:33.335332 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8207 01:21:33.335453 == TX Byte 1 ==
8208 01:21:33.335575 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8209 01:21:33.335675 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8210 01:21:33.335774 ==
8211 01:21:33.335874 Dram Type= 6, Freq= 0, CH_0, rank 1
8212 01:21:33.335973 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8213 01:21:33.336074 ==
8214 01:21:33.336172
8215 01:21:33.336270 TX Vref early break, caculate TX vref
8216 01:21:33.336371 TX Vref=16, minBit 7, minWin=22, winSum=375
8217 01:21:33.336472 TX Vref=18, minBit 1, minWin=23, winSum=384
8218 01:21:33.336571 TX Vref=20, minBit 1, minWin=23, winSum=395
8219 01:21:33.336671 TX Vref=22, minBit 1, minWin=24, winSum=402
8220 01:21:33.336770 TX Vref=24, minBit 1, minWin=24, winSum=404
8221 01:21:33.336870 TX Vref=26, minBit 1, minWin=24, winSum=412
8222 01:21:33.336969 TX Vref=28, minBit 0, minWin=24, winSum=406
8223 01:21:33.337069 TX Vref=30, minBit 0, minWin=24, winSum=400
8224 01:21:33.337168 TX Vref=32, minBit 5, minWin=23, winSum=392
8225 01:21:33.337267 TX Vref=34, minBit 2, minWin=23, winSum=382
8226 01:21:33.337609 [TxChooseVref] Worse bit 1, Min win 24, Win sum 412, Final Vref 26
8227 01:21:33.337726
8228 01:21:33.337828 Final TX Range 0 Vref 26
8229 01:21:33.337929
8230 01:21:33.338028 ==
8231 01:21:33.338127 Dram Type= 6, Freq= 0, CH_0, rank 1
8232 01:21:33.338226 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8233 01:21:33.338326 ==
8234 01:21:33.338424
8235 01:21:33.338523
8236 01:21:33.338622 TX Vref Scan disable
8237 01:21:33.338723 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8238 01:21:33.338823 == TX Byte 0 ==
8239 01:21:33.338922 u2DelayCellOfst[0]=14 cells (4 PI)
8240 01:21:33.339022 u2DelayCellOfst[1]=22 cells (6 PI)
8241 01:21:33.339122 u2DelayCellOfst[2]=14 cells (4 PI)
8242 01:21:33.339229 u2DelayCellOfst[3]=18 cells (5 PI)
8243 01:21:33.339348 u2DelayCellOfst[4]=11 cells (3 PI)
8244 01:21:33.339449 u2DelayCellOfst[5]=0 cells (0 PI)
8245 01:21:33.339549 u2DelayCellOfst[6]=18 cells (5 PI)
8246 01:21:33.339648 u2DelayCellOfst[7]=22 cells (6 PI)
8247 01:21:33.339747 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8248 01:21:33.339847 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8249 01:21:33.339946 == TX Byte 1 ==
8250 01:21:33.340044 u2DelayCellOfst[8]=0 cells (0 PI)
8251 01:21:33.340142 u2DelayCellOfst[9]=0 cells (0 PI)
8252 01:21:33.340241 u2DelayCellOfst[10]=7 cells (2 PI)
8253 01:21:33.340340 u2DelayCellOfst[11]=0 cells (0 PI)
8254 01:21:33.340438 u2DelayCellOfst[12]=11 cells (3 PI)
8255 01:21:33.340545 u2DelayCellOfst[13]=11 cells (3 PI)
8256 01:21:33.340631 u2DelayCellOfst[14]=18 cells (5 PI)
8257 01:21:33.340715 u2DelayCellOfst[15]=11 cells (3 PI)
8258 01:21:33.340800 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8259 01:21:33.340885 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8260 01:21:33.340969 DramC Write-DBI on
8261 01:21:33.341054 ==
8262 01:21:33.341140 Dram Type= 6, Freq= 0, CH_0, rank 1
8263 01:21:33.341224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8264 01:21:33.341309 ==
8265 01:21:33.341410
8266 01:21:33.341496
8267 01:21:33.341580 TX Vref Scan disable
8268 01:21:33.341665 == TX Byte 0 ==
8269 01:21:33.341750 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8270 01:21:33.341835 == TX Byte 1 ==
8271 01:21:33.341920 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8272 01:21:33.342005 DramC Write-DBI off
8273 01:21:33.342090
8274 01:21:33.342175 [DATLAT]
8275 01:21:33.342260 Freq=1600, CH0 RK1
8276 01:21:33.342346
8277 01:21:33.342431 DATLAT Default: 0xf
8278 01:21:33.342516 0, 0xFFFF, sum = 0
8279 01:21:33.342603 1, 0xFFFF, sum = 0
8280 01:21:33.342691 2, 0xFFFF, sum = 0
8281 01:21:33.342777 3, 0xFFFF, sum = 0
8282 01:21:33.342863 4, 0xFFFF, sum = 0
8283 01:21:33.342950 5, 0xFFFF, sum = 0
8284 01:21:33.343071 6, 0xFFFF, sum = 0
8285 01:21:33.343184 7, 0xFFFF, sum = 0
8286 01:21:33.343327 8, 0xFFFF, sum = 0
8287 01:21:33.343422 9, 0xFFFF, sum = 0
8288 01:21:33.343510 10, 0xFFFF, sum = 0
8289 01:21:33.343597 11, 0xFFFF, sum = 0
8290 01:21:33.343684 12, 0xFFFF, sum = 0
8291 01:21:33.343771 13, 0xFFFF, sum = 0
8292 01:21:33.343857 14, 0x0, sum = 1
8293 01:21:33.343944 15, 0x0, sum = 2
8294 01:21:33.344030 16, 0x0, sum = 3
8295 01:21:33.344116 17, 0x0, sum = 4
8296 01:21:33.344202 best_step = 15
8297 01:21:33.344287
8298 01:21:33.344372 ==
8299 01:21:33.344457 Dram Type= 6, Freq= 0, CH_0, rank 1
8300 01:21:33.344542 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8301 01:21:33.344629 ==
8302 01:21:33.344714 RX Vref Scan: 0
8303 01:21:33.344799
8304 01:21:33.344885 RX Vref 0 -> 0, step: 1
8305 01:21:33.344970
8306 01:21:33.345055 RX Delay 11 -> 252, step: 4
8307 01:21:33.345141 iDelay=195, Bit 0, Center 126 (75 ~ 178) 104
8308 01:21:33.345227 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
8309 01:21:33.345312 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8310 01:21:33.345411 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8311 01:21:33.345507 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8312 01:21:33.345583 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8313 01:21:33.345657 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8314 01:21:33.345732 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8315 01:21:33.345807 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8316 01:21:33.345881 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8317 01:21:33.345955 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8318 01:21:33.346029 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8319 01:21:33.346103 iDelay=195, Bit 12, Center 130 (79 ~ 182) 104
8320 01:21:33.346178 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8321 01:21:33.346253 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8322 01:21:33.346328 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8323 01:21:33.346402 ==
8324 01:21:33.346476 Dram Type= 6, Freq= 0, CH_0, rank 1
8325 01:21:33.346552 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8326 01:21:33.346627 ==
8327 01:21:33.346702 DQS Delay:
8328 01:21:33.346776 DQS0 = 0, DQS1 = 0
8329 01:21:33.346851 DQM Delay:
8330 01:21:33.346925 DQM0 = 129, DQM1 = 125
8331 01:21:33.347000 DQ Delay:
8332 01:21:33.347074 DQ0 =126, DQ1 =132, DQ2 =124, DQ3 =126
8333 01:21:33.347148 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =140
8334 01:21:33.347223 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8335 01:21:33.347298 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8336 01:21:33.347372
8337 01:21:33.347446
8338 01:21:33.347519
8339 01:21:33.347592 [DramC_TX_OE_Calibration] TA2
8340 01:21:33.347667 Original DQ_B0 (3 6) =30, OEN = 27
8341 01:21:33.347742 Original DQ_B1 (3 6) =30, OEN = 27
8342 01:21:33.347817 24, 0x0, End_B0=24 End_B1=24
8343 01:21:33.347893 25, 0x0, End_B0=25 End_B1=25
8344 01:21:33.347969 26, 0x0, End_B0=26 End_B1=26
8345 01:21:33.348045 27, 0x0, End_B0=27 End_B1=27
8346 01:21:33.348120 28, 0x0, End_B0=28 End_B1=28
8347 01:21:33.348196 29, 0x0, End_B0=29 End_B1=29
8348 01:21:33.348272 30, 0x0, End_B0=30 End_B1=30
8349 01:21:33.348348 31, 0x4141, End_B0=30 End_B1=30
8350 01:21:33.348424 Byte0 end_step=30 best_step=27
8351 01:21:33.348500 Byte1 end_step=30 best_step=27
8352 01:21:33.348574 Byte0 TX OE(2T, 0.5T) = (3, 3)
8353 01:21:33.348648 Byte1 TX OE(2T, 0.5T) = (3, 3)
8354 01:21:33.348723
8355 01:21:33.348797
8356 01:21:33.348871 [DQSOSCAuto] RK1, (LSB)MR18= 0x1bfe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 396 ps
8357 01:21:33.348948 CH0 RK1: MR19=302, MR18=1BFE
8358 01:21:33.349023 CH0_RK1: MR19=0x302, MR18=0x1BFE, DQSOSC=396, MR23=63, INC=23, DEC=15
8359 01:21:33.349099 [RxdqsGatingPostProcess] freq 1600
8360 01:21:33.349173 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8361 01:21:33.349247 best DQS0 dly(2T, 0.5T) = (1, 1)
8362 01:21:33.349321 best DQS1 dly(2T, 0.5T) = (1, 1)
8363 01:21:33.349413 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8364 01:21:33.349488 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8365 01:21:33.349561 best DQS0 dly(2T, 0.5T) = (1, 1)
8366 01:21:33.349634 best DQS1 dly(2T, 0.5T) = (1, 1)
8367 01:21:33.349708 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8368 01:21:33.349781 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8369 01:21:33.350069 Pre-setting of DQS Precalculation
8370 01:21:33.350155 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8371 01:21:33.350232 ==
8372 01:21:33.350306 Dram Type= 6, Freq= 0, CH_1, rank 0
8373 01:21:33.350381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8374 01:21:33.350456 ==
8375 01:21:33.350539 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8376 01:21:33.350606 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8377 01:21:33.350671 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8378 01:21:33.350738 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8379 01:21:33.350805 [CA 0] Center 41 (12~71) winsize 60
8380 01:21:33.350871 [CA 1] Center 42 (12~72) winsize 61
8381 01:21:33.350936 [CA 2] Center 37 (8~66) winsize 59
8382 01:21:33.351002 [CA 3] Center 36 (7~65) winsize 59
8383 01:21:33.351068 [CA 4] Center 37 (8~66) winsize 59
8384 01:21:33.351133 [CA 5] Center 36 (7~66) winsize 60
8385 01:21:33.351198
8386 01:21:33.351264 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8387 01:21:33.351330
8388 01:21:33.351396 [CATrainingPosCal] consider 1 rank data
8389 01:21:33.351461 u2DelayCellTimex100 = 262/100 ps
8390 01:21:33.351527 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8391 01:21:33.351593 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8392 01:21:33.351658 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8393 01:21:33.351724 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8394 01:21:33.351790 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8395 01:21:33.351855 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8396 01:21:33.351921
8397 01:21:33.351986 CA PerBit enable=1, Macro0, CA PI delay=36
8398 01:21:33.352052
8399 01:21:33.352119 [CBTSetCACLKResult] CA Dly = 36
8400 01:21:33.352185 CS Dly: 9 (0~40)
8401 01:21:33.352251 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8402 01:21:33.352317 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8403 01:21:33.352382 ==
8404 01:21:33.352447 Dram Type= 6, Freq= 0, CH_1, rank 1
8405 01:21:33.352513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8406 01:21:33.352580 ==
8407 01:21:33.352645 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8408 01:21:33.352712 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8409 01:21:33.352778 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8410 01:21:33.352843 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8411 01:21:33.352909 [CA 0] Center 42 (13~72) winsize 60
8412 01:21:33.352975 [CA 1] Center 42 (13~72) winsize 60
8413 01:21:33.353041 [CA 2] Center 37 (8~67) winsize 60
8414 01:21:33.353106 [CA 3] Center 37 (8~66) winsize 59
8415 01:21:33.353172 [CA 4] Center 37 (8~67) winsize 60
8416 01:21:33.353237 [CA 5] Center 37 (7~67) winsize 61
8417 01:21:33.353302
8418 01:21:33.353379 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8419 01:21:33.353446
8420 01:21:33.353510 [CATrainingPosCal] consider 2 rank data
8421 01:21:33.353576 u2DelayCellTimex100 = 262/100 ps
8422 01:21:33.353643 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8423 01:21:33.353709 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8424 01:21:33.353775 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8425 01:21:33.353841 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8426 01:21:33.353907 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8427 01:21:33.353972 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8428 01:21:33.354037
8429 01:21:33.354102 CA PerBit enable=1, Macro0, CA PI delay=36
8430 01:21:33.354168
8431 01:21:33.354234 [CBTSetCACLKResult] CA Dly = 36
8432 01:21:33.354299 CS Dly: 10 (0~43)
8433 01:21:33.354365 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8434 01:21:33.354432 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8435 01:21:33.354498
8436 01:21:33.354563 ----->DramcWriteLeveling(PI) begin...
8437 01:21:33.354630 ==
8438 01:21:33.354697 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 01:21:33.354762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 01:21:33.354828 ==
8441 01:21:33.354893 Write leveling (Byte 0): 22 => 22
8442 01:21:33.354959 Write leveling (Byte 1): 26 => 26
8443 01:21:33.355024 DramcWriteLeveling(PI) end<-----
8444 01:21:33.355090
8445 01:21:33.355155 ==
8446 01:21:33.355220 Dram Type= 6, Freq= 0, CH_1, rank 0
8447 01:21:33.355286 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8448 01:21:33.355353 ==
8449 01:21:33.355418 [Gating] SW mode calibration
8450 01:21:33.355496 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8451 01:21:33.355556 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8452 01:21:33.355616 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8453 01:21:33.355677 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8454 01:21:33.355736 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8455 01:21:33.355796 1 4 12 | B1->B0 | 2e2d 3333 | 1 0 | (0 0) (0 0)
8456 01:21:33.355855 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8457 01:21:33.355914 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8458 01:21:33.355973 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8459 01:21:33.356031 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8460 01:21:33.356091 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8461 01:21:33.356150 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8462 01:21:33.356209 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8463 01:21:33.356269 1 5 12 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 1)
8464 01:21:33.356328 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8465 01:21:33.356387 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8466 01:21:33.356446 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8467 01:21:33.356506 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8468 01:21:33.356565 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8469 01:21:33.356624 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8470 01:21:33.356683 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8471 01:21:33.356742 1 6 12 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
8472 01:21:33.356801 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8473 01:21:33.356860 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8474 01:21:33.356919 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8475 01:21:33.356979 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8476 01:21:33.357232 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8477 01:21:33.357300 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8478 01:21:33.357374 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8479 01:21:33.357435 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8480 01:21:33.357495 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8481 01:21:33.357555 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8482 01:21:33.357614 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8483 01:21:33.357674 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8484 01:21:33.357732 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8485 01:21:33.357791 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8486 01:21:33.357850 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8487 01:21:33.357910 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8488 01:21:33.357969 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8489 01:21:33.358029 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8490 01:21:33.358088 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8491 01:21:33.358147 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8492 01:21:33.358207 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8493 01:21:33.358266 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8494 01:21:33.358324 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8495 01:21:33.358384 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8496 01:21:33.358444 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8497 01:21:33.358503 Total UI for P1: 0, mck2ui 16
8498 01:21:33.358563 best dqsien dly found for B0: ( 1, 9, 10)
8499 01:21:33.358623 Total UI for P1: 0, mck2ui 16
8500 01:21:33.358682 best dqsien dly found for B1: ( 1, 9, 12)
8501 01:21:33.358741 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8502 01:21:33.358799 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8503 01:21:33.358858
8504 01:21:33.358917 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8505 01:21:33.358976 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8506 01:21:33.359035 [Gating] SW calibration Done
8507 01:21:33.359094 ==
8508 01:21:33.359153 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 01:21:33.359213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 01:21:33.359273 ==
8511 01:21:33.359331 RX Vref Scan: 0
8512 01:21:33.359390
8513 01:21:33.359447 RX Vref 0 -> 0, step: 1
8514 01:21:33.359506
8515 01:21:33.359564 RX Delay 0 -> 252, step: 8
8516 01:21:33.359623 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8517 01:21:33.359682 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8518 01:21:33.359741 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8519 01:21:33.359800 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8520 01:21:33.359859 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8521 01:21:33.359918 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8522 01:21:33.359977 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8523 01:21:33.360036 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8524 01:21:33.360095 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8525 01:21:33.360153 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8526 01:21:33.360212 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8527 01:21:33.360270 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8528 01:21:33.360329 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8529 01:21:33.360388 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8530 01:21:33.360447 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8531 01:21:33.360517 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8532 01:21:33.360571 ==
8533 01:21:33.360624 Dram Type= 6, Freq= 0, CH_1, rank 0
8534 01:21:33.360678 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8535 01:21:33.360732 ==
8536 01:21:33.360786 DQS Delay:
8537 01:21:33.360839 DQS0 = 0, DQS1 = 0
8538 01:21:33.360894 DQM Delay:
8539 01:21:33.360947 DQM0 = 137, DQM1 = 129
8540 01:21:33.361001 DQ Delay:
8541 01:21:33.361054 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135
8542 01:21:33.361108 DQ4 =135, DQ5 =151, DQ6 =143, DQ7 =135
8543 01:21:33.361161 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8544 01:21:33.361215 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8545 01:21:33.361269
8546 01:21:33.361323
8547 01:21:33.361384 ==
8548 01:21:33.361438 Dram Type= 6, Freq= 0, CH_1, rank 0
8549 01:21:33.361493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8550 01:21:33.361547 ==
8551 01:21:33.361601
8552 01:21:33.361653
8553 01:21:33.361707 TX Vref Scan disable
8554 01:21:33.361761 == TX Byte 0 ==
8555 01:21:33.361814 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8556 01:21:33.361869 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8557 01:21:33.361922 == TX Byte 1 ==
8558 01:21:33.361975 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8559 01:21:33.362029 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8560 01:21:33.362082 ==
8561 01:21:33.362136 Dram Type= 6, Freq= 0, CH_1, rank 0
8562 01:21:33.362190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8563 01:21:33.362244 ==
8564 01:21:33.362297
8565 01:21:33.362351 TX Vref early break, caculate TX vref
8566 01:21:33.362406 TX Vref=16, minBit 0, minWin=21, winSum=373
8567 01:21:33.362460 TX Vref=18, minBit 0, minWin=22, winSum=384
8568 01:21:33.362514 TX Vref=20, minBit 0, minWin=22, winSum=388
8569 01:21:33.362568 TX Vref=22, minBit 0, minWin=23, winSum=400
8570 01:21:33.362622 TX Vref=24, minBit 5, minWin=23, winSum=410
8571 01:21:33.362676 TX Vref=26, minBit 0, minWin=24, winSum=416
8572 01:21:33.362730 TX Vref=28, minBit 0, minWin=24, winSum=413
8573 01:21:33.362784 TX Vref=30, minBit 0, minWin=23, winSum=410
8574 01:21:33.362838 TX Vref=32, minBit 0, minWin=23, winSum=399
8575 01:21:33.362891 TX Vref=34, minBit 0, minWin=23, winSum=394
8576 01:21:33.362945 [TxChooseVref] Worse bit 0, Min win 24, Win sum 416, Final Vref 26
8577 01:21:33.363000
8578 01:21:33.363053 Final TX Range 0 Vref 26
8579 01:21:33.363107
8580 01:21:33.363160 ==
8581 01:21:33.363214 Dram Type= 6, Freq= 0, CH_1, rank 0
8582 01:21:33.363268 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8583 01:21:33.363322 ==
8584 01:21:33.363375
8585 01:21:33.363428
8586 01:21:33.363481 TX Vref Scan disable
8587 01:21:33.363535 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8588 01:21:33.363588 == TX Byte 0 ==
8589 01:21:33.363641 u2DelayCellOfst[0]=18 cells (5 PI)
8590 01:21:33.363696 u2DelayCellOfst[1]=11 cells (3 PI)
8591 01:21:33.363750 u2DelayCellOfst[2]=0 cells (0 PI)
8592 01:21:33.363804 u2DelayCellOfst[3]=7 cells (2 PI)
8593 01:21:33.363857 u2DelayCellOfst[4]=11 cells (3 PI)
8594 01:21:33.363911 u2DelayCellOfst[5]=22 cells (6 PI)
8595 01:21:33.364157 u2DelayCellOfst[6]=22 cells (6 PI)
8596 01:21:33.364219 u2DelayCellOfst[7]=7 cells (2 PI)
8597 01:21:33.364274 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8598 01:21:33.364328 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8599 01:21:33.364383 == TX Byte 1 ==
8600 01:21:33.364436 u2DelayCellOfst[8]=0 cells (0 PI)
8601 01:21:33.364490 u2DelayCellOfst[9]=7 cells (2 PI)
8602 01:21:33.364544 u2DelayCellOfst[10]=11 cells (3 PI)
8603 01:21:33.364597 u2DelayCellOfst[11]=3 cells (1 PI)
8604 01:21:33.364651 u2DelayCellOfst[12]=14 cells (4 PI)
8605 01:21:33.364704 u2DelayCellOfst[13]=14 cells (4 PI)
8606 01:21:33.364757 u2DelayCellOfst[14]=18 cells (5 PI)
8607 01:21:33.364811 u2DelayCellOfst[15]=18 cells (5 PI)
8608 01:21:33.364864 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8609 01:21:33.364918 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8610 01:21:33.364972 DramC Write-DBI on
8611 01:21:33.365026 ==
8612 01:21:33.365079 Dram Type= 6, Freq= 0, CH_1, rank 0
8613 01:21:33.365134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8614 01:21:33.365188 ==
8615 01:21:33.365242
8616 01:21:33.365295
8617 01:21:33.365358 TX Vref Scan disable
8618 01:21:33.365414 == TX Byte 0 ==
8619 01:21:33.365468 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8620 01:21:33.365535 == TX Byte 1 ==
8621 01:21:33.365587 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8622 01:21:33.365639 DramC Write-DBI off
8623 01:21:33.365692
8624 01:21:33.365744 [DATLAT]
8625 01:21:33.365796 Freq=1600, CH1 RK0
8626 01:21:33.365849
8627 01:21:33.365901 DATLAT Default: 0xf
8628 01:21:33.365953 0, 0xFFFF, sum = 0
8629 01:21:33.366007 1, 0xFFFF, sum = 0
8630 01:21:33.366060 2, 0xFFFF, sum = 0
8631 01:21:33.366114 3, 0xFFFF, sum = 0
8632 01:21:33.366168 4, 0xFFFF, sum = 0
8633 01:21:33.366221 5, 0xFFFF, sum = 0
8634 01:21:33.366273 6, 0xFFFF, sum = 0
8635 01:21:33.366327 7, 0xFFFF, sum = 0
8636 01:21:33.366380 8, 0xFFFF, sum = 0
8637 01:21:33.366433 9, 0xFFFF, sum = 0
8638 01:21:33.366486 10, 0xFFFF, sum = 0
8639 01:21:33.366539 11, 0xFFFF, sum = 0
8640 01:21:33.366593 12, 0xFFFF, sum = 0
8641 01:21:33.366646 13, 0xFFFF, sum = 0
8642 01:21:33.366700 14, 0x0, sum = 1
8643 01:21:33.366753 15, 0x0, sum = 2
8644 01:21:33.366806 16, 0x0, sum = 3
8645 01:21:33.366858 17, 0x0, sum = 4
8646 01:21:33.366912 best_step = 15
8647 01:21:33.366964
8648 01:21:33.367017 ==
8649 01:21:33.367069 Dram Type= 6, Freq= 0, CH_1, rank 0
8650 01:21:33.367122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8651 01:21:33.367175 ==
8652 01:21:33.367228 RX Vref Scan: 1
8653 01:21:33.367280
8654 01:21:33.367332 Set Vref Range= 24 -> 127
8655 01:21:33.367384
8656 01:21:33.367436 RX Vref 24 -> 127, step: 1
8657 01:21:33.367489
8658 01:21:33.367541 RX Delay 11 -> 252, step: 4
8659 01:21:33.367593
8660 01:21:33.367646 Set Vref, RX VrefLevel [Byte0]: 24
8661 01:21:33.367698 [Byte1]: 24
8662 01:21:33.367751
8663 01:21:33.367803 Set Vref, RX VrefLevel [Byte0]: 25
8664 01:21:33.367856 [Byte1]: 25
8665 01:21:33.367909
8666 01:21:33.367961 Set Vref, RX VrefLevel [Byte0]: 26
8667 01:21:33.368014 [Byte1]: 26
8668 01:21:33.368066
8669 01:21:33.368118 Set Vref, RX VrefLevel [Byte0]: 27
8670 01:21:33.368171 [Byte1]: 27
8671 01:21:33.368223
8672 01:21:33.368275 Set Vref, RX VrefLevel [Byte0]: 28
8673 01:21:33.368328 [Byte1]: 28
8674 01:21:33.368380
8675 01:21:33.368433 Set Vref, RX VrefLevel [Byte0]: 29
8676 01:21:33.368486 [Byte1]: 29
8677 01:21:33.368539
8678 01:21:33.368590 Set Vref, RX VrefLevel [Byte0]: 30
8679 01:21:33.368643 [Byte1]: 30
8680 01:21:33.368696
8681 01:21:33.368748 Set Vref, RX VrefLevel [Byte0]: 31
8682 01:21:33.368800 [Byte1]: 31
8683 01:21:33.368852
8684 01:21:33.368904 Set Vref, RX VrefLevel [Byte0]: 32
8685 01:21:33.368956 [Byte1]: 32
8686 01:21:33.369008
8687 01:21:33.369060 Set Vref, RX VrefLevel [Byte0]: 33
8688 01:21:33.369112 [Byte1]: 33
8689 01:21:33.369165
8690 01:21:33.369217 Set Vref, RX VrefLevel [Byte0]: 34
8691 01:21:33.369269 [Byte1]: 34
8692 01:21:33.369322
8693 01:21:33.369384 Set Vref, RX VrefLevel [Byte0]: 35
8694 01:21:33.369438 [Byte1]: 35
8695 01:21:33.369490
8696 01:21:33.369542 Set Vref, RX VrefLevel [Byte0]: 36
8697 01:21:33.369595 [Byte1]: 36
8698 01:21:33.369648
8699 01:21:33.369700 Set Vref, RX VrefLevel [Byte0]: 37
8700 01:21:33.369752 [Byte1]: 37
8701 01:21:33.369804
8702 01:21:33.369856 Set Vref, RX VrefLevel [Byte0]: 38
8703 01:21:33.369908 [Byte1]: 38
8704 01:21:33.369960
8705 01:21:33.370012 Set Vref, RX VrefLevel [Byte0]: 39
8706 01:21:33.370064 [Byte1]: 39
8707 01:21:33.370117
8708 01:21:33.370168 Set Vref, RX VrefLevel [Byte0]: 40
8709 01:21:33.370220 [Byte1]: 40
8710 01:21:33.370273
8711 01:21:33.370325 Set Vref, RX VrefLevel [Byte0]: 41
8712 01:21:33.370377 [Byte1]: 41
8713 01:21:33.370429
8714 01:21:33.370481 Set Vref, RX VrefLevel [Byte0]: 42
8715 01:21:33.370534 [Byte1]: 42
8716 01:21:33.370586
8717 01:21:33.370638 Set Vref, RX VrefLevel [Byte0]: 43
8718 01:21:33.370691 [Byte1]: 43
8719 01:21:33.370743
8720 01:21:33.370795 Set Vref, RX VrefLevel [Byte0]: 44
8721 01:21:33.370847 [Byte1]: 44
8722 01:21:33.370899
8723 01:21:33.370951 Set Vref, RX VrefLevel [Byte0]: 45
8724 01:21:33.371003 [Byte1]: 45
8725 01:21:33.371055
8726 01:21:33.371107 Set Vref, RX VrefLevel [Byte0]: 46
8727 01:21:33.371159 [Byte1]: 46
8728 01:21:33.371211
8729 01:21:33.371262 Set Vref, RX VrefLevel [Byte0]: 47
8730 01:21:33.371314 [Byte1]: 47
8731 01:21:33.371366
8732 01:21:33.371419 Set Vref, RX VrefLevel [Byte0]: 48
8733 01:21:33.371471 [Byte1]: 48
8734 01:21:33.371523
8735 01:21:33.371575 Set Vref, RX VrefLevel [Byte0]: 49
8736 01:21:33.371628 [Byte1]: 49
8737 01:21:33.371681
8738 01:21:33.371733 Set Vref, RX VrefLevel [Byte0]: 50
8739 01:21:33.371785 [Byte1]: 50
8740 01:21:33.371838
8741 01:21:33.371889 Set Vref, RX VrefLevel [Byte0]: 51
8742 01:21:33.371942 [Byte1]: 51
8743 01:21:33.371993
8744 01:21:33.372045 Set Vref, RX VrefLevel [Byte0]: 52
8745 01:21:33.372098 [Byte1]: 52
8746 01:21:33.372150
8747 01:21:33.372202 Set Vref, RX VrefLevel [Byte0]: 53
8748 01:21:33.372254 [Byte1]: 53
8749 01:21:33.372306
8750 01:21:33.372358 Set Vref, RX VrefLevel [Byte0]: 54
8751 01:21:33.372410 [Byte1]: 54
8752 01:21:33.372463
8753 01:21:33.372515 Set Vref, RX VrefLevel [Byte0]: 55
8754 01:21:33.372567 [Byte1]: 55
8755 01:21:33.372619
8756 01:21:33.372671 Set Vref, RX VrefLevel [Byte0]: 56
8757 01:21:33.372723 [Byte1]: 56
8758 01:21:33.372776
8759 01:21:33.372828 Set Vref, RX VrefLevel [Byte0]: 57
8760 01:21:33.372881 [Byte1]: 57
8761 01:21:33.372934
8762 01:21:33.373175 Set Vref, RX VrefLevel [Byte0]: 58
8763 01:21:33.373236 [Byte1]: 58
8764 01:21:33.373290
8765 01:21:33.373354 Set Vref, RX VrefLevel [Byte0]: 59
8766 01:21:33.373409 [Byte1]: 59
8767 01:21:33.373462
8768 01:21:33.373513 Set Vref, RX VrefLevel [Byte0]: 60
8769 01:21:33.373566 [Byte1]: 60
8770 01:21:33.373618
8771 01:21:33.373670 Set Vref, RX VrefLevel [Byte0]: 61
8772 01:21:33.373723 [Byte1]: 61
8773 01:21:33.373774
8774 01:21:33.373826 Set Vref, RX VrefLevel [Byte0]: 62
8775 01:21:33.373879 [Byte1]: 62
8776 01:21:33.373931
8777 01:21:33.373983 Set Vref, RX VrefLevel [Byte0]: 63
8778 01:21:33.374035 [Byte1]: 63
8779 01:21:33.374088
8780 01:21:33.374140 Set Vref, RX VrefLevel [Byte0]: 64
8781 01:21:33.374192 [Byte1]: 64
8782 01:21:33.374243
8783 01:21:33.374296 Set Vref, RX VrefLevel [Byte0]: 65
8784 01:21:33.374348 [Byte1]: 65
8785 01:21:33.374400
8786 01:21:33.374452 Set Vref, RX VrefLevel [Byte0]: 66
8787 01:21:33.374504 [Byte1]: 66
8788 01:21:33.374557
8789 01:21:33.374609 Set Vref, RX VrefLevel [Byte0]: 67
8790 01:21:33.374661 [Byte1]: 67
8791 01:21:33.374713
8792 01:21:33.374765 Set Vref, RX VrefLevel [Byte0]: 68
8793 01:21:33.374818 [Byte1]: 68
8794 01:21:33.374870
8795 01:21:33.374922 Set Vref, RX VrefLevel [Byte0]: 69
8796 01:21:33.374974 [Byte1]: 69
8797 01:21:33.375026
8798 01:21:33.375078 Set Vref, RX VrefLevel [Byte0]: 70
8799 01:21:33.375130 [Byte1]: 70
8800 01:21:33.375182
8801 01:21:33.375235 Set Vref, RX VrefLevel [Byte0]: 71
8802 01:21:33.375288 [Byte1]: 71
8803 01:21:33.375340
8804 01:21:33.375392 Set Vref, RX VrefLevel [Byte0]: 72
8805 01:21:33.375445 [Byte1]: 72
8806 01:21:33.375496
8807 01:21:33.375549 Final RX Vref Byte 0 = 52 to rank0
8808 01:21:33.375601 Final RX Vref Byte 1 = 58 to rank0
8809 01:21:33.375654 Final RX Vref Byte 0 = 52 to rank1
8810 01:21:33.375706 Final RX Vref Byte 1 = 58 to rank1==
8811 01:21:33.375759 Dram Type= 6, Freq= 0, CH_1, rank 0
8812 01:21:33.375812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 01:21:33.375865 ==
8814 01:21:33.375918 DQS Delay:
8815 01:21:33.375971 DQS0 = 0, DQS1 = 0
8816 01:21:33.376023 DQM Delay:
8817 01:21:33.376075 DQM0 = 133, DQM1 = 127
8818 01:21:33.376128 DQ Delay:
8819 01:21:33.376180 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =132
8820 01:21:33.376232 DQ4 =130, DQ5 =146, DQ6 =142, DQ7 =128
8821 01:21:33.376284 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =116
8822 01:21:33.376337 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8823 01:21:33.376389
8824 01:21:33.376441
8825 01:21:33.376493
8826 01:21:33.376545 [DramC_TX_OE_Calibration] TA2
8827 01:21:33.376597 Original DQ_B0 (3 6) =30, OEN = 27
8828 01:21:33.376650 Original DQ_B1 (3 6) =30, OEN = 27
8829 01:21:33.376703 24, 0x0, End_B0=24 End_B1=24
8830 01:21:33.376757 25, 0x0, End_B0=25 End_B1=25
8831 01:21:33.376810 26, 0x0, End_B0=26 End_B1=26
8832 01:21:33.376863 27, 0x0, End_B0=27 End_B1=27
8833 01:21:33.376917 28, 0x0, End_B0=28 End_B1=28
8834 01:21:33.376970 29, 0x0, End_B0=29 End_B1=29
8835 01:21:33.377023 30, 0x0, End_B0=30 End_B1=30
8836 01:21:33.377076 31, 0x4545, End_B0=30 End_B1=30
8837 01:21:33.377129 Byte0 end_step=30 best_step=27
8838 01:21:33.377181 Byte1 end_step=30 best_step=27
8839 01:21:33.377234 Byte0 TX OE(2T, 0.5T) = (3, 3)
8840 01:21:33.377287 Byte1 TX OE(2T, 0.5T) = (3, 3)
8841 01:21:33.377345
8842 01:21:33.377399
8843 01:21:33.377452 [DQSOSCAuto] RK0, (LSB)MR18= 0x180e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8844 01:21:33.377507 CH1 RK0: MR19=303, MR18=180E
8845 01:21:33.377560 CH1_RK0: MR19=0x303, MR18=0x180E, DQSOSC=397, MR23=63, INC=23, DEC=15
8846 01:21:33.377613
8847 01:21:33.377666 ----->DramcWriteLeveling(PI) begin...
8848 01:21:33.377720 ==
8849 01:21:33.377772 Dram Type= 6, Freq= 0, CH_1, rank 1
8850 01:21:33.377824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8851 01:21:33.377878 ==
8852 01:21:33.377930 Write leveling (Byte 0): 24 => 24
8853 01:21:33.377983 Write leveling (Byte 1): 26 => 26
8854 01:21:33.378035 DramcWriteLeveling(PI) end<-----
8855 01:21:33.378088
8856 01:21:33.378140 ==
8857 01:21:33.378193 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 01:21:33.378246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 01:21:33.378298 ==
8860 01:21:33.378350 [Gating] SW mode calibration
8861 01:21:33.378403 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8862 01:21:33.378456 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8863 01:21:33.378509 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8864 01:21:33.378562 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8865 01:21:33.378616 1 4 8 | B1->B0 | 2524 2323 | 1 0 | (0 0) (0 0)
8866 01:21:33.378669 1 4 12 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
8867 01:21:33.378721 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8868 01:21:33.378774 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8869 01:21:33.378827 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8870 01:21:33.378879 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8871 01:21:33.378931 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8872 01:21:33.378984 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8873 01:21:33.379036 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8874 01:21:33.379089 1 5 12 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 1)
8875 01:21:33.379142 1 5 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
8876 01:21:33.379194 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8877 01:21:33.379247 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8878 01:21:33.379300 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8879 01:21:33.379352 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8880 01:21:33.379406 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8881 01:21:33.379458 1 6 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8882 01:21:33.379511 1 6 12 | B1->B0 | 4545 2323 | 0 0 | (0 0) (0 0)
8883 01:21:33.379564 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8884 01:21:33.379616 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8885 01:21:33.379668 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8886 01:21:33.379721 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8887 01:21:33.379774 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8888 01:21:33.380017 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8889 01:21:33.380081 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8890 01:21:33.380135 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8891 01:21:33.380189 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8892 01:21:33.380242 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8893 01:21:33.380295 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8894 01:21:33.380347 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8895 01:21:33.380400 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8896 01:21:33.380452 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8897 01:21:33.380505 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8898 01:21:33.380558 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8899 01:21:33.380610 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8900 01:21:33.380662 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8901 01:21:33.380715 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8902 01:21:33.380768 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8903 01:21:33.380820 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8904 01:21:33.380873 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8905 01:21:33.380926 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8906 01:21:33.380979 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8907 01:21:33.381032 Total UI for P1: 0, mck2ui 16
8908 01:21:33.381084 best dqsien dly found for B1: ( 1, 9, 8)
8909 01:21:33.381137 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8910 01:21:33.381190 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8911 01:21:33.381242 Total UI for P1: 0, mck2ui 16
8912 01:21:33.381295 best dqsien dly found for B0: ( 1, 9, 14)
8913 01:21:33.381361 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8914 01:21:33.381417 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8915 01:21:33.381471
8916 01:21:33.381523 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8917 01:21:33.381577 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8918 01:21:33.381630 [Gating] SW calibration Done
8919 01:21:33.381683 ==
8920 01:21:33.381735 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 01:21:33.381788 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 01:21:33.381841 ==
8923 01:21:33.381893 RX Vref Scan: 0
8924 01:21:33.381946
8925 01:21:33.381998 RX Vref 0 -> 0, step: 1
8926 01:21:33.382051
8927 01:21:33.382103 RX Delay 0 -> 252, step: 8
8928 01:21:33.382155 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8929 01:21:33.382208 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8930 01:21:33.382261 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8931 01:21:33.382314 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8932 01:21:33.382366 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8933 01:21:33.382418 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8934 01:21:33.382470 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8935 01:21:33.382522 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8936 01:21:33.382575 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8937 01:21:33.382627 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8938 01:21:33.382679 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8939 01:21:33.382732 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8940 01:21:33.382784 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8941 01:21:33.382836 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8942 01:21:33.382888 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8943 01:21:33.382941 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8944 01:21:33.382993 ==
8945 01:21:33.383045 Dram Type= 6, Freq= 0, CH_1, rank 1
8946 01:21:33.383098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8947 01:21:33.383151 ==
8948 01:21:33.383203 DQS Delay:
8949 01:21:33.383256 DQS0 = 0, DQS1 = 0
8950 01:21:33.383307 DQM Delay:
8951 01:21:33.383359 DQM0 = 137, DQM1 = 129
8952 01:21:33.383412 DQ Delay:
8953 01:21:33.383465 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8954 01:21:33.383518 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8955 01:21:33.383570 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8956 01:21:33.383623 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8957 01:21:33.383675
8958 01:21:33.383727
8959 01:21:33.383779 ==
8960 01:21:33.383831 Dram Type= 6, Freq= 0, CH_1, rank 1
8961 01:21:33.383883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8962 01:21:33.383936 ==
8963 01:21:33.383988
8964 01:21:33.384040
8965 01:21:33.384092 TX Vref Scan disable
8966 01:21:33.384144 == TX Byte 0 ==
8967 01:21:33.384197 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8968 01:21:33.384250 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8969 01:21:33.384303 == TX Byte 1 ==
8970 01:21:33.384355 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8971 01:21:33.384408 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8972 01:21:33.384460 ==
8973 01:21:33.384513 Dram Type= 6, Freq= 0, CH_1, rank 1
8974 01:21:33.384565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8975 01:21:33.384619 ==
8976 01:21:33.384671
8977 01:21:33.384723 TX Vref early break, caculate TX vref
8978 01:21:33.384776 TX Vref=16, minBit 0, minWin=23, winSum=387
8979 01:21:33.384829 TX Vref=18, minBit 1, minWin=22, winSum=392
8980 01:21:33.384881 TX Vref=20, minBit 0, minWin=24, winSum=404
8981 01:21:33.384934 TX Vref=22, minBit 1, minWin=25, winSum=414
8982 01:21:33.384987 TX Vref=24, minBit 1, minWin=24, winSum=420
8983 01:21:33.385040 TX Vref=26, minBit 0, minWin=25, winSum=422
8984 01:21:33.385093 TX Vref=28, minBit 0, minWin=24, winSum=424
8985 01:21:33.385145 TX Vref=30, minBit 1, minWin=24, winSum=416
8986 01:21:33.385198 TX Vref=32, minBit 0, minWin=24, winSum=407
8987 01:21:33.385251 TX Vref=34, minBit 1, minWin=23, winSum=398
8988 01:21:33.385304 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 26
8989 01:21:33.385372
8990 01:21:33.385427 Final TX Range 0 Vref 26
8991 01:21:33.385480
8992 01:21:33.385533 ==
8993 01:21:33.385586 Dram Type= 6, Freq= 0, CH_1, rank 1
8994 01:21:33.590581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8995 01:21:33.591117 ==
8996 01:21:33.591488
8997 01:21:33.591832
8998 01:21:33.592161 TX Vref Scan disable
8999 01:21:33.592488 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
9000 01:21:33.592807 == TX Byte 0 ==
9001 01:21:33.593121 u2DelayCellOfst[0]=18 cells (5 PI)
9002 01:21:33.593511 u2DelayCellOfst[1]=11 cells (3 PI)
9003 01:21:33.593840 u2DelayCellOfst[2]=0 cells (0 PI)
9004 01:21:33.594145 u2DelayCellOfst[3]=7 cells (2 PI)
9005 01:21:33.594446 u2DelayCellOfst[4]=11 cells (3 PI)
9006 01:21:33.594749 u2DelayCellOfst[5]=22 cells (6 PI)
9007 01:21:33.595443 u2DelayCellOfst[6]=22 cells (6 PI)
9008 01:21:33.595791 u2DelayCellOfst[7]=7 cells (2 PI)
9009 01:21:33.596100 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9010 01:21:33.596411 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9011 01:21:33.596717 == TX Byte 1 ==
9012 01:21:33.597016 u2DelayCellOfst[8]=0 cells (0 PI)
9013 01:21:33.597316 u2DelayCellOfst[9]=7 cells (2 PI)
9014 01:21:33.597708 u2DelayCellOfst[10]=11 cells (3 PI)
9015 01:21:33.598018 u2DelayCellOfst[11]=7 cells (2 PI)
9016 01:21:33.598324 u2DelayCellOfst[12]=14 cells (4 PI)
9017 01:21:33.598626 u2DelayCellOfst[13]=18 cells (5 PI)
9018 01:21:33.598924 u2DelayCellOfst[14]=22 cells (6 PI)
9019 01:21:33.599222 u2DelayCellOfst[15]=18 cells (5 PI)
9020 01:21:33.599520 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
9021 01:21:33.599821 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9022 01:21:33.600118 DramC Write-DBI on
9023 01:21:33.600416 ==
9024 01:21:33.600717 Dram Type= 6, Freq= 0, CH_1, rank 1
9025 01:21:33.601017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9026 01:21:33.601317 ==
9027 01:21:33.601704
9028 01:21:33.602004
9029 01:21:33.602302 TX Vref Scan disable
9030 01:21:33.602601 == TX Byte 0 ==
9031 01:21:33.602899 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9032 01:21:33.603200 == TX Byte 1 ==
9033 01:21:33.603501 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9034 01:21:33.603800 DramC Write-DBI off
9035 01:21:33.604097
9036 01:21:33.604394 [DATLAT]
9037 01:21:33.604692 Freq=1600, CH1 RK1
9038 01:21:33.604990
9039 01:21:33.605284 DATLAT Default: 0xf
9040 01:21:33.605671 0, 0xFFFF, sum = 0
9041 01:21:33.606035 1, 0xFFFF, sum = 0
9042 01:21:33.606383 2, 0xFFFF, sum = 0
9043 01:21:33.606687 3, 0xFFFF, sum = 0
9044 01:21:33.606992 4, 0xFFFF, sum = 0
9045 01:21:33.607294 5, 0xFFFF, sum = 0
9046 01:21:33.607598 6, 0xFFFF, sum = 0
9047 01:21:33.607899 7, 0xFFFF, sum = 0
9048 01:21:33.608200 8, 0xFFFF, sum = 0
9049 01:21:33.608499 9, 0xFFFF, sum = 0
9050 01:21:33.608801 10, 0xFFFF, sum = 0
9051 01:21:33.609103 11, 0xFFFF, sum = 0
9052 01:21:33.609477 12, 0xFFFF, sum = 0
9053 01:21:33.609796 13, 0xFFFF, sum = 0
9054 01:21:33.610098 14, 0x0, sum = 1
9055 01:21:33.610402 15, 0x0, sum = 2
9056 01:21:33.610706 16, 0x0, sum = 3
9057 01:21:33.611010 17, 0x0, sum = 4
9058 01:21:33.611329 best_step = 15
9059 01:21:33.611684
9060 01:21:33.611989 ==
9061 01:21:33.612291 Dram Type= 6, Freq= 0, CH_1, rank 1
9062 01:21:33.612592 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9063 01:21:33.612895 ==
9064 01:21:33.613191 RX Vref Scan: 0
9065 01:21:33.613581
9066 01:21:33.613861 RX Vref 0 -> 0, step: 1
9067 01:21:33.614136
9068 01:21:33.614410 RX Delay 11 -> 252, step: 4
9069 01:21:33.614684 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9070 01:21:33.614958 iDelay=203, Bit 1, Center 126 (75 ~ 178) 104
9071 01:21:33.615230 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9072 01:21:33.615511 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9073 01:21:33.615707 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9074 01:21:33.615902 iDelay=203, Bit 5, Center 144 (95 ~ 194) 100
9075 01:21:33.616097 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9076 01:21:33.616293 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9077 01:21:33.616488 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9078 01:21:33.616684 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9079 01:21:33.616877 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9080 01:21:33.617072 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9081 01:21:33.617268 iDelay=203, Bit 12, Center 136 (79 ~ 194) 116
9082 01:21:33.617519 iDelay=203, Bit 13, Center 136 (83 ~ 190) 108
9083 01:21:33.617718 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9084 01:21:33.617913 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9085 01:21:33.618146 ==
9086 01:21:33.618356 Dram Type= 6, Freq= 0, CH_1, rank 1
9087 01:21:33.618555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9088 01:21:33.618822 ==
9089 01:21:33.619028 DQS Delay:
9090 01:21:33.619227 DQS0 = 0, DQS1 = 0
9091 01:21:33.619425 DQM Delay:
9092 01:21:33.619620 DQM0 = 133, DQM1 = 127
9093 01:21:33.619816 DQ Delay:
9094 01:21:33.620013 DQ0 =138, DQ1 =126, DQ2 =122, DQ3 =130
9095 01:21:33.620207 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9096 01:21:33.620403 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =118
9097 01:21:33.620586 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
9098 01:21:33.620733
9099 01:21:33.620877
9100 01:21:33.621022
9101 01:21:33.621171 [DramC_TX_OE_Calibration] TA2
9102 01:21:33.621320 Original DQ_B0 (3 6) =30, OEN = 27
9103 01:21:33.621493 Original DQ_B1 (3 6) =30, OEN = 27
9104 01:21:33.621643 24, 0x0, End_B0=24 End_B1=24
9105 01:21:33.621795 25, 0x0, End_B0=25 End_B1=25
9106 01:21:33.621946 26, 0x0, End_B0=26 End_B1=26
9107 01:21:33.622098 27, 0x0, End_B0=27 End_B1=27
9108 01:21:33.622248 28, 0x0, End_B0=28 End_B1=28
9109 01:21:33.622397 29, 0x0, End_B0=29 End_B1=29
9110 01:21:33.622547 30, 0x0, End_B0=30 End_B1=30
9111 01:21:33.622726 31, 0x4545, End_B0=30 End_B1=30
9112 01:21:33.622882 Byte0 end_step=30 best_step=27
9113 01:21:33.623040 Byte1 end_step=30 best_step=27
9114 01:21:33.623201 Byte0 TX OE(2T, 0.5T) = (3, 3)
9115 01:21:33.623350 Byte1 TX OE(2T, 0.5T) = (3, 3)
9116 01:21:33.623497
9117 01:21:33.623645
9118 01:21:33.623793 [DQSOSCAuto] RK1, (LSB)MR18= 0x906, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
9119 01:21:33.623959 CH1 RK1: MR19=303, MR18=906
9120 01:21:33.624115 CH1_RK1: MR19=0x303, MR18=0x906, DQSOSC=405, MR23=63, INC=22, DEC=15
9121 01:21:33.624266 [RxdqsGatingPostProcess] freq 1600
9122 01:21:33.624415 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9123 01:21:33.624587 best DQS0 dly(2T, 0.5T) = (1, 1)
9124 01:21:33.624740 best DQS1 dly(2T, 0.5T) = (1, 1)
9125 01:21:33.624889 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9126 01:21:33.625050 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9127 01:21:33.625207 best DQS0 dly(2T, 0.5T) = (1, 1)
9128 01:21:33.625378 best DQS1 dly(2T, 0.5T) = (1, 1)
9129 01:21:33.625537 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9130 01:21:33.625677 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9131 01:21:33.625799 Pre-setting of DQS Precalculation
9132 01:21:33.625919 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9133 01:21:33.626057 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9134 01:21:33.626182 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9135 01:21:33.626302
9136 01:21:33.626433
9137 01:21:33.626558 [Calibration Summary] 3200 Mbps
9138 01:21:33.626640 CH 0, Rank 0
9139 01:21:33.626706 SW Impedance : PASS
9140 01:21:33.626758 DUTY Scan : NO K
9141 01:21:33.626827 ZQ Calibration : PASS
9142 01:21:33.626913 Jitter Meter : NO K
9143 01:21:33.626968 CBT Training : PASS
9144 01:21:33.627021 Write leveling : PASS
9145 01:21:33.627074 RX DQS gating : PASS
9146 01:21:33.627325 RX DQ/DQS(RDDQC) : PASS
9147 01:21:33.627398 TX DQ/DQS : PASS
9148 01:21:33.627452 RX DATLAT : PASS
9149 01:21:33.627506 RX DQ/DQS(Engine): PASS
9150 01:21:33.627558 TX OE : PASS
9151 01:21:33.627611 All Pass.
9152 01:21:33.627664
9153 01:21:33.627732 CH 0, Rank 1
9154 01:21:33.627820 SW Impedance : PASS
9155 01:21:33.627874 DUTY Scan : NO K
9156 01:21:33.627928 ZQ Calibration : PASS
9157 01:21:33.627994 Jitter Meter : NO K
9158 01:21:33.628063 CBT Training : PASS
9159 01:21:33.628152 Write leveling : PASS
9160 01:21:33.628205 RX DQS gating : PASS
9161 01:21:33.628259 RX DQ/DQS(RDDQC) : PASS
9162 01:21:33.628315 TX DQ/DQS : PASS
9163 01:21:33.628368 RX DATLAT : PASS
9164 01:21:33.628421 RX DQ/DQS(Engine): PASS
9165 01:21:33.628483 TX OE : PASS
9166 01:21:33.628541 All Pass.
9167 01:21:33.628598
9168 01:21:33.628652 CH 1, Rank 0
9169 01:21:33.628705 SW Impedance : PASS
9170 01:21:33.628790 DUTY Scan : NO K
9171 01:21:33.628845 ZQ Calibration : PASS
9172 01:21:33.628899 Jitter Meter : NO K
9173 01:21:33.628952 CBT Training : PASS
9174 01:21:33.629018 Write leveling : PASS
9175 01:21:33.629070 RX DQS gating : PASS
9176 01:21:33.629123 RX DQ/DQS(RDDQC) : PASS
9177 01:21:33.629176 TX DQ/DQS : PASS
9178 01:21:33.629228 RX DATLAT : PASS
9179 01:21:33.629280 RX DQ/DQS(Engine): PASS
9180 01:21:33.629358 TX OE : PASS
9181 01:21:33.629441 All Pass.
9182 01:21:33.629494
9183 01:21:33.629546 CH 1, Rank 1
9184 01:21:33.629598 SW Impedance : PASS
9185 01:21:33.629650 DUTY Scan : NO K
9186 01:21:33.629702 ZQ Calibration : PASS
9187 01:21:33.629754 Jitter Meter : NO K
9188 01:21:33.629806 CBT Training : PASS
9189 01:21:33.629858 Write leveling : PASS
9190 01:21:33.629924 RX DQS gating : PASS
9191 01:21:33.629977 RX DQ/DQS(RDDQC) : PASS
9192 01:21:33.630030 TX DQ/DQS : PASS
9193 01:21:33.630111 RX DATLAT : PASS
9194 01:21:33.630163 RX DQ/DQS(Engine): PASS
9195 01:21:33.630216 TX OE : PASS
9196 01:21:33.630308 All Pass.
9197 01:21:33.630360
9198 01:21:33.630412 DramC Write-DBI on
9199 01:21:33.630464 PER_BANK_REFRESH: Hybrid Mode
9200 01:21:33.630517 TX_TRACKING: ON
9201 01:21:33.630569 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9202 01:21:33.630623 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9203 01:21:33.630676 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9204 01:21:33.630729 [FAST_K] Save calibration result to emmc
9205 01:21:33.630782 sync common calibartion params.
9206 01:21:33.630834 sync cbt_mode0:1, 1:1
9207 01:21:33.630886 dram_init: ddr_geometry: 2
9208 01:21:33.630939 dram_init: ddr_geometry: 2
9209 01:21:33.630991 dram_init: ddr_geometry: 2
9210 01:21:33.631043 0:dram_rank_size:100000000
9211 01:21:33.631097 1:dram_rank_size:100000000
9212 01:21:33.631151 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9213 01:21:33.631205 DFS_SHUFFLE_HW_MODE: ON
9214 01:21:33.631257 dramc_set_vcore_voltage set vcore to 725000
9215 01:21:33.631310 Read voltage for 1600, 0
9216 01:21:33.631362 Vio18 = 0
9217 01:21:33.631414 Vcore = 725000
9218 01:21:33.631466 Vdram = 0
9219 01:21:33.631519 Vddq = 0
9220 01:21:33.631570 Vmddr = 0
9221 01:21:33.631622 switch to 3200 Mbps bootup
9222 01:21:33.631675 [DramcRunTimeConfig]
9223 01:21:33.631741 PHYPLL
9224 01:21:33.631794 DPM_CONTROL_AFTERK: ON
9225 01:21:33.631860 PER_BANK_REFRESH: ON
9226 01:21:33.631912 REFRESH_OVERHEAD_REDUCTION: ON
9227 01:21:33.631964 CMD_PICG_NEW_MODE: OFF
9228 01:21:33.632017 XRTWTW_NEW_MODE: ON
9229 01:21:33.632068 XRTRTR_NEW_MODE: ON
9230 01:21:33.632121 TX_TRACKING: ON
9231 01:21:33.632173 RDSEL_TRACKING: OFF
9232 01:21:33.632225 DQS Precalculation for DVFS: ON
9233 01:21:33.632304 RX_TRACKING: OFF
9234 01:21:33.632356 HW_GATING DBG: ON
9235 01:21:33.632408 ZQCS_ENABLE_LP4: ON
9236 01:21:33.632460 RX_PICG_NEW_MODE: ON
9237 01:21:33.632512 TX_PICG_NEW_MODE: ON
9238 01:21:33.632564 ENABLE_RX_DCM_DPHY: ON
9239 01:21:33.632616 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9240 01:21:33.632668 DUMMY_READ_FOR_TRACKING: OFF
9241 01:21:33.632721 !!! SPM_CONTROL_AFTERK: OFF
9242 01:21:33.632780 !!! SPM could not control APHY
9243 01:21:33.632834 IMPEDANCE_TRACKING: ON
9244 01:21:33.632886 TEMP_SENSOR: ON
9245 01:21:33.632938 HW_SAVE_FOR_SR: OFF
9246 01:21:33.632990 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9247 01:21:33.633042 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9248 01:21:33.633108 Read ODT Tracking: ON
9249 01:21:33.633161 Refresh Rate DeBounce: ON
9250 01:21:33.633230 DFS_NO_QUEUE_FLUSH: ON
9251 01:21:33.633285 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9252 01:21:33.633346 ENABLE_DFS_RUNTIME_MRW: OFF
9253 01:21:33.633414 DDR_RESERVE_NEW_MODE: ON
9254 01:21:33.633467 MR_CBT_SWITCH_FREQ: ON
9255 01:21:33.633519 =========================
9256 01:21:33.633572 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9257 01:21:33.633626 dram_init: ddr_geometry: 2
9258 01:21:33.633678 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9259 01:21:33.633732 dram_init: dram init end (result: 0)
9260 01:21:33.633784 DRAM-K: Full calibration passed in 24618 msecs
9261 01:21:33.633837 MRC: failed to locate region type 0.
9262 01:21:33.633890 DRAM rank0 size:0x100000000,
9263 01:21:33.633942 DRAM rank1 size=0x100000000
9264 01:21:33.633994 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9265 01:21:33.634048 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9266 01:21:33.634101 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9267 01:21:33.634154 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9268 01:21:33.634207 DRAM rank0 size:0x100000000,
9269 01:21:33.634259 DRAM rank1 size=0x100000000
9270 01:21:33.634311 CBMEM:
9271 01:21:33.634363 IMD: root @ 0xfffff000 254 entries.
9272 01:21:33.634415 IMD: root @ 0xffffec00 62 entries.
9273 01:21:33.634468 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9274 01:21:33.634521 WARNING: RO_VPD is uninitialized or empty.
9275 01:21:33.634573 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9276 01:21:33.634626 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9277 01:21:33.634679 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9278 01:21:33.634732 BS: romstage times (exec / console): total (unknown) / 24113 ms
9279 01:21:33.634800
9280 01:21:33.634854
9281 01:21:33.635095 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9282 01:21:33.635157 ARM64: Exception handlers installed.
9283 01:21:33.635225 ARM64: Testing exception
9284 01:21:33.635280 ARM64: Done test exception
9285 01:21:33.635334 Enumerating buses...
9286 01:21:33.635387 Show all devs... Before device enumeration.
9287 01:21:33.635441 Root Device: enabled 1
9288 01:21:33.635494 CPU_CLUSTER: 0: enabled 1
9289 01:21:33.635548 CPU: 00: enabled 1
9290 01:21:33.635601 Compare with tree...
9291 01:21:33.635654 Root Device: enabled 1
9292 01:21:33.635707 CPU_CLUSTER: 0: enabled 1
9293 01:21:33.635760 CPU: 00: enabled 1
9294 01:21:33.635813 Root Device scanning...
9295 01:21:33.635866 scan_static_bus for Root Device
9296 01:21:33.635920 CPU_CLUSTER: 0 enabled
9297 01:21:33.635973 scan_static_bus for Root Device done
9298 01:21:33.636026 scan_bus: bus Root Device finished in 8 msecs
9299 01:21:33.636080 done
9300 01:21:33.636133 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9301 01:21:33.636187 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9302 01:21:33.636242 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9303 01:21:33.636296 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9304 01:21:33.636350 Allocating resources...
9305 01:21:33.636403 Reading resources...
9306 01:21:33.636456 Root Device read_resources bus 0 link: 0
9307 01:21:33.636510 DRAM rank0 size:0x100000000,
9308 01:21:33.636563 DRAM rank1 size=0x100000000
9309 01:21:33.636617 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9310 01:21:33.636670 CPU: 00 missing read_resources
9311 01:21:33.636723 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9312 01:21:33.636777 Root Device read_resources bus 0 link: 0 done
9313 01:21:33.636830 Done reading resources.
9314 01:21:33.636883 Show resources in subtree (Root Device)...After reading.
9315 01:21:33.636936 Root Device child on link 0 CPU_CLUSTER: 0
9316 01:21:33.636989 CPU_CLUSTER: 0 child on link 0 CPU: 00
9317 01:21:33.637042 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9318 01:21:33.637096 CPU: 00
9319 01:21:33.637149 Root Device assign_resources, bus 0 link: 0
9320 01:21:33.637203 CPU_CLUSTER: 0 missing set_resources
9321 01:21:33.637256 Root Device assign_resources, bus 0 link: 0 done
9322 01:21:33.637310 Done setting resources.
9323 01:21:33.637415 Show resources in subtree (Root Device)...After assigning values.
9324 01:21:33.637471 Root Device child on link 0 CPU_CLUSTER: 0
9325 01:21:33.637526 CPU_CLUSTER: 0 child on link 0 CPU: 00
9326 01:21:33.637580 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9327 01:21:33.637634 CPU: 00
9328 01:21:33.637688 Done allocating resources.
9329 01:21:33.637741 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9330 01:21:33.637794 Enabling resources...
9331 01:21:33.637847 done.
9332 01:21:33.637900 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9333 01:21:33.637954 Initializing devices...
9334 01:21:33.638007 Root Device init
9335 01:21:33.638060 init hardware done!
9336 01:21:33.638114 0x00000018: ctrlr->caps
9337 01:21:33.638168 52.000 MHz: ctrlr->f_max
9338 01:21:33.638223 0.400 MHz: ctrlr->f_min
9339 01:21:33.638277 0x40ff8080: ctrlr->voltages
9340 01:21:33.638380 sclk: 390625
9341 01:21:33.638434 Bus Width = 1
9342 01:21:33.638487 sclk: 390625
9343 01:21:33.638541 Bus Width = 1
9344 01:21:33.638594 Early init status = 3
9345 01:21:33.638647 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9346 01:21:33.638702 in-header: 03 fc 00 00 01 00 00 00
9347 01:21:33.638755 in-data: 00
9348 01:21:33.638808 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9349 01:21:33.638862 in-header: 03 fd 00 00 00 00 00 00
9350 01:21:33.638915 in-data:
9351 01:21:33.638968 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9352 01:21:33.639021 in-header: 03 fc 00 00 01 00 00 00
9353 01:21:33.639074 in-data: 00
9354 01:21:33.639126 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9355 01:21:33.639180 in-header: 03 fd 00 00 00 00 00 00
9356 01:21:33.639233 in-data:
9357 01:21:33.639286 [SSUSB] Setting up USB HOST controller...
9358 01:21:33.639339 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9359 01:21:33.639392 [SSUSB] phy power-on done.
9360 01:21:33.639445 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9361 01:21:33.639499 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9362 01:21:33.639551 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9363 01:21:33.639605 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9364 01:21:33.639657 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9365 01:21:33.639710 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9366 01:21:33.639764 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9367 01:21:33.639817 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9368 01:21:33.639870 SPM: binary array size = 0x9dc
9369 01:21:33.639938 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9370 01:21:33.639994 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9371 01:21:33.640048 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9372 01:21:33.640102 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9373 01:21:33.640156 configure_display: Starting display init
9374 01:21:33.640209 anx7625_power_on_init: Init interface.
9375 01:21:33.640261 anx7625_disable_pd_protocol: Disabled PD feature.
9376 01:21:33.640314 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9377 01:21:33.640367 anx7625_start_dp_work: Secure OCM version=00
9378 01:21:33.640420 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9379 01:21:33.640472 sp_tx_get_edid_block: EDID Block = 1
9380 01:21:33.640525 Extracted contents:
9381 01:21:33.640578 header: 00 ff ff ff ff ff ff 00
9382 01:21:33.640631 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9383 01:21:33.640683 version: 01 04
9384 01:21:33.640738 basic params: 95 1f 11 78 0a
9385 01:21:33.640792 chroma info: 76 90 94 55 54 90 27 21 50 54
9386 01:21:33.640845 established: 00 00 00
9387 01:21:33.641085 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9388 01:21:33.641149 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9389 01:21:33.641204 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9390 01:21:33.641257 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9391 01:21:33.641310 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9392 01:21:33.641417 extensions: 00
9393 01:21:33.641471 checksum: fb
9394 01:21:33.641525
9395 01:21:33.641578 Manufacturer: IVO Model 57d Serial Number 0
9396 01:21:33.641632 Made week 0 of 2020
9397 01:21:33.641684 EDID version: 1.4
9398 01:21:33.641736 Digital display
9399 01:21:33.641789 6 bits per primary color channel
9400 01:21:33.641842 DisplayPort interface
9401 01:21:33.641895 Maximum image size: 31 cm x 17 cm
9402 01:21:33.641947 Gamma: 220%
9403 01:21:33.642000 Check DPMS levels
9404 01:21:33.642052 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9405 01:21:33.642105 First detailed timing is preferred timing
9406 01:21:33.642159 Established timings supported:
9407 01:21:33.642211 Standard timings supported:
9408 01:21:33.642264 Detailed timings
9409 01:21:33.642317 Hex of detail: 383680a07038204018303c0035ae10000019
9410 01:21:33.642370 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9411 01:21:33.642422 0780 0798 07c8 0820 hborder 0
9412 01:21:33.642475 0438 043b 0447 0458 vborder 0
9413 01:21:33.642528 -hsync -vsync
9414 01:21:33.642580 Did detailed timing
9415 01:21:33.642632 Hex of detail: 000000000000000000000000000000000000
9416 01:21:33.642685 Manufacturer-specified data, tag 0
9417 01:21:33.642738 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9418 01:21:33.642791 ASCII string: InfoVision
9419 01:21:33.642843 Hex of detail: 000000fe00523134304e574635205248200a
9420 01:21:33.642897 ASCII string: R140NWF5 RH
9421 01:21:33.642949 Checksum
9422 01:21:33.643286 Checksum: 0xfb (valid)
9423 01:21:33.646632 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9424 01:21:33.649882 DSI data_rate: 832800000 bps
9425 01:21:33.656527 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9426 01:21:33.659600 anx7625_parse_edid: pixelclock(138800).
9427 01:21:33.662947 hactive(1920), hsync(48), hfp(24), hbp(88)
9428 01:21:33.666068 vactive(1080), vsync(12), vfp(3), vbp(17)
9429 01:21:33.669477 anx7625_dsi_config: config dsi.
9430 01:21:33.676635 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9431 01:21:33.690622 anx7625_dsi_config: success to config DSI
9432 01:21:33.694055 anx7625_dp_start: MIPI phy setup OK.
9433 01:21:33.696811 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9434 01:21:33.700539 mtk_ddp_mode_set invalid vrefresh 60
9435 01:21:33.703502 main_disp_path_setup
9436 01:21:33.703970 ovl_layer_smi_id_en
9437 01:21:33.706843 ovl_layer_smi_id_en
9438 01:21:33.707312 ccorr_config
9439 01:21:33.707676 aal_config
9440 01:21:33.710189 gamma_config
9441 01:21:33.710744 postmask_config
9442 01:21:33.713540 dither_config
9443 01:21:33.717242 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9444 01:21:33.723582 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9445 01:21:33.727011 Root Device init finished in 552 msecs
9446 01:21:33.729769 CPU_CLUSTER: 0 init
9447 01:21:33.736579 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9448 01:21:33.743436 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9449 01:21:33.744003 APU_MBOX 0x190000b0 = 0x10001
9450 01:21:33.747019 APU_MBOX 0x190001b0 = 0x10001
9451 01:21:33.749990 APU_MBOX 0x190005b0 = 0x10001
9452 01:21:33.753534 APU_MBOX 0x190006b0 = 0x10001
9453 01:21:33.759676 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9454 01:21:33.769873 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9455 01:21:33.781817 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9456 01:21:33.788893 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9457 01:21:33.800395 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9458 01:21:33.809641 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9459 01:21:33.812836 CPU_CLUSTER: 0 init finished in 81 msecs
9460 01:21:33.816419 Devices initialized
9461 01:21:33.819468 Show all devs... After init.
9462 01:21:33.819932 Root Device: enabled 1
9463 01:21:33.822551 CPU_CLUSTER: 0: enabled 1
9464 01:21:33.825684 CPU: 00: enabled 1
9465 01:21:33.829874 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9466 01:21:33.832479 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9467 01:21:33.836095 ELOG: NV offset 0x57f000 size 0x1000
9468 01:21:33.842631 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9469 01:21:33.849406 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9470 01:21:33.853017 ELOG: Event(17) added with size 13 at 2024-04-23 01:21:33 UTC
9471 01:21:33.859438 out: cmd=0x121: 03 db 21 01 00 00 00 00
9472 01:21:33.862444 in-header: 03 a3 00 00 2c 00 00 00
9473 01:21:33.876067 in-data: bc 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9474 01:21:33.878431 ELOG: Event(A1) added with size 10 at 2024-04-23 01:21:33 UTC
9475 01:21:33.886039 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9476 01:21:33.891889 ELOG: Event(A0) added with size 9 at 2024-04-23 01:21:33 UTC
9477 01:21:33.895576 elog_add_boot_reason: Logged dev mode boot
9478 01:21:33.901838 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9479 01:21:33.902406 Finalize devices...
9480 01:21:33.904938 Devices finalized
9481 01:21:33.908035 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9482 01:21:33.911859 Writing coreboot table at 0xffe64000
9483 01:21:33.918077 0. 000000000010a000-0000000000113fff: RAMSTAGE
9484 01:21:33.921077 1. 0000000040000000-00000000400fffff: RAM
9485 01:21:33.924267 2. 0000000040100000-000000004032afff: RAMSTAGE
9486 01:21:33.927853 3. 000000004032b000-00000000545fffff: RAM
9487 01:21:33.931320 4. 0000000054600000-000000005465ffff: BL31
9488 01:21:33.937573 5. 0000000054660000-00000000ffe63fff: RAM
9489 01:21:33.941228 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9490 01:21:33.944170 7. 0000000100000000-000000023fffffff: RAM
9491 01:21:33.947910 Passing 5 GPIOs to payload:
9492 01:21:33.951232 NAME | PORT | POLARITY | VALUE
9493 01:21:33.957971 EC in RW | 0x000000aa | low | undefined
9494 01:21:33.960954 EC interrupt | 0x00000005 | low | undefined
9495 01:21:33.967470 TPM interrupt | 0x000000ab | high | undefined
9496 01:21:33.971287 SD card detect | 0x00000011 | high | undefined
9497 01:21:33.974300 speaker enable | 0x00000093 | high | undefined
9498 01:21:33.981483 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9499 01:21:33.984052 in-header: 03 f9 00 00 02 00 00 00
9500 01:21:33.984625 in-data: 02 00
9501 01:21:33.987606 ADC[4]: Raw value=902291 ID=7
9502 01:21:33.991181 ADC[3]: Raw value=213652 ID=1
9503 01:21:33.991766 RAM Code: 0x71
9504 01:21:33.994115 ADC[6]: Raw value=75036 ID=0
9505 01:21:33.997359 ADC[5]: Raw value=213282 ID=1
9506 01:21:33.997925 SKU Code: 0x1
9507 01:21:34.003861 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ec0b
9508 01:21:34.006967 coreboot table: 964 bytes.
9509 01:21:34.010804 IMD ROOT 0. 0xfffff000 0x00001000
9510 01:21:34.013902 IMD SMALL 1. 0xffffe000 0x00001000
9511 01:21:34.017174 RO MCACHE 2. 0xffffc000 0x00001104
9512 01:21:34.020116 CONSOLE 3. 0xfff7c000 0x00080000
9513 01:21:34.023530 FMAP 4. 0xfff7b000 0x00000452
9514 01:21:34.027073 TIME STAMP 5. 0xfff7a000 0x00000910
9515 01:21:34.029961 VBOOT WORK 6. 0xfff66000 0x00014000
9516 01:21:34.033104 RAMOOPS 7. 0xffe66000 0x00100000
9517 01:21:34.036410 COREBOOT 8. 0xffe64000 0x00002000
9518 01:21:34.036886 IMD small region:
9519 01:21:34.039895 IMD ROOT 0. 0xffffec00 0x00000400
9520 01:21:34.043398 VPD 1. 0xffffeb80 0x0000006c
9521 01:21:34.046568 MMC STATUS 2. 0xffffeb60 0x00000004
9522 01:21:34.053187 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9523 01:21:34.053697 Probing TPM: done!
9524 01:21:34.059583 Connected to device vid:did:rid of 1ae0:0028:00
9525 01:21:34.070042 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9526 01:21:34.073306 Initialized TPM device CR50 revision 0
9527 01:21:34.073900 Checking cr50 for pending updates
9528 01:21:34.079372 Reading cr50 TPM mode
9529 01:21:34.088590 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9530 01:21:34.094718 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9531 01:21:34.134773 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9532 01:21:34.137978 Checking segment from ROM address 0x40100000
9533 01:21:34.141452 Checking segment from ROM address 0x4010001c
9534 01:21:34.148141 Loading segment from ROM address 0x40100000
9535 01:21:34.148700 code (compression=0)
9536 01:21:34.157852 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9537 01:21:34.164581 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9538 01:21:34.165149 it's not compressed!
9539 01:21:34.171203 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9540 01:21:34.177710 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9541 01:21:34.195339 Loading segment from ROM address 0x4010001c
9542 01:21:34.195910 Entry Point 0x80000000
9543 01:21:34.198516 Loaded segments
9544 01:21:34.201514 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9545 01:21:34.208019 Jumping to boot code at 0x80000000(0xffe64000)
9546 01:21:34.215347 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9547 01:21:34.221445 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9548 01:21:34.229682 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9549 01:21:34.232886 Checking segment from ROM address 0x40100000
9550 01:21:34.236347 Checking segment from ROM address 0x4010001c
9551 01:21:34.242757 Loading segment from ROM address 0x40100000
9552 01:21:34.243234 code (compression=1)
9553 01:21:34.249191 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9554 01:21:34.259687 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9555 01:21:34.260278 using LZMA
9556 01:21:34.267586 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9557 01:21:34.274615 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9558 01:21:34.277824 Loading segment from ROM address 0x4010001c
9559 01:21:34.278369 Entry Point 0x54601000
9560 01:21:34.281096 Loaded segments
9561 01:21:34.284599 NOTICE: MT8192 bl31_setup
9562 01:21:34.291243 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9563 01:21:34.294644 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9564 01:21:34.297838 WARNING: region 0:
9565 01:21:34.301647 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9566 01:21:34.302081 WARNING: region 1:
9567 01:21:34.308144 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9568 01:21:34.311265 WARNING: region 2:
9569 01:21:34.314810 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9570 01:21:34.318017 WARNING: region 3:
9571 01:21:34.324410 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9572 01:21:34.324980 WARNING: region 4:
9573 01:21:34.331011 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9574 01:21:34.331649 WARNING: region 5:
9575 01:21:34.333890 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9576 01:21:34.337429 WARNING: region 6:
9577 01:21:34.340741 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9578 01:21:34.344542 WARNING: region 7:
9579 01:21:34.347130 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9580 01:21:34.353861 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9581 01:21:34.357558 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9582 01:21:34.363693 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9583 01:21:34.367045 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9584 01:21:34.370659 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9585 01:21:34.376980 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9586 01:21:34.380574 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9587 01:21:34.384025 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9588 01:21:34.390402 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9589 01:21:34.393931 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9590 01:21:34.400604 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9591 01:21:34.403755 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9592 01:21:34.406980 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9593 01:21:34.413485 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9594 01:21:34.417244 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9595 01:21:34.420239 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9596 01:21:34.426968 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9597 01:21:34.429908 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9598 01:21:34.436861 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9599 01:21:34.440031 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9600 01:21:34.443782 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9601 01:21:34.449913 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9602 01:21:34.453258 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9603 01:21:34.460006 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9604 01:21:34.463602 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9605 01:21:34.466396 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9606 01:21:34.472917 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9607 01:21:34.476484 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9608 01:21:34.483565 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9609 01:21:34.486536 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9610 01:21:34.492945 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9611 01:21:34.495802 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9612 01:21:34.499379 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9613 01:21:34.502848 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9614 01:21:34.509067 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9615 01:21:34.512952 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9616 01:21:34.515976 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9617 01:21:34.519134 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9618 01:21:34.526198 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9619 01:21:34.529171 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9620 01:21:34.532506 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9621 01:21:34.535912 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9622 01:21:34.542299 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9623 01:21:34.545369 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9624 01:21:34.549532 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9625 01:21:34.555879 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9626 01:21:34.559064 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9627 01:21:34.562009 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9628 01:21:34.568863 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9629 01:21:34.572433 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9630 01:21:34.575906 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9631 01:21:34.582300 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9632 01:21:34.586074 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9633 01:21:34.591787 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9634 01:21:34.595248 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9635 01:21:34.602137 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9636 01:21:34.605465 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9637 01:21:34.608895 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9638 01:21:34.614963 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9639 01:21:34.618419 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9640 01:21:34.624818 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9641 01:21:34.628024 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9642 01:21:34.634733 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9643 01:21:34.638068 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9644 01:21:34.644704 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9645 01:21:34.648367 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9646 01:21:34.654563 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9647 01:21:34.658453 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9648 01:21:34.661266 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9649 01:21:34.668293 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9650 01:21:34.672017 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9651 01:21:34.678333 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9652 01:21:34.681380 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9653 01:21:34.684710 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9654 01:21:34.691375 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9655 01:21:34.694519 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9656 01:21:34.701501 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9657 01:21:34.704636 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9658 01:21:34.711765 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9659 01:21:34.714812 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9660 01:21:34.720964 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9661 01:21:34.724370 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9662 01:21:34.730802 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9663 01:21:34.734081 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9664 01:21:34.737464 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9665 01:21:34.743911 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9666 01:21:34.747669 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9667 01:21:34.753987 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9668 01:21:34.757233 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9669 01:21:34.764271 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9670 01:21:34.767572 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9671 01:21:34.773916 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9672 01:21:34.776967 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9673 01:21:34.780073 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9674 01:21:34.786971 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9675 01:21:34.790576 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9676 01:21:34.796798 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9677 01:21:34.800340 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9678 01:21:34.803234 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9679 01:21:34.807177 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9680 01:21:34.813809 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9681 01:21:34.816717 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9682 01:21:34.819906 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9683 01:21:34.826770 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9684 01:21:34.830155 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9685 01:21:34.836970 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9686 01:21:34.840221 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9687 01:21:34.846904 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9688 01:21:34.850268 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9689 01:21:34.853104 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9690 01:21:34.859702 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9691 01:21:34.863151 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9692 01:21:34.870225 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9693 01:21:34.873318 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9694 01:21:34.876267 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9695 01:21:34.883528 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9696 01:21:34.886320 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9697 01:21:34.889513 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9698 01:21:34.896561 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9699 01:21:34.899302 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9700 01:21:34.902937 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9701 01:21:34.906445 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9702 01:21:34.912752 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9703 01:21:34.915933 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9704 01:21:34.919628 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9705 01:21:34.925839 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9706 01:21:34.929311 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9707 01:21:34.936085 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9708 01:21:34.939083 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9709 01:21:34.942480 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9710 01:21:34.949277 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9711 01:21:34.952788 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9712 01:21:34.956027 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9713 01:21:34.962108 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9714 01:21:34.965897 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9715 01:21:34.971922 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9716 01:21:34.976161 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9717 01:21:34.979240 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9718 01:21:34.985836 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9719 01:21:34.988968 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9720 01:21:34.995568 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9721 01:21:34.998724 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9722 01:21:35.002240 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9723 01:21:35.008963 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9724 01:21:35.012146 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9725 01:21:35.018559 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9726 01:21:35.021975 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9727 01:21:35.025165 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9728 01:21:35.031877 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9729 01:21:35.035415 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9730 01:21:35.041705 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9731 01:21:35.044992 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9732 01:21:35.048726 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9733 01:21:35.054560 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9734 01:21:35.058631 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9735 01:21:35.064964 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9736 01:21:35.068380 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9737 01:21:35.071328 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9738 01:21:35.077707 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9739 01:21:35.080976 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9740 01:21:35.087974 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9741 01:21:35.091081 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9742 01:21:35.094425 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9743 01:21:35.101424 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9744 01:21:35.104306 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9745 01:21:35.110752 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9746 01:21:35.114043 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9747 01:21:35.117936 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9748 01:21:35.124497 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9749 01:21:35.127749 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9750 01:21:35.133855 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9751 01:21:35.136976 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9752 01:21:35.140475 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9753 01:21:35.146925 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9754 01:21:35.150622 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9755 01:21:35.156805 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9756 01:21:35.160324 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9757 01:21:35.163244 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9758 01:21:35.170172 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9759 01:21:35.173653 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9760 01:21:35.180654 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9761 01:21:35.184010 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9762 01:21:35.186751 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9763 01:21:35.193223 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9764 01:21:35.196389 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9765 01:21:35.203121 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9766 01:21:35.206138 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9767 01:21:35.209975 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9768 01:21:35.216173 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9769 01:21:35.219879 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9770 01:21:35.226002 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9771 01:21:35.229659 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9772 01:21:35.235944 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9773 01:21:35.239525 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9774 01:21:35.242540 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9775 01:21:35.249067 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9776 01:21:35.252772 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9777 01:21:35.259664 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9778 01:21:35.262580 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9779 01:21:35.269105 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9780 01:21:35.272475 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9781 01:21:35.278985 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9782 01:21:35.282282 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9783 01:21:35.285385 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9784 01:21:35.292118 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9785 01:21:35.295417 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9786 01:21:35.301516 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9787 01:21:35.305163 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9788 01:21:35.311977 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9789 01:21:35.314529 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9790 01:21:35.318745 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9791 01:21:35.324623 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9792 01:21:35.328127 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9793 01:21:35.334637 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9794 01:21:35.337620 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9795 01:21:35.344638 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9796 01:21:35.347559 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9797 01:21:35.351315 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9798 01:21:35.357666 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9799 01:21:35.361004 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9800 01:21:35.367167 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9801 01:21:35.371055 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9802 01:21:35.377372 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9803 01:21:35.381326 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9804 01:21:35.384061 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9805 01:21:35.390552 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9806 01:21:35.393739 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9807 01:21:35.401326 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9808 01:21:35.403547 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9809 01:21:35.406779 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9810 01:21:35.413578 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9811 01:21:35.416884 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9812 01:21:35.419897 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9813 01:21:35.423281 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9814 01:21:35.430667 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9815 01:21:35.433058 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9816 01:21:35.436555 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9817 01:21:35.442848 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9818 01:21:35.446256 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9819 01:21:35.453081 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9820 01:21:35.455916 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9821 01:21:35.459418 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9822 01:21:35.466081 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9823 01:21:35.469434 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9824 01:21:35.472837 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9825 01:21:35.479474 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9826 01:21:35.483013 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9827 01:21:35.489194 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9828 01:21:35.492613 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9829 01:21:35.496033 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9830 01:21:35.502626 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9831 01:21:35.505612 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9832 01:21:35.512615 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9833 01:21:35.515411 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9834 01:21:35.518785 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9835 01:21:35.525222 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9836 01:21:35.529311 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9837 01:21:35.532112 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9838 01:21:35.538408 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9839 01:21:35.542127 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9840 01:21:35.544950 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9841 01:21:35.552095 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9842 01:21:35.554990 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9843 01:21:35.561973 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9844 01:21:35.565188 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9845 01:21:35.568206 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9846 01:21:35.574521 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9847 01:21:35.578038 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9848 01:21:35.581707 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9849 01:21:35.588280 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9850 01:21:35.591690 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9851 01:21:35.594759 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9852 01:21:35.597887 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9853 01:21:35.604762 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9854 01:21:35.607726 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9855 01:21:35.610976 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9856 01:21:35.614250 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9857 01:21:35.620997 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9858 01:21:35.624122 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9859 01:21:35.627663 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9860 01:21:35.634108 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9861 01:21:35.637148 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9862 01:21:35.641037 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9863 01:21:35.647081 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9864 01:21:35.650701 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9865 01:21:35.657259 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9866 01:21:35.660554 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9867 01:21:35.664114 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9868 01:21:35.670666 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9869 01:21:35.673420 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9870 01:21:35.680162 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9871 01:21:35.683493 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9872 01:21:35.686922 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9873 01:21:35.693438 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9874 01:21:35.696891 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9875 01:21:35.703326 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9876 01:21:35.706147 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9877 01:21:35.713057 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9878 01:21:35.716249 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9879 01:21:35.719847 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9880 01:21:35.726576 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9881 01:21:35.729452 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9882 01:21:35.736325 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9883 01:21:35.739333 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9884 01:21:35.745729 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9885 01:21:35.749096 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9886 01:21:35.752596 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9887 01:21:35.759360 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9888 01:21:35.762681 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9889 01:21:35.769326 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9890 01:21:35.772329 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9891 01:21:35.779011 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9892 01:21:35.782272 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9893 01:21:35.785698 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9894 01:21:35.792295 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9895 01:21:35.795316 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9896 01:21:35.802180 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9897 01:21:35.805312 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9898 01:21:35.811371 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9899 01:21:35.814989 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9900 01:21:35.818030 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9901 01:21:35.824907 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9902 01:21:35.828290 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9903 01:21:35.834537 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9904 01:21:35.838050 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9905 01:21:35.841228 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9906 01:21:35.847905 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9907 01:21:35.851546 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9908 01:21:35.857460 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9909 01:21:35.861096 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9910 01:21:35.867803 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9911 01:21:35.870584 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9912 01:21:35.874061 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9913 01:21:35.880893 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9914 01:21:35.884102 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9915 01:21:35.890710 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9916 01:21:35.893627 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9917 01:21:35.897297 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9918 01:21:35.903915 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9919 01:21:35.906744 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9920 01:21:35.913737 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9921 01:21:35.916901 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9922 01:21:35.923238 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9923 01:21:35.926412 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9924 01:21:35.933038 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9925 01:21:35.936032 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9926 01:21:35.939163 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9927 01:21:35.946251 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9928 01:21:35.949441 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9929 01:21:35.956075 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9930 01:21:35.959207 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9931 01:21:35.966027 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9932 01:21:35.969486 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9933 01:21:35.972165 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9934 01:21:35.978705 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9935 01:21:35.982165 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9936 01:21:35.988665 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9937 01:21:35.992020 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9938 01:21:35.998499 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9939 01:21:36.001688 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9940 01:21:36.008440 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9941 01:21:36.012193 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9942 01:21:36.015153 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9943 01:21:36.021833 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9944 01:21:36.025219 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9945 01:21:36.031641 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9946 01:21:36.034694 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9947 01:21:36.041430 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9948 01:21:36.044583 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9949 01:21:36.047962 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9950 01:21:36.055054 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9951 01:21:36.057692 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9952 01:21:36.064524 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9953 01:21:36.068197 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9954 01:21:36.074440 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9955 01:21:36.077771 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9956 01:21:36.084105 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9957 01:21:36.087752 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9958 01:21:36.091183 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9959 01:21:36.098160 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9960 01:21:36.101241 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9961 01:21:36.107784 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9962 01:21:36.111252 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9963 01:21:36.117285 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9964 01:21:36.120648 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9965 01:21:36.127295 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9966 01:21:36.130811 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9967 01:21:36.134025 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9968 01:21:36.140490 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9969 01:21:36.144263 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9970 01:21:36.150275 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9971 01:21:36.153692 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9972 01:21:36.160320 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9973 01:21:36.163488 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9974 01:21:36.170016 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9975 01:21:36.173323 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9976 01:21:36.176594 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9977 01:21:36.183289 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9978 01:21:36.186785 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9979 01:21:36.193143 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9980 01:21:36.196665 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9981 01:21:36.202942 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9982 01:21:36.206762 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9983 01:21:36.209901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9984 01:21:36.216603 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9985 01:21:36.219477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9986 01:21:36.226021 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9987 01:21:36.229487 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9988 01:21:36.236163 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9989 01:21:36.239651 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9990 01:21:36.245969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9991 01:21:36.249206 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9992 01:21:36.256022 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9993 01:21:36.258910 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9994 01:21:36.265913 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9995 01:21:36.269188 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9996 01:21:36.275808 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9997 01:21:36.278892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9998 01:21:36.285320 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9999 01:21:36.288573 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10000 01:21:36.295469 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10001 01:21:36.298485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10002 01:21:36.305146 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10003 01:21:36.308862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10004 01:21:36.314945 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10005 01:21:36.318407 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10006 01:21:36.324719 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10007 01:21:36.327946 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10008 01:21:36.334882 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10009 01:21:36.337791 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10010 01:21:36.344866 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10011 01:21:36.347591 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10012 01:21:36.354518 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10013 01:21:36.357948 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10014 01:21:36.364365 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10015 01:21:36.364925 INFO: [APUAPC] vio 0
10016 01:21:36.371523 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10017 01:21:36.374658 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10018 01:21:36.378036 INFO: [APUAPC] D0_APC_0: 0x400510
10019 01:21:36.381407 INFO: [APUAPC] D0_APC_1: 0x0
10020 01:21:36.384912 INFO: [APUAPC] D0_APC_2: 0x1540
10021 01:21:36.388324 INFO: [APUAPC] D0_APC_3: 0x0
10022 01:21:36.391008 INFO: [APUAPC] D1_APC_0: 0xffffffff
10023 01:21:36.394507 INFO: [APUAPC] D1_APC_1: 0xffffffff
10024 01:21:36.397714 INFO: [APUAPC] D1_APC_2: 0x3fffff
10025 01:21:36.400989 INFO: [APUAPC] D1_APC_3: 0x0
10026 01:21:36.404454 INFO: [APUAPC] D2_APC_0: 0xffffffff
10027 01:21:36.407953 INFO: [APUAPC] D2_APC_1: 0xffffffff
10028 01:21:36.411170 INFO: [APUAPC] D2_APC_2: 0x3fffff
10029 01:21:36.414449 INFO: [APUAPC] D2_APC_3: 0x0
10030 01:21:36.417186 INFO: [APUAPC] D3_APC_0: 0xffffffff
10031 01:21:36.420443 INFO: [APUAPC] D3_APC_1: 0xffffffff
10032 01:21:36.423776 INFO: [APUAPC] D3_APC_2: 0x3fffff
10033 01:21:36.427383 INFO: [APUAPC] D3_APC_3: 0x0
10034 01:21:36.430268 INFO: [APUAPC] D4_APC_0: 0xffffffff
10035 01:21:36.434131 INFO: [APUAPC] D4_APC_1: 0xffffffff
10036 01:21:36.436982 INFO: [APUAPC] D4_APC_2: 0x3fffff
10037 01:21:36.440359 INFO: [APUAPC] D4_APC_3: 0x0
10038 01:21:36.444015 INFO: [APUAPC] D5_APC_0: 0xffffffff
10039 01:21:36.446964 INFO: [APUAPC] D5_APC_1: 0xffffffff
10040 01:21:36.450270 INFO: [APUAPC] D5_APC_2: 0x3fffff
10041 01:21:36.453611 INFO: [APUAPC] D5_APC_3: 0x0
10042 01:21:36.456909 INFO: [APUAPC] D6_APC_0: 0xffffffff
10043 01:21:36.459935 INFO: [APUAPC] D6_APC_1: 0xffffffff
10044 01:21:36.463254 INFO: [APUAPC] D6_APC_2: 0x3fffff
10045 01:21:36.467021 INFO: [APUAPC] D6_APC_3: 0x0
10046 01:21:36.470070 INFO: [APUAPC] D7_APC_0: 0xffffffff
10047 01:21:36.473309 INFO: [APUAPC] D7_APC_1: 0xffffffff
10048 01:21:36.476749 INFO: [APUAPC] D7_APC_2: 0x3fffff
10049 01:21:36.479870 INFO: [APUAPC] D7_APC_3: 0x0
10050 01:21:36.483198 INFO: [APUAPC] D8_APC_0: 0xffffffff
10051 01:21:36.486299 INFO: [APUAPC] D8_APC_1: 0xffffffff
10052 01:21:36.489723 INFO: [APUAPC] D8_APC_2: 0x3fffff
10053 01:21:36.490200 INFO: [APUAPC] D8_APC_3: 0x0
10054 01:21:36.496583 INFO: [APUAPC] D9_APC_0: 0xffffffff
10055 01:21:36.499701 INFO: [APUAPC] D9_APC_1: 0xffffffff
10056 01:21:36.503276 INFO: [APUAPC] D9_APC_2: 0x3fffff
10057 01:21:36.503861 INFO: [APUAPC] D9_APC_3: 0x0
10058 01:21:36.506083 INFO: [APUAPC] D10_APC_0: 0xffffffff
10059 01:21:36.512638 INFO: [APUAPC] D10_APC_1: 0xffffffff
10060 01:21:36.516435 INFO: [APUAPC] D10_APC_2: 0x3fffff
10061 01:21:36.516917 INFO: [APUAPC] D10_APC_3: 0x0
10062 01:21:36.522671 INFO: [APUAPC] D11_APC_0: 0xffffffff
10063 01:21:36.525844 INFO: [APUAPC] D11_APC_1: 0xffffffff
10064 01:21:36.529384 INFO: [APUAPC] D11_APC_2: 0x3fffff
10065 01:21:36.532585 INFO: [APUAPC] D11_APC_3: 0x0
10066 01:21:36.535536 INFO: [APUAPC] D12_APC_0: 0xffffffff
10067 01:21:36.538942 INFO: [APUAPC] D12_APC_1: 0xffffffff
10068 01:21:36.542915 INFO: [APUAPC] D12_APC_2: 0x3fffff
10069 01:21:36.545652 INFO: [APUAPC] D12_APC_3: 0x0
10070 01:21:36.548963 INFO: [APUAPC] D13_APC_0: 0xffffffff
10071 01:21:36.552149 INFO: [APUAPC] D13_APC_1: 0xffffffff
10072 01:21:36.555256 INFO: [APUAPC] D13_APC_2: 0x3fffff
10073 01:21:36.558946 INFO: [APUAPC] D13_APC_3: 0x0
10074 01:21:36.561883 INFO: [APUAPC] D14_APC_0: 0xffffffff
10075 01:21:36.565575 INFO: [APUAPC] D14_APC_1: 0xffffffff
10076 01:21:36.568389 INFO: [APUAPC] D14_APC_2: 0x3fffff
10077 01:21:36.571788 INFO: [APUAPC] D14_APC_3: 0x0
10078 01:21:36.575608 INFO: [APUAPC] D15_APC_0: 0xffffffff
10079 01:21:36.578959 INFO: [APUAPC] D15_APC_1: 0xffffffff
10080 01:21:36.581851 INFO: [APUAPC] D15_APC_2: 0x3fffff
10081 01:21:36.585088 INFO: [APUAPC] D15_APC_3: 0x0
10082 01:21:36.588414 INFO: [APUAPC] APC_CON: 0x4
10083 01:21:36.591634 INFO: [NOCDAPC] D0_APC_0: 0x0
10084 01:21:36.592066 INFO: [NOCDAPC] D0_APC_1: 0x0
10085 01:21:36.595093 INFO: [NOCDAPC] D1_APC_0: 0x0
10086 01:21:36.598145 INFO: [NOCDAPC] D1_APC_1: 0xfff
10087 01:21:36.601648 INFO: [NOCDAPC] D2_APC_0: 0x0
10088 01:21:36.604907 INFO: [NOCDAPC] D2_APC_1: 0xfff
10089 01:21:36.608446 INFO: [NOCDAPC] D3_APC_0: 0x0
10090 01:21:36.611269 INFO: [NOCDAPC] D3_APC_1: 0xfff
10091 01:21:36.615062 INFO: [NOCDAPC] D4_APC_0: 0x0
10092 01:21:36.617713 INFO: [NOCDAPC] D4_APC_1: 0xfff
10093 01:21:36.621097 INFO: [NOCDAPC] D5_APC_0: 0x0
10094 01:21:36.624330 INFO: [NOCDAPC] D5_APC_1: 0xfff
10095 01:21:36.627524 INFO: [NOCDAPC] D6_APC_0: 0x0
10096 01:21:36.628071 INFO: [NOCDAPC] D6_APC_1: 0xfff
10097 01:21:36.630844 INFO: [NOCDAPC] D7_APC_0: 0x0
10098 01:21:36.634327 INFO: [NOCDAPC] D7_APC_1: 0xfff
10099 01:21:36.637404 INFO: [NOCDAPC] D8_APC_0: 0x0
10100 01:21:36.641201 INFO: [NOCDAPC] D8_APC_1: 0xfff
10101 01:21:36.643923 INFO: [NOCDAPC] D9_APC_0: 0x0
10102 01:21:36.647524 INFO: [NOCDAPC] D9_APC_1: 0xfff
10103 01:21:36.650849 INFO: [NOCDAPC] D10_APC_0: 0x0
10104 01:21:36.654205 INFO: [NOCDAPC] D10_APC_1: 0xfff
10105 01:21:36.657995 INFO: [NOCDAPC] D11_APC_0: 0x0
10106 01:21:36.660724 INFO: [NOCDAPC] D11_APC_1: 0xfff
10107 01:21:36.664052 INFO: [NOCDAPC] D12_APC_0: 0x0
10108 01:21:36.666935 INFO: [NOCDAPC] D12_APC_1: 0xfff
10109 01:21:36.670126 INFO: [NOCDAPC] D13_APC_0: 0x0
10110 01:21:36.673638 INFO: [NOCDAPC] D13_APC_1: 0xfff
10111 01:21:36.674177 INFO: [NOCDAPC] D14_APC_0: 0x0
10112 01:21:36.677430 INFO: [NOCDAPC] D14_APC_1: 0xfff
10113 01:21:36.680825 INFO: [NOCDAPC] D15_APC_0: 0x0
10114 01:21:36.684149 INFO: [NOCDAPC] D15_APC_1: 0xfff
10115 01:21:36.686890 INFO: [NOCDAPC] APC_CON: 0x4
10116 01:21:36.690247 INFO: [APUAPC] set_apusys_apc done
10117 01:21:36.693753 INFO: [DEVAPC] devapc_init done
10118 01:21:36.696716 INFO: GICv3 without legacy support detected.
10119 01:21:36.703442 INFO: ARM GICv3 driver initialized in EL3
10120 01:21:36.706944 INFO: Maximum SPI INTID supported: 639
10121 01:21:36.710456 INFO: BL31: Initializing runtime services
10122 01:21:36.716904 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10123 01:21:36.717534 INFO: SPM: enable CPC mode
10124 01:21:36.723226 INFO: mcdi ready for mcusys-off-idle and system suspend
10125 01:21:36.726771 INFO: BL31: Preparing for EL3 exit to normal world
10126 01:21:36.733034 INFO: Entry point address = 0x80000000
10127 01:21:36.733644 INFO: SPSR = 0x8
10128 01:21:36.739825
10129 01:21:36.740395
10130 01:21:36.740765
10131 01:21:36.743017 Starting depthcharge on Spherion...
10132 01:21:36.743598
10133 01:21:36.743971 Wipe memory regions:
10134 01:21:36.744315
10135 01:21:36.746593 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10136 01:21:36.747158 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10137 01:21:36.747608 Setting prompt string to ['asurada:']
10138 01:21:36.748220 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10139 01:21:36.748953 [0x00000040000000, 0x00000054600000)
10140 01:21:36.868637
10141 01:21:36.869214 [0x00000054660000, 0x00000080000000)
10142 01:21:37.129127
10143 01:21:37.129754 [0x000000821a7280, 0x000000ffe64000)
10144 01:21:37.874310
10145 01:21:37.874893 [0x00000100000000, 0x00000240000000)
10146 01:21:39.764096
10147 01:21:39.767352 Initializing XHCI USB controller at 0x11200000.
10148 01:21:40.805608
10149 01:21:40.808936 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10150 01:21:40.809563
10151 01:21:40.809942
10152 01:21:40.810291
10153 01:21:40.811123 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10155 01:21:40.912393 asurada: tftpboot 192.168.201.1 13468763/tftp-deploy-pagevbpx/kernel/image.itb 13468763/tftp-deploy-pagevbpx/kernel/cmdline
10156 01:21:40.913064 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10157 01:21:40.913566 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10158 01:21:40.918108 tftpboot 192.168.201.1 13468763/tftp-deploy-pagevbpx/kernel/image.ittp-deploy-pagevbpx/kernel/cmdline
10159 01:21:40.918591
10160 01:21:40.918963 Waiting for link
10161 01:21:41.078753
10162 01:21:41.079335 R8152: Initializing
10163 01:21:41.079712
10164 01:21:41.082206 Version 6 (ocp_data = 5c30)
10165 01:21:41.082681
10166 01:21:41.085416 R8152: Done initializing
10167 01:21:41.085891
10168 01:21:41.086260 Adding net device
10169 01:21:42.985036
10170 01:21:42.985649 done.
10171 01:21:42.986025
10172 01:21:42.986370 MAC: 00:e0:4c:68:02:81
10173 01:21:42.986707
10174 01:21:42.987687 Sending DHCP discover... done.
10175 01:21:42.988160
10176 01:21:46.491535 Waiting for reply... done.
10177 01:21:46.492140
10178 01:21:46.492519 Sending DHCP request... done.
10179 01:21:46.494199
10180 01:21:46.500231 Waiting for reply... done.
10181 01:21:46.500806
10182 01:21:46.501406 My ip is 192.168.201.14
10183 01:21:46.501899
10184 01:21:46.502913 The DHCP server ip is 192.168.201.1
10185 01:21:46.503386
10186 01:21:46.509755 TFTP server IP predefined by user: 192.168.201.1
10187 01:21:46.510332
10188 01:21:46.515753 Bootfile predefined by user: 13468763/tftp-deploy-pagevbpx/kernel/image.itb
10189 01:21:46.516319
10190 01:21:46.519577 Sending tftp read request... done.
10191 01:21:46.520044
10192 01:21:46.526135 Waiting for the transfer...
10193 01:21:46.526605
10194 01:21:47.229954 00000000 ################################################################
10195 01:21:47.230471
10196 01:21:47.935800 00080000 ################################################################
10197 01:21:47.936336
10198 01:21:48.642733 00100000 ################################################################
10199 01:21:48.643299
10200 01:21:49.328444 00180000 ################################################################
10201 01:21:49.328968
10202 01:21:50.020664 00200000 ################################################################
10203 01:21:50.021396
10204 01:21:50.714624 00280000 ################################################################
10205 01:21:50.715209
10206 01:21:51.413248 00300000 ################################################################
10207 01:21:51.413826
10208 01:21:52.136721 00380000 ################################################################
10209 01:21:52.137325
10210 01:21:52.854208 00400000 ################################################################
10211 01:21:52.854732
10212 01:21:53.561256 00480000 ################################################################
10213 01:21:53.561946
10214 01:21:54.281432 00500000 ################################################################
10215 01:21:54.282030
10216 01:21:54.997187 00580000 ################################################################
10217 01:21:54.997745
10218 01:21:55.687927 00600000 ################################################################
10219 01:21:55.688459
10220 01:21:56.388820 00680000 ################################################################
10221 01:21:56.389425
10222 01:21:57.099020 00700000 ################################################################
10223 01:21:57.099546
10224 01:21:57.804879 00780000 ################################################################
10225 01:21:57.805422
10226 01:21:58.500480 00800000 ################################################################
10227 01:21:58.501014
10228 01:21:59.203184 00880000 ################################################################
10229 01:21:59.203762
10230 01:21:59.909493 00900000 ################################################################
10231 01:21:59.910029
10232 01:22:00.624871 00980000 ################################################################
10233 01:22:00.625442
10234 01:22:01.344344 00a00000 ################################################################
10235 01:22:01.344928
10236 01:22:02.059087 00a80000 ################################################################
10237 01:22:02.059617
10238 01:22:02.779176 00b00000 ################################################################
10239 01:22:02.779703
10240 01:22:03.489176 00b80000 ################################################################
10241 01:22:03.489740
10242 01:22:04.206878 00c00000 ################################################################
10243 01:22:04.207411
10244 01:22:04.917382 00c80000 ################################################################
10245 01:22:04.917905
10246 01:22:05.600951 00d00000 ################################################################
10247 01:22:05.601551
10248 01:22:06.317300 00d80000 ################################################################
10249 01:22:06.317851
10250 01:22:07.021601 00e00000 ################################################################
10251 01:22:07.022198
10252 01:22:07.739061 00e80000 ################################################################
10253 01:22:07.739578
10254 01:22:08.470263 00f00000 ################################################################
10255 01:22:08.470806
10256 01:22:09.169367 00f80000 ################################################################
10257 01:22:09.169884
10258 01:22:09.882149 01000000 ################################################################
10259 01:22:09.882675
10260 01:22:10.576419 01080000 ################################################################
10261 01:22:10.576942
10262 01:22:11.283502 01100000 ################################################################
10263 01:22:11.284020
10264 01:22:11.975046 01180000 ################################################################
10265 01:22:11.975581
10266 01:22:12.670933 01200000 ################################################################
10267 01:22:12.671452
10268 01:22:13.355022 01280000 ################################################################
10269 01:22:13.355605
10270 01:22:14.075431 01300000 ################################################################
10271 01:22:14.076146
10272 01:22:14.789261 01380000 ################################################################
10273 01:22:14.789837
10274 01:22:15.515988 01400000 ################################################################
10275 01:22:15.516613
10276 01:22:16.225455 01480000 ################################################################
10277 01:22:16.226049
10278 01:22:16.953215 01500000 ################################################################
10279 01:22:16.953837
10280 01:22:17.674099 01580000 ################################################################
10281 01:22:17.674630
10282 01:22:18.394874 01600000 ################################################################
10283 01:22:18.395467
10284 01:22:19.112440 01680000 ################################################################
10285 01:22:19.112963
10286 01:22:19.824467 01700000 ################################################################
10287 01:22:19.825012
10288 01:22:20.548291 01780000 ################################################################
10289 01:22:20.548847
10290 01:22:21.237432 01800000 ################################################################
10291 01:22:21.237943
10292 01:22:21.943531 01880000 ################################################################
10293 01:22:21.944069
10294 01:22:22.638385 01900000 ################################################################
10295 01:22:22.638958
10296 01:22:23.354233 01980000 ################################################################
10297 01:22:23.354785
10298 01:22:24.053557 01a00000 ################################################################
10299 01:22:24.054079
10300 01:22:24.758176 01a80000 ################################################################
10301 01:22:24.758737
10302 01:22:25.447350 01b00000 ################################################################
10303 01:22:25.447872
10304 01:22:26.139643 01b80000 ################################################################
10305 01:22:26.140166
10306 01:22:26.861137 01c00000 ################################################################
10307 01:22:26.861849
10308 01:22:27.573261 01c80000 ################################################################
10309 01:22:27.573854
10310 01:22:28.279538 01d00000 ################################################################
10311 01:22:28.280105
10312 01:22:28.988986 01d80000 ################################################################
10313 01:22:28.989546
10314 01:22:29.358561 01e00000 ################################### done.
10315 01:22:29.359067
10316 01:22:29.361641 The bootfile was 31736994 bytes long.
10317 01:22:29.362069
10318 01:22:29.364787 Sending tftp read request... done.
10319 01:22:29.365219
10320 01:22:29.368214 Waiting for the transfer...
10321 01:22:29.368639
10322 01:22:29.371804 00000000 # done.
10323 01:22:29.372240
10324 01:22:29.378099 Command line loaded dynamically from TFTP file: 13468763/tftp-deploy-pagevbpx/kernel/cmdline
10325 01:22:29.378530
10326 01:22:29.401443 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13468763/extract-nfsrootfs-bow5lg9n,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10327 01:22:29.401966
10328 01:22:29.402302 Loading FIT.
10329 01:22:29.402615
10330 01:22:29.404327 Image ramdisk-1 has 18777679 bytes.
10331 01:22:29.404754
10332 01:22:29.407892 Image fdt-1 has 47230 bytes.
10333 01:22:29.408422
10334 01:22:29.411273 Image kernel-1 has 12910050 bytes.
10335 01:22:29.411914
10336 01:22:29.417284 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10337 01:22:29.417756
10338 01:22:29.437573 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10339 01:22:29.438113
10340 01:22:29.440861 Choosing best match conf-1 for compat google,spherion-rev2.
10341 01:22:29.446008
10342 01:22:29.450107 Connected to device vid:did:rid of 1ae0:0028:00
10343 01:22:29.457892
10344 01:22:29.460957 tpm_get_response: command 0x17b, return code 0x0
10345 01:22:29.461520
10346 01:22:29.464364 ec_init: CrosEC protocol v3 supported (256, 248)
10347 01:22:29.467982
10348 01:22:29.471261 tpm_cleanup: add release locality here.
10349 01:22:29.471734
10350 01:22:29.472076 Shutting down all USB controllers.
10351 01:22:29.474480
10352 01:22:29.474902 Removing current net device
10353 01:22:29.475238
10354 01:22:29.481394 Exiting depthcharge with code 4 at timestamp: 82180103
10355 01:22:29.481922
10356 01:22:29.484349 LZMA decompressing kernel-1 to 0x821a6718
10357 01:22:29.484780
10358 01:22:29.487357 LZMA decompressing kernel-1 to 0x40000000
10359 01:22:31.082126
10360 01:22:31.082694 jumping to kernel
10361 01:22:31.084529 end: 2.2.4 bootloader-commands (duration 00:00:54) [common]
10362 01:22:31.085071 start: 2.2.5 auto-login-action (timeout 00:03:31) [common]
10363 01:22:31.085532 Setting prompt string to ['Linux version [0-9]']
10364 01:22:31.085931 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10365 01:22:31.086304 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10366 01:22:31.163981
10367 01:22:31.167253 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10368 01:22:31.170930 start: 2.2.5.1 login-action (timeout 00:03:31) [common]
10369 01:22:31.171514 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10370 01:22:31.171915 Setting prompt string to []
10371 01:22:31.172345 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10372 01:22:31.172767 Using line separator: #'\n'#
10373 01:22:31.173103 No login prompt set.
10374 01:22:31.173489 Parsing kernel messages
10375 01:22:31.173805 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10376 01:22:31.174376 [login-action] Waiting for messages, (timeout 00:03:31)
10377 01:22:31.174740 Waiting using forced prompt support (timeout 00:01:45)
10378 01:22:31.190545 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j174389-arm64-gcc-10-defconfig-arm64-chromebook-96m9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024
10379 01:22:31.193889 [ 0.000000] random: crng init done
10380 01:22:31.200508 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10381 01:22:31.203603 [ 0.000000] efi: UEFI not found.
10382 01:22:31.210015 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10383 01:22:31.220551 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10384 01:22:31.226665 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10385 01:22:31.236703 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10386 01:22:31.243130 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10387 01:22:31.249588 [ 0.000000] printk: bootconsole [mtk8250] enabled
10388 01:22:31.256724 [ 0.000000] NUMA: No NUMA configuration found
10389 01:22:31.262984 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10390 01:22:31.269832 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10391 01:22:31.270406 [ 0.000000] Zone ranges:
10392 01:22:31.276358 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10393 01:22:31.279248 [ 0.000000] DMA32 empty
10394 01:22:31.286065 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10395 01:22:31.289106 [ 0.000000] Movable zone start for each node
10396 01:22:31.292531 [ 0.000000] Early memory node ranges
10397 01:22:31.299370 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10398 01:22:31.305541 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10399 01:22:31.312490 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10400 01:22:31.318540 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10401 01:22:31.325646 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10402 01:22:31.331663 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10403 01:22:31.388389 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10404 01:22:31.395185 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10405 01:22:31.401671 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10406 01:22:31.404893 [ 0.000000] psci: probing for conduit method from DT.
10407 01:22:31.411648 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10408 01:22:31.414859 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10409 01:22:31.421223 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10410 01:22:31.424976 [ 0.000000] psci: SMC Calling Convention v1.2
10411 01:22:31.431676 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10412 01:22:31.434357 [ 0.000000] Detected VIPT I-cache on CPU0
10413 01:22:31.441417 [ 0.000000] CPU features: detected: GIC system register CPU interface
10414 01:22:31.447824 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10415 01:22:31.454419 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10416 01:22:31.460947 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10417 01:22:31.470894 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10418 01:22:31.477538 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10419 01:22:31.480687 [ 0.000000] alternatives: applying boot alternatives
10420 01:22:31.487854 [ 0.000000] Fallback order for Node 0: 0
10421 01:22:31.494447 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10422 01:22:31.498023 [ 0.000000] Policy zone: Normal
10423 01:22:31.521116 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13468763/extract-nfsrootfs-bow5lg9n,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10424 01:22:31.530216 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10425 01:22:31.541850 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10426 01:22:31.551206 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10427 01:22:31.557905 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10428 01:22:31.561139 <6>[ 0.000000] software IO TLB: area num 8.
10429 01:22:31.618077 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10430 01:22:31.766775 <6>[ 0.000000] Memory: 7946172K/8385536K available (18048K kernel code, 4118K rwdata, 22292K rodata, 8448K init, 616K bss, 406596K reserved, 32768K cma-reserved)
10431 01:22:31.773499 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10432 01:22:31.780563 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10433 01:22:31.783560 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10434 01:22:31.790096 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10435 01:22:31.796823 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10436 01:22:31.799942 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10437 01:22:31.809886 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10438 01:22:31.816390 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10439 01:22:31.822922 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10440 01:22:31.829516 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10441 01:22:31.833004 <6>[ 0.000000] GICv3: 608 SPIs implemented
10442 01:22:31.836209 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10443 01:22:31.842575 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10444 01:22:31.846143 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10445 01:22:31.852312 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10446 01:22:31.865555 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10447 01:22:31.878920 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10448 01:22:31.885781 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10449 01:22:31.893321 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10450 01:22:31.907159 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10451 01:22:31.913442 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10452 01:22:31.919806 <6>[ 0.009144] Console: colour dummy device 80x25
10453 01:22:31.929675 <6>[ 0.013874] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10454 01:22:31.936351 <6>[ 0.024381] pid_max: default: 32768 minimum: 301
10455 01:22:31.939542 <6>[ 0.029252] LSM: Security Framework initializing
10456 01:22:31.946247 <6>[ 0.034189] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10457 01:22:31.957003 <6>[ 0.042004] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10458 01:22:31.966485 <6>[ 0.051414] cblist_init_generic: Setting adjustable number of callback queues.
10459 01:22:31.969874 <6>[ 0.058902] cblist_init_generic: Setting shift to 3 and lim to 1.
10460 01:22:31.979471 <6>[ 0.065280] cblist_init_generic: Setting adjustable number of callback queues.
10461 01:22:31.985880 <6>[ 0.072708] cblist_init_generic: Setting shift to 3 and lim to 1.
10462 01:22:31.989466 <6>[ 0.079106] rcu: Hierarchical SRCU implementation.
10463 01:22:31.995706 <6>[ 0.084121] rcu: Max phase no-delay instances is 1000.
10464 01:22:32.002515 <6>[ 0.091152] EFI services will not be available.
10465 01:22:32.005388 <6>[ 0.096108] smp: Bringing up secondary CPUs ...
10466 01:22:32.014437 <6>[ 0.101186] Detected VIPT I-cache on CPU1
10467 01:22:32.021140 <6>[ 0.101254] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10468 01:22:32.027606 <6>[ 0.101284] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10469 01:22:32.030791 <6>[ 0.101616] Detected VIPT I-cache on CPU2
10470 01:22:32.040583 <6>[ 0.101666] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10471 01:22:32.047382 <6>[ 0.101682] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10472 01:22:32.050743 <6>[ 0.101938] Detected VIPT I-cache on CPU3
10473 01:22:32.056931 <6>[ 0.101985] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10474 01:22:32.063469 <6>[ 0.101999] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10475 01:22:32.070355 <6>[ 0.102301] CPU features: detected: Spectre-v4
10476 01:22:32.073712 <6>[ 0.102307] CPU features: detected: Spectre-BHB
10477 01:22:32.076482 <6>[ 0.102312] Detected PIPT I-cache on CPU4
10478 01:22:32.083481 <6>[ 0.102370] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10479 01:22:32.093570 <6>[ 0.102386] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10480 01:22:32.096589 <6>[ 0.102676] Detected PIPT I-cache on CPU5
10481 01:22:32.103081 <6>[ 0.102739] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10482 01:22:32.110026 <6>[ 0.102756] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10483 01:22:32.113181 <6>[ 0.103035] Detected PIPT I-cache on CPU6
10484 01:22:32.123030 <6>[ 0.103099] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10485 01:22:32.130067 <6>[ 0.103115] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10486 01:22:32.133263 <6>[ 0.103414] Detected PIPT I-cache on CPU7
10487 01:22:32.139508 <6>[ 0.103479] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10488 01:22:32.146167 <6>[ 0.103494] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10489 01:22:32.149630 <6>[ 0.103541] smp: Brought up 1 node, 8 CPUs
10490 01:22:32.155660 <6>[ 0.245031] SMP: Total of 8 processors activated.
10491 01:22:32.162787 <6>[ 0.249983] CPU features: detected: 32-bit EL0 Support
10492 01:22:32.168972 <6>[ 0.255380] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10493 01:22:32.175752 <6>[ 0.264180] CPU features: detected: Common not Private translations
10494 01:22:32.181984 <6>[ 0.270657] CPU features: detected: CRC32 instructions
10495 01:22:32.188709 <6>[ 0.276041] CPU features: detected: RCpc load-acquire (LDAPR)
10496 01:22:32.192155 <6>[ 0.282039] CPU features: detected: LSE atomic instructions
10497 01:22:32.198606 <6>[ 0.287821] CPU features: detected: Privileged Access Never
10498 01:22:32.205413 <6>[ 0.293601] CPU features: detected: RAS Extension Support
10499 01:22:32.211375 <6>[ 0.299210] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10500 01:22:32.215535 <6>[ 0.306450] CPU: All CPU(s) started at EL2
10501 01:22:32.221374 <6>[ 0.310767] alternatives: applying system-wide alternatives
10502 01:22:32.232370 <6>[ 0.321582] devtmpfs: initialized
10503 01:22:32.244650 <6>[ 0.330482] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10504 01:22:32.254408 <6>[ 0.340442] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10505 01:22:32.261739 <6>[ 0.348687] pinctrl core: initialized pinctrl subsystem
10506 01:22:32.264306 <6>[ 0.355392] DMI not present or invalid.
10507 01:22:32.271252 <6>[ 0.359802] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10508 01:22:32.281207 <6>[ 0.366697] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10509 01:22:32.287633 <6>[ 0.374285] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10510 01:22:32.297236 <6>[ 0.382519] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10511 01:22:32.300277 <6>[ 0.390758] audit: initializing netlink subsys (disabled)
10512 01:22:32.310727 <5>[ 0.396455] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10513 01:22:32.317000 <6>[ 0.397166] thermal_sys: Registered thermal governor 'step_wise'
10514 01:22:32.323824 <6>[ 0.404424] thermal_sys: Registered thermal governor 'power_allocator'
10515 01:22:32.326755 <6>[ 0.410680] cpuidle: using governor menu
10516 01:22:32.333674 <6>[ 0.421635] NET: Registered PF_QIPCRTR protocol family
10517 01:22:32.340016 <6>[ 0.427132] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10518 01:22:32.346614 <6>[ 0.434235] ASID allocator initialised with 32768 entries
10519 01:22:32.349904 <6>[ 0.440817] Serial: AMBA PL011 UART driver
10520 01:22:32.360339 <4>[ 0.449582] Trying to register duplicate clock ID: 134
10521 01:22:32.414819 <6>[ 0.507254] KASLR enabled
10522 01:22:32.429382 <6>[ 0.514947] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10523 01:22:32.435679 <6>[ 0.521962] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10524 01:22:32.442031 <6>[ 0.528451] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10525 01:22:32.448950 <6>[ 0.535456] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10526 01:22:32.455925 <6>[ 0.541944] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10527 01:22:32.462017 <6>[ 0.548948] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10528 01:22:32.468403 <6>[ 0.555436] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10529 01:22:32.474794 <6>[ 0.562442] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10530 01:22:32.478474 <6>[ 0.569956] ACPI: Interpreter disabled.
10531 01:22:32.487152 <6>[ 0.576376] iommu: Default domain type: Translated
10532 01:22:32.493622 <6>[ 0.581490] iommu: DMA domain TLB invalidation policy: strict mode
10533 01:22:32.497373 <5>[ 0.588147] SCSI subsystem initialized
10534 01:22:32.503340 <6>[ 0.592313] usbcore: registered new interface driver usbfs
10535 01:22:32.510076 <6>[ 0.598046] usbcore: registered new interface driver hub
10536 01:22:32.513280 <6>[ 0.603594] usbcore: registered new device driver usb
10537 01:22:32.520175 <6>[ 0.609688] pps_core: LinuxPPS API ver. 1 registered
10538 01:22:32.530412 <6>[ 0.614878] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10539 01:22:32.533442 <6>[ 0.624224] PTP clock support registered
10540 01:22:32.536749 <6>[ 0.628463] EDAC MC: Ver: 3.0.0
10541 01:22:32.544185 <6>[ 0.633612] FPGA manager framework
10542 01:22:32.550733 <6>[ 0.637291] Advanced Linux Sound Architecture Driver Initialized.
10543 01:22:32.554226 <6>[ 0.644069] vgaarb: loaded
10544 01:22:32.560902 <6>[ 0.647252] clocksource: Switched to clocksource arch_sys_counter
10545 01:22:32.564047 <5>[ 0.653693] VFS: Disk quotas dquot_6.6.0
10546 01:22:32.570866 <6>[ 0.657879] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10547 01:22:32.574167 <6>[ 0.665068] pnp: PnP ACPI: disabled
10548 01:22:32.582527 <6>[ 0.671772] NET: Registered PF_INET protocol family
10549 01:22:32.592651 <6>[ 0.677383] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10550 01:22:32.603625 <6>[ 0.689714] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10551 01:22:32.613466 <6>[ 0.698527] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10552 01:22:32.620564 <6>[ 0.706497] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10553 01:22:32.630092 <6>[ 0.715196] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10554 01:22:32.636742 <6>[ 0.724943] TCP: Hash tables configured (established 65536 bind 65536)
10555 01:22:32.643316 <6>[ 0.731802] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10556 01:22:32.653065 <6>[ 0.739002] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10557 01:22:32.659766 <6>[ 0.746679] NET: Registered PF_UNIX/PF_LOCAL protocol family
10558 01:22:32.666632 <6>[ 0.752845] RPC: Registered named UNIX socket transport module.
10559 01:22:32.669366 <6>[ 0.758999] RPC: Registered udp transport module.
10560 01:22:32.676397 <6>[ 0.763934] RPC: Registered tcp transport module.
10561 01:22:32.682899 <6>[ 0.768865] RPC: Registered tcp NFSv4.1 backchannel transport module.
10562 01:22:32.686378 <6>[ 0.775531] PCI: CLS 0 bytes, default 64
10563 01:22:32.688998 <6>[ 0.779870] Unpacking initramfs...
10564 01:22:32.713420 <6>[ 0.799370] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10565 01:22:32.723261 <6>[ 0.808020] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10566 01:22:32.726396 <6>[ 0.816856] kvm [1]: IPA Size Limit: 40 bits
10567 01:22:32.733066 <6>[ 0.821381] kvm [1]: GICv3: no GICV resource entry
10568 01:22:32.736510 <6>[ 0.826402] kvm [1]: disabling GICv2 emulation
10569 01:22:32.742783 <6>[ 0.831088] kvm [1]: GIC system register CPU interface enabled
10570 01:22:32.745812 <6>[ 0.837252] kvm [1]: vgic interrupt IRQ18
10571 01:22:32.752422 <6>[ 0.841610] kvm [1]: VHE mode initialized successfully
10572 01:22:32.758947 <5>[ 0.847935] Initialise system trusted keyrings
10573 01:22:32.766185 <6>[ 0.852772] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10574 01:22:32.773432 <6>[ 0.862759] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10575 01:22:32.780281 <5>[ 0.869158] NFS: Registering the id_resolver key type
10576 01:22:32.783256 <5>[ 0.874453] Key type id_resolver registered
10577 01:22:32.789897 <5>[ 0.878869] Key type id_legacy registered
10578 01:22:32.796802 <6>[ 0.883147] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10579 01:22:32.803020 <6>[ 0.890067] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10580 01:22:32.809935 <6>[ 0.897819] 9p: Installing v9fs 9p2000 file system support
10581 01:22:32.846640 <5>[ 0.936014] Key type asymmetric registered
10582 01:22:32.849784 <5>[ 0.940347] Asymmetric key parser 'x509' registered
10583 01:22:32.860244 <6>[ 0.945501] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10584 01:22:32.863236 <6>[ 0.953120] io scheduler mq-deadline registered
10585 01:22:32.866141 <6>[ 0.957894] io scheduler kyber registered
10586 01:22:32.885050 <6>[ 0.974770] EINJ: ACPI disabled.
10587 01:22:32.917645 <4>[ 1.000624] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10588 01:22:32.927488 <4>[ 1.011252] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10589 01:22:32.942636 <6>[ 1.031937] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10590 01:22:32.950429 <6>[ 1.039913] printk: console [ttyS0] disabled
10591 01:22:32.978245 <6>[ 1.064540] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10592 01:22:32.985256 <6>[ 1.074017] printk: console [ttyS0] enabled
10593 01:22:32.988446 <6>[ 1.074017] printk: console [ttyS0] enabled
10594 01:22:32.994933 <6>[ 1.082916] printk: bootconsole [mtk8250] disabled
10595 01:22:32.998171 <6>[ 1.082916] printk: bootconsole [mtk8250] disabled
10596 01:22:33.005458 <6>[ 1.093937] SuperH (H)SCI(F) driver initialized
10597 01:22:33.008606 <6>[ 1.099209] msm_serial: driver initialized
10598 01:22:33.021814 <6>[ 1.108125] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10599 01:22:33.031939 <6>[ 1.116673] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10600 01:22:33.038621 <6>[ 1.125214] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10601 01:22:33.048320 <6>[ 1.133845] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10602 01:22:33.058001 <6>[ 1.142555] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10603 01:22:33.064616 <6>[ 1.151268] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10604 01:22:33.074474 <6>[ 1.159808] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10605 01:22:33.084308 <6>[ 1.168601] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10606 01:22:33.090985 <6>[ 1.177142] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10607 01:22:33.103568 <6>[ 1.192818] loop: module loaded
10608 01:22:33.110529 <6>[ 1.198756] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10609 01:22:33.132811 <4>[ 1.222166] mtk-pmic-keys: Failed to locate of_node [id: -1]
10610 01:22:33.139835 <6>[ 1.228993] megasas: 07.719.03.00-rc1
10611 01:22:33.149210 <6>[ 1.238712] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10612 01:22:33.157997 <6>[ 1.246633] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10613 01:22:33.174161 <6>[ 1.263256] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10614 01:22:33.234442 <6>[ 1.316993] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10615 01:22:33.481867 <6>[ 1.571437] Freeing initrd memory: 18332K
10616 01:22:33.493519 <6>[ 1.582866] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10617 01:22:33.505061 <6>[ 1.593889] tun: Universal TUN/TAP device driver, 1.6
10618 01:22:33.507667 <6>[ 1.599973] thunder_xcv, ver 1.0
10619 01:22:33.511641 <6>[ 1.603478] thunder_bgx, ver 1.0
10620 01:22:33.514112 <6>[ 1.606967] nicpf, ver 1.0
10621 01:22:33.525035 <6>[ 1.611008] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10622 01:22:33.528784 <6>[ 1.618484] hns3: Copyright (c) 2017 Huawei Corporation.
10623 01:22:33.535246 <6>[ 1.624073] hclge is initializing
10624 01:22:33.538443 <6>[ 1.627655] e1000: Intel(R) PRO/1000 Network Driver
10625 01:22:33.544917 <6>[ 1.632784] e1000: Copyright (c) 1999-2006 Intel Corporation.
10626 01:22:33.548586 <6>[ 1.638799] e1000e: Intel(R) PRO/1000 Network Driver
10627 01:22:33.554785 <6>[ 1.644015] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10628 01:22:33.561774 <6>[ 1.650201] igb: Intel(R) Gigabit Ethernet Network Driver
10629 01:22:33.567744 <6>[ 1.655851] igb: Copyright (c) 2007-2014 Intel Corporation.
10630 01:22:33.574531 <6>[ 1.661687] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10631 01:22:33.581149 <6>[ 1.668204] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10632 01:22:33.584564 <6>[ 1.674668] sky2: driver version 1.30
10633 01:22:33.590661 <6>[ 1.679665] VFIO - User Level meta-driver version: 0.3
10634 01:22:33.599175 <6>[ 1.687871] usbcore: registered new interface driver usb-storage
10635 01:22:33.605184 <6>[ 1.694316] usbcore: registered new device driver onboard-usb-hub
10636 01:22:33.613998 <6>[ 1.703479] mt6397-rtc mt6359-rtc: registered as rtc0
10637 01:22:33.623886 <6>[ 1.708944] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-23T01:22:33 UTC (1713835353)
10638 01:22:33.627101 <6>[ 1.718508] i2c_dev: i2c /dev entries driver
10639 01:22:33.644524 <6>[ 1.730281] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10640 01:22:33.650651 <4>[ 1.739009] cpu cpu0: supply cpu not found, using dummy regulator
10641 01:22:33.657951 <4>[ 1.745433] cpu cpu1: supply cpu not found, using dummy regulator
10642 01:22:33.663918 <4>[ 1.751830] cpu cpu2: supply cpu not found, using dummy regulator
10643 01:22:33.670832 <4>[ 1.758253] cpu cpu3: supply cpu not found, using dummy regulator
10644 01:22:33.677584 <4>[ 1.764646] cpu cpu4: supply cpu not found, using dummy regulator
10645 01:22:33.683805 <4>[ 1.771046] cpu cpu5: supply cpu not found, using dummy regulator
10646 01:22:33.690445 <4>[ 1.777444] cpu cpu6: supply cpu not found, using dummy regulator
10647 01:22:33.696857 <4>[ 1.783844] cpu cpu7: supply cpu not found, using dummy regulator
10648 01:22:33.715247 <6>[ 1.804493] cpu cpu0: EM: created perf domain
10649 01:22:33.718553 <6>[ 1.809428] cpu cpu4: EM: created perf domain
10650 01:22:33.725373 <6>[ 1.815094] sdhci: Secure Digital Host Controller Interface driver
10651 01:22:33.732560 <6>[ 1.821527] sdhci: Copyright(c) Pierre Ossman
10652 01:22:33.739330 <6>[ 1.826483] Synopsys Designware Multimedia Card Interface Driver
10653 01:22:33.745880 <6>[ 1.833120] sdhci-pltfm: SDHCI platform and OF driver helper
10654 01:22:33.749151 <6>[ 1.833163] mmc0: CQHCI version 5.10
10655 01:22:33.756011 <6>[ 1.843158] ledtrig-cpu: registered to indicate activity on CPUs
10656 01:22:33.761968 <6>[ 1.850277] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10657 01:22:33.768909 <6>[ 1.857338] usbcore: registered new interface driver usbhid
10658 01:22:33.772417 <6>[ 1.863165] usbhid: USB HID core driver
10659 01:22:33.778733 <6>[ 1.867369] spi_master spi0: will run message pump with realtime priority
10660 01:22:33.824984 <6>[ 1.908066] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10661 01:22:33.843699 <6>[ 1.923166] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10662 01:22:33.850867 <6>[ 1.938920] cros-ec-spi spi0.0: Chrome EC device registered
10663 01:22:33.854200 <6>[ 1.944906] mmc0: Command Queue Engine enabled
10664 01:22:33.860815 <6>[ 1.949665] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10665 01:22:33.868110 <6>[ 1.957455] mmcblk0: mmc0:0001 DA4128 116 GiB
10666 01:22:33.878127 <6>[ 1.957963] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10667 01:22:33.881279 <6>[ 1.967089] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10668 01:22:33.887994 <6>[ 1.972613] NET: Registered PF_PACKET protocol family
10669 01:22:33.894546 <6>[ 1.978696] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10670 01:22:33.897743 <6>[ 1.982789] 9pnet: Installing 9P2000 support
10671 01:22:33.904747 <6>[ 1.988601] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10672 01:22:33.907956 <5>[ 1.992478] Key type dns_resolver registered
10673 01:22:33.914266 <6>[ 1.998298] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10674 01:22:33.917660 <6>[ 2.002751] registered taskstats version 1
10675 01:22:33.923800 <5>[ 2.013074] Loading compiled-in X.509 certificates
10676 01:22:33.951738 <4>[ 2.034294] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10677 01:22:33.961253 <4>[ 2.044983] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10678 01:22:33.968067 <3>[ 2.055508] debugfs: File 'uA_load' in directory '/' already present!
10679 01:22:33.974405 <3>[ 2.062207] debugfs: File 'min_uV' in directory '/' already present!
10680 01:22:33.981455 <3>[ 2.068814] debugfs: File 'max_uV' in directory '/' already present!
10681 01:22:33.988059 <3>[ 2.075478] debugfs: File 'constraint_flags' in directory '/' already present!
10682 01:22:33.998666 <3>[ 2.085001] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10683 01:22:34.008429 <6>[ 2.097959] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10684 01:22:34.015467 <6>[ 2.104816] xhci-mtk 11200000.usb: xHCI Host Controller
10685 01:22:34.022032 <6>[ 2.110308] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10686 01:22:34.031997 <6>[ 2.118174] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10687 01:22:34.038859 <6>[ 2.127608] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10688 01:22:34.045115 <6>[ 2.133693] xhci-mtk 11200000.usb: xHCI Host Controller
10689 01:22:34.052681 <6>[ 2.139177] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10690 01:22:34.058505 <6>[ 2.146841] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10691 01:22:34.065656 <6>[ 2.154384] hub 1-0:1.0: USB hub found
10692 01:22:34.068640 <6>[ 2.158392] hub 1-0:1.0: 1 port detected
10693 01:22:34.075300 <6>[ 2.162642] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10694 01:22:34.081979 <6>[ 2.171283] hub 2-0:1.0: USB hub found
10695 01:22:34.085143 <6>[ 2.175294] hub 2-0:1.0: 1 port detected
10696 01:22:34.094147 <6>[ 2.183479] mtk-msdc 11f70000.mmc: Got CD GPIO
10697 01:22:34.104274 <6>[ 2.190228] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10698 01:22:34.110754 <6>[ 2.198256] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10699 01:22:34.121096 <4>[ 2.206176] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10700 01:22:34.130585 <6>[ 2.215703] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10701 01:22:34.137493 <6>[ 2.223779] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10702 01:22:34.143881 <6>[ 2.231872] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10703 01:22:34.153581 <6>[ 2.239839] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10704 01:22:34.160381 <6>[ 2.247659] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10705 01:22:34.170070 <6>[ 2.255476] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10706 01:22:34.179835 <6>[ 2.265982] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10707 01:22:34.186634 <6>[ 2.274373] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10708 01:22:34.196699 <6>[ 2.282715] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10709 01:22:34.206720 <6>[ 2.291053] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10710 01:22:34.213100 <6>[ 2.299392] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10711 01:22:34.223485 <6>[ 2.307734] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10712 01:22:34.229458 <6>[ 2.316073] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10713 01:22:34.239636 <6>[ 2.324410] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10714 01:22:34.246130 <6>[ 2.332748] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10715 01:22:34.256697 <6>[ 2.341086] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10716 01:22:34.262826 <6>[ 2.349427] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10717 01:22:34.272696 <6>[ 2.357766] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10718 01:22:34.279226 <6>[ 2.366104] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10719 01:22:34.289171 <6>[ 2.374444] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10720 01:22:34.295978 <6>[ 2.382783] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10721 01:22:34.302187 <6>[ 2.391661] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10722 01:22:34.309200 <6>[ 2.399002] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10723 01:22:34.316147 <6>[ 2.405811] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10724 01:22:34.326371 <6>[ 2.412718] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10725 01:22:34.333104 <6>[ 2.419762] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10726 01:22:34.343092 <6>[ 2.426646] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10727 01:22:34.350004 <6>[ 2.435776] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10728 01:22:34.359105 <6>[ 2.444895] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10729 01:22:34.369460 <6>[ 2.454191] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10730 01:22:34.379441 <6>[ 2.463659] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10731 01:22:34.388760 <6>[ 2.473127] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10732 01:22:34.398835 <6>[ 2.482246] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10733 01:22:34.405861 <6>[ 2.491713] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10734 01:22:34.415416 <6>[ 2.500833] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10735 01:22:34.425077 <6>[ 2.510127] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10736 01:22:34.434944 <6>[ 2.520287] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10737 01:22:34.445788 <6>[ 2.531837] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10738 01:22:34.452269 <6>[ 2.541552] Trying to probe devices needed for running init ...
10739 01:22:34.497852 <6>[ 2.583527] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10740 01:22:34.652016 <6>[ 2.741435] hub 1-1:1.0: USB hub found
10741 01:22:34.655082 <6>[ 2.745838] hub 1-1:1.0: 4 ports detected
10742 01:22:34.664132 <6>[ 2.753723] hub 1-1:1.0: USB hub found
10743 01:22:34.667208 <6>[ 2.758049] hub 1-1:1.0: 4 ports detected
10744 01:22:34.777628 <6>[ 2.863860] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10745 01:22:34.803848 <6>[ 2.893340] hub 2-1:1.0: USB hub found
10746 01:22:34.806875 <6>[ 2.897859] hub 2-1:1.0: 3 ports detected
10747 01:22:34.816730 <6>[ 2.905936] hub 2-1:1.0: USB hub found
10748 01:22:34.819768 <6>[ 2.910390] hub 2-1:1.0: 3 ports detected
10749 01:22:34.993298 <6>[ 3.079568] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10750 01:22:35.125437 <6>[ 3.214980] hub 1-1.4:1.0: USB hub found
10751 01:22:35.128589 <6>[ 3.219597] hub 1-1.4:1.0: 2 ports detected
10752 01:22:35.139159 <6>[ 3.228110] hub 1-1.4:1.0: USB hub found
10753 01:22:35.141708 <6>[ 3.232820] hub 1-1.4:1.0: 2 ports detected
10754 01:22:35.205534 <6>[ 3.291776] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10755 01:22:35.437199 <6>[ 3.523568] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10756 01:22:35.629204 <6>[ 3.715536] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10757 01:22:46.738726 <6>[ 14.832582] ALSA device list:
10758 01:22:46.744878 <6>[ 14.835875] No soundcards found.
10759 01:22:46.753209 <6>[ 14.843796] Freeing unused kernel memory: 8448K
10760 01:22:46.756377 <6>[ 14.849263] Run /init as init process
10761 01:22:46.767404 Loading, please wait...
10762 01:22:46.792008 Starting systemd-udevd version 252.22-1~deb12u1
10763 01:22:46.792682
10764 01:22:47.046789 <6>[ 15.133983] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10765 01:22:47.056091 <6>[ 15.142041] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10766 01:22:47.062929 <6>[ 15.150964] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10767 01:22:47.075426 <3>[ 15.163164] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10768 01:22:47.082526 <6>[ 15.165060] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10769 01:22:47.091970 <3>[ 15.172108] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10770 01:22:47.095570 <6>[ 15.181678] remoteproc remoteproc0: scp is available
10771 01:22:47.105222 <3>[ 15.186840] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10772 01:22:47.112152 <4>[ 15.188433] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10773 01:22:47.118758 <6>[ 15.188811] usbcore: registered new device driver r8152-cfgselector
10774 01:22:47.125567 <4>[ 15.192237] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10775 01:22:47.132290 <6>[ 15.192480] remoteproc remoteproc0: powering up scp
10776 01:22:47.138864 <6>[ 15.192535] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10777 01:22:47.144921 <6>[ 15.192684] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10778 01:22:47.151761 <3>[ 15.200523] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10779 01:22:47.158773 <6>[ 15.208235] mc: Linux media interface: v0.10
10780 01:22:47.164559 <3>[ 15.214076] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10781 01:22:47.174739 <3>[ 15.261306] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10782 01:22:47.181053 <3>[ 15.269444] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10783 01:22:47.187878 <6>[ 15.270234] videodev: Linux video capture interface: v2.00
10784 01:22:47.193948 <3>[ 15.277531] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10785 01:22:47.204302 <3>[ 15.283137] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10786 01:22:47.210977 <6>[ 15.284677] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10787 01:22:47.217205 <6>[ 15.292445] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10788 01:22:47.227532 <3>[ 15.296219] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10789 01:22:47.234203 <3>[ 15.296237] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10790 01:22:47.243868 <3>[ 15.296245] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10791 01:22:47.250114 <3>[ 15.301237] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10792 01:22:47.257055 <6>[ 15.307225] pci_bus 0000:00: root bus resource [bus 00-ff]
10793 01:22:47.263374 <6>[ 15.307238] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10794 01:22:47.273500 <6>[ 15.307248] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10795 01:22:47.280179 <6>[ 15.307332] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10796 01:22:47.286687 <6>[ 15.307348] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10797 01:22:47.296376 <3>[ 15.314386] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10798 01:22:47.302997 <6>[ 15.318101] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10799 01:22:47.310301 <6>[ 15.318141] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10800 01:22:47.316536 <6>[ 15.318149] remoteproc remoteproc0: remote processor scp is now up
10801 01:22:47.322972 <6>[ 15.322352] pci 0000:00:00.0: supports D1 D2
10802 01:22:47.332913 <6>[ 15.327539] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10803 01:22:47.339426 <3>[ 15.330375] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10804 01:22:47.346051 <6>[ 15.338490] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10805 01:22:47.356029 <3>[ 15.346528] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10806 01:22:47.362688 <6>[ 15.353375] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10807 01:22:47.369463 <3>[ 15.359547] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10808 01:22:47.379248 <3>[ 15.359584] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10809 01:22:47.386055 <6>[ 15.363638] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10810 01:22:47.392485 <6>[ 15.369560] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10811 01:22:47.401918 <6>[ 15.372858] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10812 01:22:47.412019 <6>[ 15.373169] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10813 01:22:47.422099 <6>[ 15.385880] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10814 01:22:47.428770 <4>[ 15.387778] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10815 01:22:47.438564 <4>[ 15.387788] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10816 01:22:47.445259 <6>[ 15.391344] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10817 01:22:47.454968 <6>[ 15.401313] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10818 01:22:47.461402 <6>[ 15.406927] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10819 01:22:47.464502 <6>[ 15.418938] Bluetooth: Core ver 2.22
10820 01:22:47.471932 <6>[ 15.420204] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10821 01:22:47.484713 <6>[ 15.421374] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10822 01:22:47.491335 <6>[ 15.421517] usbcore: registered new interface driver uvcvideo
10823 01:22:47.497624 <6>[ 15.427193] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10824 01:22:47.504524 <6>[ 15.435431] NET: Registered PF_BLUETOOTH protocol family
10825 01:22:47.507483 <6>[ 15.439466] r8152 2-1.3:1.0 eth0: v1.12.13
10826 01:22:47.514474 <6>[ 15.439521] usbcore: registered new interface driver r8152
10827 01:22:47.517517 <6>[ 15.442279] pci 0000:01:00.0: supports D1 D2
10828 01:22:47.524276 <6>[ 15.450235] Bluetooth: HCI device and connection manager initialized
10829 01:22:47.530813 <6>[ 15.450516] usbcore: registered new interface driver cdc_ether
10830 01:22:47.537501 <6>[ 15.458491] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10831 01:22:47.543867 <6>[ 15.458806] usbcore: registered new interface driver r8153_ecm
10832 01:22:47.550749 <6>[ 15.459112] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10833 01:22:47.553539 <6>[ 15.466684] Bluetooth: HCI socket layer initialized
10834 01:22:47.560843 <6>[ 15.476220] r8152 2-1.3:1.0 enx00e04c680281: renamed from eth0
10835 01:22:47.567317 <6>[ 15.482979] Bluetooth: L2CAP socket layer initialized
10836 01:22:47.570689 <6>[ 15.482991] Bluetooth: SCO socket layer initialized
10837 01:22:47.577158 <6>[ 15.487344] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10838 01:22:47.584011 <6>[ 15.541661] usbcore: registered new interface driver btusb
10839 01:22:47.593915 <4>[ 15.542659] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10840 01:22:47.600305 <3>[ 15.542665] Bluetooth: hci0: Failed to load firmware file (-2)
10841 01:22:47.607211 <3>[ 15.542667] Bluetooth: hci0: Failed to set up firmware (-2)
10842 01:22:47.616801 <4>[ 15.542670] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10843 01:22:47.626724 <6>[ 15.549494] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10844 01:22:47.633190 <6>[ 15.721081] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10845 01:22:47.639883 <6>[ 15.729091] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10846 01:22:47.650277 <6>[ 15.737109] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10847 01:22:47.656041 <6>[ 15.745121] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10848 01:22:47.662896 <6>[ 15.753133] pci 0000:00:00.0: PCI bridge to [bus 01]
10849 01:22:47.669422 <6>[ 15.758363] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10850 01:22:47.675846 <6>[ 15.766516] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10851 01:22:47.682361 <6>[ 15.773609] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10852 01:22:47.688826 <6>[ 15.780168] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10853 01:22:47.710957 <4>[ 15.798343] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10854 01:22:47.717395 <4>[ 15.798343] Fallback method does not support PEC.
10855 01:22:47.723698 <5>[ 15.799118] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10856 01:22:47.740681 <3>[ 15.828417] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10857 01:22:47.747446 <5>[ 15.831311] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10858 01:22:47.757535 <5>[ 15.845028] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10859 01:22:47.768521 <4>[ 15.853506] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10860 01:22:47.774463 <3>[ 15.857512] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10861 01:22:47.780929 <6>[ 15.862407] cfg80211: failed to load regulatory.db
10862 01:22:47.835818 <6>[ 15.923327] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10863 01:22:47.842210 <6>[ 15.930861] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10864 01:22:47.866659 <6>[ 15.957648] mt7921e 0000:01:00.0: ASIC revision: 79610010
10865 01:22:47.972406 <6>[ 16.060172] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10866 01:22:47.975707 <6>[ 16.060172]
10867 01:22:47.988992 Begin: Loading essential drivers ... done.
10868 01:22:47.992501 Begin: Running /scripts/init-premount ... done.
10869 01:22:47.999005 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10870 01:22:48.008914 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10871 01:22:48.012450 Device /sys/class/net/enx00e04c680281 found
10872 01:22:48.012973 done.
10873 01:22:48.036804 Begin: Waiting up to 180 secs for any network device to become available ... done.
10874 01:22:48.095937 IP-Config: enx00e04c680281 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10875 01:22:48.238299 <6>[ 16.326368] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10876 01:22:48.930526 <6>[ 17.021671] r8152 2-1.3:1.0 enx00e04c680281: carrier on
10877 01:22:49.092458 <6>[ 17.183399] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10878 01:22:49.117757 IP-Config: no response after 2 secs - giving up
10879 01:22:49.160546 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:47 mtu 1500 DHCP
10880 01:22:49.831950 IP-Config: enx00e04c680281 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10881 01:22:49.834658 IP-Config: enx00e04c680281 complete (dhcp from 192.168.201.1):
10882 01:22:49.844895 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10883 01:22:49.850726 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10884 01:22:49.857700 host : mt8192-asurada-spherion-r0-cbg-9
10885 01:22:49.864154 domain : lava-rack
10886 01:22:49.867415 rootserver: 192.168.201.1 rootpath:
10887 01:22:49.867887 filename :
10888 01:22:49.967048 done.
10889 01:22:49.976281 Begin: Running /scripts/nfs-bottom ... done.
10890 01:22:49.990663 Begin: Running /scripts/init-bottom ... done.
10891 01:22:51.364081 <6>[ 19.455585] NET: Registered PF_INET6 protocol family
10892 01:22:51.372017 <6>[ 19.463334] Segment Routing with IPv6
10893 01:22:51.374958 <6>[ 19.467319] In-situ OAM (IOAM) with IPv6
10894 01:22:51.584012 <30>[ 19.649119] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10895 01:22:51.590871 <30>[ 19.682384] systemd[1]: Detected architecture arm64.
10896 01:22:51.611378
10897 01:22:51.614181 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10898 01:22:51.614615
10899 01:22:51.615047
10900 01:22:51.637739 <30>[ 19.729318] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10901 01:22:52.846610 <30>[ 20.934843] systemd[1]: Queued start job for default target graphical.target.
10902 01:22:52.884416 <30>[ 20.972729] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10903 01:22:52.891232 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10904 01:22:52.891783
10905 01:22:52.913060 <30>[ 21.001331] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10906 01:22:52.922534 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10907 01:22:52.923022
10908 01:22:52.941047 <30>[ 21.029245] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10909 01:22:52.951127 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10910 01:22:52.951703
10911 01:22:52.969515 <30>[ 21.057634] systemd[1]: Created slice user.slice - User and Session Slice.
10912 01:22:52.976060 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10913 01:22:52.976640
10914 01:22:52.999202 <30>[ 21.084409] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10915 01:22:53.009435 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10916 01:22:53.010010
10917 01:22:53.026975 <30>[ 21.111781] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10918 01:22:53.033703 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10919 01:22:53.034235
10920 01:22:53.061396 <30>[ 21.140197] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10921 01:22:53.071884 <30>[ 21.160108] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10922 01:22:53.078100 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10923 01:22:53.078581
10924 01:22:53.095832 <30>[ 21.183846] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10925 01:22:53.105931 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10926 01:22:53.106520
10927 01:22:53.124144 <30>[ 21.212074] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10928 01:22:53.133697 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10929 01:22:53.134301
10930 01:22:53.148263 <30>[ 21.239642] systemd[1]: Reached target paths.target - Path Units.
10931 01:22:53.155314 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10932 01:22:53.157889
10933 01:22:53.176186 <30>[ 21.264029] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10934 01:22:53.181983 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10935 01:22:53.182462
10936 01:22:53.199407 <30>[ 21.287543] systemd[1]: Reached target slices.target - Slice Units.
10937 01:22:53.205849 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10938 01:22:53.206419
10939 01:22:53.220437 <30>[ 21.311938] systemd[1]: Reached target swap.target - Swaps.
10940 01:22:53.226974 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10941 01:22:53.227470
10942 01:22:53.247966 <30>[ 21.336059] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10943 01:22:53.257552 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10944 01:22:53.258037
10945 01:22:53.276019 <30>[ 21.364072] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10946 01:22:53.285809 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10947 01:22:53.286387
10948 01:22:53.307469 <30>[ 21.395790] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10949 01:22:53.317694 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10950 01:22:53.318274
10951 01:22:53.337093 <30>[ 21.425257] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10952 01:22:53.346589 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10953 01:22:53.347160
10954 01:22:53.363704 <30>[ 21.452227] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10955 01:22:53.370471 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10956 01:22:53.371028
10957 01:22:53.389263 <30>[ 21.477355] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10958 01:22:53.399203 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10959 01:22:53.399778
10960 01:22:53.419758 <30>[ 21.508280] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10961 01:22:53.429910 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10962 01:22:53.430397
10963 01:22:53.447877 <30>[ 21.536064] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10964 01:22:53.457586 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10965 01:22:53.458324
10966 01:22:53.508096 <30>[ 21.596109] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10967 01:22:53.514255 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10968 01:22:53.514767
10969 01:22:53.537680 <30>[ 21.626150] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10970 01:22:53.544217 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10971 01:22:53.544794
10972 01:22:53.595751 <30>[ 21.683678] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10973 01:22:53.601823 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10974 01:22:53.602300
10975 01:22:53.626237 <30>[ 21.708149] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10976 01:22:53.641972 <30>[ 21.730508] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10977 01:22:53.652062 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10978 01:22:53.652511
10979 01:22:53.676873 <30>[ 21.765338] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10980 01:22:53.686933 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10981 01:22:53.687424
10982 01:22:53.708665 <30>[ 21.797035] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10983 01:22:53.718685 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10984 01:22:53.719134
10985 01:22:53.741403 <30>[ 21.829796] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10986 01:22:53.747666 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10987 01:22:53.748107
10988 01:22:53.760804 <6>[ 21.849403] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10989 01:22:53.776105 <30>[ 21.864675] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10990 01:22:53.786225 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10991 01:22:53.786682
10992 01:22:53.808679 <30>[ 21.897411] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10993 01:22:53.815437 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10994 01:22:53.815887
10995 01:22:53.841290 <30>[ 21.929495] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10996 01:22:53.847475 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10997 01:22:53.847955
10998 01:22:53.853827 <6>[ 21.945382] fuse: init (API version 7.37)
10999 01:22:53.876894 <30>[ 21.965303] systemd[1]: Starting systemd-journald.service - Journal Service...
11000 01:22:53.883174 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
11001 01:22:53.883617
11002 01:22:53.916935 <30>[ 22.005289] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
11003 01:22:53.923410 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
11004 01:22:53.923858
11005 01:22:53.951970 <30>[ 22.037740] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
11006 01:22:53.958633 Starting [0;1;39msystemd-network-g… units from Kernel command line...
11007 01:22:53.958813
11008 01:22:53.986100 <30>[ 22.074216] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
11009 01:22:53.995529 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
11010 01:22:53.996005
11011 01:22:54.017255 <30>[ 22.105852] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
11012 01:22:54.023833 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
11013 01:22:54.027352
11014 01:22:54.050030 <3>[ 22.138317] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11015 01:22:54.056540 <30>[ 22.143837] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
11016 01:22:54.071746 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
11017 01:22:54.072195
11018 01:22:54.081222 <3>[ 22.168437] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11019 01:22:54.088271 <30>[ 22.178185] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
11020 01:22:54.097655 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
11021 01:22:54.098104
11022 01:22:54.119861 <3>[ 22.207692] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11023 01:22:54.129427 <30>[ 22.207961] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
11024 01:22:54.135680 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
11025 01:22:54.136128
11026 01:22:54.150766 <3>[ 22.239129] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11027 01:22:54.161437 <30>[ 22.249546] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
11028 01:22:54.170824 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
11029 01:22:54.171339
11030 01:22:54.183894 <3>[ 22.272346] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11031 01:22:54.195086 <30>[ 22.283192] systemd[1]: modprobe@configfs.service: Deactivated successfully.
11032 01:22:54.204765 <30>[ 22.292021] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
11033 01:22:54.219059 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Modu<3>[ 22.306868] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11034 01:22:54.221998 le configfs.
11035 01:22:54.222471
11036 01:22:54.240891 <30>[ 22.328690] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
11037 01:22:54.247334 <30>[ 22.336540] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
11038 01:22:54.257426 <3>[ 22.343058] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11039 01:22:54.266764 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
11040 01:22:54.267353
11041 01:22:54.285407 <30>[ 22.373782] systemd[1]: modprobe@drm.service: Deactivated successfully.
11042 01:22:54.292252 <30>[ 22.382370] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
11043 01:22:54.302469 <3>[ 22.386140] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11044 01:22:54.309063 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
11045 01:22:54.309705
11046 01:22:54.330158 <30>[ 22.417912] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
11047 01:22:54.337453 <3>[ 22.424663] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11048 01:22:54.346951 <30>[ 22.426495] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
11049 01:22:54.356423 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11050 01:22:54.357026
11051 01:22:54.368706 <3>[ 22.457210] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11052 01:22:54.379693 <30>[ 22.468200] systemd[1]: modprobe@fuse.service: Deactivated successfully.
11053 01:22:54.385910 <30>[ 22.476396] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
11054 01:22:54.396477 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11055 01:22:54.397060
11056 01:22:54.421051 <30>[ 22.509843] systemd[1]: modprobe@loop.service: Deactivated successfully.
11057 01:22:54.427988 <30>[ 22.518158] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
11058 01:22:54.438224 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11059 01:22:54.438703
11060 01:22:54.460755 <30>[ 22.548778] systemd[1]: Started systemd-journald.service - Journal Service.
11061 01:22:54.466817 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11062 01:22:54.467399
11063 01:22:54.492951 <4>[ 22.574943] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11064 01:22:54.502999 <3>[ 22.590656] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11065 01:22:54.509911 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11066 01:22:54.510504
11067 01:22:54.533731 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11068 01:22:54.534349
11069 01:22:54.553397 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11070 01:22:54.553979
11071 01:22:54.576615 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11072 01:22:54.577191
11073 01:22:54.602165 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11074 01:22:54.602748
11075 01:22:54.651596 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11076 01:22:54.652339
11077 01:22:54.676717 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11078 01:22:54.677210
11079 01:22:54.703289 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11080 01:22:54.703787
11081 01:22:54.729100 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11082 01:22:54.729664
11083 01:22:54.765561 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11084 01:22:54.765999
11085 01:22:54.776819 <46>[ 22.865461] systemd-journald[305]: Received client request to flush runtime journal.
11086 01:22:54.795721 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11087 01:22:54.796160
11088 01:22:54.839588 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11089 01:22:54.840161
11090 01:22:54.860514 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11091 01:22:54.861076
11092 01:22:54.881167 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11093 01:22:54.881714
11094 01:22:55.558317 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11095 01:22:55.558478
11096 01:22:55.914823 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11097 01:22:55.915050
11098 01:22:55.968339 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11099 01:22:55.968460
11100 01:22:56.218314 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11101 01:22:56.218504
11102 01:22:56.333281 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11103 01:22:56.333903
11104 01:22:56.355943 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11105 01:22:56.356520
11106 01:22:56.374946 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11107 01:22:56.375562
11108 01:22:56.439325 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11109 01:22:56.439884
11110 01:22:56.461661 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11111 01:22:56.462255
11112 01:22:56.710266 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11113 01:22:56.710786
11114 01:22:56.780464 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11115 01:22:56.780946
11116 01:22:56.823150 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11117 01:22:56.823667
11118 01:22:57.138279 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11119 01:22:57.138955
11120 01:22:57.180934 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11121 01:22:57.181541
11122 01:22:57.245106 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11123 01:22:57.245217
11124 01:22:57.338383 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11125 01:22:57.338940
11126 01:22:57.359952 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11127 01:22:57.360474
11128 01:22:57.415542 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11129 01:22:57.416153
11130 01:22:57.436166 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11131 01:22:57.436637
11132 01:22:57.459382 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11133 01:22:57.459904
11134 01:22:57.472576 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11135 01:22:57.473064
11136 01:22:57.523576 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11137 01:22:57.524087
11138 01:22:57.548859 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11139 01:22:57.549297
11140 01:22:57.568117 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11141 01:22:57.568553
11142 01:22:57.605766 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11143 01:22:57.606339
11144 01:22:57.706685 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11145 01:22:57.707187
11146 01:22:57.726939 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11147 01:22:57.727370
11148 01:22:57.747383 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11149 01:22:57.747815
11150 01:22:57.766566 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11151 01:22:57.767119
11152 01:22:57.792947 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11153 01:22:57.793562
11154 01:22:57.814985 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11155 01:22:57.815562
11156 01:22:57.831612 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11157 01:22:57.832190
11158 01:22:57.851100 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11159 01:22:57.851656
11160 01:22:57.871244 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11161 01:22:57.871819
11162 01:22:57.886899 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11163 01:22:57.887660
11164 01:22:57.905617 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11165 01:22:57.906184
11166 01:22:57.923201 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11167 01:22:57.923770
11168 01:22:57.929399 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11169 01:22:57.930145
11170 01:22:57.983020 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11171 01:22:57.986325
11172 01:22:58.064257 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11173 01:22:58.064710
11174 01:22:58.171477 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11175 01:22:58.171946
11176 01:22:58.200403 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11177 01:22:58.200837
11178 01:22:58.290617 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11179 01:22:58.290725
11180 01:22:58.344574 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11181 01:22:58.344664
11182 01:22:58.365991 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11183 01:22:58.366078
11184 01:22:58.387511 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11185 01:22:58.387596
11186 01:22:58.425449 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11187 01:22:58.425966
11188 01:22:58.447722 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11189 01:22:58.448190
11190 01:22:58.491326 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11191 01:22:58.491893
11192 01:22:58.511426 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11193 01:22:58.511919
11194 01:22:58.530293 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11195 01:22:58.530827
11196 01:22:58.582634 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11197 01:22:58.583218
11198 01:22:58.605069 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11199 01:22:58.605537
11200 01:22:58.671895 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11201 01:22:58.672488
11202 01:22:58.750765 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11203 01:22:58.751349
11204 01:22:58.829937
11205 01:22:58.830448
11206 01:22:58.833205 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11207 01:22:58.833721
11208 01:22:58.836817 debian-bookworm-arm64 login: root (automatic login)
11209 01:22:58.837238
11210 01:22:58.837624
11211 01:22:59.198355 Linux debian-bookworm-arm64 6.1.86-cip19 #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024 aarch64
11212 01:22:59.198904
11213 01:22:59.205124 The programs included with the Debian GNU/Linux system are free software;
11214 01:22:59.211655 the exact distribution terms for each program are described in the
11215 01:22:59.214917 individual files in /usr/share/doc/*/copyright.
11216 01:22:59.215339
11217 01:22:59.221419 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11218 01:22:59.224705 permitted by applicable law.
11219 01:23:00.384730 Matched prompt #10: / #
11221 01:23:00.386134 Setting prompt string to ['/ #']
11222 01:23:00.386572 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11224 01:23:00.387636 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11225 01:23:00.388085 start: 2.2.6 expect-shell-connection (timeout 00:03:01) [common]
11226 01:23:00.388441 Setting prompt string to ['/ #']
11227 01:23:00.388609 Forcing a shell prompt, looking for ['/ #']
11229 01:23:00.438912 / #
11230 01:23:00.439310 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11231 01:23:00.439593 Waiting using forced prompt support (timeout 00:02:30)
11232 01:23:00.444662
11233 01:23:00.445457 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11234 01:23:00.445818 start: 2.2.7 export-device-env (timeout 00:03:01) [common]
11236 01:23:00.546869 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13468763/extract-nfsrootfs-bow5lg9n'
11237 01:23:00.553108 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13468763/extract-nfsrootfs-bow5lg9n'
11239 01:23:00.654826 / # export NFS_SERVER_IP='192.168.201.1'
11240 01:23:00.661138 export NFS_SERVER_IP='192.168.201.1'
11241 01:23:00.662118 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11242 01:23:00.662645 end: 2.2 depthcharge-retry (duration 00:01:59) [common]
11243 01:23:00.663154 end: 2 depthcharge-action (duration 00:01:59) [common]
11244 01:23:00.663649 start: 3 lava-test-retry (timeout 00:07:21) [common]
11245 01:23:00.664129 start: 3.1 lava-test-shell (timeout 00:07:21) [common]
11246 01:23:00.664576 Using namespace: common
11248 01:23:00.765895 / # #
11249 01:23:00.766537 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11250 01:23:00.772099 #
11251 01:23:00.772856 Using /lava-13468763
11253 01:23:00.874064 / # export SHELL=/bin/bash
11254 01:23:00.880427 export SHELL=/bin/bash
11256 01:23:00.982145 / # . /lava-13468763/environment
11257 01:23:00.988263 . /lava-13468763/environment
11259 01:23:01.097016 / # /lava-13468763/bin/lava-test-runner /lava-13468763/0
11260 01:23:01.097720 Test shell timeout: 10s (minimum of the action and connection timeout)
11261 01:23:01.103165 /lava-13468763/bin/lava-test-runner /lava-13468763/0
11262 01:23:01.421101 + export TESTRUN_ID=0_timesync-off
11263 01:23:01.424478 + TESTRUN_ID=0_timesync-off
11264 01:23:01.427551 + cd /lava-13468763/0/tests/0_timesync-off
11265 01:23:01.430695 ++ cat uuid
11266 01:23:01.439199 + UUID=13468763_1.6.2.3.1
11267 01:23:01.439624 + set +x
11268 01:23:01.446159 <LAVA_SIGNAL_STARTRUN 0_timesync-off 13468763_1.6.2.3.1>
11269 01:23:01.446915 Received signal: <STARTRUN> 0_timesync-off 13468763_1.6.2.3.1
11270 01:23:01.447382 Starting test lava.0_timesync-off (13468763_1.6.2.3.1)
11271 01:23:01.447854 Skipping test definition patterns.
11272 01:23:01.448832 + systemctl stop systemd-timesyncd
11273 01:23:01.530199 + set +x
11274 01:23:01.533550 <LAVA_SIGNAL_ENDRUN 0_timesync-off 13468763_1.6.2.3.1>
11275 01:23:01.534229 Received signal: <ENDRUN> 0_timesync-off 13468763_1.6.2.3.1
11276 01:23:01.534651 Ending use of test pattern.
11277 01:23:01.534979 Ending test lava.0_timesync-off (13468763_1.6.2.3.1), duration 0.09
11279 01:23:01.636544 + export TESTRUN_ID=1_kselftest-tpm2
11280 01:23:01.639586 + TESTRUN_ID=1_kselftest-tpm2
11281 01:23:01.646158 + cd /lava-13468763/0/tests/1_kselftest-tpm2
11282 01:23:01.646592 ++ cat uuid
11283 01:23:01.655888 + UUID=13468763_1.6.2.3.5
11284 01:23:01.656314 + set +x
11285 01:23:01.662663 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 13468763_1.6.2.3.5>
11286 01:23:01.663347 Received signal: <STARTRUN> 1_kselftest-tpm2 13468763_1.6.2.3.5
11287 01:23:01.663717 Starting test lava.1_kselftest-tpm2 (13468763_1.6.2.3.5)
11288 01:23:01.664141 Skipping test definition patterns.
11289 01:23:01.665903 + cd ./automated/linux/kselftest/
11290 01:23:01.692254 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11291 01:23:01.752536 INFO: install_deps skipped
11292 01:23:02.275182 --2024-04-23 01:23:02-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11293 01:23:02.286673 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11294 01:23:02.415103 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11295 01:23:02.542334 HTTP request sent, awaiting response... 200 OK
11296 01:23:02.545644 Length: 1651524 (1.6M) [application/octet-stream]
11297 01:23:02.549038 Saving to: 'kselftest_armhf.tar.gz'
11298 01:23:02.549669
11299 01:23:02.550260
11300 01:23:02.797628 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11301 01:23:03.051267 kselftest_armhf.tar 2%[ ] 47.81K 186KB/s
11302 01:23:03.351648 kselftest_armhf.tar 13%[=> ] 217.50K 424KB/s
11303 01:23:03.482378 kselftest_armhf.tar 51%[=========> ] 825.54K 1012KB/s
11304 01:23:03.489030 kselftest_armhf.tar 100%[===================>] 1.57M 1.66MB/s in 0.9s
11305 01:23:03.489550
11306 01:23:03.635551 2024-04-23 01:23:03 (1.66 MB/s) - 'kselftest_armhf.tar.gz' saved [1651524/1651524]
11307 01:23:03.636076
11308 01:23:09.138082 skiplist:
11309 01:23:09.141289 ========================================
11310 01:23:09.144443 ========================================
11311 01:23:09.202175 tpm2:test_smoke.sh
11312 01:23:09.205142 tpm2:test_space.sh
11313 01:23:09.226378 ============== Tests to run ===============
11314 01:23:09.229300 tpm2:test_smoke.sh
11315 01:23:09.229787 tpm2:test_space.sh
11316 01:23:09.235935 ===========End Tests to run ===============
11317 01:23:09.239369 shardfile-tpm2 pass
11318 01:23:09.374768 <12>[ 37.467840] kselftest: Running tests in tpm2
11319 01:23:09.385509 TAP version 13
11320 01:23:09.402219 1..2
11321 01:23:09.442806 # selftests: tpm2: test_smoke.sh
11322 01:23:11.366995 # test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite) ... ERROR
11323 01:23:11.373215 # test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp) ... ERROR
11324 01:23:11.380247 # Exception ignored in: <function Client.__del__ at 0xffff7fceccc0>
11325 01:23:11.383529 # Traceback (most recent call last):
11326 01:23:11.393644 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11327 01:23:11.394089 # if self.tpm:
11328 01:23:11.396770 # ^^^^^^^^
11329 01:23:11.400222 # AttributeError: 'Client' object has no attribute 'tpm'
11330 01:23:11.406968 # test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth) ... ERROR
11331 01:23:11.413497 # Exception ignored in: <function Client.__del__ at 0xffff7fceccc0>
11332 01:23:11.416786 # Traceback (most recent call last):
11333 01:23:11.426755 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11334 01:23:11.427224 # if self.tpm:
11335 01:23:11.430593 # ^^^^^^^^
11336 01:23:11.433174 # AttributeError: 'Client' object has no attribute 'tpm'
11337 01:23:11.443095 # test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy) ... ERROR
11338 01:23:11.446573 # Exception ignored in: <function Client.__del__ at 0xffff7fceccc0>
11339 01:23:11.449608 # Traceback (most recent call last):
11340 01:23:11.459436 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11341 01:23:11.463071 # if self.tpm:
11342 01:23:11.463508 # ^^^^^^^^
11343 01:23:11.469431 # AttributeError: 'Client' object has no attribute 'tpm'
11344 01:23:11.476613 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth) ... ERROR
11345 01:23:11.483320 # Exception ignored in: <function Client.__del__ at 0xffff7fceccc0>
11346 01:23:11.486361 # Traceback (most recent call last):
11347 01:23:11.496294 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11348 01:23:11.499349 # if self.tpm:
11349 01:23:11.499830 # ^^^^^^^^
11350 01:23:11.505963 # AttributeError: 'Client' object has no attribute 'tpm'
11351 01:23:11.512808 # test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds) ... ERROR
11352 01:23:11.516067 # Exception ignored in: <function Client.__del__ at 0xffff7fceccc0>
11353 01:23:11.518987 # Traceback (most recent call last):
11354 01:23:11.529038 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11355 01:23:11.532261 # if self.tpm:
11356 01:23:11.532748 # ^^^^^^^^
11357 01:23:11.538760 # AttributeError: 'Client' object has no attribute 'tpm'
11358 01:23:11.545535 # test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd) ... ERROR
11359 01:23:11.552053 # Exception ignored in: <function Client.__del__ at 0xffff7fceccc0>
11360 01:23:11.555302 # Traceback (most recent call last):
11361 01:23:11.565476 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11362 01:23:11.566068 # if self.tpm:
11363 01:23:11.568315 # ^^^^^^^^
11364 01:23:11.572014 # AttributeError: 'Client' object has no attribute 'tpm'
11365 01:23:11.581750 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth) ... ERROR
11366 01:23:11.585283 # Exception ignored in: <function Client.__del__ at 0xffff7fceccc0>
11367 01:23:11.588729 # Traceback (most recent call last):
11368 01:23:11.598397 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11369 01:23:11.601601 # if self.tpm:
11370 01:23:11.602087 # ^^^^^^^^
11371 01:23:11.607919 # AttributeError: 'Client' object has no attribute 'tpm'
11372 01:23:11.618258 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy) ... ERROR
11373 01:23:11.621487 # Exception ignored in: <function Client.__del__ at 0xffff7fceccc0>
11374 01:23:11.625003 # Traceback (most recent call last):
11375 01:23:11.634590 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11376 01:23:11.638108 # if self.tpm:
11377 01:23:11.638704 # ^^^^^^^^
11378 01:23:11.644301 # AttributeError: 'Client' object has no attribute 'tpm'
11379 01:23:11.644787 #
11380 01:23:11.651434 # ======================================================================
11381 01:23:11.657851 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite)
11382 01:23:11.664591 # ----------------------------------------------------------------------
11383 01:23:11.667652 # Traceback (most recent call last):
11384 01:23:11.677451 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11385 01:23:11.684024 # self.root_key = self.client.create_root_key()
11386 01:23:11.687679 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11387 01:23:11.697483 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11388 01:23:11.703889 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11389 01:23:11.707174 # ^^^^^^^^^^^^^^^^^^
11390 01:23:11.717243 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11391 01:23:11.720466 # raise ProtocolError(cc, rc)
11392 01:23:11.726969 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11393 01:23:11.727555 #
11394 01:23:11.733907 # ======================================================================
11395 01:23:11.740343 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp)
11396 01:23:11.746608 # ----------------------------------------------------------------------
11397 01:23:11.749841 # Traceback (most recent call last):
11398 01:23:11.759857 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11399 01:23:11.763362 # self.client = tpm2.Client()
11400 01:23:11.766579 # ^^^^^^^^^^^^^
11401 01:23:11.776140 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11402 01:23:11.780020 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11403 01:23:11.784932 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11404 01:23:11.793265 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11405 01:23:11.793750 #
11406 01:23:11.799590 # ======================================================================
11407 01:23:11.803075 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth)
11408 01:23:11.809701 # ----------------------------------------------------------------------
11409 01:23:11.812942 # Traceback (most recent call last):
11410 01:23:11.822674 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11411 01:23:11.825914 # self.client = tpm2.Client()
11412 01:23:11.829299 # ^^^^^^^^^^^^^
11413 01:23:11.839859 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11414 01:23:11.846290 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11415 01:23:11.849780 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11416 01:23:11.856203 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11417 01:23:11.856772 #
11418 01:23:11.862866 # ======================================================================
11419 01:23:11.869178 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy)
11420 01:23:11.876012 # ----------------------------------------------------------------------
11421 01:23:11.879181 # Traceback (most recent call last):
11422 01:23:11.888934 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11423 01:23:11.892472 # self.client = tpm2.Client()
11424 01:23:11.895562 # ^^^^^^^^^^^^^
11425 01:23:11.905806 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11426 01:23:11.908719 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11427 01:23:11.915459 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11428 01:23:11.918822 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11429 01:23:11.919246 #
11430 01:23:11.925541 # ======================================================================
11431 01:23:11.935646 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth)
11432 01:23:11.938802 # ----------------------------------------------------------------------
11433 01:23:11.941908 # Traceback (most recent call last):
11434 01:23:11.952380 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11435 01:23:11.955520 # self.client = tpm2.Client()
11436 01:23:11.958698 # ^^^^^^^^^^^^^
11437 01:23:11.968894 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11438 01:23:11.975461 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11439 01:23:11.978691 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11440 01:23:11.985394 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11441 01:23:11.985909 #
11442 01:23:11.991741 # ======================================================================
11443 01:23:11.998640 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds)
11444 01:23:12.005390 # ----------------------------------------------------------------------
11445 01:23:12.008223 # Traceback (most recent call last):
11446 01:23:12.018437 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11447 01:23:12.021701 # self.client = tpm2.Client()
11448 01:23:12.022124 # ^^^^^^^^^^^^^
11449 01:23:12.031888 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11450 01:23:12.038479 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11451 01:23:12.041683 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11452 01:23:12.048638 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11453 01:23:12.049227 #
11454 01:23:12.055220 # ======================================================================
11455 01:23:12.061961 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd)
11456 01:23:12.068749 # ----------------------------------------------------------------------
11457 01:23:12.071865 # Traceback (most recent call last):
11458 01:23:12.081303 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11459 01:23:12.085224 # self.client = tpm2.Client()
11460 01:23:12.088174 # ^^^^^^^^^^^^^
11461 01:23:12.097729 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11462 01:23:12.101601 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11463 01:23:12.108130 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11464 01:23:12.111742 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11465 01:23:12.112210 #
11466 01:23:12.117633 # ======================================================================
11467 01:23:12.127767 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth)
11468 01:23:12.131338 # ----------------------------------------------------------------------
11469 01:23:12.134654 # Traceback (most recent call last):
11470 01:23:12.148418 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11471 01:23:12.148989 # self.client = tpm2.Client()
11472 01:23:12.151420 # ^^^^^^^^^^^^^
11473 01:23:12.160899 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11474 01:23:12.165659 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11475 01:23:12.172341 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11476 01:23:12.175582 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11477 01:23:12.178918 #
11478 01:23:12.182345 # ======================================================================
11479 01:23:12.193052 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy)
11480 01:23:12.197553 # ----------------------------------------------------------------------
11481 01:23:12.201101 # Traceback (most recent call last):
11482 01:23:12.211303 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11483 01:23:12.214235 # self.client = tpm2.Client()
11484 01:23:12.221261 # ^^^^^^^^^^^^^
11485 01:23:12.227471 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11486 01:23:12.230920 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11487 01:23:12.237913 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11488 01:23:12.241702 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11489 01:23:12.242266 #
11490 01:23:12.248708 # ----------------------------------------------------------------------
11491 01:23:12.251920 # Ran 9 tests in 0.057s
11492 01:23:12.252508 #
11493 01:23:12.255346 # FAILED (errors=9)
11494 01:23:12.258573 # test_async (tpm2_tests.AsyncTest.test_async) ... ok
11495 01:23:12.265210 # test_flush_invalid_context (tpm2_tests.AsyncTest.test_flush_invalid_context) ... ok
11496 01:23:12.265820 #
11497 01:23:12.271928 # ----------------------------------------------------------------------
11498 01:23:12.275185 # Ran 2 tests in 0.027s
11499 01:23:12.275659 #
11500 01:23:12.276024 # OK
11501 01:23:12.278213 ok 1 selftests: tpm2: test_smoke.sh
11502 01:23:12.281966 # selftests: tpm2: test_space.sh
11503 01:23:12.288508 # test_flush_context (tpm2_tests.SpaceTest.test_flush_context) ... ERROR
11504 01:23:12.295409 # test_get_handles (tpm2_tests.SpaceTest.test_get_handles) ... ERROR
11505 01:23:12.301937 # test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc) ... ERROR
11506 01:23:12.308748 # test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces) ... ERROR
11507 01:23:12.309382 #
11508 01:23:12.315168 # ======================================================================
11509 01:23:12.321963 # ERROR: test_flush_context (tpm2_tests.SpaceTest.test_flush_context)
11510 01:23:12.325141 # ----------------------------------------------------------------------
11511 01:23:12.328373 # Traceback (most recent call last):
11512 01:23:12.341416 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11513 01:23:12.344704 # root1 = space1.create_root_key()
11514 01:23:12.348081 # ^^^^^^^^^^^^^^^^^^^^^^^^
11515 01:23:12.358378 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11516 01:23:12.364985 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11517 01:23:12.368087 # ^^^^^^^^^^^^^^^^^^
11518 01:23:12.378355 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11519 01:23:12.381467 # raise ProtocolError(cc, rc)
11520 01:23:12.387866 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11521 01:23:12.388292 #
11522 01:23:12.394739 # ======================================================================
11523 01:23:12.401140 # ERROR: test_get_handles (tpm2_tests.SpaceTest.test_get_handles)
11524 01:23:12.407874 # ----------------------------------------------------------------------
11525 01:23:12.411297 # Traceback (most recent call last):
11526 01:23:12.420918 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11527 01:23:12.424212 # space1.create_root_key()
11528 01:23:12.434213 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11529 01:23:12.440601 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11530 01:23:12.444043 # ^^^^^^^^^^^^^^^^^^
11531 01:23:12.453848 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11532 01:23:12.457432 # raise ProtocolError(cc, rc)
11533 01:23:12.463709 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11534 01:23:12.464282 #
11535 01:23:12.470338 # ======================================================================
11536 01:23:12.477031 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc)
11537 01:23:12.483374 # ----------------------------------------------------------------------
11538 01:23:12.487402 # Traceback (most recent call last):
11539 01:23:12.496730 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11540 01:23:12.500952 # root1 = space1.create_root_key()
11541 01:23:12.503530 # ^^^^^^^^^^^^^^^^^^^^^^^^
11542 01:23:12.513305 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11543 01:23:12.519704 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11544 01:23:12.523145 # ^^^^^^^^^^^^^^^^^^
11545 01:23:12.533250 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11546 01:23:12.536759 # raise ProtocolError(cc, rc)
11547 01:23:12.543016 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11548 01:23:12.543484 #
11549 01:23:12.549988 # ======================================================================
11550 01:23:12.556756 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces)
11551 01:23:12.563211 # ----------------------------------------------------------------------
11552 01:23:12.565991 # Traceback (most recent call last):
11553 01:23:12.576523 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11554 01:23:12.579319 # root1 = space1.create_root_key()
11555 01:23:12.582805 # ^^^^^^^^^^^^^^^^^^^^^^^^
11556 01:23:12.595932 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11557 01:23:12.599171 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11558 01:23:12.606119 # ^^^^^^^^^^^^^^^^^^
11559 01:23:12.615784 # File "/lava-13468763/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11560 01:23:12.619059 # raise ProtocolError(cc, rc)
11561 01:23:12.622817 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11562 01:23:12.625606 #
11563 01:23:12.628829 # ----------------------------------------------------------------------
11564 01:23:12.632658 # Ran 4 tests in 0.094s
11565 01:23:12.633083 #
11566 01:23:12.635702 # FAILED (errors=4)
11567 01:23:12.639015 not ok 2 selftests: tpm2: test_space.sh # exit=1
11568 01:23:13.019104 tpm2_test_smoke_sh pass
11569 01:23:13.021958 tpm2_test_space_sh fail
11570 01:23:13.090255 + ../../utils/send-to-lava.sh ./output/result.txt
11571 01:23:13.187924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11572 01:23:13.188785 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11574 01:23:13.259634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11575 01:23:13.260493 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11577 01:23:13.329519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11578 01:23:13.330338 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11580 01:23:13.332916 + set +x
11581 01:23:13.336206 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 13468763_1.6.2.3.5>
11582 01:23:13.336939 Received signal: <ENDRUN> 1_kselftest-tpm2 13468763_1.6.2.3.5
11583 01:23:13.337399 Ending use of test pattern.
11584 01:23:13.337760 Ending test lava.1_kselftest-tpm2 (13468763_1.6.2.3.5), duration 11.67
11586 01:23:13.339353 <LAVA_TEST_RUNNER EXIT>
11587 01:23:13.340074 ok: lava_test_shell seems to have completed
11588 01:23:13.340666 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11589 01:23:13.341115 end: 3.1 lava-test-shell (duration 00:00:13) [common]
11590 01:23:13.341609 end: 3 lava-test-retry (duration 00:00:13) [common]
11591 01:23:13.342088 start: 4 finalize (timeout 00:07:09) [common]
11592 01:23:13.342599 start: 4.1 power-off (timeout 00:00:30) [common]
11593 01:23:13.343412 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11594 01:23:13.465599 >> Command sent successfully.
11595 01:23:13.469669 Returned 0 in 0 seconds
11596 01:23:13.570542 end: 4.1 power-off (duration 00:00:00) [common]
11598 01:23:13.572043 start: 4.2 read-feedback (timeout 00:07:09) [common]
11599 01:23:13.573287 Listened to connection for namespace 'common' for up to 1s
11600 01:23:14.573638 Finalising connection for namespace 'common'
11601 01:23:14.574343 Disconnecting from shell: Finalise
11602 01:23:14.574740 / #
11603 01:23:14.675689 end: 4.2 read-feedback (duration 00:00:01) [common]
11604 01:23:14.676372 end: 4 finalize (duration 00:00:01) [common]
11605 01:23:14.676980 Cleaning after the job
11606 01:23:14.677575 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468763/tftp-deploy-pagevbpx/ramdisk
11607 01:23:14.687655 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468763/tftp-deploy-pagevbpx/kernel
11608 01:23:14.718042 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468763/tftp-deploy-pagevbpx/dtb
11609 01:23:14.718370 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468763/tftp-deploy-pagevbpx/nfsrootfs
11610 01:23:14.786066 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468763/tftp-deploy-pagevbpx/modules
11611 01:23:14.791603 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13468763
11612 01:23:15.335889 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13468763
11613 01:23:15.336070 Job finished correctly