Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 47
- Errors: 0
- Kernel Errors: 34
- Boot result: PASS
1 01:14:58.801107 lava-dispatcher, installed at version: 2024.01
2 01:14:58.801315 start: 0 validate
3 01:14:58.801441 Start time: 2024-04-23 01:14:58.801433+00:00 (UTC)
4 01:14:58.801570 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:14:58.801696 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 01:14:59.073801 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:14:59.074469 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:14:59.332280 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:14:59.332905 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:14:59.591237 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:14:59.592096 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 01:15:00.100999 validate duration: 1.30
14 01:15:00.102319 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:15:00.102837 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:15:00.103312 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:15:00.103912 Not decompressing ramdisk as can be used compressed.
18 01:15:00.104345 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/rootfs.cpio.gz
19 01:15:00.104670 saving as /var/lib/lava/dispatcher/tmp/13468740/tftp-deploy-rrunqafy/ramdisk/rootfs.cpio.gz
20 01:15:00.104994 total size: 95552279 (91 MB)
21 01:15:00.109691 progress 0 % (0 MB)
22 01:15:00.162622 progress 5 % (4 MB)
23 01:15:00.186977 progress 10 % (9 MB)
24 01:15:00.211064 progress 15 % (13 MB)
25 01:15:00.235353 progress 20 % (18 MB)
26 01:15:00.259641 progress 25 % (22 MB)
27 01:15:00.283775 progress 30 % (27 MB)
28 01:15:00.307862 progress 35 % (31 MB)
29 01:15:00.332176 progress 40 % (36 MB)
30 01:15:00.356239 progress 45 % (41 MB)
31 01:15:00.380390 progress 50 % (45 MB)
32 01:15:00.404321 progress 55 % (50 MB)
33 01:15:00.428616 progress 60 % (54 MB)
34 01:15:00.452704 progress 65 % (59 MB)
35 01:15:00.476713 progress 70 % (63 MB)
36 01:15:00.501170 progress 75 % (68 MB)
37 01:15:00.526508 progress 80 % (72 MB)
38 01:15:00.550814 progress 85 % (77 MB)
39 01:15:00.575445 progress 90 % (82 MB)
40 01:15:00.600169 progress 95 % (86 MB)
41 01:15:00.624178 progress 100 % (91 MB)
42 01:15:00.624331 91 MB downloaded in 0.52 s (175.46 MB/s)
43 01:15:00.624491 end: 1.1.1 http-download (duration 00:00:01) [common]
45 01:15:00.624741 end: 1.1 download-retry (duration 00:00:01) [common]
46 01:15:00.624828 start: 1.2 download-retry (timeout 00:09:59) [common]
47 01:15:00.624912 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 01:15:00.625045 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 01:15:00.625118 saving as /var/lib/lava/dispatcher/tmp/13468740/tftp-deploy-rrunqafy/kernel/Image
50 01:15:00.625179 total size: 54352384 (51 MB)
51 01:15:00.625241 No compression specified
52 01:15:00.626379 progress 0 % (0 MB)
53 01:15:00.640136 progress 5 % (2 MB)
54 01:15:00.653811 progress 10 % (5 MB)
55 01:15:00.667615 progress 15 % (7 MB)
56 01:15:00.681341 progress 20 % (10 MB)
57 01:15:00.695060 progress 25 % (12 MB)
58 01:15:00.708878 progress 30 % (15 MB)
59 01:15:00.722648 progress 35 % (18 MB)
60 01:15:00.736613 progress 40 % (20 MB)
61 01:15:00.750341 progress 45 % (23 MB)
62 01:15:00.764130 progress 50 % (25 MB)
63 01:15:00.777765 progress 55 % (28 MB)
64 01:15:00.791526 progress 60 % (31 MB)
65 01:15:00.805232 progress 65 % (33 MB)
66 01:15:00.819166 progress 70 % (36 MB)
67 01:15:00.833035 progress 75 % (38 MB)
68 01:15:00.846855 progress 80 % (41 MB)
69 01:15:00.860713 progress 85 % (44 MB)
70 01:15:00.874443 progress 90 % (46 MB)
71 01:15:00.888209 progress 95 % (49 MB)
72 01:15:00.901590 progress 100 % (51 MB)
73 01:15:00.901802 51 MB downloaded in 0.28 s (187.39 MB/s)
74 01:15:00.901949 end: 1.2.1 http-download (duration 00:00:00) [common]
76 01:15:00.902189 end: 1.2 download-retry (duration 00:00:00) [common]
77 01:15:00.902280 start: 1.3 download-retry (timeout 00:09:59) [common]
78 01:15:00.902367 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 01:15:00.902500 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 01:15:00.902586 saving as /var/lib/lava/dispatcher/tmp/13468740/tftp-deploy-rrunqafy/dtb/mt8192-asurada-spherion-r0.dtb
81 01:15:00.902649 total size: 47230 (0 MB)
82 01:15:00.902711 No compression specified
83 01:15:00.903822 progress 69 % (0 MB)
84 01:15:00.904147 progress 100 % (0 MB)
85 01:15:00.904304 0 MB downloaded in 0.00 s (27.26 MB/s)
86 01:15:00.904428 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:15:00.904648 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:15:00.904731 start: 1.4 download-retry (timeout 00:09:59) [common]
90 01:15:00.904813 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 01:15:00.904931 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 01:15:00.905000 saving as /var/lib/lava/dispatcher/tmp/13468740/tftp-deploy-rrunqafy/modules/modules.tar
93 01:15:00.905061 total size: 8638160 (8 MB)
94 01:15:00.905122 Using unxz to decompress xz
95 01:15:00.909296 progress 0 % (0 MB)
96 01:15:00.928366 progress 5 % (0 MB)
97 01:15:00.953950 progress 10 % (0 MB)
98 01:15:00.978558 progress 15 % (1 MB)
99 01:15:01.002638 progress 20 % (1 MB)
100 01:15:01.027813 progress 25 % (2 MB)
101 01:15:01.053903 progress 30 % (2 MB)
102 01:15:01.078409 progress 35 % (2 MB)
103 01:15:01.103750 progress 40 % (3 MB)
104 01:15:01.126964 progress 45 % (3 MB)
105 01:15:01.152310 progress 50 % (4 MB)
106 01:15:01.176478 progress 55 % (4 MB)
107 01:15:01.204285 progress 60 % (4 MB)
108 01:15:01.229487 progress 65 % (5 MB)
109 01:15:01.254347 progress 70 % (5 MB)
110 01:15:01.278270 progress 75 % (6 MB)
111 01:15:01.302765 progress 80 % (6 MB)
112 01:15:01.330116 progress 85 % (7 MB)
113 01:15:01.357124 progress 90 % (7 MB)
114 01:15:01.388029 progress 95 % (7 MB)
115 01:15:01.416266 progress 100 % (8 MB)
116 01:15:01.422397 8 MB downloaded in 0.52 s (15.92 MB/s)
117 01:15:01.422635 end: 1.4.1 http-download (duration 00:00:01) [common]
119 01:15:01.422913 end: 1.4 download-retry (duration 00:00:01) [common]
120 01:15:01.423003 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 01:15:01.423096 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 01:15:01.423175 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:15:01.423264 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 01:15:01.423487 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr
125 01:15:01.423617 makedir: /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/bin
126 01:15:01.423718 makedir: /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/tests
127 01:15:01.423814 makedir: /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/results
128 01:15:01.423972 Creating /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/bin/lava-add-keys
129 01:15:01.424116 Creating /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/bin/lava-add-sources
130 01:15:01.424243 Creating /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/bin/lava-background-process-start
131 01:15:01.424371 Creating /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/bin/lava-background-process-stop
132 01:15:01.424494 Creating /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/bin/lava-common-functions
133 01:15:01.424616 Creating /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/bin/lava-echo-ipv4
134 01:15:01.424737 Creating /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/bin/lava-install-packages
135 01:15:01.424857 Creating /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/bin/lava-installed-packages
136 01:15:01.424976 Creating /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/bin/lava-os-build
137 01:15:01.425097 Creating /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/bin/lava-probe-channel
138 01:15:01.425215 Creating /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/bin/lava-probe-ip
139 01:15:01.425334 Creating /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/bin/lava-target-ip
140 01:15:01.425451 Creating /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/bin/lava-target-mac
141 01:15:01.425569 Creating /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/bin/lava-target-storage
142 01:15:01.425691 Creating /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/bin/lava-test-case
143 01:15:01.425812 Creating /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/bin/lava-test-event
144 01:15:01.425930 Creating /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/bin/lava-test-feedback
145 01:15:01.426049 Creating /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/bin/lava-test-raise
146 01:15:01.426172 Creating /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/bin/lava-test-reference
147 01:15:01.426292 Creating /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/bin/lava-test-runner
148 01:15:01.426410 Creating /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/bin/lava-test-set
149 01:15:01.426531 Creating /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/bin/lava-test-shell
150 01:15:01.426652 Updating /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/bin/lava-install-packages (oe)
151 01:15:01.426817 Updating /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/bin/lava-installed-packages (oe)
152 01:15:01.426935 Creating /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/environment
153 01:15:01.427041 LAVA metadata
154 01:15:01.427115 - LAVA_JOB_ID=13468740
155 01:15:01.427177 - LAVA_DISPATCHER_IP=192.168.201.1
156 01:15:01.427279 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 01:15:01.427344 skipped lava-vland-overlay
158 01:15:01.427417 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 01:15:01.427497 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 01:15:01.427558 skipped lava-multinode-overlay
161 01:15:01.427630 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 01:15:01.427719 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 01:15:01.427792 Loading test definitions
164 01:15:01.427878 start: 1.5.2.3.1 git-repo-action (timeout 00:09:59) [common]
165 01:15:01.428023 Using /lava-13468740 at stage 0
166 01:15:01.428150 Fetching tests from https://github.com/kernelci/kernelci-core
167 01:15:01.428244 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/0/tests/0_sleep'
168 01:15:02.045351 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/0/tests/0_sleep
169 01:15:02.046600 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 01:15:02.047006 uuid=13468740_1.5.2.3.1 testdef=None
171 01:15:02.047156 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 01:15:02.047412 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 01:15:02.047973 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 01:15:02.048210 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 01:15:02.048932 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 01:15:02.049179 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 01:15:02.049850 runner path: /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/0/tests/0_sleep test_uuid 13468740_1.5.2.3.1
181 01:15:02.049938 sleep_params='mem'
182 01:15:02.050090 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 01:15:02.050312 Creating lava-test-runner.conf files
185 01:15:02.050378 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13468740/lava-overlay-0fnkxinr/lava-13468740/0 for stage 0
186 01:15:02.050473 - 0_sleep
187 01:15:02.050583 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 01:15:02.050672 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 01:15:02.193829 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 01:15:02.193987 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
191 01:15:02.194080 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 01:15:02.194177 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 01:15:02.194266 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
194 01:15:05.035689 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:03) [common]
195 01:15:05.036123 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
196 01:15:05.036239 extracting modules file /var/lib/lava/dispatcher/tmp/13468740/tftp-deploy-rrunqafy/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13468740/extract-overlay-ramdisk-4t98l440/ramdisk
197 01:15:05.261562 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 01:15:05.261738 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
199 01:15:05.261833 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13468740/compress-overlay-qq0u_te1/overlay-1.5.2.4.tar.gz to ramdisk
200 01:15:05.261903 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13468740/compress-overlay-qq0u_te1/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13468740/extract-overlay-ramdisk-4t98l440/ramdisk
201 01:15:05.369571 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 01:15:05.369743 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
203 01:15:05.369840 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 01:15:05.369937 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
205 01:15:05.370021 Building ramdisk /var/lib/lava/dispatcher/tmp/13468740/extract-overlay-ramdisk-4t98l440/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13468740/extract-overlay-ramdisk-4t98l440/ramdisk
206 01:15:07.091717 >> 675492 blocks
207 01:15:19.049375 rename /var/lib/lava/dispatcher/tmp/13468740/extract-overlay-ramdisk-4t98l440/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13468740/tftp-deploy-rrunqafy/ramdisk/ramdisk.cpio.gz
208 01:15:19.049826 end: 1.5.7 compress-ramdisk (duration 00:00:14) [common]
209 01:15:19.049952 start: 1.5.8 prepare-kernel (timeout 00:09:41) [common]
210 01:15:19.050050 start: 1.5.8.1 prepare-fit (timeout 00:09:41) [common]
211 01:15:19.050158 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13468740/tftp-deploy-rrunqafy/kernel/Image'
212 01:15:32.007960 Returned 0 in 12 seconds
213 01:15:32.108837 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13468740/tftp-deploy-rrunqafy/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13468740/tftp-deploy-rrunqafy/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13468740/tftp-deploy-rrunqafy/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13468740/tftp-deploy-rrunqafy/kernel/image.itb
214 01:15:33.502358 output: FIT description: Kernel Image image with one or more FDT blobs
215 01:15:33.502731 output: Created: Tue Apr 23 02:15:33 2024
216 01:15:33.502803 output: Image 0 (kernel-1)
217 01:15:33.502870 output: Description:
218 01:15:33.502931 output: Created: Tue Apr 23 02:15:33 2024
219 01:15:33.502992 output: Type: Kernel Image
220 01:15:33.503053 output: Compression: lzma compressed
221 01:15:33.503113 output: Data Size: 12910050 Bytes = 12607.47 KiB = 12.31 MiB
222 01:15:33.503173 output: Architecture: AArch64
223 01:15:33.503231 output: OS: Linux
224 01:15:33.503288 output: Load Address: 0x00000000
225 01:15:33.503345 output: Entry Point: 0x00000000
226 01:15:33.503400 output: Hash algo: crc32
227 01:15:33.503490 output: Hash value: 1126c3f9
228 01:15:33.503594 output: Image 1 (fdt-1)
229 01:15:33.503680 output: Description: mt8192-asurada-spherion-r0
230 01:15:33.503765 output: Created: Tue Apr 23 02:15:33 2024
231 01:15:33.503848 output: Type: Flat Device Tree
232 01:15:33.503956 output: Compression: uncompressed
233 01:15:33.504012 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
234 01:15:33.504067 output: Architecture: AArch64
235 01:15:33.504121 output: Hash algo: crc32
236 01:15:33.504174 output: Hash value: 4bf0d1ac
237 01:15:33.504227 output: Image 2 (ramdisk-1)
238 01:15:33.504280 output: Description: unavailable
239 01:15:33.504333 output: Created: Tue Apr 23 02:15:33 2024
240 01:15:33.504386 output: Type: RAMDisk Image
241 01:15:33.504439 output: Compression: Unknown Compression
242 01:15:33.504492 output: Data Size: 109008076 Bytes = 106453.20 KiB = 103.96 MiB
243 01:15:33.504546 output: Architecture: AArch64
244 01:15:33.504598 output: OS: Linux
245 01:15:33.504650 output: Load Address: unavailable
246 01:15:33.504703 output: Entry Point: unavailable
247 01:15:33.504755 output: Hash algo: crc32
248 01:15:33.504808 output: Hash value: dfd689eb
249 01:15:33.504861 output: Default Configuration: 'conf-1'
250 01:15:33.504913 output: Configuration 0 (conf-1)
251 01:15:33.504966 output: Description: mt8192-asurada-spherion-r0
252 01:15:33.505018 output: Kernel: kernel-1
253 01:15:33.505070 output: Init Ramdisk: ramdisk-1
254 01:15:33.505122 output: FDT: fdt-1
255 01:15:33.505174 output: Loadables: kernel-1
256 01:15:33.505227 output:
257 01:15:33.505430 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
258 01:15:33.505524 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
259 01:15:33.505623 end: 1.5 prepare-tftp-overlay (duration 00:00:32) [common]
260 01:15:33.505716 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:27) [common]
261 01:15:33.505803 No LXC device requested
262 01:15:33.505881 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 01:15:33.505966 start: 1.7 deploy-device-env (timeout 00:09:27) [common]
264 01:15:33.506043 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 01:15:33.506108 Checking files for TFTP limit of 4294967296 bytes.
266 01:15:33.506591 end: 1 tftp-deploy (duration 00:00:33) [common]
267 01:15:33.506699 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 01:15:33.506792 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 01:15:33.506920 substitutions:
270 01:15:33.506991 - {DTB}: 13468740/tftp-deploy-rrunqafy/dtb/mt8192-asurada-spherion-r0.dtb
271 01:15:33.507055 - {INITRD}: 13468740/tftp-deploy-rrunqafy/ramdisk/ramdisk.cpio.gz
272 01:15:33.507114 - {KERNEL}: 13468740/tftp-deploy-rrunqafy/kernel/Image
273 01:15:33.507172 - {LAVA_MAC}: None
274 01:15:33.507229 - {PRESEED_CONFIG}: None
275 01:15:33.507286 - {PRESEED_LOCAL}: None
276 01:15:33.507341 - {RAMDISK}: 13468740/tftp-deploy-rrunqafy/ramdisk/ramdisk.cpio.gz
277 01:15:33.507396 - {ROOT_PART}: None
278 01:15:33.507451 - {ROOT}: None
279 01:15:33.507506 - {SERVER_IP}: 192.168.201.1
280 01:15:33.507576 - {TEE}: None
281 01:15:33.507661 Parsed boot commands:
282 01:15:33.507743 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 01:15:33.507987 Parsed boot commands: tftpboot 192.168.201.1 13468740/tftp-deploy-rrunqafy/kernel/image.itb 13468740/tftp-deploy-rrunqafy/kernel/cmdline
284 01:15:33.508080 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 01:15:33.508165 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 01:15:33.508262 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 01:15:33.508349 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 01:15:33.508423 Not connected, no need to disconnect.
289 01:15:33.508499 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 01:15:33.508577 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 01:15:33.508642 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
292 01:15:33.512490 Setting prompt string to ['lava-test: # ']
293 01:15:33.512858 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 01:15:33.512965 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 01:15:33.513061 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 01:15:33.513152 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 01:15:33.513358 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
298 01:15:38.662010 >> Command sent successfully.
299 01:15:38.672557 Returned 0 in 5 seconds
300 01:15:38.773824 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 01:15:38.775243 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 01:15:38.775772 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 01:15:38.776264 Setting prompt string to 'Starting depthcharge on Spherion...'
305 01:15:38.776627 Changing prompt to 'Starting depthcharge on Spherion...'
306 01:15:38.776976 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 01:15:38.778163 [Enter `^Ec?' for help]
308 01:15:38.937969
309 01:15:38.938502
310 01:15:38.938904 F0: 102B 0000
311 01:15:38.939401
312 01:15:38.939748 F3: 1001 0000 [0200]
313 01:15:38.940111
314 01:15:38.941764 F3: 1001 0000
315 01:15:38.942254
316 01:15:38.942598 F7: 102D 0000
317 01:15:38.942917
318 01:15:38.943218 F1: 0000 0000
319 01:15:38.943533
320 01:15:38.945505 V0: 0000 0000 [0001]
321 01:15:38.945926
322 01:15:38.946287 00: 0007 8000
323 01:15:38.946730
324 01:15:38.949179 01: 0000 0000
325 01:15:38.949680
326 01:15:38.950167 BP: 0C00 0209 [0000]
327 01:15:38.950497
328 01:15:38.952998 G0: 1182 0000
329 01:15:38.953468
330 01:15:38.953807 EC: 0000 0021 [4000]
331 01:15:38.954122
332 01:15:38.954419 S7: 0000 0000 [0000]
333 01:15:38.956581
334 01:15:38.957041 CC: 0000 0000 [0001]
335 01:15:38.957376
336 01:15:38.960134 T0: 0000 0040 [010F]
337 01:15:38.960554
338 01:15:38.960886 Jump to BL
339 01:15:38.961191
340 01:15:38.985265
341 01:15:38.985683
342 01:15:38.986011
343 01:15:38.992252 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 01:15:38.995293 ARM64: Exception handlers installed.
345 01:15:38.998983 ARM64: Testing exception
346 01:15:39.002470 ARM64: Done test exception
347 01:15:39.010006 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 01:15:39.020558 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 01:15:39.027229 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 01:15:39.037161 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 01:15:39.043801 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 01:15:39.050798 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 01:15:39.061362 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 01:15:39.067991 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 01:15:39.087829 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 01:15:39.090619 WDT: Last reset was cold boot
357 01:15:39.094256 SPI1(PAD0) initialized at 2873684 Hz
358 01:15:39.097627 SPI5(PAD0) initialized at 992727 Hz
359 01:15:39.100918 VBOOT: Loading verstage.
360 01:15:39.107413 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 01:15:39.110544 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 01:15:39.113970 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 01:15:39.117078 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 01:15:39.125037 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 01:15:39.131937 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 01:15:39.142668 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
367 01:15:39.143097
368 01:15:39.143449
369 01:15:39.152773 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 01:15:39.155422 ARM64: Exception handlers installed.
371 01:15:39.158829 ARM64: Testing exception
372 01:15:39.159255 ARM64: Done test exception
373 01:15:39.166150 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 01:15:39.169835 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 01:15:39.183727 Probing TPM: . done!
376 01:15:39.184200 TPM ready after 0 ms
377 01:15:39.191765 Connected to device vid:did:rid of 1ae0:0028:00
378 01:15:39.198542 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
379 01:15:39.256250 Initialized TPM device CR50 revision 0
380 01:15:39.267766 tlcl_send_startup: Startup return code is 0
381 01:15:39.268236 TPM: setup succeeded
382 01:15:39.279177 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 01:15:39.288191 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 01:15:39.300836 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 01:15:39.310423 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 01:15:39.314152 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 01:15:39.317459 in-header: 03 07 00 00 08 00 00 00
388 01:15:39.321634 in-data: aa e4 47 04 13 02 00 00
389 01:15:39.325494 Chrome EC: UHEPI supported
390 01:15:39.332997 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 01:15:39.336774 in-header: 03 95 00 00 08 00 00 00
392 01:15:39.340647 in-data: 18 20 20 08 00 00 00 00
393 01:15:39.341088 Phase 1
394 01:15:39.344198 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 01:15:39.351424 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 01:15:39.355275 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 01:15:39.359030 Recovery requested (1009000e)
398 01:15:39.366750 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 01:15:39.372430 tlcl_extend: response is 0
400 01:15:39.381737 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 01:15:39.387096 tlcl_extend: response is 0
402 01:15:39.393807 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 01:15:39.414413 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
404 01:15:39.420958 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 01:15:39.421474
406 01:15:39.421805
407 01:15:39.431053 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 01:15:39.434522 ARM64: Exception handlers installed.
409 01:15:39.437578 ARM64: Testing exception
410 01:15:39.438020 ARM64: Done test exception
411 01:15:39.459521 pmic_efuse_setting: Set efuses in 11 msecs
412 01:15:39.462524 pmwrap_interface_init: Select PMIF_VLD_RDY
413 01:15:39.469156 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 01:15:39.472680 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 01:15:39.479022 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 01:15:39.483105 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 01:15:39.487176 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 01:15:39.494327 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 01:15:39.497523 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 01:15:39.501612 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 01:15:39.508455 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 01:15:39.511972 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 01:15:39.515619 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 01:15:39.519133 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 01:15:39.526463 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 01:15:39.530592 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 01:15:39.537383 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 01:15:39.544689 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 01:15:39.548680 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 01:15:39.555930 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 01:15:39.559596 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 01:15:39.566758 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 01:15:39.570507 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 01:15:39.577853 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 01:15:39.581655 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 01:15:39.588558 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 01:15:39.592633 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 01:15:39.599925 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 01:15:39.603409 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 01:15:39.610723 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 01:15:39.614051 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 01:15:39.617727 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 01:15:39.625265 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 01:15:39.628860 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 01:15:39.632330 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 01:15:39.639493 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 01:15:39.643258 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 01:15:39.646917 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 01:15:39.654640 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 01:15:39.658261 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 01:15:39.661963 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 01:15:39.665500 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 01:15:39.672764 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 01:15:39.676101 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 01:15:39.679948 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 01:15:39.683616 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 01:15:39.690914 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 01:15:39.694196 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 01:15:39.698359 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 01:15:39.701472 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 01:15:39.705188 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 01:15:39.711882 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 01:15:39.715568 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 01:15:39.723374 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 01:15:39.731173 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 01:15:39.734959 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 01:15:39.745116 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 01:15:39.752563 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 01:15:39.756713 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 01:15:39.760424 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 01:15:39.763937 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 01:15:39.772981 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0xa
473 01:15:39.776468 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 01:15:39.784857 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
475 01:15:39.788206 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 01:15:39.796980 [RTC]rtc_get_frequency_meter,154: input=15, output=851
477 01:15:39.806455 [RTC]rtc_get_frequency_meter,154: input=7, output=724
478 01:15:39.815549 [RTC]rtc_get_frequency_meter,154: input=11, output=788
479 01:15:39.825369 [RTC]rtc_get_frequency_meter,154: input=13, output=820
480 01:15:39.834637 [RTC]rtc_get_frequency_meter,154: input=12, output=804
481 01:15:39.844542 [RTC]rtc_get_frequency_meter,154: input=11, output=788
482 01:15:39.854599 [RTC]rtc_get_frequency_meter,154: input=12, output=804
483 01:15:39.858130 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
484 01:15:39.861808 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
485 01:15:39.869372 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 01:15:39.872222 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
487 01:15:39.875788 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 01:15:39.879637 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
489 01:15:39.883058 ADC[4]: Raw value=904802 ID=7
490 01:15:39.886963 ADC[3]: Raw value=213916 ID=1
491 01:15:39.887400 RAM Code: 0x71
492 01:15:39.890946 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 01:15:39.898329 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 01:15:39.905638 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 01:15:39.913390 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 01:15:39.916328 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 01:15:39.919873 in-header: 03 07 00 00 08 00 00 00
498 01:15:39.923685 in-data: aa e4 47 04 13 02 00 00
499 01:15:39.924158 Chrome EC: UHEPI supported
500 01:15:39.931092 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 01:15:39.934796 in-header: 03 95 00 00 08 00 00 00
502 01:15:39.938384 in-data: 18 20 20 08 00 00 00 00
503 01:15:39.942084 MRC: failed to locate region type 0.
504 01:15:39.949627 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 01:15:39.950079 DRAM-K: Running full calibration
506 01:15:39.956566 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 01:15:39.960439 header.status = 0x0
508 01:15:39.964198 header.version = 0x6 (expected: 0x6)
509 01:15:39.964646 header.size = 0xd00 (expected: 0xd00)
510 01:15:39.967393 header.flags = 0x0
511 01:15:39.974940 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 01:15:39.991638 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
513 01:15:39.998848 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 01:15:40.002266 dram_init: ddr_geometry: 2
515 01:15:40.002648 [EMI] MDL number = 2
516 01:15:40.006287 [EMI] Get MDL freq = 0
517 01:15:40.006666 dram_init: ddr_type: 0
518 01:15:40.010000 is_discrete_lpddr4: 1
519 01:15:40.013627 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 01:15:40.014079
521 01:15:40.014424
522 01:15:40.014742 [Bian_co] ETT version 0.0.0.1
523 01:15:40.021227 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 01:15:40.021859
525 01:15:40.024980 dramc_set_vcore_voltage set vcore to 650000
526 01:15:40.025541 Read voltage for 800, 4
527 01:15:40.028769 Vio18 = 0
528 01:15:40.029197 Vcore = 650000
529 01:15:40.029565 Vdram = 0
530 01:15:40.029884 Vddq = 0
531 01:15:40.032064 Vmddr = 0
532 01:15:40.032490 dram_init: config_dvfs: 1
533 01:15:40.038623 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 01:15:40.045316 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 01:15:40.049063 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
536 01:15:40.052776 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
537 01:15:40.056508 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
538 01:15:40.060092 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
539 01:15:40.060524 MEM_TYPE=3, freq_sel=18
540 01:15:40.063795 sv_algorithm_assistance_LP4_1600
541 01:15:40.066853 ============ PULL DRAM RESETB DOWN ============
542 01:15:40.074157 ========== PULL DRAM RESETB DOWN end =========
543 01:15:40.077039 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 01:15:40.080487 ===================================
545 01:15:40.083975 LPDDR4 DRAM CONFIGURATION
546 01:15:40.087160 ===================================
547 01:15:40.087587 EX_ROW_EN[0] = 0x0
548 01:15:40.090856 EX_ROW_EN[1] = 0x0
549 01:15:40.091283 LP4Y_EN = 0x0
550 01:15:40.094641 WORK_FSP = 0x0
551 01:15:40.095068 WL = 0x2
552 01:15:40.097457 RL = 0x2
553 01:15:40.097886 BL = 0x2
554 01:15:40.100940 RPST = 0x0
555 01:15:40.101422 RD_PRE = 0x0
556 01:15:40.104393 WR_PRE = 0x1
557 01:15:40.104836 WR_PST = 0x0
558 01:15:40.107371 DBI_WR = 0x0
559 01:15:40.107811 DBI_RD = 0x0
560 01:15:40.110729 OTF = 0x1
561 01:15:40.114363 ===================================
562 01:15:40.117832 ===================================
563 01:15:40.118465 ANA top config
564 01:15:40.120930 ===================================
565 01:15:40.124019 DLL_ASYNC_EN = 0
566 01:15:40.127409 ALL_SLAVE_EN = 1
567 01:15:40.130775 NEW_RANK_MODE = 1
568 01:15:40.131350 DLL_IDLE_MODE = 1
569 01:15:40.134006 LP45_APHY_COMB_EN = 1
570 01:15:40.137806 TX_ODT_DIS = 1
571 01:15:40.140568 NEW_8X_MODE = 1
572 01:15:40.144020 ===================================
573 01:15:40.147439 ===================================
574 01:15:40.150352 data_rate = 1600
575 01:15:40.154038 CKR = 1
576 01:15:40.154539 DQ_P2S_RATIO = 8
577 01:15:40.157007 ===================================
578 01:15:40.160857 CA_P2S_RATIO = 8
579 01:15:40.164537 DQ_CA_OPEN = 0
580 01:15:40.167778 DQ_SEMI_OPEN = 0
581 01:15:40.168253 CA_SEMI_OPEN = 0
582 01:15:40.171636 CA_FULL_RATE = 0
583 01:15:40.174614 DQ_CKDIV4_EN = 1
584 01:15:40.178158 CA_CKDIV4_EN = 1
585 01:15:40.181267 CA_PREDIV_EN = 0
586 01:15:40.184379 PH8_DLY = 0
587 01:15:40.184807 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 01:15:40.187757 DQ_AAMCK_DIV = 4
589 01:15:40.190912 CA_AAMCK_DIV = 4
590 01:15:40.194423 CA_ADMCK_DIV = 4
591 01:15:40.197996 DQ_TRACK_CA_EN = 0
592 01:15:40.201067 CA_PICK = 800
593 01:15:40.201495 CA_MCKIO = 800
594 01:15:40.204613 MCKIO_SEMI = 0
595 01:15:40.208389 PLL_FREQ = 3068
596 01:15:40.211777 DQ_UI_PI_RATIO = 32
597 01:15:40.215469 CA_UI_PI_RATIO = 0
598 01:15:40.218866 ===================================
599 01:15:40.221900 ===================================
600 01:15:40.222481 memory_type:LPDDR4
601 01:15:40.226185 GP_NUM : 10
602 01:15:40.226626 SRAM_EN : 1
603 01:15:40.229833 MD32_EN : 0
604 01:15:40.233493 ===================================
605 01:15:40.233942 [ANA_INIT] >>>>>>>>>>>>>>
606 01:15:40.236874 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 01:15:40.240887 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 01:15:40.244660 ===================================
609 01:15:40.247651 data_rate = 1600,PCW = 0X7600
610 01:15:40.251393 ===================================
611 01:15:40.254590 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 01:15:40.257604 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 01:15:40.264148 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 01:15:40.270924 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 01:15:40.274286 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 01:15:40.277364 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 01:15:40.277794 [ANA_INIT] flow start
618 01:15:40.281024 [ANA_INIT] PLL >>>>>>>>
619 01:15:40.284284 [ANA_INIT] PLL <<<<<<<<
620 01:15:40.284756 [ANA_INIT] MIDPI >>>>>>>>
621 01:15:40.288097 [ANA_INIT] MIDPI <<<<<<<<
622 01:15:40.291071 [ANA_INIT] DLL >>>>>>>>
623 01:15:40.291527 [ANA_INIT] flow end
624 01:15:40.297405 ============ LP4 DIFF to SE enter ============
625 01:15:40.300822 ============ LP4 DIFF to SE exit ============
626 01:15:40.303866 [ANA_INIT] <<<<<<<<<<<<<
627 01:15:40.304425 [Flow] Enable top DCM control >>>>>
628 01:15:40.307485 [Flow] Enable top DCM control <<<<<
629 01:15:40.310388 Enable DLL master slave shuffle
630 01:15:40.317265 ==============================================================
631 01:15:40.320521 Gating Mode config
632 01:15:40.324084 ==============================================================
633 01:15:40.327568 Config description:
634 01:15:40.337059 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 01:15:40.343921 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 01:15:40.347103 SELPH_MODE 0: By rank 1: By Phase
637 01:15:40.353543 ==============================================================
638 01:15:40.357036 GAT_TRACK_EN = 1
639 01:15:40.360270 RX_GATING_MODE = 2
640 01:15:40.364152 RX_GATING_TRACK_MODE = 2
641 01:15:40.366802 SELPH_MODE = 1
642 01:15:40.367230 PICG_EARLY_EN = 1
643 01:15:40.370573 VALID_LAT_VALUE = 1
644 01:15:40.377156 ==============================================================
645 01:15:40.380128 Enter into Gating configuration >>>>
646 01:15:40.383935 Exit from Gating configuration <<<<
647 01:15:40.386823 Enter into DVFS_PRE_config >>>>>
648 01:15:40.397188 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 01:15:40.400307 Exit from DVFS_PRE_config <<<<<
650 01:15:40.403425 Enter into PICG configuration >>>>
651 01:15:40.406546 Exit from PICG configuration <<<<
652 01:15:40.410009 [RX_INPUT] configuration >>>>>
653 01:15:40.413680 [RX_INPUT] configuration <<<<<
654 01:15:40.416577 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 01:15:40.423213 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 01:15:40.430266 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 01:15:40.437025 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 01:15:40.443516 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 01:15:40.446991 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 01:15:40.453471 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 01:15:40.456134 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 01:15:40.459604 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 01:15:40.462883 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 01:15:40.469638 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 01:15:40.472606 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 01:15:40.476464 ===================================
667 01:15:40.479418 LPDDR4 DRAM CONFIGURATION
668 01:15:40.483147 ===================================
669 01:15:40.483273 EX_ROW_EN[0] = 0x0
670 01:15:40.486040 EX_ROW_EN[1] = 0x0
671 01:15:40.486138 LP4Y_EN = 0x0
672 01:15:40.489812 WORK_FSP = 0x0
673 01:15:40.489923 WL = 0x2
674 01:15:40.492755 RL = 0x2
675 01:15:40.492876 BL = 0x2
676 01:15:40.496248 RPST = 0x0
677 01:15:40.496372 RD_PRE = 0x0
678 01:15:40.499320 WR_PRE = 0x1
679 01:15:40.503038 WR_PST = 0x0
680 01:15:40.503170 DBI_WR = 0x0
681 01:15:40.506038 DBI_RD = 0x0
682 01:15:40.506157 OTF = 0x1
683 01:15:40.509027 ===================================
684 01:15:40.512740 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 01:15:40.515668 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 01:15:40.522565 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 01:15:40.525688 ===================================
688 01:15:40.529283 LPDDR4 DRAM CONFIGURATION
689 01:15:40.532468 ===================================
690 01:15:40.532770 EX_ROW_EN[0] = 0x10
691 01:15:40.535972 EX_ROW_EN[1] = 0x0
692 01:15:40.536278 LP4Y_EN = 0x0
693 01:15:40.539404 WORK_FSP = 0x0
694 01:15:40.539812 WL = 0x2
695 01:15:40.542613 RL = 0x2
696 01:15:40.543032 BL = 0x2
697 01:15:40.545630 RPST = 0x0
698 01:15:40.546183 RD_PRE = 0x0
699 01:15:40.549578 WR_PRE = 0x1
700 01:15:40.550002 WR_PST = 0x0
701 01:15:40.552296 DBI_WR = 0x0
702 01:15:40.555958 DBI_RD = 0x0
703 01:15:40.556383 OTF = 0x1
704 01:15:40.559200 ===================================
705 01:15:40.565854 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 01:15:40.569712 nWR fixed to 40
707 01:15:40.572691 [ModeRegInit_LP4] CH0 RK0
708 01:15:40.573191 [ModeRegInit_LP4] CH0 RK1
709 01:15:40.575675 [ModeRegInit_LP4] CH1 RK0
710 01:15:40.579416 [ModeRegInit_LP4] CH1 RK1
711 01:15:40.579995 match AC timing 13
712 01:15:40.585895 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 01:15:40.589395 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 01:15:40.592501 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 01:15:40.598971 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 01:15:40.602593 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 01:15:40.603153 [EMI DOE] emi_dcm 0
718 01:15:40.609537 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 01:15:40.609992 ==
720 01:15:40.612675 Dram Type= 6, Freq= 0, CH_0, rank 0
721 01:15:40.615543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 01:15:40.615980 ==
723 01:15:40.622731 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 01:15:40.628784 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 01:15:40.636668 [CA 0] Center 37 (7~68) winsize 62
726 01:15:40.640305 [CA 1] Center 37 (6~68) winsize 63
727 01:15:40.643527 [CA 2] Center 34 (4~65) winsize 62
728 01:15:40.647147 [CA 3] Center 35 (4~66) winsize 63
729 01:15:40.650192 [CA 4] Center 33 (3~64) winsize 62
730 01:15:40.653622 [CA 5] Center 33 (3~64) winsize 62
731 01:15:40.654069
732 01:15:40.656627 [CmdBusTrainingLP45] Vref(ca) range 1: 34
733 01:15:40.657206
734 01:15:40.660021 [CATrainingPosCal] consider 1 rank data
735 01:15:40.663296 u2DelayCellTimex100 = 270/100 ps
736 01:15:40.666772 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
737 01:15:40.673769 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
738 01:15:40.677131 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
739 01:15:40.679990 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
740 01:15:40.683167 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
741 01:15:40.686521 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
742 01:15:40.686951
743 01:15:40.689869 CA PerBit enable=1, Macro0, CA PI delay=33
744 01:15:40.690298
745 01:15:40.693204 [CBTSetCACLKResult] CA Dly = 33
746 01:15:40.696202 CS Dly: 6 (0~37)
747 01:15:40.696629 ==
748 01:15:40.699878 Dram Type= 6, Freq= 0, CH_0, rank 1
749 01:15:40.702898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 01:15:40.703328 ==
751 01:15:40.709973 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 01:15:40.713094 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 01:15:40.723500 [CA 0] Center 38 (7~69) winsize 63
754 01:15:40.726667 [CA 1] Center 38 (7~69) winsize 63
755 01:15:40.730257 [CA 2] Center 35 (4~66) winsize 63
756 01:15:40.733261 [CA 3] Center 35 (4~66) winsize 63
757 01:15:40.737190 [CA 4] Center 34 (3~65) winsize 63
758 01:15:40.739923 [CA 5] Center 33 (3~64) winsize 62
759 01:15:40.740602
760 01:15:40.743540 [CmdBusTrainingLP45] Vref(ca) range 1: 34
761 01:15:40.743999
762 01:15:40.746743 [CATrainingPosCal] consider 2 rank data
763 01:15:40.749646 u2DelayCellTimex100 = 270/100 ps
764 01:15:40.753365 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
765 01:15:40.759741 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
766 01:15:40.763034 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
767 01:15:40.766443 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
768 01:15:40.769351 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
769 01:15:40.772684 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
770 01:15:40.773378
771 01:15:40.775988 CA PerBit enable=1, Macro0, CA PI delay=33
772 01:15:40.776616
773 01:15:40.779439 [CBTSetCACLKResult] CA Dly = 33
774 01:15:40.782871 CS Dly: 6 (0~38)
775 01:15:40.783429
776 01:15:40.785839 ----->DramcWriteLeveling(PI) begin...
777 01:15:40.786375 ==
778 01:15:40.789533 Dram Type= 6, Freq= 0, CH_0, rank 0
779 01:15:40.793166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 01:15:40.793648 ==
781 01:15:40.797054 Write leveling (Byte 0): 32 => 32
782 01:15:40.800681 Write leveling (Byte 1): 26 => 26
783 01:15:40.801116 DramcWriteLeveling(PI) end<-----
784 01:15:40.801599
785 01:15:40.802003 ==
786 01:15:40.804108 Dram Type= 6, Freq= 0, CH_0, rank 0
787 01:15:40.810896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 01:15:40.811329 ==
789 01:15:40.811668 [Gating] SW mode calibration
790 01:15:40.821636 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 01:15:40.824610 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 01:15:40.828355 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 01:15:40.834687 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
794 01:15:40.837634 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
795 01:15:40.841418 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 01:15:40.848227 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 01:15:40.851104 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 01:15:40.854773 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 01:15:40.861208 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 01:15:40.864929 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 01:15:40.868222 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 01:15:40.874721 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 01:15:40.877713 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 01:15:40.881548 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 01:15:40.887572 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 01:15:40.890953 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 01:15:40.894330 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 01:15:40.898000 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 01:15:40.904586 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
810 01:15:40.907545 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
811 01:15:40.911250 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 01:15:40.917610 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 01:15:40.921121 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 01:15:40.924146 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 01:15:40.931002 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 01:15:40.934540 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 01:15:40.937423 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
818 01:15:40.944262 0 9 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
819 01:15:40.947389 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
820 01:15:40.951020 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 01:15:40.957588 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 01:15:40.960536 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 01:15:40.964157 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 01:15:40.970696 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 01:15:40.973637 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
826 01:15:40.977270 0 10 8 | B1->B0 | 3030 2525 | 0 0 | (0 1) (0 0)
827 01:15:40.984231 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
828 01:15:40.986995 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 01:15:40.990544 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 01:15:40.997191 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 01:15:41.000515 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 01:15:41.003490 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 01:15:41.010189 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
834 01:15:41.013703 0 11 8 | B1->B0 | 2525 4343 | 0 1 | (0 0) (0 0)
835 01:15:41.016721 0 11 12 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
836 01:15:41.023504 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 01:15:41.026611 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 01:15:41.029792 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 01:15:41.036819 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 01:15:41.040059 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 01:15:41.043462 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
842 01:15:41.050424 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
843 01:15:41.053270 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 01:15:41.056960 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 01:15:41.063964 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 01:15:41.066625 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 01:15:41.070179 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 01:15:41.076878 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 01:15:41.079725 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 01:15:41.083710 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 01:15:41.090307 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 01:15:41.093501 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 01:15:41.096758 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 01:15:41.103123 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 01:15:41.106414 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 01:15:41.109951 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 01:15:41.116600 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
858 01:15:41.119686 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
859 01:15:41.122743 Total UI for P1: 0, mck2ui 16
860 01:15:41.126391 best dqsien dly found for B0: ( 0, 14, 4)
861 01:15:41.129309 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
862 01:15:41.132698 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 01:15:41.135816 Total UI for P1: 0, mck2ui 16
864 01:15:41.138932 best dqsien dly found for B1: ( 0, 14, 10)
865 01:15:41.146093 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
866 01:15:41.149061 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
867 01:15:41.149519
868 01:15:41.152360 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
869 01:15:41.155958 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
870 01:15:41.159157 [Gating] SW calibration Done
871 01:15:41.159583 ==
872 01:15:41.163082 Dram Type= 6, Freq= 0, CH_0, rank 0
873 01:15:41.166219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
874 01:15:41.166713 ==
875 01:15:41.167057 RX Vref Scan: 0
876 01:15:41.167376
877 01:15:41.169421 RX Vref 0 -> 0, step: 1
878 01:15:41.169850
879 01:15:41.172981 RX Delay -130 -> 252, step: 16
880 01:15:41.176507 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
881 01:15:41.179556 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
882 01:15:41.186333 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
883 01:15:41.189891 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
884 01:15:41.193036 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
885 01:15:41.196125 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
886 01:15:41.199665 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
887 01:15:41.206062 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
888 01:15:41.209394 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
889 01:15:41.212495 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
890 01:15:41.216065 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
891 01:15:41.219438 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
892 01:15:41.225736 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
893 01:15:41.229274 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
894 01:15:41.232435 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
895 01:15:41.235975 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
896 01:15:41.236408 ==
897 01:15:41.239029 Dram Type= 6, Freq= 0, CH_0, rank 0
898 01:15:41.245791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
899 01:15:41.246221 ==
900 01:15:41.246562 DQS Delay:
901 01:15:41.249265 DQS0 = 0, DQS1 = 0
902 01:15:41.249689 DQM Delay:
903 01:15:41.250028 DQM0 = 88, DQM1 = 75
904 01:15:41.252399 DQ Delay:
905 01:15:41.255757 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
906 01:15:41.259361 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
907 01:15:41.262594 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
908 01:15:41.266083 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
909 01:15:41.266511
910 01:15:41.266846
911 01:15:41.267155 ==
912 01:15:41.269914 Dram Type= 6, Freq= 0, CH_0, rank 0
913 01:15:41.272746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 01:15:41.273176 ==
915 01:15:41.273519
916 01:15:41.273835
917 01:15:41.275765 TX Vref Scan disable
918 01:15:41.278807 == TX Byte 0 ==
919 01:15:41.282280 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
920 01:15:41.285762 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
921 01:15:41.288840 == TX Byte 1 ==
922 01:15:41.292161 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
923 01:15:41.295583 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
924 01:15:41.296063 ==
925 01:15:41.298593 Dram Type= 6, Freq= 0, CH_0, rank 0
926 01:15:41.302426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 01:15:41.305388 ==
928 01:15:41.317161 TX Vref=22, minBit 5, minWin=26, winSum=441
929 01:15:41.320831 TX Vref=24, minBit 1, minWin=27, winSum=442
930 01:15:41.324437 TX Vref=26, minBit 3, minWin=27, winSum=446
931 01:15:41.327176 TX Vref=28, minBit 1, minWin=27, winSum=447
932 01:15:41.330492 TX Vref=30, minBit 1, minWin=27, winSum=451
933 01:15:41.333900 TX Vref=32, minBit 1, minWin=27, winSum=448
934 01:15:41.340465 [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 30
935 01:15:41.340895
936 01:15:41.344280 Final TX Range 1 Vref 30
937 01:15:41.344712
938 01:15:41.345054 ==
939 01:15:41.347155 Dram Type= 6, Freq= 0, CH_0, rank 0
940 01:15:41.350784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
941 01:15:41.351229 ==
942 01:15:41.351566
943 01:15:41.353661
944 01:15:41.354081 TX Vref Scan disable
945 01:15:41.357231 == TX Byte 0 ==
946 01:15:41.360464 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
947 01:15:41.367441 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
948 01:15:41.367950 == TX Byte 1 ==
949 01:15:41.370754 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
950 01:15:41.377004 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
951 01:15:41.377512
952 01:15:41.377957 [DATLAT]
953 01:15:41.378376 Freq=800, CH0 RK0
954 01:15:41.378788
955 01:15:41.380313 DATLAT Default: 0xa
956 01:15:41.383565 0, 0xFFFF, sum = 0
957 01:15:41.384048 1, 0xFFFF, sum = 0
958 01:15:41.386925 2, 0xFFFF, sum = 0
959 01:15:41.387458 3, 0xFFFF, sum = 0
960 01:15:41.390420 4, 0xFFFF, sum = 0
961 01:15:41.390867 5, 0xFFFF, sum = 0
962 01:15:41.393347 6, 0xFFFF, sum = 0
963 01:15:41.393793 7, 0xFFFF, sum = 0
964 01:15:41.396985 8, 0xFFFF, sum = 0
965 01:15:41.397421 9, 0x0, sum = 1
966 01:15:41.400022 10, 0x0, sum = 2
967 01:15:41.400467 11, 0x0, sum = 3
968 01:15:41.403876 12, 0x0, sum = 4
969 01:15:41.404451 best_step = 10
970 01:15:41.404901
971 01:15:41.405318 ==
972 01:15:41.406646 Dram Type= 6, Freq= 0, CH_0, rank 0
973 01:15:41.410595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 01:15:41.411050 ==
975 01:15:41.413713 RX Vref Scan: 1
976 01:15:41.414152
977 01:15:41.416784 Set Vref Range= 32 -> 127
978 01:15:41.417223
979 01:15:41.417666 RX Vref 32 -> 127, step: 1
980 01:15:41.418087
981 01:15:41.420181 RX Delay -111 -> 252, step: 8
982 01:15:41.420661
983 01:15:41.423526 Set Vref, RX VrefLevel [Byte0]: 32
984 01:15:41.426675 [Byte1]: 32
985 01:15:41.430414
986 01:15:41.430952 Set Vref, RX VrefLevel [Byte0]: 33
987 01:15:41.433302 [Byte1]: 33
988 01:15:41.437932
989 01:15:41.438353 Set Vref, RX VrefLevel [Byte0]: 34
990 01:15:41.441662 [Byte1]: 34
991 01:15:41.445617
992 01:15:41.446039 Set Vref, RX VrefLevel [Byte0]: 35
993 01:15:41.448654 [Byte1]: 35
994 01:15:41.453393
995 01:15:41.453816 Set Vref, RX VrefLevel [Byte0]: 36
996 01:15:41.456957 [Byte1]: 36
997 01:15:41.460694
998 01:15:41.461145 Set Vref, RX VrefLevel [Byte0]: 37
999 01:15:41.464168 [Byte1]: 37
1000 01:15:41.468651
1001 01:15:41.469075 Set Vref, RX VrefLevel [Byte0]: 38
1002 01:15:41.471930 [Byte1]: 38
1003 01:15:41.476673
1004 01:15:41.477187 Set Vref, RX VrefLevel [Byte0]: 39
1005 01:15:41.479553 [Byte1]: 39
1006 01:15:41.484038
1007 01:15:41.484467 Set Vref, RX VrefLevel [Byte0]: 40
1008 01:15:41.487516 [Byte1]: 40
1009 01:15:41.491111
1010 01:15:41.491534 Set Vref, RX VrefLevel [Byte0]: 41
1011 01:15:41.494561 [Byte1]: 41
1012 01:15:41.498934
1013 01:15:41.499358 Set Vref, RX VrefLevel [Byte0]: 42
1014 01:15:41.502384 [Byte1]: 42
1015 01:15:41.506518
1016 01:15:41.506943 Set Vref, RX VrefLevel [Byte0]: 43
1017 01:15:41.509813 [Byte1]: 43
1018 01:15:41.514536
1019 01:15:41.514976 Set Vref, RX VrefLevel [Byte0]: 44
1020 01:15:41.517490 [Byte1]: 44
1021 01:15:41.522226
1022 01:15:41.522653 Set Vref, RX VrefLevel [Byte0]: 45
1023 01:15:41.525128 [Byte1]: 45
1024 01:15:41.529670
1025 01:15:41.530111 Set Vref, RX VrefLevel [Byte0]: 46
1026 01:15:41.532946 [Byte1]: 46
1027 01:15:41.537043
1028 01:15:41.537465 Set Vref, RX VrefLevel [Byte0]: 47
1029 01:15:41.540526 [Byte1]: 47
1030 01:15:41.544537
1031 01:15:41.544957 Set Vref, RX VrefLevel [Byte0]: 48
1032 01:15:41.548268 [Byte1]: 48
1033 01:15:41.552273
1034 01:15:41.552691 Set Vref, RX VrefLevel [Byte0]: 49
1035 01:15:41.555689 [Byte1]: 49
1036 01:15:41.560144
1037 01:15:41.560631 Set Vref, RX VrefLevel [Byte0]: 50
1038 01:15:41.563185 [Byte1]: 50
1039 01:15:41.567593
1040 01:15:41.567776 Set Vref, RX VrefLevel [Byte0]: 51
1041 01:15:41.570953 [Byte1]: 51
1042 01:15:41.575119
1043 01:15:41.575271 Set Vref, RX VrefLevel [Byte0]: 52
1044 01:15:41.578089 [Byte1]: 52
1045 01:15:41.582436
1046 01:15:41.582551 Set Vref, RX VrefLevel [Byte0]: 53
1047 01:15:41.586472 [Byte1]: 53
1048 01:15:41.590437
1049 01:15:41.590539 Set Vref, RX VrefLevel [Byte0]: 54
1050 01:15:41.593857 [Byte1]: 54
1051 01:15:41.598131
1052 01:15:41.598223 Set Vref, RX VrefLevel [Byte0]: 55
1053 01:15:41.601327 [Byte1]: 55
1054 01:15:41.605863
1055 01:15:41.605955 Set Vref, RX VrefLevel [Byte0]: 56
1056 01:15:41.608763 [Byte1]: 56
1057 01:15:41.613087
1058 01:15:41.613179 Set Vref, RX VrefLevel [Byte0]: 57
1059 01:15:41.616755 [Byte1]: 57
1060 01:15:41.621194
1061 01:15:41.621286 Set Vref, RX VrefLevel [Byte0]: 58
1062 01:15:41.624075 [Byte1]: 58
1063 01:15:41.629005
1064 01:15:41.629112 Set Vref, RX VrefLevel [Byte0]: 59
1065 01:15:41.631847 [Byte1]: 59
1066 01:15:41.636525
1067 01:15:41.636724 Set Vref, RX VrefLevel [Byte0]: 60
1068 01:15:41.639417 [Byte1]: 60
1069 01:15:41.644281
1070 01:15:41.644466 Set Vref, RX VrefLevel [Byte0]: 61
1071 01:15:41.647070 [Byte1]: 61
1072 01:15:41.651726
1073 01:15:41.651933 Set Vref, RX VrefLevel [Byte0]: 62
1074 01:15:41.654919 [Byte1]: 62
1075 01:15:41.659587
1076 01:15:41.659814 Set Vref, RX VrefLevel [Byte0]: 63
1077 01:15:41.662863 [Byte1]: 63
1078 01:15:41.667034
1079 01:15:41.667496 Set Vref, RX VrefLevel [Byte0]: 64
1080 01:15:41.670779 [Byte1]: 64
1081 01:15:41.674851
1082 01:15:41.675288 Set Vref, RX VrefLevel [Byte0]: 65
1083 01:15:41.678419 [Byte1]: 65
1084 01:15:41.682727
1085 01:15:41.683241 Set Vref, RX VrefLevel [Byte0]: 66
1086 01:15:41.685621 [Byte1]: 66
1087 01:15:41.690006
1088 01:15:41.690445 Set Vref, RX VrefLevel [Byte0]: 67
1089 01:15:41.693505 [Byte1]: 67
1090 01:15:41.697921
1091 01:15:41.698356 Set Vref, RX VrefLevel [Byte0]: 68
1092 01:15:41.701233 [Byte1]: 68
1093 01:15:41.705274
1094 01:15:41.705714 Set Vref, RX VrefLevel [Byte0]: 69
1095 01:15:41.708834 [Byte1]: 69
1096 01:15:41.713109
1097 01:15:41.713638 Set Vref, RX VrefLevel [Byte0]: 70
1098 01:15:41.716401 [Byte1]: 70
1099 01:15:41.720929
1100 01:15:41.721364 Set Vref, RX VrefLevel [Byte0]: 71
1101 01:15:41.724079 [Byte1]: 71
1102 01:15:41.728512
1103 01:15:41.729054 Set Vref, RX VrefLevel [Byte0]: 72
1104 01:15:41.732258 [Byte1]: 72
1105 01:15:41.736289
1106 01:15:41.736726 Set Vref, RX VrefLevel [Byte0]: 73
1107 01:15:41.739158 [Byte1]: 73
1108 01:15:41.743711
1109 01:15:41.744183 Set Vref, RX VrefLevel [Byte0]: 74
1110 01:15:41.746719 [Byte1]: 74
1111 01:15:41.750924
1112 01:15:41.751355 Set Vref, RX VrefLevel [Byte0]: 75
1113 01:15:41.754415 [Byte1]: 75
1114 01:15:41.758744
1115 01:15:41.759289 Set Vref, RX VrefLevel [Byte0]: 76
1116 01:15:41.762488 [Byte1]: 76
1117 01:15:41.766534
1118 01:15:41.767060 Final RX Vref Byte 0 = 55 to rank0
1119 01:15:41.769995 Final RX Vref Byte 1 = 59 to rank0
1120 01:15:41.773423 Final RX Vref Byte 0 = 55 to rank1
1121 01:15:41.776632 Final RX Vref Byte 1 = 59 to rank1==
1122 01:15:41.779986 Dram Type= 6, Freq= 0, CH_0, rank 0
1123 01:15:41.786860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1124 01:15:41.787297 ==
1125 01:15:41.787737 DQS Delay:
1126 01:15:41.788195 DQS0 = 0, DQS1 = 0
1127 01:15:41.789866 DQM Delay:
1128 01:15:41.790303 DQM0 = 88, DQM1 = 77
1129 01:15:41.793131 DQ Delay:
1130 01:15:41.796484 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =88
1131 01:15:41.796919 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1132 01:15:41.799735 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =72
1133 01:15:41.803539 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1134 01:15:41.806534
1135 01:15:41.806970
1136 01:15:41.813007 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a23, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 399 ps
1137 01:15:41.816532 CH0 RK0: MR19=606, MR18=2A23
1138 01:15:41.822921 CH0_RK0: MR19=0x606, MR18=0x2A23, DQSOSC=399, MR23=63, INC=92, DEC=61
1139 01:15:41.823360
1140 01:15:41.826567 ----->DramcWriteLeveling(PI) begin...
1141 01:15:41.827023 ==
1142 01:15:41.829548 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 01:15:41.833132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 01:15:41.833574 ==
1145 01:15:41.836168 Write leveling (Byte 0): 32 => 32
1146 01:15:41.839365 Write leveling (Byte 1): 27 => 27
1147 01:15:41.842900 DramcWriteLeveling(PI) end<-----
1148 01:15:41.843335
1149 01:15:41.843782 ==
1150 01:15:41.846541 Dram Type= 6, Freq= 0, CH_0, rank 1
1151 01:15:41.849781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1152 01:15:41.850220 ==
1153 01:15:41.893845 [Gating] SW mode calibration
1154 01:15:41.894301 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1155 01:15:41.895192 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1156 01:15:41.895590 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 01:15:41.896107 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1158 01:15:41.896518 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1159 01:15:41.896914 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 01:15:41.897314 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 01:15:41.897707 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 01:15:41.938196 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 01:15:41.938774 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 01:15:41.939487 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 01:15:41.939867 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 01:15:41.940233 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 01:15:41.940541 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 01:15:41.940840 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 01:15:41.941129 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 01:15:41.941415 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 01:15:41.941762 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 01:15:41.942836 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1173 01:15:41.946174 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1174 01:15:41.949684 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1175 01:15:41.952724 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 01:15:41.959465 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 01:15:41.962815 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 01:15:41.965931 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 01:15:41.972618 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 01:15:41.976223 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 01:15:41.979265 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
1182 01:15:41.985922 0 9 8 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
1183 01:15:41.988895 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1184 01:15:41.992402 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 01:15:41.995818 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 01:15:42.002242 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 01:15:42.005829 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 01:15:42.008830 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1189 01:15:42.015545 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
1190 01:15:42.019127 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
1191 01:15:42.022231 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 01:15:42.028932 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 01:15:42.032393 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 01:15:42.036193 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 01:15:42.043461 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 01:15:42.047179 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 01:15:42.050831 0 11 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
1198 01:15:42.053924 0 11 8 | B1->B0 | 2a2a 4646 | 0 0 | (1 1) (0 0)
1199 01:15:42.057588 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1200 01:15:42.064204 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 01:15:42.068165 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 01:15:42.071223 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 01:15:42.078014 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 01:15:42.081050 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 01:15:42.084830 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 01:15:42.087985 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 01:15:42.094892 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 01:15:42.097693 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 01:15:42.101558 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 01:15:42.107835 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 01:15:42.111151 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 01:15:42.114432 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 01:15:42.120884 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 01:15:42.124743 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 01:15:42.127626 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 01:15:42.134351 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 01:15:42.137730 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 01:15:42.141229 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 01:15:42.147756 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 01:15:42.150942 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 01:15:42.154387 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1222 01:15:42.161002 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 01:15:42.161424 Total UI for P1: 0, mck2ui 16
1224 01:15:42.167685 best dqsien dly found for B0: ( 0, 14, 4)
1225 01:15:42.168168 Total UI for P1: 0, mck2ui 16
1226 01:15:42.174104 best dqsien dly found for B1: ( 0, 14, 6)
1227 01:15:42.177061 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1228 01:15:42.180269 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1229 01:15:42.180350
1230 01:15:42.183839 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1231 01:15:42.186894 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1232 01:15:42.190570 [Gating] SW calibration Done
1233 01:15:42.190651 ==
1234 01:15:42.193840 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 01:15:42.196888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 01:15:42.196987 ==
1237 01:15:42.200545 RX Vref Scan: 0
1238 01:15:42.200651
1239 01:15:42.200728 RX Vref 0 -> 0, step: 1
1240 01:15:42.200800
1241 01:15:42.203415 RX Delay -130 -> 252, step: 16
1242 01:15:42.207185 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1243 01:15:42.214549 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1244 01:15:42.216781 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1245 01:15:42.220340 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1246 01:15:42.223281 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1247 01:15:42.226697 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1248 01:15:42.233108 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1249 01:15:42.236690 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1250 01:15:42.240217 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1251 01:15:42.243391 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1252 01:15:42.246488 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1253 01:15:42.253269 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1254 01:15:42.256281 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1255 01:15:42.259594 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1256 01:15:42.263524 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1257 01:15:42.269838 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1258 01:15:42.270082 ==
1259 01:15:42.273062 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 01:15:42.277001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 01:15:42.277176 ==
1262 01:15:42.277315 DQS Delay:
1263 01:15:42.279560 DQS0 = 0, DQS1 = 0
1264 01:15:42.279732 DQM Delay:
1265 01:15:42.283081 DQM0 = 85, DQM1 = 77
1266 01:15:42.283281 DQ Delay:
1267 01:15:42.286692 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1268 01:15:42.290046 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
1269 01:15:42.293255 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1270 01:15:42.296325 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1271 01:15:42.296622
1272 01:15:42.296854
1273 01:15:42.297161 ==
1274 01:15:42.300211 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 01:15:42.303679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 01:15:42.304253 ==
1277 01:15:42.304598
1278 01:15:42.306631
1279 01:15:42.307046 TX Vref Scan disable
1280 01:15:42.310033 == TX Byte 0 ==
1281 01:15:42.313256 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1282 01:15:42.316737 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1283 01:15:42.320278 == TX Byte 1 ==
1284 01:15:42.323521 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1285 01:15:42.326473 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1286 01:15:42.326889 ==
1287 01:15:42.329651 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 01:15:42.336371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 01:15:42.336885 ==
1290 01:15:42.348984 TX Vref=22, minBit 1, minWin=27, winSum=440
1291 01:15:42.351998 TX Vref=24, minBit 1, minWin=27, winSum=444
1292 01:15:42.355755 TX Vref=26, minBit 1, minWin=27, winSum=448
1293 01:15:42.358621 TX Vref=28, minBit 1, minWin=27, winSum=452
1294 01:15:42.362167 TX Vref=30, minBit 1, minWin=27, winSum=450
1295 01:15:42.368850 TX Vref=32, minBit 1, minWin=27, winSum=448
1296 01:15:42.371943 [TxChooseVref] Worse bit 1, Min win 27, Win sum 452, Final Vref 28
1297 01:15:42.372362
1298 01:15:42.375067 Final TX Range 1 Vref 28
1299 01:15:42.375502
1300 01:15:42.375834 ==
1301 01:15:42.378468 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 01:15:42.381598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 01:15:42.385382 ==
1304 01:15:42.385793
1305 01:15:42.386117
1306 01:15:42.386417 TX Vref Scan disable
1307 01:15:42.389035 == TX Byte 0 ==
1308 01:15:42.392464 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1309 01:15:42.398565 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1310 01:15:42.398982 == TX Byte 1 ==
1311 01:15:42.402099 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1312 01:15:42.408539 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1313 01:15:42.408970
1314 01:15:42.409304 [DATLAT]
1315 01:15:42.409612 Freq=800, CH0 RK1
1316 01:15:42.410058
1317 01:15:42.412212 DATLAT Default: 0xa
1318 01:15:42.412697 0, 0xFFFF, sum = 0
1319 01:15:42.415271 1, 0xFFFF, sum = 0
1320 01:15:42.415872 2, 0xFFFF, sum = 0
1321 01:15:42.418932 3, 0xFFFF, sum = 0
1322 01:15:42.421984 4, 0xFFFF, sum = 0
1323 01:15:42.422558 5, 0xFFFF, sum = 0
1324 01:15:42.425415 6, 0xFFFF, sum = 0
1325 01:15:42.425853 7, 0xFFFF, sum = 0
1326 01:15:42.428313 8, 0xFFFF, sum = 0
1327 01:15:42.428738 9, 0x0, sum = 1
1328 01:15:42.429075 10, 0x0, sum = 2
1329 01:15:42.432052 11, 0x0, sum = 3
1330 01:15:42.432477 12, 0x0, sum = 4
1331 01:15:42.434886 best_step = 10
1332 01:15:42.435300
1333 01:15:42.435629 ==
1334 01:15:42.438709 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 01:15:42.441634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 01:15:42.442052 ==
1337 01:15:42.445319 RX Vref Scan: 0
1338 01:15:42.445734
1339 01:15:42.446063 RX Vref 0 -> 0, step: 1
1340 01:15:42.448482
1341 01:15:42.448900 RX Delay -95 -> 252, step: 8
1342 01:15:42.455741 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1343 01:15:42.459089 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1344 01:15:42.461833 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1345 01:15:42.465198 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1346 01:15:42.468925 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1347 01:15:42.475031 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1348 01:15:42.478639 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1349 01:15:42.481752 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1350 01:15:42.485494 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1351 01:15:42.488437 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1352 01:15:42.494965 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1353 01:15:42.498714 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1354 01:15:42.502115 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1355 01:15:42.504878 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1356 01:15:42.511570 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1357 01:15:42.515075 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1358 01:15:42.515490 ==
1359 01:15:42.518383 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 01:15:42.521430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 01:15:42.521869 ==
1362 01:15:42.525049 DQS Delay:
1363 01:15:42.525461 DQS0 = 0, DQS1 = 0
1364 01:15:42.525784 DQM Delay:
1365 01:15:42.528281 DQM0 = 86, DQM1 = 76
1366 01:15:42.528690 DQ Delay:
1367 01:15:42.531785 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1368 01:15:42.534872 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1369 01:15:42.538378 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1370 01:15:42.541466 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1371 01:15:42.542022
1372 01:15:42.542489
1373 01:15:42.551396 [DQSOSCAuto] RK1, (LSB)MR18= 0x2522, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1374 01:15:42.551982 CH0 RK1: MR19=606, MR18=2522
1375 01:15:42.558287 CH0_RK1: MR19=0x606, MR18=0x2522, DQSOSC=400, MR23=63, INC=92, DEC=61
1376 01:15:42.561289 [RxdqsGatingPostProcess] freq 800
1377 01:15:42.568042 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1378 01:15:42.571079 Pre-setting of DQS Precalculation
1379 01:15:42.574817 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1380 01:15:42.575230 ==
1381 01:15:42.577854 Dram Type= 6, Freq= 0, CH_1, rank 0
1382 01:15:42.584461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 01:15:42.585008 ==
1384 01:15:42.587818 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1385 01:15:42.594187 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1386 01:15:42.603573 [CA 0] Center 36 (6~67) winsize 62
1387 01:15:42.606953 [CA 1] Center 37 (6~68) winsize 63
1388 01:15:42.610239 [CA 2] Center 35 (5~65) winsize 61
1389 01:15:42.613672 [CA 3] Center 34 (4~65) winsize 62
1390 01:15:42.617331 [CA 4] Center 34 (4~65) winsize 62
1391 01:15:42.620472 [CA 5] Center 34 (3~65) winsize 63
1392 01:15:42.621016
1393 01:15:42.623713 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1394 01:15:42.624230
1395 01:15:42.626814 [CATrainingPosCal] consider 1 rank data
1396 01:15:42.630070 u2DelayCellTimex100 = 270/100 ps
1397 01:15:42.633516 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1398 01:15:42.640568 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1399 01:15:42.643559 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1400 01:15:42.647443 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1401 01:15:42.650583 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1402 01:15:42.653470 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1403 01:15:42.653883
1404 01:15:42.657118 CA PerBit enable=1, Macro0, CA PI delay=34
1405 01:15:42.657536
1406 01:15:42.660320 [CBTSetCACLKResult] CA Dly = 34
1407 01:15:42.660745 CS Dly: 4 (0~35)
1408 01:15:42.663981 ==
1409 01:15:42.664400 Dram Type= 6, Freq= 0, CH_1, rank 1
1410 01:15:42.670139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 01:15:42.670653 ==
1412 01:15:42.673851 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 01:15:42.680370 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 01:15:42.690105 [CA 0] Center 36 (6~67) winsize 62
1415 01:15:42.693651 [CA 1] Center 37 (6~68) winsize 63
1416 01:15:42.696534 [CA 2] Center 34 (4~65) winsize 62
1417 01:15:42.700128 [CA 3] Center 34 (3~65) winsize 63
1418 01:15:42.703796 [CA 4] Center 34 (4~65) winsize 62
1419 01:15:42.707872 [CA 5] Center 33 (3~64) winsize 62
1420 01:15:42.708450
1421 01:15:42.711530 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1422 01:15:42.712173
1423 01:15:42.715037 [CATrainingPosCal] consider 2 rank data
1424 01:15:42.718596 u2DelayCellTimex100 = 270/100 ps
1425 01:15:42.722171 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1426 01:15:42.725612 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1427 01:15:42.729668 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1428 01:15:42.733163 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1429 01:15:42.736314 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1430 01:15:42.739837 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1431 01:15:42.740438
1432 01:15:42.743093 CA PerBit enable=1, Macro0, CA PI delay=33
1433 01:15:42.743508
1434 01:15:42.746572 [CBTSetCACLKResult] CA Dly = 33
1435 01:15:42.747084 CS Dly: 5 (0~37)
1436 01:15:42.749703
1437 01:15:42.753128 ----->DramcWriteLeveling(PI) begin...
1438 01:15:42.753546 ==
1439 01:15:42.756248 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 01:15:42.759553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 01:15:42.760110 ==
1442 01:15:42.763258 Write leveling (Byte 0): 27 => 27
1443 01:15:42.766211 Write leveling (Byte 1): 29 => 29
1444 01:15:42.769317 DramcWriteLeveling(PI) end<-----
1445 01:15:42.769731
1446 01:15:42.770072 ==
1447 01:15:42.773042 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 01:15:42.776001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 01:15:42.776439 ==
1450 01:15:42.779029 [Gating] SW mode calibration
1451 01:15:42.785884 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1452 01:15:42.792660 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1453 01:15:42.795681 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1454 01:15:42.799495 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1455 01:15:42.805903 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1456 01:15:42.809529 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 01:15:42.812458 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 01:15:42.819189 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 01:15:42.822395 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 01:15:42.826109 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 01:15:42.832515 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 01:15:42.835989 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 01:15:42.839276 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 01:15:42.845679 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 01:15:42.849350 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 01:15:42.852386 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 01:15:42.858985 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 01:15:42.862210 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 01:15:42.865479 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1470 01:15:42.868946 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1471 01:15:42.875488 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1472 01:15:42.879459 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 01:15:42.882508 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 01:15:42.889204 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 01:15:42.892096 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 01:15:42.895624 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 01:15:42.902374 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 01:15:42.905341 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1479 01:15:42.908840 0 9 8 | B1->B0 | 2e2e 3131 | 1 0 | (1 1) (0 0)
1480 01:15:42.915656 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 01:15:42.918689 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 01:15:42.921853 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 01:15:42.928808 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 01:15:42.931743 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 01:15:42.935023 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 01:15:42.942169 0 10 4 | B1->B0 | 3333 3131 | 1 0 | (1 1) (0 0)
1487 01:15:42.945471 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
1488 01:15:42.949393 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 01:15:42.955341 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 01:15:42.958331 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 01:15:42.961715 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 01:15:42.968479 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 01:15:42.971828 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 01:15:42.975146 0 11 4 | B1->B0 | 2a2a 3232 | 0 0 | (0 0) (0 0)
1495 01:15:42.981418 0 11 8 | B1->B0 | 4141 4343 | 0 0 | (0 0) (0 0)
1496 01:15:42.984835 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 01:15:42.988294 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 01:15:42.994520 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 01:15:42.998422 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 01:15:43.001224 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 01:15:43.007989 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 01:15:43.011554 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1503 01:15:43.014613 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 01:15:43.021410 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 01:15:43.024322 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 01:15:43.027756 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 01:15:43.034653 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 01:15:43.038058 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 01:15:43.040935 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 01:15:43.047695 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 01:15:43.050761 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 01:15:43.054467 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 01:15:43.061264 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 01:15:43.063988 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 01:15:43.067469 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 01:15:43.074242 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 01:15:43.077371 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 01:15:43.080641 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1519 01:15:43.084178 Total UI for P1: 0, mck2ui 16
1520 01:15:43.087770 best dqsien dly found for B0: ( 0, 14, 2)
1521 01:15:43.090570 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 01:15:43.094152 Total UI for P1: 0, mck2ui 16
1523 01:15:43.097382 best dqsien dly found for B1: ( 0, 14, 4)
1524 01:15:43.100552 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1525 01:15:43.107553 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1526 01:15:43.108013
1527 01:15:43.110461 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1528 01:15:43.113698 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1529 01:15:43.117122 [Gating] SW calibration Done
1530 01:15:43.117545 ==
1531 01:15:43.120697 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 01:15:43.123741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1533 01:15:43.124219 ==
1534 01:15:43.124561 RX Vref Scan: 0
1535 01:15:43.127581
1536 01:15:43.128151 RX Vref 0 -> 0, step: 1
1537 01:15:43.128547
1538 01:15:43.130505 RX Delay -130 -> 252, step: 16
1539 01:15:43.134154 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1540 01:15:43.137332 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1541 01:15:43.143545 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1542 01:15:43.147047 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1543 01:15:43.150142 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1544 01:15:43.153864 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1545 01:15:43.156890 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1546 01:15:43.163543 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1547 01:15:43.167206 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1548 01:15:43.170200 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1549 01:15:43.173875 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1550 01:15:43.180170 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1551 01:15:43.183666 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1552 01:15:43.186734 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1553 01:15:43.190021 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1554 01:15:43.193380 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1555 01:15:43.193816 ==
1556 01:15:43.197054 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 01:15:43.203386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 01:15:43.203968 ==
1559 01:15:43.204335 DQS Delay:
1560 01:15:43.206916 DQS0 = 0, DQS1 = 0
1561 01:15:43.207430 DQM Delay:
1562 01:15:43.210173 DQM0 = 86, DQM1 = 82
1563 01:15:43.210618 DQ Delay:
1564 01:15:43.213697 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1565 01:15:43.217105 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =85
1566 01:15:43.220025 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1567 01:15:43.222939 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1568 01:15:43.223456
1569 01:15:43.223845
1570 01:15:43.224228 ==
1571 01:15:43.226618 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 01:15:43.229816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 01:15:43.230263 ==
1574 01:15:43.230595
1575 01:15:43.230902
1576 01:15:43.233306 TX Vref Scan disable
1577 01:15:43.236860 == TX Byte 0 ==
1578 01:15:43.239911 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1579 01:15:43.243080 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1580 01:15:43.246669 == TX Byte 1 ==
1581 01:15:43.249875 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1582 01:15:43.253303 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1583 01:15:43.253714 ==
1584 01:15:43.256251 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 01:15:43.260137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 01:15:43.262983 ==
1587 01:15:43.274503 TX Vref=22, minBit 0, minWin=27, winSum=443
1588 01:15:43.277505 TX Vref=24, minBit 1, minWin=27, winSum=447
1589 01:15:43.281126 TX Vref=26, minBit 1, minWin=27, winSum=449
1590 01:15:43.285290 TX Vref=28, minBit 0, minWin=28, winSum=455
1591 01:15:43.288081 TX Vref=30, minBit 1, minWin=27, winSum=454
1592 01:15:43.290924 TX Vref=32, minBit 1, minWin=27, winSum=451
1593 01:15:43.298244 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 28
1594 01:15:43.298328
1595 01:15:43.301121 Final TX Range 1 Vref 28
1596 01:15:43.301194
1597 01:15:43.301255 ==
1598 01:15:43.304541 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 01:15:43.307936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 01:15:43.308021 ==
1601 01:15:43.308092
1602 01:15:43.308158
1603 01:15:43.310971 TX Vref Scan disable
1604 01:15:43.314733 == TX Byte 0 ==
1605 01:15:43.317953 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1606 01:15:43.321545 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1607 01:15:43.324722 == TX Byte 1 ==
1608 01:15:43.327957 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1609 01:15:43.331461 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1610 01:15:43.334624
1611 01:15:43.335183 [DATLAT]
1612 01:15:43.335528 Freq=800, CH1 RK0
1613 01:15:43.336056
1614 01:15:43.337577 DATLAT Default: 0xa
1615 01:15:43.337991 0, 0xFFFF, sum = 0
1616 01:15:43.341139 1, 0xFFFF, sum = 0
1617 01:15:43.341562 2, 0xFFFF, sum = 0
1618 01:15:43.344911 3, 0xFFFF, sum = 0
1619 01:15:43.345336 4, 0xFFFF, sum = 0
1620 01:15:43.347926 5, 0xFFFF, sum = 0
1621 01:15:43.348355 6, 0xFFFF, sum = 0
1622 01:15:43.350893 7, 0xFFFF, sum = 0
1623 01:15:43.354657 8, 0xFFFF, sum = 0
1624 01:15:43.355134 9, 0x0, sum = 1
1625 01:15:43.355475 10, 0x0, sum = 2
1626 01:15:43.357865 11, 0x0, sum = 3
1627 01:15:43.358335 12, 0x0, sum = 4
1628 01:15:43.360959 best_step = 10
1629 01:15:43.361371
1630 01:15:43.361699 ==
1631 01:15:43.364256 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 01:15:43.367523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 01:15:43.367976 ==
1634 01:15:43.371225 RX Vref Scan: 1
1635 01:15:43.371637
1636 01:15:43.372040 Set Vref Range= 32 -> 127
1637 01:15:43.374128
1638 01:15:43.374582 RX Vref 32 -> 127, step: 1
1639 01:15:43.374919
1640 01:15:43.377879 RX Delay -95 -> 252, step: 8
1641 01:15:43.378292
1642 01:15:43.381174 Set Vref, RX VrefLevel [Byte0]: 32
1643 01:15:43.384285 [Byte1]: 32
1644 01:15:43.384848
1645 01:15:43.387931 Set Vref, RX VrefLevel [Byte0]: 33
1646 01:15:43.390841 [Byte1]: 33
1647 01:15:43.395146
1648 01:15:43.395655 Set Vref, RX VrefLevel [Byte0]: 34
1649 01:15:43.398180 [Byte1]: 34
1650 01:15:43.402611
1651 01:15:43.403070 Set Vref, RX VrefLevel [Byte0]: 35
1652 01:15:43.405475 [Byte1]: 35
1653 01:15:43.409795
1654 01:15:43.410207 Set Vref, RX VrefLevel [Byte0]: 36
1655 01:15:43.413237 [Byte1]: 36
1656 01:15:43.417496
1657 01:15:43.418015 Set Vref, RX VrefLevel [Byte0]: 37
1658 01:15:43.421072 [Byte1]: 37
1659 01:15:43.425136
1660 01:15:43.425549 Set Vref, RX VrefLevel [Byte0]: 38
1661 01:15:43.428639 [Byte1]: 38
1662 01:15:43.432752
1663 01:15:43.433196 Set Vref, RX VrefLevel [Byte0]: 39
1664 01:15:43.436461 [Byte1]: 39
1665 01:15:43.440189
1666 01:15:43.440627 Set Vref, RX VrefLevel [Byte0]: 40
1667 01:15:43.444029 [Byte1]: 40
1668 01:15:43.447749
1669 01:15:43.448228 Set Vref, RX VrefLevel [Byte0]: 41
1670 01:15:43.451277 [Byte1]: 41
1671 01:15:43.455478
1672 01:15:43.456092 Set Vref, RX VrefLevel [Byte0]: 42
1673 01:15:43.458637 [Byte1]: 42
1674 01:15:43.463536
1675 01:15:43.464136 Set Vref, RX VrefLevel [Byte0]: 43
1676 01:15:43.466588 [Byte1]: 43
1677 01:15:43.470587
1678 01:15:43.471132 Set Vref, RX VrefLevel [Byte0]: 44
1679 01:15:43.473683 [Byte1]: 44
1680 01:15:43.478257
1681 01:15:43.478672 Set Vref, RX VrefLevel [Byte0]: 45
1682 01:15:43.481771 [Byte1]: 45
1683 01:15:43.486141
1684 01:15:43.486553 Set Vref, RX VrefLevel [Byte0]: 46
1685 01:15:43.489377 [Byte1]: 46
1686 01:15:43.493487
1687 01:15:43.493901 Set Vref, RX VrefLevel [Byte0]: 47
1688 01:15:43.497071 [Byte1]: 47
1689 01:15:43.501315
1690 01:15:43.501772 Set Vref, RX VrefLevel [Byte0]: 48
1691 01:15:43.504350 [Byte1]: 48
1692 01:15:43.508628
1693 01:15:43.509053 Set Vref, RX VrefLevel [Byte0]: 49
1694 01:15:43.511694 [Byte1]: 49
1695 01:15:43.516536
1696 01:15:43.516970 Set Vref, RX VrefLevel [Byte0]: 50
1697 01:15:43.519731 [Byte1]: 50
1698 01:15:43.523730
1699 01:15:43.524178 Set Vref, RX VrefLevel [Byte0]: 51
1700 01:15:43.527111 [Byte1]: 51
1701 01:15:43.531214
1702 01:15:43.531640 Set Vref, RX VrefLevel [Byte0]: 52
1703 01:15:43.534490 [Byte1]: 52
1704 01:15:43.538954
1705 01:15:43.539387 Set Vref, RX VrefLevel [Byte0]: 53
1706 01:15:43.542283 [Byte1]: 53
1707 01:15:43.546404
1708 01:15:43.546828 Set Vref, RX VrefLevel [Byte0]: 54
1709 01:15:43.549900 [Byte1]: 54
1710 01:15:43.554401
1711 01:15:43.554824 Set Vref, RX VrefLevel [Byte0]: 55
1712 01:15:43.557694 [Byte1]: 55
1713 01:15:43.561991
1714 01:15:43.562474 Set Vref, RX VrefLevel [Byte0]: 56
1715 01:15:43.565090 [Byte1]: 56
1716 01:15:43.569761
1717 01:15:43.570178 Set Vref, RX VrefLevel [Byte0]: 57
1718 01:15:43.572981 [Byte1]: 57
1719 01:15:43.577139
1720 01:15:43.577557 Set Vref, RX VrefLevel [Byte0]: 58
1721 01:15:43.580520 [Byte1]: 58
1722 01:15:43.584416
1723 01:15:43.584834 Set Vref, RX VrefLevel [Byte0]: 59
1724 01:15:43.587959 [Byte1]: 59
1725 01:15:43.592271
1726 01:15:43.592689 Set Vref, RX VrefLevel [Byte0]: 60
1727 01:15:43.595279 [Byte1]: 60
1728 01:15:43.600077
1729 01:15:43.600491 Set Vref, RX VrefLevel [Byte0]: 61
1730 01:15:43.603015 [Byte1]: 61
1731 01:15:43.607287
1732 01:15:43.607701 Set Vref, RX VrefLevel [Byte0]: 62
1733 01:15:43.611059 [Byte1]: 62
1734 01:15:43.615293
1735 01:15:43.615719 Set Vref, RX VrefLevel [Byte0]: 63
1736 01:15:43.618179 [Byte1]: 63
1737 01:15:43.622890
1738 01:15:43.623300 Set Vref, RX VrefLevel [Byte0]: 64
1739 01:15:43.626030 [Byte1]: 64
1740 01:15:43.630291
1741 01:15:43.630703 Set Vref, RX VrefLevel [Byte0]: 65
1742 01:15:43.633562 [Byte1]: 65
1743 01:15:43.638059
1744 01:15:43.638471 Set Vref, RX VrefLevel [Byte0]: 66
1745 01:15:43.640945 [Byte1]: 66
1746 01:15:43.645260
1747 01:15:43.645674 Set Vref, RX VrefLevel [Byte0]: 67
1748 01:15:43.648665 [Byte1]: 67
1749 01:15:43.653463
1750 01:15:43.653874 Set Vref, RX VrefLevel [Byte0]: 68
1751 01:15:43.656294 [Byte1]: 68
1752 01:15:43.660464
1753 01:15:43.660872 Set Vref, RX VrefLevel [Byte0]: 69
1754 01:15:43.664126 [Byte1]: 69
1755 01:15:43.668131
1756 01:15:43.668546 Set Vref, RX VrefLevel [Byte0]: 70
1757 01:15:43.671761 [Byte1]: 70
1758 01:15:43.676080
1759 01:15:43.676493 Set Vref, RX VrefLevel [Byte0]: 71
1760 01:15:43.679055 [Byte1]: 71
1761 01:15:43.683358
1762 01:15:43.683772 Set Vref, RX VrefLevel [Byte0]: 72
1763 01:15:43.686952 [Byte1]: 72
1764 01:15:43.690923
1765 01:15:43.691442 Set Vref, RX VrefLevel [Byte0]: 73
1766 01:15:43.694748 [Byte1]: 73
1767 01:15:43.698853
1768 01:15:43.699268 Set Vref, RX VrefLevel [Byte0]: 74
1769 01:15:43.701783 [Byte1]: 74
1770 01:15:43.706404
1771 01:15:43.706485 Set Vref, RX VrefLevel [Byte0]: 75
1772 01:15:43.709224 [Byte1]: 75
1773 01:15:43.713579
1774 01:15:43.713659 Final RX Vref Byte 0 = 56 to rank0
1775 01:15:43.717310 Final RX Vref Byte 1 = 58 to rank0
1776 01:15:43.720276 Final RX Vref Byte 0 = 56 to rank1
1777 01:15:43.723271 Final RX Vref Byte 1 = 58 to rank1==
1778 01:15:43.726939 Dram Type= 6, Freq= 0, CH_1, rank 0
1779 01:15:43.733096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1780 01:15:43.733225 ==
1781 01:15:43.733307 DQS Delay:
1782 01:15:43.736660 DQS0 = 0, DQS1 = 0
1783 01:15:43.736761 DQM Delay:
1784 01:15:43.736859 DQM0 = 85, DQM1 = 80
1785 01:15:43.740346 DQ Delay:
1786 01:15:43.743170 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1787 01:15:43.746807 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =80
1788 01:15:43.749814 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
1789 01:15:43.753478 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1790 01:15:43.753627
1791 01:15:43.753745
1792 01:15:43.760192 [DQSOSCAuto] RK0, (LSB)MR18= 0x1529, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
1793 01:15:43.763056 CH1 RK0: MR19=606, MR18=1529
1794 01:15:43.769930 CH1_RK0: MR19=0x606, MR18=0x1529, DQSOSC=399, MR23=63, INC=92, DEC=61
1795 01:15:43.770179
1796 01:15:43.773747 ----->DramcWriteLeveling(PI) begin...
1797 01:15:43.774142 ==
1798 01:15:43.776306 Dram Type= 6, Freq= 0, CH_1, rank 1
1799 01:15:43.779778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1800 01:15:43.780208 ==
1801 01:15:43.782981 Write leveling (Byte 0): 25 => 25
1802 01:15:43.786744 Write leveling (Byte 1): 27 => 27
1803 01:15:43.789692 DramcWriteLeveling(PI) end<-----
1804 01:15:43.790107
1805 01:15:43.790476 ==
1806 01:15:43.793368 Dram Type= 6, Freq= 0, CH_1, rank 1
1807 01:15:43.796154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1808 01:15:43.796607 ==
1809 01:15:43.799441 [Gating] SW mode calibration
1810 01:15:43.806531 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1811 01:15:43.813028 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1812 01:15:43.816254 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1813 01:15:43.822839 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1814 01:15:43.826009 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 01:15:43.828965 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 01:15:43.836078 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 01:15:43.838960 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 01:15:43.842667 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 01:15:43.849056 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 01:15:43.852719 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 01:15:43.855939 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 01:15:43.862618 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 01:15:43.865640 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 01:15:43.869259 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 01:15:43.875594 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 01:15:43.878860 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 01:15:43.881908 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 01:15:43.888539 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 01:15:43.891974 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1830 01:15:43.895296 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1831 01:15:43.902167 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 01:15:43.905627 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 01:15:43.908371 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 01:15:43.915551 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 01:15:43.918578 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 01:15:43.922307 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 01:15:43.928194 0 9 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1838 01:15:43.931714 0 9 8 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
1839 01:15:43.935238 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 01:15:43.941383 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 01:15:43.944945 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 01:15:43.948354 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 01:15:43.951421 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 01:15:43.957919 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1845 01:15:43.961699 0 10 4 | B1->B0 | 3333 2727 | 1 0 | (1 0) (0 0)
1846 01:15:43.964767 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
1847 01:15:43.971371 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 01:15:43.975175 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 01:15:43.978306 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 01:15:43.985249 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 01:15:43.988403 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 01:15:43.991722 0 11 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1853 01:15:43.998083 0 11 4 | B1->B0 | 2525 4242 | 0 0 | (0 0) (0 0)
1854 01:15:44.001391 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
1855 01:15:44.005187 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 01:15:44.011737 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 01:15:44.014485 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 01:15:44.017886 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 01:15:44.024378 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 01:15:44.027996 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1861 01:15:44.031354 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1862 01:15:44.037751 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 01:15:44.041312 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 01:15:44.044346 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 01:15:44.051176 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 01:15:44.054575 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 01:15:44.057675 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 01:15:44.064748 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 01:15:44.067666 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 01:15:44.070780 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 01:15:44.077501 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 01:15:44.081089 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 01:15:44.084047 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 01:15:44.090691 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 01:15:44.094420 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 01:15:44.097609 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 01:15:44.104083 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1878 01:15:44.104603 Total UI for P1: 0, mck2ui 16
1879 01:15:44.110917 best dqsien dly found for B0: ( 0, 14, 2)
1880 01:15:44.111359 Total UI for P1: 0, mck2ui 16
1881 01:15:44.114301 best dqsien dly found for B1: ( 0, 14, 2)
1882 01:15:44.121165 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1883 01:15:44.124175 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1884 01:15:44.124623
1885 01:15:44.127304 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1886 01:15:44.130885 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1887 01:15:44.134147 [Gating] SW calibration Done
1888 01:15:44.134626 ==
1889 01:15:44.137392 Dram Type= 6, Freq= 0, CH_1, rank 1
1890 01:15:44.140592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1891 01:15:44.141034 ==
1892 01:15:44.141390 RX Vref Scan: 0
1893 01:15:44.144504
1894 01:15:44.144934 RX Vref 0 -> 0, step: 1
1895 01:15:44.145356
1896 01:15:44.147672 RX Delay -130 -> 252, step: 16
1897 01:15:44.151257 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1898 01:15:44.154139 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1899 01:15:44.160826 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1900 01:15:44.163816 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1901 01:15:44.167407 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1902 01:15:44.170939 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1903 01:15:44.173981 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1904 01:15:44.180764 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1905 01:15:44.184287 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1906 01:15:44.187324 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1907 01:15:44.190530 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1908 01:15:44.194304 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1909 01:15:44.200233 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1910 01:15:44.203693 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1911 01:15:44.207225 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1912 01:15:44.210110 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1913 01:15:44.213798 ==
1914 01:15:44.214212 Dram Type= 6, Freq= 0, CH_1, rank 1
1915 01:15:44.220447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1916 01:15:44.220862 ==
1917 01:15:44.221216 DQS Delay:
1918 01:15:44.223477 DQS0 = 0, DQS1 = 0
1919 01:15:44.223909 DQM Delay:
1920 01:15:44.226915 DQM0 = 83, DQM1 = 80
1921 01:15:44.227273 DQ Delay:
1922 01:15:44.230106 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1923 01:15:44.233739 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1924 01:15:44.236691 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1925 01:15:44.240006 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1926 01:15:44.240540
1927 01:15:44.240874
1928 01:15:44.241181 ==
1929 01:15:44.243291 Dram Type= 6, Freq= 0, CH_1, rank 1
1930 01:15:44.246550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1931 01:15:44.247112 ==
1932 01:15:44.247585
1933 01:15:44.248047
1934 01:15:44.250119 TX Vref Scan disable
1935 01:15:44.253418 == TX Byte 0 ==
1936 01:15:44.256622 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1937 01:15:44.259839 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1938 01:15:44.263368 == TX Byte 1 ==
1939 01:15:44.266515 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1940 01:15:44.269968 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1941 01:15:44.270441 ==
1942 01:15:44.273618 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 01:15:44.276583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 01:15:44.279615 ==
1945 01:15:44.291034 TX Vref=22, minBit 0, minWin=27, winSum=442
1946 01:15:44.294843 TX Vref=24, minBit 1, minWin=27, winSum=447
1947 01:15:44.297906 TX Vref=26, minBit 3, minWin=27, winSum=453
1948 01:15:44.300922 TX Vref=28, minBit 0, minWin=28, winSum=455
1949 01:15:44.304665 TX Vref=30, minBit 1, minWin=28, winSum=458
1950 01:15:44.311169 TX Vref=32, minBit 0, minWin=28, winSum=457
1951 01:15:44.314199 [TxChooseVref] Worse bit 1, Min win 28, Win sum 458, Final Vref 30
1952 01:15:44.314618
1953 01:15:44.317788 Final TX Range 1 Vref 30
1954 01:15:44.318332
1955 01:15:44.318829 ==
1956 01:15:44.321018 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 01:15:44.324664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 01:15:44.327668 ==
1959 01:15:44.328177
1960 01:15:44.328512
1961 01:15:44.329108 TX Vref Scan disable
1962 01:15:44.331261 == TX Byte 0 ==
1963 01:15:44.334435 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1964 01:15:44.341167 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1965 01:15:44.341581 == TX Byte 1 ==
1966 01:15:44.344602 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1967 01:15:44.351591 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1968 01:15:44.352163
1969 01:15:44.352513 [DATLAT]
1970 01:15:44.352824 Freq=800, CH1 RK1
1971 01:15:44.353122
1972 01:15:44.354366 DATLAT Default: 0xa
1973 01:15:44.354781 0, 0xFFFF, sum = 0
1974 01:15:44.357322 1, 0xFFFF, sum = 0
1975 01:15:44.360900 2, 0xFFFF, sum = 0
1976 01:15:44.361390 3, 0xFFFF, sum = 0
1977 01:15:44.363831 4, 0xFFFF, sum = 0
1978 01:15:44.364304 5, 0xFFFF, sum = 0
1979 01:15:44.367447 6, 0xFFFF, sum = 0
1980 01:15:44.367865 7, 0xFFFF, sum = 0
1981 01:15:44.370971 8, 0xFFFF, sum = 0
1982 01:15:44.371391 9, 0x0, sum = 1
1983 01:15:44.373868 10, 0x0, sum = 2
1984 01:15:44.374291 11, 0x0, sum = 3
1985 01:15:44.377615 12, 0x0, sum = 4
1986 01:15:44.378036 best_step = 10
1987 01:15:44.378361
1988 01:15:44.378696 ==
1989 01:15:44.380586 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 01:15:44.384372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 01:15:44.384804 ==
1992 01:15:44.387444 RX Vref Scan: 0
1993 01:15:44.387855
1994 01:15:44.390629 RX Vref 0 -> 0, step: 1
1995 01:15:44.391044
1996 01:15:44.391411 RX Delay -95 -> 252, step: 8
1997 01:15:44.398004 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1998 01:15:44.401136 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1999 01:15:44.404773 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2000 01:15:44.407769 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
2001 01:15:44.411424 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
2002 01:15:44.417901 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2003 01:15:44.421405 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2004 01:15:44.424595 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2005 01:15:44.427642 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2006 01:15:44.431239 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2007 01:15:44.437851 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2008 01:15:44.440884 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2009 01:15:44.444002 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2010 01:15:44.447576 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2011 01:15:44.454354 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2012 01:15:44.457979 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2013 01:15:44.458508 ==
2014 01:15:44.460682 Dram Type= 6, Freq= 0, CH_1, rank 1
2015 01:15:44.464301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2016 01:15:44.464720 ==
2017 01:15:44.467398 DQS Delay:
2018 01:15:44.467812 DQS0 = 0, DQS1 = 0
2019 01:15:44.468189 DQM Delay:
2020 01:15:44.470870 DQM0 = 87, DQM1 = 82
2021 01:15:44.471285 DQ Delay:
2022 01:15:44.473987 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2023 01:15:44.477605 DQ4 =88, DQ5 =96, DQ6 =92, DQ7 =84
2024 01:15:44.480808 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
2025 01:15:44.484188 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2026 01:15:44.484602
2027 01:15:44.484927
2028 01:15:44.494132 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2029 01:15:44.494552 CH1 RK1: MR19=606, MR18=1E3A
2030 01:15:44.500781 CH1_RK1: MR19=0x606, MR18=0x1E3A, DQSOSC=395, MR23=63, INC=94, DEC=63
2031 01:15:44.504043 [RxdqsGatingPostProcess] freq 800
2032 01:15:44.510344 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2033 01:15:44.513604 Pre-setting of DQS Precalculation
2034 01:15:44.516780 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2035 01:15:44.523778 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2036 01:15:44.533492 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2037 01:15:44.533914
2038 01:15:44.534245
2039 01:15:44.537318 [Calibration Summary] 1600 Mbps
2040 01:15:44.537735 CH 0, Rank 0
2041 01:15:44.540150 SW Impedance : PASS
2042 01:15:44.540797 DUTY Scan : NO K
2043 01:15:44.543784 ZQ Calibration : PASS
2044 01:15:44.546776 Jitter Meter : NO K
2045 01:15:44.547189 CBT Training : PASS
2046 01:15:44.549895 Write leveling : PASS
2047 01:15:44.553560 RX DQS gating : PASS
2048 01:15:44.553974 RX DQ/DQS(RDDQC) : PASS
2049 01:15:44.556579 TX DQ/DQS : PASS
2050 01:15:44.556996 RX DATLAT : PASS
2051 01:15:44.560140 RX DQ/DQS(Engine): PASS
2052 01:15:44.563084 TX OE : NO K
2053 01:15:44.563498 All Pass.
2054 01:15:44.563826
2055 01:15:44.564178 CH 0, Rank 1
2056 01:15:44.566720 SW Impedance : PASS
2057 01:15:44.569819 DUTY Scan : NO K
2058 01:15:44.570236 ZQ Calibration : PASS
2059 01:15:44.573519 Jitter Meter : NO K
2060 01:15:44.577029 CBT Training : PASS
2061 01:15:44.577442 Write leveling : PASS
2062 01:15:44.580165 RX DQS gating : PASS
2063 01:15:44.583314 RX DQ/DQS(RDDQC) : PASS
2064 01:15:44.583728 TX DQ/DQS : PASS
2065 01:15:44.586828 RX DATLAT : PASS
2066 01:15:44.590062 RX DQ/DQS(Engine): PASS
2067 01:15:44.590475 TX OE : NO K
2068 01:15:44.593000 All Pass.
2069 01:15:44.593410
2070 01:15:44.593739 CH 1, Rank 0
2071 01:15:44.596702 SW Impedance : PASS
2072 01:15:44.597116 DUTY Scan : NO K
2073 01:15:44.599612 ZQ Calibration : PASS
2074 01:15:44.603279 Jitter Meter : NO K
2075 01:15:44.603689 CBT Training : PASS
2076 01:15:44.606485 Write leveling : PASS
2077 01:15:44.609944 RX DQS gating : PASS
2078 01:15:44.610357 RX DQ/DQS(RDDQC) : PASS
2079 01:15:44.613430 TX DQ/DQS : PASS
2080 01:15:44.613877 RX DATLAT : PASS
2081 01:15:44.616390 RX DQ/DQS(Engine): PASS
2082 01:15:44.619607 TX OE : NO K
2083 01:15:44.620059 All Pass.
2084 01:15:44.620394
2085 01:15:44.620698 CH 1, Rank 1
2086 01:15:44.622953 SW Impedance : PASS
2087 01:15:44.626562 DUTY Scan : NO K
2088 01:15:44.626976 ZQ Calibration : PASS
2089 01:15:44.630200 Jitter Meter : NO K
2090 01:15:44.633211 CBT Training : PASS
2091 01:15:44.633629 Write leveling : PASS
2092 01:15:44.636122 RX DQS gating : PASS
2093 01:15:44.639437 RX DQ/DQS(RDDQC) : PASS
2094 01:15:44.639910 TX DQ/DQS : PASS
2095 01:15:44.642847 RX DATLAT : PASS
2096 01:15:44.646319 RX DQ/DQS(Engine): PASS
2097 01:15:44.646751 TX OE : NO K
2098 01:15:44.649609 All Pass.
2099 01:15:44.650160
2100 01:15:44.650620 DramC Write-DBI off
2101 01:15:44.652533 PER_BANK_REFRESH: Hybrid Mode
2102 01:15:44.652953 TX_TRACKING: ON
2103 01:15:44.656140 [GetDramInforAfterCalByMRR] Vendor 6.
2104 01:15:44.662749 [GetDramInforAfterCalByMRR] Revision 606.
2105 01:15:44.666424 [GetDramInforAfterCalByMRR] Revision 2 0.
2106 01:15:44.666844 MR0 0x3b3b
2107 01:15:44.667177 MR8 0x5151
2108 01:15:44.669356 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2109 01:15:44.672544
2110 01:15:44.672963 MR0 0x3b3b
2111 01:15:44.673293 MR8 0x5151
2112 01:15:44.676237 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2113 01:15:44.676707
2114 01:15:44.686184 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2115 01:15:44.689371 [FAST_K] Save calibration result to emmc
2116 01:15:44.692517 [FAST_K] Save calibration result to emmc
2117 01:15:44.696135 dram_init: config_dvfs: 1
2118 01:15:44.699195 dramc_set_vcore_voltage set vcore to 662500
2119 01:15:44.702772 Read voltage for 1200, 2
2120 01:15:44.703192 Vio18 = 0
2121 01:15:44.703528 Vcore = 662500
2122 01:15:44.705658 Vdram = 0
2123 01:15:44.706074 Vddq = 0
2124 01:15:44.706410 Vmddr = 0
2125 01:15:44.712610 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2126 01:15:44.716133 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2127 01:15:44.719314 MEM_TYPE=3, freq_sel=15
2128 01:15:44.722330 sv_algorithm_assistance_LP4_1600
2129 01:15:44.725777 ============ PULL DRAM RESETB DOWN ============
2130 01:15:44.728840 ========== PULL DRAM RESETB DOWN end =========
2131 01:15:44.735724 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2132 01:15:44.739526 ===================================
2133 01:15:44.739992 LPDDR4 DRAM CONFIGURATION
2134 01:15:44.742565 ===================================
2135 01:15:44.745530 EX_ROW_EN[0] = 0x0
2136 01:15:44.748925 EX_ROW_EN[1] = 0x0
2137 01:15:44.749344 LP4Y_EN = 0x0
2138 01:15:44.752178 WORK_FSP = 0x0
2139 01:15:44.752595 WL = 0x4
2140 01:15:44.755500 RL = 0x4
2141 01:15:44.755946 BL = 0x2
2142 01:15:44.758783 RPST = 0x0
2143 01:15:44.759197 RD_PRE = 0x0
2144 01:15:44.762449 WR_PRE = 0x1
2145 01:15:44.762924 WR_PST = 0x0
2146 01:15:44.765362 DBI_WR = 0x0
2147 01:15:44.765794 DBI_RD = 0x0
2148 01:15:44.769132 OTF = 0x1
2149 01:15:44.772381 ===================================
2150 01:15:44.775986 ===================================
2151 01:15:44.776488 ANA top config
2152 01:15:44.778501 ===================================
2153 01:15:44.782007 DLL_ASYNC_EN = 0
2154 01:15:44.785574 ALL_SLAVE_EN = 0
2155 01:15:44.788557 NEW_RANK_MODE = 1
2156 01:15:44.791835 DLL_IDLE_MODE = 1
2157 01:15:44.792382 LP45_APHY_COMB_EN = 1
2158 01:15:44.795457 TX_ODT_DIS = 1
2159 01:15:44.798517 NEW_8X_MODE = 1
2160 01:15:44.801442 ===================================
2161 01:15:44.804923 ===================================
2162 01:15:44.808716 data_rate = 2400
2163 01:15:44.811595 CKR = 1
2164 01:15:44.812054 DQ_P2S_RATIO = 8
2165 01:15:44.814767 ===================================
2166 01:15:44.818357 CA_P2S_RATIO = 8
2167 01:15:44.821538 DQ_CA_OPEN = 0
2168 01:15:44.825124 DQ_SEMI_OPEN = 0
2169 01:15:44.827971 CA_SEMI_OPEN = 0
2170 01:15:44.831599 CA_FULL_RATE = 0
2171 01:15:44.832057 DQ_CKDIV4_EN = 0
2172 01:15:44.834765 CA_CKDIV4_EN = 0
2173 01:15:44.838374 CA_PREDIV_EN = 0
2174 01:15:44.841536 PH8_DLY = 17
2175 01:15:44.844640 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2176 01:15:44.848625 DQ_AAMCK_DIV = 4
2177 01:15:44.849091 CA_AAMCK_DIV = 4
2178 01:15:44.851247 CA_ADMCK_DIV = 4
2179 01:15:44.854949 DQ_TRACK_CA_EN = 0
2180 01:15:44.857969 CA_PICK = 1200
2181 01:15:44.861014 CA_MCKIO = 1200
2182 01:15:44.864534 MCKIO_SEMI = 0
2183 01:15:44.867562 PLL_FREQ = 2366
2184 01:15:44.871231 DQ_UI_PI_RATIO = 32
2185 01:15:44.871648 CA_UI_PI_RATIO = 0
2186 01:15:44.874487 ===================================
2187 01:15:44.877750 ===================================
2188 01:15:44.880842 memory_type:LPDDR4
2189 01:15:44.884159 GP_NUM : 10
2190 01:15:44.884592 SRAM_EN : 1
2191 01:15:44.887778 MD32_EN : 0
2192 01:15:44.891139 ===================================
2193 01:15:44.894377 [ANA_INIT] >>>>>>>>>>>>>>
2194 01:15:44.897726 <<<<<< [CONFIGURE PHASE]: ANA_TX
2195 01:15:44.900877 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2196 01:15:44.904083 ===================================
2197 01:15:44.904505 data_rate = 2400,PCW = 0X5b00
2198 01:15:44.907416 ===================================
2199 01:15:44.910836 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2200 01:15:44.917547 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2201 01:15:44.924058 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2202 01:15:44.927702 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2203 01:15:44.930788 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2204 01:15:44.934250 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2205 01:15:44.937225 [ANA_INIT] flow start
2206 01:15:44.940479 [ANA_INIT] PLL >>>>>>>>
2207 01:15:44.940892 [ANA_INIT] PLL <<<<<<<<
2208 01:15:44.944013 [ANA_INIT] MIDPI >>>>>>>>
2209 01:15:44.947078 [ANA_INIT] MIDPI <<<<<<<<
2210 01:15:44.947492 [ANA_INIT] DLL >>>>>>>>
2211 01:15:44.950741 [ANA_INIT] DLL <<<<<<<<
2212 01:15:44.953829 [ANA_INIT] flow end
2213 01:15:44.957374 ============ LP4 DIFF to SE enter ============
2214 01:15:44.960392 ============ LP4 DIFF to SE exit ============
2215 01:15:44.964017 [ANA_INIT] <<<<<<<<<<<<<
2216 01:15:44.967071 [Flow] Enable top DCM control >>>>>
2217 01:15:44.970869 [Flow] Enable top DCM control <<<<<
2218 01:15:44.973835 Enable DLL master slave shuffle
2219 01:15:44.977031 ==============================================================
2220 01:15:44.980695 Gating Mode config
2221 01:15:44.987076 ==============================================================
2222 01:15:44.987597 Config description:
2223 01:15:44.996706 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2224 01:15:45.003486 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2225 01:15:45.006979 SELPH_MODE 0: By rank 1: By Phase
2226 01:15:45.013374 ==============================================================
2227 01:15:45.016504 GAT_TRACK_EN = 1
2228 01:15:45.019778 RX_GATING_MODE = 2
2229 01:15:45.023698 RX_GATING_TRACK_MODE = 2
2230 01:15:45.026571 SELPH_MODE = 1
2231 01:15:45.029996 PICG_EARLY_EN = 1
2232 01:15:45.033032 VALID_LAT_VALUE = 1
2233 01:15:45.036443 ==============================================================
2234 01:15:45.039977 Enter into Gating configuration >>>>
2235 01:15:45.042744 Exit from Gating configuration <<<<
2236 01:15:45.046583 Enter into DVFS_PRE_config >>>>>
2237 01:15:45.059419 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2238 01:15:45.062894 Exit from DVFS_PRE_config <<<<<
2239 01:15:45.063358 Enter into PICG configuration >>>>
2240 01:15:45.066097 Exit from PICG configuration <<<<
2241 01:15:45.069878 [RX_INPUT] configuration >>>>>
2242 01:15:45.072983 [RX_INPUT] configuration <<<<<
2243 01:15:45.079611 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2244 01:15:45.082729 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2245 01:15:45.089415 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2246 01:15:45.096299 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2247 01:15:45.102734 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2248 01:15:45.109372 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2249 01:15:45.112384 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2250 01:15:45.116074 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2251 01:15:45.119171 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2252 01:15:45.126026 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2253 01:15:45.128884 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2254 01:15:45.132406 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2255 01:15:45.135700 ===================================
2256 01:15:45.138966 LPDDR4 DRAM CONFIGURATION
2257 01:15:45.142431 ===================================
2258 01:15:45.145459 EX_ROW_EN[0] = 0x0
2259 01:15:45.145877 EX_ROW_EN[1] = 0x0
2260 01:15:45.149025 LP4Y_EN = 0x0
2261 01:15:45.149482 WORK_FSP = 0x0
2262 01:15:45.152442 WL = 0x4
2263 01:15:45.152884 RL = 0x4
2264 01:15:45.155635 BL = 0x2
2265 01:15:45.156081 RPST = 0x0
2266 01:15:45.158955 RD_PRE = 0x0
2267 01:15:45.159417 WR_PRE = 0x1
2268 01:15:45.162077 WR_PST = 0x0
2269 01:15:45.162494 DBI_WR = 0x0
2270 01:15:45.165632 DBI_RD = 0x0
2271 01:15:45.166052 OTF = 0x1
2272 01:15:45.168930 ===================================
2273 01:15:45.175487 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2274 01:15:45.178643 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2275 01:15:45.181699 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2276 01:15:45.185359 ===================================
2277 01:15:45.188579 LPDDR4 DRAM CONFIGURATION
2278 01:15:45.191978 ===================================
2279 01:15:45.195481 EX_ROW_EN[0] = 0x10
2280 01:15:45.196054 EX_ROW_EN[1] = 0x0
2281 01:15:45.198738 LP4Y_EN = 0x0
2282 01:15:45.199158 WORK_FSP = 0x0
2283 01:15:45.201822 WL = 0x4
2284 01:15:45.202241 RL = 0x4
2285 01:15:45.205170 BL = 0x2
2286 01:15:45.205588 RPST = 0x0
2287 01:15:45.208354 RD_PRE = 0x0
2288 01:15:45.208866 WR_PRE = 0x1
2289 01:15:45.212107 WR_PST = 0x0
2290 01:15:45.212527 DBI_WR = 0x0
2291 01:15:45.215026 DBI_RD = 0x0
2292 01:15:45.215447 OTF = 0x1
2293 01:15:45.218171 ===================================
2294 01:15:45.224900 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2295 01:15:45.225358 ==
2296 01:15:45.228477 Dram Type= 6, Freq= 0, CH_0, rank 0
2297 01:15:45.234639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2298 01:15:45.235094 ==
2299 01:15:45.235440 [Duty_Offset_Calibration]
2300 01:15:45.238628 B0:2 B1:0 CA:4
2301 01:15:45.239041
2302 01:15:45.241473 [DutyScan_Calibration_Flow] k_type=0
2303 01:15:45.250010
2304 01:15:45.250424 ==CLK 0==
2305 01:15:45.253519 Final CLK duty delay cell = -4
2306 01:15:45.256684 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2307 01:15:45.259831 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2308 01:15:45.263258 [-4] AVG Duty = 4937%(X100)
2309 01:15:45.263553
2310 01:15:45.266381 CH0 CLK Duty spec in!! Max-Min= 187%
2311 01:15:45.269638 [DutyScan_Calibration_Flow] ====Done====
2312 01:15:45.269935
2313 01:15:45.272887 [DutyScan_Calibration_Flow] k_type=1
2314 01:15:45.288448
2315 01:15:45.288753 ==DQS 0 ==
2316 01:15:45.292232 Final DQS duty delay cell = -4
2317 01:15:45.295115 [-4] MAX Duty = 4938%(X100), DQS PI = 0
2318 01:15:45.298142 [-4] MIN Duty = 4876%(X100), DQS PI = 2
2319 01:15:45.301870 [-4] AVG Duty = 4907%(X100)
2320 01:15:45.302286
2321 01:15:45.302612 ==DQS 1 ==
2322 01:15:45.305039 Final DQS duty delay cell = 0
2323 01:15:45.308656 [0] MAX Duty = 5125%(X100), DQS PI = 4
2324 01:15:45.311642 [0] MIN Duty = 5000%(X100), DQS PI = 0
2325 01:15:45.315104 [0] AVG Duty = 5062%(X100)
2326 01:15:45.315516
2327 01:15:45.318440 CH0 DQS 0 Duty spec in!! Max-Min= 62%
2328 01:15:45.318857
2329 01:15:45.321645 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2330 01:15:45.324709 [DutyScan_Calibration_Flow] ====Done====
2331 01:15:45.325122
2332 01:15:45.328001 [DutyScan_Calibration_Flow] k_type=3
2333 01:15:45.344888
2334 01:15:45.345390 ==DQM 0 ==
2335 01:15:45.348584 Final DQM duty delay cell = 0
2336 01:15:45.352000 [0] MAX Duty = 5125%(X100), DQS PI = 20
2337 01:15:45.354846 [0] MIN Duty = 4844%(X100), DQS PI = 52
2338 01:15:45.355231 [0] AVG Duty = 4984%(X100)
2339 01:15:45.358407
2340 01:15:45.358823 ==DQM 1 ==
2341 01:15:45.361777 Final DQM duty delay cell = 0
2342 01:15:45.365073 [0] MAX Duty = 4969%(X100), DQS PI = 2
2343 01:15:45.368126 [0] MIN Duty = 4875%(X100), DQS PI = 20
2344 01:15:45.368546 [0] AVG Duty = 4922%(X100)
2345 01:15:45.371704
2346 01:15:45.375448 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2347 01:15:45.375862
2348 01:15:45.378254 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2349 01:15:45.381347 [DutyScan_Calibration_Flow] ====Done====
2350 01:15:45.381761
2351 01:15:45.385234 [DutyScan_Calibration_Flow] k_type=2
2352 01:15:45.400613
2353 01:15:45.401025 ==DQ 0 ==
2354 01:15:45.404351 Final DQ duty delay cell = -4
2355 01:15:45.407299 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2356 01:15:45.410591 [-4] MIN Duty = 4844%(X100), DQS PI = 52
2357 01:15:45.414258 [-4] AVG Duty = 4922%(X100)
2358 01:15:45.414709
2359 01:15:45.415044 ==DQ 1 ==
2360 01:15:45.417079 Final DQ duty delay cell = 0
2361 01:15:45.420729 [0] MAX Duty = 5156%(X100), DQS PI = 6
2362 01:15:45.423472 [0] MIN Duty = 4938%(X100), DQS PI = 14
2363 01:15:45.427158 [0] AVG Duty = 5047%(X100)
2364 01:15:45.427631
2365 01:15:45.430215 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2366 01:15:45.430634
2367 01:15:45.433918 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2368 01:15:45.436873 [DutyScan_Calibration_Flow] ====Done====
2369 01:15:45.437550 ==
2370 01:15:45.441130 Dram Type= 6, Freq= 0, CH_1, rank 0
2371 01:15:45.443615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2372 01:15:45.444104 ==
2373 01:15:45.446965 [Duty_Offset_Calibration]
2374 01:15:45.447380 B0:0 B1:-1 CA:3
2375 01:15:45.447711
2376 01:15:45.449967 [DutyScan_Calibration_Flow] k_type=0
2377 01:15:45.460314
2378 01:15:45.460831 ==CLK 0==
2379 01:15:45.463198 Final CLK duty delay cell = -4
2380 01:15:45.466626 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2381 01:15:45.470530 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2382 01:15:45.473673 [-4] AVG Duty = 4938%(X100)
2383 01:15:45.474092
2384 01:15:45.476694 CH1 CLK Duty spec in!! Max-Min= 124%
2385 01:15:45.479731 [DutyScan_Calibration_Flow] ====Done====
2386 01:15:45.480186
2387 01:15:45.483320 [DutyScan_Calibration_Flow] k_type=1
2388 01:15:45.499792
2389 01:15:45.500361 ==DQS 0 ==
2390 01:15:45.503416 Final DQS duty delay cell = 0
2391 01:15:45.506655 [0] MAX Duty = 5187%(X100), DQS PI = 18
2392 01:15:45.509896 [0] MIN Duty = 4907%(X100), DQS PI = 38
2393 01:15:45.510458 [0] AVG Duty = 5047%(X100)
2394 01:15:45.512967
2395 01:15:45.513422 ==DQS 1 ==
2396 01:15:45.516590 Final DQS duty delay cell = 0
2397 01:15:45.519767 [0] MAX Duty = 5156%(X100), DQS PI = 8
2398 01:15:45.523079 [0] MIN Duty = 5031%(X100), DQS PI = 18
2399 01:15:45.526540 [0] AVG Duty = 5093%(X100)
2400 01:15:45.527002
2401 01:15:45.529353 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2402 01:15:45.529770
2403 01:15:45.532932 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2404 01:15:45.536217 [DutyScan_Calibration_Flow] ====Done====
2405 01:15:45.536636
2406 01:15:45.539583 [DutyScan_Calibration_Flow] k_type=3
2407 01:15:45.556130
2408 01:15:45.556565 ==DQM 0 ==
2409 01:15:45.559264 Final DQM duty delay cell = 0
2410 01:15:45.563057 [0] MAX Duty = 5031%(X100), DQS PI = 28
2411 01:15:45.566314 [0] MIN Duty = 4782%(X100), DQS PI = 38
2412 01:15:45.569714 [0] AVG Duty = 4906%(X100)
2413 01:15:45.570134
2414 01:15:45.570467 ==DQM 1 ==
2415 01:15:45.572646 Final DQM duty delay cell = 0
2416 01:15:45.576266 [0] MAX Duty = 5000%(X100), DQS PI = 34
2417 01:15:45.579242 [0] MIN Duty = 4813%(X100), DQS PI = 0
2418 01:15:45.582823 [0] AVG Duty = 4906%(X100)
2419 01:15:45.583242
2420 01:15:45.586253 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2421 01:15:45.586675
2422 01:15:45.589409 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2423 01:15:45.592503 [DutyScan_Calibration_Flow] ====Done====
2424 01:15:45.592989
2425 01:15:45.596188 [DutyScan_Calibration_Flow] k_type=2
2426 01:15:45.612129
2427 01:15:45.612614 ==DQ 0 ==
2428 01:15:45.615304 Final DQ duty delay cell = -4
2429 01:15:45.618623 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2430 01:15:45.621571 [-4] MIN Duty = 4844%(X100), DQS PI = 34
2431 01:15:45.625376 [-4] AVG Duty = 4937%(X100)
2432 01:15:45.625794
2433 01:15:45.626123 ==DQ 1 ==
2434 01:15:45.628459 Final DQ duty delay cell = 0
2435 01:15:45.631546 [0] MAX Duty = 5031%(X100), DQS PI = 34
2436 01:15:45.634908 [0] MIN Duty = 4844%(X100), DQS PI = 62
2437 01:15:45.638527 [0] AVG Duty = 4937%(X100)
2438 01:15:45.638946
2439 01:15:45.641575 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2440 01:15:45.641994
2441 01:15:45.645102 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2442 01:15:45.648172 [DutyScan_Calibration_Flow] ====Done====
2443 01:15:45.651703 nWR fixed to 30
2444 01:15:45.655167 [ModeRegInit_LP4] CH0 RK0
2445 01:15:45.655584 [ModeRegInit_LP4] CH0 RK1
2446 01:15:45.658221 [ModeRegInit_LP4] CH1 RK0
2447 01:15:45.661497 [ModeRegInit_LP4] CH1 RK1
2448 01:15:45.661931 match AC timing 7
2449 01:15:45.668233 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2450 01:15:45.671965 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2451 01:15:45.674760 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2452 01:15:45.681592 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2453 01:15:45.684956 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2454 01:15:45.685376 ==
2455 01:15:45.688158 Dram Type= 6, Freq= 0, CH_0, rank 0
2456 01:15:45.691206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2457 01:15:45.691626 ==
2458 01:15:45.698122 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2459 01:15:45.704498 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2460 01:15:45.712562 [CA 0] Center 39 (9~70) winsize 62
2461 01:15:45.715347 [CA 1] Center 39 (9~70) winsize 62
2462 01:15:45.719036 [CA 2] Center 35 (5~66) winsize 62
2463 01:15:45.722322 [CA 3] Center 35 (5~66) winsize 62
2464 01:15:45.725272 [CA 4] Center 33 (3~64) winsize 62
2465 01:15:45.728918 [CA 5] Center 33 (3~64) winsize 62
2466 01:15:45.729339
2467 01:15:45.732157 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2468 01:15:45.732577
2469 01:15:45.735320 [CATrainingPosCal] consider 1 rank data
2470 01:15:45.738541 u2DelayCellTimex100 = 270/100 ps
2471 01:15:45.742463 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2472 01:15:45.748509 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2473 01:15:45.752109 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2474 01:15:45.755566 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2475 01:15:45.758439 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2476 01:15:45.761890 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2477 01:15:45.762302
2478 01:15:45.765351 CA PerBit enable=1, Macro0, CA PI delay=33
2479 01:15:45.765779
2480 01:15:45.768962 [CBTSetCACLKResult] CA Dly = 33
2481 01:15:45.771719 CS Dly: 7 (0~38)
2482 01:15:45.772179 ==
2483 01:15:45.775502 Dram Type= 6, Freq= 0, CH_0, rank 1
2484 01:15:45.778569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2485 01:15:45.778981 ==
2486 01:15:45.785014 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2487 01:15:45.787841 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2488 01:15:45.797899 [CA 0] Center 39 (9~70) winsize 62
2489 01:15:45.801335 [CA 1] Center 39 (9~70) winsize 62
2490 01:15:45.804775 [CA 2] Center 35 (5~66) winsize 62
2491 01:15:45.807803 [CA 3] Center 35 (5~66) winsize 62
2492 01:15:45.811471 [CA 4] Center 34 (4~65) winsize 62
2493 01:15:45.814576 [CA 5] Center 33 (3~64) winsize 62
2494 01:15:45.815005
2495 01:15:45.817931 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2496 01:15:45.818340
2497 01:15:45.821143 [CATrainingPosCal] consider 2 rank data
2498 01:15:45.824246 u2DelayCellTimex100 = 270/100 ps
2499 01:15:45.827294 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2500 01:15:45.833839 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2501 01:15:45.837590 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2502 01:15:45.841312 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2503 01:15:45.844178 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2504 01:15:45.847687 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2505 01:15:45.848136
2506 01:15:45.850740 CA PerBit enable=1, Macro0, CA PI delay=33
2507 01:15:45.851267
2508 01:15:45.854311 [CBTSetCACLKResult] CA Dly = 33
2509 01:15:45.857376 CS Dly: 8 (0~41)
2510 01:15:45.857784
2511 01:15:45.860418 ----->DramcWriteLeveling(PI) begin...
2512 01:15:45.860878 ==
2513 01:15:45.863989 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 01:15:45.867332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2515 01:15:45.867862 ==
2516 01:15:45.870190 Write leveling (Byte 0): 31 => 31
2517 01:15:45.873588 Write leveling (Byte 1): 29 => 29
2518 01:15:45.876851 DramcWriteLeveling(PI) end<-----
2519 01:15:45.877258
2520 01:15:45.877584 ==
2521 01:15:45.880426 Dram Type= 6, Freq= 0, CH_0, rank 0
2522 01:15:45.883505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2523 01:15:45.884156 ==
2524 01:15:45.887086 [Gating] SW mode calibration
2525 01:15:45.893511 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2526 01:15:45.899785 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2527 01:15:45.903449 0 15 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
2528 01:15:45.906402 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
2529 01:15:45.913238 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 01:15:45.916203 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 01:15:45.922800 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 01:15:45.926190 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 01:15:45.929244 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2534 01:15:45.932884 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2535 01:15:45.939359 1 0 0 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
2536 01:15:45.942621 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2537 01:15:45.945633 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 01:15:45.952761 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 01:15:45.955695 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 01:15:45.959175 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 01:15:45.965872 1 0 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
2542 01:15:45.968870 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2543 01:15:45.972351 1 1 0 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
2544 01:15:45.978709 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2545 01:15:45.982041 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 01:15:45.985491 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 01:15:45.992115 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 01:15:45.995736 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 01:15:45.998580 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2550 01:15:46.005377 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2551 01:15:46.008525 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2552 01:15:46.012321 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 01:15:46.018852 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 01:15:46.021955 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 01:15:46.025626 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 01:15:46.032040 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 01:15:46.035812 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 01:15:46.038952 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 01:15:46.045584 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 01:15:46.048958 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 01:15:46.052337 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 01:15:46.059127 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 01:15:46.062402 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 01:15:46.065243 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 01:15:46.072438 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2566 01:15:46.075368 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2567 01:15:46.078880 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2568 01:15:46.082212 Total UI for P1: 0, mck2ui 16
2569 01:15:46.085950 best dqsien dly found for B0: ( 1, 3, 26)
2570 01:15:46.092426 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2571 01:15:46.095467 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2572 01:15:46.098794 Total UI for P1: 0, mck2ui 16
2573 01:15:46.101801 best dqsien dly found for B1: ( 1, 4, 4)
2574 01:15:46.105513 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2575 01:15:46.108434 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2576 01:15:46.109001
2577 01:15:46.111982 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2578 01:15:46.115009 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2579 01:15:46.118644 [Gating] SW calibration Done
2580 01:15:46.119189 ==
2581 01:15:46.122053 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 01:15:46.125075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 01:15:46.125487 ==
2584 01:15:46.128679 RX Vref Scan: 0
2585 01:15:46.129086
2586 01:15:46.131916 RX Vref 0 -> 0, step: 1
2587 01:15:46.132329
2588 01:15:46.132657 RX Delay -40 -> 252, step: 8
2589 01:15:46.138512 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2590 01:15:46.142214 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2591 01:15:46.145184 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2592 01:15:46.148754 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2593 01:15:46.151628 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2594 01:15:46.158174 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2595 01:15:46.162070 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2596 01:15:46.165108 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2597 01:15:46.168564 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2598 01:15:46.171446 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2599 01:15:46.178474 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2600 01:15:46.181199 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2601 01:15:46.184860 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2602 01:15:46.188203 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2603 01:15:46.192077 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2604 01:15:46.198263 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2605 01:15:46.198753 ==
2606 01:15:46.201152 Dram Type= 6, Freq= 0, CH_0, rank 0
2607 01:15:46.204464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2608 01:15:46.204949 ==
2609 01:15:46.205372 DQS Delay:
2610 01:15:46.208088 DQS0 = 0, DQS1 = 0
2611 01:15:46.208505 DQM Delay:
2612 01:15:46.211677 DQM0 = 118, DQM1 = 107
2613 01:15:46.212238 DQ Delay:
2614 01:15:46.214434 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2615 01:15:46.217899 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =127
2616 01:15:46.221158 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2617 01:15:46.224728 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2618 01:15:46.225290
2619 01:15:46.228109
2620 01:15:46.228625 ==
2621 01:15:46.231229 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 01:15:46.234454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 01:15:46.235044 ==
2624 01:15:46.235467
2625 01:15:46.235979
2626 01:15:46.237858 TX Vref Scan disable
2627 01:15:46.238432 == TX Byte 0 ==
2628 01:15:46.244622 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2629 01:15:46.247632 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2630 01:15:46.248272 == TX Byte 1 ==
2631 01:15:46.254474 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2632 01:15:46.257879 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2633 01:15:46.258301 ==
2634 01:15:46.260752 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 01:15:46.264453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 01:15:46.264879 ==
2637 01:15:46.276551 TX Vref=22, minBit 1, minWin=25, winSum=415
2638 01:15:46.280087 TX Vref=24, minBit 1, minWin=25, winSum=417
2639 01:15:46.283477 TX Vref=26, minBit 0, minWin=26, winSum=428
2640 01:15:46.286558 TX Vref=28, minBit 1, minWin=26, winSum=430
2641 01:15:46.289868 TX Vref=30, minBit 13, minWin=26, winSum=431
2642 01:15:46.296734 TX Vref=32, minBit 0, minWin=26, winSum=426
2643 01:15:46.299824 [TxChooseVref] Worse bit 13, Min win 26, Win sum 431, Final Vref 30
2644 01:15:46.300289
2645 01:15:46.303432 Final TX Range 1 Vref 30
2646 01:15:46.303850
2647 01:15:46.304232 ==
2648 01:15:46.306571 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 01:15:46.310102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 01:15:46.310520 ==
2651 01:15:46.313450
2652 01:15:46.313866
2653 01:15:46.314278 TX Vref Scan disable
2654 01:15:46.316856 == TX Byte 0 ==
2655 01:15:46.319878 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2656 01:15:46.323556 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2657 01:15:46.326663 == TX Byte 1 ==
2658 01:15:46.329980 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2659 01:15:46.333543 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2660 01:15:46.336675
2661 01:15:46.337091 [DATLAT]
2662 01:15:46.337420 Freq=1200, CH0 RK0
2663 01:15:46.337729
2664 01:15:46.339661 DATLAT Default: 0xd
2665 01:15:46.340119 0, 0xFFFF, sum = 0
2666 01:15:46.343175 1, 0xFFFF, sum = 0
2667 01:15:46.343600 2, 0xFFFF, sum = 0
2668 01:15:46.346682 3, 0xFFFF, sum = 0
2669 01:15:46.349957 4, 0xFFFF, sum = 0
2670 01:15:46.350383 5, 0xFFFF, sum = 0
2671 01:15:46.353647 6, 0xFFFF, sum = 0
2672 01:15:46.354068 7, 0xFFFF, sum = 0
2673 01:15:46.356482 8, 0xFFFF, sum = 0
2674 01:15:46.356906 9, 0xFFFF, sum = 0
2675 01:15:46.359640 10, 0xFFFF, sum = 0
2676 01:15:46.360092 11, 0xFFFF, sum = 0
2677 01:15:46.362946 12, 0x0, sum = 1
2678 01:15:46.363368 13, 0x0, sum = 2
2679 01:15:46.366377 14, 0x0, sum = 3
2680 01:15:46.366800 15, 0x0, sum = 4
2681 01:15:46.369527 best_step = 13
2682 01:15:46.369942
2683 01:15:46.370271 ==
2684 01:15:46.373174 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 01:15:46.376073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 01:15:46.376491 ==
2687 01:15:46.376825 RX Vref Scan: 1
2688 01:15:46.377137
2689 01:15:46.379792 Set Vref Range= 32 -> 127
2690 01:15:46.380367
2691 01:15:46.382828 RX Vref 32 -> 127, step: 1
2692 01:15:46.383249
2693 01:15:46.386433 RX Delay -21 -> 252, step: 4
2694 01:15:46.386851
2695 01:15:46.389343 Set Vref, RX VrefLevel [Byte0]: 32
2696 01:15:46.392844 [Byte1]: 32
2697 01:15:46.393261
2698 01:15:46.396143 Set Vref, RX VrefLevel [Byte0]: 33
2699 01:15:46.399396 [Byte1]: 33
2700 01:15:46.403182
2701 01:15:46.403595 Set Vref, RX VrefLevel [Byte0]: 34
2702 01:15:46.406118 [Byte1]: 34
2703 01:15:46.411039
2704 01:15:46.411458 Set Vref, RX VrefLevel [Byte0]: 35
2705 01:15:46.414207 [Byte1]: 35
2706 01:15:46.419101
2707 01:15:46.419518 Set Vref, RX VrefLevel [Byte0]: 36
2708 01:15:46.422178 [Byte1]: 36
2709 01:15:46.427066
2710 01:15:46.427627 Set Vref, RX VrefLevel [Byte0]: 37
2711 01:15:46.430304 [Byte1]: 37
2712 01:15:46.434969
2713 01:15:46.435387 Set Vref, RX VrefLevel [Byte0]: 38
2714 01:15:46.438198 [Byte1]: 38
2715 01:15:46.442458
2716 01:15:46.443080 Set Vref, RX VrefLevel [Byte0]: 39
2717 01:15:46.445986 [Byte1]: 39
2718 01:15:46.450911
2719 01:15:46.451362 Set Vref, RX VrefLevel [Byte0]: 40
2720 01:15:46.454059 [Byte1]: 40
2721 01:15:46.458614
2722 01:15:46.459032 Set Vref, RX VrefLevel [Byte0]: 41
2723 01:15:46.461781 [Byte1]: 41
2724 01:15:46.466587
2725 01:15:46.467001 Set Vref, RX VrefLevel [Byte0]: 42
2726 01:15:46.469527 [Byte1]: 42
2727 01:15:46.474690
2728 01:15:46.475113 Set Vref, RX VrefLevel [Byte0]: 43
2729 01:15:46.477733 [Byte1]: 43
2730 01:15:46.482638
2731 01:15:46.483053 Set Vref, RX VrefLevel [Byte0]: 44
2732 01:15:46.485590 [Byte1]: 44
2733 01:15:46.490444
2734 01:15:46.490859 Set Vref, RX VrefLevel [Byte0]: 45
2735 01:15:46.493628 [Byte1]: 45
2736 01:15:46.498342
2737 01:15:46.498761 Set Vref, RX VrefLevel [Byte0]: 46
2738 01:15:46.501249 [Byte1]: 46
2739 01:15:46.506167
2740 01:15:46.506710 Set Vref, RX VrefLevel [Byte0]: 47
2741 01:15:46.509528 [Byte1]: 47
2742 01:15:46.514305
2743 01:15:46.514787 Set Vref, RX VrefLevel [Byte0]: 48
2744 01:15:46.517525 [Byte1]: 48
2745 01:15:46.522158
2746 01:15:46.522597 Set Vref, RX VrefLevel [Byte0]: 49
2747 01:15:46.525480 [Byte1]: 49
2748 01:15:46.529582
2749 01:15:46.529998 Set Vref, RX VrefLevel [Byte0]: 50
2750 01:15:46.533024 [Byte1]: 50
2751 01:15:46.537268
2752 01:15:46.537349 Set Vref, RX VrefLevel [Byte0]: 51
2753 01:15:46.540826 [Byte1]: 51
2754 01:15:46.545416
2755 01:15:46.545498 Set Vref, RX VrefLevel [Byte0]: 52
2756 01:15:46.548882 [Byte1]: 52
2757 01:15:46.553124
2758 01:15:46.553206 Set Vref, RX VrefLevel [Byte0]: 53
2759 01:15:46.556736 [Byte1]: 53
2760 01:15:46.561161
2761 01:15:46.561242 Set Vref, RX VrefLevel [Byte0]: 54
2762 01:15:46.564388 [Byte1]: 54
2763 01:15:46.569116
2764 01:15:46.569203 Set Vref, RX VrefLevel [Byte0]: 55
2765 01:15:46.572892 [Byte1]: 55
2766 01:15:46.577037
2767 01:15:46.577138 Set Vref, RX VrefLevel [Byte0]: 56
2768 01:15:46.580636 [Byte1]: 56
2769 01:15:46.585520
2770 01:15:46.585939 Set Vref, RX VrefLevel [Byte0]: 57
2771 01:15:46.588733 [Byte1]: 57
2772 01:15:46.593343
2773 01:15:46.593759 Set Vref, RX VrefLevel [Byte0]: 58
2774 01:15:46.596733 [Byte1]: 58
2775 01:15:46.600955
2776 01:15:46.601371 Set Vref, RX VrefLevel [Byte0]: 59
2777 01:15:46.604292 [Byte1]: 59
2778 01:15:46.608521
2779 01:15:46.608602 Set Vref, RX VrefLevel [Byte0]: 60
2780 01:15:46.612068 [Byte1]: 60
2781 01:15:46.616930
2782 01:15:46.617040 Set Vref, RX VrefLevel [Byte0]: 61
2783 01:15:46.620069 [Byte1]: 61
2784 01:15:46.624803
2785 01:15:46.624884 Set Vref, RX VrefLevel [Byte0]: 62
2786 01:15:46.627917 [Byte1]: 62
2787 01:15:46.632839
2788 01:15:46.632920 Set Vref, RX VrefLevel [Byte0]: 63
2789 01:15:46.635862 [Byte1]: 63
2790 01:15:46.640790
2791 01:15:46.640871 Set Vref, RX VrefLevel [Byte0]: 64
2792 01:15:46.643837 [Byte1]: 64
2793 01:15:46.648693
2794 01:15:46.648780 Set Vref, RX VrefLevel [Byte0]: 65
2795 01:15:46.651685 [Byte1]: 65
2796 01:15:46.656560
2797 01:15:46.656641 Set Vref, RX VrefLevel [Byte0]: 66
2798 01:15:46.659650 [Byte1]: 66
2799 01:15:46.664360
2800 01:15:46.664441 Set Vref, RX VrefLevel [Byte0]: 67
2801 01:15:46.667773 [Byte1]: 67
2802 01:15:46.672158
2803 01:15:46.672239 Set Vref, RX VrefLevel [Byte0]: 68
2804 01:15:46.678614 [Byte1]: 68
2805 01:15:46.678695
2806 01:15:46.681731 Set Vref, RX VrefLevel [Byte0]: 69
2807 01:15:46.685354 [Byte1]: 69
2808 01:15:46.685436
2809 01:15:46.688600 Final RX Vref Byte 0 = 57 to rank0
2810 01:15:46.692171 Final RX Vref Byte 1 = 59 to rank0
2811 01:15:46.695703 Final RX Vref Byte 0 = 57 to rank1
2812 01:15:46.698868 Final RX Vref Byte 1 = 59 to rank1==
2813 01:15:46.702234 Dram Type= 6, Freq= 0, CH_0, rank 0
2814 01:15:46.705027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2815 01:15:46.708113 ==
2816 01:15:46.708280 DQS Delay:
2817 01:15:46.708382 DQS0 = 0, DQS1 = 0
2818 01:15:46.711862 DQM Delay:
2819 01:15:46.712074 DQM0 = 117, DQM1 = 105
2820 01:15:46.714762 DQ Delay:
2821 01:15:46.718676 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =112
2822 01:15:46.721323 DQ4 =120, DQ5 =112, DQ6 =126, DQ7 =122
2823 01:15:46.725258 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2824 01:15:46.728274 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2825 01:15:46.728543
2826 01:15:46.728706
2827 01:15:46.735201 [DQSOSCAuto] RK0, (LSB)MR18= 0x1fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
2828 01:15:46.738214 CH0 RK0: MR19=403, MR18=1FC
2829 01:15:46.745023 CH0_RK0: MR19=0x403, MR18=0x1FC, DQSOSC=409, MR23=63, INC=39, DEC=26
2830 01:15:46.745424
2831 01:15:46.748112 ----->DramcWriteLeveling(PI) begin...
2832 01:15:46.748507 ==
2833 01:15:46.751929 Dram Type= 6, Freq= 0, CH_0, rank 1
2834 01:15:46.755362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2835 01:15:46.755964 ==
2836 01:15:46.758534 Write leveling (Byte 0): 32 => 32
2837 01:15:46.761451 Write leveling (Byte 1): 25 => 25
2838 01:15:46.765060 DramcWriteLeveling(PI) end<-----
2839 01:15:46.765478
2840 01:15:46.765811 ==
2841 01:15:46.768152 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 01:15:46.775170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2843 01:15:46.775694 ==
2844 01:15:46.776093 [Gating] SW mode calibration
2845 01:15:46.784893 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2846 01:15:46.788246 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2847 01:15:46.791173 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2848 01:15:46.797706 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2849 01:15:46.801034 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 01:15:46.804378 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 01:15:46.811568 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 01:15:46.814411 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 01:15:46.817852 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2854 01:15:46.824805 0 15 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 1)
2855 01:15:46.827574 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
2856 01:15:46.831257 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 01:15:46.837878 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 01:15:46.841071 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 01:15:46.844326 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 01:15:46.850621 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 01:15:46.854373 1 0 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2862 01:15:46.857386 1 0 28 | B1->B0 | 2b2b 4646 | 0 0 | (1 1) (0 0)
2863 01:15:46.864158 1 1 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2864 01:15:46.867770 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 01:15:46.870780 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 01:15:46.877522 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 01:15:46.880747 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 01:15:46.884326 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 01:15:46.891087 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2870 01:15:46.894157 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2871 01:15:46.897431 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2872 01:15:46.904056 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 01:15:46.907241 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 01:15:46.910836 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 01:15:46.917564 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 01:15:46.920892 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 01:15:46.923760 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 01:15:46.929820 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 01:15:46.933568 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 01:15:46.936702 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 01:15:46.943600 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 01:15:46.946721 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 01:15:46.950080 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 01:15:46.956466 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 01:15:46.959496 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2886 01:15:46.963035 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2887 01:15:46.966582 Total UI for P1: 0, mck2ui 16
2888 01:15:46.969638 best dqsien dly found for B0: ( 1, 3, 24)
2889 01:15:46.976394 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2890 01:15:46.976476 Total UI for P1: 0, mck2ui 16
2891 01:15:46.979599 best dqsien dly found for B1: ( 1, 3, 28)
2892 01:15:46.986824 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2893 01:15:46.989654 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2894 01:15:46.989828
2895 01:15:46.992925 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2896 01:15:46.996550 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2897 01:15:46.999432 [Gating] SW calibration Done
2898 01:15:46.999569 ==
2899 01:15:47.002850 Dram Type= 6, Freq= 0, CH_0, rank 1
2900 01:15:47.005940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2901 01:15:47.006062 ==
2902 01:15:47.009378 RX Vref Scan: 0
2903 01:15:47.009512
2904 01:15:47.009620 RX Vref 0 -> 0, step: 1
2905 01:15:47.009719
2906 01:15:47.012764 RX Delay -40 -> 252, step: 8
2907 01:15:47.016248 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2908 01:15:47.022681 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2909 01:15:47.026081 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2910 01:15:47.029591 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2911 01:15:47.032835 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2912 01:15:47.036328 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2913 01:15:47.042837 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2914 01:15:47.046455 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2915 01:15:47.049451 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2916 01:15:47.052882 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2917 01:15:47.056383 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2918 01:15:47.062517 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2919 01:15:47.065993 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2920 01:15:47.069575 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2921 01:15:47.072825 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2922 01:15:47.076534 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2923 01:15:47.079587 ==
2924 01:15:47.080035 Dram Type= 6, Freq= 0, CH_0, rank 1
2925 01:15:47.086373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2926 01:15:47.086794 ==
2927 01:15:47.087126 DQS Delay:
2928 01:15:47.089478 DQS0 = 0, DQS1 = 0
2929 01:15:47.089895 DQM Delay:
2930 01:15:47.092467 DQM0 = 116, DQM1 = 109
2931 01:15:47.092884 DQ Delay:
2932 01:15:47.096230 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2933 01:15:47.099032 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =119
2934 01:15:47.102658 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
2935 01:15:47.105508 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2936 01:15:47.105589
2937 01:15:47.105654
2938 01:15:47.105713 ==
2939 01:15:47.108945 Dram Type= 6, Freq= 0, CH_0, rank 1
2940 01:15:47.115689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2941 01:15:47.115770 ==
2942 01:15:47.115834
2943 01:15:47.115920
2944 01:15:47.115995 TX Vref Scan disable
2945 01:15:47.118817 == TX Byte 0 ==
2946 01:15:47.122273 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2947 01:15:47.128717 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2948 01:15:47.128801 == TX Byte 1 ==
2949 01:15:47.132192 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2950 01:15:47.138632 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2951 01:15:47.138714 ==
2952 01:15:47.142246 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 01:15:47.145289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 01:15:47.145371 ==
2955 01:15:47.157275 TX Vref=22, minBit 14, minWin=25, winSum=420
2956 01:15:47.160862 TX Vref=24, minBit 0, minWin=26, winSum=423
2957 01:15:47.164104 TX Vref=26, minBit 10, minWin=26, winSum=434
2958 01:15:47.167131 TX Vref=28, minBit 8, minWin=26, winSum=433
2959 01:15:47.170939 TX Vref=30, minBit 10, minWin=25, winSum=431
2960 01:15:47.177625 TX Vref=32, minBit 8, minWin=26, winSum=431
2961 01:15:47.180857 [TxChooseVref] Worse bit 10, Min win 26, Win sum 434, Final Vref 26
2962 01:15:47.180980
2963 01:15:47.183991 Final TX Range 1 Vref 26
2964 01:15:47.184125
2965 01:15:47.184232 ==
2966 01:15:47.187288 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 01:15:47.190788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 01:15:47.193766 ==
2969 01:15:47.193938
2970 01:15:47.194074
2971 01:15:47.194203 TX Vref Scan disable
2972 01:15:47.197427 == TX Byte 0 ==
2973 01:15:47.201078 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2974 01:15:47.207416 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2975 01:15:47.207713 == TX Byte 1 ==
2976 01:15:47.210684 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2977 01:15:47.217693 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2978 01:15:47.218109
2979 01:15:47.218442 [DATLAT]
2980 01:15:47.218757 Freq=1200, CH0 RK1
2981 01:15:47.219056
2982 01:15:47.221359 DATLAT Default: 0xd
2983 01:15:47.221776 0, 0xFFFF, sum = 0
2984 01:15:47.224319 1, 0xFFFF, sum = 0
2985 01:15:47.227378 2, 0xFFFF, sum = 0
2986 01:15:47.227834 3, 0xFFFF, sum = 0
2987 01:15:47.230407 4, 0xFFFF, sum = 0
2988 01:15:47.230490 5, 0xFFFF, sum = 0
2989 01:15:47.233784 6, 0xFFFF, sum = 0
2990 01:15:47.233867 7, 0xFFFF, sum = 0
2991 01:15:47.237023 8, 0xFFFF, sum = 0
2992 01:15:47.237106 9, 0xFFFF, sum = 0
2993 01:15:47.240493 10, 0xFFFF, sum = 0
2994 01:15:47.240576 11, 0xFFFF, sum = 0
2995 01:15:47.243772 12, 0x0, sum = 1
2996 01:15:47.243903 13, 0x0, sum = 2
2997 01:15:47.247376 14, 0x0, sum = 3
2998 01:15:47.247458 15, 0x0, sum = 4
2999 01:15:47.250369 best_step = 13
3000 01:15:47.250450
3001 01:15:47.250514 ==
3002 01:15:47.254083 Dram Type= 6, Freq= 0, CH_0, rank 1
3003 01:15:47.257042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3004 01:15:47.257124 ==
3005 01:15:47.260140 RX Vref Scan: 0
3006 01:15:47.260221
3007 01:15:47.260286 RX Vref 0 -> 0, step: 1
3008 01:15:47.260346
3009 01:15:47.263894 RX Delay -21 -> 252, step: 4
3010 01:15:47.270239 iDelay=195, Bit 0, Center 112 (47 ~ 178) 132
3011 01:15:47.273736 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3012 01:15:47.276734 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
3013 01:15:47.280089 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3014 01:15:47.283677 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3015 01:15:47.290080 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3016 01:15:47.293389 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3017 01:15:47.296677 iDelay=195, Bit 7, Center 120 (55 ~ 186) 132
3018 01:15:47.300339 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3019 01:15:47.303600 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3020 01:15:47.309911 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3021 01:15:47.313569 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3022 01:15:47.316492 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3023 01:15:47.320183 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3024 01:15:47.323471 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3025 01:15:47.330031 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3026 01:15:47.330446 ==
3027 01:15:47.333643 Dram Type= 6, Freq= 0, CH_0, rank 1
3028 01:15:47.336505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3029 01:15:47.336922 ==
3030 01:15:47.337254 DQS Delay:
3031 01:15:47.340039 DQS0 = 0, DQS1 = 0
3032 01:15:47.340453 DQM Delay:
3033 01:15:47.343457 DQM0 = 115, DQM1 = 106
3034 01:15:47.343926 DQ Delay:
3035 01:15:47.346506 DQ0 =112, DQ1 =116, DQ2 =112, DQ3 =112
3036 01:15:47.350199 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =120
3037 01:15:47.353532 DQ8 =96, DQ9 =92, DQ10 =108, DQ11 =100
3038 01:15:47.356438 DQ12 =112, DQ13 =112, DQ14 =120, DQ15 =112
3039 01:15:47.356856
3040 01:15:47.357191
3041 01:15:47.366703 [DQSOSCAuto] RK1, (LSB)MR18= 0xfaf8, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 412 ps
3042 01:15:47.369588 CH0 RK1: MR19=303, MR18=FAF8
3043 01:15:47.376306 CH0_RK1: MR19=0x303, MR18=0xFAF8, DQSOSC=412, MR23=63, INC=38, DEC=25
3044 01:15:47.379945 [RxdqsGatingPostProcess] freq 1200
3045 01:15:47.383346 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3046 01:15:47.386198 best DQS0 dly(2T, 0.5T) = (0, 11)
3047 01:15:47.389642 best DQS1 dly(2T, 0.5T) = (0, 12)
3048 01:15:47.393133 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3049 01:15:47.396513 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3050 01:15:47.399743 best DQS0 dly(2T, 0.5T) = (0, 11)
3051 01:15:47.403181 best DQS1 dly(2T, 0.5T) = (0, 11)
3052 01:15:47.406252 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3053 01:15:47.409763 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3054 01:15:47.413073 Pre-setting of DQS Precalculation
3055 01:15:47.416577 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3056 01:15:47.416998 ==
3057 01:15:47.420093 Dram Type= 6, Freq= 0, CH_1, rank 0
3058 01:15:47.422809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3059 01:15:47.426237 ==
3060 01:15:47.429961 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3061 01:15:47.435906 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3062 01:15:47.444125 [CA 0] Center 38 (8~68) winsize 61
3063 01:15:47.447556 [CA 1] Center 37 (7~68) winsize 62
3064 01:15:47.450873 [CA 2] Center 35 (5~65) winsize 61
3065 01:15:47.454534 [CA 3] Center 34 (4~64) winsize 61
3066 01:15:47.457508 [CA 4] Center 35 (5~65) winsize 61
3067 01:15:47.460950 [CA 5] Center 33 (4~63) winsize 60
3068 01:15:47.461463
3069 01:15:47.464630 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3070 01:15:47.464927
3071 01:15:47.467332 [CATrainingPosCal] consider 1 rank data
3072 01:15:47.470489 u2DelayCellTimex100 = 270/100 ps
3073 01:15:47.474099 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3074 01:15:47.480198 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3075 01:15:47.483729 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3076 01:15:47.487098 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3077 01:15:47.490148 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3078 01:15:47.493650 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3079 01:15:47.493730
3080 01:15:47.496573 CA PerBit enable=1, Macro0, CA PI delay=33
3081 01:15:47.496654
3082 01:15:47.500144 [CBTSetCACLKResult] CA Dly = 33
3083 01:15:47.503546 CS Dly: 5 (0~36)
3084 01:15:47.503627 ==
3085 01:15:47.506483 Dram Type= 6, Freq= 0, CH_1, rank 1
3086 01:15:47.509889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3087 01:15:47.509970 ==
3088 01:15:47.516511 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3089 01:15:47.519695 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3090 01:15:47.529793 [CA 0] Center 38 (8~68) winsize 61
3091 01:15:47.532826 [CA 1] Center 38 (8~69) winsize 62
3092 01:15:47.536357 [CA 2] Center 34 (4~65) winsize 62
3093 01:15:47.539765 [CA 3] Center 33 (3~64) winsize 62
3094 01:15:47.542559 [CA 4] Center 34 (4~64) winsize 61
3095 01:15:47.546312 [CA 5] Center 33 (3~63) winsize 61
3096 01:15:47.546395
3097 01:15:47.549943 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3098 01:15:47.550025
3099 01:15:47.552528 [CATrainingPosCal] consider 2 rank data
3100 01:15:47.556305 u2DelayCellTimex100 = 270/100 ps
3101 01:15:47.559425 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3102 01:15:47.565828 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3103 01:15:47.569229 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3104 01:15:47.572364 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3105 01:15:47.575450 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3106 01:15:47.579169 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3107 01:15:47.579292
3108 01:15:47.582209 CA PerBit enable=1, Macro0, CA PI delay=33
3109 01:15:47.582343
3110 01:15:47.586019 [CBTSetCACLKResult] CA Dly = 33
3111 01:15:47.588883 CS Dly: 6 (0~39)
3112 01:15:47.589035
3113 01:15:47.592303 ----->DramcWriteLeveling(PI) begin...
3114 01:15:47.592503 ==
3115 01:15:47.595380 Dram Type= 6, Freq= 0, CH_1, rank 0
3116 01:15:47.599378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3117 01:15:47.599798 ==
3118 01:15:47.602455 Write leveling (Byte 0): 24 => 24
3119 01:15:47.605463 Write leveling (Byte 1): 26 => 26
3120 01:15:47.608896 DramcWriteLeveling(PI) end<-----
3121 01:15:47.609338
3122 01:15:47.609672 ==
3123 01:15:47.612212 Dram Type= 6, Freq= 0, CH_1, rank 0
3124 01:15:47.615744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3125 01:15:47.616268 ==
3126 01:15:47.619451 [Gating] SW mode calibration
3127 01:15:47.626119 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3128 01:15:47.632753 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3129 01:15:47.635639 0 15 0 | B1->B0 | 3030 3434 | 1 0 | (1 1) (0 0)
3130 01:15:47.639116 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 01:15:47.645880 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 01:15:47.649341 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 01:15:47.652708 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 01:15:47.658958 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 01:15:47.662083 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
3136 01:15:47.665580 0 15 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (1 0)
3137 01:15:47.672050 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 01:15:47.675624 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 01:15:47.678640 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 01:15:47.685447 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 01:15:47.688496 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 01:15:47.692233 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 01:15:47.698697 1 0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3144 01:15:47.702111 1 0 28 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
3145 01:15:47.705091 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 01:15:47.711712 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 01:15:47.715177 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 01:15:47.718490 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 01:15:47.724737 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 01:15:47.728161 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 01:15:47.731835 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3152 01:15:47.738526 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3153 01:15:47.741616 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3154 01:15:47.744608 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 01:15:47.751523 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 01:15:47.754575 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 01:15:47.758097 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 01:15:47.764765 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 01:15:47.767997 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 01:15:47.771439 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 01:15:47.778034 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 01:15:47.781493 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 01:15:47.784239 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 01:15:47.790919 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 01:15:47.794784 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 01:15:47.797640 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 01:15:47.804201 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3168 01:15:47.807687 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3169 01:15:47.810544 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3170 01:15:47.814221 Total UI for P1: 0, mck2ui 16
3171 01:15:47.817270 best dqsien dly found for B1: ( 1, 3, 28)
3172 01:15:47.824137 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3173 01:15:47.824559 Total UI for P1: 0, mck2ui 16
3174 01:15:47.827528 best dqsien dly found for B0: ( 1, 3, 28)
3175 01:15:47.834081 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3176 01:15:47.837144 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3177 01:15:47.837562
3178 01:15:47.840395 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3179 01:15:47.843915 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3180 01:15:47.847532 [Gating] SW calibration Done
3181 01:15:47.847982 ==
3182 01:15:47.850497 Dram Type= 6, Freq= 0, CH_1, rank 0
3183 01:15:47.853980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 01:15:47.854406 ==
3185 01:15:47.856916 RX Vref Scan: 0
3186 01:15:47.857332
3187 01:15:47.857665 RX Vref 0 -> 0, step: 1
3188 01:15:47.857975
3189 01:15:47.860688 RX Delay -40 -> 252, step: 8
3190 01:15:47.863826 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3191 01:15:47.870578 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3192 01:15:47.874093 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3193 01:15:47.876923 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3194 01:15:47.880988 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3195 01:15:47.883829 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3196 01:15:47.890351 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3197 01:15:47.894247 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3198 01:15:47.897024 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3199 01:15:47.900481 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3200 01:15:47.903464 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3201 01:15:47.910523 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3202 01:15:47.913461 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3203 01:15:47.916673 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3204 01:15:47.920180 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3205 01:15:47.923268 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3206 01:15:47.926769 ==
3207 01:15:47.930084 Dram Type= 6, Freq= 0, CH_1, rank 0
3208 01:15:47.933421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3209 01:15:47.933841 ==
3210 01:15:47.934206 DQS Delay:
3211 01:15:47.936704 DQS0 = 0, DQS1 = 0
3212 01:15:47.937144 DQM Delay:
3213 01:15:47.939961 DQM0 = 115, DQM1 = 112
3214 01:15:47.940381 DQ Delay:
3215 01:15:47.943027 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3216 01:15:47.946823 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3217 01:15:47.949851 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3218 01:15:47.953666 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3219 01:15:47.954270
3220 01:15:47.954616
3221 01:15:47.954926 ==
3222 01:15:47.956427 Dram Type= 6, Freq= 0, CH_1, rank 0
3223 01:15:47.962923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3224 01:15:47.963366 ==
3225 01:15:47.963724
3226 01:15:47.964194
3227 01:15:47.964573 TX Vref Scan disable
3228 01:15:47.966542 == TX Byte 0 ==
3229 01:15:47.969646 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3230 01:15:47.976445 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3231 01:15:47.976915 == TX Byte 1 ==
3232 01:15:47.979493 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3233 01:15:47.986267 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3234 01:15:47.986835 ==
3235 01:15:47.989952 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 01:15:47.993111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 01:15:47.993567 ==
3238 01:15:48.004128 TX Vref=22, minBit 1, minWin=25, winSum=408
3239 01:15:48.007243 TX Vref=24, minBit 9, minWin=23, winSum=412
3240 01:15:48.010648 TX Vref=26, minBit 2, minWin=25, winSum=421
3241 01:15:48.014364 TX Vref=28, minBit 9, minWin=25, winSum=427
3242 01:15:48.017343 TX Vref=30, minBit 2, minWin=26, winSum=429
3243 01:15:48.024314 TX Vref=32, minBit 9, minWin=25, winSum=426
3244 01:15:48.027467 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 30
3245 01:15:48.028146
3246 01:15:48.031125 Final TX Range 1 Vref 30
3247 01:15:48.031746
3248 01:15:48.032331 ==
3249 01:15:48.033935 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 01:15:48.037846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 01:15:48.038516 ==
3252 01:15:48.040540
3253 01:15:48.040641
3254 01:15:48.040749 TX Vref Scan disable
3255 01:15:48.043813 == TX Byte 0 ==
3256 01:15:48.046884 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3257 01:15:48.050260 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3258 01:15:48.053983 == TX Byte 1 ==
3259 01:15:48.057118 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3260 01:15:48.060659 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3261 01:15:48.063699
3262 01:15:48.063800 [DATLAT]
3263 01:15:48.063916 Freq=1200, CH1 RK0
3264 01:15:48.063994
3265 01:15:48.067371 DATLAT Default: 0xd
3266 01:15:48.067453 0, 0xFFFF, sum = 0
3267 01:15:48.070286 1, 0xFFFF, sum = 0
3268 01:15:48.070357 2, 0xFFFF, sum = 0
3269 01:15:48.073954 3, 0xFFFF, sum = 0
3270 01:15:48.077064 4, 0xFFFF, sum = 0
3271 01:15:48.077165 5, 0xFFFF, sum = 0
3272 01:15:48.080080 6, 0xFFFF, sum = 0
3273 01:15:48.080181 7, 0xFFFF, sum = 0
3274 01:15:48.083757 8, 0xFFFF, sum = 0
3275 01:15:48.083857 9, 0xFFFF, sum = 0
3276 01:15:48.086923 10, 0xFFFF, sum = 0
3277 01:15:48.087000 11, 0xFFFF, sum = 0
3278 01:15:48.090010 12, 0x0, sum = 1
3279 01:15:48.090110 13, 0x0, sum = 2
3280 01:15:48.093615 14, 0x0, sum = 3
3281 01:15:48.093690 15, 0x0, sum = 4
3282 01:15:48.096737 best_step = 13
3283 01:15:48.096814
3284 01:15:48.096877 ==
3285 01:15:48.100357 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 01:15:48.103523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3287 01:15:48.103626 ==
3288 01:15:48.103717 RX Vref Scan: 1
3289 01:15:48.103840
3290 01:15:48.106725 Set Vref Range= 32 -> 127
3291 01:15:48.106842
3292 01:15:48.110183 RX Vref 32 -> 127, step: 1
3293 01:15:48.110260
3294 01:15:48.113653 RX Delay -13 -> 252, step: 4
3295 01:15:48.113728
3296 01:15:48.116750 Set Vref, RX VrefLevel [Byte0]: 32
3297 01:15:48.119732 [Byte1]: 32
3298 01:15:48.119851
3299 01:15:48.123237 Set Vref, RX VrefLevel [Byte0]: 33
3300 01:15:48.126277 [Byte1]: 33
3301 01:15:48.129950
3302 01:15:48.130052 Set Vref, RX VrefLevel [Byte0]: 34
3303 01:15:48.133741 [Byte1]: 34
3304 01:15:48.137715
3305 01:15:48.137815 Set Vref, RX VrefLevel [Byte0]: 35
3306 01:15:48.141268 [Byte1]: 35
3307 01:15:48.146023
3308 01:15:48.146132 Set Vref, RX VrefLevel [Byte0]: 36
3309 01:15:48.149342 [Byte1]: 36
3310 01:15:48.153740
3311 01:15:48.153847 Set Vref, RX VrefLevel [Byte0]: 37
3312 01:15:48.156930 [Byte1]: 37
3313 01:15:48.162102
3314 01:15:48.162204 Set Vref, RX VrefLevel [Byte0]: 38
3315 01:15:48.165078 [Byte1]: 38
3316 01:15:48.169663
3317 01:15:48.169766 Set Vref, RX VrefLevel [Byte0]: 39
3318 01:15:48.173116 [Byte1]: 39
3319 01:15:48.177415
3320 01:15:48.177519 Set Vref, RX VrefLevel [Byte0]: 40
3321 01:15:48.180527 [Byte1]: 40
3322 01:15:48.185364
3323 01:15:48.185471 Set Vref, RX VrefLevel [Byte0]: 41
3324 01:15:48.188494 [Byte1]: 41
3325 01:15:48.193200
3326 01:15:48.193300 Set Vref, RX VrefLevel [Byte0]: 42
3327 01:15:48.196377 [Byte1]: 42
3328 01:15:48.201147
3329 01:15:48.201248 Set Vref, RX VrefLevel [Byte0]: 43
3330 01:15:48.204110 [Byte1]: 43
3331 01:15:48.209337
3332 01:15:48.209440 Set Vref, RX VrefLevel [Byte0]: 44
3333 01:15:48.212194 [Byte1]: 44
3334 01:15:48.217127
3335 01:15:48.217226 Set Vref, RX VrefLevel [Byte0]: 45
3336 01:15:48.220051 [Byte1]: 45
3337 01:15:48.224477
3338 01:15:48.224571 Set Vref, RX VrefLevel [Byte0]: 46
3339 01:15:48.227854 [Byte1]: 46
3340 01:15:48.232711
3341 01:15:48.232785 Set Vref, RX VrefLevel [Byte0]: 47
3342 01:15:48.235795 [Byte1]: 47
3343 01:15:48.240225
3344 01:15:48.240325 Set Vref, RX VrefLevel [Byte0]: 48
3345 01:15:48.243752 [Byte1]: 48
3346 01:15:48.248688
3347 01:15:48.248793 Set Vref, RX VrefLevel [Byte0]: 49
3348 01:15:48.251568 [Byte1]: 49
3349 01:15:48.256364
3350 01:15:48.256466 Set Vref, RX VrefLevel [Byte0]: 50
3351 01:15:48.259687 [Byte1]: 50
3352 01:15:48.263838
3353 01:15:48.263984 Set Vref, RX VrefLevel [Byte0]: 51
3354 01:15:48.267557 [Byte1]: 51
3355 01:15:48.271723
3356 01:15:48.271827 Set Vref, RX VrefLevel [Byte0]: 52
3357 01:15:48.275216 [Byte1]: 52
3358 01:15:48.280011
3359 01:15:48.280112 Set Vref, RX VrefLevel [Byte0]: 53
3360 01:15:48.283292 [Byte1]: 53
3361 01:15:48.288188
3362 01:15:48.288263 Set Vref, RX VrefLevel [Byte0]: 54
3363 01:15:48.290791 [Byte1]: 54
3364 01:15:48.295708
3365 01:15:48.295813 Set Vref, RX VrefLevel [Byte0]: 55
3366 01:15:48.298825 [Byte1]: 55
3367 01:15:48.303577
3368 01:15:48.303683 Set Vref, RX VrefLevel [Byte0]: 56
3369 01:15:48.307106 [Byte1]: 56
3370 01:15:48.311072
3371 01:15:48.311183 Set Vref, RX VrefLevel [Byte0]: 57
3372 01:15:48.314814 [Byte1]: 57
3373 01:15:48.318934
3374 01:15:48.319012 Set Vref, RX VrefLevel [Byte0]: 58
3375 01:15:48.322608 [Byte1]: 58
3376 01:15:48.327017
3377 01:15:48.327095 Set Vref, RX VrefLevel [Byte0]: 59
3378 01:15:48.330618 [Byte1]: 59
3379 01:15:48.334662
3380 01:15:48.334762 Set Vref, RX VrefLevel [Byte0]: 60
3381 01:15:48.338369 [Byte1]: 60
3382 01:15:48.342554
3383 01:15:48.342654 Set Vref, RX VrefLevel [Byte0]: 61
3384 01:15:48.346473 [Byte1]: 61
3385 01:15:48.350617
3386 01:15:48.350723 Set Vref, RX VrefLevel [Byte0]: 62
3387 01:15:48.354206 [Byte1]: 62
3388 01:15:48.358520
3389 01:15:48.358626 Set Vref, RX VrefLevel [Byte0]: 63
3390 01:15:48.362196 [Byte1]: 63
3391 01:15:48.366681
3392 01:15:48.366782 Set Vref, RX VrefLevel [Byte0]: 64
3393 01:15:48.369618 [Byte1]: 64
3394 01:15:48.374672
3395 01:15:48.374771 Final RX Vref Byte 0 = 50 to rank0
3396 01:15:48.377565 Final RX Vref Byte 1 = 54 to rank0
3397 01:15:48.381184 Final RX Vref Byte 0 = 50 to rank1
3398 01:15:48.384297 Final RX Vref Byte 1 = 54 to rank1==
3399 01:15:48.387321 Dram Type= 6, Freq= 0, CH_1, rank 0
3400 01:15:48.394562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3401 01:15:48.394668 ==
3402 01:15:48.394760 DQS Delay:
3403 01:15:48.394852 DQS0 = 0, DQS1 = 0
3404 01:15:48.397830 DQM Delay:
3405 01:15:48.397930 DQM0 = 114, DQM1 = 113
3406 01:15:48.400897 DQ Delay:
3407 01:15:48.404344 DQ0 =120, DQ1 =108, DQ2 =106, DQ3 =114
3408 01:15:48.407134 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3409 01:15:48.410467 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3410 01:15:48.413751 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =122
3411 01:15:48.413859
3412 01:15:48.413951
3413 01:15:48.424123 [DQSOSCAuto] RK0, (LSB)MR18= 0xf400, (MSB)MR19= 0x304, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3414 01:15:48.424225 CH1 RK0: MR19=304, MR18=F400
3415 01:15:48.430195 CH1_RK0: MR19=0x304, MR18=0xF400, DQSOSC=410, MR23=63, INC=39, DEC=26
3416 01:15:48.430294
3417 01:15:48.434040 ----->DramcWriteLeveling(PI) begin...
3418 01:15:48.434137 ==
3419 01:15:48.437159 Dram Type= 6, Freq= 0, CH_1, rank 1
3420 01:15:48.443484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3421 01:15:48.443581 ==
3422 01:15:48.447046 Write leveling (Byte 0): 24 => 24
3423 01:15:48.450175 Write leveling (Byte 1): 29 => 29
3424 01:15:48.450258 DramcWriteLeveling(PI) end<-----
3425 01:15:48.453672
3426 01:15:48.453754 ==
3427 01:15:48.457321 Dram Type= 6, Freq= 0, CH_1, rank 1
3428 01:15:48.460361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3429 01:15:48.460443 ==
3430 01:15:48.463453 [Gating] SW mode calibration
3431 01:15:48.470033 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3432 01:15:48.473458 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3433 01:15:48.480172 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3434 01:15:48.483091 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 01:15:48.486570 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 01:15:48.493312 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 01:15:48.496358 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 01:15:48.500072 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3439 01:15:48.506587 0 15 24 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
3440 01:15:48.509830 0 15 28 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
3441 01:15:48.513123 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3442 01:15:48.519715 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 01:15:48.523384 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 01:15:48.526727 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 01:15:48.532663 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 01:15:48.536190 1 0 20 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
3447 01:15:48.539483 1 0 24 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
3448 01:15:48.546017 1 0 28 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
3449 01:15:48.549575 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3450 01:15:48.552952 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 01:15:48.559248 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 01:15:48.562672 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 01:15:48.565951 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 01:15:48.572492 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 01:15:48.575433 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3456 01:15:48.578798 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 01:15:48.585645 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 01:15:48.589080 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 01:15:48.592026 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 01:15:48.598926 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 01:15:48.602059 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 01:15:48.605117 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 01:15:48.611820 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 01:15:48.614830 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 01:15:48.618483 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 01:15:48.624733 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 01:15:48.628454 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 01:15:48.634834 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 01:15:48.638083 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 01:15:48.641601 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 01:15:48.647682 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 01:15:48.651178 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3473 01:15:48.654226 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 01:15:48.657962 Total UI for P1: 0, mck2ui 16
3475 01:15:48.661488 best dqsien dly found for B0: ( 1, 3, 28)
3476 01:15:48.664330 Total UI for P1: 0, mck2ui 16
3477 01:15:48.668043 best dqsien dly found for B1: ( 1, 3, 28)
3478 01:15:48.671242 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3479 01:15:48.674447 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3480 01:15:48.674526
3481 01:15:48.677689 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3482 01:15:48.684243 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3483 01:15:48.684325 [Gating] SW calibration Done
3484 01:15:48.684390 ==
3485 01:15:48.687595 Dram Type= 6, Freq= 0, CH_1, rank 1
3486 01:15:48.694016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3487 01:15:48.694133 ==
3488 01:15:48.694231 RX Vref Scan: 0
3489 01:15:48.694323
3490 01:15:48.697557 RX Vref 0 -> 0, step: 1
3491 01:15:48.697658
3492 01:15:48.700745 RX Delay -40 -> 252, step: 8
3493 01:15:48.703760 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3494 01:15:48.707410 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3495 01:15:48.710576 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3496 01:15:48.717156 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3497 01:15:48.720175 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3498 01:15:48.723957 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3499 01:15:48.726959 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3500 01:15:48.733557 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3501 01:15:48.736704 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3502 01:15:48.740124 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3503 01:15:48.743297 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3504 01:15:48.746383 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3505 01:15:48.753178 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3506 01:15:48.756450 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3507 01:15:48.760082 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3508 01:15:48.763018 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3509 01:15:48.763090 ==
3510 01:15:48.766541 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 01:15:48.772829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 01:15:48.772936 ==
3513 01:15:48.773041 DQS Delay:
3514 01:15:48.776477 DQS0 = 0, DQS1 = 0
3515 01:15:48.776577 DQM Delay:
3516 01:15:48.776680 DQM0 = 115, DQM1 = 112
3517 01:15:48.779799 DQ Delay:
3518 01:15:48.782814 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3519 01:15:48.785927 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3520 01:15:48.789179 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3521 01:15:48.792551 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3522 01:15:48.792655
3523 01:15:48.792746
3524 01:15:48.792836 ==
3525 01:15:48.796094 Dram Type= 6, Freq= 0, CH_1, rank 1
3526 01:15:48.802639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3527 01:15:48.802742 ==
3528 01:15:48.802853
3529 01:15:48.802954
3530 01:15:48.803015 TX Vref Scan disable
3531 01:15:48.805984 == TX Byte 0 ==
3532 01:15:48.809071 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3533 01:15:48.815606 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3534 01:15:48.815705 == TX Byte 1 ==
3535 01:15:48.818786 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3536 01:15:48.825356 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3537 01:15:48.825457 ==
3538 01:15:48.828432 Dram Type= 6, Freq= 0, CH_1, rank 1
3539 01:15:48.832058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3540 01:15:48.832132 ==
3541 01:15:48.843786 TX Vref=22, minBit 3, minWin=25, winSum=419
3542 01:15:48.847269 TX Vref=24, minBit 9, minWin=25, winSum=428
3543 01:15:48.850707 TX Vref=26, minBit 1, minWin=26, winSum=432
3544 01:15:48.853608 TX Vref=28, minBit 1, minWin=26, winSum=432
3545 01:15:48.857364 TX Vref=30, minBit 1, minWin=26, winSum=434
3546 01:15:48.863472 TX Vref=32, minBit 9, minWin=25, winSum=434
3547 01:15:48.866852 [TxChooseVref] Worse bit 1, Min win 26, Win sum 434, Final Vref 30
3548 01:15:48.866953
3549 01:15:48.870220 Final TX Range 1 Vref 30
3550 01:15:48.870323
3551 01:15:48.870418 ==
3552 01:15:48.873227 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 01:15:48.877123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 01:15:48.879800 ==
3555 01:15:48.879934
3556 01:15:48.879999
3557 01:15:48.880068 TX Vref Scan disable
3558 01:15:48.883409 == TX Byte 0 ==
3559 01:15:48.886559 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3560 01:15:48.893129 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3561 01:15:48.893204 == TX Byte 1 ==
3562 01:15:48.896705 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3563 01:15:48.903214 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3564 01:15:48.903321
3565 01:15:48.903417 [DATLAT]
3566 01:15:48.903507 Freq=1200, CH1 RK1
3567 01:15:48.903601
3568 01:15:48.906562 DATLAT Default: 0xd
3569 01:15:48.909694 0, 0xFFFF, sum = 0
3570 01:15:48.909796 1, 0xFFFF, sum = 0
3571 01:15:48.913536 2, 0xFFFF, sum = 0
3572 01:15:48.913640 3, 0xFFFF, sum = 0
3573 01:15:48.916673 4, 0xFFFF, sum = 0
3574 01:15:48.916776 5, 0xFFFF, sum = 0
3575 01:15:48.919943 6, 0xFFFF, sum = 0
3576 01:15:48.920053 7, 0xFFFF, sum = 0
3577 01:15:48.923109 8, 0xFFFF, sum = 0
3578 01:15:48.923190 9, 0xFFFF, sum = 0
3579 01:15:48.926720 10, 0xFFFF, sum = 0
3580 01:15:48.926802 11, 0xFFFF, sum = 0
3581 01:15:48.929839 12, 0x0, sum = 1
3582 01:15:48.929921 13, 0x0, sum = 2
3583 01:15:48.932826 14, 0x0, sum = 3
3584 01:15:48.932907 15, 0x0, sum = 4
3585 01:15:48.936467 best_step = 13
3586 01:15:48.936548
3587 01:15:48.936611 ==
3588 01:15:48.939601 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 01:15:48.943313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 01:15:48.943394 ==
3591 01:15:48.943458 RX Vref Scan: 0
3592 01:15:48.946423
3593 01:15:48.946502 RX Vref 0 -> 0, step: 1
3594 01:15:48.946567
3595 01:15:48.949492 RX Delay -13 -> 252, step: 4
3596 01:15:48.956025 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3597 01:15:48.959237 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3598 01:15:48.962705 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3599 01:15:48.965807 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3600 01:15:48.969445 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3601 01:15:48.976056 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3602 01:15:48.979321 iDelay=195, Bit 6, Center 120 (51 ~ 190) 140
3603 01:15:48.982588 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3604 01:15:48.986020 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3605 01:15:48.988844 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3606 01:15:48.995458 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3607 01:15:48.999232 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3608 01:15:49.001863 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3609 01:15:49.005593 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3610 01:15:49.012391 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3611 01:15:49.015368 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3612 01:15:49.015449 ==
3613 01:15:49.018748 Dram Type= 6, Freq= 0, CH_1, rank 1
3614 01:15:49.021770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3615 01:15:49.021849 ==
3616 01:15:49.025234 DQS Delay:
3617 01:15:49.025316 DQS0 = 0, DQS1 = 0
3618 01:15:49.025380 DQM Delay:
3619 01:15:49.028605 DQM0 = 114, DQM1 = 113
3620 01:15:49.028685 DQ Delay:
3621 01:15:49.031774 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3622 01:15:49.034845 DQ4 =112, DQ5 =122, DQ6 =120, DQ7 =112
3623 01:15:49.041632 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3624 01:15:49.044605 DQ12 =122, DQ13 =118, DQ14 =118, DQ15 =122
3625 01:15:49.044687
3626 01:15:49.044789
3627 01:15:49.051402 [DQSOSCAuto] RK1, (LSB)MR18= 0xf709, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3628 01:15:49.054445 CH1 RK1: MR19=304, MR18=F709
3629 01:15:49.061206 CH1_RK1: MR19=0x304, MR18=0xF709, DQSOSC=406, MR23=63, INC=39, DEC=26
3630 01:15:49.064586 [RxdqsGatingPostProcess] freq 1200
3631 01:15:49.070839 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3632 01:15:49.070946 best DQS0 dly(2T, 0.5T) = (0, 11)
3633 01:15:49.074420 best DQS1 dly(2T, 0.5T) = (0, 11)
3634 01:15:49.077639 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3635 01:15:49.081288 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3636 01:15:49.084166 best DQS0 dly(2T, 0.5T) = (0, 11)
3637 01:15:49.087457 best DQS1 dly(2T, 0.5T) = (0, 11)
3638 01:15:49.090649 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3639 01:15:49.094034 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3640 01:15:49.097359 Pre-setting of DQS Precalculation
3641 01:15:49.104372 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3642 01:15:49.110367 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3643 01:15:49.117349 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3644 01:15:49.117432
3645 01:15:49.117500
3646 01:15:49.121005 [Calibration Summary] 2400 Mbps
3647 01:15:49.121158 CH 0, Rank 0
3648 01:15:49.123930 SW Impedance : PASS
3649 01:15:49.127393 DUTY Scan : NO K
3650 01:15:49.127529 ZQ Calibration : PASS
3651 01:15:49.131050 Jitter Meter : NO K
3652 01:15:49.133917 CBT Training : PASS
3653 01:15:49.134102 Write leveling : PASS
3654 01:15:49.137074 RX DQS gating : PASS
3655 01:15:49.140334 RX DQ/DQS(RDDQC) : PASS
3656 01:15:49.140520 TX DQ/DQS : PASS
3657 01:15:49.143465 RX DATLAT : PASS
3658 01:15:49.147153 RX DQ/DQS(Engine): PASS
3659 01:15:49.147378 TX OE : NO K
3660 01:15:49.150144 All Pass.
3661 01:15:49.150364
3662 01:15:49.150546 CH 0, Rank 1
3663 01:15:49.154040 SW Impedance : PASS
3664 01:15:49.154463 DUTY Scan : NO K
3665 01:15:49.157047 ZQ Calibration : PASS
3666 01:15:49.160625 Jitter Meter : NO K
3667 01:15:49.161043 CBT Training : PASS
3668 01:15:49.163622 Write leveling : PASS
3669 01:15:49.164164 RX DQS gating : PASS
3670 01:15:49.167286 RX DQ/DQS(RDDQC) : PASS
3671 01:15:49.170465 TX DQ/DQS : PASS
3672 01:15:49.170940 RX DATLAT : PASS
3673 01:15:49.173757 RX DQ/DQS(Engine): PASS
3674 01:15:49.177215 TX OE : NO K
3675 01:15:49.177631 All Pass.
3676 01:15:49.178154
3677 01:15:49.178495 CH 1, Rank 0
3678 01:15:49.179809 SW Impedance : PASS
3679 01:15:49.183696 DUTY Scan : NO K
3680 01:15:49.184207 ZQ Calibration : PASS
3681 01:15:49.186859 Jitter Meter : NO K
3682 01:15:49.189732 CBT Training : PASS
3683 01:15:49.190164 Write leveling : PASS
3684 01:15:49.193581 RX DQS gating : PASS
3685 01:15:49.196581 RX DQ/DQS(RDDQC) : PASS
3686 01:15:49.196996 TX DQ/DQS : PASS
3687 01:15:49.199779 RX DATLAT : PASS
3688 01:15:49.203132 RX DQ/DQS(Engine): PASS
3689 01:15:49.203676 TX OE : NO K
3690 01:15:49.206651 All Pass.
3691 01:15:49.207075
3692 01:15:49.207616 CH 1, Rank 1
3693 01:15:49.209795 SW Impedance : PASS
3694 01:15:49.210220 DUTY Scan : NO K
3695 01:15:49.213477 ZQ Calibration : PASS
3696 01:15:49.216642 Jitter Meter : NO K
3697 01:15:49.217136 CBT Training : PASS
3698 01:15:49.219721 Write leveling : PASS
3699 01:15:49.223165 RX DQS gating : PASS
3700 01:15:49.223579 RX DQ/DQS(RDDQC) : PASS
3701 01:15:49.226489 TX DQ/DQS : PASS
3702 01:15:49.229461 RX DATLAT : PASS
3703 01:15:49.229913 RX DQ/DQS(Engine): PASS
3704 01:15:49.232856 TX OE : NO K
3705 01:15:49.233303 All Pass.
3706 01:15:49.233636
3707 01:15:49.236222 DramC Write-DBI off
3708 01:15:49.239611 PER_BANK_REFRESH: Hybrid Mode
3709 01:15:49.240162 TX_TRACKING: ON
3710 01:15:49.249215 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3711 01:15:49.252882 [FAST_K] Save calibration result to emmc
3712 01:15:49.255939 dramc_set_vcore_voltage set vcore to 650000
3713 01:15:49.259083 Read voltage for 600, 5
3714 01:15:49.259518 Vio18 = 0
3715 01:15:49.259847 Vcore = 650000
3716 01:15:49.262561 Vdram = 0
3717 01:15:49.262975 Vddq = 0
3718 01:15:49.263306 Vmddr = 0
3719 01:15:49.269333 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3720 01:15:49.272372 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3721 01:15:49.276429 MEM_TYPE=3, freq_sel=19
3722 01:15:49.279007 sv_algorithm_assistance_LP4_1600
3723 01:15:49.282388 ============ PULL DRAM RESETB DOWN ============
3724 01:15:49.285793 ========== PULL DRAM RESETB DOWN end =========
3725 01:15:49.291875 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3726 01:15:49.295595 ===================================
3727 01:15:49.298905 LPDDR4 DRAM CONFIGURATION
3728 01:15:49.301694 ===================================
3729 01:15:49.302112 EX_ROW_EN[0] = 0x0
3730 01:15:49.305049 EX_ROW_EN[1] = 0x0
3731 01:15:49.305559 LP4Y_EN = 0x0
3732 01:15:49.308228 WORK_FSP = 0x0
3733 01:15:49.308640 WL = 0x2
3734 01:15:49.311867 RL = 0x2
3735 01:15:49.314691 BL = 0x2
3736 01:15:49.315105 RPST = 0x0
3737 01:15:49.318355 RD_PRE = 0x0
3738 01:15:49.318767 WR_PRE = 0x1
3739 01:15:49.321099 WR_PST = 0x0
3740 01:15:49.321514 DBI_WR = 0x0
3741 01:15:49.324677 DBI_RD = 0x0
3742 01:15:49.325090 OTF = 0x1
3743 01:15:49.327868 ===================================
3744 01:15:49.331057 ===================================
3745 01:15:49.335096 ANA top config
3746 01:15:49.337624 ===================================
3747 01:15:49.338039 DLL_ASYNC_EN = 0
3748 01:15:49.341395 ALL_SLAVE_EN = 1
3749 01:15:49.344438 NEW_RANK_MODE = 1
3750 01:15:49.347694 DLL_IDLE_MODE = 1
3751 01:15:49.351047 LP45_APHY_COMB_EN = 1
3752 01:15:49.351462 TX_ODT_DIS = 1
3753 01:15:49.354444 NEW_8X_MODE = 1
3754 01:15:49.357574 ===================================
3755 01:15:49.360714 ===================================
3756 01:15:49.363766 data_rate = 1200
3757 01:15:49.367473 CKR = 1
3758 01:15:49.370461 DQ_P2S_RATIO = 8
3759 01:15:49.374145 ===================================
3760 01:15:49.377250 CA_P2S_RATIO = 8
3761 01:15:49.377801 DQ_CA_OPEN = 0
3762 01:15:49.380234 DQ_SEMI_OPEN = 0
3763 01:15:49.383956 CA_SEMI_OPEN = 0
3764 01:15:49.387182 CA_FULL_RATE = 0
3765 01:15:49.390409 DQ_CKDIV4_EN = 1
3766 01:15:49.393877 CA_CKDIV4_EN = 1
3767 01:15:49.394426 CA_PREDIV_EN = 0
3768 01:15:49.397428 PH8_DLY = 0
3769 01:15:49.400502 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3770 01:15:49.403590 DQ_AAMCK_DIV = 4
3771 01:15:49.407349 CA_AAMCK_DIV = 4
3772 01:15:49.410235 CA_ADMCK_DIV = 4
3773 01:15:49.410679 DQ_TRACK_CA_EN = 0
3774 01:15:49.413919 CA_PICK = 600
3775 01:15:49.416752 CA_MCKIO = 600
3776 01:15:49.420230 MCKIO_SEMI = 0
3777 01:15:49.423764 PLL_FREQ = 2288
3778 01:15:49.426707 DQ_UI_PI_RATIO = 32
3779 01:15:49.429728 CA_UI_PI_RATIO = 0
3780 01:15:49.433319 ===================================
3781 01:15:49.436745 ===================================
3782 01:15:49.437278 memory_type:LPDDR4
3783 01:15:49.440241 GP_NUM : 10
3784 01:15:49.442984 SRAM_EN : 1
3785 01:15:49.443447 MD32_EN : 0
3786 01:15:49.446197 ===================================
3787 01:15:49.449590 [ANA_INIT] >>>>>>>>>>>>>>
3788 01:15:49.452964 <<<<<< [CONFIGURE PHASE]: ANA_TX
3789 01:15:49.455969 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3790 01:15:49.459418 ===================================
3791 01:15:49.462672 data_rate = 1200,PCW = 0X5800
3792 01:15:49.466049 ===================================
3793 01:15:49.469239 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3794 01:15:49.472604 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3795 01:15:49.479326 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3796 01:15:49.485972 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3797 01:15:49.488940 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3798 01:15:49.491982 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3799 01:15:49.492409 [ANA_INIT] flow start
3800 01:15:49.495573 [ANA_INIT] PLL >>>>>>>>
3801 01:15:49.498581 [ANA_INIT] PLL <<<<<<<<
3802 01:15:49.498998 [ANA_INIT] MIDPI >>>>>>>>
3803 01:15:49.502473 [ANA_INIT] MIDPI <<<<<<<<
3804 01:15:49.505249 [ANA_INIT] DLL >>>>>>>>
3805 01:15:49.505666 [ANA_INIT] flow end
3806 01:15:49.511984 ============ LP4 DIFF to SE enter ============
3807 01:15:49.515057 ============ LP4 DIFF to SE exit ============
3808 01:15:49.518626 [ANA_INIT] <<<<<<<<<<<<<
3809 01:15:49.521617 [Flow] Enable top DCM control >>>>>
3810 01:15:49.525400 [Flow] Enable top DCM control <<<<<
3811 01:15:49.525932 Enable DLL master slave shuffle
3812 01:15:49.531916 ==============================================================
3813 01:15:49.535138 Gating Mode config
3814 01:15:49.538792 ==============================================================
3815 01:15:49.541590 Config description:
3816 01:15:49.551528 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3817 01:15:49.557954 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3818 01:15:49.561320 SELPH_MODE 0: By rank 1: By Phase
3819 01:15:49.567783 ==============================================================
3820 01:15:49.570967 GAT_TRACK_EN = 1
3821 01:15:49.574413 RX_GATING_MODE = 2
3822 01:15:49.577894 RX_GATING_TRACK_MODE = 2
3823 01:15:49.580846 SELPH_MODE = 1
3824 01:15:49.584069 PICG_EARLY_EN = 1
3825 01:15:49.587584 VALID_LAT_VALUE = 1
3826 01:15:49.590654 ==============================================================
3827 01:15:49.594642 Enter into Gating configuration >>>>
3828 01:15:49.597477 Exit from Gating configuration <<<<
3829 01:15:49.600442 Enter into DVFS_PRE_config >>>>>
3830 01:15:49.613590 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3831 01:15:49.617294 Exit from DVFS_PRE_config <<<<<
3832 01:15:49.617710 Enter into PICG configuration >>>>
3833 01:15:49.620150 Exit from PICG configuration <<<<
3834 01:15:49.623774 [RX_INPUT] configuration >>>>>
3835 01:15:49.626735 [RX_INPUT] configuration <<<<<
3836 01:15:49.633347 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3837 01:15:49.636886 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3838 01:15:49.643627 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3839 01:15:49.649703 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3840 01:15:49.656374 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3841 01:15:49.662859 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3842 01:15:49.666659 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3843 01:15:49.669527 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3844 01:15:49.676004 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3845 01:15:49.679701 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3846 01:15:49.682631 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3847 01:15:49.686094 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3848 01:15:49.689588 ===================================
3849 01:15:49.692500 LPDDR4 DRAM CONFIGURATION
3850 01:15:49.696174 ===================================
3851 01:15:49.699333 EX_ROW_EN[0] = 0x0
3852 01:15:49.699952 EX_ROW_EN[1] = 0x0
3853 01:15:49.702769 LP4Y_EN = 0x0
3854 01:15:49.703212 WORK_FSP = 0x0
3855 01:15:49.705989 WL = 0x2
3856 01:15:49.706402 RL = 0x2
3857 01:15:49.708872 BL = 0x2
3858 01:15:49.712665 RPST = 0x0
3859 01:15:49.713077 RD_PRE = 0x0
3860 01:15:49.715561 WR_PRE = 0x1
3861 01:15:49.716005 WR_PST = 0x0
3862 01:15:49.718988 DBI_WR = 0x0
3863 01:15:49.719402 DBI_RD = 0x0
3864 01:15:49.722406 OTF = 0x1
3865 01:15:49.725793 ===================================
3866 01:15:49.728629 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3867 01:15:49.731790 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3868 01:15:49.738792 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3869 01:15:49.741920 ===================================
3870 01:15:49.742488 LPDDR4 DRAM CONFIGURATION
3871 01:15:49.745438 ===================================
3872 01:15:49.748433 EX_ROW_EN[0] = 0x10
3873 01:15:49.748865 EX_ROW_EN[1] = 0x0
3874 01:15:49.751565 LP4Y_EN = 0x0
3875 01:15:49.755219 WORK_FSP = 0x0
3876 01:15:49.755632 WL = 0x2
3877 01:15:49.758095 RL = 0x2
3878 01:15:49.758508 BL = 0x2
3879 01:15:49.761794 RPST = 0x0
3880 01:15:49.762205 RD_PRE = 0x0
3881 01:15:49.764698 WR_PRE = 0x1
3882 01:15:49.765129 WR_PST = 0x0
3883 01:15:49.768186 DBI_WR = 0x0
3884 01:15:49.768603 DBI_RD = 0x0
3885 01:15:49.771684 OTF = 0x1
3886 01:15:49.774943 ===================================
3887 01:15:49.781595 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3888 01:15:49.784652 nWR fixed to 30
3889 01:15:49.785159 [ModeRegInit_LP4] CH0 RK0
3890 01:15:49.788147 [ModeRegInit_LP4] CH0 RK1
3891 01:15:49.791171 [ModeRegInit_LP4] CH1 RK0
3892 01:15:49.794160 [ModeRegInit_LP4] CH1 RK1
3893 01:15:49.794651 match AC timing 17
3894 01:15:49.800528 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3895 01:15:49.804158 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3896 01:15:49.807358 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3897 01:15:49.814161 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3898 01:15:49.817279 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3899 01:15:49.817362 ==
3900 01:15:49.820178 Dram Type= 6, Freq= 0, CH_0, rank 0
3901 01:15:49.823718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3902 01:15:49.823809 ==
3903 01:15:49.830315 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3904 01:15:49.837166 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3905 01:15:49.840660 [CA 0] Center 36 (6~67) winsize 62
3906 01:15:49.843485 [CA 1] Center 36 (5~67) winsize 63
3907 01:15:49.847093 [CA 2] Center 34 (4~65) winsize 62
3908 01:15:49.850312 [CA 3] Center 34 (4~65) winsize 62
3909 01:15:49.853853 [CA 4] Center 33 (3~64) winsize 62
3910 01:15:49.856857 [CA 5] Center 33 (3~64) winsize 62
3911 01:15:49.857277
3912 01:15:49.860561 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3913 01:15:49.860982
3914 01:15:49.863741 [CATrainingPosCal] consider 1 rank data
3915 01:15:49.867239 u2DelayCellTimex100 = 270/100 ps
3916 01:15:49.870229 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3917 01:15:49.873482 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3918 01:15:49.876512 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3919 01:15:49.880113 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3920 01:15:49.886892 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3921 01:15:49.890151 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3922 01:15:49.890570
3923 01:15:49.893573 CA PerBit enable=1, Macro0, CA PI delay=33
3924 01:15:49.893994
3925 01:15:49.896765 [CBTSetCACLKResult] CA Dly = 33
3926 01:15:49.897270 CS Dly: 4 (0~35)
3927 01:15:49.897608 ==
3928 01:15:49.899858 Dram Type= 6, Freq= 0, CH_0, rank 1
3929 01:15:49.902962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3930 01:15:49.906534 ==
3931 01:15:49.909698 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3932 01:15:49.916456 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3933 01:15:49.919411 [CA 0] Center 36 (6~67) winsize 62
3934 01:15:49.922823 [CA 1] Center 36 (6~67) winsize 62
3935 01:15:49.926259 [CA 2] Center 34 (4~65) winsize 62
3936 01:15:49.929349 [CA 3] Center 34 (4~65) winsize 62
3937 01:15:49.932984 [CA 4] Center 33 (3~64) winsize 62
3938 01:15:49.936035 [CA 5] Center 33 (3~64) winsize 62
3939 01:15:49.936467
3940 01:15:49.939511 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3941 01:15:49.940061
3942 01:15:49.942778 [CATrainingPosCal] consider 2 rank data
3943 01:15:49.945662 u2DelayCellTimex100 = 270/100 ps
3944 01:15:49.949220 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3945 01:15:49.955665 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3946 01:15:49.958814 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3947 01:15:49.962451 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3948 01:15:49.965620 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3949 01:15:49.969133 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3950 01:15:49.969552
3951 01:15:49.972086 CA PerBit enable=1, Macro0, CA PI delay=33
3952 01:15:49.972529
3953 01:15:49.975273 [CBTSetCACLKResult] CA Dly = 33
3954 01:15:49.978908 CS Dly: 5 (0~37)
3955 01:15:49.979347
3956 01:15:49.981842 ----->DramcWriteLeveling(PI) begin...
3957 01:15:49.982260 ==
3958 01:15:49.985590 Dram Type= 6, Freq= 0, CH_0, rank 0
3959 01:15:49.988772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3960 01:15:49.989189 ==
3961 01:15:49.991938 Write leveling (Byte 0): 36 => 36
3962 01:15:49.994971 Write leveling (Byte 1): 29 => 29
3963 01:15:49.998398 DramcWriteLeveling(PI) end<-----
3964 01:15:49.998816
3965 01:15:49.999145 ==
3966 01:15:50.001803 Dram Type= 6, Freq= 0, CH_0, rank 0
3967 01:15:50.005155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3968 01:15:50.005683 ==
3969 01:15:50.008422 [Gating] SW mode calibration
3970 01:15:50.015198 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3971 01:15:50.021740 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3972 01:15:50.024411 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3973 01:15:50.027778 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3974 01:15:50.034685 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3975 01:15:50.038092 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3976 01:15:50.041264 0 9 16 | B1->B0 | 2e2e 2929 | 0 0 | (0 0) (0 0)
3977 01:15:50.048143 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 01:15:50.050792 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 01:15:50.054192 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 01:15:50.060934 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 01:15:50.064224 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 01:15:50.070666 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 01:15:50.073976 0 10 12 | B1->B0 | 2626 3030 | 0 0 | (0 0) (0 0)
3984 01:15:50.077161 0 10 16 | B1->B0 | 3a3a 4343 | 0 1 | (0 0) (0 0)
3985 01:15:50.080866 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 01:15:50.087031 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 01:15:50.090546 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 01:15:50.096947 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 01:15:50.100414 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 01:15:50.103961 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 01:15:50.110055 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3992 01:15:50.113438 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3993 01:15:50.116932 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 01:15:50.123525 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 01:15:50.126571 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 01:15:50.129933 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 01:15:50.136637 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 01:15:50.140360 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 01:15:50.143051 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 01:15:50.149666 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 01:15:50.152769 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 01:15:50.155868 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 01:15:50.162660 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 01:15:50.166172 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 01:15:50.169512 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 01:15:50.175418 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 01:15:50.179022 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 01:15:50.182446 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4009 01:15:50.185629 Total UI for P1: 0, mck2ui 16
4010 01:15:50.188679 best dqsien dly found for B0: ( 0, 13, 14)
4011 01:15:50.195430 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 01:15:50.195988 Total UI for P1: 0, mck2ui 16
4013 01:15:50.202593 best dqsien dly found for B1: ( 0, 13, 18)
4014 01:15:50.205100 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4015 01:15:50.208843 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4016 01:15:50.209410
4017 01:15:50.211783 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4018 01:15:50.215154 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4019 01:15:50.218941 [Gating] SW calibration Done
4020 01:15:50.219502 ==
4021 01:15:50.221403 Dram Type= 6, Freq= 0, CH_0, rank 0
4022 01:15:50.225009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4023 01:15:50.225600 ==
4024 01:15:50.228623 RX Vref Scan: 0
4025 01:15:50.229086
4026 01:15:50.229454 RX Vref 0 -> 0, step: 1
4027 01:15:50.231653
4028 01:15:50.232170 RX Delay -230 -> 252, step: 16
4029 01:15:50.238770 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4030 01:15:50.241890 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4031 01:15:50.245211 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4032 01:15:50.248583 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4033 01:15:50.254881 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4034 01:15:50.258032 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4035 01:15:50.261119 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4036 01:15:50.264946 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4037 01:15:50.271008 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4038 01:15:50.274516 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4039 01:15:50.277680 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4040 01:15:50.280971 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4041 01:15:50.284318 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4042 01:15:50.290874 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4043 01:15:50.294245 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4044 01:15:50.297992 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4045 01:15:50.298409 ==
4046 01:15:50.301185 Dram Type= 6, Freq= 0, CH_0, rank 0
4047 01:15:50.307244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4048 01:15:50.307818 ==
4049 01:15:50.308354 DQS Delay:
4050 01:15:50.310671 DQS0 = 0, DQS1 = 0
4051 01:15:50.311230 DQM Delay:
4052 01:15:50.311723 DQM0 = 43, DQM1 = 32
4053 01:15:50.313821 DQ Delay:
4054 01:15:50.317506 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4055 01:15:50.320489 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4056 01:15:50.323833 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4057 01:15:50.327076 DQ12 =41, DQ13 =33, DQ14 =49, DQ15 =33
4058 01:15:50.327688
4059 01:15:50.328199
4060 01:15:50.328670 ==
4061 01:15:50.330388 Dram Type= 6, Freq= 0, CH_0, rank 0
4062 01:15:50.334028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4063 01:15:50.334465 ==
4064 01:15:50.334803
4065 01:15:50.335109
4066 01:15:50.336882 TX Vref Scan disable
4067 01:15:50.340638 == TX Byte 0 ==
4068 01:15:50.343509 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4069 01:15:50.347073 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4070 01:15:50.350083 == TX Byte 1 ==
4071 01:15:50.353112 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4072 01:15:50.356718 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4073 01:15:50.357144 ==
4074 01:15:50.360145 Dram Type= 6, Freq= 0, CH_0, rank 0
4075 01:15:50.366744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4076 01:15:50.367288 ==
4077 01:15:50.367783
4078 01:15:50.368188
4079 01:15:50.368496 TX Vref Scan disable
4080 01:15:50.371116 == TX Byte 0 ==
4081 01:15:50.374040 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4082 01:15:50.380718 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4083 01:15:50.381171 == TX Byte 1 ==
4084 01:15:50.384357 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4085 01:15:50.390868 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4086 01:15:50.391284
4087 01:15:50.391611 [DATLAT]
4088 01:15:50.391959 Freq=600, CH0 RK0
4089 01:15:50.392267
4090 01:15:50.393869 DATLAT Default: 0x9
4091 01:15:50.397335 0, 0xFFFF, sum = 0
4092 01:15:50.397759 1, 0xFFFF, sum = 0
4093 01:15:50.400764 2, 0xFFFF, sum = 0
4094 01:15:50.401185 3, 0xFFFF, sum = 0
4095 01:15:50.403955 4, 0xFFFF, sum = 0
4096 01:15:50.404386 5, 0xFFFF, sum = 0
4097 01:15:50.407022 6, 0xFFFF, sum = 0
4098 01:15:50.407441 7, 0xFFFF, sum = 0
4099 01:15:50.410244 8, 0x0, sum = 1
4100 01:15:50.410665 9, 0x0, sum = 2
4101 01:15:50.413837 10, 0x0, sum = 3
4102 01:15:50.414307 11, 0x0, sum = 4
4103 01:15:50.414658 best_step = 9
4104 01:15:50.414966
4105 01:15:50.416997 ==
4106 01:15:50.417413 Dram Type= 6, Freq= 0, CH_0, rank 0
4107 01:15:50.423550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4108 01:15:50.424004 ==
4109 01:15:50.424337 RX Vref Scan: 1
4110 01:15:50.424648
4111 01:15:50.427223 RX Vref 0 -> 0, step: 1
4112 01:15:50.427636
4113 01:15:50.430174 RX Delay -195 -> 252, step: 8
4114 01:15:50.430589
4115 01:15:50.433419 Set Vref, RX VrefLevel [Byte0]: 57
4116 01:15:50.436909 [Byte1]: 59
4117 01:15:50.437324
4118 01:15:50.439964 Final RX Vref Byte 0 = 57 to rank0
4119 01:15:50.443346 Final RX Vref Byte 1 = 59 to rank0
4120 01:15:50.446604 Final RX Vref Byte 0 = 57 to rank1
4121 01:15:50.449854 Final RX Vref Byte 1 = 59 to rank1==
4122 01:15:50.453718 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 01:15:50.459455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 01:15:50.460066 ==
4125 01:15:50.460548 DQS Delay:
4126 01:15:50.460904 DQS0 = 0, DQS1 = 0
4127 01:15:50.462928 DQM Delay:
4128 01:15:50.463374 DQM0 = 40, DQM1 = 33
4129 01:15:50.466325 DQ Delay:
4130 01:15:50.469433 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =36
4131 01:15:50.472641 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44
4132 01:15:50.476187 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4133 01:15:50.479296 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4134 01:15:50.479767
4135 01:15:50.480267
4136 01:15:50.485981 [DQSOSCAuto] RK0, (LSB)MR18= 0x4941, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4137 01:15:50.488950 CH0 RK0: MR19=808, MR18=4941
4138 01:15:50.495512 CH0_RK0: MR19=0x808, MR18=0x4941, DQSOSC=396, MR23=63, INC=167, DEC=111
4139 01:15:50.495961
4140 01:15:50.499124 ----->DramcWriteLeveling(PI) begin...
4141 01:15:50.499545 ==
4142 01:15:50.502187 Dram Type= 6, Freq= 0, CH_0, rank 1
4143 01:15:50.505598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 01:15:50.506012 ==
4145 01:15:50.509037 Write leveling (Byte 0): 35 => 35
4146 01:15:50.511861 Write leveling (Byte 1): 29 => 29
4147 01:15:50.515458 DramcWriteLeveling(PI) end<-----
4148 01:15:50.515929
4149 01:15:50.516266 ==
4150 01:15:50.518655 Dram Type= 6, Freq= 0, CH_0, rank 1
4151 01:15:50.525308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 01:15:50.525761 ==
4153 01:15:50.526088 [Gating] SW mode calibration
4154 01:15:50.534967 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4155 01:15:50.538349 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4156 01:15:50.541855 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4157 01:15:50.548781 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4158 01:15:50.551582 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4159 01:15:50.555169 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
4160 01:15:50.561535 0 9 16 | B1->B0 | 2d2d 2424 | 0 0 | (1 0) (0 0)
4161 01:15:50.564750 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4162 01:15:50.568387 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 01:15:50.574579 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 01:15:50.578249 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 01:15:50.581271 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 01:15:50.587865 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 01:15:50.590959 0 10 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
4168 01:15:50.594494 0 10 16 | B1->B0 | 3b3b 4545 | 0 0 | (1 1) (0 0)
4169 01:15:50.601193 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4170 01:15:50.604103 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 01:15:50.607646 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 01:15:50.614232 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 01:15:50.617415 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 01:15:50.620507 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 01:15:50.627508 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 01:15:50.630596 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4177 01:15:50.637280 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 01:15:50.640376 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 01:15:50.643550 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 01:15:50.650320 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 01:15:50.653552 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 01:15:50.656673 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 01:15:50.663081 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 01:15:50.666419 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 01:15:50.669571 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 01:15:50.676836 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 01:15:50.679792 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 01:15:50.683229 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 01:15:50.689780 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 01:15:50.692761 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4191 01:15:50.696502 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 01:15:50.702912 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 01:15:50.703330 Total UI for P1: 0, mck2ui 16
4194 01:15:50.709410 best dqsien dly found for B0: ( 0, 13, 14)
4195 01:15:50.709866 Total UI for P1: 0, mck2ui 16
4196 01:15:50.715789 best dqsien dly found for B1: ( 0, 13, 14)
4197 01:15:50.719080 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4198 01:15:50.722560 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4199 01:15:50.723052
4200 01:15:50.725470 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4201 01:15:50.729069 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4202 01:15:50.732352 [Gating] SW calibration Done
4203 01:15:50.732762 ==
4204 01:15:50.735311 Dram Type= 6, Freq= 0, CH_0, rank 1
4205 01:15:50.738469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4206 01:15:50.738880 ==
4207 01:15:50.742079 RX Vref Scan: 0
4208 01:15:50.742489
4209 01:15:50.745398 RX Vref 0 -> 0, step: 1
4210 01:15:50.745916
4211 01:15:50.746250 RX Delay -230 -> 252, step: 16
4212 01:15:50.751953 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4213 01:15:50.754878 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4214 01:15:50.758355 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4215 01:15:50.761687 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4216 01:15:50.768599 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4217 01:15:50.771459 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4218 01:15:50.774637 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4219 01:15:50.778320 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4220 01:15:50.784929 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4221 01:15:50.788060 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4222 01:15:50.791265 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4223 01:15:50.794871 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4224 01:15:50.801012 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4225 01:15:50.804116 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4226 01:15:50.807784 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4227 01:15:50.810817 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4228 01:15:50.811236 ==
4229 01:15:50.814359 Dram Type= 6, Freq= 0, CH_0, rank 1
4230 01:15:50.820955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4231 01:15:50.821433 ==
4232 01:15:50.821763 DQS Delay:
4233 01:15:50.823958 DQS0 = 0, DQS1 = 0
4234 01:15:50.824374 DQM Delay:
4235 01:15:50.827700 DQM0 = 46, DQM1 = 32
4236 01:15:50.828140 DQ Delay:
4237 01:15:50.830698 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =49
4238 01:15:50.834379 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4239 01:15:50.837091 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4240 01:15:50.841013 DQ12 =41, DQ13 =33, DQ14 =49, DQ15 =41
4241 01:15:50.841424
4242 01:15:50.841746
4243 01:15:50.842047 ==
4244 01:15:50.844018 Dram Type= 6, Freq= 0, CH_0, rank 1
4245 01:15:50.847065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4246 01:15:50.847470 ==
4247 01:15:50.847908
4248 01:15:50.848312
4249 01:15:50.850599 TX Vref Scan disable
4250 01:15:50.853604 == TX Byte 0 ==
4251 01:15:50.857197 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4252 01:15:50.860090 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4253 01:15:50.863968 == TX Byte 1 ==
4254 01:15:50.866847 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4255 01:15:50.870215 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4256 01:15:50.870618 ==
4257 01:15:50.873210 Dram Type= 6, Freq= 0, CH_0, rank 1
4258 01:15:50.879658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4259 01:15:50.880183 ==
4260 01:15:50.880631
4261 01:15:50.881124
4262 01:15:50.881519 TX Vref Scan disable
4263 01:15:50.884533 == TX Byte 0 ==
4264 01:15:50.888037 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4265 01:15:50.894856 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4266 01:15:50.895505 == TX Byte 1 ==
4267 01:15:50.897623 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4268 01:15:50.904119 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4269 01:15:50.904632
4270 01:15:50.905143 [DATLAT]
4271 01:15:50.905546 Freq=600, CH0 RK1
4272 01:15:50.905943
4273 01:15:50.907592 DATLAT Default: 0x9
4274 01:15:50.910753 0, 0xFFFF, sum = 0
4275 01:15:50.911232 1, 0xFFFF, sum = 0
4276 01:15:50.914165 2, 0xFFFF, sum = 0
4277 01:15:50.914596 3, 0xFFFF, sum = 0
4278 01:15:50.917977 4, 0xFFFF, sum = 0
4279 01:15:50.918509 5, 0xFFFF, sum = 0
4280 01:15:50.920775 6, 0xFFFF, sum = 0
4281 01:15:50.921204 7, 0xFFFF, sum = 0
4282 01:15:50.924250 8, 0x0, sum = 1
4283 01:15:50.924680 9, 0x0, sum = 2
4284 01:15:50.927218 10, 0x0, sum = 3
4285 01:15:50.927801 11, 0x0, sum = 4
4286 01:15:50.928301 best_step = 9
4287 01:15:50.928729
4288 01:15:50.930945 ==
4289 01:15:50.933957 Dram Type= 6, Freq= 0, CH_0, rank 1
4290 01:15:50.937168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4291 01:15:50.938055 ==
4292 01:15:50.938773 RX Vref Scan: 0
4293 01:15:50.939116
4294 01:15:50.940751 RX Vref 0 -> 0, step: 1
4295 01:15:50.941260
4296 01:15:50.943733 RX Delay -195 -> 252, step: 8
4297 01:15:50.950610 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4298 01:15:50.953481 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4299 01:15:50.956585 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4300 01:15:50.960351 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4301 01:15:50.966998 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4302 01:15:50.970044 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4303 01:15:50.972963 iDelay=205, Bit 6, Center 48 (-99 ~ 196) 296
4304 01:15:50.976583 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4305 01:15:50.979583 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4306 01:15:50.986170 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4307 01:15:50.990117 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4308 01:15:50.993310 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4309 01:15:50.996162 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4310 01:15:51.002781 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4311 01:15:51.005760 iDelay=205, Bit 14, Center 48 (-107 ~ 204) 312
4312 01:15:51.008716 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4313 01:15:51.008799 ==
4314 01:15:51.012168 Dram Type= 6, Freq= 0, CH_0, rank 1
4315 01:15:51.018538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4316 01:15:51.018614 ==
4317 01:15:51.018694 DQS Delay:
4318 01:15:51.022186 DQS0 = 0, DQS1 = 0
4319 01:15:51.022262 DQM Delay:
4320 01:15:51.022330 DQM0 = 40, DQM1 = 34
4321 01:15:51.025562 DQ Delay:
4322 01:15:51.028405 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4323 01:15:51.031971 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =48
4324 01:15:51.035108 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4325 01:15:51.038943 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =40
4326 01:15:51.039017
4327 01:15:51.039076
4328 01:15:51.045362 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f3a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4329 01:15:51.048332 CH0 RK1: MR19=808, MR18=3F3A
4330 01:15:51.055458 CH0_RK1: MR19=0x808, MR18=0x3F3A, DQSOSC=397, MR23=63, INC=166, DEC=110
4331 01:15:51.058353 [RxdqsGatingPostProcess] freq 600
4332 01:15:51.065347 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4333 01:15:51.065799 Pre-setting of DQS Precalculation
4334 01:15:51.071865 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4335 01:15:51.072346 ==
4336 01:15:51.074954 Dram Type= 6, Freq= 0, CH_1, rank 0
4337 01:15:51.078189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4338 01:15:51.078741 ==
4339 01:15:51.085159 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4340 01:15:51.091764 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4341 01:15:51.094670 [CA 0] Center 36 (6~66) winsize 61
4342 01:15:51.098045 [CA 1] Center 35 (5~66) winsize 62
4343 01:15:51.101302 [CA 2] Center 34 (4~65) winsize 62
4344 01:15:51.104524 [CA 3] Center 34 (3~65) winsize 63
4345 01:15:51.108154 [CA 4] Center 34 (4~65) winsize 62
4346 01:15:51.111146 [CA 5] Center 34 (3~65) winsize 63
4347 01:15:51.111608
4348 01:15:51.114535 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4349 01:15:51.115063
4350 01:15:51.117919 [CATrainingPosCal] consider 1 rank data
4351 01:15:51.120819 u2DelayCellTimex100 = 270/100 ps
4352 01:15:51.124428 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4353 01:15:51.127954 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4354 01:15:51.130699 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4355 01:15:51.134066 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4356 01:15:51.137621 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4357 01:15:51.144143 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4358 01:15:51.144555
4359 01:15:51.147296 CA PerBit enable=1, Macro0, CA PI delay=34
4360 01:15:51.147703
4361 01:15:51.150950 [CBTSetCACLKResult] CA Dly = 34
4362 01:15:51.151360 CS Dly: 5 (0~36)
4363 01:15:51.151685 ==
4364 01:15:51.153865 Dram Type= 6, Freq= 0, CH_1, rank 1
4365 01:15:51.157582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4366 01:15:51.160485 ==
4367 01:15:51.163783 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4368 01:15:51.170388 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4369 01:15:51.174082 [CA 0] Center 36 (6~66) winsize 61
4370 01:15:51.177009 [CA 1] Center 36 (6~66) winsize 61
4371 01:15:51.180580 [CA 2] Center 34 (4~65) winsize 62
4372 01:15:51.183429 [CA 3] Center 34 (3~65) winsize 63
4373 01:15:51.186557 [CA 4] Center 34 (4~65) winsize 62
4374 01:15:51.190233 [CA 5] Center 34 (3~65) winsize 63
4375 01:15:51.190641
4376 01:15:51.193279 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4377 01:15:51.193721
4378 01:15:51.197034 [CATrainingPosCal] consider 2 rank data
4379 01:15:51.200088 u2DelayCellTimex100 = 270/100 ps
4380 01:15:51.203125 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4381 01:15:51.209894 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4382 01:15:51.213606 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4383 01:15:51.216446 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4384 01:15:51.219822 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4385 01:15:51.222965 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4386 01:15:51.223377
4387 01:15:51.226147 CA PerBit enable=1, Macro0, CA PI delay=34
4388 01:15:51.226577
4389 01:15:51.229797 [CBTSetCACLKResult] CA Dly = 34
4390 01:15:51.232792 CS Dly: 5 (0~37)
4391 01:15:51.233231
4392 01:15:51.236363 ----->DramcWriteLeveling(PI) begin...
4393 01:15:51.236899 ==
4394 01:15:51.239529 Dram Type= 6, Freq= 0, CH_1, rank 0
4395 01:15:51.243062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 01:15:51.243627 ==
4397 01:15:51.246031 Write leveling (Byte 0): 29 => 29
4398 01:15:51.249798 Write leveling (Byte 1): 31 => 31
4399 01:15:51.252564 DramcWriteLeveling(PI) end<-----
4400 01:15:51.252991
4401 01:15:51.253420 ==
4402 01:15:51.255928 Dram Type= 6, Freq= 0, CH_1, rank 0
4403 01:15:51.259196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4404 01:15:51.259627 ==
4405 01:15:51.262143 [Gating] SW mode calibration
4406 01:15:51.268825 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4407 01:15:51.275736 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4408 01:15:51.278898 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4409 01:15:51.282395 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4410 01:15:51.288489 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4411 01:15:51.292389 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
4412 01:15:51.295234 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 01:15:51.302282 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 01:15:51.305040 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 01:15:51.308696 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 01:15:51.315319 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 01:15:51.318452 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 01:15:51.321392 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4419 01:15:51.328012 0 10 12 | B1->B0 | 3333 3939 | 0 1 | (0 0) (0 0)
4420 01:15:51.331196 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 01:15:51.335039 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 01:15:51.341400 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 01:15:51.344614 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 01:15:51.351123 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 01:15:51.354481 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 01:15:51.357452 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 01:15:51.364432 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4428 01:15:51.367552 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 01:15:51.370690 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 01:15:51.377326 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 01:15:51.380926 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 01:15:51.384359 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 01:15:51.390113 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 01:15:51.393651 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 01:15:51.396682 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 01:15:51.403429 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 01:15:51.406536 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 01:15:51.409630 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 01:15:51.416698 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 01:15:51.419650 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 01:15:51.423455 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 01:15:51.429561 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 01:15:51.433230 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4444 01:15:51.436084 Total UI for P1: 0, mck2ui 16
4445 01:15:51.439812 best dqsien dly found for B0: ( 0, 13, 10)
4446 01:15:51.442713 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 01:15:51.446264 Total UI for P1: 0, mck2ui 16
4448 01:15:51.449286 best dqsien dly found for B1: ( 0, 13, 12)
4449 01:15:51.452806 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4450 01:15:51.455972 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4451 01:15:51.456397
4452 01:15:51.462953 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4453 01:15:51.466104 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4454 01:15:51.469441 [Gating] SW calibration Done
4455 01:15:51.469855 ==
4456 01:15:51.472641 Dram Type= 6, Freq= 0, CH_1, rank 0
4457 01:15:51.475737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4458 01:15:51.476187 ==
4459 01:15:51.476528 RX Vref Scan: 0
4460 01:15:51.479085
4461 01:15:51.479165 RX Vref 0 -> 0, step: 1
4462 01:15:51.479229
4463 01:15:51.482140 RX Delay -230 -> 252, step: 16
4464 01:15:51.485133 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4465 01:15:51.492111 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4466 01:15:51.495729 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4467 01:15:51.498530 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4468 01:15:51.502276 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4469 01:15:51.508957 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4470 01:15:51.512196 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4471 01:15:51.515254 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4472 01:15:51.518616 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4473 01:15:51.521545 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4474 01:15:51.528146 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4475 01:15:51.531856 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4476 01:15:51.534812 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4477 01:15:51.541307 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4478 01:15:51.544753 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4479 01:15:51.548422 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4480 01:15:51.548844 ==
4481 01:15:51.551354 Dram Type= 6, Freq= 0, CH_1, rank 0
4482 01:15:51.554898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4483 01:15:51.555314 ==
4484 01:15:51.558088 DQS Delay:
4485 01:15:51.558530 DQS0 = 0, DQS1 = 0
4486 01:15:51.560976 DQM Delay:
4487 01:15:51.561401 DQM0 = 46, DQM1 = 38
4488 01:15:51.561825 DQ Delay:
4489 01:15:51.564167 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4490 01:15:51.567917 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4491 01:15:51.571293 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4492 01:15:51.574292 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4493 01:15:51.574705
4494 01:15:51.575143
4495 01:15:51.577588 ==
4496 01:15:51.580784 Dram Type= 6, Freq= 0, CH_1, rank 0
4497 01:15:51.584422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4498 01:15:51.584818 ==
4499 01:15:51.585155
4500 01:15:51.585483
4501 01:15:51.587254 TX Vref Scan disable
4502 01:15:51.587663 == TX Byte 0 ==
4503 01:15:51.594124 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4504 01:15:51.597502 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4505 01:15:51.597913 == TX Byte 1 ==
4506 01:15:51.604222 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4507 01:15:51.607262 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4508 01:15:51.607700 ==
4509 01:15:51.610425 Dram Type= 6, Freq= 0, CH_1, rank 0
4510 01:15:51.613953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4511 01:15:51.614369 ==
4512 01:15:51.614693
4513 01:15:51.614996
4514 01:15:51.616992 TX Vref Scan disable
4515 01:15:51.620241 == TX Byte 0 ==
4516 01:15:51.623615 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4517 01:15:51.630476 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4518 01:15:51.630951 == TX Byte 1 ==
4519 01:15:51.633541 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4520 01:15:51.640342 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4521 01:15:51.640803
4522 01:15:51.641136 [DATLAT]
4523 01:15:51.641471 Freq=600, CH1 RK0
4524 01:15:51.641779
4525 01:15:51.643209 DATLAT Default: 0x9
4526 01:15:51.646684 0, 0xFFFF, sum = 0
4527 01:15:51.647154 1, 0xFFFF, sum = 0
4528 01:15:51.650031 2, 0xFFFF, sum = 0
4529 01:15:51.650497 3, 0xFFFF, sum = 0
4530 01:15:51.653397 4, 0xFFFF, sum = 0
4531 01:15:51.653866 5, 0xFFFF, sum = 0
4532 01:15:51.656589 6, 0xFFFF, sum = 0
4533 01:15:51.657019 7, 0xFFFF, sum = 0
4534 01:15:51.660075 8, 0x0, sum = 1
4535 01:15:51.660639 9, 0x0, sum = 2
4536 01:15:51.663314 10, 0x0, sum = 3
4537 01:15:51.663729 11, 0x0, sum = 4
4538 01:15:51.664097 best_step = 9
4539 01:15:51.664404
4540 01:15:51.666404 ==
4541 01:15:51.669955 Dram Type= 6, Freq= 0, CH_1, rank 0
4542 01:15:51.672908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4543 01:15:51.673328 ==
4544 01:15:51.673810 RX Vref Scan: 1
4545 01:15:51.674130
4546 01:15:51.676360 RX Vref 0 -> 0, step: 1
4547 01:15:51.676771
4548 01:15:51.679200 RX Delay -179 -> 252, step: 8
4549 01:15:51.679634
4550 01:15:51.683026 Set Vref, RX VrefLevel [Byte0]: 50
4551 01:15:51.685865 [Byte1]: 54
4552 01:15:51.686277
4553 01:15:51.689824 Final RX Vref Byte 0 = 50 to rank0
4554 01:15:51.692929 Final RX Vref Byte 1 = 54 to rank0
4555 01:15:51.695934 Final RX Vref Byte 0 = 50 to rank1
4556 01:15:51.699216 Final RX Vref Byte 1 = 54 to rank1==
4557 01:15:51.702386 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 01:15:51.709343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 01:15:51.709798 ==
4560 01:15:51.710217 DQS Delay:
4561 01:15:51.710766 DQS0 = 0, DQS1 = 0
4562 01:15:51.712558 DQM Delay:
4563 01:15:51.712972 DQM0 = 41, DQM1 = 34
4564 01:15:51.715493 DQ Delay:
4565 01:15:51.718973 DQ0 =48, DQ1 =36, DQ2 =32, DQ3 =44
4566 01:15:51.721917 DQ4 =36, DQ5 =52, DQ6 =48, DQ7 =36
4567 01:15:51.725378 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4568 01:15:51.728704 DQ12 =44, DQ13 =48, DQ14 =40, DQ15 =40
4569 01:15:51.729142
4570 01:15:51.729485
4571 01:15:51.735718 [DQSOSCAuto] RK0, (LSB)MR18= 0x2842, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
4572 01:15:51.738551 CH1 RK0: MR19=808, MR18=2842
4573 01:15:51.745270 CH1_RK0: MR19=0x808, MR18=0x2842, DQSOSC=397, MR23=63, INC=166, DEC=110
4574 01:15:51.745744
4575 01:15:51.748303 ----->DramcWriteLeveling(PI) begin...
4576 01:15:51.748740 ==
4577 01:15:51.752135 Dram Type= 6, Freq= 0, CH_1, rank 1
4578 01:15:51.755212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 01:15:51.755624 ==
4580 01:15:51.758702 Write leveling (Byte 0): 28 => 28
4581 01:15:51.761667 Write leveling (Byte 1): 32 => 32
4582 01:15:51.765090 DramcWriteLeveling(PI) end<-----
4583 01:15:51.765525
4584 01:15:51.765920 ==
4585 01:15:51.768086 Dram Type= 6, Freq= 0, CH_1, rank 1
4586 01:15:51.771483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 01:15:51.775255 ==
4588 01:15:51.775697 [Gating] SW mode calibration
4589 01:15:51.784738 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4590 01:15:51.787717 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4591 01:15:51.791453 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4592 01:15:51.798328 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4593 01:15:51.801206 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4594 01:15:51.804584 0 9 12 | B1->B0 | 3131 2d2d | 1 0 | (1 0) (0 0)
4595 01:15:51.811025 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4596 01:15:51.814572 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 01:15:51.817492 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 01:15:51.824079 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 01:15:51.827219 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 01:15:51.834372 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 01:15:51.836959 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4602 01:15:51.840323 0 10 12 | B1->B0 | 3030 3e3e | 1 0 | (0 0) (0 0)
4603 01:15:51.847292 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4604 01:15:51.850225 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 01:15:51.854189 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 01:15:51.860225 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 01:15:51.863582 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 01:15:51.866586 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 01:15:51.873245 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4610 01:15:51.876681 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4611 01:15:51.879632 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4612 01:15:51.886521 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 01:15:51.889403 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 01:15:51.893022 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 01:15:51.899715 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 01:15:51.902507 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 01:15:51.906159 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 01:15:51.912872 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 01:15:51.915817 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 01:15:51.919202 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 01:15:51.925718 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 01:15:51.929398 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 01:15:51.932424 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 01:15:51.939295 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 01:15:51.942410 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 01:15:51.945962 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4627 01:15:51.952029 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 01:15:51.952449 Total UI for P1: 0, mck2ui 16
4629 01:15:51.958702 best dqsien dly found for B0: ( 0, 13, 12)
4630 01:15:51.959125 Total UI for P1: 0, mck2ui 16
4631 01:15:51.965456 best dqsien dly found for B1: ( 0, 13, 12)
4632 01:15:51.968400 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4633 01:15:51.971688 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4634 01:15:51.972132
4635 01:15:51.975330 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4636 01:15:51.978355 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4637 01:15:51.981496 [Gating] SW calibration Done
4638 01:15:51.981909 ==
4639 01:15:51.985122 Dram Type= 6, Freq= 0, CH_1, rank 1
4640 01:15:51.988623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4641 01:15:51.989040 ==
4642 01:15:51.991711 RX Vref Scan: 0
4643 01:15:51.992170
4644 01:15:51.992500 RX Vref 0 -> 0, step: 1
4645 01:15:51.995227
4646 01:15:51.995638 RX Delay -230 -> 252, step: 16
4647 01:15:52.001813 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4648 01:15:52.004622 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4649 01:15:52.008401 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4650 01:15:52.011360 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4651 01:15:52.018482 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4652 01:15:52.021291 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4653 01:15:52.024348 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4654 01:15:52.027950 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4655 01:15:52.031486 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4656 01:15:52.037432 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4657 01:15:52.041188 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4658 01:15:52.044519 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4659 01:15:52.050584 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4660 01:15:52.054000 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4661 01:15:52.057170 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4662 01:15:52.060873 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4663 01:15:52.061287 ==
4664 01:15:52.063858 Dram Type= 6, Freq= 0, CH_1, rank 1
4665 01:15:52.070584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4666 01:15:52.071000 ==
4667 01:15:52.071328 DQS Delay:
4668 01:15:52.074002 DQS0 = 0, DQS1 = 0
4669 01:15:52.074438 DQM Delay:
4670 01:15:52.074771 DQM0 = 42, DQM1 = 39
4671 01:15:52.076817 DQ Delay:
4672 01:15:52.080143 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4673 01:15:52.083430 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4674 01:15:52.086652 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4675 01:15:52.090355 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4676 01:15:52.090776
4677 01:15:52.091105
4678 01:15:52.091411 ==
4679 01:15:52.093311 Dram Type= 6, Freq= 0, CH_1, rank 1
4680 01:15:52.096687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4681 01:15:52.097102 ==
4682 01:15:52.097431
4683 01:15:52.097734
4684 01:15:52.100343 TX Vref Scan disable
4685 01:15:52.103364 == TX Byte 0 ==
4686 01:15:52.106801 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4687 01:15:52.109966 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4688 01:15:52.113099 == TX Byte 1 ==
4689 01:15:52.116606 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4690 01:15:52.119941 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4691 01:15:52.120359 ==
4692 01:15:52.122952 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 01:15:52.129774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 01:15:52.130205 ==
4695 01:15:52.130588
4696 01:15:52.130902
4697 01:15:52.131197 TX Vref Scan disable
4698 01:15:52.134061 == TX Byte 0 ==
4699 01:15:52.137350 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4700 01:15:52.144039 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4701 01:15:52.144455 == TX Byte 1 ==
4702 01:15:52.146697 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4703 01:15:52.153875 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4704 01:15:52.154291
4705 01:15:52.154617 [DATLAT]
4706 01:15:52.154921 Freq=600, CH1 RK1
4707 01:15:52.155216
4708 01:15:52.156844 DATLAT Default: 0x9
4709 01:15:52.159968 0, 0xFFFF, sum = 0
4710 01:15:52.160404 1, 0xFFFF, sum = 0
4711 01:15:52.163120 2, 0xFFFF, sum = 0
4712 01:15:52.163556 3, 0xFFFF, sum = 0
4713 01:15:52.166776 4, 0xFFFF, sum = 0
4714 01:15:52.167198 5, 0xFFFF, sum = 0
4715 01:15:52.169993 6, 0xFFFF, sum = 0
4716 01:15:52.170434 7, 0xFFFF, sum = 0
4717 01:15:52.172997 8, 0x0, sum = 1
4718 01:15:52.173422 9, 0x0, sum = 2
4719 01:15:52.176755 10, 0x0, sum = 3
4720 01:15:52.177183 11, 0x0, sum = 4
4721 01:15:52.177523 best_step = 9
4722 01:15:52.177832
4723 01:15:52.179782 ==
4724 01:15:52.182985 Dram Type= 6, Freq= 0, CH_1, rank 1
4725 01:15:52.186616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4726 01:15:52.187035 ==
4727 01:15:52.187364 RX Vref Scan: 0
4728 01:15:52.187672
4729 01:15:52.189828 RX Vref 0 -> 0, step: 1
4730 01:15:52.190245
4731 01:15:52.193172 RX Delay -179 -> 252, step: 8
4732 01:15:52.199457 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4733 01:15:52.202755 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4734 01:15:52.206062 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4735 01:15:52.209260 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4736 01:15:52.216002 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4737 01:15:52.219273 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4738 01:15:52.222539 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4739 01:15:52.225693 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4740 01:15:52.232212 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4741 01:15:52.235794 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4742 01:15:52.238730 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4743 01:15:52.241924 iDelay=205, Bit 11, Center 32 (-123 ~ 188) 312
4744 01:15:52.248464 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4745 01:15:52.252284 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4746 01:15:52.255293 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4747 01:15:52.258350 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4748 01:15:52.258787 ==
4749 01:15:52.261734 Dram Type= 6, Freq= 0, CH_1, rank 1
4750 01:15:52.268552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4751 01:15:52.268978 ==
4752 01:15:52.269313 DQS Delay:
4753 01:15:52.271953 DQS0 = 0, DQS1 = 0
4754 01:15:52.272375 DQM Delay:
4755 01:15:52.272905 DQM0 = 37, DQM1 = 35
4756 01:15:52.275398 DQ Delay:
4757 01:15:52.278456 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4758 01:15:52.281492 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4759 01:15:52.284696 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =32
4760 01:15:52.288144 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =44
4761 01:15:52.288566
4762 01:15:52.288896
4763 01:15:52.294853 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e52, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
4764 01:15:52.297990 CH1 RK1: MR19=808, MR18=2E52
4765 01:15:52.304663 CH1_RK1: MR19=0x808, MR18=0x2E52, DQSOSC=394, MR23=63, INC=168, DEC=112
4766 01:15:52.307679 [RxdqsGatingPostProcess] freq 600
4767 01:15:52.314696 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4768 01:15:52.315119 Pre-setting of DQS Precalculation
4769 01:15:52.321116 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4770 01:15:52.327836 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4771 01:15:52.334569 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4772 01:15:52.335096
4773 01:15:52.335439
4774 01:15:52.338104 [Calibration Summary] 1200 Mbps
4775 01:15:52.340567 CH 0, Rank 0
4776 01:15:52.340987 SW Impedance : PASS
4777 01:15:52.344038 DUTY Scan : NO K
4778 01:15:52.347327 ZQ Calibration : PASS
4779 01:15:52.347745 Jitter Meter : NO K
4780 01:15:52.350527 CBT Training : PASS
4781 01:15:52.353672 Write leveling : PASS
4782 01:15:52.354091 RX DQS gating : PASS
4783 01:15:52.357257 RX DQ/DQS(RDDQC) : PASS
4784 01:15:52.360323 TX DQ/DQS : PASS
4785 01:15:52.360986 RX DATLAT : PASS
4786 01:15:52.363718 RX DQ/DQS(Engine): PASS
4787 01:15:52.367144 TX OE : NO K
4788 01:15:52.367557 All Pass.
4789 01:15:52.367921
4790 01:15:52.368277 CH 0, Rank 1
4791 01:15:52.370100 SW Impedance : PASS
4792 01:15:52.373747 DUTY Scan : NO K
4793 01:15:52.374160 ZQ Calibration : PASS
4794 01:15:52.376570 Jitter Meter : NO K
4795 01:15:52.379828 CBT Training : PASS
4796 01:15:52.380299 Write leveling : PASS
4797 01:15:52.383027 RX DQS gating : PASS
4798 01:15:52.386864 RX DQ/DQS(RDDQC) : PASS
4799 01:15:52.387274 TX DQ/DQS : PASS
4800 01:15:52.389544 RX DATLAT : PASS
4801 01:15:52.389955 RX DQ/DQS(Engine): PASS
4802 01:15:52.393313 TX OE : NO K
4803 01:15:52.393729 All Pass.
4804 01:15:52.394059
4805 01:15:52.396434 CH 1, Rank 0
4806 01:15:52.396846 SW Impedance : PASS
4807 01:15:52.400000 DUTY Scan : NO K
4808 01:15:52.402938 ZQ Calibration : PASS
4809 01:15:52.403352 Jitter Meter : NO K
4810 01:15:52.406122 CBT Training : PASS
4811 01:15:52.409576 Write leveling : PASS
4812 01:15:52.409988 RX DQS gating : PASS
4813 01:15:52.412743 RX DQ/DQS(RDDQC) : PASS
4814 01:15:52.416380 TX DQ/DQS : PASS
4815 01:15:52.416799 RX DATLAT : PASS
4816 01:15:52.419380 RX DQ/DQS(Engine): PASS
4817 01:15:52.423085 TX OE : NO K
4818 01:15:52.423505 All Pass.
4819 01:15:52.423836
4820 01:15:52.424184 CH 1, Rank 1
4821 01:15:52.426060 SW Impedance : PASS
4822 01:15:52.429029 DUTY Scan : NO K
4823 01:15:52.429445 ZQ Calibration : PASS
4824 01:15:52.432853 Jitter Meter : NO K
4825 01:15:52.435758 CBT Training : PASS
4826 01:15:52.436248 Write leveling : PASS
4827 01:15:52.439074 RX DQS gating : PASS
4828 01:15:52.442470 RX DQ/DQS(RDDQC) : PASS
4829 01:15:52.442887 TX DQ/DQS : PASS
4830 01:15:52.445518 RX DATLAT : PASS
4831 01:15:52.449171 RX DQ/DQS(Engine): PASS
4832 01:15:52.449611 TX OE : NO K
4833 01:15:52.452492 All Pass.
4834 01:15:52.452912
4835 01:15:52.453245 DramC Write-DBI off
4836 01:15:52.455758 PER_BANK_REFRESH: Hybrid Mode
4837 01:15:52.456207 TX_TRACKING: ON
4838 01:15:52.465057 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4839 01:15:52.468320 [FAST_K] Save calibration result to emmc
4840 01:15:52.471832 dramc_set_vcore_voltage set vcore to 662500
4841 01:15:52.474673 Read voltage for 933, 3
4842 01:15:52.474755 Vio18 = 0
4843 01:15:52.478341 Vcore = 662500
4844 01:15:52.478422 Vdram = 0
4845 01:15:52.478487 Vddq = 0
4846 01:15:52.481427 Vmddr = 0
4847 01:15:52.484494 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4848 01:15:52.491133 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4849 01:15:52.491321 MEM_TYPE=3, freq_sel=17
4850 01:15:52.495034 sv_algorithm_assistance_LP4_1600
4851 01:15:52.501511 ============ PULL DRAM RESETB DOWN ============
4852 01:15:52.504598 ========== PULL DRAM RESETB DOWN end =========
4853 01:15:52.507599 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4854 01:15:52.511296 ===================================
4855 01:15:52.514336 LPDDR4 DRAM CONFIGURATION
4856 01:15:52.517980 ===================================
4857 01:15:52.520858 EX_ROW_EN[0] = 0x0
4858 01:15:52.521121 EX_ROW_EN[1] = 0x0
4859 01:15:52.524446 LP4Y_EN = 0x0
4860 01:15:52.524685 WORK_FSP = 0x0
4861 01:15:52.527446 WL = 0x3
4862 01:15:52.527682 RL = 0x3
4863 01:15:52.531079 BL = 0x2
4864 01:15:52.531371 RPST = 0x0
4865 01:15:52.534184 RD_PRE = 0x0
4866 01:15:52.534631 WR_PRE = 0x1
4867 01:15:52.537741 WR_PST = 0x0
4868 01:15:52.537956 DBI_WR = 0x0
4869 01:15:52.540502 DBI_RD = 0x0
4870 01:15:52.540583 OTF = 0x1
4871 01:15:52.544062 ===================================
4872 01:15:52.546815 ===================================
4873 01:15:52.550150 ANA top config
4874 01:15:52.553742 ===================================
4875 01:15:52.556976 DLL_ASYNC_EN = 0
4876 01:15:52.557057 ALL_SLAVE_EN = 1
4877 01:15:52.560523 NEW_RANK_MODE = 1
4878 01:15:52.563471 DLL_IDLE_MODE = 1
4879 01:15:52.566881 LP45_APHY_COMB_EN = 1
4880 01:15:52.569895 TX_ODT_DIS = 1
4881 01:15:52.569977 NEW_8X_MODE = 1
4882 01:15:52.573263 ===================================
4883 01:15:52.576608 ===================================
4884 01:15:52.579733 data_rate = 1866
4885 01:15:52.583386 CKR = 1
4886 01:15:52.586491 DQ_P2S_RATIO = 8
4887 01:15:52.590062 ===================================
4888 01:15:52.593463 CA_P2S_RATIO = 8
4889 01:15:52.596505 DQ_CA_OPEN = 0
4890 01:15:52.596586 DQ_SEMI_OPEN = 0
4891 01:15:52.600472 CA_SEMI_OPEN = 0
4892 01:15:52.603280 CA_FULL_RATE = 0
4893 01:15:52.606740 DQ_CKDIV4_EN = 1
4894 01:15:52.610363 CA_CKDIV4_EN = 1
4895 01:15:52.612899 CA_PREDIV_EN = 0
4896 01:15:52.613050 PH8_DLY = 0
4897 01:15:52.616718 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4898 01:15:52.619732 DQ_AAMCK_DIV = 4
4899 01:15:52.623162 CA_AAMCK_DIV = 4
4900 01:15:52.626104 CA_ADMCK_DIV = 4
4901 01:15:52.629747 DQ_TRACK_CA_EN = 0
4902 01:15:52.632761 CA_PICK = 933
4903 01:15:52.632883 CA_MCKIO = 933
4904 01:15:52.636462 MCKIO_SEMI = 0
4905 01:15:52.639955 PLL_FREQ = 3732
4906 01:15:52.642917 DQ_UI_PI_RATIO = 32
4907 01:15:52.645935 CA_UI_PI_RATIO = 0
4908 01:15:52.649644 ===================================
4909 01:15:52.652768 ===================================
4910 01:15:52.656028 memory_type:LPDDR4
4911 01:15:52.656164 GP_NUM : 10
4912 01:15:52.659557 SRAM_EN : 1
4913 01:15:52.659714 MD32_EN : 0
4914 01:15:52.662568 ===================================
4915 01:15:52.665736 [ANA_INIT] >>>>>>>>>>>>>>
4916 01:15:52.669406 <<<<<< [CONFIGURE PHASE]: ANA_TX
4917 01:15:52.672771 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4918 01:15:52.675740 ===================================
4919 01:15:52.679410 data_rate = 1866,PCW = 0X8f00
4920 01:15:52.682419 ===================================
4921 01:15:52.685585 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4922 01:15:52.691968 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4923 01:15:52.695429 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4924 01:15:52.702166 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4925 01:15:52.705451 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4926 01:15:52.709188 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4927 01:15:52.709717 [ANA_INIT] flow start
4928 01:15:52.711980 [ANA_INIT] PLL >>>>>>>>
4929 01:15:52.715795 [ANA_INIT] PLL <<<<<<<<
4930 01:15:52.719132 [ANA_INIT] MIDPI >>>>>>>>
4931 01:15:52.719654 [ANA_INIT] MIDPI <<<<<<<<
4932 01:15:52.722632 [ANA_INIT] DLL >>>>>>>>
4933 01:15:52.725239 [ANA_INIT] flow end
4934 01:15:52.728930 ============ LP4 DIFF to SE enter ============
4935 01:15:52.731943 ============ LP4 DIFF to SE exit ============
4936 01:15:52.735711 [ANA_INIT] <<<<<<<<<<<<<
4937 01:15:52.738759 [Flow] Enable top DCM control >>>>>
4938 01:15:52.741729 [Flow] Enable top DCM control <<<<<
4939 01:15:52.745111 Enable DLL master slave shuffle
4940 01:15:52.748203 ==============================================================
4941 01:15:52.751672 Gating Mode config
4942 01:15:52.758596 ==============================================================
4943 01:15:52.759100 Config description:
4944 01:15:52.768180 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4945 01:15:52.774821 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4946 01:15:52.781359 SELPH_MODE 0: By rank 1: By Phase
4947 01:15:52.784749 ==============================================================
4948 01:15:52.787597 GAT_TRACK_EN = 1
4949 01:15:52.791312 RX_GATING_MODE = 2
4950 01:15:52.794841 RX_GATING_TRACK_MODE = 2
4951 01:15:52.797595 SELPH_MODE = 1
4952 01:15:52.800627 PICG_EARLY_EN = 1
4953 01:15:52.804077 VALID_LAT_VALUE = 1
4954 01:15:52.807429 ==============================================================
4955 01:15:52.810690 Enter into Gating configuration >>>>
4956 01:15:52.813777 Exit from Gating configuration <<<<
4957 01:15:52.817184 Enter into DVFS_PRE_config >>>>>
4958 01:15:52.830103 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4959 01:15:52.833880 Exit from DVFS_PRE_config <<<<<
4960 01:15:52.837341 Enter into PICG configuration >>>>
4961 01:15:52.840430 Exit from PICG configuration <<<<
4962 01:15:52.840916 [RX_INPUT] configuration >>>>>
4963 01:15:52.843747 [RX_INPUT] configuration <<<<<
4964 01:15:52.850479 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4965 01:15:52.856456 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4966 01:15:52.860237 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4967 01:15:52.866757 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4968 01:15:52.873114 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4969 01:15:52.879548 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4970 01:15:52.883170 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4971 01:15:52.886138 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4972 01:15:52.892756 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4973 01:15:52.896260 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4974 01:15:52.899397 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4975 01:15:52.906241 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4976 01:15:52.909380 ===================================
4977 01:15:52.909910 LPDDR4 DRAM CONFIGURATION
4978 01:15:52.912709 ===================================
4979 01:15:52.916064 EX_ROW_EN[0] = 0x0
4980 01:15:52.919168 EX_ROW_EN[1] = 0x0
4981 01:15:52.919587 LP4Y_EN = 0x0
4982 01:15:52.922804 WORK_FSP = 0x0
4983 01:15:52.923347 WL = 0x3
4984 01:15:52.925741 RL = 0x3
4985 01:15:52.926156 BL = 0x2
4986 01:15:52.928951 RPST = 0x0
4987 01:15:52.929371 RD_PRE = 0x0
4988 01:15:52.932678 WR_PRE = 0x1
4989 01:15:52.933094 WR_PST = 0x0
4990 01:15:52.935490 DBI_WR = 0x0
4991 01:15:52.935941 DBI_RD = 0x0
4992 01:15:52.939288 OTF = 0x1
4993 01:15:52.942460 ===================================
4994 01:15:52.945346 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4995 01:15:52.949279 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4996 01:15:52.955210 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4997 01:15:52.958671 ===================================
4998 01:15:52.959095 LPDDR4 DRAM CONFIGURATION
4999 01:15:52.961920 ===================================
5000 01:15:52.964904 EX_ROW_EN[0] = 0x10
5001 01:15:52.968575 EX_ROW_EN[1] = 0x0
5002 01:15:52.968992 LP4Y_EN = 0x0
5003 01:15:52.971693 WORK_FSP = 0x0
5004 01:15:52.972217 WL = 0x3
5005 01:15:52.974831 RL = 0x3
5006 01:15:52.975247 BL = 0x2
5007 01:15:52.978285 RPST = 0x0
5008 01:15:52.978701 RD_PRE = 0x0
5009 01:15:52.981854 WR_PRE = 0x1
5010 01:15:52.982490 WR_PST = 0x0
5011 01:15:52.985181 DBI_WR = 0x0
5012 01:15:52.985600 DBI_RD = 0x0
5013 01:15:52.988296 OTF = 0x1
5014 01:15:52.991280 ===================================
5015 01:15:52.998372 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5016 01:15:53.001200 nWR fixed to 30
5017 01:15:53.004854 [ModeRegInit_LP4] CH0 RK0
5018 01:15:53.005275 [ModeRegInit_LP4] CH0 RK1
5019 01:15:53.008043 [ModeRegInit_LP4] CH1 RK0
5020 01:15:53.011534 [ModeRegInit_LP4] CH1 RK1
5021 01:15:53.011975 match AC timing 9
5022 01:15:53.018032 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5023 01:15:53.021121 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5024 01:15:53.023980 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5025 01:15:53.030606 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5026 01:15:53.034166 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5027 01:15:53.034590 ==
5028 01:15:53.037606 Dram Type= 6, Freq= 0, CH_0, rank 0
5029 01:15:53.040566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5030 01:15:53.040987 ==
5031 01:15:53.047405 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5032 01:15:53.054339 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5033 01:15:53.057331 [CA 0] Center 37 (7~68) winsize 62
5034 01:15:53.060667 [CA 1] Center 37 (7~68) winsize 62
5035 01:15:53.063767 [CA 2] Center 34 (4~64) winsize 61
5036 01:15:53.067226 [CA 3] Center 34 (3~65) winsize 63
5037 01:15:53.070581 [CA 4] Center 33 (2~64) winsize 63
5038 01:15:53.073779 [CA 5] Center 32 (2~63) winsize 62
5039 01:15:53.074190
5040 01:15:53.076842 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5041 01:15:53.077253
5042 01:15:53.080140 [CATrainingPosCal] consider 1 rank data
5043 01:15:53.083136 u2DelayCellTimex100 = 270/100 ps
5044 01:15:53.086731 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5045 01:15:53.090027 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5046 01:15:53.093511 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5047 01:15:53.100346 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5048 01:15:53.103356 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5049 01:15:53.106387 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5050 01:15:53.106809
5051 01:15:53.110067 CA PerBit enable=1, Macro0, CA PI delay=32
5052 01:15:53.110486
5053 01:15:53.113192 [CBTSetCACLKResult] CA Dly = 32
5054 01:15:53.113612 CS Dly: 5 (0~36)
5055 01:15:53.116111 ==
5056 01:15:53.119716 Dram Type= 6, Freq= 0, CH_0, rank 1
5057 01:15:53.122503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5058 01:15:53.122925 ==
5059 01:15:53.126062 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5060 01:15:53.132549 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5061 01:15:53.136364 [CA 0] Center 38 (8~68) winsize 61
5062 01:15:53.139947 [CA 1] Center 37 (7~68) winsize 62
5063 01:15:53.142990 [CA 2] Center 35 (5~65) winsize 61
5064 01:15:53.146744 [CA 3] Center 34 (4~65) winsize 62
5065 01:15:53.149732 [CA 4] Center 33 (3~64) winsize 62
5066 01:15:53.153191 [CA 5] Center 32 (2~63) winsize 62
5067 01:15:53.153610
5068 01:15:53.156431 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5069 01:15:53.156850
5070 01:15:53.159483 [CATrainingPosCal] consider 2 rank data
5071 01:15:53.162437 u2DelayCellTimex100 = 270/100 ps
5072 01:15:53.165876 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5073 01:15:53.172440 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5074 01:15:53.175562 CA2 delay=34 (5~64),Diff = 2 PI (12 cell)
5075 01:15:53.179035 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5076 01:15:53.182455 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5077 01:15:53.185541 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5078 01:15:53.185955
5079 01:15:53.188716 CA PerBit enable=1, Macro0, CA PI delay=32
5080 01:15:53.189129
5081 01:15:53.192099 [CBTSetCACLKResult] CA Dly = 32
5082 01:15:53.195373 CS Dly: 6 (0~39)
5083 01:15:53.195783
5084 01:15:53.198586 ----->DramcWriteLeveling(PI) begin...
5085 01:15:53.199005 ==
5086 01:15:53.202186 Dram Type= 6, Freq= 0, CH_0, rank 0
5087 01:15:53.205226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5088 01:15:53.205656 ==
5089 01:15:53.208839 Write leveling (Byte 0): 30 => 30
5090 01:15:53.211932 Write leveling (Byte 1): 29 => 29
5091 01:15:53.214956 DramcWriteLeveling(PI) end<-----
5092 01:15:53.215382
5093 01:15:53.215869 ==
5094 01:15:53.218391 Dram Type= 6, Freq= 0, CH_0, rank 0
5095 01:15:53.221856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5096 01:15:53.222401 ==
5097 01:15:53.224727 [Gating] SW mode calibration
5098 01:15:53.231364 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5099 01:15:53.238197 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5100 01:15:53.241399 0 14 0 | B1->B0 | 2323 3333 | 1 0 | (1 1) (0 0)
5101 01:15:53.247402 0 14 4 | B1->B0 | 3433 3434 | 1 1 | (0 0) (1 1)
5102 01:15:53.250919 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 01:15:53.253893 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 01:15:53.260577 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 01:15:53.264133 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 01:15:53.266811 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 01:15:53.274024 0 14 28 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 0)
5108 01:15:53.276947 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5109 01:15:53.280035 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5110 01:15:53.286698 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 01:15:53.290372 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 01:15:53.293665 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 01:15:53.300179 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 01:15:53.303371 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 01:15:53.306511 0 15 28 | B1->B0 | 2323 3838 | 0 0 | (0 0) (1 1)
5116 01:15:53.313138 1 0 0 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
5117 01:15:53.316219 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 01:15:53.320020 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 01:15:53.326484 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 01:15:53.329708 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 01:15:53.333258 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 01:15:53.339559 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 01:15:53.342619 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5124 01:15:53.345752 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5125 01:15:53.352535 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 01:15:53.355745 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 01:15:53.359312 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 01:15:53.365579 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 01:15:53.369274 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 01:15:53.372336 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 01:15:53.378812 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 01:15:53.382080 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 01:15:53.388648 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 01:15:53.391624 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 01:15:53.395325 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 01:15:53.402101 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 01:15:53.405039 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 01:15:53.408119 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5139 01:15:53.414820 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 01:15:53.417885 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5141 01:15:53.421519 Total UI for P1: 0, mck2ui 16
5142 01:15:53.424560 best dqsien dly found for B0: ( 1, 2, 30)
5143 01:15:53.427993 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5144 01:15:53.434892 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 01:15:53.435010 Total UI for P1: 0, mck2ui 16
5146 01:15:53.440871 best dqsien dly found for B1: ( 1, 3, 2)
5147 01:15:53.444360 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5148 01:15:53.447805 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5149 01:15:53.447910
5150 01:15:53.451183 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5151 01:15:53.454233 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5152 01:15:53.457808 [Gating] SW calibration Done
5153 01:15:53.457890 ==
5154 01:15:53.460934 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 01:15:53.464090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 01:15:53.464177 ==
5157 01:15:53.467678 RX Vref Scan: 0
5158 01:15:53.467760
5159 01:15:53.467823 RX Vref 0 -> 0, step: 1
5160 01:15:53.467911
5161 01:15:53.470741 RX Delay -80 -> 252, step: 8
5162 01:15:53.473833 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5163 01:15:53.480690 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5164 01:15:53.483645 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5165 01:15:53.487400 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5166 01:15:53.490554 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5167 01:15:53.493829 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5168 01:15:53.497136 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5169 01:15:53.503720 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5170 01:15:53.506609 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5171 01:15:53.510098 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5172 01:15:53.513169 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5173 01:15:53.520015 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5174 01:15:53.523028 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5175 01:15:53.526529 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5176 01:15:53.529698 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5177 01:15:53.532704 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5178 01:15:53.532786 ==
5179 01:15:53.536299 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 01:15:53.543131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 01:15:53.543212 ==
5182 01:15:53.543277 DQS Delay:
5183 01:15:53.543337 DQS0 = 0, DQS1 = 0
5184 01:15:53.546114 DQM Delay:
5185 01:15:53.546194 DQM0 = 100, DQM1 = 88
5186 01:15:53.549282 DQ Delay:
5187 01:15:53.552555 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5188 01:15:53.555920 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =111
5189 01:15:53.559287 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5190 01:15:53.562544 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5191 01:15:53.562626
5192 01:15:53.562690
5193 01:15:53.562749 ==
5194 01:15:53.565647 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 01:15:53.569004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 01:15:53.569088 ==
5197 01:15:53.569219
5198 01:15:53.569279
5199 01:15:53.572758 TX Vref Scan disable
5200 01:15:53.575803 == TX Byte 0 ==
5201 01:15:53.578813 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5202 01:15:53.582560 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5203 01:15:53.585573 == TX Byte 1 ==
5204 01:15:53.588806 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5205 01:15:53.591819 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5206 01:15:53.591939 ==
5207 01:15:53.595364 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 01:15:53.601886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 01:15:53.601968 ==
5210 01:15:53.602033
5211 01:15:53.602092
5212 01:15:53.602149 TX Vref Scan disable
5213 01:15:53.605975 == TX Byte 0 ==
5214 01:15:53.609283 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5215 01:15:53.615612 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5216 01:15:53.615694 == TX Byte 1 ==
5217 01:15:53.619276 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5218 01:15:53.625871 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5219 01:15:53.625953
5220 01:15:53.626018 [DATLAT]
5221 01:15:53.626078 Freq=933, CH0 RK0
5222 01:15:53.626136
5223 01:15:53.628889 DATLAT Default: 0xd
5224 01:15:53.632431 0, 0xFFFF, sum = 0
5225 01:15:53.632513 1, 0xFFFF, sum = 0
5226 01:15:53.635547 2, 0xFFFF, sum = 0
5227 01:15:53.635629 3, 0xFFFF, sum = 0
5228 01:15:53.638630 4, 0xFFFF, sum = 0
5229 01:15:53.638713 5, 0xFFFF, sum = 0
5230 01:15:53.642354 6, 0xFFFF, sum = 0
5231 01:15:53.642437 7, 0xFFFF, sum = 0
5232 01:15:53.645500 8, 0xFFFF, sum = 0
5233 01:15:53.645582 9, 0xFFFF, sum = 0
5234 01:15:53.648453 10, 0x0, sum = 1
5235 01:15:53.648536 11, 0x0, sum = 2
5236 01:15:53.652015 12, 0x0, sum = 3
5237 01:15:53.652097 13, 0x0, sum = 4
5238 01:15:53.655390 best_step = 11
5239 01:15:53.655470
5240 01:15:53.655534 ==
5241 01:15:53.658268 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 01:15:53.662004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 01:15:53.662085 ==
5244 01:15:53.662149 RX Vref Scan: 1
5245 01:15:53.665266
5246 01:15:53.665346 RX Vref 0 -> 0, step: 1
5247 01:15:53.665411
5248 01:15:53.668402 RX Delay -61 -> 252, step: 4
5249 01:15:53.668484
5250 01:15:53.671625 Set Vref, RX VrefLevel [Byte0]: 57
5251 01:15:53.675017 [Byte1]: 59
5252 01:15:53.678896
5253 01:15:53.679408 Final RX Vref Byte 0 = 57 to rank0
5254 01:15:53.682101 Final RX Vref Byte 1 = 59 to rank0
5255 01:15:53.685230 Final RX Vref Byte 0 = 57 to rank1
5256 01:15:53.688863 Final RX Vref Byte 1 = 59 to rank1==
5257 01:15:53.691920 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 01:15:53.698372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 01:15:53.698937 ==
5260 01:15:53.699335 DQS Delay:
5261 01:15:53.701553 DQS0 = 0, DQS1 = 0
5262 01:15:53.702017 DQM Delay:
5263 01:15:53.702357 DQM0 = 99, DQM1 = 88
5264 01:15:53.705226 DQ Delay:
5265 01:15:53.708400 DQ0 =100, DQ1 =100, DQ2 =94, DQ3 =94
5266 01:15:53.711871 DQ4 =100, DQ5 =90, DQ6 =110, DQ7 =104
5267 01:15:53.714976 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =84
5268 01:15:53.718350 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =94
5269 01:15:53.718769
5270 01:15:53.719100
5271 01:15:53.724749 [DQSOSCAuto] RK0, (LSB)MR18= 0x1712, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
5272 01:15:53.727984 CH0 RK0: MR19=505, MR18=1712
5273 01:15:53.734240 CH0_RK0: MR19=0x505, MR18=0x1712, DQSOSC=414, MR23=63, INC=63, DEC=42
5274 01:15:53.734690
5275 01:15:53.737916 ----->DramcWriteLeveling(PI) begin...
5276 01:15:53.738339 ==
5277 01:15:53.741023 Dram Type= 6, Freq= 0, CH_0, rank 1
5278 01:15:53.744826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 01:15:53.747920 ==
5280 01:15:53.748349 Write leveling (Byte 0): 33 => 33
5281 01:15:53.751028 Write leveling (Byte 1): 26 => 26
5282 01:15:53.754670 DramcWriteLeveling(PI) end<-----
5283 01:15:53.755197
5284 01:15:53.755545 ==
5285 01:15:53.757643 Dram Type= 6, Freq= 0, CH_0, rank 1
5286 01:15:53.764034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 01:15:53.764458 ==
5288 01:15:53.767329 [Gating] SW mode calibration
5289 01:15:53.774232 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5290 01:15:53.777432 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5291 01:15:53.783622 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
5292 01:15:53.787276 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 01:15:53.790239 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 01:15:53.797259 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 01:15:53.800746 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 01:15:53.803740 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 01:15:53.810447 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5298 01:15:53.813265 0 14 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
5299 01:15:53.816510 0 15 0 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
5300 01:15:53.823212 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 01:15:53.826804 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 01:15:53.829746 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 01:15:53.836490 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 01:15:53.839736 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 01:15:53.843201 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 01:15:53.849640 0 15 28 | B1->B0 | 2626 3c3c | 0 1 | (0 0) (0 0)
5307 01:15:53.852789 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5308 01:15:53.856196 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 01:15:53.862630 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 01:15:53.865729 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 01:15:53.869321 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 01:15:53.875597 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 01:15:53.879085 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5314 01:15:53.882104 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5315 01:15:53.888929 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 01:15:53.891950 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 01:15:53.895677 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 01:15:53.902359 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 01:15:53.905487 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 01:15:53.909052 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 01:15:53.915855 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 01:15:53.918580 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 01:15:53.921761 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 01:15:53.928178 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 01:15:53.932135 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 01:15:53.938553 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 01:15:53.941504 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 01:15:53.944598 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 01:15:53.951217 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5330 01:15:53.954512 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5331 01:15:53.957577 Total UI for P1: 0, mck2ui 16
5332 01:15:53.961612 best dqsien dly found for B0: ( 1, 2, 24)
5333 01:15:53.964640 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5334 01:15:53.970701 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 01:15:53.971120 Total UI for P1: 0, mck2ui 16
5336 01:15:53.974321 best dqsien dly found for B1: ( 1, 3, 2)
5337 01:15:53.980829 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5338 01:15:53.984331 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5339 01:15:53.984747
5340 01:15:53.987627 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5341 01:15:53.990762 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5342 01:15:53.993857 [Gating] SW calibration Done
5343 01:15:53.994367 ==
5344 01:15:53.997250 Dram Type= 6, Freq= 0, CH_0, rank 1
5345 01:15:54.000977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5346 01:15:54.001394 ==
5347 01:15:54.004160 RX Vref Scan: 0
5348 01:15:54.004573
5349 01:15:54.004903 RX Vref 0 -> 0, step: 1
5350 01:15:54.005211
5351 01:15:54.007333 RX Delay -80 -> 252, step: 8
5352 01:15:54.010656 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5353 01:15:54.016866 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5354 01:15:54.020715 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5355 01:15:54.023638 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5356 01:15:54.026618 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5357 01:15:54.030249 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5358 01:15:54.033396 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5359 01:15:54.040235 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5360 01:15:54.043182 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5361 01:15:54.046522 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5362 01:15:54.049865 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5363 01:15:54.053103 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5364 01:15:54.057112 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5365 01:15:54.062988 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5366 01:15:54.066393 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5367 01:15:54.069967 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5368 01:15:54.070388 ==
5369 01:15:54.073229 Dram Type= 6, Freq= 0, CH_0, rank 1
5370 01:15:54.076529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5371 01:15:54.076950 ==
5372 01:15:54.080155 DQS Delay:
5373 01:15:54.080602 DQS0 = 0, DQS1 = 0
5374 01:15:54.083178 DQM Delay:
5375 01:15:54.083595 DQM0 = 97, DQM1 = 91
5376 01:15:54.083972 DQ Delay:
5377 01:15:54.086311 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5378 01:15:54.089494 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =107
5379 01:15:54.092896 DQ8 =87, DQ9 =79, DQ10 =91, DQ11 =83
5380 01:15:54.096390 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =99
5381 01:15:54.099334
5382 01:15:54.099748
5383 01:15:54.100126 ==
5384 01:15:54.102442 Dram Type= 6, Freq= 0, CH_0, rank 1
5385 01:15:54.106052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5386 01:15:54.106471 ==
5387 01:15:54.106803
5388 01:15:54.107115
5389 01:15:54.109218 TX Vref Scan disable
5390 01:15:54.109634 == TX Byte 0 ==
5391 01:15:54.115950 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5392 01:15:54.119019 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5393 01:15:54.119449 == TX Byte 1 ==
5394 01:15:54.125655 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5395 01:15:54.129075 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5396 01:15:54.129557 ==
5397 01:15:54.132362 Dram Type= 6, Freq= 0, CH_0, rank 1
5398 01:15:54.135276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5399 01:15:54.135695 ==
5400 01:15:54.136066
5401 01:15:54.138366
5402 01:15:54.138783 TX Vref Scan disable
5403 01:15:54.142023 == TX Byte 0 ==
5404 01:15:54.145495 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5405 01:15:54.151869 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5406 01:15:54.152319 == TX Byte 1 ==
5407 01:15:54.155102 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5408 01:15:54.162076 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5409 01:15:54.162585
5410 01:15:54.162922 [DATLAT]
5411 01:15:54.163234 Freq=933, CH0 RK1
5412 01:15:54.163536
5413 01:15:54.164854 DATLAT Default: 0xb
5414 01:15:54.165272 0, 0xFFFF, sum = 0
5415 01:15:54.168462 1, 0xFFFF, sum = 0
5416 01:15:54.171619 2, 0xFFFF, sum = 0
5417 01:15:54.172199 3, 0xFFFF, sum = 0
5418 01:15:54.175112 4, 0xFFFF, sum = 0
5419 01:15:54.175533 5, 0xFFFF, sum = 0
5420 01:15:54.177981 6, 0xFFFF, sum = 0
5421 01:15:54.178404 7, 0xFFFF, sum = 0
5422 01:15:54.181271 8, 0xFFFF, sum = 0
5423 01:15:54.181709 9, 0xFFFF, sum = 0
5424 01:15:54.184792 10, 0x0, sum = 1
5425 01:15:54.185215 11, 0x0, sum = 2
5426 01:15:54.187839 12, 0x0, sum = 3
5427 01:15:54.188362 13, 0x0, sum = 4
5428 01:15:54.191400 best_step = 11
5429 01:15:54.191812
5430 01:15:54.192195 ==
5431 01:15:54.194735 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 01:15:54.197922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 01:15:54.198363 ==
5434 01:15:54.198708 RX Vref Scan: 0
5435 01:15:54.200991
5436 01:15:54.201407 RX Vref 0 -> 0, step: 1
5437 01:15:54.201742
5438 01:15:54.204477 RX Delay -53 -> 252, step: 4
5439 01:15:54.211122 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5440 01:15:54.214322 iDelay=199, Bit 1, Center 100 (11 ~ 190) 180
5441 01:15:54.217864 iDelay=199, Bit 2, Center 94 (7 ~ 182) 176
5442 01:15:54.220793 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5443 01:15:54.224508 iDelay=199, Bit 4, Center 100 (11 ~ 190) 180
5444 01:15:54.227504 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5445 01:15:54.234343 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5446 01:15:54.237424 iDelay=199, Bit 7, Center 104 (15 ~ 194) 180
5447 01:15:54.240450 iDelay=199, Bit 8, Center 80 (-5 ~ 166) 172
5448 01:15:54.244152 iDelay=199, Bit 9, Center 76 (-9 ~ 162) 172
5449 01:15:54.247443 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5450 01:15:54.253796 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5451 01:15:54.257465 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5452 01:15:54.260481 iDelay=199, Bit 13, Center 96 (7 ~ 186) 180
5453 01:15:54.263745 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5454 01:15:54.266748 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5455 01:15:54.270186 ==
5456 01:15:54.270601 Dram Type= 6, Freq= 0, CH_0, rank 1
5457 01:15:54.276855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5458 01:15:54.277297 ==
5459 01:15:54.277627 DQS Delay:
5460 01:15:54.279659 DQS0 = 0, DQS1 = 0
5461 01:15:54.280221 DQM Delay:
5462 01:15:54.283357 DQM0 = 97, DQM1 = 89
5463 01:15:54.283925 DQ Delay:
5464 01:15:54.286490 DQ0 =96, DQ1 =100, DQ2 =94, DQ3 =94
5465 01:15:54.289996 DQ4 =100, DQ5 =86, DQ6 =106, DQ7 =104
5466 01:15:54.292790 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =84
5467 01:15:54.296639 DQ12 =94, DQ13 =96, DQ14 =98, DQ15 =96
5468 01:15:54.297202
5469 01:15:54.297686
5470 01:15:54.302820 [DQSOSCAuto] RK1, (LSB)MR18= 0x1210, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5471 01:15:54.306357 CH0 RK1: MR19=505, MR18=1210
5472 01:15:54.312950 CH0_RK1: MR19=0x505, MR18=0x1210, DQSOSC=416, MR23=63, INC=62, DEC=41
5473 01:15:54.316177 [RxdqsGatingPostProcess] freq 933
5474 01:15:54.322587 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5475 01:15:54.326123 best DQS0 dly(2T, 0.5T) = (0, 10)
5476 01:15:54.329108 best DQS1 dly(2T, 0.5T) = (0, 11)
5477 01:15:54.332331 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5478 01:15:54.335941 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5479 01:15:54.338931 best DQS0 dly(2T, 0.5T) = (0, 10)
5480 01:15:54.339433 best DQS1 dly(2T, 0.5T) = (0, 11)
5481 01:15:54.342701 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5482 01:15:54.345832 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5483 01:15:54.348740 Pre-setting of DQS Precalculation
5484 01:15:54.355372 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5485 01:15:54.355787 ==
5486 01:15:54.358996 Dram Type= 6, Freq= 0, CH_1, rank 0
5487 01:15:54.362190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5488 01:15:54.362604 ==
5489 01:15:54.368860 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5490 01:15:54.375676 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5491 01:15:54.378729 [CA 0] Center 36 (6~67) winsize 62
5492 01:15:54.381626 [CA 1] Center 36 (6~67) winsize 62
5493 01:15:54.385405 [CA 2] Center 34 (4~65) winsize 62
5494 01:15:54.388874 [CA 3] Center 34 (4~65) winsize 62
5495 01:15:54.391969 [CA 4] Center 34 (4~65) winsize 62
5496 01:15:54.395333 [CA 5] Center 33 (3~64) winsize 62
5497 01:15:54.395794
5498 01:15:54.398152 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5499 01:15:54.398565
5500 01:15:54.401886 [CATrainingPosCal] consider 1 rank data
5501 01:15:54.404506 u2DelayCellTimex100 = 270/100 ps
5502 01:15:54.408273 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5503 01:15:54.411156 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5504 01:15:54.414374 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5505 01:15:54.417695 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5506 01:15:54.421245 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5507 01:15:54.427230 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5508 01:15:54.427332
5509 01:15:54.430784 CA PerBit enable=1, Macro0, CA PI delay=33
5510 01:15:54.430855
5511 01:15:54.434251 [CBTSetCACLKResult] CA Dly = 33
5512 01:15:54.434360 CS Dly: 5 (0~36)
5513 01:15:54.434452 ==
5514 01:15:54.437295 Dram Type= 6, Freq= 0, CH_1, rank 1
5515 01:15:54.440710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 01:15:54.444074 ==
5517 01:15:54.446972 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5518 01:15:54.453730 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5519 01:15:54.457333 [CA 0] Center 36 (6~66) winsize 61
5520 01:15:54.460417 [CA 1] Center 36 (6~67) winsize 62
5521 01:15:54.463370 [CA 2] Center 34 (4~64) winsize 61
5522 01:15:54.467042 [CA 3] Center 33 (3~64) winsize 62
5523 01:15:54.470210 [CA 4] Center 34 (4~64) winsize 61
5524 01:15:54.473664 [CA 5] Center 33 (3~64) winsize 62
5525 01:15:54.473774
5526 01:15:54.476953 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5527 01:15:54.477100
5528 01:15:54.480108 [CATrainingPosCal] consider 2 rank data
5529 01:15:54.483331 u2DelayCellTimex100 = 270/100 ps
5530 01:15:54.486675 CA0 delay=36 (6~66),Diff = 3 PI (18 cell)
5531 01:15:54.490149 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5532 01:15:54.496744 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5533 01:15:54.500026 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5534 01:15:54.503399 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5535 01:15:54.506346 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5536 01:15:54.506465
5537 01:15:54.509377 CA PerBit enable=1, Macro0, CA PI delay=33
5538 01:15:54.509504
5539 01:15:54.513153 [CBTSetCACLKResult] CA Dly = 33
5540 01:15:54.513272 CS Dly: 6 (0~38)
5541 01:15:54.516290
5542 01:15:54.520046 ----->DramcWriteLeveling(PI) begin...
5543 01:15:54.520465 ==
5544 01:15:54.523623 Dram Type= 6, Freq= 0, CH_1, rank 0
5545 01:15:54.526403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5546 01:15:54.526933 ==
5547 01:15:54.529798 Write leveling (Byte 0): 25 => 25
5548 01:15:54.532833 Write leveling (Byte 1): 25 => 25
5549 01:15:54.536591 DramcWriteLeveling(PI) end<-----
5550 01:15:54.537003
5551 01:15:54.537329 ==
5552 01:15:54.539510 Dram Type= 6, Freq= 0, CH_1, rank 0
5553 01:15:54.543067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 01:15:54.543663 ==
5555 01:15:54.546107 [Gating] SW mode calibration
5556 01:15:54.553013 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5557 01:15:54.559464 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5558 01:15:54.562309 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5559 01:15:54.566170 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 01:15:54.572841 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 01:15:54.575838 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 01:15:54.579181 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 01:15:54.585879 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 01:15:54.589358 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
5565 01:15:54.592511 0 14 28 | B1->B0 | 2e2e 2a2a | 0 0 | (1 0) (0 0)
5566 01:15:54.598897 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 01:15:54.602122 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 01:15:54.605617 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 01:15:54.612335 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 01:15:54.615090 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 01:15:54.618571 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 01:15:54.624815 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5573 01:15:54.628472 0 15 28 | B1->B0 | 3b3b 3d3d | 0 1 | (0 0) (0 0)
5574 01:15:54.631361 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 01:15:54.637877 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 01:15:54.641099 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 01:15:54.644804 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 01:15:54.651578 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 01:15:54.654526 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 01:15:54.657683 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5581 01:15:54.664576 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5582 01:15:54.667748 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5583 01:15:54.670953 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 01:15:54.677874 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 01:15:54.680829 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 01:15:54.684354 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 01:15:54.690861 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 01:15:54.694286 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 01:15:54.700720 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 01:15:54.703781 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 01:15:54.707201 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 01:15:54.713949 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 01:15:54.717084 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 01:15:54.720317 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 01:15:54.726932 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 01:15:54.730044 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 01:15:54.733882 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5598 01:15:54.740441 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 01:15:54.740967 Total UI for P1: 0, mck2ui 16
5600 01:15:54.746367 best dqsien dly found for B0: ( 1, 2, 28)
5601 01:15:54.746777 Total UI for P1: 0, mck2ui 16
5602 01:15:54.749708 best dqsien dly found for B1: ( 1, 2, 28)
5603 01:15:54.756562 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5604 01:15:54.759531 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5605 01:15:54.760033
5606 01:15:54.763184 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5607 01:15:54.766435 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5608 01:15:54.769617 [Gating] SW calibration Done
5609 01:15:54.770209 ==
5610 01:15:54.772767 Dram Type= 6, Freq= 0, CH_1, rank 0
5611 01:15:54.776381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5612 01:15:54.776861 ==
5613 01:15:54.779466 RX Vref Scan: 0
5614 01:15:54.780061
5615 01:15:54.780467 RX Vref 0 -> 0, step: 1
5616 01:15:54.780786
5617 01:15:54.782967 RX Delay -80 -> 252, step: 8
5618 01:15:54.786110 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5619 01:15:54.792328 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5620 01:15:54.795729 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5621 01:15:54.799321 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5622 01:15:54.802511 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5623 01:15:54.805509 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5624 01:15:54.812133 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5625 01:15:54.815844 iDelay=208, Bit 7, Center 91 (0 ~ 183) 184
5626 01:15:54.818804 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5627 01:15:54.822290 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5628 01:15:54.825475 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5629 01:15:54.828521 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5630 01:15:54.835504 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5631 01:15:54.838750 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5632 01:15:54.841621 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5633 01:15:54.845209 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5634 01:15:54.845623 ==
5635 01:15:54.848662 Dram Type= 6, Freq= 0, CH_1, rank 0
5636 01:15:54.854931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5637 01:15:54.855346 ==
5638 01:15:54.855706 DQS Delay:
5639 01:15:54.857955 DQS0 = 0, DQS1 = 0
5640 01:15:54.858402 DQM Delay:
5641 01:15:54.858942 DQM0 = 100, DQM1 = 95
5642 01:15:54.861588 DQ Delay:
5643 01:15:54.864673 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =103
5644 01:15:54.867673 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =91
5645 01:15:54.871502 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5646 01:15:54.874478 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5647 01:15:54.874891
5648 01:15:54.875254
5649 01:15:54.875594 ==
5650 01:15:54.877994 Dram Type= 6, Freq= 0, CH_1, rank 0
5651 01:15:54.881022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5652 01:15:54.881447 ==
5653 01:15:54.884665
5654 01:15:54.885087
5655 01:15:54.885421 TX Vref Scan disable
5656 01:15:54.887956 == TX Byte 0 ==
5657 01:15:54.890862 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5658 01:15:54.894180 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5659 01:15:54.897631 == TX Byte 1 ==
5660 01:15:54.901086 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5661 01:15:54.904171 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5662 01:15:54.904593 ==
5663 01:15:54.907614 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 01:15:54.914368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 01:15:54.914757 ==
5666 01:15:54.915082
5667 01:15:54.915385
5668 01:15:54.917443 TX Vref Scan disable
5669 01:15:54.917854 == TX Byte 0 ==
5670 01:15:54.924044 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5671 01:15:54.927215 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5672 01:15:54.927630 == TX Byte 1 ==
5673 01:15:54.933755 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5674 01:15:54.937319 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5675 01:15:54.937735
5676 01:15:54.938066 [DATLAT]
5677 01:15:54.940486 Freq=933, CH1 RK0
5678 01:15:54.940902
5679 01:15:54.941229 DATLAT Default: 0xd
5680 01:15:54.943988 0, 0xFFFF, sum = 0
5681 01:15:54.944560 1, 0xFFFF, sum = 0
5682 01:15:54.947161 2, 0xFFFF, sum = 0
5683 01:15:54.947690 3, 0xFFFF, sum = 0
5684 01:15:54.950125 4, 0xFFFF, sum = 0
5685 01:15:54.950544 5, 0xFFFF, sum = 0
5686 01:15:54.953911 6, 0xFFFF, sum = 0
5687 01:15:54.954431 7, 0xFFFF, sum = 0
5688 01:15:54.957303 8, 0xFFFF, sum = 0
5689 01:15:54.960267 9, 0xFFFF, sum = 0
5690 01:15:54.960686 10, 0x0, sum = 1
5691 01:15:54.961027 11, 0x0, sum = 2
5692 01:15:54.963672 12, 0x0, sum = 3
5693 01:15:54.964196 13, 0x0, sum = 4
5694 01:15:54.966984 best_step = 11
5695 01:15:54.967397
5696 01:15:54.967725 ==
5697 01:15:54.970080 Dram Type= 6, Freq= 0, CH_1, rank 0
5698 01:15:54.973723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5699 01:15:54.974156 ==
5700 01:15:54.976712 RX Vref Scan: 1
5701 01:15:54.977127
5702 01:15:54.977461 RX Vref 0 -> 0, step: 1
5703 01:15:54.980239
5704 01:15:54.980677 RX Delay -53 -> 252, step: 4
5705 01:15:54.981008
5706 01:15:54.983173 Set Vref, RX VrefLevel [Byte0]: 50
5707 01:15:54.986814 [Byte1]: 54
5708 01:15:54.990876
5709 01:15:54.991386 Final RX Vref Byte 0 = 50 to rank0
5710 01:15:54.994332 Final RX Vref Byte 1 = 54 to rank0
5711 01:15:54.998240 Final RX Vref Byte 0 = 50 to rank1
5712 01:15:55.000800 Final RX Vref Byte 1 = 54 to rank1==
5713 01:15:55.004251 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 01:15:55.010942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 01:15:55.011369 ==
5716 01:15:55.011703 DQS Delay:
5717 01:15:55.014178 DQS0 = 0, DQS1 = 0
5718 01:15:55.014704 DQM Delay:
5719 01:15:55.015053 DQM0 = 99, DQM1 = 95
5720 01:15:55.017571 DQ Delay:
5721 01:15:55.020778 DQ0 =104, DQ1 =94, DQ2 =88, DQ3 =98
5722 01:15:55.024070 DQ4 =96, DQ5 =108, DQ6 =110, DQ7 =94
5723 01:15:55.027528 DQ8 =82, DQ9 =86, DQ10 =94, DQ11 =88
5724 01:15:55.030559 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =104
5725 01:15:55.030974
5726 01:15:55.031301
5727 01:15:55.037157 [DQSOSCAuto] RK0, (LSB)MR18= 0x717, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 419 ps
5728 01:15:55.040185 CH1 RK0: MR19=505, MR18=717
5729 01:15:55.047223 CH1_RK0: MR19=0x505, MR18=0x717, DQSOSC=414, MR23=63, INC=63, DEC=42
5730 01:15:55.047740
5731 01:15:55.050177 ----->DramcWriteLeveling(PI) begin...
5732 01:15:55.050720 ==
5733 01:15:55.054018 Dram Type= 6, Freq= 0, CH_1, rank 1
5734 01:15:55.056967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 01:15:55.057490 ==
5736 01:15:55.060384 Write leveling (Byte 0): 25 => 25
5737 01:15:55.063372 Write leveling (Byte 1): 31 => 31
5738 01:15:55.066422 DramcWriteLeveling(PI) end<-----
5739 01:15:55.066836
5740 01:15:55.067166 ==
5741 01:15:55.069985 Dram Type= 6, Freq= 0, CH_1, rank 1
5742 01:15:55.076462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 01:15:55.076546 ==
5744 01:15:55.076610 [Gating] SW mode calibration
5745 01:15:55.086194 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5746 01:15:55.089198 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5747 01:15:55.095990 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 01:15:55.099393 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 01:15:55.102413 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 01:15:55.109159 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 01:15:55.112295 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 01:15:55.115347 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 01:15:55.121901 0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)
5754 01:15:55.125251 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
5755 01:15:55.128521 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 01:15:55.135202 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 01:15:55.138580 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 01:15:55.141702 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 01:15:55.148487 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 01:15:55.151489 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 01:15:55.155316 0 15 24 | B1->B0 | 2a2a 3636 | 0 0 | (0 0) (0 0)
5762 01:15:55.161969 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5763 01:15:55.164749 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 01:15:55.168137 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 01:15:55.174957 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 01:15:55.178496 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 01:15:55.181362 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 01:15:55.187839 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 01:15:55.191304 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 01:15:55.194729 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5771 01:15:55.200974 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5772 01:15:55.204564 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 01:15:55.207874 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 01:15:55.214560 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 01:15:55.217684 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 01:15:55.220843 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 01:15:55.227568 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 01:15:55.230500 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 01:15:55.233889 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 01:15:55.240664 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 01:15:55.243748 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 01:15:55.246688 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 01:15:55.253291 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 01:15:55.256924 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 01:15:55.260456 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5786 01:15:55.267043 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5787 01:15:55.270298 Total UI for P1: 0, mck2ui 16
5788 01:15:55.273505 best dqsien dly found for B0: ( 1, 2, 24)
5789 01:15:55.276922 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5790 01:15:55.279870 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 01:15:55.283668 Total UI for P1: 0, mck2ui 16
5792 01:15:55.286630 best dqsien dly found for B1: ( 1, 2, 30)
5793 01:15:55.290076 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5794 01:15:55.293163 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5795 01:15:55.296999
5796 01:15:55.300016 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5797 01:15:55.303028 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5798 01:15:55.306533 [Gating] SW calibration Done
5799 01:15:55.306965 ==
5800 01:15:55.309729 Dram Type= 6, Freq= 0, CH_1, rank 1
5801 01:15:55.313297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5802 01:15:55.313714 ==
5803 01:15:55.316164 RX Vref Scan: 0
5804 01:15:55.316578
5805 01:15:55.316908 RX Vref 0 -> 0, step: 1
5806 01:15:55.317215
5807 01:15:55.320027 RX Delay -80 -> 252, step: 8
5808 01:15:55.322867 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5809 01:15:55.329877 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5810 01:15:55.332883 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5811 01:15:55.336289 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5812 01:15:55.339410 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5813 01:15:55.342747 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5814 01:15:55.345882 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5815 01:15:55.349363 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5816 01:15:55.355826 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5817 01:15:55.359315 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5818 01:15:55.362354 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5819 01:15:55.366208 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5820 01:15:55.369075 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5821 01:15:55.375392 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5822 01:15:55.378948 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5823 01:15:55.382308 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5824 01:15:55.382744 ==
5825 01:15:55.385448 Dram Type= 6, Freq= 0, CH_1, rank 1
5826 01:15:55.388626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5827 01:15:55.389068 ==
5828 01:15:55.391781 DQS Delay:
5829 01:15:55.392248 DQS0 = 0, DQS1 = 0
5830 01:15:55.395205 DQM Delay:
5831 01:15:55.395624 DQM0 = 97, DQM1 = 93
5832 01:15:55.396004 DQ Delay:
5833 01:15:55.398718 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5834 01:15:55.401838 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5835 01:15:55.405100 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5836 01:15:55.408588 DQ12 =103, DQ13 =99, DQ14 =95, DQ15 =99
5837 01:15:55.411623
5838 01:15:55.412103
5839 01:15:55.412440 ==
5840 01:15:55.415011 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 01:15:55.418105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 01:15:55.418526 ==
5843 01:15:55.418857
5844 01:15:55.419167
5845 01:15:55.421827 TX Vref Scan disable
5846 01:15:55.422247 == TX Byte 0 ==
5847 01:15:55.427767 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5848 01:15:55.431511 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5849 01:15:55.431976 == TX Byte 1 ==
5850 01:15:55.438266 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5851 01:15:55.441349 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5852 01:15:55.441769 ==
5853 01:15:55.444324 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 01:15:55.447761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 01:15:55.448269 ==
5856 01:15:55.448615
5857 01:15:55.450834
5858 01:15:55.451280 TX Vref Scan disable
5859 01:15:55.454440 == TX Byte 0 ==
5860 01:15:55.457805 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5861 01:15:55.464394 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5862 01:15:55.464817 == TX Byte 1 ==
5863 01:15:55.467418 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5864 01:15:55.473931 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5865 01:15:55.474362
5866 01:15:55.474747 [DATLAT]
5867 01:15:55.475235 Freq=933, CH1 RK1
5868 01:15:55.475561
5869 01:15:55.477672 DATLAT Default: 0xb
5870 01:15:55.478091 0, 0xFFFF, sum = 0
5871 01:15:55.480626 1, 0xFFFF, sum = 0
5872 01:15:55.483969 2, 0xFFFF, sum = 0
5873 01:15:55.484440 3, 0xFFFF, sum = 0
5874 01:15:55.487162 4, 0xFFFF, sum = 0
5875 01:15:55.487685 5, 0xFFFF, sum = 0
5876 01:15:55.490590 6, 0xFFFF, sum = 0
5877 01:15:55.491096 7, 0xFFFF, sum = 0
5878 01:15:55.493867 8, 0xFFFF, sum = 0
5879 01:15:55.494483 9, 0xFFFF, sum = 0
5880 01:15:55.496685 10, 0x0, sum = 1
5881 01:15:55.497256 11, 0x0, sum = 2
5882 01:15:55.500232 12, 0x0, sum = 3
5883 01:15:55.500658 13, 0x0, sum = 4
5884 01:15:55.503331 best_step = 11
5885 01:15:55.503747
5886 01:15:55.504151 ==
5887 01:15:55.506858 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 01:15:55.510083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 01:15:55.510506 ==
5890 01:15:55.510843 RX Vref Scan: 0
5891 01:15:55.513285
5892 01:15:55.513703 RX Vref 0 -> 0, step: 1
5893 01:15:55.514156
5894 01:15:55.516662 RX Delay -53 -> 252, step: 4
5895 01:15:55.523122 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5896 01:15:55.526760 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5897 01:15:55.530365 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5898 01:15:55.533586 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5899 01:15:55.536591 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5900 01:15:55.543305 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5901 01:15:55.546193 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5902 01:15:55.549812 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5903 01:15:55.553389 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5904 01:15:55.556346 iDelay=199, Bit 9, Center 84 (-9 ~ 178) 188
5905 01:15:55.559937 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5906 01:15:55.566547 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5907 01:15:55.569489 iDelay=199, Bit 12, Center 100 (7 ~ 194) 188
5908 01:15:55.572584 iDelay=199, Bit 13, Center 100 (7 ~ 194) 188
5909 01:15:55.576676 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5910 01:15:55.579602 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5911 01:15:55.583202 ==
5912 01:15:55.586137 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 01:15:55.589161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 01:15:55.589584 ==
5915 01:15:55.589920 DQS Delay:
5916 01:15:55.592625 DQS0 = 0, DQS1 = 0
5917 01:15:55.593203 DQM Delay:
5918 01:15:55.595950 DQM0 = 96, DQM1 = 92
5919 01:15:55.596372 DQ Delay:
5920 01:15:55.599443 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =94
5921 01:15:55.602798 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =92
5922 01:15:55.605782 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =86
5923 01:15:55.609297 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =102
5924 01:15:55.609718
5925 01:15:55.610048
5926 01:15:55.619075 [DQSOSCAuto] RK1, (LSB)MR18= 0x61d, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 420 ps
5927 01:15:55.619499 CH1 RK1: MR19=505, MR18=61D
5928 01:15:55.625880 CH1_RK1: MR19=0x505, MR18=0x61D, DQSOSC=412, MR23=63, INC=63, DEC=42
5929 01:15:55.629059 [RxdqsGatingPostProcess] freq 933
5930 01:15:55.635391 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5931 01:15:55.638724 best DQS0 dly(2T, 0.5T) = (0, 10)
5932 01:15:55.641991 best DQS1 dly(2T, 0.5T) = (0, 10)
5933 01:15:55.645382 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5934 01:15:55.648785 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5935 01:15:55.649207 best DQS0 dly(2T, 0.5T) = (0, 10)
5936 01:15:55.651978 best DQS1 dly(2T, 0.5T) = (0, 10)
5937 01:15:55.655398 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5938 01:15:55.658692 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5939 01:15:55.662072 Pre-setting of DQS Precalculation
5940 01:15:55.668311 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5941 01:15:55.674859 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5942 01:15:55.681339 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5943 01:15:55.681764
5944 01:15:55.682097
5945 01:15:55.684978 [Calibration Summary] 1866 Mbps
5946 01:15:55.687765 CH 0, Rank 0
5947 01:15:55.688380 SW Impedance : PASS
5948 01:15:55.691026 DUTY Scan : NO K
5949 01:15:55.694730 ZQ Calibration : PASS
5950 01:15:55.695177 Jitter Meter : NO K
5951 01:15:55.698088 CBT Training : PASS
5952 01:15:55.698534 Write leveling : PASS
5953 01:15:55.701149 RX DQS gating : PASS
5954 01:15:55.704114 RX DQ/DQS(RDDQC) : PASS
5955 01:15:55.704662 TX DQ/DQS : PASS
5956 01:15:55.707456 RX DATLAT : PASS
5957 01:15:55.711090 RX DQ/DQS(Engine): PASS
5958 01:15:55.711508 TX OE : NO K
5959 01:15:55.714405 All Pass.
5960 01:15:55.714828
5961 01:15:55.715165 CH 0, Rank 1
5962 01:15:55.717555 SW Impedance : PASS
5963 01:15:55.718103 DUTY Scan : NO K
5964 01:15:55.721134 ZQ Calibration : PASS
5965 01:15:55.724280 Jitter Meter : NO K
5966 01:15:55.724784 CBT Training : PASS
5967 01:15:55.727210 Write leveling : PASS
5968 01:15:55.731185 RX DQS gating : PASS
5969 01:15:55.731603 RX DQ/DQS(RDDQC) : PASS
5970 01:15:55.733929 TX DQ/DQS : PASS
5971 01:15:55.737126 RX DATLAT : PASS
5972 01:15:55.737548 RX DQ/DQS(Engine): PASS
5973 01:15:55.740549 TX OE : NO K
5974 01:15:55.740968 All Pass.
5975 01:15:55.741301
5976 01:15:55.744181 CH 1, Rank 0
5977 01:15:55.744614 SW Impedance : PASS
5978 01:15:55.747578 DUTY Scan : NO K
5979 01:15:55.751288 ZQ Calibration : PASS
5980 01:15:55.751812 Jitter Meter : NO K
5981 01:15:55.754151 CBT Training : PASS
5982 01:15:55.757123 Write leveling : PASS
5983 01:15:55.757652 RX DQS gating : PASS
5984 01:15:55.760630 RX DQ/DQS(RDDQC) : PASS
5985 01:15:55.763652 TX DQ/DQS : PASS
5986 01:15:55.764211 RX DATLAT : PASS
5987 01:15:55.767276 RX DQ/DQS(Engine): PASS
5988 01:15:55.770426 TX OE : NO K
5989 01:15:55.770972 All Pass.
5990 01:15:55.771318
5991 01:15:55.771630 CH 1, Rank 1
5992 01:15:55.773678 SW Impedance : PASS
5993 01:15:55.777218 DUTY Scan : NO K
5994 01:15:55.777639 ZQ Calibration : PASS
5995 01:15:55.780293 Jitter Meter : NO K
5996 01:15:55.780713 CBT Training : PASS
5997 01:15:55.783291 Write leveling : PASS
5998 01:15:55.787210 RX DQS gating : PASS
5999 01:15:55.787756 RX DQ/DQS(RDDQC) : PASS
6000 01:15:55.790083 TX DQ/DQS : PASS
6001 01:15:55.793697 RX DATLAT : PASS
6002 01:15:55.794228 RX DQ/DQS(Engine): PASS
6003 01:15:55.796703 TX OE : NO K
6004 01:15:55.797124 All Pass.
6005 01:15:55.797470
6006 01:15:55.800241 DramC Write-DBI off
6007 01:15:55.803237 PER_BANK_REFRESH: Hybrid Mode
6008 01:15:55.803658 TX_TRACKING: ON
6009 01:15:55.813298 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6010 01:15:55.816512 [FAST_K] Save calibration result to emmc
6011 01:15:55.819420 dramc_set_vcore_voltage set vcore to 650000
6012 01:15:55.822904 Read voltage for 400, 6
6013 01:15:55.823322 Vio18 = 0
6014 01:15:55.826019 Vcore = 650000
6015 01:15:55.826439 Vdram = 0
6016 01:15:55.826771 Vddq = 0
6017 01:15:55.827080 Vmddr = 0
6018 01:15:55.832519 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6019 01:15:55.838993 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6020 01:15:55.839076 MEM_TYPE=3, freq_sel=20
6021 01:15:55.841983 sv_algorithm_assistance_LP4_800
6022 01:15:55.845545 ============ PULL DRAM RESETB DOWN ============
6023 01:15:55.852485 ========== PULL DRAM RESETB DOWN end =========
6024 01:15:55.855250 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6025 01:15:55.858548 ===================================
6026 01:15:55.862153 LPDDR4 DRAM CONFIGURATION
6027 01:15:55.865127 ===================================
6028 01:15:55.865209 EX_ROW_EN[0] = 0x0
6029 01:15:55.868842 EX_ROW_EN[1] = 0x0
6030 01:15:55.871804 LP4Y_EN = 0x0
6031 01:15:55.871892 WORK_FSP = 0x0
6032 01:15:55.875279 WL = 0x2
6033 01:15:55.875368 RL = 0x2
6034 01:15:55.878420 BL = 0x2
6035 01:15:55.878507 RPST = 0x0
6036 01:15:55.881517 RD_PRE = 0x0
6037 01:15:55.881610 WR_PRE = 0x1
6038 01:15:55.885189 WR_PST = 0x0
6039 01:15:55.885290 DBI_WR = 0x0
6040 01:15:55.888140 DBI_RD = 0x0
6041 01:15:55.888240 OTF = 0x1
6042 01:15:55.891752 ===================================
6043 01:15:55.894557 ===================================
6044 01:15:55.898325 ANA top config
6045 01:15:55.901458 ===================================
6046 01:15:55.905074 DLL_ASYNC_EN = 0
6047 01:15:55.905155 ALL_SLAVE_EN = 1
6048 01:15:55.908179 NEW_RANK_MODE = 1
6049 01:15:55.911537 DLL_IDLE_MODE = 1
6050 01:15:55.914495 LP45_APHY_COMB_EN = 1
6051 01:15:55.914579 TX_ODT_DIS = 1
6052 01:15:55.918031 NEW_8X_MODE = 1
6053 01:15:55.921043 ===================================
6054 01:15:55.924504 ===================================
6055 01:15:55.927995 data_rate = 800
6056 01:15:55.930838 CKR = 1
6057 01:15:55.934616 DQ_P2S_RATIO = 4
6058 01:15:55.937802 ===================================
6059 01:15:55.940678 CA_P2S_RATIO = 4
6060 01:15:55.940759 DQ_CA_OPEN = 0
6061 01:15:55.944366 DQ_SEMI_OPEN = 1
6062 01:15:55.947234 CA_SEMI_OPEN = 1
6063 01:15:55.950960 CA_FULL_RATE = 0
6064 01:15:55.953787 DQ_CKDIV4_EN = 0
6065 01:15:55.957268 CA_CKDIV4_EN = 1
6066 01:15:55.957349 CA_PREDIV_EN = 0
6067 01:15:55.961020 PH8_DLY = 0
6068 01:15:55.963732 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6069 01:15:55.967024 DQ_AAMCK_DIV = 0
6070 01:15:55.970330 CA_AAMCK_DIV = 0
6071 01:15:55.973851 CA_ADMCK_DIV = 4
6072 01:15:55.973931 DQ_TRACK_CA_EN = 0
6073 01:15:55.977449 CA_PICK = 800
6074 01:15:55.980473 CA_MCKIO = 400
6075 01:15:55.983380 MCKIO_SEMI = 400
6076 01:15:55.987204 PLL_FREQ = 3016
6077 01:15:55.990072 DQ_UI_PI_RATIO = 32
6078 01:15:55.993583 CA_UI_PI_RATIO = 32
6079 01:15:55.996839 ===================================
6080 01:15:56.000087 ===================================
6081 01:15:56.003670 memory_type:LPDDR4
6082 01:15:56.003751 GP_NUM : 10
6083 01:15:56.006792 SRAM_EN : 1
6084 01:15:56.006872 MD32_EN : 0
6085 01:15:56.009722 ===================================
6086 01:15:56.013323 [ANA_INIT] >>>>>>>>>>>>>>
6087 01:15:56.016255 <<<<<< [CONFIGURE PHASE]: ANA_TX
6088 01:15:56.019937 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6089 01:15:56.023329 ===================================
6090 01:15:56.026437 data_rate = 800,PCW = 0X7400
6091 01:15:56.029892 ===================================
6092 01:15:56.032904 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6093 01:15:56.039379 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6094 01:15:56.049698 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6095 01:15:56.052930 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6096 01:15:56.056289 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6097 01:15:56.062977 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6098 01:15:56.063178 [ANA_INIT] flow start
6099 01:15:56.066023 [ANA_INIT] PLL >>>>>>>>
6100 01:15:56.069279 [ANA_INIT] PLL <<<<<<<<
6101 01:15:56.069575 [ANA_INIT] MIDPI >>>>>>>>
6102 01:15:56.072899 [ANA_INIT] MIDPI <<<<<<<<
6103 01:15:56.076302 [ANA_INIT] DLL >>>>>>>>
6104 01:15:56.076682 [ANA_INIT] flow end
6105 01:15:56.082795 ============ LP4 DIFF to SE enter ============
6106 01:15:56.085902 ============ LP4 DIFF to SE exit ============
6107 01:15:56.086358 [ANA_INIT] <<<<<<<<<<<<<
6108 01:15:56.089509 [Flow] Enable top DCM control >>>>>
6109 01:15:56.092532 [Flow] Enable top DCM control <<<<<
6110 01:15:56.096182 Enable DLL master slave shuffle
6111 01:15:56.102381 ==============================================================
6112 01:15:56.105849 Gating Mode config
6113 01:15:56.109389 ==============================================================
6114 01:15:56.112421 Config description:
6115 01:15:56.122479 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6116 01:15:56.128694 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6117 01:15:56.131830 SELPH_MODE 0: By rank 1: By Phase
6118 01:15:56.138393 ==============================================================
6119 01:15:56.141932 GAT_TRACK_EN = 0
6120 01:15:56.145374 RX_GATING_MODE = 2
6121 01:15:56.148260 RX_GATING_TRACK_MODE = 2
6122 01:15:56.151410 SELPH_MODE = 1
6123 01:15:56.154875 PICG_EARLY_EN = 1
6124 01:15:56.155449 VALID_LAT_VALUE = 1
6125 01:15:56.161466 ==============================================================
6126 01:15:56.164586 Enter into Gating configuration >>>>
6127 01:15:56.168135 Exit from Gating configuration <<<<
6128 01:15:56.171450 Enter into DVFS_PRE_config >>>>>
6129 01:15:56.181623 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6130 01:15:56.184634 Exit from DVFS_PRE_config <<<<<
6131 01:15:56.188077 Enter into PICG configuration >>>>
6132 01:15:56.191087 Exit from PICG configuration <<<<
6133 01:15:56.194306 [RX_INPUT] configuration >>>>>
6134 01:15:56.197907 [RX_INPUT] configuration <<<<<
6135 01:15:56.204173 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6136 01:15:56.208157 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6137 01:15:56.214172 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6138 01:15:56.220946 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6139 01:15:56.227402 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6140 01:15:56.233557 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6141 01:15:56.237204 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6142 01:15:56.240268 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6143 01:15:56.243989 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6144 01:15:56.250564 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6145 01:15:56.253699 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6146 01:15:56.256719 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6147 01:15:56.260045 ===================================
6148 01:15:56.263259 LPDDR4 DRAM CONFIGURATION
6149 01:15:56.266699 ===================================
6150 01:15:56.269813 EX_ROW_EN[0] = 0x0
6151 01:15:56.270233 EX_ROW_EN[1] = 0x0
6152 01:15:56.273502 LP4Y_EN = 0x0
6153 01:15:56.273924 WORK_FSP = 0x0
6154 01:15:56.276474 WL = 0x2
6155 01:15:56.276895 RL = 0x2
6156 01:15:56.279971 BL = 0x2
6157 01:15:56.280394 RPST = 0x0
6158 01:15:56.283049 RD_PRE = 0x0
6159 01:15:56.283514 WR_PRE = 0x1
6160 01:15:56.286640 WR_PST = 0x0
6161 01:15:56.289762 DBI_WR = 0x0
6162 01:15:56.290180 DBI_RD = 0x0
6163 01:15:56.292808 OTF = 0x1
6164 01:15:56.296429 ===================================
6165 01:15:56.299581 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6166 01:15:56.302969 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6167 01:15:56.306377 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6168 01:15:56.309299 ===================================
6169 01:15:56.312248 LPDDR4 DRAM CONFIGURATION
6170 01:15:56.315850 ===================================
6171 01:15:56.319141 EX_ROW_EN[0] = 0x10
6172 01:15:56.319228 EX_ROW_EN[1] = 0x0
6173 01:15:56.322581 LP4Y_EN = 0x0
6174 01:15:56.322691 WORK_FSP = 0x0
6175 01:15:56.325554 WL = 0x2
6176 01:15:56.325647 RL = 0x2
6177 01:15:56.328968 BL = 0x2
6178 01:15:56.329050 RPST = 0x0
6179 01:15:56.332032 RD_PRE = 0x0
6180 01:15:56.335439 WR_PRE = 0x1
6181 01:15:56.335524 WR_PST = 0x0
6182 01:15:56.338684 DBI_WR = 0x0
6183 01:15:56.338766 DBI_RD = 0x0
6184 01:15:56.342120 OTF = 0x1
6185 01:15:56.345032 ===================================
6186 01:15:56.351648 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6187 01:15:56.354814 nWR fixed to 30
6188 01:15:56.354900 [ModeRegInit_LP4] CH0 RK0
6189 01:15:56.358475 [ModeRegInit_LP4] CH0 RK1
6190 01:15:56.361672 [ModeRegInit_LP4] CH1 RK0
6191 01:15:56.365225 [ModeRegInit_LP4] CH1 RK1
6192 01:15:56.365380 match AC timing 19
6193 01:15:56.368214 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6194 01:15:56.374699 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6195 01:15:56.377992 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6196 01:15:56.384448 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6197 01:15:56.388068 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6198 01:15:56.388204 ==
6199 01:15:56.391129 Dram Type= 6, Freq= 0, CH_0, rank 0
6200 01:15:56.394372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6201 01:15:56.394545 ==
6202 01:15:56.401537 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6203 01:15:56.407691 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6204 01:15:56.411320 [CA 0] Center 36 (8~64) winsize 57
6205 01:15:56.414589 [CA 1] Center 36 (8~64) winsize 57
6206 01:15:56.415006 [CA 2] Center 36 (8~64) winsize 57
6207 01:15:56.418003 [CA 3] Center 36 (8~64) winsize 57
6208 01:15:56.421254 [CA 4] Center 36 (8~64) winsize 57
6209 01:15:56.424421 [CA 5] Center 36 (8~64) winsize 57
6210 01:15:56.424846
6211 01:15:56.430807 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6212 01:15:56.431233
6213 01:15:56.434379 [CATrainingPosCal] consider 1 rank data
6214 01:15:56.437859 u2DelayCellTimex100 = 270/100 ps
6215 01:15:56.440749 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 01:15:56.444234 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 01:15:56.447294 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 01:15:56.450625 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 01:15:56.453744 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 01:15:56.457230 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 01:15:56.457651
6222 01:15:56.460780 CA PerBit enable=1, Macro0, CA PI delay=36
6223 01:15:56.461203
6224 01:15:56.463717 [CBTSetCACLKResult] CA Dly = 36
6225 01:15:56.467275 CS Dly: 1 (0~32)
6226 01:15:56.467696 ==
6227 01:15:56.470301 Dram Type= 6, Freq= 0, CH_0, rank 1
6228 01:15:56.473853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6229 01:15:56.474274 ==
6230 01:15:56.480515 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6231 01:15:56.486348 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6232 01:15:56.490205 [CA 0] Center 36 (8~64) winsize 57
6233 01:15:56.493241 [CA 1] Center 36 (8~64) winsize 57
6234 01:15:56.493854 [CA 2] Center 36 (8~64) winsize 57
6235 01:15:56.496941 [CA 3] Center 36 (8~64) winsize 57
6236 01:15:56.500163 [CA 4] Center 36 (8~64) winsize 57
6237 01:15:56.503544 [CA 5] Center 36 (8~64) winsize 57
6238 01:15:56.504004
6239 01:15:56.506426 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6240 01:15:56.509524
6241 01:15:56.513147 [CATrainingPosCal] consider 2 rank data
6242 01:15:56.513570 u2DelayCellTimex100 = 270/100 ps
6243 01:15:56.519821 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 01:15:56.522811 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 01:15:56.526575 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 01:15:56.529483 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 01:15:56.532739 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 01:15:56.536134 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 01:15:56.536575
6250 01:15:56.539880 CA PerBit enable=1, Macro0, CA PI delay=36
6251 01:15:56.540343
6252 01:15:56.542906 [CBTSetCACLKResult] CA Dly = 36
6253 01:15:56.546114 CS Dly: 1 (0~32)
6254 01:15:56.546533
6255 01:15:56.549098 ----->DramcWriteLeveling(PI) begin...
6256 01:15:56.549640 ==
6257 01:15:56.552401 Dram Type= 6, Freq= 0, CH_0, rank 0
6258 01:15:56.555662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6259 01:15:56.556106 ==
6260 01:15:56.559056 Write leveling (Byte 0): 40 => 8
6261 01:15:56.562713 Write leveling (Byte 1): 40 => 8
6262 01:15:56.565478 DramcWriteLeveling(PI) end<-----
6263 01:15:56.565901
6264 01:15:56.566241 ==
6265 01:15:56.568602 Dram Type= 6, Freq= 0, CH_0, rank 0
6266 01:15:56.572125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6267 01:15:56.572580 ==
6268 01:15:56.575541 [Gating] SW mode calibration
6269 01:15:56.582236 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6270 01:15:56.589029 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6271 01:15:56.592402 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6272 01:15:56.598482 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6273 01:15:56.602056 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6274 01:15:56.605182 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6275 01:15:56.611838 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 01:15:56.614873 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 01:15:56.618544 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 01:15:56.624634 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 01:15:56.628419 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6280 01:15:56.631615 Total UI for P1: 0, mck2ui 16
6281 01:15:56.634652 best dqsien dly found for B0: ( 0, 14, 24)
6282 01:15:56.638131 Total UI for P1: 0, mck2ui 16
6283 01:15:56.641355 best dqsien dly found for B1: ( 0, 14, 24)
6284 01:15:56.644403 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6285 01:15:56.648177 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6286 01:15:56.648597
6287 01:15:56.651232 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6288 01:15:56.654741 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6289 01:15:56.657918 [Gating] SW calibration Done
6290 01:15:56.658345 ==
6291 01:15:56.661303 Dram Type= 6, Freq= 0, CH_0, rank 0
6292 01:15:56.664605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 01:15:56.667985 ==
6294 01:15:56.668432 RX Vref Scan: 0
6295 01:15:56.668769
6296 01:15:56.671031 RX Vref 0 -> 0, step: 1
6297 01:15:56.671452
6298 01:15:56.674290 RX Delay -410 -> 252, step: 16
6299 01:15:56.677577 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6300 01:15:56.681092 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6301 01:15:56.684361 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6302 01:15:56.690482 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6303 01:15:56.693822 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6304 01:15:56.697765 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6305 01:15:56.703828 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6306 01:15:56.706646 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6307 01:15:56.710507 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6308 01:15:56.713397 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6309 01:15:56.719965 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6310 01:15:56.723576 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6311 01:15:56.726688 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6312 01:15:56.729691 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6313 01:15:56.736787 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6314 01:15:56.739778 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6315 01:15:56.740155 ==
6316 01:15:56.743585 Dram Type= 6, Freq= 0, CH_0, rank 0
6317 01:15:56.746681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6318 01:15:56.747097 ==
6319 01:15:56.749666 DQS Delay:
6320 01:15:56.750079 DQS0 = 35, DQS1 = 59
6321 01:15:56.753644 DQM Delay:
6322 01:15:56.754071 DQM0 = 4, DQM1 = 18
6323 01:15:56.756380 DQ Delay:
6324 01:15:56.756792 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6325 01:15:56.759683 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6326 01:15:56.762915 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =16
6327 01:15:56.766367 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6328 01:15:56.766782
6329 01:15:56.767108
6330 01:15:56.767415 ==
6331 01:15:56.769320 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 01:15:56.775912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 01:15:56.776342 ==
6334 01:15:56.776734
6335 01:15:56.777202
6336 01:15:56.777517 TX Vref Scan disable
6337 01:15:56.779454 == TX Byte 0 ==
6338 01:15:56.782455 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6339 01:15:56.785999 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6340 01:15:56.789609 == TX Byte 1 ==
6341 01:15:56.792442 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6342 01:15:56.795856 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6343 01:15:56.799047 ==
6344 01:15:56.802266 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 01:15:56.805500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 01:15:56.805806 ==
6347 01:15:56.806041
6348 01:15:56.806264
6349 01:15:56.809073 TX Vref Scan disable
6350 01:15:56.809366 == TX Byte 0 ==
6351 01:15:56.812106 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6352 01:15:56.818627 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6353 01:15:56.819070 == TX Byte 1 ==
6354 01:15:56.822538 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6355 01:15:56.828606 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6356 01:15:56.828898
6357 01:15:56.829131 [DATLAT]
6358 01:15:56.829344 Freq=400, CH0 RK0
6359 01:15:56.829555
6360 01:15:56.831533 DATLAT Default: 0xf
6361 01:15:56.835152 0, 0xFFFF, sum = 0
6362 01:15:56.835448 1, 0xFFFF, sum = 0
6363 01:15:56.838774 2, 0xFFFF, sum = 0
6364 01:15:56.839068 3, 0xFFFF, sum = 0
6365 01:15:56.841803 4, 0xFFFF, sum = 0
6366 01:15:56.842250 5, 0xFFFF, sum = 0
6367 01:15:56.845068 6, 0xFFFF, sum = 0
6368 01:15:56.845363 7, 0xFFFF, sum = 0
6369 01:15:56.847976 8, 0xFFFF, sum = 0
6370 01:15:56.848320 9, 0xFFFF, sum = 0
6371 01:15:56.851805 10, 0xFFFF, sum = 0
6372 01:15:56.852169 11, 0xFFFF, sum = 0
6373 01:15:56.854939 12, 0xFFFF, sum = 0
6374 01:15:56.855289 13, 0x0, sum = 1
6375 01:15:56.857950 14, 0x0, sum = 2
6376 01:15:56.858264 15, 0x0, sum = 3
6377 01:15:56.861525 16, 0x0, sum = 4
6378 01:15:56.861841 best_step = 14
6379 01:15:56.862093
6380 01:15:56.862345 ==
6381 01:15:56.864571 Dram Type= 6, Freq= 0, CH_0, rank 0
6382 01:15:56.870902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6383 01:15:56.871349 ==
6384 01:15:56.871593 RX Vref Scan: 1
6385 01:15:56.871856
6386 01:15:56.874655 RX Vref 0 -> 0, step: 1
6387 01:15:56.875035
6388 01:15:56.877562 RX Delay -359 -> 252, step: 8
6389 01:15:56.877972
6390 01:15:56.880955 Set Vref, RX VrefLevel [Byte0]: 57
6391 01:15:56.884175 [Byte1]: 59
6392 01:15:56.887587
6393 01:15:56.888020 Final RX Vref Byte 0 = 57 to rank0
6394 01:15:56.891034 Final RX Vref Byte 1 = 59 to rank0
6395 01:15:56.894031 Final RX Vref Byte 0 = 57 to rank1
6396 01:15:56.897338 Final RX Vref Byte 1 = 59 to rank1==
6397 01:15:56.900915 Dram Type= 6, Freq= 0, CH_0, rank 0
6398 01:15:56.907456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6399 01:15:56.907822 ==
6400 01:15:56.908192 DQS Delay:
6401 01:15:56.910503 DQS0 = 44, DQS1 = 60
6402 01:15:56.910817 DQM Delay:
6403 01:15:56.913528 DQM0 = 10, DQM1 = 17
6404 01:15:56.913853 DQ Delay:
6405 01:15:56.917045 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6406 01:15:56.920265 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6407 01:15:56.923729 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6408 01:15:56.926893 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6409 01:15:56.927324
6410 01:15:56.927590
6411 01:15:56.933749 [DQSOSCAuto] RK0, (LSB)MR18= 0x8a7f, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6412 01:15:56.936824 CH0 RK0: MR19=C0C, MR18=8A7F
6413 01:15:56.943167 CH0_RK0: MR19=0xC0C, MR18=0x8A7F, DQSOSC=392, MR23=63, INC=384, DEC=256
6414 01:15:56.943463 ==
6415 01:15:56.946876 Dram Type= 6, Freq= 0, CH_0, rank 1
6416 01:15:56.949866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6417 01:15:56.950160 ==
6418 01:15:56.953381 [Gating] SW mode calibration
6419 01:15:56.960154 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6420 01:15:56.966534 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6421 01:15:56.970320 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6422 01:15:56.976406 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6423 01:15:56.979556 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6424 01:15:56.983216 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6425 01:15:56.989313 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 01:15:56.992563 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 01:15:56.996273 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 01:15:57.002715 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 01:15:57.005818 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6430 01:15:57.009225 Total UI for P1: 0, mck2ui 16
6431 01:15:57.012333 best dqsien dly found for B0: ( 0, 14, 24)
6432 01:15:57.015866 Total UI for P1: 0, mck2ui 16
6433 01:15:57.018897 best dqsien dly found for B1: ( 0, 14, 24)
6434 01:15:57.022411 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6435 01:15:57.025666 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6436 01:15:57.026089
6437 01:15:57.029262 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6438 01:15:57.032245 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6439 01:15:57.035840 [Gating] SW calibration Done
6440 01:15:57.036310 ==
6441 01:15:57.038778 Dram Type= 6, Freq= 0, CH_0, rank 1
6442 01:15:57.045592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 01:15:57.046008 ==
6444 01:15:57.046333 RX Vref Scan: 0
6445 01:15:57.046640
6446 01:15:57.049012 RX Vref 0 -> 0, step: 1
6447 01:15:57.049457
6448 01:15:57.052291 RX Delay -410 -> 252, step: 16
6449 01:15:57.055586 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6450 01:15:57.058767 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6451 01:15:57.061804 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6452 01:15:57.068836 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6453 01:15:57.071861 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6454 01:15:57.074964 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6455 01:15:57.081530 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6456 01:15:57.085327 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6457 01:15:57.088277 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6458 01:15:57.091353 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6459 01:15:57.098230 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6460 01:15:57.101299 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6461 01:15:57.104876 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6462 01:15:57.107824 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6463 01:15:57.114726 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6464 01:15:57.117958 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6465 01:15:57.118505 ==
6466 01:15:57.121178 Dram Type= 6, Freq= 0, CH_0, rank 1
6467 01:15:57.124603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6468 01:15:57.125030 ==
6469 01:15:57.127399 DQS Delay:
6470 01:15:57.127819 DQS0 = 35, DQS1 = 59
6471 01:15:57.131131 DQM Delay:
6472 01:15:57.131552 DQM0 = 7, DQM1 = 17
6473 01:15:57.134018 DQ Delay:
6474 01:15:57.134439 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6475 01:15:57.137592 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6476 01:15:57.140676 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6477 01:15:57.143774 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6478 01:15:57.144256
6479 01:15:57.144601
6480 01:15:57.144915 ==
6481 01:15:57.147345 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 01:15:57.153642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 01:15:57.154068 ==
6484 01:15:57.154407
6485 01:15:57.154732
6486 01:15:57.155031 TX Vref Scan disable
6487 01:15:57.157007 == TX Byte 0 ==
6488 01:15:57.160481 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6489 01:15:57.166981 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6490 01:15:57.167403 == TX Byte 1 ==
6491 01:15:57.170478 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6492 01:15:57.173501 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6493 01:15:57.176899 ==
6494 01:15:57.179988 Dram Type= 6, Freq= 0, CH_0, rank 1
6495 01:15:57.183755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 01:15:57.184216 ==
6497 01:15:57.184659
6498 01:15:57.185148
6499 01:15:57.186496 TX Vref Scan disable
6500 01:15:57.186920 == TX Byte 0 ==
6501 01:15:57.189826 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6502 01:15:57.196312 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6503 01:15:57.196734 == TX Byte 1 ==
6504 01:15:57.200018 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6505 01:15:57.206747 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6506 01:15:57.207169
6507 01:15:57.207504 [DATLAT]
6508 01:15:57.207819 Freq=400, CH0 RK1
6509 01:15:57.208196
6510 01:15:57.209652 DATLAT Default: 0xe
6511 01:15:57.213269 0, 0xFFFF, sum = 0
6512 01:15:57.213701 1, 0xFFFF, sum = 0
6513 01:15:57.216432 2, 0xFFFF, sum = 0
6514 01:15:57.216863 3, 0xFFFF, sum = 0
6515 01:15:57.219818 4, 0xFFFF, sum = 0
6516 01:15:57.220357 5, 0xFFFF, sum = 0
6517 01:15:57.222933 6, 0xFFFF, sum = 0
6518 01:15:57.223362 7, 0xFFFF, sum = 0
6519 01:15:57.227913 8, 0xFFFF, sum = 0
6520 01:15:57.228399 9, 0xFFFF, sum = 0
6521 01:15:57.229270 10, 0xFFFF, sum = 0
6522 01:15:57.229646 11, 0xFFFF, sum = 0
6523 01:15:57.232712 12, 0xFFFF, sum = 0
6524 01:15:57.233159 13, 0x0, sum = 1
6525 01:15:57.235824 14, 0x0, sum = 2
6526 01:15:57.236343 15, 0x0, sum = 3
6527 01:15:57.239395 16, 0x0, sum = 4
6528 01:15:57.239824 best_step = 14
6529 01:15:57.240210
6530 01:15:57.240530 ==
6531 01:15:57.242564 Dram Type= 6, Freq= 0, CH_0, rank 1
6532 01:15:57.249181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6533 01:15:57.249644 ==
6534 01:15:57.249983 RX Vref Scan: 0
6535 01:15:57.250300
6536 01:15:57.252818 RX Vref 0 -> 0, step: 1
6537 01:15:57.253239
6538 01:15:57.255390 RX Delay -359 -> 252, step: 8
6539 01:15:57.262066 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6540 01:15:57.265390 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6541 01:15:57.268690 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6542 01:15:57.272470 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6543 01:15:57.278781 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6544 01:15:57.282019 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6545 01:15:57.285210 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6546 01:15:57.291710 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6547 01:15:57.294803 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6548 01:15:57.298430 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6549 01:15:57.301786 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6550 01:15:57.308413 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6551 01:15:57.311675 iDelay=209, Bit 12, Center -40 (-287 ~ 208) 496
6552 01:15:57.314744 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6553 01:15:57.318392 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6554 01:15:57.324527 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6555 01:15:57.324951 ==
6556 01:15:57.328053 Dram Type= 6, Freq= 0, CH_0, rank 1
6557 01:15:57.331531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6558 01:15:57.331996 ==
6559 01:15:57.334347 DQS Delay:
6560 01:15:57.334765 DQS0 = 44, DQS1 = 60
6561 01:15:57.335099 DQM Delay:
6562 01:15:57.337800 DQM0 = 9, DQM1 = 15
6563 01:15:57.338220 DQ Delay:
6564 01:15:57.341284 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6565 01:15:57.344523 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6566 01:15:57.347535 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6567 01:15:57.351382 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6568 01:15:57.351941
6569 01:15:57.352291
6570 01:15:57.360645 [DQSOSCAuto] RK1, (LSB)MR18= 0x817a, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6571 01:15:57.361074 CH0 RK1: MR19=C0C, MR18=817A
6572 01:15:57.367245 CH0_RK1: MR19=0xC0C, MR18=0x817A, DQSOSC=393, MR23=63, INC=382, DEC=254
6573 01:15:57.371039 [RxdqsGatingPostProcess] freq 400
6574 01:15:57.377314 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6575 01:15:57.380749 best DQS0 dly(2T, 0.5T) = (0, 10)
6576 01:15:57.383862 best DQS1 dly(2T, 0.5T) = (0, 10)
6577 01:15:57.387431 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6578 01:15:57.390542 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6579 01:15:57.394068 best DQS0 dly(2T, 0.5T) = (0, 10)
6580 01:15:57.396959 best DQS1 dly(2T, 0.5T) = (0, 10)
6581 01:15:57.400192 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6582 01:15:57.403639 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6583 01:15:57.404103 Pre-setting of DQS Precalculation
6584 01:15:57.409899 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6585 01:15:57.410321 ==
6586 01:15:57.413256 Dram Type= 6, Freq= 0, CH_1, rank 0
6587 01:15:57.416388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6588 01:15:57.416813 ==
6589 01:15:57.423209 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6590 01:15:57.429762 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6591 01:15:57.433421 [CA 0] Center 36 (8~64) winsize 57
6592 01:15:57.436490 [CA 1] Center 36 (8~64) winsize 57
6593 01:15:57.439544 [CA 2] Center 36 (8~64) winsize 57
6594 01:15:57.443265 [CA 3] Center 36 (8~64) winsize 57
6595 01:15:57.446582 [CA 4] Center 36 (8~64) winsize 57
6596 01:15:57.449670 [CA 5] Center 36 (8~64) winsize 57
6597 01:15:57.450205
6598 01:15:57.453165 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6599 01:15:57.453696
6600 01:15:57.456265 [CATrainingPosCal] consider 1 rank data
6601 01:15:57.459560 u2DelayCellTimex100 = 270/100 ps
6602 01:15:57.462833 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 01:15:57.466309 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 01:15:57.469042 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 01:15:57.472467 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 01:15:57.476093 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 01:15:57.479091 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 01:15:57.479514
6609 01:15:57.485747 CA PerBit enable=1, Macro0, CA PI delay=36
6610 01:15:57.486283
6611 01:15:57.486634 [CBTSetCACLKResult] CA Dly = 36
6612 01:15:57.488758 CS Dly: 1 (0~32)
6613 01:15:57.489171 ==
6614 01:15:57.492414 Dram Type= 6, Freq= 0, CH_1, rank 1
6615 01:15:57.495501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6616 01:15:57.495968 ==
6617 01:15:57.501817 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6618 01:15:57.508460 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6619 01:15:57.512216 [CA 0] Center 36 (8~64) winsize 57
6620 01:15:57.515182 [CA 1] Center 36 (8~64) winsize 57
6621 01:15:57.518473 [CA 2] Center 36 (8~64) winsize 57
6622 01:15:57.522168 [CA 3] Center 36 (8~64) winsize 57
6623 01:15:57.524970 [CA 4] Center 36 (8~64) winsize 57
6624 01:15:57.525386 [CA 5] Center 36 (8~64) winsize 57
6625 01:15:57.528279
6626 01:15:57.531781 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6627 01:15:57.532282
6628 01:15:57.534865 [CATrainingPosCal] consider 2 rank data
6629 01:15:57.538620 u2DelayCellTimex100 = 270/100 ps
6630 01:15:57.541878 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 01:15:57.544806 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 01:15:57.548691 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 01:15:57.551560 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 01:15:57.554742 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 01:15:57.558320 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 01:15:57.558848
6637 01:15:57.561353 CA PerBit enable=1, Macro0, CA PI delay=36
6638 01:15:57.561891
6639 01:15:57.565148 [CBTSetCACLKResult] CA Dly = 36
6640 01:15:57.568082 CS Dly: 1 (0~32)
6641 01:15:57.568507
6642 01:15:57.571157 ----->DramcWriteLeveling(PI) begin...
6643 01:15:57.571585 ==
6644 01:15:57.574632 Dram Type= 6, Freq= 0, CH_1, rank 0
6645 01:15:57.578061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6646 01:15:57.578487 ==
6647 01:15:57.580825 Write leveling (Byte 0): 40 => 8
6648 01:15:57.584394 Write leveling (Byte 1): 40 => 8
6649 01:15:57.587654 DramcWriteLeveling(PI) end<-----
6650 01:15:57.588187
6651 01:15:57.588530 ==
6652 01:15:57.591043 Dram Type= 6, Freq= 0, CH_1, rank 0
6653 01:15:57.594068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6654 01:15:57.597689 ==
6655 01:15:57.598108 [Gating] SW mode calibration
6656 01:15:57.604382 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6657 01:15:57.610773 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6658 01:15:57.614144 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6659 01:15:57.620259 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6660 01:15:57.623938 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6661 01:15:57.627273 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6662 01:15:57.633923 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6663 01:15:57.637219 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 01:15:57.640427 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 01:15:57.646599 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 01:15:57.650247 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6667 01:15:57.653389 Total UI for P1: 0, mck2ui 16
6668 01:15:57.656456 best dqsien dly found for B0: ( 0, 14, 24)
6669 01:15:57.660046 Total UI for P1: 0, mck2ui 16
6670 01:15:57.663017 best dqsien dly found for B1: ( 0, 14, 24)
6671 01:15:57.666787 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6672 01:15:57.670035 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6673 01:15:57.670462
6674 01:15:57.673104 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6675 01:15:57.679837 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6676 01:15:57.680297 [Gating] SW calibration Done
6677 01:15:57.680640 ==
6678 01:15:57.682976 Dram Type= 6, Freq= 0, CH_1, rank 0
6679 01:15:57.689542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 01:15:57.689996 ==
6681 01:15:57.690430 RX Vref Scan: 0
6682 01:15:57.690982
6683 01:15:57.693259 RX Vref 0 -> 0, step: 1
6684 01:15:57.693682
6685 01:15:57.695926 RX Delay -410 -> 252, step: 16
6686 01:15:57.699506 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6687 01:15:57.702899 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6688 01:15:57.709190 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6689 01:15:57.712750 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6690 01:15:57.716313 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6691 01:15:57.718945 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6692 01:15:57.725802 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6693 01:15:57.728879 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6694 01:15:57.732432 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6695 01:15:57.738984 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6696 01:15:57.742193 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6697 01:15:57.745718 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6698 01:15:57.749009 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6699 01:15:57.755457 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6700 01:15:57.758802 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6701 01:15:57.761975 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6702 01:15:57.762496 ==
6703 01:15:57.765050 Dram Type= 6, Freq= 0, CH_1, rank 0
6704 01:15:57.771724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6705 01:15:57.772180 ==
6706 01:15:57.772520 DQS Delay:
6707 01:15:57.774944 DQS0 = 43, DQS1 = 51
6708 01:15:57.775366 DQM Delay:
6709 01:15:57.775704 DQM0 = 13, DQM1 = 13
6710 01:15:57.778585 DQ Delay:
6711 01:15:57.781507 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6712 01:15:57.782028 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6713 01:15:57.785118 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6714 01:15:57.788266 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6715 01:15:57.788685
6716 01:15:57.789019
6717 01:15:57.791251 ==
6718 01:15:57.794660 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 01:15:57.798375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 01:15:57.798840 ==
6721 01:15:57.799191
6722 01:15:57.799504
6723 01:15:57.801275 TX Vref Scan disable
6724 01:15:57.801723 == TX Byte 0 ==
6725 01:15:57.804773 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6726 01:15:57.811500 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6727 01:15:57.811964 == TX Byte 1 ==
6728 01:15:57.814565 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6729 01:15:57.821019 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6730 01:15:57.821522 ==
6731 01:15:57.824738 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 01:15:57.828072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 01:15:57.828496 ==
6734 01:15:57.828831
6735 01:15:57.829142
6736 01:15:57.831228 TX Vref Scan disable
6737 01:15:57.831648 == TX Byte 0 ==
6738 01:15:57.837620 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6739 01:15:57.841283 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6740 01:15:57.841706 == TX Byte 1 ==
6741 01:15:57.847747 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6742 01:15:57.850898 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6743 01:15:57.851320
6744 01:15:57.851655 [DATLAT]
6745 01:15:57.853948 Freq=400, CH1 RK0
6746 01:15:57.854368
6747 01:15:57.854702 DATLAT Default: 0xf
6748 01:15:57.857058 0, 0xFFFF, sum = 0
6749 01:15:57.857483 1, 0xFFFF, sum = 0
6750 01:15:57.860704 2, 0xFFFF, sum = 0
6751 01:15:57.861131 3, 0xFFFF, sum = 0
6752 01:15:57.863706 4, 0xFFFF, sum = 0
6753 01:15:57.864155 5, 0xFFFF, sum = 0
6754 01:15:57.867281 6, 0xFFFF, sum = 0
6755 01:15:57.867704 7, 0xFFFF, sum = 0
6756 01:15:57.870378 8, 0xFFFF, sum = 0
6757 01:15:57.870858 9, 0xFFFF, sum = 0
6758 01:15:57.873977 10, 0xFFFF, sum = 0
6759 01:15:57.877039 11, 0xFFFF, sum = 0
6760 01:15:57.877532 12, 0xFFFF, sum = 0
6761 01:15:57.880151 13, 0x0, sum = 1
6762 01:15:57.880629 14, 0x0, sum = 2
6763 01:15:57.883480 15, 0x0, sum = 3
6764 01:15:57.884116 16, 0x0, sum = 4
6765 01:15:57.884600 best_step = 14
6766 01:15:57.885159
6767 01:15:57.886888 ==
6768 01:15:57.890008 Dram Type= 6, Freq= 0, CH_1, rank 0
6769 01:15:57.893740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6770 01:15:57.894305 ==
6771 01:15:57.894851 RX Vref Scan: 1
6772 01:15:57.895277
6773 01:15:57.896806 RX Vref 0 -> 0, step: 1
6774 01:15:57.897321
6775 01:15:57.899667 RX Delay -343 -> 252, step: 8
6776 01:15:57.900236
6777 01:15:57.903354 Set Vref, RX VrefLevel [Byte0]: 50
6778 01:15:57.906187 [Byte1]: 54
6779 01:15:57.910408
6780 01:15:57.911035 Final RX Vref Byte 0 = 50 to rank0
6781 01:15:57.913393 Final RX Vref Byte 1 = 54 to rank0
6782 01:15:57.917105 Final RX Vref Byte 0 = 50 to rank1
6783 01:15:57.920208 Final RX Vref Byte 1 = 54 to rank1==
6784 01:15:57.923799 Dram Type= 6, Freq= 0, CH_1, rank 0
6785 01:15:57.930365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6786 01:15:57.930781 ==
6787 01:15:57.931110 DQS Delay:
6788 01:15:57.933422 DQS0 = 44, DQS1 = 52
6789 01:15:57.933858 DQM Delay:
6790 01:15:57.934219 DQM0 = 11, DQM1 = 11
6791 01:15:57.936640 DQ Delay:
6792 01:15:57.940111 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6793 01:15:57.943618 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6794 01:15:57.944160 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6795 01:15:57.946578 DQ12 =20, DQ13 =24, DQ14 =16, DQ15 =16
6796 01:15:57.949841
6797 01:15:57.950275
6798 01:15:57.956721 [DQSOSCAuto] RK0, (LSB)MR18= 0x6187, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 397 ps
6799 01:15:57.959781 CH1 RK0: MR19=C0C, MR18=6187
6800 01:15:57.966624 CH1_RK0: MR19=0xC0C, MR18=0x6187, DQSOSC=392, MR23=63, INC=384, DEC=256
6801 01:15:57.967043 ==
6802 01:15:57.969650 Dram Type= 6, Freq= 0, CH_1, rank 1
6803 01:15:57.973412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6804 01:15:57.973844 ==
6805 01:15:57.976445 [Gating] SW mode calibration
6806 01:15:57.983841 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6807 01:15:57.989644 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6808 01:15:57.993342 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6809 01:15:57.995978 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6810 01:15:58.002661 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6811 01:15:58.006102 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6812 01:15:58.009729 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6813 01:15:58.015769 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6814 01:15:58.019513 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 01:15:58.022489 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 01:15:58.029271 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6817 01:15:58.029702 Total UI for P1: 0, mck2ui 16
6818 01:15:58.035666 best dqsien dly found for B0: ( 0, 14, 24)
6819 01:15:58.036136 Total UI for P1: 0, mck2ui 16
6820 01:15:58.042737 best dqsien dly found for B1: ( 0, 14, 24)
6821 01:15:58.045454 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6822 01:15:58.049119 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6823 01:15:58.049547
6824 01:15:58.052106 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6825 01:15:58.055192 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6826 01:15:58.058949 [Gating] SW calibration Done
6827 01:15:58.059485 ==
6828 01:15:58.061866 Dram Type= 6, Freq= 0, CH_1, rank 1
6829 01:15:58.065130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 01:15:58.065593 ==
6831 01:15:58.068419 RX Vref Scan: 0
6832 01:15:58.068847
6833 01:15:58.071720 RX Vref 0 -> 0, step: 1
6834 01:15:58.072226
6835 01:15:58.072712 RX Delay -410 -> 252, step: 16
6836 01:15:58.078368 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6837 01:15:58.081644 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6838 01:15:58.084756 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6839 01:15:58.091297 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6840 01:15:58.095012 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6841 01:15:58.097946 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6842 01:15:58.101451 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6843 01:15:58.107954 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6844 01:15:58.110951 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6845 01:15:58.114778 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6846 01:15:58.117874 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6847 01:15:58.123929 iDelay=230, Bit 11, Center -35 (-282 ~ 213) 496
6848 01:15:58.127582 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6849 01:15:58.130679 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6850 01:15:58.137207 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6851 01:15:58.140435 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6852 01:15:58.140863 ==
6853 01:15:58.144190 Dram Type= 6, Freq= 0, CH_1, rank 1
6854 01:15:58.147205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6855 01:15:58.147633 ==
6856 01:15:58.150614 DQS Delay:
6857 01:15:58.151039 DQS0 = 43, DQS1 = 51
6858 01:15:58.153594 DQM Delay:
6859 01:15:58.154019 DQM0 = 9, DQM1 = 14
6860 01:15:58.154455 DQ Delay:
6861 01:15:58.157124 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6862 01:15:58.160234 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6863 01:15:58.163356 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6864 01:15:58.167070 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6865 01:15:58.167499
6866 01:15:58.168041
6867 01:15:58.168456 ==
6868 01:15:58.169962 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 01:15:58.176449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 01:15:58.176920 ==
6871 01:15:58.177353
6872 01:15:58.177756
6873 01:15:58.178149 TX Vref Scan disable
6874 01:15:58.180095 == TX Byte 0 ==
6875 01:15:58.183091 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6876 01:15:58.186824 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6877 01:15:58.189743 == TX Byte 1 ==
6878 01:15:58.192791 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6879 01:15:58.196499 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6880 01:15:58.196930 ==
6881 01:15:58.199814 Dram Type= 6, Freq= 0, CH_1, rank 1
6882 01:15:58.206255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 01:15:58.206683 ==
6884 01:15:58.207118
6885 01:15:58.207520
6886 01:15:58.208036 TX Vref Scan disable
6887 01:15:58.209814 == TX Byte 0 ==
6888 01:15:58.212635 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6889 01:15:58.216155 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6890 01:15:58.219435 == TX Byte 1 ==
6891 01:15:58.222783 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6892 01:15:58.226070 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6893 01:15:58.229154
6894 01:15:58.229579 [DATLAT]
6895 01:15:58.230003 Freq=400, CH1 RK1
6896 01:15:58.230408
6897 01:15:58.232436 DATLAT Default: 0xe
6898 01:15:58.232860 0, 0xFFFF, sum = 0
6899 01:15:58.235484 1, 0xFFFF, sum = 0
6900 01:15:58.235938 2, 0xFFFF, sum = 0
6901 01:15:58.239264 3, 0xFFFF, sum = 0
6902 01:15:58.242805 4, 0xFFFF, sum = 0
6903 01:15:58.243232 5, 0xFFFF, sum = 0
6904 01:15:58.245810 6, 0xFFFF, sum = 0
6905 01:15:58.246235 7, 0xFFFF, sum = 0
6906 01:15:58.249091 8, 0xFFFF, sum = 0
6907 01:15:58.249520 9, 0xFFFF, sum = 0
6908 01:15:58.252492 10, 0xFFFF, sum = 0
6909 01:15:58.252919 11, 0xFFFF, sum = 0
6910 01:15:58.255725 12, 0xFFFF, sum = 0
6911 01:15:58.256174 13, 0x0, sum = 1
6912 01:15:58.258425 14, 0x0, sum = 2
6913 01:15:58.258508 15, 0x0, sum = 3
6914 01:15:58.261643 16, 0x0, sum = 4
6915 01:15:58.261725 best_step = 14
6916 01:15:58.261790
6917 01:15:58.261850 ==
6918 01:15:58.265535 Dram Type= 6, Freq= 0, CH_1, rank 1
6919 01:15:58.268335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6920 01:15:58.271418 ==
6921 01:15:58.271499 RX Vref Scan: 0
6922 01:15:58.271567
6923 01:15:58.274861 RX Vref 0 -> 0, step: 1
6924 01:15:58.274943
6925 01:15:58.278393 RX Delay -343 -> 252, step: 8
6926 01:15:58.284661 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6927 01:15:58.288216 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6928 01:15:58.291324 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6929 01:15:58.294514 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6930 01:15:58.301192 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6931 01:15:58.304387 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6932 01:15:58.307761 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6933 01:15:58.311018 iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488
6934 01:15:58.317974 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6935 01:15:58.321009 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6936 01:15:58.324032 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6937 01:15:58.327384 iDelay=217, Bit 11, Center -48 (-295 ~ 200) 496
6938 01:15:58.333966 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6939 01:15:58.337454 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6940 01:15:58.340821 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6941 01:15:58.347938 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6942 01:15:58.348349 ==
6943 01:15:58.350449 Dram Type= 6, Freq= 0, CH_1, rank 1
6944 01:15:58.353898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6945 01:15:58.354323 ==
6946 01:15:58.354659 DQS Delay:
6947 01:15:58.357430 DQS0 = 48, DQS1 = 52
6948 01:15:58.357962 DQM Delay:
6949 01:15:58.360504 DQM0 = 12, DQM1 = 10
6950 01:15:58.360927 DQ Delay:
6951 01:15:58.363773 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6952 01:15:58.367558 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =12
6953 01:15:58.370432 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6954 01:15:58.373586 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6955 01:15:58.374009
6956 01:15:58.374346
6957 01:15:58.380257 [DQSOSCAuto] RK1, (LSB)MR18= 0x6aa1, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
6958 01:15:58.383785 CH1 RK1: MR19=C0C, MR18=6AA1
6959 01:15:58.390450 CH1_RK1: MR19=0xC0C, MR18=0x6AA1, DQSOSC=389, MR23=63, INC=390, DEC=260
6960 01:15:58.393558 [RxdqsGatingPostProcess] freq 400
6961 01:15:58.400212 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6962 01:15:58.403246 best DQS0 dly(2T, 0.5T) = (0, 10)
6963 01:15:58.406751 best DQS1 dly(2T, 0.5T) = (0, 10)
6964 01:15:58.410020 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6965 01:15:58.413402 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6966 01:15:58.416683 best DQS0 dly(2T, 0.5T) = (0, 10)
6967 01:15:58.417107 best DQS1 dly(2T, 0.5T) = (0, 10)
6968 01:15:58.419658 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6969 01:15:58.423314 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6970 01:15:58.426270 Pre-setting of DQS Precalculation
6971 01:15:58.432835 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6972 01:15:58.439337 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6973 01:15:58.446492 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6974 01:15:58.446917
6975 01:15:58.447251
6976 01:15:58.449743 [Calibration Summary] 800 Mbps
6977 01:15:58.452836 CH 0, Rank 0
6978 01:15:58.453419 SW Impedance : PASS
6979 01:15:58.456151 DUTY Scan : NO K
6980 01:15:58.459411 ZQ Calibration : PASS
6981 01:15:58.459832 Jitter Meter : NO K
6982 01:15:58.462510 CBT Training : PASS
6983 01:15:58.462927 Write leveling : PASS
6984 01:15:58.465885 RX DQS gating : PASS
6985 01:15:58.468883 RX DQ/DQS(RDDQC) : PASS
6986 01:15:58.469457 TX DQ/DQS : PASS
6987 01:15:58.472579 RX DATLAT : PASS
6988 01:15:58.475973 RX DQ/DQS(Engine): PASS
6989 01:15:58.476394 TX OE : NO K
6990 01:15:58.479065 All Pass.
6991 01:15:58.479483
6992 01:15:58.479813 CH 0, Rank 1
6993 01:15:58.482246 SW Impedance : PASS
6994 01:15:58.482668 DUTY Scan : NO K
6995 01:15:58.485581 ZQ Calibration : PASS
6996 01:15:58.489078 Jitter Meter : NO K
6997 01:15:58.489533 CBT Training : PASS
6998 01:15:58.492085 Write leveling : NO K
6999 01:15:58.495279 RX DQS gating : PASS
7000 01:15:58.495701 RX DQ/DQS(RDDQC) : PASS
7001 01:15:58.498827 TX DQ/DQS : PASS
7002 01:15:58.502558 RX DATLAT : PASS
7003 01:15:58.502977 RX DQ/DQS(Engine): PASS
7004 01:15:58.505628 TX OE : NO K
7005 01:15:58.506050 All Pass.
7006 01:15:58.506385
7007 01:15:58.508555 CH 1, Rank 0
7008 01:15:58.508977 SW Impedance : PASS
7009 01:15:58.512249 DUTY Scan : NO K
7010 01:15:58.515307 ZQ Calibration : PASS
7011 01:15:58.515745 Jitter Meter : NO K
7012 01:15:58.518366 CBT Training : PASS
7013 01:15:58.521928 Write leveling : PASS
7014 01:15:58.522470 RX DQS gating : PASS
7015 01:15:58.524984 RX DQ/DQS(RDDQC) : PASS
7016 01:15:58.528691 TX DQ/DQS : PASS
7017 01:15:58.529114 RX DATLAT : PASS
7018 01:15:58.531587 RX DQ/DQS(Engine): PASS
7019 01:15:58.535317 TX OE : NO K
7020 01:15:58.535740 All Pass.
7021 01:15:58.536137
7022 01:15:58.536458 CH 1, Rank 1
7023 01:15:58.538493 SW Impedance : PASS
7024 01:15:58.541776 DUTY Scan : NO K
7025 01:15:58.542204 ZQ Calibration : PASS
7026 01:15:58.544934 Jitter Meter : NO K
7027 01:15:58.545355 CBT Training : PASS
7028 01:15:58.548245 Write leveling : NO K
7029 01:15:58.551632 RX DQS gating : PASS
7030 01:15:58.552094 RX DQ/DQS(RDDQC) : PASS
7031 01:15:58.554944 TX DQ/DQS : PASS
7032 01:15:58.558557 RX DATLAT : PASS
7033 01:15:58.558979 RX DQ/DQS(Engine): PASS
7034 01:15:58.561693 TX OE : NO K
7035 01:15:58.562119 All Pass.
7036 01:15:58.562457
7037 01:15:58.564498 DramC Write-DBI off
7038 01:15:58.567796 PER_BANK_REFRESH: Hybrid Mode
7039 01:15:58.568273 TX_TRACKING: ON
7040 01:15:58.578126 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7041 01:15:58.581227 [FAST_K] Save calibration result to emmc
7042 01:15:58.584600 dramc_set_vcore_voltage set vcore to 725000
7043 01:15:58.587443 Read voltage for 1600, 0
7044 01:15:58.587866 Vio18 = 0
7045 01:15:58.590697 Vcore = 725000
7046 01:15:58.591117 Vdram = 0
7047 01:15:58.591454 Vddq = 0
7048 01:15:58.591819 Vmddr = 0
7049 01:15:58.597515 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7050 01:15:58.604159 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7051 01:15:58.604583 MEM_TYPE=3, freq_sel=13
7052 01:15:58.607146 sv_algorithm_assistance_LP4_3733
7053 01:15:58.610851 ============ PULL DRAM RESETB DOWN ============
7054 01:15:58.617547 ========== PULL DRAM RESETB DOWN end =========
7055 01:15:58.620579 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7056 01:15:58.624242 ===================================
7057 01:15:58.627106 LPDDR4 DRAM CONFIGURATION
7058 01:15:58.630267 ===================================
7059 01:15:58.630688 EX_ROW_EN[0] = 0x0
7060 01:15:58.633855 EX_ROW_EN[1] = 0x0
7061 01:15:58.636922 LP4Y_EN = 0x0
7062 01:15:58.637341 WORK_FSP = 0x1
7063 01:15:58.639987 WL = 0x5
7064 01:15:58.640409 RL = 0x5
7065 01:15:58.643790 BL = 0x2
7066 01:15:58.644283 RPST = 0x0
7067 01:15:58.646881 RD_PRE = 0x0
7068 01:15:58.647300 WR_PRE = 0x1
7069 01:15:58.649974 WR_PST = 0x1
7070 01:15:58.650055 DBI_WR = 0x0
7071 01:15:58.653040 DBI_RD = 0x0
7072 01:15:58.653122 OTF = 0x1
7073 01:15:58.656221 ===================================
7074 01:15:58.659358 ===================================
7075 01:15:58.662926 ANA top config
7076 01:15:58.666463 ===================================
7077 01:15:58.669887 DLL_ASYNC_EN = 0
7078 01:15:58.669968 ALL_SLAVE_EN = 0
7079 01:15:58.672761 NEW_RANK_MODE = 1
7080 01:15:58.675827 DLL_IDLE_MODE = 1
7081 01:15:58.679395 LP45_APHY_COMB_EN = 1
7082 01:15:58.679501 TX_ODT_DIS = 0
7083 01:15:58.682703 NEW_8X_MODE = 1
7084 01:15:58.685743 ===================================
7085 01:15:58.688991 ===================================
7086 01:15:58.692501 data_rate = 3200
7087 01:15:58.695563 CKR = 1
7088 01:15:58.699280 DQ_P2S_RATIO = 8
7089 01:15:58.702567 ===================================
7090 01:15:58.705862 CA_P2S_RATIO = 8
7091 01:15:58.709014 DQ_CA_OPEN = 0
7092 01:15:58.709093 DQ_SEMI_OPEN = 0
7093 01:15:58.712341 CA_SEMI_OPEN = 0
7094 01:15:58.715185 CA_FULL_RATE = 0
7095 01:15:58.718675 DQ_CKDIV4_EN = 0
7096 01:15:58.721797 CA_CKDIV4_EN = 0
7097 01:15:58.725595 CA_PREDIV_EN = 0
7098 01:15:58.725676 PH8_DLY = 12
7099 01:15:58.728431 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7100 01:15:58.731660 DQ_AAMCK_DIV = 4
7101 01:15:58.735394 CA_AAMCK_DIV = 4
7102 01:15:58.738404 CA_ADMCK_DIV = 4
7103 01:15:58.742249 DQ_TRACK_CA_EN = 0
7104 01:15:58.745161 CA_PICK = 1600
7105 01:15:58.745274 CA_MCKIO = 1600
7106 01:15:58.748387 MCKIO_SEMI = 0
7107 01:15:58.751762 PLL_FREQ = 3068
7108 01:15:58.755235 DQ_UI_PI_RATIO = 32
7109 01:15:58.758735 CA_UI_PI_RATIO = 0
7110 01:15:58.761839 ===================================
7111 01:15:58.765587 ===================================
7112 01:15:58.768618 memory_type:LPDDR4
7113 01:15:58.769032 GP_NUM : 10
7114 01:15:58.771630 SRAM_EN : 1
7115 01:15:58.772067 MD32_EN : 0
7116 01:15:58.775421 ===================================
7117 01:15:58.778359 [ANA_INIT] >>>>>>>>>>>>>>
7118 01:15:58.781871 <<<<<< [CONFIGURE PHASE]: ANA_TX
7119 01:15:58.784972 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7120 01:15:58.788352 ===================================
7121 01:15:58.791747 data_rate = 3200,PCW = 0X7600
7122 01:15:58.794931 ===================================
7123 01:15:58.798194 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7124 01:15:58.804408 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7125 01:15:58.807986 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7126 01:15:58.814358 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7127 01:15:58.818110 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7128 01:15:58.821156 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7129 01:15:58.821709 [ANA_INIT] flow start
7130 01:15:58.824482 [ANA_INIT] PLL >>>>>>>>
7131 01:15:58.827771 [ANA_INIT] PLL <<<<<<<<
7132 01:15:58.831045 [ANA_INIT] MIDPI >>>>>>>>
7133 01:15:58.831488 [ANA_INIT] MIDPI <<<<<<<<
7134 01:15:58.834281 [ANA_INIT] DLL >>>>>>>>
7135 01:15:58.837778 [ANA_INIT] DLL <<<<<<<<
7136 01:15:58.838191 [ANA_INIT] flow end
7137 01:15:58.840948 ============ LP4 DIFF to SE enter ============
7138 01:15:58.847596 ============ LP4 DIFF to SE exit ============
7139 01:15:58.848094 [ANA_INIT] <<<<<<<<<<<<<
7140 01:15:58.850925 [Flow] Enable top DCM control >>>>>
7141 01:15:58.854372 [Flow] Enable top DCM control <<<<<
7142 01:15:58.857469 Enable DLL master slave shuffle
7143 01:15:58.864275 ==============================================================
7144 01:15:58.867197 Gating Mode config
7145 01:15:58.870912 ==============================================================
7146 01:15:58.874028 Config description:
7147 01:15:58.883611 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7148 01:15:58.889939 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7149 01:15:58.893435 SELPH_MODE 0: By rank 1: By Phase
7150 01:15:58.899938 ==============================================================
7151 01:15:58.903449 GAT_TRACK_EN = 1
7152 01:15:58.906444 RX_GATING_MODE = 2
7153 01:15:58.909767 RX_GATING_TRACK_MODE = 2
7154 01:15:58.912978 SELPH_MODE = 1
7155 01:15:58.913539 PICG_EARLY_EN = 1
7156 01:15:58.916319 VALID_LAT_VALUE = 1
7157 01:15:58.922822 ==============================================================
7158 01:15:58.926368 Enter into Gating configuration >>>>
7159 01:15:58.929969 Exit from Gating configuration <<<<
7160 01:15:58.933080 Enter into DVFS_PRE_config >>>>>
7161 01:15:58.942861 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7162 01:15:58.945901 Exit from DVFS_PRE_config <<<<<
7163 01:15:58.949348 Enter into PICG configuration >>>>
7164 01:15:58.952833 Exit from PICG configuration <<<<
7165 01:15:58.955738 [RX_INPUT] configuration >>>>>
7166 01:15:58.959151 [RX_INPUT] configuration <<<<<
7167 01:15:58.965777 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7168 01:15:58.968852 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7169 01:15:58.975682 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7170 01:15:58.981922 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7171 01:15:58.988463 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7172 01:15:58.995204 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7173 01:15:58.998943 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7174 01:15:59.001792 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7175 01:15:59.005388 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7176 01:15:59.012170 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7177 01:15:59.015142 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7178 01:15:59.018562 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7179 01:15:59.021945 ===================================
7180 01:15:59.025113 LPDDR4 DRAM CONFIGURATION
7181 01:15:59.028358 ===================================
7182 01:15:59.031406 EX_ROW_EN[0] = 0x0
7183 01:15:59.031947 EX_ROW_EN[1] = 0x0
7184 01:15:59.034618 LP4Y_EN = 0x0
7185 01:15:59.035039 WORK_FSP = 0x1
7186 01:15:59.037902 WL = 0x5
7187 01:15:59.038535 RL = 0x5
7188 01:15:59.041319 BL = 0x2
7189 01:15:59.042016 RPST = 0x0
7190 01:15:59.044563 RD_PRE = 0x0
7191 01:15:59.045252 WR_PRE = 0x1
7192 01:15:59.047982 WR_PST = 0x1
7193 01:15:59.048519 DBI_WR = 0x0
7194 01:15:59.050977 DBI_RD = 0x0
7195 01:15:59.054444 OTF = 0x1
7196 01:15:59.058009 ===================================
7197 01:15:59.061335 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7198 01:15:59.064483 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7199 01:15:59.067723 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7200 01:15:59.071152 ===================================
7201 01:15:59.074050 LPDDR4 DRAM CONFIGURATION
7202 01:15:59.077792 ===================================
7203 01:15:59.080801 EX_ROW_EN[0] = 0x10
7204 01:15:59.081280 EX_ROW_EN[1] = 0x0
7205 01:15:59.083822 LP4Y_EN = 0x0
7206 01:15:59.084278 WORK_FSP = 0x1
7207 01:15:59.087622 WL = 0x5
7208 01:15:59.088081 RL = 0x5
7209 01:15:59.090793 BL = 0x2
7210 01:15:59.091220 RPST = 0x0
7211 01:15:59.093876 RD_PRE = 0x0
7212 01:15:59.097513 WR_PRE = 0x1
7213 01:15:59.098006 WR_PST = 0x1
7214 01:15:59.100524 DBI_WR = 0x0
7215 01:15:59.101091 DBI_RD = 0x0
7216 01:15:59.103717 OTF = 0x1
7217 01:15:59.107023 ===================================
7218 01:15:59.110686 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7219 01:15:59.113689 ==
7220 01:15:59.116628 Dram Type= 6, Freq= 0, CH_0, rank 0
7221 01:15:59.120259 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7222 01:15:59.120675 ==
7223 01:15:59.123975 [Duty_Offset_Calibration]
7224 01:15:59.124395 B0:2 B1:0 CA:4
7225 01:15:59.124804
7226 01:15:59.126621 [DutyScan_Calibration_Flow] k_type=0
7227 01:15:59.136271
7228 01:15:59.136686 ==CLK 0==
7229 01:15:59.139088 Final CLK duty delay cell = -4
7230 01:15:59.142705 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7231 01:15:59.145643 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7232 01:15:59.148942 [-4] AVG Duty = 4922%(X100)
7233 01:15:59.149519
7234 01:15:59.152456 CH0 CLK Duty spec in!! Max-Min= 218%
7235 01:15:59.155766 [DutyScan_Calibration_Flow] ====Done====
7236 01:15:59.156370
7237 01:15:59.158739 [DutyScan_Calibration_Flow] k_type=1
7238 01:15:59.176585
7239 01:15:59.177077 ==DQS 0 ==
7240 01:15:59.179433 Final DQS duty delay cell = 0
7241 01:15:59.182805 [0] MAX Duty = 5218%(X100), DQS PI = 38
7242 01:15:59.186439 [0] MIN Duty = 5062%(X100), DQS PI = 12
7243 01:15:59.189368 [0] AVG Duty = 5140%(X100)
7244 01:15:59.189783
7245 01:15:59.190112 ==DQS 1 ==
7246 01:15:59.192468 Final DQS duty delay cell = 0
7247 01:15:59.196136 [0] MAX Duty = 5187%(X100), DQS PI = 2
7248 01:15:59.199347 [0] MIN Duty = 4969%(X100), DQS PI = 10
7249 01:15:59.202622 [0] AVG Duty = 5078%(X100)
7250 01:15:59.203045
7251 01:15:59.205712 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7252 01:15:59.206141
7253 01:15:59.209309 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7254 01:15:59.212328 [DutyScan_Calibration_Flow] ====Done====
7255 01:15:59.212778
7256 01:15:59.215691 [DutyScan_Calibration_Flow] k_type=3
7257 01:15:59.233702
7258 01:15:59.234295 ==DQM 0 ==
7259 01:15:59.236645 Final DQM duty delay cell = 0
7260 01:15:59.240065 [0] MAX Duty = 5124%(X100), DQS PI = 22
7261 01:15:59.243087 [0] MIN Duty = 4875%(X100), DQS PI = 54
7262 01:15:59.246753 [0] AVG Duty = 4999%(X100)
7263 01:15:59.247167
7264 01:15:59.247498 ==DQM 1 ==
7265 01:15:59.249981 Final DQM duty delay cell = 0
7266 01:15:59.253405 [0] MAX Duty = 5000%(X100), DQS PI = 4
7267 01:15:59.256659 [0] MIN Duty = 4844%(X100), DQS PI = 16
7268 01:15:59.259984 [0] AVG Duty = 4922%(X100)
7269 01:15:59.260402
7270 01:15:59.263098 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7271 01:15:59.263513
7272 01:15:59.266905 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7273 01:15:59.269758 [DutyScan_Calibration_Flow] ====Done====
7274 01:15:59.270237
7275 01:15:59.273213 [DutyScan_Calibration_Flow] k_type=2
7276 01:15:59.290415
7277 01:15:59.290848 ==DQ 0 ==
7278 01:15:59.293867 Final DQ duty delay cell = 0
7279 01:15:59.296987 [0] MAX Duty = 5124%(X100), DQS PI = 20
7280 01:15:59.300786 [0] MIN Duty = 4938%(X100), DQS PI = 60
7281 01:15:59.301330 [0] AVG Duty = 5031%(X100)
7282 01:15:59.303853
7283 01:15:59.304276 ==DQ 1 ==
7284 01:15:59.307074 Final DQ duty delay cell = 0
7285 01:15:59.309987 [0] MAX Duty = 5218%(X100), DQS PI = 2
7286 01:15:59.313725 [0] MIN Duty = 4907%(X100), DQS PI = 32
7287 01:15:59.314455 [0] AVG Duty = 5062%(X100)
7288 01:15:59.316603
7289 01:15:59.320295 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7290 01:15:59.320707
7291 01:15:59.323249 CH0 DQ 1 Duty spec in!! Max-Min= 311%
7292 01:15:59.327006 [DutyScan_Calibration_Flow] ====Done====
7293 01:15:59.327418 ==
7294 01:15:59.330096 Dram Type= 6, Freq= 0, CH_1, rank 0
7295 01:15:59.333233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7296 01:15:59.333646 ==
7297 01:15:59.336608 [Duty_Offset_Calibration]
7298 01:15:59.337023 B0:0 B1:-1 CA:3
7299 01:15:59.337347
7300 01:15:59.339942 [DutyScan_Calibration_Flow] k_type=0
7301 01:15:59.350306
7302 01:15:59.350717 ==CLK 0==
7303 01:15:59.353276 Final CLK duty delay cell = -4
7304 01:15:59.356945 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7305 01:15:59.360037 [-4] MIN Duty = 4813%(X100), DQS PI = 40
7306 01:15:59.363257 [-4] AVG Duty = 4906%(X100)
7307 01:15:59.363665
7308 01:15:59.366468 CH1 CLK Duty spec in!! Max-Min= 187%
7309 01:15:59.369550 [DutyScan_Calibration_Flow] ====Done====
7310 01:15:59.370099
7311 01:15:59.373078 [DutyScan_Calibration_Flow] k_type=1
7312 01:15:59.389010
7313 01:15:59.389440 ==DQS 0 ==
7314 01:15:59.392737 Final DQS duty delay cell = 0
7315 01:15:59.395479 [0] MAX Duty = 5250%(X100), DQS PI = 28
7316 01:15:59.399096 [0] MIN Duty = 4938%(X100), DQS PI = 56
7317 01:15:59.402454 [0] AVG Duty = 5094%(X100)
7318 01:15:59.402868
7319 01:15:59.403190 ==DQS 1 ==
7320 01:15:59.406081 Final DQS duty delay cell = -4
7321 01:15:59.408702 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7322 01:15:59.411878 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7323 01:15:59.415405 [-4] AVG Duty = 4922%(X100)
7324 01:15:59.415931
7325 01:15:59.419139 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7326 01:15:59.419572
7327 01:15:59.422164 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7328 01:15:59.425150 [DutyScan_Calibration_Flow] ====Done====
7329 01:15:59.425560
7330 01:15:59.428927 [DutyScan_Calibration_Flow] k_type=3
7331 01:15:59.446815
7332 01:15:59.447270 ==DQM 0 ==
7333 01:15:59.449554 Final DQM duty delay cell = 0
7334 01:15:59.453351 [0] MAX Duty = 5031%(X100), DQS PI = 30
7335 01:15:59.455982 [0] MIN Duty = 4782%(X100), DQS PI = 38
7336 01:15:59.459712 [0] AVG Duty = 4906%(X100)
7337 01:15:59.460177
7338 01:15:59.460508 ==DQM 1 ==
7339 01:15:59.462814 Final DQM duty delay cell = 0
7340 01:15:59.466363 [0] MAX Duty = 4969%(X100), DQS PI = 30
7341 01:15:59.469472 [0] MIN Duty = 4782%(X100), DQS PI = 62
7342 01:15:59.472720 [0] AVG Duty = 4875%(X100)
7343 01:15:59.473133
7344 01:15:59.475960 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7345 01:15:59.476376
7346 01:15:59.479001 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7347 01:15:59.482884 [DutyScan_Calibration_Flow] ====Done====
7348 01:15:59.483297
7349 01:15:59.485711 [DutyScan_Calibration_Flow] k_type=2
7350 01:15:59.502889
7351 01:15:59.503320 ==DQ 0 ==
7352 01:15:59.506261 Final DQ duty delay cell = -4
7353 01:15:59.509284 [-4] MAX Duty = 4938%(X100), DQS PI = 32
7354 01:15:59.512258 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7355 01:15:59.515913 [-4] AVG Duty = 4875%(X100)
7356 01:15:59.516371
7357 01:15:59.516701 ==DQ 1 ==
7358 01:15:59.518613 Final DQ duty delay cell = 0
7359 01:15:59.521967 [0] MAX Duty = 5062%(X100), DQS PI = 32
7360 01:15:59.525427 [0] MIN Duty = 4844%(X100), DQS PI = 58
7361 01:15:59.528668 [0] AVG Duty = 4953%(X100)
7362 01:15:59.529208
7363 01:15:59.531925 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7364 01:15:59.532353
7365 01:15:59.535413 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7366 01:15:59.538540 [DutyScan_Calibration_Flow] ====Done====
7367 01:15:59.542119 nWR fixed to 30
7368 01:15:59.545199 [ModeRegInit_LP4] CH0 RK0
7369 01:15:59.545614 [ModeRegInit_LP4] CH0 RK1
7370 01:15:59.548770 [ModeRegInit_LP4] CH1 RK0
7371 01:15:59.551765 [ModeRegInit_LP4] CH1 RK1
7372 01:15:59.552200 match AC timing 5
7373 01:15:59.558686 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7374 01:15:59.561893 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7375 01:15:59.565622 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7376 01:15:59.571552 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7377 01:15:59.575322 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7378 01:15:59.578240 [MiockJmeterHQA]
7379 01:15:59.578652
7380 01:15:59.581964 [DramcMiockJmeter] u1RxGatingPI = 0
7381 01:15:59.582484 0 : 4366, 4137
7382 01:15:59.582830 4 : 4252, 4027
7383 01:15:59.584867 8 : 4363, 4138
7384 01:15:59.585290 12 : 4253, 4026
7385 01:15:59.588503 16 : 4363, 4138
7386 01:15:59.589127 20 : 4252, 4027
7387 01:15:59.591482 24 : 4360, 4138
7388 01:15:59.591946 28 : 4252, 4026
7389 01:15:59.592374 32 : 4250, 4027
7390 01:15:59.594588 36 : 4249, 4027
7391 01:15:59.595010 40 : 4363, 4137
7392 01:15:59.597855 44 : 4360, 4138
7393 01:15:59.598279 48 : 4250, 4026
7394 01:15:59.601427 52 : 4250, 4027
7395 01:15:59.601844 56 : 4249, 4027
7396 01:15:59.604500 60 : 4250, 4026
7397 01:15:59.604919 64 : 4255, 4030
7398 01:15:59.607545 68 : 4360, 4137
7399 01:15:59.608016 72 : 4250, 4027
7400 01:15:59.608365 76 : 4249, 4027
7401 01:15:59.611371 80 : 4250, 4026
7402 01:15:59.611792 84 : 4252, 4030
7403 01:15:59.614207 88 : 4249, 4027
7404 01:15:59.614629 92 : 4361, 4137
7405 01:15:59.617924 96 : 4360, 2467
7406 01:15:59.618442 100 : 4250, 0
7407 01:15:59.618783 104 : 4361, 0
7408 01:15:59.621122 108 : 4255, 0
7409 01:15:59.621641 112 : 4250, 0
7410 01:15:59.624736 116 : 4250, 0
7411 01:15:59.625156 120 : 4252, 0
7412 01:15:59.625489 124 : 4250, 0
7413 01:15:59.627720 128 : 4250, 0
7414 01:15:59.628173 132 : 4252, 0
7415 01:15:59.630907 136 : 4361, 0
7416 01:15:59.631433 140 : 4250, 0
7417 01:15:59.631773 144 : 4249, 0
7418 01:15:59.634186 148 : 4360, 0
7419 01:15:59.634641 152 : 4250, 0
7420 01:15:59.637557 156 : 4361, 0
7421 01:15:59.637977 160 : 4250, 0
7422 01:15:59.638323 164 : 4250, 0
7423 01:15:59.640987 168 : 4249, 0
7424 01:15:59.641409 172 : 4252, 0
7425 01:15:59.641748 176 : 4250, 0
7426 01:15:59.644002 180 : 4250, 0
7427 01:15:59.644447 184 : 4252, 0
7428 01:15:59.647437 188 : 4361, 0
7429 01:15:59.647857 192 : 4361, 0
7430 01:15:59.648232 196 : 4363, 0
7431 01:15:59.650489 200 : 4360, 0
7432 01:15:59.651064 204 : 4250, 0
7433 01:15:59.653974 208 : 4361, 0
7434 01:15:59.654484 212 : 4250, 0
7435 01:15:59.654819 216 : 4250, 0
7436 01:15:59.657417 220 : 4250, 740
7437 01:15:59.657840 224 : 4250, 4017
7438 01:15:59.660234 228 : 4250, 4027
7439 01:15:59.660666 232 : 4360, 4138
7440 01:15:59.663942 236 : 4250, 4027
7441 01:15:59.664367 240 : 4250, 4026
7442 01:15:59.666983 244 : 4250, 4027
7443 01:15:59.667403 248 : 4253, 4029
7444 01:15:59.670203 252 : 4250, 4026
7445 01:15:59.670624 256 : 4250, 4026
7446 01:15:59.673971 260 : 4361, 4137
7447 01:15:59.674392 264 : 4250, 4027
7448 01:15:59.676967 268 : 4249, 4027
7449 01:15:59.677389 272 : 4361, 4138
7450 01:15:59.677726 276 : 4250, 4026
7451 01:15:59.680390 280 : 4250, 4027
7452 01:15:59.680810 284 : 4363, 4140
7453 01:15:59.683475 288 : 4250, 4027
7454 01:15:59.683916 292 : 4250, 4026
7455 01:15:59.687217 296 : 4250, 4027
7456 01:15:59.687735 300 : 4253, 4029
7457 01:15:59.689963 304 : 4250, 4026
7458 01:15:59.690388 308 : 4250, 4027
7459 01:15:59.693115 312 : 4361, 4137
7460 01:15:59.693542 316 : 4250, 4027
7461 01:15:59.696724 320 : 4250, 4027
7462 01:15:59.697181 324 : 4361, 4138
7463 01:15:59.699751 328 : 4250, 4026
7464 01:15:59.700225 332 : 4250, 3897
7465 01:15:59.703430 336 : 4363, 1492
7466 01:15:59.703954
7467 01:15:59.704295 MIOCK jitter meter ch=0
7468 01:15:59.704605
7469 01:15:59.706697 1T = (336-100) = 236 dly cells
7470 01:15:59.713524 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7471 01:15:59.714143 ==
7472 01:15:59.716312 Dram Type= 6, Freq= 0, CH_0, rank 0
7473 01:15:59.720055 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7474 01:15:59.720470 ==
7475 01:15:59.726501 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7476 01:15:59.730150 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7477 01:15:59.732968 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7478 01:15:59.739313 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7479 01:15:59.749160 [CA 0] Center 43 (13~74) winsize 62
7480 01:15:59.752912 [CA 1] Center 43 (13~73) winsize 61
7481 01:15:59.755650 [CA 2] Center 38 (9~67) winsize 59
7482 01:15:59.759100 [CA 3] Center 37 (8~67) winsize 60
7483 01:15:59.762258 [CA 4] Center 36 (6~66) winsize 61
7484 01:15:59.765942 [CA 5] Center 35 (5~66) winsize 62
7485 01:15:59.766048
7486 01:15:59.768817 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7487 01:15:59.768929
7488 01:15:59.775378 [CATrainingPosCal] consider 1 rank data
7489 01:15:59.775949 u2DelayCellTimex100 = 275/100 ps
7490 01:15:59.782046 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7491 01:15:59.786011 CA1 delay=43 (13~73),Diff = 8 PI (28 cell)
7492 01:15:59.788395 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7493 01:15:59.792192 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7494 01:15:59.795259 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7495 01:15:59.798746 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7496 01:15:59.799160
7497 01:15:59.801987 CA PerBit enable=1, Macro0, CA PI delay=35
7498 01:15:59.802404
7499 01:15:59.805035 [CBTSetCACLKResult] CA Dly = 35
7500 01:15:59.808719 CS Dly: 11 (0~42)
7501 01:15:59.811815 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7502 01:15:59.815570 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7503 01:15:59.816229 ==
7504 01:15:59.818585 Dram Type= 6, Freq= 0, CH_0, rank 1
7505 01:15:59.825305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7506 01:15:59.825897 ==
7507 01:15:59.828445 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7508 01:15:59.834775 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7509 01:15:59.838598 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7510 01:15:59.844781 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7511 01:15:59.853075 [CA 0] Center 44 (14~74) winsize 61
7512 01:15:59.856124 [CA 1] Center 44 (14~74) winsize 61
7513 01:15:59.858986 [CA 2] Center 39 (10~68) winsize 59
7514 01:15:59.862510 [CA 3] Center 39 (10~68) winsize 59
7515 01:15:59.865612 [CA 4] Center 37 (7~67) winsize 61
7516 01:15:59.868923 [CA 5] Center 36 (6~66) winsize 61
7517 01:15:59.869362
7518 01:15:59.872292 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7519 01:15:59.872709
7520 01:15:59.878865 [CATrainingPosCal] consider 2 rank data
7521 01:15:59.879499 u2DelayCellTimex100 = 275/100 ps
7522 01:15:59.885660 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7523 01:15:59.888582 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7524 01:15:59.891998 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7525 01:15:59.895508 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7526 01:15:59.898667 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7527 01:15:59.901810 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7528 01:15:59.902237
7529 01:15:59.905206 CA PerBit enable=1, Macro0, CA PI delay=36
7530 01:15:59.905653
7531 01:15:59.908465 [CBTSetCACLKResult] CA Dly = 36
7532 01:15:59.912078 CS Dly: 11 (0~43)
7533 01:15:59.915192 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7534 01:15:59.918407 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7535 01:15:59.918823
7536 01:15:59.925211 ----->DramcWriteLeveling(PI) begin...
7537 01:15:59.925633 ==
7538 01:15:59.928323 Dram Type= 6, Freq= 0, CH_0, rank 0
7539 01:15:59.931456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7540 01:15:59.931873 ==
7541 01:15:59.934804 Write leveling (Byte 0): 35 => 35
7542 01:15:59.937880 Write leveling (Byte 1): 27 => 27
7543 01:15:59.941384 DramcWriteLeveling(PI) end<-----
7544 01:15:59.941809
7545 01:15:59.942139 ==
7546 01:15:59.944446 Dram Type= 6, Freq= 0, CH_0, rank 0
7547 01:15:59.948131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7548 01:15:59.948548 ==
7549 01:15:59.951457 [Gating] SW mode calibration
7550 01:15:59.957933 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7551 01:15:59.964669 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7552 01:15:59.968105 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7553 01:15:59.971532 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7554 01:15:59.977649 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7555 01:15:59.980871 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7556 01:15:59.983849 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7557 01:15:59.990711 1 4 20 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
7558 01:15:59.993741 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7559 01:15:59.997013 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7560 01:16:00.003978 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7561 01:16:00.006889 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7562 01:16:00.009989 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7563 01:16:00.016890 1 5 12 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
7564 01:16:00.020270 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7565 01:16:00.024026 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
7566 01:16:00.030026 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 01:16:00.033706 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7568 01:16:00.036740 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7569 01:16:00.043200 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7570 01:16:00.046517 1 6 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
7571 01:16:00.050214 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
7572 01:16:00.056783 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7573 01:16:00.059639 1 6 20 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
7574 01:16:00.063646 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 01:16:00.069750 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 01:16:00.072965 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7577 01:16:00.076588 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7578 01:16:00.082542 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7579 01:16:00.086085 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7580 01:16:00.089011 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7581 01:16:00.095675 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7582 01:16:00.098977 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7583 01:16:00.102147 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 01:16:00.108949 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 01:16:00.112358 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 01:16:00.115379 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 01:16:00.122043 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 01:16:00.125718 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 01:16:00.128722 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 01:16:00.135057 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 01:16:00.138712 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 01:16:00.145183 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 01:16:00.148360 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 01:16:00.151510 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7595 01:16:00.158290 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7596 01:16:00.158711 Total UI for P1: 0, mck2ui 16
7597 01:16:00.165106 best dqsien dly found for B0: ( 1, 9, 8)
7598 01:16:00.167960 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7599 01:16:00.171066 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7600 01:16:00.177674 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7601 01:16:00.181257 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 01:16:00.184382 Total UI for P1: 0, mck2ui 16
7603 01:16:00.188116 best dqsien dly found for B1: ( 1, 9, 22)
7604 01:16:00.190970 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7605 01:16:00.194133 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7606 01:16:00.194585
7607 01:16:00.197600 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7608 01:16:00.201130 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7609 01:16:00.204500 [Gating] SW calibration Done
7610 01:16:00.205059 ==
7611 01:16:00.207251 Dram Type= 6, Freq= 0, CH_0, rank 0
7612 01:16:00.210708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7613 01:16:00.214055 ==
7614 01:16:00.214624 RX Vref Scan: 0
7615 01:16:00.215116
7616 01:16:00.217047 RX Vref 0 -> 0, step: 1
7617 01:16:00.217585
7618 01:16:00.218067 RX Delay 0 -> 252, step: 8
7619 01:16:00.223762 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7620 01:16:00.227415 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7621 01:16:00.230478 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7622 01:16:00.234124 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7623 01:16:00.240181 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7624 01:16:00.243880 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7625 01:16:00.246869 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7626 01:16:00.249955 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7627 01:16:00.253806 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7628 01:16:00.260040 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7629 01:16:00.263641 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7630 01:16:00.266818 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7631 01:16:00.269708 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7632 01:16:00.273486 iDelay=192, Bit 13, Center 135 (80 ~ 191) 112
7633 01:16:00.279696 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7634 01:16:00.283268 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7635 01:16:00.284007 ==
7636 01:16:00.286230 Dram Type= 6, Freq= 0, CH_0, rank 0
7637 01:16:00.289431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7638 01:16:00.289850 ==
7639 01:16:00.292941 DQS Delay:
7640 01:16:00.293387 DQS0 = 0, DQS1 = 0
7641 01:16:00.295964 DQM Delay:
7642 01:16:00.296387 DQM0 = 131, DQM1 = 126
7643 01:16:00.296755 DQ Delay:
7644 01:16:00.302762 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7645 01:16:00.306244 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7646 01:16:00.309250 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
7647 01:16:00.312843 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
7648 01:16:00.313258
7649 01:16:00.313583
7650 01:16:00.313887 ==
7651 01:16:00.315769 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 01:16:00.319071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7653 01:16:00.319486 ==
7654 01:16:00.319814
7655 01:16:00.320225
7656 01:16:00.322302 TX Vref Scan disable
7657 01:16:00.325720 == TX Byte 0 ==
7658 01:16:00.329387 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7659 01:16:00.332339 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7660 01:16:00.335864 == TX Byte 1 ==
7661 01:16:00.339160 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7662 01:16:00.342256 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7663 01:16:00.342801 ==
7664 01:16:00.345663 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 01:16:00.352000 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 01:16:00.352451 ==
7667 01:16:00.365908
7668 01:16:00.368923 TX Vref early break, caculate TX vref
7669 01:16:00.372498 TX Vref=16, minBit 1, minWin=22, winSum=369
7670 01:16:00.375572 TX Vref=18, minBit 7, minWin=22, winSum=376
7671 01:16:00.379310 TX Vref=20, minBit 8, minWin=23, winSum=392
7672 01:16:00.382241 TX Vref=22, minBit 3, minWin=24, winSum=400
7673 01:16:00.385094 TX Vref=24, minBit 1, minWin=25, winSum=411
7674 01:16:00.392087 TX Vref=26, minBit 1, minWin=25, winSum=419
7675 01:16:00.395354 TX Vref=28, minBit 2, minWin=25, winSum=422
7676 01:16:00.398502 TX Vref=30, minBit 1, minWin=25, winSum=417
7677 01:16:00.402237 TX Vref=32, minBit 2, minWin=24, winSum=409
7678 01:16:00.405271 TX Vref=34, minBit 1, minWin=24, winSum=404
7679 01:16:00.408960 TX Vref=36, minBit 1, minWin=23, winSum=389
7680 01:16:00.415318 [TxChooseVref] Worse bit 2, Min win 25, Win sum 422, Final Vref 28
7681 01:16:00.415736
7682 01:16:00.418466 Final TX Range 0 Vref 28
7683 01:16:00.418883
7684 01:16:00.419209 ==
7685 01:16:00.421573 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 01:16:00.425311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 01:16:00.428393 ==
7688 01:16:00.428807
7689 01:16:00.429133
7690 01:16:00.429438 TX Vref Scan disable
7691 01:16:00.435098 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7692 01:16:00.435540 == TX Byte 0 ==
7693 01:16:00.438213 u2DelayCellOfst[0]=10 cells (3 PI)
7694 01:16:00.441832 u2DelayCellOfst[1]=14 cells (4 PI)
7695 01:16:00.444948 u2DelayCellOfst[2]=10 cells (3 PI)
7696 01:16:00.448542 u2DelayCellOfst[3]=10 cells (3 PI)
7697 01:16:00.451678 u2DelayCellOfst[4]=7 cells (2 PI)
7698 01:16:00.455044 u2DelayCellOfst[5]=0 cells (0 PI)
7699 01:16:00.458023 u2DelayCellOfst[6]=17 cells (5 PI)
7700 01:16:00.461528 u2DelayCellOfst[7]=14 cells (4 PI)
7701 01:16:00.464366 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7702 01:16:00.468313 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7703 01:16:00.471377 == TX Byte 1 ==
7704 01:16:00.474775 u2DelayCellOfst[8]=0 cells (0 PI)
7705 01:16:00.477601 u2DelayCellOfst[9]=0 cells (0 PI)
7706 01:16:00.481120 u2DelayCellOfst[10]=7 cells (2 PI)
7707 01:16:00.484192 u2DelayCellOfst[11]=3 cells (1 PI)
7708 01:16:00.487972 u2DelayCellOfst[12]=10 cells (3 PI)
7709 01:16:00.491017 u2DelayCellOfst[13]=10 cells (3 PI)
7710 01:16:00.494600 u2DelayCellOfst[14]=14 cells (4 PI)
7711 01:16:00.497520 u2DelayCellOfst[15]=10 cells (3 PI)
7712 01:16:00.501151 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7713 01:16:00.504269 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7714 01:16:00.507402 DramC Write-DBI on
7715 01:16:00.507945 ==
7716 01:16:00.510938 Dram Type= 6, Freq= 0, CH_0, rank 0
7717 01:16:00.514058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7718 01:16:00.514492 ==
7719 01:16:00.514823
7720 01:16:00.515130
7721 01:16:00.517204 TX Vref Scan disable
7722 01:16:00.520361 == TX Byte 0 ==
7723 01:16:00.524142 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7724 01:16:00.524571 == TX Byte 1 ==
7725 01:16:00.530381 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7726 01:16:00.530797 DramC Write-DBI off
7727 01:16:00.531124
7728 01:16:00.531432 [DATLAT]
7729 01:16:00.534154 Freq=1600, CH0 RK0
7730 01:16:00.534597
7731 01:16:00.537414 DATLAT Default: 0xf
7732 01:16:00.537829 0, 0xFFFF, sum = 0
7733 01:16:00.540203 1, 0xFFFF, sum = 0
7734 01:16:00.540650 2, 0xFFFF, sum = 0
7735 01:16:00.543590 3, 0xFFFF, sum = 0
7736 01:16:00.544042 4, 0xFFFF, sum = 0
7737 01:16:00.546557 5, 0xFFFF, sum = 0
7738 01:16:00.547146 6, 0xFFFF, sum = 0
7739 01:16:00.550415 7, 0xFFFF, sum = 0
7740 01:16:00.550836 8, 0xFFFF, sum = 0
7741 01:16:00.553166 9, 0xFFFF, sum = 0
7742 01:16:00.553590 10, 0xFFFF, sum = 0
7743 01:16:00.556691 11, 0xFFFF, sum = 0
7744 01:16:00.557262 12, 0xFFFF, sum = 0
7745 01:16:00.559685 13, 0xFFFF, sum = 0
7746 01:16:00.559964 14, 0x0, sum = 1
7747 01:16:00.562991 15, 0x0, sum = 2
7748 01:16:00.563078 16, 0x0, sum = 3
7749 01:16:00.566059 17, 0x0, sum = 4
7750 01:16:00.566141 best_step = 15
7751 01:16:00.566204
7752 01:16:00.566263 ==
7753 01:16:00.569177 Dram Type= 6, Freq= 0, CH_0, rank 0
7754 01:16:00.576156 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7755 01:16:00.576645 ==
7756 01:16:00.576982 RX Vref Scan: 1
7757 01:16:00.577290
7758 01:16:00.579451 Set Vref Range= 24 -> 127
7759 01:16:00.579863
7760 01:16:00.582745 RX Vref 24 -> 127, step: 1
7761 01:16:00.583156
7762 01:16:00.586347 RX Delay 11 -> 252, step: 4
7763 01:16:00.586867
7764 01:16:00.589194 Set Vref, RX VrefLevel [Byte0]: 24
7765 01:16:00.592685 [Byte1]: 24
7766 01:16:00.593113
7767 01:16:00.596344 Set Vref, RX VrefLevel [Byte0]: 25
7768 01:16:00.599180 [Byte1]: 25
7769 01:16:00.599638
7770 01:16:00.603065 Set Vref, RX VrefLevel [Byte0]: 26
7771 01:16:00.605965 [Byte1]: 26
7772 01:16:00.609546
7773 01:16:00.609959 Set Vref, RX VrefLevel [Byte0]: 27
7774 01:16:00.612779 [Byte1]: 27
7775 01:16:00.616992
7776 01:16:00.617405 Set Vref, RX VrefLevel [Byte0]: 28
7777 01:16:00.620682 [Byte1]: 28
7778 01:16:00.624937
7779 01:16:00.625356 Set Vref, RX VrefLevel [Byte0]: 29
7780 01:16:00.627766 [Byte1]: 29
7781 01:16:00.632612
7782 01:16:00.633027 Set Vref, RX VrefLevel [Byte0]: 30
7783 01:16:00.635569 [Byte1]: 30
7784 01:16:00.639935
7785 01:16:00.640352 Set Vref, RX VrefLevel [Byte0]: 31
7786 01:16:00.643123 [Byte1]: 31
7787 01:16:00.647511
7788 01:16:00.647954 Set Vref, RX VrefLevel [Byte0]: 32
7789 01:16:00.650942 [Byte1]: 32
7790 01:16:00.655044
7791 01:16:00.655459 Set Vref, RX VrefLevel [Byte0]: 33
7792 01:16:00.658200 [Byte1]: 33
7793 01:16:00.662806
7794 01:16:00.663292 Set Vref, RX VrefLevel [Byte0]: 34
7795 01:16:00.666003 [Byte1]: 34
7796 01:16:00.670328
7797 01:16:00.670743 Set Vref, RX VrefLevel [Byte0]: 35
7798 01:16:00.673709 [Byte1]: 35
7799 01:16:00.677797
7800 01:16:00.678213 Set Vref, RX VrefLevel [Byte0]: 36
7801 01:16:00.681538 [Byte1]: 36
7802 01:16:00.685484
7803 01:16:00.685926 Set Vref, RX VrefLevel [Byte0]: 37
7804 01:16:00.689008 [Byte1]: 37
7805 01:16:00.692960
7806 01:16:00.693371 Set Vref, RX VrefLevel [Byte0]: 38
7807 01:16:00.696386 [Byte1]: 38
7808 01:16:00.701102
7809 01:16:00.701530 Set Vref, RX VrefLevel [Byte0]: 39
7810 01:16:00.704156 [Byte1]: 39
7811 01:16:00.708314
7812 01:16:00.708754 Set Vref, RX VrefLevel [Byte0]: 40
7813 01:16:00.711988 [Byte1]: 40
7814 01:16:00.716234
7815 01:16:00.716648 Set Vref, RX VrefLevel [Byte0]: 41
7816 01:16:00.719221 [Byte1]: 41
7817 01:16:00.723698
7818 01:16:00.724171 Set Vref, RX VrefLevel [Byte0]: 42
7819 01:16:00.727220 [Byte1]: 42
7820 01:16:00.731265
7821 01:16:00.731676 Set Vref, RX VrefLevel [Byte0]: 43
7822 01:16:00.734357 [Byte1]: 43
7823 01:16:00.739379
7824 01:16:00.739793 Set Vref, RX VrefLevel [Byte0]: 44
7825 01:16:00.742190 [Byte1]: 44
7826 01:16:00.746855
7827 01:16:00.747376 Set Vref, RX VrefLevel [Byte0]: 45
7828 01:16:00.750029 [Byte1]: 45
7829 01:16:00.754368
7830 01:16:00.754886 Set Vref, RX VrefLevel [Byte0]: 46
7831 01:16:00.758028 [Byte1]: 46
7832 01:16:00.762021
7833 01:16:00.762545 Set Vref, RX VrefLevel [Byte0]: 47
7834 01:16:00.764908 [Byte1]: 47
7835 01:16:00.769874
7836 01:16:00.770396 Set Vref, RX VrefLevel [Byte0]: 48
7837 01:16:00.772797 [Byte1]: 48
7838 01:16:00.777282
7839 01:16:00.777697 Set Vref, RX VrefLevel [Byte0]: 49
7840 01:16:00.780284 [Byte1]: 49
7841 01:16:00.784489
7842 01:16:00.784902 Set Vref, RX VrefLevel [Byte0]: 50
7843 01:16:00.787794 [Byte1]: 50
7844 01:16:00.792280
7845 01:16:00.792696 Set Vref, RX VrefLevel [Byte0]: 51
7846 01:16:00.795571 [Byte1]: 51
7847 01:16:00.799841
7848 01:16:00.800347 Set Vref, RX VrefLevel [Byte0]: 52
7849 01:16:00.803125 [Byte1]: 52
7850 01:16:00.807390
7851 01:16:00.807843 Set Vref, RX VrefLevel [Byte0]: 53
7852 01:16:00.810735 [Byte1]: 53
7853 01:16:00.815007
7854 01:16:00.815421 Set Vref, RX VrefLevel [Byte0]: 54
7855 01:16:00.818384 [Byte1]: 54
7856 01:16:00.823201
7857 01:16:00.823734 Set Vref, RX VrefLevel [Byte0]: 55
7858 01:16:00.826091 [Byte1]: 55
7859 01:16:00.830767
7860 01:16:00.831299 Set Vref, RX VrefLevel [Byte0]: 56
7861 01:16:00.833753 [Byte1]: 56
7862 01:16:00.837977
7863 01:16:00.838405 Set Vref, RX VrefLevel [Byte0]: 57
7864 01:16:00.841059 [Byte1]: 57
7865 01:16:00.845354
7866 01:16:00.845768 Set Vref, RX VrefLevel [Byte0]: 58
7867 01:16:00.849253 [Byte1]: 58
7868 01:16:00.853501
7869 01:16:00.854033 Set Vref, RX VrefLevel [Byte0]: 59
7870 01:16:00.856554 [Byte1]: 59
7871 01:16:00.860937
7872 01:16:00.861462 Set Vref, RX VrefLevel [Byte0]: 60
7873 01:16:00.864151 [Byte1]: 60
7874 01:16:00.868475
7875 01:16:00.868984 Set Vref, RX VrefLevel [Byte0]: 61
7876 01:16:00.871858 [Byte1]: 61
7877 01:16:00.876289
7878 01:16:00.876801 Set Vref, RX VrefLevel [Byte0]: 62
7879 01:16:00.879426 [Byte1]: 62
7880 01:16:00.883472
7881 01:16:00.883969 Set Vref, RX VrefLevel [Byte0]: 63
7882 01:16:00.887027 [Byte1]: 63
7883 01:16:00.891103
7884 01:16:00.891730 Set Vref, RX VrefLevel [Byte0]: 64
7885 01:16:00.894884 [Byte1]: 64
7886 01:16:00.898697
7887 01:16:00.899115 Set Vref, RX VrefLevel [Byte0]: 65
7888 01:16:00.902043 [Byte1]: 65
7889 01:16:00.906634
7890 01:16:00.907159 Set Vref, RX VrefLevel [Byte0]: 66
7891 01:16:00.909531 [Byte1]: 66
7892 01:16:00.913816
7893 01:16:00.914231 Set Vref, RX VrefLevel [Byte0]: 67
7894 01:16:00.917143 [Byte1]: 67
7895 01:16:00.921818
7896 01:16:00.922338 Set Vref, RX VrefLevel [Byte0]: 68
7897 01:16:00.925014 [Byte1]: 68
7898 01:16:00.929241
7899 01:16:00.929762 Set Vref, RX VrefLevel [Byte0]: 69
7900 01:16:00.932640 [Byte1]: 69
7901 01:16:00.936713
7902 01:16:00.937169 Set Vref, RX VrefLevel [Byte0]: 70
7903 01:16:00.940214 [Byte1]: 70
7904 01:16:00.944276
7905 01:16:00.944860 Set Vref, RX VrefLevel [Byte0]: 71
7906 01:16:00.947442 [Byte1]: 71
7907 01:16:00.952347
7908 01:16:00.952809 Set Vref, RX VrefLevel [Byte0]: 72
7909 01:16:00.955454 [Byte1]: 72
7910 01:16:00.959712
7911 01:16:00.960218 Set Vref, RX VrefLevel [Byte0]: 73
7912 01:16:00.962690 [Byte1]: 73
7913 01:16:00.966913
7914 01:16:00.967421 Set Vref, RX VrefLevel [Byte0]: 74
7915 01:16:00.970497 [Byte1]: 74
7916 01:16:00.974607
7917 01:16:00.975156 Set Vref, RX VrefLevel [Byte0]: 75
7918 01:16:00.977816 [Byte1]: 75
7919 01:16:00.982773
7920 01:16:00.983319 Set Vref, RX VrefLevel [Byte0]: 76
7921 01:16:00.985822 [Byte1]: 76
7922 01:16:00.990080
7923 01:16:00.990623 Final RX Vref Byte 0 = 55 to rank0
7924 01:16:00.993386 Final RX Vref Byte 1 = 55 to rank0
7925 01:16:00.996569 Final RX Vref Byte 0 = 55 to rank1
7926 01:16:00.999641 Final RX Vref Byte 1 = 55 to rank1==
7927 01:16:01.003235 Dram Type= 6, Freq= 0, CH_0, rank 0
7928 01:16:01.010154 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7929 01:16:01.010661 ==
7930 01:16:01.010994 DQS Delay:
7931 01:16:01.012854 DQS0 = 0, DQS1 = 0
7932 01:16:01.013283 DQM Delay:
7933 01:16:01.016333 DQM0 = 128, DQM1 = 124
7934 01:16:01.016748 DQ Delay:
7935 01:16:01.019870 DQ0 =130, DQ1 =130, DQ2 =124, DQ3 =124
7936 01:16:01.023053 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =134
7937 01:16:01.026326 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7938 01:16:01.029474 DQ12 =130, DQ13 =130, DQ14 =134, DQ15 =132
7939 01:16:01.030024
7940 01:16:01.030493
7941 01:16:01.030949
7942 01:16:01.032694 [DramC_TX_OE_Calibration] TA2
7943 01:16:01.036038 Original DQ_B0 (3 6) =30, OEN = 27
7944 01:16:01.039376 Original DQ_B1 (3 6) =30, OEN = 27
7945 01:16:01.042329 24, 0x0, End_B0=24 End_B1=24
7946 01:16:01.045288 25, 0x0, End_B0=25 End_B1=25
7947 01:16:01.045398 26, 0x0, End_B0=26 End_B1=26
7948 01:16:01.048505 27, 0x0, End_B0=27 End_B1=27
7949 01:16:01.052226 28, 0x0, End_B0=28 End_B1=28
7950 01:16:01.055168 29, 0x0, End_B0=29 End_B1=29
7951 01:16:01.058823 30, 0x0, End_B0=30 End_B1=30
7952 01:16:01.058917 31, 0x4141, End_B0=30 End_B1=30
7953 01:16:01.062058 Byte0 end_step=30 best_step=27
7954 01:16:01.065607 Byte1 end_step=30 best_step=27
7955 01:16:01.068881 Byte0 TX OE(2T, 0.5T) = (3, 3)
7956 01:16:01.071865 Byte1 TX OE(2T, 0.5T) = (3, 3)
7957 01:16:01.071997
7958 01:16:01.072093
7959 01:16:01.078563 [DQSOSCAuto] RK0, (LSB)MR18= 0x1512, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
7960 01:16:01.081590 CH0 RK0: MR19=303, MR18=1512
7961 01:16:01.088514 CH0_RK0: MR19=0x303, MR18=0x1512, DQSOSC=399, MR23=63, INC=23, DEC=15
7962 01:16:01.088698
7963 01:16:01.091289 ----->DramcWriteLeveling(PI) begin...
7964 01:16:01.091579 ==
7965 01:16:01.094868 Dram Type= 6, Freq= 0, CH_0, rank 1
7966 01:16:01.098042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7967 01:16:01.101274 ==
7968 01:16:01.104548 Write leveling (Byte 0): 35 => 35
7969 01:16:01.104831 Write leveling (Byte 1): 24 => 24
7970 01:16:01.107962 DramcWriteLeveling(PI) end<-----
7971 01:16:01.108302
7972 01:16:01.108591 ==
7973 01:16:01.111110 Dram Type= 6, Freq= 0, CH_0, rank 1
7974 01:16:01.117910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7975 01:16:01.117997 ==
7976 01:16:01.120835 [Gating] SW mode calibration
7977 01:16:01.127496 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7978 01:16:01.131104 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7979 01:16:01.137353 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7980 01:16:01.140795 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7981 01:16:01.143938 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7982 01:16:01.150538 1 4 12 | B1->B0 | 2323 3130 | 0 1 | (0 0) (0 0)
7983 01:16:01.153977 1 4 16 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
7984 01:16:01.157425 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7985 01:16:01.163752 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7986 01:16:01.166824 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7987 01:16:01.170528 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7988 01:16:01.177497 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7989 01:16:01.180456 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7990 01:16:01.183740 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
7991 01:16:01.190564 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7992 01:16:01.193643 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
7993 01:16:01.196991 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 01:16:01.203421 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7995 01:16:01.207073 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7996 01:16:01.209905 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7997 01:16:01.216417 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7998 01:16:01.219974 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7999 01:16:01.223297 1 6 16 | B1->B0 | 3333 4646 | 1 0 | (0 0) (0 0)
8000 01:16:01.230175 1 6 20 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
8001 01:16:01.233442 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8002 01:16:01.236831 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8003 01:16:01.243159 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8004 01:16:01.246185 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8005 01:16:01.249731 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8006 01:16:01.256271 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8007 01:16:01.259752 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8008 01:16:01.263173 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8009 01:16:01.269219 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 01:16:01.272397 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 01:16:01.275605 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 01:16:01.282719 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 01:16:01.285929 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 01:16:01.288990 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 01:16:01.295821 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 01:16:01.299393 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 01:16:01.302556 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 01:16:01.308632 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 01:16:01.312212 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 01:16:01.315616 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 01:16:01.322141 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8022 01:16:01.325303 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8023 01:16:01.328890 Total UI for P1: 0, mck2ui 16
8024 01:16:01.331791 best dqsien dly found for B0: ( 1, 9, 8)
8025 01:16:01.335177 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8026 01:16:01.341736 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8027 01:16:01.345176 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 01:16:01.348550 Total UI for P1: 0, mck2ui 16
8029 01:16:01.351874 best dqsien dly found for B1: ( 1, 9, 18)
8030 01:16:01.354831 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8031 01:16:01.358421 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8032 01:16:01.358837
8033 01:16:01.361614 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8034 01:16:01.365054 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8035 01:16:01.368053 [Gating] SW calibration Done
8036 01:16:01.368467 ==
8037 01:16:01.371762 Dram Type= 6, Freq= 0, CH_0, rank 1
8038 01:16:01.378055 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8039 01:16:01.378494 ==
8040 01:16:01.378841 RX Vref Scan: 0
8041 01:16:01.379151
8042 01:16:01.381464 RX Vref 0 -> 0, step: 1
8043 01:16:01.381879
8044 01:16:01.384660 RX Delay 0 -> 252, step: 8
8045 01:16:01.388309 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8046 01:16:01.391429 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8047 01:16:01.394811 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8048 01:16:01.400749 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8049 01:16:01.404680 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8050 01:16:01.407568 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8051 01:16:01.410593 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8052 01:16:01.414325 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8053 01:16:01.420955 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8054 01:16:01.423725 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8055 01:16:01.427297 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8056 01:16:01.430502 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8057 01:16:01.434222 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8058 01:16:01.440121 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8059 01:16:01.444021 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8060 01:16:01.446815 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8061 01:16:01.447231 ==
8062 01:16:01.450473 Dram Type= 6, Freq= 0, CH_0, rank 1
8063 01:16:01.453604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8064 01:16:01.456970 ==
8065 01:16:01.457385 DQS Delay:
8066 01:16:01.457718 DQS0 = 0, DQS1 = 0
8067 01:16:01.460183 DQM Delay:
8068 01:16:01.460597 DQM0 = 131, DQM1 = 128
8069 01:16:01.463473 DQ Delay:
8070 01:16:01.466572 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8071 01:16:01.470061 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
8072 01:16:01.473183 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8073 01:16:01.476262 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8074 01:16:01.476680
8075 01:16:01.477083
8076 01:16:01.477433 ==
8077 01:16:01.479856 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 01:16:01.482932 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 01:16:01.486378 ==
8080 01:16:01.486795
8081 01:16:01.487123
8082 01:16:01.487425 TX Vref Scan disable
8083 01:16:01.489733 == TX Byte 0 ==
8084 01:16:01.492604 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8085 01:16:01.499245 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8086 01:16:01.499677 == TX Byte 1 ==
8087 01:16:01.502550 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8088 01:16:01.509290 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8089 01:16:01.509711 ==
8090 01:16:01.512484 Dram Type= 6, Freq= 0, CH_0, rank 1
8091 01:16:01.515977 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8092 01:16:01.516397 ==
8093 01:16:01.530947
8094 01:16:01.534445 TX Vref early break, caculate TX vref
8095 01:16:01.537539 TX Vref=16, minBit 9, minWin=22, winSum=379
8096 01:16:01.541236 TX Vref=18, minBit 8, minWin=23, winSum=387
8097 01:16:01.544200 TX Vref=20, minBit 1, minWin=24, winSum=394
8098 01:16:01.547050 TX Vref=22, minBit 2, minWin=24, winSum=405
8099 01:16:01.550754 TX Vref=24, minBit 3, minWin=25, winSum=408
8100 01:16:01.557172 TX Vref=26, minBit 1, minWin=25, winSum=413
8101 01:16:01.560489 TX Vref=28, minBit 2, minWin=25, winSum=413
8102 01:16:01.563637 TX Vref=30, minBit 0, minWin=25, winSum=405
8103 01:16:01.566915 TX Vref=32, minBit 1, minWin=24, winSum=405
8104 01:16:01.570183 TX Vref=34, minBit 1, minWin=24, winSum=392
8105 01:16:01.576921 TX Vref=36, minBit 0, minWin=24, winSum=387
8106 01:16:01.580310 [TxChooseVref] Worse bit 1, Min win 25, Win sum 413, Final Vref 26
8107 01:16:01.580726
8108 01:16:01.583398 Final TX Range 0 Vref 26
8109 01:16:01.583912
8110 01:16:01.584276 ==
8111 01:16:01.586329 Dram Type= 6, Freq= 0, CH_0, rank 1
8112 01:16:01.590049 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8113 01:16:01.592946 ==
8114 01:16:01.593356
8115 01:16:01.593684
8116 01:16:01.593989 TX Vref Scan disable
8117 01:16:01.600099 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8118 01:16:01.600725 == TX Byte 0 ==
8119 01:16:01.603121 u2DelayCellOfst[0]=10 cells (3 PI)
8120 01:16:01.606831 u2DelayCellOfst[1]=14 cells (4 PI)
8121 01:16:01.610382 u2DelayCellOfst[2]=7 cells (2 PI)
8122 01:16:01.613467 u2DelayCellOfst[3]=7 cells (2 PI)
8123 01:16:01.616849 u2DelayCellOfst[4]=7 cells (2 PI)
8124 01:16:01.620228 u2DelayCellOfst[5]=0 cells (0 PI)
8125 01:16:01.623125 u2DelayCellOfst[6]=14 cells (4 PI)
8126 01:16:01.626919 u2DelayCellOfst[7]=14 cells (4 PI)
8127 01:16:01.629836 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8128 01:16:01.633287 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8129 01:16:01.636220 == TX Byte 1 ==
8130 01:16:01.639703 u2DelayCellOfst[8]=0 cells (0 PI)
8131 01:16:01.642832 u2DelayCellOfst[9]=0 cells (0 PI)
8132 01:16:01.646356 u2DelayCellOfst[10]=3 cells (1 PI)
8133 01:16:01.649593 u2DelayCellOfst[11]=3 cells (1 PI)
8134 01:16:01.652537 u2DelayCellOfst[12]=7 cells (2 PI)
8135 01:16:01.652988 u2DelayCellOfst[13]=7 cells (2 PI)
8136 01:16:01.656193 u2DelayCellOfst[14]=10 cells (3 PI)
8137 01:16:01.659212 u2DelayCellOfst[15]=7 cells (2 PI)
8138 01:16:01.666277 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8139 01:16:01.669205 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8140 01:16:01.669664 DramC Write-DBI on
8141 01:16:01.672675 ==
8142 01:16:01.676211 Dram Type= 6, Freq= 0, CH_0, rank 1
8143 01:16:01.678833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8144 01:16:01.679355 ==
8145 01:16:01.679863
8146 01:16:01.680343
8147 01:16:01.682150 TX Vref Scan disable
8148 01:16:01.682682 == TX Byte 0 ==
8149 01:16:01.689408 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8150 01:16:01.689867 == TX Byte 1 ==
8151 01:16:01.692293 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8152 01:16:01.695462 DramC Write-DBI off
8153 01:16:01.695936
8154 01:16:01.696335 [DATLAT]
8155 01:16:01.698894 Freq=1600, CH0 RK1
8156 01:16:01.699436
8157 01:16:01.701730 DATLAT Default: 0xf
8158 01:16:01.702407 0, 0xFFFF, sum = 0
8159 01:16:01.705393 1, 0xFFFF, sum = 0
8160 01:16:01.705906 2, 0xFFFF, sum = 0
8161 01:16:01.708511 3, 0xFFFF, sum = 0
8162 01:16:01.708972 4, 0xFFFF, sum = 0
8163 01:16:01.711666 5, 0xFFFF, sum = 0
8164 01:16:01.712133 6, 0xFFFF, sum = 0
8165 01:16:01.715178 7, 0xFFFF, sum = 0
8166 01:16:01.715728 8, 0xFFFF, sum = 0
8167 01:16:01.718336 9, 0xFFFF, sum = 0
8168 01:16:01.718880 10, 0xFFFF, sum = 0
8169 01:16:01.721380 11, 0xFFFF, sum = 0
8170 01:16:01.721797 12, 0xFFFF, sum = 0
8171 01:16:01.724977 13, 0xFFFF, sum = 0
8172 01:16:01.725392 14, 0x0, sum = 1
8173 01:16:01.728027 15, 0x0, sum = 2
8174 01:16:01.728466 16, 0x0, sum = 3
8175 01:16:01.731690 17, 0x0, sum = 4
8176 01:16:01.732160 best_step = 15
8177 01:16:01.732540
8178 01:16:01.733022 ==
8179 01:16:01.734938 Dram Type= 6, Freq= 0, CH_0, rank 1
8180 01:16:01.741137 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8181 01:16:01.741707 ==
8182 01:16:01.742057 RX Vref Scan: 0
8183 01:16:01.742368
8184 01:16:01.744966 RX Vref 0 -> 0, step: 1
8185 01:16:01.745381
8186 01:16:01.747881 RX Delay 11 -> 252, step: 4
8187 01:16:01.751044 iDelay=191, Bit 0, Center 126 (79 ~ 174) 96
8188 01:16:01.754934 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8189 01:16:01.761728 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8190 01:16:01.764615 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8191 01:16:01.767745 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8192 01:16:01.771337 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8193 01:16:01.774609 iDelay=191, Bit 6, Center 138 (91 ~ 186) 96
8194 01:16:01.781422 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8195 01:16:01.784650 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8196 01:16:01.787483 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8197 01:16:01.791010 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8198 01:16:01.794109 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8199 01:16:01.800538 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8200 01:16:01.803682 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8201 01:16:01.807135 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8202 01:16:01.810520 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8203 01:16:01.810937 ==
8204 01:16:01.814143 Dram Type= 6, Freq= 0, CH_0, rank 1
8205 01:16:01.820351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8206 01:16:01.820769 ==
8207 01:16:01.821170 DQS Delay:
8208 01:16:01.823502 DQS0 = 0, DQS1 = 0
8209 01:16:01.823937 DQM Delay:
8210 01:16:01.827286 DQM0 = 128, DQM1 = 123
8211 01:16:01.827798 DQ Delay:
8212 01:16:01.830280 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8213 01:16:01.833561 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =134
8214 01:16:01.836656 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =118
8215 01:16:01.840379 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =130
8216 01:16:01.840798
8217 01:16:01.841128
8218 01:16:01.841436
8219 01:16:01.843174 [DramC_TX_OE_Calibration] TA2
8220 01:16:01.846351 Original DQ_B0 (3 6) =30, OEN = 27
8221 01:16:01.849923 Original DQ_B1 (3 6) =30, OEN = 27
8222 01:16:01.853565 24, 0x0, End_B0=24 End_B1=24
8223 01:16:01.856437 25, 0x0, End_B0=25 End_B1=25
8224 01:16:01.856865 26, 0x0, End_B0=26 End_B1=26
8225 01:16:01.860271 27, 0x0, End_B0=27 End_B1=27
8226 01:16:01.863426 28, 0x0, End_B0=28 End_B1=28
8227 01:16:01.867120 29, 0x0, End_B0=29 End_B1=29
8228 01:16:01.870109 30, 0x0, End_B0=30 End_B1=30
8229 01:16:01.870630 31, 0x4545, End_B0=30 End_B1=30
8230 01:16:01.873041 Byte0 end_step=30 best_step=27
8231 01:16:01.876219 Byte1 end_step=30 best_step=27
8232 01:16:01.879783 Byte0 TX OE(2T, 0.5T) = (3, 3)
8233 01:16:01.883098 Byte1 TX OE(2T, 0.5T) = (3, 3)
8234 01:16:01.883612
8235 01:16:01.884012
8236 01:16:01.889492 [DQSOSCAuto] RK1, (LSB)MR18= 0x1413, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8237 01:16:01.892658 CH0 RK1: MR19=303, MR18=1413
8238 01:16:01.899225 CH0_RK1: MR19=0x303, MR18=0x1413, DQSOSC=399, MR23=63, INC=23, DEC=15
8239 01:16:01.902735 [RxdqsGatingPostProcess] freq 1600
8240 01:16:01.908872 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8241 01:16:01.912397 best DQS0 dly(2T, 0.5T) = (1, 1)
8242 01:16:01.912841 best DQS1 dly(2T, 0.5T) = (1, 1)
8243 01:16:01.915571 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8244 01:16:01.918647 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8245 01:16:01.922266 best DQS0 dly(2T, 0.5T) = (1, 1)
8246 01:16:01.925811 best DQS1 dly(2T, 0.5T) = (1, 1)
8247 01:16:01.928810 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8248 01:16:01.932018 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8249 01:16:01.935608 Pre-setting of DQS Precalculation
8250 01:16:01.941380 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8251 01:16:01.941485 ==
8252 01:16:01.944884 Dram Type= 6, Freq= 0, CH_1, rank 0
8253 01:16:01.947906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8254 01:16:01.948002 ==
8255 01:16:01.954727 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8256 01:16:01.958191 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8257 01:16:01.961554 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8258 01:16:01.968017 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8259 01:16:01.976874 [CA 0] Center 41 (12~71) winsize 60
8260 01:16:01.979895 [CA 1] Center 41 (11~72) winsize 62
8261 01:16:01.983567 [CA 2] Center 38 (9~67) winsize 59
8262 01:16:01.986582 [CA 3] Center 37 (8~66) winsize 59
8263 01:16:01.989769 [CA 4] Center 37 (8~67) winsize 60
8264 01:16:01.993197 [CA 5] Center 36 (7~66) winsize 60
8265 01:16:01.993400
8266 01:16:01.996305 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8267 01:16:01.996616
8268 01:16:01.999700 [CATrainingPosCal] consider 1 rank data
8269 01:16:02.002757 u2DelayCellTimex100 = 275/100 ps
8270 01:16:02.009690 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8271 01:16:02.012767 CA1 delay=41 (11~72),Diff = 5 PI (17 cell)
8272 01:16:02.016270 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8273 01:16:02.019180 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8274 01:16:02.022874 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8275 01:16:02.025714 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8276 01:16:02.025812
8277 01:16:02.028984 CA PerBit enable=1, Macro0, CA PI delay=36
8278 01:16:02.029065
8279 01:16:02.032490 [CBTSetCACLKResult] CA Dly = 36
8280 01:16:02.035844 CS Dly: 7 (0~38)
8281 01:16:02.039143 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8282 01:16:02.042771 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8283 01:16:02.042851 ==
8284 01:16:02.045746 Dram Type= 6, Freq= 0, CH_1, rank 1
8285 01:16:02.052255 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8286 01:16:02.052336 ==
8287 01:16:02.055465 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8288 01:16:02.062307 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8289 01:16:02.065298 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8290 01:16:02.072012 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8291 01:16:02.079568 [CA 0] Center 42 (12~72) winsize 61
8292 01:16:02.083287 [CA 1] Center 41 (12~71) winsize 60
8293 01:16:02.086498 [CA 2] Center 37 (8~67) winsize 60
8294 01:16:02.089899 [CA 3] Center 36 (7~65) winsize 59
8295 01:16:02.093360 [CA 4] Center 37 (7~67) winsize 61
8296 01:16:02.096062 [CA 5] Center 35 (6~65) winsize 60
8297 01:16:02.096242
8298 01:16:02.099527 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8299 01:16:02.099704
8300 01:16:02.106294 [CATrainingPosCal] consider 2 rank data
8301 01:16:02.106549 u2DelayCellTimex100 = 275/100 ps
8302 01:16:02.113102 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8303 01:16:02.116206 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8304 01:16:02.119135 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8305 01:16:02.122664 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8306 01:16:02.125705 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8307 01:16:02.129383 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8308 01:16:02.129814
8309 01:16:02.132454 CA PerBit enable=1, Macro0, CA PI delay=36
8310 01:16:02.133023
8311 01:16:02.135554 [CBTSetCACLKResult] CA Dly = 36
8312 01:16:02.139238 CS Dly: 9 (0~42)
8313 01:16:02.142630 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8314 01:16:02.145460 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8315 01:16:02.145897
8316 01:16:02.148991 ----->DramcWriteLeveling(PI) begin...
8317 01:16:02.149503 ==
8318 01:16:02.152029 Dram Type= 6, Freq= 0, CH_1, rank 0
8319 01:16:02.158485 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8320 01:16:02.158897 ==
8321 01:16:02.161942 Write leveling (Byte 0): 24 => 24
8322 01:16:02.165578 Write leveling (Byte 1): 26 => 26
8323 01:16:02.168666 DramcWriteLeveling(PI) end<-----
8324 01:16:02.169073
8325 01:16:02.169394 ==
8326 01:16:02.172012 Dram Type= 6, Freq= 0, CH_1, rank 0
8327 01:16:02.175329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8328 01:16:02.175782 ==
8329 01:16:02.178667 [Gating] SW mode calibration
8330 01:16:02.184953 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8331 01:16:02.191833 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8332 01:16:02.194751 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 01:16:02.198538 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 01:16:02.204912 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 01:16:02.208419 1 4 12 | B1->B0 | 2323 2c2c | 0 1 | (1 1) (1 1)
8336 01:16:02.211548 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8337 01:16:02.217808 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8338 01:16:02.220946 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8339 01:16:02.224514 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8340 01:16:02.231144 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8341 01:16:02.234184 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8342 01:16:02.237388 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8343 01:16:02.244144 1 5 12 | B1->B0 | 3131 2525 | 1 0 | (1 0) (1 0)
8344 01:16:02.247066 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 01:16:02.250860 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 01:16:02.257273 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 01:16:02.260618 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 01:16:02.264030 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 01:16:02.270679 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8350 01:16:02.273484 1 6 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8351 01:16:02.277152 1 6 12 | B1->B0 | 3737 4545 | 0 0 | (0 0) (0 0)
8352 01:16:02.283353 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 01:16:02.287043 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 01:16:02.290250 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 01:16:02.297050 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8356 01:16:02.300006 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8357 01:16:02.303059 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8358 01:16:02.309742 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8359 01:16:02.312877 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8360 01:16:02.316346 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8361 01:16:02.322802 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 01:16:02.326384 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 01:16:02.329580 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 01:16:02.335836 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 01:16:02.339521 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 01:16:02.342394 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 01:16:02.349424 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 01:16:02.352389 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 01:16:02.356154 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 01:16:02.362693 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 01:16:02.365534 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 01:16:02.368696 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 01:16:02.375561 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 01:16:02.379226 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8375 01:16:02.382078 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8376 01:16:02.389045 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8377 01:16:02.392105 Total UI for P1: 0, mck2ui 16
8378 01:16:02.395353 best dqsien dly found for B0: ( 1, 9, 10)
8379 01:16:02.398759 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 01:16:02.402156 Total UI for P1: 0, mck2ui 16
8381 01:16:02.405164 best dqsien dly found for B1: ( 1, 9, 14)
8382 01:16:02.408391 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8383 01:16:02.411610 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8384 01:16:02.412215
8385 01:16:02.415234 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8386 01:16:02.421853 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8387 01:16:02.422365 [Gating] SW calibration Done
8388 01:16:02.422702 ==
8389 01:16:02.425206 Dram Type= 6, Freq= 0, CH_1, rank 0
8390 01:16:02.431801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8391 01:16:02.432289 ==
8392 01:16:02.432627 RX Vref Scan: 0
8393 01:16:02.432940
8394 01:16:02.434757 RX Vref 0 -> 0, step: 1
8395 01:16:02.435185
8396 01:16:02.438391 RX Delay 0 -> 252, step: 8
8397 01:16:02.441374 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8398 01:16:02.444988 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8399 01:16:02.448206 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8400 01:16:02.454732 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8401 01:16:02.457628 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8402 01:16:02.461189 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8403 01:16:02.464650 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8404 01:16:02.467398 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8405 01:16:02.474529 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8406 01:16:02.477871 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8407 01:16:02.480869 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8408 01:16:02.484015 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8409 01:16:02.490815 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8410 01:16:02.494274 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8411 01:16:02.497220 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8412 01:16:02.500480 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8413 01:16:02.500895 ==
8414 01:16:02.504137 Dram Type= 6, Freq= 0, CH_1, rank 0
8415 01:16:02.510744 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 01:16:02.511249 ==
8417 01:16:02.511581 DQS Delay:
8418 01:16:02.512106 DQS0 = 0, DQS1 = 0
8419 01:16:02.513971 DQM Delay:
8420 01:16:02.514383 DQM0 = 135, DQM1 = 131
8421 01:16:02.517333 DQ Delay:
8422 01:16:02.520394 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8423 01:16:02.523499 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8424 01:16:02.527390 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8425 01:16:02.530446 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8426 01:16:02.530887
8427 01:16:02.531214
8428 01:16:02.531520 ==
8429 01:16:02.533409 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 01:16:02.537124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 01:16:02.539879 ==
8432 01:16:02.540342
8433 01:16:02.540751
8434 01:16:02.541067 TX Vref Scan disable
8435 01:16:02.543665 == TX Byte 0 ==
8436 01:16:02.546754 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8437 01:16:02.549851 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8438 01:16:02.553702 == TX Byte 1 ==
8439 01:16:02.556429 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8440 01:16:02.562907 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8441 01:16:02.563491 ==
8442 01:16:02.566608 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 01:16:02.569719 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8444 01:16:02.570298 ==
8445 01:16:02.582999
8446 01:16:02.586685 TX Vref early break, caculate TX vref
8447 01:16:02.589549 TX Vref=16, minBit 8, minWin=21, winSum=367
8448 01:16:02.592593 TX Vref=18, minBit 9, minWin=22, winSum=378
8449 01:16:02.596224 TX Vref=20, minBit 3, minWin=23, winSum=381
8450 01:16:02.599066 TX Vref=22, minBit 8, minWin=23, winSum=397
8451 01:16:02.602703 TX Vref=24, minBit 8, minWin=24, winSum=409
8452 01:16:02.609490 TX Vref=26, minBit 3, minWin=25, winSum=412
8453 01:16:02.612442 TX Vref=28, minBit 0, minWin=25, winSum=417
8454 01:16:02.616288 TX Vref=30, minBit 0, minWin=25, winSum=416
8455 01:16:02.619206 TX Vref=32, minBit 11, minWin=24, winSum=406
8456 01:16:02.622699 TX Vref=34, minBit 9, minWin=23, winSum=397
8457 01:16:02.628658 TX Vref=36, minBit 0, minWin=23, winSum=388
8458 01:16:02.631596 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
8459 01:16:02.631703
8460 01:16:02.635242 Final TX Range 0 Vref 28
8461 01:16:02.635324
8462 01:16:02.635388 ==
8463 01:16:02.638234 Dram Type= 6, Freq= 0, CH_1, rank 0
8464 01:16:02.644947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8465 01:16:02.645053 ==
8466 01:16:02.645145
8467 01:16:02.645233
8468 01:16:02.645319 TX Vref Scan disable
8469 01:16:02.652200 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8470 01:16:02.652309 == TX Byte 0 ==
8471 01:16:02.655283 u2DelayCellOfst[0]=17 cells (5 PI)
8472 01:16:02.658377 u2DelayCellOfst[1]=10 cells (3 PI)
8473 01:16:02.662178 u2DelayCellOfst[2]=0 cells (0 PI)
8474 01:16:02.665171 u2DelayCellOfst[3]=7 cells (2 PI)
8475 01:16:02.668082 u2DelayCellOfst[4]=10 cells (3 PI)
8476 01:16:02.671646 u2DelayCellOfst[5]=17 cells (5 PI)
8477 01:16:02.674805 u2DelayCellOfst[6]=14 cells (4 PI)
8478 01:16:02.678277 u2DelayCellOfst[7]=7 cells (2 PI)
8479 01:16:02.681999 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8480 01:16:02.684967 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8481 01:16:02.688246 == TX Byte 1 ==
8482 01:16:02.691515 u2DelayCellOfst[8]=0 cells (0 PI)
8483 01:16:02.694636 u2DelayCellOfst[9]=3 cells (1 PI)
8484 01:16:02.698058 u2DelayCellOfst[10]=10 cells (3 PI)
8485 01:16:02.701173 u2DelayCellOfst[11]=3 cells (1 PI)
8486 01:16:02.704747 u2DelayCellOfst[12]=14 cells (4 PI)
8487 01:16:02.707801 u2DelayCellOfst[13]=14 cells (4 PI)
8488 01:16:02.710956 u2DelayCellOfst[14]=17 cells (5 PI)
8489 01:16:02.714651 u2DelayCellOfst[15]=17 cells (5 PI)
8490 01:16:02.717619 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8491 01:16:02.721362 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8492 01:16:02.724391 DramC Write-DBI on
8493 01:16:02.724590 ==
8494 01:16:02.728009 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 01:16:02.731069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8496 01:16:02.731394 ==
8497 01:16:02.731661
8498 01:16:02.731913
8499 01:16:02.734220 TX Vref Scan disable
8500 01:16:02.737610 == TX Byte 0 ==
8501 01:16:02.741132 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8502 01:16:02.741564 == TX Byte 1 ==
8503 01:16:02.747964 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8504 01:16:02.748399 DramC Write-DBI off
8505 01:16:02.748737
8506 01:16:02.749046 [DATLAT]
8507 01:16:02.751056 Freq=1600, CH1 RK0
8508 01:16:02.751471
8509 01:16:02.754846 DATLAT Default: 0xf
8510 01:16:02.755376 0, 0xFFFF, sum = 0
8511 01:16:02.757450 1, 0xFFFF, sum = 0
8512 01:16:02.757872 2, 0xFFFF, sum = 0
8513 01:16:02.761024 3, 0xFFFF, sum = 0
8514 01:16:02.761449 4, 0xFFFF, sum = 0
8515 01:16:02.764081 5, 0xFFFF, sum = 0
8516 01:16:02.764501 6, 0xFFFF, sum = 0
8517 01:16:02.767933 7, 0xFFFF, sum = 0
8518 01:16:02.768358 8, 0xFFFF, sum = 0
8519 01:16:02.771040 9, 0xFFFF, sum = 0
8520 01:16:02.771563 10, 0xFFFF, sum = 0
8521 01:16:02.773901 11, 0xFFFF, sum = 0
8522 01:16:02.774325 12, 0xFFFF, sum = 0
8523 01:16:02.777558 13, 0xFFFF, sum = 0
8524 01:16:02.777980 14, 0x0, sum = 1
8525 01:16:02.780625 15, 0x0, sum = 2
8526 01:16:02.781044 16, 0x0, sum = 3
8527 01:16:02.784219 17, 0x0, sum = 4
8528 01:16:02.784640 best_step = 15
8529 01:16:02.784971
8530 01:16:02.785278 ==
8531 01:16:02.787625 Dram Type= 6, Freq= 0, CH_1, rank 0
8532 01:16:02.793773 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8533 01:16:02.794193 ==
8534 01:16:02.794522 RX Vref Scan: 1
8535 01:16:02.794865
8536 01:16:02.797507 Set Vref Range= 24 -> 127
8537 01:16:02.797981
8538 01:16:02.800573 RX Vref 24 -> 127, step: 1
8539 01:16:02.800986
8540 01:16:02.804041 RX Delay 19 -> 252, step: 4
8541 01:16:02.804473
8542 01:16:02.807175 Set Vref, RX VrefLevel [Byte0]: 24
8543 01:16:02.810391 [Byte1]: 24
8544 01:16:02.810844
8545 01:16:02.813692 Set Vref, RX VrefLevel [Byte0]: 25
8546 01:16:02.816862 [Byte1]: 25
8547 01:16:02.817279
8548 01:16:02.820065 Set Vref, RX VrefLevel [Byte0]: 26
8549 01:16:02.823570 [Byte1]: 26
8550 01:16:02.824015
8551 01:16:02.826609 Set Vref, RX VrefLevel [Byte0]: 27
8552 01:16:02.830147 [Byte1]: 27
8553 01:16:02.834718
8554 01:16:02.835238 Set Vref, RX VrefLevel [Byte0]: 28
8555 01:16:02.837431 [Byte1]: 28
8556 01:16:02.841675
8557 01:16:02.842088 Set Vref, RX VrefLevel [Byte0]: 29
8558 01:16:02.844802 [Byte1]: 29
8559 01:16:02.849164
8560 01:16:02.849578 Set Vref, RX VrefLevel [Byte0]: 30
8561 01:16:02.852661 [Byte1]: 30
8562 01:16:02.856995
8563 01:16:02.857408 Set Vref, RX VrefLevel [Byte0]: 31
8564 01:16:02.859957 [Byte1]: 31
8565 01:16:02.864306
8566 01:16:02.864720 Set Vref, RX VrefLevel [Byte0]: 32
8567 01:16:02.867843 [Byte1]: 32
8568 01:16:02.872101
8569 01:16:02.872512 Set Vref, RX VrefLevel [Byte0]: 33
8570 01:16:02.875168 [Byte1]: 33
8571 01:16:02.879459
8572 01:16:02.879875 Set Vref, RX VrefLevel [Byte0]: 34
8573 01:16:02.883141 [Byte1]: 34
8574 01:16:02.887181
8575 01:16:02.887593 Set Vref, RX VrefLevel [Byte0]: 35
8576 01:16:02.890642 [Byte1]: 35
8577 01:16:02.895019
8578 01:16:02.895613 Set Vref, RX VrefLevel [Byte0]: 36
8579 01:16:02.898046 [Byte1]: 36
8580 01:16:02.902222
8581 01:16:02.902687 Set Vref, RX VrefLevel [Byte0]: 37
8582 01:16:02.905326 [Byte1]: 37
8583 01:16:02.910205
8584 01:16:02.910637 Set Vref, RX VrefLevel [Byte0]: 38
8585 01:16:02.913269 [Byte1]: 38
8586 01:16:02.917288
8587 01:16:02.917699 Set Vref, RX VrefLevel [Byte0]: 39
8588 01:16:02.920560 [Byte1]: 39
8589 01:16:02.925176
8590 01:16:02.925611 Set Vref, RX VrefLevel [Byte0]: 40
8591 01:16:02.928145 [Byte1]: 40
8592 01:16:02.932350
8593 01:16:02.932763 Set Vref, RX VrefLevel [Byte0]: 41
8594 01:16:02.936129 [Byte1]: 41
8595 01:16:02.939992
8596 01:16:02.940407 Set Vref, RX VrefLevel [Byte0]: 42
8597 01:16:02.943811 [Byte1]: 42
8598 01:16:02.947575
8599 01:16:02.948026 Set Vref, RX VrefLevel [Byte0]: 43
8600 01:16:02.951194 [Byte1]: 43
8601 01:16:02.955382
8602 01:16:02.955798 Set Vref, RX VrefLevel [Byte0]: 44
8603 01:16:02.958298 [Byte1]: 44
8604 01:16:02.963173
8605 01:16:02.963583 Set Vref, RX VrefLevel [Byte0]: 45
8606 01:16:02.966189 [Byte1]: 45
8607 01:16:02.970396
8608 01:16:02.970809 Set Vref, RX VrefLevel [Byte0]: 46
8609 01:16:02.974067 [Byte1]: 46
8610 01:16:02.978186
8611 01:16:02.978600 Set Vref, RX VrefLevel [Byte0]: 47
8612 01:16:02.981363 [Byte1]: 47
8613 01:16:02.985685
8614 01:16:02.986101 Set Vref, RX VrefLevel [Byte0]: 48
8615 01:16:02.988758 [Byte1]: 48
8616 01:16:02.993005
8617 01:16:02.993417 Set Vref, RX VrefLevel [Byte0]: 49
8618 01:16:02.996393 [Byte1]: 49
8619 01:16:03.000899
8620 01:16:03.001313 Set Vref, RX VrefLevel [Byte0]: 50
8621 01:16:03.004315 [Byte1]: 50
8622 01:16:03.008543
8623 01:16:03.008960 Set Vref, RX VrefLevel [Byte0]: 51
8624 01:16:03.011662 [Byte1]: 51
8625 01:16:03.015696
8626 01:16:03.016158 Set Vref, RX VrefLevel [Byte0]: 52
8627 01:16:03.018817 [Byte1]: 52
8628 01:16:03.023674
8629 01:16:03.024185 Set Vref, RX VrefLevel [Byte0]: 53
8630 01:16:03.026800 [Byte1]: 53
8631 01:16:03.030869
8632 01:16:03.031313 Set Vref, RX VrefLevel [Byte0]: 54
8633 01:16:03.034100 [Byte1]: 54
8634 01:16:03.038683
8635 01:16:03.039105 Set Vref, RX VrefLevel [Byte0]: 55
8636 01:16:03.042248 [Byte1]: 55
8637 01:16:03.046041
8638 01:16:03.046456 Set Vref, RX VrefLevel [Byte0]: 56
8639 01:16:03.049450 [Byte1]: 56
8640 01:16:03.053664
8641 01:16:03.054075 Set Vref, RX VrefLevel [Byte0]: 57
8642 01:16:03.057332 [Byte1]: 57
8643 01:16:03.061656
8644 01:16:03.062207 Set Vref, RX VrefLevel [Byte0]: 58
8645 01:16:03.064402 [Byte1]: 58
8646 01:16:03.069417
8647 01:16:03.069833 Set Vref, RX VrefLevel [Byte0]: 59
8648 01:16:03.072361 [Byte1]: 59
8649 01:16:03.076618
8650 01:16:03.077034 Set Vref, RX VrefLevel [Byte0]: 60
8651 01:16:03.079659 [Byte1]: 60
8652 01:16:03.084415
8653 01:16:03.084831 Set Vref, RX VrefLevel [Byte0]: 61
8654 01:16:03.087423 [Byte1]: 61
8655 01:16:03.091713
8656 01:16:03.092222 Set Vref, RX VrefLevel [Byte0]: 62
8657 01:16:03.095160 [Byte1]: 62
8658 01:16:03.099416
8659 01:16:03.099927 Set Vref, RX VrefLevel [Byte0]: 63
8660 01:16:03.102551 [Byte1]: 63
8661 01:16:03.106957
8662 01:16:03.107437 Set Vref, RX VrefLevel [Byte0]: 64
8663 01:16:03.110118 [Byte1]: 64
8664 01:16:03.114552
8665 01:16:03.115074 Set Vref, RX VrefLevel [Byte0]: 65
8666 01:16:03.117849 [Byte1]: 65
8667 01:16:03.121870
8668 01:16:03.122401 Set Vref, RX VrefLevel [Byte0]: 66
8669 01:16:03.125577 [Byte1]: 66
8670 01:16:03.129440
8671 01:16:03.130015 Set Vref, RX VrefLevel [Byte0]: 67
8672 01:16:03.133159 [Byte1]: 67
8673 01:16:03.137413
8674 01:16:03.137828 Set Vref, RX VrefLevel [Byte0]: 68
8675 01:16:03.140772 [Byte1]: 68
8676 01:16:03.144536
8677 01:16:03.144950 Set Vref, RX VrefLevel [Byte0]: 69
8678 01:16:03.147868 [Byte1]: 69
8679 01:16:03.152418
8680 01:16:03.152836 Set Vref, RX VrefLevel [Byte0]: 70
8681 01:16:03.155234 [Byte1]: 70
8682 01:16:03.160048
8683 01:16:03.160482 Final RX Vref Byte 0 = 56 to rank0
8684 01:16:03.162810 Final RX Vref Byte 1 = 60 to rank0
8685 01:16:03.166400 Final RX Vref Byte 0 = 56 to rank1
8686 01:16:03.169963 Final RX Vref Byte 1 = 60 to rank1==
8687 01:16:03.172990 Dram Type= 6, Freq= 0, CH_1, rank 0
8688 01:16:03.179651 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8689 01:16:03.180188 ==
8690 01:16:03.180603 DQS Delay:
8691 01:16:03.182780 DQS0 = 0, DQS1 = 0
8692 01:16:03.183206 DQM Delay:
8693 01:16:03.183617 DQM0 = 132, DQM1 = 129
8694 01:16:03.186219 DQ Delay:
8695 01:16:03.189212 DQ0 =142, DQ1 =130, DQ2 =118, DQ3 =130
8696 01:16:03.192344 DQ4 =128, DQ5 =142, DQ6 =146, DQ7 =126
8697 01:16:03.196086 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =122
8698 01:16:03.199003 DQ12 =140, DQ13 =140, DQ14 =136, DQ15 =140
8699 01:16:03.199446
8700 01:16:03.199790
8701 01:16:03.200141
8702 01:16:03.202524 [DramC_TX_OE_Calibration] TA2
8703 01:16:03.206048 Original DQ_B0 (3 6) =30, OEN = 27
8704 01:16:03.209095 Original DQ_B1 (3 6) =30, OEN = 27
8705 01:16:03.212329 24, 0x0, End_B0=24 End_B1=24
8706 01:16:03.215576 25, 0x0, End_B0=25 End_B1=25
8707 01:16:03.216173 26, 0x0, End_B0=26 End_B1=26
8708 01:16:03.219197 27, 0x0, End_B0=27 End_B1=27
8709 01:16:03.222319 28, 0x0, End_B0=28 End_B1=28
8710 01:16:03.225684 29, 0x0, End_B0=29 End_B1=29
8711 01:16:03.226110 30, 0x0, End_B0=30 End_B1=30
8712 01:16:03.228664 31, 0x4545, End_B0=30 End_B1=30
8713 01:16:03.232138 Byte0 end_step=30 best_step=27
8714 01:16:03.235197 Byte1 end_step=30 best_step=27
8715 01:16:03.238888 Byte0 TX OE(2T, 0.5T) = (3, 3)
8716 01:16:03.241655 Byte1 TX OE(2T, 0.5T) = (3, 3)
8717 01:16:03.241737
8718 01:16:03.241801
8719 01:16:03.248179 [DQSOSCAuto] RK0, (LSB)MR18= 0x812, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 405 ps
8720 01:16:03.251662 CH1 RK0: MR19=303, MR18=812
8721 01:16:03.257974 CH1_RK0: MR19=0x303, MR18=0x812, DQSOSC=400, MR23=63, INC=23, DEC=15
8722 01:16:03.258057
8723 01:16:03.261332 ----->DramcWriteLeveling(PI) begin...
8724 01:16:03.261421 ==
8725 01:16:03.264631 Dram Type= 6, Freq= 0, CH_1, rank 1
8726 01:16:03.267656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8727 01:16:03.267738 ==
8728 01:16:03.271229 Write leveling (Byte 0): 21 => 21
8729 01:16:03.274607 Write leveling (Byte 1): 26 => 26
8730 01:16:03.277709 DramcWriteLeveling(PI) end<-----
8731 01:16:03.277791
8732 01:16:03.277855 ==
8733 01:16:03.281416 Dram Type= 6, Freq= 0, CH_1, rank 1
8734 01:16:03.287365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8735 01:16:03.287447 ==
8736 01:16:03.287512 [Gating] SW mode calibration
8737 01:16:03.297137 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8738 01:16:03.300858 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8739 01:16:03.307217 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8740 01:16:03.310719 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8741 01:16:03.313824 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8742 01:16:03.320250 1 4 12 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8743 01:16:03.323674 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8744 01:16:03.326962 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8745 01:16:03.333559 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8746 01:16:03.336753 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8747 01:16:03.340160 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8748 01:16:03.346822 1 5 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8749 01:16:03.350069 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8750 01:16:03.353208 1 5 12 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8751 01:16:03.359673 1 5 16 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
8752 01:16:03.363291 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 01:16:03.366691 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 01:16:03.373008 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 01:16:03.376341 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 01:16:03.379611 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8757 01:16:03.386301 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8758 01:16:03.389915 1 6 12 | B1->B0 | 2828 4646 | 1 0 | (0 0) (0 0)
8759 01:16:03.393225 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8760 01:16:03.399594 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8761 01:16:03.402555 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8762 01:16:03.406271 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8763 01:16:03.413384 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8764 01:16:03.416065 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8765 01:16:03.419182 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8766 01:16:03.426465 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8767 01:16:03.429081 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8768 01:16:03.432573 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 01:16:03.438959 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 01:16:03.442281 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 01:16:03.445465 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 01:16:03.452532 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 01:16:03.455651 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 01:16:03.459424 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 01:16:03.465102 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 01:16:03.468795 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 01:16:03.471755 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 01:16:03.478386 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 01:16:03.481464 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 01:16:03.485095 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8781 01:16:03.491614 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8782 01:16:03.495027 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8783 01:16:03.498482 Total UI for P1: 0, mck2ui 16
8784 01:16:03.501272 best dqsien dly found for B0: ( 1, 9, 6)
8785 01:16:03.504856 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 01:16:03.507950 Total UI for P1: 0, mck2ui 16
8787 01:16:03.510906 best dqsien dly found for B1: ( 1, 9, 12)
8788 01:16:03.514645 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8789 01:16:03.517636 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8790 01:16:03.517865
8791 01:16:03.524261 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8792 01:16:03.527242 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8793 01:16:03.530947 [Gating] SW calibration Done
8794 01:16:03.531142 ==
8795 01:16:03.533803 Dram Type= 6, Freq= 0, CH_1, rank 1
8796 01:16:03.537344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8797 01:16:03.537450 ==
8798 01:16:03.537517 RX Vref Scan: 0
8799 01:16:03.537579
8800 01:16:03.540931 RX Vref 0 -> 0, step: 1
8801 01:16:03.541018
8802 01:16:03.543723 RX Delay 0 -> 252, step: 8
8803 01:16:03.547209 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8804 01:16:03.550636 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8805 01:16:03.557090 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8806 01:16:03.560582 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8807 01:16:03.564043 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8808 01:16:03.566978 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8809 01:16:03.570780 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8810 01:16:03.576822 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8811 01:16:03.580231 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8812 01:16:03.583608 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8813 01:16:03.587082 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8814 01:16:03.593258 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8815 01:16:03.596279 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8816 01:16:03.600007 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8817 01:16:03.603249 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8818 01:16:03.606370 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8819 01:16:03.606450 ==
8820 01:16:03.609638 Dram Type= 6, Freq= 0, CH_1, rank 1
8821 01:16:03.616289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8822 01:16:03.616371 ==
8823 01:16:03.616437 DQS Delay:
8824 01:16:03.619418 DQS0 = 0, DQS1 = 0
8825 01:16:03.619514 DQM Delay:
8826 01:16:03.623099 DQM0 = 137, DQM1 = 130
8827 01:16:03.623173 DQ Delay:
8828 01:16:03.626122 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =135
8829 01:16:03.629695 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =135
8830 01:16:03.632648 DQ8 =115, DQ9 =115, DQ10 =135, DQ11 =123
8831 01:16:03.636510 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8832 01:16:03.636600
8833 01:16:03.636671
8834 01:16:03.636734 ==
8835 01:16:03.639491 Dram Type= 6, Freq= 0, CH_1, rank 1
8836 01:16:03.646091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8837 01:16:03.646198 ==
8838 01:16:03.646276
8839 01:16:03.646349
8840 01:16:03.646419 TX Vref Scan disable
8841 01:16:03.649753 == TX Byte 0 ==
8842 01:16:03.652895 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8843 01:16:03.659471 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8844 01:16:03.659590 == TX Byte 1 ==
8845 01:16:03.662527 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8846 01:16:03.669798 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8847 01:16:03.670232 ==
8848 01:16:03.672810 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 01:16:03.676102 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 01:16:03.676532 ==
8851 01:16:03.690416
8852 01:16:03.693755 TX Vref early break, caculate TX vref
8853 01:16:03.696924 TX Vref=16, minBit 9, minWin=22, winSum=376
8854 01:16:03.699788 TX Vref=18, minBit 9, minWin=22, winSum=383
8855 01:16:03.703514 TX Vref=20, minBit 9, minWin=22, winSum=394
8856 01:16:03.706475 TX Vref=22, minBit 9, minWin=23, winSum=403
8857 01:16:03.710159 TX Vref=24, minBit 9, minWin=23, winSum=405
8858 01:16:03.716863 TX Vref=26, minBit 9, minWin=24, winSum=416
8859 01:16:03.720129 TX Vref=28, minBit 9, minWin=25, winSum=417
8860 01:16:03.722943 TX Vref=30, minBit 9, minWin=24, winSum=415
8861 01:16:03.726217 TX Vref=32, minBit 8, minWin=24, winSum=408
8862 01:16:03.729700 TX Vref=34, minBit 0, minWin=24, winSum=399
8863 01:16:03.736591 TX Vref=36, minBit 9, minWin=23, winSum=392
8864 01:16:03.739399 [TxChooseVref] Worse bit 9, Min win 25, Win sum 417, Final Vref 28
8865 01:16:03.739954
8866 01:16:03.743011 Final TX Range 0 Vref 28
8867 01:16:03.743672
8868 01:16:03.744150 ==
8869 01:16:03.746043 Dram Type= 6, Freq= 0, CH_1, rank 1
8870 01:16:03.749718 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8871 01:16:03.752740 ==
8872 01:16:03.753260
8873 01:16:03.753599
8874 01:16:03.753947 TX Vref Scan disable
8875 01:16:03.759516 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8876 01:16:03.760215 == TX Byte 0 ==
8877 01:16:03.762844 u2DelayCellOfst[0]=14 cells (4 PI)
8878 01:16:03.766005 u2DelayCellOfst[1]=10 cells (3 PI)
8879 01:16:03.769618 u2DelayCellOfst[2]=0 cells (0 PI)
8880 01:16:03.772514 u2DelayCellOfst[3]=7 cells (2 PI)
8881 01:16:03.775632 u2DelayCellOfst[4]=7 cells (2 PI)
8882 01:16:03.779054 u2DelayCellOfst[5]=14 cells (4 PI)
8883 01:16:03.782465 u2DelayCellOfst[6]=17 cells (5 PI)
8884 01:16:03.785522 u2DelayCellOfst[7]=7 cells (2 PI)
8885 01:16:03.789027 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8886 01:16:03.792266 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8887 01:16:03.795798 == TX Byte 1 ==
8888 01:16:03.798955 u2DelayCellOfst[8]=0 cells (0 PI)
8889 01:16:03.802586 u2DelayCellOfst[9]=0 cells (0 PI)
8890 01:16:03.805706 u2DelayCellOfst[10]=10 cells (3 PI)
8891 01:16:03.808682 u2DelayCellOfst[11]=7 cells (2 PI)
8892 01:16:03.812036 u2DelayCellOfst[12]=14 cells (4 PI)
8893 01:16:03.815183 u2DelayCellOfst[13]=14 cells (4 PI)
8894 01:16:03.818889 u2DelayCellOfst[14]=17 cells (5 PI)
8895 01:16:03.821930 u2DelayCellOfst[15]=17 cells (5 PI)
8896 01:16:03.825366 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8897 01:16:03.828614 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8898 01:16:03.832013 DramC Write-DBI on
8899 01:16:03.832446 ==
8900 01:16:03.835048 Dram Type= 6, Freq= 0, CH_1, rank 1
8901 01:16:03.838687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8902 01:16:03.839106 ==
8903 01:16:03.839433
8904 01:16:03.839739
8905 01:16:03.841573 TX Vref Scan disable
8906 01:16:03.845259 == TX Byte 0 ==
8907 01:16:03.848454 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8908 01:16:03.848991 == TX Byte 1 ==
8909 01:16:03.854728 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8910 01:16:03.855146 DramC Write-DBI off
8911 01:16:03.855476
8912 01:16:03.855781 [DATLAT]
8913 01:16:03.858516 Freq=1600, CH1 RK1
8914 01:16:03.858998
8915 01:16:03.861338 DATLAT Default: 0xf
8916 01:16:03.861745 0, 0xFFFF, sum = 0
8917 01:16:03.864885 1, 0xFFFF, sum = 0
8918 01:16:03.865307 2, 0xFFFF, sum = 0
8919 01:16:03.868039 3, 0xFFFF, sum = 0
8920 01:16:03.868462 4, 0xFFFF, sum = 0
8921 01:16:03.871047 5, 0xFFFF, sum = 0
8922 01:16:03.871534 6, 0xFFFF, sum = 0
8923 01:16:03.874798 7, 0xFFFF, sum = 0
8924 01:16:03.875216 8, 0xFFFF, sum = 0
8925 01:16:03.877851 9, 0xFFFF, sum = 0
8926 01:16:03.878369 10, 0xFFFF, sum = 0
8927 01:16:03.880895 11, 0xFFFF, sum = 0
8928 01:16:03.881315 12, 0xFFFF, sum = 0
8929 01:16:03.884678 13, 0xFFFF, sum = 0
8930 01:16:03.885178 14, 0x0, sum = 1
8931 01:16:03.887967 15, 0x0, sum = 2
8932 01:16:03.888390 16, 0x0, sum = 3
8933 01:16:03.890832 17, 0x0, sum = 4
8934 01:16:03.891250 best_step = 15
8935 01:16:03.891578
8936 01:16:03.891879 ==
8937 01:16:03.894659 Dram Type= 6, Freq= 0, CH_1, rank 1
8938 01:16:03.900611 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8939 01:16:03.901024 ==
8940 01:16:03.901352 RX Vref Scan: 0
8941 01:16:03.901655
8942 01:16:03.904275 RX Vref 0 -> 0, step: 1
8943 01:16:03.904687
8944 01:16:03.907532 RX Delay 11 -> 252, step: 4
8945 01:16:03.910707 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8946 01:16:03.914193 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8947 01:16:03.921051 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8948 01:16:03.923979 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8949 01:16:03.927008 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8950 01:16:03.930572 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8951 01:16:03.933522 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8952 01:16:03.940235 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8953 01:16:03.943183 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8954 01:16:03.946783 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8955 01:16:03.949944 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8956 01:16:03.953679 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8957 01:16:03.959773 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8958 01:16:03.963359 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8959 01:16:03.966554 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8960 01:16:03.969584 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8961 01:16:03.973431 ==
8962 01:16:03.973868 Dram Type= 6, Freq= 0, CH_1, rank 1
8963 01:16:03.979763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8964 01:16:03.980228 ==
8965 01:16:03.980569 DQS Delay:
8966 01:16:03.983371 DQS0 = 0, DQS1 = 0
8967 01:16:03.983940 DQM Delay:
8968 01:16:03.986678 DQM0 = 132, DQM1 = 127
8969 01:16:03.987091 DQ Delay:
8970 01:16:03.989626 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =130
8971 01:16:03.993390 DQ4 =130, DQ5 =144, DQ6 =142, DQ7 =130
8972 01:16:03.996376 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =120
8973 01:16:03.999408 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
8974 01:16:04.000116
8975 01:16:04.000656
8976 01:16:04.001181
8977 01:16:04.002826 [DramC_TX_OE_Calibration] TA2
8978 01:16:04.006359 Original DQ_B0 (3 6) =30, OEN = 27
8979 01:16:04.009319 Original DQ_B1 (3 6) =30, OEN = 27
8980 01:16:04.012786 24, 0x0, End_B0=24 End_B1=24
8981 01:16:04.016027 25, 0x0, End_B0=25 End_B1=25
8982 01:16:04.016544 26, 0x0, End_B0=26 End_B1=26
8983 01:16:04.019512 27, 0x0, End_B0=27 End_B1=27
8984 01:16:04.022700 28, 0x0, End_B0=28 End_B1=28
8985 01:16:04.026080 29, 0x0, End_B0=29 End_B1=29
8986 01:16:04.029217 30, 0x0, End_B0=30 End_B1=30
8987 01:16:04.029821 31, 0x4141, End_B0=30 End_B1=30
8988 01:16:04.032682 Byte0 end_step=30 best_step=27
8989 01:16:04.035600 Byte1 end_step=30 best_step=27
8990 01:16:04.039193 Byte0 TX OE(2T, 0.5T) = (3, 3)
8991 01:16:04.042309 Byte1 TX OE(2T, 0.5T) = (3, 3)
8992 01:16:04.042746
8993 01:16:04.043075
8994 01:16:04.048898 [DQSOSCAuto] RK1, (LSB)MR18= 0x101e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
8995 01:16:04.052373 CH1 RK1: MR19=303, MR18=101E
8996 01:16:04.058189 CH1_RK1: MR19=0x303, MR18=0x101E, DQSOSC=394, MR23=63, INC=23, DEC=15
8997 01:16:04.061763 [RxdqsGatingPostProcess] freq 1600
8998 01:16:04.068377 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8999 01:16:04.071451 best DQS0 dly(2T, 0.5T) = (1, 1)
9000 01:16:04.074599 best DQS1 dly(2T, 0.5T) = (1, 1)
9001 01:16:04.078456 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9002 01:16:04.078526 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9003 01:16:04.081274 best DQS0 dly(2T, 0.5T) = (1, 1)
9004 01:16:04.085109 best DQS1 dly(2T, 0.5T) = (1, 1)
9005 01:16:04.088015 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9006 01:16:04.091529 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9007 01:16:04.094829 Pre-setting of DQS Precalculation
9008 01:16:04.101879 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9009 01:16:04.107742 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9010 01:16:04.114743 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9011 01:16:04.114953
9012 01:16:04.115064
9013 01:16:04.117646 [Calibration Summary] 3200 Mbps
9014 01:16:04.117846 CH 0, Rank 0
9015 01:16:04.121189 SW Impedance : PASS
9016 01:16:04.124373 DUTY Scan : NO K
9017 01:16:04.124544 ZQ Calibration : PASS
9018 01:16:04.127586 Jitter Meter : NO K
9019 01:16:04.130857 CBT Training : PASS
9020 01:16:04.131080 Write leveling : PASS
9021 01:16:04.134474 RX DQS gating : PASS
9022 01:16:04.137904 RX DQ/DQS(RDDQC) : PASS
9023 01:16:04.138207 TX DQ/DQS : PASS
9024 01:16:04.141217 RX DATLAT : PASS
9025 01:16:04.144431 RX DQ/DQS(Engine): PASS
9026 01:16:04.144848 TX OE : PASS
9027 01:16:04.145201 All Pass.
9028 01:16:04.145514
9029 01:16:04.147817 CH 0, Rank 1
9030 01:16:04.151771 SW Impedance : PASS
9031 01:16:04.152318 DUTY Scan : NO K
9032 01:16:04.154396 ZQ Calibration : PASS
9033 01:16:04.154814 Jitter Meter : NO K
9034 01:16:04.157615 CBT Training : PASS
9035 01:16:04.161169 Write leveling : PASS
9036 01:16:04.161622 RX DQS gating : PASS
9037 01:16:04.163992 RX DQ/DQS(RDDQC) : PASS
9038 01:16:04.167588 TX DQ/DQS : PASS
9039 01:16:04.168148 RX DATLAT : PASS
9040 01:16:04.170742 RX DQ/DQS(Engine): PASS
9041 01:16:04.173936 TX OE : PASS
9042 01:16:04.174432 All Pass.
9043 01:16:04.174773
9044 01:16:04.175131 CH 1, Rank 0
9045 01:16:04.177097 SW Impedance : PASS
9046 01:16:04.180565 DUTY Scan : NO K
9047 01:16:04.181007 ZQ Calibration : PASS
9048 01:16:04.183606 Jitter Meter : NO K
9049 01:16:04.187470 CBT Training : PASS
9050 01:16:04.187913 Write leveling : PASS
9051 01:16:04.190656 RX DQS gating : PASS
9052 01:16:04.193954 RX DQ/DQS(RDDQC) : PASS
9053 01:16:04.194364 TX DQ/DQS : PASS
9054 01:16:04.196641 RX DATLAT : PASS
9055 01:16:04.200262 RX DQ/DQS(Engine): PASS
9056 01:16:04.200766 TX OE : PASS
9057 01:16:04.203689 All Pass.
9058 01:16:04.204146
9059 01:16:04.204575 CH 1, Rank 1
9060 01:16:04.207082 SW Impedance : PASS
9061 01:16:04.207593 DUTY Scan : NO K
9062 01:16:04.209863 ZQ Calibration : PASS
9063 01:16:04.213457 Jitter Meter : NO K
9064 01:16:04.213869 CBT Training : PASS
9065 01:16:04.216504 Write leveling : PASS
9066 01:16:04.219657 RX DQS gating : PASS
9067 01:16:04.220099 RX DQ/DQS(RDDQC) : PASS
9068 01:16:04.222898 TX DQ/DQS : PASS
9069 01:16:04.226454 RX DATLAT : PASS
9070 01:16:04.226864 RX DQ/DQS(Engine): PASS
9071 01:16:04.229497 TX OE : PASS
9072 01:16:04.229982 All Pass.
9073 01:16:04.230317
9074 01:16:04.232899 DramC Write-DBI on
9075 01:16:04.236152 PER_BANK_REFRESH: Hybrid Mode
9076 01:16:04.236577 TX_TRACKING: ON
9077 01:16:04.246253 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9078 01:16:04.252932 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9079 01:16:04.259171 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9080 01:16:04.265835 [FAST_K] Save calibration result to emmc
9081 01:16:04.266325 sync common calibartion params.
9082 01:16:04.269395 sync cbt_mode0:1, 1:1
9083 01:16:04.272245 dram_init: ddr_geometry: 2
9084 01:16:04.272687 dram_init: ddr_geometry: 2
9085 01:16:04.275725 dram_init: ddr_geometry: 2
9086 01:16:04.279355 0:dram_rank_size:100000000
9087 01:16:04.282262 1:dram_rank_size:100000000
9088 01:16:04.285524 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9089 01:16:04.289066 DFS_SHUFFLE_HW_MODE: ON
9090 01:16:04.291997 dramc_set_vcore_voltage set vcore to 725000
9091 01:16:04.295692 Read voltage for 1600, 0
9092 01:16:04.296145 Vio18 = 0
9093 01:16:04.298615 Vcore = 725000
9094 01:16:04.299030 Vdram = 0
9095 01:16:04.299361 Vddq = 0
9096 01:16:04.299670 Vmddr = 0
9097 01:16:04.302189 switch to 3200 Mbps bootup
9098 01:16:04.305004 [DramcRunTimeConfig]
9099 01:16:04.305085 PHYPLL
9100 01:16:04.308511 DPM_CONTROL_AFTERK: ON
9101 01:16:04.308618 PER_BANK_REFRESH: ON
9102 01:16:04.311511 REFRESH_OVERHEAD_REDUCTION: ON
9103 01:16:04.315117 CMD_PICG_NEW_MODE: OFF
9104 01:16:04.315221 XRTWTW_NEW_MODE: ON
9105 01:16:04.318238 XRTRTR_NEW_MODE: ON
9106 01:16:04.318346 TX_TRACKING: ON
9107 01:16:04.321366 RDSEL_TRACKING: OFF
9108 01:16:04.324434 DQS Precalculation for DVFS: ON
9109 01:16:04.324517 RX_TRACKING: OFF
9110 01:16:04.328178 HW_GATING DBG: ON
9111 01:16:04.328274 ZQCS_ENABLE_LP4: ON
9112 01:16:04.331303 RX_PICG_NEW_MODE: ON
9113 01:16:04.331398 TX_PICG_NEW_MODE: ON
9114 01:16:04.334823 ENABLE_RX_DCM_DPHY: ON
9115 01:16:04.337726 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9116 01:16:04.341425 DUMMY_READ_FOR_TRACKING: OFF
9117 01:16:04.341505 !!! SPM_CONTROL_AFTERK: OFF
9118 01:16:04.344319 !!! SPM could not control APHY
9119 01:16:04.348234 IMPEDANCE_TRACKING: ON
9120 01:16:04.348320 TEMP_SENSOR: ON
9121 01:16:04.351540 HW_SAVE_FOR_SR: OFF
9122 01:16:04.354477 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9123 01:16:04.357568 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9124 01:16:04.357669 Read ODT Tracking: ON
9125 01:16:04.361114 Refresh Rate DeBounce: ON
9126 01:16:04.364663 DFS_NO_QUEUE_FLUSH: ON
9127 01:16:04.367633 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9128 01:16:04.371190 ENABLE_DFS_RUNTIME_MRW: OFF
9129 01:16:04.371382 DDR_RESERVE_NEW_MODE: ON
9130 01:16:04.374461 MR_CBT_SWITCH_FREQ: ON
9131 01:16:04.377377 =========================
9132 01:16:04.394864 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9133 01:16:04.398540 dram_init: ddr_geometry: 2
9134 01:16:04.416587 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9135 01:16:04.419834 dram_init: dram init end (result: 0)
9136 01:16:04.426570 DRAM-K: Full calibration passed in 24463 msecs
9137 01:16:04.429913 MRC: failed to locate region type 0.
9138 01:16:04.430334 DRAM rank0 size:0x100000000,
9139 01:16:04.432968 DRAM rank1 size=0x100000000
9140 01:16:04.443115 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9141 01:16:04.449859 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9142 01:16:04.456110 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9143 01:16:04.466000 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9144 01:16:04.466457 DRAM rank0 size:0x100000000,
9145 01:16:04.469208 DRAM rank1 size=0x100000000
9146 01:16:04.469627 CBMEM:
9147 01:16:04.472398 IMD: root @ 0xfffff000 254 entries.
9148 01:16:04.475909 IMD: root @ 0xffffec00 62 entries.
9149 01:16:04.482392 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9150 01:16:04.485334 WARNING: RO_VPD is uninitialized or empty.
9151 01:16:04.488943 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9152 01:16:04.496588 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9153 01:16:04.509422 read SPI 0x42894 0xe01e: 6223 us, 9219 KB/s, 73.752 Mbps
9154 01:16:04.521014 BS: romstage times (exec / console): total (unknown) / 23986 ms
9155 01:16:04.521433
9156 01:16:04.521759
9157 01:16:04.530616 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9158 01:16:04.533510 ARM64: Exception handlers installed.
9159 01:16:04.537145 ARM64: Testing exception
9160 01:16:04.540101 ARM64: Done test exception
9161 01:16:04.540518 Enumerating buses...
9162 01:16:04.543632 Show all devs... Before device enumeration.
9163 01:16:04.546687 Root Device: enabled 1
9164 01:16:04.549901 CPU_CLUSTER: 0: enabled 1
9165 01:16:04.550006 CPU: 00: enabled 1
9166 01:16:04.553130 Compare with tree...
9167 01:16:04.556199 Root Device: enabled 1
9168 01:16:04.556280 CPU_CLUSTER: 0: enabled 1
9169 01:16:04.559845 CPU: 00: enabled 1
9170 01:16:04.559974 Root Device scanning...
9171 01:16:04.562893 scan_static_bus for Root Device
9172 01:16:04.566335 CPU_CLUSTER: 0 enabled
9173 01:16:04.569398 scan_static_bus for Root Device done
9174 01:16:04.572889 scan_bus: bus Root Device finished in 8 msecs
9175 01:16:04.572969 done
9176 01:16:04.579941 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9177 01:16:04.582862 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9178 01:16:04.589476 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9179 01:16:04.595925 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9180 01:16:04.596111 Allocating resources...
9181 01:16:04.598986 Reading resources...
9182 01:16:04.602657 Root Device read_resources bus 0 link: 0
9183 01:16:04.605456 DRAM rank0 size:0x100000000,
9184 01:16:04.608958 DRAM rank1 size=0x100000000
9185 01:16:04.612345 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9186 01:16:04.615444 CPU: 00 missing read_resources
9187 01:16:04.618796 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9188 01:16:04.622162 Root Device read_resources bus 0 link: 0 done
9189 01:16:04.625095 Done reading resources.
9190 01:16:04.628862 Show resources in subtree (Root Device)...After reading.
9191 01:16:04.631869 Root Device child on link 0 CPU_CLUSTER: 0
9192 01:16:04.638725 CPU_CLUSTER: 0 child on link 0 CPU: 00
9193 01:16:04.645070 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9194 01:16:04.648556 CPU: 00
9195 01:16:04.651421 Root Device assign_resources, bus 0 link: 0
9196 01:16:04.654985 CPU_CLUSTER: 0 missing set_resources
9197 01:16:04.658270 Root Device assign_resources, bus 0 link: 0 done
9198 01:16:04.661789 Done setting resources.
9199 01:16:04.664644 Show resources in subtree (Root Device)...After assigning values.
9200 01:16:04.671070 Root Device child on link 0 CPU_CLUSTER: 0
9201 01:16:04.674512 CPU_CLUSTER: 0 child on link 0 CPU: 00
9202 01:16:04.681102 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9203 01:16:04.684417 CPU: 00
9204 01:16:04.684505 Done allocating resources.
9205 01:16:04.691031 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9206 01:16:04.694018 Enabling resources...
9207 01:16:04.694162 done.
9208 01:16:04.697833 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9209 01:16:04.701424 Initializing devices...
9210 01:16:04.701839 Root Device init
9211 01:16:04.704468 init hardware done!
9212 01:16:04.707636 0x00000018: ctrlr->caps
9213 01:16:04.708105 52.000 MHz: ctrlr->f_max
9214 01:16:04.711227 0.400 MHz: ctrlr->f_min
9215 01:16:04.714287 0x40ff8080: ctrlr->voltages
9216 01:16:04.714711 sclk: 390625
9217 01:16:04.717553 Bus Width = 1
9218 01:16:04.718019 sclk: 390625
9219 01:16:04.718659 Bus Width = 1
9220 01:16:04.721213 Early init status = 3
9221 01:16:04.724182 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9222 01:16:04.728653 in-header: 03 fc 00 00 01 00 00 00
9223 01:16:04.731750 in-data: 00
9224 01:16:04.734812 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9225 01:16:04.740398 in-header: 03 fd 00 00 00 00 00 00
9226 01:16:04.743696 in-data:
9227 01:16:04.746857 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9228 01:16:04.751998 in-header: 03 fc 00 00 01 00 00 00
9229 01:16:04.755086 in-data: 00
9230 01:16:04.757977 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9231 01:16:04.763527 in-header: 03 fd 00 00 00 00 00 00
9232 01:16:04.767151 in-data:
9233 01:16:04.769971 [SSUSB] Setting up USB HOST controller...
9234 01:16:04.773420 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9235 01:16:04.776779 [SSUSB] phy power-on done.
9236 01:16:04.780377 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9237 01:16:04.786584 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9238 01:16:04.789969 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9239 01:16:04.796751 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9240 01:16:04.803128 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9241 01:16:04.809893 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9242 01:16:04.816670 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9243 01:16:04.822829 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9244 01:16:04.826058 SPM: binary array size = 0x9dc
9245 01:16:04.829660 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9246 01:16:04.835800 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9247 01:16:04.842686 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9248 01:16:04.849131 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9249 01:16:04.852194 configure_display: Starting display init
9250 01:16:04.887086 anx7625_power_on_init: Init interface.
9251 01:16:04.890234 anx7625_disable_pd_protocol: Disabled PD feature.
9252 01:16:04.893651 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9253 01:16:04.921461 anx7625_start_dp_work: Secure OCM version=00
9254 01:16:04.924486 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9255 01:16:04.939745 sp_tx_get_edid_block: EDID Block = 1
9256 01:16:05.042460 Extracted contents:
9257 01:16:05.045398 header: 00 ff ff ff ff ff ff 00
9258 01:16:05.048527 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9259 01:16:05.051991 version: 01 04
9260 01:16:05.055320 basic params: 95 1f 11 78 0a
9261 01:16:05.058822 chroma info: 76 90 94 55 54 90 27 21 50 54
9262 01:16:05.062174 established: 00 00 00
9263 01:16:05.068526 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9264 01:16:05.071937 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9265 01:16:05.078707 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9266 01:16:05.085090 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9267 01:16:05.091420 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9268 01:16:05.094760 extensions: 00
9269 01:16:05.095312 checksum: fb
9270 01:16:05.095663
9271 01:16:05.101357 Manufacturer: IVO Model 57d Serial Number 0
9272 01:16:05.101884 Made week 0 of 2020
9273 01:16:05.104678 EDID version: 1.4
9274 01:16:05.105093 Digital display
9275 01:16:05.107824 6 bits per primary color channel
9276 01:16:05.108315 DisplayPort interface
9277 01:16:05.111545 Maximum image size: 31 cm x 17 cm
9278 01:16:05.114453 Gamma: 220%
9279 01:16:05.115051 Check DPMS levels
9280 01:16:05.121049 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9281 01:16:05.124379 First detailed timing is preferred timing
9282 01:16:05.124924 Established timings supported:
9283 01:16:05.127505 Standard timings supported:
9284 01:16:05.131036 Detailed timings
9285 01:16:05.134480 Hex of detail: 383680a07038204018303c0035ae10000019
9286 01:16:05.140650 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9287 01:16:05.143791 0780 0798 07c8 0820 hborder 0
9288 01:16:05.147494 0438 043b 0447 0458 vborder 0
9289 01:16:05.150485 -hsync -vsync
9290 01:16:05.151040 Did detailed timing
9291 01:16:05.157573 Hex of detail: 000000000000000000000000000000000000
9292 01:16:05.160750 Manufacturer-specified data, tag 0
9293 01:16:05.163687 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9294 01:16:05.167414 ASCII string: InfoVision
9295 01:16:05.170390 Hex of detail: 000000fe00523134304e574635205248200a
9296 01:16:05.173694 ASCII string: R140NWF5 RH
9297 01:16:05.174326 Checksum
9298 01:16:05.176713 Checksum: 0xfb (valid)
9299 01:16:05.180086 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9300 01:16:05.182920 DSI data_rate: 832800000 bps
9301 01:16:05.189576 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9302 01:16:05.192875 anx7625_parse_edid: pixelclock(138800).
9303 01:16:05.196503 hactive(1920), hsync(48), hfp(24), hbp(88)
9304 01:16:05.199609 vactive(1080), vsync(12), vfp(3), vbp(17)
9305 01:16:05.202738 anx7625_dsi_config: config dsi.
9306 01:16:05.209388 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9307 01:16:05.223804 anx7625_dsi_config: success to config DSI
9308 01:16:05.227331 anx7625_dp_start: MIPI phy setup OK.
9309 01:16:05.230785 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9310 01:16:05.233851 mtk_ddp_mode_set invalid vrefresh 60
9311 01:16:05.237212 main_disp_path_setup
9312 01:16:05.237628 ovl_layer_smi_id_en
9313 01:16:05.240135 ovl_layer_smi_id_en
9314 01:16:05.240633 ccorr_config
9315 01:16:05.241187 aal_config
9316 01:16:05.243380 gamma_config
9317 01:16:05.243925 postmask_config
9318 01:16:05.246791 dither_config
9319 01:16:05.250339 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9320 01:16:05.256646 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9321 01:16:05.260016 Root Device init finished in 554 msecs
9322 01:16:05.263709 CPU_CLUSTER: 0 init
9323 01:16:05.269875 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9324 01:16:05.276506 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9325 01:16:05.276961 APU_MBOX 0x190000b0 = 0x10001
9326 01:16:05.280034 APU_MBOX 0x190001b0 = 0x10001
9327 01:16:05.283014 APU_MBOX 0x190005b0 = 0x10001
9328 01:16:05.286688 APU_MBOX 0x190006b0 = 0x10001
9329 01:16:05.292765 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9330 01:16:05.303077 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9331 01:16:05.315098 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9332 01:16:05.321997 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9333 01:16:05.333768 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9334 01:16:05.342700 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9335 01:16:05.346399 CPU_CLUSTER: 0 init finished in 81 msecs
9336 01:16:05.349402 Devices initialized
9337 01:16:05.352643 Show all devs... After init.
9338 01:16:05.353060 Root Device: enabled 1
9339 01:16:05.355837 CPU_CLUSTER: 0: enabled 1
9340 01:16:05.359389 CPU: 00: enabled 1
9341 01:16:05.362411 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9342 01:16:05.366191 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9343 01:16:05.369060 ELOG: NV offset 0x57f000 size 0x1000
9344 01:16:05.376178 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9345 01:16:05.382567 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9346 01:16:05.385551 ELOG: Event(17) added with size 13 at 2024-04-23 01:16:05 UTC
9347 01:16:05.392393 out: cmd=0x121: 03 db 21 01 00 00 00 00
9348 01:16:05.395459 in-header: 03 03 00 00 2c 00 00 00
9349 01:16:05.405314 in-data: 5c 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9350 01:16:05.412457 ELOG: Event(A1) added with size 10 at 2024-04-23 01:16:05 UTC
9351 01:16:05.418700 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9352 01:16:05.425303 ELOG: Event(A0) added with size 9 at 2024-04-23 01:16:05 UTC
9353 01:16:05.428415 elog_add_boot_reason: Logged dev mode boot
9354 01:16:05.435054 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9355 01:16:05.435470 Finalize devices...
9356 01:16:05.438141 Devices finalized
9357 01:16:05.441673 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9358 01:16:05.445472 Writing coreboot table at 0xffe64000
9359 01:16:05.448052 0. 000000000010a000-0000000000113fff: RAMSTAGE
9360 01:16:05.454994 1. 0000000040000000-00000000400fffff: RAM
9361 01:16:05.458121 2. 0000000040100000-000000004032afff: RAMSTAGE
9362 01:16:05.461266 3. 000000004032b000-00000000545fffff: RAM
9363 01:16:05.464554 4. 0000000054600000-000000005465ffff: BL31
9364 01:16:05.468022 5. 0000000054660000-00000000ffe63fff: RAM
9365 01:16:05.474421 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9366 01:16:05.477961 7. 0000000100000000-000000023fffffff: RAM
9367 01:16:05.481138 Passing 5 GPIOs to payload:
9368 01:16:05.484879 NAME | PORT | POLARITY | VALUE
9369 01:16:05.491515 EC in RW | 0x000000aa | low | undefined
9370 01:16:05.494422 EC interrupt | 0x00000005 | low | undefined
9371 01:16:05.500678 TPM interrupt | 0x000000ab | high | undefined
9372 01:16:05.504474 SD card detect | 0x00000011 | high | undefined
9373 01:16:05.507360 speaker enable | 0x00000093 | high | undefined
9374 01:16:05.510939 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9375 01:16:05.514163 in-header: 03 f9 00 00 02 00 00 00
9376 01:16:05.517698 in-data: 02 00
9377 01:16:05.521492 ADC[4]: Raw value=902586 ID=7
9378 01:16:05.524047 ADC[3]: Raw value=213546 ID=1
9379 01:16:05.524468 RAM Code: 0x71
9380 01:16:05.527451 ADC[6]: Raw value=75000 ID=0
9381 01:16:05.530849 ADC[5]: Raw value=213546 ID=1
9382 01:16:05.531382 SKU Code: 0x1
9383 01:16:05.537243 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum c8cd
9384 01:16:05.537712 coreboot table: 964 bytes.
9385 01:16:05.540873 IMD ROOT 0. 0xfffff000 0x00001000
9386 01:16:05.543949 IMD SMALL 1. 0xffffe000 0x00001000
9387 01:16:05.547523 RO MCACHE 2. 0xffffc000 0x00001104
9388 01:16:05.550719 CONSOLE 3. 0xfff7c000 0x00080000
9389 01:16:05.553724 FMAP 4. 0xfff7b000 0x00000452
9390 01:16:05.557031 TIME STAMP 5. 0xfff7a000 0x00000910
9391 01:16:05.560416 VBOOT WORK 6. 0xfff66000 0x00014000
9392 01:16:05.563522 RAMOOPS 7. 0xffe66000 0x00100000
9393 01:16:05.567130 COREBOOT 8. 0xffe64000 0x00002000
9394 01:16:05.570143 IMD small region:
9395 01:16:05.573444 IMD ROOT 0. 0xffffec00 0x00000400
9396 01:16:05.576454 VPD 1. 0xffffeb80 0x0000006c
9397 01:16:05.579814 MMC STATUS 2. 0xffffeb60 0x00000004
9398 01:16:05.586498 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9399 01:16:05.587052 Probing TPM: done!
9400 01:16:05.593591 Connected to device vid:did:rid of 1ae0:0028:00
9401 01:16:05.600502 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9402 01:16:05.603470 Initialized TPM device CR50 revision 0
9403 01:16:05.607108 Checking cr50 for pending updates
9404 01:16:05.612738 Reading cr50 TPM mode
9405 01:16:05.621369 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9406 01:16:05.627731 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9407 01:16:05.667612 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9408 01:16:05.670944 Checking segment from ROM address 0x40100000
9409 01:16:05.674012 Checking segment from ROM address 0x4010001c
9410 01:16:05.681076 Loading segment from ROM address 0x40100000
9411 01:16:05.681158 code (compression=0)
9412 01:16:05.690503 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9413 01:16:05.697302 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9414 01:16:05.697386 it's not compressed!
9415 01:16:05.704036 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9416 01:16:05.710052 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9417 01:16:05.727818 Loading segment from ROM address 0x4010001c
9418 01:16:05.727958 Entry Point 0x80000000
9419 01:16:05.731186 Loaded segments
9420 01:16:05.734498 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9421 01:16:05.740996 Jumping to boot code at 0x80000000(0xffe64000)
9422 01:16:05.747593 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9423 01:16:05.754649 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9424 01:16:05.762691 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9425 01:16:05.765549 Checking segment from ROM address 0x40100000
9426 01:16:05.769271 Checking segment from ROM address 0x4010001c
9427 01:16:05.775692 Loading segment from ROM address 0x40100000
9428 01:16:05.775809 code (compression=1)
9429 01:16:05.782399 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9430 01:16:05.792166 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9431 01:16:05.792248 using LZMA
9432 01:16:05.800827 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9433 01:16:05.807180 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9434 01:16:05.810407 Loading segment from ROM address 0x4010001c
9435 01:16:05.813486 Entry Point 0x54601000
9436 01:16:05.813567 Loaded segments
9437 01:16:05.816866 NOTICE: MT8192 bl31_setup
9438 01:16:05.824235 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9439 01:16:05.827850 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9440 01:16:05.830898 WARNING: region 0:
9441 01:16:05.834047 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9442 01:16:05.834121 WARNING: region 1:
9443 01:16:05.841012 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9444 01:16:05.844376 WARNING: region 2:
9445 01:16:05.847720 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9446 01:16:05.850951 WARNING: region 3:
9447 01:16:05.853968 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9448 01:16:05.857363 WARNING: region 4:
9449 01:16:05.864169 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9450 01:16:05.864253 WARNING: region 5:
9451 01:16:05.867320 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9452 01:16:05.870509 WARNING: region 6:
9453 01:16:05.874078 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9454 01:16:05.877165 WARNING: region 7:
9455 01:16:05.880624 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9456 01:16:05.886991 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9457 01:16:05.890584 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9458 01:16:05.896944 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9459 01:16:05.900251 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9460 01:16:05.903751 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9461 01:16:05.910266 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9462 01:16:05.913215 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9463 01:16:05.916841 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9464 01:16:05.923577 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9465 01:16:05.926660 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9466 01:16:05.933317 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9467 01:16:05.936471 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9468 01:16:05.940424 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9469 01:16:05.946971 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9470 01:16:05.949978 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9471 01:16:05.953318 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9472 01:16:05.959715 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9473 01:16:05.963199 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9474 01:16:05.969517 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9475 01:16:05.972752 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9476 01:16:05.976106 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9477 01:16:05.982824 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9478 01:16:05.986409 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9479 01:16:05.993338 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9480 01:16:05.996361 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9481 01:16:05.999525 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9482 01:16:06.006412 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9483 01:16:06.009689 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9484 01:16:06.016145 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9485 01:16:06.019713 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9486 01:16:06.022650 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9487 01:16:06.029716 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9488 01:16:06.032654 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9489 01:16:06.036327 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9490 01:16:06.042588 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9491 01:16:06.046400 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9492 01:16:06.049336 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9493 01:16:06.052546 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9494 01:16:06.058900 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9495 01:16:06.062544 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9496 01:16:06.065919 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9497 01:16:06.068990 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9498 01:16:06.075680 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9499 01:16:06.078897 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9500 01:16:06.082311 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9501 01:16:06.085739 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9502 01:16:06.092099 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9503 01:16:06.095604 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9504 01:16:06.098704 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9505 01:16:06.105685 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9506 01:16:06.108726 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9507 01:16:06.115673 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9508 01:16:06.118529 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9509 01:16:06.125472 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9510 01:16:06.129049 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9511 01:16:06.132164 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9512 01:16:06.138976 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9513 01:16:06.142082 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9514 01:16:06.148837 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9515 01:16:06.151981 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9516 01:16:06.158869 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9517 01:16:06.162622 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9518 01:16:06.165683 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9519 01:16:06.172370 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9520 01:16:06.175777 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9521 01:16:06.181748 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9522 01:16:06.185511 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9523 01:16:06.191433 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9524 01:16:06.194753 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9525 01:16:06.201468 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9526 01:16:06.204890 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9527 01:16:06.208223 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9528 01:16:06.214903 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9529 01:16:06.218437 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9530 01:16:06.225417 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9531 01:16:06.228389 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9532 01:16:06.234691 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9533 01:16:06.238421 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9534 01:16:06.245247 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9535 01:16:06.248317 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9536 01:16:06.251662 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9537 01:16:06.258558 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9538 01:16:06.261537 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9539 01:16:06.268002 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9540 01:16:06.271786 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9541 01:16:06.278103 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9542 01:16:06.281542 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9543 01:16:06.287876 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9544 01:16:06.291537 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9545 01:16:06.294694 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9546 01:16:06.301522 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9547 01:16:06.304370 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9548 01:16:06.310789 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9549 01:16:06.314130 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9550 01:16:06.320896 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9551 01:16:06.324372 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9552 01:16:06.327726 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9553 01:16:06.334049 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9554 01:16:06.337667 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9555 01:16:06.340689 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9556 01:16:06.344152 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9557 01:16:06.350985 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9558 01:16:06.353992 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9559 01:16:06.360609 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9560 01:16:06.363762 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9561 01:16:06.367469 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9562 01:16:06.373781 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9563 01:16:06.377255 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9564 01:16:06.383556 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9565 01:16:06.387422 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9566 01:16:06.390428 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9567 01:16:06.397250 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9568 01:16:06.400278 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9569 01:16:06.406883 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9570 01:16:06.410499 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9571 01:16:06.413901 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9572 01:16:06.420403 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9573 01:16:06.423777 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9574 01:16:06.426752 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9575 01:16:06.433577 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9576 01:16:06.436715 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9577 01:16:06.440202 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9578 01:16:06.443447 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9579 01:16:06.449967 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9580 01:16:06.453458 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9581 01:16:06.456448 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9582 01:16:06.463435 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9583 01:16:06.466500 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9584 01:16:06.473057 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9585 01:16:06.476798 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9586 01:16:06.479661 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9587 01:16:06.486542 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9588 01:16:06.489703 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9589 01:16:06.496617 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9590 01:16:06.499549 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9591 01:16:06.503262 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9592 01:16:06.510072 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9593 01:16:06.512873 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9594 01:16:06.519347 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9595 01:16:06.522831 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9596 01:16:06.526192 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9597 01:16:06.532703 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9598 01:16:06.536314 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9599 01:16:06.542306 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9600 01:16:06.545770 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9601 01:16:06.549028 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9602 01:16:06.555829 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9603 01:16:06.559286 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9604 01:16:06.565981 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9605 01:16:06.569040 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9606 01:16:06.572542 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9607 01:16:06.579327 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9608 01:16:06.582489 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9609 01:16:06.585992 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9610 01:16:06.592297 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9611 01:16:06.595987 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9612 01:16:06.602230 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9613 01:16:06.605757 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9614 01:16:06.608867 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9615 01:16:06.615600 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9616 01:16:06.618548 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9617 01:16:06.625450 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9618 01:16:06.628362 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9619 01:16:06.635174 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9620 01:16:06.638469 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9621 01:16:06.641424 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9622 01:16:06.648285 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9623 01:16:06.651290 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9624 01:16:06.658422 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9625 01:16:06.661258 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9626 01:16:06.664854 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9627 01:16:06.671046 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9628 01:16:06.674343 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9629 01:16:06.680679 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9630 01:16:06.684388 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9631 01:16:06.687417 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9632 01:16:06.693763 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9633 01:16:06.697235 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9634 01:16:06.704293 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9635 01:16:06.706909 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9636 01:16:06.710280 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9637 01:16:06.717114 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9638 01:16:06.720788 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9639 01:16:06.726894 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9640 01:16:06.730449 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9641 01:16:06.734043 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9642 01:16:06.740519 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9643 01:16:06.743474 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9644 01:16:06.750182 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9645 01:16:06.753161 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9646 01:16:06.759923 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9647 01:16:06.763616 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9648 01:16:06.766375 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9649 01:16:06.773079 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9650 01:16:06.776058 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9651 01:16:06.782840 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9652 01:16:06.786374 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9653 01:16:06.793096 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9654 01:16:06.796236 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9655 01:16:06.802383 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9656 01:16:06.806154 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9657 01:16:06.809068 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9658 01:16:06.815952 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9659 01:16:06.818752 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9660 01:16:06.825746 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9661 01:16:06.829250 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9662 01:16:06.835684 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9663 01:16:06.838775 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9664 01:16:06.841840 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9665 01:16:06.848476 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9666 01:16:06.851688 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9667 01:16:06.858680 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9668 01:16:06.861610 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9669 01:16:06.868158 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9670 01:16:06.872048 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9671 01:16:06.874705 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9672 01:16:06.881677 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9673 01:16:06.884672 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9674 01:16:06.891622 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9675 01:16:06.894609 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9676 01:16:06.901357 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9677 01:16:06.904542 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9678 01:16:06.908044 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9679 01:16:06.914326 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9680 01:16:06.917998 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9681 01:16:06.924260 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9682 01:16:06.927993 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9683 01:16:06.931059 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9684 01:16:06.937725 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9685 01:16:06.941000 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9686 01:16:06.944034 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9687 01:16:06.950669 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9688 01:16:06.954120 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9689 01:16:06.957156 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9690 01:16:06.960603 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9691 01:16:06.967375 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9692 01:16:06.970498 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9693 01:16:06.977077 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9694 01:16:06.980465 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9695 01:16:06.983914 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9696 01:16:06.990457 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9697 01:16:06.993348 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9698 01:16:06.999870 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9699 01:16:07.003321 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9700 01:16:07.006445 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9701 01:16:07.013105 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9702 01:16:07.016065 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9703 01:16:07.022672 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9704 01:16:07.026333 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9705 01:16:07.029320 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9706 01:16:07.035880 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9707 01:16:07.039153 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9708 01:16:07.042778 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9709 01:16:07.049473 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9710 01:16:07.052226 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9711 01:16:07.056012 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9712 01:16:07.062219 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9713 01:16:07.065781 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9714 01:16:07.072151 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9715 01:16:07.075590 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9716 01:16:07.078450 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9717 01:16:07.085143 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9718 01:16:07.088781 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9719 01:16:07.092080 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9720 01:16:07.098093 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9721 01:16:07.101720 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9722 01:16:07.107918 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9723 01:16:07.111689 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9724 01:16:07.114719 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9725 01:16:07.121410 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9726 01:16:07.125093 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9727 01:16:07.127939 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9728 01:16:07.131289 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9729 01:16:07.134530 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9730 01:16:07.141187 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9731 01:16:07.144787 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9732 01:16:07.147803 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9733 01:16:07.154580 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9734 01:16:07.157401 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9735 01:16:07.161160 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9736 01:16:07.164055 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9737 01:16:07.170677 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9738 01:16:07.173771 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9739 01:16:07.180127 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9740 01:16:07.183540 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9741 01:16:07.186777 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9742 01:16:07.193932 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9743 01:16:07.196825 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9744 01:16:07.203473 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9745 01:16:07.206924 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9746 01:16:07.213644 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9747 01:16:07.216569 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9748 01:16:07.219776 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9749 01:16:07.226671 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9750 01:16:07.229791 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9751 01:16:07.236375 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9752 01:16:07.239789 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9753 01:16:07.242789 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9754 01:16:07.249405 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9755 01:16:07.252837 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9756 01:16:07.259614 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9757 01:16:07.263273 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9758 01:16:07.269519 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9759 01:16:07.273204 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9760 01:16:07.279203 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9761 01:16:07.282783 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9762 01:16:07.285747 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9763 01:16:07.292613 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9764 01:16:07.295489 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9765 01:16:07.302315 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9766 01:16:07.305399 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9767 01:16:07.311978 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9768 01:16:07.314982 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9769 01:16:07.318434 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9770 01:16:07.325334 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9771 01:16:07.328235 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9772 01:16:07.334846 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9773 01:16:07.338479 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9774 01:16:07.341426 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9775 01:16:07.347830 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9776 01:16:07.351417 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9777 01:16:07.358194 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9778 01:16:07.361318 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9779 01:16:07.364960 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9780 01:16:07.371019 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9781 01:16:07.374640 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9782 01:16:07.381493 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9783 01:16:07.384406 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9784 01:16:07.391416 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9785 01:16:07.394564 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9786 01:16:07.397718 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9787 01:16:07.403838 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9788 01:16:07.407422 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9789 01:16:07.413910 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9790 01:16:07.417289 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9791 01:16:07.423735 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9792 01:16:07.427056 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9793 01:16:07.430407 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9794 01:16:07.436972 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9795 01:16:07.440352 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9796 01:16:07.447197 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9797 01:16:07.450228 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9798 01:16:07.456519 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9799 01:16:07.459845 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9800 01:16:07.463296 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9801 01:16:07.470018 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9802 01:16:07.472735 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9803 01:16:07.479909 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9804 01:16:07.482817 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9805 01:16:07.489442 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9806 01:16:07.492360 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9807 01:16:07.496092 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9808 01:16:07.502518 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9809 01:16:07.506200 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9810 01:16:07.512403 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9811 01:16:07.515954 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9812 01:16:07.522162 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9813 01:16:07.526014 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9814 01:16:07.528964 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9815 01:16:07.535439 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9816 01:16:07.539165 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9817 01:16:07.545371 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9818 01:16:07.548998 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9819 01:16:07.555690 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9820 01:16:07.558468 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9821 01:16:07.565105 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9822 01:16:07.568479 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9823 01:16:07.571698 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9824 01:16:07.578110 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9825 01:16:07.581794 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9826 01:16:07.587834 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9827 01:16:07.591527 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9828 01:16:07.597729 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9829 01:16:07.601366 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9830 01:16:07.608039 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9831 01:16:07.610726 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9832 01:16:07.617763 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9833 01:16:07.620786 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9834 01:16:07.624629 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9835 01:16:07.630995 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9836 01:16:07.633983 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9837 01:16:07.640594 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9838 01:16:07.643523 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9839 01:16:07.650469 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9840 01:16:07.653580 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9841 01:16:07.659955 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9842 01:16:07.663309 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9843 01:16:07.666850 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9844 01:16:07.673708 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9845 01:16:07.676668 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9846 01:16:07.683347 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9847 01:16:07.686364 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9848 01:16:07.693292 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9849 01:16:07.696214 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9850 01:16:07.702998 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9851 01:16:07.705970 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9852 01:16:07.712451 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9853 01:16:07.716039 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9854 01:16:07.719591 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9855 01:16:07.725581 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9856 01:16:07.729412 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9857 01:16:07.735977 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9858 01:16:07.739105 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9859 01:16:07.742665 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9860 01:16:07.748862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9861 01:16:07.752197 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9862 01:16:07.758689 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9863 01:16:07.762431 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9864 01:16:07.768527 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9865 01:16:07.771872 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9866 01:16:07.778431 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9867 01:16:07.781777 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9868 01:16:07.788323 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9869 01:16:07.791910 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9870 01:16:07.798381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9871 01:16:07.801446 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9872 01:16:07.808315 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9873 01:16:07.811269 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9874 01:16:07.818429 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9875 01:16:07.821044 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9876 01:16:07.827755 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9877 01:16:07.830743 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9878 01:16:07.837518 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9879 01:16:07.841019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9880 01:16:07.847506 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9881 01:16:07.850750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9882 01:16:07.857472 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9883 01:16:07.863718 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9884 01:16:07.867421 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9885 01:16:07.874168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9886 01:16:07.877160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9887 01:16:07.883873 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9888 01:16:07.886790 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9889 01:16:07.893519 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9890 01:16:07.897074 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9891 01:16:07.900254 INFO: [APUAPC] vio 0
9892 01:16:07.903737 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9893 01:16:07.906989 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9894 01:16:07.910014 INFO: [APUAPC] D0_APC_0: 0x400510
9895 01:16:07.913448 INFO: [APUAPC] D0_APC_1: 0x0
9896 01:16:07.916571 INFO: [APUAPC] D0_APC_2: 0x1540
9897 01:16:07.919527 INFO: [APUAPC] D0_APC_3: 0x0
9898 01:16:07.923079 INFO: [APUAPC] D1_APC_0: 0xffffffff
9899 01:16:07.926905 INFO: [APUAPC] D1_APC_1: 0xffffffff
9900 01:16:07.929533 INFO: [APUAPC] D1_APC_2: 0x3fffff
9901 01:16:07.932937 INFO: [APUAPC] D1_APC_3: 0x0
9902 01:16:07.936027 INFO: [APUAPC] D2_APC_0: 0xffffffff
9903 01:16:07.939946 INFO: [APUAPC] D2_APC_1: 0xffffffff
9904 01:16:07.942933 INFO: [APUAPC] D2_APC_2: 0x3fffff
9905 01:16:07.946536 INFO: [APUAPC] D2_APC_3: 0x0
9906 01:16:07.949827 INFO: [APUAPC] D3_APC_0: 0xffffffff
9907 01:16:07.953036 INFO: [APUAPC] D3_APC_1: 0xffffffff
9908 01:16:07.956487 INFO: [APUAPC] D3_APC_2: 0x3fffff
9909 01:16:07.959049 INFO: [APUAPC] D3_APC_3: 0x0
9910 01:16:07.962818 INFO: [APUAPC] D4_APC_0: 0xffffffff
9911 01:16:07.965755 INFO: [APUAPC] D4_APC_1: 0xffffffff
9912 01:16:07.969081 INFO: [APUAPC] D4_APC_2: 0x3fffff
9913 01:16:07.972676 INFO: [APUAPC] D4_APC_3: 0x0
9914 01:16:07.975569 INFO: [APUAPC] D5_APC_0: 0xffffffff
9915 01:16:07.978757 INFO: [APUAPC] D5_APC_1: 0xffffffff
9916 01:16:07.982318 INFO: [APUAPC] D5_APC_2: 0x3fffff
9917 01:16:07.985717 INFO: [APUAPC] D5_APC_3: 0x0
9918 01:16:07.988568 INFO: [APUAPC] D6_APC_0: 0xffffffff
9919 01:16:07.991818 INFO: [APUAPC] D6_APC_1: 0xffffffff
9920 01:16:07.995073 INFO: [APUAPC] D6_APC_2: 0x3fffff
9921 01:16:07.998677 INFO: [APUAPC] D6_APC_3: 0x0
9922 01:16:08.001718 INFO: [APUAPC] D7_APC_0: 0xffffffff
9923 01:16:08.005316 INFO: [APUAPC] D7_APC_1: 0xffffffff
9924 01:16:08.008589 INFO: [APUAPC] D7_APC_2: 0x3fffff
9925 01:16:08.011587 INFO: [APUAPC] D7_APC_3: 0x0
9926 01:16:08.015159 INFO: [APUAPC] D8_APC_0: 0xffffffff
9927 01:16:08.018490 INFO: [APUAPC] D8_APC_1: 0xffffffff
9928 01:16:08.021590 INFO: [APUAPC] D8_APC_2: 0x3fffff
9929 01:16:08.024919 INFO: [APUAPC] D8_APC_3: 0x0
9930 01:16:08.028427 INFO: [APUAPC] D9_APC_0: 0xffffffff
9931 01:16:08.031440 INFO: [APUAPC] D9_APC_1: 0xffffffff
9932 01:16:08.034577 INFO: [APUAPC] D9_APC_2: 0x3fffff
9933 01:16:08.038135 INFO: [APUAPC] D9_APC_3: 0x0
9934 01:16:08.041377 INFO: [APUAPC] D10_APC_0: 0xffffffff
9935 01:16:08.044377 INFO: [APUAPC] D10_APC_1: 0xffffffff
9936 01:16:08.048055 INFO: [APUAPC] D10_APC_2: 0x3fffff
9937 01:16:08.050997 INFO: [APUAPC] D10_APC_3: 0x0
9938 01:16:08.054637 INFO: [APUAPC] D11_APC_0: 0xffffffff
9939 01:16:08.057704 INFO: [APUAPC] D11_APC_1: 0xffffffff
9940 01:16:08.061184 INFO: [APUAPC] D11_APC_2: 0x3fffff
9941 01:16:08.064006 INFO: [APUAPC] D11_APC_3: 0x0
9942 01:16:08.067724 INFO: [APUAPC] D12_APC_0: 0xffffffff
9943 01:16:08.070970 INFO: [APUAPC] D12_APC_1: 0xffffffff
9944 01:16:08.074403 INFO: [APUAPC] D12_APC_2: 0x3fffff
9945 01:16:08.077309 INFO: [APUAPC] D12_APC_3: 0x0
9946 01:16:08.080491 INFO: [APUAPC] D13_APC_0: 0xffffffff
9947 01:16:08.084233 INFO: [APUAPC] D13_APC_1: 0xffffffff
9948 01:16:08.087437 INFO: [APUAPC] D13_APC_2: 0x3fffff
9949 01:16:08.090823 INFO: [APUAPC] D13_APC_3: 0x0
9950 01:16:08.093956 INFO: [APUAPC] D14_APC_0: 0xffffffff
9951 01:16:08.097222 INFO: [APUAPC] D14_APC_1: 0xffffffff
9952 01:16:08.100560 INFO: [APUAPC] D14_APC_2: 0x3fffff
9953 01:16:08.103990 INFO: [APUAPC] D14_APC_3: 0x0
9954 01:16:08.107083 INFO: [APUAPC] D15_APC_0: 0xffffffff
9955 01:16:08.109909 INFO: [APUAPC] D15_APC_1: 0xffffffff
9956 01:16:08.113709 INFO: [APUAPC] D15_APC_2: 0x3fffff
9957 01:16:08.116750 INFO: [APUAPC] D15_APC_3: 0x0
9958 01:16:08.119915 INFO: [APUAPC] APC_CON: 0x4
9959 01:16:08.123371 INFO: [NOCDAPC] D0_APC_0: 0x0
9960 01:16:08.126896 INFO: [NOCDAPC] D0_APC_1: 0x0
9961 01:16:08.129814 INFO: [NOCDAPC] D1_APC_0: 0x0
9962 01:16:08.133325 INFO: [NOCDAPC] D1_APC_1: 0xfff
9963 01:16:08.136714 INFO: [NOCDAPC] D2_APC_0: 0x0
9964 01:16:08.137138 INFO: [NOCDAPC] D2_APC_1: 0xfff
9965 01:16:08.139937 INFO: [NOCDAPC] D3_APC_0: 0x0
9966 01:16:08.142944 INFO: [NOCDAPC] D3_APC_1: 0xfff
9967 01:16:08.146602 INFO: [NOCDAPC] D4_APC_0: 0x0
9968 01:16:08.149450 INFO: [NOCDAPC] D4_APC_1: 0xfff
9969 01:16:08.153056 INFO: [NOCDAPC] D5_APC_0: 0x0
9970 01:16:08.156059 INFO: [NOCDAPC] D5_APC_1: 0xfff
9971 01:16:08.159761 INFO: [NOCDAPC] D6_APC_0: 0x0
9972 01:16:08.162669 INFO: [NOCDAPC] D6_APC_1: 0xfff
9973 01:16:08.166478 INFO: [NOCDAPC] D7_APC_0: 0x0
9974 01:16:08.169439 INFO: [NOCDAPC] D7_APC_1: 0xfff
9975 01:16:08.172571 INFO: [NOCDAPC] D8_APC_0: 0x0
9976 01:16:08.176371 INFO: [NOCDAPC] D8_APC_1: 0xfff
9977 01:16:08.176791 INFO: [NOCDAPC] D9_APC_0: 0x0
9978 01:16:08.179525 INFO: [NOCDAPC] D9_APC_1: 0xfff
9979 01:16:08.182368 INFO: [NOCDAPC] D10_APC_0: 0x0
9980 01:16:08.185858 INFO: [NOCDAPC] D10_APC_1: 0xfff
9981 01:16:08.189283 INFO: [NOCDAPC] D11_APC_0: 0x0
9982 01:16:08.192899 INFO: [NOCDAPC] D11_APC_1: 0xfff
9983 01:16:08.196404 INFO: [NOCDAPC] D12_APC_0: 0x0
9984 01:16:08.199157 INFO: [NOCDAPC] D12_APC_1: 0xfff
9985 01:16:08.202093 INFO: [NOCDAPC] D13_APC_0: 0x0
9986 01:16:08.205624 INFO: [NOCDAPC] D13_APC_1: 0xfff
9987 01:16:08.208796 INFO: [NOCDAPC] D14_APC_0: 0x0
9988 01:16:08.212112 INFO: [NOCDAPC] D14_APC_1: 0xfff
9989 01:16:08.215171 INFO: [NOCDAPC] D15_APC_0: 0x0
9990 01:16:08.218780 INFO: [NOCDAPC] D15_APC_1: 0xfff
9991 01:16:08.222282 INFO: [NOCDAPC] APC_CON: 0x4
9992 01:16:08.225164 INFO: [APUAPC] set_apusys_apc done
9993 01:16:08.228555 INFO: [DEVAPC] devapc_init done
9994 01:16:08.231756 INFO: GICv3 without legacy support detected.
9995 01:16:08.234962 INFO: ARM GICv3 driver initialized in EL3
9996 01:16:08.238647 INFO: Maximum SPI INTID supported: 639
9997 01:16:08.241535 INFO: BL31: Initializing runtime services
9998 01:16:08.247772 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9999 01:16:08.250887 INFO: SPM: enable CPC mode
10000 01:16:08.257850 INFO: mcdi ready for mcusys-off-idle and system suspend
10001 01:16:08.260889 INFO: BL31: Preparing for EL3 exit to normal world
10002 01:16:08.264294 INFO: Entry point address = 0x80000000
10003 01:16:08.267220 INFO: SPSR = 0x8
10004 01:16:08.272145
10005 01:16:08.272225
10006 01:16:08.272288
10007 01:16:08.275902 Starting depthcharge on Spherion...
10008 01:16:08.275989
10009 01:16:08.276050 Wipe memory regions:
10010 01:16:08.276124
10011 01:16:08.276785 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10012 01:16:08.276894 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10013 01:16:08.277006 Setting prompt string to ['asurada:']
10014 01:16:08.277131 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10015 01:16:08.278589 [0x00000040000000, 0x00000054600000)
10016 01:16:08.401324
10017 01:16:08.401509 [0x00000054660000, 0x00000080000000)
10018 01:16:08.661445
10019 01:16:08.661945 [0x000000821a7280, 0x000000ffe64000)
10020 01:16:09.405252
10021 01:16:09.405767 [0x00000100000000, 0x00000240000000)
10022 01:16:11.291734
10023 01:16:11.294591 Initializing XHCI USB controller at 0x11200000.
10024 01:16:12.332583
10025 01:16:12.335807 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10026 01:16:12.336291
10027 01:16:12.336626
10028 01:16:12.336942
10029 01:16:12.337713 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10031 01:16:12.438859 asurada: tftpboot 192.168.201.1 13468740/tftp-deploy-rrunqafy/kernel/image.itb 13468740/tftp-deploy-rrunqafy/kernel/cmdline
10032 01:16:12.439431 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10033 01:16:12.439973 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10034 01:16:12.444125 tftpboot 192.168.201.1 13468740/tftp-deploy-rrunqafy/kernel/image.itp-deploy-rrunqafy/kernel/cmdline
10035 01:16:12.444682
10036 01:16:12.445075 Waiting for link
10037 01:16:12.604504
10038 01:16:12.604664 R8152: Initializing
10039 01:16:12.604735
10040 01:16:12.607571 Version 6 (ocp_data = 5c30)
10041 01:16:12.607664
10042 01:16:12.610913 R8152: Done initializing
10043 01:16:12.611007
10044 01:16:12.611082 Adding net device
10045 01:16:14.478957
10046 01:16:14.479112 done.
10047 01:16:14.479182
10048 01:16:14.479250 MAC: 00:24:32:30:7c:7b
10049 01:16:14.479310
10050 01:16:14.482471 Sending DHCP discover... done.
10051 01:16:14.482573
10052 01:16:17.604955 Waiting for reply... done.
10053 01:16:17.605107
10054 01:16:17.605174 Sending DHCP request... done.
10055 01:16:17.608403
10056 01:16:17.612766 Waiting for reply... done.
10057 01:16:17.612846
10058 01:16:17.612909 My ip is 192.168.201.14
10059 01:16:17.612968
10060 01:16:17.616388 The DHCP server ip is 192.168.201.1
10061 01:16:17.616469
10062 01:16:17.622954 TFTP server IP predefined by user: 192.168.201.1
10063 01:16:17.623034
10064 01:16:17.629627 Bootfile predefined by user: 13468740/tftp-deploy-rrunqafy/kernel/image.itb
10065 01:16:17.629712
10066 01:16:17.632711 Sending tftp read request... done.
10067 01:16:17.632791
10068 01:16:17.632854 Waiting for the transfer...
10069 01:16:17.632912
10070 01:16:18.249685 00000000 ################################################################
10071 01:16:18.250366
10072 01:16:18.883593 00080000 ################################################################
10073 01:16:18.884033
10074 01:16:19.536237 00100000 ################################################################
10075 01:16:19.536385
10076 01:16:20.184944 00180000 ################################################################
10077 01:16:20.185462
10078 01:16:20.811223 00200000 ################################################################
10079 01:16:20.811394
10080 01:16:21.427140 00280000 ################################################################
10081 01:16:21.427285
10082 01:16:22.050418 00300000 ################################################################
10083 01:16:22.050575
10084 01:16:22.695521 00380000 ################################################################
10085 01:16:22.696099
10086 01:16:23.338404 00400000 ################################################################
10087 01:16:23.338550
10088 01:16:23.980341 00480000 ################################################################
10089 01:16:23.980897
10090 01:16:24.580075 00500000 ################################################################
10091 01:16:24.580221
10092 01:16:25.142037 00580000 ################################################################
10093 01:16:25.142211
10094 01:16:25.756139 00600000 ################################################################
10095 01:16:25.756691
10096 01:16:26.358446 00680000 ################################################################
10097 01:16:26.358588
10098 01:16:26.982678 00700000 ################################################################
10099 01:16:26.983198
10100 01:16:27.589462 00780000 ################################################################
10101 01:16:27.589862
10102 01:16:28.216939 00800000 ################################################################
10103 01:16:28.217637
10104 01:16:28.848292 00880000 ################################################################
10105 01:16:28.848561
10106 01:16:29.475935 00900000 ################################################################
10107 01:16:29.476455
10108 01:16:30.100378 00980000 ################################################################
10109 01:16:30.100524
10110 01:16:30.744427 00a00000 ################################################################
10111 01:16:30.744969
10112 01:16:31.405481 00a80000 ################################################################
10113 01:16:31.405995
10114 01:16:32.069592 00b00000 ################################################################
10115 01:16:32.070099
10116 01:16:32.697131 00b80000 ################################################################
10117 01:16:32.697285
10118 01:16:33.349270 00c00000 ################################################################
10119 01:16:33.349511
10120 01:16:33.978584 00c80000 ################################################################
10121 01:16:33.978829
10122 01:16:34.599484 00d00000 ################################################################
10123 01:16:34.600052
10124 01:16:35.205769 00d80000 ################################################################
10125 01:16:35.205912
10126 01:16:35.831300 00e00000 ################################################################
10127 01:16:35.831453
10128 01:16:36.469716 00e80000 ################################################################
10129 01:16:36.470419
10130 01:16:37.079106 00f00000 ################################################################
10131 01:16:37.079489
10132 01:16:37.742349 00f80000 ################################################################
10133 01:16:37.742856
10134 01:16:38.411043 01000000 ################################################################
10135 01:16:38.411667
10136 01:16:39.038221 01080000 ################################################################
10137 01:16:39.038388
10138 01:16:39.594762 01100000 ################################################################
10139 01:16:39.594915
10140 01:16:40.144031 01180000 ################################################################
10141 01:16:40.144184
10142 01:16:40.766394 01200000 ################################################################
10143 01:16:40.766793
10144 01:16:41.396188 01280000 ################################################################
10145 01:16:41.396707
10146 01:16:42.057558 01300000 ################################################################
10147 01:16:42.058232
10148 01:16:42.714360 01380000 ################################################################
10149 01:16:42.714864
10150 01:16:43.319760 01400000 ################################################################
10151 01:16:43.319967
10152 01:16:43.966830 01480000 ################################################################
10153 01:16:43.967343
10154 01:16:44.631295 01500000 ################################################################
10155 01:16:44.631944
10156 01:16:45.271192 01580000 ################################################################
10157 01:16:45.271347
10158 01:16:45.883631 01600000 ################################################################
10159 01:16:45.884222
10160 01:16:46.530427 01680000 ################################################################
10161 01:16:46.531089
10162 01:16:47.182171 01700000 ################################################################
10163 01:16:47.182773
10164 01:16:47.835226 01780000 ################################################################
10165 01:16:47.835736
10166 01:16:48.491313 01800000 ################################################################
10167 01:16:48.491817
10168 01:16:49.173369 01880000 ################################################################
10169 01:16:49.174081
10170 01:16:49.813731 01900000 ################################################################
10171 01:16:49.814240
10172 01:16:50.468006 01980000 ################################################################
10173 01:16:50.468508
10174 01:16:51.118607 01a00000 ################################################################
10175 01:16:51.119268
10176 01:16:51.774731 01a80000 ################################################################
10177 01:16:51.775293
10178 01:16:52.394112 01b00000 ################################################################
10179 01:16:52.394616
10180 01:16:53.050642 01b80000 ################################################################
10181 01:16:53.051153
10182 01:16:53.646393 01c00000 ################################################################
10183 01:16:53.646543
10184 01:16:54.210224 01c80000 ################################################################
10185 01:16:54.210366
10186 01:16:54.820850 01d00000 ################################################################
10187 01:16:54.821009
10188 01:16:55.426151 01d80000 ################################################################
10189 01:16:55.426652
10190 01:16:56.071265 01e00000 ################################################################
10191 01:16:56.071436
10192 01:16:56.703621 01e80000 ################################################################
10193 01:16:56.703773
10194 01:16:57.344230 01f00000 ################################################################
10195 01:16:57.344735
10196 01:16:58.015013 01f80000 ################################################################
10197 01:16:58.015522
10198 01:16:58.676953 02000000 ################################################################
10199 01:16:58.677476
10200 01:16:59.334726 02080000 ################################################################
10201 01:16:59.335233
10202 01:16:59.992079 02100000 ################################################################
10203 01:16:59.992231
10204 01:17:00.612358 02180000 ################################################################
10205 01:17:00.612518
10206 01:17:01.264782 02200000 ################################################################
10207 01:17:01.265299
10208 01:17:01.914980 02280000 ################################################################
10209 01:17:01.915133
10210 01:17:02.554500 02300000 ################################################################
10211 01:17:02.554641
10212 01:17:03.152506 02380000 ################################################################
10213 01:17:03.152638
10214 01:17:03.769496 02400000 ################################################################
10215 01:17:03.769658
10216 01:17:04.409185 02480000 ################################################################
10217 01:17:04.409724
10218 01:17:04.998501 02500000 ################################################################
10219 01:17:04.999059
10220 01:17:05.632673 02580000 ################################################################
10221 01:17:05.633388
10222 01:17:06.280182 02600000 ################################################################
10223 01:17:06.280703
10224 01:17:06.931271 02680000 ################################################################
10225 01:17:06.931626
10226 01:17:07.568611 02700000 ################################################################
10227 01:17:07.569285
10228 01:17:08.175115 02780000 ################################################################
10229 01:17:08.175620
10230 01:17:08.790689 02800000 ################################################################
10231 01:17:08.790838
10232 01:17:09.393260 02880000 ################################################################
10233 01:17:09.393875
10234 01:17:10.048835 02900000 ################################################################
10235 01:17:10.049444
10236 01:17:10.687714 02980000 ################################################################
10237 01:17:10.688051
10238 01:17:11.324046 02a00000 ################################################################
10239 01:17:11.324880
10240 01:17:11.976711 02a80000 ################################################################
10241 01:17:11.977231
10242 01:17:12.609690 02b00000 ################################################################
10243 01:17:12.610188
10244 01:17:13.273505 02b80000 ################################################################
10245 01:17:13.274025
10246 01:17:13.880783 02c00000 ################################################################
10247 01:17:13.880936
10248 01:17:14.480911 02c80000 ################################################################
10249 01:17:14.481061
10250 01:17:15.085262 02d00000 ################################################################
10251 01:17:15.085441
10252 01:17:15.644946 02d80000 ################################################################
10253 01:17:15.645100
10254 01:17:16.249328 02e00000 ################################################################
10255 01:17:16.249907
10256 01:17:16.850155 02e80000 ################################################################
10257 01:17:16.850540
10258 01:17:17.506404 02f00000 ################################################################
10259 01:17:17.506907
10260 01:17:18.166464 02f80000 ################################################################
10261 01:17:18.166977
10262 01:17:18.817669 03000000 ################################################################
10263 01:17:18.818225
10264 01:17:19.483579 03080000 ################################################################
10265 01:17:19.484255
10266 01:17:20.126525 03100000 ################################################################
10267 01:17:20.127044
10268 01:17:20.771197 03180000 ################################################################
10269 01:17:20.771334
10270 01:17:21.357311 03200000 ################################################################
10271 01:17:21.357461
10272 01:17:21.951008 03280000 ################################################################
10273 01:17:21.951581
10274 01:17:22.609054 03300000 ################################################################
10275 01:17:22.609556
10276 01:17:23.274023 03380000 ################################################################
10277 01:17:23.274539
10278 01:17:23.942076 03400000 ################################################################
10279 01:17:23.942590
10280 01:17:24.607879 03480000 ################################################################
10281 01:17:24.608456
10282 01:17:25.269034 03500000 ################################################################
10283 01:17:25.269547
10284 01:17:25.942843 03580000 ################################################################
10285 01:17:25.943397
10286 01:17:26.590200 03600000 ################################################################
10287 01:17:26.590376
10288 01:17:27.242822 03680000 ################################################################
10289 01:17:27.243364
10290 01:17:27.897100 03700000 ################################################################
10291 01:17:27.897245
10292 01:17:28.460761 03780000 ################################################################
10293 01:17:28.460906
10294 01:17:29.003491 03800000 ################################################################
10295 01:17:29.003641
10296 01:17:29.576113 03880000 ################################################################
10297 01:17:29.576255
10298 01:17:30.133884 03900000 ################################################################
10299 01:17:30.134049
10300 01:17:30.705095 03980000 ################################################################
10301 01:17:30.705751
10302 01:17:31.331911 03a00000 ################################################################
10303 01:17:31.332092
10304 01:17:31.889905 03a80000 ################################################################
10305 01:17:31.890046
10306 01:17:32.473129 03b00000 ################################################################
10307 01:17:32.473686
10308 01:17:33.146418 03b80000 ################################################################
10309 01:17:33.147053
10310 01:17:33.806719 03c00000 ################################################################
10311 01:17:33.806878
10312 01:17:34.438985 03c80000 ################################################################
10313 01:17:34.439607
10314 01:17:35.099871 03d00000 ################################################################
10315 01:17:35.100425
10316 01:17:35.748900 03d80000 ################################################################
10317 01:17:35.749414
10318 01:17:36.386982 03e00000 ################################################################
10319 01:17:36.387533
10320 01:17:37.028905 03e80000 ################################################################
10321 01:17:37.029394
10322 01:17:37.682120 03f00000 ################################################################
10323 01:17:37.682266
10324 01:17:38.315650 03f80000 ################################################################
10325 01:17:38.315778
10326 01:17:38.972881 04000000 ################################################################
10327 01:17:38.973375
10328 01:17:39.580333 04080000 ################################################################
10329 01:17:39.580485
10330 01:17:40.149971 04100000 ################################################################
10331 01:17:40.150123
10332 01:17:40.718669 04180000 ################################################################
10333 01:17:40.718823
10334 01:17:41.311979 04200000 ################################################################
10335 01:17:41.312495
10336 01:17:41.956194 04280000 ################################################################
10337 01:17:41.956346
10338 01:17:42.610331 04300000 ################################################################
10339 01:17:42.610867
10340 01:17:43.273961 04380000 ################################################################
10341 01:17:43.274476
10342 01:17:43.910637 04400000 ################################################################
10343 01:17:43.911187
10344 01:17:44.550871 04480000 ################################################################
10345 01:17:44.551463
10346 01:17:45.172310 04500000 ################################################################
10347 01:17:45.172834
10348 01:17:45.819306 04580000 ################################################################
10349 01:17:45.820000
10350 01:17:46.471391 04600000 ################################################################
10351 01:17:46.471949
10352 01:17:47.121792 04680000 ################################################################
10353 01:17:47.122346
10354 01:17:47.794287 04700000 ################################################################
10355 01:17:47.794816
10356 01:17:48.408377 04780000 ################################################################
10357 01:17:48.408531
10358 01:17:49.031822 04800000 ################################################################
10359 01:17:49.032007
10360 01:17:49.659548 04880000 ################################################################
10361 01:17:49.659739
10362 01:17:50.286367 04900000 ################################################################
10363 01:17:50.286507
10364 01:17:50.923120 04980000 ################################################################
10365 01:17:50.923649
10366 01:17:51.570228 04a00000 ################################################################
10367 01:17:51.570404
10368 01:17:52.226870 04a80000 ################################################################
10369 01:17:52.227392
10370 01:17:52.902545 04b00000 ################################################################
10371 01:17:52.903048
10372 01:17:53.562134 04b80000 ################################################################
10373 01:17:53.562308
10374 01:17:54.189525 04c00000 ################################################################
10375 01:17:54.189671
10376 01:17:54.794339 04c80000 ################################################################
10377 01:17:54.794995
10378 01:17:55.408377 04d00000 ################################################################
10379 01:17:55.408846
10380 01:17:56.077664 04d80000 ################################################################
10381 01:17:56.078172
10382 01:17:56.716896 04e00000 ################################################################
10383 01:17:56.717061
10384 01:17:57.369237 04e80000 ################################################################
10385 01:17:57.369740
10386 01:17:58.039943 04f00000 ################################################################
10387 01:17:58.040500
10388 01:17:58.695249 04f80000 ################################################################
10389 01:17:58.695398
10390 01:17:59.316964 05000000 ################################################################
10391 01:17:59.317662
10392 01:17:59.964619 05080000 ################################################################
10393 01:17:59.964757
10394 01:18:00.534786 05100000 ################################################################
10395 01:18:00.534925
10396 01:18:01.084464 05180000 ################################################################
10397 01:18:01.084600
10398 01:18:01.641767 05200000 ################################################################
10399 01:18:01.641916
10400 01:18:02.203354 05280000 ################################################################
10401 01:18:02.203507
10402 01:18:02.754774 05300000 ################################################################
10403 01:18:02.754915
10404 01:18:03.319871 05380000 ################################################################
10405 01:18:03.320050
10406 01:18:03.890792 05400000 ################################################################
10407 01:18:03.890940
10408 01:18:04.444932 05480000 ################################################################
10409 01:18:04.445074
10410 01:18:05.004517 05500000 ################################################################
10411 01:18:05.004716
10412 01:18:05.571300 05580000 ################################################################
10413 01:18:05.571449
10414 01:18:06.125700 05600000 ################################################################
10415 01:18:06.125846
10416 01:18:06.667901 05680000 ################################################################
10417 01:18:06.668057
10418 01:18:07.216851 05700000 ################################################################
10419 01:18:07.216987
10420 01:18:07.768554 05780000 ################################################################
10421 01:18:07.768701
10422 01:18:08.322205 05800000 ################################################################
10423 01:18:08.322353
10424 01:18:08.872318 05880000 ################################################################
10425 01:18:08.872469
10426 01:18:09.433858 05900000 ################################################################
10427 01:18:09.434005
10428 01:18:09.992727 05980000 ################################################################
10429 01:18:09.992874
10430 01:18:10.560723 05a00000 ################################################################
10431 01:18:10.560873
10432 01:18:11.129897 05a80000 ################################################################
10433 01:18:11.130048
10434 01:18:11.690140 05b00000 ################################################################
10435 01:18:11.690291
10436 01:18:12.246763 05b80000 ################################################################
10437 01:18:12.246912
10438 01:18:12.818458 05c00000 ################################################################
10439 01:18:12.818618
10440 01:18:13.377105 05c80000 ################################################################
10441 01:18:13.377264
10442 01:18:13.945691 05d00000 ################################################################
10443 01:18:13.945885
10444 01:18:14.499358 05d80000 ################################################################
10445 01:18:14.499574
10446 01:18:15.061291 05e00000 ################################################################
10447 01:18:15.061462
10448 01:18:15.600307 05e80000 ################################################################
10449 01:18:15.600465
10450 01:18:16.161226 05f00000 ################################################################
10451 01:18:16.161409
10452 01:18:16.725828 05f80000 ################################################################
10453 01:18:16.725989
10454 01:18:17.274038 06000000 ################################################################
10455 01:18:17.274214
10456 01:18:17.828622 06080000 ################################################################
10457 01:18:17.828795
10458 01:18:18.404282 06100000 ################################################################
10459 01:18:18.404441
10460 01:18:18.966763 06180000 ################################################################
10461 01:18:18.966912
10462 01:18:19.535813 06200000 ################################################################
10463 01:18:19.536006
10464 01:18:20.110324 06280000 ################################################################
10465 01:18:20.110479
10466 01:18:20.681703 06300000 ################################################################
10467 01:18:20.681870
10468 01:18:21.232442 06380000 ################################################################
10469 01:18:21.232598
10470 01:18:21.782958 06400000 ################################################################
10471 01:18:21.783108
10472 01:18:22.341664 06480000 ################################################################
10473 01:18:22.341815
10474 01:18:22.898935 06500000 ################################################################
10475 01:18:22.899090
10476 01:18:23.471970 06580000 ################################################################
10477 01:18:23.472377
10478 01:18:24.024918 06600000 ################################################################
10479 01:18:24.025069
10480 01:18:24.578379 06680000 ################################################################
10481 01:18:24.578527
10482 01:18:25.219409 06700000 ################################################################
10483 01:18:25.219942
10484 01:18:25.875264 06780000 ################################################################
10485 01:18:25.875779
10486 01:18:26.537161 06800000 ################################################################
10487 01:18:26.537673
10488 01:18:27.180300 06880000 ################################################################
10489 01:18:27.180483
10490 01:18:27.801146 06900000 ################################################################
10491 01:18:27.801706
10492 01:18:28.370115 06980000 ################################################################
10493 01:18:28.370257
10494 01:18:28.941042 06a00000 ################################################################
10495 01:18:28.941184
10496 01:18:29.579241 06a80000 ################################################################
10497 01:18:29.579427
10498 01:18:30.203136 06b00000 ################################################################
10499 01:18:30.203312
10500 01:18:30.848882 06b80000 ################################################################
10501 01:18:30.849022
10502 01:18:31.478682 06c00000 ################################################################
10503 01:18:31.479182
10504 01:18:32.134014 06c80000 ################################################################
10505 01:18:32.134508
10506 01:18:32.770651 06d00000 ################################################################
10507 01:18:32.770878
10508 01:18:33.420630 06d80000 ################################################################
10509 01:18:33.421130
10510 01:18:34.074491 06e00000 ################################################################
10511 01:18:34.075149
10512 01:18:34.635291 06e80000 ################################################################
10513 01:18:34.635448
10514 01:18:35.188414 06f00000 ################################################################
10515 01:18:35.188551
10516 01:18:35.712237 06f80000 ################################################################
10517 01:18:35.712411
10518 01:18:36.254647 07000000 ################################################################
10519 01:18:36.254790
10520 01:18:36.776030 07080000 ################################################################
10521 01:18:36.776200
10522 01:18:37.302137 07100000 ################################################################
10523 01:18:37.302278
10524 01:18:37.828460 07180000 ################################################################
10525 01:18:37.828601
10526 01:18:38.348402 07200000 ################################################################
10527 01:18:38.348545
10528 01:18:38.873242 07280000 ################################################################
10529 01:18:38.873386
10530 01:18:39.398761 07300000 ################################################################
10531 01:18:39.398901
10532 01:18:39.928514 07380000 ################################################################
10533 01:18:39.928647
10534 01:18:40.265886 07400000 ######################################### done.
10535 01:18:40.266024
10536 01:18:40.269588 The bootfile was 121967390 bytes long.
10537 01:18:40.269668
10538 01:18:40.272959 Sending tftp read request... done.
10539 01:18:40.273030
10540 01:18:40.273111 Waiting for the transfer...
10541 01:18:40.275879
10542 01:18:40.275986 00000000 # done.
10543 01:18:40.276051
10544 01:18:40.282850 Command line loaded dynamically from TFTP file: 13468740/tftp-deploy-rrunqafy/kernel/cmdline
10545 01:18:40.282932
10546 01:18:40.295604 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10547 01:18:40.298949
10548 01:18:40.299031 Loading FIT.
10549 01:18:40.299097
10550 01:18:40.302593 Image ramdisk-1 has 109008076 bytes.
10551 01:18:40.302734
10552 01:18:40.305802 Image fdt-1 has 47230 bytes.
10553 01:18:40.305874
10554 01:18:40.308839 Image kernel-1 has 12910050 bytes.
10555 01:18:40.308915
10556 01:18:40.315242 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10557 01:18:40.315322
10558 01:18:40.335352 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10559 01:18:40.335437
10560 01:18:40.338862 Choosing best match conf-1 for compat google,spherion-rev2.
10561 01:18:40.343472
10562 01:18:40.348037 Connected to device vid:did:rid of 1ae0:0028:00
10563 01:18:40.355137
10564 01:18:40.358336 tpm_get_response: command 0x17b, return code 0x0
10565 01:18:40.358415
10566 01:18:40.361300 ec_init: CrosEC protocol v3 supported (256, 248)
10567 01:18:40.364870
10568 01:18:40.368268 tpm_cleanup: add release locality here.
10569 01:18:40.368368
10570 01:18:40.371766 Shutting down all USB controllers.
10571 01:18:40.371838
10572 01:18:40.374774 Removing current net device
10573 01:18:40.374843
10574 01:18:40.378121 Exiting depthcharge with code 4 at timestamp: 181392075
10575 01:18:40.378194
10576 01:18:40.381805 LZMA decompressing kernel-1 to 0x821a6718
10577 01:18:40.384576
10578 01:18:40.387964 LZMA decompressing kernel-1 to 0x40000000
10579 01:18:41.981445
10580 01:18:41.981596 jumping to kernel
10581 01:18:41.982233 end: 2.2.4 bootloader-commands (duration 00:02:34) [common]
10582 01:18:41.982361 start: 2.2.5 auto-login-action (timeout 00:01:52) [common]
10583 01:18:41.982469 Setting prompt string to ['Linux version [0-9]']
10584 01:18:41.982569 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10585 01:18:41.982671 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10586 01:18:42.063362
10587 01:18:42.066501 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10588 01:18:42.070207 start: 2.2.5.1 login-action (timeout 00:01:51) [common]
10589 01:18:42.070298 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10590 01:18:42.070369 Setting prompt string to []
10591 01:18:42.070447 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10592 01:18:42.070536 Using line separator: #'\n'#
10593 01:18:42.070600 No login prompt set.
10594 01:18:42.070661 Parsing kernel messages
10595 01:18:42.070717 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10596 01:18:42.070827 [login-action] Waiting for messages, (timeout 00:01:51)
10597 01:18:42.070891 Waiting using forced prompt support (timeout 00:00:56)
10598 01:18:42.089597 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j174389-arm64-gcc-10-defconfig-arm64-chromebook-96m9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024
10599 01:18:42.093100 [ 0.000000] random: crng init done
10600 01:18:42.099656 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10601 01:18:42.102620 [ 0.000000] efi: UEFI not found.
10602 01:18:42.109677 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10603 01:18:42.115704 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10604 01:18:42.125876 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10605 01:18:42.135531 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10606 01:18:42.142576 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10607 01:18:42.149087 [ 0.000000] printk: bootconsole [mtk8250] enabled
10608 01:18:42.155721 [ 0.000000] NUMA: No NUMA configuration found
10609 01:18:42.162266 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10610 01:18:42.168804 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10611 01:18:42.168916 [ 0.000000] Zone ranges:
10612 01:18:42.174992 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10613 01:18:42.178587 [ 0.000000] DMA32 empty
10614 01:18:42.185274 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10615 01:18:42.188274 [ 0.000000] Movable zone start for each node
10616 01:18:42.191755 [ 0.000000] Early memory node ranges
10617 01:18:42.198230 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10618 01:18:42.205127 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10619 01:18:42.211108 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10620 01:18:42.218484 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10621 01:18:42.224332 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10622 01:18:42.231232 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10623 01:18:42.288186 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10624 01:18:42.294550 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10625 01:18:42.301064 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10626 01:18:42.304298 [ 0.000000] psci: probing for conduit method from DT.
10627 01:18:42.310951 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10628 01:18:42.314016 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10629 01:18:42.321020 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10630 01:18:42.323920 [ 0.000000] psci: SMC Calling Convention v1.2
10631 01:18:42.330756 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10632 01:18:42.334287 [ 0.000000] Detected VIPT I-cache on CPU0
10633 01:18:42.340577 [ 0.000000] CPU features: detected: GIC system register CPU interface
10634 01:18:42.347267 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10635 01:18:42.353753 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10636 01:18:42.360444 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10637 01:18:42.370472 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10638 01:18:42.376904 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10639 01:18:42.379751 [ 0.000000] alternatives: applying boot alternatives
10640 01:18:42.386607 [ 0.000000] Fallback order for Node 0: 0
10641 01:18:42.393711 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10642 01:18:42.396590 [ 0.000000] Policy zone: Normal
10643 01:18:42.409743 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10644 01:18:42.419795 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10645 01:18:42.432175 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10646 01:18:42.442405 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10647 01:18:42.448877 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10648 01:18:42.452184 <6>[ 0.000000] software IO TLB: area num 8.
10649 01:18:42.508741 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10650 01:18:42.658391 <6>[ 0.000000] Memory: 7858056K/8385536K available (18048K kernel code, 4118K rwdata, 22292K rodata, 8448K init, 616K bss, 494712K reserved, 32768K cma-reserved)
10651 01:18:42.664764 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10652 01:18:42.671321 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10653 01:18:42.674421 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10654 01:18:42.680808 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10655 01:18:42.688004 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10656 01:18:42.691010 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10657 01:18:42.700549 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10658 01:18:42.707173 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10659 01:18:42.713891 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10660 01:18:42.720451 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10661 01:18:42.723631 <6>[ 0.000000] GICv3: 608 SPIs implemented
10662 01:18:42.726896 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10663 01:18:42.734025 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10664 01:18:42.737055 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10665 01:18:42.743467 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10666 01:18:42.756802 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10667 01:18:42.769781 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10668 01:18:42.776378 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10669 01:18:42.784598 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10670 01:18:42.797999 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10671 01:18:42.804428 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10672 01:18:42.811026 <6>[ 0.009187] Console: colour dummy device 80x25
10673 01:18:42.820761 <6>[ 0.013916] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10674 01:18:42.827230 <6>[ 0.024358] pid_max: default: 32768 minimum: 301
10675 01:18:42.830529 <6>[ 0.029231] LSM: Security Framework initializing
10676 01:18:42.837299 <6>[ 0.034169] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10677 01:18:42.847443 <6>[ 0.042032] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10678 01:18:42.857382 <6>[ 0.051446] cblist_init_generic: Setting adjustable number of callback queues.
10679 01:18:42.863722 <6>[ 0.058934] cblist_init_generic: Setting shift to 3 and lim to 1.
10680 01:18:42.870371 <6>[ 0.065273] cblist_init_generic: Setting adjustable number of callback queues.
10681 01:18:42.876640 <6>[ 0.072700] cblist_init_generic: Setting shift to 3 and lim to 1.
10682 01:18:42.880188 <6>[ 0.079101] rcu: Hierarchical SRCU implementation.
10683 01:18:42.886738 <6>[ 0.084116] rcu: Max phase no-delay instances is 1000.
10684 01:18:42.893281 <6>[ 0.091143] EFI services will not be available.
10685 01:18:42.896808 <6>[ 0.096129] smp: Bringing up secondary CPUs ...
10686 01:18:42.905479 <6>[ 0.101177] Detected VIPT I-cache on CPU1
10687 01:18:42.911790 <6>[ 0.101248] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10688 01:18:42.918829 <6>[ 0.101280] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10689 01:18:42.921838 <6>[ 0.101612] Detected VIPT I-cache on CPU2
10690 01:18:42.928455 <6>[ 0.101660] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10691 01:18:42.934978 <6>[ 0.101676] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10692 01:18:42.941615 <6>[ 0.101932] Detected VIPT I-cache on CPU3
10693 01:18:42.948579 <6>[ 0.101978] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10694 01:18:42.955214 <6>[ 0.101992] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10695 01:18:42.958211 <6>[ 0.102294] CPU features: detected: Spectre-v4
10696 01:18:42.964942 <6>[ 0.102299] CPU features: detected: Spectre-BHB
10697 01:18:42.968291 <6>[ 0.102304] Detected PIPT I-cache on CPU4
10698 01:18:42.974807 <6>[ 0.102354] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10699 01:18:42.981475 <6>[ 0.102370] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10700 01:18:42.987543 <6>[ 0.102646] Detected PIPT I-cache on CPU5
10701 01:18:42.994017 <6>[ 0.102701] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10702 01:18:43.000690 <6>[ 0.102718] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10703 01:18:43.004122 <6>[ 0.102995] Detected PIPT I-cache on CPU6
10704 01:18:43.014233 <6>[ 0.103058] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10705 01:18:43.020781 <6>[ 0.103074] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10706 01:18:43.023824 <6>[ 0.103372] Detected PIPT I-cache on CPU7
10707 01:18:43.030615 <6>[ 0.103437] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10708 01:18:43.036982 <6>[ 0.103453] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10709 01:18:43.040241 <6>[ 0.103500] smp: Brought up 1 node, 8 CPUs
10710 01:18:43.046824 <6>[ 0.244816] SMP: Total of 8 processors activated.
10711 01:18:43.050006 <6>[ 0.249738] CPU features: detected: 32-bit EL0 Support
10712 01:18:43.060335 <6>[ 0.255101] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10713 01:18:43.067167 <6>[ 0.263902] CPU features: detected: Common not Private translations
10714 01:18:43.073609 <6>[ 0.270418] CPU features: detected: CRC32 instructions
10715 01:18:43.079771 <6>[ 0.275769] CPU features: detected: RCpc load-acquire (LDAPR)
10716 01:18:43.083353 <6>[ 0.281729] CPU features: detected: LSE atomic instructions
10717 01:18:43.089995 <6>[ 0.287547] CPU features: detected: Privileged Access Never
10718 01:18:43.096325 <6>[ 0.293327] CPU features: detected: RAS Extension Support
10719 01:18:43.103403 <6>[ 0.298936] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10720 01:18:43.106742 <6>[ 0.306158] CPU: All CPU(s) started at EL2
10721 01:18:43.113161 <6>[ 0.310475] alternatives: applying system-wide alternatives
10722 01:18:43.122985 <6>[ 0.321292] devtmpfs: initialized
10723 01:18:43.138456 <6>[ 0.330165] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10724 01:18:43.145057 <6>[ 0.340123] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10725 01:18:43.151651 <6>[ 0.348274] pinctrl core: initialized pinctrl subsystem
10726 01:18:43.155358 <6>[ 0.354896] DMI not present or invalid.
10727 01:18:43.161277 <6>[ 0.359304] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10728 01:18:43.171327 <6>[ 0.366168] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10729 01:18:43.177915 <6>[ 0.373751] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10730 01:18:43.187716 <6>[ 0.381970] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10731 01:18:43.191470 <6>[ 0.390212] audit: initializing netlink subsys (disabled)
10732 01:18:43.201230 <5>[ 0.395907] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10733 01:18:43.207640 <6>[ 0.396602] thermal_sys: Registered thermal governor 'step_wise'
10734 01:18:43.214182 <6>[ 0.403875] thermal_sys: Registered thermal governor 'power_allocator'
10735 01:18:43.217285 <6>[ 0.410129] cpuidle: using governor menu
10736 01:18:43.224020 <6>[ 0.421084] NET: Registered PF_QIPCRTR protocol family
10737 01:18:43.230600 <6>[ 0.426569] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10738 01:18:43.237326 <6>[ 0.433672] ASID allocator initialised with 32768 entries
10739 01:18:43.241063 <6>[ 0.440239] Serial: AMBA PL011 UART driver
10740 01:18:43.250836 <4>[ 0.448977] Trying to register duplicate clock ID: 134
10741 01:18:43.304636 <6>[ 0.506332] KASLR enabled
10742 01:18:43.319247 <6>[ 0.513980] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10743 01:18:43.325743 <6>[ 0.520994] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10744 01:18:43.332620 <6>[ 0.527485] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10745 01:18:43.339124 <6>[ 0.534488] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10746 01:18:43.345156 <6>[ 0.540976] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10747 01:18:43.352293 <6>[ 0.547981] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10748 01:18:43.358506 <6>[ 0.554467] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10749 01:18:43.365290 <6>[ 0.561470] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10750 01:18:43.368345 <6>[ 0.568938] ACPI: Interpreter disabled.
10751 01:18:43.377127 <6>[ 0.575382] iommu: Default domain type: Translated
10752 01:18:43.383913 <6>[ 0.580496] iommu: DMA domain TLB invalidation policy: strict mode
10753 01:18:43.387345 <5>[ 0.587156] SCSI subsystem initialized
10754 01:18:43.393718 <6>[ 0.591405] usbcore: registered new interface driver usbfs
10755 01:18:43.400477 <6>[ 0.597135] usbcore: registered new interface driver hub
10756 01:18:43.403303 <6>[ 0.602689] usbcore: registered new device driver usb
10757 01:18:43.410365 <6>[ 0.608807] pps_core: LinuxPPS API ver. 1 registered
10758 01:18:43.420430 <6>[ 0.614000] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10759 01:18:43.423978 <6>[ 0.623340] PTP clock support registered
10760 01:18:43.426944 <6>[ 0.627579] EDAC MC: Ver: 3.0.0
10761 01:18:43.434823 <6>[ 0.632765] FPGA manager framework
10762 01:18:43.441045 <6>[ 0.636441] Advanced Linux Sound Architecture Driver Initialized.
10763 01:18:43.444600 <6>[ 0.643213] vgaarb: loaded
10764 01:18:43.451226 <6>[ 0.646365] clocksource: Switched to clocksource arch_sys_counter
10765 01:18:43.454175 <5>[ 0.652808] VFS: Disk quotas dquot_6.6.0
10766 01:18:43.460663 <6>[ 0.656997] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10767 01:18:43.464163 <6>[ 0.664190] pnp: PnP ACPI: disabled
10768 01:18:43.472583 <6>[ 0.670857] NET: Registered PF_INET protocol family
10769 01:18:43.482122 <6>[ 0.676446] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10770 01:18:43.494043 <6>[ 0.688779] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10771 01:18:43.503841 <6>[ 0.697595] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10772 01:18:43.510142 <6>[ 0.705562] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10773 01:18:43.520149 <6>[ 0.714264] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10774 01:18:43.526878 <6>[ 0.723979] TCP: Hash tables configured (established 65536 bind 65536)
10775 01:18:43.533516 <6>[ 0.730851] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10776 01:18:43.543321 <6>[ 0.738048] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10777 01:18:43.549860 <6>[ 0.745749] NET: Registered PF_UNIX/PF_LOCAL protocol family
10778 01:18:43.556462 <6>[ 0.751891] RPC: Registered named UNIX socket transport module.
10779 01:18:43.559442 <6>[ 0.758043] RPC: Registered udp transport module.
10780 01:18:43.565866 <6>[ 0.762973] RPC: Registered tcp transport module.
10781 01:18:43.573094 <6>[ 0.767907] RPC: Registered tcp NFSv4.1 backchannel transport module.
10782 01:18:43.575904 <6>[ 0.774572] PCI: CLS 0 bytes, default 64
10783 01:18:43.579030 <6>[ 0.778917] Unpacking initramfs...
10784 01:18:43.603585 <6>[ 0.798546] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10785 01:18:43.613453 <6>[ 0.807176] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10786 01:18:43.617004 <6>[ 0.816005] kvm [1]: IPA Size Limit: 40 bits
10787 01:18:43.623771 <6>[ 0.820530] kvm [1]: GICv3: no GICV resource entry
10788 01:18:43.626826 <6>[ 0.825548] kvm [1]: disabling GICv2 emulation
10789 01:18:43.633214 <6>[ 0.830230] kvm [1]: GIC system register CPU interface enabled
10790 01:18:43.636758 <6>[ 0.836407] kvm [1]: vgic interrupt IRQ18
10791 01:18:43.643047 <6>[ 0.840759] kvm [1]: VHE mode initialized successfully
10792 01:18:43.649751 <5>[ 0.847288] Initialise system trusted keyrings
10793 01:18:43.656210 <6>[ 0.852122] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10794 01:18:43.664015 <6>[ 0.862167] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10795 01:18:43.670478 <5>[ 0.868555] NFS: Registering the id_resolver key type
10796 01:18:43.673985 <5>[ 0.873855] Key type id_resolver registered
10797 01:18:43.680632 <5>[ 0.878270] Key type id_legacy registered
10798 01:18:43.687131 <6>[ 0.882549] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10799 01:18:43.693645 <6>[ 0.889468] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10800 01:18:43.700286 <6>[ 0.897171] 9p: Installing v9fs 9p2000 file system support
10801 01:18:43.736265 <5>[ 0.934317] Key type asymmetric registered
10802 01:18:43.739192 <5>[ 0.938648] Asymmetric key parser 'x509' registered
10803 01:18:43.749335 <6>[ 0.943788] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10804 01:18:43.752557 <6>[ 0.951400] io scheduler mq-deadline registered
10805 01:18:43.755850 <6>[ 0.956159] io scheduler kyber registered
10806 01:18:43.774892 <6>[ 0.973124] EINJ: ACPI disabled.
10807 01:18:43.806894 <4>[ 0.998539] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10808 01:18:43.816515 <4>[ 1.009170] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10809 01:18:43.831525 <6>[ 1.029759] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10810 01:18:43.839356 <6>[ 1.037683] printk: console [ttyS0] disabled
10811 01:18:43.867512 <6>[ 1.062313] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10812 01:18:43.873812 <6>[ 1.071784] printk: console [ttyS0] enabled
10813 01:18:43.877616 <6>[ 1.071784] printk: console [ttyS0] enabled
10814 01:18:43.883702 <6>[ 1.080677] printk: bootconsole [mtk8250] disabled
10815 01:18:43.887215 <6>[ 1.080677] printk: bootconsole [mtk8250] disabled
10816 01:18:43.893761 <6>[ 1.091666] SuperH (H)SCI(F) driver initialized
10817 01:18:43.897205 <6>[ 1.096933] msm_serial: driver initialized
10818 01:18:43.910975 <6>[ 1.105858] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10819 01:18:43.920668 <6>[ 1.114408] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10820 01:18:43.926994 <6>[ 1.122951] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10821 01:18:43.937164 <6>[ 1.131579] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10822 01:18:43.946986 <6>[ 1.140284] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10823 01:18:43.953768 <6>[ 1.149004] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10824 01:18:43.963503 <6>[ 1.157544] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10825 01:18:43.970361 <6>[ 1.166350] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10826 01:18:43.980309 <6>[ 1.174899] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10827 01:18:43.991682 <6>[ 1.190264] loop: module loaded
10828 01:18:43.998311 <6>[ 1.196215] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10829 01:18:44.021092 <4>[ 1.219317] mtk-pmic-keys: Failed to locate of_node [id: -1]
10830 01:18:44.027458 <6>[ 1.226043] megasas: 07.719.03.00-rc1
10831 01:18:44.037155 <6>[ 1.235557] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10832 01:18:44.047877 <6>[ 1.245747] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10833 01:18:44.064203 <6>[ 1.262454] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10834 01:18:44.120800 <6>[ 1.312564] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10835 01:18:48.207276 <6>[ 5.406269] Freeing initrd memory: 106448K
10836 01:18:48.219349 <6>[ 5.417956] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10837 01:18:48.230065 <6>[ 5.428868] tun: Universal TUN/TAP device driver, 1.6
10838 01:18:48.233759 <6>[ 5.434940] thunder_xcv, ver 1.0
10839 01:18:48.236667 <6>[ 5.438443] thunder_bgx, ver 1.0
10840 01:18:48.239746 <6>[ 5.441933] nicpf, ver 1.0
10841 01:18:48.250557 <6>[ 5.445939] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10842 01:18:48.253804 <6>[ 5.453414] hns3: Copyright (c) 2017 Huawei Corporation.
10843 01:18:48.260370 <6>[ 5.459002] hclge is initializing
10844 01:18:48.263817 <6>[ 5.462580] e1000: Intel(R) PRO/1000 Network Driver
10845 01:18:48.270579 <6>[ 5.467709] e1000: Copyright (c) 1999-2006 Intel Corporation.
10846 01:18:48.273650 <6>[ 5.473722] e1000e: Intel(R) PRO/1000 Network Driver
10847 01:18:48.280187 <6>[ 5.478938] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10848 01:18:48.286881 <6>[ 5.485137] igb: Intel(R) Gigabit Ethernet Network Driver
10849 01:18:48.293360 <6>[ 5.490787] igb: Copyright (c) 2007-2014 Intel Corporation.
10850 01:18:48.300258 <6>[ 5.496624] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10851 01:18:48.306493 <6>[ 5.503141] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10852 01:18:48.310274 <6>[ 5.509606] sky2: driver version 1.30
10853 01:18:48.316892 <6>[ 5.514602] VFIO - User Level meta-driver version: 0.3
10854 01:18:48.323794 <6>[ 5.522849] usbcore: registered new interface driver usb-storage
10855 01:18:48.330892 <6>[ 5.529287] usbcore: registered new device driver onboard-usb-hub
10856 01:18:48.339833 <6>[ 5.538421] mt6397-rtc mt6359-rtc: registered as rtc0
10857 01:18:48.349358 <6>[ 5.543883] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-23T01:18:48 UTC (1713835128)
10858 01:18:48.353215 <6>[ 5.553442] i2c_dev: i2c /dev entries driver
10859 01:18:48.369667 <6>[ 5.565173] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10860 01:18:48.376124 <4>[ 5.573914] cpu cpu0: supply cpu not found, using dummy regulator
10861 01:18:48.383074 <4>[ 5.580338] cpu cpu1: supply cpu not found, using dummy regulator
10862 01:18:48.389412 <4>[ 5.586749] cpu cpu2: supply cpu not found, using dummy regulator
10863 01:18:48.396307 <4>[ 5.593167] cpu cpu3: supply cpu not found, using dummy regulator
10864 01:18:48.403035 <4>[ 5.599559] cpu cpu4: supply cpu not found, using dummy regulator
10865 01:18:48.409496 <4>[ 5.605957] cpu cpu5: supply cpu not found, using dummy regulator
10866 01:18:48.416074 <4>[ 5.612352] cpu cpu6: supply cpu not found, using dummy regulator
10867 01:18:48.422417 <4>[ 5.618750] cpu cpu7: supply cpu not found, using dummy regulator
10868 01:18:48.440857 <6>[ 5.639399] cpu cpu0: EM: created perf domain
10869 01:18:48.444002 <6>[ 5.644357] cpu cpu4: EM: created perf domain
10870 01:18:48.450964 <6>[ 5.649723] sdhci: Secure Digital Host Controller Interface driver
10871 01:18:48.457329 <6>[ 5.656155] sdhci: Copyright(c) Pierre Ossman
10872 01:18:48.464262 <6>[ 5.661112] Synopsys Designware Multimedia Card Interface Driver
10873 01:18:48.470863 <6>[ 5.667767] sdhci-pltfm: SDHCI platform and OF driver helper
10874 01:18:48.473810 <6>[ 5.667795] mmc0: CQHCI version 5.10
10875 01:18:48.480912 <6>[ 5.677627] ledtrig-cpu: registered to indicate activity on CPUs
10876 01:18:48.487266 <6>[ 5.684611] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10877 01:18:48.493621 <6>[ 5.691662] usbcore: registered new interface driver usbhid
10878 01:18:48.497104 <6>[ 5.697487] usbhid: USB HID core driver
10879 01:18:48.504014 <6>[ 5.701686] spi_master spi0: will run message pump with realtime priority
10880 01:18:48.547797 <6>[ 5.739845] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10881 01:18:48.567281 <6>[ 5.755630] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10882 01:18:48.570485 <6>[ 5.770129] mmc0: Command Queue Engine enabled
10883 01:18:48.577185 <6>[ 5.774913] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10884 01:18:48.583644 <6>[ 5.781635] cros-ec-spi spi0.0: Chrome EC device registered
10885 01:18:48.587123 <6>[ 5.782195] mmcblk0: mmc0:0001 DA4128 116 GiB
10886 01:18:48.597357 <6>[ 5.796425] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10887 01:18:48.605599 <6>[ 5.804642] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10888 01:18:48.612513 <6>[ 5.810560] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10889 01:18:48.619346 <6>[ 5.816548] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10890 01:18:48.634139 <6>[ 5.829647] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10891 01:18:48.641357 <6>[ 5.840253] NET: Registered PF_PACKET protocol family
10892 01:18:48.644627 <6>[ 5.845651] 9pnet: Installing 9P2000 support
10893 01:18:48.651424 <5>[ 5.850218] Key type dns_resolver registered
10894 01:18:48.654981 <6>[ 5.855232] registered taskstats version 1
10895 01:18:48.661531 <5>[ 5.859618] Loading compiled-in X.509 certificates
10896 01:18:48.690918 <4>[ 5.883316] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10897 01:18:48.700971 <4>[ 5.894147] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10898 01:18:48.707579 <3>[ 5.904692] debugfs: File 'uA_load' in directory '/' already present!
10899 01:18:48.714452 <3>[ 5.911395] debugfs: File 'min_uV' in directory '/' already present!
10900 01:18:48.721016 <3>[ 5.918005] debugfs: File 'max_uV' in directory '/' already present!
10901 01:18:48.727745 <3>[ 5.924612] debugfs: File 'constraint_flags' in directory '/' already present!
10902 01:18:48.738812 <3>[ 5.934429] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10903 01:18:48.752058 <6>[ 5.950797] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10904 01:18:48.758577 <6>[ 5.957609] xhci-mtk 11200000.usb: xHCI Host Controller
10905 01:18:48.765533 <6>[ 5.963131] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10906 01:18:48.775527 <6>[ 5.971054] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10907 01:18:48.781952 <6>[ 5.980511] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10908 01:18:48.788744 <6>[ 5.986599] xhci-mtk 11200000.usb: xHCI Host Controller
10909 01:18:48.795317 <6>[ 5.992079] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10910 01:18:48.801804 <6>[ 5.999731] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10911 01:18:48.808893 <6>[ 6.007564] hub 1-0:1.0: USB hub found
10912 01:18:48.811848 <6>[ 6.011594] hub 1-0:1.0: 1 port detected
10913 01:18:48.821594 <6>[ 6.015882] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10914 01:18:48.825307 <6>[ 6.024590] hub 2-0:1.0: USB hub found
10915 01:18:48.828246 <6>[ 6.028612] hub 2-0:1.0: 1 port detected
10916 01:18:48.836761 <6>[ 6.035550] mtk-msdc 11f70000.mmc: Got CD GPIO
10917 01:18:48.850145 <6>[ 6.045833] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10918 01:18:48.856844 <6>[ 6.053866] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10919 01:18:48.866677 <4>[ 6.061784] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10920 01:18:48.877050 <6>[ 6.071327] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10921 01:18:48.883464 <6>[ 6.079403] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10922 01:18:48.890573 <6>[ 6.087427] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10923 01:18:48.899975 <6>[ 6.095345] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10924 01:18:48.906574 <6>[ 6.103161] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10925 01:18:48.916661 <6>[ 6.110978] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10926 01:18:48.926479 <6>[ 6.121461] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10927 01:18:48.933259 <6>[ 6.129820] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10928 01:18:48.943364 <6>[ 6.138167] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10929 01:18:48.949823 <6>[ 6.146507] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10930 01:18:48.959211 <6>[ 6.154846] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10931 01:18:48.969558 <6>[ 6.163184] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10932 01:18:48.975864 <6>[ 6.171523] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10933 01:18:48.985782 <6>[ 6.179860] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10934 01:18:48.992493 <6>[ 6.188197] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10935 01:18:49.002491 <6>[ 6.196535] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10936 01:18:49.009324 <6>[ 6.204873] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10937 01:18:49.018711 <6>[ 6.213212] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10938 01:18:49.025406 <6>[ 6.221572] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10939 01:18:49.035453 <6>[ 6.229910] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10940 01:18:49.042090 <6>[ 6.238249] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10941 01:18:49.048192 <6>[ 6.247015] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10942 01:18:49.055353 <6>[ 6.254196] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10943 01:18:49.062027 <6>[ 6.260969] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10944 01:18:49.072174 <6>[ 6.267750] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10945 01:18:49.078833 <6>[ 6.274675] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10946 01:18:49.085467 <6>[ 6.281531] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10947 01:18:49.095149 <6>[ 6.290663] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10948 01:18:49.105394 <6>[ 6.299782] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10949 01:18:49.115060 <6>[ 6.309076] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10950 01:18:49.125083 <6>[ 6.318543] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10951 01:18:49.131663 <6>[ 6.328010] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10952 01:18:49.141538 <6>[ 6.337130] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10953 01:18:49.151219 <6>[ 6.346600] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10954 01:18:49.161507 <6>[ 6.355723] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10955 01:18:49.171314 <6>[ 6.365017] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10956 01:18:49.181238 <6>[ 6.375178] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10957 01:18:49.191550 <6>[ 6.386797] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10958 01:18:49.238661 <6>[ 6.434635] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10959 01:18:49.394111 <6>[ 6.592723] hub 1-1:1.0: USB hub found
10960 01:18:49.397233 <6>[ 6.597237] hub 1-1:1.0: 4 ports detected
10961 01:18:49.407129 <6>[ 6.605937] hub 1-1:1.0: USB hub found
10962 01:18:49.409942 <6>[ 6.610278] hub 1-1:1.0: 4 ports detected
10963 01:18:49.519767 <6>[ 6.715099] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10964 01:18:49.545915 <6>[ 6.744615] hub 2-1:1.0: USB hub found
10965 01:18:49.549092 <6>[ 6.749126] hub 2-1:1.0: 3 ports detected
10966 01:18:49.558743 <6>[ 6.757466] hub 2-1:1.0: USB hub found
10967 01:18:49.561805 <6>[ 6.761938] hub 2-1:1.0: 3 ports detected
10968 01:18:49.734767 <6>[ 6.930745] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10969 01:18:49.867815 <6>[ 7.066687] hub 1-1.4:1.0: USB hub found
10970 01:18:49.871341 <6>[ 7.071372] hub 1-1.4:1.0: 2 ports detected
10971 01:18:49.880491 <6>[ 7.079266] hub 1-1.4:1.0: USB hub found
10972 01:18:49.883708 <6>[ 7.083823] hub 1-1.4:1.0: 2 ports detected
10973 01:18:49.950995 <6>[ 7.146770] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10974 01:18:50.179329 <6>[ 7.374690] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10975 01:18:50.370935 <6>[ 7.566689] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10976 01:19:01.467936 <6>[ 18.671721] ALSA device list:
10977 01:19:01.474500 <6>[ 18.675004] No soundcards found.
10978 01:19:01.482867 <6>[ 18.682682] Freeing unused kernel memory: 8448K
10979 01:19:01.485950 <6>[ 18.688321] Run /init as init process
10980 01:19:01.530412 <6>[ 18.730119] NET: Registered PF_INET6 protocol family
10981 01:19:01.536299 <6>[ 18.736287] Segment Routing with IPv6
10982 01:19:01.539490 <6>[ 18.740250] In-situ OAM (IOAM) with IPv6
10983 01:19:01.579121 <30>[ 18.752840] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10984 01:19:01.585724 <30>[ 18.785907] systemd[1]: Detected architecture arm64.
10985 01:19:01.585810
10986 01:19:01.592340 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10987 01:19:01.592438
10988 01:19:01.592563
10989 01:19:01.606699 <30>[ 18.806936] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10990 01:19:01.774749 <30>[ 18.971507] systemd[1]: Queued start job for default target graphical.target.
10991 01:19:01.803427 <30>[ 19.000396] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10992 01:19:01.809652 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10993 01:19:01.809735
10994 01:19:01.830255 <30>[ 19.026815] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10995 01:19:01.839764 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10996 01:19:01.839875
10997 01:19:01.854995 <30>[ 19.052165] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10998 01:19:01.865123 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10999 01:19:01.865228
11000 01:19:01.882528 <30>[ 19.079676] systemd[1]: Created slice user.slice - User and Session Slice.
11001 01:19:01.889265 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
11002 01:19:01.889361
11003 01:19:01.908888 <30>[ 19.102670] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
11004 01:19:01.915344 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
11005 01:19:01.915428
11006 01:19:01.937158 <30>[ 19.131044] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
11007 01:19:01.943722 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
11008 01:19:01.943827
11009 01:19:01.972151 <30>[ 19.158916] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
11010 01:19:01.982096 <30>[ 19.178718] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
11011 01:19:01.988092 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
11012 01:19:01.988171
11013 01:19:02.005626 <30>[ 19.202866] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
11014 01:19:02.012535 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
11015 01:19:02.012620
11016 01:19:02.029481 <30>[ 19.226632] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
11017 01:19:02.039522 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
11018 01:19:02.039633
11019 01:19:02.054932 <30>[ 19.255063] systemd[1]: Reached target paths.target - Path Units.
11020 01:19:02.061507 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
11021 01:19:02.064826
11022 01:19:02.081790 <30>[ 19.279005] systemd[1]: Reached target remote-fs.target - Remote File Systems.
11023 01:19:02.088355 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
11024 01:19:02.088437
11025 01:19:02.102300 <30>[ 19.302642] systemd[1]: Reached target slices.target - Slice Units.
11026 01:19:02.112096 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
11027 01:19:02.112178
11028 01:19:02.126766 <30>[ 19.327060] systemd[1]: Reached target swap.target - Swaps.
11029 01:19:02.133197 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
11030 01:19:02.133279
11031 01:19:02.153648 <30>[ 19.350738] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
11032 01:19:02.163766 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
11033 01:19:02.163877
11034 01:19:02.182700 <30>[ 19.379522] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
11035 01:19:02.192164 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
11036 01:19:02.192247
11037 01:19:02.211565 <30>[ 19.408459] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
11038 01:19:02.221194 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
11039 01:19:02.221286
11040 01:19:02.238441 <30>[ 19.435456] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
11041 01:19:02.248478 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
11042 01:19:02.248570
11043 01:19:02.266404 <30>[ 19.463497] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
11044 01:19:02.273051 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
11045 01:19:02.273137
11046 01:19:02.290261 <30>[ 19.487447] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
11047 01:19:02.300312 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
11048 01:19:02.300399
11049 01:19:02.318265 <30>[ 19.515250] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
11050 01:19:02.327919 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
11051 01:19:02.328017
11052 01:19:02.377782 <30>[ 19.574953] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
11053 01:19:02.384510 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
11054 01:19:02.384595
11055 01:19:02.398299 <30>[ 19.595164] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
11056 01:19:02.405123 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
11057 01:19:02.405207
11058 01:19:02.461931 <30>[ 19.659021] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
11059 01:19:02.468605 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
11060 01:19:02.468693
11061 01:19:02.497223 <30>[ 19.687280] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
11062 01:19:02.511200 <30>[ 19.708184] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
11063 01:19:02.521097 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
11064 01:19:02.521214
11065 01:19:02.543374 <30>[ 19.740316] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
11066 01:19:02.549938 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
11067 01:19:02.550087
11068 01:19:02.575372 <30>[ 19.772293] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
11069 01:19:02.584833 Startin<6>[ 19.781375] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
11070 01:19:02.591680 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
11071 01:19:02.591763
11072 01:19:02.650145 <30>[ 19.847196] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
11073 01:19:02.656585 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
11074 01:19:02.656668
11075 01:19:02.683421 <30>[ 19.880284] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
11076 01:19:02.693069 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
11077 01:19:02.693153
11078 01:19:02.742251 <30>[ 19.939277] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
11079 01:19:02.748812 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
11080 01:19:02.748902
11081 01:19:02.779322 <30>[ 19.976268] systemd[1]: Starting systemd-journald.service - Journal Service...
11082 01:19:02.785585 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
11083 01:19:02.785664
11084 01:19:02.807330 <30>[ 20.004581] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
11085 01:19:02.814051 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
11086 01:19:02.814137
11087 01:19:02.877631 <30>[ 20.071328] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
11088 01:19:02.884205 Starting [0;1;39msystemd-network-g… units from Kernel command line...
11089 01:19:02.884296
11090 01:19:02.907106 <30>[ 20.104101] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
11091 01:19:02.917034 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
11092 01:19:02.917148
11093 01:19:02.938560 <30>[ 20.135658] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
11094 01:19:02.945012 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
11095 01:19:02.945093
11096 01:19:02.968821 <30>[ 20.166161] systemd[1]: Started systemd-journald.service - Journal Service.
11097 01:19:02.975689 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11098 01:19:02.975766
11099 01:19:02.995239 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
11100 01:19:02.995328
11101 01:19:03.013691 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
11102 01:19:03.013804
11103 01:19:03.029929 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
11104 01:19:03.030015
11105 01:19:03.046295 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
11106 01:19:03.046387
11107 01:19:03.068268 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
11108 01:19:03.068358
11109 01:19:03.087938 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
11110 01:19:03.088017
11111 01:19:03.108741 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
11112 01:19:03.108820
11113 01:19:03.128531 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11114 01:19:03.128614
11115 01:19:03.148232 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11116 01:19:03.148325
11117 01:19:03.168348 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11118 01:19:03.168432
11119 01:19:03.187340 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11120 01:19:03.187421
11121 01:19:03.208227 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
11122 01:19:03.208307
11123 01:19:03.222421 See 'systemctl status systemd-remount-fs.service' for details.
11124 01:19:03.222501
11125 01:19:03.233025 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11126 01:19:03.233114
11127 01:19:03.252639 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11128 01:19:03.252728
11129 01:19:03.318238 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11130 01:19:03.318354
11131 01:19:03.339337 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11132 01:19:03.339426
11133 01:19:03.345690 <46>[ 20.544429] systemd-journald[186]: Received client request to flush runtime journal.
11134 01:19:03.363106 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11135 01:19:03.363195
11136 01:19:03.384420 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11137 01:19:03.384507
11138 01:19:03.404521 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11139 01:19:03.404607
11140 01:19:03.437656 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11141 01:19:03.437748
11142 01:19:03.459134 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11143 01:19:03.459221
11144 01:19:03.479076 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11145 01:19:03.479164
11146 01:19:03.499317 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11147 01:19:03.499396
11148 01:19:03.519319 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11149 01:19:03.519401
11150 01:19:03.574219 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11151 01:19:03.574322
11152 01:19:03.604294 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11153 01:19:03.604391
11154 01:19:03.622129 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11155 01:19:03.622215
11156 01:19:03.641729 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11157 01:19:03.641818
11158 01:19:03.698078 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11159 01:19:03.698170
11160 01:19:03.723328 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11161 01:19:03.723414
11162 01:19:03.749211 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11163 01:19:03.749307
11164 01:19:03.765905 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11165 01:19:03.765987
11166 01:19:03.786138 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11167 01:19:03.786220
11168 01:19:03.874439 [[0;32m OK [<6>[ 21.072475] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11169 01:19:03.884080 0m] Created slice [0;1;39msyste<3>[ 21.081901] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11170 01:19:03.891021 m-syste…- Slic<6>[ 21.082672] remoteproc remoteproc0: scp is available
11171 01:19:03.900869 <3>[ 21.091450] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11172 01:19:03.907415 e /system/system<6>[ 21.098232] mc: Linux media interface: v0.10
11173 01:19:03.914038 <6>[ 21.098574] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11174 01:19:03.914118 d-backlight.
11175 01:19:03.914189
11176 01:19:03.924063 <6>[ 21.098599] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11177 01:19:03.934004 <6>[ 21.098608] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11178 01:19:03.937119 <6>[ 21.099128] remoteproc remoteproc0: powering up scp
11179 01:19:03.947467 <6>[ 21.099132] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11180 01:19:03.950312 <6>[ 21.099139] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11181 01:19:03.960354 <3>[ 21.111976] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11182 01:19:03.967150 <6>[ 21.117733] usbcore: registered new device driver r8152-cfgselector
11183 01:19:03.973539 <4>[ 21.124508] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11184 01:19:03.980088 <3>[ 21.129677] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11185 01:19:03.990242 <4>[ 21.138287] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11186 01:19:03.996944 <3>[ 21.143658] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11187 01:19:04.004040 <6>[ 21.155358] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11188 01:19:04.014444 <3>[ 21.157479] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11189 01:19:04.021046 <4>[ 21.184318] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11190 01:19:04.027498 <4>[ 21.184318] Fallback method does not support PEC.
11191 01:19:04.033950 <3>[ 21.187564] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11192 01:19:04.044072 <3>[ 21.212806] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11193 01:19:04.051190 <3>[ 21.218551] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11194 01:19:04.058841 <3>[ 21.218584] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11195 01:19:04.068204 <6>[ 21.223654] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11196 01:19:04.071439 <6>[ 21.223658] pci_bus 0000:00: root bus resource [bus 00-ff]
11197 01:19:04.079470 <6>[ 21.223661] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11198 01:19:04.088843 <6>[ 21.223663] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11199 01:19:04.095469 <6>[ 21.223679] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11200 01:19:04.102565 <6>[ 21.223692] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11201 01:19:04.106191 <6>[ 21.223746] pci 0000:00:00.0: supports D1 D2
11202 01:19:04.116112 <6>[ 21.223748] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11203 01:19:04.122757 <6>[ 21.224402] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11204 01:19:04.129051 <6>[ 21.224466] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11205 01:19:04.135440 <6>[ 21.224490] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11206 01:19:04.142094 <6>[ 21.224505] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11207 01:19:04.152930 <6>[ 21.224520] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11208 01:19:04.159583 <6>[ 21.224535] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11209 01:19:04.163125 <6>[ 21.224620] pci 0000:01:00.0: supports D1 D2
11210 01:19:04.170483 <6>[ 21.224621] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11211 01:19:04.176752 <6>[ 21.234397] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11212 01:19:04.186331 <6>[ 21.240276] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11213 01:19:04.193511 <3>[ 21.240826] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11214 01:19:04.200201 <3>[ 21.240836] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11215 01:19:04.210375 <3>[ 21.240844] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11216 01:19:04.217073 <3>[ 21.240916] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11217 01:19:04.227243 <3>[ 21.240921] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11218 01:19:04.233647 <3>[ 21.240924] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11219 01:19:04.243500 <3>[ 21.240927] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11220 01:19:04.249829 <3>[ 21.240930] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11221 01:19:04.256783 <3>[ 21.240946] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11222 01:19:04.266793 <6>[ 21.241297] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11223 01:19:04.273261 <6>[ 21.242926] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11224 01:19:04.282871 <6>[ 21.249052] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11225 01:19:04.289699 <6>[ 21.250761] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11226 01:19:04.296441 <6>[ 21.257125] remoteproc remoteproc0: remote processor scp is now up
11227 01:19:04.307604 <6>[ 21.262627] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11228 01:19:04.313844 <6>[ 21.265331] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11229 01:19:04.324091 <3>[ 21.268829] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11230 01:19:04.333483 <6>[ 21.275199] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11231 01:19:04.340121 <6>[ 21.277856] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11232 01:19:04.350410 <3>[ 21.284959] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11233 01:19:04.357746 <6>[ 21.286096] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11234 01:19:04.367662 <6>[ 21.294871] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11235 01:19:04.374622 <6>[ 21.294884] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11236 01:19:04.384883 <4>[ 21.297788] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
11237 01:19:04.391399 <4>[ 21.297801] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
11238 01:19:04.402037 <3>[ 21.306930] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11239 01:19:04.405019 <6>[ 21.308616] pci 0000:00:00.0: PCI bridge to [bus 01]
11240 01:19:04.411676 <6>[ 21.313844] Bluetooth: Core ver 2.22
11241 01:19:04.415226 <6>[ 21.313847] videodev: Linux video capture interface: v2.00
11242 01:19:04.422183 <6>[ 21.319985] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11243 01:19:04.428759 <6>[ 21.320103] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11244 01:19:04.435940 <6>[ 21.328270] NET: Registered PF_BLUETOOTH protocol family
11245 01:19:04.443090 <6>[ 21.334889] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11246 01:19:04.449532 <6>[ 21.341971] Bluetooth: HCI device and connection manager initialized
11247 01:19:04.452515 <6>[ 21.341977] Bluetooth: HCI socket layer initialized
11248 01:19:04.460146 <6>[ 21.349603] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11249 01:19:04.463077 <6>[ 21.350445] r8152 2-1.3:1.0 eth0: v1.12.13
11250 01:19:04.470111 <6>[ 21.350520] usbcore: registered new interface driver r8152
11251 01:19:04.476717 <6>[ 21.356920] Bluetooth: L2CAP socket layer initialized
11252 01:19:04.484062 <6>[ 21.357498] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11253 01:19:04.494264 <6>[ 21.358460] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11254 01:19:04.500502 <6>[ 21.358530] usbcore: registered new interface driver uvcvideo
11255 01:19:04.507074 <6>[ 21.375647] usbcore: registered new interface driver cdc_ether
11256 01:19:04.510332 <6>[ 21.382205] Bluetooth: SCO socket layer initialized
11257 01:19:04.517246 <6>[ 21.383191] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11258 01:19:04.526891 <5>[ 21.383320] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11259 01:19:04.533214 <3>[ 21.391056] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11260 01:19:04.539688 <5>[ 21.391845] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11261 01:19:04.549846 <5>[ 21.392068] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11262 01:19:04.559787 <4>[ 21.392107] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11263 01:19:04.563251 <6>[ 21.392111] cfg80211: failed to load regulatory.db
11264 01:19:04.569694 <6>[ 21.399112] usbcore: registered new interface driver r8153_ecm
11265 01:19:04.576423 <6>[ 21.431810] usbcore: registered new interface driver btusb
11266 01:19:04.586399 <4>[ 21.439674] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11267 01:19:04.592842 <6>[ 21.455080] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
11268 01:19:04.599212 <6>[ 21.455559] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11269 01:19:04.605856 <3>[ 21.455634] Bluetooth: hci0: Failed to load firmware file (-2)
11270 01:19:04.612459 <3>[ 21.455641] Bluetooth: hci0: Failed to set up firmware (-2)
11271 01:19:04.622761 <4>[ 21.455647] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11272 01:19:04.628932 <3>[ 21.463678] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11273 01:19:04.635673 <6>[ 21.471887] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11274 01:19:04.645542 <3>[ 21.511864] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11275 01:19:04.655784 <3>[ 21.512673] power_supply sbs-5-000b: driver failed to report `voltage_now' property: -6
11276 01:19:04.658785 <6>[ 21.530400] mt7921e 0000:01:00.0: ASIC revision: 79610010
11277 01:19:04.668868 <3>[ 21.563928] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11278 01:19:04.678551 <3>[ 21.564725] power_supply sbs-5-000b: driver failed to report `manufacture_year' property: -6
11279 01:19:04.685003 <6>[ 21.648111] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11280 01:19:04.688590 <6>[ 21.648111]
11281 01:19:04.694747 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11282 01:19:04.694827
11283 01:19:04.741844 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11284 01:19:04.741943
11285 01:19:04.762646 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11286 01:19:04.762769
11287 01:19:04.782733 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11288 01:19:04.782818
11289 01:19:04.839114 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11290 01:19:04.839215
11291 01:19:04.881477 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11292 01:19:04.881574
11293 01:19:04.906649 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11294 01:19:04.906734
11295 01:19:04.925473 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11296 01:19:04.925555
11297 01:19:04.941730 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11298 01:19:04.941819
11299 01:19:04.956851 <6>[ 22.154397] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11300 01:19:04.963619 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11301 01:19:04.963723
11302 01:19:04.982798 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11303 01:19:04.982890
11304 01:19:05.001499 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11305 01:19:05.001587
11306 01:19:05.017895 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11307 01:19:05.017980
11308 01:19:05.037891 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11309 01:19:05.037985
11310 01:19:05.044421 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11311 01:19:05.044507
11312 01:19:05.061890 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11313 01:19:05.061976
11314 01:19:05.115084 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11315 01:19:05.115271
11316 01:19:05.142550 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11317 01:19:05.142680
11318 01:19:05.166761 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11319 01:19:05.166856
11320 01:19:05.196043 <46>[ 22.380331] systemd-journald[186]: Data hash table of /var/log/journal/6cfa758ce87d4acd800e1258fdce5dda/system.journal has a fill level at 75.8 (1551 of 2047 items, 524288 file size, 338 bytes per hash table item), suggesting rotation.
11321 01:19:05.209207 <46>[ 22.401642] systemd-journald[186]: /var/log/journal/6cfa758ce87d4acd800e1258fdce5dda/system.journal: Journal header limits reached or header out-of-date, rotating.
11322 01:19:05.219287 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11323 01:19:05.219375
11324 01:19:05.248951 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11325 01:19:05.249062
11326 01:19:05.302452 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11327 01:19:05.302557
11328 01:19:05.323287 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11329 01:19:05.323378
11330 01:19:05.341407 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11331 01:19:05.341507
11332 01:19:05.386205 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11333 01:19:05.386296
11334 01:19:05.406700 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11335 01:19:05.406790
11336 01:19:05.426408 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11337 01:19:05.426489
11338 01:19:05.448113 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11339 01:19:05.448203
11340 01:19:05.466454 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11341 01:19:05.466544
11342 01:19:05.522954 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11343 01:19:05.523048
11344 01:19:05.564158 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11345 01:19:05.564259
11346 01:19:05.613780
11347 01:19:05.613887
11348 01:19:05.616692 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11349 01:19:05.616772
11350 01:19:05.620246 debian-bookworm-arm64 login: root (automatic login)
11351 01:19:05.620325
11352 01:19:05.620385
11353 01:19:05.632203 Linux debian-bookworm-arm64 6.1.86-cip19 #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024 aarch64
11354 01:19:05.632295
11355 01:19:05.638808 The programs included with the Debian GNU/Linux system are free software;
11356 01:19:05.645411 the exact distribution terms for each program are described in the
11357 01:19:05.648265 individual files in /usr/share/doc/*/copyright.
11358 01:19:05.648340
11359 01:19:05.655495 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11360 01:19:05.658502 permitted by applicable law.
11361 01:19:05.659054 Matched prompt #10: / #
11363 01:19:05.659389 Setting prompt string to ['/ #']
11364 01:19:05.659522 end: 2.2.5.1 login-action (duration 00:00:24) [common]
11366 01:19:05.659898 end: 2.2.5 auto-login-action (duration 00:00:24) [common]
11367 01:19:05.660002 start: 2.2.6 expect-shell-connection (timeout 00:01:28) [common]
11368 01:19:05.660072 Setting prompt string to ['/ #']
11369 01:19:05.660132 Forcing a shell prompt, looking for ['/ #']
11371 01:19:05.710315 / #
11372 01:19:05.710423 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11373 01:19:05.710512 Waiting using forced prompt support (timeout 00:02:30)
11374 01:19:05.715591
11375 01:19:05.715913 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11376 01:19:05.716027 start: 2.2.7 export-device-env (timeout 00:01:28) [common]
11377 01:19:05.716136 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11378 01:19:05.716227 end: 2.2 depthcharge-retry (duration 00:03:32) [common]
11379 01:19:05.716315 end: 2 depthcharge-action (duration 00:03:32) [common]
11380 01:19:05.716417 start: 3 lava-test-retry (timeout 00:05:00) [common]
11381 01:19:05.716504 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11382 01:19:05.716583 Using namespace: common
11384 01:19:05.816894 / # #
11385 01:19:05.817025 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11386 01:19:05.818133 #<6>[ 23.018764] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11387 01:19:05.859991
11388 01:19:05.860272 Using /lava-13468740
11390 01:19:05.960544 / # export SHELL=/bin/sh
11391 01:19:05.965713 export SHELL=/bin/sh
11393 01:19:06.066177 / # . /lava-13468740/environment
11394 01:19:06.072012 . /lava-13468740/environment
11396 01:19:06.172482 / # /lava-13468740/bin/lava-test-runner /lava-13468740/0
11397 01:19:06.172640 Test shell timeout: 10s (minimum of the action and connection timeout)
11398 01:19:06.177860 /lava-13468740/bin/lava-test-runner /lava-13468740/0
11399 01:19:06.192669 + export TESTRUN_ID=0_sleep
11400 01:19:06.195559 + cd /lava-13468740/0/tests/0_sleep
11401 01:19:06.199268 + cat uuid
11402 01:19:06.199340 + UUID=13468740_1.5.2.3.1
11403 01:19:06.202384 + set +x
11404 01:19:06.205960 <LAVA_SIGNAL_STARTRUN 0_sleep 13468740_1.5.2.3.1>
11405 01:19:06.206225 Received signal: <STARTRUN> 0_sleep 13468740_1.5.2.3.1
11406 01:19:06.206295 Starting test lava.0_sleep (13468740_1.5.2.3.1)
11407 01:19:06.206383 Skipping test definition patterns.
11408 01:19:06.209043 + ./config/lava/sleep/sleep.sh mem
11409 01:19:06.212198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11410 01:19:06.212442 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11412 01:19:06.218718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11413 01:19:06.218982 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11415 01:19:06.222021 rtcwake: assuming RTC uses UTC ...
11416 01:19:06.232414 rtcwake: wakeup from "mem" using rtc0 at Tue Apr 23<6>[ 23.431591] PM: suspend entry (deep)
11417 01:19:06.232493 01:19:12 2024
11418 01:19:06.235349 <6>[ 23.436520] Filesystems sync: 0.000 seconds
11419 01:19:06.242993 <6>[ 23.443412] Freezing user space processes
11420 01:19:06.249073 <6>[ 23.449055] Freezing user space processes completed (elapsed 0.001 seconds)
11421 01:19:06.252570 <6>[ 23.456284] OOM killer disabled.
11422 01:19:06.259383 <6>[ 23.459765] Freezing remaining freezable tasks
11423 01:19:06.269154 <6>[ 23.465687] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11424 01:19:06.275411 <6>[ 23.473349] printk: Suspending console(s) (use no_console_suspend to debug)
11425 01:19:12.315331 <6>[ 23.618268] Disabling non-boot CPUs ...
11426 01:19:12.318841 <4>[ 23.619291] IRQ282: set affinity failed(-22).
11427 01:19:12.325419 <4>[ 23.619308] IRQ284: set affinity failed(-22).
11428 01:19:12.328669 <6>[ 23.620396] psci: CPU1 killed (polled 0 ms)
11429 01:19:12.332283 <4>[ 23.621719] IRQ282: set affinity failed(-22).
11430 01:19:12.338502 <4>[ 23.621732] IRQ284: set affinity failed(-22).
11431 01:19:12.342167 <6>[ 23.622396] psci: CPU2 killed (polled 4 ms)
11432 01:19:12.345191 <4>[ 23.623691] IRQ282: set affinity failed(-22).
11433 01:19:12.351517 <4>[ 23.623704] IRQ284: set affinity failed(-22).
11434 01:19:12.355138 <6>[ 23.624775] psci: CPU3 killed (polled 0 ms)
11435 01:19:12.361705 <4>[ 23.625546] IRQ282: set affinity failed(-22).
11436 01:19:12.365043 <4>[ 23.625550] IRQ284: set affinity failed(-22).
11437 01:19:12.368559 <6>[ 23.625587] psci: CPU4 killed (polled 0 ms)
11438 01:19:12.375109 <4>[ 23.626429] IRQ282: set affinity failed(-22).
11439 01:19:12.378615 <4>[ 23.626435] IRQ284: set affinity failed(-22).
11440 01:19:12.381473 <6>[ 23.626487] psci: CPU5 killed (polled 0 ms)
11441 01:19:12.388172 <6>[ 23.627357] psci: CPU6 killed (polled 0 ms)
11442 01:19:12.391972 <6>[ 23.628132] psci: CPU7 killed (polled 0 ms)
11443 01:19:12.394918 <6>[ 23.628647] Enabling non-boot CPUs ...
11444 01:19:12.401475 <6>[ 23.628893] Detected VIPT I-cache on CPU1
11445 01:19:12.408018 <6>[ 23.628985] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11446 01:19:12.414903 <6>[ 23.629049] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11447 01:19:12.418153 <6>[ 23.629697] CPU1 is up
11448 01:19:12.421524 <6>[ 23.629850] Detected VIPT I-cache on CPU2
11449 01:19:12.427791 <6>[ 23.629913] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11450 01:19:12.434878 <6>[ 23.629956] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11451 01:19:12.438373 <6>[ 23.630515] CPU2 is up
11452 01:19:12.441213 <6>[ 23.630669] Detected VIPT I-cache on CPU3
11453 01:19:12.448046 <6>[ 23.630732] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11454 01:19:12.457550 <6>[ 23.630774] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11455 01:19:12.457712 <6>[ 23.631328] CPU3 is up
11456 01:19:12.464248 <6>[ 23.631445] CPU features: detected: Hardware dirty bit management
11457 01:19:12.471401 <6>[ 23.631460] Detected PIPT I-cache on CPU4
11458 01:19:12.477762 <6>[ 23.631480] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11459 01:19:12.484418 <6>[ 23.631494] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11460 01:19:12.487700 <6>[ 23.631738] CPU4 is up
11461 01:19:12.490871 <6>[ 23.631866] Detected PIPT I-cache on CPU5
11462 01:19:12.497911 <6>[ 23.631888] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11463 01:19:12.504367 <6>[ 23.631902] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11464 01:19:12.507436 <6>[ 23.632134] CPU5 is up
11465 01:19:12.511306 <6>[ 23.632263] Detected PIPT I-cache on CPU6
11466 01:19:12.517447 <6>[ 23.632285] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11467 01:19:12.523966 <6>[ 23.632299] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11468 01:19:12.527382 <6>[ 23.632540] CPU6 is up
11469 01:19:12.533661 <6>[ 23.632667] Detected PIPT I-cache on CPU7
11470 01:19:12.540794 <6>[ 23.632689] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11471 01:19:12.547267 <6>[ 23.632703] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11472 01:19:12.551040 <6>[ 23.632947] CPU7 is up
11473 01:19:12.557330 <4>[ 23.772403] typec port0-partner: PM: parent port0 should not be sleeping
11474 01:19:12.560149 <6>[ 24.218044] OOM killer enabled.
11475 01:19:12.563563 <6>[ 24.221435] Restarting tasks ... done.
11476 01:19:12.570634 <5>[ 24.225799] random: crng reseeded on system resumption
11477 01:19:12.573969 <6>[ 24.232092] PM: suspend exit
11478 01:19:12.582460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=pass>
11479 01:19:12.583224 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=pass
11481 01:19:12.585482 rtcwake: assuming RTC uses UTC ...
11482 01:19:12.592477 rtcwake: wakeup from "mem" using rtc0 at Tue Apr 23 01:19:18 2024
11483 01:19:12.605032 <6>[ 24.262102] PM: suspend entry (deep)
11484 01:19:12.608757 <6>[ 24.265971] Filesystems sync: 0.000 seconds
11485 01:19:12.611616 <6>[ 24.270722] Freezing user space processes
11486 01:19:12.622629 <6>[ 24.276299] Freezing user space processes completed (elapsed 0.001 seconds)
11487 01:19:12.626055 <6>[ 24.283525] OOM killer disabled.
11488 01:19:12.629148 <6>[ 24.287008] Freezing remaining freezable tasks
11489 01:19:12.639238 <6>[ 24.292806] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11490 01:19:12.645408 <6>[ 24.300464] printk: Suspending console(s) (use no_console_suspend to debug)
11491 01:19:18.326263 <6>[ 24.372938] Disabling non-boot CPUs ...
11492 01:19:18.329904 <6>[ 24.373554] psci: CPU1 killed (polled 0 ms)
11493 01:19:18.336395 <4>[ 24.374198] NOHZ tick-stop error: local softirq work is pending, handler #45!!!
11494 01:19:18.343325 <6>[ 24.374326] psci: CPU2 killed (polled 0 ms)
11495 01:19:18.346701 <6>[ 24.375963] psci: CPU3 killed (polled 0 ms)
11496 01:19:18.349518 <6>[ 24.376352] psci: CPU4 killed (polled 0 ms)
11497 01:19:18.356581 <6>[ 24.376804] psci: CPU5 killed (polled 0 ms)
11498 01:19:18.359558 <6>[ 24.378187] psci: CPU6 killed (polled 0 ms)
11499 01:19:18.363034 <6>[ 24.379726] psci: CPU7 killed (polled 0 ms)
11500 01:19:18.369575 <6>[ 24.379988] Enabling non-boot CPUs ...
11501 01:19:18.373074 <6>[ 24.380162] Detected VIPT I-cache on CPU1
11502 01:19:18.379904 <6>[ 24.380224] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11503 01:19:18.386070 <6>[ 24.380266] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11504 01:19:18.389692 <6>[ 24.380684] CPU1 is up
11505 01:19:18.392410 <6>[ 24.380774] Detected VIPT I-cache on CPU2
11506 01:19:18.399151 <6>[ 24.380804] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11507 01:19:18.409262 <6>[ 24.380825] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11508 01:19:18.409348 <6>[ 24.381098] CPU2 is up
11509 01:19:18.415566 <6>[ 24.381185] Detected VIPT I-cache on CPU3
11510 01:19:18.422740 <6>[ 24.381216] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11511 01:19:18.429075 <6>[ 24.381237] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11512 01:19:18.432658 <6>[ 24.381515] CPU3 is up
11513 01:19:18.435539 <6>[ 24.381611] Detected PIPT I-cache on CPU4
11514 01:19:18.442282 <6>[ 24.381632] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11515 01:19:18.448887 <6>[ 24.381646] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11516 01:19:18.452412 <6>[ 24.381866] CPU4 is up
11517 01:19:18.455723 <6>[ 24.381959] Detected PIPT I-cache on CPU5
11518 01:19:18.465549 <6>[ 24.381980] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11519 01:19:18.472105 <6>[ 24.381994] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11520 01:19:18.472263 <6>[ 24.382216] CPU5 is up
11521 01:19:18.478676 <6>[ 24.382315] Detected PIPT I-cache on CPU6
11522 01:19:18.485416 <6>[ 24.382336] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11523 01:19:18.492379 <6>[ 24.382350] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11524 01:19:18.495266 <6>[ 24.382566] CPU6 is up
11525 01:19:18.498280 <6>[ 24.382661] Detected PIPT I-cache on CPU7
11526 01:19:18.505432 <6>[ 24.382682] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11527 01:19:18.512150 <6>[ 24.382696] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11528 01:19:18.515115 <6>[ 24.382929] CPU7 is up
11529 01:19:18.518640 <6>[ 24.929653] OOM killer enabled.
11530 01:19:18.522180 <6>[ 24.933045] Restarting tasks ... done.
11531 01:19:18.528459 <5>[ 24.937416] random: crng reseeded on system resumption
11532 01:19:18.531436 <6>[ 24.943903] PM: suspend exit
11533 01:19:18.541549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=pass>
11534 01:19:18.541812 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=pass
11536 01:19:18.545119 rtcwake: assuming RTC uses UTC ...
11537 01:19:18.551159 rtcwake: wakeup from "mem" using rtc0 at Tue Apr 23 01:19:24 2024
11538 01:19:18.563525 <6>[ 24.973213] PM: suspend entry (deep)
11539 01:19:18.567044 <6>[ 24.977080] Filesystems sync: 0.000 seconds
11540 01:19:18.570282 <6>[ 24.981814] Freezing user space processes
11541 01:19:18.580927 <6>[ 24.987375] Freezing user space processes completed (elapsed 0.001 seconds)
11542 01:19:18.584572 <6>[ 24.994596] OOM killer disabled.
11543 01:19:18.587580 <6>[ 24.998071] Freezing remaining freezable tasks
11544 01:19:18.597794 <6>[ 25.003959] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11545 01:19:18.604247 <6>[ 25.011618] printk: Suspending console(s) (use no_console_suspend to debug)
11546 01:19:24.317168 <6>[ 25.086920] Disabling non-boot CPUs ...
11547 01:19:24.320510 <6>[ 25.088041] psci: CPU1 killed (polled 0 ms)
11548 01:19:24.323994 <6>[ 25.089214] psci: CPU2 killed (polled 0 ms)
11549 01:19:24.330425 <6>[ 25.090333] psci: CPU3 killed (polled 0 ms)
11550 01:19:24.333678 <6>[ 25.090928] psci: CPU4 killed (polled 0 ms)
11551 01:19:24.336951 <6>[ 25.091547] psci: CPU5 killed (polled 0 ms)
11552 01:19:24.343785 <6>[ 25.092129] psci: CPU6 killed (polled 0 ms)
11553 01:19:24.346816 <6>[ 25.092758] psci: CPU7 killed (polled 0 ms)
11554 01:19:24.350490 <6>[ 25.093127] Enabling non-boot CPUs ...
11555 01:19:24.356841 <6>[ 25.093371] Detected VIPT I-cache on CPU1
11556 01:19:24.364026 <6>[ 25.093464] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11557 01:19:24.370137 <6>[ 25.093527] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11558 01:19:24.373613 <6>[ 25.094301] CPU1 is up
11559 01:19:24.377027 <6>[ 25.094465] Detected VIPT I-cache on CPU2
11560 01:19:24.383327 <6>[ 25.094529] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11561 01:19:24.390003 <6>[ 25.094570] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11562 01:19:24.393641 <6>[ 25.095127] CPU2 is up
11563 01:19:24.396716 <6>[ 25.095284] Detected VIPT I-cache on CPU3
11564 01:19:24.403496 <6>[ 25.095349] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11565 01:19:24.413218 <6>[ 25.095389] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11566 01:19:24.413310 <6>[ 25.095964] CPU3 is up
11567 01:19:24.419888 <6>[ 25.096091] Detected PIPT I-cache on CPU4
11568 01:19:24.426559 <6>[ 25.096111] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11569 01:19:24.433265 <6>[ 25.096124] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11570 01:19:24.436200 <6>[ 25.096368] CPU4 is up
11571 01:19:24.439803 <6>[ 25.096495] Detected PIPT I-cache on CPU5
11572 01:19:24.446212 <6>[ 25.096516] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11573 01:19:24.453031 <6>[ 25.096529] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11574 01:19:24.456259 <6>[ 25.096748] CPU5 is up
11575 01:19:24.459870 <6>[ 25.096873] Detected PIPT I-cache on CPU6
11576 01:19:24.469179 <6>[ 25.096893] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11577 01:19:24.475930 <6>[ 25.096906] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11578 01:19:24.476013 <6>[ 25.097132] CPU6 is up
11579 01:19:24.482509 <6>[ 25.097275] Detected PIPT I-cache on CPU7
11580 01:19:24.489479 <6>[ 25.097295] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11581 01:19:24.495714 <6>[ 25.097308] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11582 01:19:24.498966 <6>[ 25.097549] CPU7 is up
11583 01:19:24.502423 <6>[ 25.626660] OOM killer enabled.
11584 01:19:24.505897 <6>[ 25.630050] Restarting tasks ... done.
11585 01:19:24.512326 <5>[ 25.634405] random: crng reseeded on system resumption
11586 01:19:24.515847 <6>[ 25.640705] PM: suspend exit
11587 01:19:24.526174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=pass>
11588 01:19:24.526463 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=pass
11590 01:19:24.528972 rtcwake: assuming RTC uses UTC ...
11591 01:19:24.535779 rtcwake: wakeup from "mem" using rtc0 at Tue Apr 23 01:19:30 2024
11592 01:19:24.550686 <6>[ 25.674339] PM: suspend entry (deep)
11593 01:19:24.554309 <6>[ 25.678258] Filesystems sync: 0.000 seconds
11594 01:19:24.560598 <6>[ 25.683411] Freezing user space processes
11595 01:19:24.567486 <6>[ 25.689405] Freezing user space processes completed (elapsed 0.001 seconds)
11596 01:19:24.571065 <6>[ 25.696700] OOM killer disabled.
11597 01:19:24.577488 <6>[ 25.700195] Freezing remaining freezable tasks
11598 01:19:24.584161 <6>[ 25.706113] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11599 01:19:24.593981 <6>[ 25.713788] printk: Suspending console(s) (use no_console_suspend to debug)
11600 01:19:30.326621 <6>[ 25.790601] Disabling non-boot CPUs ...
11601 01:19:30.330125 <6>[ 25.791242] psci: CPU1 killed (polled 0 ms)
11602 01:19:30.333442 <6>[ 25.791973] psci: CPU2 killed (polled 0 ms)
11603 01:19:30.339773 <6>[ 25.793542] psci: CPU3 killed (polled 0 ms)
11604 01:19:30.343340 <6>[ 25.794244] psci: CPU4 killed (polled 4 ms)
11605 01:19:30.347006 <6>[ 25.795898] psci: CPU5 killed (polled 0 ms)
11606 01:19:30.387373 <6>[ 25.797457] psci: CPU6 killed (polled 0 ms)
11607 01:19:30.387543 <6>[ 25.797991] psci: CPU7 killed (polled 0 ms)
11608 01:19:30.387725 <6>[ 25.798286] Enabling non-boot CPUs ...
11609 01:19:30.387822 <6>[ 25.798463] Detected VIPT I-cache on CPU1
11610 01:19:30.387958 <6>[ 25.798524] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11611 01:19:30.388025 <6>[ 25.798565] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11612 01:19:30.388093 <6>[ 25.798981] CPU1 is up
11613 01:19:30.388151 <6>[ 25.799070] Detected VIPT I-cache on CPU2
11614 01:19:30.392958 <6>[ 25.799101] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11615 01:19:30.399361 <6>[ 25.799122] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11616 01:19:30.403013 <6>[ 25.799395] CPU2 is up
11617 01:19:30.406181 <6>[ 25.799481] Detected VIPT I-cache on CPU3
11618 01:19:30.412661 <6>[ 25.799512] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11619 01:19:30.422397 <6>[ 25.799534] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11620 01:19:30.422483 <6>[ 25.799816] CPU3 is up
11621 01:19:30.429024 <6>[ 25.799932] Detected PIPT I-cache on CPU4
11622 01:19:30.435830 <6>[ 25.799967] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11623 01:19:30.442620 <6>[ 25.799990] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11624 01:19:30.445495 <6>[ 25.800318] CPU4 is up
11625 01:19:30.449037 <6>[ 25.800434] Detected PIPT I-cache on CPU5
11626 01:19:30.455774 <6>[ 25.800470] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11627 01:19:30.462777 <6>[ 25.800492] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11628 01:19:30.465432 <6>[ 25.800812] CPU5 is up
11629 01:19:30.468884 <6>[ 25.800927] Detected PIPT I-cache on CPU6
11630 01:19:30.479002 <6>[ 25.800964] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11631 01:19:30.485125 <6>[ 25.800986] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11632 01:19:30.485209 <6>[ 25.801327] CPU6 is up
11633 01:19:30.491683 <6>[ 25.801442] Detected PIPT I-cache on CPU7
11634 01:19:30.498549 <6>[ 25.801479] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11635 01:19:30.505107 <6>[ 25.801501] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11636 01:19:30.508299 <6>[ 25.801859] CPU7 is up
11637 01:19:30.511844 <6>[ 26.342088] OOM killer enabled.
11638 01:19:30.514837 <6>[ 26.345481] Restarting tasks ... done.
11639 01:19:30.521466 <5>[ 26.349856] random: crng reseeded on system resumption
11640 01:19:30.525025 <6>[ 26.356260] PM: suspend exit
11641 01:19:30.534071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=pass>
11642 01:19:30.534335 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=pass
11644 01:19:30.537316 rtcwake: assuming RTC uses UTC ...
11645 01:19:30.544171 rtcwake: wakeup from "mem" using rtc0 at Tue Apr 23 01:19:36 2024
11646 01:19:30.556598 <6>[ 26.386099] PM: suspend entry (deep)
11647 01:19:30.559801 <6>[ 26.389974] Filesystems sync: 0.000 seconds
11648 01:19:30.563299 <6>[ 26.394747] Freezing user space processes
11649 01:19:30.574103 <6>[ 26.400397] Freezing user space processes completed (elapsed 0.001 seconds)
11650 01:19:30.577777 <6>[ 26.407629] OOM killer disabled.
11651 01:19:30.580760 <6>[ 26.411109] Freezing remaining freezable tasks
11652 01:19:30.590694 <6>[ 26.417015] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11653 01:19:30.597453 <6>[ 26.424683] printk: Suspending console(s) (use no_console_suspend to debug)
11654 01:19:36.326338 <6>[ 26.505531] Disabling non-boot CPUs ...
11655 01:19:36.329917 <6>[ 26.506206] psci: CPU1 killed (polled 0 ms)
11656 01:19:36.333064 <6>[ 26.506981] psci: CPU2 killed (polled 0 ms)
11657 01:19:36.340138 <6>[ 26.508532] psci: CPU3 killed (polled 0 ms)
11658 01:19:36.343670 <6>[ 26.508915] psci: CPU4 killed (polled 0 ms)
11659 01:19:36.346952 <6>[ 26.510204] psci: CPU5 killed (polled 4 ms)
11660 01:19:36.353114 <6>[ 26.511674] psci: CPU6 killed (polled 0 ms)
11661 01:19:36.356098 <6>[ 26.513123] psci: CPU7 killed (polled 0 ms)
11662 01:19:36.359684 <6>[ 26.513405] Enabling non-boot CPUs ...
11663 01:19:36.366779 <6>[ 26.513584] Detected VIPT I-cache on CPU1
11664 01:19:36.373130 <6>[ 26.513647] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11665 01:19:36.379844 <6>[ 26.513689] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11666 01:19:36.382699 <6>[ 26.514122] CPU1 is up
11667 01:19:36.386125 <6>[ 26.514271] Detected VIPT I-cache on CPU2
11668 01:19:36.393118 <6>[ 26.514303] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11669 01:19:36.399370 <6>[ 26.514326] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11670 01:19:36.402566 <6>[ 26.514611] CPU2 is up
11671 01:19:36.406183 <6>[ 26.514705] Detected VIPT I-cache on CPU3
11672 01:19:36.415662 <6>[ 26.514738] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11673 01:19:36.422343 <6>[ 26.514761] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11674 01:19:36.422423 <6>[ 26.515059] CPU3 is up
11675 01:19:36.428811 <6>[ 26.515156] Detected PIPT I-cache on CPU4
11676 01:19:36.436170 <6>[ 26.515177] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11677 01:19:36.442322 <6>[ 26.515192] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11678 01:19:36.445756 <6>[ 26.515424] CPU4 is up
11679 01:19:36.448708 <6>[ 26.515521] Detected PIPT I-cache on CPU5
11680 01:19:36.455634 <6>[ 26.515543] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11681 01:19:36.462321 <6>[ 26.515558] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11682 01:19:36.465376 <6>[ 26.515787] CPU5 is up
11683 01:19:36.468620 <6>[ 26.515893] Detected PIPT I-cache on CPU6
11684 01:19:36.478511 <6>[ 26.515915] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11685 01:19:36.485165 <6>[ 26.515929] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11686 01:19:36.485247 <6>[ 26.516153] CPU6 is up
11687 01:19:36.492132 <6>[ 26.516250] Detected PIPT I-cache on CPU7
11688 01:19:36.498350 <6>[ 26.516272] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11689 01:19:36.504688 <6>[ 26.516286] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11690 01:19:36.508113 <6>[ 26.516531] CPU7 is up
11691 01:19:36.511390 <6>[ 27.057993] OOM killer enabled.
11692 01:19:36.514714 <6>[ 27.061384] Restarting tasks ... done.
11693 01:19:36.521501 <5>[ 27.065741] random: crng reseeded on system resumption
11694 01:19:36.524529 <6>[ 27.072264] PM: suspend exit
11695 01:19:36.533732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=pass>
11696 01:19:36.534022 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=pass
11698 01:19:36.537779 rtcwake: assuming RTC uses UTC ...
11699 01:19:36.543411 rtcwake: wakeup from "mem" using rtc0 at Tue Apr 23 01:19:42 2024
11700 01:19:36.556260 <6>[ 27.102090] PM: suspend entry (deep)
11701 01:19:36.559815 <6>[ 27.105965] Filesystems sync: 0.000 seconds
11702 01:19:36.562970 <6>[ 27.110750] Freezing user space processes
11703 01:19:36.574196 <6>[ 27.116394] Freezing user space processes completed (elapsed 0.001 seconds)
11704 01:19:36.577278 <6>[ 27.123641] OOM killer disabled.
11705 01:19:36.580555 <6>[ 27.127121] Freezing remaining freezable tasks
11706 01:19:36.591051 <6>[ 27.133034] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11707 01:19:36.597282 <6>[ 27.140700] printk: Suspending console(s) (use no_console_suspend to debug)
11708 01:19:42.324454 <6>[ 27.212986] Disabling non-boot CPUs ...
11709 01:19:42.327788 <6>[ 27.213779] psci: CPU1 killed (polled 0 ms)
11710 01:19:42.330862 <6>[ 27.214575] psci: CPU2 killed (polled 0 ms)
11711 01:19:42.337597 <6>[ 27.216271] psci: CPU3 killed (polled 0 ms)
11712 01:19:42.341216 <6>[ 27.216759] psci: CPU4 killed (polled 0 ms)
11713 01:19:42.344703 <6>[ 27.217284] psci: CPU5 killed (polled 0 ms)
11714 01:19:42.350932 <6>[ 27.217889] psci: CPU6 killed (polled 0 ms)
11715 01:19:42.354472 <6>[ 27.218393] psci: CPU7 killed (polled 0 ms)
11716 01:19:42.357445 <6>[ 27.218770] Enabling non-boot CPUs ...
11717 01:19:42.364358 <6>[ 27.218974] Detected VIPT I-cache on CPU1
11718 01:19:42.370801 <6>[ 27.219044] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11719 01:19:42.377716 <6>[ 27.219094] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11720 01:19:42.380975 <6>[ 27.219601] CPU1 is up
11721 01:19:42.384159 <6>[ 27.219711] Detected VIPT I-cache on CPU2
11722 01:19:42.390771 <6>[ 27.219753] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11723 01:19:42.397435 <6>[ 27.219782] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11724 01:19:42.400962 <6>[ 27.220149] CPU2 is up
11725 01:19:42.403781 <6>[ 27.220256] Detected VIPT I-cache on CPU3
11726 01:19:42.410357 <6>[ 27.220298] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11727 01:19:42.420516 <6>[ 27.220327] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11728 01:19:42.420602 <6>[ 27.220707] CPU3 is up
11729 01:19:42.426960 <6>[ 27.220816] Detected PIPT I-cache on CPU4
11730 01:19:42.433665 <6>[ 27.220838] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11731 01:19:42.440693 <6>[ 27.220852] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11732 01:19:42.443686 <6>[ 27.221094] CPU4 is up
11733 01:19:42.447177 <6>[ 27.221200] Detected PIPT I-cache on CPU5
11734 01:19:42.453882 <6>[ 27.221221] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11735 01:19:42.460687 <6>[ 27.221235] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11736 01:19:42.463856 <6>[ 27.221456] CPU5 is up
11737 01:19:42.466801 <6>[ 27.221562] Detected PIPT I-cache on CPU6
11738 01:19:42.473299 <6>[ 27.221583] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11739 01:19:42.483442 <6>[ 27.221598] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11740 01:19:42.483528 <6>[ 27.221840] CPU6 is up
11741 01:19:42.489830 <6>[ 27.221951] Detected PIPT I-cache on CPU7
11742 01:19:42.497078 <6>[ 27.221973] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11743 01:19:42.503425 <6>[ 27.221986] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11744 01:19:42.506692 <6>[ 27.222260] CPU7 is up
11745 01:19:42.510130 <6>[ 27.762200] OOM killer enabled.
11746 01:19:42.513428 <6>[ 27.765589] Restarting tasks ... done.
11747 01:19:42.519740 <5>[ 27.769971] random: crng reseeded on system resumption
11748 01:19:42.522864 <6>[ 27.776289] PM: suspend exit
11749 01:19:42.531827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=pass>
11750 01:19:42.532097 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=pass
11752 01:19:42.534701 rtcwake: assuming RTC uses UTC ...
11753 01:19:42.541594 rtcwake: wakeup from "mem" using rtc0 at Tue Apr 23 01:19:48 2024
11754 01:19:42.554558 <6>[ 27.806131] PM: suspend entry (deep)
11755 01:19:42.557696 <6>[ 27.809985] Filesystems sync: 0.000 seconds
11756 01:19:42.560977 <6>[ 27.814748] Freezing user space processes
11757 01:19:42.572024 <6>[ 27.820407] Freezing user space processes completed (elapsed 0.001 seconds)
11758 01:19:42.575499 <6>[ 27.827636] OOM killer disabled.
11759 01:19:42.578408 <6>[ 27.831120] Freezing remaining freezable tasks
11760 01:19:42.589100 <6>[ 27.837032] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11761 01:19:42.595161 <6>[ 27.844698] printk: Suspending console(s) (use no_console_suspend to debug)
11762 01:19:48.326351 <6>[ 27.918924] Disabling non-boot CPUs ...
11763 01:19:48.329830 <6>[ 27.921030] psci: CPU1 killed (polled 0 ms)
11764 01:19:48.333280 <6>[ 27.923337] psci: CPU2 killed (polled 0 ms)
11765 01:19:48.339630 <6>[ 27.925338] psci: CPU3 killed (polled 0 ms)
11766 01:19:48.343166 <6>[ 27.925864] psci: CPU4 killed (polled 0 ms)
11767 01:19:48.346139 <6>[ 27.926525] psci: CPU5 killed (polled 0 ms)
11768 01:19:48.353101 <6>[ 27.927141] psci: CPU6 killed (polled 0 ms)
11769 01:19:48.356124 <6>[ 27.927824] psci: CPU7 killed (polled 0 ms)
11770 01:19:48.359292 <6>[ 27.928258] Enabling non-boot CPUs ...
11771 01:19:48.366300 <6>[ 27.928502] Detected VIPT I-cache on CPU1
11772 01:19:48.372958 <6>[ 27.928595] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11773 01:19:48.379228 <6>[ 27.928658] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11774 01:19:48.382854 <6>[ 27.929353] CPU1 is up
11775 01:19:48.385891 <6>[ 27.929504] Detected VIPT I-cache on CPU2
11776 01:19:48.392605 <6>[ 27.929568] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11777 01:19:48.399060 <6>[ 27.929610] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11778 01:19:48.402606 <6>[ 27.930207] CPU2 is up
11779 01:19:48.406214 <6>[ 27.930358] Detected VIPT I-cache on CPU3
11780 01:19:48.412724 <6>[ 27.930423] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11781 01:19:48.422416 <6>[ 27.930465] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11782 01:19:48.422511 <6>[ 27.931046] CPU3 is up
11783 01:19:48.429007 <6>[ 27.931175] Detected PIPT I-cache on CPU4
11784 01:19:48.435752 <6>[ 27.931196] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11785 01:19:48.442505 <6>[ 27.931211] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11786 01:19:48.445558 <6>[ 27.931471] CPU4 is up
11787 01:19:48.449160 <6>[ 27.931611] Detected PIPT I-cache on CPU5
11788 01:19:48.456144 <6>[ 27.931633] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11789 01:19:48.462279 <6>[ 27.931647] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11790 01:19:48.465697 <6>[ 27.931888] CPU5 is up
11791 01:19:48.468624 <6>[ 27.932019] Detected PIPT I-cache on CPU6
11792 01:19:48.478526 <6>[ 27.932041] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11793 01:19:48.484992 <6>[ 27.932056] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11794 01:19:48.485079 <6>[ 27.932297] CPU6 is up
11795 01:19:48.492105 <6>[ 27.932425] Detected PIPT I-cache on CPU7
11796 01:19:48.498637 <6>[ 27.932448] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11797 01:19:48.504998 <6>[ 27.932462] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11798 01:19:48.507807 <6>[ 27.932720] CPU7 is up
11799 01:19:48.511455 <6>[ 28.474417] OOM killer enabled.
11800 01:19:48.515028 <6>[ 28.477806] Restarting tasks ... done.
11801 01:19:48.521284 <5>[ 28.482170] random: crng reseeded on system resumption
11802 01:19:48.524829 <6>[ 28.488503] PM: suspend exit
11803 01:19:48.533537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=pass>
11804 01:19:48.533805 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=pass
11806 01:19:48.537062 rtcwake: assuming RTC uses UTC ...
11807 01:19:48.543434 rtcwake: wakeup from "mem" using rtc0 at Tue Apr 23 01:19:54 2024
11808 01:19:48.555940 <6>[ 28.518266] PM: suspend entry (deep)
11809 01:19:48.559315 <6>[ 28.522136] Filesystems sync: 0.000 seconds
11810 01:19:48.562866 <6>[ 28.526906] Freezing user space processes
11811 01:19:48.573698 <6>[ 28.532638] Freezing user space processes completed (elapsed 0.001 seconds)
11812 01:19:48.577110 <6>[ 28.539869] OOM killer disabled.
11813 01:19:48.580441 <6>[ 28.543352] Freezing remaining freezable tasks
11814 01:19:48.590821 <6>[ 28.549271] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11815 01:19:48.597119 <6>[ 28.556942] printk: Suspending console(s) (use no_console_suspend to debug)
11816 01:19:54.328229 <6>[ 28.638608] Disabling non-boot CPUs ...
11817 01:19:54.331013 <4>[ 28.639658] migrate_one_irq: 88 callbacks suppressed
11818 01:19:54.337932 <4>[ 28.639672] IRQ282: set affinity failed(-22).
11819 01:19:54.340969 <4>[ 28.639684] IRQ284: set affinity failed(-22).
11820 01:19:54.344736 <6>[ 28.639765] psci: CPU1 killed (polled 0 ms)
11821 01:19:54.351256 <4>[ 28.640941] IRQ282: set affinity failed(-22).
11822 01:19:54.354368 <4>[ 28.640954] IRQ284: set affinity failed(-22).
11823 01:19:54.360958 <6>[ 28.641020] psci: CPU2 killed (polled 0 ms)
11824 01:19:54.364443 <4>[ 28.641970] IRQ282: set affinity failed(-22).
11825 01:19:54.367565 <4>[ 28.641983] IRQ284: set affinity failed(-22).
11826 01:19:54.373928 <6>[ 28.643057] psci: CPU3 killed (polled 4 ms)
11827 01:19:54.377441 <4>[ 28.643709] IRQ282: set affinity failed(-22).
11828 01:19:54.384039 <4>[ 28.643713] IRQ284: set affinity failed(-22).
11829 01:19:54.387095 <6>[ 28.643748] psci: CPU4 killed (polled 0 ms)
11830 01:19:54.390745 <4>[ 28.644400] IRQ282: set affinity failed(-22).
11831 01:19:54.397473 <4>[ 28.644406] IRQ284: set affinity failed(-22).
11832 01:19:54.400821 <6>[ 28.644444] psci: CPU5 killed (polled 0 ms)
11833 01:19:54.404061 <6>[ 28.645070] psci: CPU6 killed (polled 0 ms)
11834 01:19:54.410488 <6>[ 28.645673] psci: CPU7 killed (polled 0 ms)
11835 01:19:54.413918 <6>[ 28.646141] Enabling non-boot CPUs ...
11836 01:19:54.417218 <6>[ 28.646387] Detected VIPT I-cache on CPU1
11837 01:19:54.423849 <6>[ 28.646481] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11838 01:19:54.430234 <6>[ 28.646543] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11839 01:19:54.433658 <6>[ 28.647251] CPU1 is up
11840 01:19:54.440158 <6>[ 28.647403] Detected VIPT I-cache on CPU2
11841 01:19:54.446644 <6>[ 28.647467] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11842 01:19:54.453636 <6>[ 28.647510] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11843 01:19:54.456642 <6>[ 28.648075] CPU2 is up
11844 01:19:54.460353 <6>[ 28.648227] Detected VIPT I-cache on CPU3
11845 01:19:54.466775 <6>[ 28.648292] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11846 01:19:54.473500 <6>[ 28.648334] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11847 01:19:54.477154 <6>[ 28.648910] CPU3 is up
11848 01:19:54.480162 <6>[ 28.649041] Detected PIPT I-cache on CPU4
11849 01:19:54.486817 <6>[ 28.649064] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11850 01:19:54.493098 <6>[ 28.649079] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11851 01:19:54.496705 <6>[ 28.649354] CPU4 is up
11852 01:19:54.499689 <6>[ 28.649484] Detected PIPT I-cache on CPU5
11853 01:19:54.509753 <6>[ 28.649507] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11854 01:19:54.516270 <6>[ 28.649522] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11855 01:19:54.516436 <6>[ 28.649761] CPU5 is up
11856 01:19:54.523051 <6>[ 28.649894] Detected PIPT I-cache on CPU6
11857 01:19:54.529485 <6>[ 28.649917] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11858 01:19:54.536607 <6>[ 28.649932] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11859 01:19:54.540186 <6>[ 28.650196] CPU6 is up
11860 01:19:54.542971 <6>[ 28.650335] Detected PIPT I-cache on CPU7
11861 01:19:54.549779 <6>[ 28.650358] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11862 01:19:54.556032 <6>[ 28.650373] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11863 01:19:54.559657 <6>[ 28.650647] CPU7 is up
11864 01:19:54.562591 <6>[ 29.245698] OOM killer enabled.
11865 01:19:54.568990 <6>[ 29.249090] Restarting tasks ... done.
11866 01:19:54.572786 <5>[ 29.253438] random: crng reseeded on system resumption
11867 01:19:54.576782 <6>[ 29.260774] PM: suspend exit
11868 01:19:54.586832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=pass>
11869 01:19:54.587596 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=pass
11871 01:19:54.589951 rtcwake: assuming RTC uses UTC ...
11872 01:19:54.596603 rtcwake: wakeup from "mem" using rtc0 at Tue Apr 23 01:20:00 2024
11873 01:19:54.608680 <6>[ 29.289291] PM: suspend entry (deep)
11874 01:19:54.612344 <6>[ 29.293155] Filesystems sync: 0.000 seconds
11875 01:19:54.615239 <6>[ 29.297885] Freezing user space processes
11876 01:19:54.626806 <6>[ 29.303640] Freezing user space processes completed (elapsed 0.001 seconds)
11877 01:19:54.630022 <6>[ 29.310866] OOM killer disabled.
11878 01:19:54.633271 <6>[ 29.314349] Freezing remaining freezable tasks
11879 01:19:54.642983 <6>[ 29.320255] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11880 01:19:54.649380 <6>[ 29.327923] printk: Suspending console(s) (use no_console_suspend to debug)
11881 01:20:00.326168 <6>[ 29.402242] Disabling non-boot CPUs ...
11882 01:20:00.329770 <6>[ 29.404102] psci: CPU1 killed (polled 0 ms)
11883 01:20:00.332824 <6>[ 29.406044] psci: CPU2 killed (polled 4 ms)
11884 01:20:00.339723 <6>[ 29.407798] psci: CPU3 killed (polled 0 ms)
11885 01:20:00.342805 <6>[ 29.408320] psci: CPU4 killed (polled 0 ms)
11886 01:20:00.346073 <6>[ 29.408873] psci: CPU5 killed (polled 0 ms)
11887 01:20:00.353057 <6>[ 29.409395] psci: CPU6 killed (polled 0 ms)
11888 01:20:00.356171 <6>[ 29.409893] psci: CPU7 killed (polled 0 ms)
11889 01:20:00.359184 <6>[ 29.410324] Enabling non-boot CPUs ...
11890 01:20:00.365837 <6>[ 29.410532] Detected VIPT I-cache on CPU1
11891 01:20:00.372737 <6>[ 29.410607] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11892 01:20:00.379384 <6>[ 29.410660] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11893 01:20:00.382685 <6>[ 29.411190] CPU1 is up
11894 01:20:00.385770 <6>[ 29.411307] Detected VIPT I-cache on CPU2
11895 01:20:00.392419 <6>[ 29.411353] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11896 01:20:00.398717 <6>[ 29.411384] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11897 01:20:00.402598 <6>[ 29.411787] CPU2 is up
11898 01:20:00.405539 <6>[ 29.411902] Detected VIPT I-cache on CPU3
11899 01:20:00.415372 <6>[ 29.411948] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11900 01:20:00.421953 <6>[ 29.411979] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11901 01:20:00.422052 <6>[ 29.412389] CPU3 is up
11902 01:20:00.428918 <6>[ 29.412502] Detected PIPT I-cache on CPU4
11903 01:20:00.435537 <6>[ 29.412524] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11904 01:20:00.442133 <6>[ 29.412538] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11905 01:20:00.445676 <6>[ 29.412805] CPU4 is up
11906 01:20:00.448559 <6>[ 29.412925] Detected PIPT I-cache on CPU5
11907 01:20:00.455173 <6>[ 29.412947] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11908 01:20:00.461755 <6>[ 29.412961] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11909 01:20:00.465579 <6>[ 29.413181] CPU5 is up
11910 01:20:00.468775 <6>[ 29.413292] Detected PIPT I-cache on CPU6
11911 01:20:00.475214 <6>[ 29.413314] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11912 01:20:00.485060 <6>[ 29.413328] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11913 01:20:00.485172 <6>[ 29.413558] CPU6 is up
11914 01:20:00.492009 <6>[ 29.413667] Detected PIPT I-cache on CPU7
11915 01:20:00.498297 <6>[ 29.413688] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11916 01:20:00.505239 <6>[ 29.413702] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11917 01:20:00.508410 <6>[ 29.413938] CPU7 is up
11918 01:20:00.511756 <6>[ 29.958129] OOM killer enabled.
11919 01:20:00.514651 <6>[ 29.961519] Restarting tasks ... done.
11920 01:20:00.521478 <5>[ 29.965865] random: crng reseeded on system resumption
11921 01:20:00.524672 <6>[ 29.972227] PM: suspend exit
11922 01:20:00.533448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=pass>
11923 01:20:00.533712 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=pass
11925 01:20:00.536444 rtcwake: assuming RTC uses UTC ...
11926 01:20:00.543024 rtcwake: wakeup from "mem" using rtc0 at Tue Apr 23 01:20:06 2024
11927 01:20:00.555291 <6>[ 30.001579] PM: suspend entry (deep)
11928 01:20:00.558925 <6>[ 30.005459] Filesystems sync: 0.000 seconds
11929 01:20:00.562127 <6>[ 30.010200] Freezing user space processes
11930 01:20:00.573213 <6>[ 30.015832] Freezing user space processes completed (elapsed 0.001 seconds)
11931 01:20:00.576763 <6>[ 30.023064] OOM killer disabled.
11932 01:20:00.579751 <6>[ 30.026549] Freezing remaining freezable tasks
11933 01:20:00.589761 <6>[ 30.032463] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11934 01:20:00.596649 <6>[ 30.040134] printk: Suspending console(s) (use no_console_suspend to debug)
11935 01:20:06.323125 <6>[ 30.126259] Disabling non-boot CPUs ...
11936 01:20:06.326476 <6>[ 30.127107] psci: CPU1 killed (polled 0 ms)
11937 01:20:06.329462 <6>[ 30.129012] psci: CPU2 killed (polled 0 ms)
11938 01:20:06.336339 <6>[ 30.129989] psci: CPU3 killed (polled 4 ms)
11939 01:20:06.339682 <6>[ 30.130590] psci: CPU4 killed (polled 0 ms)
11940 01:20:06.342991 <6>[ 30.131141] psci: CPU5 killed (polled 0 ms)
11941 01:20:06.350007 <6>[ 30.131625] psci: CPU6 killed (polled 0 ms)
11942 01:20:06.352876 <6>[ 30.132131] psci: CPU7 killed (polled 0 ms)
11943 01:20:06.356387 <6>[ 30.132444] Enabling non-boot CPUs ...
11944 01:20:06.362879 <6>[ 30.132651] Detected VIPT I-cache on CPU1
11945 01:20:06.369223 <6>[ 30.132727] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11946 01:20:06.376516 <6>[ 30.132780] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11947 01:20:06.379408 <6>[ 30.133318] CPU1 is up
11948 01:20:06.382516 <6>[ 30.133436] Detected VIPT I-cache on CPU2
11949 01:20:06.389479 <6>[ 30.133482] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11950 01:20:06.395874 <6>[ 30.133513] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11951 01:20:06.399140 <6>[ 30.134003] CPU2 is up
11952 01:20:06.402396 <6>[ 30.134120] Detected VIPT I-cache on CPU3
11953 01:20:06.412513 <6>[ 30.134166] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11954 01:20:06.418893 <6>[ 30.134196] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11955 01:20:06.418976 <6>[ 30.134609] CPU3 is up
11956 01:20:06.425403 <6>[ 30.134722] Detected PIPT I-cache on CPU4
11957 01:20:06.432363 <6>[ 30.134744] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11958 01:20:06.438811 <6>[ 30.134758] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11959 01:20:06.442243 <6>[ 30.135022] CPU4 is up
11960 01:20:06.445429 <6>[ 30.135144] Detected PIPT I-cache on CPU5
11961 01:20:06.451869 <6>[ 30.135166] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11962 01:20:06.458491 <6>[ 30.135180] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11963 01:20:06.461998 <6>[ 30.135400] CPU5 is up
11964 01:20:06.465639 <6>[ 30.135510] Detected PIPT I-cache on CPU6
11965 01:20:06.475399 <6>[ 30.135531] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11966 01:20:06.481566 <6>[ 30.135546] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11967 01:20:06.481649 <6>[ 30.135774] CPU6 is up
11968 01:20:06.488390 <6>[ 30.135885] Detected PIPT I-cache on CPU7
11969 01:20:06.495127 <6>[ 30.135907] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11970 01:20:06.501546 <6>[ 30.135921] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11971 01:20:06.504887 <6>[ 30.136161] CPU7 is up
11972 01:20:06.508400 <6>[ 30.677978] OOM killer enabled.
11973 01:20:06.511363 <6>[ 30.681368] Restarting tasks ... done.
11974 01:20:06.517769 <5>[ 30.685717] random: crng reseeded on system resumption
11975 01:20:06.521285 <6>[ 30.692112] PM: suspend exit
11976 01:20:06.530524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=pass>
11977 01:20:06.530607 + set +x
11978 01:20:06.530855 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=pass
11980 01:20:06.537215 <LAVA_SIGNAL_ENDRUN 0_sleep 13468740_1.5.2.3.1>
11981 01:20:06.537334 <LAVA_TEST_RUNNER EXIT>
11982 01:20:06.537589 Received signal: <ENDRUN> 0_sleep 13468740_1.5.2.3.1
11983 01:20:06.537675 Ending use of test pattern.
11984 01:20:06.537738 Ending test lava.0_sleep (13468740_1.5.2.3.1), duration 60.33
11986 01:20:06.537973 ok: lava_test_shell seems to have completed
11987 01:20:06.538116 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-mem-1: pass
rtcwake-mem-10: pass
rtcwake-mem-2: pass
rtcwake-mem-3: pass
rtcwake-mem-4: pass
rtcwake-mem-5: pass
rtcwake-mem-6: pass
rtcwake-mem-7: pass
rtcwake-mem-8: pass
rtcwake-mem-9: pass
11988 01:20:06.538210 end: 3.1 lava-test-shell (duration 00:01:01) [common]
11989 01:20:06.538300 end: 3 lava-test-retry (duration 00:01:01) [common]
11990 01:20:06.538385 start: 4 finalize (timeout 00:04:54) [common]
11991 01:20:06.538503 start: 4.1 power-off (timeout 00:00:30) [common]
11992 01:20:06.538656 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11993 01:20:06.615089 >> Command sent successfully.
11994 01:20:06.617556 Returned 0 in 0 seconds
11995 01:20:06.717914 end: 4.1 power-off (duration 00:00:00) [common]
11997 01:20:06.718234 start: 4.2 read-feedback (timeout 00:04:53) [common]
11998 01:20:06.718506 Listened to connection for namespace 'common' for up to 1s
11999 01:20:07.719426 Finalising connection for namespace 'common'
12000 01:20:07.719592 Disconnecting from shell: Finalise
12001 01:20:07.719696 / #
12002 01:20:07.820010 end: 4.2 read-feedback (duration 00:00:01) [common]
12003 01:20:07.820157 end: 4 finalize (duration 00:00:01) [common]
12004 01:20:07.820275 Cleaning after the job
12005 01:20:07.820374 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468740/tftp-deploy-rrunqafy/ramdisk
12006 01:20:07.832339 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468740/tftp-deploy-rrunqafy/kernel
12007 01:20:07.852773 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468740/tftp-deploy-rrunqafy/dtb
12008 01:20:07.853004 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468740/tftp-deploy-rrunqafy/modules
12009 01:20:07.858719 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13468740
12010 01:20:08.024194 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13468740
12011 01:20:08.024393 Job finished correctly