Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 25
- Errors: 1
- Kernel Errors: 34
- Boot result: PASS
1 01:22:46.280001 lava-dispatcher, installed at version: 2024.01
2 01:22:46.280202 start: 0 validate
3 01:22:46.280328 Start time: 2024-04-23 01:22:46.280320+00:00 (UTC)
4 01:22:46.280448 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:22:46.280575 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 01:22:46.542058 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:22:46.542930 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:22:46.812419 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:22:46.813132 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:22:47.070976 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:22:47.071757 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 01:22:47.333240 validate duration: 1.05
14 01:22:47.333516 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:22:47.333644 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:22:47.333759 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:22:47.333880 Not decompressing ramdisk as can be used compressed.
18 01:22:47.333963 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 01:22:47.334027 saving as /var/lib/lava/dispatcher/tmp/13468761/tftp-deploy-xzv199mm/ramdisk/rootfs.cpio.gz
20 01:22:47.334087 total size: 28105535 (26 MB)
21 01:22:47.335221 progress 0 % (0 MB)
22 01:22:47.342439 progress 5 % (1 MB)
23 01:22:47.349699 progress 10 % (2 MB)
24 01:22:47.356802 progress 15 % (4 MB)
25 01:22:47.363923 progress 20 % (5 MB)
26 01:22:47.371107 progress 25 % (6 MB)
27 01:22:47.378196 progress 30 % (8 MB)
28 01:22:47.385254 progress 35 % (9 MB)
29 01:22:47.392293 progress 40 % (10 MB)
30 01:22:47.399239 progress 45 % (12 MB)
31 01:22:47.406274 progress 50 % (13 MB)
32 01:22:47.413593 progress 55 % (14 MB)
33 01:22:47.420701 progress 60 % (16 MB)
34 01:22:47.427827 progress 65 % (17 MB)
35 01:22:47.435029 progress 70 % (18 MB)
36 01:22:47.442156 progress 75 % (20 MB)
37 01:22:47.449272 progress 80 % (21 MB)
38 01:22:47.456448 progress 85 % (22 MB)
39 01:22:47.463430 progress 90 % (24 MB)
40 01:22:47.470541 progress 95 % (25 MB)
41 01:22:47.477554 progress 100 % (26 MB)
42 01:22:47.477759 26 MB downloaded in 0.14 s (186.56 MB/s)
43 01:22:47.477920 end: 1.1.1 http-download (duration 00:00:00) [common]
45 01:22:47.478159 end: 1.1 download-retry (duration 00:00:00) [common]
46 01:22:47.478245 start: 1.2 download-retry (timeout 00:10:00) [common]
47 01:22:47.478373 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 01:22:47.478540 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 01:22:47.478614 saving as /var/lib/lava/dispatcher/tmp/13468761/tftp-deploy-xzv199mm/kernel/Image
50 01:22:47.478676 total size: 54352384 (51 MB)
51 01:22:47.478737 No compression specified
52 01:22:47.479825 progress 0 % (0 MB)
53 01:22:47.493963 progress 5 % (2 MB)
54 01:22:47.507613 progress 10 % (5 MB)
55 01:22:47.521282 progress 15 % (7 MB)
56 01:22:47.535154 progress 20 % (10 MB)
57 01:22:47.548785 progress 25 % (12 MB)
58 01:22:47.562528 progress 30 % (15 MB)
59 01:22:47.576261 progress 35 % (18 MB)
60 01:22:47.590006 progress 40 % (20 MB)
61 01:22:47.603763 progress 45 % (23 MB)
62 01:22:47.617401 progress 50 % (25 MB)
63 01:22:47.631155 progress 55 % (28 MB)
64 01:22:47.644826 progress 60 % (31 MB)
65 01:22:47.658572 progress 65 % (33 MB)
66 01:22:47.672326 progress 70 % (36 MB)
67 01:22:47.686066 progress 75 % (38 MB)
68 01:22:47.699537 progress 80 % (41 MB)
69 01:22:47.713205 progress 85 % (44 MB)
70 01:22:47.726994 progress 90 % (46 MB)
71 01:22:47.740543 progress 95 % (49 MB)
72 01:22:47.753946 progress 100 % (51 MB)
73 01:22:47.754162 51 MB downloaded in 0.28 s (188.16 MB/s)
74 01:22:47.754323 end: 1.2.1 http-download (duration 00:00:00) [common]
76 01:22:47.754561 end: 1.2 download-retry (duration 00:00:00) [common]
77 01:22:47.754647 start: 1.3 download-retry (timeout 00:10:00) [common]
78 01:22:47.754737 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 01:22:47.754876 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 01:22:47.754945 saving as /var/lib/lava/dispatcher/tmp/13468761/tftp-deploy-xzv199mm/dtb/mt8192-asurada-spherion-r0.dtb
81 01:22:47.755007 total size: 47230 (0 MB)
82 01:22:47.755068 No compression specified
83 01:22:47.756251 progress 69 % (0 MB)
84 01:22:47.756522 progress 100 % (0 MB)
85 01:22:47.756677 0 MB downloaded in 0.00 s (27.01 MB/s)
86 01:22:47.756798 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:22:47.757019 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:22:47.757102 start: 1.4 download-retry (timeout 00:10:00) [common]
90 01:22:47.757185 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 01:22:47.757295 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 01:22:47.757362 saving as /var/lib/lava/dispatcher/tmp/13468761/tftp-deploy-xzv199mm/modules/modules.tar
93 01:22:47.757422 total size: 8638160 (8 MB)
94 01:22:47.757482 Using unxz to decompress xz
95 01:22:47.761482 progress 0 % (0 MB)
96 01:22:47.780374 progress 5 % (0 MB)
97 01:22:47.804373 progress 10 % (0 MB)
98 01:22:47.827986 progress 15 % (1 MB)
99 01:22:47.850659 progress 20 % (1 MB)
100 01:22:47.874789 progress 25 % (2 MB)
101 01:22:47.899870 progress 30 % (2 MB)
102 01:22:47.923449 progress 35 % (2 MB)
103 01:22:47.947981 progress 40 % (3 MB)
104 01:22:47.971320 progress 45 % (3 MB)
105 01:22:47.995537 progress 50 % (4 MB)
106 01:22:48.019525 progress 55 % (4 MB)
107 01:22:48.046718 progress 60 % (4 MB)
108 01:22:48.071208 progress 65 % (5 MB)
109 01:22:48.095579 progress 70 % (5 MB)
110 01:22:48.119472 progress 75 % (6 MB)
111 01:22:48.144006 progress 80 % (6 MB)
112 01:22:48.171293 progress 85 % (7 MB)
113 01:22:48.196828 progress 90 % (7 MB)
114 01:22:48.225391 progress 95 % (7 MB)
115 01:22:48.251075 progress 100 % (8 MB)
116 01:22:48.256732 8 MB downloaded in 0.50 s (16.50 MB/s)
117 01:22:48.256971 end: 1.4.1 http-download (duration 00:00:00) [common]
119 01:22:48.257237 end: 1.4 download-retry (duration 00:00:01) [common]
120 01:22:48.257329 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 01:22:48.257425 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 01:22:48.257507 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:22:48.257595 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 01:22:48.257819 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb
125 01:22:48.257952 makedir: /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/bin
126 01:22:48.258056 makedir: /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/tests
127 01:22:48.258153 makedir: /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/results
128 01:22:48.258270 Creating /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/bin/lava-add-keys
129 01:22:48.258444 Creating /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/bin/lava-add-sources
130 01:22:48.258629 Creating /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/bin/lava-background-process-start
131 01:22:48.258765 Creating /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/bin/lava-background-process-stop
132 01:22:48.258894 Creating /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/bin/lava-common-functions
133 01:22:48.259018 Creating /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/bin/lava-echo-ipv4
134 01:22:48.259143 Creating /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/bin/lava-install-packages
135 01:22:48.259266 Creating /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/bin/lava-installed-packages
136 01:22:48.259390 Creating /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/bin/lava-os-build
137 01:22:48.259514 Creating /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/bin/lava-probe-channel
138 01:22:48.259637 Creating /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/bin/lava-probe-ip
139 01:22:48.259761 Creating /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/bin/lava-target-ip
140 01:22:48.259884 Creating /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/bin/lava-target-mac
141 01:22:48.260006 Creating /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/bin/lava-target-storage
142 01:22:48.260133 Creating /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/bin/lava-test-case
143 01:22:48.260257 Creating /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/bin/lava-test-event
144 01:22:48.260379 Creating /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/bin/lava-test-feedback
145 01:22:48.260501 Creating /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/bin/lava-test-raise
146 01:22:48.260625 Creating /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/bin/lava-test-reference
147 01:22:48.260752 Creating /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/bin/lava-test-runner
148 01:22:48.260876 Creating /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/bin/lava-test-set
149 01:22:48.261000 Creating /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/bin/lava-test-shell
150 01:22:48.261128 Updating /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/bin/lava-install-packages (oe)
151 01:22:48.261277 Updating /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/bin/lava-installed-packages (oe)
152 01:22:48.261396 Creating /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/environment
153 01:22:48.261496 LAVA metadata
154 01:22:48.261571 - LAVA_JOB_ID=13468761
155 01:22:48.261634 - LAVA_DISPATCHER_IP=192.168.201.1
156 01:22:48.261754 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 01:22:48.261823 skipped lava-vland-overlay
158 01:22:48.261897 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 01:22:48.261980 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 01:22:48.262041 skipped lava-multinode-overlay
161 01:22:48.262116 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 01:22:48.262218 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 01:22:48.262294 Loading test definitions
164 01:22:48.262426 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 01:22:48.262501 Using /lava-13468761 at stage 0
166 01:22:48.262800 uuid=13468761_1.5.2.3.1 testdef=None
167 01:22:48.262890 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 01:22:48.262974 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 01:22:48.263501 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 01:22:48.263720 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 01:22:48.264331 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 01:22:48.264562 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 01:22:48.265219 runner path: /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 13468761_1.5.2.3.1
176 01:22:48.265379 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 01:22:48.265584 Creating lava-test-runner.conf files
179 01:22:48.265647 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13468761/lava-overlay-pvh_5rkb/lava-13468761/0 for stage 0
180 01:22:48.265735 - 0_v4l2-compliance-mtk-vcodec-enc
181 01:22:48.265831 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 01:22:48.265916 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 01:22:48.273130 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 01:22:48.273243 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 01:22:48.273329 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 01:22:48.273415 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 01:22:48.273501 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 01:22:49.139315 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 01:22:49.139696 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 01:22:49.139809 extracting modules file /var/lib/lava/dispatcher/tmp/13468761/tftp-deploy-xzv199mm/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13468761/extract-overlay-ramdisk-mxe54vv_/ramdisk
191 01:22:49.358002 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 01:22:49.358175 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 01:22:49.358266 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13468761/compress-overlay-3m5eoif5/overlay-1.5.2.4.tar.gz to ramdisk
194 01:22:49.358395 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13468761/compress-overlay-3m5eoif5/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13468761/extract-overlay-ramdisk-mxe54vv_/ramdisk
195 01:22:49.365039 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 01:22:49.365148 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 01:22:49.365237 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 01:22:49.365327 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 01:22:49.365400 Building ramdisk /var/lib/lava/dispatcher/tmp/13468761/extract-overlay-ramdisk-mxe54vv_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13468761/extract-overlay-ramdisk-mxe54vv_/ramdisk
200 01:22:50.069869 >> 276171 blocks
201 01:22:54.229289 rename /var/lib/lava/dispatcher/tmp/13468761/extract-overlay-ramdisk-mxe54vv_/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13468761/tftp-deploy-xzv199mm/ramdisk/ramdisk.cpio.gz
202 01:22:54.229718 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 01:22:54.229843 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 01:22:54.229940 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 01:22:54.230047 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13468761/tftp-deploy-xzv199mm/kernel/Image'
206 01:23:07.140083 Returned 0 in 12 seconds
207 01:23:07.240660 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13468761/tftp-deploy-xzv199mm/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13468761/tftp-deploy-xzv199mm/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13468761/tftp-deploy-xzv199mm/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13468761/tftp-deploy-xzv199mm/kernel/image.itb
208 01:23:07.857931 output: FIT description: Kernel Image image with one or more FDT blobs
209 01:23:07.858330 output: Created: Tue Apr 23 02:23:07 2024
210 01:23:07.858441 output: Image 0 (kernel-1)
211 01:23:07.858536 output: Description:
212 01:23:07.858630 output: Created: Tue Apr 23 02:23:07 2024
213 01:23:07.858720 output: Type: Kernel Image
214 01:23:07.858809 output: Compression: lzma compressed
215 01:23:07.858898 output: Data Size: 12910050 Bytes = 12607.47 KiB = 12.31 MiB
216 01:23:07.858984 output: Architecture: AArch64
217 01:23:07.859070 output: OS: Linux
218 01:23:07.859157 output: Load Address: 0x00000000
219 01:23:07.859242 output: Entry Point: 0x00000000
220 01:23:07.859328 output: Hash algo: crc32
221 01:23:07.859416 output: Hash value: 1126c3f9
222 01:23:07.859503 output: Image 1 (fdt-1)
223 01:23:07.859590 output: Description: mt8192-asurada-spherion-r0
224 01:23:07.859674 output: Created: Tue Apr 23 02:23:07 2024
225 01:23:07.859757 output: Type: Flat Device Tree
226 01:23:07.859840 output: Compression: uncompressed
227 01:23:07.859923 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
228 01:23:07.860006 output: Architecture: AArch64
229 01:23:07.860088 output: Hash algo: crc32
230 01:23:07.860171 output: Hash value: 4bf0d1ac
231 01:23:07.860253 output: Image 2 (ramdisk-1)
232 01:23:07.860335 output: Description: unavailable
233 01:23:07.860417 output: Created: Tue Apr 23 02:23:07 2024
234 01:23:07.860500 output: Type: RAMDisk Image
235 01:23:07.860582 output: Compression: Unknown Compression
236 01:23:07.860664 output: Data Size: 41251605 Bytes = 40284.77 KiB = 39.34 MiB
237 01:23:07.860747 output: Architecture: AArch64
238 01:23:07.860829 output: OS: Linux
239 01:23:07.860911 output: Load Address: unavailable
240 01:23:07.860994 output: Entry Point: unavailable
241 01:23:07.861076 output: Hash algo: crc32
242 01:23:07.861158 output: Hash value: 197fda82
243 01:23:07.861240 output: Default Configuration: 'conf-1'
244 01:23:07.861322 output: Configuration 0 (conf-1)
245 01:23:07.861404 output: Description: mt8192-asurada-spherion-r0
246 01:23:07.861486 output: Kernel: kernel-1
247 01:23:07.861569 output: Init Ramdisk: ramdisk-1
248 01:23:07.861651 output: FDT: fdt-1
249 01:23:07.861733 output: Loadables: kernel-1
250 01:23:07.861815 output:
251 01:23:07.862057 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 01:23:07.862181 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 01:23:07.862328 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 01:23:07.862426 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 01:23:07.862505 No LXC device requested
256 01:23:07.862587 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 01:23:07.862673 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 01:23:07.862755 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 01:23:07.862849 Checking files for TFTP limit of 4294967296 bytes.
260 01:23:07.863528 end: 1 tftp-deploy (duration 00:00:21) [common]
261 01:23:07.863687 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 01:23:07.863831 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 01:23:07.864007 substitutions:
264 01:23:07.864106 - {DTB}: 13468761/tftp-deploy-xzv199mm/dtb/mt8192-asurada-spherion-r0.dtb
265 01:23:07.864208 - {INITRD}: 13468761/tftp-deploy-xzv199mm/ramdisk/ramdisk.cpio.gz
266 01:23:07.864298 - {KERNEL}: 13468761/tftp-deploy-xzv199mm/kernel/Image
267 01:23:07.864386 - {LAVA_MAC}: None
268 01:23:07.864472 - {PRESEED_CONFIG}: None
269 01:23:07.864557 - {PRESEED_LOCAL}: None
270 01:23:07.864641 - {RAMDISK}: 13468761/tftp-deploy-xzv199mm/ramdisk/ramdisk.cpio.gz
271 01:23:07.864726 - {ROOT_PART}: None
272 01:23:07.864809 - {ROOT}: None
273 01:23:07.864893 - {SERVER_IP}: 192.168.201.1
274 01:23:07.864976 - {TEE}: None
275 01:23:07.865062 Parsed boot commands:
276 01:23:07.865154 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 01:23:07.865378 Parsed boot commands: tftpboot 192.168.201.1 13468761/tftp-deploy-xzv199mm/kernel/image.itb 13468761/tftp-deploy-xzv199mm/kernel/cmdline
278 01:23:07.865497 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 01:23:07.865614 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 01:23:07.865737 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 01:23:07.865868 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 01:23:07.865973 Not connected, no need to disconnect.
283 01:23:07.866079 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 01:23:07.866189 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 01:23:07.866285 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 01:23:07.870238 Setting prompt string to ['lava-test: # ']
287 01:23:07.870675 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 01:23:07.870822 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 01:23:07.870955 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 01:23:07.871078 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 01:23:07.871419 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 01:23:13.004721 >> Command sent successfully.
293 01:23:13.007124 Returned 0 in 5 seconds
294 01:23:13.107484 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 01:23:13.107913 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 01:23:13.108044 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 01:23:13.108166 Setting prompt string to 'Starting depthcharge on Spherion...'
299 01:23:13.108260 Changing prompt to 'Starting depthcharge on Spherion...'
300 01:23:13.108353 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 01:23:13.108692 [Enter `^Ec?' for help]
302 01:23:13.282106
303 01:23:13.282262
304 01:23:13.282381 F0: 102B 0000
305 01:23:13.282450
306 01:23:13.282513 F3: 1001 0000 [0200]
307 01:23:13.282572
308 01:23:13.285144 F3: 1001 0000
309 01:23:13.285226
310 01:23:13.285289 F7: 102D 0000
311 01:23:13.285349
312 01:23:13.288671 F1: 0000 0000
313 01:23:13.288752
314 01:23:13.288819 V0: 0000 0000 [0001]
315 01:23:13.288882
316 01:23:13.292069 00: 0007 8000
317 01:23:13.292187
318 01:23:13.292282 01: 0000 0000
319 01:23:13.292373
320 01:23:13.292464 BP: 0C00 0209 [0000]
321 01:23:13.295285
322 01:23:13.295390 G0: 1182 0000
323 01:23:13.295480
324 01:23:13.295565 EC: 0000 0021 [4000]
325 01:23:13.295654
326 01:23:13.299181 S7: 0000 0000 [0000]
327 01:23:13.299287
328 01:23:13.299379 CC: 0000 0000 [0001]
329 01:23:13.302238
330 01:23:13.302380 T0: 0000 0040 [010F]
331 01:23:13.302474
332 01:23:13.302564 Jump to BL
333 01:23:13.302654
334 01:23:13.328705
335 01:23:13.328878
336 01:23:13.329009
337 01:23:13.335843 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 01:23:13.339756 ARM64: Exception handlers installed.
339 01:23:13.342924 ARM64: Testing exception
340 01:23:13.346196 ARM64: Done test exception
341 01:23:13.352803 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 01:23:13.363709 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 01:23:13.370091 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 01:23:13.380405 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 01:23:13.387031 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 01:23:13.393337 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 01:23:13.405959 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 01:23:13.412232 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 01:23:13.431250 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 01:23:13.434504 WDT: Last reset was cold boot
351 01:23:13.438018 SPI1(PAD0) initialized at 2873684 Hz
352 01:23:13.441246 SPI5(PAD0) initialized at 992727 Hz
353 01:23:13.444418 VBOOT: Loading verstage.
354 01:23:13.451432 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 01:23:13.454383 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 01:23:13.458133 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 01:23:13.461154 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 01:23:13.468544 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 01:23:13.475764 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 01:23:13.486824 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 01:23:13.486944
362 01:23:13.487041
363 01:23:13.497428 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 01:23:13.500373 ARM64: Exception handlers installed.
365 01:23:13.500484 ARM64: Testing exception
366 01:23:13.503961 ARM64: Done test exception
367 01:23:13.507518 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 01:23:13.514053 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 01:23:13.527527 Probing TPM: . done!
370 01:23:13.527651 TPM ready after 0 ms
371 01:23:13.534181 Connected to device vid:did:rid of 1ae0:0028:00
372 01:23:13.541266 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 01:23:13.600360 Initialized TPM device CR50 revision 0
374 01:23:13.611935 tlcl_send_startup: Startup return code is 0
375 01:23:13.612084 TPM: setup succeeded
376 01:23:13.623339 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 01:23:13.632465 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 01:23:13.644448 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 01:23:13.654538 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 01:23:13.659091 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 01:23:13.662069 in-header: 03 07 00 00 08 00 00 00
382 01:23:13.666382 in-data: aa e4 47 04 13 02 00 00
383 01:23:13.666466 Chrome EC: UHEPI supported
384 01:23:13.673200 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 01:23:13.677546 in-header: 03 95 00 00 08 00 00 00
386 01:23:13.681248 in-data: 18 20 20 08 00 00 00 00
387 01:23:13.681356 Phase 1
388 01:23:13.684940 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 01:23:13.692415 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 01:23:13.699752 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 01:23:13.699873 Recovery requested (1009000e)
392 01:23:13.711937 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 01:23:13.715959 tlcl_extend: response is 0
394 01:23:13.725079 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 01:23:13.730897 tlcl_extend: response is 0
396 01:23:13.737401 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 01:23:13.757793 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 01:23:13.764107 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 01:23:13.764225
400 01:23:13.764319
401 01:23:13.774231 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 01:23:13.777749 ARM64: Exception handlers installed.
403 01:23:13.780604 ARM64: Testing exception
404 01:23:13.780715 ARM64: Done test exception
405 01:23:13.803072 pmic_efuse_setting: Set efuses in 11 msecs
406 01:23:13.806486 pmwrap_interface_init: Select PMIF_VLD_RDY
407 01:23:13.813096 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 01:23:13.816811 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 01:23:13.820834 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 01:23:13.828258 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 01:23:13.831904 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 01:23:13.835807 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 01:23:13.843046 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 01:23:13.846972 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 01:23:13.850896 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 01:23:13.854152 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 01:23:13.861904 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 01:23:13.865717 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 01:23:13.868972 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 01:23:13.876766 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 01:23:13.880479 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 01:23:13.887646 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 01:23:13.891325 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 01:23:13.899433 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 01:23:13.902554 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 01:23:13.910095 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 01:23:13.914455 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 01:23:13.921608 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 01:23:13.925271 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 01:23:13.932597 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 01:23:13.936135 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 01:23:13.943086 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 01:23:13.946984 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 01:23:13.954211 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 01:23:13.958069 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 01:23:13.961867 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 01:23:13.968995 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 01:23:13.972333 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 01:23:13.976163 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 01:23:13.983992 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 01:23:13.987539 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 01:23:13.991340 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 01:23:13.998917 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 01:23:14.002777 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 01:23:14.006575 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 01:23:14.009852 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 01:23:14.017254 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 01:23:14.021202 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 01:23:14.024423 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 01:23:14.028416 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 01:23:14.032166 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 01:23:14.035843 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 01:23:14.040072 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 01:23:14.046841 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 01:23:14.050769 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 01:23:14.053928 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 01:23:14.057883 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 01:23:14.065037 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 01:23:14.076543 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 01:23:14.079700 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 01:23:14.086793 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 01:23:14.094195 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 01:23:14.101582 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 01:23:14.105413 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 01:23:14.109189 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 01:23:14.116729 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x26
467 01:23:14.120106 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 01:23:14.128626 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 01:23:14.132061 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 01:23:14.141191 [RTC]rtc_get_frequency_meter,154: input=15, output=760
471 01:23:14.150942 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 01:23:14.159828 [RTC]rtc_get_frequency_meter,154: input=19, output=850
473 01:23:14.169606 [RTC]rtc_get_frequency_meter,154: input=17, output=807
474 01:23:14.179095 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 01:23:14.188240 [RTC]rtc_get_frequency_meter,154: input=16, output=782
476 01:23:14.198457 [RTC]rtc_get_frequency_meter,154: input=17, output=805
477 01:23:14.202210 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 01:23:14.206397 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 01:23:14.209657 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 01:23:14.216848 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 01:23:14.220757 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 01:23:14.224420 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 01:23:14.228156 ADC[4]: Raw value=906573 ID=7
484 01:23:14.228244 ADC[3]: Raw value=213441 ID=1
485 01:23:14.231886 RAM Code: 0x71
486 01:23:14.235406 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 01:23:14.239576 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 01:23:14.250557 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 01:23:14.254252 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 01:23:14.257588 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 01:23:14.262027 in-header: 03 07 00 00 08 00 00 00
492 01:23:14.265054 in-data: aa e4 47 04 13 02 00 00
493 01:23:14.268755 Chrome EC: UHEPI supported
494 01:23:14.276076 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 01:23:14.279723 in-header: 03 95 00 00 08 00 00 00
496 01:23:14.284463 in-data: 18 20 20 08 00 00 00 00
497 01:23:14.284553 MRC: failed to locate region type 0.
498 01:23:14.291432 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 01:23:14.295308 DRAM-K: Running full calibration
500 01:23:14.302432 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 01:23:14.302518 header.status = 0x0
502 01:23:14.306035 header.version = 0x6 (expected: 0x6)
503 01:23:14.309710 header.size = 0xd00 (expected: 0xd00)
504 01:23:14.309797 header.flags = 0x0
505 01:23:14.317107 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 01:23:14.335134 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 01:23:14.342625 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 01:23:14.346214 dram_init: ddr_geometry: 2
509 01:23:14.346337 [EMI] MDL number = 2
510 01:23:14.349752 [EMI] Get MDL freq = 0
511 01:23:14.349836 dram_init: ddr_type: 0
512 01:23:14.353642 is_discrete_lpddr4: 1
513 01:23:14.357382 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 01:23:14.357466
515 01:23:14.357532
516 01:23:14.357592 [Bian_co] ETT version 0.0.0.1
517 01:23:14.364720 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 01:23:14.364807
519 01:23:14.368696 dramc_set_vcore_voltage set vcore to 650000
520 01:23:14.368791 Read voltage for 800, 4
521 01:23:14.372598 Vio18 = 0
522 01:23:14.372681 Vcore = 650000
523 01:23:14.372747 Vdram = 0
524 01:23:14.372809 Vddq = 0
525 01:23:14.375853 Vmddr = 0
526 01:23:14.375935 dram_init: config_dvfs: 1
527 01:23:14.383423 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 01:23:14.387128 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 01:23:14.391435 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 01:23:14.394799 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 01:23:14.398582 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 01:23:14.402335 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 01:23:14.405564 MEM_TYPE=3, freq_sel=18
534 01:23:14.408870 sv_algorithm_assistance_LP4_1600
535 01:23:14.412666 ============ PULL DRAM RESETB DOWN ============
536 01:23:14.415891 ========== PULL DRAM RESETB DOWN end =========
537 01:23:14.422534 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 01:23:14.426424 ===================================
539 01:23:14.426508 LPDDR4 DRAM CONFIGURATION
540 01:23:14.430249 ===================================
541 01:23:14.433518 EX_ROW_EN[0] = 0x0
542 01:23:14.433602 EX_ROW_EN[1] = 0x0
543 01:23:14.436723 LP4Y_EN = 0x0
544 01:23:14.436806 WORK_FSP = 0x0
545 01:23:14.440628 WL = 0x2
546 01:23:14.440711 RL = 0x2
547 01:23:14.440776 BL = 0x2
548 01:23:14.444422 RPST = 0x0
549 01:23:14.444505 RD_PRE = 0x0
550 01:23:14.447681 WR_PRE = 0x1
551 01:23:14.447764 WR_PST = 0x0
552 01:23:14.451540 DBI_WR = 0x0
553 01:23:14.451624 DBI_RD = 0x0
554 01:23:14.454885 OTF = 0x1
555 01:23:14.458004 ===================================
556 01:23:14.461286 ===================================
557 01:23:14.461371 ANA top config
558 01:23:14.464896 ===================================
559 01:23:14.467980 DLL_ASYNC_EN = 0
560 01:23:14.471371 ALL_SLAVE_EN = 1
561 01:23:14.474672 NEW_RANK_MODE = 1
562 01:23:14.474760 DLL_IDLE_MODE = 1
563 01:23:14.477940 LP45_APHY_COMB_EN = 1
564 01:23:14.481191 TX_ODT_DIS = 1
565 01:23:14.485038 NEW_8X_MODE = 1
566 01:23:14.488791 ===================================
567 01:23:14.488874 ===================================
568 01:23:14.492006 data_rate = 1600
569 01:23:14.495415 CKR = 1
570 01:23:14.498620 DQ_P2S_RATIO = 8
571 01:23:14.502543 ===================================
572 01:23:14.505840 CA_P2S_RATIO = 8
573 01:23:14.508835 DQ_CA_OPEN = 0
574 01:23:14.508919 DQ_SEMI_OPEN = 0
575 01:23:14.511947 CA_SEMI_OPEN = 0
576 01:23:14.515377 CA_FULL_RATE = 0
577 01:23:14.518654 DQ_CKDIV4_EN = 1
578 01:23:14.521778 CA_CKDIV4_EN = 1
579 01:23:14.525353 CA_PREDIV_EN = 0
580 01:23:14.525435 PH8_DLY = 0
581 01:23:14.528828 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 01:23:14.532374 DQ_AAMCK_DIV = 4
583 01:23:14.535556 CA_AAMCK_DIV = 4
584 01:23:14.538732 CA_ADMCK_DIV = 4
585 01:23:14.541949 DQ_TRACK_CA_EN = 0
586 01:23:14.542031 CA_PICK = 800
587 01:23:14.545153 CA_MCKIO = 800
588 01:23:14.548978 MCKIO_SEMI = 0
589 01:23:14.552920 PLL_FREQ = 3068
590 01:23:14.556514 DQ_UI_PI_RATIO = 32
591 01:23:14.556674 CA_UI_PI_RATIO = 0
592 01:23:14.560438 ===================================
593 01:23:14.563768 ===================================
594 01:23:14.567302 memory_type:LPDDR4
595 01:23:14.567387 GP_NUM : 10
596 01:23:14.571662 SRAM_EN : 1
597 01:23:14.571782 MD32_EN : 0
598 01:23:14.575413 ===================================
599 01:23:14.578881 [ANA_INIT] >>>>>>>>>>>>>>
600 01:23:14.582740 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 01:23:14.586063 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 01:23:14.589900 ===================================
603 01:23:14.589989 data_rate = 1600,PCW = 0X7600
604 01:23:14.593009 ===================================
605 01:23:14.596234 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 01:23:14.602789 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 01:23:14.609552 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 01:23:14.613111 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 01:23:14.616192 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 01:23:14.619402 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 01:23:14.622664 [ANA_INIT] flow start
612 01:23:14.626264 [ANA_INIT] PLL >>>>>>>>
613 01:23:14.626394 [ANA_INIT] PLL <<<<<<<<
614 01:23:14.629284 [ANA_INIT] MIDPI >>>>>>>>
615 01:23:14.632670 [ANA_INIT] MIDPI <<<<<<<<
616 01:23:14.632773 [ANA_INIT] DLL >>>>>>>>
617 01:23:14.635942 [ANA_INIT] flow end
618 01:23:14.639206 ============ LP4 DIFF to SE enter ============
619 01:23:14.642593 ============ LP4 DIFF to SE exit ============
620 01:23:14.646244 [ANA_INIT] <<<<<<<<<<<<<
621 01:23:14.649712 [Flow] Enable top DCM control >>>>>
622 01:23:14.652883 [Flow] Enable top DCM control <<<<<
623 01:23:14.656027 Enable DLL master slave shuffle
624 01:23:14.662286 ==============================================================
625 01:23:14.662392 Gating Mode config
626 01:23:14.669349 ==============================================================
627 01:23:14.669433 Config description:
628 01:23:14.679324 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 01:23:14.685993 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 01:23:14.692868 SELPH_MODE 0: By rank 1: By Phase
631 01:23:14.696188 ==============================================================
632 01:23:14.699300 GAT_TRACK_EN = 1
633 01:23:14.703177 RX_GATING_MODE = 2
634 01:23:14.706434 RX_GATING_TRACK_MODE = 2
635 01:23:14.709630 SELPH_MODE = 1
636 01:23:14.712922 PICG_EARLY_EN = 1
637 01:23:14.715998 VALID_LAT_VALUE = 1
638 01:23:14.719525 ==============================================================
639 01:23:14.723053 Enter into Gating configuration >>>>
640 01:23:14.726099 Exit from Gating configuration <<<<
641 01:23:14.729380 Enter into DVFS_PRE_config >>>>>
642 01:23:14.742970 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 01:23:14.746039 Exit from DVFS_PRE_config <<<<<
644 01:23:14.746122 Enter into PICG configuration >>>>
645 01:23:14.749901 Exit from PICG configuration <<<<
646 01:23:14.753121 [RX_INPUT] configuration >>>>>
647 01:23:14.756275 [RX_INPUT] configuration <<<<<
648 01:23:14.763289 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 01:23:14.766121 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 01:23:14.773002 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 01:23:14.780015 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 01:23:14.786173 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 01:23:14.793104 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 01:23:14.796305 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 01:23:14.799914 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 01:23:14.803177 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 01:23:14.809591 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 01:23:14.813539 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 01:23:14.816880 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 01:23:14.820326 ===================================
661 01:23:14.823315 LPDDR4 DRAM CONFIGURATION
662 01:23:14.826797 ===================================
663 01:23:14.826879 EX_ROW_EN[0] = 0x0
664 01:23:14.829996 EX_ROW_EN[1] = 0x0
665 01:23:14.830078 LP4Y_EN = 0x0
666 01:23:14.833517 WORK_FSP = 0x0
667 01:23:14.833598 WL = 0x2
668 01:23:14.836836 RL = 0x2
669 01:23:14.836925 BL = 0x2
670 01:23:14.839977 RPST = 0x0
671 01:23:14.843151 RD_PRE = 0x0
672 01:23:14.843282 WR_PRE = 0x1
673 01:23:14.846885 WR_PST = 0x0
674 01:23:14.846968 DBI_WR = 0x0
675 01:23:14.850039 DBI_RD = 0x0
676 01:23:14.850121 OTF = 0x1
677 01:23:14.853222 ===================================
678 01:23:14.856489 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 01:23:14.860395 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 01:23:14.866985 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 01:23:14.869954 ===================================
682 01:23:14.873504 LPDDR4 DRAM CONFIGURATION
683 01:23:14.876912 ===================================
684 01:23:14.876994 EX_ROW_EN[0] = 0x10
685 01:23:14.880168 EX_ROW_EN[1] = 0x0
686 01:23:14.880307 LP4Y_EN = 0x0
687 01:23:14.883613 WORK_FSP = 0x0
688 01:23:14.883695 WL = 0x2
689 01:23:14.886848 RL = 0x2
690 01:23:14.886929 BL = 0x2
691 01:23:14.890261 RPST = 0x0
692 01:23:14.890382 RD_PRE = 0x0
693 01:23:14.893297 WR_PRE = 0x1
694 01:23:14.893378 WR_PST = 0x0
695 01:23:14.896873 DBI_WR = 0x0
696 01:23:14.896954 DBI_RD = 0x0
697 01:23:14.900322 OTF = 0x1
698 01:23:14.903541 ===================================
699 01:23:14.910425 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 01:23:14.913593 nWR fixed to 40
701 01:23:14.916585 [ModeRegInit_LP4] CH0 RK0
702 01:23:14.916667 [ModeRegInit_LP4] CH0 RK1
703 01:23:14.920197 [ModeRegInit_LP4] CH1 RK0
704 01:23:14.923431 [ModeRegInit_LP4] CH1 RK1
705 01:23:14.923513 match AC timing 13
706 01:23:14.929794 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 01:23:14.933786 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 01:23:14.936824 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 01:23:14.943397 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 01:23:14.947044 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 01:23:14.947124 [EMI DOE] emi_dcm 0
712 01:23:14.953397 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 01:23:14.953479 ==
714 01:23:14.956963 Dram Type= 6, Freq= 0, CH_0, rank 0
715 01:23:14.960290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 01:23:14.960372 ==
717 01:23:14.966762 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 01:23:14.969919 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 01:23:14.980965 [CA 0] Center 36 (6~67) winsize 62
720 01:23:14.984022 [CA 1] Center 36 (6~67) winsize 62
721 01:23:14.987542 [CA 2] Center 34 (4~65) winsize 62
722 01:23:14.990455 [CA 3] Center 33 (3~64) winsize 62
723 01:23:14.994082 [CA 4] Center 33 (3~64) winsize 62
724 01:23:14.997240 [CA 5] Center 32 (3~62) winsize 60
725 01:23:14.997321
726 01:23:15.000554 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 01:23:15.000636
728 01:23:15.004292 [CATrainingPosCal] consider 1 rank data
729 01:23:15.007547 u2DelayCellTimex100 = 270/100 ps
730 01:23:15.010500 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 01:23:15.013856 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 01:23:15.020765 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 01:23:15.023968 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 01:23:15.027763 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
735 01:23:15.030928 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
736 01:23:15.031010
737 01:23:15.034257 CA PerBit enable=1, Macro0, CA PI delay=32
738 01:23:15.034375
739 01:23:15.037389 [CBTSetCACLKResult] CA Dly = 32
740 01:23:15.037471 CS Dly: 4 (0~35)
741 01:23:15.037536 ==
742 01:23:15.041199 Dram Type= 6, Freq= 0, CH_0, rank 1
743 01:23:15.047989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 01:23:15.048077 ==
745 01:23:15.050927 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 01:23:15.057689 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 01:23:15.066945 [CA 0] Center 36 (6~67) winsize 62
748 01:23:15.070193 [CA 1] Center 36 (6~67) winsize 62
749 01:23:15.073379 [CA 2] Center 34 (3~65) winsize 63
750 01:23:15.076522 [CA 3] Center 33 (3~64) winsize 62
751 01:23:15.079893 [CA 4] Center 32 (2~63) winsize 62
752 01:23:15.083056 [CA 5] Center 32 (2~63) winsize 62
753 01:23:15.083174
754 01:23:15.087051 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 01:23:15.087168
756 01:23:15.090240 [CATrainingPosCal] consider 2 rank data
757 01:23:15.093192 u2DelayCellTimex100 = 270/100 ps
758 01:23:15.096891 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 01:23:15.099847 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 01:23:15.106890 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 01:23:15.110089 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
762 01:23:15.113189 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 01:23:15.117260 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
764 01:23:15.117341
765 01:23:15.120231 CA PerBit enable=1, Macro0, CA PI delay=32
766 01:23:15.120312
767 01:23:15.123419 [CBTSetCACLKResult] CA Dly = 32
768 01:23:15.123500 CS Dly: 5 (0~37)
769 01:23:15.123565
770 01:23:15.126947 ----->DramcWriteLeveling(PI) begin...
771 01:23:15.127030 ==
772 01:23:15.130590 Dram Type= 6, Freq= 0, CH_0, rank 0
773 01:23:15.137981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 01:23:15.138065 ==
775 01:23:15.138130 Write leveling (Byte 0): 33 => 33
776 01:23:15.141946 Write leveling (Byte 1): 29 => 29
777 01:23:15.145072 DramcWriteLeveling(PI) end<-----
778 01:23:15.145154
779 01:23:15.145218 ==
780 01:23:15.148909 Dram Type= 6, Freq= 0, CH_0, rank 0
781 01:23:15.152327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 01:23:15.152410 ==
783 01:23:15.156066 [Gating] SW mode calibration
784 01:23:15.163604 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 01:23:15.166736 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 01:23:15.173061 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 01:23:15.176773 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 01:23:15.180058 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 01:23:15.186596 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 01:23:15.190386 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 01:23:15.193592 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 01:23:15.199902 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 01:23:15.203254 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 01:23:15.206841 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 01:23:15.212995 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 01:23:15.216814 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 01:23:15.220211 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 01:23:15.226649 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 01:23:15.229816 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 01:23:15.233217 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 01:23:15.240074 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 01:23:15.243258 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 01:23:15.246616 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 01:23:15.253450 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
805 01:23:15.256485 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
806 01:23:15.259748 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 01:23:15.263104 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 01:23:15.269756 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 01:23:15.272971 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 01:23:15.276504 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 01:23:15.283166 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 01:23:15.286169 0 9 8 | B1->B0 | 2323 3030 | 1 0 | (1 1) (0 0)
813 01:23:15.289855 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
814 01:23:15.296444 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 01:23:15.300078 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 01:23:15.303050 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 01:23:15.310083 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 01:23:15.313287 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 01:23:15.316303 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 01:23:15.323416 0 10 8 | B1->B0 | 3030 2424 | 0 0 | (0 0) (1 0)
821 01:23:15.326738 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 01:23:15.329968 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 01:23:15.336457 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 01:23:15.339738 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 01:23:15.342966 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 01:23:15.349888 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 01:23:15.353397 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
828 01:23:15.356293 0 11 8 | B1->B0 | 2a2a 3837 | 0 1 | (0 0) (0 0)
829 01:23:15.360267 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
830 01:23:15.366868 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 01:23:15.370039 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 01:23:15.373485 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 01:23:15.380321 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 01:23:15.383591 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 01:23:15.386997 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 01:23:15.393579 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 01:23:15.396972 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 01:23:15.400397 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 01:23:15.406773 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 01:23:15.410101 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 01:23:15.413217 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 01:23:15.420409 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 01:23:15.423335 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 01:23:15.426833 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 01:23:15.433603 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 01:23:15.436783 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 01:23:15.440006 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 01:23:15.443244 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 01:23:15.450231 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 01:23:15.453577 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 01:23:15.456828 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 01:23:15.463670 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 01:23:15.466788 Total UI for P1: 0, mck2ui 16
854 01:23:15.469978 best dqsien dly found for B0: ( 0, 14, 6)
855 01:23:15.473518 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 01:23:15.476896 Total UI for P1: 0, mck2ui 16
857 01:23:15.480451 best dqsien dly found for B1: ( 0, 14, 8)
858 01:23:15.483697 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 01:23:15.487047 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 01:23:15.487131
861 01:23:15.490355 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 01:23:15.493536 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 01:23:15.497529 [Gating] SW calibration Done
864 01:23:15.497612 ==
865 01:23:15.500795 Dram Type= 6, Freq= 0, CH_0, rank 0
866 01:23:15.503962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 01:23:15.504045 ==
868 01:23:15.507324 RX Vref Scan: 0
869 01:23:15.507407
870 01:23:15.507473 RX Vref 0 -> 0, step: 1
871 01:23:15.510487
872 01:23:15.510571 RX Delay -130 -> 252, step: 16
873 01:23:15.517077 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
874 01:23:15.520951 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
875 01:23:15.523952 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
876 01:23:15.527588 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
877 01:23:15.530661 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
878 01:23:15.537295 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
879 01:23:15.540785 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
880 01:23:15.544097 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
881 01:23:15.547203 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
882 01:23:15.550671 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
883 01:23:15.554498 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
884 01:23:15.560794 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
885 01:23:15.564601 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
886 01:23:15.567889 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
887 01:23:15.570954 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
888 01:23:15.574204 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
889 01:23:15.577566 ==
890 01:23:15.581095 Dram Type= 6, Freq= 0, CH_0, rank 0
891 01:23:15.584610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 01:23:15.584694 ==
893 01:23:15.584761 DQS Delay:
894 01:23:15.587526 DQS0 = 0, DQS1 = 0
895 01:23:15.587607 DQM Delay:
896 01:23:15.590809 DQM0 = 88, DQM1 = 82
897 01:23:15.590890 DQ Delay:
898 01:23:15.594516 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
899 01:23:15.597645 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
900 01:23:15.600916 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
901 01:23:15.604684 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
902 01:23:15.604765
903 01:23:15.604831
904 01:23:15.604894 ==
905 01:23:15.607757 Dram Type= 6, Freq= 0, CH_0, rank 0
906 01:23:15.610914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 01:23:15.611092 ==
908 01:23:15.611193
909 01:23:15.611282
910 01:23:15.614762 TX Vref Scan disable
911 01:23:15.617921 == TX Byte 0 ==
912 01:23:15.620946 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
913 01:23:15.624484 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
914 01:23:15.627964 == TX Byte 1 ==
915 01:23:15.631243 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
916 01:23:15.634339 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
917 01:23:15.634434 ==
918 01:23:15.638150 Dram Type= 6, Freq= 0, CH_0, rank 0
919 01:23:15.641298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 01:23:15.641380 ==
921 01:23:15.655576 TX Vref=22, minBit 7, minWin=27, winSum=446
922 01:23:15.659002 TX Vref=24, minBit 4, minWin=27, winSum=448
923 01:23:15.662428 TX Vref=26, minBit 8, minWin=27, winSum=454
924 01:23:15.666037 TX Vref=28, minBit 8, minWin=28, winSum=459
925 01:23:15.669323 TX Vref=30, minBit 8, minWin=28, winSum=460
926 01:23:15.675981 TX Vref=32, minBit 10, minWin=27, winSum=453
927 01:23:15.679193 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 30
928 01:23:15.679275
929 01:23:15.682343 Final TX Range 1 Vref 30
930 01:23:15.682424
931 01:23:15.682489 ==
932 01:23:15.685673 Dram Type= 6, Freq= 0, CH_0, rank 0
933 01:23:15.689291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 01:23:15.689372 ==
935 01:23:15.692557
936 01:23:15.692637
937 01:23:15.692701 TX Vref Scan disable
938 01:23:15.695840 == TX Byte 0 ==
939 01:23:15.698966 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
940 01:23:15.706072 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
941 01:23:15.706154 == TX Byte 1 ==
942 01:23:15.708945 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
943 01:23:15.715753 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
944 01:23:15.715836
945 01:23:15.715901 [DATLAT]
946 01:23:15.715960 Freq=800, CH0 RK0
947 01:23:15.716038
948 01:23:15.719292 DATLAT Default: 0xa
949 01:23:15.719424 0, 0xFFFF, sum = 0
950 01:23:15.722347 1, 0xFFFF, sum = 0
951 01:23:15.722449 2, 0xFFFF, sum = 0
952 01:23:15.725631 3, 0xFFFF, sum = 0
953 01:23:15.725715 4, 0xFFFF, sum = 0
954 01:23:15.729285 5, 0xFFFF, sum = 0
955 01:23:15.732838 6, 0xFFFF, sum = 0
956 01:23:15.732923 7, 0xFFFF, sum = 0
957 01:23:15.735950 8, 0xFFFF, sum = 0
958 01:23:15.736034 9, 0x0, sum = 1
959 01:23:15.736101 10, 0x0, sum = 2
960 01:23:15.738985 11, 0x0, sum = 3
961 01:23:15.739069 12, 0x0, sum = 4
962 01:23:15.742901 best_step = 10
963 01:23:15.742983
964 01:23:15.743048 ==
965 01:23:15.746006 Dram Type= 6, Freq= 0, CH_0, rank 0
966 01:23:15.749317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 01:23:15.749400 ==
968 01:23:15.752559 RX Vref Scan: 1
969 01:23:15.752642
970 01:23:15.752708 Set Vref Range= 32 -> 127
971 01:23:15.752770
972 01:23:15.756686 RX Vref 32 -> 127, step: 1
973 01:23:15.756768
974 01:23:15.759677 RX Delay -95 -> 252, step: 8
975 01:23:15.759759
976 01:23:15.762878 Set Vref, RX VrefLevel [Byte0]: 32
977 01:23:15.765980 [Byte1]: 32
978 01:23:15.766062
979 01:23:15.769149 Set Vref, RX VrefLevel [Byte0]: 33
980 01:23:15.772519 [Byte1]: 33
981 01:23:15.776381
982 01:23:15.776464 Set Vref, RX VrefLevel [Byte0]: 34
983 01:23:15.779781 [Byte1]: 34
984 01:23:15.783555
985 01:23:15.783637 Set Vref, RX VrefLevel [Byte0]: 35
986 01:23:15.787377 [Byte1]: 35
987 01:23:15.791709
988 01:23:15.791791 Set Vref, RX VrefLevel [Byte0]: 36
989 01:23:15.795611 [Byte1]: 36
990 01:23:15.799593
991 01:23:15.799675 Set Vref, RX VrefLevel [Byte0]: 37
992 01:23:15.802856 [Byte1]: 37
993 01:23:15.807364
994 01:23:15.807447 Set Vref, RX VrefLevel [Byte0]: 38
995 01:23:15.810719 [Byte1]: 38
996 01:23:15.815329
997 01:23:15.815411 Set Vref, RX VrefLevel [Byte0]: 39
998 01:23:15.818421 [Byte1]: 39
999 01:23:15.822752
1000 01:23:15.822834 Set Vref, RX VrefLevel [Byte0]: 40
1001 01:23:15.825729 [Byte1]: 40
1002 01:23:15.829187
1003 01:23:15.829269 Set Vref, RX VrefLevel [Byte0]: 41
1004 01:23:15.832842 [Byte1]: 41
1005 01:23:15.837083
1006 01:23:15.837165 Set Vref, RX VrefLevel [Byte0]: 42
1007 01:23:15.840189 [Byte1]: 42
1008 01:23:15.844440
1009 01:23:15.844523 Set Vref, RX VrefLevel [Byte0]: 43
1010 01:23:15.847845 [Byte1]: 43
1011 01:23:15.852402
1012 01:23:15.852485 Set Vref, RX VrefLevel [Byte0]: 44
1013 01:23:15.855721 [Byte1]: 44
1014 01:23:15.860268
1015 01:23:15.860350 Set Vref, RX VrefLevel [Byte0]: 45
1016 01:23:15.863329 [Byte1]: 45
1017 01:23:15.867199
1018 01:23:15.867286 Set Vref, RX VrefLevel [Byte0]: 46
1019 01:23:15.870495 [Byte1]: 46
1020 01:23:15.874974
1021 01:23:15.875058 Set Vref, RX VrefLevel [Byte0]: 47
1022 01:23:15.878169 [Byte1]: 47
1023 01:23:15.882298
1024 01:23:15.882519 Set Vref, RX VrefLevel [Byte0]: 48
1025 01:23:15.886150 [Byte1]: 48
1026 01:23:15.889893
1027 01:23:15.889993 Set Vref, RX VrefLevel [Byte0]: 49
1028 01:23:15.893456 [Byte1]: 49
1029 01:23:15.897633
1030 01:23:15.897718 Set Vref, RX VrefLevel [Byte0]: 50
1031 01:23:15.901222 [Byte1]: 50
1032 01:23:15.905377
1033 01:23:15.905495 Set Vref, RX VrefLevel [Byte0]: 51
1034 01:23:15.908539 [Byte1]: 51
1035 01:23:15.912960
1036 01:23:15.913047 Set Vref, RX VrefLevel [Byte0]: 52
1037 01:23:15.916234 [Byte1]: 52
1038 01:23:15.920833
1039 01:23:15.920916 Set Vref, RX VrefLevel [Byte0]: 53
1040 01:23:15.924494 [Byte1]: 53
1041 01:23:15.928020
1042 01:23:15.928117 Set Vref, RX VrefLevel [Byte0]: 54
1043 01:23:15.931207 [Byte1]: 54
1044 01:23:15.935642
1045 01:23:15.935729 Set Vref, RX VrefLevel [Byte0]: 55
1046 01:23:15.939008 [Byte1]: 55
1047 01:23:15.943298
1048 01:23:15.943398 Set Vref, RX VrefLevel [Byte0]: 56
1049 01:23:15.946839 [Byte1]: 56
1050 01:23:15.950804
1051 01:23:15.950930 Set Vref, RX VrefLevel [Byte0]: 57
1052 01:23:15.954221 [Byte1]: 57
1053 01:23:15.958483
1054 01:23:15.958573 Set Vref, RX VrefLevel [Byte0]: 58
1055 01:23:15.961986 [Byte1]: 58
1056 01:23:15.966343
1057 01:23:15.966449 Set Vref, RX VrefLevel [Byte0]: 59
1058 01:23:15.969642 [Byte1]: 59
1059 01:23:15.973654
1060 01:23:15.973748 Set Vref, RX VrefLevel [Byte0]: 60
1061 01:23:15.976944 [Byte1]: 60
1062 01:23:15.981366
1063 01:23:15.981450 Set Vref, RX VrefLevel [Byte0]: 61
1064 01:23:15.984545 [Byte1]: 61
1065 01:23:15.988827
1066 01:23:15.988942 Set Vref, RX VrefLevel [Byte0]: 62
1067 01:23:15.992416 [Byte1]: 62
1068 01:23:15.996280
1069 01:23:15.996384 Set Vref, RX VrefLevel [Byte0]: 63
1070 01:23:16.000097 [Byte1]: 63
1071 01:23:16.003803
1072 01:23:16.003911 Set Vref, RX VrefLevel [Byte0]: 64
1073 01:23:16.007348 [Byte1]: 64
1074 01:23:16.011985
1075 01:23:16.012105 Set Vref, RX VrefLevel [Byte0]: 65
1076 01:23:16.015168 [Byte1]: 65
1077 01:23:16.019283
1078 01:23:16.019396 Set Vref, RX VrefLevel [Byte0]: 66
1079 01:23:16.022794 [Byte1]: 66
1080 01:23:16.026996
1081 01:23:16.027119 Set Vref, RX VrefLevel [Byte0]: 67
1082 01:23:16.030173 [Byte1]: 67
1083 01:23:16.034771
1084 01:23:16.034878 Set Vref, RX VrefLevel [Byte0]: 68
1085 01:23:16.037867 [Byte1]: 68
1086 01:23:16.042223
1087 01:23:16.042353 Set Vref, RX VrefLevel [Byte0]: 69
1088 01:23:16.045630 [Byte1]: 69
1089 01:23:16.050018
1090 01:23:16.050135 Set Vref, RX VrefLevel [Byte0]: 70
1091 01:23:16.053068 [Byte1]: 70
1092 01:23:16.057250
1093 01:23:16.057371 Set Vref, RX VrefLevel [Byte0]: 71
1094 01:23:16.060916 [Byte1]: 71
1095 01:23:16.065111
1096 01:23:16.065224 Set Vref, RX VrefLevel [Byte0]: 72
1097 01:23:16.068199 [Byte1]: 72
1098 01:23:16.072513
1099 01:23:16.072635 Set Vref, RX VrefLevel [Byte0]: 73
1100 01:23:16.075946 [Byte1]: 73
1101 01:23:16.080191
1102 01:23:16.080357 Set Vref, RX VrefLevel [Byte0]: 74
1103 01:23:16.083371 [Byte1]: 74
1104 01:23:16.087655
1105 01:23:16.087822 Set Vref, RX VrefLevel [Byte0]: 75
1106 01:23:16.090823 [Byte1]: 75
1107 01:23:16.095073
1108 01:23:16.095198 Set Vref, RX VrefLevel [Byte0]: 76
1109 01:23:16.098722 [Byte1]: 76
1110 01:23:16.103249
1111 01:23:16.103380 Final RX Vref Byte 0 = 59 to rank0
1112 01:23:16.106457 Final RX Vref Byte 1 = 60 to rank0
1113 01:23:16.109741 Final RX Vref Byte 0 = 59 to rank1
1114 01:23:16.112763 Final RX Vref Byte 1 = 60 to rank1==
1115 01:23:16.115918 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 01:23:16.122967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 01:23:16.123114 ==
1118 01:23:16.123210 DQS Delay:
1119 01:23:16.123298 DQS0 = 0, DQS1 = 0
1120 01:23:16.126186 DQM Delay:
1121 01:23:16.126297 DQM0 = 92, DQM1 = 86
1122 01:23:16.129961 DQ Delay:
1123 01:23:16.133101 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1124 01:23:16.135997 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1125 01:23:16.139932 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =76
1126 01:23:16.143448 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1127 01:23:16.143583
1128 01:23:16.143676
1129 01:23:16.149788 [DQSOSCAuto] RK0, (LSB)MR18= 0x493f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1130 01:23:16.153046 CH0 RK0: MR19=606, MR18=493F
1131 01:23:16.159895 CH0_RK0: MR19=0x606, MR18=0x493F, DQSOSC=391, MR23=63, INC=96, DEC=64
1132 01:23:16.160050
1133 01:23:16.163092 ----->DramcWriteLeveling(PI) begin...
1134 01:23:16.163217 ==
1135 01:23:16.166226 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 01:23:16.169364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 01:23:16.169486 ==
1138 01:23:16.172892 Write leveling (Byte 0): 30 => 30
1139 01:23:16.176708 Write leveling (Byte 1): 29 => 29
1140 01:23:16.179622 DramcWriteLeveling(PI) end<-----
1141 01:23:16.179744
1142 01:23:16.179839 ==
1143 01:23:16.183636 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 01:23:16.186623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 01:23:16.186744 ==
1146 01:23:16.189791 [Gating] SW mode calibration
1147 01:23:16.196796 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 01:23:16.241167 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 01:23:16.241567 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 01:23:16.241697 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1151 01:23:16.242201 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1152 01:23:16.242322 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 01:23:16.242620 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 01:23:16.242730 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 01:23:16.242830 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 01:23:16.242929 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 01:23:16.243023 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 01:23:16.283077 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 01:23:16.283692 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 01:23:16.284162 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 01:23:16.284283 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 01:23:16.284389 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 01:23:16.284929 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 01:23:16.285372 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 01:23:16.285714 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 01:23:16.285847 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1167 01:23:16.285959 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1168 01:23:16.288945 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 01:23:16.295609 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 01:23:16.298761 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 01:23:16.302389 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 01:23:16.309149 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 01:23:16.312457 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 01:23:16.315924 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 01:23:16.322195 0 9 8 | B1->B0 | 3131 2828 | 0 0 | (0 0) (0 0)
1176 01:23:16.326034 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 01:23:16.329230 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 01:23:16.332314 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 01:23:16.339109 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 01:23:16.342132 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 01:23:16.345975 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 01:23:16.352458 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 01:23:16.355857 0 10 8 | B1->B0 | 2727 2929 | 0 0 | (0 0) (0 1)
1184 01:23:16.358973 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1185 01:23:16.365663 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 01:23:16.369501 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 01:23:16.372719 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 01:23:16.376638 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 01:23:16.384766 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 01:23:16.388571 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1191 01:23:16.391439 0 11 8 | B1->B0 | 3c3c 3535 | 0 1 | (0 0) (0 0)
1192 01:23:16.395234 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 01:23:16.398577 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 01:23:16.405919 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 01:23:16.409141 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 01:23:16.412355 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 01:23:16.415978 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 01:23:16.422368 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 01:23:16.425781 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1200 01:23:16.429215 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 01:23:16.435721 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 01:23:16.438879 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 01:23:16.442326 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 01:23:16.448855 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 01:23:16.452643 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 01:23:16.455926 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 01:23:16.462275 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 01:23:16.465538 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 01:23:16.468833 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 01:23:16.475752 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 01:23:16.479066 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 01:23:16.482274 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 01:23:16.488812 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 01:23:16.492363 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 01:23:16.495920 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1216 01:23:16.499219 Total UI for P1: 0, mck2ui 16
1217 01:23:16.502482 best dqsien dly found for B0: ( 0, 14, 6)
1218 01:23:16.505737 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 01:23:16.508950 Total UI for P1: 0, mck2ui 16
1220 01:23:16.512156 best dqsien dly found for B1: ( 0, 14, 8)
1221 01:23:16.515422 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1222 01:23:16.522469 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1223 01:23:16.522669
1224 01:23:16.525689 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1225 01:23:16.528831 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1226 01:23:16.532452 [Gating] SW calibration Done
1227 01:23:16.532624 ==
1228 01:23:16.535464 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 01:23:16.538781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 01:23:16.538955 ==
1231 01:23:16.539064 RX Vref Scan: 0
1232 01:23:16.539158
1233 01:23:16.542554 RX Vref 0 -> 0, step: 1
1234 01:23:16.542728
1235 01:23:16.545756 RX Delay -130 -> 252, step: 16
1236 01:23:16.548632 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1237 01:23:16.552397 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1238 01:23:16.558899 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1239 01:23:16.562153 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1240 01:23:16.566003 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1241 01:23:16.568882 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1242 01:23:16.572026 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1243 01:23:16.578937 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1244 01:23:16.582436 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1245 01:23:16.586016 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1246 01:23:16.589359 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1247 01:23:16.592690 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1248 01:23:16.599269 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1249 01:23:16.602341 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1250 01:23:16.605558 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1251 01:23:16.608821 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1252 01:23:16.609058 ==
1253 01:23:16.612811 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 01:23:16.615984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 01:23:16.619279 ==
1256 01:23:16.619542 DQS Delay:
1257 01:23:16.619690 DQS0 = 0, DQS1 = 0
1258 01:23:16.622494 DQM Delay:
1259 01:23:16.622680 DQM0 = 93, DQM1 = 85
1260 01:23:16.626319 DQ Delay:
1261 01:23:16.628863 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1262 01:23:16.629294 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1263 01:23:16.632573 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1264 01:23:16.638883 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1265 01:23:16.639164
1266 01:23:16.639318
1267 01:23:16.639550 ==
1268 01:23:16.642871 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 01:23:16.645880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 01:23:16.646185 ==
1271 01:23:16.646384
1272 01:23:16.646517
1273 01:23:16.649373 TX Vref Scan disable
1274 01:23:16.649579 == TX Byte 0 ==
1275 01:23:16.655846 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1276 01:23:16.658916 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1277 01:23:16.659102 == TX Byte 1 ==
1278 01:23:16.666122 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1279 01:23:16.669147 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1280 01:23:16.669316 ==
1281 01:23:16.672651 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 01:23:16.675991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 01:23:16.676143 ==
1284 01:23:16.689707 TX Vref=22, minBit 15, minWin=27, winSum=451
1285 01:23:16.692880 TX Vref=24, minBit 1, minWin=28, winSum=455
1286 01:23:16.696065 TX Vref=26, minBit 1, minWin=28, winSum=458
1287 01:23:16.699973 TX Vref=28, minBit 8, minWin=28, winSum=461
1288 01:23:16.703169 TX Vref=30, minBit 5, minWin=28, winSum=457
1289 01:23:16.709655 TX Vref=32, minBit 8, minWin=28, winSum=459
1290 01:23:16.712664 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 28
1291 01:23:16.712837
1292 01:23:16.718915 Final TX Range 1 Vref 28
1293 01:23:16.719099
1294 01:23:16.719205 ==
1295 01:23:16.723317 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 01:23:16.723701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 01:23:16.723835 ==
1298 01:23:16.725791
1299 01:23:16.725912
1300 01:23:16.726007 TX Vref Scan disable
1301 01:23:16.729771 == TX Byte 0 ==
1302 01:23:16.732885 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1303 01:23:16.735957 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1304 01:23:16.739955 == TX Byte 1 ==
1305 01:23:16.743183 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1306 01:23:16.746590 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1307 01:23:16.749831
1308 01:23:16.749971 [DATLAT]
1309 01:23:16.750076 Freq=800, CH0 RK1
1310 01:23:16.750163
1311 01:23:16.753240 DATLAT Default: 0xa
1312 01:23:16.753372 0, 0xFFFF, sum = 0
1313 01:23:16.756569 1, 0xFFFF, sum = 0
1314 01:23:16.756742 2, 0xFFFF, sum = 0
1315 01:23:16.759855 3, 0xFFFF, sum = 0
1316 01:23:16.760014 4, 0xFFFF, sum = 0
1317 01:23:16.762824 5, 0xFFFF, sum = 0
1318 01:23:16.763027 6, 0xFFFF, sum = 0
1319 01:23:16.766651 7, 0xFFFF, sum = 0
1320 01:23:16.769819 8, 0xFFFF, sum = 0
1321 01:23:16.770015 9, 0x0, sum = 1
1322 01:23:16.770112 10, 0x0, sum = 2
1323 01:23:16.773099 11, 0x0, sum = 3
1324 01:23:16.773228 12, 0x0, sum = 4
1325 01:23:16.776418 best_step = 10
1326 01:23:16.776598
1327 01:23:16.776694 ==
1328 01:23:16.779294 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 01:23:16.782980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 01:23:16.783147 ==
1331 01:23:16.786354 RX Vref Scan: 0
1332 01:23:16.786523
1333 01:23:16.786628 RX Vref 0 -> 0, step: 1
1334 01:23:16.786722
1335 01:23:16.789618 RX Delay -95 -> 252, step: 8
1336 01:23:16.796703 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1337 01:23:16.799943 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1338 01:23:16.803224 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1339 01:23:16.806363 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1340 01:23:16.810102 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1341 01:23:16.816365 iDelay=209, Bit 5, Center 84 (-31 ~ 200) 232
1342 01:23:16.819821 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1343 01:23:16.822940 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1344 01:23:16.826469 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1345 01:23:16.829963 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1346 01:23:16.833276 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1347 01:23:16.839845 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1348 01:23:16.843379 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1349 01:23:16.846698 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1350 01:23:16.850016 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1351 01:23:16.856920 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1352 01:23:16.857108 ==
1353 01:23:16.860000 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 01:23:16.863111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 01:23:16.863275 ==
1356 01:23:16.863381 DQS Delay:
1357 01:23:16.866359 DQS0 = 0, DQS1 = 0
1358 01:23:16.866506 DQM Delay:
1359 01:23:16.869881 DQM0 = 91, DQM1 = 83
1360 01:23:16.870030 DQ Delay:
1361 01:23:16.873011 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =88
1362 01:23:16.877116 DQ4 =92, DQ5 =84, DQ6 =96, DQ7 =100
1363 01:23:16.880226 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1364 01:23:16.883504 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =92
1365 01:23:16.883669
1366 01:23:16.883778
1367 01:23:16.890117 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e0f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps
1368 01:23:16.893348 CH0 RK1: MR19=606, MR18=3E0F
1369 01:23:16.899987 CH0_RK1: MR19=0x606, MR18=0x3E0F, DQSOSC=394, MR23=63, INC=95, DEC=63
1370 01:23:16.903486 [RxdqsGatingPostProcess] freq 800
1371 01:23:16.909992 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1372 01:23:16.910179 Pre-setting of DQS Precalculation
1373 01:23:16.917008 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1374 01:23:16.917196 ==
1375 01:23:16.920183 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 01:23:16.923317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 01:23:16.923487 ==
1378 01:23:16.930395 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1379 01:23:16.936621 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1380 01:23:16.944579 [CA 0] Center 36 (6~67) winsize 62
1381 01:23:16.947761 [CA 1] Center 36 (6~67) winsize 62
1382 01:23:16.951502 [CA 2] Center 35 (4~66) winsize 63
1383 01:23:16.954587 [CA 3] Center 34 (4~65) winsize 62
1384 01:23:16.957723 [CA 4] Center 35 (5~65) winsize 61
1385 01:23:16.961202 [CA 5] Center 34 (4~64) winsize 61
1386 01:23:16.961361
1387 01:23:16.964789 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1388 01:23:16.964946
1389 01:23:16.967781 [CATrainingPosCal] consider 1 rank data
1390 01:23:16.971753 u2DelayCellTimex100 = 270/100 ps
1391 01:23:16.974629 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1392 01:23:16.977814 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1393 01:23:16.984436 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1394 01:23:16.987713 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1395 01:23:16.991244 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1396 01:23:16.994479 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1397 01:23:16.994633
1398 01:23:16.998049 CA PerBit enable=1, Macro0, CA PI delay=34
1399 01:23:16.998243
1400 01:23:17.001440 [CBTSetCACLKResult] CA Dly = 34
1401 01:23:17.001587 CS Dly: 6 (0~37)
1402 01:23:17.001692 ==
1403 01:23:17.004877 Dram Type= 6, Freq= 0, CH_1, rank 1
1404 01:23:17.011406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 01:23:17.011862 ==
1406 01:23:17.014638 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 01:23:17.021113 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 01:23:17.030536 [CA 0] Center 36 (6~67) winsize 62
1409 01:23:17.034133 [CA 1] Center 37 (6~68) winsize 63
1410 01:23:17.037545 [CA 2] Center 35 (4~66) winsize 63
1411 01:23:17.040926 [CA 3] Center 34 (4~65) winsize 62
1412 01:23:17.044720 [CA 4] Center 35 (5~66) winsize 62
1413 01:23:17.048621 [CA 5] Center 34 (4~65) winsize 62
1414 01:23:17.048811
1415 01:23:17.052561 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1416 01:23:17.052736
1417 01:23:17.056294 [CATrainingPosCal] consider 2 rank data
1418 01:23:17.060172 u2DelayCellTimex100 = 270/100 ps
1419 01:23:17.060368 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1420 01:23:17.064162 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1421 01:23:17.068080 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1422 01:23:17.071370 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1423 01:23:17.074771 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1424 01:23:17.081550 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1425 01:23:17.081730
1426 01:23:17.084768 CA PerBit enable=1, Macro0, CA PI delay=34
1427 01:23:17.084903
1428 01:23:17.088127 [CBTSetCACLKResult] CA Dly = 34
1429 01:23:17.088274 CS Dly: 7 (0~39)
1430 01:23:17.088377
1431 01:23:17.091511 ----->DramcWriteLeveling(PI) begin...
1432 01:23:17.091646 ==
1433 01:23:17.094702 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 01:23:17.101389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 01:23:17.101573 ==
1436 01:23:17.104936 Write leveling (Byte 0): 27 => 27
1437 01:23:17.105075 Write leveling (Byte 1): 27 => 27
1438 01:23:17.107883 DramcWriteLeveling(PI) end<-----
1439 01:23:17.108010
1440 01:23:17.108107 ==
1441 01:23:17.111222 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 01:23:17.117935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 01:23:17.118117 ==
1444 01:23:17.121531 [Gating] SW mode calibration
1445 01:23:17.128002 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1446 01:23:17.131107 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1447 01:23:17.137798 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 01:23:17.141527 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1449 01:23:17.144768 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 01:23:17.148166 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 01:23:17.154538 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 01:23:17.158344 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 01:23:17.161515 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 01:23:17.167885 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 01:23:17.171679 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 01:23:17.174904 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 01:23:17.181390 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 01:23:17.184694 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 01:23:17.187916 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 01:23:17.194808 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 01:23:17.197917 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 01:23:17.201592 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 01:23:17.207879 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1464 01:23:17.211263 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1465 01:23:17.215002 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 01:23:17.221570 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 01:23:17.224712 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 01:23:17.228156 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 01:23:17.234757 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 01:23:17.237804 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 01:23:17.241293 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 01:23:17.248007 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
1473 01:23:17.251050 0 9 8 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
1474 01:23:17.254382 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 01:23:17.258140 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 01:23:17.264483 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 01:23:17.267840 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 01:23:17.271371 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 01:23:17.277995 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1480 01:23:17.281945 0 10 4 | B1->B0 | 3030 2d2d | 0 1 | (0 1) (1 1)
1481 01:23:17.284726 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1482 01:23:17.291612 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 01:23:17.295056 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 01:23:17.298170 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 01:23:17.304514 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 01:23:17.308105 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 01:23:17.311220 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1488 01:23:17.318397 0 11 4 | B1->B0 | 2c2c 3737 | 1 1 | (0 0) (0 0)
1489 01:23:17.321675 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1490 01:23:17.324839 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 01:23:17.331262 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 01:23:17.334596 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 01:23:17.337860 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 01:23:17.344377 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 01:23:17.348076 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 01:23:17.351082 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1497 01:23:17.354596 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 01:23:17.361292 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 01:23:17.364567 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 01:23:17.367819 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 01:23:17.374820 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 01:23:17.377799 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 01:23:17.381104 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 01:23:17.387714 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 01:23:17.391120 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 01:23:17.394676 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 01:23:17.401354 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 01:23:17.404588 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 01:23:17.407771 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 01:23:17.414535 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 01:23:17.417689 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 01:23:17.421014 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1513 01:23:17.428087 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1514 01:23:17.428349 Total UI for P1: 0, mck2ui 16
1515 01:23:17.434647 best dqsien dly found for B1: ( 0, 14, 4)
1516 01:23:17.437704 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 01:23:17.440965 Total UI for P1: 0, mck2ui 16
1518 01:23:17.444786 best dqsien dly found for B0: ( 0, 14, 8)
1519 01:23:17.448002 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1520 01:23:17.451301 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1521 01:23:17.451510
1522 01:23:17.454508 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1523 01:23:17.457838 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1524 01:23:17.460934 [Gating] SW calibration Done
1525 01:23:17.461144 ==
1526 01:23:17.464559 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 01:23:17.467611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 01:23:17.467832 ==
1529 01:23:17.470769 RX Vref Scan: 0
1530 01:23:17.470915
1531 01:23:17.474527 RX Vref 0 -> 0, step: 1
1532 01:23:17.474673
1533 01:23:17.474778 RX Delay -130 -> 252, step: 16
1534 01:23:17.480852 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1535 01:23:17.484227 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1536 01:23:17.487727 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1537 01:23:17.490867 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1538 01:23:17.494144 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1539 01:23:17.501084 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1540 01:23:17.504081 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1541 01:23:17.507972 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1542 01:23:17.511124 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1543 01:23:17.514396 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1544 01:23:17.520939 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1545 01:23:17.524544 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1546 01:23:17.527694 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1547 01:23:17.530871 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1548 01:23:17.534159 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1549 01:23:17.541390 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1550 01:23:17.541576 ==
1551 01:23:17.544526 Dram Type= 6, Freq= 0, CH_1, rank 0
1552 01:23:17.547777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1553 01:23:17.547934 ==
1554 01:23:17.548036 DQS Delay:
1555 01:23:17.550986 DQS0 = 0, DQS1 = 0
1556 01:23:17.551115 DQM Delay:
1557 01:23:17.554235 DQM0 = 93, DQM1 = 87
1558 01:23:17.554385 DQ Delay:
1559 01:23:17.557463 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1560 01:23:17.561252 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1561 01:23:17.564613 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1562 01:23:17.567848 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1563 01:23:17.568006
1564 01:23:17.568106
1565 01:23:17.568199 ==
1566 01:23:17.570890 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 01:23:17.574531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 01:23:17.574717 ==
1569 01:23:17.577502
1570 01:23:17.577668
1571 01:23:17.577804 TX Vref Scan disable
1572 01:23:17.581180 == TX Byte 0 ==
1573 01:23:17.584410 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1574 01:23:17.587842 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1575 01:23:17.591393 == TX Byte 1 ==
1576 01:23:17.594291 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1577 01:23:17.597744 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1578 01:23:17.597894 ==
1579 01:23:17.601223 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 01:23:17.607557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 01:23:17.607741 ==
1582 01:23:17.620362 TX Vref=22, minBit 1, minWin=26, winSum=436
1583 01:23:17.623606 TX Vref=24, minBit 0, minWin=27, winSum=444
1584 01:23:17.627234 TX Vref=26, minBit 1, minWin=27, winSum=447
1585 01:23:17.630294 TX Vref=28, minBit 1, minWin=27, winSum=448
1586 01:23:17.633776 TX Vref=30, minBit 1, minWin=27, winSum=451
1587 01:23:17.636769 TX Vref=32, minBit 1, minWin=27, winSum=447
1588 01:23:17.643848 [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 30
1589 01:23:17.644047
1590 01:23:17.646748 Final TX Range 1 Vref 30
1591 01:23:17.646919
1592 01:23:17.647021 ==
1593 01:23:17.650191 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 01:23:17.653488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 01:23:17.653661 ==
1596 01:23:17.653763
1597 01:23:17.653856
1598 01:23:17.657365 TX Vref Scan disable
1599 01:23:17.660611 == TX Byte 0 ==
1600 01:23:17.663767 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1601 01:23:17.667025 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1602 01:23:17.670297 == TX Byte 1 ==
1603 01:23:17.673557 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1604 01:23:17.677554 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1605 01:23:17.677734
1606 01:23:17.677834 [DATLAT]
1607 01:23:17.680437 Freq=800, CH1 RK0
1608 01:23:17.680571
1609 01:23:17.683564 DATLAT Default: 0xa
1610 01:23:17.683716 0, 0xFFFF, sum = 0
1611 01:23:17.687165 1, 0xFFFF, sum = 0
1612 01:23:17.687338 2, 0xFFFF, sum = 0
1613 01:23:17.690359 3, 0xFFFF, sum = 0
1614 01:23:17.690513 4, 0xFFFF, sum = 0
1615 01:23:17.693496 5, 0xFFFF, sum = 0
1616 01:23:17.693651 6, 0xFFFF, sum = 0
1617 01:23:17.697229 7, 0xFFFF, sum = 0
1618 01:23:17.697392 8, 0xFFFF, sum = 0
1619 01:23:17.700364 9, 0x0, sum = 1
1620 01:23:17.700610 10, 0x0, sum = 2
1621 01:23:17.704027 11, 0x0, sum = 3
1622 01:23:17.704184 12, 0x0, sum = 4
1623 01:23:17.704285 best_step = 10
1624 01:23:17.706871
1625 01:23:17.707022 ==
1626 01:23:17.710448 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 01:23:17.713587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 01:23:17.713758 ==
1629 01:23:17.713860 RX Vref Scan: 1
1630 01:23:17.713954
1631 01:23:17.717432 Set Vref Range= 32 -> 127
1632 01:23:17.717592
1633 01:23:17.720670 RX Vref 32 -> 127, step: 1
1634 01:23:17.720830
1635 01:23:17.723961 RX Delay -79 -> 252, step: 8
1636 01:23:17.724128
1637 01:23:17.727155 Set Vref, RX VrefLevel [Byte0]: 32
1638 01:23:17.730191 [Byte1]: 32
1639 01:23:17.730367
1640 01:23:17.733627 Set Vref, RX VrefLevel [Byte0]: 33
1641 01:23:17.737152 [Byte1]: 33
1642 01:23:17.737392
1643 01:23:17.740318 Set Vref, RX VrefLevel [Byte0]: 34
1644 01:23:17.743890 [Byte1]: 34
1645 01:23:17.747045
1646 01:23:17.747350 Set Vref, RX VrefLevel [Byte0]: 35
1647 01:23:17.750333 [Byte1]: 35
1648 01:23:17.754743
1649 01:23:17.754985 Set Vref, RX VrefLevel [Byte0]: 36
1650 01:23:17.758156 [Byte1]: 36
1651 01:23:17.762508
1652 01:23:17.762750 Set Vref, RX VrefLevel [Byte0]: 37
1653 01:23:17.765706 [Byte1]: 37
1654 01:23:17.769782
1655 01:23:17.770031 Set Vref, RX VrefLevel [Byte0]: 38
1656 01:23:17.773083 [Byte1]: 38
1657 01:23:17.777690
1658 01:23:17.778028 Set Vref, RX VrefLevel [Byte0]: 39
1659 01:23:17.780876 [Byte1]: 39
1660 01:23:17.784854
1661 01:23:17.785181 Set Vref, RX VrefLevel [Byte0]: 40
1662 01:23:17.788411 [Byte1]: 40
1663 01:23:17.792645
1664 01:23:17.792893 Set Vref, RX VrefLevel [Byte0]: 41
1665 01:23:17.795589 [Byte1]: 41
1666 01:23:17.799993
1667 01:23:17.800190 Set Vref, RX VrefLevel [Byte0]: 42
1668 01:23:17.803155 [Byte1]: 42
1669 01:23:17.807725
1670 01:23:17.807962 Set Vref, RX VrefLevel [Byte0]: 43
1671 01:23:17.810886 [Byte1]: 43
1672 01:23:17.815182
1673 01:23:17.815424 Set Vref, RX VrefLevel [Byte0]: 44
1674 01:23:17.818104 [Byte1]: 44
1675 01:23:17.822533
1676 01:23:17.822745 Set Vref, RX VrefLevel [Byte0]: 45
1677 01:23:17.825713 [Byte1]: 45
1678 01:23:17.830164
1679 01:23:17.830380 Set Vref, RX VrefLevel [Byte0]: 46
1680 01:23:17.833419 [Byte1]: 46
1681 01:23:17.837815
1682 01:23:17.838063 Set Vref, RX VrefLevel [Byte0]: 47
1683 01:23:17.840903 [Byte1]: 47
1684 01:23:17.845049
1685 01:23:17.845289 Set Vref, RX VrefLevel [Byte0]: 48
1686 01:23:17.848698 [Byte1]: 48
1687 01:23:17.852670
1688 01:23:17.852909 Set Vref, RX VrefLevel [Byte0]: 49
1689 01:23:17.856272 [Byte1]: 49
1690 01:23:17.860147
1691 01:23:17.860336 Set Vref, RX VrefLevel [Byte0]: 50
1692 01:23:17.864040 [Byte1]: 50
1693 01:23:17.868092
1694 01:23:17.868328 Set Vref, RX VrefLevel [Byte0]: 51
1695 01:23:17.871460 [Byte1]: 51
1696 01:23:17.875345
1697 01:23:17.875561 Set Vref, RX VrefLevel [Byte0]: 52
1698 01:23:17.878865 [Byte1]: 52
1699 01:23:17.882858
1700 01:23:17.883030 Set Vref, RX VrefLevel [Byte0]: 53
1701 01:23:17.886278 [Byte1]: 53
1702 01:23:17.890763
1703 01:23:17.890942 Set Vref, RX VrefLevel [Byte0]: 54
1704 01:23:17.893952 [Byte1]: 54
1705 01:23:17.898197
1706 01:23:17.898378 Set Vref, RX VrefLevel [Byte0]: 55
1707 01:23:17.901205 [Byte1]: 55
1708 01:23:17.905374
1709 01:23:17.905539 Set Vref, RX VrefLevel [Byte0]: 56
1710 01:23:17.909015 [Byte1]: 56
1711 01:23:17.912909
1712 01:23:17.913142 Set Vref, RX VrefLevel [Byte0]: 57
1713 01:23:17.916185 [Byte1]: 57
1714 01:23:17.920443
1715 01:23:17.920685 Set Vref, RX VrefLevel [Byte0]: 58
1716 01:23:17.924248 [Byte1]: 58
1717 01:23:17.928321
1718 01:23:17.928585 Set Vref, RX VrefLevel [Byte0]: 59
1719 01:23:17.931409 [Byte1]: 59
1720 01:23:17.935847
1721 01:23:17.936069 Set Vref, RX VrefLevel [Byte0]: 60
1722 01:23:17.939023 [Byte1]: 60
1723 01:23:17.943598
1724 01:23:17.943762 Set Vref, RX VrefLevel [Byte0]: 61
1725 01:23:17.946874 [Byte1]: 61
1726 01:23:17.950765
1727 01:23:17.950977 Set Vref, RX VrefLevel [Byte0]: 62
1728 01:23:17.954010 [Byte1]: 62
1729 01:23:17.958326
1730 01:23:17.958499 Set Vref, RX VrefLevel [Byte0]: 63
1731 01:23:17.961806 [Byte1]: 63
1732 01:23:17.966240
1733 01:23:17.966428 Set Vref, RX VrefLevel [Byte0]: 64
1734 01:23:17.969336 [Byte1]: 64
1735 01:23:17.973436
1736 01:23:17.973605 Set Vref, RX VrefLevel [Byte0]: 65
1737 01:23:17.976832 [Byte1]: 65
1738 01:23:17.981504
1739 01:23:17.981683 Set Vref, RX VrefLevel [Byte0]: 66
1740 01:23:17.984624 [Byte1]: 66
1741 01:23:17.988794
1742 01:23:17.988959 Set Vref, RX VrefLevel [Byte0]: 67
1743 01:23:17.991752 [Byte1]: 67
1744 01:23:17.996172
1745 01:23:17.996339 Set Vref, RX VrefLevel [Byte0]: 68
1746 01:23:17.999114 [Byte1]: 68
1747 01:23:18.003838
1748 01:23:18.003995 Set Vref, RX VrefLevel [Byte0]: 69
1749 01:23:18.007024 [Byte1]: 69
1750 01:23:18.011430
1751 01:23:18.011602 Set Vref, RX VrefLevel [Byte0]: 70
1752 01:23:18.014831 [Byte1]: 70
1753 01:23:18.018953
1754 01:23:18.019164 Set Vref, RX VrefLevel [Byte0]: 71
1755 01:23:18.022150 [Byte1]: 71
1756 01:23:18.026512
1757 01:23:18.026715 Final RX Vref Byte 0 = 57 to rank0
1758 01:23:18.029757 Final RX Vref Byte 1 = 55 to rank0
1759 01:23:18.032872 Final RX Vref Byte 0 = 57 to rank1
1760 01:23:18.036406 Final RX Vref Byte 1 = 55 to rank1==
1761 01:23:18.039617 Dram Type= 6, Freq= 0, CH_1, rank 0
1762 01:23:18.046138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1763 01:23:18.046347 ==
1764 01:23:18.046472 DQS Delay:
1765 01:23:18.046595 DQS0 = 0, DQS1 = 0
1766 01:23:18.049378 DQM Delay:
1767 01:23:18.049537 DQM0 = 94, DQM1 = 90
1768 01:23:18.053186 DQ Delay:
1769 01:23:18.056162 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1770 01:23:18.059595 DQ4 =96, DQ5 =108, DQ6 =100, DQ7 =92
1771 01:23:18.062623 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1772 01:23:18.066295 DQ12 =96, DQ13 =100, DQ14 =96, DQ15 =96
1773 01:23:18.066540
1774 01:23:18.066694
1775 01:23:18.073249 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a46, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1776 01:23:18.076086 CH1 RK0: MR19=606, MR18=2A46
1777 01:23:18.082868 CH1_RK0: MR19=0x606, MR18=0x2A46, DQSOSC=392, MR23=63, INC=96, DEC=64
1778 01:23:18.083054
1779 01:23:18.085998 ----->DramcWriteLeveling(PI) begin...
1780 01:23:18.086139 ==
1781 01:23:18.089785 Dram Type= 6, Freq= 0, CH_1, rank 1
1782 01:23:18.093003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1783 01:23:18.093165 ==
1784 01:23:18.096247 Write leveling (Byte 0): 27 => 27
1785 01:23:18.099496 Write leveling (Byte 1): 29 => 29
1786 01:23:18.103210 DramcWriteLeveling(PI) end<-----
1787 01:23:18.103371
1788 01:23:18.103473 ==
1789 01:23:18.106149 Dram Type= 6, Freq= 0, CH_1, rank 1
1790 01:23:18.109467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 01:23:18.109614 ==
1792 01:23:18.112772 [Gating] SW mode calibration
1793 01:23:18.119580 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1794 01:23:18.126116 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1795 01:23:18.129605 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1796 01:23:18.133140 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1797 01:23:18.140087 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1798 01:23:18.143003 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1799 01:23:18.146629 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 01:23:18.153069 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 01:23:18.156214 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 01:23:18.159300 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 01:23:18.166153 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 01:23:18.169943 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 01:23:18.173080 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 01:23:18.179896 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 01:23:18.182745 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 01:23:18.186053 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 01:23:18.192760 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 01:23:18.196750 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 01:23:18.199930 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 01:23:18.203169 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1813 01:23:18.209909 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1814 01:23:18.212978 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 01:23:18.216656 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 01:23:18.223214 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 01:23:18.226446 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 01:23:18.229677 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 01:23:18.236745 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 01:23:18.239960 0 9 4 | B1->B0 | 2929 2323 | 0 1 | (0 0) (1 1)
1821 01:23:18.243462 0 9 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
1822 01:23:18.249777 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1823 01:23:18.253433 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1824 01:23:18.256563 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 01:23:18.263185 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 01:23:18.266915 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 01:23:18.270018 0 10 0 | B1->B0 | 3232 3434 | 0 1 | (0 1) (1 1)
1828 01:23:18.276810 0 10 4 | B1->B0 | 2828 3232 | 0 1 | (0 0) (1 0)
1829 01:23:18.280074 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1830 01:23:18.283162 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 01:23:18.286875 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 01:23:18.293034 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 01:23:18.296651 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 01:23:18.299748 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 01:23:18.306461 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1836 01:23:18.310166 0 11 4 | B1->B0 | 3a3a 2e2e | 0 1 | (0 0) (0 0)
1837 01:23:18.313533 0 11 8 | B1->B0 | 4646 4343 | 0 1 | (0 0) (0 0)
1838 01:23:18.319979 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1839 01:23:18.323143 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1840 01:23:18.326851 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 01:23:18.333208 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 01:23:18.336686 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 01:23:18.339726 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 01:23:18.346792 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1845 01:23:18.349830 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1846 01:23:18.353753 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1847 01:23:18.359827 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 01:23:18.363131 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 01:23:18.367124 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 01:23:18.369857 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 01:23:18.376875 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 01:23:18.379790 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 01:23:18.383468 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 01:23:18.390782 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 01:23:18.393338 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 01:23:18.396423 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 01:23:18.402959 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 01:23:18.406618 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 01:23:18.409930 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 01:23:18.416492 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1861 01:23:18.416682 Total UI for P1: 0, mck2ui 16
1862 01:23:18.423179 best dqsien dly found for B1: ( 0, 14, 2)
1863 01:23:18.426963 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1864 01:23:18.430329 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 01:23:18.433554 Total UI for P1: 0, mck2ui 16
1866 01:23:18.436925 best dqsien dly found for B0: ( 0, 14, 6)
1867 01:23:18.440129 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1868 01:23:18.443222 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1869 01:23:18.443391
1870 01:23:18.446293 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1871 01:23:18.453560 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1872 01:23:18.453751 [Gating] SW calibration Done
1873 01:23:18.453861 ==
1874 01:23:18.456663 Dram Type= 6, Freq= 0, CH_1, rank 1
1875 01:23:18.463212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1876 01:23:18.463392 ==
1877 01:23:18.463506 RX Vref Scan: 0
1878 01:23:18.463603
1879 01:23:18.466323 RX Vref 0 -> 0, step: 1
1880 01:23:18.466465
1881 01:23:18.470101 RX Delay -130 -> 252, step: 16
1882 01:23:18.473310 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1883 01:23:18.476761 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1884 01:23:18.479920 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1885 01:23:18.486702 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1886 01:23:18.490372 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1887 01:23:18.493231 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1888 01:23:18.497082 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1889 01:23:18.500128 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1890 01:23:18.503229 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1891 01:23:18.509981 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1892 01:23:18.513379 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1893 01:23:18.516717 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1894 01:23:18.519955 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1895 01:23:18.526628 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1896 01:23:18.530577 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1897 01:23:18.533251 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1898 01:23:18.533421 ==
1899 01:23:18.536558 Dram Type= 6, Freq= 0, CH_1, rank 1
1900 01:23:18.539891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1901 01:23:18.540039 ==
1902 01:23:18.543190 DQS Delay:
1903 01:23:18.543349 DQS0 = 0, DQS1 = 0
1904 01:23:18.543449 DQM Delay:
1905 01:23:18.547095 DQM0 = 92, DQM1 = 87
1906 01:23:18.547234 DQ Delay:
1907 01:23:18.550190 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1908 01:23:18.553251 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1909 01:23:18.557100 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1910 01:23:18.560019 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1911 01:23:18.560168
1912 01:23:18.560271
1913 01:23:18.560369 ==
1914 01:23:18.563447 Dram Type= 6, Freq= 0, CH_1, rank 1
1915 01:23:18.570435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1916 01:23:18.570626 ==
1917 01:23:18.570733
1918 01:23:18.570827
1919 01:23:18.570922 TX Vref Scan disable
1920 01:23:18.574213 == TX Byte 0 ==
1921 01:23:18.577532 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1922 01:23:18.580734 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1923 01:23:18.583860 == TX Byte 1 ==
1924 01:23:18.587232 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1925 01:23:18.590703 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1926 01:23:18.593740 ==
1927 01:23:18.597383 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 01:23:18.600632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 01:23:18.600800 ==
1930 01:23:18.612987 TX Vref=22, minBit 1, minWin=26, winSum=443
1931 01:23:18.616137 TX Vref=24, minBit 0, minWin=27, winSum=446
1932 01:23:18.619546 TX Vref=26, minBit 1, minWin=27, winSum=447
1933 01:23:18.623216 TX Vref=28, minBit 2, minWin=27, winSum=448
1934 01:23:18.626195 TX Vref=30, minBit 2, minWin=27, winSum=451
1935 01:23:18.629748 TX Vref=32, minBit 1, minWin=27, winSum=450
1936 01:23:18.636326 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 30
1937 01:23:18.636522
1938 01:23:18.639683 Final TX Range 1 Vref 30
1939 01:23:18.639855
1940 01:23:18.639960 ==
1941 01:23:18.642954 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 01:23:18.646158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 01:23:18.646362 ==
1944 01:23:18.646463
1945 01:23:18.649423
1946 01:23:18.649590 TX Vref Scan disable
1947 01:23:18.652813 == TX Byte 0 ==
1948 01:23:18.656568 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1949 01:23:18.659470 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1950 01:23:18.662756 == TX Byte 1 ==
1951 01:23:18.666571 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1952 01:23:18.669650 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1953 01:23:18.673140
1954 01:23:18.673364 [DATLAT]
1955 01:23:18.673505 Freq=800, CH1 RK1
1956 01:23:18.673635
1957 01:23:18.676541 DATLAT Default: 0xa
1958 01:23:18.676722 0, 0xFFFF, sum = 0
1959 01:23:18.679392 1, 0xFFFF, sum = 0
1960 01:23:18.679624 2, 0xFFFF, sum = 0
1961 01:23:18.683167 3, 0xFFFF, sum = 0
1962 01:23:18.683355 4, 0xFFFF, sum = 0
1963 01:23:18.686477 5, 0xFFFF, sum = 0
1964 01:23:18.689802 6, 0xFFFF, sum = 0
1965 01:23:18.689950 7, 0xFFFF, sum = 0
1966 01:23:18.692975 8, 0xFFFF, sum = 0
1967 01:23:18.693099 9, 0x0, sum = 1
1968 01:23:18.693196 10, 0x0, sum = 2
1969 01:23:18.696162 11, 0x0, sum = 3
1970 01:23:18.696290 12, 0x0, sum = 4
1971 01:23:18.699232 best_step = 10
1972 01:23:18.699347
1973 01:23:18.699449 ==
1974 01:23:18.702800 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 01:23:18.706014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 01:23:18.706156 ==
1977 01:23:18.709210 RX Vref Scan: 0
1978 01:23:18.709331
1979 01:23:18.709428 RX Vref 0 -> 0, step: 1
1980 01:23:18.709522
1981 01:23:18.712529 RX Delay -79 -> 252, step: 8
1982 01:23:18.719569 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1983 01:23:18.723121 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1984 01:23:18.726596 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1985 01:23:18.729691 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1986 01:23:18.732790 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1987 01:23:18.735979 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1988 01:23:18.742871 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1989 01:23:18.746195 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1990 01:23:18.749634 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1991 01:23:18.752807 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1992 01:23:18.756757 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
1993 01:23:18.763383 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
1994 01:23:18.766541 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
1995 01:23:18.769947 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
1996 01:23:18.773233 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
1997 01:23:18.776479 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
1998 01:23:18.776629 ==
1999 01:23:18.779725 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 01:23:18.786283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 01:23:18.786493 ==
2002 01:23:18.786604 DQS Delay:
2003 01:23:18.789719 DQS0 = 0, DQS1 = 0
2004 01:23:18.789883 DQM Delay:
2005 01:23:18.789984 DQM0 = 97, DQM1 = 91
2006 01:23:18.792711 DQ Delay:
2007 01:23:18.796092 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2008 01:23:18.799467 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2009 01:23:18.803372 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =84
2010 01:23:18.806615 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2011 01:23:18.806746
2012 01:23:18.806839
2013 01:23:18.812996 [DQSOSCAuto] RK1, (LSB)MR18= 0x4712, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
2014 01:23:18.816430 CH1 RK1: MR19=606, MR18=4712
2015 01:23:18.823186 CH1_RK1: MR19=0x606, MR18=0x4712, DQSOSC=392, MR23=63, INC=96, DEC=64
2016 01:23:18.826457 [RxdqsGatingPostProcess] freq 800
2017 01:23:18.830012 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2018 01:23:18.833001 Pre-setting of DQS Precalculation
2019 01:23:18.839558 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2020 01:23:18.846110 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2021 01:23:18.853402 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2022 01:23:18.853591
2023 01:23:18.853701
2024 01:23:18.856711 [Calibration Summary] 1600 Mbps
2025 01:23:18.856831 CH 0, Rank 0
2026 01:23:18.859849 SW Impedance : PASS
2027 01:23:18.862844 DUTY Scan : NO K
2028 01:23:18.862972 ZQ Calibration : PASS
2029 01:23:18.866315 Jitter Meter : NO K
2030 01:23:18.870122 CBT Training : PASS
2031 01:23:18.870277 Write leveling : PASS
2032 01:23:18.872814 RX DQS gating : PASS
2033 01:23:18.876968 RX DQ/DQS(RDDQC) : PASS
2034 01:23:18.877115 TX DQ/DQS : PASS
2035 01:23:18.879553 RX DATLAT : PASS
2036 01:23:18.883452 RX DQ/DQS(Engine): PASS
2037 01:23:18.883596 TX OE : NO K
2038 01:23:18.883696 All Pass.
2039 01:23:18.886587
2040 01:23:18.886705 CH 0, Rank 1
2041 01:23:18.889803 SW Impedance : PASS
2042 01:23:18.889927 DUTY Scan : NO K
2043 01:23:18.893108 ZQ Calibration : PASS
2044 01:23:18.893236 Jitter Meter : NO K
2045 01:23:18.896532 CBT Training : PASS
2046 01:23:18.900287 Write leveling : PASS
2047 01:23:18.900427 RX DQS gating : PASS
2048 01:23:18.903338 RX DQ/DQS(RDDQC) : PASS
2049 01:23:18.906671 TX DQ/DQS : PASS
2050 01:23:18.906825 RX DATLAT : PASS
2051 01:23:18.910041 RX DQ/DQS(Engine): PASS
2052 01:23:18.913369 TX OE : NO K
2053 01:23:18.913532 All Pass.
2054 01:23:18.913658
2055 01:23:18.913747 CH 1, Rank 0
2056 01:23:18.916553 SW Impedance : PASS
2057 01:23:18.919806 DUTY Scan : NO K
2058 01:23:18.919944 ZQ Calibration : PASS
2059 01:23:18.923464 Jitter Meter : NO K
2060 01:23:18.926498 CBT Training : PASS
2061 01:23:18.926631 Write leveling : PASS
2062 01:23:18.930179 RX DQS gating : PASS
2063 01:23:18.930320 RX DQ/DQS(RDDQC) : PASS
2064 01:23:18.933228 TX DQ/DQS : PASS
2065 01:23:18.936784 RX DATLAT : PASS
2066 01:23:18.936933 RX DQ/DQS(Engine): PASS
2067 01:23:18.939811 TX OE : NO K
2068 01:23:18.939933 All Pass.
2069 01:23:18.940073
2070 01:23:18.943030 CH 1, Rank 1
2071 01:23:18.943144 SW Impedance : PASS
2072 01:23:18.946228 DUTY Scan : NO K
2073 01:23:18.950205 ZQ Calibration : PASS
2074 01:23:18.950365 Jitter Meter : NO K
2075 01:23:18.953426 CBT Training : PASS
2076 01:23:18.956649 Write leveling : PASS
2077 01:23:18.956781 RX DQS gating : PASS
2078 01:23:18.959802 RX DQ/DQS(RDDQC) : PASS
2079 01:23:18.963096 TX DQ/DQS : PASS
2080 01:23:18.963240 RX DATLAT : PASS
2081 01:23:18.966512 RX DQ/DQS(Engine): PASS
2082 01:23:18.969821 TX OE : NO K
2083 01:23:18.969959 All Pass.
2084 01:23:18.970068
2085 01:23:18.970166 DramC Write-DBI off
2086 01:23:18.973082 PER_BANK_REFRESH: Hybrid Mode
2087 01:23:18.976262 TX_TRACKING: ON
2088 01:23:18.980142 [GetDramInforAfterCalByMRR] Vendor 6.
2089 01:23:18.983353 [GetDramInforAfterCalByMRR] Revision 606.
2090 01:23:18.986400 [GetDramInforAfterCalByMRR] Revision 2 0.
2091 01:23:18.986530 MR0 0x3b3b
2092 01:23:18.990061 MR8 0x5151
2093 01:23:18.993150 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2094 01:23:18.993280
2095 01:23:18.993377 MR0 0x3b3b
2096 01:23:18.993467 MR8 0x5151
2097 01:23:18.996449 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2098 01:23:18.996575
2099 01:23:19.006598 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2100 01:23:19.009889 [FAST_K] Save calibration result to emmc
2101 01:23:19.013299 [FAST_K] Save calibration result to emmc
2102 01:23:19.016840 dram_init: config_dvfs: 1
2103 01:23:19.019837 dramc_set_vcore_voltage set vcore to 662500
2104 01:23:19.023086 Read voltage for 1200, 2
2105 01:23:19.023230 Vio18 = 0
2106 01:23:19.023329 Vcore = 662500
2107 01:23:19.026361 Vdram = 0
2108 01:23:19.026487 Vddq = 0
2109 01:23:19.026584 Vmddr = 0
2110 01:23:19.033367 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2111 01:23:19.036556 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2112 01:23:19.039938 MEM_TYPE=3, freq_sel=15
2113 01:23:19.043478 sv_algorithm_assistance_LP4_1600
2114 01:23:19.046413 ============ PULL DRAM RESETB DOWN ============
2115 01:23:19.049914 ========== PULL DRAM RESETB DOWN end =========
2116 01:23:19.056535 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2117 01:23:19.059751 ===================================
2118 01:23:19.063489 LPDDR4 DRAM CONFIGURATION
2119 01:23:19.066713 ===================================
2120 01:23:19.066864 EX_ROW_EN[0] = 0x0
2121 01:23:19.070000 EX_ROW_EN[1] = 0x0
2122 01:23:19.070130 LP4Y_EN = 0x0
2123 01:23:19.073176 WORK_FSP = 0x0
2124 01:23:19.073321 WL = 0x4
2125 01:23:19.076547 RL = 0x4
2126 01:23:19.076692 BL = 0x2
2127 01:23:19.079755 RPST = 0x0
2128 01:23:19.079885 RD_PRE = 0x0
2129 01:23:19.083426 WR_PRE = 0x1
2130 01:23:19.083563 WR_PST = 0x0
2131 01:23:19.086742 DBI_WR = 0x0
2132 01:23:19.086870 DBI_RD = 0x0
2133 01:23:19.090204 OTF = 0x1
2134 01:23:19.093364 ===================================
2135 01:23:19.096657 ===================================
2136 01:23:19.096796 ANA top config
2137 01:23:19.099972 ===================================
2138 01:23:19.103836 DLL_ASYNC_EN = 0
2139 01:23:19.107075 ALL_SLAVE_EN = 0
2140 01:23:19.110410 NEW_RANK_MODE = 1
2141 01:23:19.110551 DLL_IDLE_MODE = 1
2142 01:23:19.113550 LP45_APHY_COMB_EN = 1
2143 01:23:19.116856 TX_ODT_DIS = 1
2144 01:23:19.120027 NEW_8X_MODE = 1
2145 01:23:19.123553 ===================================
2146 01:23:19.126538 ===================================
2147 01:23:19.130506 data_rate = 2400
2148 01:23:19.130653 CKR = 1
2149 01:23:19.133382 DQ_P2S_RATIO = 8
2150 01:23:19.136855 ===================================
2151 01:23:19.140219 CA_P2S_RATIO = 8
2152 01:23:19.143553 DQ_CA_OPEN = 0
2153 01:23:19.146725 DQ_SEMI_OPEN = 0
2154 01:23:19.146875 CA_SEMI_OPEN = 0
2155 01:23:19.150067 CA_FULL_RATE = 0
2156 01:23:19.153806 DQ_CKDIV4_EN = 0
2157 01:23:19.156696 CA_CKDIV4_EN = 0
2158 01:23:19.160206 CA_PREDIV_EN = 0
2159 01:23:19.163660 PH8_DLY = 17
2160 01:23:19.163817 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2161 01:23:19.167110 DQ_AAMCK_DIV = 4
2162 01:23:19.170154 CA_AAMCK_DIV = 4
2163 01:23:19.173873 CA_ADMCK_DIV = 4
2164 01:23:19.177098 DQ_TRACK_CA_EN = 0
2165 01:23:19.180442 CA_PICK = 1200
2166 01:23:19.183606 CA_MCKIO = 1200
2167 01:23:19.183745 MCKIO_SEMI = 0
2168 01:23:19.186813 PLL_FREQ = 2366
2169 01:23:19.190002 DQ_UI_PI_RATIO = 32
2170 01:23:19.193310 CA_UI_PI_RATIO = 0
2171 01:23:19.197163 ===================================
2172 01:23:19.200403 ===================================
2173 01:23:19.203708 memory_type:LPDDR4
2174 01:23:19.203845 GP_NUM : 10
2175 01:23:19.206810 SRAM_EN : 1
2176 01:23:19.209953 MD32_EN : 0
2177 01:23:19.213305 ===================================
2178 01:23:19.213442 [ANA_INIT] >>>>>>>>>>>>>>
2179 01:23:19.216683 <<<<<< [CONFIGURE PHASE]: ANA_TX
2180 01:23:19.219830 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2181 01:23:19.223114 ===================================
2182 01:23:19.227092 data_rate = 2400,PCW = 0X5b00
2183 01:23:19.230424 ===================================
2184 01:23:19.233122 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2185 01:23:19.240074 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2186 01:23:19.243284 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2187 01:23:19.250393 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2188 01:23:19.253598 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2189 01:23:19.256991 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2190 01:23:19.257162 [ANA_INIT] flow start
2191 01:23:19.259917 [ANA_INIT] PLL >>>>>>>>
2192 01:23:19.263221 [ANA_INIT] PLL <<<<<<<<
2193 01:23:19.263360 [ANA_INIT] MIDPI >>>>>>>>
2194 01:23:19.266716 [ANA_INIT] MIDPI <<<<<<<<
2195 01:23:19.270051 [ANA_INIT] DLL >>>>>>>>
2196 01:23:19.270220 [ANA_INIT] DLL <<<<<<<<
2197 01:23:19.273598 [ANA_INIT] flow end
2198 01:23:19.276762 ============ LP4 DIFF to SE enter ============
2199 01:23:19.283379 ============ LP4 DIFF to SE exit ============
2200 01:23:19.283561 [ANA_INIT] <<<<<<<<<<<<<
2201 01:23:19.286552 [Flow] Enable top DCM control >>>>>
2202 01:23:19.290240 [Flow] Enable top DCM control <<<<<
2203 01:23:19.293493 Enable DLL master slave shuffle
2204 01:23:19.299899 ==============================================================
2205 01:23:19.300078 Gating Mode config
2206 01:23:19.307151 ==============================================================
2207 01:23:19.307329 Config description:
2208 01:23:19.316644 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2209 01:23:19.323268 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2210 01:23:19.330542 SELPH_MODE 0: By rank 1: By Phase
2211 01:23:19.333863 ==============================================================
2212 01:23:19.337162 GAT_TRACK_EN = 1
2213 01:23:19.340369 RX_GATING_MODE = 2
2214 01:23:19.343814 RX_GATING_TRACK_MODE = 2
2215 01:23:19.346993 SELPH_MODE = 1
2216 01:23:19.350026 PICG_EARLY_EN = 1
2217 01:23:19.353837 VALID_LAT_VALUE = 1
2218 01:23:19.360332 ==============================================================
2219 01:23:19.363543 Enter into Gating configuration >>>>
2220 01:23:19.363694 Exit from Gating configuration <<<<
2221 01:23:19.366761 Enter into DVFS_PRE_config >>>>>
2222 01:23:19.380583 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2223 01:23:19.383637 Exit from DVFS_PRE_config <<<<<
2224 01:23:19.387086 Enter into PICG configuration >>>>
2225 01:23:19.387189 Exit from PICG configuration <<<<
2226 01:23:19.390118 [RX_INPUT] configuration >>>>>
2227 01:23:19.393823 [RX_INPUT] configuration <<<<<
2228 01:23:19.400193 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2229 01:23:19.403607 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2230 01:23:19.410093 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2231 01:23:19.417121 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2232 01:23:19.423887 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2233 01:23:19.430484 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2234 01:23:19.433778 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2235 01:23:19.437236 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2236 01:23:19.440526 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2237 01:23:19.446963 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2238 01:23:19.450166 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2239 01:23:19.454065 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2240 01:23:19.457000 ===================================
2241 01:23:19.460534 LPDDR4 DRAM CONFIGURATION
2242 01:23:19.463611 ===================================
2243 01:23:19.466878 EX_ROW_EN[0] = 0x0
2244 01:23:19.466995 EX_ROW_EN[1] = 0x0
2245 01:23:19.470159 LP4Y_EN = 0x0
2246 01:23:19.470289 WORK_FSP = 0x0
2247 01:23:19.473469 WL = 0x4
2248 01:23:19.473567 RL = 0x4
2249 01:23:19.477288 BL = 0x2
2250 01:23:19.477418 RPST = 0x0
2251 01:23:19.480405 RD_PRE = 0x0
2252 01:23:19.480538 WR_PRE = 0x1
2253 01:23:19.483594 WR_PST = 0x0
2254 01:23:19.483693 DBI_WR = 0x0
2255 01:23:19.487213 DBI_RD = 0x0
2256 01:23:19.487373 OTF = 0x1
2257 01:23:19.490497 ===================================
2258 01:23:19.493759 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2259 01:23:19.500869 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2260 01:23:19.504196 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2261 01:23:19.507369 ===================================
2262 01:23:19.510694 LPDDR4 DRAM CONFIGURATION
2263 01:23:19.513948 ===================================
2264 01:23:19.514091 EX_ROW_EN[0] = 0x10
2265 01:23:19.516946 EX_ROW_EN[1] = 0x0
2266 01:23:19.517080 LP4Y_EN = 0x0
2267 01:23:19.520151 WORK_FSP = 0x0
2268 01:23:19.523611 WL = 0x4
2269 01:23:19.523728 RL = 0x4
2270 01:23:19.526984 BL = 0x2
2271 01:23:19.527113 RPST = 0x0
2272 01:23:19.530226 RD_PRE = 0x0
2273 01:23:19.530363 WR_PRE = 0x1
2274 01:23:19.533573 WR_PST = 0x0
2275 01:23:19.533703 DBI_WR = 0x0
2276 01:23:19.537313 DBI_RD = 0x0
2277 01:23:19.537462 OTF = 0x1
2278 01:23:19.540422 ===================================
2279 01:23:19.547364 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2280 01:23:19.547537 ==
2281 01:23:19.550573 Dram Type= 6, Freq= 0, CH_0, rank 0
2282 01:23:19.553761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2283 01:23:19.553895 ==
2284 01:23:19.557065 [Duty_Offset_Calibration]
2285 01:23:19.560261 B0:2 B1:1 CA:1
2286 01:23:19.560397
2287 01:23:19.563577 [DutyScan_Calibration_Flow] k_type=0
2288 01:23:19.571540
2289 01:23:19.571802 ==CLK 0==
2290 01:23:19.574881 Final CLK duty delay cell = 0
2291 01:23:19.578124 [0] MAX Duty = 5218%(X100), DQS PI = 24
2292 01:23:19.581865 [0] MIN Duty = 4844%(X100), DQS PI = 48
2293 01:23:19.582030 [0] AVG Duty = 5031%(X100)
2294 01:23:19.584980
2295 01:23:19.585118 CH0 CLK Duty spec in!! Max-Min= 374%
2296 01:23:19.591972 [DutyScan_Calibration_Flow] ====Done====
2297 01:23:19.592146
2298 01:23:19.595295 [DutyScan_Calibration_Flow] k_type=1
2299 01:23:19.610404
2300 01:23:19.610586 ==DQS 0 ==
2301 01:23:19.613784 Final DQS duty delay cell = -4
2302 01:23:19.617025 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2303 01:23:19.620303 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2304 01:23:19.623699 [-4] AVG Duty = 4937%(X100)
2305 01:23:19.623843
2306 01:23:19.623937 ==DQS 1 ==
2307 01:23:19.626915 Final DQS duty delay cell = 0
2308 01:23:19.630227 [0] MAX Duty = 5187%(X100), DQS PI = 62
2309 01:23:19.633420 [0] MIN Duty = 5031%(X100), DQS PI = 32
2310 01:23:19.636603 [0] AVG Duty = 5109%(X100)
2311 01:23:19.636770
2312 01:23:19.640397 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2313 01:23:19.640532
2314 01:23:19.643859 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2315 01:23:19.646655 [DutyScan_Calibration_Flow] ====Done====
2316 01:23:19.646787
2317 01:23:19.650226 [DutyScan_Calibration_Flow] k_type=3
2318 01:23:19.667170
2319 01:23:19.667371 ==DQM 0 ==
2320 01:23:19.670379 Final DQM duty delay cell = 0
2321 01:23:19.673640 [0] MAX Duty = 5156%(X100), DQS PI = 28
2322 01:23:19.677494 [0] MIN Duty = 4907%(X100), DQS PI = 58
2323 01:23:19.677644 [0] AVG Duty = 5031%(X100)
2324 01:23:19.680340
2325 01:23:19.680467 ==DQM 1 ==
2326 01:23:19.683881 Final DQM duty delay cell = 0
2327 01:23:19.687204 [0] MAX Duty = 5093%(X100), DQS PI = 0
2328 01:23:19.690291 [0] MIN Duty = 5031%(X100), DQS PI = 2
2329 01:23:19.690456 [0] AVG Duty = 5062%(X100)
2330 01:23:19.690557
2331 01:23:19.696965 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2332 01:23:19.697136
2333 01:23:19.700686 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2334 01:23:19.704164 [DutyScan_Calibration_Flow] ====Done====
2335 01:23:19.704274
2336 01:23:19.707321 [DutyScan_Calibration_Flow] k_type=2
2337 01:23:19.723613
2338 01:23:19.723761 ==DQ 0 ==
2339 01:23:19.726755 Final DQ duty delay cell = 0
2340 01:23:19.730058 [0] MAX Duty = 5031%(X100), DQS PI = 26
2341 01:23:19.733938 [0] MIN Duty = 4875%(X100), DQS PI = 62
2342 01:23:19.734103 [0] AVG Duty = 4953%(X100)
2343 01:23:19.734219
2344 01:23:19.737116 ==DQ 1 ==
2345 01:23:19.740546 Final DQ duty delay cell = 0
2346 01:23:19.743726 [0] MAX Duty = 5093%(X100), DQS PI = 26
2347 01:23:19.747011 [0] MIN Duty = 4907%(X100), DQS PI = 36
2348 01:23:19.747161 [0] AVG Duty = 5000%(X100)
2349 01:23:19.747266
2350 01:23:19.750197 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2351 01:23:19.750356
2352 01:23:19.753811 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2353 01:23:19.760218 [DutyScan_Calibration_Flow] ====Done====
2354 01:23:19.760408 ==
2355 01:23:19.763903 Dram Type= 6, Freq= 0, CH_1, rank 0
2356 01:23:19.767086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2357 01:23:19.767240 ==
2358 01:23:19.770194 [Duty_Offset_Calibration]
2359 01:23:19.770356 B0:1 B1:0 CA:0
2360 01:23:19.770457
2361 01:23:19.773646 [DutyScan_Calibration_Flow] k_type=0
2362 01:23:19.783064
2363 01:23:19.783271 ==CLK 0==
2364 01:23:19.786252 Final CLK duty delay cell = -4
2365 01:23:19.789551 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2366 01:23:19.793111 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2367 01:23:19.796669 [-4] AVG Duty = 4937%(X100)
2368 01:23:19.796852
2369 01:23:19.799667 CH1 CLK Duty spec in!! Max-Min= 125%
2370 01:23:19.803225 [DutyScan_Calibration_Flow] ====Done====
2371 01:23:19.803381
2372 01:23:19.806268 [DutyScan_Calibration_Flow] k_type=1
2373 01:23:19.822322
2374 01:23:19.822513 ==DQS 0 ==
2375 01:23:19.825594 Final DQS duty delay cell = 0
2376 01:23:19.829509 [0] MAX Duty = 5094%(X100), DQS PI = 26
2377 01:23:19.832789 [0] MIN Duty = 4875%(X100), DQS PI = 0
2378 01:23:19.832934 [0] AVG Duty = 4984%(X100)
2379 01:23:19.833034
2380 01:23:19.836150 ==DQS 1 ==
2381 01:23:19.839308 Final DQS duty delay cell = 0
2382 01:23:19.842499 [0] MAX Duty = 5187%(X100), DQS PI = 18
2383 01:23:19.845877 [0] MIN Duty = 4969%(X100), DQS PI = 10
2384 01:23:19.846018 [0] AVG Duty = 5078%(X100)
2385 01:23:19.846115
2386 01:23:19.852488 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2387 01:23:19.852663
2388 01:23:19.855707 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2389 01:23:19.859492 [DutyScan_Calibration_Flow] ====Done====
2390 01:23:19.859642
2391 01:23:19.862517 [DutyScan_Calibration_Flow] k_type=3
2392 01:23:19.878883
2393 01:23:19.879079 ==DQM 0 ==
2394 01:23:19.882206 Final DQM duty delay cell = 0
2395 01:23:19.885774 [0] MAX Duty = 5156%(X100), DQS PI = 8
2396 01:23:19.888682 [0] MIN Duty = 5031%(X100), DQS PI = 0
2397 01:23:19.888854 [0] AVG Duty = 5093%(X100)
2398 01:23:19.892099
2399 01:23:19.892234 ==DQM 1 ==
2400 01:23:19.895771 Final DQM duty delay cell = 0
2401 01:23:19.898773 [0] MAX Duty = 5031%(X100), DQS PI = 16
2402 01:23:19.901924 [0] MIN Duty = 4875%(X100), DQS PI = 52
2403 01:23:19.902068 [0] AVG Duty = 4953%(X100)
2404 01:23:19.905550
2405 01:23:19.908969 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2406 01:23:19.909124
2407 01:23:19.912136 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2408 01:23:19.915175 [DutyScan_Calibration_Flow] ====Done====
2409 01:23:19.915315
2410 01:23:19.918972 [DutyScan_Calibration_Flow] k_type=2
2411 01:23:19.934928
2412 01:23:19.935125 ==DQ 0 ==
2413 01:23:19.937872 Final DQ duty delay cell = -4
2414 01:23:19.941304 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2415 01:23:19.944529 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2416 01:23:19.947863 [-4] AVG Duty = 4984%(X100)
2417 01:23:19.948008
2418 01:23:19.948110 ==DQ 1 ==
2419 01:23:19.951206 Final DQ duty delay cell = 0
2420 01:23:19.954529 [0] MAX Duty = 5125%(X100), DQS PI = 20
2421 01:23:19.957780 [0] MIN Duty = 4969%(X100), DQS PI = 12
2422 01:23:19.960999 [0] AVG Duty = 5047%(X100)
2423 01:23:19.961142
2424 01:23:19.964325 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2425 01:23:19.964462
2426 01:23:19.967939 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2427 01:23:19.971067 [DutyScan_Calibration_Flow] ====Done====
2428 01:23:19.974732 nWR fixed to 30
2429 01:23:19.974895 [ModeRegInit_LP4] CH0 RK0
2430 01:23:19.977782 [ModeRegInit_LP4] CH0 RK1
2431 01:23:19.981596 [ModeRegInit_LP4] CH1 RK0
2432 01:23:19.984794 [ModeRegInit_LP4] CH1 RK1
2433 01:23:19.984939 match AC timing 7
2434 01:23:19.991270 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2435 01:23:19.994588 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2436 01:23:19.997617 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2437 01:23:20.004740 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2438 01:23:20.007902 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2439 01:23:20.008052 ==
2440 01:23:20.011097 Dram Type= 6, Freq= 0, CH_0, rank 0
2441 01:23:20.014910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2442 01:23:20.015061 ==
2443 01:23:20.021228 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2444 01:23:20.028121 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2445 01:23:20.035297 [CA 0] Center 39 (8~70) winsize 63
2446 01:23:20.038368 [CA 1] Center 39 (8~70) winsize 63
2447 01:23:20.041944 [CA 2] Center 35 (5~66) winsize 62
2448 01:23:20.044881 [CA 3] Center 34 (4~65) winsize 62
2449 01:23:20.048379 [CA 4] Center 33 (3~64) winsize 62
2450 01:23:20.051725 [CA 5] Center 32 (3~62) winsize 60
2451 01:23:20.051881
2452 01:23:20.054934 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2453 01:23:20.055065
2454 01:23:20.058200 [CATrainingPosCal] consider 1 rank data
2455 01:23:20.061490 u2DelayCellTimex100 = 270/100 ps
2456 01:23:20.064846 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2457 01:23:20.068147 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2458 01:23:20.074718 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2459 01:23:20.078441 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2460 01:23:20.081566 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2461 01:23:20.084756 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2462 01:23:20.084908
2463 01:23:20.088290 CA PerBit enable=1, Macro0, CA PI delay=32
2464 01:23:20.088445
2465 01:23:20.091406 [CBTSetCACLKResult] CA Dly = 32
2466 01:23:20.091543 CS Dly: 6 (0~37)
2467 01:23:20.091646 ==
2468 01:23:20.094746 Dram Type= 6, Freq= 0, CH_0, rank 1
2469 01:23:20.101336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2470 01:23:20.101528 ==
2471 01:23:20.104573 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2472 01:23:20.111203 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2473 01:23:20.120589 [CA 0] Center 38 (8~69) winsize 62
2474 01:23:20.123923 [CA 1] Center 38 (8~69) winsize 62
2475 01:23:20.127661 [CA 2] Center 35 (5~66) winsize 62
2476 01:23:20.130467 [CA 3] Center 34 (4~65) winsize 62
2477 01:23:20.133991 [CA 4] Center 33 (3~64) winsize 62
2478 01:23:20.137103 [CA 5] Center 32 (3~62) winsize 60
2479 01:23:20.137298
2480 01:23:20.140738 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2481 01:23:20.140884
2482 01:23:20.143715 [CATrainingPosCal] consider 2 rank data
2483 01:23:20.147381 u2DelayCellTimex100 = 270/100 ps
2484 01:23:20.150814 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2485 01:23:20.154012 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2486 01:23:20.160709 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2487 01:23:20.163725 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2488 01:23:20.167490 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2489 01:23:20.170749 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2490 01:23:20.170896
2491 01:23:20.173963 CA PerBit enable=1, Macro0, CA PI delay=32
2492 01:23:20.174087
2493 01:23:20.177228 [CBTSetCACLKResult] CA Dly = 32
2494 01:23:20.177368 CS Dly: 6 (0~38)
2495 01:23:20.177467
2496 01:23:20.180581 ----->DramcWriteLeveling(PI) begin...
2497 01:23:20.188882 ==
2498 01:23:20.189077 Dram Type= 6, Freq= 0, CH_0, rank 0
2499 01:23:20.190437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2500 01:23:20.190552 ==
2501 01:23:20.194097 Write leveling (Byte 0): 34 => 34
2502 01:23:20.197224 Write leveling (Byte 1): 28 => 28
2503 01:23:20.200759 DramcWriteLeveling(PI) end<-----
2504 01:23:20.200912
2505 01:23:20.201009 ==
2506 01:23:20.203959 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 01:23:20.207338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 01:23:20.207479 ==
2509 01:23:20.210547 [Gating] SW mode calibration
2510 01:23:20.217656 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2511 01:23:20.220988 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2512 01:23:20.227344 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2513 01:23:20.230596 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
2514 01:23:20.233955 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2515 01:23:20.240935 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2516 01:23:20.243917 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2517 01:23:20.247542 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 01:23:20.253850 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2519 01:23:20.257596 0 15 28 | B1->B0 | 3434 2323 | 0 1 | (0 0) (1 0)
2520 01:23:20.260611 1 0 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
2521 01:23:20.267105 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2522 01:23:20.270426 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 01:23:20.273932 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 01:23:20.280627 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 01:23:20.284131 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 01:23:20.287448 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
2527 01:23:20.293861 1 0 28 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
2528 01:23:20.297087 1 1 0 | B1->B0 | 3333 4646 | 1 0 | (0 0) (0 0)
2529 01:23:20.300359 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2530 01:23:20.307079 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 01:23:20.310550 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 01:23:20.314268 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 01:23:20.317436 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 01:23:20.323952 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 01:23:20.327561 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2536 01:23:20.330465 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2537 01:23:20.337211 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2538 01:23:20.340982 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 01:23:20.344051 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 01:23:20.350528 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 01:23:20.353839 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 01:23:20.357242 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 01:23:20.363689 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 01:23:20.367046 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 01:23:20.370565 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 01:23:20.377076 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 01:23:20.380339 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 01:23:20.383675 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 01:23:20.390769 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 01:23:20.394331 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 01:23:20.397525 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2552 01:23:20.404030 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2553 01:23:20.404214 Total UI for P1: 0, mck2ui 16
2554 01:23:20.407562 best dqsien dly found for B0: ( 1, 3, 28)
2555 01:23:20.414103 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 01:23:20.417281 Total UI for P1: 0, mck2ui 16
2557 01:23:20.420737 best dqsien dly found for B1: ( 1, 4, 0)
2558 01:23:20.424314 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2559 01:23:20.427360 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2560 01:23:20.427523
2561 01:23:20.430712 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2562 01:23:20.434006 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2563 01:23:20.437225 [Gating] SW calibration Done
2564 01:23:20.437371 ==
2565 01:23:20.441130 Dram Type= 6, Freq= 0, CH_0, rank 0
2566 01:23:20.444393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2567 01:23:20.444526 ==
2568 01:23:20.447480 RX Vref Scan: 0
2569 01:23:20.447628
2570 01:23:20.447752 RX Vref 0 -> 0, step: 1
2571 01:23:20.447877
2572 01:23:20.450859 RX Delay -40 -> 252, step: 8
2573 01:23:20.454145 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2574 01:23:20.460645 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2575 01:23:20.464422 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2576 01:23:20.467636 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2577 01:23:20.470868 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2578 01:23:20.474135 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2579 01:23:20.480747 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2580 01:23:20.483808 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2581 01:23:20.487181 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2582 01:23:20.491178 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2583 01:23:20.494295 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2584 01:23:20.500846 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2585 01:23:20.504342 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2586 01:23:20.507273 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2587 01:23:20.510889 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2588 01:23:20.513978 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2589 01:23:20.514126 ==
2590 01:23:20.517663 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 01:23:20.524498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 01:23:20.524683 ==
2593 01:23:20.524786 DQS Delay:
2594 01:23:20.527436 DQS0 = 0, DQS1 = 0
2595 01:23:20.527560 DQM Delay:
2596 01:23:20.530428 DQM0 = 121, DQM1 = 113
2597 01:23:20.530551 DQ Delay:
2598 01:23:20.534203 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2599 01:23:20.537176 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2600 01:23:20.540722 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2601 01:23:20.543999 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2602 01:23:20.544150
2603 01:23:20.544248
2604 01:23:20.544342 ==
2605 01:23:20.547178 Dram Type= 6, Freq= 0, CH_0, rank 0
2606 01:23:20.553713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2607 01:23:20.553890 ==
2608 01:23:20.553993
2609 01:23:20.554089
2610 01:23:20.554182 TX Vref Scan disable
2611 01:23:20.557521 == TX Byte 0 ==
2612 01:23:20.560839 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2613 01:23:20.564185 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2614 01:23:20.567216 == TX Byte 1 ==
2615 01:23:20.570492 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2616 01:23:20.573806 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2617 01:23:20.577776 ==
2618 01:23:20.580986 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 01:23:20.584296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 01:23:20.584441 ==
2621 01:23:20.596075 TX Vref=22, minBit 0, minWin=24, winSum=405
2622 01:23:20.599382 TX Vref=24, minBit 0, minWin=25, winSum=414
2623 01:23:20.602582 TX Vref=26, minBit 3, minWin=25, winSum=419
2624 01:23:20.605708 TX Vref=28, minBit 10, minWin=25, winSum=420
2625 01:23:20.608974 TX Vref=30, minBit 13, minWin=25, winSum=422
2626 01:23:20.615721 TX Vref=32, minBit 5, minWin=25, winSum=422
2627 01:23:20.619267 [TxChooseVref] Worse bit 13, Min win 25, Win sum 422, Final Vref 30
2628 01:23:20.619424
2629 01:23:20.622147 Final TX Range 1 Vref 30
2630 01:23:20.622288
2631 01:23:20.622428 ==
2632 01:23:20.625399 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 01:23:20.629388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 01:23:20.629533 ==
2635 01:23:20.629637
2636 01:23:20.632647
2637 01:23:20.632787 TX Vref Scan disable
2638 01:23:20.635838 == TX Byte 0 ==
2639 01:23:20.639173 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2640 01:23:20.642210 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2641 01:23:20.645920 == TX Byte 1 ==
2642 01:23:20.649317 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2643 01:23:20.652452 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2644 01:23:20.652593
2645 01:23:20.655702 [DATLAT]
2646 01:23:20.655832 Freq=1200, CH0 RK0
2647 01:23:20.655935
2648 01:23:20.659259 DATLAT Default: 0xd
2649 01:23:20.659391 0, 0xFFFF, sum = 0
2650 01:23:20.662342 1, 0xFFFF, sum = 0
2651 01:23:20.662484 2, 0xFFFF, sum = 0
2652 01:23:20.665690 3, 0xFFFF, sum = 0
2653 01:23:20.665820 4, 0xFFFF, sum = 0
2654 01:23:20.668634 5, 0xFFFF, sum = 0
2655 01:23:20.672506 6, 0xFFFF, sum = 0
2656 01:23:20.672668 7, 0xFFFF, sum = 0
2657 01:23:20.675810 8, 0xFFFF, sum = 0
2658 01:23:20.675960 9, 0xFFFF, sum = 0
2659 01:23:20.679118 10, 0xFFFF, sum = 0
2660 01:23:20.679267 11, 0xFFFF, sum = 0
2661 01:23:20.682288 12, 0x0, sum = 1
2662 01:23:20.682460 13, 0x0, sum = 2
2663 01:23:20.685755 14, 0x0, sum = 3
2664 01:23:20.685888 15, 0x0, sum = 4
2665 01:23:20.685987 best_step = 13
2666 01:23:20.686084
2667 01:23:20.688882 ==
2668 01:23:20.692639 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 01:23:20.695229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 01:23:20.695363 ==
2671 01:23:20.695462 RX Vref Scan: 1
2672 01:23:20.695561
2673 01:23:20.699161 Set Vref Range= 32 -> 127
2674 01:23:20.699308
2675 01:23:20.702402 RX Vref 32 -> 127, step: 1
2676 01:23:20.702539
2677 01:23:20.705830 RX Delay -13 -> 252, step: 4
2678 01:23:20.705965
2679 01:23:20.708941 Set Vref, RX VrefLevel [Byte0]: 32
2680 01:23:20.712223 [Byte1]: 32
2681 01:23:20.712436
2682 01:23:20.715345 Set Vref, RX VrefLevel [Byte0]: 33
2683 01:23:20.718506 [Byte1]: 33
2684 01:23:20.722489
2685 01:23:20.722671 Set Vref, RX VrefLevel [Byte0]: 34
2686 01:23:20.725481 [Byte1]: 34
2687 01:23:20.729863
2688 01:23:20.730036 Set Vref, RX VrefLevel [Byte0]: 35
2689 01:23:20.733438 [Byte1]: 35
2690 01:23:20.738029
2691 01:23:20.738205 Set Vref, RX VrefLevel [Byte0]: 36
2692 01:23:20.741380 [Byte1]: 36
2693 01:23:20.745894
2694 01:23:20.746076 Set Vref, RX VrefLevel [Byte0]: 37
2695 01:23:20.749071 [Byte1]: 37
2696 01:23:20.753560
2697 01:23:20.753737 Set Vref, RX VrefLevel [Byte0]: 38
2698 01:23:20.756968 [Byte1]: 38
2699 01:23:20.761616
2700 01:23:20.764950 Set Vref, RX VrefLevel [Byte0]: 39
2701 01:23:20.765128 [Byte1]: 39
2702 01:23:20.769248
2703 01:23:20.769418 Set Vref, RX VrefLevel [Byte0]: 40
2704 01:23:20.772954 [Byte1]: 40
2705 01:23:20.777375
2706 01:23:20.777548 Set Vref, RX VrefLevel [Byte0]: 41
2707 01:23:20.780467 [Byte1]: 41
2708 01:23:20.785428
2709 01:23:20.785591 Set Vref, RX VrefLevel [Byte0]: 42
2710 01:23:20.788552 [Byte1]: 42
2711 01:23:20.793224
2712 01:23:20.793402 Set Vref, RX VrefLevel [Byte0]: 43
2713 01:23:20.796354 [Byte1]: 43
2714 01:23:20.800636
2715 01:23:20.800792 Set Vref, RX VrefLevel [Byte0]: 44
2716 01:23:20.804312 [Byte1]: 44
2717 01:23:20.808561
2718 01:23:20.808713 Set Vref, RX VrefLevel [Byte0]: 45
2719 01:23:20.812222 [Byte1]: 45
2720 01:23:20.816805
2721 01:23:20.816961 Set Vref, RX VrefLevel [Byte0]: 46
2722 01:23:20.820003 [Byte1]: 46
2723 01:23:20.824360
2724 01:23:20.824509 Set Vref, RX VrefLevel [Byte0]: 47
2725 01:23:20.828080 [Byte1]: 47
2726 01:23:20.832596
2727 01:23:20.832749 Set Vref, RX VrefLevel [Byte0]: 48
2728 01:23:20.835778 [Byte1]: 48
2729 01:23:20.840466
2730 01:23:20.840680 Set Vref, RX VrefLevel [Byte0]: 49
2731 01:23:20.843720 [Byte1]: 49
2732 01:23:20.848302
2733 01:23:20.848450 Set Vref, RX VrefLevel [Byte0]: 50
2734 01:23:20.851600 [Byte1]: 50
2735 01:23:20.856062
2736 01:23:20.856214 Set Vref, RX VrefLevel [Byte0]: 51
2737 01:23:20.859235 [Byte1]: 51
2738 01:23:20.863865
2739 01:23:20.864020 Set Vref, RX VrefLevel [Byte0]: 52
2740 01:23:20.867152 [Byte1]: 52
2741 01:23:20.871698
2742 01:23:20.871848 Set Vref, RX VrefLevel [Byte0]: 53
2743 01:23:20.875504 [Byte1]: 53
2744 01:23:20.879950
2745 01:23:20.880102 Set Vref, RX VrefLevel [Byte0]: 54
2746 01:23:20.883162 [Byte1]: 54
2747 01:23:20.887867
2748 01:23:20.888012 Set Vref, RX VrefLevel [Byte0]: 55
2749 01:23:20.891068 [Byte1]: 55
2750 01:23:20.895664
2751 01:23:20.895875 Set Vref, RX VrefLevel [Byte0]: 56
2752 01:23:20.898846 [Byte1]: 56
2753 01:23:20.903905
2754 01:23:20.904058 Set Vref, RX VrefLevel [Byte0]: 57
2755 01:23:20.906571 [Byte1]: 57
2756 01:23:20.911422
2757 01:23:20.911574 Set Vref, RX VrefLevel [Byte0]: 58
2758 01:23:20.915017 [Byte1]: 58
2759 01:23:20.919180
2760 01:23:20.919484 Set Vref, RX VrefLevel [Byte0]: 59
2761 01:23:20.922311 [Byte1]: 59
2762 01:23:20.926939
2763 01:23:20.927095 Set Vref, RX VrefLevel [Byte0]: 60
2764 01:23:20.930543 [Byte1]: 60
2765 01:23:20.935094
2766 01:23:20.935240 Set Vref, RX VrefLevel [Byte0]: 61
2767 01:23:20.938627 [Byte1]: 61
2768 01:23:20.943186
2769 01:23:20.943337 Set Vref, RX VrefLevel [Byte0]: 62
2770 01:23:20.946161 [Byte1]: 62
2771 01:23:20.950586
2772 01:23:20.950741 Set Vref, RX VrefLevel [Byte0]: 63
2773 01:23:20.954208 [Byte1]: 63
2774 01:23:20.958809
2775 01:23:20.958962 Set Vref, RX VrefLevel [Byte0]: 64
2776 01:23:20.961863 [Byte1]: 64
2777 01:23:20.966486
2778 01:23:20.966629 Set Vref, RX VrefLevel [Byte0]: 65
2779 01:23:20.969778 [Byte1]: 65
2780 01:23:20.974363
2781 01:23:20.974515 Set Vref, RX VrefLevel [Byte0]: 66
2782 01:23:20.977699 [Byte1]: 66
2783 01:23:20.982674
2784 01:23:20.982834 Set Vref, RX VrefLevel [Byte0]: 67
2785 01:23:20.985913 [Byte1]: 67
2786 01:23:20.990359
2787 01:23:20.990512 Final RX Vref Byte 0 = 56 to rank0
2788 01:23:20.993523 Final RX Vref Byte 1 = 50 to rank0
2789 01:23:20.996849 Final RX Vref Byte 0 = 56 to rank1
2790 01:23:21.000078 Final RX Vref Byte 1 = 50 to rank1==
2791 01:23:21.003331 Dram Type= 6, Freq= 0, CH_0, rank 0
2792 01:23:21.010559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2793 01:23:21.010744 ==
2794 01:23:21.010851 DQS Delay:
2795 01:23:21.010948 DQS0 = 0, DQS1 = 0
2796 01:23:21.013827 DQM Delay:
2797 01:23:21.013945 DQM0 = 120, DQM1 = 112
2798 01:23:21.017098 DQ Delay:
2799 01:23:21.020345 DQ0 =120, DQ1 =120, DQ2 =120, DQ3 =118
2800 01:23:21.023533 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2801 01:23:21.027105 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =106
2802 01:23:21.030163 DQ12 =120, DQ13 =116, DQ14 =124, DQ15 =122
2803 01:23:21.030313
2804 01:23:21.030416
2805 01:23:21.036739 [DQSOSCAuto] RK0, (LSB)MR18= 0x110a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 403 ps
2806 01:23:21.040639 CH0 RK0: MR19=404, MR18=110A
2807 01:23:21.046881 CH0_RK0: MR19=0x404, MR18=0x110A, DQSOSC=403, MR23=63, INC=40, DEC=26
2808 01:23:21.047070
2809 01:23:21.050596 ----->DramcWriteLeveling(PI) begin...
2810 01:23:21.050740 ==
2811 01:23:21.054159 Dram Type= 6, Freq= 0, CH_0, rank 1
2812 01:23:21.056688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2813 01:23:21.060254 ==
2814 01:23:21.060407 Write leveling (Byte 0): 33 => 33
2815 01:23:21.063699 Write leveling (Byte 1): 28 => 28
2816 01:23:21.067002 DramcWriteLeveling(PI) end<-----
2817 01:23:21.067141
2818 01:23:21.067284 ==
2819 01:23:21.070236 Dram Type= 6, Freq= 0, CH_0, rank 1
2820 01:23:21.076981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2821 01:23:21.077157 ==
2822 01:23:21.077265 [Gating] SW mode calibration
2823 01:23:21.086726 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2824 01:23:21.090452 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2825 01:23:21.093591 0 15 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
2826 01:23:21.100200 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2827 01:23:21.103449 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2828 01:23:21.106780 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2829 01:23:21.113353 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2830 01:23:21.117299 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2831 01:23:21.120390 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2832 01:23:21.126963 0 15 28 | B1->B0 | 3232 2f2f | 1 0 | (1 0) (0 0)
2833 01:23:21.130265 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2834 01:23:21.133960 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2835 01:23:21.140472 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2836 01:23:21.143889 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2837 01:23:21.146929 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2838 01:23:21.153775 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2839 01:23:21.157057 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2840 01:23:21.160334 1 0 28 | B1->B0 | 3939 3a3a | 0 0 | (0 0) (0 0)
2841 01:23:21.163830 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2842 01:23:21.170352 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2843 01:23:21.174344 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2844 01:23:21.177081 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2845 01:23:21.183729 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2846 01:23:21.187088 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2847 01:23:21.190528 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2848 01:23:21.197008 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2849 01:23:21.200715 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2850 01:23:21.203972 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2851 01:23:21.210506 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2852 01:23:21.214443 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2853 01:23:21.217685 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2854 01:23:21.224065 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2855 01:23:21.227460 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2856 01:23:21.230747 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 01:23:21.237255 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 01:23:21.240540 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 01:23:21.244335 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 01:23:21.247350 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 01:23:21.253902 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 01:23:21.257167 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 01:23:21.260869 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 01:23:21.267809 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2865 01:23:21.270954 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 01:23:21.274068 Total UI for P1: 0, mck2ui 16
2867 01:23:21.277834 best dqsien dly found for B0: ( 1, 3, 28)
2868 01:23:21.280775 Total UI for P1: 0, mck2ui 16
2869 01:23:21.284528 best dqsien dly found for B1: ( 1, 3, 28)
2870 01:23:21.287676 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2871 01:23:21.290710 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2872 01:23:21.290844
2873 01:23:21.294525 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2874 01:23:21.297575 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2875 01:23:21.301173 [Gating] SW calibration Done
2876 01:23:21.301311 ==
2877 01:23:21.304444 Dram Type= 6, Freq= 0, CH_0, rank 1
2878 01:23:21.307786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2879 01:23:21.310785 ==
2880 01:23:21.310918 RX Vref Scan: 0
2881 01:23:21.311016
2882 01:23:21.314355 RX Vref 0 -> 0, step: 1
2883 01:23:21.314483
2884 01:23:21.314578 RX Delay -40 -> 252, step: 8
2885 01:23:21.321500 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2886 01:23:21.324798 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2887 01:23:21.328124 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2888 01:23:21.331338 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2889 01:23:21.334582 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2890 01:23:21.341078 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2891 01:23:21.344442 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2892 01:23:21.348212 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2893 01:23:21.351413 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2894 01:23:21.354708 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2895 01:23:21.357935 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2896 01:23:21.364612 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2897 01:23:21.368039 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2898 01:23:21.371419 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2899 01:23:21.374702 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2900 01:23:21.381204 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2901 01:23:21.381384 ==
2902 01:23:21.384722 Dram Type= 6, Freq= 0, CH_0, rank 1
2903 01:23:21.387957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2904 01:23:21.388118 ==
2905 01:23:21.388224 DQS Delay:
2906 01:23:21.391306 DQS0 = 0, DQS1 = 0
2907 01:23:21.391439 DQM Delay:
2908 01:23:21.394827 DQM0 = 122, DQM1 = 112
2909 01:23:21.394958 DQ Delay:
2910 01:23:21.397715 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2911 01:23:21.401574 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2912 01:23:21.404869 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2913 01:23:21.408166 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2914 01:23:21.408311
2915 01:23:21.408413
2916 01:23:21.408508 ==
2917 01:23:21.411285 Dram Type= 6, Freq= 0, CH_0, rank 1
2918 01:23:21.417678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2919 01:23:21.417855 ==
2920 01:23:21.417957
2921 01:23:21.418055
2922 01:23:21.418149 TX Vref Scan disable
2923 01:23:21.421483 == TX Byte 0 ==
2924 01:23:21.425330 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2925 01:23:21.428803 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2926 01:23:21.431876 == TX Byte 1 ==
2927 01:23:21.434954 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2928 01:23:21.438774 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2929 01:23:21.442143 ==
2930 01:23:21.445344 Dram Type= 6, Freq= 0, CH_0, rank 1
2931 01:23:21.448578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2932 01:23:21.448709 ==
2933 01:23:21.460088 TX Vref=22, minBit 2, minWin=25, winSum=415
2934 01:23:21.463420 TX Vref=24, minBit 13, minWin=25, winSum=419
2935 01:23:21.466618 TX Vref=26, minBit 13, minWin=25, winSum=419
2936 01:23:21.469954 TX Vref=28, minBit 1, minWin=26, winSum=422
2937 01:23:21.473234 TX Vref=30, minBit 1, minWin=26, winSum=424
2938 01:23:21.480523 TX Vref=32, minBit 13, minWin=25, winSum=424
2939 01:23:21.483452 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 30
2940 01:23:21.483593
2941 01:23:21.486952 Final TX Range 1 Vref 30
2942 01:23:21.487095
2943 01:23:21.487195 ==
2944 01:23:21.490322 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 01:23:21.493541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 01:23:21.493678 ==
2947 01:23:21.497016
2948 01:23:21.497155
2949 01:23:21.497254 TX Vref Scan disable
2950 01:23:21.499856 == TX Byte 0 ==
2951 01:23:21.503397 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2952 01:23:21.506960 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2953 01:23:21.510026 == TX Byte 1 ==
2954 01:23:21.513566 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2955 01:23:21.516954 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2956 01:23:21.520122
2957 01:23:21.520259 [DATLAT]
2958 01:23:21.520358 Freq=1200, CH0 RK1
2959 01:23:21.520454
2960 01:23:21.523321 DATLAT Default: 0xd
2961 01:23:21.523450 0, 0xFFFF, sum = 0
2962 01:23:21.526946 1, 0xFFFF, sum = 0
2963 01:23:21.527077 2, 0xFFFF, sum = 0
2964 01:23:21.529884 3, 0xFFFF, sum = 0
2965 01:23:21.533430 4, 0xFFFF, sum = 0
2966 01:23:21.533566 5, 0xFFFF, sum = 0
2967 01:23:21.536836 6, 0xFFFF, sum = 0
2968 01:23:21.536964 7, 0xFFFF, sum = 0
2969 01:23:21.540227 8, 0xFFFF, sum = 0
2970 01:23:21.540363 9, 0xFFFF, sum = 0
2971 01:23:21.543144 10, 0xFFFF, sum = 0
2972 01:23:21.543272 11, 0xFFFF, sum = 0
2973 01:23:21.546500 12, 0x0, sum = 1
2974 01:23:21.546627 13, 0x0, sum = 2
2975 01:23:21.549861 14, 0x0, sum = 3
2976 01:23:21.549985 15, 0x0, sum = 4
2977 01:23:21.553078 best_step = 13
2978 01:23:21.553202
2979 01:23:21.553299 ==
2980 01:23:21.556949 Dram Type= 6, Freq= 0, CH_0, rank 1
2981 01:23:21.560091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2982 01:23:21.560227 ==
2983 01:23:21.560328 RX Vref Scan: 0
2984 01:23:21.560423
2985 01:23:21.563413 RX Vref 0 -> 0, step: 1
2986 01:23:21.563532
2987 01:23:21.566695 RX Delay -13 -> 252, step: 4
2988 01:23:21.569995 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
2989 01:23:21.576518 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
2990 01:23:21.579814 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
2991 01:23:21.583097 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
2992 01:23:21.587027 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
2993 01:23:21.590066 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
2994 01:23:21.596366 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
2995 01:23:21.600188 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
2996 01:23:21.603197 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
2997 01:23:21.606963 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
2998 01:23:21.610037 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
2999 01:23:21.616527 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3000 01:23:21.620106 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3001 01:23:21.623663 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3002 01:23:21.626876 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3003 01:23:21.630123 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3004 01:23:21.630262 ==
3005 01:23:21.633242 Dram Type= 6, Freq= 0, CH_0, rank 1
3006 01:23:21.639810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3007 01:23:21.639974 ==
3008 01:23:21.640075 DQS Delay:
3009 01:23:21.643547 DQS0 = 0, DQS1 = 0
3010 01:23:21.643674 DQM Delay:
3011 01:23:21.646870 DQM0 = 120, DQM1 = 110
3012 01:23:21.646998 DQ Delay:
3013 01:23:21.649710 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3014 01:23:21.653364 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3015 01:23:21.656472 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =104
3016 01:23:21.659962 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3017 01:23:21.660112
3018 01:23:21.660214
3019 01:23:21.670438 [DQSOSCAuto] RK1, (LSB)MR18= 0xef0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 404 ps
3020 01:23:21.670626 CH0 RK1: MR19=403, MR18=EF0
3021 01:23:21.676825 CH0_RK1: MR19=0x403, MR18=0xEF0, DQSOSC=404, MR23=63, INC=40, DEC=26
3022 01:23:21.680211 [RxdqsGatingPostProcess] freq 1200
3023 01:23:21.686738 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3024 01:23:21.689920 best DQS0 dly(2T, 0.5T) = (0, 11)
3025 01:23:21.693209 best DQS1 dly(2T, 0.5T) = (0, 12)
3026 01:23:21.696276 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3027 01:23:21.699916 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3028 01:23:21.700062 best DQS0 dly(2T, 0.5T) = (0, 11)
3029 01:23:21.703001 best DQS1 dly(2T, 0.5T) = (0, 11)
3030 01:23:21.706813 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3031 01:23:21.709741 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3032 01:23:21.713126 Pre-setting of DQS Precalculation
3033 01:23:21.720016 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3034 01:23:21.720185 ==
3035 01:23:21.723076 Dram Type= 6, Freq= 0, CH_1, rank 0
3036 01:23:21.726559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3037 01:23:21.726698 ==
3038 01:23:21.733064 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3039 01:23:21.736822 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3040 01:23:21.746422 [CA 0] Center 37 (7~68) winsize 62
3041 01:23:21.749622 [CA 1] Center 37 (7~68) winsize 62
3042 01:23:21.753173 [CA 2] Center 35 (5~65) winsize 61
3043 01:23:21.756191 [CA 3] Center 34 (4~64) winsize 61
3044 01:23:21.759806 [CA 4] Center 34 (4~64) winsize 61
3045 01:23:21.763176 [CA 5] Center 33 (3~63) winsize 61
3046 01:23:21.763318
3047 01:23:21.766419 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3048 01:23:21.766541
3049 01:23:21.769416 [CATrainingPosCal] consider 1 rank data
3050 01:23:21.773160 u2DelayCellTimex100 = 270/100 ps
3051 01:23:21.776170 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3052 01:23:21.779497 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3053 01:23:21.786460 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3054 01:23:21.789583 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3055 01:23:21.792916 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3056 01:23:21.796108 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3057 01:23:21.796244
3058 01:23:21.799390 CA PerBit enable=1, Macro0, CA PI delay=33
3059 01:23:21.799511
3060 01:23:21.803117 [CBTSetCACLKResult] CA Dly = 33
3061 01:23:21.803248 CS Dly: 8 (0~39)
3062 01:23:21.803348 ==
3063 01:23:21.806323 Dram Type= 6, Freq= 0, CH_1, rank 1
3064 01:23:21.813237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3065 01:23:21.813415 ==
3066 01:23:21.816413 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3067 01:23:21.822944 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3068 01:23:21.831799 [CA 0] Center 37 (7~68) winsize 62
3069 01:23:21.835494 [CA 1] Center 37 (7~68) winsize 62
3070 01:23:21.838640 [CA 2] Center 35 (5~65) winsize 61
3071 01:23:21.842617 [CA 3] Center 34 (4~65) winsize 62
3072 01:23:21.845201 [CA 4] Center 34 (4~65) winsize 62
3073 01:23:21.848728 [CA 5] Center 34 (4~64) winsize 61
3074 01:23:21.848870
3075 01:23:21.852163 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3076 01:23:21.852296
3077 01:23:21.855456 [CATrainingPosCal] consider 2 rank data
3078 01:23:21.858709 u2DelayCellTimex100 = 270/100 ps
3079 01:23:21.862371 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3080 01:23:21.865325 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3081 01:23:21.872381 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3082 01:23:21.875602 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3083 01:23:21.878901 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3084 01:23:21.881952 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3085 01:23:21.882092
3086 01:23:21.885598 CA PerBit enable=1, Macro0, CA PI delay=33
3087 01:23:21.885731
3088 01:23:21.888660 [CBTSetCACLKResult] CA Dly = 33
3089 01:23:21.888789 CS Dly: 9 (0~41)
3090 01:23:21.888888
3091 01:23:21.892447 ----->DramcWriteLeveling(PI) begin...
3092 01:23:21.895301 ==
3093 01:23:21.895434 Dram Type= 6, Freq= 0, CH_1, rank 0
3094 01:23:21.901809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3095 01:23:21.901976 ==
3096 01:23:21.905522 Write leveling (Byte 0): 28 => 28
3097 01:23:21.908809 Write leveling (Byte 1): 26 => 26
3098 01:23:21.911827 DramcWriteLeveling(PI) end<-----
3099 01:23:21.911965
3100 01:23:21.912065 ==
3101 01:23:21.915551 Dram Type= 6, Freq= 0, CH_1, rank 0
3102 01:23:21.918684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3103 01:23:21.918816 ==
3104 01:23:21.921827 [Gating] SW mode calibration
3105 01:23:21.929167 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3106 01:23:21.932338 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3107 01:23:21.938862 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3108 01:23:21.942054 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3109 01:23:21.945699 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3110 01:23:21.952208 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3111 01:23:21.955686 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3112 01:23:21.958775 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3113 01:23:21.965306 0 15 24 | B1->B0 | 3131 2c2c | 1 1 | (1 0) (1 0)
3114 01:23:21.968701 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3115 01:23:21.972431 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3116 01:23:21.979105 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3117 01:23:21.982230 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3118 01:23:21.986080 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3119 01:23:21.992473 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3120 01:23:21.995789 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3121 01:23:21.998851 1 0 24 | B1->B0 | 3232 3d3d | 0 0 | (0 0) (0 0)
3122 01:23:22.002071 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3123 01:23:22.009111 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3124 01:23:22.012308 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3125 01:23:22.015351 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3126 01:23:22.022312 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3127 01:23:22.025544 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3128 01:23:22.029309 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3129 01:23:22.035765 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3130 01:23:22.039003 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3131 01:23:22.042225 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3132 01:23:22.048737 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3133 01:23:22.051938 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3134 01:23:22.055575 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3135 01:23:22.062295 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3136 01:23:22.065350 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3137 01:23:22.069084 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3138 01:23:22.075328 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 01:23:22.078421 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 01:23:22.082133 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 01:23:22.089091 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 01:23:22.092329 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 01:23:22.095507 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 01:23:22.101932 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 01:23:22.105265 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3146 01:23:22.109068 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3147 01:23:22.112246 Total UI for P1: 0, mck2ui 16
3148 01:23:22.115213 best dqsien dly found for B0: ( 1, 3, 24)
3149 01:23:22.118617 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 01:23:22.122113 Total UI for P1: 0, mck2ui 16
3151 01:23:22.125227 best dqsien dly found for B1: ( 1, 3, 26)
3152 01:23:22.129263 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3153 01:23:22.132102 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3154 01:23:22.132252
3155 01:23:22.138887 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3156 01:23:22.142134 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3157 01:23:22.142271 [Gating] SW calibration Done
3158 01:23:22.146080 ==
3159 01:23:22.149392 Dram Type= 6, Freq= 0, CH_1, rank 0
3160 01:23:22.152611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3161 01:23:22.152744 ==
3162 01:23:22.152847 RX Vref Scan: 0
3163 01:23:22.152941
3164 01:23:22.155831 RX Vref 0 -> 0, step: 1
3165 01:23:22.155946
3166 01:23:22.159159 RX Delay -40 -> 252, step: 8
3167 01:23:22.162421 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3168 01:23:22.165450 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3169 01:23:22.169330 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3170 01:23:22.175667 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3171 01:23:22.179330 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3172 01:23:22.182419 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3173 01:23:22.185773 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3174 01:23:22.189026 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3175 01:23:22.195858 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3176 01:23:22.198968 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3177 01:23:22.202073 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3178 01:23:22.205958 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3179 01:23:22.209123 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3180 01:23:22.215816 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3181 01:23:22.218989 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3182 01:23:22.222364 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3183 01:23:22.222543 ==
3184 01:23:22.225423 Dram Type= 6, Freq= 0, CH_1, rank 0
3185 01:23:22.228939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3186 01:23:22.232441 ==
3187 01:23:22.232600 DQS Delay:
3188 01:23:22.232705 DQS0 = 0, DQS1 = 0
3189 01:23:22.235518 DQM Delay:
3190 01:23:22.235669 DQM0 = 120, DQM1 = 116
3191 01:23:22.238946 DQ Delay:
3192 01:23:22.242471 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3193 01:23:22.245382 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =123
3194 01:23:22.248774 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =111
3195 01:23:22.252215 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3196 01:23:22.252399
3197 01:23:22.252541
3198 01:23:22.252665 ==
3199 01:23:22.255901 Dram Type= 6, Freq= 0, CH_1, rank 0
3200 01:23:22.259032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3201 01:23:22.259584 ==
3202 01:23:22.259843
3203 01:23:22.260386
3204 01:23:22.262577 TX Vref Scan disable
3205 01:23:22.266049 == TX Byte 0 ==
3206 01:23:22.269160 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3207 01:23:22.272416 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3208 01:23:22.275875 == TX Byte 1 ==
3209 01:23:22.279060 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3210 01:23:22.282395 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3211 01:23:22.282561 ==
3212 01:23:22.285849 Dram Type= 6, Freq= 0, CH_1, rank 0
3213 01:23:22.288810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3214 01:23:22.292368 ==
3215 01:23:22.302449 TX Vref=22, minBit 1, minWin=24, winSum=408
3216 01:23:22.305544 TX Vref=24, minBit 9, minWin=25, winSum=417
3217 01:23:22.309204 TX Vref=26, minBit 12, minWin=25, winSum=420
3218 01:23:22.312742 TX Vref=28, minBit 11, minWin=25, winSum=426
3219 01:23:22.315935 TX Vref=30, minBit 12, minWin=25, winSum=429
3220 01:23:22.322522 TX Vref=32, minBit 9, minWin=25, winSum=432
3221 01:23:22.325858 [TxChooseVref] Worse bit 9, Min win 25, Win sum 432, Final Vref 32
3222 01:23:22.326021
3223 01:23:22.329643 Final TX Range 1 Vref 32
3224 01:23:22.329856
3225 01:23:22.329983 ==
3226 01:23:22.332399 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 01:23:22.335631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 01:23:22.338794 ==
3229 01:23:22.338952
3230 01:23:22.339051
3231 01:23:22.339231 TX Vref Scan disable
3232 01:23:22.342248 == TX Byte 0 ==
3233 01:23:22.345545 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3234 01:23:22.349358 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3235 01:23:22.352076 == TX Byte 1 ==
3236 01:23:22.355489 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3237 01:23:22.359220 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3238 01:23:22.362357
3239 01:23:22.362512 [DATLAT]
3240 01:23:22.362613 Freq=1200, CH1 RK0
3241 01:23:22.362707
3242 01:23:22.365885 DATLAT Default: 0xd
3243 01:23:22.366026 0, 0xFFFF, sum = 0
3244 01:23:22.368836 1, 0xFFFF, sum = 0
3245 01:23:22.368969 2, 0xFFFF, sum = 0
3246 01:23:22.372751 3, 0xFFFF, sum = 0
3247 01:23:22.372894 4, 0xFFFF, sum = 0
3248 01:23:22.375546 5, 0xFFFF, sum = 0
3249 01:23:22.378785 6, 0xFFFF, sum = 0
3250 01:23:22.378937 7, 0xFFFF, sum = 0
3251 01:23:22.382670 8, 0xFFFF, sum = 0
3252 01:23:22.382812 9, 0xFFFF, sum = 0
3253 01:23:22.386008 10, 0xFFFF, sum = 0
3254 01:23:22.386146 11, 0xFFFF, sum = 0
3255 01:23:22.389276 12, 0x0, sum = 1
3256 01:23:22.389480 13, 0x0, sum = 2
3257 01:23:22.392580 14, 0x0, sum = 3
3258 01:23:22.392731 15, 0x0, sum = 4
3259 01:23:22.392836 best_step = 13
3260 01:23:22.392936
3261 01:23:22.395613 ==
3262 01:23:22.399204 Dram Type= 6, Freq= 0, CH_1, rank 0
3263 01:23:22.402205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3264 01:23:22.402363 ==
3265 01:23:22.402468 RX Vref Scan: 1
3266 01:23:22.402564
3267 01:23:22.405779 Set Vref Range= 32 -> 127
3268 01:23:22.405921
3269 01:23:22.409050 RX Vref 32 -> 127, step: 1
3270 01:23:22.409185
3271 01:23:22.412151 RX Delay -5 -> 252, step: 4
3272 01:23:22.412283
3273 01:23:22.415997 Set Vref, RX VrefLevel [Byte0]: 32
3274 01:23:22.418999 [Byte1]: 32
3275 01:23:22.419139
3276 01:23:22.422680 Set Vref, RX VrefLevel [Byte0]: 33
3277 01:23:22.425921 [Byte1]: 33
3278 01:23:22.426074
3279 01:23:22.429124 Set Vref, RX VrefLevel [Byte0]: 34
3280 01:23:22.432341 [Byte1]: 34
3281 01:23:22.436268
3282 01:23:22.436423 Set Vref, RX VrefLevel [Byte0]: 35
3283 01:23:22.439644 [Byte1]: 35
3284 01:23:22.444194
3285 01:23:22.444356 Set Vref, RX VrefLevel [Byte0]: 36
3286 01:23:22.447748 [Byte1]: 36
3287 01:23:22.452092
3288 01:23:22.452258 Set Vref, RX VrefLevel [Byte0]: 37
3289 01:23:22.455419 [Byte1]: 37
3290 01:23:22.459926
3291 01:23:22.460087 Set Vref, RX VrefLevel [Byte0]: 38
3292 01:23:22.463116 [Byte1]: 38
3293 01:23:22.467756
3294 01:23:22.467934 Set Vref, RX VrefLevel [Byte0]: 39
3295 01:23:22.471591 [Byte1]: 39
3296 01:23:22.475871
3297 01:23:22.476042 Set Vref, RX VrefLevel [Byte0]: 40
3298 01:23:22.478825 [Byte1]: 40
3299 01:23:22.483597
3300 01:23:22.483773 Set Vref, RX VrefLevel [Byte0]: 41
3301 01:23:22.486608 [Byte1]: 41
3302 01:23:22.491225
3303 01:23:22.491390 Set Vref, RX VrefLevel [Byte0]: 42
3304 01:23:22.494533 [Byte1]: 42
3305 01:23:22.499390
3306 01:23:22.499553 Set Vref, RX VrefLevel [Byte0]: 43
3307 01:23:22.502351 [Byte1]: 43
3308 01:23:22.507275
3309 01:23:22.507446 Set Vref, RX VrefLevel [Byte0]: 44
3310 01:23:22.510807 [Byte1]: 44
3311 01:23:22.515231
3312 01:23:22.515398 Set Vref, RX VrefLevel [Byte0]: 45
3313 01:23:22.518506 [Byte1]: 45
3314 01:23:22.522915
3315 01:23:22.523085 Set Vref, RX VrefLevel [Byte0]: 46
3316 01:23:22.525980 [Byte1]: 46
3317 01:23:22.530712
3318 01:23:22.530878 Set Vref, RX VrefLevel [Byte0]: 47
3319 01:23:22.533734 [Byte1]: 47
3320 01:23:22.538884
3321 01:23:22.539053 Set Vref, RX VrefLevel [Byte0]: 48
3322 01:23:22.542256 [Byte1]: 48
3323 01:23:22.546298
3324 01:23:22.546459 Set Vref, RX VrefLevel [Byte0]: 49
3325 01:23:22.549464 [Byte1]: 49
3326 01:23:22.554037
3327 01:23:22.554189 Set Vref, RX VrefLevel [Byte0]: 50
3328 01:23:22.557881 [Byte1]: 50
3329 01:23:22.562201
3330 01:23:22.562367 Set Vref, RX VrefLevel [Byte0]: 51
3331 01:23:22.565531 [Byte1]: 51
3332 01:23:22.569956
3333 01:23:22.570114 Set Vref, RX VrefLevel [Byte0]: 52
3334 01:23:22.573283 [Byte1]: 52
3335 01:23:22.577643
3336 01:23:22.577804 Set Vref, RX VrefLevel [Byte0]: 53
3337 01:23:22.580780 [Byte1]: 53
3338 01:23:22.585423
3339 01:23:22.585588 Set Vref, RX VrefLevel [Byte0]: 54
3340 01:23:22.588971 [Byte1]: 54
3341 01:23:22.593334
3342 01:23:22.593500 Set Vref, RX VrefLevel [Byte0]: 55
3343 01:23:22.596565 [Byte1]: 55
3344 01:23:22.601215
3345 01:23:22.601382 Set Vref, RX VrefLevel [Byte0]: 56
3346 01:23:22.607625 [Byte1]: 56
3347 01:23:22.607793
3348 01:23:22.611456 Set Vref, RX VrefLevel [Byte0]: 57
3349 01:23:22.614469 [Byte1]: 57
3350 01:23:22.614613
3351 01:23:22.618063 Set Vref, RX VrefLevel [Byte0]: 58
3352 01:23:22.620872 [Byte1]: 58
3353 01:23:22.624934
3354 01:23:22.625100 Set Vref, RX VrefLevel [Byte0]: 59
3355 01:23:22.628167 [Byte1]: 59
3356 01:23:22.632541
3357 01:23:22.632695 Set Vref, RX VrefLevel [Byte0]: 60
3358 01:23:22.636518 [Byte1]: 60
3359 01:23:22.641089
3360 01:23:22.641250 Set Vref, RX VrefLevel [Byte0]: 61
3361 01:23:22.644063 [Byte1]: 61
3362 01:23:22.648451
3363 01:23:22.648600 Set Vref, RX VrefLevel [Byte0]: 62
3364 01:23:22.651822 [Byte1]: 62
3365 01:23:22.656162
3366 01:23:22.656325 Set Vref, RX VrefLevel [Byte0]: 63
3367 01:23:22.659301 [Byte1]: 63
3368 01:23:22.664246
3369 01:23:22.664412 Set Vref, RX VrefLevel [Byte0]: 64
3370 01:23:22.667264 [Byte1]: 64
3371 01:23:22.671808
3372 01:23:22.672049 Set Vref, RX VrefLevel [Byte0]: 65
3373 01:23:22.675012 [Byte1]: 65
3374 01:23:22.679562
3375 01:23:22.679719 Set Vref, RX VrefLevel [Byte0]: 66
3376 01:23:22.683285 [Byte1]: 66
3377 01:23:22.687613
3378 01:23:22.687774 Set Vref, RX VrefLevel [Byte0]: 67
3379 01:23:22.690966 [Byte1]: 67
3380 01:23:22.695227
3381 01:23:22.695376 Set Vref, RX VrefLevel [Byte0]: 68
3382 01:23:22.699262 [Byte1]: 68
3383 01:23:22.703416
3384 01:23:22.703561 Final RX Vref Byte 0 = 54 to rank0
3385 01:23:22.706600 Final RX Vref Byte 1 = 54 to rank0
3386 01:23:22.709895 Final RX Vref Byte 0 = 54 to rank1
3387 01:23:22.713800 Final RX Vref Byte 1 = 54 to rank1==
3388 01:23:22.717154 Dram Type= 6, Freq= 0, CH_1, rank 0
3389 01:23:22.723446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3390 01:23:22.723631 ==
3391 01:23:22.723734 DQS Delay:
3392 01:23:22.723828 DQS0 = 0, DQS1 = 0
3393 01:23:22.726751 DQM Delay:
3394 01:23:22.726924 DQM0 = 120, DQM1 = 117
3395 01:23:22.729978 DQ Delay:
3396 01:23:22.733777 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3397 01:23:22.736833 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3398 01:23:22.740138 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3399 01:23:22.743303 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3400 01:23:22.743438
3401 01:23:22.743539
3402 01:23:22.750163 [DQSOSCAuto] RK0, (LSB)MR18= 0x12, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3403 01:23:22.753234 CH1 RK0: MR19=404, MR18=12
3404 01:23:22.760284 CH1_RK0: MR19=0x404, MR18=0x12, DQSOSC=403, MR23=63, INC=40, DEC=26
3405 01:23:22.760468
3406 01:23:22.763428 ----->DramcWriteLeveling(PI) begin...
3407 01:23:22.763557 ==
3408 01:23:22.766709 Dram Type= 6, Freq= 0, CH_1, rank 1
3409 01:23:22.770382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3410 01:23:22.770531 ==
3411 01:23:22.773971 Write leveling (Byte 0): 26 => 26
3412 01:23:22.776966 Write leveling (Byte 1): 30 => 30
3413 01:23:22.780106 DramcWriteLeveling(PI) end<-----
3414 01:23:22.780260
3415 01:23:22.780362 ==
3416 01:23:22.783535 Dram Type= 6, Freq= 0, CH_1, rank 1
3417 01:23:22.786602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3418 01:23:22.790488 ==
3419 01:23:22.790638 [Gating] SW mode calibration
3420 01:23:22.797199 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3421 01:23:22.803755 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3422 01:23:22.806985 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3423 01:23:22.813800 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3424 01:23:22.817202 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3425 01:23:22.820450 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3426 01:23:22.827080 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3427 01:23:22.830289 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3428 01:23:22.833542 0 15 24 | B1->B0 | 2727 3333 | 0 0 | (0 0) (0 1)
3429 01:23:22.837175 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3430 01:23:22.843333 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3431 01:23:22.847195 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3432 01:23:22.850511 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3433 01:23:22.857039 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3434 01:23:22.860124 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3435 01:23:22.863927 1 0 20 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
3436 01:23:22.870278 1 0 24 | B1->B0 | 4141 2a2a | 1 0 | (0 0) (0 0)
3437 01:23:22.873948 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3438 01:23:22.876896 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3439 01:23:22.883708 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3440 01:23:22.886502 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3441 01:23:22.890184 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3442 01:23:22.896482 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3443 01:23:22.899652 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3444 01:23:22.903413 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3445 01:23:22.910069 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3446 01:23:22.913255 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3447 01:23:22.916290 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3448 01:23:22.922867 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3449 01:23:22.926128 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3450 01:23:22.929531 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 01:23:22.936654 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 01:23:22.940054 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 01:23:22.943217 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 01:23:22.949693 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 01:23:22.952817 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 01:23:22.956076 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 01:23:22.963387 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 01:23:22.966714 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 01:23:22.969431 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3460 01:23:22.976214 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3461 01:23:22.979442 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3462 01:23:22.983230 Total UI for P1: 0, mck2ui 16
3463 01:23:22.986358 best dqsien dly found for B1: ( 1, 3, 22)
3464 01:23:22.989478 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 01:23:22.993204 Total UI for P1: 0, mck2ui 16
3466 01:23:22.996122 best dqsien dly found for B0: ( 1, 3, 28)
3467 01:23:22.999735 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3468 01:23:23.002486 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3469 01:23:23.002598
3470 01:23:23.005995 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3471 01:23:23.012573 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3472 01:23:23.012710 [Gating] SW calibration Done
3473 01:23:23.012781 ==
3474 01:23:23.015868 Dram Type= 6, Freq= 0, CH_1, rank 1
3475 01:23:23.022967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3476 01:23:23.023098 ==
3477 01:23:23.023176 RX Vref Scan: 0
3478 01:23:23.023266
3479 01:23:23.026202 RX Vref 0 -> 0, step: 1
3480 01:23:23.026292
3481 01:23:23.029521 RX Delay -40 -> 252, step: 8
3482 01:23:23.032351 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3483 01:23:23.035802 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3484 01:23:23.039105 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3485 01:23:23.046189 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3486 01:23:23.049554 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3487 01:23:23.052861 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3488 01:23:23.056129 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3489 01:23:23.059371 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3490 01:23:23.065695 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3491 01:23:23.068889 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3492 01:23:23.072333 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3493 01:23:23.075742 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3494 01:23:23.079234 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3495 01:23:23.085779 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3496 01:23:23.088822 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3497 01:23:23.092512 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3498 01:23:23.092669 ==
3499 01:23:23.095858 Dram Type= 6, Freq= 0, CH_1, rank 1
3500 01:23:23.099095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3501 01:23:23.102332 ==
3502 01:23:23.102478 DQS Delay:
3503 01:23:23.102584 DQS0 = 0, DQS1 = 0
3504 01:23:23.105449 DQM Delay:
3505 01:23:23.105571 DQM0 = 120, DQM1 = 117
3506 01:23:23.108492 DQ Delay:
3507 01:23:23.112055 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3508 01:23:23.115592 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =119
3509 01:23:23.118622 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3510 01:23:23.122029 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3511 01:23:23.122178
3512 01:23:23.122280
3513 01:23:23.122388 ==
3514 01:23:23.125441 Dram Type= 6, Freq= 0, CH_1, rank 1
3515 01:23:23.128732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3516 01:23:23.128877 ==
3517 01:23:23.129020
3518 01:23:23.131755
3519 01:23:23.131886 TX Vref Scan disable
3520 01:23:23.135562 == TX Byte 0 ==
3521 01:23:23.138858 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3522 01:23:23.142279 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3523 01:23:23.145364 == TX Byte 1 ==
3524 01:23:23.148740 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3525 01:23:23.152085 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3526 01:23:23.152224 ==
3527 01:23:23.155420 Dram Type= 6, Freq= 0, CH_1, rank 1
3528 01:23:23.161890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3529 01:23:23.162058 ==
3530 01:23:23.172297 TX Vref=22, minBit 1, minWin=26, winSum=422
3531 01:23:23.176207 TX Vref=24, minBit 1, minWin=26, winSum=426
3532 01:23:23.179474 TX Vref=26, minBit 2, minWin=26, winSum=429
3533 01:23:23.182844 TX Vref=28, minBit 8, minWin=26, winSum=430
3534 01:23:23.185517 TX Vref=30, minBit 1, minWin=26, winSum=435
3535 01:23:23.192298 TX Vref=32, minBit 9, minWin=26, winSum=436
3536 01:23:23.195819 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 32
3537 01:23:23.195964
3538 01:23:23.199086 Final TX Range 1 Vref 32
3539 01:23:23.199223
3540 01:23:23.199322 ==
3541 01:23:23.202511 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 01:23:23.205793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 01:23:23.205954 ==
3544 01:23:23.209106
3545 01:23:23.209243
3546 01:23:23.209346 TX Vref Scan disable
3547 01:23:23.212426 == TX Byte 0 ==
3548 01:23:23.215757 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3549 01:23:23.218908 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3550 01:23:23.222224 == TX Byte 1 ==
3551 01:23:23.225364 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3552 01:23:23.228762 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3553 01:23:23.232127
3554 01:23:23.232283 [DATLAT]
3555 01:23:23.232391 Freq=1200, CH1 RK1
3556 01:23:23.232495
3557 01:23:23.235277 DATLAT Default: 0xd
3558 01:23:23.235395 0, 0xFFFF, sum = 0
3559 01:23:23.239104 1, 0xFFFF, sum = 0
3560 01:23:23.239232 2, 0xFFFF, sum = 0
3561 01:23:23.241963 3, 0xFFFF, sum = 0
3562 01:23:23.245387 4, 0xFFFF, sum = 0
3563 01:23:23.245525 5, 0xFFFF, sum = 0
3564 01:23:23.248700 6, 0xFFFF, sum = 0
3565 01:23:23.248820 7, 0xFFFF, sum = 0
3566 01:23:23.251754 8, 0xFFFF, sum = 0
3567 01:23:23.251891 9, 0xFFFF, sum = 0
3568 01:23:23.255331 10, 0xFFFF, sum = 0
3569 01:23:23.255466 11, 0xFFFF, sum = 0
3570 01:23:23.259047 12, 0x0, sum = 1
3571 01:23:23.259182 13, 0x0, sum = 2
3572 01:23:23.262014 14, 0x0, sum = 3
3573 01:23:23.262142 15, 0x0, sum = 4
3574 01:23:23.262245 best_step = 13
3575 01:23:23.265601
3576 01:23:23.265750 ==
3577 01:23:23.268968 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 01:23:23.272208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 01:23:23.272353 ==
3580 01:23:23.272456 RX Vref Scan: 0
3581 01:23:23.272553
3582 01:23:23.275366 RX Vref 0 -> 0, step: 1
3583 01:23:23.275484
3584 01:23:23.278597 RX Delay -5 -> 252, step: 4
3585 01:23:23.281969 iDelay=195, Bit 0, Center 124 (63 ~ 186) 124
3586 01:23:23.288770 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3587 01:23:23.291935 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3588 01:23:23.295385 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3589 01:23:23.298694 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3590 01:23:23.301946 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3591 01:23:23.305222 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3592 01:23:23.311862 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3593 01:23:23.315329 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3594 01:23:23.318589 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3595 01:23:23.321934 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3596 01:23:23.328366 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3597 01:23:23.331645 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3598 01:23:23.335234 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3599 01:23:23.338450 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3600 01:23:23.341830 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3601 01:23:23.345341 ==
3602 01:23:23.348669 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 01:23:23.351944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 01:23:23.352045 ==
3605 01:23:23.352114 DQS Delay:
3606 01:23:23.355211 DQS0 = 0, DQS1 = 0
3607 01:23:23.355302 DQM Delay:
3608 01:23:23.358441 DQM0 = 120, DQM1 = 118
3609 01:23:23.358573 DQ Delay:
3610 01:23:23.361387 DQ0 =124, DQ1 =116, DQ2 =110, DQ3 =118
3611 01:23:23.365232 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3612 01:23:23.368441 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3613 01:23:23.371728 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3614 01:23:23.371828
3615 01:23:23.371896
3616 01:23:23.381738 [DQSOSCAuto] RK1, (LSB)MR18= 0xeeb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 404 ps
3617 01:23:23.381881 CH1 RK1: MR19=403, MR18=EEB
3618 01:23:23.388377 CH1_RK1: MR19=0x403, MR18=0xEEB, DQSOSC=404, MR23=63, INC=40, DEC=26
3619 01:23:23.391334 [RxdqsGatingPostProcess] freq 1200
3620 01:23:23.398113 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3621 01:23:23.401481 best DQS0 dly(2T, 0.5T) = (0, 11)
3622 01:23:23.404923 best DQS1 dly(2T, 0.5T) = (0, 11)
3623 01:23:23.408176 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3624 01:23:23.411478 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3625 01:23:23.414767 best DQS0 dly(2T, 0.5T) = (0, 11)
3626 01:23:23.417934 best DQS1 dly(2T, 0.5T) = (0, 11)
3627 01:23:23.421159 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3628 01:23:23.424773 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3629 01:23:23.424924 Pre-setting of DQS Precalculation
3630 01:23:23.431156 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3631 01:23:23.437957 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3632 01:23:23.444600 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3633 01:23:23.444747
3634 01:23:23.444816
3635 01:23:23.447894 [Calibration Summary] 2400 Mbps
3636 01:23:23.451219 CH 0, Rank 0
3637 01:23:23.451344 SW Impedance : PASS
3638 01:23:23.454611 DUTY Scan : NO K
3639 01:23:23.457846 ZQ Calibration : PASS
3640 01:23:23.457990 Jitter Meter : NO K
3641 01:23:23.461306 CBT Training : PASS
3642 01:23:23.461432 Write leveling : PASS
3643 01:23:23.464450 RX DQS gating : PASS
3644 01:23:23.467810 RX DQ/DQS(RDDQC) : PASS
3645 01:23:23.467918 TX DQ/DQS : PASS
3646 01:23:23.471173 RX DATLAT : PASS
3647 01:23:23.474565 RX DQ/DQS(Engine): PASS
3648 01:23:23.474679 TX OE : NO K
3649 01:23:23.477863 All Pass.
3650 01:23:23.477990
3651 01:23:23.478092 CH 0, Rank 1
3652 01:23:23.481181 SW Impedance : PASS
3653 01:23:23.481317 DUTY Scan : NO K
3654 01:23:23.484462 ZQ Calibration : PASS
3655 01:23:23.487929 Jitter Meter : NO K
3656 01:23:23.488078 CBT Training : PASS
3657 01:23:23.491104 Write leveling : PASS
3658 01:23:23.494246 RX DQS gating : PASS
3659 01:23:23.494399 RX DQ/DQS(RDDQC) : PASS
3660 01:23:23.497902 TX DQ/DQS : PASS
3661 01:23:23.500935 RX DATLAT : PASS
3662 01:23:23.501084 RX DQ/DQS(Engine): PASS
3663 01:23:23.504400 TX OE : NO K
3664 01:23:23.504530 All Pass.
3665 01:23:23.504634
3666 01:23:23.507500 CH 1, Rank 0
3667 01:23:23.507622 SW Impedance : PASS
3668 01:23:23.510954 DUTY Scan : NO K
3669 01:23:23.514489 ZQ Calibration : PASS
3670 01:23:23.514697 Jitter Meter : NO K
3671 01:23:23.517899 CBT Training : PASS
3672 01:23:23.518089 Write leveling : PASS
3673 01:23:23.521076 RX DQS gating : PASS
3674 01:23:23.524313 RX DQ/DQS(RDDQC) : PASS
3675 01:23:23.524447 TX DQ/DQS : PASS
3676 01:23:23.527767 RX DATLAT : PASS
3677 01:23:23.531109 RX DQ/DQS(Engine): PASS
3678 01:23:23.531249 TX OE : NO K
3679 01:23:23.534273 All Pass.
3680 01:23:23.534407
3681 01:23:23.534514 CH 1, Rank 1
3682 01:23:23.537541 SW Impedance : PASS
3683 01:23:23.537670 DUTY Scan : NO K
3684 01:23:23.540796 ZQ Calibration : PASS
3685 01:23:23.544196 Jitter Meter : NO K
3686 01:23:23.544336 CBT Training : PASS
3687 01:23:23.547461 Write leveling : PASS
3688 01:23:23.550784 RX DQS gating : PASS
3689 01:23:23.550951 RX DQ/DQS(RDDQC) : PASS
3690 01:23:23.553859 TX DQ/DQS : PASS
3691 01:23:23.557323 RX DATLAT : PASS
3692 01:23:23.557530 RX DQ/DQS(Engine): PASS
3693 01:23:23.560503 TX OE : NO K
3694 01:23:23.560670 All Pass.
3695 01:23:23.560778
3696 01:23:23.563968 DramC Write-DBI off
3697 01:23:23.567330 PER_BANK_REFRESH: Hybrid Mode
3698 01:23:23.567473 TX_TRACKING: ON
3699 01:23:23.577219 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3700 01:23:23.580381 [FAST_K] Save calibration result to emmc
3701 01:23:23.583865 dramc_set_vcore_voltage set vcore to 650000
3702 01:23:23.587349 Read voltage for 600, 5
3703 01:23:23.587489 Vio18 = 0
3704 01:23:23.587600 Vcore = 650000
3705 01:23:23.590589 Vdram = 0
3706 01:23:23.590712 Vddq = 0
3707 01:23:23.590818 Vmddr = 0
3708 01:23:23.597139 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3709 01:23:23.600514 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3710 01:23:23.603863 MEM_TYPE=3, freq_sel=19
3711 01:23:23.606681 sv_algorithm_assistance_LP4_1600
3712 01:23:23.610537 ============ PULL DRAM RESETB DOWN ============
3713 01:23:23.613841 ========== PULL DRAM RESETB DOWN end =========
3714 01:23:23.620089 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3715 01:23:23.623642 ===================================
3716 01:23:23.626601 LPDDR4 DRAM CONFIGURATION
3717 01:23:23.630004 ===================================
3718 01:23:23.630158 EX_ROW_EN[0] = 0x0
3719 01:23:23.633590 EX_ROW_EN[1] = 0x0
3720 01:23:23.633728 LP4Y_EN = 0x0
3721 01:23:23.637066 WORK_FSP = 0x0
3722 01:23:23.637193 WL = 0x2
3723 01:23:23.640529 RL = 0x2
3724 01:23:23.640658 BL = 0x2
3725 01:23:23.643205 RPST = 0x0
3726 01:23:23.643325 RD_PRE = 0x0
3727 01:23:23.646679 WR_PRE = 0x1
3728 01:23:23.646801 WR_PST = 0x0
3729 01:23:23.650038 DBI_WR = 0x0
3730 01:23:23.650171 DBI_RD = 0x0
3731 01:23:23.653433 OTF = 0x1
3732 01:23:23.656573 ===================================
3733 01:23:23.659660 ===================================
3734 01:23:23.659796 ANA top config
3735 01:23:23.663245 ===================================
3736 01:23:23.666152 DLL_ASYNC_EN = 0
3737 01:23:23.670156 ALL_SLAVE_EN = 1
3738 01:23:23.672990 NEW_RANK_MODE = 1
3739 01:23:23.673129 DLL_IDLE_MODE = 1
3740 01:23:23.676096 LP45_APHY_COMB_EN = 1
3741 01:23:23.679999 TX_ODT_DIS = 1
3742 01:23:23.683193 NEW_8X_MODE = 1
3743 01:23:23.686532 ===================================
3744 01:23:23.689837 ===================================
3745 01:23:23.692983 data_rate = 1200
3746 01:23:23.696302 CKR = 1
3747 01:23:23.696440 DQ_P2S_RATIO = 8
3748 01:23:23.699612 ===================================
3749 01:23:23.702780 CA_P2S_RATIO = 8
3750 01:23:23.706247 DQ_CA_OPEN = 0
3751 01:23:23.709541 DQ_SEMI_OPEN = 0
3752 01:23:23.712892 CA_SEMI_OPEN = 0
3753 01:23:23.716199 CA_FULL_RATE = 0
3754 01:23:23.716352 DQ_CKDIV4_EN = 1
3755 01:23:23.719923 CA_CKDIV4_EN = 1
3756 01:23:23.722325 CA_PREDIV_EN = 0
3757 01:23:23.726033 PH8_DLY = 0
3758 01:23:23.729266 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3759 01:23:23.732677 DQ_AAMCK_DIV = 4
3760 01:23:23.732821 CA_AAMCK_DIV = 4
3761 01:23:23.735892 CA_ADMCK_DIV = 4
3762 01:23:23.738971 DQ_TRACK_CA_EN = 0
3763 01:23:23.742437 CA_PICK = 600
3764 01:23:23.746105 CA_MCKIO = 600
3765 01:23:23.749167 MCKIO_SEMI = 0
3766 01:23:23.752721 PLL_FREQ = 2288
3767 01:23:23.752871 DQ_UI_PI_RATIO = 32
3768 01:23:23.755561 CA_UI_PI_RATIO = 0
3769 01:23:23.759092 ===================================
3770 01:23:23.762620 ===================================
3771 01:23:23.765966 memory_type:LPDDR4
3772 01:23:23.768771 GP_NUM : 10
3773 01:23:23.768908 SRAM_EN : 1
3774 01:23:23.772140 MD32_EN : 0
3775 01:23:23.775411 ===================================
3776 01:23:23.778897 [ANA_INIT] >>>>>>>>>>>>>>
3777 01:23:23.779042 <<<<<< [CONFIGURE PHASE]: ANA_TX
3778 01:23:23.782570 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3779 01:23:23.785540 ===================================
3780 01:23:23.789058 data_rate = 1200,PCW = 0X5800
3781 01:23:23.792301 ===================================
3782 01:23:23.795315 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3783 01:23:23.802075 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3784 01:23:23.808576 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3785 01:23:23.811856 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3786 01:23:23.815255 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3787 01:23:23.818483 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3788 01:23:23.821907 [ANA_INIT] flow start
3789 01:23:23.822047 [ANA_INIT] PLL >>>>>>>>
3790 01:23:23.825426 [ANA_INIT] PLL <<<<<<<<
3791 01:23:23.828595 [ANA_INIT] MIDPI >>>>>>>>
3792 01:23:23.828738 [ANA_INIT] MIDPI <<<<<<<<
3793 01:23:23.831971 [ANA_INIT] DLL >>>>>>>>
3794 01:23:23.835522 [ANA_INIT] flow end
3795 01:23:23.839038 ============ LP4 DIFF to SE enter ============
3796 01:23:23.841803 ============ LP4 DIFF to SE exit ============
3797 01:23:23.845122 [ANA_INIT] <<<<<<<<<<<<<
3798 01:23:23.848530 [Flow] Enable top DCM control >>>>>
3799 01:23:23.851802 [Flow] Enable top DCM control <<<<<
3800 01:23:23.855310 Enable DLL master slave shuffle
3801 01:23:23.858459 ==============================================================
3802 01:23:23.862182 Gating Mode config
3803 01:23:23.868628 ==============================================================
3804 01:23:23.868793 Config description:
3805 01:23:23.878055 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3806 01:23:23.885126 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3807 01:23:23.892314 SELPH_MODE 0: By rank 1: By Phase
3808 01:23:23.894701 ==============================================================
3809 01:23:23.898201 GAT_TRACK_EN = 1
3810 01:23:23.901700 RX_GATING_MODE = 2
3811 01:23:23.905215 RX_GATING_TRACK_MODE = 2
3812 01:23:23.908466 SELPH_MODE = 1
3813 01:23:23.911755 PICG_EARLY_EN = 1
3814 01:23:23.915081 VALID_LAT_VALUE = 1
3815 01:23:23.917984 ==============================================================
3816 01:23:23.921432 Enter into Gating configuration >>>>
3817 01:23:23.924696 Exit from Gating configuration <<<<
3818 01:23:23.928310 Enter into DVFS_PRE_config >>>>>
3819 01:23:23.941556 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3820 01:23:23.944989 Exit from DVFS_PRE_config <<<<<
3821 01:23:23.948295 Enter into PICG configuration >>>>
3822 01:23:23.948445 Exit from PICG configuration <<<<
3823 01:23:23.951221 [RX_INPUT] configuration >>>>>
3824 01:23:23.954550 [RX_INPUT] configuration <<<<<
3825 01:23:23.961381 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3826 01:23:23.964597 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3827 01:23:23.971493 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3828 01:23:23.978145 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3829 01:23:23.984470 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3830 01:23:23.991122 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3831 01:23:23.994476 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3832 01:23:23.997829 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3833 01:23:24.001223 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3834 01:23:24.007411 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3835 01:23:24.010908 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3836 01:23:24.014214 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3837 01:23:24.017523 ===================================
3838 01:23:24.020809 LPDDR4 DRAM CONFIGURATION
3839 01:23:24.024123 ===================================
3840 01:23:24.027836 EX_ROW_EN[0] = 0x0
3841 01:23:24.027984 EX_ROW_EN[1] = 0x0
3842 01:23:24.030901 LP4Y_EN = 0x0
3843 01:23:24.031022 WORK_FSP = 0x0
3844 01:23:24.034402 WL = 0x2
3845 01:23:24.034533 RL = 0x2
3846 01:23:24.037497 BL = 0x2
3847 01:23:24.037620 RPST = 0x0
3848 01:23:24.040709 RD_PRE = 0x0
3849 01:23:24.040829 WR_PRE = 0x1
3850 01:23:24.044613 WR_PST = 0x0
3851 01:23:24.044738 DBI_WR = 0x0
3852 01:23:24.047579 DBI_RD = 0x0
3853 01:23:24.047704 OTF = 0x1
3854 01:23:24.051130 ===================================
3855 01:23:24.057747 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3856 01:23:24.060916 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3857 01:23:24.064035 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3858 01:23:24.067760 ===================================
3859 01:23:24.070902 LPDDR4 DRAM CONFIGURATION
3860 01:23:24.074258 ===================================
3861 01:23:24.077368 EX_ROW_EN[0] = 0x10
3862 01:23:24.077492 EX_ROW_EN[1] = 0x0
3863 01:23:24.081079 LP4Y_EN = 0x0
3864 01:23:24.081214 WORK_FSP = 0x0
3865 01:23:24.084292 WL = 0x2
3866 01:23:24.084411 RL = 0x2
3867 01:23:24.087454 BL = 0x2
3868 01:23:24.087571 RPST = 0x0
3869 01:23:24.090464 RD_PRE = 0x0
3870 01:23:24.090583 WR_PRE = 0x1
3871 01:23:24.093922 WR_PST = 0x0
3872 01:23:24.094049 DBI_WR = 0x0
3873 01:23:24.097069 DBI_RD = 0x0
3874 01:23:24.097187 OTF = 0x1
3875 01:23:24.100598 ===================================
3876 01:23:24.107190 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3877 01:23:24.111871 nWR fixed to 30
3878 01:23:24.115277 [ModeRegInit_LP4] CH0 RK0
3879 01:23:24.115423 [ModeRegInit_LP4] CH0 RK1
3880 01:23:24.118526 [ModeRegInit_LP4] CH1 RK0
3881 01:23:24.121752 [ModeRegInit_LP4] CH1 RK1
3882 01:23:24.121884 match AC timing 17
3883 01:23:24.128307 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3884 01:23:24.131597 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3885 01:23:24.134804 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3886 01:23:24.141506 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3887 01:23:24.145001 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3888 01:23:24.145154 ==
3889 01:23:24.148248 Dram Type= 6, Freq= 0, CH_0, rank 0
3890 01:23:24.151776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3891 01:23:24.151914 ==
3892 01:23:24.157820 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3893 01:23:24.164667 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3894 01:23:24.167966 [CA 0] Center 35 (5~66) winsize 62
3895 01:23:24.171486 [CA 1] Center 35 (5~66) winsize 62
3896 01:23:24.175364 [CA 2] Center 34 (3~65) winsize 63
3897 01:23:24.178257 [CA 3] Center 33 (2~64) winsize 63
3898 01:23:24.181583 [CA 4] Center 33 (2~64) winsize 63
3899 01:23:24.185119 [CA 5] Center 32 (2~63) winsize 62
3900 01:23:24.185269
3901 01:23:24.188043 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3902 01:23:24.188169
3903 01:23:24.191406 [CATrainingPosCal] consider 1 rank data
3904 01:23:24.194838 u2DelayCellTimex100 = 270/100 ps
3905 01:23:24.198153 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3906 01:23:24.201538 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3907 01:23:24.204638 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3908 01:23:24.208310 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3909 01:23:24.211140 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3910 01:23:24.217601 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3911 01:23:24.217763
3912 01:23:24.221070 CA PerBit enable=1, Macro0, CA PI delay=32
3913 01:23:24.221195
3914 01:23:24.224424 [CBTSetCACLKResult] CA Dly = 32
3915 01:23:24.224548 CS Dly: 4 (0~35)
3916 01:23:24.224640 ==
3917 01:23:24.227745 Dram Type= 6, Freq= 0, CH_0, rank 1
3918 01:23:24.231056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3919 01:23:24.234333 ==
3920 01:23:24.237555 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3921 01:23:24.244728 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3922 01:23:24.248184 [CA 0] Center 35 (5~66) winsize 62
3923 01:23:24.250797 [CA 1] Center 35 (5~66) winsize 62
3924 01:23:24.254214 [CA 2] Center 33 (3~64) winsize 62
3925 01:23:24.257593 [CA 3] Center 33 (3~64) winsize 62
3926 01:23:24.260918 [CA 4] Center 33 (2~64) winsize 63
3927 01:23:24.264356 [CA 5] Center 32 (2~63) winsize 62
3928 01:23:24.264494
3929 01:23:24.267809 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3930 01:23:24.267946
3931 01:23:24.271129 [CATrainingPosCal] consider 2 rank data
3932 01:23:24.274565 u2DelayCellTimex100 = 270/100 ps
3933 01:23:24.277378 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3934 01:23:24.280795 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3935 01:23:24.284086 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3936 01:23:24.290745 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3937 01:23:24.294481 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3938 01:23:24.297355 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3939 01:23:24.297498
3940 01:23:24.300820 CA PerBit enable=1, Macro0, CA PI delay=32
3941 01:23:24.300954
3942 01:23:24.304308 [CBTSetCACLKResult] CA Dly = 32
3943 01:23:24.304441 CS Dly: 4 (0~35)
3944 01:23:24.304551
3945 01:23:24.307345 ----->DramcWriteLeveling(PI) begin...
3946 01:23:24.307471 ==
3947 01:23:24.310867 Dram Type= 6, Freq= 0, CH_0, rank 0
3948 01:23:24.317471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3949 01:23:24.317635 ==
3950 01:23:24.320560 Write leveling (Byte 0): 33 => 33
3951 01:23:24.324174 Write leveling (Byte 1): 32 => 32
3952 01:23:24.324320 DramcWriteLeveling(PI) end<-----
3953 01:23:24.327449
3954 01:23:24.327593 ==
3955 01:23:24.330707 Dram Type= 6, Freq= 0, CH_0, rank 0
3956 01:23:24.333937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3957 01:23:24.334075 ==
3958 01:23:24.337227 [Gating] SW mode calibration
3959 01:23:24.343665 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3960 01:23:24.347166 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3961 01:23:24.353900 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3962 01:23:24.357331 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3963 01:23:24.360735 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3964 01:23:24.366912 0 9 12 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 1)
3965 01:23:24.370256 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
3966 01:23:24.373636 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3967 01:23:24.380874 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3968 01:23:24.384186 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3969 01:23:24.387002 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3970 01:23:24.393578 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3971 01:23:24.397136 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 01:23:24.400439 0 10 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (1 1)
3973 01:23:24.406942 0 10 16 | B1->B0 | 3333 4646 | 1 0 | (1 1) (0 0)
3974 01:23:24.410184 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3975 01:23:24.413870 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3976 01:23:24.420560 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3977 01:23:24.423407 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3978 01:23:24.427143 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 01:23:24.433656 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 01:23:24.436749 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3981 01:23:24.440310 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3982 01:23:24.446615 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3983 01:23:24.450489 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 01:23:24.453687 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 01:23:24.456894 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 01:23:24.463792 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 01:23:24.467131 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 01:23:24.470554 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 01:23:24.476544 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 01:23:24.480055 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 01:23:24.483515 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 01:23:24.490293 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 01:23:24.493546 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 01:23:24.496736 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 01:23:24.503356 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 01:23:24.506807 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3997 01:23:24.510156 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3998 01:23:24.513578 Total UI for P1: 0, mck2ui 16
3999 01:23:24.516838 best dqsien dly found for B0: ( 0, 13, 12)
4000 01:23:24.523311 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 01:23:24.523535 Total UI for P1: 0, mck2ui 16
4002 01:23:24.529811 best dqsien dly found for B1: ( 0, 13, 16)
4003 01:23:24.533375 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4004 01:23:24.536373 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4005 01:23:24.536569
4006 01:23:24.540116 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4007 01:23:24.543173 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4008 01:23:24.546958 [Gating] SW calibration Done
4009 01:23:24.547156 ==
4010 01:23:24.550269 Dram Type= 6, Freq= 0, CH_0, rank 0
4011 01:23:24.553263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4012 01:23:24.553438 ==
4013 01:23:24.556703 RX Vref Scan: 0
4014 01:23:24.556851
4015 01:23:24.556982 RX Vref 0 -> 0, step: 1
4016 01:23:24.557106
4017 01:23:24.559894 RX Delay -230 -> 252, step: 16
4018 01:23:24.566519 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4019 01:23:24.569883 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4020 01:23:24.573001 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4021 01:23:24.576458 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4022 01:23:24.579472 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4023 01:23:24.586137 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4024 01:23:24.589550 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4025 01:23:24.592876 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4026 01:23:24.596146 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4027 01:23:24.599451 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4028 01:23:24.606163 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4029 01:23:24.609476 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4030 01:23:24.612681 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4031 01:23:24.616049 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4032 01:23:24.622908 iDelay=218, Bit 14, Center 65 (-86 ~ 217) 304
4033 01:23:24.626476 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4034 01:23:24.626623 ==
4035 01:23:24.629772 Dram Type= 6, Freq= 0, CH_0, rank 0
4036 01:23:24.633085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4037 01:23:24.633245 ==
4038 01:23:24.636291 DQS Delay:
4039 01:23:24.636437 DQS0 = 0, DQS1 = 0
4040 01:23:24.639426 DQM Delay:
4041 01:23:24.639564 DQM0 = 53, DQM1 = 47
4042 01:23:24.639688 DQ Delay:
4043 01:23:24.642991 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4044 01:23:24.645897 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4045 01:23:24.649614 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4046 01:23:24.652514 DQ12 =49, DQ13 =49, DQ14 =65, DQ15 =57
4047 01:23:24.652657
4048 01:23:24.652778
4049 01:23:24.652899 ==
4050 01:23:24.656004 Dram Type= 6, Freq= 0, CH_0, rank 0
4051 01:23:24.662436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4052 01:23:24.662627 ==
4053 01:23:24.662767
4054 01:23:24.662896
4055 01:23:24.663024 TX Vref Scan disable
4056 01:23:24.666425 == TX Byte 0 ==
4057 01:23:24.669677 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4058 01:23:24.676182 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4059 01:23:24.676360 == TX Byte 1 ==
4060 01:23:24.679781 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4061 01:23:24.686046 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4062 01:23:24.686223 ==
4063 01:23:24.689951 Dram Type= 6, Freq= 0, CH_0, rank 0
4064 01:23:24.693226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4065 01:23:24.693384 ==
4066 01:23:24.693509
4067 01:23:24.693628
4068 01:23:24.696643 TX Vref Scan disable
4069 01:23:24.699898 == TX Byte 0 ==
4070 01:23:24.703114 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4071 01:23:24.706530 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4072 01:23:24.709823 == TX Byte 1 ==
4073 01:23:24.712968 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4074 01:23:24.716294 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4075 01:23:24.716448
4076 01:23:24.716575 [DATLAT]
4077 01:23:24.719754 Freq=600, CH0 RK0
4078 01:23:24.719892
4079 01:23:24.720016 DATLAT Default: 0x9
4080 01:23:24.723055 0, 0xFFFF, sum = 0
4081 01:23:24.726434 1, 0xFFFF, sum = 0
4082 01:23:24.726575 2, 0xFFFF, sum = 0
4083 01:23:24.729142 3, 0xFFFF, sum = 0
4084 01:23:24.729295 4, 0xFFFF, sum = 0
4085 01:23:24.732924 5, 0xFFFF, sum = 0
4086 01:23:24.733070 6, 0xFFFF, sum = 0
4087 01:23:24.736209 7, 0xFFFF, sum = 0
4088 01:23:24.736351 8, 0x0, sum = 1
4089 01:23:24.739639 9, 0x0, sum = 2
4090 01:23:24.739777 10, 0x0, sum = 3
4091 01:23:24.739903 11, 0x0, sum = 4
4092 01:23:24.742916 best_step = 9
4093 01:23:24.743060
4094 01:23:24.743184 ==
4095 01:23:24.745919 Dram Type= 6, Freq= 0, CH_0, rank 0
4096 01:23:24.749106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4097 01:23:24.749253 ==
4098 01:23:24.752374 RX Vref Scan: 1
4099 01:23:24.752543
4100 01:23:24.752670 RX Vref 0 -> 0, step: 1
4101 01:23:24.756261
4102 01:23:24.756482 RX Delay -163 -> 252, step: 8
4103 01:23:24.756610
4104 01:23:24.759466 Set Vref, RX VrefLevel [Byte0]: 56
4105 01:23:24.762459 [Byte1]: 50
4106 01:23:24.767201
4107 01:23:24.767363 Final RX Vref Byte 0 = 56 to rank0
4108 01:23:24.770159 Final RX Vref Byte 1 = 50 to rank0
4109 01:23:24.774135 Final RX Vref Byte 0 = 56 to rank1
4110 01:23:24.777113 Final RX Vref Byte 1 = 50 to rank1==
4111 01:23:24.780258 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 01:23:24.786687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 01:23:24.786842 ==
4114 01:23:24.786943 DQS Delay:
4115 01:23:24.787032 DQS0 = 0, DQS1 = 0
4116 01:23:24.789985 DQM Delay:
4117 01:23:24.790097 DQM0 = 53, DQM1 = 46
4118 01:23:24.793380 DQ Delay:
4119 01:23:24.796951 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4120 01:23:24.800269 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4121 01:23:24.800392 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4122 01:23:24.806737 DQ12 =56, DQ13 =48, DQ14 =56, DQ15 =52
4123 01:23:24.806903
4124 01:23:24.807029
4125 01:23:24.813409 [DQSOSCAuto] RK0, (LSB)MR18= 0x6c60, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4126 01:23:24.816749 CH0 RK0: MR19=808, MR18=6C60
4127 01:23:24.823503 CH0_RK0: MR19=0x808, MR18=0x6C60, DQSOSC=389, MR23=63, INC=173, DEC=115
4128 01:23:24.823674
4129 01:23:24.826813 ----->DramcWriteLeveling(PI) begin...
4130 01:23:24.826954 ==
4131 01:23:24.830250 Dram Type= 6, Freq= 0, CH_0, rank 1
4132 01:23:24.832839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 01:23:24.832989 ==
4134 01:23:24.836176 Write leveling (Byte 0): 33 => 33
4135 01:23:24.840038 Write leveling (Byte 1): 33 => 33
4136 01:23:24.842737 DramcWriteLeveling(PI) end<-----
4137 01:23:24.842899
4138 01:23:24.843007 ==
4139 01:23:24.846121 Dram Type= 6, Freq= 0, CH_0, rank 1
4140 01:23:24.849463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 01:23:24.852820 ==
4142 01:23:24.852984 [Gating] SW mode calibration
4143 01:23:24.859275 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4144 01:23:24.865960 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4145 01:23:24.869322 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4146 01:23:24.876100 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4147 01:23:24.878958 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4148 01:23:24.882547 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (1 1)
4149 01:23:24.889217 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
4150 01:23:24.892628 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4151 01:23:24.895462 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4152 01:23:24.902094 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4153 01:23:24.905644 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4154 01:23:24.908768 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4155 01:23:24.915636 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4156 01:23:24.918835 0 10 12 | B1->B0 | 2626 2626 | 1 0 | (0 0) (0 0)
4157 01:23:24.922115 0 10 16 | B1->B0 | 4040 4545 | 0 0 | (1 1) (1 1)
4158 01:23:24.929241 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4159 01:23:24.932594 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4160 01:23:24.935816 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4161 01:23:24.941910 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4162 01:23:24.945084 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4163 01:23:24.948409 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4164 01:23:24.955099 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4165 01:23:24.958378 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4166 01:23:24.961792 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4167 01:23:24.968510 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4168 01:23:24.971764 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 01:23:24.975286 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 01:23:24.981791 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 01:23:24.984930 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 01:23:24.988876 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 01:23:24.995037 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 01:23:24.998253 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 01:23:25.001961 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 01:23:25.005035 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 01:23:25.011893 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 01:23:25.014983 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 01:23:25.018167 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 01:23:25.025255 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 01:23:25.028630 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 01:23:25.031787 Total UI for P1: 0, mck2ui 16
4183 01:23:25.034854 best dqsien dly found for B0: ( 0, 13, 14)
4184 01:23:25.038287 Total UI for P1: 0, mck2ui 16
4185 01:23:25.041527 best dqsien dly found for B1: ( 0, 13, 14)
4186 01:23:25.044954 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4187 01:23:25.048175 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4188 01:23:25.048326
4189 01:23:25.051320 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4190 01:23:25.058362 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4191 01:23:25.058558 [Gating] SW calibration Done
4192 01:23:25.058668 ==
4193 01:23:25.061651 Dram Type= 6, Freq= 0, CH_0, rank 1
4194 01:23:25.068224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4195 01:23:25.068414 ==
4196 01:23:25.068526 RX Vref Scan: 0
4197 01:23:25.068629
4198 01:23:25.071217 RX Vref 0 -> 0, step: 1
4199 01:23:25.071347
4200 01:23:25.074271 RX Delay -230 -> 252, step: 16
4201 01:23:25.077619 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4202 01:23:25.081130 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4203 01:23:25.088018 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4204 01:23:25.091144 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4205 01:23:25.094405 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4206 01:23:25.097591 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4207 01:23:25.101256 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4208 01:23:25.107638 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4209 01:23:25.111036 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4210 01:23:25.114290 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4211 01:23:25.117515 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4212 01:23:25.124015 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4213 01:23:25.127422 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4214 01:23:25.130749 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4215 01:23:25.134417 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4216 01:23:25.140623 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4217 01:23:25.140833 ==
4218 01:23:25.144089 Dram Type= 6, Freq= 0, CH_0, rank 1
4219 01:23:25.147405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4220 01:23:25.147563 ==
4221 01:23:25.147681 DQS Delay:
4222 01:23:25.150916 DQS0 = 0, DQS1 = 0
4223 01:23:25.151078 DQM Delay:
4224 01:23:25.154265 DQM0 = 54, DQM1 = 44
4225 01:23:25.154432 DQ Delay:
4226 01:23:25.157483 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4227 01:23:25.160748 DQ4 =57, DQ5 =49, DQ6 =65, DQ7 =65
4228 01:23:25.164160 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4229 01:23:25.167581 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4230 01:23:25.167762
4231 01:23:25.167878
4232 01:23:25.167984 ==
4233 01:23:25.170836 Dram Type= 6, Freq= 0, CH_0, rank 1
4234 01:23:25.173529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 01:23:25.173691 ==
4236 01:23:25.173808
4237 01:23:25.177323
4238 01:23:25.177492 TX Vref Scan disable
4239 01:23:25.180178 == TX Byte 0 ==
4240 01:23:25.183916 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4241 01:23:25.186762 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4242 01:23:25.190167 == TX Byte 1 ==
4243 01:23:25.193589 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4244 01:23:25.197325 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4245 01:23:25.197513 ==
4246 01:23:25.200677 Dram Type= 6, Freq= 0, CH_0, rank 1
4247 01:23:25.206642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4248 01:23:25.206832 ==
4249 01:23:25.206946
4250 01:23:25.207055
4251 01:23:25.207159 TX Vref Scan disable
4252 01:23:25.211998 == TX Byte 0 ==
4253 01:23:25.214679 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4254 01:23:25.217806 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4255 01:23:25.221722 == TX Byte 1 ==
4256 01:23:25.224860 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4257 01:23:25.228178 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4258 01:23:25.231588
4259 01:23:25.231743 [DATLAT]
4260 01:23:25.231849 Freq=600, CH0 RK1
4261 01:23:25.231944
4262 01:23:25.234896 DATLAT Default: 0x9
4263 01:23:25.235024 0, 0xFFFF, sum = 0
4264 01:23:25.238188 1, 0xFFFF, sum = 0
4265 01:23:25.238356 2, 0xFFFF, sum = 0
4266 01:23:25.241604 3, 0xFFFF, sum = 0
4267 01:23:25.244842 4, 0xFFFF, sum = 0
4268 01:23:25.245015 5, 0xFFFF, sum = 0
4269 01:23:25.248226 6, 0xFFFF, sum = 0
4270 01:23:25.248397 7, 0xFFFF, sum = 0
4271 01:23:25.251448 8, 0x0, sum = 1
4272 01:23:25.251587 9, 0x0, sum = 2
4273 01:23:25.251696 10, 0x0, sum = 3
4274 01:23:25.254618 11, 0x0, sum = 4
4275 01:23:25.254769 best_step = 9
4276 01:23:25.254873
4277 01:23:25.254970 ==
4278 01:23:25.257686 Dram Type= 6, Freq= 0, CH_0, rank 1
4279 01:23:25.264125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4280 01:23:25.264307 ==
4281 01:23:25.264410 RX Vref Scan: 0
4282 01:23:25.264505
4283 01:23:25.267779 RX Vref 0 -> 0, step: 1
4284 01:23:25.267908
4285 01:23:25.270667 RX Delay -163 -> 252, step: 8
4286 01:23:25.274394 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4287 01:23:25.281079 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4288 01:23:25.284284 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4289 01:23:25.287486 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4290 01:23:25.290770 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4291 01:23:25.294139 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4292 01:23:25.300778 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4293 01:23:25.304198 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4294 01:23:25.307370 iDelay=205, Bit 8, Center 40 (-99 ~ 180) 280
4295 01:23:25.310787 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4296 01:23:25.313929 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4297 01:23:25.320688 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4298 01:23:25.324188 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4299 01:23:25.327532 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4300 01:23:25.330657 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4301 01:23:25.337084 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4302 01:23:25.337273 ==
4303 01:23:25.340974 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 01:23:25.343760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 01:23:25.343906 ==
4306 01:23:25.344008 DQS Delay:
4307 01:23:25.347068 DQS0 = 0, DQS1 = 0
4308 01:23:25.347199 DQM Delay:
4309 01:23:25.350436 DQM0 = 53, DQM1 = 46
4310 01:23:25.350576 DQ Delay:
4311 01:23:25.353813 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4312 01:23:25.357309 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =60
4313 01:23:25.360721 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =36
4314 01:23:25.363811 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4315 01:23:25.363959
4316 01:23:25.364060
4317 01:23:25.370606 [DQSOSCAuto] RK1, (LSB)MR18= 0x6425, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
4318 01:23:25.374123 CH0 RK1: MR19=808, MR18=6425
4319 01:23:25.380334 CH0_RK1: MR19=0x808, MR18=0x6425, DQSOSC=391, MR23=63, INC=171, DEC=114
4320 01:23:25.383900 [RxdqsGatingPostProcess] freq 600
4321 01:23:25.390730 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4322 01:23:25.393708 Pre-setting of DQS Precalculation
4323 01:23:25.397369 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4324 01:23:25.397524 ==
4325 01:23:25.400741 Dram Type= 6, Freq= 0, CH_1, rank 0
4326 01:23:25.404253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4327 01:23:25.404403 ==
4328 01:23:25.410654 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4329 01:23:25.416705 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4330 01:23:25.420091 [CA 0] Center 35 (5~66) winsize 62
4331 01:23:25.423450 [CA 1] Center 36 (5~67) winsize 63
4332 01:23:25.426803 [CA 2] Center 34 (4~65) winsize 62
4333 01:23:25.430665 [CA 3] Center 34 (4~65) winsize 62
4334 01:23:25.433579 [CA 4] Center 34 (4~65) winsize 62
4335 01:23:25.436721 [CA 5] Center 34 (4~64) winsize 61
4336 01:23:25.436897
4337 01:23:25.440446 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4338 01:23:25.440607
4339 01:23:25.443463 [CATrainingPosCal] consider 1 rank data
4340 01:23:25.446704 u2DelayCellTimex100 = 270/100 ps
4341 01:23:25.450433 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4342 01:23:25.453339 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4343 01:23:25.456788 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4344 01:23:25.460137 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4345 01:23:25.464425 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4346 01:23:25.466737 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4347 01:23:25.469857
4348 01:23:25.473355 CA PerBit enable=1, Macro0, CA PI delay=34
4349 01:23:25.473522
4350 01:23:25.476698 [CBTSetCACLKResult] CA Dly = 34
4351 01:23:25.476848 CS Dly: 5 (0~36)
4352 01:23:25.476972 ==
4353 01:23:25.479913 Dram Type= 6, Freq= 0, CH_1, rank 1
4354 01:23:25.483183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 01:23:25.483339 ==
4356 01:23:25.489794 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4357 01:23:25.496819 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4358 01:23:25.499914 [CA 0] Center 36 (5~67) winsize 63
4359 01:23:25.503516 [CA 1] Center 36 (5~67) winsize 63
4360 01:23:25.506354 [CA 2] Center 34 (4~65) winsize 62
4361 01:23:25.509836 [CA 3] Center 34 (4~65) winsize 62
4362 01:23:25.513568 [CA 4] Center 35 (4~66) winsize 63
4363 01:23:25.516513 [CA 5] Center 34 (3~65) winsize 63
4364 01:23:25.516736
4365 01:23:25.519839 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4366 01:23:25.520050
4367 01:23:25.523257 [CATrainingPosCal] consider 2 rank data
4368 01:23:25.526500 u2DelayCellTimex100 = 270/100 ps
4369 01:23:25.529868 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4370 01:23:25.533255 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4371 01:23:25.536447 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4372 01:23:25.539754 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4373 01:23:25.546508 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4374 01:23:25.549930 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4375 01:23:25.550114
4376 01:23:25.553220 CA PerBit enable=1, Macro0, CA PI delay=34
4377 01:23:25.553387
4378 01:23:25.556445 [CBTSetCACLKResult] CA Dly = 34
4379 01:23:25.556610 CS Dly: 5 (0~37)
4380 01:23:25.556738
4381 01:23:25.559693 ----->DramcWriteLeveling(PI) begin...
4382 01:23:25.559844 ==
4383 01:23:25.562850 Dram Type= 6, Freq= 0, CH_1, rank 0
4384 01:23:25.569771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 01:23:25.570017 ==
4386 01:23:25.572882 Write leveling (Byte 0): 31 => 31
4387 01:23:25.573085 Write leveling (Byte 1): 31 => 31
4388 01:23:25.576158 DramcWriteLeveling(PI) end<-----
4389 01:23:25.576321
4390 01:23:25.576449 ==
4391 01:23:25.579546 Dram Type= 6, Freq= 0, CH_1, rank 0
4392 01:23:25.586383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4393 01:23:25.586571 ==
4394 01:23:25.589733 [Gating] SW mode calibration
4395 01:23:25.596601 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4396 01:23:25.600052 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4397 01:23:25.606606 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4398 01:23:25.609807 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4399 01:23:25.612970 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4400 01:23:25.619686 0 9 12 | B1->B0 | 2e2e 2e2e | 1 1 | (1 0) (1 0)
4401 01:23:25.622752 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4402 01:23:25.625812 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4403 01:23:25.632835 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4404 01:23:25.636071 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 01:23:25.639221 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 01:23:25.642488 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 01:23:25.649028 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 01:23:25.652876 0 10 12 | B1->B0 | 3636 3737 | 0 0 | (0 0) (0 0)
4409 01:23:25.656040 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4410 01:23:25.662824 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4411 01:23:25.665915 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4412 01:23:25.669192 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 01:23:25.675824 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 01:23:25.678955 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 01:23:25.682395 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4416 01:23:25.689183 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4417 01:23:25.692571 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4418 01:23:25.695886 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 01:23:25.702359 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 01:23:25.705735 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 01:23:25.709227 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 01:23:25.715891 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 01:23:25.719190 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 01:23:25.722254 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 01:23:25.729242 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 01:23:25.732438 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 01:23:25.735638 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 01:23:25.742069 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 01:23:25.745393 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 01:23:25.748698 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 01:23:25.755354 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 01:23:25.758435 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4433 01:23:25.762031 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 01:23:25.765463 Total UI for P1: 0, mck2ui 16
4435 01:23:25.768661 best dqsien dly found for B0: ( 0, 13, 12)
4436 01:23:25.772066 Total UI for P1: 0, mck2ui 16
4437 01:23:25.775333 best dqsien dly found for B1: ( 0, 13, 14)
4438 01:23:25.778681 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4439 01:23:25.781801 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4440 01:23:25.781980
4441 01:23:25.788672 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4442 01:23:25.791955 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4443 01:23:25.795221 [Gating] SW calibration Done
4444 01:23:25.795371 ==
4445 01:23:25.798578 Dram Type= 6, Freq= 0, CH_1, rank 0
4446 01:23:25.801856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4447 01:23:25.801978 ==
4448 01:23:25.802076 RX Vref Scan: 0
4449 01:23:25.802170
4450 01:23:25.805045 RX Vref 0 -> 0, step: 1
4451 01:23:25.805161
4452 01:23:25.808094 RX Delay -230 -> 252, step: 16
4453 01:23:25.811406 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4454 01:23:25.814746 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4455 01:23:25.821156 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4456 01:23:25.825203 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4457 01:23:25.828478 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4458 01:23:25.831747 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4459 01:23:25.837951 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4460 01:23:25.841741 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4461 01:23:25.844849 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4462 01:23:25.847916 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4463 01:23:25.851481 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4464 01:23:25.858272 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4465 01:23:25.861482 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4466 01:23:25.864850 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4467 01:23:25.868242 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4468 01:23:25.874912 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4469 01:23:25.875094 ==
4470 01:23:25.878285 Dram Type= 6, Freq= 0, CH_1, rank 0
4471 01:23:25.881643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4472 01:23:25.881795 ==
4473 01:23:25.881896 DQS Delay:
4474 01:23:25.884509 DQS0 = 0, DQS1 = 0
4475 01:23:25.884633 DQM Delay:
4476 01:23:25.888250 DQM0 = 47, DQM1 = 46
4477 01:23:25.888376 DQ Delay:
4478 01:23:25.891466 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4479 01:23:25.894907 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4480 01:23:25.898281 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4481 01:23:25.901521 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4482 01:23:25.901648
4483 01:23:25.901746
4484 01:23:25.901837 ==
4485 01:23:25.905015 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 01:23:25.907720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 01:23:25.911476 ==
4488 01:23:25.911591
4489 01:23:25.911687
4490 01:23:25.911778 TX Vref Scan disable
4491 01:23:25.914788 == TX Byte 0 ==
4492 01:23:25.917514 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4493 01:23:25.920979 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4494 01:23:25.924248 == TX Byte 1 ==
4495 01:23:25.928126 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4496 01:23:25.931424 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4497 01:23:25.934759 ==
4498 01:23:25.938104 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 01:23:25.941303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 01:23:25.941460 ==
4501 01:23:25.941586
4502 01:23:25.941716
4503 01:23:25.944410 TX Vref Scan disable
4504 01:23:25.944546 == TX Byte 0 ==
4505 01:23:25.951473 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4506 01:23:25.954635 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4507 01:23:25.954800 == TX Byte 1 ==
4508 01:23:25.960845 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4509 01:23:25.964073 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4510 01:23:25.964235
4511 01:23:25.964363 [DATLAT]
4512 01:23:25.967421 Freq=600, CH1 RK0
4513 01:23:25.967552
4514 01:23:25.967678 DATLAT Default: 0x9
4515 01:23:25.970832 0, 0xFFFF, sum = 0
4516 01:23:25.970975 1, 0xFFFF, sum = 0
4517 01:23:25.974077 2, 0xFFFF, sum = 0
4518 01:23:25.974226 3, 0xFFFF, sum = 0
4519 01:23:25.977325 4, 0xFFFF, sum = 0
4520 01:23:25.980866 5, 0xFFFF, sum = 0
4521 01:23:25.981013 6, 0xFFFF, sum = 0
4522 01:23:25.984126 7, 0xFFFF, sum = 0
4523 01:23:25.984255 8, 0x0, sum = 1
4524 01:23:25.984355 9, 0x0, sum = 2
4525 01:23:25.987728 10, 0x0, sum = 3
4526 01:23:25.987883 11, 0x0, sum = 4
4527 01:23:25.990710 best_step = 9
4528 01:23:25.990838
4529 01:23:25.990937 ==
4530 01:23:25.994051 Dram Type= 6, Freq= 0, CH_1, rank 0
4531 01:23:25.997127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4532 01:23:25.997299 ==
4533 01:23:26.000812 RX Vref Scan: 1
4534 01:23:26.000979
4535 01:23:26.001101 RX Vref 0 -> 0, step: 1
4536 01:23:26.001234
4537 01:23:26.003975 RX Delay -163 -> 252, step: 8
4538 01:23:26.004117
4539 01:23:26.007443 Set Vref, RX VrefLevel [Byte0]: 54
4540 01:23:26.010721 [Byte1]: 54
4541 01:23:26.014699
4542 01:23:26.014845 Final RX Vref Byte 0 = 54 to rank0
4543 01:23:26.017974 Final RX Vref Byte 1 = 54 to rank0
4544 01:23:26.021282 Final RX Vref Byte 0 = 54 to rank1
4545 01:23:26.024287 Final RX Vref Byte 1 = 54 to rank1==
4546 01:23:26.027683 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 01:23:26.034113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 01:23:26.034276 ==
4549 01:23:26.034405 DQS Delay:
4550 01:23:26.037851 DQS0 = 0, DQS1 = 0
4551 01:23:26.037977 DQM Delay:
4552 01:23:26.038089 DQM0 = 49, DQM1 = 45
4553 01:23:26.041254 DQ Delay:
4554 01:23:26.044648 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =48
4555 01:23:26.048033 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4556 01:23:26.051248 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =36
4557 01:23:26.054324 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4558 01:23:26.054450
4559 01:23:26.054560
4560 01:23:26.061194 [DQSOSCAuto] RK0, (LSB)MR18= 0x4469, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 396 ps
4561 01:23:26.064334 CH1 RK0: MR19=808, MR18=4469
4562 01:23:26.071335 CH1_RK0: MR19=0x808, MR18=0x4469, DQSOSC=390, MR23=63, INC=172, DEC=114
4563 01:23:26.071530
4564 01:23:26.074588 ----->DramcWriteLeveling(PI) begin...
4565 01:23:26.074723 ==
4566 01:23:26.077890 Dram Type= 6, Freq= 0, CH_1, rank 1
4567 01:23:26.081135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 01:23:26.081281 ==
4569 01:23:26.084317 Write leveling (Byte 0): 30 => 30
4570 01:23:26.087806 Write leveling (Byte 1): 30 => 30
4571 01:23:26.091247 DramcWriteLeveling(PI) end<-----
4572 01:23:26.091382
4573 01:23:26.091492 ==
4574 01:23:26.094258 Dram Type= 6, Freq= 0, CH_1, rank 1
4575 01:23:26.097487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 01:23:26.097617 ==
4577 01:23:26.100967 [Gating] SW mode calibration
4578 01:23:26.107845 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4579 01:23:26.114117 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4580 01:23:26.118019 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4581 01:23:26.120631 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4582 01:23:26.127830 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4583 01:23:26.131109 0 9 12 | B1->B0 | 2e2e 2e2e | 0 1 | (0 0) (1 0)
4584 01:23:26.134351 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4585 01:23:26.140875 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4586 01:23:26.144084 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4587 01:23:26.147353 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4588 01:23:26.154187 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4589 01:23:26.157624 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4590 01:23:26.160762 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4591 01:23:26.167469 0 10 12 | B1->B0 | 3b3b 3333 | 0 1 | (0 0) (0 0)
4592 01:23:26.170513 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4593 01:23:26.174274 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4594 01:23:26.180598 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4595 01:23:26.183940 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4596 01:23:26.187103 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4597 01:23:26.193745 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4598 01:23:26.197098 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4599 01:23:26.200469 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4600 01:23:26.206896 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4601 01:23:26.210571 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4602 01:23:26.213693 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4603 01:23:26.220100 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 01:23:26.223713 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 01:23:26.226790 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 01:23:26.233883 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 01:23:26.237053 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 01:23:26.240537 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 01:23:26.247231 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 01:23:26.250435 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 01:23:26.253730 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 01:23:26.260426 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 01:23:26.263807 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 01:23:26.266429 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 01:23:26.273670 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 01:23:26.273829 Total UI for P1: 0, mck2ui 16
4617 01:23:26.280102 best dqsien dly found for B0: ( 0, 13, 10)
4618 01:23:26.280254 Total UI for P1: 0, mck2ui 16
4619 01:23:26.283175 best dqsien dly found for B1: ( 0, 13, 10)
4620 01:23:26.290043 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4621 01:23:26.293377 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4622 01:23:26.293476
4623 01:23:26.296821 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4624 01:23:26.300157 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4625 01:23:26.303603 [Gating] SW calibration Done
4626 01:23:26.303692 ==
4627 01:23:26.306736 Dram Type= 6, Freq= 0, CH_1, rank 1
4628 01:23:26.309950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4629 01:23:26.310039 ==
4630 01:23:26.313326 RX Vref Scan: 0
4631 01:23:26.313409
4632 01:23:26.313473 RX Vref 0 -> 0, step: 1
4633 01:23:26.313533
4634 01:23:26.316614 RX Delay -230 -> 252, step: 16
4635 01:23:26.319669 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4636 01:23:26.326205 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4637 01:23:26.329571 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4638 01:23:26.333062 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4639 01:23:26.336218 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4640 01:23:26.343158 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4641 01:23:26.346569 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4642 01:23:26.349857 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4643 01:23:26.353338 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4644 01:23:26.356476 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4645 01:23:26.362886 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4646 01:23:26.366288 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4647 01:23:26.369783 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4648 01:23:26.372999 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4649 01:23:26.379706 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4650 01:23:26.383077 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4651 01:23:26.383198 ==
4652 01:23:26.386172 Dram Type= 6, Freq= 0, CH_1, rank 1
4653 01:23:26.389157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 01:23:26.389280 ==
4655 01:23:26.392570 DQS Delay:
4656 01:23:26.392687 DQS0 = 0, DQS1 = 0
4657 01:23:26.392779 DQM Delay:
4658 01:23:26.396131 DQM0 = 49, DQM1 = 48
4659 01:23:26.396245 DQ Delay:
4660 01:23:26.399297 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =49
4661 01:23:26.402886 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4662 01:23:26.406208 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4663 01:23:26.409584 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4664 01:23:26.409712
4665 01:23:26.409813
4666 01:23:26.409902 ==
4667 01:23:26.413026 Dram Type= 6, Freq= 0, CH_1, rank 1
4668 01:23:26.419532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4669 01:23:26.419700 ==
4670 01:23:26.419799
4671 01:23:26.419888
4672 01:23:26.419975 TX Vref Scan disable
4673 01:23:26.422880 == TX Byte 0 ==
4674 01:23:26.426696 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4675 01:23:26.430085 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4676 01:23:26.433177 == TX Byte 1 ==
4677 01:23:26.436405 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4678 01:23:26.443249 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4679 01:23:26.443395 ==
4680 01:23:26.446404 Dram Type= 6, Freq= 0, CH_1, rank 1
4681 01:23:26.450035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 01:23:26.450152 ==
4683 01:23:26.450248
4684 01:23:26.450348
4685 01:23:26.452989 TX Vref Scan disable
4686 01:23:26.456615 == TX Byte 0 ==
4687 01:23:26.460111 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4688 01:23:26.462968 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4689 01:23:26.463085 == TX Byte 1 ==
4690 01:23:26.469696 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4691 01:23:26.473061 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4692 01:23:26.473180
4693 01:23:26.473274 [DATLAT]
4694 01:23:26.476315 Freq=600, CH1 RK1
4695 01:23:26.476424
4696 01:23:26.476516 DATLAT Default: 0x9
4697 01:23:26.479553 0, 0xFFFF, sum = 0
4698 01:23:26.479668 1, 0xFFFF, sum = 0
4699 01:23:26.482867 2, 0xFFFF, sum = 0
4700 01:23:26.482979 3, 0xFFFF, sum = 0
4701 01:23:26.486276 4, 0xFFFF, sum = 0
4702 01:23:26.489560 5, 0xFFFF, sum = 0
4703 01:23:26.489670 6, 0xFFFF, sum = 0
4704 01:23:26.492941 7, 0xFFFF, sum = 0
4705 01:23:26.493050 8, 0x0, sum = 1
4706 01:23:26.493144 9, 0x0, sum = 2
4707 01:23:26.496172 10, 0x0, sum = 3
4708 01:23:26.496273 11, 0x0, sum = 4
4709 01:23:26.499424 best_step = 9
4710 01:23:26.499528
4711 01:23:26.499618 ==
4712 01:23:26.502867 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 01:23:26.506441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 01:23:26.506549 ==
4715 01:23:26.509287 RX Vref Scan: 0
4716 01:23:26.509388
4717 01:23:26.509475 RX Vref 0 -> 0, step: 1
4718 01:23:26.509561
4719 01:23:26.512866 RX Delay -163 -> 252, step: 8
4720 01:23:26.520251 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4721 01:23:26.523474 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4722 01:23:26.526927 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4723 01:23:26.530132 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4724 01:23:26.533463 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4725 01:23:26.540190 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4726 01:23:26.543395 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4727 01:23:26.546558 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4728 01:23:26.549599 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4729 01:23:26.556631 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4730 01:23:26.559837 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4731 01:23:26.563084 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4732 01:23:26.566690 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4733 01:23:26.569815 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4734 01:23:26.576441 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4735 01:23:26.579891 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4736 01:23:26.580011 ==
4737 01:23:26.582985 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 01:23:26.586519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 01:23:26.586629 ==
4740 01:23:26.589901 DQS Delay:
4741 01:23:26.590008 DQS0 = 0, DQS1 = 0
4742 01:23:26.590101 DQM Delay:
4743 01:23:26.593205 DQM0 = 48, DQM1 = 45
4744 01:23:26.593311 DQ Delay:
4745 01:23:26.596538 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4746 01:23:26.599813 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4747 01:23:26.603182 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4748 01:23:26.606607 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4749 01:23:26.606716
4750 01:23:26.606810
4751 01:23:26.616154 [DQSOSCAuto] RK1, (LSB)MR18= 0x641b, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
4752 01:23:26.616271 CH1 RK1: MR19=808, MR18=641B
4753 01:23:26.623187 CH1_RK1: MR19=0x808, MR18=0x641B, DQSOSC=391, MR23=63, INC=171, DEC=114
4754 01:23:26.626136 [RxdqsGatingPostProcess] freq 600
4755 01:23:26.633236 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4756 01:23:26.636269 Pre-setting of DQS Precalculation
4757 01:23:26.639573 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4758 01:23:26.646477 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4759 01:23:26.656913 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4760 01:23:26.657041
4761 01:23:26.657135
4762 01:23:26.660011 [Calibration Summary] 1200 Mbps
4763 01:23:26.660135 CH 0, Rank 0
4764 01:23:26.662784 SW Impedance : PASS
4765 01:23:26.662894 DUTY Scan : NO K
4766 01:23:26.666410 ZQ Calibration : PASS
4767 01:23:26.666514 Jitter Meter : NO K
4768 01:23:26.669575 CBT Training : PASS
4769 01:23:26.672890 Write leveling : PASS
4770 01:23:26.672994 RX DQS gating : PASS
4771 01:23:26.676524 RX DQ/DQS(RDDQC) : PASS
4772 01:23:26.679464 TX DQ/DQS : PASS
4773 01:23:26.679575 RX DATLAT : PASS
4774 01:23:26.683327 RX DQ/DQS(Engine): PASS
4775 01:23:26.686506 TX OE : NO K
4776 01:23:26.686614 All Pass.
4777 01:23:26.686706
4778 01:23:26.686794 CH 0, Rank 1
4779 01:23:26.689803 SW Impedance : PASS
4780 01:23:26.693140 DUTY Scan : NO K
4781 01:23:26.693244 ZQ Calibration : PASS
4782 01:23:26.696591 Jitter Meter : NO K
4783 01:23:26.699915 CBT Training : PASS
4784 01:23:26.700018 Write leveling : PASS
4785 01:23:26.703214 RX DQS gating : PASS
4786 01:23:26.703318 RX DQ/DQS(RDDQC) : PASS
4787 01:23:26.706572 TX DQ/DQS : PASS
4788 01:23:26.709788 RX DATLAT : PASS
4789 01:23:26.709889 RX DQ/DQS(Engine): PASS
4790 01:23:26.712924 TX OE : NO K
4791 01:23:26.713055 All Pass.
4792 01:23:26.713148
4793 01:23:26.716391 CH 1, Rank 0
4794 01:23:26.716498 SW Impedance : PASS
4795 01:23:26.719708 DUTY Scan : NO K
4796 01:23:26.723026 ZQ Calibration : PASS
4797 01:23:26.723136 Jitter Meter : NO K
4798 01:23:26.726191 CBT Training : PASS
4799 01:23:26.729506 Write leveling : PASS
4800 01:23:26.729616 RX DQS gating : PASS
4801 01:23:26.732825 RX DQ/DQS(RDDQC) : PASS
4802 01:23:26.735945 TX DQ/DQS : PASS
4803 01:23:26.736060 RX DATLAT : PASS
4804 01:23:26.739531 RX DQ/DQS(Engine): PASS
4805 01:23:26.743332 TX OE : NO K
4806 01:23:26.743440 All Pass.
4807 01:23:26.743534
4808 01:23:26.743623 CH 1, Rank 1
4809 01:23:26.746028 SW Impedance : PASS
4810 01:23:26.749814 DUTY Scan : NO K
4811 01:23:26.749935 ZQ Calibration : PASS
4812 01:23:26.752579 Jitter Meter : NO K
4813 01:23:26.755849 CBT Training : PASS
4814 01:23:26.755960 Write leveling : PASS
4815 01:23:26.760237 RX DQS gating : PASS
4816 01:23:26.760349 RX DQ/DQS(RDDQC) : PASS
4817 01:23:26.762403 TX DQ/DQS : PASS
4818 01:23:26.766317 RX DATLAT : PASS
4819 01:23:26.766431 RX DQ/DQS(Engine): PASS
4820 01:23:26.769502 TX OE : NO K
4821 01:23:26.769615 All Pass.
4822 01:23:26.769709
4823 01:23:26.772840 DramC Write-DBI off
4824 01:23:26.775857 PER_BANK_REFRESH: Hybrid Mode
4825 01:23:26.775970 TX_TRACKING: ON
4826 01:23:26.786278 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4827 01:23:26.789042 [FAST_K] Save calibration result to emmc
4828 01:23:26.792742 dramc_set_vcore_voltage set vcore to 662500
4829 01:23:26.795721 Read voltage for 933, 3
4830 01:23:26.795839 Vio18 = 0
4831 01:23:26.795934 Vcore = 662500
4832 01:23:26.799422 Vdram = 0
4833 01:23:26.799538 Vddq = 0
4834 01:23:26.799634 Vmddr = 0
4835 01:23:26.806173 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4836 01:23:26.809504 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4837 01:23:26.812116 MEM_TYPE=3, freq_sel=17
4838 01:23:26.815480 sv_algorithm_assistance_LP4_1600
4839 01:23:26.819398 ============ PULL DRAM RESETB DOWN ============
4840 01:23:26.825534 ========== PULL DRAM RESETB DOWN end =========
4841 01:23:26.829340 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4842 01:23:26.832054 ===================================
4843 01:23:26.835396 LPDDR4 DRAM CONFIGURATION
4844 01:23:26.839345 ===================================
4845 01:23:26.839522 EX_ROW_EN[0] = 0x0
4846 01:23:26.842624 EX_ROW_EN[1] = 0x0
4847 01:23:26.842796 LP4Y_EN = 0x0
4848 01:23:26.845799 WORK_FSP = 0x0
4849 01:23:26.845933 WL = 0x3
4850 01:23:26.848883 RL = 0x3
4851 01:23:26.849001 BL = 0x2
4852 01:23:26.852597 RPST = 0x0
4853 01:23:26.852744 RD_PRE = 0x0
4854 01:23:26.855743 WR_PRE = 0x1
4855 01:23:26.855893 WR_PST = 0x0
4856 01:23:26.858831 DBI_WR = 0x0
4857 01:23:26.862522 DBI_RD = 0x0
4858 01:23:26.862692 OTF = 0x1
4859 01:23:26.865716 ===================================
4860 01:23:26.869191 ===================================
4861 01:23:26.869343 ANA top config
4862 01:23:26.872293 ===================================
4863 01:23:26.875547 DLL_ASYNC_EN = 0
4864 01:23:26.879028 ALL_SLAVE_EN = 1
4865 01:23:26.882355 NEW_RANK_MODE = 1
4866 01:23:26.885700 DLL_IDLE_MODE = 1
4867 01:23:26.885866 LP45_APHY_COMB_EN = 1
4868 01:23:26.888428 TX_ODT_DIS = 1
4869 01:23:26.891633 NEW_8X_MODE = 1
4870 01:23:26.895497 ===================================
4871 01:23:26.898930 ===================================
4872 01:23:26.902180 data_rate = 1866
4873 01:23:26.905305 CKR = 1
4874 01:23:26.905428 DQ_P2S_RATIO = 8
4875 01:23:26.908559 ===================================
4876 01:23:26.911733 CA_P2S_RATIO = 8
4877 01:23:26.915383 DQ_CA_OPEN = 0
4878 01:23:26.918771 DQ_SEMI_OPEN = 0
4879 01:23:26.922197 CA_SEMI_OPEN = 0
4880 01:23:26.924928 CA_FULL_RATE = 0
4881 01:23:26.925058 DQ_CKDIV4_EN = 1
4882 01:23:26.928319 CA_CKDIV4_EN = 1
4883 01:23:26.931662 CA_PREDIV_EN = 0
4884 01:23:26.934784 PH8_DLY = 0
4885 01:23:26.938126 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4886 01:23:26.941426 DQ_AAMCK_DIV = 4
4887 01:23:26.941553 CA_AAMCK_DIV = 4
4888 01:23:26.944861 CA_ADMCK_DIV = 4
4889 01:23:26.948255 DQ_TRACK_CA_EN = 0
4890 01:23:26.951729 CA_PICK = 933
4891 01:23:26.955105 CA_MCKIO = 933
4892 01:23:26.958311 MCKIO_SEMI = 0
4893 01:23:26.961807 PLL_FREQ = 3732
4894 01:23:26.961925 DQ_UI_PI_RATIO = 32
4895 01:23:26.964739 CA_UI_PI_RATIO = 0
4896 01:23:26.967808 ===================================
4897 01:23:26.971440 ===================================
4898 01:23:26.974421 memory_type:LPDDR4
4899 01:23:26.978109 GP_NUM : 10
4900 01:23:26.978279 SRAM_EN : 1
4901 01:23:26.981337 MD32_EN : 0
4902 01:23:26.984433 ===================================
4903 01:23:26.987884 [ANA_INIT] >>>>>>>>>>>>>>
4904 01:23:26.988005 <<<<<< [CONFIGURE PHASE]: ANA_TX
4905 01:23:26.994746 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4906 01:23:26.998002 ===================================
4907 01:23:26.998167 data_rate = 1866,PCW = 0X8f00
4908 01:23:27.001203 ===================================
4909 01:23:27.004618 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4910 01:23:27.010698 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4911 01:23:27.017899 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4912 01:23:27.021095 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4913 01:23:27.024572 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4914 01:23:27.027912 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4915 01:23:27.030716 [ANA_INIT] flow start
4916 01:23:27.030863 [ANA_INIT] PLL >>>>>>>>
4917 01:23:27.034146 [ANA_INIT] PLL <<<<<<<<
4918 01:23:27.037813 [ANA_INIT] MIDPI >>>>>>>>
4919 01:23:27.041061 [ANA_INIT] MIDPI <<<<<<<<
4920 01:23:27.041208 [ANA_INIT] DLL >>>>>>>>
4921 01:23:27.044181 [ANA_INIT] flow end
4922 01:23:27.047611 ============ LP4 DIFF to SE enter ============
4923 01:23:27.051115 ============ LP4 DIFF to SE exit ============
4924 01:23:27.054549 [ANA_INIT] <<<<<<<<<<<<<
4925 01:23:27.057195 [Flow] Enable top DCM control >>>>>
4926 01:23:33.813805 [Flow] Enable top DCM control <<<<<
4927 01:23:33.814049 Enable DLL master slave shuffle
4928 01:23:33.814195 ==============================================================
4929 01:23:33.814372 Gating Mode config
4930 01:23:33.814489 ==============================================================
4931 01:23:33.814576 Config description:
4932 01:23:33.814662 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4933 01:23:33.814748 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4934 01:23:33.814832 SELPH_MODE 0: By rank 1: By Phase
4935 01:23:33.814915 ==============================================================
4936 01:23:33.814997 GAT_TRACK_EN = 1
4937 01:23:33.815079 RX_GATING_MODE = 2
4938 01:23:33.815170 RX_GATING_TRACK_MODE = 2
4939 01:23:33.815251 SELPH_MODE = 1
4940 01:23:33.815332 PICG_EARLY_EN = 1
4941 01:23:33.815412 VALID_LAT_VALUE = 1
4942 01:23:33.815493 ==============================================================
4943 01:23:33.815574 Enter into Gating configuration >>>>
4944 01:23:33.815655 Exit from Gating configuration <<<<
4945 01:23:33.815735 Enter into DVFS_PRE_config >>>>>
4946 01:23:33.815817 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4947 01:23:33.815899 Exit from DVFS_PRE_config <<<<<
4948 01:23:33.815989 Enter into PICG configuration >>>>
4949 01:23:33.816069 Exit from PICG configuration <<<<
4950 01:23:33.816149 [RX_INPUT] configuration >>>>>
4951 01:23:33.816229 [RX_INPUT] configuration <<<<<
4952 01:23:33.816310 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4953 01:23:33.816391 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4954 01:23:33.816472 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4955 01:23:33.816554 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4956 01:23:33.816635 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4957 01:23:33.816716 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4958 01:23:33.816796 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4959 01:23:33.816877 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4960 01:23:33.816958 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4961 01:23:33.817055 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4962 01:23:33.817173 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4963 01:23:33.817265 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4964 01:23:33.817362 ===================================
4965 01:23:33.817443 LPDDR4 DRAM CONFIGURATION
4966 01:23:33.817523 ===================================
4967 01:23:33.817603 EX_ROW_EN[0] = 0x0
4968 01:23:33.817683 EX_ROW_EN[1] = 0x0
4969 01:23:33.817763 LP4Y_EN = 0x0
4970 01:23:33.817843 WORK_FSP = 0x0
4971 01:23:33.817923 WL = 0x3
4972 01:23:33.818002 RL = 0x3
4973 01:23:33.818082 BL = 0x2
4974 01:23:33.818161 RPST = 0x0
4975 01:23:33.818241 RD_PRE = 0x0
4976 01:23:33.818340 WR_PRE = 0x1
4977 01:23:33.818409 WR_PST = 0x0
4978 01:23:33.818460 DBI_WR = 0x0
4979 01:23:33.818511 DBI_RD = 0x0
4980 01:23:33.818562 OTF = 0x1
4981 01:23:33.818614 ===================================
4982 01:23:33.818675 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4983 01:23:33.818727 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4984 01:23:33.818779 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4985 01:23:33.818830 ===================================
4986 01:23:33.818882 LPDDR4 DRAM CONFIGURATION
4987 01:23:33.818933 ===================================
4988 01:23:33.818984 EX_ROW_EN[0] = 0x10
4989 01:23:33.819035 EX_ROW_EN[1] = 0x0
4990 01:23:33.819086 LP4Y_EN = 0x0
4991 01:23:33.819137 WORK_FSP = 0x0
4992 01:23:33.819188 WL = 0x3
4993 01:23:33.819239 RL = 0x3
4994 01:23:33.819290 BL = 0x2
4995 01:23:33.819340 RPST = 0x0
4996 01:23:33.819400 RD_PRE = 0x0
4997 01:23:33.819451 WR_PRE = 0x1
4998 01:23:33.819502 WR_PST = 0x0
4999 01:23:33.819552 DBI_WR = 0x0
5000 01:23:33.819603 DBI_RD = 0x0
5001 01:23:33.819654 OTF = 0x1
5002 01:23:33.819705 ===================================
5003 01:23:33.819756 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5004 01:23:33.819807 nWR fixed to 30
5005 01:23:33.819859 [ModeRegInit_LP4] CH0 RK0
5006 01:23:33.819910 [ModeRegInit_LP4] CH0 RK1
5007 01:23:33.819961 [ModeRegInit_LP4] CH1 RK0
5008 01:23:33.820011 [ModeRegInit_LP4] CH1 RK1
5009 01:23:33.820061 match AC timing 9
5010 01:23:33.820112 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5011 01:23:33.820163 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5012 01:23:33.820214 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5013 01:23:33.820265 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5014 01:23:33.820315 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5015 01:23:33.820366 ==
5016 01:23:33.820418 Dram Type= 6, Freq= 0, CH_0, rank 0
5017 01:23:33.820470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5018 01:23:33.820521 ==
5019 01:23:33.820626 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5020 01:23:33.820685 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5021 01:23:33.820739 [CA 0] Center 37 (6~68) winsize 63
5022 01:23:33.820792 [CA 1] Center 37 (7~68) winsize 62
5023 01:23:33.820844 [CA 2] Center 34 (4~65) winsize 62
5024 01:23:33.820897 [CA 3] Center 34 (3~65) winsize 63
5025 01:23:33.820980 [CA 4] Center 33 (3~64) winsize 62
5026 01:23:33.821045 [CA 5] Center 32 (2~62) winsize 61
5027 01:23:33.821096
5028 01:23:33.821148 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5029 01:23:33.821200
5030 01:23:33.821251 [CATrainingPosCal] consider 1 rank data
5031 01:23:33.821302 u2DelayCellTimex100 = 270/100 ps
5032 01:23:33.821354 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5033 01:23:33.821405 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5034 01:23:33.821460 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5035 01:23:33.821728 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5036 01:23:33.821857 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5037 01:23:33.821984 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5038 01:23:33.822109
5039 01:23:33.822235 CA PerBit enable=1, Macro0, CA PI delay=32
5040 01:23:33.822365
5041 01:23:33.822423 [CBTSetCACLKResult] CA Dly = 32
5042 01:23:33.822477 CS Dly: 5 (0~36)
5043 01:23:33.822530 ==
5044 01:23:33.822583 Dram Type= 6, Freq= 0, CH_0, rank 1
5045 01:23:33.822636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5046 01:23:33.822689 ==
5047 01:23:33.822741 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5048 01:23:33.822793 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5049 01:23:33.822846 [CA 0] Center 37 (6~68) winsize 63
5050 01:23:33.822898 [CA 1] Center 37 (6~68) winsize 63
5051 01:23:33.822949 [CA 2] Center 34 (4~65) winsize 62
5052 01:23:33.823001 [CA 3] Center 34 (4~64) winsize 61
5053 01:23:33.823053 [CA 4] Center 33 (3~63) winsize 61
5054 01:23:33.823115 [CA 5] Center 32 (2~62) winsize 61
5055 01:23:33.823167
5056 01:23:33.823219 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5057 01:23:33.823270
5058 01:23:33.823362 [CATrainingPosCal] consider 2 rank data
5059 01:23:33.823428 u2DelayCellTimex100 = 270/100 ps
5060 01:23:33.823482 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5061 01:23:33.823536 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5062 01:23:33.823589 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5063 01:23:33.823642 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5064 01:23:33.823695 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5065 01:23:33.823760 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5066 01:23:33.823812
5067 01:23:33.823864 CA PerBit enable=1, Macro0, CA PI delay=32
5068 01:23:33.823915
5069 01:23:33.823967 [CBTSetCACLKResult] CA Dly = 32
5070 01:23:33.824019 CS Dly: 6 (0~38)
5071 01:23:33.824070
5072 01:23:33.824121 ----->DramcWriteLeveling(PI) begin...
5073 01:23:33.824174 ==
5074 01:23:33.824226 Dram Type= 6, Freq= 0, CH_0, rank 0
5075 01:23:33.824278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5076 01:23:33.824331 ==
5077 01:23:33.824383 Write leveling (Byte 0): 33 => 33
5078 01:23:33.824460 Write leveling (Byte 1): 28 => 28
5079 01:23:33.824513 DramcWriteLeveling(PI) end<-----
5080 01:23:33.824597
5081 01:23:33.824652 ==
5082 01:23:33.824765 Dram Type= 6, Freq= 0, CH_0, rank 0
5083 01:23:33.824836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5084 01:23:33.824918 ==
5085 01:23:33.824984 [Gating] SW mode calibration
5086 01:23:33.825077 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5087 01:23:33.825153 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5088 01:23:33.825207 0 14 0 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
5089 01:23:33.825280 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5090 01:23:33.825336 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5091 01:23:33.825390 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5092 01:23:33.825443 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5093 01:23:33.825495 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5094 01:23:33.825549 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5095 01:23:33.825602 0 14 28 | B1->B0 | 3333 2727 | 0 0 | (0 0) (1 0)
5096 01:23:33.825655 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
5097 01:23:33.825708 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5098 01:23:33.825760 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5099 01:23:33.825821 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5100 01:23:33.825874 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5101 01:23:33.825947 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5102 01:23:33.826002 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 01:23:33.826055 0 15 28 | B1->B0 | 2424 3838 | 0 0 | (0 0) (0 0)
5104 01:23:33.826108 1 0 0 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
5105 01:23:33.826161 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5106 01:23:33.826213 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5107 01:23:33.826266 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5108 01:23:33.826353 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5109 01:23:33.826406 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 01:23:33.826458 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 01:23:33.826534 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5112 01:23:33.826602 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5113 01:23:33.826655 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5114 01:23:33.826706 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 01:23:33.826758 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 01:23:33.826838 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 01:23:33.826978 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 01:23:33.827071 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 01:23:33.827127 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 01:23:33.827180 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 01:23:33.827232 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 01:23:33.827284 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 01:23:33.827336 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 01:23:33.827387 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 01:23:33.827439 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 01:23:33.827490 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 01:23:33.827541 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5128 01:23:33.827593 Total UI for P1: 0, mck2ui 16
5129 01:23:33.827645 best dqsien dly found for B0: ( 1, 2, 26)
5130 01:23:33.827697 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5131 01:23:33.827749 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 01:23:33.827800 Total UI for P1: 0, mck2ui 16
5133 01:23:33.827851 best dqsien dly found for B1: ( 1, 3, 0)
5134 01:23:33.827903 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5135 01:23:33.827954 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5136 01:23:33.828005
5137 01:23:33.828058 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5138 01:23:33.828325 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5139 01:23:33.828425 [Gating] SW calibration Done
5140 01:23:33.828492 ==
5141 01:23:33.828545 Dram Type= 6, Freq= 0, CH_0, rank 0
5142 01:23:33.828597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5143 01:23:33.828650 ==
5144 01:23:33.828702 RX Vref Scan: 0
5145 01:23:33.828753
5146 01:23:33.828805 RX Vref 0 -> 0, step: 1
5147 01:23:33.828856
5148 01:23:33.828908 RX Delay -80 -> 252, step: 8
5149 01:23:33.828959 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5150 01:23:33.829015 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5151 01:23:33.829074 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5152 01:23:33.829183 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5153 01:23:33.829275 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5154 01:23:33.829327 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5155 01:23:33.829378 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5156 01:23:33.829430 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5157 01:23:33.829481 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5158 01:23:33.829533 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5159 01:23:33.829584 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5160 01:23:33.829636 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5161 01:23:33.829687 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5162 01:23:33.829738 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5163 01:23:33.829790 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5164 01:23:33.829841 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5165 01:23:33.829892 ==
5166 01:23:33.829944 Dram Type= 6, Freq= 0, CH_0, rank 0
5167 01:23:33.829996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5168 01:23:33.830064 ==
5169 01:23:33.830117 DQS Delay:
5170 01:23:33.830251 DQS0 = 0, DQS1 = 0
5171 01:23:33.830368 DQM Delay:
5172 01:23:33.830437 DQM0 = 104, DQM1 = 94
5173 01:23:33.830507 DQ Delay:
5174 01:23:33.830590 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5175 01:23:33.830672 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =111
5176 01:23:33.830728 DQ8 =87, DQ9 =83, DQ10 =91, DQ11 =87
5177 01:23:33.830789 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5178 01:23:33.830843
5179 01:23:33.830895
5180 01:23:33.830947 ==
5181 01:23:33.831000 Dram Type= 6, Freq= 0, CH_0, rank 0
5182 01:23:33.831053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5183 01:23:33.831106 ==
5184 01:23:33.831169
5185 01:23:33.831241
5186 01:23:33.831295 TX Vref Scan disable
5187 01:23:33.831348 == TX Byte 0 ==
5188 01:23:33.831401 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5189 01:23:33.831454 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5190 01:23:33.831507 == TX Byte 1 ==
5191 01:23:33.831559 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5192 01:23:33.831611 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5193 01:23:33.831664 ==
5194 01:23:33.831725 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 01:23:33.831779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 01:23:33.831832 ==
5197 01:23:33.831885
5198 01:23:33.831937
5199 01:23:33.831989 TX Vref Scan disable
5200 01:23:33.832042 == TX Byte 0 ==
5201 01:23:33.832094 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5202 01:23:33.832147 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5203 01:23:33.832199 == TX Byte 1 ==
5204 01:23:33.832252 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5205 01:23:33.832305 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5206 01:23:33.832357
5207 01:23:33.832409 [DATLAT]
5208 01:23:33.832461 Freq=933, CH0 RK0
5209 01:23:33.832514
5210 01:23:33.832566 DATLAT Default: 0xd
5211 01:23:33.832619 0, 0xFFFF, sum = 0
5212 01:23:33.832673 1, 0xFFFF, sum = 0
5213 01:23:33.832727 2, 0xFFFF, sum = 0
5214 01:23:33.832780 3, 0xFFFF, sum = 0
5215 01:23:33.832833 4, 0xFFFF, sum = 0
5216 01:23:33.832887 5, 0xFFFF, sum = 0
5217 01:23:33.832940 6, 0xFFFF, sum = 0
5218 01:23:33.832993 7, 0xFFFF, sum = 0
5219 01:23:33.833047 8, 0xFFFF, sum = 0
5220 01:23:33.833100 9, 0xFFFF, sum = 0
5221 01:23:33.833157 10, 0x0, sum = 1
5222 01:23:33.833223 11, 0x0, sum = 2
5223 01:23:33.833277 12, 0x0, sum = 3
5224 01:23:33.833344 13, 0x0, sum = 4
5225 01:23:33.833424 best_step = 11
5226 01:23:33.833479
5227 01:23:33.833532 ==
5228 01:23:33.833585 Dram Type= 6, Freq= 0, CH_0, rank 0
5229 01:23:33.833639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5230 01:23:33.833706 ==
5231 01:23:33.833758 RX Vref Scan: 1
5232 01:23:33.833809
5233 01:23:33.833861 RX Vref 0 -> 0, step: 1
5234 01:23:33.833912
5235 01:23:33.833964 RX Delay -53 -> 252, step: 4
5236 01:23:33.834016
5237 01:23:33.834067 Set Vref, RX VrefLevel [Byte0]: 56
5238 01:23:33.834119 [Byte1]: 50
5239 01:23:33.834170
5240 01:23:33.834222 Final RX Vref Byte 0 = 56 to rank0
5241 01:23:33.834274 Final RX Vref Byte 1 = 50 to rank0
5242 01:23:33.834351 Final RX Vref Byte 0 = 56 to rank1
5243 01:23:33.834418 Final RX Vref Byte 1 = 50 to rank1==
5244 01:23:33.834471 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 01:23:33.834522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 01:23:33.834573 ==
5247 01:23:33.834625 DQS Delay:
5248 01:23:33.834676 DQS0 = 0, DQS1 = 0
5249 01:23:33.834728 DQM Delay:
5250 01:23:33.834779 DQM0 = 104, DQM1 = 96
5251 01:23:33.834840 DQ Delay:
5252 01:23:33.834892 DQ0 =104, DQ1 =104, DQ2 =104, DQ3 =102
5253 01:23:33.834945 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =110
5254 01:23:33.834996 DQ8 =86, DQ9 =86, DQ10 =96, DQ11 =92
5255 01:23:33.835047 DQ12 =100, DQ13 =100, DQ14 =106, DQ15 =102
5256 01:23:33.835098
5257 01:23:33.835153
5258 01:23:33.835258 [DQSOSCAuto] RK0, (LSB)MR18= 0x3129, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5259 01:23:33.835364 CH0 RK0: MR19=505, MR18=3129
5260 01:23:33.835506 CH0_RK0: MR19=0x505, MR18=0x3129, DQSOSC=406, MR23=63, INC=65, DEC=43
5261 01:23:33.835578
5262 01:23:33.835630 ----->DramcWriteLeveling(PI) begin...
5263 01:23:33.835684 ==
5264 01:23:33.835736 Dram Type= 6, Freq= 0, CH_0, rank 1
5265 01:23:33.835787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 01:23:33.835839 ==
5267 01:23:33.835891 Write leveling (Byte 0): 34 => 34
5268 01:23:33.835943 Write leveling (Byte 1): 33 => 33
5269 01:23:33.835995 DramcWriteLeveling(PI) end<-----
5270 01:23:33.836046
5271 01:23:33.836097 ==
5272 01:23:33.836157 Dram Type= 6, Freq= 0, CH_0, rank 1
5273 01:23:33.836210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 01:23:33.836261 ==
5275 01:23:33.836313 [Gating] SW mode calibration
5276 01:23:33.836364 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5277 01:23:33.836416 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5278 01:23:33.836468 0 14 0 | B1->B0 | 3333 3131 | 1 1 | (0 0) (1 1)
5279 01:23:33.836519 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5280 01:23:33.836571 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5281 01:23:33.836664 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5282 01:23:33.836727 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5283 01:23:33.836780 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5284 01:23:33.837051 0 14 24 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
5285 01:23:33.837180 0 14 28 | B1->B0 | 2b2b 2626 | 0 0 | (0 0) (0 1)
5286 01:23:33.837319 0 15 0 | B1->B0 | 2828 2626 | 0 0 | (0 0) (0 0)
5287 01:23:33.837532 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5288 01:23:33.837674 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5289 01:23:33.837802 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5290 01:23:33.837929 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5291 01:23:33.838055 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5292 01:23:33.838194 0 15 24 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
5293 01:23:33.838329 0 15 28 | B1->B0 | 3737 3232 | 0 0 | (0 0) (1 1)
5294 01:23:33.838402 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5295 01:23:33.838455 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5296 01:23:33.838507 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5297 01:23:33.838559 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5298 01:23:33.838610 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5299 01:23:33.838662 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5300 01:23:33.838713 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5301 01:23:33.838763 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5302 01:23:33.838815 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5303 01:23:33.838866 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5304 01:23:33.838917 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5305 01:23:33.838968 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5306 01:23:33.839019 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 01:23:33.839087 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 01:23:33.839143 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 01:23:33.839195 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 01:23:33.839260 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 01:23:33.839310 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 01:23:33.839361 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 01:23:33.839412 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 01:23:33.839463 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 01:23:33.839514 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 01:23:33.839564 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 01:23:33.839625 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5318 01:23:33.839675 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5319 01:23:33.839742 Total UI for P1: 0, mck2ui 16
5320 01:23:33.839807 best dqsien dly found for B0: ( 1, 2, 28)
5321 01:23:33.839857 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 01:23:33.839908 Total UI for P1: 0, mck2ui 16
5323 01:23:33.839978 best dqsien dly found for B1: ( 1, 2, 30)
5324 01:23:33.840067 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5325 01:23:33.840121 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5326 01:23:33.840173
5327 01:23:33.840226 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5328 01:23:33.840293 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5329 01:23:33.840345 [Gating] SW calibration Done
5330 01:23:33.840395 ==
5331 01:23:33.840446 Dram Type= 6, Freq= 0, CH_0, rank 1
5332 01:23:33.840498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5333 01:23:33.840549 ==
5334 01:23:33.840601 RX Vref Scan: 0
5335 01:23:33.840652
5336 01:23:33.840703 RX Vref 0 -> 0, step: 1
5337 01:23:33.840753
5338 01:23:33.840804 RX Delay -80 -> 252, step: 8
5339 01:23:33.840855 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5340 01:23:33.840906 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5341 01:23:33.840970 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5342 01:23:33.841054 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5343 01:23:33.841107 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5344 01:23:33.841171 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5345 01:23:33.841222 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5346 01:23:33.841273 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5347 01:23:33.841324 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5348 01:23:33.841375 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5349 01:23:33.841426 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5350 01:23:33.841493 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5351 01:23:33.841557 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5352 01:23:33.841607 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5353 01:23:33.841668 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5354 01:23:33.841720 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5355 01:23:33.841771 ==
5356 01:23:33.841822 Dram Type= 6, Freq= 0, CH_0, rank 1
5357 01:23:33.841873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5358 01:23:33.841925 ==
5359 01:23:33.841975 DQS Delay:
5360 01:23:33.842025 DQS0 = 0, DQS1 = 0
5361 01:23:33.842077 DQM Delay:
5362 01:23:33.842128 DQM0 = 105, DQM1 = 94
5363 01:23:33.842179 DQ Delay:
5364 01:23:33.842230 DQ0 =103, DQ1 =111, DQ2 =103, DQ3 =99
5365 01:23:33.842281 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5366 01:23:33.842372 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =87
5367 01:23:33.842425 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =103
5368 01:23:33.842487
5369 01:23:33.842538
5370 01:23:33.842589 ==
5371 01:23:33.842640 Dram Type= 6, Freq= 0, CH_0, rank 1
5372 01:23:33.842691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5373 01:23:33.842743 ==
5374 01:23:33.842794
5375 01:23:33.842844
5376 01:23:33.842910 TX Vref Scan disable
5377 01:23:33.842976 == TX Byte 0 ==
5378 01:23:33.843030 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5379 01:23:33.843152 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5380 01:23:33.843223 == TX Byte 1 ==
5381 01:23:33.843274 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5382 01:23:33.843325 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5383 01:23:33.843377 ==
5384 01:23:33.843481 Dram Type= 6, Freq= 0, CH_0, rank 1
5385 01:23:33.843539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5386 01:23:33.843593 ==
5387 01:23:33.843645
5388 01:23:33.843697
5389 01:23:33.843749 TX Vref Scan disable
5390 01:23:33.843801 == TX Byte 0 ==
5391 01:23:33.843867 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5392 01:23:33.843918 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5393 01:23:33.843970 == TX Byte 1 ==
5394 01:23:33.844020 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5395 01:23:33.844072 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5396 01:23:33.844123
5397 01:23:33.844174 [DATLAT]
5398 01:23:33.844437 Freq=933, CH0 RK1
5399 01:23:33.844563
5400 01:23:33.844687 DATLAT Default: 0xb
5401 01:23:33.844834 0, 0xFFFF, sum = 0
5402 01:23:33.844967 1, 0xFFFF, sum = 0
5403 01:23:33.845064 2, 0xFFFF, sum = 0
5404 01:23:33.845120 3, 0xFFFF, sum = 0
5405 01:23:33.845184 4, 0xFFFF, sum = 0
5406 01:23:33.845262 5, 0xFFFF, sum = 0
5407 01:23:33.845329 6, 0xFFFF, sum = 0
5408 01:23:33.845382 7, 0xFFFF, sum = 0
5409 01:23:33.845434 8, 0xFFFF, sum = 0
5410 01:23:33.845487 9, 0xFFFF, sum = 0
5411 01:23:33.845539 10, 0x0, sum = 1
5412 01:23:33.845591 11, 0x0, sum = 2
5413 01:23:33.845643 12, 0x0, sum = 3
5414 01:23:33.845725 13, 0x0, sum = 4
5415 01:23:33.845776 best_step = 11
5416 01:23:33.845827
5417 01:23:33.845879 ==
5418 01:23:33.845939 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 01:23:33.845991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 01:23:33.846043 ==
5421 01:23:33.846095 RX Vref Scan: 0
5422 01:23:33.846146
5423 01:23:33.846197 RX Vref 0 -> 0, step: 1
5424 01:23:33.846247
5425 01:23:33.846298 RX Delay -53 -> 252, step: 4
5426 01:23:33.846392 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5427 01:23:33.846443 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5428 01:23:33.846494 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5429 01:23:33.846545 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5430 01:23:33.846596 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5431 01:23:33.846647 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5432 01:23:33.846698 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5433 01:23:33.846749 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5434 01:23:33.846864 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5435 01:23:33.846920 iDelay=199, Bit 9, Center 84 (-1 ~ 170) 172
5436 01:23:33.846974 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5437 01:23:33.847027 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5438 01:23:33.847079 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5439 01:23:33.847131 iDelay=199, Bit 13, Center 100 (19 ~ 182) 164
5440 01:23:33.847183 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5441 01:23:33.847251 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5442 01:23:33.847308 ==
5443 01:23:33.847395 Dram Type= 6, Freq= 0, CH_0, rank 1
5444 01:23:33.847456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5445 01:23:33.847560 ==
5446 01:23:33.847615 DQS Delay:
5447 01:23:33.847667 DQS0 = 0, DQS1 = 0
5448 01:23:33.847729 DQM Delay:
5449 01:23:33.847781 DQM0 = 105, DQM1 = 94
5450 01:23:33.847832 DQ Delay:
5451 01:23:33.847915 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5452 01:23:33.847967 DQ4 =106, DQ5 =98, DQ6 =112, DQ7 =112
5453 01:23:33.848018 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =88
5454 01:23:33.848070 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =102
5455 01:23:33.848120
5456 01:23:33.848171
5457 01:23:33.848222 [DQSOSCAuto] RK1, (LSB)MR18= 0x25fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 410 ps
5458 01:23:33.848274 CH0 RK1: MR19=504, MR18=25FD
5459 01:23:33.848325 CH0_RK1: MR19=0x504, MR18=0x25FD, DQSOSC=410, MR23=63, INC=64, DEC=42
5460 01:23:33.848377 [RxdqsGatingPostProcess] freq 933
5461 01:23:33.848428 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5462 01:23:33.848479 best DQS0 dly(2T, 0.5T) = (0, 10)
5463 01:23:33.848530 best DQS1 dly(2T, 0.5T) = (0, 11)
5464 01:23:33.848580 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5465 01:23:33.848661 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5466 01:23:33.848712 best DQS0 dly(2T, 0.5T) = (0, 10)
5467 01:23:33.848763 best DQS1 dly(2T, 0.5T) = (0, 10)
5468 01:23:33.848813 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5469 01:23:33.848863 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5470 01:23:33.848914 Pre-setting of DQS Precalculation
5471 01:23:33.848965 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5472 01:23:33.849015 ==
5473 01:23:33.849067 Dram Type= 6, Freq= 0, CH_1, rank 0
5474 01:23:33.849118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 01:23:33.849170 ==
5476 01:23:33.849230 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5477 01:23:33.849282 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5478 01:23:33.849334 [CA 0] Center 36 (6~67) winsize 62
5479 01:23:33.849385 [CA 1] Center 36 (6~67) winsize 62
5480 01:23:33.849435 [CA 2] Center 34 (4~65) winsize 62
5481 01:23:33.849503 [CA 3] Center 34 (4~65) winsize 62
5482 01:23:33.849556 [CA 4] Center 34 (4~64) winsize 61
5483 01:23:33.849620 [CA 5] Center 33 (3~64) winsize 62
5484 01:23:33.849670
5485 01:23:33.849721 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5486 01:23:33.849772
5487 01:23:33.849822 [CATrainingPosCal] consider 1 rank data
5488 01:23:33.849872 u2DelayCellTimex100 = 270/100 ps
5489 01:23:33.849924 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5490 01:23:33.849976 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5491 01:23:33.850027 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5492 01:23:33.850077 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5493 01:23:33.850128 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5494 01:23:33.850179 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5495 01:23:33.850247
5496 01:23:33.850363 CA PerBit enable=1, Macro0, CA PI delay=33
5497 01:23:33.850417
5498 01:23:33.850468 [CBTSetCACLKResult] CA Dly = 33
5499 01:23:33.850520 CS Dly: 7 (0~38)
5500 01:23:33.850571 ==
5501 01:23:33.850623 Dram Type= 6, Freq= 0, CH_1, rank 1
5502 01:23:33.850674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 01:23:33.850726 ==
5504 01:23:33.850778 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5505 01:23:33.850830 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5506 01:23:33.850881 [CA 0] Center 36 (6~67) winsize 62
5507 01:23:33.850932 [CA 1] Center 37 (6~68) winsize 63
5508 01:23:33.850983 [CA 2] Center 35 (5~66) winsize 62
5509 01:23:33.851033 [CA 3] Center 34 (4~65) winsize 62
5510 01:23:33.851084 [CA 4] Center 34 (4~65) winsize 62
5511 01:23:33.851138 [CA 5] Center 34 (4~64) winsize 61
5512 01:23:33.851200
5513 01:23:33.851260 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5514 01:23:33.851311
5515 01:23:33.851361 [CATrainingPosCal] consider 2 rank data
5516 01:23:33.851413 u2DelayCellTimex100 = 270/100 ps
5517 01:23:33.851463 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5518 01:23:33.851514 CA1 delay=36 (6~67),Diff = 2 PI (12 cell)
5519 01:23:33.851565 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5520 01:23:33.851616 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5521 01:23:33.851666 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5522 01:23:33.851717 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5523 01:23:33.851768
5524 01:23:33.851819 CA PerBit enable=1, Macro0, CA PI delay=34
5525 01:23:33.851870
5526 01:23:33.851921 [CBTSetCACLKResult] CA Dly = 34
5527 01:23:33.851972 CS Dly: 8 (0~40)
5528 01:23:33.852023
5529 01:23:33.852279 ----->DramcWriteLeveling(PI) begin...
5530 01:23:33.852339 ==
5531 01:23:33.852391 Dram Type= 6, Freq= 0, CH_1, rank 0
5532 01:23:33.852443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 01:23:33.852495 ==
5534 01:23:33.852547 Write leveling (Byte 0): 28 => 28
5535 01:23:33.852599 Write leveling (Byte 1): 28 => 28
5536 01:23:33.852649 DramcWriteLeveling(PI) end<-----
5537 01:23:33.852711
5538 01:23:33.852762 ==
5539 01:23:33.852813 Dram Type= 6, Freq= 0, CH_1, rank 0
5540 01:23:33.852864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5541 01:23:33.852916 ==
5542 01:23:33.852967 [Gating] SW mode calibration
5543 01:23:33.853018 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5544 01:23:33.853070 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5545 01:23:33.853121 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5546 01:23:33.853173 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5547 01:23:33.853225 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5548 01:23:33.853276 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5549 01:23:33.853326 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 01:23:33.853377 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5551 01:23:33.853428 0 14 24 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 0)
5552 01:23:33.853479 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
5553 01:23:33.853530 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5554 01:23:33.853581 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5555 01:23:33.853632 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5556 01:23:33.853683 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5557 01:23:33.853734 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 01:23:33.853785 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 01:23:33.853835 0 15 24 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
5560 01:23:33.853886 0 15 28 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
5561 01:23:33.853936 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5562 01:23:33.853987 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5563 01:23:33.854038 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5564 01:23:33.854089 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 01:23:33.854140 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 01:23:33.854191 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 01:23:33.854242 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5568 01:23:33.854293 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5569 01:23:33.854389 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 01:23:33.854440 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 01:23:33.854491 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 01:23:33.854543 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 01:23:33.854594 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 01:23:33.854655 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 01:23:33.854706 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 01:23:33.854757 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 01:23:33.854808 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 01:23:33.854858 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 01:23:33.854909 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 01:23:33.854959 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 01:23:33.855010 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 01:23:33.855061 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 01:23:33.855111 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 01:23:33.855162 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5585 01:23:33.855213 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 01:23:33.855267 Total UI for P1: 0, mck2ui 16
5587 01:23:33.855325 best dqsien dly found for B0: ( 1, 2, 28)
5588 01:23:33.855384 Total UI for P1: 0, mck2ui 16
5589 01:23:33.855435 best dqsien dly found for B1: ( 1, 2, 28)
5590 01:23:33.855486 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5591 01:23:33.855537 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5592 01:23:33.855588
5593 01:23:33.855639 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5594 01:23:33.855690 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5595 01:23:33.855741 [Gating] SW calibration Done
5596 01:23:33.855791 ==
5597 01:23:33.855843 Dram Type= 6, Freq= 0, CH_1, rank 0
5598 01:23:33.855894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 01:23:33.855945 ==
5600 01:23:33.855996 RX Vref Scan: 0
5601 01:23:33.856047
5602 01:23:33.856097 RX Vref 0 -> 0, step: 1
5603 01:23:33.856156
5604 01:23:33.856208 RX Delay -80 -> 252, step: 8
5605 01:23:33.856258 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5606 01:23:33.856309 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5607 01:23:33.856360 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5608 01:23:33.856410 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5609 01:23:33.856460 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5610 01:23:33.856511 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5611 01:23:33.856562 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5612 01:23:33.856612 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5613 01:23:33.856663 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5614 01:23:33.856714 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5615 01:23:33.856765 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5616 01:23:33.856816 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5617 01:23:33.856866 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5618 01:23:33.856917 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5619 01:23:33.856967 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5620 01:23:33.857018 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5621 01:23:33.857068 ==
5622 01:23:33.857119 Dram Type= 6, Freq= 0, CH_1, rank 0
5623 01:23:33.857170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5624 01:23:33.857221 ==
5625 01:23:33.857272 DQS Delay:
5626 01:23:33.857323 DQS0 = 0, DQS1 = 0
5627 01:23:33.857373 DQM Delay:
5628 01:23:33.857424 DQM0 = 103, DQM1 = 98
5629 01:23:33.857475 DQ Delay:
5630 01:23:33.857526 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5631 01:23:33.857577 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5632 01:23:33.857828 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5633 01:23:33.857958 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =103
5634 01:23:33.858094
5635 01:23:33.858219
5636 01:23:33.858384 ==
5637 01:23:33.858511 Dram Type= 6, Freq= 0, CH_1, rank 0
5638 01:23:33.858637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5639 01:23:33.858790 ==
5640 01:23:33.858915
5641 01:23:33.859034
5642 01:23:33.859091 TX Vref Scan disable
5643 01:23:33.859144 == TX Byte 0 ==
5644 01:23:33.859196 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5645 01:23:33.859252 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5646 01:23:33.859310 == TX Byte 1 ==
5647 01:23:33.859386 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5648 01:23:33.859461 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5649 01:23:33.859513 ==
5650 01:23:33.859565 Dram Type= 6, Freq= 0, CH_1, rank 0
5651 01:23:33.859617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5652 01:23:33.859669 ==
5653 01:23:33.859720
5654 01:23:33.859770
5655 01:23:33.859820 TX Vref Scan disable
5656 01:23:33.859871 == TX Byte 0 ==
5657 01:23:33.859922 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5658 01:23:33.859973 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5659 01:23:33.860024 == TX Byte 1 ==
5660 01:23:33.860075 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5661 01:23:33.860126 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5662 01:23:33.860176
5663 01:23:33.860227 [DATLAT]
5664 01:23:33.860279 Freq=933, CH1 RK0
5665 01:23:33.860329
5666 01:23:33.860380 DATLAT Default: 0xd
5667 01:23:33.860431 0, 0xFFFF, sum = 0
5668 01:23:33.860482 1, 0xFFFF, sum = 0
5669 01:23:33.860534 2, 0xFFFF, sum = 0
5670 01:23:33.860585 3, 0xFFFF, sum = 0
5671 01:23:33.860636 4, 0xFFFF, sum = 0
5672 01:23:33.860688 5, 0xFFFF, sum = 0
5673 01:23:33.860739 6, 0xFFFF, sum = 0
5674 01:23:33.860800 7, 0xFFFF, sum = 0
5675 01:23:33.860852 8, 0xFFFF, sum = 0
5676 01:23:33.860904 9, 0xFFFF, sum = 0
5677 01:23:33.860955 10, 0x0, sum = 1
5678 01:23:33.861007 11, 0x0, sum = 2
5679 01:23:33.861058 12, 0x0, sum = 3
5680 01:23:33.861110 13, 0x0, sum = 4
5681 01:23:33.861160 best_step = 11
5682 01:23:33.861211
5683 01:23:33.861262 ==
5684 01:23:33.861313 Dram Type= 6, Freq= 0, CH_1, rank 0
5685 01:23:33.861365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5686 01:23:33.861417 ==
5687 01:23:33.861467 RX Vref Scan: 1
5688 01:23:33.861518
5689 01:23:33.861584 RX Vref 0 -> 0, step: 1
5690 01:23:33.861650
5691 01:23:33.861701 RX Delay -45 -> 252, step: 4
5692 01:23:33.861751
5693 01:23:33.861802 Set Vref, RX VrefLevel [Byte0]: 54
5694 01:23:33.861853 [Byte1]: 54
5695 01:23:33.861904
5696 01:23:33.861954 Final RX Vref Byte 0 = 54 to rank0
5697 01:23:33.862005 Final RX Vref Byte 1 = 54 to rank0
5698 01:23:33.862056 Final RX Vref Byte 0 = 54 to rank1
5699 01:23:33.862107 Final RX Vref Byte 1 = 54 to rank1==
5700 01:23:33.862158 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 01:23:33.862209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 01:23:33.862260 ==
5703 01:23:33.862334 DQS Delay:
5704 01:23:33.862402 DQS0 = 0, DQS1 = 0
5705 01:23:33.862453 DQM Delay:
5706 01:23:33.862513 DQM0 = 103, DQM1 = 99
5707 01:23:33.862565 DQ Delay:
5708 01:23:33.862616 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =102
5709 01:23:33.862667 DQ4 =102, DQ5 =112, DQ6 =110, DQ7 =104
5710 01:23:33.862718 DQ8 =90, DQ9 =92, DQ10 =98, DQ11 =92
5711 01:23:33.862768 DQ12 =106, DQ13 =106, DQ14 =106, DQ15 =106
5712 01:23:33.862819
5713 01:23:33.862870
5714 01:23:33.862920 [DQSOSCAuto] RK0, (LSB)MR18= 0x142b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
5715 01:23:33.862973 CH1 RK0: MR19=505, MR18=142B
5716 01:23:33.863024 CH1_RK0: MR19=0x505, MR18=0x142B, DQSOSC=408, MR23=63, INC=65, DEC=43
5717 01:23:33.863075
5718 01:23:33.863126 ----->DramcWriteLeveling(PI) begin...
5719 01:23:33.863179 ==
5720 01:23:33.863230 Dram Type= 6, Freq= 0, CH_1, rank 1
5721 01:23:33.863285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 01:23:33.863368 ==
5723 01:23:33.863434 Write leveling (Byte 0): 27 => 27
5724 01:23:33.863485 Write leveling (Byte 1): 31 => 31
5725 01:23:33.863536 DramcWriteLeveling(PI) end<-----
5726 01:23:33.863586
5727 01:23:33.863637 ==
5728 01:23:33.863689 Dram Type= 6, Freq= 0, CH_1, rank 1
5729 01:23:33.863739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 01:23:33.863790 ==
5731 01:23:33.863841 [Gating] SW mode calibration
5732 01:23:33.863892 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5733 01:23:33.863943 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5734 01:23:33.863994 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5735 01:23:33.864045 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5736 01:23:33.864096 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5737 01:23:33.864147 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5738 01:23:33.864198 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5739 01:23:33.864258 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5740 01:23:33.864345 0 14 24 | B1->B0 | 2d2d 3333 | 1 1 | (1 1) (1 0)
5741 01:23:33.864430 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5742 01:23:33.864522 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5743 01:23:33.864573 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5744 01:23:33.864624 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5745 01:23:33.864675 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5746 01:23:33.864726 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5747 01:23:33.864777 0 15 20 | B1->B0 | 2625 2323 | 1 0 | (0 0) (0 0)
5748 01:23:33.864827 0 15 24 | B1->B0 | 3434 2828 | 0 0 | (0 0) (0 0)
5749 01:23:33.864878 0 15 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
5750 01:23:33.864929 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5751 01:23:33.864980 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5752 01:23:33.865031 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5753 01:23:33.865082 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5754 01:23:33.865133 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5755 01:23:33.865183 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5756 01:23:33.865234 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5757 01:23:33.865284 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5758 01:23:33.865335 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5759 01:23:33.865390 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5760 01:23:33.865448 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5761 01:23:33.865522 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 01:23:33.865588 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 01:23:33.865639 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 01:23:33.865892 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 01:23:33.865965 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 01:23:33.866019 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 01:23:33.866071 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 01:23:33.866123 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 01:23:33.866174 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 01:23:33.866226 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 01:23:33.866276 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5772 01:23:33.866368 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5773 01:23:33.866420 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 01:23:33.866471 Total UI for P1: 0, mck2ui 16
5775 01:23:33.866522 best dqsien dly found for B0: ( 1, 2, 24)
5776 01:23:33.866573 Total UI for P1: 0, mck2ui 16
5777 01:23:33.866625 best dqsien dly found for B1: ( 1, 2, 22)
5778 01:23:33.866675 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5779 01:23:33.866726 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5780 01:23:33.866777
5781 01:23:33.866828 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5782 01:23:33.866879 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5783 01:23:33.866930 [Gating] SW calibration Done
5784 01:23:33.866980 ==
5785 01:23:33.867031 Dram Type= 6, Freq= 0, CH_1, rank 1
5786 01:23:33.867082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5787 01:23:33.867134 ==
5788 01:23:33.867185 RX Vref Scan: 0
5789 01:23:33.867235
5790 01:23:33.867288 RX Vref 0 -> 0, step: 1
5791 01:23:33.867340
5792 01:23:33.867390 RX Delay -80 -> 252, step: 8
5793 01:23:33.867441 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5794 01:23:33.867495 iDelay=208, Bit 1, Center 103 (16 ~ 191) 176
5795 01:23:33.867553 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5796 01:23:33.867605 iDelay=208, Bit 3, Center 99 (16 ~ 183) 168
5797 01:23:33.867655 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5798 01:23:33.867706 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5799 01:23:33.867778 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5800 01:23:33.867860 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5801 01:23:33.867927 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5802 01:23:33.868003 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5803 01:23:33.868070 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5804 01:23:33.868120 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5805 01:23:33.868172 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5806 01:23:33.868222 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5807 01:23:33.868273 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5808 01:23:33.868323 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5809 01:23:33.868374 ==
5810 01:23:33.868426 Dram Type= 6, Freq= 0, CH_1, rank 1
5811 01:23:33.868477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5812 01:23:33.868529 ==
5813 01:23:33.868579 DQS Delay:
5814 01:23:33.868630 DQS0 = 0, DQS1 = 0
5815 01:23:33.868681 DQM Delay:
5816 01:23:33.868732 DQM0 = 103, DQM1 = 99
5817 01:23:33.868783 DQ Delay:
5818 01:23:33.868834 DQ0 =107, DQ1 =103, DQ2 =91, DQ3 =99
5819 01:23:33.868885 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =103
5820 01:23:33.868936 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5821 01:23:33.868987 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5822 01:23:33.869038
5823 01:23:33.869088
5824 01:23:33.869141 ==
5825 01:23:33.869193 Dram Type= 6, Freq= 0, CH_1, rank 1
5826 01:23:33.869244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5827 01:23:33.869295 ==
5828 01:23:33.869346
5829 01:23:33.869404
5830 01:23:33.869455 TX Vref Scan disable
5831 01:23:33.869509 == TX Byte 0 ==
5832 01:23:33.869609 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5833 01:23:33.869705 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5834 01:23:33.869756 == TX Byte 1 ==
5835 01:23:33.869807 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5836 01:23:33.869857 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5837 01:23:33.869908 ==
5838 01:23:33.869958 Dram Type= 6, Freq= 0, CH_1, rank 1
5839 01:23:33.870010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5840 01:23:33.870061 ==
5841 01:23:33.870111
5842 01:23:33.870161
5843 01:23:33.870212 TX Vref Scan disable
5844 01:23:33.870262 == TX Byte 0 ==
5845 01:23:33.870342 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5846 01:23:33.870409 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5847 01:23:33.870460 == TX Byte 1 ==
5848 01:23:33.870510 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5849 01:23:33.870561 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5850 01:23:33.870611
5851 01:23:33.870662 [DATLAT]
5852 01:23:33.870712 Freq=933, CH1 RK1
5853 01:23:33.870763
5854 01:23:33.870814 DATLAT Default: 0xb
5855 01:23:33.870864 0, 0xFFFF, sum = 0
5856 01:23:33.870916 1, 0xFFFF, sum = 0
5857 01:23:33.870968 2, 0xFFFF, sum = 0
5858 01:23:33.871029 3, 0xFFFF, sum = 0
5859 01:23:33.871126 4, 0xFFFF, sum = 0
5860 01:23:33.871235 5, 0xFFFF, sum = 0
5861 01:23:33.871288 6, 0xFFFF, sum = 0
5862 01:23:33.871340 7, 0xFFFF, sum = 0
5863 01:23:33.871392 8, 0xFFFF, sum = 0
5864 01:23:33.871444 9, 0xFFFF, sum = 0
5865 01:23:33.871499 10, 0x0, sum = 1
5866 01:23:33.871556 11, 0x0, sum = 2
5867 01:23:33.871616 12, 0x0, sum = 3
5868 01:23:33.871684 13, 0x0, sum = 4
5869 01:23:33.871769 best_step = 11
5870 01:23:33.871833
5871 01:23:33.871884 ==
5872 01:23:33.871935 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 01:23:33.871987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 01:23:33.872038 ==
5875 01:23:33.872090 RX Vref Scan: 0
5876 01:23:33.872141
5877 01:23:33.872191 RX Vref 0 -> 0, step: 1
5878 01:23:33.872242
5879 01:23:33.872292 RX Delay -45 -> 252, step: 4
5880 01:23:33.872343 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5881 01:23:33.872393 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5882 01:23:33.872445 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5883 01:23:33.872497 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5884 01:23:33.872548 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5885 01:23:33.872599 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5886 01:23:33.872649 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5887 01:23:33.872708 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5888 01:23:33.872760 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5889 01:23:33.872811 iDelay=203, Bit 9, Center 90 (7 ~ 174) 168
5890 01:23:33.872862 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5891 01:23:33.872913 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5892 01:23:33.872964 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5893 01:23:33.873015 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5894 01:23:33.873066 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5895 01:23:33.873117 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5896 01:23:33.873167 ==
5897 01:23:33.873219 Dram Type= 6, Freq= 0, CH_1, rank 1
5898 01:23:33.873473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5899 01:23:33.873601 ==
5900 01:23:33.873726 DQS Delay:
5901 01:23:33.873878 DQS0 = 0, DQS1 = 0
5902 01:23:33.874029 DQM Delay:
5903 01:23:33.874155 DQM0 = 104, DQM1 = 100
5904 01:23:33.874309 DQ Delay:
5905 01:23:33.874451 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5906 01:23:33.874576 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102
5907 01:23:33.874656 DQ8 =90, DQ9 =90, DQ10 =102, DQ11 =94
5908 01:23:33.874710 DQ12 =110, DQ13 =106, DQ14 =104, DQ15 =108
5909 01:23:33.874762
5910 01:23:33.874814
5911 01:23:33.874865 [DQSOSCAuto] RK1, (LSB)MR18= 0x28fc, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 409 ps
5912 01:23:33.874918 CH1 RK1: MR19=504, MR18=28FC
5913 01:23:33.874970 CH1_RK1: MR19=0x504, MR18=0x28FC, DQSOSC=409, MR23=63, INC=64, DEC=43
5914 01:23:33.875022 [RxdqsGatingPostProcess] freq 933
5915 01:23:33.875073 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5916 01:23:33.875124 best DQS0 dly(2T, 0.5T) = (0, 10)
5917 01:23:33.875200 best DQS1 dly(2T, 0.5T) = (0, 10)
5918 01:23:33.875276 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5919 01:23:33.875343 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5920 01:23:33.875394 best DQS0 dly(2T, 0.5T) = (0, 10)
5921 01:23:34.001765 best DQS1 dly(2T, 0.5T) = (0, 10)
5922 01:23:34.001894 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5923 01:23:34.001959 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5924 01:23:34.002018 Pre-setting of DQS Precalculation
5925 01:23:34.002076 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5926 01:23:34.002132 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5927 01:23:34.002188 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5928 01:23:34.002241
5929 01:23:34.002295
5930 01:23:34.002386 [Calibration Summary] 1866 Mbps
5931 01:23:34.002438 CH 0, Rank 0
5932 01:23:34.002491 SW Impedance : PASS
5933 01:23:34.002544 DUTY Scan : NO K
5934 01:23:34.002596 ZQ Calibration : PASS
5935 01:23:34.002647 Jitter Meter : NO K
5936 01:23:34.002699 CBT Training : PASS
5937 01:23:34.002749 Write leveling : PASS
5938 01:23:34.002800 RX DQS gating : PASS
5939 01:23:34.002851 RX DQ/DQS(RDDQC) : PASS
5940 01:23:34.002902 TX DQ/DQS : PASS
5941 01:23:34.002953 RX DATLAT : PASS
5942 01:23:34.003004 RX DQ/DQS(Engine): PASS
5943 01:23:34.003054 TX OE : NO K
5944 01:23:34.003106 All Pass.
5945 01:23:34.003157
5946 01:23:34.003207 CH 0, Rank 1
5947 01:23:34.003258 SW Impedance : PASS
5948 01:23:34.003310 DUTY Scan : NO K
5949 01:23:34.003361 ZQ Calibration : PASS
5950 01:23:34.003412 Jitter Meter : NO K
5951 01:23:34.003463 CBT Training : PASS
5952 01:23:34.003514 Write leveling : PASS
5953 01:23:34.003565 RX DQS gating : PASS
5954 01:23:34.003625 RX DQ/DQS(RDDQC) : PASS
5955 01:23:34.003677 TX DQ/DQS : PASS
5956 01:23:34.003728 RX DATLAT : PASS
5957 01:23:34.003779 RX DQ/DQS(Engine): PASS
5958 01:23:34.003830 TX OE : NO K
5959 01:23:34.003880 All Pass.
5960 01:23:34.003931
5961 01:23:34.003982 CH 1, Rank 0
5962 01:23:34.004032 SW Impedance : PASS
5963 01:23:34.004084 DUTY Scan : NO K
5964 01:23:34.004134 ZQ Calibration : PASS
5965 01:23:34.004202 Jitter Meter : NO K
5966 01:23:34.004266 CBT Training : PASS
5967 01:23:34.004317 Write leveling : PASS
5968 01:23:34.004367 RX DQS gating : PASS
5969 01:23:34.004417 RX DQ/DQS(RDDQC) : PASS
5970 01:23:34.004468 TX DQ/DQS : PASS
5971 01:23:34.004520 RX DATLAT : PASS
5972 01:23:34.004570 RX DQ/DQS(Engine): PASS
5973 01:23:34.004620 TX OE : NO K
5974 01:23:34.004672 All Pass.
5975 01:23:34.004722
5976 01:23:34.004773 CH 1, Rank 1
5977 01:23:34.004823 SW Impedance : PASS
5978 01:23:34.004874 DUTY Scan : NO K
5979 01:23:34.004924 ZQ Calibration : PASS
5980 01:23:34.004975 Jitter Meter : NO K
5981 01:23:34.005025 CBT Training : PASS
5982 01:23:34.005085 Write leveling : PASS
5983 01:23:34.005136 RX DQS gating : PASS
5984 01:23:34.005187 RX DQ/DQS(RDDQC) : PASS
5985 01:23:34.005238 TX DQ/DQS : PASS
5986 01:23:34.005289 RX DATLAT : PASS
5987 01:23:34.005339 RX DQ/DQS(Engine): PASS
5988 01:23:34.005390 TX OE : NO K
5989 01:23:34.005441 All Pass.
5990 01:23:34.005492
5991 01:23:34.005542 DramC Write-DBI off
5992 01:23:34.005593 PER_BANK_REFRESH: Hybrid Mode
5993 01:23:34.005644 TX_TRACKING: ON
5994 01:23:34.005696 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5995 01:23:34.005748 [FAST_K] Save calibration result to emmc
5996 01:23:34.005799 dramc_set_vcore_voltage set vcore to 650000
5997 01:23:34.005850 Read voltage for 400, 6
5998 01:23:34.005901 Vio18 = 0
5999 01:23:34.005952 Vcore = 650000
6000 01:23:34.006003 Vdram = 0
6001 01:23:34.006054 Vddq = 0
6002 01:23:34.006104 Vmddr = 0
6003 01:23:34.006155 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6004 01:23:34.006207 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6005 01:23:34.006258 MEM_TYPE=3, freq_sel=20
6006 01:23:34.006332 sv_algorithm_assistance_LP4_800
6007 01:23:34.006399 ============ PULL DRAM RESETB DOWN ============
6008 01:23:34.006450 ========== PULL DRAM RESETB DOWN end =========
6009 01:23:34.006502 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6010 01:23:34.006553 ===================================
6011 01:23:34.006604 LPDDR4 DRAM CONFIGURATION
6012 01:23:34.006654 ===================================
6013 01:23:34.006705 EX_ROW_EN[0] = 0x0
6014 01:23:34.006756 EX_ROW_EN[1] = 0x0
6015 01:23:34.006807 LP4Y_EN = 0x0
6016 01:23:34.006857 WORK_FSP = 0x0
6017 01:23:34.006907 WL = 0x2
6018 01:23:34.006958 RL = 0x2
6019 01:23:34.007009 BL = 0x2
6020 01:23:34.007068 RPST = 0x0
6021 01:23:34.007120 RD_PRE = 0x0
6022 01:23:34.007170 WR_PRE = 0x1
6023 01:23:34.007221 WR_PST = 0x0
6024 01:23:34.007271 DBI_WR = 0x0
6025 01:23:34.007322 DBI_RD = 0x0
6026 01:23:34.007372 OTF = 0x1
6027 01:23:34.007423 ===================================
6028 01:23:34.007475 ===================================
6029 01:23:34.007542 ANA top config
6030 01:23:34.007606 ===================================
6031 01:23:34.007657 DLL_ASYNC_EN = 0
6032 01:23:34.007709 ALL_SLAVE_EN = 1
6033 01:23:34.007760 NEW_RANK_MODE = 1
6034 01:23:34.007811 DLL_IDLE_MODE = 1
6035 01:23:34.007862 LP45_APHY_COMB_EN = 1
6036 01:23:34.007913 TX_ODT_DIS = 1
6037 01:23:34.007964 NEW_8X_MODE = 1
6038 01:23:34.008016 ===================================
6039 01:23:34.008067 ===================================
6040 01:23:34.008117 data_rate = 800
6041 01:23:34.008168 CKR = 1
6042 01:23:34.008220 DQ_P2S_RATIO = 4
6043 01:23:34.008275 ===================================
6044 01:23:34.008565 CA_P2S_RATIO = 4
6045 01:23:34.008720 DQ_CA_OPEN = 0
6046 01:23:34.008848 DQ_SEMI_OPEN = 1
6047 01:23:34.009003 CA_SEMI_OPEN = 1
6048 01:23:34.009159 CA_FULL_RATE = 0
6049 01:23:34.009258 DQ_CKDIV4_EN = 0
6050 01:23:34.009327 CA_CKDIV4_EN = 1
6051 01:23:34.009397 CA_PREDIV_EN = 0
6052 01:23:34.009480 PH8_DLY = 0
6053 01:23:34.009547 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6054 01:23:34.009599 DQ_AAMCK_DIV = 0
6055 01:23:34.009651 CA_AAMCK_DIV = 0
6056 01:23:34.009703 CA_ADMCK_DIV = 4
6057 01:23:34.009755 DQ_TRACK_CA_EN = 0
6058 01:23:34.009807 CA_PICK = 800
6059 01:23:34.009859 CA_MCKIO = 400
6060 01:23:34.009910 MCKIO_SEMI = 400
6061 01:23:34.009962 PLL_FREQ = 3016
6062 01:23:34.010013 DQ_UI_PI_RATIO = 32
6063 01:23:34.010064 CA_UI_PI_RATIO = 32
6064 01:23:34.010115 ===================================
6065 01:23:34.010167 ===================================
6066 01:23:34.010219 memory_type:LPDDR4
6067 01:23:34.010270 GP_NUM : 10
6068 01:23:34.010347 SRAM_EN : 1
6069 01:23:34.010414 MD32_EN : 0
6070 01:23:34.010466 ===================================
6071 01:23:34.010517 [ANA_INIT] >>>>>>>>>>>>>>
6072 01:23:34.010568 <<<<<< [CONFIGURE PHASE]: ANA_TX
6073 01:23:34.010621 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6074 01:23:34.010683 ===================================
6075 01:23:34.010751 data_rate = 800,PCW = 0X7400
6076 01:23:34.010818 ===================================
6077 01:23:34.010870 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6078 01:23:34.010922 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6079 01:23:34.010974 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6080 01:23:34.011028 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6081 01:23:34.011079 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6082 01:23:34.011130 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6083 01:23:34.011183 [ANA_INIT] flow start
6084 01:23:34.011234 [ANA_INIT] PLL >>>>>>>>
6085 01:23:34.011286 [ANA_INIT] PLL <<<<<<<<
6086 01:23:34.011337 [ANA_INIT] MIDPI >>>>>>>>
6087 01:23:34.011389 [ANA_INIT] MIDPI <<<<<<<<
6088 01:23:34.011440 [ANA_INIT] DLL >>>>>>>>
6089 01:23:34.011492 [ANA_INIT] flow end
6090 01:23:34.011543 ============ LP4 DIFF to SE enter ============
6091 01:23:34.011595 ============ LP4 DIFF to SE exit ============
6092 01:23:34.011647 [ANA_INIT] <<<<<<<<<<<<<
6093 01:23:34.011698 [Flow] Enable top DCM control >>>>>
6094 01:23:34.011749 [Flow] Enable top DCM control <<<<<
6095 01:23:34.011801 Enable DLL master slave shuffle
6096 01:23:34.011853 ==============================================================
6097 01:23:34.011905 Gating Mode config
6098 01:23:34.011957 ==============================================================
6099 01:23:34.012009 Config description:
6100 01:23:34.012061 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6101 01:23:34.012115 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6102 01:23:34.012167 SELPH_MODE 0: By rank 1: By Phase
6103 01:23:34.012229 ==============================================================
6104 01:23:34.012291 GAT_TRACK_EN = 0
6105 01:23:34.012372 RX_GATING_MODE = 2
6106 01:23:34.012438 RX_GATING_TRACK_MODE = 2
6107 01:23:34.012490 SELPH_MODE = 1
6108 01:23:34.012542 PICG_EARLY_EN = 1
6109 01:23:34.012593 VALID_LAT_VALUE = 1
6110 01:23:34.012645 ==============================================================
6111 01:23:34.012697 Enter into Gating configuration >>>>
6112 01:23:34.012748 Exit from Gating configuration <<<<
6113 01:23:34.012800 Enter into DVFS_PRE_config >>>>>
6114 01:23:34.012851 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6115 01:23:34.012904 Exit from DVFS_PRE_config <<<<<
6116 01:23:34.012956 Enter into PICG configuration >>>>
6117 01:23:34.013008 Exit from PICG configuration <<<<
6118 01:23:34.013059 [RX_INPUT] configuration >>>>>
6119 01:23:34.013111 [RX_INPUT] configuration <<<<<
6120 01:23:34.013162 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6121 01:23:34.013214 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6122 01:23:34.013266 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6123 01:23:34.013318 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6124 01:23:34.013370 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6125 01:23:34.013422 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6126 01:23:34.013483 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6127 01:23:34.013535 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6128 01:23:34.013587 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6129 01:23:34.013639 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6130 01:23:34.013690 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6131 01:23:34.013742 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6132 01:23:34.013794 ===================================
6133 01:23:34.013846 LPDDR4 DRAM CONFIGURATION
6134 01:23:34.013897 ===================================
6135 01:23:34.013949 EX_ROW_EN[0] = 0x0
6136 01:23:34.014000 EX_ROW_EN[1] = 0x0
6137 01:23:34.014051 LP4Y_EN = 0x0
6138 01:23:34.014102 WORK_FSP = 0x0
6139 01:23:34.014152 WL = 0x2
6140 01:23:34.014203 RL = 0x2
6141 01:23:34.014254 BL = 0x2
6142 01:23:34.014328 RPST = 0x0
6143 01:23:34.014401 RD_PRE = 0x0
6144 01:23:34.014459 WR_PRE = 0x1
6145 01:23:34.014510 WR_PST = 0x0
6146 01:23:34.014561 DBI_WR = 0x0
6147 01:23:34.014612 DBI_RD = 0x0
6148 01:23:34.014881 OTF = 0x1
6149 01:23:34.015013 ===================================
6150 01:23:34.015141 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6151 01:23:34.015267 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6152 01:23:34.015393 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6153 01:23:34.015461 ===================================
6154 01:23:34.015515 LPDDR4 DRAM CONFIGURATION
6155 01:23:34.015568 ===================================
6156 01:23:34.015620 EX_ROW_EN[0] = 0x10
6157 01:23:34.015672 EX_ROW_EN[1] = 0x0
6158 01:23:34.015723 LP4Y_EN = 0x0
6159 01:23:34.015775 WORK_FSP = 0x0
6160 01:23:34.015825 WL = 0x2
6161 01:23:34.015877 RL = 0x2
6162 01:23:34.015928 BL = 0x2
6163 01:23:34.015979 RPST = 0x0
6164 01:23:34.016030 RD_PRE = 0x0
6165 01:23:34.016081 WR_PRE = 0x1
6166 01:23:34.016132 WR_PST = 0x0
6167 01:23:34.016183 DBI_WR = 0x0
6168 01:23:34.016234 DBI_RD = 0x0
6169 01:23:34.016306 OTF = 0x1
6170 01:23:34.016376 ===================================
6171 01:23:34.016457 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6172 01:23:34.016540 nWR fixed to 30
6173 01:23:34.016625 [ModeRegInit_LP4] CH0 RK0
6174 01:23:34.016677 [ModeRegInit_LP4] CH0 RK1
6175 01:23:34.016760 [ModeRegInit_LP4] CH1 RK0
6176 01:23:34.016853 [ModeRegInit_LP4] CH1 RK1
6177 01:23:34.016907 match AC timing 19
6178 01:23:34.016959 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6179 01:23:34.017012 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6180 01:23:34.017065 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6181 01:23:34.017118 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6182 01:23:34.017170 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6183 01:23:34.017223 ==
6184 01:23:34.017277 Dram Type= 6, Freq= 0, CH_0, rank 0
6185 01:23:34.017330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6186 01:23:34.017383 ==
6187 01:23:34.017437 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6188 01:23:34.017490 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6189 01:23:34.017543 [CA 0] Center 36 (8~64) winsize 57
6190 01:23:34.017595 [CA 1] Center 36 (8~64) winsize 57
6191 01:23:34.017647 [CA 2] Center 36 (8~64) winsize 57
6192 01:23:34.017700 [CA 3] Center 36 (8~64) winsize 57
6193 01:23:34.017753 [CA 4] Center 36 (8~64) winsize 57
6194 01:23:34.017815 [CA 5] Center 36 (8~64) winsize 57
6195 01:23:34.017869
6196 01:23:34.017922 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6197 01:23:34.017975
6198 01:23:34.018028 [CATrainingPosCal] consider 1 rank data
6199 01:23:34.018090 u2DelayCellTimex100 = 270/100 ps
6200 01:23:34.018143 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6201 01:23:34.018195 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6202 01:23:34.018248 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6203 01:23:34.018309 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6204 01:23:34.018365 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6205 01:23:34.018427 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6206 01:23:34.018480
6207 01:23:34.018533 CA PerBit enable=1, Macro0, CA PI delay=36
6208 01:23:34.018586
6209 01:23:34.018639 [CBTSetCACLKResult] CA Dly = 36
6210 01:23:34.018692 CS Dly: 1 (0~32)
6211 01:23:34.018744 ==
6212 01:23:34.018797 Dram Type= 6, Freq= 0, CH_0, rank 1
6213 01:23:34.018850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6214 01:23:34.018903 ==
6215 01:23:34.018957 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6216 01:23:34.019009 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6217 01:23:34.019063 [CA 0] Center 36 (8~64) winsize 57
6218 01:23:34.019115 [CA 1] Center 36 (8~64) winsize 57
6219 01:23:34.019168 [CA 2] Center 36 (8~64) winsize 57
6220 01:23:34.019221 [CA 3] Center 36 (8~64) winsize 57
6221 01:23:34.019273 [CA 4] Center 36 (8~64) winsize 57
6222 01:23:34.019326 [CA 5] Center 36 (8~64) winsize 57
6223 01:23:34.019379
6224 01:23:34.019432 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6225 01:23:34.019485
6226 01:23:34.019537 [CATrainingPosCal] consider 2 rank data
6227 01:23:34.019590 u2DelayCellTimex100 = 270/100 ps
6228 01:23:34.019643 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 01:23:34.019695 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 01:23:34.019749 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 01:23:34.019801 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 01:23:34.019854 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 01:23:34.019906 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 01:23:34.019959
6235 01:23:34.020012 CA PerBit enable=1, Macro0, CA PI delay=36
6236 01:23:34.020074
6237 01:23:34.020127 [CBTSetCACLKResult] CA Dly = 36
6238 01:23:34.020180 CS Dly: 1 (0~32)
6239 01:23:34.020233
6240 01:23:34.020286 ----->DramcWriteLeveling(PI) begin...
6241 01:23:34.020341 ==
6242 01:23:34.020398 Dram Type= 6, Freq= 0, CH_0, rank 0
6243 01:23:34.020492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6244 01:23:34.020559 ==
6245 01:23:34.020611 Write leveling (Byte 0): 40 => 8
6246 01:23:34.020662 Write leveling (Byte 1): 40 => 8
6247 01:23:34.020713 DramcWriteLeveling(PI) end<-----
6248 01:23:34.020764
6249 01:23:34.020816 ==
6250 01:23:34.020867 Dram Type= 6, Freq= 0, CH_0, rank 0
6251 01:23:34.020920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6252 01:23:34.020972 ==
6253 01:23:34.021050 [Gating] SW mode calibration
6254 01:23:34.021103 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6255 01:23:34.021157 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6256 01:23:34.021210 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6257 01:23:34.021263 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6258 01:23:34.021329 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6259 01:23:34.021381 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6260 01:23:34.021432 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6261 01:23:34.021483 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6262 01:23:34.021535 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6263 01:23:34.021587 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6264 01:23:34.021638 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6265 01:23:34.021689 Total UI for P1: 0, mck2ui 16
6266 01:23:34.021741 best dqsien dly found for B0: ( 0, 14, 24)
6267 01:23:34.021793 Total UI for P1: 0, mck2ui 16
6268 01:23:34.021844 best dqsien dly found for B1: ( 0, 14, 24)
6269 01:23:34.021896 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6270 01:23:34.022150 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6271 01:23:34.022278
6272 01:23:34.022513 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6273 01:23:34.022658 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6274 01:23:34.022784 [Gating] SW calibration Done
6275 01:23:34.022883 ==
6276 01:23:34.022939 Dram Type= 6, Freq= 0, CH_0, rank 0
6277 01:23:34.022992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6278 01:23:34.023046 ==
6279 01:23:34.023099 RX Vref Scan: 0
6280 01:23:34.023151
6281 01:23:34.023203 RX Vref 0 -> 0, step: 1
6282 01:23:34.023263
6283 01:23:34.023316 RX Delay -410 -> 252, step: 16
6284 01:23:34.023368 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6285 01:23:34.023420 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6286 01:23:34.023471 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6287 01:23:34.023522 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6288 01:23:34.023574 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6289 01:23:34.023625 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6290 01:23:34.023676 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6291 01:23:34.023727 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6292 01:23:34.023778 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6293 01:23:34.023830 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6294 01:23:34.023881 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6295 01:23:34.023932 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6296 01:23:34.023984 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6297 01:23:34.024035 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6298 01:23:34.024086 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6299 01:23:34.024137 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6300 01:23:34.024188 ==
6301 01:23:34.024239 Dram Type= 6, Freq= 0, CH_0, rank 0
6302 01:23:34.024353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6303 01:23:34.024427 ==
6304 01:23:34.024515 DQS Delay:
6305 01:23:34.024610 DQS0 = 27, DQS1 = 35
6306 01:23:34.024696 DQM Delay:
6307 01:23:34.024792 DQM0 = 9, DQM1 = 11
6308 01:23:34.024873 DQ Delay:
6309 01:23:34.024955 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6310 01:23:34.025016 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6311 01:23:34.025069 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6312 01:23:34.025121 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6313 01:23:34.025172
6314 01:23:34.025233
6315 01:23:34.025286 ==
6316 01:23:34.025337 Dram Type= 6, Freq= 0, CH_0, rank 0
6317 01:23:34.025389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6318 01:23:34.025441 ==
6319 01:23:34.025492
6320 01:23:34.025543
6321 01:23:34.025594 TX Vref Scan disable
6322 01:23:34.025645 == TX Byte 0 ==
6323 01:23:34.025697 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6324 01:23:34.025748 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6325 01:23:34.025799 == TX Byte 1 ==
6326 01:23:34.025850 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6327 01:23:34.025901 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6328 01:23:34.025952 ==
6329 01:23:34.026003 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 01:23:34.026054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 01:23:34.026105 ==
6332 01:23:34.026156
6333 01:23:34.026207
6334 01:23:34.026258 TX Vref Scan disable
6335 01:23:34.026336 == TX Byte 0 ==
6336 01:23:34.026409 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6337 01:23:34.026492 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6338 01:23:34.026567 == TX Byte 1 ==
6339 01:23:34.026618 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6340 01:23:34.026670 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6341 01:23:34.026721
6342 01:23:34.026771 [DATLAT]
6343 01:23:34.026822 Freq=400, CH0 RK0
6344 01:23:34.026873
6345 01:23:34.026924 DATLAT Default: 0xf
6346 01:23:34.026975 0, 0xFFFF, sum = 0
6347 01:23:34.027028 1, 0xFFFF, sum = 0
6348 01:23:34.027117 2, 0xFFFF, sum = 0
6349 01:23:34.027192 3, 0xFFFF, sum = 0
6350 01:23:34.027246 4, 0xFFFF, sum = 0
6351 01:23:34.027300 5, 0xFFFF, sum = 0
6352 01:23:34.027353 6, 0xFFFF, sum = 0
6353 01:23:34.027406 7, 0xFFFF, sum = 0
6354 01:23:34.027460 8, 0xFFFF, sum = 0
6355 01:23:34.027526 9, 0xFFFF, sum = 0
6356 01:23:34.027578 10, 0xFFFF, sum = 0
6357 01:23:34.027630 11, 0xFFFF, sum = 0
6358 01:23:34.027682 12, 0xFFFF, sum = 0
6359 01:23:34.027733 13, 0x0, sum = 1
6360 01:23:34.027785 14, 0x0, sum = 2
6361 01:23:34.027837 15, 0x0, sum = 3
6362 01:23:34.027889 16, 0x0, sum = 4
6363 01:23:34.027940 best_step = 14
6364 01:23:34.027991
6365 01:23:34.028043 ==
6366 01:23:34.028094 Dram Type= 6, Freq= 0, CH_0, rank 0
6367 01:23:34.028145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6368 01:23:34.028197 ==
6369 01:23:34.028248 RX Vref Scan: 1
6370 01:23:34.028299
6371 01:23:34.028349 RX Vref 0 -> 0, step: 1
6372 01:23:34.028400
6373 01:23:34.028451 RX Delay -311 -> 252, step: 8
6374 01:23:34.028507
6375 01:23:34.028564 Set Vref, RX VrefLevel [Byte0]: 56
6376 01:23:34.028666 [Byte1]: 50
6377 01:23:34.028744
6378 01:23:34.028819 Final RX Vref Byte 0 = 56 to rank0
6379 01:23:34.028887 Final RX Vref Byte 1 = 50 to rank0
6380 01:23:34.028942 Final RX Vref Byte 0 = 56 to rank1
6381 01:23:34.028994 Final RX Vref Byte 1 = 50 to rank1==
6382 01:23:34.029046 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 01:23:34.029097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 01:23:34.029149 ==
6385 01:23:34.029201 DQS Delay:
6386 01:23:34.029252 DQS0 = 28, DQS1 = 36
6387 01:23:34.029303 DQM Delay:
6388 01:23:34.029354 DQM0 = 10, DQM1 = 13
6389 01:23:34.029405 DQ Delay:
6390 01:23:34.029456 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6391 01:23:34.029507 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6392 01:23:34.029558 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6393 01:23:34.029609 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6394 01:23:34.029660
6395 01:23:34.029710
6396 01:23:34.029761 [DQSOSCAuto] RK0, (LSB)MR18= 0xc8b6, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6397 01:23:34.029824 CH0 RK0: MR19=C0C, MR18=C8B6
6398 01:23:34.029876 CH0_RK0: MR19=0xC0C, MR18=0xC8B6, DQSOSC=385, MR23=63, INC=398, DEC=265
6399 01:23:34.029928 ==
6400 01:23:34.029979 Dram Type= 6, Freq= 0, CH_0, rank 1
6401 01:23:34.030031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 01:23:34.030082 ==
6403 01:23:34.030134 [Gating] SW mode calibration
6404 01:23:34.030184 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6405 01:23:34.030236 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6406 01:23:34.030288 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6407 01:23:34.030393 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6408 01:23:34.030444 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6409 01:23:34.030495 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6410 01:23:34.030546 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6411 01:23:34.030598 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6412 01:23:34.030648 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6413 01:23:34.030905 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6414 01:23:34.031077 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6415 01:23:34.031205 Total UI for P1: 0, mck2ui 16
6416 01:23:34.031332 best dqsien dly found for B0: ( 0, 14, 24)
6417 01:23:34.031471 Total UI for P1: 0, mck2ui 16
6418 01:23:34.031537 best dqsien dly found for B1: ( 0, 14, 24)
6419 01:23:34.031591 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6420 01:23:34.031643 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6421 01:23:34.031694
6422 01:23:34.031746 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6423 01:23:34.031798 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6424 01:23:34.031848 [Gating] SW calibration Done
6425 01:23:34.031899 ==
6426 01:23:34.031949 Dram Type= 6, Freq= 0, CH_0, rank 1
6427 01:23:34.032001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6428 01:23:34.032052 ==
6429 01:23:34.032103 RX Vref Scan: 0
6430 01:23:34.032154
6431 01:23:34.032205 RX Vref 0 -> 0, step: 1
6432 01:23:34.032256
6433 01:23:34.032306 RX Delay -410 -> 252, step: 16
6434 01:23:34.032358 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6435 01:23:34.032409 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6436 01:23:34.032460 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6437 01:23:34.032510 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6438 01:23:34.032561 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6439 01:23:34.032612 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6440 01:23:34.032663 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6441 01:23:34.032713 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6442 01:23:34.032765 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6443 01:23:34.032816 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6444 01:23:34.032867 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6445 01:23:34.032918 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6446 01:23:34.032969 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6447 01:23:34.033019 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6448 01:23:34.033070 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6449 01:23:34.033121 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6450 01:23:34.033172 ==
6451 01:23:34.033223 Dram Type= 6, Freq= 0, CH_0, rank 1
6452 01:23:34.033274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6453 01:23:34.033326 ==
6454 01:23:34.033387 DQS Delay:
6455 01:23:34.033438 DQS0 = 27, DQS1 = 35
6456 01:23:34.033489 DQM Delay:
6457 01:23:34.033541 DQM0 = 12, DQM1 = 12
6458 01:23:34.033593 DQ Delay:
6459 01:23:34.033643 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6460 01:23:34.033694 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6461 01:23:34.033745 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6462 01:23:34.033796 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6463 01:23:34.033846
6464 01:23:34.033897
6465 01:23:34.033947 ==
6466 01:23:34.033997 Dram Type= 6, Freq= 0, CH_0, rank 1
6467 01:23:34.034049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6468 01:23:34.034100 ==
6469 01:23:34.034151
6470 01:23:34.034201
6471 01:23:34.034251 TX Vref Scan disable
6472 01:23:34.034311 == TX Byte 0 ==
6473 01:23:34.034398 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6474 01:23:34.034450 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6475 01:23:34.034502 == TX Byte 1 ==
6476 01:23:34.034562 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6477 01:23:34.034644 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6478 01:23:34.034695 ==
6479 01:23:34.034746 Dram Type= 6, Freq= 0, CH_0, rank 1
6480 01:23:34.034798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 01:23:34.034850 ==
6482 01:23:34.034901
6483 01:23:34.034960
6484 01:23:34.035011 TX Vref Scan disable
6485 01:23:34.035062 == TX Byte 0 ==
6486 01:23:34.035113 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6487 01:23:34.035164 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6488 01:23:34.035215 == TX Byte 1 ==
6489 01:23:34.035266 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6490 01:23:34.035317 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6491 01:23:34.035367
6492 01:23:34.035419 [DATLAT]
6493 01:23:34.035470 Freq=400, CH0 RK1
6494 01:23:34.035521
6495 01:23:34.035572 DATLAT Default: 0xe
6496 01:23:34.035623 0, 0xFFFF, sum = 0
6497 01:23:34.035675 1, 0xFFFF, sum = 0
6498 01:23:34.035727 2, 0xFFFF, sum = 0
6499 01:23:34.035778 3, 0xFFFF, sum = 0
6500 01:23:34.035830 4, 0xFFFF, sum = 0
6501 01:23:34.035882 5, 0xFFFF, sum = 0
6502 01:23:34.035933 6, 0xFFFF, sum = 0
6503 01:23:34.035984 7, 0xFFFF, sum = 0
6504 01:23:34.036036 8, 0xFFFF, sum = 0
6505 01:23:34.036087 9, 0xFFFF, sum = 0
6506 01:23:34.036138 10, 0xFFFF, sum = 0
6507 01:23:34.036190 11, 0xFFFF, sum = 0
6508 01:23:34.036241 12, 0xFFFF, sum = 0
6509 01:23:34.036292 13, 0x0, sum = 1
6510 01:23:34.036343 14, 0x0, sum = 2
6511 01:23:34.036395 15, 0x0, sum = 3
6512 01:23:34.036447 16, 0x0, sum = 4
6513 01:23:34.036498 best_step = 14
6514 01:23:34.036549
6515 01:23:34.036599 ==
6516 01:23:34.036650 Dram Type= 6, Freq= 0, CH_0, rank 1
6517 01:23:34.036701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6518 01:23:34.036752 ==
6519 01:23:34.036803 RX Vref Scan: 0
6520 01:23:34.036853
6521 01:23:34.036904 RX Vref 0 -> 0, step: 1
6522 01:23:34.036964
6523 01:23:34.037015 RX Delay -311 -> 252, step: 8
6524 01:23:34.037067 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6525 01:23:34.037118 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6526 01:23:34.037170 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6527 01:23:34.037221 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6528 01:23:34.037272 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6529 01:23:34.037323 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6530 01:23:34.037374 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6531 01:23:34.037424 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6532 01:23:34.037475 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6533 01:23:34.037525 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6534 01:23:34.037576 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6535 01:23:34.037626 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6536 01:23:34.037677 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6537 01:23:34.037728 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6538 01:23:34.037778 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6539 01:23:34.037829 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6540 01:23:34.037881 ==
6541 01:23:34.037932 Dram Type= 6, Freq= 0, CH_0, rank 1
6542 01:23:34.037983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6543 01:23:34.038034 ==
6544 01:23:34.038085 DQS Delay:
6545 01:23:34.038144 DQS0 = 24, DQS1 = 32
6546 01:23:34.038196 DQM Delay:
6547 01:23:34.038264 DQM0 = 7, DQM1 = 9
6548 01:23:34.038325 DQ Delay:
6549 01:23:34.038391 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6550 01:23:34.038452 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6551 01:23:34.038503 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =0
6552 01:23:34.038554 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6553 01:23:34.038604
6554 01:23:34.038655
6555 01:23:34.038911 [DQSOSCAuto] RK1, (LSB)MR18= 0xb151, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 387 ps
6556 01:23:34.039041 CH0 RK1: MR19=C0C, MR18=B151
6557 01:23:34.039169 CH0_RK1: MR19=0xC0C, MR18=0xB151, DQSOSC=387, MR23=63, INC=394, DEC=262
6558 01:23:34.039296 [RxdqsGatingPostProcess] freq 400
6559 01:23:34.039422 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6560 01:23:34.039509 best DQS0 dly(2T, 0.5T) = (0, 10)
6561 01:23:34.039565 best DQS1 dly(2T, 0.5T) = (0, 10)
6562 01:23:34.039617 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6563 01:23:34.039670 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6564 01:23:34.039721 best DQS0 dly(2T, 0.5T) = (0, 10)
6565 01:23:34.039782 best DQS1 dly(2T, 0.5T) = (0, 10)
6566 01:23:34.039835 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6567 01:23:34.039886 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6568 01:23:34.039936 Pre-setting of DQS Precalculation
6569 01:23:34.039987 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6570 01:23:34.040039 ==
6571 01:23:34.040091 Dram Type= 6, Freq= 0, CH_1, rank 0
6572 01:23:34.040142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 01:23:34.040193 ==
6574 01:23:34.040245 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6575 01:23:34.040296 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6576 01:23:34.040347 [CA 0] Center 36 (8~64) winsize 57
6577 01:23:34.040398 [CA 1] Center 36 (8~64) winsize 57
6578 01:23:34.040449 [CA 2] Center 36 (8~64) winsize 57
6579 01:23:34.040501 [CA 3] Center 36 (8~64) winsize 57
6580 01:23:34.040551 [CA 4] Center 36 (8~64) winsize 57
6581 01:23:34.040601 [CA 5] Center 36 (8~64) winsize 57
6582 01:23:34.040652
6583 01:23:34.040702 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6584 01:23:34.040753
6585 01:23:34.040804 [CATrainingPosCal] consider 1 rank data
6586 01:23:34.040855 u2DelayCellTimex100 = 270/100 ps
6587 01:23:34.040905 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6588 01:23:34.040956 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6589 01:23:34.041007 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6590 01:23:34.041058 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6591 01:23:34.041108 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6592 01:23:34.041159 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6593 01:23:34.041222
6594 01:23:34.041275 CA PerBit enable=1, Macro0, CA PI delay=36
6595 01:23:34.041361
6596 01:23:34.041412 [CBTSetCACLKResult] CA Dly = 36
6597 01:23:34.041463 CS Dly: 1 (0~32)
6598 01:23:34.041513 ==
6599 01:23:34.041564 Dram Type= 6, Freq= 0, CH_1, rank 1
6600 01:23:34.041616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6601 01:23:34.041678 ==
6602 01:23:34.041746 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6603 01:23:34.041811 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6604 01:23:34.041872 [CA 0] Center 36 (8~64) winsize 57
6605 01:23:34.041924 [CA 1] Center 36 (8~64) winsize 57
6606 01:23:34.041974 [CA 2] Center 36 (8~64) winsize 57
6607 01:23:34.042025 [CA 3] Center 36 (8~64) winsize 57
6608 01:23:34.042075 [CA 4] Center 36 (8~64) winsize 57
6609 01:23:34.042125 [CA 5] Center 36 (8~64) winsize 57
6610 01:23:34.042175
6611 01:23:34.042225 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6612 01:23:34.042276
6613 01:23:34.042361 [CATrainingPosCal] consider 2 rank data
6614 01:23:34.042450 u2DelayCellTimex100 = 270/100 ps
6615 01:23:34.042515 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 01:23:34.042566 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 01:23:34.042617 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 01:23:34.042669 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 01:23:34.042719 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 01:23:34.042770 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 01:23:34.042820
6622 01:23:34.042871 CA PerBit enable=1, Macro0, CA PI delay=36
6623 01:23:34.042922
6624 01:23:34.042972 [CBTSetCACLKResult] CA Dly = 36
6625 01:23:34.043023 CS Dly: 1 (0~32)
6626 01:23:34.043074
6627 01:23:34.043124 ----->DramcWriteLeveling(PI) begin...
6628 01:23:34.043176 ==
6629 01:23:34.043228 Dram Type= 6, Freq= 0, CH_1, rank 0
6630 01:23:34.043288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6631 01:23:34.043340 ==
6632 01:23:34.043392 Write leveling (Byte 0): 40 => 8
6633 01:23:34.043443 Write leveling (Byte 1): 40 => 8
6634 01:23:34.043493 DramcWriteLeveling(PI) end<-----
6635 01:23:34.043543
6636 01:23:34.043594 ==
6637 01:23:34.043644 Dram Type= 6, Freq= 0, CH_1, rank 0
6638 01:23:34.043695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6639 01:23:34.043747 ==
6640 01:23:34.043797 [Gating] SW mode calibration
6641 01:23:34.043848 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6642 01:23:34.043899 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6643 01:23:34.043951 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6644 01:23:34.044002 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6645 01:23:34.044053 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6646 01:23:34.044104 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6647 01:23:34.044154 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6648 01:23:34.044205 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6649 01:23:34.044255 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6650 01:23:34.044306 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6651 01:23:34.044356 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6652 01:23:34.044406 Total UI for P1: 0, mck2ui 16
6653 01:23:34.044458 best dqsien dly found for B0: ( 0, 14, 24)
6654 01:23:34.044508 Total UI for P1: 0, mck2ui 16
6655 01:23:34.044559 best dqsien dly found for B1: ( 0, 14, 24)
6656 01:23:34.044610 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6657 01:23:34.044661 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6658 01:23:34.044711
6659 01:23:34.044762 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6660 01:23:34.044821 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6661 01:23:34.044873 [Gating] SW calibration Done
6662 01:23:34.044924 ==
6663 01:23:34.044975 Dram Type= 6, Freq= 0, CH_1, rank 0
6664 01:23:34.045026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6665 01:23:34.045077 ==
6666 01:23:34.045128 RX Vref Scan: 0
6667 01:23:34.045244
6668 01:23:34.045344 RX Vref 0 -> 0, step: 1
6669 01:23:34.045425
6670 01:23:34.045478 RX Delay -410 -> 252, step: 16
6671 01:23:34.045530 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6672 01:23:34.045582 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6673 01:23:34.045634 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6674 01:23:34.045890 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6675 01:23:34.045980 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6676 01:23:34.046062 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6677 01:23:34.046144 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6678 01:23:34.046226 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6679 01:23:34.046335 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6680 01:23:34.046406 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6681 01:23:34.046458 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6682 01:23:34.046510 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6683 01:23:34.046562 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6684 01:23:34.046613 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6685 01:23:34.046664 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6686 01:23:34.046716 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6687 01:23:34.046778 ==
6688 01:23:34.046831 Dram Type= 6, Freq= 0, CH_1, rank 0
6689 01:23:34.046883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6690 01:23:34.046935 ==
6691 01:23:34.046987 DQS Delay:
6692 01:23:34.047038 DQS0 = 35, DQS1 = 35
6693 01:23:34.047089 DQM Delay:
6694 01:23:34.047141 DQM0 = 17, DQM1 = 12
6695 01:23:34.047193 DQ Delay:
6696 01:23:34.047245 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6697 01:23:34.047296 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6698 01:23:34.047347 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6699 01:23:34.047398 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =16
6700 01:23:34.047450
6701 01:23:34.047501
6702 01:23:34.047552 ==
6703 01:23:34.047626 Dram Type= 6, Freq= 0, CH_1, rank 0
6704 01:23:34.047691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6705 01:23:34.047743 ==
6706 01:23:34.047794
6707 01:23:34.047845
6708 01:23:34.047895 TX Vref Scan disable
6709 01:23:34.047947 == TX Byte 0 ==
6710 01:23:34.047999 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6711 01:23:34.048050 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6712 01:23:34.048101 == TX Byte 1 ==
6713 01:23:34.048153 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6714 01:23:34.048204 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6715 01:23:34.048254 ==
6716 01:23:34.048306 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 01:23:34.048357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 01:23:34.048408 ==
6719 01:23:34.048459
6720 01:23:34.048509
6721 01:23:34.048560 TX Vref Scan disable
6722 01:23:34.048611 == TX Byte 0 ==
6723 01:23:34.048662 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6724 01:23:34.048726 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6725 01:23:34.048805 == TX Byte 1 ==
6726 01:23:34.048859 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6727 01:23:34.048941 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6728 01:23:34.048992
6729 01:23:34.049044 [DATLAT]
6730 01:23:34.049094 Freq=400, CH1 RK0
6731 01:23:34.049146
6732 01:23:34.049197 DATLAT Default: 0xf
6733 01:23:34.049248 0, 0xFFFF, sum = 0
6734 01:23:34.049301 1, 0xFFFF, sum = 0
6735 01:23:34.049353 2, 0xFFFF, sum = 0
6736 01:23:34.049405 3, 0xFFFF, sum = 0
6737 01:23:34.049456 4, 0xFFFF, sum = 0
6738 01:23:34.049513 5, 0xFFFF, sum = 0
6739 01:23:34.049572 6, 0xFFFF, sum = 0
6740 01:23:34.049623 7, 0xFFFF, sum = 0
6741 01:23:34.049675 8, 0xFFFF, sum = 0
6742 01:23:34.049726 9, 0xFFFF, sum = 0
6743 01:23:34.049778 10, 0xFFFF, sum = 0
6744 01:23:34.049829 11, 0xFFFF, sum = 0
6745 01:23:34.049881 12, 0xFFFF, sum = 0
6746 01:23:34.049932 13, 0x0, sum = 1
6747 01:23:34.049983 14, 0x0, sum = 2
6748 01:23:34.050035 15, 0x0, sum = 3
6749 01:23:34.050087 16, 0x0, sum = 4
6750 01:23:34.050138 best_step = 14
6751 01:23:34.050189
6752 01:23:34.050240 ==
6753 01:23:34.050325 Dram Type= 6, Freq= 0, CH_1, rank 0
6754 01:23:34.050394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6755 01:23:34.050445 ==
6756 01:23:34.050497 RX Vref Scan: 1
6757 01:23:34.050547
6758 01:23:34.050599 RX Vref 0 -> 0, step: 1
6759 01:23:34.050649
6760 01:23:34.050700 RX Delay -311 -> 252, step: 8
6761 01:23:34.050752
6762 01:23:34.050803 Set Vref, RX VrefLevel [Byte0]: 54
6763 01:23:34.050855 [Byte1]: 54
6764 01:23:34.050906
6765 01:23:34.050956 Final RX Vref Byte 0 = 54 to rank0
6766 01:23:34.051008 Final RX Vref Byte 1 = 54 to rank0
6767 01:23:34.051059 Final RX Vref Byte 0 = 54 to rank1
6768 01:23:34.051110 Final RX Vref Byte 1 = 54 to rank1==
6769 01:23:34.051161 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 01:23:34.051212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 01:23:34.051263 ==
6772 01:23:34.051315 DQS Delay:
6773 01:23:34.051366 DQS0 = 28, DQS1 = 32
6774 01:23:34.051417 DQM Delay:
6775 01:23:34.051467 DQM0 = 10, DQM1 = 10
6776 01:23:34.051522 DQ Delay:
6777 01:23:34.051580 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6778 01:23:34.051631 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =8
6779 01:23:34.051682 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6780 01:23:34.051733 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6781 01:23:34.051784
6782 01:23:34.051836
6783 01:23:34.051895 [DQSOSCAuto] RK0, (LSB)MR18= 0x8dc6, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6784 01:23:34.051974 CH1 RK0: MR19=C0C, MR18=8DC6
6785 01:23:34.052031 CH1_RK0: MR19=0xC0C, MR18=0x8DC6, DQSOSC=385, MR23=63, INC=398, DEC=265
6786 01:23:34.052083 ==
6787 01:23:34.052136 Dram Type= 6, Freq= 0, CH_1, rank 1
6788 01:23:34.052187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 01:23:34.052239 ==
6790 01:23:34.052290 [Gating] SW mode calibration
6791 01:23:34.052342 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6792 01:23:34.052394 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6793 01:23:34.052446 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6794 01:23:34.052497 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6795 01:23:34.052549 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6796 01:23:34.052600 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6797 01:23:34.052651 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6798 01:23:34.052702 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6799 01:23:34.052753 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6800 01:23:34.052804 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6801 01:23:34.052855 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6802 01:23:34.052905 Total UI for P1: 0, mck2ui 16
6803 01:23:34.052957 best dqsien dly found for B0: ( 0, 14, 24)
6804 01:23:34.053008 Total UI for P1: 0, mck2ui 16
6805 01:23:34.053059 best dqsien dly found for B1: ( 0, 14, 24)
6806 01:23:34.053110 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6807 01:23:34.053161 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6808 01:23:34.053212
6809 01:23:34.053263 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6810 01:23:34.053314 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6811 01:23:34.053365 [Gating] SW calibration Done
6812 01:23:34.053416 ==
6813 01:23:34.053467 Dram Type= 6, Freq= 0, CH_1, rank 1
6814 01:23:34.053725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6815 01:23:34.053854 ==
6816 01:23:34.053981 RX Vref Scan: 0
6817 01:23:34.054067
6818 01:23:34.054149 RX Vref 0 -> 0, step: 1
6819 01:23:34.054229
6820 01:23:34.054336 RX Delay -410 -> 252, step: 16
6821 01:23:34.054406 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6822 01:23:34.054460 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6823 01:23:34.054512 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6824 01:23:34.054564 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6825 01:23:34.054615 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6826 01:23:34.054666 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6827 01:23:34.054717 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6828 01:23:34.054768 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6829 01:23:34.054819 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6830 01:23:34.054870 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6831 01:23:34.054922 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6832 01:23:34.054983 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6833 01:23:34.055052 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6834 01:23:34.055105 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6835 01:23:34.055157 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6836 01:23:34.055208 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6837 01:23:34.055259 ==
6838 01:23:34.055310 Dram Type= 6, Freq= 0, CH_1, rank 1
6839 01:23:34.055397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6840 01:23:34.055453 ==
6841 01:23:34.055509 DQS Delay:
6842 01:23:34.055603 DQS0 = 35, DQS1 = 35
6843 01:23:34.055658 DQM Delay:
6844 01:23:34.055725 DQM0 = 17, DQM1 = 14
6845 01:23:34.055776 DQ Delay:
6846 01:23:34.055827 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6847 01:23:34.055879 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6848 01:23:34.055929 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6849 01:23:34.055980 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6850 01:23:34.056031
6851 01:23:34.056081
6852 01:23:34.056132 ==
6853 01:23:34.056183 Dram Type= 6, Freq= 0, CH_1, rank 1
6854 01:23:34.056234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6855 01:23:34.056285 ==
6856 01:23:34.056336
6857 01:23:34.056387
6858 01:23:34.056437 TX Vref Scan disable
6859 01:23:34.056488 == TX Byte 0 ==
6860 01:23:34.056540 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6861 01:23:34.056592 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6862 01:23:34.056643 == TX Byte 1 ==
6863 01:23:34.056694 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6864 01:23:34.056744 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6865 01:23:34.056805 ==
6866 01:23:34.056856 Dram Type= 6, Freq= 0, CH_1, rank 1
6867 01:23:34.056908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 01:23:34.056959 ==
6869 01:23:34.057009
6870 01:23:34.057059
6871 01:23:34.057110 TX Vref Scan disable
6872 01:23:34.057160 == TX Byte 0 ==
6873 01:23:34.057211 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6874 01:23:34.057262 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6875 01:23:34.057313 == TX Byte 1 ==
6876 01:23:34.057363 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6877 01:23:34.057414 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6878 01:23:34.057464
6879 01:23:34.057520 [DATLAT]
6880 01:23:34.057605 Freq=400, CH1 RK1
6881 01:23:34.057680
6882 01:23:34.057731 DATLAT Default: 0xe
6883 01:23:34.057782 0, 0xFFFF, sum = 0
6884 01:23:34.057835 1, 0xFFFF, sum = 0
6885 01:23:34.057887 2, 0xFFFF, sum = 0
6886 01:23:34.057939 3, 0xFFFF, sum = 0
6887 01:23:34.057991 4, 0xFFFF, sum = 0
6888 01:23:34.058042 5, 0xFFFF, sum = 0
6889 01:23:34.058094 6, 0xFFFF, sum = 0
6890 01:23:34.058145 7, 0xFFFF, sum = 0
6891 01:23:34.058196 8, 0xFFFF, sum = 0
6892 01:23:34.058248 9, 0xFFFF, sum = 0
6893 01:23:34.058307 10, 0xFFFF, sum = 0
6894 01:23:34.058434 11, 0xFFFF, sum = 0
6895 01:23:34.058489 12, 0xFFFF, sum = 0
6896 01:23:34.058541 13, 0x0, sum = 1
6897 01:23:34.058593 14, 0x0, sum = 2
6898 01:23:34.058645 15, 0x0, sum = 3
6899 01:23:34.058697 16, 0x0, sum = 4
6900 01:23:34.058757 best_step = 14
6901 01:23:34.058828
6902 01:23:34.058881 ==
6903 01:23:34.058933 Dram Type= 6, Freq= 0, CH_1, rank 1
6904 01:23:34.058985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6905 01:23:34.059037 ==
6906 01:23:34.059088 RX Vref Scan: 0
6907 01:23:34.059140
6908 01:23:34.059191 RX Vref 0 -> 0, step: 1
6909 01:23:34.059242
6910 01:23:34.059292 RX Delay -311 -> 252, step: 8
6911 01:23:34.059343 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6912 01:23:34.059394 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6913 01:23:34.059445 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6914 01:23:34.059501 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6915 01:23:34.059558 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6916 01:23:34.059609 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6917 01:23:34.059660 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6918 01:23:34.059711 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6919 01:23:34.059762 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6920 01:23:34.059813 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6921 01:23:34.059863 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6922 01:23:34.059914 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6923 01:23:34.059977 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6924 01:23:34.060029 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6925 01:23:34.060080 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6926 01:23:34.060131 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6927 01:23:34.060182 ==
6928 01:23:34.060233 Dram Type= 6, Freq= 0, CH_1, rank 1
6929 01:23:34.060284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6930 01:23:34.060336 ==
6931 01:23:34.060387 DQS Delay:
6932 01:23:34.060437 DQS0 = 28, DQS1 = 36
6933 01:23:34.060488 DQM Delay:
6934 01:23:34.060539 DQM0 = 10, DQM1 = 14
6935 01:23:34.060589 DQ Delay:
6936 01:23:34.060640 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6937 01:23:34.060691 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6938 01:23:34.060742 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6939 01:23:34.060792 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6940 01:23:34.060843
6941 01:23:34.060894
6942 01:23:34.060944 [DQSOSCAuto] RK1, (LSB)MR18= 0xc354, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
6943 01:23:34.407087 CH1 RK1: MR19=C0C, MR18=C354
6944 01:23:34.407219 CH1_RK1: MR19=0xC0C, MR18=0xC354, DQSOSC=385, MR23=63, INC=398, DEC=265
6945 01:23:34.407335 [RxdqsGatingPostProcess] freq 400
6946 01:23:34.407433 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6947 01:23:34.407492 best DQS0 dly(2T, 0.5T) = (0, 10)
6948 01:23:34.407549 best DQS1 dly(2T, 0.5T) = (0, 10)
6949 01:23:34.407604 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6950 01:23:34.407658 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6951 01:23:34.407711 best DQS0 dly(2T, 0.5T) = (0, 10)
6952 01:23:34.407764 best DQS1 dly(2T, 0.5T) = (0, 10)
6953 01:23:34.408035 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6954 01:23:34.408095 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6955 01:23:34.408154 Pre-setting of DQS Precalculation
6956 01:23:34.408289 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6957 01:23:34.408361 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6958 01:23:34.408416 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6959 01:23:34.408469
6960 01:23:34.408523
6961 01:23:34.408588 [Calibration Summary] 800 Mbps
6962 01:23:34.408640 CH 0, Rank 0
6963 01:23:34.408691 SW Impedance : PASS
6964 01:23:34.408743 DUTY Scan : NO K
6965 01:23:34.408795 ZQ Calibration : PASS
6966 01:23:34.408846 Jitter Meter : NO K
6967 01:23:34.408898 CBT Training : PASS
6968 01:23:34.408950 Write leveling : PASS
6969 01:23:34.409001 RX DQS gating : PASS
6970 01:23:34.409052 RX DQ/DQS(RDDQC) : PASS
6971 01:23:34.409104 TX DQ/DQS : PASS
6972 01:23:34.409172 RX DATLAT : PASS
6973 01:23:34.409265 RX DQ/DQS(Engine): PASS
6974 01:23:34.409318 TX OE : NO K
6975 01:23:34.409370 All Pass.
6976 01:23:34.409423
6977 01:23:34.409475 CH 0, Rank 1
6978 01:23:34.409527 SW Impedance : PASS
6979 01:23:34.409580 DUTY Scan : NO K
6980 01:23:34.409632 ZQ Calibration : PASS
6981 01:23:34.409684 Jitter Meter : NO K
6982 01:23:34.409737 CBT Training : PASS
6983 01:23:34.409788 Write leveling : NO K
6984 01:23:34.409841 RX DQS gating : PASS
6985 01:23:34.409893 RX DQ/DQS(RDDQC) : PASS
6986 01:23:34.409944 TX DQ/DQS : PASS
6987 01:23:34.410011 RX DATLAT : PASS
6988 01:23:34.410065 RX DQ/DQS(Engine): PASS
6989 01:23:34.410118 TX OE : NO K
6990 01:23:34.410182 All Pass.
6991 01:23:34.410235
6992 01:23:34.410287 CH 1, Rank 0
6993 01:23:34.410365 SW Impedance : PASS
6994 01:23:34.410417 DUTY Scan : NO K
6995 01:23:34.410468 ZQ Calibration : PASS
6996 01:23:34.410561 Jitter Meter : NO K
6997 01:23:34.410661 CBT Training : PASS
6998 01:23:34.410714 Write leveling : PASS
6999 01:23:34.410766 RX DQS gating : PASS
7000 01:23:34.410818 RX DQ/DQS(RDDQC) : PASS
7001 01:23:34.410869 TX DQ/DQS : PASS
7002 01:23:34.410921 RX DATLAT : PASS
7003 01:23:34.410971 RX DQ/DQS(Engine): PASS
7004 01:23:34.411022 TX OE : NO K
7005 01:23:34.411073 All Pass.
7006 01:23:34.411125
7007 01:23:34.411176 CH 1, Rank 1
7008 01:23:34.411227 SW Impedance : PASS
7009 01:23:34.411278 DUTY Scan : NO K
7010 01:23:34.411329 ZQ Calibration : PASS
7011 01:23:34.411422 Jitter Meter : NO K
7012 01:23:34.411492 CBT Training : PASS
7013 01:23:34.411544 Write leveling : NO K
7014 01:23:34.411597 RX DQS gating : PASS
7015 01:23:34.411649 RX DQ/DQS(RDDQC) : PASS
7016 01:23:34.411701 TX DQ/DQS : PASS
7017 01:23:34.411753 RX DATLAT : PASS
7018 01:23:34.411818 RX DQ/DQS(Engine): PASS
7019 01:23:34.411869 TX OE : NO K
7020 01:23:34.411920 All Pass.
7021 01:23:34.411971
7022 01:23:34.412022 DramC Write-DBI off
7023 01:23:34.412073 PER_BANK_REFRESH: Hybrid Mode
7024 01:23:34.412129 TX_TRACKING: ON
7025 01:23:34.412188 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7026 01:23:34.412241 [FAST_K] Save calibration result to emmc
7027 01:23:34.412292 dramc_set_vcore_voltage set vcore to 725000
7028 01:23:34.412343 Read voltage for 1600, 0
7029 01:23:34.412394 Vio18 = 0
7030 01:23:34.412445 Vcore = 725000
7031 01:23:34.412496 Vdram = 0
7032 01:23:34.412546 Vddq = 0
7033 01:23:34.412598 Vmddr = 0
7034 01:23:34.412649 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7035 01:23:34.412701 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7036 01:23:34.412752 MEM_TYPE=3, freq_sel=13
7037 01:23:34.412830 sv_algorithm_assistance_LP4_3733
7038 01:23:34.412883 ============ PULL DRAM RESETB DOWN ============
7039 01:23:34.412936 ========== PULL DRAM RESETB DOWN end =========
7040 01:23:34.412988 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7041 01:23:34.413041 ===================================
7042 01:23:34.413093 LPDDR4 DRAM CONFIGURATION
7043 01:23:34.413146 ===================================
7044 01:23:34.413204 EX_ROW_EN[0] = 0x0
7045 01:23:34.413294 EX_ROW_EN[1] = 0x0
7046 01:23:34.413351 LP4Y_EN = 0x0
7047 01:23:34.413404 WORK_FSP = 0x1
7048 01:23:34.413456 WL = 0x5
7049 01:23:34.413522 RL = 0x5
7050 01:23:34.413619 BL = 0x2
7051 01:23:34.413673 RPST = 0x0
7052 01:23:34.413756 RD_PRE = 0x0
7053 01:23:34.413809 WR_PRE = 0x1
7054 01:23:34.413861 WR_PST = 0x1
7055 01:23:34.413913 DBI_WR = 0x0
7056 01:23:34.413965 DBI_RD = 0x0
7057 01:23:34.414018 OTF = 0x1
7058 01:23:34.414070 ===================================
7059 01:23:34.414126 ===================================
7060 01:23:34.414203 ANA top config
7061 01:23:34.414286 ===================================
7062 01:23:34.414369 DLL_ASYNC_EN = 0
7063 01:23:34.414424 ALL_SLAVE_EN = 0
7064 01:23:34.414478 NEW_RANK_MODE = 1
7065 01:23:34.414532 DLL_IDLE_MODE = 1
7066 01:23:34.414585 LP45_APHY_COMB_EN = 1
7067 01:23:34.414638 TX_ODT_DIS = 0
7068 01:23:34.414690 NEW_8X_MODE = 1
7069 01:23:34.414744 ===================================
7070 01:23:34.414807 ===================================
7071 01:23:34.414861 data_rate = 3200
7072 01:23:34.414913 CKR = 1
7073 01:23:34.414966 DQ_P2S_RATIO = 8
7074 01:23:34.415019 ===================================
7075 01:23:34.415072 CA_P2S_RATIO = 8
7076 01:23:34.415124 DQ_CA_OPEN = 0
7077 01:23:34.415176 DQ_SEMI_OPEN = 0
7078 01:23:34.415228 CA_SEMI_OPEN = 0
7079 01:23:34.415280 CA_FULL_RATE = 0
7080 01:23:34.415333 DQ_CKDIV4_EN = 0
7081 01:23:34.415385 CA_CKDIV4_EN = 0
7082 01:23:34.415437 CA_PREDIV_EN = 0
7083 01:23:34.415490 PH8_DLY = 12
7084 01:23:34.415543 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7085 01:23:34.415595 DQ_AAMCK_DIV = 4
7086 01:23:34.415657 CA_AAMCK_DIV = 4
7087 01:23:34.415710 CA_ADMCK_DIV = 4
7088 01:23:34.415762 DQ_TRACK_CA_EN = 0
7089 01:23:34.415814 CA_PICK = 1600
7090 01:23:34.415867 CA_MCKIO = 1600
7091 01:23:34.415920 MCKIO_SEMI = 0
7092 01:23:34.415972 PLL_FREQ = 3068
7093 01:23:34.416026 DQ_UI_PI_RATIO = 32
7094 01:23:34.416078 CA_UI_PI_RATIO = 0
7095 01:23:34.416134 ===================================
7096 01:23:34.416194 ===================================
7097 01:23:34.416248 memory_type:LPDDR4
7098 01:23:34.416299 GP_NUM : 10
7099 01:23:34.416352 SRAM_EN : 1
7100 01:23:34.416609 MD32_EN : 0
7101 01:23:34.416667 ===================================
7102 01:23:34.416722 [ANA_INIT] >>>>>>>>>>>>>>
7103 01:23:34.416776 <<<<<< [CONFIGURE PHASE]: ANA_TX
7104 01:23:34.416829 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7105 01:23:34.416883 ===================================
7106 01:23:34.416936 data_rate = 3200,PCW = 0X7600
7107 01:23:34.417006 ===================================
7108 01:23:34.417071 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7109 01:23:34.417125 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7110 01:23:34.417178 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7111 01:23:34.417232 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7112 01:23:34.417285 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7113 01:23:34.417351 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7114 01:23:34.417402 [ANA_INIT] flow start
7115 01:23:34.417454 [ANA_INIT] PLL >>>>>>>>
7116 01:23:34.417506 [ANA_INIT] PLL <<<<<<<<
7117 01:23:34.417557 [ANA_INIT] MIDPI >>>>>>>>
7118 01:23:34.417609 [ANA_INIT] MIDPI <<<<<<<<
7119 01:23:34.417660 [ANA_INIT] DLL >>>>>>>>
7120 01:23:34.417711 [ANA_INIT] DLL <<<<<<<<
7121 01:23:34.417763 [ANA_INIT] flow end
7122 01:23:34.417824 ============ LP4 DIFF to SE enter ============
7123 01:23:34.417894 ============ LP4 DIFF to SE exit ============
7124 01:23:34.417947 [ANA_INIT] <<<<<<<<<<<<<
7125 01:23:34.418000 [Flow] Enable top DCM control >>>>>
7126 01:23:34.418052 [Flow] Enable top DCM control <<<<<
7127 01:23:34.418105 Enable DLL master slave shuffle
7128 01:23:34.418174 ==============================================================
7129 01:23:34.418238 Gating Mode config
7130 01:23:34.418337 ==============================================================
7131 01:23:34.418441 Config description:
7132 01:23:34.418497 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7133 01:23:34.418551 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7134 01:23:34.418605 SELPH_MODE 0: By rank 1: By Phase
7135 01:23:34.418657 ==============================================================
7136 01:23:34.418710 GAT_TRACK_EN = 1
7137 01:23:34.418762 RX_GATING_MODE = 2
7138 01:23:34.418813 RX_GATING_TRACK_MODE = 2
7139 01:23:34.418865 SELPH_MODE = 1
7140 01:23:34.418917 PICG_EARLY_EN = 1
7141 01:23:34.418968 VALID_LAT_VALUE = 1
7142 01:23:34.419020 ==============================================================
7143 01:23:34.419072 Enter into Gating configuration >>>>
7144 01:23:34.419124 Exit from Gating configuration <<<<
7145 01:23:34.419175 Enter into DVFS_PRE_config >>>>>
7146 01:23:34.419227 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7147 01:23:34.419280 Exit from DVFS_PRE_config <<<<<
7148 01:23:34.419364 Enter into PICG configuration >>>>
7149 01:23:34.419430 Exit from PICG configuration <<<<
7150 01:23:34.419481 [RX_INPUT] configuration >>>>>
7151 01:23:34.419533 [RX_INPUT] configuration <<<<<
7152 01:23:34.419584 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7153 01:23:34.419636 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7154 01:23:34.419688 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7155 01:23:34.419740 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7156 01:23:34.419792 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7157 01:23:34.419844 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7158 01:23:34.419896 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7159 01:23:34.419947 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7160 01:23:34.419999 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7161 01:23:34.420051 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7162 01:23:34.420102 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7163 01:23:34.420206 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7164 01:23:34.420350 ===================================
7165 01:23:34.420429 LPDDR4 DRAM CONFIGURATION
7166 01:23:34.420482 ===================================
7167 01:23:34.420534 EX_ROW_EN[0] = 0x0
7168 01:23:34.420585 EX_ROW_EN[1] = 0x0
7169 01:23:34.420637 LP4Y_EN = 0x0
7170 01:23:34.420689 WORK_FSP = 0x1
7171 01:23:34.420740 WL = 0x5
7172 01:23:34.420792 RL = 0x5
7173 01:23:34.420843 BL = 0x2
7174 01:23:34.420894 RPST = 0x0
7175 01:23:34.420946 RD_PRE = 0x0
7176 01:23:34.420998 WR_PRE = 0x1
7177 01:23:34.421049 WR_PST = 0x1
7178 01:23:34.421141 DBI_WR = 0x0
7179 01:23:34.421209 DBI_RD = 0x0
7180 01:23:34.421261 OTF = 0x1
7181 01:23:34.421315 ===================================
7182 01:23:34.421368 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7183 01:23:34.421421 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7184 01:23:34.421473 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7185 01:23:34.421541 ===================================
7186 01:23:34.421593 LPDDR4 DRAM CONFIGURATION
7187 01:23:34.421645 ===================================
7188 01:23:34.421696 EX_ROW_EN[0] = 0x10
7189 01:23:34.421748 EX_ROW_EN[1] = 0x0
7190 01:23:34.421799 LP4Y_EN = 0x0
7191 01:23:34.421851 WORK_FSP = 0x1
7192 01:23:34.421902 WL = 0x5
7193 01:23:34.421954 RL = 0x5
7194 01:23:34.422036 BL = 0x2
7195 01:23:34.422088 RPST = 0x0
7196 01:23:34.422143 RD_PRE = 0x0
7197 01:23:34.422202 WR_PRE = 0x1
7198 01:23:34.422253 WR_PST = 0x1
7199 01:23:34.422325 DBI_WR = 0x0
7200 01:23:34.422393 DBI_RD = 0x0
7201 01:23:34.422444 OTF = 0x1
7202 01:23:34.422496 ===================================
7203 01:23:34.422548 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7204 01:23:34.422600 ==
7205 01:23:34.422653 Dram Type= 6, Freq= 0, CH_0, rank 0
7206 01:23:34.422730 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7207 01:23:34.422797 ==
7208 01:23:34.422849 [Duty_Offset_Calibration]
7209 01:23:34.422900 B0:2 B1:1 CA:1
7210 01:23:34.422952
7211 01:23:34.423222 [DutyScan_Calibration_Flow] k_type=0
7212 01:23:34.423293
7213 01:23:34.423347 ==CLK 0==
7214 01:23:34.423423 Final CLK duty delay cell = 0
7215 01:23:34.423492 [0] MAX Duty = 5156%(X100), DQS PI = 22
7216 01:23:34.423573 [0] MIN Duty = 4907%(X100), DQS PI = 0
7217 01:23:34.423625 [0] AVG Duty = 5031%(X100)
7218 01:23:34.423676
7219 01:23:34.423728 CH0 CLK Duty spec in!! Max-Min= 249%
7220 01:23:34.423779 [DutyScan_Calibration_Flow] ====Done====
7221 01:23:34.423831
7222 01:23:34.423882 [DutyScan_Calibration_Flow] k_type=1
7223 01:23:34.423935
7224 01:23:34.423986 ==DQS 0 ==
7225 01:23:34.424037 Final DQS duty delay cell = -4
7226 01:23:34.424089 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7227 01:23:34.424144 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7228 01:23:34.424204 [-4] AVG Duty = 4891%(X100)
7229 01:23:34.424255
7230 01:23:34.424327 ==DQS 1 ==
7231 01:23:34.424380 Final DQS duty delay cell = 0
7232 01:23:34.424433 [0] MAX Duty = 5218%(X100), DQS PI = 22
7233 01:23:34.424485 [0] MIN Duty = 5031%(X100), DQS PI = 52
7234 01:23:34.424562 [0] AVG Duty = 5124%(X100)
7235 01:23:34.424645
7236 01:23:34.424699 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7237 01:23:34.424752
7238 01:23:34.424804 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7239 01:23:34.424858 [DutyScan_Calibration_Flow] ====Done====
7240 01:23:34.424911
7241 01:23:34.424964 [DutyScan_Calibration_Flow] k_type=3
7242 01:23:34.425029
7243 01:23:34.425081 ==DQM 0 ==
7244 01:23:34.425132 Final DQM duty delay cell = 0
7245 01:23:34.425184 [0] MAX Duty = 5187%(X100), DQS PI = 26
7246 01:23:34.425235 [0] MIN Duty = 4907%(X100), DQS PI = 54
7247 01:23:34.425286 [0] AVG Duty = 5047%(X100)
7248 01:23:34.425338
7249 01:23:34.425389 ==DQM 1 ==
7250 01:23:34.425440 Final DQM duty delay cell = 0
7251 01:23:34.425492 [0] MAX Duty = 5187%(X100), DQS PI = 4
7252 01:23:34.425543 [0] MIN Duty = 5031%(X100), DQS PI = 48
7253 01:23:34.425595 [0] AVG Duty = 5109%(X100)
7254 01:23:34.425646
7255 01:23:34.425698 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7256 01:23:34.425749
7257 01:23:34.425801 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7258 01:23:34.425852 [DutyScan_Calibration_Flow] ====Done====
7259 01:23:34.425904
7260 01:23:34.425955 [DutyScan_Calibration_Flow] k_type=2
7261 01:23:34.426031
7262 01:23:34.426098 ==DQ 0 ==
7263 01:23:34.426154 Final DQ duty delay cell = 0
7264 01:23:34.426273 [0] MAX Duty = 5062%(X100), DQS PI = 26
7265 01:23:34.426394 [0] MIN Duty = 4907%(X100), DQS PI = 0
7266 01:23:34.426452 [0] AVG Duty = 4984%(X100)
7267 01:23:34.426506
7268 01:23:34.426558 ==DQ 1 ==
7269 01:23:34.426611 Final DQ duty delay cell = 0
7270 01:23:34.426689 [0] MAX Duty = 5156%(X100), DQS PI = 22
7271 01:23:34.426772 [0] MIN Duty = 4938%(X100), DQS PI = 34
7272 01:23:34.426837 [0] AVG Duty = 5047%(X100)
7273 01:23:34.426889
7274 01:23:34.426940 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7275 01:23:34.426992
7276 01:23:34.427044 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7277 01:23:34.427096 [DutyScan_Calibration_Flow] ====Done====
7278 01:23:34.427148 ==
7279 01:23:34.427214 Dram Type= 6, Freq= 0, CH_1, rank 0
7280 01:23:34.427267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7281 01:23:34.427333 ==
7282 01:23:34.427385 [Duty_Offset_Calibration]
7283 01:23:34.427436 B0:1 B1:0 CA:0
7284 01:23:34.427488
7285 01:23:34.427540 [DutyScan_Calibration_Flow] k_type=0
7286 01:23:34.427591
7287 01:23:34.427643 ==CLK 0==
7288 01:23:34.427694 Final CLK duty delay cell = -4
7289 01:23:34.427746 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7290 01:23:34.427797 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7291 01:23:34.427848 [-4] AVG Duty = 4906%(X100)
7292 01:23:34.427924
7293 01:23:34.428006 CH1 CLK Duty spec in!! Max-Min= 125%
7294 01:23:34.428058 [DutyScan_Calibration_Flow] ====Done====
7295 01:23:34.428111
7296 01:23:34.428182 [DutyScan_Calibration_Flow] k_type=1
7297 01:23:34.428237
7298 01:23:34.428288 ==DQS 0 ==
7299 01:23:34.428353 Final DQS duty delay cell = 0
7300 01:23:34.428405 [0] MAX Duty = 5094%(X100), DQS PI = 24
7301 01:23:34.428456 [0] MIN Duty = 4844%(X100), DQS PI = 48
7302 01:23:34.428507 [0] AVG Duty = 4969%(X100)
7303 01:23:34.428558
7304 01:23:34.428609 ==DQS 1 ==
7305 01:23:34.428660 Final DQS duty delay cell = 0
7306 01:23:34.428750 [0] MAX Duty = 5249%(X100), DQS PI = 16
7307 01:23:34.428802 [0] MIN Duty = 4938%(X100), DQS PI = 8
7308 01:23:34.428853 [0] AVG Duty = 5093%(X100)
7309 01:23:34.428903
7310 01:23:34.428954 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7311 01:23:34.429005
7312 01:23:34.429056 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7313 01:23:34.429107 [DutyScan_Calibration_Flow] ====Done====
7314 01:23:34.429158
7315 01:23:34.429209 [DutyScan_Calibration_Flow] k_type=3
7316 01:23:34.429259
7317 01:23:34.429310 ==DQM 0 ==
7318 01:23:34.429361 Final DQM duty delay cell = 0
7319 01:23:34.429412 [0] MAX Duty = 5187%(X100), DQS PI = 8
7320 01:23:34.429463 [0] MIN Duty = 4969%(X100), DQS PI = 48
7321 01:23:34.429514 [0] AVG Duty = 5078%(X100)
7322 01:23:34.429565
7323 01:23:34.429615 ==DQM 1 ==
7324 01:23:34.429666 Final DQM duty delay cell = 0
7325 01:23:34.429718 [0] MAX Duty = 5093%(X100), DQS PI = 16
7326 01:23:34.429769 [0] MIN Duty = 4907%(X100), DQS PI = 50
7327 01:23:34.429820 [0] AVG Duty = 5000%(X100)
7328 01:23:34.429870
7329 01:23:34.429921 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7330 01:23:34.429972
7331 01:23:34.430023 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7332 01:23:34.430114 [DutyScan_Calibration_Flow] ====Done====
7333 01:23:34.430223
7334 01:23:34.430313 [DutyScan_Calibration_Flow] k_type=2
7335 01:23:34.430382
7336 01:23:34.430433 ==DQ 0 ==
7337 01:23:34.430487 Final DQ duty delay cell = -4
7338 01:23:34.430539 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7339 01:23:34.430591 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7340 01:23:34.430642 [-4] AVG Duty = 4937%(X100)
7341 01:23:34.430693
7342 01:23:34.430744 ==DQ 1 ==
7343 01:23:34.430795 Final DQ duty delay cell = 0
7344 01:23:34.430847 [0] MAX Duty = 5156%(X100), DQS PI = 18
7345 01:23:34.430898 [0] MIN Duty = 4938%(X100), DQS PI = 10
7346 01:23:34.430949 [0] AVG Duty = 5047%(X100)
7347 01:23:34.431000
7348 01:23:34.431051 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7349 01:23:34.431143
7350 01:23:34.431212 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7351 01:23:34.431277 [DutyScan_Calibration_Flow] ====Done====
7352 01:23:34.431328 nWR fixed to 30
7353 01:23:34.431380 [ModeRegInit_LP4] CH0 RK0
7354 01:23:34.431431 [ModeRegInit_LP4] CH0 RK1
7355 01:23:34.431482 [ModeRegInit_LP4] CH1 RK0
7356 01:23:34.431532 [ModeRegInit_LP4] CH1 RK1
7357 01:23:34.431582 match AC timing 5
7358 01:23:34.431633 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7359 01:23:34.431684 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7360 01:23:34.431735 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7361 01:23:34.431787 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7362 01:23:34.431838 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7363 01:23:34.431889 [MiockJmeterHQA]
7364 01:23:34.431940
7365 01:23:34.431991 [DramcMiockJmeter] u1RxGatingPI = 0
7366 01:23:34.432042 0 : 4363, 4138
7367 01:23:34.432103 4 : 4252, 4026
7368 01:23:34.432166 8 : 4252, 4027
7369 01:23:34.432220 12 : 4252, 4027
7370 01:23:34.432271 16 : 4252, 4027
7371 01:23:34.432323 20 : 4363, 4137
7372 01:23:34.432576 24 : 4252, 4027
7373 01:23:34.432634 28 : 4252, 4027
7374 01:23:34.432687 32 : 4253, 4026
7375 01:23:34.432739 36 : 4255, 4030
7376 01:23:34.432792 40 : 4252, 4027
7377 01:23:34.432843 44 : 4363, 4137
7378 01:23:34.432895 48 : 4363, 4138
7379 01:23:34.432947 52 : 4253, 4026
7380 01:23:34.433000 56 : 4252, 4027
7381 01:23:34.433052 60 : 4252, 4026
7382 01:23:34.433103 64 : 4253, 4026
7383 01:23:34.433155 68 : 4255, 4029
7384 01:23:34.433206 72 : 4361, 4137
7385 01:23:34.433258 76 : 4250, 4027
7386 01:23:34.433309 80 : 4250, 4026
7387 01:23:34.433361 84 : 4250, 4026
7388 01:23:34.433412 88 : 4252, 127
7389 01:23:34.433474 92 : 4250, 0
7390 01:23:34.433527 96 : 4252, 0
7391 01:23:34.433579 100 : 4360, 0
7392 01:23:34.433631 104 : 4253, 0
7393 01:23:34.433683 108 : 4252, 0
7394 01:23:34.433734 112 : 4250, 0
7395 01:23:34.433786 116 : 4250, 0
7396 01:23:34.433837 120 : 4250, 0
7397 01:23:34.433889 124 : 4250, 0
7398 01:23:34.433940 128 : 4252, 0
7399 01:23:34.433991 132 : 4250, 0
7400 01:23:34.434043 136 : 4250, 0
7401 01:23:34.434095 140 : 4252, 0
7402 01:23:34.434151 144 : 4360, 0
7403 01:23:34.434251 148 : 4361, 0
7404 01:23:34.434366 152 : 4363, 0
7405 01:23:34.434421 156 : 4250, 0
7406 01:23:34.434474 160 : 4250, 0
7407 01:23:34.434526 164 : 4250, 0
7408 01:23:34.434578 168 : 4249, 0
7409 01:23:34.434630 172 : 4250, 0
7410 01:23:34.434681 176 : 4250, 0
7411 01:23:34.434733 180 : 4252, 0
7412 01:23:34.434785 184 : 4250, 0
7413 01:23:34.434837 188 : 4250, 0
7414 01:23:34.434888 192 : 4252, 0
7415 01:23:34.434940 196 : 4366, 0
7416 01:23:34.434992 200 : 4361, 0
7417 01:23:34.435044 204 : 4250, 1181
7418 01:23:34.435096 208 : 4360, 4062
7419 01:23:34.435147 212 : 4253, 4026
7420 01:23:34.435199 216 : 4250, 4027
7421 01:23:34.435251 220 : 4360, 4138
7422 01:23:34.435302 224 : 4250, 4027
7423 01:23:34.435353 228 : 4250, 4026
7424 01:23:34.435414 232 : 4250, 4027
7425 01:23:34.435466 236 : 4252, 4030
7426 01:23:34.435519 240 : 4250, 4027
7427 01:23:34.435570 244 : 4250, 4026
7428 01:23:34.435622 248 : 4361, 4137
7429 01:23:34.435674 252 : 4250, 4027
7430 01:23:34.435725 256 : 4250, 4027
7431 01:23:34.435777 260 : 4360, 4137
7432 01:23:34.435828 264 : 4250, 4027
7433 01:23:34.435880 268 : 4250, 4027
7434 01:23:34.435931 272 : 4363, 4139
7435 01:23:34.435982 276 : 4250, 4027
7436 01:23:34.436033 280 : 4250, 4027
7437 01:23:34.436085 284 : 4250, 4027
7438 01:23:34.436140 288 : 4252, 4030
7439 01:23:34.436231 292 : 4250, 4027
7440 01:23:34.436297 296 : 4250, 4026
7441 01:23:34.436349 300 : 4361, 4137
7442 01:23:34.436401 304 : 4250, 4027
7443 01:23:34.436453 308 : 4249, 3982
7444 01:23:34.436505 312 : 4360, 2400
7445 01:23:34.436556 316 : 4250, 3
7446 01:23:34.436608
7447 01:23:34.436668 MIOCK jitter meter ch=0
7448 01:23:34.436720
7449 01:23:34.436771 1T = (316-88) = 228 dly cells
7450 01:23:34.436824 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7451 01:23:34.436876 ==
7452 01:23:34.436927 Dram Type= 6, Freq= 0, CH_0, rank 0
7453 01:23:34.436979 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7454 01:23:34.437031 ==
7455 01:23:34.437082 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7456 01:23:34.437133 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7457 01:23:34.437187 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7458 01:23:34.437238 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7459 01:23:34.437290 [CA 0] Center 42 (12~73) winsize 62
7460 01:23:34.437341 [CA 1] Center 42 (12~73) winsize 62
7461 01:23:34.437392 [CA 2] Center 37 (8~67) winsize 60
7462 01:23:34.437443 [CA 3] Center 37 (7~67) winsize 61
7463 01:23:34.437494 [CA 4] Center 36 (6~66) winsize 61
7464 01:23:34.437544 [CA 5] Center 35 (6~64) winsize 59
7465 01:23:34.437595
7466 01:23:34.437646 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7467 01:23:34.437697
7468 01:23:34.437748 [CATrainingPosCal] consider 1 rank data
7469 01:23:34.437799 u2DelayCellTimex100 = 285/100 ps
7470 01:23:34.437851 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7471 01:23:34.437902 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7472 01:23:34.437953 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7473 01:23:34.438004 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7474 01:23:34.438055 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7475 01:23:34.438106 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7476 01:23:34.438171
7477 01:23:34.438255 CA PerBit enable=1, Macro0, CA PI delay=35
7478 01:23:34.438365
7479 01:23:34.438418 [CBTSetCACLKResult] CA Dly = 35
7480 01:23:34.438470 CS Dly: 9 (0~40)
7481 01:23:34.438520 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7482 01:23:34.438572 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7483 01:23:34.438623 ==
7484 01:23:34.438675 Dram Type= 6, Freq= 0, CH_0, rank 1
7485 01:23:34.438726 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7486 01:23:34.438777 ==
7487 01:23:34.438829 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7488 01:23:34.438880 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7489 01:23:34.438930 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7490 01:23:34.438981 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7491 01:23:34.439033 [CA 0] Center 43 (13~73) winsize 61
7492 01:23:34.439084 [CA 1] Center 43 (13~73) winsize 61
7493 01:23:34.439135 [CA 2] Center 38 (8~68) winsize 61
7494 01:23:34.439195 [CA 3] Center 38 (8~68) winsize 61
7495 01:23:34.439246 [CA 4] Center 36 (6~66) winsize 61
7496 01:23:34.439297 [CA 5] Center 35 (6~65) winsize 60
7497 01:23:34.439348
7498 01:23:34.439399 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7499 01:23:34.439450
7500 01:23:34.439501 [CATrainingPosCal] consider 2 rank data
7501 01:23:34.439551 u2DelayCellTimex100 = 285/100 ps
7502 01:23:34.439603 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7503 01:23:34.439654 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7504 01:23:34.439705 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7505 01:23:34.439756 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7506 01:23:34.439807 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7507 01:23:34.439858 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7508 01:23:34.439909
7509 01:23:34.439995 CA PerBit enable=1, Macro0, CA PI delay=35
7510 01:23:34.440060
7511 01:23:34.440111 [CBTSetCACLKResult] CA Dly = 35
7512 01:23:34.440181 CS Dly: 10 (0~42)
7513 01:23:34.440317 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7514 01:23:34.440388 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7515 01:23:34.440441
7516 01:23:34.440493 ----->DramcWriteLeveling(PI) begin...
7517 01:23:34.440546 ==
7518 01:23:34.440598 Dram Type= 6, Freq= 0, CH_0, rank 0
7519 01:23:34.440649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7520 01:23:34.440700 ==
7521 01:23:34.440752 Write leveling (Byte 0): 34 => 34
7522 01:23:34.440803 Write leveling (Byte 1): 27 => 27
7523 01:23:34.440855 DramcWriteLeveling(PI) end<-----
7524 01:23:34.440906
7525 01:23:34.440957 ==
7526 01:23:34.441008 Dram Type= 6, Freq= 0, CH_0, rank 0
7527 01:23:34.441059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7528 01:23:34.441111 ==
7529 01:23:34.441163 [Gating] SW mode calibration
7530 01:23:34.441214 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7531 01:23:34.441266 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7532 01:23:34.441521 1 4 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7533 01:23:34.441582 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7534 01:23:34.441636 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7535 01:23:34.441689 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
7536 01:23:34.441752 1 4 16 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
7537 01:23:34.441804 1 4 20 | B1->B0 | 3333 3635 | 0 1 | (0 0) (0 0)
7538 01:23:34.441855 1 4 24 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7539 01:23:34.441906 1 4 28 | B1->B0 | 3434 3736 | 1 1 | (1 1) (1 1)
7540 01:23:34.441968 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7541 01:23:34.442020 1 5 4 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7542 01:23:34.442070 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 0)
7543 01:23:34.442121 1 5 12 | B1->B0 | 3434 2c2b | 1 1 | (1 1) (0 0)
7544 01:23:34.442172 1 5 16 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
7545 01:23:34.442224 1 5 20 | B1->B0 | 2424 2626 | 1 0 | (1 0) (0 0)
7546 01:23:34.442275 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7547 01:23:34.442386 1 5 28 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7548 01:23:34.442439 1 6 0 | B1->B0 | 2323 2827 | 0 1 | (0 0) (1 1)
7549 01:23:34.442491 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7550 01:23:34.442541 1 6 8 | B1->B0 | 2323 3534 | 0 1 | (0 0) (0 0)
7551 01:23:34.442592 1 6 12 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
7552 01:23:34.442643 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7553 01:23:34.442694 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7554 01:23:34.442744 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7555 01:23:34.442795 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7556 01:23:34.442846 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7557 01:23:34.442897 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7558 01:23:34.442947 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7559 01:23:34.442998 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7560 01:23:34.443049 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7561 01:23:34.443100 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7562 01:23:34.443151 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7563 01:23:34.443201 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7564 01:23:34.443252 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7565 01:23:34.443303 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7566 01:23:34.443354 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7567 01:23:34.443414 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 01:23:34.443465 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 01:23:34.443516 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 01:23:34.443576 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 01:23:34.443643 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 01:23:34.449952 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 01:23:34.453588 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 01:23:34.456940 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 01:23:34.463495 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7576 01:23:34.466753 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7577 01:23:34.470242 Total UI for P1: 0, mck2ui 16
7578 01:23:34.473069 best dqsien dly found for B0: ( 1, 9, 12)
7579 01:23:34.476657 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7580 01:23:34.483111 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7581 01:23:34.483220 Total UI for P1: 0, mck2ui 16
7582 01:23:34.489653 best dqsien dly found for B1: ( 1, 9, 18)
7583 01:23:34.492896 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7584 01:23:34.496429 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7585 01:23:34.496522
7586 01:23:34.499822 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7587 01:23:34.503389 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7588 01:23:34.506210 [Gating] SW calibration Done
7589 01:23:34.506362 ==
7590 01:23:34.509699 Dram Type= 6, Freq= 0, CH_0, rank 0
7591 01:23:34.513309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7592 01:23:34.513399 ==
7593 01:23:34.516643 RX Vref Scan: 0
7594 01:23:34.516730
7595 01:23:34.516794 RX Vref 0 -> 0, step: 1
7596 01:23:34.516854
7597 01:23:34.519421 RX Delay 0 -> 252, step: 8
7598 01:23:34.523332 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7599 01:23:34.529809 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7600 01:23:34.533091 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7601 01:23:34.536116 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7602 01:23:34.540016 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7603 01:23:34.543329 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7604 01:23:34.549872 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7605 01:23:34.553154 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7606 01:23:34.556374 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7607 01:23:34.559877 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7608 01:23:34.562782 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7609 01:23:34.569344 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7610 01:23:34.572737 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7611 01:23:34.575944 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7612 01:23:34.579786 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7613 01:23:34.582974 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7614 01:23:34.586282 ==
7615 01:23:34.586418 Dram Type= 6, Freq= 0, CH_0, rank 0
7616 01:23:34.592668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7617 01:23:34.592765 ==
7618 01:23:34.592829 DQS Delay:
7619 01:23:34.596219 DQS0 = 0, DQS1 = 0
7620 01:23:34.596333 DQM Delay:
7621 01:23:34.599745 DQM0 = 137, DQM1 = 131
7622 01:23:34.599830 DQ Delay:
7623 01:23:34.603277 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135
7624 01:23:34.606017 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7625 01:23:34.609574 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7626 01:23:34.612452 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =135
7627 01:23:34.612542
7628 01:23:34.612605
7629 01:23:34.612664 ==
7630 01:23:34.616030 Dram Type= 6, Freq= 0, CH_0, rank 0
7631 01:23:34.622498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7632 01:23:34.622598 ==
7633 01:23:34.622663
7634 01:23:34.622723
7635 01:23:34.622780 TX Vref Scan disable
7636 01:23:34.626081 == TX Byte 0 ==
7637 01:23:34.629407 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7638 01:23:34.632840 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7639 01:23:34.636285 == TX Byte 1 ==
7640 01:23:34.639884 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7641 01:23:34.645857 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7642 01:23:34.645968 ==
7643 01:23:34.649457 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 01:23:34.652893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 01:23:34.652991 ==
7646 01:23:34.664503
7647 01:23:34.667855 TX Vref early break, caculate TX vref
7648 01:23:34.670668 TX Vref=16, minBit 0, minWin=23, winSum=379
7649 01:23:34.674000 TX Vref=18, minBit 7, minWin=23, winSum=387
7650 01:23:34.677566 TX Vref=20, minBit 4, minWin=24, winSum=402
7651 01:23:34.680984 TX Vref=22, minBit 1, minWin=25, winSum=411
7652 01:23:34.684523 TX Vref=24, minBit 0, minWin=25, winSum=419
7653 01:23:34.690663 TX Vref=26, minBit 0, minWin=26, winSum=429
7654 01:23:34.694193 TX Vref=28, minBit 6, minWin=25, winSum=423
7655 01:23:34.697884 TX Vref=30, minBit 6, minWin=24, winSum=413
7656 01:23:34.700646 TX Vref=32, minBit 1, minWin=23, winSum=404
7657 01:23:34.707276 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 26
7658 01:23:34.707394
7659 01:23:34.710744 Final TX Range 0 Vref 26
7660 01:23:34.710833
7661 01:23:34.710898 ==
7662 01:23:34.714261 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 01:23:34.717793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 01:23:34.717880 ==
7665 01:23:34.717945
7666 01:23:34.718004
7667 01:23:34.720643 TX Vref Scan disable
7668 01:23:34.727216 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7669 01:23:34.727311 == TX Byte 0 ==
7670 01:23:34.730699 u2DelayCellOfst[0]=10 cells (3 PI)
7671 01:23:34.734393 u2DelayCellOfst[1]=13 cells (4 PI)
7672 01:23:34.737679 u2DelayCellOfst[2]=10 cells (3 PI)
7673 01:23:34.740876 u2DelayCellOfst[3]=10 cells (3 PI)
7674 01:23:34.744318 u2DelayCellOfst[4]=6 cells (2 PI)
7675 01:23:34.747166 u2DelayCellOfst[5]=0 cells (0 PI)
7676 01:23:34.747261 u2DelayCellOfst[6]=17 cells (5 PI)
7677 01:23:34.750417 u2DelayCellOfst[7]=17 cells (5 PI)
7678 01:23:34.757021 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7679 01:23:34.760865 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7680 01:23:34.760961 == TX Byte 1 ==
7681 01:23:34.764267 u2DelayCellOfst[8]=3 cells (1 PI)
7682 01:23:34.767298 u2DelayCellOfst[9]=0 cells (0 PI)
7683 01:23:34.770470 u2DelayCellOfst[10]=10 cells (3 PI)
7684 01:23:34.773773 u2DelayCellOfst[11]=6 cells (2 PI)
7685 01:23:34.776929 u2DelayCellOfst[12]=10 cells (3 PI)
7686 01:23:34.780709 u2DelayCellOfst[13]=13 cells (4 PI)
7687 01:23:34.783855 u2DelayCellOfst[14]=17 cells (5 PI)
7688 01:23:34.787271 u2DelayCellOfst[15]=10 cells (3 PI)
7689 01:23:34.790825 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7690 01:23:34.797073 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7691 01:23:34.797175 DramC Write-DBI on
7692 01:23:34.797241 ==
7693 01:23:34.800331 Dram Type= 6, Freq= 0, CH_0, rank 0
7694 01:23:34.803907 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7695 01:23:34.804041 ==
7696 01:23:34.807014
7697 01:23:34.807099
7698 01:23:34.807163 TX Vref Scan disable
7699 01:23:34.810239 == TX Byte 0 ==
7700 01:23:34.813446 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7701 01:23:34.816986 == TX Byte 1 ==
7702 01:23:34.820645 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7703 01:23:34.823313 DramC Write-DBI off
7704 01:23:34.823397
7705 01:23:34.823460 [DATLAT]
7706 01:23:34.823518 Freq=1600, CH0 RK0
7707 01:23:34.823576
7708 01:23:34.826833 DATLAT Default: 0xf
7709 01:23:34.826914 0, 0xFFFF, sum = 0
7710 01:23:34.830478 1, 0xFFFF, sum = 0
7711 01:23:34.830561 2, 0xFFFF, sum = 0
7712 01:23:34.833268 3, 0xFFFF, sum = 0
7713 01:23:34.836873 4, 0xFFFF, sum = 0
7714 01:23:34.836969 5, 0xFFFF, sum = 0
7715 01:23:34.840507 6, 0xFFFF, sum = 0
7716 01:23:34.840606 7, 0xFFFF, sum = 0
7717 01:23:34.843210 8, 0xFFFF, sum = 0
7718 01:23:34.843292 9, 0xFFFF, sum = 0
7719 01:23:34.846617 10, 0xFFFF, sum = 0
7720 01:23:34.846728 11, 0xFFFF, sum = 0
7721 01:23:34.849925 12, 0xFFFF, sum = 0
7722 01:23:34.850040 13, 0xFFFF, sum = 0
7723 01:23:34.853516 14, 0x0, sum = 1
7724 01:23:34.853599 15, 0x0, sum = 2
7725 01:23:34.857067 16, 0x0, sum = 3
7726 01:23:34.857150 17, 0x0, sum = 4
7727 01:23:34.859638 best_step = 15
7728 01:23:34.859720
7729 01:23:34.859783 ==
7730 01:23:34.863281 Dram Type= 6, Freq= 0, CH_0, rank 0
7731 01:23:34.866643 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7732 01:23:34.866756 ==
7733 01:23:34.869873 RX Vref Scan: 1
7734 01:23:34.869980
7735 01:23:34.870070 Set Vref Range= 24 -> 127
7736 01:23:34.870157
7737 01:23:34.873112 RX Vref 24 -> 127, step: 1
7738 01:23:34.873206
7739 01:23:34.876367 RX Delay 27 -> 252, step: 4
7740 01:23:34.876449
7741 01:23:34.880324 Set Vref, RX VrefLevel [Byte0]: 24
7742 01:23:34.883315 [Byte1]: 24
7743 01:23:34.883402
7744 01:23:34.886752 Set Vref, RX VrefLevel [Byte0]: 25
7745 01:23:34.889960 [Byte1]: 25
7746 01:23:34.890072
7747 01:23:34.893140 Set Vref, RX VrefLevel [Byte0]: 26
7748 01:23:34.896254 [Byte1]: 26
7749 01:23:34.900548
7750 01:23:34.900645 Set Vref, RX VrefLevel [Byte0]: 27
7751 01:23:34.903861 [Byte1]: 27
7752 01:23:34.907581
7753 01:23:34.907674 Set Vref, RX VrefLevel [Byte0]: 28
7754 01:23:34.911076 [Byte1]: 28
7755 01:23:34.915714
7756 01:23:34.915836 Set Vref, RX VrefLevel [Byte0]: 29
7757 01:23:34.919042 [Byte1]: 29
7758 01:23:34.922926
7759 01:23:34.923015 Set Vref, RX VrefLevel [Byte0]: 30
7760 01:23:34.926142 [Byte1]: 30
7761 01:23:34.930687
7762 01:23:34.930788 Set Vref, RX VrefLevel [Byte0]: 31
7763 01:23:34.933447 [Byte1]: 31
7764 01:23:34.938463
7765 01:23:34.938559 Set Vref, RX VrefLevel [Byte0]: 32
7766 01:23:34.941263 [Byte1]: 32
7767 01:23:34.945405
7768 01:23:34.945523 Set Vref, RX VrefLevel [Byte0]: 33
7769 01:23:34.949005 [Byte1]: 33
7770 01:23:34.953195
7771 01:23:34.953291 Set Vref, RX VrefLevel [Byte0]: 34
7772 01:23:34.956440 [Byte1]: 34
7773 01:23:34.960743
7774 01:23:34.960834 Set Vref, RX VrefLevel [Byte0]: 35
7775 01:23:34.964286 [Byte1]: 35
7776 01:23:34.968333
7777 01:23:34.968425 Set Vref, RX VrefLevel [Byte0]: 36
7778 01:23:34.971274 [Byte1]: 36
7779 01:23:34.976022
7780 01:23:34.976119 Set Vref, RX VrefLevel [Byte0]: 37
7781 01:23:34.979184 [Byte1]: 37
7782 01:23:34.983001
7783 01:23:34.983095 Set Vref, RX VrefLevel [Byte0]: 38
7784 01:23:34.986423 [Byte1]: 38
7785 01:23:34.991029
7786 01:23:34.991146 Set Vref, RX VrefLevel [Byte0]: 39
7787 01:23:34.993931 [Byte1]: 39
7788 01:23:34.998161
7789 01:23:34.998277 Set Vref, RX VrefLevel [Byte0]: 40
7790 01:23:35.001433 [Byte1]: 40
7791 01:23:35.006080
7792 01:23:35.006174 Set Vref, RX VrefLevel [Byte0]: 41
7793 01:23:35.009339 [Byte1]: 41
7794 01:23:35.013279
7795 01:23:35.013371 Set Vref, RX VrefLevel [Byte0]: 42
7796 01:23:35.016330 [Byte1]: 42
7797 01:23:35.020805
7798 01:23:35.020897 Set Vref, RX VrefLevel [Byte0]: 43
7799 01:23:35.024166 [Byte1]: 43
7800 01:23:35.028572
7801 01:23:35.028680 Set Vref, RX VrefLevel [Byte0]: 44
7802 01:23:35.031703 [Byte1]: 44
7803 01:23:35.036124
7804 01:23:35.036213 Set Vref, RX VrefLevel [Byte0]: 45
7805 01:23:35.039442 [Byte1]: 45
7806 01:23:35.043660
7807 01:23:35.043757 Set Vref, RX VrefLevel [Byte0]: 46
7808 01:23:35.046945 [Byte1]: 46
7809 01:23:35.051190
7810 01:23:35.051316 Set Vref, RX VrefLevel [Byte0]: 47
7811 01:23:35.054637 [Byte1]: 47
7812 01:23:35.058837
7813 01:23:35.058929 Set Vref, RX VrefLevel [Byte0]: 48
7814 01:23:35.062230 [Byte1]: 48
7815 01:23:35.066280
7816 01:23:35.066390 Set Vref, RX VrefLevel [Byte0]: 49
7817 01:23:35.069134 [Byte1]: 49
7818 01:23:35.073396
7819 01:23:35.073513 Set Vref, RX VrefLevel [Byte0]: 50
7820 01:23:35.076879 [Byte1]: 50
7821 01:23:35.081123
7822 01:23:35.081217 Set Vref, RX VrefLevel [Byte0]: 51
7823 01:23:35.084553 [Byte1]: 51
7824 01:23:35.088490
7825 01:23:35.088585 Set Vref, RX VrefLevel [Byte0]: 52
7826 01:23:35.091778 [Byte1]: 52
7827 01:23:35.096254
7828 01:23:35.096350 Set Vref, RX VrefLevel [Byte0]: 53
7829 01:23:35.099523 [Byte1]: 53
7830 01:23:35.103908
7831 01:23:35.104006 Set Vref, RX VrefLevel [Byte0]: 54
7832 01:23:35.107382 [Byte1]: 54
7833 01:23:35.111533
7834 01:23:35.111630 Set Vref, RX VrefLevel [Byte0]: 55
7835 01:23:35.114844 [Byte1]: 55
7836 01:23:35.118993
7837 01:23:35.119083 Set Vref, RX VrefLevel [Byte0]: 56
7838 01:23:35.122413 [Byte1]: 56
7839 01:23:35.126355
7840 01:23:35.126486 Set Vref, RX VrefLevel [Byte0]: 57
7841 01:23:35.129694 [Byte1]: 57
7842 01:23:35.133580
7843 01:23:35.133703 Set Vref, RX VrefLevel [Byte0]: 58
7844 01:23:35.137067 [Byte1]: 58
7845 01:23:35.141072
7846 01:23:35.141191 Set Vref, RX VrefLevel [Byte0]: 59
7847 01:23:35.144911 [Byte1]: 59
7848 01:23:35.148532
7849 01:23:35.148662 Set Vref, RX VrefLevel [Byte0]: 60
7850 01:23:35.152182 [Byte1]: 60
7851 01:23:35.156425
7852 01:23:35.156549 Set Vref, RX VrefLevel [Byte0]: 61
7853 01:23:35.159928 [Byte1]: 61
7854 01:23:35.164083
7855 01:23:35.164199 Set Vref, RX VrefLevel [Byte0]: 62
7856 01:23:35.167291 [Byte1]: 62
7857 01:23:35.171413
7858 01:23:35.171532 Set Vref, RX VrefLevel [Byte0]: 63
7859 01:23:35.174884 [Byte1]: 63
7860 01:23:35.179104
7861 01:23:35.179222 Set Vref, RX VrefLevel [Byte0]: 64
7862 01:23:35.182607 [Byte1]: 64
7863 01:23:35.186849
7864 01:23:35.186973 Set Vref, RX VrefLevel [Byte0]: 65
7865 01:23:35.189504 [Byte1]: 65
7866 01:23:35.194275
7867 01:23:35.194438 Set Vref, RX VrefLevel [Byte0]: 66
7868 01:23:35.197674 [Byte1]: 66
7869 01:23:35.201510
7870 01:23:35.201673 Set Vref, RX VrefLevel [Byte0]: 67
7871 01:23:35.204754 [Byte1]: 67
7872 01:23:35.209489
7873 01:23:35.209609 Set Vref, RX VrefLevel [Byte0]: 68
7874 01:23:35.212221 [Byte1]: 68
7875 01:23:35.216440
7876 01:23:35.216559 Set Vref, RX VrefLevel [Byte0]: 69
7877 01:23:35.219891 [Byte1]: 69
7878 01:23:35.224345
7879 01:23:35.224438 Set Vref, RX VrefLevel [Byte0]: 70
7880 01:23:35.227429 [Byte1]: 70
7881 01:23:35.231649
7882 01:23:35.231740 Set Vref, RX VrefLevel [Byte0]: 71
7883 01:23:35.235023 [Byte1]: 71
7884 01:23:35.239229
7885 01:23:35.239342 Set Vref, RX VrefLevel [Byte0]: 72
7886 01:23:35.242524 [Byte1]: 72
7887 01:23:35.246786
7888 01:23:35.246941 Set Vref, RX VrefLevel [Byte0]: 73
7889 01:23:35.250194 [Byte1]: 73
7890 01:23:35.254225
7891 01:23:35.254365 Final RX Vref Byte 0 = 57 to rank0
7892 01:23:35.257662 Final RX Vref Byte 1 = 64 to rank0
7893 01:23:35.260893 Final RX Vref Byte 0 = 57 to rank1
7894 01:23:35.264065 Final RX Vref Byte 1 = 64 to rank1==
7895 01:23:35.267756 Dram Type= 6, Freq= 0, CH_0, rank 0
7896 01:23:35.274328 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7897 01:23:35.274446 ==
7898 01:23:35.274514 DQS Delay:
7899 01:23:35.274574 DQS0 = 0, DQS1 = 0
7900 01:23:35.277603 DQM Delay:
7901 01:23:35.277687 DQM0 = 133, DQM1 = 128
7902 01:23:35.280930 DQ Delay:
7903 01:23:35.284567 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =130
7904 01:23:35.287356 DQ4 =132, DQ5 =124, DQ6 =138, DQ7 =138
7905 01:23:35.290881 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122
7906 01:23:35.294332 DQ12 =132, DQ13 =132, DQ14 =140, DQ15 =136
7907 01:23:35.294438
7908 01:23:35.294503
7909 01:23:35.294562
7910 01:23:35.298195 [DramC_TX_OE_Calibration] TA2
7911 01:23:35.300852 Original DQ_B0 (3 6) =30, OEN = 27
7912 01:23:35.304329 Original DQ_B1 (3 6) =30, OEN = 27
7913 01:23:35.307590 24, 0x0, End_B0=24 End_B1=24
7914 01:23:35.307691 25, 0x0, End_B0=25 End_B1=25
7915 01:23:35.310893 26, 0x0, End_B0=26 End_B1=26
7916 01:23:35.314229 27, 0x0, End_B0=27 End_B1=27
7917 01:23:35.317548 28, 0x0, End_B0=28 End_B1=28
7918 01:23:35.320995 29, 0x0, End_B0=29 End_B1=29
7919 01:23:35.321087 30, 0x0, End_B0=30 End_B1=30
7920 01:23:35.324518 31, 0x4545, End_B0=30 End_B1=30
7921 01:23:35.327319 Byte0 end_step=30 best_step=27
7922 01:23:35.330764 Byte1 end_step=30 best_step=27
7923 01:23:35.351924 Byte0 TX OE(2T, 0.5T) = (3, 3)
7924 01:23:35.352062 Byte1 TX OE(2T, 0.5T) = (3, 3)
7925 01:23:35.352130
7926 01:23:35.352191
7927 01:23:35.352248 [DQSOSCAuto] RK0, (LSB)MR18= 0x231f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 392 ps
7928 01:23:35.352306 CH0 RK0: MR19=303, MR18=231F
7929 01:23:35.354168 CH0_RK0: MR19=0x303, MR18=0x231F, DQSOSC=392, MR23=63, INC=24, DEC=16
7930 01:23:35.354255
7931 01:23:35.357505 ----->DramcWriteLeveling(PI) begin...
7932 01:23:35.357592 ==
7933 01:23:35.360950 Dram Type= 6, Freq= 0, CH_0, rank 1
7934 01:23:35.363799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7935 01:23:35.363886 ==
7936 01:23:35.367037 Write leveling (Byte 0): 36 => 36
7937 01:23:35.370530 Write leveling (Byte 1): 29 => 29
7938 01:23:35.373856 DramcWriteLeveling(PI) end<-----
7939 01:23:35.373968
7940 01:23:35.374086 ==
7941 01:23:35.377220 Dram Type= 6, Freq= 0, CH_0, rank 1
7942 01:23:35.380321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7943 01:23:35.380410 ==
7944 01:23:35.383492 [Gating] SW mode calibration
7945 01:23:35.390649 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7946 01:23:35.396968 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7947 01:23:35.400383 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7948 01:23:35.406959 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7949 01:23:35.410359 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7950 01:23:35.413844 1 4 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7951 01:23:35.417141 1 4 16 | B1->B0 | 2d2d 3636 | 1 0 | (1 1) (1 1)
7952 01:23:36.010206 1 4 20 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
7953 01:23:36.010383 1 4 24 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7954 01:23:36.010451 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7955 01:23:36.010512 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7956 01:23:36.010570 1 5 4 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7957 01:23:36.010626 1 5 8 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
7958 01:23:36.010681 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
7959 01:23:36.010735 1 5 16 | B1->B0 | 2f2f 2726 | 1 1 | (1 0) (0 1)
7960 01:23:36.010788 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7961 01:23:36.010842 1 5 24 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (1 1)
7962 01:23:36.010895 1 5 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7963 01:23:36.010947 1 6 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7964 01:23:36.011000 1 6 4 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (1 1)
7965 01:23:36.011059 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7966 01:23:36.011139 1 6 12 | B1->B0 | 2424 3636 | 0 0 | (0 0) (1 1)
7967 01:23:36.011243 1 6 16 | B1->B0 | 3636 4645 | 1 1 | (0 0) (0 0)
7968 01:23:36.011315 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7969 01:23:36.011368 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7970 01:23:36.011421 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7971 01:23:36.011473 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7972 01:23:36.011525 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7973 01:23:36.011578 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7974 01:23:36.011630 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7975 01:23:36.011715 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7976 01:23:36.011767 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7977 01:23:36.011819 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7978 01:23:36.011871 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7979 01:23:36.011924 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7980 01:23:36.011976 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7981 01:23:36.012045 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7982 01:23:36.012112 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7983 01:23:36.012164 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7984 01:23:36.012215 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7985 01:23:36.012266 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7986 01:23:36.012318 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7987 01:23:36.012370 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7988 01:23:36.012421 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 01:23:36.012473 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 01:23:36.012525 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7991 01:23:36.012576 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7992 01:23:36.012628 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7993 01:23:36.012679 Total UI for P1: 0, mck2ui 16
7994 01:23:36.012732 best dqsien dly found for B0: ( 1, 9, 14)
7995 01:23:36.012784 Total UI for P1: 0, mck2ui 16
7996 01:23:36.012836 best dqsien dly found for B1: ( 1, 9, 14)
7997 01:23:36.012888 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7998 01:23:36.012939 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
7999 01:23:36.012991
8000 01:23:36.013044 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8001 01:23:36.013097 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8002 01:23:36.013148 [Gating] SW calibration Done
8003 01:23:36.013200 ==
8004 01:23:36.013252 Dram Type= 6, Freq= 0, CH_0, rank 1
8005 01:23:36.013305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8006 01:23:36.013357 ==
8007 01:23:36.013409 RX Vref Scan: 0
8008 01:23:36.013461
8009 01:23:36.013512 RX Vref 0 -> 0, step: 1
8010 01:23:36.013564
8011 01:23:36.013616 RX Delay 0 -> 252, step: 8
8012 01:23:36.013667 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8013 01:23:36.013720 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8014 01:23:36.013772 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8015 01:23:36.013823 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8016 01:23:36.013874 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8017 01:23:36.013926 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8018 01:23:36.013977 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8019 01:23:36.014029 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8020 01:23:36.014080 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8021 01:23:36.014132 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8022 01:23:36.014183 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8023 01:23:36.014235 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8024 01:23:36.014287 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8025 01:23:36.014375 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8026 01:23:36.014427 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8027 01:23:36.014479 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8028 01:23:36.014531 ==
8029 01:23:36.014583 Dram Type= 6, Freq= 0, CH_0, rank 1
8030 01:23:36.014636 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8031 01:23:36.014688 ==
8032 01:23:36.014740 DQS Delay:
8033 01:23:36.014809 DQS0 = 0, DQS1 = 0
8034 01:23:36.014862 DQM Delay:
8035 01:23:36.014929 DQM0 = 137, DQM1 = 127
8036 01:23:36.014981 DQ Delay:
8037 01:23:36.015033 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8038 01:23:36.015085 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8039 01:23:36.015137 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
8040 01:23:36.015205 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8041 01:23:36.015258
8042 01:23:36.015311
8043 01:23:36.015363 ==
8044 01:23:36.015416 Dram Type= 6, Freq= 0, CH_0, rank 1
8045 01:23:36.015470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8046 01:23:36.015523 ==
8047 01:23:36.015589
8048 01:23:36.015640
8049 01:23:36.015691 TX Vref Scan disable
8050 01:23:36.015743 == TX Byte 0 ==
8051 01:23:36.015794 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8052 01:23:36.015847 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8053 01:23:36.015899 == TX Byte 1 ==
8054 01:23:36.015950 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8055 01:23:36.016001 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8056 01:23:36.016052 ==
8057 01:23:36.016105 Dram Type= 6, Freq= 0, CH_0, rank 1
8058 01:23:36.016361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8059 01:23:36.016421 ==
8060 01:23:36.016475
8061 01:23:36.016527 TX Vref early break, caculate TX vref
8062 01:23:36.016581 TX Vref=16, minBit 1, minWin=23, winSum=386
8063 01:23:36.016634 TX Vref=18, minBit 0, minWin=24, winSum=400
8064 01:23:36.016686 TX Vref=20, minBit 0, minWin=24, winSum=403
8065 01:23:36.016740 TX Vref=22, minBit 3, minWin=24, winSum=410
8066 01:23:36.016793 TX Vref=24, minBit 0, minWin=25, winSum=419
8067 01:23:36.016845 TX Vref=26, minBit 0, minWin=25, winSum=427
8068 01:23:36.016897 TX Vref=28, minBit 7, minWin=25, winSum=420
8069 01:23:36.016949 TX Vref=30, minBit 3, minWin=25, winSum=418
8070 01:23:36.017032 TX Vref=32, minBit 3, minWin=24, winSum=412
8071 01:23:36.017083 TX Vref=34, minBit 1, minWin=24, winSum=401
8072 01:23:36.017135 [TxChooseVref] Worse bit 0, Min win 25, Win sum 427, Final Vref 26
8073 01:23:36.017188
8074 01:23:36.017240 Final TX Range 0 Vref 26
8075 01:23:36.017292
8076 01:23:36.017344 ==
8077 01:23:36.017396 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 01:23:36.017448 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 01:23:36.017500 ==
8080 01:23:36.017552
8081 01:23:36.017604
8082 01:23:36.017655 TX Vref Scan disable
8083 01:23:36.017707 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8084 01:23:36.017759 == TX Byte 0 ==
8085 01:23:36.017811 u2DelayCellOfst[0]=10 cells (3 PI)
8086 01:23:36.017862 u2DelayCellOfst[1]=17 cells (5 PI)
8087 01:23:36.017914 u2DelayCellOfst[2]=10 cells (3 PI)
8088 01:23:36.017965 u2DelayCellOfst[3]=10 cells (3 PI)
8089 01:23:36.018017 u2DelayCellOfst[4]=6 cells (2 PI)
8090 01:23:36.018068 u2DelayCellOfst[5]=0 cells (0 PI)
8091 01:23:36.018119 u2DelayCellOfst[6]=13 cells (4 PI)
8092 01:23:36.018170 u2DelayCellOfst[7]=13 cells (4 PI)
8093 01:23:36.018221 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8094 01:23:36.018291 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8095 01:23:36.018365 == TX Byte 1 ==
8096 01:23:36.018417 u2DelayCellOfst[8]=0 cells (0 PI)
8097 01:23:36.018469 u2DelayCellOfst[9]=0 cells (0 PI)
8098 01:23:36.018520 u2DelayCellOfst[10]=6 cells (2 PI)
8099 01:23:36.018572 u2DelayCellOfst[11]=3 cells (1 PI)
8100 01:23:36.018624 u2DelayCellOfst[12]=10 cells (3 PI)
8101 01:23:36.018675 u2DelayCellOfst[13]=10 cells (3 PI)
8102 01:23:36.018727 u2DelayCellOfst[14]=13 cells (4 PI)
8103 01:23:36.018795 u2DelayCellOfst[15]=10 cells (3 PI)
8104 01:23:36.018847 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8105 01:23:36.018900 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8106 01:23:36.018953 DramC Write-DBI on
8107 01:23:36.019005 ==
8108 01:23:36.019059 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 01:23:36.019127 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 01:23:36.019179 ==
8111 01:23:36.019231
8112 01:23:36.019282
8113 01:23:36.019333 TX Vref Scan disable
8114 01:23:36.019385 == TX Byte 0 ==
8115 01:23:36.019437 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8116 01:23:36.019489 == TX Byte 1 ==
8117 01:23:36.019540 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8118 01:23:36.019592 DramC Write-DBI off
8119 01:23:36.019643
8120 01:23:36.019694 [DATLAT]
8121 01:23:36.019746 Freq=1600, CH0 RK1
8122 01:23:36.019798
8123 01:23:36.019850 DATLAT Default: 0xf
8124 01:23:36.019901 0, 0xFFFF, sum = 0
8125 01:23:36.019955 1, 0xFFFF, sum = 0
8126 01:23:36.020008 2, 0xFFFF, sum = 0
8127 01:23:36.020060 3, 0xFFFF, sum = 0
8128 01:23:36.020112 4, 0xFFFF, sum = 0
8129 01:23:36.020165 5, 0xFFFF, sum = 0
8130 01:23:36.020217 6, 0xFFFF, sum = 0
8131 01:23:36.020269 7, 0xFFFF, sum = 0
8132 01:23:36.020321 8, 0xFFFF, sum = 0
8133 01:23:36.020374 9, 0xFFFF, sum = 0
8134 01:23:36.020426 10, 0xFFFF, sum = 0
8135 01:23:36.020478 11, 0xFFFF, sum = 0
8136 01:23:36.020530 12, 0xFFFF, sum = 0
8137 01:23:36.020582 13, 0xFFFF, sum = 0
8138 01:23:36.020634 14, 0x0, sum = 1
8139 01:23:36.020686 15, 0x0, sum = 2
8140 01:23:36.020738 16, 0x0, sum = 3
8141 01:23:36.020791 17, 0x0, sum = 4
8142 01:23:36.020843 best_step = 15
8143 01:23:36.020895
8144 01:23:36.020948 ==
8145 01:23:36.021022 Dram Type= 6, Freq= 0, CH_0, rank 1
8146 01:23:36.021076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8147 01:23:36.021159 ==
8148 01:23:36.021212 RX Vref Scan: 0
8149 01:23:36.021264
8150 01:23:36.021316 RX Vref 0 -> 0, step: 1
8151 01:23:36.021368
8152 01:23:36.021420 RX Delay 19 -> 252, step: 4
8153 01:23:36.021473 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8154 01:23:36.021525 iDelay=191, Bit 1, Center 136 (91 ~ 182) 92
8155 01:23:36.021578 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8156 01:23:36.021645 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8157 01:23:36.021700 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8158 01:23:36.024642 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8159 01:23:36.031509 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8160 01:23:36.034644 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8161 01:23:36.038032 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8162 01:23:36.041218 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8163 01:23:36.044509 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8164 01:23:36.051395 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8165 01:23:36.054810 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8166 01:23:36.058285 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8167 01:23:36.061454 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8168 01:23:36.064685 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8169 01:23:36.068041 ==
8170 01:23:36.071051 Dram Type= 6, Freq= 0, CH_0, rank 1
8171 01:23:36.074365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8172 01:23:36.074473 ==
8173 01:23:36.074542 DQS Delay:
8174 01:23:36.078079 DQS0 = 0, DQS1 = 0
8175 01:23:36.078163 DQM Delay:
8176 01:23:36.081136 DQM0 = 134, DQM1 = 126
8177 01:23:36.081236 DQ Delay:
8178 01:23:36.084756 DQ0 =134, DQ1 =136, DQ2 =130, DQ3 =134
8179 01:23:36.087508 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8180 01:23:36.090880 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8181 01:23:36.094217 DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =134
8182 01:23:36.094332
8183 01:23:36.094414
8184 01:23:36.094474
8185 01:23:36.097701 [DramC_TX_OE_Calibration] TA2
8186 01:23:36.101223 Original DQ_B0 (3 6) =30, OEN = 27
8187 01:23:36.104685 Original DQ_B1 (3 6) =30, OEN = 27
8188 01:23:36.107659 24, 0x0, End_B0=24 End_B1=24
8189 01:23:36.111118 25, 0x0, End_B0=25 End_B1=25
8190 01:23:36.111212 26, 0x0, End_B0=26 End_B1=26
8191 01:23:36.114664 27, 0x0, End_B0=27 End_B1=27
8192 01:23:36.118054 28, 0x0, End_B0=28 End_B1=28
8193 01:23:36.120753 29, 0x0, End_B0=29 End_B1=29
8194 01:23:36.124199 30, 0x0, End_B0=30 End_B1=30
8195 01:23:36.124292 31, 0x4141, End_B0=30 End_B1=30
8196 01:23:36.127701 Byte0 end_step=30 best_step=27
8197 01:23:36.131254 Byte1 end_step=30 best_step=27
8198 01:23:36.134126 Byte0 TX OE(2T, 0.5T) = (3, 3)
8199 01:23:36.137601 Byte1 TX OE(2T, 0.5T) = (3, 3)
8200 01:23:36.137693
8201 01:23:36.137759
8202 01:23:36.144365 [DQSOSCAuto] RK1, (LSB)MR18= 0x210a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
8203 01:23:36.147879 CH0 RK1: MR19=303, MR18=210A
8204 01:23:36.154285 CH0_RK1: MR19=0x303, MR18=0x210A, DQSOSC=393, MR23=63, INC=23, DEC=15
8205 01:23:36.157213 [RxdqsGatingPostProcess] freq 1600
8206 01:23:36.164183 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8207 01:23:36.164302 best DQS0 dly(2T, 0.5T) = (1, 1)
8208 01:23:36.167655 best DQS1 dly(2T, 0.5T) = (1, 1)
8209 01:23:36.171083 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8210 01:23:36.173884 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8211 01:23:36.177208 best DQS0 dly(2T, 0.5T) = (1, 1)
8212 01:23:36.180553 best DQS1 dly(2T, 0.5T) = (1, 1)
8213 01:23:36.183983 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8214 01:23:36.187494 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8215 01:23:36.190565 Pre-setting of DQS Precalculation
8216 01:23:36.193864 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8217 01:23:36.196998 ==
8218 01:23:36.197091 Dram Type= 6, Freq= 0, CH_1, rank 0
8219 01:23:36.204172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8220 01:23:36.204278 ==
8221 01:23:36.206962 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8222 01:23:36.213974 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8223 01:23:36.217536 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8224 01:23:36.223558 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8225 01:23:36.231927 [CA 0] Center 41 (12~71) winsize 60
8226 01:23:36.234489 [CA 1] Center 41 (12~71) winsize 60
8227 01:23:36.238065 [CA 2] Center 38 (9~68) winsize 60
8228 01:23:36.241409 [CA 3] Center 37 (8~66) winsize 59
8229 01:23:36.244905 [CA 4] Center 38 (9~68) winsize 60
8230 01:23:36.248425 [CA 5] Center 36 (7~66) winsize 60
8231 01:23:36.248581
8232 01:23:36.251809 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8233 01:23:36.251965
8234 01:23:36.254692 [CATrainingPosCal] consider 1 rank data
8235 01:23:36.258230 u2DelayCellTimex100 = 285/100 ps
8236 01:23:36.261197 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8237 01:23:36.268280 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8238 01:23:36.271400 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8239 01:23:36.275144 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8240 01:23:36.277959 CA4 delay=38 (9~68),Diff = 2 PI (6 cell)
8241 01:23:36.281274 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8242 01:23:36.281376
8243 01:23:36.284447 CA PerBit enable=1, Macro0, CA PI delay=36
8244 01:23:36.284547
8245 01:23:36.287811 [CBTSetCACLKResult] CA Dly = 36
8246 01:23:36.291210 CS Dly: 10 (0~41)
8247 01:23:36.294793 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8248 01:23:36.297607 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8249 01:23:36.297745 ==
8250 01:23:36.300985 Dram Type= 6, Freq= 0, CH_1, rank 1
8251 01:23:36.304279 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8252 01:23:36.307763 ==
8253 01:23:36.310930 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8254 01:23:36.314166 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8255 01:23:36.320912 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8256 01:23:36.327300 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8257 01:23:36.334996 [CA 0] Center 42 (12~72) winsize 61
8258 01:23:36.338234 [CA 1] Center 42 (12~72) winsize 61
8259 01:23:36.341785 [CA 2] Center 38 (9~68) winsize 60
8260 01:23:36.345129 [CA 3] Center 38 (8~68) winsize 61
8261 01:23:36.348072 [CA 4] Center 38 (8~69) winsize 62
8262 01:23:36.351587 [CA 5] Center 37 (8~67) winsize 60
8263 01:23:36.351716
8264 01:23:36.355021 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8265 01:23:36.355126
8266 01:23:36.358566 [CATrainingPosCal] consider 2 rank data
8267 01:23:36.361344 u2DelayCellTimex100 = 285/100 ps
8268 01:23:36.364924 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8269 01:23:36.371139 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8270 01:23:36.374681 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8271 01:23:36.378176 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8272 01:23:36.381672 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8273 01:23:36.384517 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8274 01:23:36.384615
8275 01:23:36.387946 CA PerBit enable=1, Macro0, CA PI delay=37
8276 01:23:36.388038
8277 01:23:36.390962 [CBTSetCACLKResult] CA Dly = 37
8278 01:23:36.394807 CS Dly: 11 (0~44)
8279 01:23:36.397628 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8280 01:23:36.401069 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8281 01:23:36.401167
8282 01:23:36.404640 ----->DramcWriteLeveling(PI) begin...
8283 01:23:36.404731 ==
8284 01:23:36.407706 Dram Type= 6, Freq= 0, CH_1, rank 0
8285 01:23:36.410782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8286 01:23:36.414319 ==
8287 01:23:36.414456 Write leveling (Byte 0): 27 => 27
8288 01:23:36.418143 Write leveling (Byte 1): 28 => 28
8289 01:23:36.421099 DramcWriteLeveling(PI) end<-----
8290 01:23:36.421220
8291 01:23:36.421316 ==
8292 01:23:36.424428 Dram Type= 6, Freq= 0, CH_1, rank 0
8293 01:23:36.431191 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8294 01:23:36.431322 ==
8295 01:23:36.434236 [Gating] SW mode calibration
8296 01:23:36.440825 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8297 01:23:36.444242 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8298 01:23:36.450599 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8299 01:23:36.454060 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8300 01:23:36.457663 1 4 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8301 01:23:36.463988 1 4 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8302 01:23:36.467480 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8303 01:23:36.470990 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8304 01:23:36.477124 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8305 01:23:36.480631 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8306 01:23:36.484135 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8307 01:23:36.490426 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8308 01:23:36.494037 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8309 01:23:36.497424 1 5 12 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (1 0)
8310 01:23:36.503703 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8311 01:23:36.506934 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8312 01:23:36.510186 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8313 01:23:36.517076 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8314 01:23:36.520528 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8315 01:23:36.523686 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8316 01:23:36.530108 1 6 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
8317 01:23:36.533344 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8318 01:23:36.536720 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8319 01:23:36.543488 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8320 01:23:36.546372 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8321 01:23:36.550084 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8322 01:23:36.553907 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8323 01:23:36.559995 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8324 01:23:36.563375 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8325 01:23:36.566708 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8326 01:23:36.573084 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8327 01:23:36.576681 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8328 01:23:36.579934 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8329 01:23:36.586906 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8330 01:23:36.590326 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8331 01:23:36.593014 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8332 01:23:36.600123 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8333 01:23:36.603075 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8334 01:23:36.606606 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8335 01:23:36.613316 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8336 01:23:36.616686 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8337 01:23:36.620100 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8338 01:23:36.626355 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 01:23:36.630006 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 01:23:36.633264 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8341 01:23:36.640142 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8342 01:23:36.643405 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8343 01:23:36.646714 Total UI for P1: 0, mck2ui 16
8344 01:23:36.650076 best dqsien dly found for B0: ( 1, 9, 10)
8345 01:23:36.653336 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 01:23:36.656425 Total UI for P1: 0, mck2ui 16
8347 01:23:36.660077 best dqsien dly found for B1: ( 1, 9, 12)
8348 01:23:36.662919 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8349 01:23:36.666579 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8350 01:23:36.666709
8351 01:23:36.669714 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8352 01:23:36.676283 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8353 01:23:36.676438 [Gating] SW calibration Done
8354 01:23:36.676534 ==
8355 01:23:36.679511 Dram Type= 6, Freq= 0, CH_1, rank 0
8356 01:23:36.686293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8357 01:23:36.686427 ==
8358 01:23:36.686497 RX Vref Scan: 0
8359 01:23:36.686558
8360 01:23:36.689647 RX Vref 0 -> 0, step: 1
8361 01:23:36.689767
8362 01:23:36.693056 RX Delay 0 -> 252, step: 8
8363 01:23:36.696200 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8364 01:23:36.699596 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8365 01:23:36.702882 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8366 01:23:36.709333 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8367 01:23:36.712898 iDelay=200, Bit 4, Center 135 (88 ~ 183) 96
8368 01:23:36.716371 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8369 01:23:36.719552 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8370 01:23:36.722802 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8371 01:23:36.729253 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
8372 01:23:36.732801 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8373 01:23:36.736338 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8374 01:23:36.739136 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8375 01:23:36.742696 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8376 01:23:36.749366 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8377 01:23:36.753017 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8378 01:23:36.755917 iDelay=200, Bit 15, Center 147 (96 ~ 199) 104
8379 01:23:36.756014 ==
8380 01:23:36.759305 Dram Type= 6, Freq= 0, CH_1, rank 0
8381 01:23:36.762776 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8382 01:23:36.762870 ==
8383 01:23:36.766200 DQS Delay:
8384 01:23:36.766286 DQS0 = 0, DQS1 = 0
8385 01:23:36.769419 DQM Delay:
8386 01:23:36.769504 DQM0 = 137, DQM1 = 134
8387 01:23:36.769571 DQ Delay:
8388 01:23:36.775812 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8389 01:23:36.778907 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8390 01:23:36.782629 DQ8 =123, DQ9 =123, DQ10 =131, DQ11 =127
8391 01:23:36.785593 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =147
8392 01:23:36.785688
8393 01:23:36.785755
8394 01:23:36.785815 ==
8395 01:23:36.788830 Dram Type= 6, Freq= 0, CH_1, rank 0
8396 01:23:36.792497 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8397 01:23:36.792602 ==
8398 01:23:36.792669
8399 01:23:36.792730
8400 01:23:36.795824 TX Vref Scan disable
8401 01:23:36.799173 == TX Byte 0 ==
8402 01:23:36.802410 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8403 01:23:36.805589 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8404 01:23:36.808646 == TX Byte 1 ==
8405 01:23:36.811847 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8406 01:23:36.815942 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8407 01:23:36.816049 ==
8408 01:23:36.818627 Dram Type= 6, Freq= 0, CH_1, rank 0
8409 01:23:36.824999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8410 01:23:36.825108 ==
8411 01:23:36.837411
8412 01:23:36.841033 TX Vref early break, caculate TX vref
8413 01:23:36.844578 TX Vref=16, minBit 0, minWin=22, winSum=377
8414 01:23:36.847383 TX Vref=18, minBit 1, minWin=23, winSum=384
8415 01:23:36.850772 TX Vref=20, minBit 1, minWin=23, winSum=392
8416 01:23:36.854189 TX Vref=22, minBit 0, minWin=24, winSum=407
8417 01:23:36.857679 TX Vref=24, minBit 1, minWin=25, winSum=417
8418 01:23:36.863836 TX Vref=26, minBit 0, minWin=25, winSum=418
8419 01:23:36.867363 TX Vref=28, minBit 0, minWin=25, winSum=422
8420 01:23:36.870885 TX Vref=30, minBit 0, minWin=25, winSum=421
8421 01:23:36.873758 TX Vref=32, minBit 0, minWin=24, winSum=409
8422 01:23:36.877011 TX Vref=34, minBit 0, minWin=24, winSum=403
8423 01:23:36.880565 TX Vref=36, minBit 0, minWin=23, winSum=390
8424 01:23:36.886986 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 28
8425 01:23:36.887103
8426 01:23:36.890527 Final TX Range 0 Vref 28
8427 01:23:36.890655
8428 01:23:36.890747 ==
8429 01:23:36.893853 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 01:23:36.897301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 01:23:36.897418 ==
8432 01:23:36.897513
8433 01:23:36.897582
8434 01:23:36.900429 TX Vref Scan disable
8435 01:23:36.906891 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8436 01:23:36.907067 == TX Byte 0 ==
8437 01:23:36.910199 u2DelayCellOfst[0]=17 cells (5 PI)
8438 01:23:36.913747 u2DelayCellOfst[1]=10 cells (3 PI)
8439 01:23:36.916870 u2DelayCellOfst[2]=0 cells (0 PI)
8440 01:23:36.920484 u2DelayCellOfst[3]=6 cells (2 PI)
8441 01:23:36.923859 u2DelayCellOfst[4]=6 cells (2 PI)
8442 01:23:36.926643 u2DelayCellOfst[5]=17 cells (5 PI)
8443 01:23:36.930150 u2DelayCellOfst[6]=17 cells (5 PI)
8444 01:23:36.934077 u2DelayCellOfst[7]=6 cells (2 PI)
8445 01:23:36.936924 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8446 01:23:36.940081 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8447 01:23:36.943460 == TX Byte 1 ==
8448 01:23:36.947173 u2DelayCellOfst[8]=0 cells (0 PI)
8449 01:23:36.947340 u2DelayCellOfst[9]=3 cells (1 PI)
8450 01:23:36.950477 u2DelayCellOfst[10]=10 cells (3 PI)
8451 01:23:36.953793 u2DelayCellOfst[11]=3 cells (1 PI)
8452 01:23:36.956521 u2DelayCellOfst[12]=13 cells (4 PI)
8453 01:23:36.960040 u2DelayCellOfst[13]=13 cells (4 PI)
8454 01:23:36.963243 u2DelayCellOfst[14]=17 cells (5 PI)
8455 01:23:36.966827 u2DelayCellOfst[15]=13 cells (4 PI)
8456 01:23:36.970416 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8457 01:23:36.976613 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8458 01:23:36.976719 DramC Write-DBI on
8459 01:23:36.976788 ==
8460 01:23:36.980037 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 01:23:36.986822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 01:23:36.986935 ==
8463 01:23:36.987001
8464 01:23:36.987060
8465 01:23:36.987116 TX Vref Scan disable
8466 01:23:36.990360 == TX Byte 0 ==
8467 01:23:36.993831 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8468 01:23:36.997338 == TX Byte 1 ==
8469 01:23:37.000292 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8470 01:23:37.003823 DramC Write-DBI off
8471 01:23:37.003919
8472 01:23:37.003985 [DATLAT]
8473 01:23:37.004044 Freq=1600, CH1 RK0
8474 01:23:37.004103
8475 01:23:37.007388 DATLAT Default: 0xf
8476 01:23:37.007478 0, 0xFFFF, sum = 0
8477 01:23:37.011002 1, 0xFFFF, sum = 0
8478 01:23:37.011153 2, 0xFFFF, sum = 0
8479 01:23:37.013573 3, 0xFFFF, sum = 0
8480 01:23:37.016973 4, 0xFFFF, sum = 0
8481 01:23:37.017092 5, 0xFFFF, sum = 0
8482 01:23:37.020203 6, 0xFFFF, sum = 0
8483 01:23:37.020293 7, 0xFFFF, sum = 0
8484 01:23:37.023572 8, 0xFFFF, sum = 0
8485 01:23:37.023661 9, 0xFFFF, sum = 0
8486 01:23:37.027463 10, 0xFFFF, sum = 0
8487 01:23:37.027598 11, 0xFFFF, sum = 0
8488 01:23:37.030127 12, 0xFFFF, sum = 0
8489 01:23:37.030216 13, 0xFFFF, sum = 0
8490 01:23:37.033395 14, 0x0, sum = 1
8491 01:23:37.033484 15, 0x0, sum = 2
8492 01:23:37.037146 16, 0x0, sum = 3
8493 01:23:37.037237 17, 0x0, sum = 4
8494 01:23:37.040220 best_step = 15
8495 01:23:37.040305
8496 01:23:37.040371 ==
8497 01:23:37.043729 Dram Type= 6, Freq= 0, CH_1, rank 0
8498 01:23:37.046844 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8499 01:23:37.046945 ==
8500 01:23:37.050051 RX Vref Scan: 1
8501 01:23:37.050140
8502 01:23:37.050208 Set Vref Range= 24 -> 127
8503 01:23:37.050272
8504 01:23:37.053117 RX Vref 24 -> 127, step: 1
8505 01:23:37.053220
8506 01:23:37.056807 RX Delay 27 -> 252, step: 4
8507 01:23:37.056911
8508 01:23:37.060272 Set Vref, RX VrefLevel [Byte0]: 24
8509 01:23:37.063052 [Byte1]: 24
8510 01:23:37.063210
8511 01:23:37.066523 Set Vref, RX VrefLevel [Byte0]: 25
8512 01:23:37.069940 [Byte1]: 25
8513 01:23:37.070085
8514 01:23:37.073520 Set Vref, RX VrefLevel [Byte0]: 26
8515 01:23:37.076244 [Byte1]: 26
8516 01:23:37.081150
8517 01:23:37.081357 Set Vref, RX VrefLevel [Byte0]: 27
8518 01:23:37.083893 [Byte1]: 27
8519 01:23:37.087894
8520 01:23:37.088057 Set Vref, RX VrefLevel [Byte0]: 28
8521 01:23:37.091398 [Byte1]: 28
8522 01:23:37.095547
8523 01:23:37.095662 Set Vref, RX VrefLevel [Byte0]: 29
8524 01:23:37.098911 [Byte1]: 29
8525 01:23:37.103274
8526 01:23:37.103374 Set Vref, RX VrefLevel [Byte0]: 30
8527 01:23:37.106800 [Byte1]: 30
8528 01:23:37.110945
8529 01:23:37.111103 Set Vref, RX VrefLevel [Byte0]: 31
8530 01:23:37.114291 [Byte1]: 31
8531 01:23:37.118543
8532 01:23:37.118646 Set Vref, RX VrefLevel [Byte0]: 32
8533 01:23:37.121883 [Byte1]: 32
8534 01:23:37.125993
8535 01:23:37.126094 Set Vref, RX VrefLevel [Byte0]: 33
8536 01:23:37.129441 [Byte1]: 33
8537 01:23:37.133403
8538 01:23:37.133508 Set Vref, RX VrefLevel [Byte0]: 34
8539 01:23:37.136995 [Byte1]: 34
8540 01:23:37.141096
8541 01:23:37.141233 Set Vref, RX VrefLevel [Byte0]: 35
8542 01:23:37.144649 [Byte1]: 35
8543 01:23:37.148515
8544 01:23:37.148623 Set Vref, RX VrefLevel [Byte0]: 36
8545 01:23:37.151782 [Byte1]: 36
8546 01:23:37.156336
8547 01:23:37.156457 Set Vref, RX VrefLevel [Byte0]: 37
8548 01:23:37.158973 [Byte1]: 37
8549 01:23:37.163179
8550 01:23:37.163284 Set Vref, RX VrefLevel [Byte0]: 38
8551 01:23:37.166601 [Byte1]: 38
8552 01:23:37.171262
8553 01:23:37.171370 Set Vref, RX VrefLevel [Byte0]: 39
8554 01:23:37.174456 [Byte1]: 39
8555 01:23:37.178896
8556 01:23:37.179002 Set Vref, RX VrefLevel [Byte0]: 40
8557 01:23:37.181960 [Byte1]: 40
8558 01:23:37.186188
8559 01:23:37.186292 Set Vref, RX VrefLevel [Byte0]: 41
8560 01:23:37.189376 [Byte1]: 41
8561 01:23:37.193546
8562 01:23:37.193702 Set Vref, RX VrefLevel [Byte0]: 42
8563 01:23:37.196984 [Byte1]: 42
8564 01:23:37.201527
8565 01:23:37.201666 Set Vref, RX VrefLevel [Byte0]: 43
8566 01:23:37.204417 [Byte1]: 43
8567 01:23:37.208707
8568 01:23:37.208840 Set Vref, RX VrefLevel [Byte0]: 44
8569 01:23:37.212129 [Byte1]: 44
8570 01:23:37.216337
8571 01:23:37.216474 Set Vref, RX VrefLevel [Byte0]: 45
8572 01:23:37.219611 [Byte1]: 45
8573 01:23:37.223750
8574 01:23:37.223902 Set Vref, RX VrefLevel [Byte0]: 46
8575 01:23:37.226939 [Byte1]: 46
8576 01:23:37.231168
8577 01:23:37.231291 Set Vref, RX VrefLevel [Byte0]: 47
8578 01:23:37.234568 [Byte1]: 47
8579 01:23:37.238539
8580 01:23:37.238654 Set Vref, RX VrefLevel [Byte0]: 48
8581 01:23:37.242116 [Byte1]: 48
8582 01:23:37.246281
8583 01:23:37.246440 Set Vref, RX VrefLevel [Byte0]: 49
8584 01:23:37.249912 [Byte1]: 49
8585 01:23:37.254015
8586 01:23:37.254141 Set Vref, RX VrefLevel [Byte0]: 50
8587 01:23:37.257434 [Byte1]: 50
8588 01:23:37.261281
8589 01:23:37.261390 Set Vref, RX VrefLevel [Byte0]: 51
8590 01:23:37.264814 [Byte1]: 51
8591 01:23:37.269216
8592 01:23:37.269325 Set Vref, RX VrefLevel [Byte0]: 52
8593 01:23:37.272060 [Byte1]: 52
8594 01:23:37.276289
8595 01:23:37.276431 Set Vref, RX VrefLevel [Byte0]: 53
8596 01:23:37.279664 [Byte1]: 53
8597 01:23:37.283713
8598 01:23:37.283820 Set Vref, RX VrefLevel [Byte0]: 54
8599 01:23:37.287268 [Byte1]: 54
8600 01:23:37.291899
8601 01:23:37.292026 Set Vref, RX VrefLevel [Byte0]: 55
8602 01:23:37.295075 [Byte1]: 55
8603 01:23:37.299407
8604 01:23:37.299545 Set Vref, RX VrefLevel [Byte0]: 56
8605 01:23:37.302483 [Byte1]: 56
8606 01:23:37.306521
8607 01:23:37.306642 Set Vref, RX VrefLevel [Byte0]: 57
8608 01:23:37.309634 [Byte1]: 57
8609 01:23:37.314049
8610 01:23:37.314188 Set Vref, RX VrefLevel [Byte0]: 58
8611 01:23:37.317330 [Byte1]: 58
8612 01:23:37.321614
8613 01:23:37.321740 Set Vref, RX VrefLevel [Byte0]: 59
8614 01:23:37.325054 [Byte1]: 59
8615 01:23:37.329116
8616 01:23:37.329248 Set Vref, RX VrefLevel [Byte0]: 60
8617 01:23:37.332739 [Byte1]: 60
8618 01:23:37.336842
8619 01:23:37.336977 Set Vref, RX VrefLevel [Byte0]: 61
8620 01:23:37.340264 [Byte1]: 61
8621 01:23:37.344466
8622 01:23:37.344560 Set Vref, RX VrefLevel [Byte0]: 62
8623 01:23:37.347795 [Byte1]: 62
8624 01:23:37.351650
8625 01:23:37.351800 Set Vref, RX VrefLevel [Byte0]: 63
8626 01:23:37.355358 [Byte1]: 63
8627 01:23:37.359612
8628 01:23:37.359737 Set Vref, RX VrefLevel [Byte0]: 64
8629 01:23:37.362978 [Byte1]: 64
8630 01:23:37.366873
8631 01:23:37.366991 Set Vref, RX VrefLevel [Byte0]: 65
8632 01:23:37.370283 [Byte1]: 65
8633 01:23:37.374177
8634 01:23:37.374278 Set Vref, RX VrefLevel [Byte0]: 66
8635 01:23:37.377472 [Byte1]: 66
8636 01:23:37.382276
8637 01:23:37.382394 Set Vref, RX VrefLevel [Byte0]: 67
8638 01:23:37.385135 [Byte1]: 67
8639 01:23:37.389316
8640 01:23:37.389421 Set Vref, RX VrefLevel [Byte0]: 68
8641 01:23:37.392635 [Byte1]: 68
8642 01:23:37.397165
8643 01:23:37.397272 Set Vref, RX VrefLevel [Byte0]: 69
8644 01:23:37.400446 [Byte1]: 69
8645 01:23:37.404478
8646 01:23:37.404583 Set Vref, RX VrefLevel [Byte0]: 70
8647 01:23:37.407962 [Byte1]: 70
8648 01:23:37.412116
8649 01:23:37.412303 Set Vref, RX VrefLevel [Byte0]: 71
8650 01:23:37.415518 [Byte1]: 71
8651 01:23:37.419460
8652 01:23:37.419644 Set Vref, RX VrefLevel [Byte0]: 72
8653 01:23:37.422650 [Byte1]: 72
8654 01:23:37.427039
8655 01:23:37.427185 Final RX Vref Byte 0 = 58 to rank0
8656 01:23:37.430412 Final RX Vref Byte 1 = 57 to rank0
8657 01:23:37.433796 Final RX Vref Byte 0 = 58 to rank1
8658 01:23:37.437252 Final RX Vref Byte 1 = 57 to rank1==
8659 01:23:37.440610 Dram Type= 6, Freq= 0, CH_1, rank 0
8660 01:23:37.447063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8661 01:23:37.447215 ==
8662 01:23:37.447327 DQS Delay:
8663 01:23:37.447419 DQS0 = 0, DQS1 = 0
8664 01:23:37.450419 DQM Delay:
8665 01:23:37.450534 DQM0 = 134, DQM1 = 131
8666 01:23:37.453762 DQ Delay:
8667 01:23:37.457021 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8668 01:23:37.461521 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8669 01:23:37.463676 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =122
8670 01:23:37.467277 DQ12 =140, DQ13 =138, DQ14 =138, DQ15 =140
8671 01:23:37.467384
8672 01:23:37.467451
8673 01:23:37.467514
8674 01:23:37.470636 [DramC_TX_OE_Calibration] TA2
8675 01:23:37.474041 Original DQ_B0 (3 6) =30, OEN = 27
8676 01:23:37.477467 Original DQ_B1 (3 6) =30, OEN = 27
8677 01:23:37.480847 24, 0x0, End_B0=24 End_B1=24
8678 01:23:37.480987 25, 0x0, End_B0=25 End_B1=25
8679 01:23:37.483998 26, 0x0, End_B0=26 End_B1=26
8680 01:23:37.486879 27, 0x0, End_B0=27 End_B1=27
8681 01:23:37.490530 28, 0x0, End_B0=28 End_B1=28
8682 01:23:37.490654 29, 0x0, End_B0=29 End_B1=29
8683 01:23:37.494023 30, 0x0, End_B0=30 End_B1=30
8684 01:23:37.496746 31, 0x4141, End_B0=30 End_B1=30
8685 01:23:37.500239 Byte0 end_step=30 best_step=27
8686 01:23:37.503682 Byte1 end_step=30 best_step=27
8687 01:23:37.506735 Byte0 TX OE(2T, 0.5T) = (3, 3)
8688 01:23:37.506858 Byte1 TX OE(2T, 0.5T) = (3, 3)
8689 01:23:37.510761
8690 01:23:37.510853
8691 01:23:37.516850 [DQSOSCAuto] RK0, (LSB)MR18= 0x1422, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8692 01:23:37.520372 CH1 RK0: MR19=303, MR18=1422
8693 01:23:37.526795 CH1_RK0: MR19=0x303, MR18=0x1422, DQSOSC=392, MR23=63, INC=24, DEC=16
8694 01:23:37.526933
8695 01:23:37.530120 ----->DramcWriteLeveling(PI) begin...
8696 01:23:37.530212 ==
8697 01:23:37.533249 Dram Type= 6, Freq= 0, CH_1, rank 1
8698 01:23:37.536521 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8699 01:23:37.536616 ==
8700 01:23:37.540032 Write leveling (Byte 0): 27 => 27
8701 01:23:37.543590 Write leveling (Byte 1): 29 => 29
8702 01:23:37.546755 DramcWriteLeveling(PI) end<-----
8703 01:23:37.546884
8704 01:23:37.546953 ==
8705 01:23:37.550239 Dram Type= 6, Freq= 0, CH_1, rank 1
8706 01:23:37.553693 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8707 01:23:37.553817 ==
8708 01:23:37.557094 [Gating] SW mode calibration
8709 01:23:37.563362 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8710 01:23:37.570015 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8711 01:23:37.573376 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8712 01:23:37.576711 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8713 01:23:37.583776 1 4 8 | B1->B0 | 2828 2323 | 1 0 | (1 1) (0 0)
8714 01:23:37.586463 1 4 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
8715 01:23:37.589747 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8716 01:23:37.596543 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8717 01:23:37.600122 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8718 01:23:37.603483 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8719 01:23:37.609867 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8720 01:23:37.613429 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8721 01:23:37.616145 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8722 01:23:37.623399 1 5 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 1)
8723 01:23:37.626528 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8724 01:23:37.629528 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8725 01:23:37.636591 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8726 01:23:37.639889 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8727 01:23:37.643297 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8728 01:23:37.649792 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8729 01:23:37.652827 1 6 8 | B1->B0 | 3a3a 2323 | 0 0 | (0 0) (0 0)
8730 01:23:37.656436 1 6 12 | B1->B0 | 4646 3a3a | 0 0 | (0 0) (0 0)
8731 01:23:37.663161 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8732 01:23:37.666629 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8733 01:23:37.669524 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8734 01:23:37.676494 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8735 01:23:37.679123 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8736 01:23:37.683114 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8737 01:23:37.689456 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8738 01:23:37.692900 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8739 01:23:37.696198 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8740 01:23:37.699666 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8741 01:23:37.706110 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8742 01:23:37.709493 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8743 01:23:37.713161 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8744 01:23:37.719537 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8745 01:23:37.722911 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8746 01:23:37.726389 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8747 01:23:37.732493 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8748 01:23:37.735922 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8749 01:23:37.739614 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8750 01:23:37.746244 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8751 01:23:37.749026 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8752 01:23:37.752552 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8753 01:23:37.759522 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8754 01:23:37.759677 Total UI for P1: 0, mck2ui 16
8755 01:23:37.766141 best dqsien dly found for B1: ( 1, 9, 6)
8756 01:23:37.769024 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8757 01:23:37.772800 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8758 01:23:37.776138 Total UI for P1: 0, mck2ui 16
8759 01:23:37.779495 best dqsien dly found for B0: ( 1, 9, 10)
8760 01:23:37.782278 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8761 01:23:37.785785 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8762 01:23:37.785947
8763 01:23:37.792455 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8764 01:23:37.795677 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8765 01:23:37.799015 [Gating] SW calibration Done
8766 01:23:37.799150 ==
8767 01:23:37.802219 Dram Type= 6, Freq= 0, CH_1, rank 1
8768 01:23:37.805534 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8769 01:23:37.805662 ==
8770 01:23:37.805770 RX Vref Scan: 0
8771 01:23:37.805865
8772 01:23:37.809157 RX Vref 0 -> 0, step: 1
8773 01:23:37.809279
8774 01:23:37.811995 RX Delay 0 -> 252, step: 8
8775 01:23:37.815462 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8776 01:23:37.819082 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8777 01:23:37.822405 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8778 01:23:37.828610 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8779 01:23:37.832209 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8780 01:23:37.835698 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8781 01:23:37.838492 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8782 01:23:37.842004 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8783 01:23:37.848586 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8784 01:23:37.852461 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8785 01:23:37.855156 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8786 01:23:37.858825 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8787 01:23:37.862380 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8788 01:23:37.868712 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8789 01:23:37.872320 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8790 01:23:37.875562 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8791 01:23:37.875742 ==
8792 01:23:37.878296 Dram Type= 6, Freq= 0, CH_1, rank 1
8793 01:23:37.881708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8794 01:23:37.884921 ==
8795 01:23:37.885099 DQS Delay:
8796 01:23:37.885203 DQS0 = 0, DQS1 = 0
8797 01:23:37.888030 DQM Delay:
8798 01:23:37.888163 DQM0 = 136, DQM1 = 133
8799 01:23:37.891645 DQ Delay:
8800 01:23:37.895362 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8801 01:23:37.898650 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8802 01:23:37.901814 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8803 01:23:37.905114 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8804 01:23:37.905223
8805 01:23:37.905315
8806 01:23:37.905396 ==
8807 01:23:37.908450 Dram Type= 6, Freq= 0, CH_1, rank 1
8808 01:23:37.911437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8809 01:23:37.914578 ==
8810 01:23:37.914709
8811 01:23:37.914807
8812 01:23:37.914898 TX Vref Scan disable
8813 01:23:37.917902 == TX Byte 0 ==
8814 01:23:37.921618 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8815 01:23:37.925124 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8816 01:23:37.927912 == TX Byte 1 ==
8817 01:23:37.931401 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8818 01:23:37.934874 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8819 01:23:37.934978 ==
8820 01:23:37.938198 Dram Type= 6, Freq= 0, CH_1, rank 1
8821 01:23:37.944425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8822 01:23:37.944551 ==
8823 01:23:37.957300
8824 01:23:37.960730 TX Vref early break, caculate TX vref
8825 01:23:37.964356 TX Vref=16, minBit 0, minWin=22, winSum=383
8826 01:23:37.967675 TX Vref=18, minBit 1, minWin=23, winSum=389
8827 01:23:37.970621 TX Vref=20, minBit 0, minWin=24, winSum=399
8828 01:23:37.973938 TX Vref=22, minBit 2, minWin=24, winSum=406
8829 01:23:37.977451 TX Vref=24, minBit 0, minWin=25, winSum=415
8830 01:23:37.983764 TX Vref=26, minBit 0, minWin=25, winSum=420
8831 01:23:37.987283 TX Vref=28, minBit 0, minWin=26, winSum=424
8832 01:23:37.990920 TX Vref=30, minBit 1, minWin=25, winSum=419
8833 01:23:37.993614 TX Vref=32, minBit 0, minWin=24, winSum=410
8834 01:23:37.996967 TX Vref=34, minBit 6, minWin=24, winSum=405
8835 01:23:38.000189 TX Vref=36, minBit 0, minWin=24, winSum=395
8836 01:23:38.006883 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
8837 01:23:38.007003
8838 01:23:38.010460 Final TX Range 0 Vref 28
8839 01:23:38.010554
8840 01:23:38.010635 ==
8841 01:23:38.013880 Dram Type= 6, Freq= 0, CH_1, rank 1
8842 01:23:38.016467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8843 01:23:38.016551 ==
8844 01:23:38.020426
8845 01:23:38.020512
8846 01:23:38.020609 TX Vref Scan disable
8847 01:23:38.026637 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8848 01:23:38.026773 == TX Byte 0 ==
8849 01:23:38.029947 u2DelayCellOfst[0]=17 cells (5 PI)
8850 01:23:38.033510 u2DelayCellOfst[1]=13 cells (4 PI)
8851 01:23:38.037063 u2DelayCellOfst[2]=0 cells (0 PI)
8852 01:23:38.039840 u2DelayCellOfst[3]=6 cells (2 PI)
8853 01:23:38.043238 u2DelayCellOfst[4]=10 cells (3 PI)
8854 01:23:38.046796 u2DelayCellOfst[5]=17 cells (5 PI)
8855 01:23:38.050225 u2DelayCellOfst[6]=17 cells (5 PI)
8856 01:23:38.053684 u2DelayCellOfst[7]=6 cells (2 PI)
8857 01:23:38.056394 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8858 01:23:38.060014 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8859 01:23:38.063372 == TX Byte 1 ==
8860 01:23:38.066464 u2DelayCellOfst[8]=0 cells (0 PI)
8861 01:23:38.069760 u2DelayCellOfst[9]=3 cells (1 PI)
8862 01:23:38.073003 u2DelayCellOfst[10]=13 cells (4 PI)
8863 01:23:38.073143 u2DelayCellOfst[11]=6 cells (2 PI)
8864 01:23:38.076518 u2DelayCellOfst[12]=17 cells (5 PI)
8865 01:23:38.080012 u2DelayCellOfst[13]=17 cells (5 PI)
8866 01:23:38.083686 u2DelayCellOfst[14]=17 cells (5 PI)
8867 01:23:38.086402 u2DelayCellOfst[15]=17 cells (5 PI)
8868 01:23:38.093253 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8869 01:23:38.096775 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8870 01:23:38.096923 DramC Write-DBI on
8871 01:23:38.097020 ==
8872 01:23:38.099568 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 01:23:38.106440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 01:23:38.106561 ==
8875 01:23:38.106635
8876 01:23:38.106695
8877 01:23:38.106757 TX Vref Scan disable
8878 01:23:38.110706 == TX Byte 0 ==
8879 01:23:38.114037 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8880 01:23:38.117177 == TX Byte 1 ==
8881 01:23:38.120402 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8882 01:23:38.123991 DramC Write-DBI off
8883 01:23:38.124100
8884 01:23:38.124170 [DATLAT]
8885 01:23:38.124232 Freq=1600, CH1 RK1
8886 01:23:38.124293
8887 01:23:38.126917 DATLAT Default: 0xf
8888 01:23:38.126989 0, 0xFFFF, sum = 0
8889 01:23:38.130591 1, 0xFFFF, sum = 0
8890 01:23:38.134033 2, 0xFFFF, sum = 0
8891 01:23:38.134157 3, 0xFFFF, sum = 0
8892 01:23:38.137138 4, 0xFFFF, sum = 0
8893 01:23:38.137249 5, 0xFFFF, sum = 0
8894 01:23:38.140321 6, 0xFFFF, sum = 0
8895 01:23:38.140408 7, 0xFFFF, sum = 0
8896 01:23:38.143788 8, 0xFFFF, sum = 0
8897 01:23:38.143872 9, 0xFFFF, sum = 0
8898 01:23:38.146781 10, 0xFFFF, sum = 0
8899 01:23:38.146859 11, 0xFFFF, sum = 0
8900 01:23:38.150347 12, 0xFFFF, sum = 0
8901 01:23:38.150446 13, 0xFFFF, sum = 0
8902 01:23:38.153804 14, 0x0, sum = 1
8903 01:23:38.153900 15, 0x0, sum = 2
8904 01:23:38.157074 16, 0x0, sum = 3
8905 01:23:38.157189 17, 0x0, sum = 4
8906 01:23:38.160442 best_step = 15
8907 01:23:38.160556
8908 01:23:38.160651 ==
8909 01:23:38.163907 Dram Type= 6, Freq= 0, CH_1, rank 1
8910 01:23:38.167231 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8911 01:23:38.167329 ==
8912 01:23:38.170134 RX Vref Scan: 0
8913 01:23:38.170245
8914 01:23:38.170351 RX Vref 0 -> 0, step: 1
8915 01:23:38.170443
8916 01:23:38.173526 RX Delay 19 -> 252, step: 4
8917 01:23:38.176802 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8918 01:23:38.183640 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8919 01:23:38.187220 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8920 01:23:38.190595 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8921 01:23:38.193463 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8922 01:23:38.197049 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8923 01:23:38.200582 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8924 01:23:38.207367 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8925 01:23:38.210110 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8926 01:23:38.213842 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8927 01:23:38.216484 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8928 01:23:38.223581 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8929 01:23:38.227066 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8930 01:23:38.230293 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8931 01:23:38.233607 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8932 01:23:38.236916 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8933 01:23:38.237042 ==
8934 01:23:38.240364 Dram Type= 6, Freq= 0, CH_1, rank 1
8935 01:23:38.246882 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8936 01:23:38.247058 ==
8937 01:23:38.247167 DQS Delay:
8938 01:23:38.250206 DQS0 = 0, DQS1 = 0
8939 01:23:38.250352 DQM Delay:
8940 01:23:38.253613 DQM0 = 134, DQM1 = 130
8941 01:23:38.253765 DQ Delay:
8942 01:23:38.256799 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8943 01:23:38.260112 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8944 01:23:38.263300 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
8945 01:23:38.267006 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8946 01:23:38.267131
8947 01:23:38.267239
8948 01:23:38.267333
8949 01:23:38.270474 [DramC_TX_OE_Calibration] TA2
8950 01:23:38.273557 Original DQ_B0 (3 6) =30, OEN = 27
8951 01:23:38.277135 Original DQ_B1 (3 6) =30, OEN = 27
8952 01:23:38.280612 24, 0x0, End_B0=24 End_B1=24
8953 01:23:38.280761 25, 0x0, End_B0=25 End_B1=25
8954 01:23:38.283477 26, 0x0, End_B0=26 End_B1=26
8955 01:23:38.286806 27, 0x0, End_B0=27 End_B1=27
8956 01:23:38.290014 28, 0x0, End_B0=28 End_B1=28
8957 01:23:38.293599 29, 0x0, End_B0=29 End_B1=29
8958 01:23:38.293742 30, 0x0, End_B0=30 End_B1=30
8959 01:23:38.297197 31, 0x4141, End_B0=30 End_B1=30
8960 01:23:38.300067 Byte0 end_step=30 best_step=27
8961 01:23:38.303499 Byte1 end_step=30 best_step=27
8962 01:23:38.306466 Byte0 TX OE(2T, 0.5T) = (3, 3)
8963 01:23:38.310006 Byte1 TX OE(2T, 0.5T) = (3, 3)
8964 01:23:38.310145
8965 01:23:38.310250
8966 01:23:38.316972 [DQSOSCAuto] RK1, (LSB)MR18= 0x2208, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
8967 01:23:38.319767 CH1 RK1: MR19=303, MR18=2208
8968 01:23:38.326882 CH1_RK1: MR19=0x303, MR18=0x2208, DQSOSC=392, MR23=63, INC=24, DEC=16
8969 01:23:38.329639 [RxdqsGatingPostProcess] freq 1600
8970 01:23:38.333046 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8971 01:23:38.336349 best DQS0 dly(2T, 0.5T) = (1, 1)
8972 01:23:38.339773 best DQS1 dly(2T, 0.5T) = (1, 1)
8973 01:23:38.343322 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8974 01:23:38.346812 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8975 01:23:38.350210 best DQS0 dly(2T, 0.5T) = (1, 1)
8976 01:23:38.353353 best DQS1 dly(2T, 0.5T) = (1, 1)
8977 01:23:38.356847 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8978 01:23:38.360132 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8979 01:23:38.363037 Pre-setting of DQS Precalculation
8980 01:23:38.366519 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8981 01:23:38.372879 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8982 01:23:38.382860 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8983 01:23:38.383002
8984 01:23:38.383071
8985 01:23:38.385913 [Calibration Summary] 3200 Mbps
8986 01:23:38.386004 CH 0, Rank 0
8987 01:23:38.389588 SW Impedance : PASS
8988 01:23:38.389713 DUTY Scan : NO K
8989 01:23:38.392807 ZQ Calibration : PASS
8990 01:23:38.395820 Jitter Meter : NO K
8991 01:23:38.395971 CBT Training : PASS
8992 01:23:38.399167 Write leveling : PASS
8993 01:23:38.399277 RX DQS gating : PASS
8994 01:23:38.403001 RX DQ/DQS(RDDQC) : PASS
8995 01:23:38.406038 TX DQ/DQS : PASS
8996 01:23:38.406150 RX DATLAT : PASS
8997 01:23:38.409070 RX DQ/DQS(Engine): PASS
8998 01:23:38.412608 TX OE : PASS
8999 01:23:38.412740 All Pass.
9000 01:23:38.412809
9001 01:23:38.412873 CH 0, Rank 1
9002 01:23:38.416083 SW Impedance : PASS
9003 01:23:38.419518 DUTY Scan : NO K
9004 01:23:38.419666 ZQ Calibration : PASS
9005 01:23:38.422270 Jitter Meter : NO K
9006 01:23:38.425762 CBT Training : PASS
9007 01:23:38.425889 Write leveling : PASS
9008 01:23:38.429267 RX DQS gating : PASS
9009 01:23:38.432671 RX DQ/DQS(RDDQC) : PASS
9010 01:23:38.432803 TX DQ/DQS : PASS
9011 01:23:38.436213 RX DATLAT : PASS
9012 01:23:38.438912 RX DQ/DQS(Engine): PASS
9013 01:23:38.439037 TX OE : PASS
9014 01:23:38.442326 All Pass.
9015 01:23:38.442423
9016 01:23:38.442491 CH 1, Rank 0
9017 01:23:38.445814 SW Impedance : PASS
9018 01:23:38.445901 DUTY Scan : NO K
9019 01:23:38.449277 ZQ Calibration : PASS
9020 01:23:38.452137 Jitter Meter : NO K
9021 01:23:38.452227 CBT Training : PASS
9022 01:23:38.455738 Write leveling : PASS
9023 01:23:38.455856 RX DQS gating : PASS
9024 01:23:38.459155 RX DQ/DQS(RDDQC) : PASS
9025 01:23:38.462466 TX DQ/DQS : PASS
9026 01:23:38.462583 RX DATLAT : PASS
9027 01:23:38.465794 RX DQ/DQS(Engine): PASS
9028 01:23:38.468753 TX OE : PASS
9029 01:23:38.468894 All Pass.
9030 01:23:38.468986
9031 01:23:38.469050 CH 1, Rank 1
9032 01:23:38.472579 SW Impedance : PASS
9033 01:23:38.475740 DUTY Scan : NO K
9034 01:23:38.475861 ZQ Calibration : PASS
9035 01:23:38.479079 Jitter Meter : NO K
9036 01:23:38.482344 CBT Training : PASS
9037 01:23:38.482439 Write leveling : PASS
9038 01:23:38.485828 RX DQS gating : PASS
9039 01:23:38.488595 RX DQ/DQS(RDDQC) : PASS
9040 01:23:38.488684 TX DQ/DQS : PASS
9041 01:23:38.492091 RX DATLAT : PASS
9042 01:23:38.495404 RX DQ/DQS(Engine): PASS
9043 01:23:38.495521 TX OE : PASS
9044 01:23:38.499051 All Pass.
9045 01:23:38.499142
9046 01:23:38.499208 DramC Write-DBI on
9047 01:23:38.502322 PER_BANK_REFRESH: Hybrid Mode
9048 01:23:38.502413 TX_TRACKING: ON
9049 01:23:38.511730 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9050 01:23:38.521804 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9051 01:23:38.528540 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9052 01:23:38.531834 [FAST_K] Save calibration result to emmc
9053 01:23:38.535401 sync common calibartion params.
9054 01:23:38.535511 sync cbt_mode0:1, 1:1
9055 01:23:38.538132 dram_init: ddr_geometry: 2
9056 01:23:38.541799 dram_init: ddr_geometry: 2
9057 01:23:38.541900 dram_init: ddr_geometry: 2
9058 01:23:38.545188 0:dram_rank_size:100000000
9059 01:23:38.548560 1:dram_rank_size:100000000
9060 01:23:38.555061 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9061 01:23:38.555191 DFS_SHUFFLE_HW_MODE: ON
9062 01:23:38.558639 dramc_set_vcore_voltage set vcore to 725000
9063 01:23:38.562038 Read voltage for 1600, 0
9064 01:23:38.562139 Vio18 = 0
9065 01:23:38.564959 Vcore = 725000
9066 01:23:38.565053 Vdram = 0
9067 01:23:38.565119 Vddq = 0
9068 01:23:38.568351 Vmddr = 0
9069 01:23:38.568474 switch to 3200 Mbps bootup
9070 01:23:38.571808 [DramcRunTimeConfig]
9071 01:23:38.571906 PHYPLL
9072 01:23:38.575223 DPM_CONTROL_AFTERK: ON
9073 01:23:38.575323 PER_BANK_REFRESH: ON
9074 01:23:38.578282 REFRESH_OVERHEAD_REDUCTION: ON
9075 01:23:38.581700 CMD_PICG_NEW_MODE: OFF
9076 01:23:38.581807 XRTWTW_NEW_MODE: ON
9077 01:23:38.585031 XRTRTR_NEW_MODE: ON
9078 01:23:38.585123 TX_TRACKING: ON
9079 01:23:38.588092 RDSEL_TRACKING: OFF
9080 01:23:38.591342 DQS Precalculation for DVFS: ON
9081 01:23:38.591442 RX_TRACKING: OFF
9082 01:23:38.594654 HW_GATING DBG: ON
9083 01:23:38.594748 ZQCS_ENABLE_LP4: ON
9084 01:23:38.598129 RX_PICG_NEW_MODE: ON
9085 01:23:38.598258 TX_PICG_NEW_MODE: ON
9086 01:23:38.601393 ENABLE_RX_DCM_DPHY: ON
9087 01:23:38.604299 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9088 01:23:38.607680 DUMMY_READ_FOR_TRACKING: OFF
9089 01:23:38.607827 !!! SPM_CONTROL_AFTERK: OFF
9090 01:23:38.611010 !!! SPM could not control APHY
9091 01:23:38.614629 IMPEDANCE_TRACKING: ON
9092 01:23:38.614745 TEMP_SENSOR: ON
9093 01:23:38.617635 HW_SAVE_FOR_SR: OFF
9094 01:23:38.621284 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9095 01:23:38.624783 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9096 01:23:38.627526 Read ODT Tracking: ON
9097 01:23:38.627628 Refresh Rate DeBounce: ON
9098 01:23:38.630921 DFS_NO_QUEUE_FLUSH: ON
9099 01:23:38.634184 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9100 01:23:38.637563 ENABLE_DFS_RUNTIME_MRW: OFF
9101 01:23:38.637707 DDR_RESERVE_NEW_MODE: ON
9102 01:23:38.641248 MR_CBT_SWITCH_FREQ: ON
9103 01:23:38.644097 =========================
9104 01:23:38.661496 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9105 01:23:38.665042 dram_init: ddr_geometry: 2
9106 01:23:38.683058 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9107 01:23:38.686489 dram_init: dram init end (result: 0)
9108 01:23:38.693259 DRAM-K: Full calibration passed in 24386 msecs
9109 01:23:38.696851 MRC: failed to locate region type 0.
9110 01:23:38.696967 DRAM rank0 size:0x100000000,
9111 01:23:38.700003 DRAM rank1 size=0x100000000
9112 01:23:38.710041 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9113 01:23:38.716584 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9114 01:23:38.723457 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9115 01:23:38.729793 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9116 01:23:38.733246 DRAM rank0 size:0x100000000,
9117 01:23:38.736267 DRAM rank1 size=0x100000000
9118 01:23:38.736357 CBMEM:
9119 01:23:38.739706 IMD: root @ 0xfffff000 254 entries.
9120 01:23:38.743412 IMD: root @ 0xffffec00 62 entries.
9121 01:23:38.746172 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9122 01:23:38.749567 WARNING: RO_VPD is uninitialized or empty.
9123 01:23:38.756373 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9124 01:23:38.762989 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9125 01:23:38.776041 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9126 01:23:38.787826 BS: romstage times (exec / console): total (unknown) / 23931 ms
9127 01:23:38.787967
9128 01:23:38.788034
9129 01:23:38.797321 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9130 01:23:38.800756 ARM64: Exception handlers installed.
9131 01:23:38.803616 ARM64: Testing exception
9132 01:23:38.807028 ARM64: Done test exception
9133 01:23:38.807130 Enumerating buses...
9134 01:23:38.810376 Show all devs... Before device enumeration.
9135 01:23:38.813597 Root Device: enabled 1
9136 01:23:38.817060 CPU_CLUSTER: 0: enabled 1
9137 01:23:38.817193 CPU: 00: enabled 1
9138 01:23:38.820524 Compare with tree...
9139 01:23:38.820638 Root Device: enabled 1
9140 01:23:38.823539 CPU_CLUSTER: 0: enabled 1
9141 01:23:38.827187 CPU: 00: enabled 1
9142 01:23:38.827319 Root Device scanning...
9143 01:23:38.830273 scan_static_bus for Root Device
9144 01:23:38.833371 CPU_CLUSTER: 0 enabled
9145 01:23:38.837258 scan_static_bus for Root Device done
9146 01:23:38.839935 scan_bus: bus Root Device finished in 8 msecs
9147 01:23:38.840088 done
9148 01:23:38.847077 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9149 01:23:38.850596 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9150 01:23:38.857144 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9151 01:23:38.860067 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9152 01:23:38.863537 Allocating resources...
9153 01:23:38.866935 Reading resources...
9154 01:23:38.870186 Root Device read_resources bus 0 link: 0
9155 01:23:38.870323 DRAM rank0 size:0x100000000,
9156 01:23:38.873363 DRAM rank1 size=0x100000000
9157 01:23:38.876644 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9158 01:23:38.880347 CPU: 00 missing read_resources
9159 01:23:38.886994 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9160 01:23:38.890166 Root Device read_resources bus 0 link: 0 done
9161 01:23:38.890331 Done reading resources.
9162 01:23:38.897020 Show resources in subtree (Root Device)...After reading.
9163 01:23:38.900313 Root Device child on link 0 CPU_CLUSTER: 0
9164 01:23:38.903751 CPU_CLUSTER: 0 child on link 0 CPU: 00
9165 01:23:38.913741 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9166 01:23:38.913917 CPU: 00
9167 01:23:38.916544 Root Device assign_resources, bus 0 link: 0
9168 01:23:38.919920 CPU_CLUSTER: 0 missing set_resources
9169 01:23:38.926395 Root Device assign_resources, bus 0 link: 0 done
9170 01:23:38.926560 Done setting resources.
9171 01:23:38.933345 Show resources in subtree (Root Device)...After assigning values.
9172 01:23:38.936720 Root Device child on link 0 CPU_CLUSTER: 0
9173 01:23:38.939632 CPU_CLUSTER: 0 child on link 0 CPU: 00
9174 01:23:38.949737 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9175 01:23:38.949875 CPU: 00
9176 01:23:38.953275 Done allocating resources.
9177 01:23:38.959515 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9178 01:23:38.959651 Enabling resources...
9179 01:23:38.959725 done.
9180 01:23:38.966581 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9181 01:23:38.966710 Initializing devices...
9182 01:23:38.969493 Root Device init
9183 01:23:38.969581 init hardware done!
9184 01:23:38.973054 0x00000018: ctrlr->caps
9185 01:23:38.976624 52.000 MHz: ctrlr->f_max
9186 01:23:38.976733 0.400 MHz: ctrlr->f_min
9187 01:23:38.979484 0x40ff8080: ctrlr->voltages
9188 01:23:38.982815 sclk: 390625
9189 01:23:38.982919 Bus Width = 1
9190 01:23:38.983003 sclk: 390625
9191 01:23:38.986176 Bus Width = 1
9192 01:23:38.986296 Early init status = 3
9193 01:23:38.992759 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9194 01:23:38.996148 in-header: 03 fc 00 00 01 00 00 00
9195 01:23:38.996272 in-data: 00
9196 01:23:39.002635 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9197 01:23:39.005852 in-header: 03 fd 00 00 00 00 00 00
9198 01:23:39.009868 in-data:
9199 01:23:39.012505 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9200 01:23:39.016688 in-header: 03 fc 00 00 01 00 00 00
9201 01:23:39.019501 in-data: 00
9202 01:23:39.023088 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9203 01:23:39.027472 in-header: 03 fd 00 00 00 00 00 00
9204 01:23:39.030951 in-data:
9205 01:23:39.034545 [SSUSB] Setting up USB HOST controller...
9206 01:23:39.038052 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9207 01:23:39.040809 [SSUSB] phy power-on done.
9208 01:23:39.044433 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9209 01:23:39.050823 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9210 01:23:39.054061 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9211 01:23:39.060907 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9212 01:23:39.067580 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9213 01:23:39.073977 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9214 01:23:39.080886 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9215 01:23:39.087512 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9216 01:23:39.090976 SPM: binary array size = 0x9dc
9217 01:23:39.093755 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9218 01:23:39.100321 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9219 01:23:39.107329 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9220 01:23:39.114158 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9221 01:23:39.117306 configure_display: Starting display init
9222 01:23:39.150855 anx7625_power_on_init: Init interface.
9223 01:23:39.154268 anx7625_disable_pd_protocol: Disabled PD feature.
9224 01:23:39.157137 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9225 01:23:39.185543 anx7625_start_dp_work: Secure OCM version=00
9226 01:23:39.188804 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9227 01:23:39.203634 sp_tx_get_edid_block: EDID Block = 1
9228 01:23:39.305794 Extracted contents:
9229 01:23:39.309291 header: 00 ff ff ff ff ff ff 00
9230 01:23:39.312764 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9231 01:23:39.316002 version: 01 04
9232 01:23:39.319211 basic params: 95 1f 11 78 0a
9233 01:23:39.322378 chroma info: 76 90 94 55 54 90 27 21 50 54
9234 01:23:39.325574 established: 00 00 00
9235 01:23:39.332606 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9236 01:23:39.336096 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9237 01:23:39.342458 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9238 01:23:39.348690 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9239 01:23:39.355707 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9240 01:23:39.359248 extensions: 00
9241 01:23:39.359350 checksum: fb
9242 01:23:39.359418
9243 01:23:39.361916 Manufacturer: IVO Model 57d Serial Number 0
9244 01:23:39.365250 Made week 0 of 2020
9245 01:23:39.365340 EDID version: 1.4
9246 01:23:39.368577 Digital display
9247 01:23:39.372282 6 bits per primary color channel
9248 01:23:39.372383 DisplayPort interface
9249 01:23:39.375153 Maximum image size: 31 cm x 17 cm
9250 01:23:39.378713 Gamma: 220%
9251 01:23:39.378809 Check DPMS levels
9252 01:23:39.382170 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9253 01:23:39.388713 First detailed timing is preferred timing
9254 01:23:39.388831 Established timings supported:
9255 01:23:39.391783 Standard timings supported:
9256 01:23:39.395495 Detailed timings
9257 01:23:39.398373 Hex of detail: 383680a07038204018303c0035ae10000019
9258 01:23:39.405449 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9259 01:23:39.408205 0780 0798 07c8 0820 hborder 0
9260 01:23:39.411852 0438 043b 0447 0458 vborder 0
9261 01:23:39.415466 -hsync -vsync
9262 01:23:39.415580 Did detailed timing
9263 01:23:39.421736 Hex of detail: 000000000000000000000000000000000000
9264 01:23:39.425012 Manufacturer-specified data, tag 0
9265 01:23:39.428469 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9266 01:23:39.431830 ASCII string: InfoVision
9267 01:23:39.435239 Hex of detail: 000000fe00523134304e574635205248200a
9268 01:23:39.438481 ASCII string: R140NWF5 RH
9269 01:23:39.438597 Checksum
9270 01:23:39.441688 Checksum: 0xfb (valid)
9271 01:23:39.445026 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9272 01:23:39.448433 DSI data_rate: 832800000 bps
9273 01:23:39.454812 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9274 01:23:39.458330 anx7625_parse_edid: pixelclock(138800).
9275 01:23:39.461656 hactive(1920), hsync(48), hfp(24), hbp(88)
9276 01:23:39.465097 vactive(1080), vsync(12), vfp(3), vbp(17)
9277 01:23:39.468040 anx7625_dsi_config: config dsi.
9278 01:23:39.475081 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9279 01:23:39.488255 anx7625_dsi_config: success to config DSI
9280 01:23:39.491042 anx7625_dp_start: MIPI phy setup OK.
9281 01:23:39.494328 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9282 01:23:39.497749 mtk_ddp_mode_set invalid vrefresh 60
9283 01:23:39.500903 main_disp_path_setup
9284 01:23:39.501001 ovl_layer_smi_id_en
9285 01:23:39.504676 ovl_layer_smi_id_en
9286 01:23:39.504768 ccorr_config
9287 01:23:39.504836 aal_config
9288 01:23:39.507799 gamma_config
9289 01:23:39.507888 postmask_config
9290 01:23:39.510864 dither_config
9291 01:23:39.514131 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9292 01:23:39.521103 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9293 01:23:39.524364 Root Device init finished in 551 msecs
9294 01:23:39.527756 CPU_CLUSTER: 0 init
9295 01:23:39.534127 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9296 01:23:39.541082 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9297 01:23:39.541237 APU_MBOX 0x190000b0 = 0x10001
9298 01:23:39.543961 APU_MBOX 0x190001b0 = 0x10001
9299 01:23:39.547164 APU_MBOX 0x190005b0 = 0x10001
9300 01:23:39.550394 APU_MBOX 0x190006b0 = 0x10001
9301 01:23:39.557092 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9302 01:23:39.567209 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9303 01:23:39.579205 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9304 01:23:39.586111 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9305 01:23:39.597963 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9306 01:23:39.606561 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9307 01:23:39.609944 CPU_CLUSTER: 0 init finished in 81 msecs
9308 01:23:39.613449 Devices initialized
9309 01:23:39.616825 Show all devs... After init.
9310 01:23:39.616943 Root Device: enabled 1
9311 01:23:39.620021 CPU_CLUSTER: 0: enabled 1
9312 01:23:39.623544 CPU: 00: enabled 1
9313 01:23:39.626929 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9314 01:23:39.630364 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9315 01:23:39.633381 ELOG: NV offset 0x57f000 size 0x1000
9316 01:23:39.639935 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9317 01:23:39.646506 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9318 01:23:39.649749 ELOG: Event(17) added with size 13 at 2024-04-23 01:19:28 UTC
9319 01:23:39.653183 out: cmd=0x121: 03 db 21 01 00 00 00 00
9320 01:23:39.657253 in-header: 03 25 00 00 2c 00 00 00
9321 01:23:39.670355 in-data: 3a 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9322 01:23:39.677386 ELOG: Event(A1) added with size 10 at 2024-04-23 01:19:28 UTC
9323 01:23:39.683590 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9324 01:23:39.690629 ELOG: Event(A0) added with size 9 at 2024-04-23 01:19:28 UTC
9325 01:23:39.693650 elog_add_boot_reason: Logged dev mode boot
9326 01:23:39.697261 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9327 01:23:39.700670 Finalize devices...
9328 01:23:39.700804 Devices finalized
9329 01:23:39.706927 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9330 01:23:39.710470 Writing coreboot table at 0xffe64000
9331 01:23:39.714082 0. 000000000010a000-0000000000113fff: RAMSTAGE
9332 01:23:39.716718 1. 0000000040000000-00000000400fffff: RAM
9333 01:23:39.720433 2. 0000000040100000-000000004032afff: RAMSTAGE
9334 01:23:39.726789 3. 000000004032b000-00000000545fffff: RAM
9335 01:23:39.730103 4. 0000000054600000-000000005465ffff: BL31
9336 01:23:39.733613 5. 0000000054660000-00000000ffe63fff: RAM
9337 01:23:39.737154 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9338 01:23:39.743306 7. 0000000100000000-000000023fffffff: RAM
9339 01:23:39.743460 Passing 5 GPIOs to payload:
9340 01:23:39.750461 NAME | PORT | POLARITY | VALUE
9341 01:23:39.753071 EC in RW | 0x000000aa | low | undefined
9342 01:23:39.759878 EC interrupt | 0x00000005 | low | undefined
9343 01:23:39.763134 TPM interrupt | 0x000000ab | high | undefined
9344 01:23:39.766353 SD card detect | 0x00000011 | high | undefined
9345 01:23:39.773042 speaker enable | 0x00000093 | high | undefined
9346 01:23:39.776400 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9347 01:23:39.779582 in-header: 03 f9 00 00 02 00 00 00
9348 01:23:39.779711 in-data: 02 00
9349 01:23:39.783194 ADC[4]: Raw value=904357 ID=7
9350 01:23:39.786290 ADC[3]: Raw value=213441 ID=1
9351 01:23:39.786400 RAM Code: 0x71
9352 01:23:39.789449 ADC[6]: Raw value=75701 ID=0
9353 01:23:39.793055 ADC[5]: Raw value=213072 ID=1
9354 01:23:39.793190 SKU Code: 0x1
9355 01:23:39.799795 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum cac8
9356 01:23:39.802843 coreboot table: 964 bytes.
9357 01:23:39.806256 IMD ROOT 0. 0xfffff000 0x00001000
9358 01:23:39.809983 IMD SMALL 1. 0xffffe000 0x00001000
9359 01:23:39.812797 RO MCACHE 2. 0xffffc000 0x00001104
9360 01:23:39.816297 CONSOLE 3. 0xfff7c000 0x00080000
9361 01:23:39.819030 FMAP 4. 0xfff7b000 0x00000452
9362 01:23:39.822621 TIME STAMP 5. 0xfff7a000 0x00000910
9363 01:23:39.826003 VBOOT WORK 6. 0xfff66000 0x00014000
9364 01:23:39.829561 RAMOOPS 7. 0xffe66000 0x00100000
9365 01:23:39.832285 COREBOOT 8. 0xffe64000 0x00002000
9366 01:23:39.832431 IMD small region:
9367 01:23:39.835784 IMD ROOT 0. 0xffffec00 0x00000400
9368 01:23:39.839245 VPD 1. 0xffffeb80 0x0000006c
9369 01:23:39.842666 MMC STATUS 2. 0xffffeb60 0x00000004
9370 01:23:39.849564 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9371 01:23:39.852903 Probing TPM: done!
9372 01:23:39.856494 Connected to device vid:did:rid of 1ae0:0028:00
9373 01:23:39.866263 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9374 01:23:39.869599 Initialized TPM device CR50 revision 0
9375 01:23:39.873324 Checking cr50 for pending updates
9376 01:23:39.876556 Reading cr50 TPM mode
9377 01:23:39.884976 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9378 01:23:39.891910 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9379 01:23:39.931647 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9380 01:23:39.935136 Checking segment from ROM address 0x40100000
9381 01:23:39.938676 Checking segment from ROM address 0x4010001c
9382 01:23:39.945571 Loading segment from ROM address 0x40100000
9383 01:23:39.945730 code (compression=0)
9384 01:23:39.955321 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9385 01:23:39.961697 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9386 01:23:39.961854 it's not compressed!
9387 01:23:39.968877 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9388 01:23:39.971607 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9389 01:23:39.992174 Loading segment from ROM address 0x4010001c
9390 01:23:39.992312 Entry Point 0x80000000
9391 01:23:39.995795 Loaded segments
9392 01:23:39.999362 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9393 01:23:40.005552 Jumping to boot code at 0x80000000(0xffe64000)
9394 01:23:40.012088 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9395 01:23:40.019114 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9396 01:23:40.026677 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9397 01:23:40.029877 Checking segment from ROM address 0x40100000
9398 01:23:40.033193 Checking segment from ROM address 0x4010001c
9399 01:23:40.039911 Loading segment from ROM address 0x40100000
9400 01:23:40.040040 code (compression=1)
9401 01:23:40.046511 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9402 01:23:40.056664 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9403 01:23:40.056873 using LZMA
9404 01:23:40.064835 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9405 01:23:40.071791 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9406 01:23:40.075245 Loading segment from ROM address 0x4010001c
9407 01:23:40.075370 Entry Point 0x54601000
9408 01:23:40.078617 Loaded segments
9409 01:23:40.081462 NOTICE: MT8192 bl31_setup
9410 01:23:40.088568 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9411 01:23:40.091869 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9412 01:23:40.095441 WARNING: region 0:
9413 01:23:40.098622 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9414 01:23:40.098728 WARNING: region 1:
9415 01:23:40.105887 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9416 01:23:40.106039 WARNING: region 2:
9417 01:23:40.112225 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9418 01:23:40.115855 WARNING: region 3:
9419 01:23:40.118596 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9420 01:23:40.122156 WARNING: region 4:
9421 01:23:40.125697 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9422 01:23:40.129272 WARNING: region 5:
9423 01:23:40.131956 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9424 01:23:40.135492 WARNING: region 6:
9425 01:23:40.138884 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9426 01:23:40.138990 WARNING: region 7:
9427 01:23:40.145928 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9428 01:23:40.152372 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9429 01:23:40.155767 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9430 01:23:40.159109 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9431 01:23:40.165286 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9432 01:23:40.168988 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9433 01:23:40.172428 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9434 01:23:40.179182 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9435 01:23:40.182434 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9436 01:23:40.185378 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9437 01:23:40.192184 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9438 01:23:40.195374 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9439 01:23:40.199124 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9440 01:23:40.205709 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9441 01:23:40.209049 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9442 01:23:40.216021 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9443 01:23:40.218873 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9444 01:23:40.222438 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9445 01:23:40.228930 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9446 01:23:40.232502 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9447 01:23:40.235397 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9448 01:23:40.242081 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9449 01:23:40.245570 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9450 01:23:40.251866 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9451 01:23:40.255485 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9452 01:23:40.262163 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9453 01:23:40.265547 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9454 01:23:40.268871 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9455 01:23:40.275637 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9456 01:23:40.279219 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9457 01:23:40.282119 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9458 01:23:40.289240 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9459 01:23:40.292023 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9460 01:23:40.295590 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9461 01:23:40.302069 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9462 01:23:40.305603 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9463 01:23:40.309066 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9464 01:23:40.312232 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9465 01:23:40.318949 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9466 01:23:40.322385 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9467 01:23:40.325413 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9468 01:23:40.328795 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9469 01:23:40.335543 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9470 01:23:40.338706 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9471 01:23:40.342220 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9472 01:23:40.345661 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9473 01:23:40.352257 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9474 01:23:40.355647 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9475 01:23:40.359124 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9476 01:23:40.366032 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9477 01:23:40.369412 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9478 01:23:40.372236 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9479 01:23:40.379658 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9480 01:23:40.382436 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9481 01:23:40.389450 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9482 01:23:40.393027 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9483 01:23:40.395718 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9484 01:23:40.402890 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9485 01:23:40.405811 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9486 01:23:40.412867 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9487 01:23:40.415667 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9488 01:23:40.422783 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9489 01:23:40.426295 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9490 01:23:40.432826 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9491 01:23:40.436175 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9492 01:23:40.439738 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9493 01:23:40.446178 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9494 01:23:40.449429 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9495 01:23:40.455735 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9496 01:23:40.459334 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9497 01:23:40.466240 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9498 01:23:40.469344 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9499 01:23:40.472863 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9500 01:23:40.479085 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9501 01:23:40.482271 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9502 01:23:40.489537 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9503 01:23:40.492721 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9504 01:23:40.499731 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9505 01:23:40.502609 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9506 01:23:40.506233 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9507 01:23:40.512498 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9508 01:23:40.516058 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9509 01:23:40.522523 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9510 01:23:40.525987 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9511 01:23:40.532996 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9512 01:23:40.536409 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9513 01:23:40.539292 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9514 01:23:40.546207 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9515 01:23:40.549123 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9516 01:23:40.556177 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9517 01:23:40.559625 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9518 01:23:40.566029 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9519 01:23:40.569580 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9520 01:23:40.572960 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9521 01:23:40.579379 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9522 01:23:40.583048 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9523 01:23:40.589183 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9524 01:23:40.592648 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9525 01:23:40.595938 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9526 01:23:40.602608 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9527 01:23:40.605903 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9528 01:23:40.609066 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9529 01:23:40.612639 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9530 01:23:40.619423 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9531 01:23:40.622722 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9532 01:23:40.629171 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9533 01:23:40.632656 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9534 01:23:40.641442 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9535 01:23:40.642831 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9536 01:23:40.646152 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9537 01:23:40.652506 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9538 01:23:40.656032 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9539 01:23:40.659404 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9540 01:23:40.666443 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9541 01:23:40.669141 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9542 01:23:40.676258 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9543 01:23:40.679790 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9544 01:23:40.683148 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9545 01:23:40.686217 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9546 01:23:40.692666 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9547 01:23:40.696099 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9548 01:23:40.699648 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9549 01:23:40.703085 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9550 01:23:40.709360 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9551 01:23:40.712869 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9552 01:23:40.716351 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9553 01:23:40.722673 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9554 01:23:40.726050 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9555 01:23:40.732949 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9556 01:23:40.736245 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9557 01:23:40.739726 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9558 01:23:40.745988 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9559 01:23:40.749558 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9560 01:23:40.756074 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9561 01:23:40.759158 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9562 01:23:40.762357 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9563 01:23:40.769036 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9564 01:23:40.772613 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9565 01:23:40.776042 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9566 01:23:40.782554 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9567 01:23:40.786077 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9568 01:23:40.792785 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9569 01:23:40.795982 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9570 01:23:40.799422 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9571 01:23:40.806379 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9572 01:23:40.809095 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9573 01:23:40.816292 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9574 01:23:40.819174 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9575 01:23:40.822927 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9576 01:23:40.829341 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9577 01:23:40.832727 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9578 01:23:40.836285 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9579 01:23:40.842659 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9580 01:23:40.846115 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9581 01:23:40.852538 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9582 01:23:40.856130 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9583 01:23:40.859636 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9584 01:23:40.865889 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9585 01:23:40.869213 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9586 01:23:40.872664 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9587 01:23:40.879354 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9588 01:23:40.882360 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9589 01:23:40.889132 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9590 01:23:40.892743 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9591 01:23:40.899292 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9592 01:23:40.902549 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9593 01:23:40.905647 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9594 01:23:40.912670 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9595 01:23:40.915750 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9596 01:23:40.919079 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9597 01:23:40.925956 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9598 01:23:40.929496 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9599 01:23:40.935854 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9600 01:23:40.939301 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9601 01:23:40.942163 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9602 01:23:40.949275 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9603 01:23:40.952801 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9604 01:23:40.959167 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9605 01:23:40.962574 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9606 01:23:40.965457 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9607 01:23:40.972332 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9608 01:23:40.975628 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9609 01:23:40.982563 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9610 01:23:40.985462 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9611 01:23:40.988984 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9612 01:23:40.995285 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9613 01:23:40.998709 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9614 01:23:41.002374 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9615 01:23:41.008534 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9616 01:23:41.011897 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9617 01:23:41.019003 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9618 01:23:41.022228 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9619 01:23:41.028991 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9620 01:23:41.032004 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9621 01:23:41.035345 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9622 01:23:41.041839 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9623 01:23:41.044982 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9624 01:23:41.051645 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9625 01:23:41.055207 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9626 01:23:41.058867 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9627 01:23:41.065236 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9628 01:23:41.068895 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9629 01:23:41.075254 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9630 01:23:41.078614 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9631 01:23:41.085003 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9632 01:23:41.088519 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9633 01:23:41.092177 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9634 01:23:41.098393 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9635 01:23:41.102042 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9636 01:23:41.108127 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9637 01:23:41.111759 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9638 01:23:41.115399 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9639 01:23:41.121765 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9640 01:23:41.125217 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9641 01:23:41.131447 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9642 01:23:41.135150 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9643 01:23:41.141379 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9644 01:23:41.144904 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9645 01:23:41.148364 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9646 01:23:41.155171 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9647 01:23:41.157997 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9648 01:23:41.164626 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9649 01:23:41.167815 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9650 01:23:41.171620 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9651 01:23:41.177960 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9652 01:23:41.181506 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9653 01:23:41.188299 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9654 01:23:41.191005 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9655 01:23:41.198074 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9656 01:23:41.200957 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9657 01:23:41.204600 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9658 01:23:41.207926 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9659 01:23:41.214279 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9660 01:23:41.217888 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9661 01:23:41.221509 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9662 01:23:41.227973 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9663 01:23:41.230778 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9664 01:23:41.234260 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9665 01:23:41.241410 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9666 01:23:41.244267 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9667 01:23:41.247984 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9668 01:23:41.254407 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9669 01:23:41.257741 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9670 01:23:41.263940 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9671 01:23:41.267493 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9672 01:23:41.270456 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9673 01:23:41.277450 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9674 01:23:41.281027 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9675 01:23:41.283836 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9676 01:23:41.290998 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9677 01:23:41.293941 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9678 01:23:41.297124 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9679 01:23:41.303839 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9680 01:23:41.307359 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9681 01:23:41.310399 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9682 01:23:41.316893 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9683 01:23:41.320444 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9684 01:23:41.327465 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9685 01:23:41.330215 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9686 01:23:41.333866 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9687 01:23:41.340245 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9688 01:23:41.343752 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9689 01:23:41.347376 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9690 01:23:41.353814 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9691 01:23:41.356762 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9692 01:23:41.363732 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9693 01:23:41.367087 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9694 01:23:41.370558 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9695 01:23:41.376980 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9696 01:23:41.379880 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9697 01:23:41.383458 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9698 01:23:41.387067 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9699 01:23:41.393894 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9700 01:23:41.396611 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9701 01:23:41.400185 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9702 01:23:41.403782 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9703 01:23:41.407244 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9704 01:23:41.413418 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9705 01:23:41.416945 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9706 01:23:41.420658 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9707 01:23:41.423327 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9708 01:23:41.429850 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9709 01:23:41.433230 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9710 01:23:41.440343 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9711 01:23:41.443285 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9712 01:23:41.446616 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9713 01:23:41.453346 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9714 01:23:41.456872 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9715 01:23:41.463485 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9716 01:23:41.466235 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9717 01:23:41.469718 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9718 01:23:41.476644 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9719 01:23:41.480315 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9720 01:23:41.486547 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9721 01:23:41.490098 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9722 01:23:41.496476 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9723 01:23:41.499402 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9724 01:23:41.502918 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9725 01:23:41.509067 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9726 01:23:41.512660 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9727 01:23:41.518951 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9728 01:23:41.522444 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9729 01:23:41.529174 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9730 01:23:41.532877 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9731 01:23:41.535721 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9732 01:23:41.542062 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9733 01:23:41.545533 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9734 01:23:41.552374 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9735 01:23:41.555612 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9736 01:23:41.558657 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9737 01:23:41.565556 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9738 01:23:41.568767 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9739 01:23:41.575550 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9740 01:23:41.579101 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9741 01:23:41.581793 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9742 01:23:41.588630 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9743 01:23:41.592028 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9744 01:23:41.598595 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9745 01:23:41.602060 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9746 01:23:41.608636 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9747 01:23:41.612214 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9748 01:23:41.615069 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9749 01:23:41.621974 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9750 01:23:41.624837 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9751 01:23:41.631972 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9752 01:23:41.634676 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9753 01:23:41.638420 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9754 01:23:41.644858 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9755 01:23:41.648339 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9756 01:23:41.654758 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9757 01:23:41.658207 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9758 01:23:41.661876 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9759 01:23:41.667978 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9760 01:23:41.671473 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9761 01:23:41.678061 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9762 01:23:41.681396 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9763 01:23:41.688051 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9764 01:23:41.691316 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9765 01:23:41.694671 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9766 01:23:41.701830 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9767 01:23:41.705306 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9768 01:23:41.708609 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9769 01:23:41.714741 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9770 01:23:41.718223 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9771 01:23:41.725172 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9772 01:23:41.728005 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9773 01:23:41.731609 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9774 01:23:41.738187 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9775 01:23:41.741545 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9776 01:23:41.748118 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9777 01:23:41.751678 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9778 01:23:41.758065 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9779 01:23:41.760936 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9780 01:23:41.767647 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9781 01:23:41.771263 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9782 01:23:41.774684 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9783 01:23:41.781384 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9784 01:23:41.784126 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9785 01:23:41.791052 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9786 01:23:41.794403 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9787 01:23:41.800986 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9788 01:23:41.804703 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9789 01:23:41.807320 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9790 01:23:41.814152 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9791 01:23:41.817553 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9792 01:23:41.823933 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9793 01:23:41.827354 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9794 01:23:41.834208 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9795 01:23:41.837328 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9796 01:23:41.840713 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9797 01:23:41.847272 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9798 01:23:41.850682 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9799 01:23:41.857097 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9800 01:23:41.860610 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9801 01:23:41.867023 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9802 01:23:41.870618 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9803 01:23:41.874127 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9804 01:23:41.880499 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9805 01:23:41.884003 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9806 01:23:41.890379 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9807 01:23:41.893963 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9808 01:23:41.900375 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9809 01:23:41.903670 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9810 01:23:41.906873 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9811 01:23:41.913843 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9812 01:23:41.917400 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9813 01:23:41.923841 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9814 01:23:41.926768 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9815 01:23:41.933779 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9816 01:23:41.937153 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9817 01:23:41.943499 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9818 01:23:41.946708 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9819 01:23:41.950347 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9820 01:23:41.956960 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9821 01:23:41.960167 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9822 01:23:41.966838 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9823 01:23:41.970495 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9824 01:23:41.976838 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9825 01:23:41.980376 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9826 01:23:41.983937 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9827 01:23:41.990285 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9828 01:23:41.993285 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9829 01:23:42.000481 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9830 01:23:42.003456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9831 01:23:42.006978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9832 01:23:42.013308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9833 01:23:42.016538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9834 01:23:42.023557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9835 01:23:42.026329 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9836 01:23:42.033581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9837 01:23:42.036442 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9838 01:23:42.043449 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9839 01:23:42.046253 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9840 01:23:42.053349 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9841 01:23:42.056308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9842 01:23:42.062917 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9843 01:23:42.066013 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9844 01:23:42.072990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9845 01:23:42.076004 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9846 01:23:42.082760 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9847 01:23:42.086275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9848 01:23:42.092641 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9849 01:23:42.095955 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9850 01:23:42.102674 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9851 01:23:42.106155 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9852 01:23:42.112596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9853 01:23:42.116177 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9854 01:23:42.122501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9855 01:23:42.125908 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9856 01:23:42.132645 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9857 01:23:42.136267 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9858 01:23:42.142689 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9859 01:23:42.145599 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9860 01:23:42.152484 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9861 01:23:42.155335 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9862 01:23:42.159190 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9863 01:23:42.162012 INFO: [APUAPC] vio 0
9864 01:23:42.169051 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9865 01:23:42.171799 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9866 01:23:42.175510 INFO: [APUAPC] D0_APC_0: 0x400510
9867 01:23:42.179052 INFO: [APUAPC] D0_APC_1: 0x0
9868 01:23:42.182201 INFO: [APUAPC] D0_APC_2: 0x1540
9869 01:23:42.185762 INFO: [APUAPC] D0_APC_3: 0x0
9870 01:23:42.188414 INFO: [APUAPC] D1_APC_0: 0xffffffff
9871 01:23:42.191904 INFO: [APUAPC] D1_APC_1: 0xffffffff
9872 01:23:42.195094 INFO: [APUAPC] D1_APC_2: 0x3fffff
9873 01:23:42.198568 INFO: [APUAPC] D1_APC_3: 0x0
9874 01:23:42.201877 INFO: [APUAPC] D2_APC_0: 0xffffffff
9875 01:23:42.205491 INFO: [APUAPC] D2_APC_1: 0xffffffff
9876 01:23:42.208848 INFO: [APUAPC] D2_APC_2: 0x3fffff
9877 01:23:42.211611 INFO: [APUAPC] D2_APC_3: 0x0
9878 01:23:42.215470 INFO: [APUAPC] D3_APC_0: 0xffffffff
9879 01:23:42.218200 INFO: [APUAPC] D3_APC_1: 0xffffffff
9880 01:23:42.221787 INFO: [APUAPC] D3_APC_2: 0x3fffff
9881 01:23:42.221898 INFO: [APUAPC] D3_APC_3: 0x0
9882 01:23:42.228306 INFO: [APUAPC] D4_APC_0: 0xffffffff
9883 01:23:42.231896 INFO: [APUAPC] D4_APC_1: 0xffffffff
9884 01:23:42.234630 INFO: [APUAPC] D4_APC_2: 0x3fffff
9885 01:23:42.234742 INFO: [APUAPC] D4_APC_3: 0x0
9886 01:23:42.238121 INFO: [APUAPC] D5_APC_0: 0xffffffff
9887 01:23:42.244778 INFO: [APUAPC] D5_APC_1: 0xffffffff
9888 01:23:42.244895 INFO: [APUAPC] D5_APC_2: 0x3fffff
9889 01:23:42.248411 INFO: [APUAPC] D5_APC_3: 0x0
9890 01:23:42.251246 INFO: [APUAPC] D6_APC_0: 0xffffffff
9891 01:23:42.254753 INFO: [APUAPC] D6_APC_1: 0xffffffff
9892 01:23:42.258229 INFO: [APUAPC] D6_APC_2: 0x3fffff
9893 01:23:42.261146 INFO: [APUAPC] D6_APC_3: 0x0
9894 01:23:42.264579 INFO: [APUAPC] D7_APC_0: 0xffffffff
9895 01:23:42.268200 INFO: [APUAPC] D7_APC_1: 0xffffffff
9896 01:23:42.271056 INFO: [APUAPC] D7_APC_2: 0x3fffff
9897 01:23:42.274618 INFO: [APUAPC] D7_APC_3: 0x0
9898 01:23:42.278112 INFO: [APUAPC] D8_APC_0: 0xffffffff
9899 01:23:42.281580 INFO: [APUAPC] D8_APC_1: 0xffffffff
9900 01:23:42.284291 INFO: [APUAPC] D8_APC_2: 0x3fffff
9901 01:23:42.287929 INFO: [APUAPC] D8_APC_3: 0x0
9902 01:23:42.291488 INFO: [APUAPC] D9_APC_0: 0xffffffff
9903 01:23:42.294348 INFO: [APUAPC] D9_APC_1: 0xffffffff
9904 01:23:42.297840 INFO: [APUAPC] D9_APC_2: 0x3fffff
9905 01:23:42.300643 INFO: [APUAPC] D9_APC_3: 0x0
9906 01:23:42.304558 INFO: [APUAPC] D10_APC_0: 0xffffffff
9907 01:23:42.307544 INFO: [APUAPC] D10_APC_1: 0xffffffff
9908 01:23:42.311219 INFO: [APUAPC] D10_APC_2: 0x3fffff
9909 01:23:42.314037 INFO: [APUAPC] D10_APC_3: 0x0
9910 01:23:42.317529 INFO: [APUAPC] D11_APC_0: 0xffffffff
9911 01:23:42.321070 INFO: [APUAPC] D11_APC_1: 0xffffffff
9912 01:23:42.324457 INFO: [APUAPC] D11_APC_2: 0x3fffff
9913 01:23:42.327080 INFO: [APUAPC] D11_APC_3: 0x0
9914 01:23:42.331069 INFO: [APUAPC] D12_APC_0: 0xffffffff
9915 01:23:42.334471 INFO: [APUAPC] D12_APC_1: 0xffffffff
9916 01:23:42.337250 INFO: [APUAPC] D12_APC_2: 0x3fffff
9917 01:23:42.340875 INFO: [APUAPC] D12_APC_3: 0x0
9918 01:23:42.344479 INFO: [APUAPC] D13_APC_0: 0xffffffff
9919 01:23:42.347320 INFO: [APUAPC] D13_APC_1: 0xffffffff
9920 01:23:42.350723 INFO: [APUAPC] D13_APC_2: 0x3fffff
9921 01:23:42.354123 INFO: [APUAPC] D13_APC_3: 0x0
9922 01:23:42.357565 INFO: [APUAPC] D14_APC_0: 0xffffffff
9923 01:23:42.361063 INFO: [APUAPC] D14_APC_1: 0xffffffff
9924 01:23:42.364480 INFO: [APUAPC] D14_APC_2: 0x3fffff
9925 01:23:42.367443 INFO: [APUAPC] D14_APC_3: 0x0
9926 01:23:42.370911 INFO: [APUAPC] D15_APC_0: 0xffffffff
9927 01:23:42.373672 INFO: [APUAPC] D15_APC_1: 0xffffffff
9928 01:23:42.377379 INFO: [APUAPC] D15_APC_2: 0x3fffff
9929 01:23:42.380845 INFO: [APUAPC] D15_APC_3: 0x0
9930 01:23:42.383683 INFO: [APUAPC] APC_CON: 0x4
9931 01:23:42.387146 INFO: [NOCDAPC] D0_APC_0: 0x0
9932 01:23:42.390480 INFO: [NOCDAPC] D0_APC_1: 0x0
9933 01:23:42.393497 INFO: [NOCDAPC] D1_APC_0: 0x0
9934 01:23:42.397095 INFO: [NOCDAPC] D1_APC_1: 0xfff
9935 01:23:42.400712 INFO: [NOCDAPC] D2_APC_0: 0x0
9936 01:23:42.403610 INFO: [NOCDAPC] D2_APC_1: 0xfff
9937 01:23:42.403717 INFO: [NOCDAPC] D3_APC_0: 0x0
9938 01:23:42.407217 INFO: [NOCDAPC] D3_APC_1: 0xfff
9939 01:23:42.410498 INFO: [NOCDAPC] D4_APC_0: 0x0
9940 01:23:42.413313 INFO: [NOCDAPC] D4_APC_1: 0xfff
9941 01:23:42.416637 INFO: [NOCDAPC] D5_APC_0: 0x0
9942 01:23:42.420197 INFO: [NOCDAPC] D5_APC_1: 0xfff
9943 01:23:42.423828 INFO: [NOCDAPC] D6_APC_0: 0x0
9944 01:23:42.427174 INFO: [NOCDAPC] D6_APC_1: 0xfff
9945 01:23:42.430130 INFO: [NOCDAPC] D7_APC_0: 0x0
9946 01:23:42.433416 INFO: [NOCDAPC] D7_APC_1: 0xfff
9947 01:23:42.433499 INFO: [NOCDAPC] D8_APC_0: 0x0
9948 01:23:42.436994 INFO: [NOCDAPC] D8_APC_1: 0xfff
9949 01:23:42.440464 INFO: [NOCDAPC] D9_APC_0: 0x0
9950 01:23:42.443765 INFO: [NOCDAPC] D9_APC_1: 0xfff
9951 01:23:42.447077 INFO: [NOCDAPC] D10_APC_0: 0x0
9952 01:23:42.450123 INFO: [NOCDAPC] D10_APC_1: 0xfff
9953 01:23:42.453655 INFO: [NOCDAPC] D11_APC_0: 0x0
9954 01:23:42.456487 INFO: [NOCDAPC] D11_APC_1: 0xfff
9955 01:23:42.460011 INFO: [NOCDAPC] D12_APC_0: 0x0
9956 01:23:42.463286 INFO: [NOCDAPC] D12_APC_1: 0xfff
9957 01:23:42.466798 INFO: [NOCDAPC] D13_APC_0: 0x0
9958 01:23:42.470268 INFO: [NOCDAPC] D13_APC_1: 0xfff
9959 01:23:42.473773 INFO: [NOCDAPC] D14_APC_0: 0x0
9960 01:23:42.476545 INFO: [NOCDAPC] D14_APC_1: 0xfff
9961 01:23:42.480048 INFO: [NOCDAPC] D15_APC_0: 0x0
9962 01:23:42.480151 INFO: [NOCDAPC] D15_APC_1: 0xfff
9963 01:23:42.483578 INFO: [NOCDAPC] APC_CON: 0x4
9964 01:23:42.487087 INFO: [APUAPC] set_apusys_apc done
9965 01:23:42.489852 INFO: [DEVAPC] devapc_init done
9966 01:23:42.493330 INFO: GICv3 without legacy support detected.
9967 01:23:42.500256 INFO: ARM GICv3 driver initialized in EL3
9968 01:23:42.503007 INFO: Maximum SPI INTID supported: 639
9969 01:23:42.506716 INFO: BL31: Initializing runtime services
9970 01:23:42.513757 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9971 01:23:42.516914 INFO: SPM: enable CPC mode
9972 01:23:42.519711 INFO: mcdi ready for mcusys-off-idle and system suspend
9973 01:23:42.526765 INFO: BL31: Preparing for EL3 exit to normal world
9974 01:23:42.529610 INFO: Entry point address = 0x80000000
9975 01:23:42.529724 INFO: SPSR = 0x8
9976 01:23:42.536829
9977 01:23:42.536913
9978 01:23:42.536991
9979 01:23:42.539601 Starting depthcharge on Spherion...
9980 01:23:42.539684
9981 01:23:42.539748 Wipe memory regions:
9982 01:23:42.539813
9983 01:23:42.540558 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9984 01:23:42.540671 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
9985 01:23:42.540753 Setting prompt string to ['asurada:']
9986 01:23:42.540876 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
9987 01:23:42.543121 [0x00000040000000, 0x00000054600000)
9988 01:23:42.665462
9989 01:23:42.665603 [0x00000054660000, 0x00000080000000)
9990 01:23:42.926192
9991 01:23:42.926362 [0x000000821a7280, 0x000000ffe64000)
9992 01:23:43.670752
9993 01:23:43.670895 [0x00000100000000, 0x00000240000000)
9994 01:23:45.561189
9995 01:23:45.564661 Initializing XHCI USB controller at 0x11200000.
9996 01:23:46.602922
9997 01:23:46.605577 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9998 01:23:46.605667
9999 01:23:46.605732
10000 01:23:46.605793
10001 01:23:46.606085 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10003 01:23:46.706380 asurada: tftpboot 192.168.201.1 13468761/tftp-deploy-xzv199mm/kernel/image.itb 13468761/tftp-deploy-xzv199mm/kernel/cmdline
10004 01:23:46.706567 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10005 01:23:46.706684 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10006 01:23:46.711072 tftpboot 192.168.201.1 13468761/tftp-deploy-xzv199mm/kernel/image.itp-deploy-xzv199mm/kernel/cmdline
10007 01:23:46.711161
10008 01:23:46.711229 Waiting for link
10009 01:23:46.871245
10010 01:23:46.871379 R8152: Initializing
10011 01:23:46.871447
10012 01:23:46.874498 Version 9 (ocp_data = 6010)
10013 01:23:46.874608
10014 01:23:46.877854 R8152: Done initializing
10015 01:23:46.877961
10016 01:23:46.878052 Adding net device
10017 01:23:48.824461
10018 01:23:48.824600 done.
10019 01:23:48.824687
10020 01:23:48.824754 MAC: 00:e0:4c:78:7a:aa
10021 01:23:48.824816
10022 01:23:48.827178 Sending DHCP discover... done.
10023 01:23:48.827283
10024 01:23:52.183212 Waiting for reply... done.
10025 01:23:52.183372
10026 01:23:52.183469 Sending DHCP request... done.
10027 01:23:52.186100
10028 01:23:52.186189 Waiting for reply... done.
10029 01:23:52.186254
10030 01:23:52.188916 My ip is 192.168.201.12
10031 01:23:52.189016
10032 01:23:52.192620 The DHCP server ip is 192.168.201.1
10033 01:23:52.192735
10034 01:23:52.196225 TFTP server IP predefined by user: 192.168.201.1
10035 01:23:52.196326
10036 01:23:52.202624 Bootfile predefined by user: 13468761/tftp-deploy-xzv199mm/kernel/image.itb
10037 01:23:52.202729
10038 01:23:52.206155 Sending tftp read request... done.
10039 01:23:52.206257
10040 01:23:52.209505 Waiting for the transfer...
10041 01:23:52.209592
10042 01:23:52.458215 00000000 ################################################################
10043 01:23:52.458376
10044 01:23:52.703859 00080000 ################################################################
10045 01:23:52.704018
10046 01:23:52.949448 00100000 ################################################################
10047 01:23:52.949624
10048 01:23:53.195380 00180000 ################################################################
10049 01:23:53.195518
10050 01:23:53.443022 00200000 ################################################################
10051 01:23:53.443184
10052 01:23:53.693147 00280000 ################################################################
10053 01:23:53.693284
10054 01:23:53.940498 00300000 ################################################################
10055 01:23:53.940654
10056 01:23:54.190389 00380000 ################################################################
10057 01:23:54.190556
10058 01:23:54.441412 00400000 ################################################################
10059 01:23:54.441577
10060 01:23:54.692537 00480000 ################################################################
10061 01:23:54.692701
10062 01:23:54.943259 00500000 ################################################################
10063 01:23:54.943425
10064 01:23:55.195542 00580000 ################################################################
10065 01:23:55.195712
10066 01:23:55.446755 00600000 ################################################################
10067 01:23:55.446893
10068 01:23:55.698254 00680000 ################################################################
10069 01:23:55.698419
10070 01:23:55.949266 00700000 ################################################################
10071 01:23:55.949436
10072 01:23:56.201114 00780000 ################################################################
10073 01:23:56.201285
10074 01:23:56.453236 00800000 ################################################################
10075 01:23:56.453406
10076 01:23:56.704062 00880000 ################################################################
10077 01:23:56.704229
10078 01:23:56.952908 00900000 ################################################################
10079 01:23:56.953063
10080 01:23:57.201257 00980000 ################################################################
10081 01:23:57.201399
10082 01:23:57.449912 00a00000 ################################################################
10083 01:23:57.450076
10084 01:23:57.685129 00a80000 ################################################################
10085 01:23:57.685287
10086 01:23:57.923871 00b00000 ################################################################
10087 01:23:57.924023
10088 01:23:58.160202 00b80000 ################################################################
10089 01:23:58.160390
10090 01:23:58.396511 00c00000 ################################################################
10091 01:23:58.396663
10092 01:23:58.632868 00c80000 ################################################################
10093 01:23:58.633004
10094 01:23:58.868680 00d00000 ################################################################
10095 01:23:58.868843
10096 01:23:59.105697 00d80000 ################################################################
10097 01:23:59.105834
10098 01:23:59.354898 00e00000 ################################################################
10099 01:23:59.355073
10100 01:23:59.603537 00e80000 ################################################################
10101 01:23:59.603705
10102 01:23:59.852416 00f00000 ################################################################
10103 01:23:59.852582
10104 01:24:00.101942 00f80000 ################################################################
10105 01:24:00.102099
10106 01:24:00.350046 01000000 ################################################################
10107 01:24:00.350181
10108 01:24:00.599501 01080000 ################################################################
10109 01:24:00.599670
10110 01:24:00.846549 01100000 ################################################################
10111 01:24:00.846699
10112 01:24:01.094671 01180000 ################################################################
10113 01:24:01.094850
10114 01:24:01.343619 01200000 ################################################################
10115 01:24:01.343773
10116 01:24:01.593144 01280000 ################################################################
10117 01:24:01.593312
10118 01:24:01.842029 01300000 ################################################################
10119 01:24:01.842163
10120 01:24:02.092476 01380000 ################################################################
10121 01:24:02.092642
10122 01:24:02.342611 01400000 ################################################################
10123 01:24:02.342764
10124 01:24:02.593778 01480000 ################################################################
10125 01:24:02.593917
10126 01:24:02.843387 01500000 ################################################################
10127 01:24:02.843535
10128 01:24:03.093530 01580000 ################################################################
10129 01:24:03.093695
10130 01:24:03.343622 01600000 ################################################################
10131 01:24:03.343782
10132 01:24:03.592922 01680000 ################################################################
10133 01:24:03.593064
10134 01:24:03.842423 01700000 ################################################################
10135 01:24:03.842583
10136 01:24:04.094532 01780000 ################################################################
10137 01:24:04.094702
10138 01:24:04.344019 01800000 ################################################################
10139 01:24:04.344192
10140 01:24:04.592956 01880000 ################################################################
10141 01:24:04.593115
10142 01:24:04.844089 01900000 ################################################################
10143 01:24:04.844253
10144 01:24:05.093074 01980000 ################################################################
10145 01:24:05.093202
10146 01:24:05.341511 01a00000 ################################################################
10147 01:24:05.341648
10148 01:24:05.590906 01a80000 ################################################################
10149 01:24:05.591066
10150 01:24:05.841102 01b00000 ################################################################
10151 01:24:05.841262
10152 01:24:06.091272 01b80000 ################################################################
10153 01:24:06.091415
10154 01:24:06.337952 01c00000 ################################################################
10155 01:24:06.338124
10156 01:24:06.589655 01c80000 ################################################################
10157 01:24:06.589821
10158 01:24:06.839719 01d00000 ################################################################
10159 01:24:06.839890
10160 01:24:07.088800 01d80000 ################################################################
10161 01:24:07.088981
10162 01:24:07.337477 01e00000 ################################################################
10163 01:24:07.337661
10164 01:24:07.588357 01e80000 ################################################################
10165 01:24:07.588513
10166 01:24:07.842663 01f00000 ################################################################
10167 01:24:07.842818
10168 01:24:08.090951 01f80000 ################################################################
10169 01:24:08.091119
10170 01:24:08.341467 02000000 ################################################################
10171 01:24:08.341719
10172 01:24:08.594289 02080000 ################################################################
10173 01:24:08.594471
10174 01:24:08.843270 02100000 ################################################################
10175 01:24:08.843411
10176 01:24:09.091680 02180000 ################################################################
10177 01:24:09.091817
10178 01:24:09.340480 02200000 ################################################################
10179 01:24:09.340613
10180 01:24:09.590472 02280000 ################################################################
10181 01:24:09.590629
10182 01:24:09.845838 02300000 ################################################################
10183 01:24:09.845997
10184 01:24:10.094625 02380000 ################################################################
10185 01:24:10.094790
10186 01:24:10.349249 02400000 ################################################################
10187 01:24:10.349414
10188 01:24:10.598099 02480000 ################################################################
10189 01:24:10.598236
10190 01:24:10.849722 02500000 ################################################################
10191 01:24:10.849855
10192 01:24:11.098243 02580000 ################################################################
10193 01:24:11.098397
10194 01:24:11.347909 02600000 ################################################################
10195 01:24:11.348047
10196 01:24:11.602372 02680000 ################################################################
10197 01:24:11.602516
10198 01:24:11.853288 02700000 ################################################################
10199 01:24:11.853434
10200 01:24:12.103468 02780000 ################################################################
10201 01:24:12.103614
10202 01:24:12.356401 02800000 ################################################################
10203 01:24:12.356575
10204 01:24:12.611613 02880000 ################################################################
10205 01:24:12.611780
10206 01:24:12.865603 02900000 ################################################################
10207 01:24:12.865739
10208 01:24:13.126899 02980000 ################################################################
10209 01:24:13.127059
10210 01:24:13.391275 02a00000 ################################################################
10211 01:24:13.391410
10212 01:24:13.651538 02a80000 ################################################################
10213 01:24:13.651697
10214 01:24:13.915282 02b00000 ################################################################
10215 01:24:13.915462
10216 01:24:14.176354 02b80000 ################################################################
10217 01:24:14.176489
10218 01:24:14.436055 02c00000 ################################################################
10219 01:24:14.436222
10220 01:24:14.688159 02c80000 ################################################################
10221 01:24:14.688320
10222 01:24:14.957240 02d00000 ################################################################
10223 01:24:14.957411
10224 01:24:15.217753 02d80000 ################################################################
10225 01:24:15.217896
10226 01:24:15.472098 02e00000 ################################################################
10227 01:24:15.472229
10228 01:24:15.727205 02e80000 ################################################################
10229 01:24:15.727340
10230 01:24:15.982316 02f00000 ################################################################
10231 01:24:15.982449
10232 01:24:16.237342 02f80000 ################################################################
10233 01:24:16.237509
10234 01:24:16.497954 03000000 ################################################################
10235 01:24:16.498116
10236 01:24:16.771383 03080000 ################################################################
10237 01:24:16.771544
10238 01:24:17.029768 03100000 ################################################################
10239 01:24:17.029905
10240 01:24:17.295082 03180000 ################################################################
10241 01:24:17.295218
10242 01:24:17.549645 03200000 ################################################################
10243 01:24:17.549777
10244 01:24:17.818111 03280000 ################################################################
10245 01:24:17.818278
10246 01:24:18.078394 03300000 ################################################################
10247 01:24:18.078533
10248 01:24:18.179186 03380000 ########################## done.
10249 01:24:18.179322
10250 01:24:18.182311 The bootfile was 54210922 bytes long.
10251 01:24:18.182425
10252 01:24:18.185956 Sending tftp read request... done.
10253 01:24:18.186070
10254 01:24:18.188927 Waiting for the transfer...
10255 01:24:18.189011
10256 01:24:18.189077 00000000 # done.
10257 01:24:18.192723
10258 01:24:18.198876 Command line loaded dynamically from TFTP file: 13468761/tftp-deploy-xzv199mm/kernel/cmdline
10259 01:24:18.198992
10260 01:24:18.212516 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10261 01:24:18.212633
10262 01:24:18.212729 Loading FIT.
10263 01:24:18.212823
10264 01:24:18.215284 Image ramdisk-1 has 41251605 bytes.
10265 01:24:18.215387
10266 01:24:18.219058 Image fdt-1 has 47230 bytes.
10267 01:24:18.219166
10268 01:24:18.222059 Image kernel-1 has 12910050 bytes.
10269 01:24:18.222168
10270 01:24:18.232284 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10271 01:24:18.232395
10272 01:24:18.248780 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10273 01:24:18.248896
10274 01:24:18.255416 Choosing best match conf-1 for compat google,spherion-rev2.
10275 01:24:18.255527
10276 01:24:18.263131 Connected to device vid:did:rid of 1ae0:0028:00
10277 01:24:18.270899
10278 01:24:18.274389 tpm_get_response: command 0x17b, return code 0x0
10279 01:24:18.274472
10280 01:24:18.277900 ec_init: CrosEC protocol v3 supported (256, 248)
10281 01:24:18.295880
10282 01:24:18.295965 tpm_cleanup: add release locality here.
10283 01:24:18.296031
10284 01:24:18.296091 Shutting down all USB controllers.
10285 01:24:18.296150
10286 01:24:18.296207 Removing current net device
10287 01:24:18.296264
10288 01:24:18.296320 Exiting depthcharge with code 4 at timestamp: 64962963
10289 01:24:18.296375
10290 01:24:18.298644 LZMA decompressing kernel-1 to 0x821a6718
10291 01:24:18.298750
10292 01:24:18.301856 LZMA decompressing kernel-1 to 0x40000000
10293 01:24:19.895848
10294 01:24:19.895982 jumping to kernel
10295 01:24:19.896492 end: 2.2.4 bootloader-commands (duration 00:00:37) [common]
10296 01:24:19.896593 start: 2.2.5 auto-login-action (timeout 00:03:48) [common]
10297 01:24:19.896668 Setting prompt string to ['Linux version [0-9]']
10298 01:24:19.896736 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10299 01:24:19.896803 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10300 01:24:19.977772
10301 01:24:19.980691 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10302 01:24:19.984639 start: 2.2.5.1 login-action (timeout 00:03:48) [common]
10303 01:24:19.984731 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10304 01:24:19.984803 Setting prompt string to []
10305 01:24:19.984958 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10306 01:24:19.985079 Using line separator: #'\n'#
10307 01:24:19.985171 No login prompt set.
10308 01:24:19.985264 Parsing kernel messages
10309 01:24:19.985347 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10310 01:24:19.985456 [login-action] Waiting for messages, (timeout 00:03:48)
10311 01:24:19.985520 Waiting using forced prompt support (timeout 00:01:54)
10312 01:24:20.004368 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j174389-arm64-gcc-10-defconfig-arm64-chromebook-96m9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024
10313 01:24:20.007366 [ 0.000000] random: crng init done
10314 01:24:20.014494 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10315 01:24:20.014578 [ 0.000000] efi: UEFI not found.
10316 01:24:20.024182 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10317 01:24:20.030957 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10318 01:24:20.040807 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10319 01:24:20.050814 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10320 01:24:20.057866 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10321 01:24:20.060714 [ 0.000000] printk: bootconsole [mtk8250] enabled
10322 01:24:20.069324 [ 0.000000] NUMA: No NUMA configuration found
10323 01:24:20.076093 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10324 01:24:20.082644 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10325 01:24:20.082725 [ 0.000000] Zone ranges:
10326 01:24:20.089332 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10327 01:24:20.092361 [ 0.000000] DMA32 empty
10328 01:24:20.099516 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10329 01:24:20.102955 [ 0.000000] Movable zone start for each node
10330 01:24:20.105750 [ 0.000000] Early memory node ranges
10331 01:24:20.112638 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10332 01:24:20.119449 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10333 01:24:20.125993 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10334 01:24:20.132343 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10335 01:24:20.139068 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10336 01:24:20.145850 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10337 01:24:20.201886 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10338 01:24:20.208907 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10339 01:24:20.215534 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10340 01:24:20.218677 [ 0.000000] psci: probing for conduit method from DT.
10341 01:24:20.225507 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10342 01:24:20.228976 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10343 01:24:20.235148 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10344 01:24:20.238580 [ 0.000000] psci: SMC Calling Convention v1.2
10345 01:24:20.245417 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10346 01:24:20.248727 [ 0.000000] Detected VIPT I-cache on CPU0
10347 01:24:20.255398 [ 0.000000] CPU features: detected: GIC system register CPU interface
10348 01:24:20.262056 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10349 01:24:20.268508 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10350 01:24:20.274801 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10351 01:24:20.282044 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10352 01:24:20.291742 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10353 01:24:20.295248 [ 0.000000] alternatives: applying boot alternatives
10354 01:24:20.301623 [ 0.000000] Fallback order for Node 0: 0
10355 01:24:20.308544 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10356 01:24:20.308672 [ 0.000000] Policy zone: Normal
10357 01:24:20.324880 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10358 01:24:20.334865 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10359 01:24:20.345663 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10360 01:24:20.355661 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10361 01:24:20.361998 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10362 01:24:20.365320 <6>[ 0.000000] software IO TLB: area num 8.
10363 01:24:20.422125 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10364 01:24:20.571072 <6>[ 0.000000] Memory: 7924224K/8385536K available (18048K kernel code, 4118K rwdata, 22292K rodata, 8448K init, 616K bss, 428544K reserved, 32768K cma-reserved)
10365 01:24:20.577885 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10366 01:24:20.584401 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10367 01:24:20.587692 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10368 01:24:20.593904 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10369 01:24:20.600868 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10370 01:24:20.604496 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10371 01:24:20.614037 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10372 01:24:20.621058 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10373 01:24:20.624001 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10374 01:24:20.632161 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10375 01:24:20.635805 <6>[ 0.000000] GICv3: 608 SPIs implemented
10376 01:24:20.641925 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10377 01:24:20.645301 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10378 01:24:20.648949 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10379 01:24:20.655288 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10380 01:24:20.668661 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10381 01:24:20.682180 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10382 01:24:20.688863 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10383 01:24:20.697657 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10384 01:24:20.710696 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10385 01:24:20.717445 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10386 01:24:20.723986 <6>[ 0.009189] Console: colour dummy device 80x25
10387 01:24:20.734177 <6>[ 0.013946] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10388 01:24:20.737608 <6>[ 0.024388] pid_max: default: 32768 minimum: 301
10389 01:24:20.744502 <6>[ 0.029289] LSM: Security Framework initializing
10390 01:24:20.750896 <6>[ 0.034228] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10391 01:24:20.760558 <6>[ 0.042045] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10392 01:24:20.767705 <6>[ 0.051453] cblist_init_generic: Setting adjustable number of callback queues.
10393 01:24:20.774073 <6>[ 0.058894] cblist_init_generic: Setting shift to 3 and lim to 1.
10394 01:24:20.784278 <6>[ 0.065233] cblist_init_generic: Setting adjustable number of callback queues.
10395 01:24:20.787040 <6>[ 0.072661] cblist_init_generic: Setting shift to 3 and lim to 1.
10396 01:24:20.793834 <6>[ 0.079061] rcu: Hierarchical SRCU implementation.
10397 01:24:20.800464 <6>[ 0.084076] rcu: Max phase no-delay instances is 1000.
10398 01:24:20.807058 <6>[ 0.091138] EFI services will not be available.
10399 01:24:20.810648 <6>[ 0.096122] smp: Bringing up secondary CPUs ...
10400 01:24:20.818617 <6>[ 0.101199] Detected VIPT I-cache on CPU1
10401 01:24:20.825017 <6>[ 0.101268] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10402 01:24:20.832189 <6>[ 0.101299] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10403 01:24:20.834948 <6>[ 0.101630] Detected VIPT I-cache on CPU2
10404 01:24:20.842080 <6>[ 0.101676] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10405 01:24:20.848583 <6>[ 0.101692] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10406 01:24:20.855020 <6>[ 0.101947] Detected VIPT I-cache on CPU3
10407 01:24:20.862128 <6>[ 0.101994] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10408 01:24:20.868361 <6>[ 0.102007] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10409 01:24:20.871781 <6>[ 0.102310] CPU features: detected: Spectre-v4
10410 01:24:20.878165 <6>[ 0.102317] CPU features: detected: Spectre-BHB
10411 01:24:20.881646 <6>[ 0.102322] Detected PIPT I-cache on CPU4
10412 01:24:20.889451 <6>[ 0.102380] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10413 01:24:20.895273 <6>[ 0.102397] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10414 01:24:20.901516 <6>[ 0.102688] Detected PIPT I-cache on CPU5
10415 01:24:20.908512 <6>[ 0.102752] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10416 01:24:20.914814 <6>[ 0.102768] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10417 01:24:20.918456 <6>[ 0.103050] Detected PIPT I-cache on CPU6
10418 01:24:20.924831 <6>[ 0.103114] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10419 01:24:20.931336 <6>[ 0.103130] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10420 01:24:20.938113 <6>[ 0.103425] Detected PIPT I-cache on CPU7
10421 01:24:20.944915 <6>[ 0.103489] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10422 01:24:20.951134 <6>[ 0.103505] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10423 01:24:20.954549 <6>[ 0.103553] smp: Brought up 1 node, 8 CPUs
10424 01:24:20.958266 <6>[ 0.244881] SMP: Total of 8 processors activated.
10425 01:24:20.964911 <6>[ 0.249802] CPU features: detected: 32-bit EL0 Support
10426 01:24:20.974448 <6>[ 0.255165] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10427 01:24:20.981335 <6>[ 0.263966] CPU features: detected: Common not Private translations
10428 01:24:20.984900 <6>[ 0.270483] CPU features: detected: CRC32 instructions
10429 01:24:20.991522 <6>[ 0.275867] CPU features: detected: RCpc load-acquire (LDAPR)
10430 01:24:20.997829 <6>[ 0.281828] CPU features: detected: LSE atomic instructions
10431 01:24:21.004534 <6>[ 0.287645] CPU features: detected: Privileged Access Never
10432 01:24:21.007989 <6>[ 0.293425] CPU features: detected: RAS Extension Support
10433 01:24:21.017958 <6>[ 0.299034] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10434 01:24:21.020919 <6>[ 0.306256] CPU: All CPU(s) started at EL2
10435 01:24:21.027365 <6>[ 0.310599] alternatives: applying system-wide alternatives
10436 01:24:21.036375 <6>[ 0.321422] devtmpfs: initialized
10437 01:24:21.048819 <6>[ 0.330326] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10438 01:24:21.058412 <6>[ 0.340287] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10439 01:24:21.065438 <6>[ 0.348518] pinctrl core: initialized pinctrl subsystem
10440 01:24:21.068137 <6>[ 0.355160] DMI not present or invalid.
10441 01:24:21.074848 <6>[ 0.359571] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10442 01:24:21.085352 <6>[ 0.366456] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10443 01:24:21.091860 <6>[ 0.374043] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10444 01:24:21.101502 <6>[ 0.382271] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10445 01:24:21.105188 <6>[ 0.390516] audit: initializing netlink subsys (disabled)
10446 01:24:21.114503 <5>[ 0.396198] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10447 01:24:21.121433 <6>[ 0.396863] thermal_sys: Registered thermal governor 'step_wise'
10448 01:24:21.128173 <6>[ 0.404162] thermal_sys: Registered thermal governor 'power_allocator'
10449 01:24:21.131675 <6>[ 0.410419] cpuidle: using governor menu
10450 01:24:21.138187 <6>[ 0.421379] NET: Registered PF_QIPCRTR protocol family
10451 01:24:21.144616 <6>[ 0.426867] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10452 01:24:21.151395 <6>[ 0.433968] ASID allocator initialised with 32768 entries
10453 01:24:21.154384 <6>[ 0.440533] Serial: AMBA PL011 UART driver
10454 01:24:21.163850 <4>[ 0.449277] Trying to register duplicate clock ID: 134
10455 01:24:21.218765 <6>[ 0.506990] KASLR enabled
10456 01:24:21.233206 <6>[ 0.514698] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10457 01:24:21.239795 <6>[ 0.521709] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10458 01:24:21.245998 <6>[ 0.528200] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10459 01:24:21.252406 <6>[ 0.535208] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10460 01:24:21.259819 <6>[ 0.541697] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10461 01:24:21.266291 <6>[ 0.548704] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10462 01:24:21.272685 <6>[ 0.555192] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10463 01:24:21.279320 <6>[ 0.562198] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10464 01:24:21.283029 <6>[ 0.569723] ACPI: Interpreter disabled.
10465 01:24:21.291114 <6>[ 0.576146] iommu: Default domain type: Translated
10466 01:24:21.297403 <6>[ 0.581257] iommu: DMA domain TLB invalidation policy: strict mode
10467 01:24:21.301020 <5>[ 0.587912] SCSI subsystem initialized
10468 01:24:21.307452 <6>[ 0.592073] usbcore: registered new interface driver usbfs
10469 01:24:21.313846 <6>[ 0.597808] usbcore: registered new interface driver hub
10470 01:24:21.317491 <6>[ 0.603360] usbcore: registered new device driver usb
10471 01:24:21.324393 <6>[ 0.609454] pps_core: LinuxPPS API ver. 1 registered
10472 01:24:21.333904 <6>[ 0.614648] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10473 01:24:21.337786 <6>[ 0.623995] PTP clock support registered
10474 01:24:21.340822 <6>[ 0.628238] EDAC MC: Ver: 3.0.0
10475 01:24:21.348072 <6>[ 0.633387] FPGA manager framework
10476 01:24:21.355286 <6>[ 0.637067] Advanced Linux Sound Architecture Driver Initialized.
10477 01:24:21.358098 <6>[ 0.643844] vgaarb: loaded
10478 01:24:21.364672 <6>[ 0.647010] clocksource: Switched to clocksource arch_sys_counter
10479 01:24:21.368203 <5>[ 0.653452] VFS: Disk quotas dquot_6.6.0
10480 01:24:21.374601 <6>[ 0.657637] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10481 01:24:21.377570 <6>[ 0.664827] pnp: PnP ACPI: disabled
10482 01:24:21.386602 <6>[ 0.671526] NET: Registered PF_INET protocol family
10483 01:24:21.396277 <6>[ 0.677138] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10484 01:24:21.407680 <6>[ 0.689448] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10485 01:24:21.417558 <6>[ 0.698266] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10486 01:24:21.424153 <6>[ 0.706235] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10487 01:24:21.430463 <6>[ 0.714887] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10488 01:24:21.442510 <6>[ 0.724629] TCP: Hash tables configured (established 65536 bind 65536)
10489 01:24:21.449619 <6>[ 0.731428] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10490 01:24:21.455870 <6>[ 0.738627] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10491 01:24:21.462624 <6>[ 0.746329] NET: Registered PF_UNIX/PF_LOCAL protocol family
10492 01:24:21.469077 <6>[ 0.752420] RPC: Registered named UNIX socket transport module.
10493 01:24:21.472865 <6>[ 0.758566] RPC: Registered udp transport module.
10494 01:24:21.479059 <6>[ 0.763497] RPC: Registered tcp transport module.
10495 01:24:21.486038 <6>[ 0.768427] RPC: Registered tcp NFSv4.1 backchannel transport module.
10496 01:24:21.488955 <6>[ 0.775092] PCI: CLS 0 bytes, default 64
10497 01:24:21.492523 <6>[ 0.779489] Unpacking initramfs...
10498 01:24:21.510025 <6>[ 0.791639] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10499 01:24:21.520064 <6>[ 0.800318] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10500 01:24:21.523199 <6>[ 0.809194] kvm [1]: IPA Size Limit: 40 bits
10501 01:24:21.529353 <6>[ 0.813719] kvm [1]: GICv3: no GICV resource entry
10502 01:24:21.533052 <6>[ 0.818738] kvm [1]: disabling GICv2 emulation
10503 01:24:21.539517 <6>[ 0.823431] kvm [1]: GIC system register CPU interface enabled
10504 01:24:21.542947 <6>[ 0.829627] kvm [1]: vgic interrupt IRQ18
10505 01:24:21.549331 <6>[ 0.833987] kvm [1]: VHE mode initialized successfully
10506 01:24:21.555892 <5>[ 0.840452] Initialise system trusted keyrings
10507 01:24:21.562236 <6>[ 0.845267] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10508 01:24:21.570509 <6>[ 0.855306] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10509 01:24:21.577062 <5>[ 0.861720] NFS: Registering the id_resolver key type
10510 01:24:21.580254 <5>[ 0.867026] Key type id_resolver registered
10511 01:24:21.586685 <5>[ 0.871440] Key type id_legacy registered
10512 01:24:21.593045 <6>[ 0.875724] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10513 01:24:21.599803 <6>[ 0.882642] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10514 01:24:21.606579 <6>[ 0.890366] 9p: Installing v9fs 9p2000 file system support
10515 01:24:21.643057 <5>[ 0.928388] Key type asymmetric registered
10516 01:24:21.646334 <5>[ 0.932719] Asymmetric key parser 'x509' registered
10517 01:24:21.656928 <6>[ 0.937888] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10518 01:24:21.659747 <6>[ 0.945501] io scheduler mq-deadline registered
10519 01:24:21.663488 <6>[ 0.950274] io scheduler kyber registered
10520 01:24:21.681885 <6>[ 0.967246] EINJ: ACPI disabled.
10521 01:24:21.714147 <4>[ 0.993022] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10522 01:24:21.724440 <4>[ 1.003640] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10523 01:24:21.738827 <6>[ 1.024373] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10524 01:24:21.747253 <6>[ 1.032417] printk: console [ttyS0] disabled
10525 01:24:21.775067 <6>[ 1.057046] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10526 01:24:21.781486 <6>[ 1.066511] printk: console [ttyS0] enabled
10527 01:24:21.785089 <6>[ 1.066511] printk: console [ttyS0] enabled
10528 01:24:21.791502 <6>[ 1.075403] printk: bootconsole [mtk8250] disabled
10529 01:24:21.795188 <6>[ 1.075403] printk: bootconsole [mtk8250] disabled
10530 01:24:21.801355 <6>[ 1.086607] SuperH (H)SCI(F) driver initialized
10531 01:24:21.804631 <6>[ 1.091902] msm_serial: driver initialized
10532 01:24:21.818637 <6>[ 1.100916] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10533 01:24:21.828540 <6>[ 1.109467] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10534 01:24:21.835322 <6>[ 1.118010] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10535 01:24:21.845719 <6>[ 1.126637] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10536 01:24:21.855065 <6>[ 1.135343] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10537 01:24:21.861496 <6>[ 1.144057] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10538 01:24:21.871816 <6>[ 1.152598] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10539 01:24:21.878819 <6>[ 1.161396] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10540 01:24:21.888437 <6>[ 1.169937] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10541 01:24:21.900669 <6>[ 1.185625] loop: module loaded
10542 01:24:21.906964 <6>[ 1.191641] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10543 01:24:21.930507 <4>[ 1.215333] mtk-pmic-keys: Failed to locate of_node [id: -1]
10544 01:24:21.936712 <6>[ 1.222204] megasas: 07.719.03.00-rc1
10545 01:24:21.946473 <6>[ 1.231949] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10546 01:24:21.957147 <6>[ 1.242389] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10547 01:24:21.973897 <6>[ 1.258947] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10548 01:24:22.029774 <6>[ 1.308290] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10549 01:24:23.223502 <6>[ 2.508972] Freeing initrd memory: 40280K
10550 01:24:23.234918 <6>[ 2.520618] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10551 01:24:23.246238 <6>[ 2.531752] tun: Universal TUN/TAP device driver, 1.6
10552 01:24:23.249608 <6>[ 2.537819] thunder_xcv, ver 1.0
10553 01:24:23.252967 <6>[ 2.541325] thunder_bgx, ver 1.0
10554 01:24:23.256580 <6>[ 2.544837] nicpf, ver 1.0
10555 01:24:23.266979 <6>[ 2.548862] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10556 01:24:23.270609 <6>[ 2.556338] hns3: Copyright (c) 2017 Huawei Corporation.
10557 01:24:23.273746 <6>[ 2.561931] hclge is initializing
10558 01:24:23.280200 <6>[ 2.565514] e1000: Intel(R) PRO/1000 Network Driver
10559 01:24:23.287140 <6>[ 2.570643] e1000: Copyright (c) 1999-2006 Intel Corporation.
10560 01:24:23.289854 <6>[ 2.576655] e1000e: Intel(R) PRO/1000 Network Driver
10561 01:24:23.296878 <6>[ 2.581871] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10562 01:24:23.303005 <6>[ 2.588057] igb: Intel(R) Gigabit Ethernet Network Driver
10563 01:24:23.310134 <6>[ 2.593706] igb: Copyright (c) 2007-2014 Intel Corporation.
10564 01:24:23.316789 <6>[ 2.599542] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10565 01:24:23.323133 <6>[ 2.606060] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10566 01:24:23.326093 <6>[ 2.612524] sky2: driver version 1.30
10567 01:24:23.333080 <6>[ 2.617508] VFIO - User Level meta-driver version: 0.3
10568 01:24:23.340605 <6>[ 2.625740] usbcore: registered new interface driver usb-storage
10569 01:24:23.347262 <6>[ 2.632191] usbcore: registered new device driver onboard-usb-hub
10570 01:24:23.355989 <6>[ 2.641353] mt6397-rtc mt6359-rtc: registered as rtc0
10571 01:24:23.366085 <6>[ 2.646817] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-23T01:20:12 UTC (1713835212)
10572 01:24:23.368757 <6>[ 2.656383] i2c_dev: i2c /dev entries driver
10573 01:24:23.386012 <6>[ 2.668255] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10574 01:24:23.393048 <4>[ 2.676984] cpu cpu0: supply cpu not found, using dummy regulator
10575 01:24:23.399502 <4>[ 2.683408] cpu cpu1: supply cpu not found, using dummy regulator
10576 01:24:23.405777 <4>[ 2.689812] cpu cpu2: supply cpu not found, using dummy regulator
10577 01:24:23.413008 <4>[ 2.696231] cpu cpu3: supply cpu not found, using dummy regulator
10578 01:24:23.419570 <4>[ 2.702628] cpu cpu4: supply cpu not found, using dummy regulator
10579 01:24:23.425884 <4>[ 2.709021] cpu cpu5: supply cpu not found, using dummy regulator
10580 01:24:23.432441 <4>[ 2.715415] cpu cpu6: supply cpu not found, using dummy regulator
10581 01:24:23.439364 <4>[ 2.721819] cpu cpu7: supply cpu not found, using dummy regulator
10582 01:24:23.457033 <6>[ 2.742431] cpu cpu0: EM: created perf domain
10583 01:24:23.460035 <6>[ 2.747372] cpu cpu4: EM: created perf domain
10584 01:24:23.467525 <6>[ 2.752996] sdhci: Secure Digital Host Controller Interface driver
10585 01:24:23.474241 <6>[ 2.759428] sdhci: Copyright(c) Pierre Ossman
10586 01:24:23.480904 <6>[ 2.764386] Synopsys Designware Multimedia Card Interface Driver
10587 01:24:23.487182 <6>[ 2.771034] sdhci-pltfm: SDHCI platform and OF driver helper
10588 01:24:23.490625 <6>[ 2.771144] mmc0: CQHCI version 5.10
10589 01:24:23.497324 <6>[ 2.781400] ledtrig-cpu: registered to indicate activity on CPUs
10590 01:24:23.503741 <6>[ 2.788556] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10591 01:24:23.510214 <6>[ 2.795616] usbcore: registered new interface driver usbhid
10592 01:24:23.513932 <6>[ 2.801446] usbhid: USB HID core driver
10593 01:24:23.523735 <6>[ 2.805647] spi_master spi0: will run message pump with realtime priority
10594 01:24:23.566714 <6>[ 2.845535] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10595 01:24:23.586060 <6>[ 2.861006] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10596 01:24:23.592728 <6>[ 2.876069] cros-ec-spi spi0.0: Chrome EC device registered
10597 01:24:23.596600 <6>[ 2.882068] mmc0: Command Queue Engine enabled
10598 01:24:23.603140 <6>[ 2.886800] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10599 01:24:23.609873 <6>[ 2.894169] mmcblk0: mmc0:0001 DA4128 116 GiB
10600 01:24:23.616273 <6>[ 2.894811] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10601 01:24:23.623212 <6>[ 2.902501] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10602 01:24:23.629703 <6>[ 2.909414] NET: Registered PF_PACKET protocol family
10603 01:24:23.632761 <6>[ 2.915263] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10604 01:24:23.639728 <6>[ 2.919576] 9pnet: Installing 9P2000 support
10605 01:24:23.642659 <6>[ 2.925350] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10606 01:24:23.649589 <5>[ 2.929261] Key type dns_resolver registered
10607 01:24:23.656314 <6>[ 2.935198] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10608 01:24:23.659505 <6>[ 2.939529] registered taskstats version 1
10609 01:24:23.665771 <5>[ 2.949911] Loading compiled-in X.509 certificates
10610 01:24:23.693036 <4>[ 2.972118] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10611 01:24:23.703309 <4>[ 2.982797] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10612 01:24:23.709791 <3>[ 2.993325] debugfs: File 'uA_load' in directory '/' already present!
10613 01:24:23.716330 <3>[ 3.000025] debugfs: File 'min_uV' in directory '/' already present!
10614 01:24:23.722713 <3>[ 3.006632] debugfs: File 'max_uV' in directory '/' already present!
10615 01:24:23.730097 <3>[ 3.013301] debugfs: File 'constraint_flags' in directory '/' already present!
10616 01:24:23.740383 <3>[ 3.022633] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10617 01:24:23.749993 <6>[ 3.035677] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10618 01:24:23.757240 <6>[ 3.042457] xhci-mtk 11200000.usb: xHCI Host Controller
10619 01:24:23.763541 <6>[ 3.047968] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10620 01:24:23.773634 <6>[ 3.055816] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10621 01:24:23.780296 <6>[ 3.065239] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10622 01:24:23.787203 <6>[ 3.071310] xhci-mtk 11200000.usb: xHCI Host Controller
10623 01:24:23.793784 <6>[ 3.076785] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10624 01:24:23.799916 <6>[ 3.084431] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10625 01:24:23.806902 <6>[ 3.092266] hub 1-0:1.0: USB hub found
10626 01:24:23.809875 <6>[ 3.096290] hub 1-0:1.0: 1 port detected
10627 01:24:23.820327 <6>[ 3.100563] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10628 01:24:23.823721 <6>[ 3.109347] hub 2-0:1.0: USB hub found
10629 01:24:23.826849 <6>[ 3.113369] hub 2-0:1.0: 1 port detected
10630 01:24:23.834468 <6>[ 3.120039] mtk-msdc 11f70000.mmc: Got CD GPIO
10631 01:24:23.847903 <6>[ 3.129749] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10632 01:24:23.854476 <6>[ 3.137777] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10633 01:24:23.863881 <4>[ 3.145681] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10634 01:24:23.874016 <6>[ 3.155208] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10635 01:24:23.880557 <6>[ 3.163286] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10636 01:24:23.887274 <6>[ 3.171332] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10637 01:24:23.897253 <6>[ 3.179258] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10638 01:24:23.904297 <6>[ 3.187075] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10639 01:24:23.913785 <6>[ 3.194891] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10640 01:24:23.923887 <6>[ 3.205329] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10641 01:24:23.930207 <6>[ 3.213695] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10642 01:24:23.940374 <6>[ 3.222043] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10643 01:24:23.946883 <6>[ 3.230381] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10644 01:24:23.956796 <6>[ 3.238718] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10645 01:24:23.963543 <6>[ 3.247062] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10646 01:24:23.973518 <6>[ 3.255400] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10647 01:24:23.979917 <6>[ 3.263738] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10648 01:24:23.989930 <6>[ 3.272077] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10649 01:24:23.996318 <6>[ 3.280416] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10650 01:24:24.006442 <6>[ 3.288754] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10651 01:24:24.016479 <6>[ 3.297091] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10652 01:24:24.022969 <6>[ 3.305429] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10653 01:24:24.032912 <6>[ 3.313767] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10654 01:24:24.039897 <6>[ 3.322117] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10655 01:24:24.046689 <6>[ 3.330847] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10656 01:24:24.052904 <6>[ 3.338011] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10657 01:24:24.059588 <6>[ 3.344774] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10658 01:24:24.066235 <6>[ 3.351582] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10659 01:24:24.076090 <6>[ 3.358515] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10660 01:24:24.083120 <6>[ 3.365399] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10661 01:24:24.092976 <6>[ 3.374532] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10662 01:24:24.102726 <6>[ 3.383656] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10663 01:24:24.112953 <6>[ 3.392949] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10664 01:24:24.122712 <6>[ 3.402424] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10665 01:24:24.129141 <6>[ 3.411893] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10666 01:24:24.139494 <6>[ 3.421013] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10667 01:24:24.149106 <6>[ 3.430478] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10668 01:24:24.159233 <6>[ 3.439599] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10669 01:24:24.169034 <6>[ 3.448894] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10670 01:24:24.179040 <6>[ 3.459056] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10671 01:24:24.189403 <6>[ 3.470635] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10672 01:24:24.241437 <6>[ 3.523276] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10673 01:24:24.395978 <6>[ 3.681285] hub 1-1:1.0: USB hub found
10674 01:24:24.399389 <6>[ 3.685798] hub 1-1:1.0: 4 ports detected
10675 01:24:24.408971 <6>[ 3.694403] hub 1-1:1.0: USB hub found
10676 01:24:24.412222 <6>[ 3.698772] hub 1-1:1.0: 4 ports detected
10677 01:24:24.521373 <6>[ 3.803686] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10678 01:24:24.549119 <6>[ 3.834679] hub 2-1:1.0: USB hub found
10679 01:24:24.552490 <6>[ 3.839257] hub 2-1:1.0: 3 ports detected
10680 01:24:24.563150 <6>[ 3.848383] hub 2-1:1.0: USB hub found
10681 01:24:24.566461 <6>[ 3.852923] hub 2-1:1.0: 3 ports detected
10682 01:24:24.732696 <6>[ 4.015264] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10683 01:24:24.864479 <6>[ 4.150194] hub 1-1.4:1.0: USB hub found
10684 01:24:24.867960 <6>[ 4.154762] hub 1-1.4:1.0: 2 ports detected
10685 01:24:24.877126 <6>[ 4.162607] hub 1-1.4:1.0: USB hub found
10686 01:24:24.880718 <6>[ 4.167266] hub 1-1.4:1.0: 2 ports detected
10687 01:24:24.949446 <6>[ 4.231410] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10688 01:24:25.176935 <6>[ 4.459299] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10689 01:24:25.369206 <6>[ 4.651293] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10690 01:24:36.470613 <6>[ 15.760320] ALSA device list:
10691 01:24:36.476416 <6>[ 15.763609] No soundcards found.
10692 01:24:36.484713 <6>[ 15.771615] Freeing unused kernel memory: 8448K
10693 01:24:36.488122 <6>[ 15.777155] Run /init as init process
10694 01:24:36.519344 <6>[ 15.806206] NET: Registered PF_INET6 protocol family
10695 01:24:36.525997 <6>[ 15.812797] Segment Routing with IPv6
10696 01:24:36.529274 <6>[ 15.816742] In-situ OAM (IOAM) with IPv6
10697 01:24:36.571434 <30>[ 15.831761] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10698 01:24:36.578254 <30>[ 15.864881] systemd[1]: Detected architecture arm64.
10699 01:24:36.578394
10700 01:24:36.584414 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10701 01:24:36.584497
10702 01:24:36.584581
10703 01:24:36.600672 <30>[ 15.887372] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10704 01:24:36.748042 <30>[ 16.031316] systemd[1]: Queued start job for default target graphical.target.
10705 01:24:36.793139 <30>[ 16.077024] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10706 01:24:36.799936 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10707 01:24:36.800026
10708 01:24:36.820369 <30>[ 16.103988] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10709 01:24:36.827208 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10710 01:24:36.830472
10711 01:24:36.849053 <30>[ 16.132382] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10712 01:24:36.858648 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10713 01:24:36.858750
10714 01:24:36.876551 <30>[ 16.160528] systemd[1]: Created slice user.slice - User and Session Slice.
10715 01:24:36.883672 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10716 01:24:36.883764
10717 01:24:36.907791 <30>[ 16.188129] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10718 01:24:36.914772 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10719 01:24:36.918064
10720 01:24:36.935358 <30>[ 16.215482] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10721 01:24:36.942102 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10722 01:24:36.942215
10723 01:24:36.969953 <30>[ 16.243866] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10724 01:24:36.980209 <30>[ 16.263766] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10725 01:24:36.987000 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10726 01:24:36.987110
10727 01:24:37.004262 <30>[ 16.287712] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10728 01:24:37.010674 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10729 01:24:37.013871
10730 01:24:37.032558 <30>[ 16.315797] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10731 01:24:37.042493 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10732 01:24:37.042621
10733 01:24:37.056732 <30>[ 16.343820] systemd[1]: Reached target paths.target - Path Units.
10734 01:24:37.063938 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10735 01:24:37.066924
10736 01:24:37.084431 <30>[ 16.367770] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10737 01:24:37.090701 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10738 01:24:37.090792
10739 01:24:37.104289 <30>[ 16.391305] systemd[1]: Reached target slices.target - Slice Units.
10740 01:24:37.114506 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10741 01:24:37.114638
10742 01:24:37.128800 <30>[ 16.415811] systemd[1]: Reached target swap.target - Swaps.
10743 01:24:37.135495 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10744 01:24:37.135589
10745 01:24:37.155870 <30>[ 16.439819] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10746 01:24:37.166246 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10747 01:24:37.166403
10748 01:24:37.184860 <30>[ 16.468244] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10749 01:24:37.194228 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10750 01:24:37.194346
10751 01:24:37.214037 <30>[ 16.497580] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10752 01:24:37.223673 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10753 01:24:37.223803
10754 01:24:37.240410 <30>[ 16.524014] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10755 01:24:37.250076 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10756 01:24:37.250212
10757 01:24:37.268355 <30>[ 16.551902] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10758 01:24:37.274574 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10759 01:24:37.274661
10760 01:24:37.292052 <30>[ 16.575993] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10761 01:24:37.302124 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10762 01:24:37.302216
10763 01:24:37.320943 <30>[ 16.604750] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10764 01:24:37.331219 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10765 01:24:37.331323
10766 01:24:37.348169 <30>[ 16.631753] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10767 01:24:37.357898 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10768 01:24:37.358028
10769 01:24:37.399543 <30>[ 16.683405] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10770 01:24:37.406381 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10771 01:24:37.406476
10772 01:24:37.428158 <30>[ 16.711568] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10773 01:24:37.434567 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10774 01:24:37.434671
10775 01:24:37.457869 <30>[ 16.741371] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10776 01:24:37.464148 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10777 01:24:37.464299
10778 01:24:37.490144 <30>[ 16.767601] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10779 01:24:37.503052 <30>[ 16.786605] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10780 01:24:37.513220 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10781 01:24:37.513322
10782 01:24:37.536623 <30>[ 16.820394] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10783 01:24:37.543080 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10784 01:24:37.543171
10785 01:24:37.569045 <30>[ 16.852428] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10786 01:24:37.582074 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel<6>[ 16.865963] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10787 01:24:37.585460 Module dm_mod...
10788 01:24:37.585550
10789 01:24:37.627977 <30>[ 16.911674] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10790 01:24:37.634214 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10791 01:24:37.634341
10792 01:24:37.656961 <30>[ 16.940357] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10793 01:24:37.663532 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10794 01:24:37.666313
10795 01:24:37.689120 <30>[ 16.972527] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10796 01:24:37.695172 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10797 01:24:37.695294
10798 01:24:37.740469 <30>[ 17.023729] systemd[1]: Starting systemd-journald.service - Journal Service...
10799 01:24:37.746539 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10800 01:24:37.746633
10801 01:24:37.766764 <30>[ 17.050411] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10802 01:24:37.773538 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10803 01:24:37.773631
10804 01:24:37.798019 <30>[ 17.078120] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10805 01:24:37.804386 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10806 01:24:37.804502
10807 01:24:37.855827 <30>[ 17.139898] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10808 01:24:37.866247 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10809 01:24:37.866440
10810 01:24:37.887316 <30>[ 17.170770] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10811 01:24:37.896891 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10812 01:24:37.897036
10813 01:24:37.921692 <30>[ 17.205165] systemd[1]: Started systemd-journald.service - Journal Service.
10814 01:24:37.928637 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10815 01:24:37.928732
10816 01:24:37.951349 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10817 01:24:37.951482
10818 01:24:37.968167 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10819 01:24:37.968291
10820 01:24:37.984468 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10821 01:24:37.984591
10822 01:24:38.004851 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10823 01:24:38.005011
10824 01:24:38.024601 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10825 01:24:38.024719
10826 01:24:38.046462 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10827 01:24:38.046588
10828 01:24:38.069938 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10829 01:24:38.070068
10830 01:24:38.093107 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10831 01:24:38.093236
10832 01:24:38.118540 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10833 01:24:38.118672
10834 01:24:38.137912 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10835 01:24:38.138046
10836 01:24:38.157794 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10837 01:24:38.157943
10838 01:24:38.178663 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10839 01:24:38.178794
10840 01:24:38.184634 See 'systemctl status systemd-remount-fs.service' for details.
10841 01:24:38.184718
10842 01:24:38.194510 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10843 01:24:38.194602
10844 01:24:38.214430 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10845 01:24:38.214532
10846 01:24:38.260195 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10847 01:24:38.260312
10848 01:24:38.280309 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10849 01:24:38.280409
10850 01:24:38.299941 Startin<46>[ 17.583601] systemd-journald[190]: Received client request to flush runtime journal.
10851 01:24:38.306132 g [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10852 01:24:38.306222
10853 01:24:38.329356 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10854 01:24:38.329462
10855 01:24:38.351715 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10856 01:24:38.351827
10857 01:24:38.378110 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10858 01:24:38.378238
10859 01:24:38.396759 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10860 01:24:38.396849
10861 01:24:38.416700 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10862 01:24:38.416818
10863 01:24:38.437362 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10864 01:24:38.437482
10865 01:24:38.456607 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10866 01:24:38.456729
10867 01:24:38.512256 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10868 01:24:38.512398
10869 01:24:38.542655 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10870 01:24:38.542758
10871 01:24:38.560481 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10872 01:24:38.560603
10873 01:24:38.579823 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10874 01:24:38.579942
10875 01:24:38.615599 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10876 01:24:38.615708
10877 01:24:38.637027 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10878 01:24:38.637118
10879 01:24:38.659209 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10880 01:24:38.659331
10881 01:24:38.715153 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10882 01:24:38.715267
10883 01:24:38.740841 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10884 01:24:38.741005
10885 01:24:38.764723 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10886 01:24:38.764862
10887 01:24:38.804406 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10888 01:24:38.804558
10889 01:24:38.849499 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10890 01:24:38.849619
10891 01:24:38.887731 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10892 01:24:38.887837
10893 01:24:38.993092 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10894 01:24:38.993257
10895 01:24:39.012967 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10896 01:24:39.013077
10897 01:24:39.032879 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10898 01:24:39.032993
10899 01:24:39.054389 [[0;32m OK [<6>[ 18.338364] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10900 01:24:39.067674 0m] Started [0;1;39mfstrim.time<6>[ 18.348717] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10901 01:24:39.077449 r[0m - Discard <6>[ 18.359403] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10902 01:24:39.084286 unused blocks on<6>[ 18.362405] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10903 01:24:39.087483 ce a week.
10904 01:24:39.087562
10905 01:24:39.094272 <3>[ 18.379515] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10906 01:24:39.104177 <3>[ 18.387863] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10907 01:24:39.110910 <3>[ 18.396335] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10908 01:24:39.116998 <6>[ 18.397470] remoteproc remoteproc0: scp is available
10909 01:24:39.123673 [[0;32m OK [<6>[ 18.410607] remoteproc remoteproc0: powering up scp
10910 01:24:39.134004 0m] Reached targ<3>[ 18.412476] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10911 01:24:39.143633 <6>[ 18.416660] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10912 01:24:39.150540 <4>[ 18.423177] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10913 01:24:39.157422 <3>[ 18.426137] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10914 01:24:39.163573 <6>[ 18.434522] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10915 01:24:39.173331 et [0;1;39mtime<6>[ 18.441247] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10916 01:24:39.180135 <4>[ 18.441301] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10917 01:24:39.186902 <3>[ 18.441782] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10918 01:24:39.197008 rs.target[0m - <4>[ 18.474767] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10919 01:24:39.203787 <4>[ 18.474767] Fallback method does not support PEC.
10920 01:24:39.210207 <3>[ 18.479951] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10921 01:24:39.214162 Timer Units.
10922 01:24:39.214256
10923 01:24:39.217450 <6>[ 18.496001] mc: Linux media interface: v0.10
10924 01:24:39.224369 <3>[ 18.503045] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10925 01:24:39.233988 <3>[ 18.510178] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10926 01:24:39.241096 <6>[ 18.511342] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10927 01:24:39.244281 <6>[ 18.511353] pci_bus 0000:00: root bus resource [bus 00-ff]
10928 01:24:39.251622 <6>[ 18.511359] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10929 01:24:39.261973 <6>[ 18.511362] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10930 01:24:39.268091 <6>[ 18.511412] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10931 01:24:39.275096 <6>[ 18.511429] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10932 01:24:39.281722 <6>[ 18.511508] pci 0000:00:00.0: supports D1 D2
10933 01:24:39.287872 <6>[ 18.511512] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10934 01:24:39.298167 <3>[ 18.511975] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 01:24:39.304609 <6>[ 18.530812] usbcore: registered new device driver r8152-cfgselector
10936 01:24:39.311944 <6>[ 18.536614] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10937 01:24:39.318859 <3>[ 18.540631] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10938 01:24:39.325079 <6>[ 18.549111] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10939 01:24:39.335109 <3>[ 18.554923] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10940 01:24:39.341645 <6>[ 18.561124] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10941 01:24:39.349133 <3>[ 18.568561] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10942 01:24:39.355313 <6>[ 18.573072] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10943 01:24:39.366667 <6>[ 18.574298] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10944 01:24:39.376391 <6>[ 18.576577] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10945 01:24:39.379746 <6>[ 18.576586] remoteproc remoteproc0: remote processor scp is now up
10946 01:24:39.389778 <6>[ 18.576589] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10947 01:24:39.397473 <3>[ 18.579928] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 01:24:39.403827 <3>[ 18.583476] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10949 01:24:39.413982 <3>[ 18.583484] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10950 01:24:39.421119 <3>[ 18.583488] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10951 01:24:39.428123 <3>[ 18.583494] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10952 01:24:39.437724 <3>[ 18.583498] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10953 01:24:39.444346 <3>[ 18.588359] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10954 01:24:39.454261 <6>[ 18.588740] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10955 01:24:39.460838 <6>[ 18.596393] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10956 01:24:39.464078 <6>[ 18.603740] pci 0000:01:00.0: supports D1 D2
10957 01:24:39.474155 <3>[ 18.608986] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 01:24:39.484458 <6>[ 18.613768] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10959 01:24:39.491119 <6>[ 18.617837] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10960 01:24:39.501630 <6>[ 18.620108] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10961 01:24:39.508576 <6>[ 18.627526] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10962 01:24:39.514835 <6>[ 18.633553] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10963 01:24:39.525061 <6>[ 18.633982] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10964 01:24:39.528595 <6>[ 18.650004] videodev: Linux video capture interface: v2.00
10965 01:24:39.539212 <3>[ 18.657514] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 01:24:39.545944 <3>[ 18.658202] power_supply sbs-5-000b: driver failed to report `status' property: -6
10967 01:24:39.552780 <6>[ 18.658323] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10968 01:24:39.563092 <4>[ 18.663200] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10969 01:24:39.573480 <4>[ 18.663207] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10970 01:24:39.576915 <6>[ 18.674012] Bluetooth: Core ver 2.22
10971 01:24:39.583649 <6>[ 18.680310] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10972 01:24:39.590312 <6>[ 18.680333] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10973 01:24:39.600858 <3>[ 18.686434] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10974 01:24:39.607710 <3>[ 18.687270] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
10975 01:24:39.614239 <6>[ 18.689189] NET: Registered PF_BLUETOOTH protocol family
10976 01:24:39.621004 <6>[ 18.697177] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10977 01:24:39.627401 <6>[ 18.705256] Bluetooth: HCI device and connection manager initialized
10978 01:24:39.637519 <3>[ 18.712203] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10979 01:24:39.643948 <6>[ 18.713340] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10980 01:24:39.650599 <6>[ 18.719215] r8152 2-1.3:1.0 eth0: v1.12.13
10981 01:24:39.654128 <6>[ 18.719267] usbcore: registered new interface driver r8152
10982 01:24:39.660338 <6>[ 18.721469] Bluetooth: HCI socket layer initialized
10983 01:24:39.667195 <6>[ 18.729503] pci 0000:00:00.0: PCI bridge to [bus 01]
10984 01:24:39.673811 <6>[ 18.731812] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10985 01:24:39.683527 <6>[ 18.733124] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10986 01:24:39.690512 <6>[ 18.733285] usbcore: registered new interface driver uvcvideo
10987 01:24:39.697427 <6>[ 18.737620] Bluetooth: L2CAP socket layer initialized
10988 01:24:39.703520 <6>[ 18.745056] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10989 01:24:39.710253 <6>[ 18.745572] usbcore: registered new interface driver cdc_ether
10990 01:24:39.716847 <6>[ 18.753371] Bluetooth: SCO socket layer initialized
10991 01:24:39.720077 <6>[ 18.753849] usbcore: registered new interface driver r8153_ecm
10992 01:24:39.727132 <6>[ 18.758111] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10993 01:24:39.733571 <6>[ 18.758582] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10994 01:24:39.740093 <6>[ 18.769274] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10995 01:24:39.746802 <6>[ 18.775785] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10996 01:24:39.756733 <3>[ 18.779300] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10997 01:24:39.763080 <3>[ 18.799778] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10998 01:24:39.770087 <6>[ 18.800444] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10999 01:24:39.776662 <6>[ 18.838875] usbcore: registered new interface driver btusb
11000 01:24:39.786099 <4>[ 18.839557] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11001 01:24:39.793009 <3>[ 18.839573] Bluetooth: hci0: Failed to load firmware file (-2)
11002 01:24:39.799893 <3>[ 18.839580] Bluetooth: hci0: Failed to set up firmware (-2)
11003 01:24:39.809363 <4>[ 18.839586] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11004 01:24:39.816281 <5>[ 18.865796] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11005 01:24:39.826090 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11006 01:24:39.826203
11007 01:24:39.841875 <5>[ 19.125647] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11008 01:24:39.848473 <5>[ 19.132748] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11009 01:24:39.858167 <4>[ 19.141213] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11010 01:24:39.862006 <6>[ 19.150091] cfg80211: failed to load regulatory.db
11011 01:24:39.871300 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11012 01:24:39.871382
11013 01:24:39.904452 <6>[ 19.188305] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11014 01:24:39.911199 <6>[ 19.195811] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11015 01:24:39.924042 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11016 01:24:39.924131
11017 01:24:39.935690 <6>[ 19.222512] mt7921e 0000:01:00.0: ASIC revision: 79610010
11018 01:24:39.941832 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11019 01:24:39.941952
11020 01:24:39.960148 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11021 01:24:39.960236
11022 01:24:39.995247 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11023 01:24:39.995341
11024 01:24:40.012507 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11025 01:24:40.012628
11026 01:24:40.039741 <6>[ 19.323620] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11027 01:24:40.043198 <6>[ 19.323620]
11028 01:24:40.049312 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11029 01:24:40.049401
11030 01:24:40.117899 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11031 01:24:40.118055
11032 01:24:40.139777 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11033 01:24:40.139895
11034 01:24:40.156740 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11035 01:24:40.156862
11036 01:24:40.172801 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11037 01:24:40.172890
11038 01:24:40.192344 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11039 01:24:40.192429
11040 01:24:40.253310 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11041 01:24:40.253448
11042 01:24:40.278436 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11043 01:24:40.278596
11044 01:24:40.301330 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11045 01:24:40.301477
11046 01:24:40.311535 <6>[ 19.593397] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11047 01:24:40.322767 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11048 01:24:40.322879
11049 01:24:40.377163 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11050 01:24:40.377300
11051 01:24:40.416501 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11052 01:24:40.416630
11053 01:24:40.436129 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11054 01:24:40.436222
11055 01:24:40.451742 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11056 01:24:40.451856
11057 01:24:40.471902 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11058 01:24:40.471991
11059 01:24:40.533515 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11060 01:24:40.533684
11061 01:24:40.557017 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11062 01:24:40.557116
11063 01:24:40.580803 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11064 01:24:40.580915
11065 01:24:40.621889 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11066 01:24:40.622038
11067 01:24:40.657271
11068 01:24:40.657395
11069 01:24:40.660537 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11070 01:24:40.660641
11071 01:24:40.663628 debian-bookworm-arm64 login: root (automatic login)
11072 01:24:40.663737
11073 01:24:40.663833
11074 01:24:40.679152 Linux debian-bookworm-arm64 6.1.86-cip19 #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024 aarch64
11075 01:24:40.679243
11076 01:24:40.685315 The programs included with the Debian GNU/Linux system are free software;
11077 01:24:40.692259 the exact distribution terms for each program are described in the
11078 01:24:40.695055 individual files in /usr/share/doc/*/copyright.
11079 01:24:40.695133
11080 01:24:40.701892 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11081 01:24:40.705271 permitted by applicable law.
11082 01:24:40.705894 Matched prompt #10: / #
11084 01:24:40.706202 Setting prompt string to ['/ #']
11085 01:24:40.706330 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11087 01:24:40.706599 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11088 01:24:40.706692 start: 2.2.6 expect-shell-connection (timeout 00:03:27) [common]
11089 01:24:40.706764 Setting prompt string to ['/ #']
11090 01:24:40.706826 Forcing a shell prompt, looking for ['/ #']
11092 01:24:40.757041 / #
11093 01:24:40.757175 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11094 01:24:40.757252 Waiting using forced prompt support (timeout 00:02:30)
11095 01:24:40.762439
11096 01:24:40.762711 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11097 01:24:40.762809 start: 2.2.7 export-device-env (timeout 00:03:27) [common]
11098 01:24:40.762901 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11099 01:24:40.762985 end: 2.2 depthcharge-retry (duration 00:01:33) [common]
11100 01:24:40.763074 end: 2 depthcharge-action (duration 00:01:33) [common]
11101 01:24:40.763167 start: 3 lava-test-retry (timeout 00:08:07) [common]
11102 01:24:40.763253 start: 3.1 lava-test-shell (timeout 00:08:07) [common]
11103 01:24:40.763329 Using namespace: common
11105 01:24:40.863654 / # #
11106 01:24:40.863806 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11107 01:24:40.868902 #
11108 01:24:40.869161 Using /lava-13468761
11110 01:24:40.969506 / # export SHELL=/bin/sh
11111 01:24:40.974318 export SHELL=/bin/sh
11113 01:24:41.074864 / # . /lava-13468761/environment
11114 01:24:41.075049 <6>[ 20.314075] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c787aaa: link becomes ready
11115 01:24:41.075124 <6>[ 20.321670] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
11116 01:24:41.079583 . /lava-13468761/environment
11118 01:24:41.180075 / # /lava-13468761/bin/lava-test-runner /lava-13468761/0
11119 01:24:41.180234 Test shell timeout: 10s (minimum of the action and connection timeout)
11120 01:24:41.180702 /lava-13468761/bin/lava-test-runner /lava-13468761/0<6>[ 20.459401] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11121 01:24:41.184852
11122 01:24:41.230450 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11123 01:24:41.230565 + cd /lava-13468761/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11124 01:24:41.230633 + cat uuid
11125 01:24:41.230697 + UUID=13468761_1.5.2.3.1
11126 01:24:41.230758 + set +x
11127 01:24:41.230817 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 13468761_1.5.2.3.1>
11128 01:24:41.230877 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11129 01:24:41.231117 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 13468761_1.5.2.3.1
11130 01:24:41.231185 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (13468761_1.5.2.3.1)
11131 01:24:41.231266 Skipping test definition patterns.
11132 01:24:41.238933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11133 01:24:41.239214 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11135 01:24:41.242426 device: /dev/video2
11136 01:24:41.249423 <4>[ 20.534102] use of bytesused == 0 is deprecated and will be removed in the future,
11137 01:24:41.252223 <4>[ 20.542304] use the actual size instead.
11138 01:24:41.268374 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11139 01:24:41.296573 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11140 01:24:41.305174
11141 01:24:41.317718 Compliance test for mtk-vcodec-enc device /dev/video2:
11142 01:24:41.322539
11143 01:24:41.332955 Driver Info:
11144 01:24:41.341783 Driver name : mtk-vcodec-enc
11145 01:24:41.356796 Card type : MT8192 video encoder
11146 01:24:41.365658 Bus info : platform:17020000.vcodec
11147 01:24:41.371632 Driver version : 6.1.86
11148 01:24:41.382614 Capabilities : 0x84204000
11149 01:24:41.394246 Video Memory-to-Memory Multiplanar
11150 01:24:41.406798 Streaming
11151 01:24:41.418203 Extended Pix Format
11152 01:24:41.430079 Device Capabilities
11153 01:24:41.440706 Device Caps : 0x04204000
11154 01:24:41.450226 Video Memory-to-Memory Multiplanar
11155 01:24:41.460557 Streaming
11156 01:24:41.470784 Extended Pix Format
11157 01:24:41.482202 Detected Stateful Encoder
11158 01:24:41.493257
11159 01:24:41.503583 Required ioctls:
11160 01:24:41.521760 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11161 01:24:41.521913 test VIDIOC_QUERYCAP: OK
11162 01:24:41.522191 Received signal: <TESTSET> START Required-ioctls
11163 01:24:41.522311 Starting test_set Required-ioctls
11164 01:24:41.544899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11165 01:24:41.545195 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11167 01:24:41.547844 test invalid ioctls: OK
11168 01:24:41.567873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11169 01:24:41.568003
11170 01:24:41.568275 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11172 01:24:41.578414 Allow for multiple opens:
11173 01:24:41.586658 <LAVA_SIGNAL_TESTSET STOP>
11174 01:24:41.586915 Received signal: <TESTSET> STOP
11175 01:24:41.586988 Closing test_set Required-ioctls
11176 01:24:41.597416 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11177 01:24:41.597674 Received signal: <TESTSET> START Allow-for-multiple-opens
11178 01:24:41.597772 Starting test_set Allow-for-multiple-opens
11179 01:24:41.601360 test second /dev/video2 open: OK
11180 01:24:41.621335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11181 01:24:41.621626 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11183 01:24:41.624840 test VIDIOC_QUERYCAP: OK
11184 01:24:41.652273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11185 01:24:41.652550 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11187 01:24:41.655855 test VIDIOC_G/S_PRIORITY: OK
11188 01:24:41.676866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11189 01:24:41.677135 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11191 01:24:41.679992 test for unlimited opens: OK
11192 01:24:41.702535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11193 01:24:41.702632
11194 01:24:41.702872 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11196 01:24:41.714049 Debug ioctls:
11197 01:24:41.721973 <LAVA_SIGNAL_TESTSET STOP>
11198 01:24:41.722256 Received signal: <TESTSET> STOP
11199 01:24:41.722362 Closing test_set Allow-for-multiple-opens
11200 01:24:41.732595 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11201 01:24:41.732856 Received signal: <TESTSET> START Debug-ioctls
11202 01:24:41.732967 Starting test_set Debug-ioctls
11203 01:24:41.735818 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11204 01:24:41.757679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11205 01:24:41.757987 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11207 01:24:41.763994 test VIDIOC_LOG_STATUS: OK (Not Supported)
11208 01:24:41.782465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11209 01:24:41.782569
11210 01:24:41.782810 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11212 01:24:41.794631 Input ioctls:
11213 01:24:41.801587 <LAVA_SIGNAL_TESTSET STOP>
11214 01:24:41.801847 Received signal: <TESTSET> STOP
11215 01:24:41.801918 Closing test_set Debug-ioctls
11216 01:24:41.811117 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11217 01:24:41.811379 Received signal: <TESTSET> START Input-ioctls
11218 01:24:41.811450 Starting test_set Input-ioctls
11219 01:24:41.814430 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11220 01:24:41.844520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11221 01:24:41.844809 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11223 01:24:41.847668 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11224 01:24:41.865594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11225 01:24:41.865868 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11227 01:24:41.872433 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11228 01:24:41.890532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11229 01:24:41.890819 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11231 01:24:41.896598 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11232 01:24:41.916323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11233 01:24:41.916590 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11235 01:24:41.919828 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11236 01:24:41.941886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11237 01:24:41.942144 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11239 01:24:41.945052 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11240 01:24:41.966949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11241 01:24:41.967242 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11243 01:24:41.969658 Inputs: 0 Audio Inputs: 0 Tuners: 0
11244 01:24:41.978405
11245 01:24:41.995857 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11246 01:24:42.016044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11247 01:24:42.016317 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11249 01:24:42.022854 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11250 01:24:42.042354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11251 01:24:42.042627 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11253 01:24:42.048663 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11254 01:24:42.067040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11255 01:24:42.067325 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11257 01:24:42.073303 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11258 01:24:42.092603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11259 01:24:42.092905 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11261 01:24:42.098846 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11262 01:24:42.117396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11263 01:24:42.117501
11264 01:24:42.117742 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11266 01:24:42.136328 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11267 01:24:42.158309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11268 01:24:42.158656 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11270 01:24:42.164643 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11271 01:24:42.185046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11272 01:24:42.185342 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11274 01:24:42.188309 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11275 01:24:42.207821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11276 01:24:42.208111 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11278 01:24:42.211409 test VIDIOC_G/S_EDID: OK (Not Supported)
11279 01:24:42.234173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11280 01:24:42.234262
11281 01:24:42.234511 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11283 01:24:42.246050 Control ioctls:
11284 01:24:42.253550 <LAVA_SIGNAL_TESTSET STOP>
11285 01:24:42.253807 Received signal: <TESTSET> STOP
11286 01:24:42.253878 Closing test_set Input-ioctls
11287 01:24:42.263632 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11288 01:24:42.263889 Received signal: <TESTSET> START Control-ioctls
11289 01:24:42.263963 Starting test_set Control-ioctls
11290 01:24:42.266318 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11291 01:24:42.291615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11292 01:24:42.291744 test VIDIOC_QUERYCTRL: OK
11293 01:24:42.292019 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11295 01:24:42.318283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11296 01:24:42.318549 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11298 01:24:42.321499 test VIDIOC_G/S_CTRL: OK
11299 01:24:42.342008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11300 01:24:42.342315 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11302 01:24:42.345415 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11303 01:24:42.367009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11304 01:24:42.367274 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11306 01:24:42.373303 fail: v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11307 01:24:42.381835 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11308 01:24:42.405275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11309 01:24:42.405536 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11311 01:24:42.408731 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11312 01:24:42.426617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11313 01:24:42.426927 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11315 01:24:42.429913 Standard Controls: 16 Private Controls: 0
11316 01:24:42.438064
11317 01:24:42.450139 Format ioctls:
11318 01:24:42.457381 <LAVA_SIGNAL_TESTSET STOP>
11319 01:24:42.457672 Received signal: <TESTSET> STOP
11320 01:24:42.457752 Closing test_set Control-ioctls
11321 01:24:42.466539 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11322 01:24:42.466793 Received signal: <TESTSET> START Format-ioctls
11323 01:24:42.466862 Starting test_set Format-ioctls
11324 01:24:42.469707 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11325 01:24:42.499281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11326 01:24:42.499549 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11328 01:24:42.502212 test VIDIOC_G/S_PARM: OK
11329 01:24:42.519987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11330 01:24:42.520251 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11332 01:24:42.523245 test VIDIOC_G_FBUF: OK (Not Supported)
11333 01:24:42.545302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11334 01:24:42.545579 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11336 01:24:42.548568 test VIDIOC_G_FMT: OK
11337 01:24:42.570355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11338 01:24:42.570671 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11340 01:24:42.573808 test VIDIOC_TRY_FMT: OK
11341 01:24:42.596191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11342 01:24:42.596500 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11344 01:24:42.602235 fail: v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11345 01:24:42.607144 test VIDIOC_S_FMT: FAIL
11346 01:24:42.633788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11347 01:24:42.634104 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11349 01:24:42.637274 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11350 01:24:42.663083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11351 01:24:42.663361 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11353 01:24:42.666293 test Cropping: OK
11354 01:24:42.690386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11355 01:24:42.690659 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11357 01:24:42.693438 test Composing: OK (Not Supported)
11358 01:24:42.714229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11359 01:24:42.714523 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11361 01:24:42.717878 test Scaling: OK (Not Supported)
11362 01:24:42.744015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11363 01:24:42.744165
11364 01:24:42.744467 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11366 01:24:42.754374 Codec ioctls:
11367 01:24:42.761913 <LAVA_SIGNAL_TESTSET STOP>
11368 01:24:42.762201 Received signal: <TESTSET> STOP
11369 01:24:42.762306 Closing test_set Format-ioctls
11370 01:24:42.770596 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11371 01:24:42.770847 Received signal: <TESTSET> START Codec-ioctls
11372 01:24:42.770914 Starting test_set Codec-ioctls
11373 01:24:42.773954 test VIDIOC_(TRY_)ENCODER_CMD: OK
11374 01:24:42.795261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11375 01:24:42.795530 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11377 01:24:42.801445 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11378 01:24:42.821622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11379 01:24:42.821904 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11381 01:24:42.828412 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11382 01:24:42.845943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11383 01:24:42.846069
11384 01:24:42.846342 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11386 01:24:42.857040 Buffer ioctls:
11387 01:24:42.863774 <LAVA_SIGNAL_TESTSET STOP>
11388 01:24:42.864071 Received signal: <TESTSET> STOP
11389 01:24:42.864142 Closing test_set Codec-ioctls
11390 01:24:42.873918 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11391 01:24:42.874200 Received signal: <TESTSET> START Buffer-ioctls
11392 01:24:42.874293 Starting test_set Buffer-ioctls
11393 01:24:42.877130 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11394 01:24:42.903409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11395 01:24:42.903667 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11397 01:24:42.906669 test CREATE_BUFS maximum buffers: OK
11398 01:24:42.926415 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11400 01:24:42.929270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11401 01:24:42.929346 test VIDIOC_EXPBUF: OK
11402 01:24:42.952478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11403 01:24:42.952747 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11405 01:24:42.955918 test Requests: OK (Not Supported)
11406 01:24:42.976803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11407 01:24:42.976891
11408 01:24:42.977125 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11410 01:24:42.986950 Test input 0:
11411 01:24:42.997208
11412 01:24:43.009391 Streaming ioctls:
11413 01:24:43.016244 <LAVA_SIGNAL_TESTSET STOP>
11414 01:24:43.016502 Received signal: <TESTSET> STOP
11415 01:24:43.016600 Closing test_set Buffer-ioctls
11416 01:24:43.028179 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11417 01:24:43.028477 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11418 01:24:43.028591 Starting test_set Streaming-ioctls_Test-input-0
11419 01:24:43.030936 test read/write: OK (Not Supported)
11420 01:24:43.055381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11421 01:24:43.055641 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11423 01:24:43.061930 fail: v4l2-test-buffers.cpp(2829): node->streamon(q.g_type())
11424 01:24:43.069920 fail: v4l2-test-buffers.cpp(2876): testBlockingDQBuf(node, q)
11425 01:24:43.078170 test blocking wait: FAIL
11426 01:24:43.106200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11427 01:24:43.106473 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11429 01:24:43.112910 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11430 01:24:43.117555 test MMAP (select): FAIL
11431 01:24:43.142025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11432 01:24:43.142296 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11434 01:24:43.149077 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11435 01:24:43.151597 test MMAP (epoll): FAIL
11436 01:24:43.175711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11437 01:24:43.175993 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11439 01:24:43.181934 fail: v4l2-test-buffers.cpp(1633): ret && ret != ENOTTY (got 22)
11440 01:24:43.190000 fail: v4l2-test-buffers.cpp(1764): setupUserPtr(node, q)
11441 01:24:43.198247 test USERPTR (select): FAIL
11442 01:24:43.223372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11443 01:24:43.223632 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11445 01:24:43.229961 test DMABUF: Cannot test, specify --expbuf-device
11446 01:24:43.233951
11447 01:24:43.252106 Total for mtk-vcodec-enc device /dev/video2: 51, Succeeded: 45, Failed: 6, Warnings: 0
11448 01:24:43.255561 <LAVA_TEST_RUNNER EXIT>
11449 01:24:43.255819 ok: lava_test_shell seems to have completed
11450 01:24:43.255896 Marking unfinished test run as failed
11452 01:24:43.256805 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls
Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11453 01:24:43.256929 end: 3.1 lava-test-shell (duration 00:00:02) [common]
11454 01:24:43.257016 end: 3 lava-test-retry (duration 00:00:02) [common]
11455 01:24:43.257108 start: 4 finalize (timeout 00:08:04) [common]
11456 01:24:43.257197 start: 4.1 power-off (timeout 00:00:30) [common]
11457 01:24:43.257350 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11458 01:24:43.332664 >> Command sent successfully.
11459 01:24:43.335667 Returned 0 in 0 seconds
11460 01:24:43.436179 end: 4.1 power-off (duration 00:00:00) [common]
11462 01:24:43.436511 start: 4.2 read-feedback (timeout 00:08:04) [common]
11463 01:24:43.436767 Listened to connection for namespace 'common' for up to 1s
11464 01:24:44.437715 Finalising connection for namespace 'common'
11465 01:24:44.437931 Disconnecting from shell: Finalise
11466 01:24:44.438010 / #
11467 01:24:44.538355 end: 4.2 read-feedback (duration 00:00:01) [common]
11468 01:24:44.538527 end: 4 finalize (duration 00:00:01) [common]
11469 01:24:44.538642 Cleaning after the job
11470 01:24:44.538743 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468761/tftp-deploy-xzv199mm/ramdisk
11471 01:24:44.543200 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468761/tftp-deploy-xzv199mm/kernel
11472 01:24:44.550497 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468761/tftp-deploy-xzv199mm/dtb
11473 01:24:44.550678 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468761/tftp-deploy-xzv199mm/modules
11474 01:24:44.556101 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13468761
11475 01:24:44.619017 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13468761
11476 01:24:44.619177 Job finished correctly