Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 23
- Errors: 1
- Kernel Errors: 35
- Boot result: PASS
1 01:20:58.860958 lava-dispatcher, installed at version: 2024.01
2 01:20:58.861161 start: 0 validate
3 01:20:58.861290 Start time: 2024-04-23 01:20:58.861280+00:00 (UTC)
4 01:20:58.861431 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:20:58.861558 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 01:20:59.121147 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:20:59.121347 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:20:59.375973 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:20:59.376127 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:20:59.629145 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:20:59.629315 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 01:20:59.885955 validate duration: 1.02
14 01:20:59.886237 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:20:59.886334 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:20:59.886420 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:20:59.886537 Not decompressing ramdisk as can be used compressed.
18 01:20:59.886618 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 01:20:59.886680 saving as /var/lib/lava/dispatcher/tmp/13468767/tftp-deploy-31iv6vbn/ramdisk/rootfs.cpio.gz
20 01:20:59.886740 total size: 28105535 (26 MB)
21 01:20:59.892273 progress 0 % (0 MB)
22 01:20:59.899314 progress 5 % (1 MB)
23 01:20:59.906470 progress 10 % (2 MB)
24 01:20:59.913551 progress 15 % (4 MB)
25 01:20:59.920612 progress 20 % (5 MB)
26 01:20:59.927664 progress 25 % (6 MB)
27 01:20:59.934848 progress 30 % (8 MB)
28 01:20:59.942091 progress 35 % (9 MB)
29 01:20:59.949507 progress 40 % (10 MB)
30 01:20:59.956474 progress 45 % (12 MB)
31 01:20:59.963608 progress 50 % (13 MB)
32 01:20:59.970881 progress 55 % (14 MB)
33 01:20:59.978036 progress 60 % (16 MB)
34 01:20:59.985271 progress 65 % (17 MB)
35 01:20:59.992438 progress 70 % (18 MB)
36 01:20:59.999612 progress 75 % (20 MB)
37 01:21:00.006746 progress 80 % (21 MB)
38 01:21:00.013889 progress 85 % (22 MB)
39 01:21:00.020744 progress 90 % (24 MB)
40 01:21:00.027688 progress 95 % (25 MB)
41 01:21:00.034658 progress 100 % (26 MB)
42 01:21:00.034860 26 MB downloaded in 0.15 s (180.96 MB/s)
43 01:21:00.035013 end: 1.1.1 http-download (duration 00:00:00) [common]
45 01:21:00.035253 end: 1.1 download-retry (duration 00:00:00) [common]
46 01:21:00.035339 start: 1.2 download-retry (timeout 00:10:00) [common]
47 01:21:00.035422 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 01:21:00.035556 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 01:21:00.035628 saving as /var/lib/lava/dispatcher/tmp/13468767/tftp-deploy-31iv6vbn/kernel/Image
50 01:21:00.035688 total size: 54352384 (51 MB)
51 01:21:00.035748 No compression specified
52 01:21:00.036871 progress 0 % (0 MB)
53 01:21:00.050411 progress 5 % (2 MB)
54 01:21:00.064052 progress 10 % (5 MB)
55 01:21:00.077660 progress 15 % (7 MB)
56 01:21:00.091336 progress 20 % (10 MB)
57 01:21:00.105431 progress 25 % (12 MB)
58 01:21:00.119202 progress 30 % (15 MB)
59 01:21:00.133263 progress 35 % (18 MB)
60 01:21:00.146896 progress 40 % (20 MB)
61 01:21:00.160888 progress 45 % (23 MB)
62 01:21:00.174543 progress 50 % (25 MB)
63 01:21:00.188296 progress 55 % (28 MB)
64 01:21:00.202019 progress 60 % (31 MB)
65 01:21:00.215698 progress 65 % (33 MB)
66 01:21:00.229498 progress 70 % (36 MB)
67 01:21:00.243167 progress 75 % (38 MB)
68 01:21:00.256551 progress 80 % (41 MB)
69 01:21:00.270159 progress 85 % (44 MB)
70 01:21:00.283734 progress 90 % (46 MB)
71 01:21:00.297347 progress 95 % (49 MB)
72 01:21:00.310708 progress 100 % (51 MB)
73 01:21:00.310923 51 MB downloaded in 0.28 s (188.33 MB/s)
74 01:21:00.311069 end: 1.2.1 http-download (duration 00:00:00) [common]
76 01:21:00.311302 end: 1.2 download-retry (duration 00:00:00) [common]
77 01:21:00.311388 start: 1.3 download-retry (timeout 00:10:00) [common]
78 01:21:00.311475 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 01:21:00.311617 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 01:21:00.311690 saving as /var/lib/lava/dispatcher/tmp/13468767/tftp-deploy-31iv6vbn/dtb/mt8192-asurada-spherion-r0.dtb
81 01:21:00.311751 total size: 47230 (0 MB)
82 01:21:00.311812 No compression specified
83 01:21:00.312952 progress 69 % (0 MB)
84 01:21:00.313221 progress 100 % (0 MB)
85 01:21:00.313374 0 MB downloaded in 0.00 s (27.80 MB/s)
86 01:21:00.313493 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:21:00.313710 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:21:00.313793 start: 1.4 download-retry (timeout 00:10:00) [common]
90 01:21:00.313874 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 01:21:00.313982 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 01:21:00.314048 saving as /var/lib/lava/dispatcher/tmp/13468767/tftp-deploy-31iv6vbn/modules/modules.tar
93 01:21:00.314108 total size: 8638160 (8 MB)
94 01:21:00.314168 Using unxz to decompress xz
95 01:21:00.318063 progress 0 % (0 MB)
96 01:21:00.336982 progress 5 % (0 MB)
97 01:21:00.361282 progress 10 % (0 MB)
98 01:21:00.385111 progress 15 % (1 MB)
99 01:21:00.408324 progress 20 % (1 MB)
100 01:21:00.432388 progress 25 % (2 MB)
101 01:21:00.457455 progress 30 % (2 MB)
102 01:21:00.481235 progress 35 % (2 MB)
103 01:21:00.506346 progress 40 % (3 MB)
104 01:21:00.529735 progress 45 % (3 MB)
105 01:21:00.553954 progress 50 % (4 MB)
106 01:21:00.577964 progress 55 % (4 MB)
107 01:21:00.605787 progress 60 % (4 MB)
108 01:21:00.631016 progress 65 % (5 MB)
109 01:21:00.655561 progress 70 % (5 MB)
110 01:21:00.679272 progress 75 % (6 MB)
111 01:21:00.704103 progress 80 % (6 MB)
112 01:21:00.731670 progress 85 % (7 MB)
113 01:21:00.757735 progress 90 % (7 MB)
114 01:21:00.786419 progress 95 % (7 MB)
115 01:21:00.812882 progress 100 % (8 MB)
116 01:21:00.818686 8 MB downloaded in 0.50 s (16.33 MB/s)
117 01:21:00.818936 end: 1.4.1 http-download (duration 00:00:01) [common]
119 01:21:00.819204 end: 1.4 download-retry (duration 00:00:01) [common]
120 01:21:00.819297 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 01:21:00.819391 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 01:21:00.819472 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:21:00.819562 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 01:21:00.819765 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn
125 01:21:00.819923 makedir: /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/bin
126 01:21:00.820040 makedir: /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/tests
127 01:21:00.820137 makedir: /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/results
128 01:21:00.820251 Creating /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/bin/lava-add-keys
129 01:21:00.820395 Creating /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/bin/lava-add-sources
130 01:21:00.820523 Creating /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/bin/lava-background-process-start
131 01:21:00.820653 Creating /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/bin/lava-background-process-stop
132 01:21:00.820779 Creating /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/bin/lava-common-functions
133 01:21:00.820901 Creating /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/bin/lava-echo-ipv4
134 01:21:00.821025 Creating /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/bin/lava-install-packages
135 01:21:00.821146 Creating /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/bin/lava-installed-packages
136 01:21:00.821267 Creating /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/bin/lava-os-build
137 01:21:00.821389 Creating /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/bin/lava-probe-channel
138 01:21:00.821511 Creating /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/bin/lava-probe-ip
139 01:21:00.821632 Creating /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/bin/lava-target-ip
140 01:21:00.821753 Creating /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/bin/lava-target-mac
141 01:21:00.821875 Creating /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/bin/lava-target-storage
142 01:21:00.822001 Creating /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/bin/lava-test-case
143 01:21:00.822123 Creating /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/bin/lava-test-event
144 01:21:00.822243 Creating /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/bin/lava-test-feedback
145 01:21:00.822364 Creating /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/bin/lava-test-raise
146 01:21:00.822489 Creating /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/bin/lava-test-reference
147 01:21:00.822611 Creating /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/bin/lava-test-runner
148 01:21:00.822752 Creating /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/bin/lava-test-set
149 01:21:00.822894 Creating /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/bin/lava-test-shell
150 01:21:00.823038 Updating /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/bin/lava-install-packages (oe)
151 01:21:00.823205 Updating /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/bin/lava-installed-packages (oe)
152 01:21:00.823342 Creating /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/environment
153 01:21:00.823478 LAVA metadata
154 01:21:00.823588 - LAVA_JOB_ID=13468767
155 01:21:00.823687 - LAVA_DISPATCHER_IP=192.168.201.1
156 01:21:00.823838 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 01:21:00.823976 skipped lava-vland-overlay
158 01:21:00.824093 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 01:21:00.824216 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 01:21:00.824311 skipped lava-multinode-overlay
161 01:21:00.824432 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 01:21:00.824576 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 01:21:00.824689 Loading test definitions
164 01:21:00.824823 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 01:21:00.824936 Using /lava-13468767 at stage 0
166 01:21:00.825264 uuid=13468767_1.5.2.3.1 testdef=None
167 01:21:00.825360 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 01:21:00.825461 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 01:21:00.826153 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 01:21:00.826516 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 01:21:00.827129 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 01:21:00.827388 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 01:21:00.828091 runner path: /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/0/tests/0_v4l2-compliance-uvc test_uuid 13468767_1.5.2.3.1
176 01:21:00.828262 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 01:21:00.828517 Creating lava-test-runner.conf files
179 01:21:00.828617 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13468767/lava-overlay-fdee8apn/lava-13468767/0 for stage 0
180 01:21:00.828799 - 0_v4l2-compliance-uvc
181 01:21:00.828934 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 01:21:00.829056 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 01:21:00.836887 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 01:21:00.837011 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 01:21:00.837113 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 01:21:00.837215 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 01:21:00.837316 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 01:21:01.717756 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 01:21:01.718153 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 01:21:01.718299 extracting modules file /var/lib/lava/dispatcher/tmp/13468767/tftp-deploy-31iv6vbn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13468767/extract-overlay-ramdisk-924v_the/ramdisk
191 01:21:01.934934 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 01:21:01.935119 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 01:21:01.935238 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13468767/compress-overlay-q74pmkva/overlay-1.5.2.4.tar.gz to ramdisk
194 01:21:01.935322 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13468767/compress-overlay-q74pmkva/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13468767/extract-overlay-ramdisk-924v_the/ramdisk
195 01:21:01.942083 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 01:21:01.942210 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 01:21:01.942348 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 01:21:01.942443 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 01:21:01.942522 Building ramdisk /var/lib/lava/dispatcher/tmp/13468767/extract-overlay-ramdisk-924v_the/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13468767/extract-overlay-ramdisk-924v_the/ramdisk
200 01:21:02.644082 >> 276170 blocks
201 01:21:06.703084 rename /var/lib/lava/dispatcher/tmp/13468767/extract-overlay-ramdisk-924v_the/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13468767/tftp-deploy-31iv6vbn/ramdisk/ramdisk.cpio.gz
202 01:21:06.703541 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 01:21:06.703668 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 01:21:06.703774 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 01:21:06.703879 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13468767/tftp-deploy-31iv6vbn/kernel/Image'
206 01:21:20.043949 Returned 0 in 13 seconds
207 01:21:20.144910 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13468767/tftp-deploy-31iv6vbn/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13468767/tftp-deploy-31iv6vbn/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13468767/tftp-deploy-31iv6vbn/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13468767/tftp-deploy-31iv6vbn/kernel/image.itb
208 01:21:20.778346 output: FIT description: Kernel Image image with one or more FDT blobs
209 01:21:20.778715 output: Created: Tue Apr 23 02:21:20 2024
210 01:21:20.778790 output: Image 0 (kernel-1)
211 01:21:20.778852 output: Description:
212 01:21:20.778913 output: Created: Tue Apr 23 02:21:20 2024
213 01:21:20.778969 output: Type: Kernel Image
214 01:21:20.779026 output: Compression: lzma compressed
215 01:21:20.779080 output: Data Size: 12910050 Bytes = 12607.47 KiB = 12.31 MiB
216 01:21:20.779135 output: Architecture: AArch64
217 01:21:20.779190 output: OS: Linux
218 01:21:20.779243 output: Load Address: 0x00000000
219 01:21:20.779298 output: Entry Point: 0x00000000
220 01:21:20.779354 output: Hash algo: crc32
221 01:21:20.779409 output: Hash value: 1126c3f9
222 01:21:20.779464 output: Image 1 (fdt-1)
223 01:21:20.779516 output: Description: mt8192-asurada-spherion-r0
224 01:21:20.779567 output: Created: Tue Apr 23 02:21:20 2024
225 01:21:20.779617 output: Type: Flat Device Tree
226 01:21:20.779667 output: Compression: uncompressed
227 01:21:20.779716 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
228 01:21:20.779767 output: Architecture: AArch64
229 01:21:20.779817 output: Hash algo: crc32
230 01:21:20.779866 output: Hash value: 4bf0d1ac
231 01:21:20.779964 output: Image 2 (ramdisk-1)
232 01:21:20.780014 output: Description: unavailable
233 01:21:20.780064 output: Created: Tue Apr 23 02:21:20 2024
234 01:21:20.780114 output: Type: RAMDisk Image
235 01:21:20.780164 output: Compression: Unknown Compression
236 01:21:20.780214 output: Data Size: 41247649 Bytes = 40280.91 KiB = 39.34 MiB
237 01:21:20.780265 output: Architecture: AArch64
238 01:21:20.780315 output: OS: Linux
239 01:21:20.780364 output: Load Address: unavailable
240 01:21:20.780415 output: Entry Point: unavailable
241 01:21:20.780464 output: Hash algo: crc32
242 01:21:20.780515 output: Hash value: 27150514
243 01:21:20.780565 output: Default Configuration: 'conf-1'
244 01:21:20.780615 output: Configuration 0 (conf-1)
245 01:21:20.780665 output: Description: mt8192-asurada-spherion-r0
246 01:21:20.780715 output: Kernel: kernel-1
247 01:21:20.780764 output: Init Ramdisk: ramdisk-1
248 01:21:20.780814 output: FDT: fdt-1
249 01:21:20.780864 output: Loadables: kernel-1
250 01:21:20.780913 output:
251 01:21:20.781118 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 01:21:20.781211 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 01:21:20.781304 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 01:21:20.781393 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 01:21:20.781470 No LXC device requested
256 01:21:20.781546 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 01:21:20.781634 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 01:21:20.781708 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 01:21:20.781778 Checking files for TFTP limit of 4294967296 bytes.
260 01:21:20.782258 end: 1 tftp-deploy (duration 00:00:21) [common]
261 01:21:20.782359 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 01:21:20.782447 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 01:21:20.782569 substitutions:
264 01:21:20.782635 - {DTB}: 13468767/tftp-deploy-31iv6vbn/dtb/mt8192-asurada-spherion-r0.dtb
265 01:21:20.782698 - {INITRD}: 13468767/tftp-deploy-31iv6vbn/ramdisk/ramdisk.cpio.gz
266 01:21:20.782755 - {KERNEL}: 13468767/tftp-deploy-31iv6vbn/kernel/Image
267 01:21:20.782810 - {LAVA_MAC}: None
268 01:21:20.782863 - {PRESEED_CONFIG}: None
269 01:21:20.782915 - {PRESEED_LOCAL}: None
270 01:21:20.782967 - {RAMDISK}: 13468767/tftp-deploy-31iv6vbn/ramdisk/ramdisk.cpio.gz
271 01:21:20.783019 - {ROOT_PART}: None
272 01:21:20.783071 - {ROOT}: None
273 01:21:20.783125 - {SERVER_IP}: 192.168.201.1
274 01:21:20.783176 - {TEE}: None
275 01:21:20.783229 Parsed boot commands:
276 01:21:20.783281 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 01:21:20.783447 Parsed boot commands: tftpboot 192.168.201.1 13468767/tftp-deploy-31iv6vbn/kernel/image.itb 13468767/tftp-deploy-31iv6vbn/kernel/cmdline
278 01:21:20.783533 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 01:21:20.783614 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 01:21:20.783704 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 01:21:20.783786 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 01:21:20.783853 Not connected, no need to disconnect.
283 01:21:20.783971 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 01:21:20.784050 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 01:21:20.784116 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
286 01:21:20.787775 Setting prompt string to ['lava-test: # ']
287 01:21:20.788165 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 01:21:20.788273 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 01:21:20.788366 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 01:21:20.788452 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 01:21:20.788669 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
292 01:21:25.941137 >> Command sent successfully.
293 01:21:25.944266 Returned 0 in 5 seconds
294 01:21:26.044979 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 01:21:26.046383 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 01:21:26.047054 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 01:21:26.047636 Setting prompt string to 'Starting depthcharge on Spherion...'
299 01:21:26.048117 Changing prompt to 'Starting depthcharge on Spherion...'
300 01:21:26.048475 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 01:21:26.049685 [Enter `^Ec?' for help]
302 01:21:26.218564
303 01:21:26.219117
304 01:21:26.219523 F0: 102B 0000
305 01:21:26.219963
306 01:21:26.220317 F3: 1001 0000 [0200]
307 01:21:26.220695
308 01:21:26.221661 F3: 1001 0000
309 01:21:26.222403
310 01:21:26.222912 F7: 102D 0000
311 01:21:26.223273
312 01:21:26.224860 F1: 0000 0000
313 01:21:26.225288
314 01:21:26.225639 V0: 0000 0000 [0001]
315 01:21:26.225969
316 01:21:26.228565 00: 0007 8000
317 01:21:26.229055
318 01:21:26.229395 01: 0000 0000
319 01:21:26.229718
320 01:21:26.231326 BP: 0C00 0209 [0000]
321 01:21:26.231819
322 01:21:26.232536 G0: 1182 0000
323 01:21:26.233011
324 01:21:26.233342 EC: 0000 0021 [4000]
325 01:21:26.235336
326 01:21:26.235852 S7: 0000 0000 [0000]
327 01:21:26.236495
328 01:21:26.239093 CC: 0000 0000 [0001]
329 01:21:26.239481
330 01:21:26.239803 T0: 0000 0040 [010F]
331 01:21:26.240167
332 01:21:26.240472 Jump to BL
333 01:21:26.240821
334 01:21:26.265332
335 01:21:26.266025
336 01:21:26.266663
337 01:21:26.272293 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 01:21:26.275420 ARM64: Exception handlers installed.
339 01:21:26.279274 ARM64: Testing exception
340 01:21:26.282426 ARM64: Done test exception
341 01:21:26.289183 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 01:21:26.299449 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 01:21:26.306003 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 01:21:26.315769 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 01:21:26.322508 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 01:21:26.332728 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 01:21:26.343554 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 01:21:26.350100 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 01:21:26.367951 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 01:21:26.371821 WDT: Last reset was cold boot
351 01:21:26.374482 SPI1(PAD0) initialized at 2873684 Hz
352 01:21:26.378149 SPI5(PAD0) initialized at 992727 Hz
353 01:21:26.381258 VBOOT: Loading verstage.
354 01:21:26.388155 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 01:21:26.391440 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 01:21:26.394685 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 01:21:26.397723 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 01:21:26.405836 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 01:21:26.412156 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 01:21:26.423396 read SPI 0x96554 0xa1eb: 4593 us, 9024 KB/s, 72.192 Mbps
361 01:21:26.423926
362 01:21:26.424269
363 01:21:26.433336 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 01:21:26.436344 ARM64: Exception handlers installed.
365 01:21:26.439289 ARM64: Testing exception
366 01:21:26.439713 ARM64: Done test exception
367 01:21:26.446850 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 01:21:26.450508 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 01:21:26.463804 Probing TPM: . done!
370 01:21:26.464392 TPM ready after 0 ms
371 01:21:26.471255 Connected to device vid:did:rid of 1ae0:0028:00
372 01:21:26.477861 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
373 01:21:26.536824 Initialized TPM device CR50 revision 0
374 01:21:26.549078 tlcl_send_startup: Startup return code is 0
375 01:21:26.549511 TPM: setup succeeded
376 01:21:26.560465 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 01:21:26.569302 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 01:21:26.581282 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 01:21:26.591725 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 01:21:26.594835 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 01:21:26.599234 in-header: 03 07 00 00 08 00 00 00
382 01:21:26.602738 in-data: aa e4 47 04 13 02 00 00
383 01:21:26.606364 Chrome EC: UHEPI supported
384 01:21:26.613626 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 01:21:26.617208 in-header: 03 95 00 00 08 00 00 00
386 01:21:26.620821 in-data: 18 20 20 08 00 00 00 00
387 01:21:26.621251 Phase 1
388 01:21:26.624550 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 01:21:26.632061 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 01:21:26.635880 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 01:21:26.639423 Recovery requested (1009000e)
392 01:21:26.647750 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 01:21:26.652878 tlcl_extend: response is 0
394 01:21:26.662299 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 01:21:26.667827 tlcl_extend: response is 0
396 01:21:26.675183 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 01:21:26.694800 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
398 01:21:26.701276 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 01:21:26.701798
400 01:21:26.702140
401 01:21:26.711840 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 01:21:26.714941 ARM64: Exception handlers installed.
403 01:21:26.717565 ARM64: Testing exception
404 01:21:26.717995 ARM64: Done test exception
405 01:21:26.740388 pmic_efuse_setting: Set efuses in 11 msecs
406 01:21:26.743865 pmwrap_interface_init: Select PMIF_VLD_RDY
407 01:21:26.750163 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 01:21:26.754031 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 01:21:26.760037 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 01:21:26.764280 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 01:21:26.767880 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 01:21:26.775270 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 01:21:26.779079 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 01:21:26.782239 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 01:21:26.786078 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 01:21:26.793439 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 01:21:26.796966 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 01:21:26.800536 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 01:21:26.807709 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 01:21:26.811333 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 01:21:26.819312 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 01:21:26.823338 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 01:21:26.830170 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 01:21:26.833813 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 01:21:26.841206 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 01:21:26.848515 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 01:21:26.852131 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 01:21:26.859308 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 01:21:26.862868 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 01:21:26.870646 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 01:21:26.873846 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 01:21:26.881279 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 01:21:26.884431 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 01:21:26.888513 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 01:21:26.895628 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 01:21:26.899266 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 01:21:26.902931 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 01:21:26.910247 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 01:21:26.913861 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 01:21:26.920705 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 01:21:26.924706 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 01:21:26.928018 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 01:21:26.935391 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 01:21:26.939138 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 01:21:26.942162 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 01:21:26.949954 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 01:21:26.953382 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 01:21:26.957038 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 01:21:26.960394 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 01:21:26.964352 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 01:21:26.971683 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 01:21:26.975518 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 01:21:26.979301 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 01:21:26.982368 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 01:21:26.986330 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 01:21:26.989670 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 01:21:26.993448 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 01:21:27.004499 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 01:21:27.011605 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 01:21:27.015552 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 01:21:27.025917 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 01:21:27.033978 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 01:21:27.037533 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 01:21:27.041144 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 01:21:27.044342 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 01:21:27.053644 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x6
467 01:21:27.057187 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 01:21:27.062115 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
469 01:21:27.068843 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 01:21:27.078141 [RTC]rtc_get_frequency_meter,154: input=15, output=851
471 01:21:27.086804 [RTC]rtc_get_frequency_meter,154: input=7, output=724
472 01:21:27.096598 [RTC]rtc_get_frequency_meter,154: input=11, output=788
473 01:21:27.106250 [RTC]rtc_get_frequency_meter,154: input=13, output=821
474 01:21:27.115879 [RTC]rtc_get_frequency_meter,154: input=12, output=804
475 01:21:27.125250 [RTC]rtc_get_frequency_meter,154: input=11, output=788
476 01:21:27.135411 [RTC]rtc_get_frequency_meter,154: input=12, output=804
477 01:21:27.139377 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
478 01:21:27.142992 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
479 01:21:27.146689 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 01:21:27.154271 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 01:21:27.157542 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 01:21:27.161484 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 01:21:27.165065 ADC[4]: Raw value=904433 ID=7
484 01:21:27.165497 ADC[3]: Raw value=213546 ID=1
485 01:21:27.168507 RAM Code: 0x71
486 01:21:27.172645 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 01:21:27.176426 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 01:21:27.186809 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 01:21:27.190682 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 01:21:27.193901 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 01:21:27.198693 in-header: 03 07 00 00 08 00 00 00
492 01:21:27.202003 in-data: aa e4 47 04 13 02 00 00
493 01:21:27.206044 Chrome EC: UHEPI supported
494 01:21:27.213054 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 01:21:27.216874 in-header: 03 95 00 00 08 00 00 00
496 01:21:27.220856 in-data: 18 20 20 08 00 00 00 00
497 01:21:27.224333 MRC: failed to locate region type 0.
498 01:21:27.227688 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 01:21:27.231419 DRAM-K: Running full calibration
500 01:21:27.239267 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 01:21:27.239795 header.status = 0x0
502 01:21:27.242657 header.version = 0x6 (expected: 0x6)
503 01:21:27.246401 header.size = 0xd00 (expected: 0xd00)
504 01:21:27.250025 header.flags = 0x0
505 01:21:27.253740 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 01:21:27.273532 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
507 01:21:27.280836 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 01:21:27.284647 dram_init: ddr_geometry: 2
509 01:21:27.285075 [EMI] MDL number = 2
510 01:21:27.287840 [EMI] Get MDL freq = 0
511 01:21:27.288316 dram_init: ddr_type: 0
512 01:21:27.291605 is_discrete_lpddr4: 1
513 01:21:27.295647 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 01:21:27.296170
515 01:21:27.296516
516 01:21:27.296833 [Bian_co] ETT version 0.0.0.1
517 01:21:27.302938 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 01:21:27.303367
519 01:21:27.306465 dramc_set_vcore_voltage set vcore to 650000
520 01:21:27.306895 Read voltage for 800, 4
521 01:21:27.310269 Vio18 = 0
522 01:21:27.310785 Vcore = 650000
523 01:21:27.311130 Vdram = 0
524 01:21:27.311447 Vddq = 0
525 01:21:27.313997 Vmddr = 0
526 01:21:27.314537 dram_init: config_dvfs: 1
527 01:21:27.320957 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 01:21:27.324640 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 01:21:27.327708 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 01:21:27.334214 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 01:21:27.338215 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 01:21:27.342089 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 01:21:27.342619 MEM_TYPE=3, freq_sel=18
534 01:21:27.345213 sv_algorithm_assistance_LP4_1600
535 01:21:27.349359 ============ PULL DRAM RESETB DOWN ============
536 01:21:27.352556 ========== PULL DRAM RESETB DOWN end =========
537 01:21:27.359705 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 01:21:27.362916 ===================================
539 01:21:27.363352 LPDDR4 DRAM CONFIGURATION
540 01:21:27.366605 ===================================
541 01:21:27.369674 EX_ROW_EN[0] = 0x0
542 01:21:27.373035 EX_ROW_EN[1] = 0x0
543 01:21:27.373465 LP4Y_EN = 0x0
544 01:21:27.376600 WORK_FSP = 0x0
545 01:21:27.377031 WL = 0x2
546 01:21:27.379689 RL = 0x2
547 01:21:27.380167 BL = 0x2
548 01:21:27.383459 RPST = 0x0
549 01:21:27.383920 RD_PRE = 0x0
550 01:21:27.386534 WR_PRE = 0x1
551 01:21:27.386960 WR_PST = 0x0
552 01:21:27.390092 DBI_WR = 0x0
553 01:21:27.390602 DBI_RD = 0x0
554 01:21:27.393162 OTF = 0x1
555 01:21:27.396782 ===================================
556 01:21:27.400364 ===================================
557 01:21:27.400879 ANA top config
558 01:21:27.403108 ===================================
559 01:21:27.406269 DLL_ASYNC_EN = 0
560 01:21:27.409724 ALL_SLAVE_EN = 1
561 01:21:27.412777 NEW_RANK_MODE = 1
562 01:21:27.413387 DLL_IDLE_MODE = 1
563 01:21:27.416400 LP45_APHY_COMB_EN = 1
564 01:21:27.419325 TX_ODT_DIS = 1
565 01:21:27.423039 NEW_8X_MODE = 1
566 01:21:27.425898 ===================================
567 01:21:27.429158 ===================================
568 01:21:27.432579 data_rate = 1600
569 01:21:27.433007 CKR = 1
570 01:21:27.436068 DQ_P2S_RATIO = 8
571 01:21:27.439169 ===================================
572 01:21:27.442887 CA_P2S_RATIO = 8
573 01:21:27.446738 DQ_CA_OPEN = 0
574 01:21:27.447302 DQ_SEMI_OPEN = 0
575 01:21:27.450386 CA_SEMI_OPEN = 0
576 01:21:27.453158 CA_FULL_RATE = 0
577 01:21:27.456972 DQ_CKDIV4_EN = 1
578 01:21:27.459747 CA_CKDIV4_EN = 1
579 01:21:27.463419 CA_PREDIV_EN = 0
580 01:21:27.463847 PH8_DLY = 0
581 01:21:27.466684 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 01:21:27.469830 DQ_AAMCK_DIV = 4
583 01:21:27.472946 CA_AAMCK_DIV = 4
584 01:21:27.476195 CA_ADMCK_DIV = 4
585 01:21:27.479956 DQ_TRACK_CA_EN = 0
586 01:21:27.480478 CA_PICK = 800
587 01:21:27.483325 CA_MCKIO = 800
588 01:21:27.486400 MCKIO_SEMI = 0
589 01:21:27.490347 PLL_FREQ = 3068
590 01:21:27.494226 DQ_UI_PI_RATIO = 32
591 01:21:27.497482 CA_UI_PI_RATIO = 0
592 01:21:27.497916 ===================================
593 01:21:27.501468 ===================================
594 01:21:27.504997 memory_type:LPDDR4
595 01:21:27.508689 GP_NUM : 10
596 01:21:27.509232 SRAM_EN : 1
597 01:21:27.512127 MD32_EN : 0
598 01:21:27.515573 ===================================
599 01:21:27.516054 [ANA_INIT] >>>>>>>>>>>>>>
600 01:21:27.519640 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 01:21:27.523441 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 01:21:27.526154 ===================================
603 01:21:27.530211 data_rate = 1600,PCW = 0X7600
604 01:21:27.533228 ===================================
605 01:21:27.536423 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 01:21:27.539692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 01:21:27.546689 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 01:21:27.552749 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 01:21:27.555837 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 01:21:27.559488 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 01:21:27.560060 [ANA_INIT] flow start
612 01:21:27.563342 [ANA_INIT] PLL >>>>>>>>
613 01:21:27.565756 [ANA_INIT] PLL <<<<<<<<
614 01:21:27.566190 [ANA_INIT] MIDPI >>>>>>>>
615 01:21:27.569377 [ANA_INIT] MIDPI <<<<<<<<
616 01:21:27.572990 [ANA_INIT] DLL >>>>>>>>
617 01:21:27.573427 [ANA_INIT] flow end
618 01:21:27.579412 ============ LP4 DIFF to SE enter ============
619 01:21:27.582667 ============ LP4 DIFF to SE exit ============
620 01:21:27.583109 [ANA_INIT] <<<<<<<<<<<<<
621 01:21:27.586056 [Flow] Enable top DCM control >>>>>
622 01:21:27.589015 [Flow] Enable top DCM control <<<<<
623 01:21:27.592637 Enable DLL master slave shuffle
624 01:21:27.599201 ==============================================================
625 01:21:27.602421 Gating Mode config
626 01:21:27.605657 ==============================================================
627 01:21:27.609402 Config description:
628 01:21:27.619126 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 01:21:27.625768 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 01:21:27.629008 SELPH_MODE 0: By rank 1: By Phase
631 01:21:27.635300 ==============================================================
632 01:21:27.638810 GAT_TRACK_EN = 1
633 01:21:27.641793 RX_GATING_MODE = 2
634 01:21:27.645938 RX_GATING_TRACK_MODE = 2
635 01:21:27.646462 SELPH_MODE = 1
636 01:21:27.648608 PICG_EARLY_EN = 1
637 01:21:27.652151 VALID_LAT_VALUE = 1
638 01:21:27.659500 ==============================================================
639 01:21:27.662343 Enter into Gating configuration >>>>
640 01:21:27.665511 Exit from Gating configuration <<<<
641 01:21:27.669080 Enter into DVFS_PRE_config >>>>>
642 01:21:27.679095 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 01:21:27.682235 Exit from DVFS_PRE_config <<<<<
644 01:21:27.685645 Enter into PICG configuration >>>>
645 01:21:27.689165 Exit from PICG configuration <<<<
646 01:21:27.691773 [RX_INPUT] configuration >>>>>
647 01:21:27.695318 [RX_INPUT] configuration <<<<<
648 01:21:27.698649 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 01:21:27.705296 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 01:21:27.711683 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 01:21:27.718496 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 01:21:27.725384 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 01:21:27.728561 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 01:21:27.734655 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 01:21:27.738010 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 01:21:27.742359 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 01:21:27.744707 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 01:21:27.751480 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 01:21:27.755234 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 01:21:27.758333 ===================================
661 01:21:27.761206 LPDDR4 DRAM CONFIGURATION
662 01:21:27.764518 ===================================
663 01:21:27.764947 EX_ROW_EN[0] = 0x0
664 01:21:27.768428 EX_ROW_EN[1] = 0x0
665 01:21:27.768950 LP4Y_EN = 0x0
666 01:21:27.771850 WORK_FSP = 0x0
667 01:21:27.772418 WL = 0x2
668 01:21:27.775075 RL = 0x2
669 01:21:27.775646 BL = 0x2
670 01:21:27.778166 RPST = 0x0
671 01:21:27.778741 RD_PRE = 0x0
672 01:21:27.781471 WR_PRE = 0x1
673 01:21:27.781902 WR_PST = 0x0
674 01:21:27.785186 DBI_WR = 0x0
675 01:21:27.788506 DBI_RD = 0x0
676 01:21:27.789033 OTF = 0x1
677 01:21:27.791015 ===================================
678 01:21:27.795544 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 01:21:27.798528 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 01:21:27.804942 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 01:21:27.807956 ===================================
682 01:21:27.811216 LPDDR4 DRAM CONFIGURATION
683 01:21:27.814420 ===================================
684 01:21:27.814942 EX_ROW_EN[0] = 0x10
685 01:21:27.817853 EX_ROW_EN[1] = 0x0
686 01:21:27.818281 LP4Y_EN = 0x0
687 01:21:27.821363 WORK_FSP = 0x0
688 01:21:27.821839 WL = 0x2
689 01:21:27.824402 RL = 0x2
690 01:21:27.824830 BL = 0x2
691 01:21:27.827991 RPST = 0x0
692 01:21:27.828528 RD_PRE = 0x0
693 01:21:27.830878 WR_PRE = 0x1
694 01:21:27.831306 WR_PST = 0x0
695 01:21:27.834432 DBI_WR = 0x0
696 01:21:27.837839 DBI_RD = 0x0
697 01:21:27.838383 OTF = 0x1
698 01:21:27.841108 ===================================
699 01:21:27.848017 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 01:21:27.851262 nWR fixed to 40
701 01:21:27.854881 [ModeRegInit_LP4] CH0 RK0
702 01:21:27.855413 [ModeRegInit_LP4] CH0 RK1
703 01:21:27.857635 [ModeRegInit_LP4] CH1 RK0
704 01:21:27.860921 [ModeRegInit_LP4] CH1 RK1
705 01:21:27.861391 match AC timing 13
706 01:21:27.867991 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 01:21:27.871173 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 01:21:27.874651 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 01:21:27.881189 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 01:21:27.884305 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 01:21:27.887543 [EMI DOE] emi_dcm 0
712 01:21:27.891106 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 01:21:27.891633 ==
714 01:21:27.894555 Dram Type= 6, Freq= 0, CH_0, rank 0
715 01:21:27.897632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 01:21:27.898066 ==
717 01:21:27.904221 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 01:21:27.910258 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 01:21:27.918745 [CA 0] Center 37 (7~68) winsize 62
720 01:21:27.921511 [CA 1] Center 37 (6~68) winsize 63
721 01:21:27.924819 [CA 2] Center 34 (4~65) winsize 62
722 01:21:27.928249 [CA 3] Center 35 (4~66) winsize 63
723 01:21:27.931304 [CA 4] Center 33 (3~64) winsize 62
724 01:21:27.934795 [CA 5] Center 33 (3~64) winsize 62
725 01:21:27.935027
726 01:21:27.937919 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 01:21:27.938106
728 01:21:27.941257 [CATrainingPosCal] consider 1 rank data
729 01:21:27.944901 u2DelayCellTimex100 = 270/100 ps
730 01:21:27.947713 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 01:21:27.954928 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 01:21:27.957475 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 01:21:27.961092 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
734 01:21:27.964368 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 01:21:27.967558 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 01:21:27.967653
737 01:21:27.971075 CA PerBit enable=1, Macro0, CA PI delay=33
738 01:21:27.971169
739 01:21:27.974378 [CBTSetCACLKResult] CA Dly = 33
740 01:21:27.977661 CS Dly: 5 (0~36)
741 01:21:27.977764 ==
742 01:21:27.981086 Dram Type= 6, Freq= 0, CH_0, rank 1
743 01:21:27.984376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 01:21:27.984471 ==
745 01:21:27.991238 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 01:21:27.994359 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 01:21:28.004486 [CA 0] Center 38 (7~69) winsize 63
748 01:21:28.008010 [CA 1] Center 37 (7~68) winsize 62
749 01:21:28.011666 [CA 2] Center 35 (5~66) winsize 62
750 01:21:28.015480 [CA 3] Center 35 (4~66) winsize 63
751 01:21:28.018432 [CA 4] Center 34 (3~65) winsize 63
752 01:21:28.021926 [CA 5] Center 33 (3~64) winsize 62
753 01:21:28.022173
754 01:21:28.024714 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 01:21:28.024919
756 01:21:28.028118 [CATrainingPosCal] consider 2 rank data
757 01:21:28.031689 u2DelayCellTimex100 = 270/100 ps
758 01:21:28.034805 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 01:21:28.038739 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 01:21:28.044871 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
761 01:21:28.048159 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
762 01:21:28.051493 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 01:21:28.055115 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 01:21:28.055642
765 01:21:28.058280 CA PerBit enable=1, Macro0, CA PI delay=33
766 01:21:28.058813
767 01:21:28.061431 [CBTSetCACLKResult] CA Dly = 33
768 01:21:28.061862 CS Dly: 6 (0~38)
769 01:21:28.064423
770 01:21:28.068771 ----->DramcWriteLeveling(PI) begin...
771 01:21:28.069320 ==
772 01:21:28.069667 Dram Type= 6, Freq= 0, CH_0, rank 0
773 01:21:28.075588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 01:21:28.076085 ==
775 01:21:28.079207 Write leveling (Byte 0): 31 => 31
776 01:21:28.079634 Write leveling (Byte 1): 25 => 25
777 01:21:28.082499 DramcWriteLeveling(PI) end<-----
778 01:21:28.082927
779 01:21:28.083266 ==
780 01:21:28.086467 Dram Type= 6, Freq= 0, CH_0, rank 0
781 01:21:28.092573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 01:21:28.093118 ==
783 01:21:28.093480 [Gating] SW mode calibration
784 01:21:28.099652 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 01:21:28.106589 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 01:21:28.109947 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 01:21:28.116549 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 01:21:28.119929 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
789 01:21:28.123197 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 01:21:28.129584 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 01:21:28.133087 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 01:21:28.136012 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 01:21:28.142606 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 01:21:28.146395 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 01:21:28.149425 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 01:21:28.156347 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 01:21:28.159262 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 01:21:28.162707 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 01:21:28.169263 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 01:21:28.172477 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 01:21:28.175927 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 01:21:28.182581 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 01:21:28.186126 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 01:21:28.189619 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 01:21:28.195717 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
806 01:21:28.198975 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 01:21:28.202147 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 01:21:28.208992 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 01:21:28.212388 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 01:21:28.216092 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 01:21:28.222566 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 01:21:28.225579 0 9 8 | B1->B0 | 2323 3030 | 1 0 | (1 1) (0 0)
813 01:21:28.228637 0 9 12 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
814 01:21:28.235266 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 01:21:28.238732 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 01:21:28.241930 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 01:21:28.245188 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 01:21:28.251834 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 01:21:28.255179 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
820 01:21:28.258715 0 10 8 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
821 01:21:28.265409 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
822 01:21:28.268608 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 01:21:28.272067 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 01:21:28.279134 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 01:21:28.281626 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 01:21:28.285323 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 01:21:28.291868 0 11 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
828 01:21:28.295082 0 11 8 | B1->B0 | 2929 4444 | 0 0 | (0 0) (0 0)
829 01:21:28.298315 0 11 12 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
830 01:21:28.305131 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 01:21:28.308572 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 01:21:28.311843 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 01:21:28.318595 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 01:21:28.321785 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 01:21:28.325204 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 01:21:28.331583 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 01:21:28.334668 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 01:21:28.338126 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 01:21:28.344590 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 01:21:28.348213 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 01:21:28.351801 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 01:21:28.358179 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 01:21:28.361384 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 01:21:28.364773 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 01:21:28.371305 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 01:21:28.374568 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 01:21:28.378145 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 01:21:28.384946 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 01:21:28.388231 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 01:21:28.391589 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 01:21:28.394840 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
852 01:21:28.401571 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 01:21:28.405004 Total UI for P1: 0, mck2ui 16
854 01:21:28.407951 best dqsien dly found for B0: ( 0, 14, 4)
855 01:21:28.411151 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
856 01:21:28.415319 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 01:21:28.417796 Total UI for P1: 0, mck2ui 16
858 01:21:28.421398 best dqsien dly found for B1: ( 0, 14, 8)
859 01:21:28.425069 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
860 01:21:28.428293 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
861 01:21:28.428723
862 01:21:28.434719 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
863 01:21:28.438068 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
864 01:21:28.441410 [Gating] SW calibration Done
865 01:21:28.441838 ==
866 01:21:28.445092 Dram Type= 6, Freq= 0, CH_0, rank 0
867 01:21:28.449127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 01:21:28.449555 ==
869 01:21:28.449892 RX Vref Scan: 0
870 01:21:28.450208
871 01:21:28.451629 RX Vref 0 -> 0, step: 1
872 01:21:28.452088
873 01:21:28.455373 RX Delay -130 -> 252, step: 16
874 01:21:28.458149 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
875 01:21:28.461606 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
876 01:21:28.465274 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 01:21:28.471835 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 01:21:28.474849 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
879 01:21:28.478320 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
880 01:21:28.481687 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
881 01:21:28.485435 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
882 01:21:28.491373 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
883 01:21:28.495019 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
884 01:21:28.498272 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
885 01:21:28.501893 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
886 01:21:28.504613 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
887 01:21:28.511204 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
888 01:21:28.514680 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
889 01:21:28.517977 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
890 01:21:28.518405 ==
891 01:21:28.521393 Dram Type= 6, Freq= 0, CH_0, rank 0
892 01:21:28.525032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 01:21:28.528166 ==
894 01:21:28.528598 DQS Delay:
895 01:21:28.528940 DQS0 = 0, DQS1 = 0
896 01:21:28.531424 DQM Delay:
897 01:21:28.531845 DQM0 = 88, DQM1 = 76
898 01:21:28.534647 DQ Delay:
899 01:21:28.535112 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
900 01:21:28.537821 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
901 01:21:28.541440 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
902 01:21:28.544467 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
903 01:21:28.547987
904 01:21:28.548433
905 01:21:28.548875 ==
906 01:21:28.551331 Dram Type= 6, Freq= 0, CH_0, rank 0
907 01:21:28.554863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 01:21:28.555366 ==
909 01:21:28.555943
910 01:21:28.556295
911 01:21:28.558226 TX Vref Scan disable
912 01:21:28.558656 == TX Byte 0 ==
913 01:21:28.564698 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
914 01:21:28.568327 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
915 01:21:28.568757 == TX Byte 1 ==
916 01:21:28.574569 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
917 01:21:28.577872 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
918 01:21:28.578301 ==
919 01:21:28.581090 Dram Type= 6, Freq= 0, CH_0, rank 0
920 01:21:28.584649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 01:21:28.585081 ==
922 01:21:28.599124 TX Vref=22, minBit 0, minWin=27, winSum=438
923 01:21:28.601861 TX Vref=24, minBit 1, minWin=27, winSum=443
924 01:21:28.605224 TX Vref=26, minBit 1, minWin=27, winSum=446
925 01:21:28.608619 TX Vref=28, minBit 2, minWin=27, winSum=450
926 01:21:28.612173 TX Vref=30, minBit 1, minWin=27, winSum=450
927 01:21:28.618760 TX Vref=32, minBit 1, minWin=27, winSum=448
928 01:21:28.621789 [TxChooseVref] Worse bit 2, Min win 27, Win sum 450, Final Vref 28
929 01:21:28.622234
930 01:21:28.625007 Final TX Range 1 Vref 28
931 01:21:28.625484
932 01:21:28.625914 ==
933 01:21:28.628684 Dram Type= 6, Freq= 0, CH_0, rank 0
934 01:21:28.631811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 01:21:28.632330 ==
936 01:21:28.635209
937 01:21:28.635633
938 01:21:28.636016 TX Vref Scan disable
939 01:21:28.638502 == TX Byte 0 ==
940 01:21:28.642504 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
941 01:21:28.648979 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
942 01:21:28.649424 == TX Byte 1 ==
943 01:21:28.652115 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
944 01:21:28.658771 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
945 01:21:28.659195
946 01:21:28.659530 [DATLAT]
947 01:21:28.660016 Freq=800, CH0 RK0
948 01:21:28.660503
949 01:21:28.661981 DATLAT Default: 0xa
950 01:21:28.662404 0, 0xFFFF, sum = 0
951 01:21:28.665291 1, 0xFFFF, sum = 0
952 01:21:28.668239 2, 0xFFFF, sum = 0
953 01:21:28.668748 3, 0xFFFF, sum = 0
954 01:21:28.671825 4, 0xFFFF, sum = 0
955 01:21:28.672300 5, 0xFFFF, sum = 0
956 01:21:28.674940 6, 0xFFFF, sum = 0
957 01:21:28.675370 7, 0xFFFF, sum = 0
958 01:21:28.678533 8, 0xFFFF, sum = 0
959 01:21:28.678965 9, 0x0, sum = 1
960 01:21:28.681961 10, 0x0, sum = 2
961 01:21:28.682484 11, 0x0, sum = 3
962 01:21:28.685225 12, 0x0, sum = 4
963 01:21:28.685670 best_step = 10
964 01:21:28.686112
965 01:21:28.686526 ==
966 01:21:28.688783 Dram Type= 6, Freq= 0, CH_0, rank 0
967 01:21:28.691437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 01:21:28.691879 ==
969 01:21:28.694836 RX Vref Scan: 1
970 01:21:28.695275
971 01:21:28.698145 Set Vref Range= 32 -> 127
972 01:21:28.698586
973 01:21:28.699029 RX Vref 32 -> 127, step: 1
974 01:21:28.699444
975 01:21:28.701765 RX Delay -95 -> 252, step: 8
976 01:21:28.702203
977 01:21:28.705391 Set Vref, RX VrefLevel [Byte0]: 32
978 01:21:28.707999 [Byte1]: 32
979 01:21:28.711342
980 01:21:28.711777 Set Vref, RX VrefLevel [Byte0]: 33
981 01:21:28.715126 [Byte1]: 33
982 01:21:28.718940
983 01:21:28.719549 Set Vref, RX VrefLevel [Byte0]: 34
984 01:21:28.722411 [Byte1]: 34
985 01:21:28.726743
986 01:21:28.727180 Set Vref, RX VrefLevel [Byte0]: 35
987 01:21:28.729800 [Byte1]: 35
988 01:21:28.734572
989 01:21:28.735008 Set Vref, RX VrefLevel [Byte0]: 36
990 01:21:28.737980 [Byte1]: 36
991 01:21:28.742450
992 01:21:28.742886 Set Vref, RX VrefLevel [Byte0]: 37
993 01:21:28.745564 [Byte1]: 37
994 01:21:28.750200
995 01:21:28.750639 Set Vref, RX VrefLevel [Byte0]: 38
996 01:21:28.753210 [Byte1]: 38
997 01:21:28.757652
998 01:21:28.758088 Set Vref, RX VrefLevel [Byte0]: 39
999 01:21:28.760766 [Byte1]: 39
1000 01:21:28.764698
1001 01:21:28.765261 Set Vref, RX VrefLevel [Byte0]: 40
1002 01:21:28.768488 [Byte1]: 40
1003 01:21:28.772188
1004 01:21:28.772630 Set Vref, RX VrefLevel [Byte0]: 41
1005 01:21:28.775417 [Byte1]: 41
1006 01:21:28.779866
1007 01:21:28.780486 Set Vref, RX VrefLevel [Byte0]: 42
1008 01:21:28.783282 [Byte1]: 42
1009 01:21:28.787352
1010 01:21:28.787795 Set Vref, RX VrefLevel [Byte0]: 43
1011 01:21:28.790845 [Byte1]: 43
1012 01:21:28.795330
1013 01:21:28.795789 Set Vref, RX VrefLevel [Byte0]: 44
1014 01:21:28.798338 [Byte1]: 44
1015 01:21:28.802685
1016 01:21:28.803075 Set Vref, RX VrefLevel [Byte0]: 45
1017 01:21:28.805747 [Byte1]: 45
1018 01:21:28.810629
1019 01:21:28.811089 Set Vref, RX VrefLevel [Byte0]: 46
1020 01:21:28.813449 [Byte1]: 46
1021 01:21:28.817735
1022 01:21:28.818194 Set Vref, RX VrefLevel [Byte0]: 47
1023 01:21:28.821355 [Byte1]: 47
1024 01:21:28.825162
1025 01:21:28.825624 Set Vref, RX VrefLevel [Byte0]: 48
1026 01:21:28.828487 [Byte1]: 48
1027 01:21:28.833370
1028 01:21:28.833828 Set Vref, RX VrefLevel [Byte0]: 49
1029 01:21:28.836137 [Byte1]: 49
1030 01:21:28.840351
1031 01:21:28.840823 Set Vref, RX VrefLevel [Byte0]: 50
1032 01:21:28.844080 [Byte1]: 50
1033 01:21:28.848223
1034 01:21:28.848649 Set Vref, RX VrefLevel [Byte0]: 51
1035 01:21:28.851723 [Byte1]: 51
1036 01:21:28.855916
1037 01:21:28.856350 Set Vref, RX VrefLevel [Byte0]: 52
1038 01:21:28.859165 [Byte1]: 52
1039 01:21:28.863842
1040 01:21:28.864302 Set Vref, RX VrefLevel [Byte0]: 53
1041 01:21:28.866659 [Byte1]: 53
1042 01:21:28.871471
1043 01:21:28.871930 Set Vref, RX VrefLevel [Byte0]: 54
1044 01:21:28.874491 [Byte1]: 54
1045 01:21:28.878597
1046 01:21:28.879009 Set Vref, RX VrefLevel [Byte0]: 55
1047 01:21:28.881719 [Byte1]: 55
1048 01:21:28.886175
1049 01:21:28.886611 Set Vref, RX VrefLevel [Byte0]: 56
1050 01:21:28.889856 [Byte1]: 56
1051 01:21:28.893301
1052 01:21:28.893381 Set Vref, RX VrefLevel [Byte0]: 57
1053 01:21:28.896546 [Byte1]: 57
1054 01:21:28.900874
1055 01:21:28.900955 Set Vref, RX VrefLevel [Byte0]: 58
1056 01:21:28.904175 [Byte1]: 58
1057 01:21:28.908602
1058 01:21:28.908682 Set Vref, RX VrefLevel [Byte0]: 59
1059 01:21:28.912208 [Byte1]: 59
1060 01:21:28.916399
1061 01:21:28.916479 Set Vref, RX VrefLevel [Byte0]: 60
1062 01:21:28.919406 [Byte1]: 60
1063 01:21:28.923696
1064 01:21:28.923776 Set Vref, RX VrefLevel [Byte0]: 61
1065 01:21:28.927234 [Byte1]: 61
1066 01:21:28.931735
1067 01:21:28.931816 Set Vref, RX VrefLevel [Byte0]: 62
1068 01:21:28.934745 [Byte1]: 62
1069 01:21:28.939248
1070 01:21:28.939329 Set Vref, RX VrefLevel [Byte0]: 63
1071 01:21:28.942264 [Byte1]: 63
1072 01:21:28.946495
1073 01:21:28.946575 Set Vref, RX VrefLevel [Byte0]: 64
1074 01:21:28.950090 [Byte1]: 64
1075 01:21:28.954112
1076 01:21:28.954194 Set Vref, RX VrefLevel [Byte0]: 65
1077 01:21:28.957947 [Byte1]: 65
1078 01:21:28.961828
1079 01:21:28.961908 Set Vref, RX VrefLevel [Byte0]: 66
1080 01:21:28.964943 [Byte1]: 66
1081 01:21:28.969169
1082 01:21:28.969251 Set Vref, RX VrefLevel [Byte0]: 67
1083 01:21:28.972468 [Byte1]: 67
1084 01:21:28.976706
1085 01:21:28.976788 Set Vref, RX VrefLevel [Byte0]: 68
1086 01:21:28.980088 [Byte1]: 68
1087 01:21:28.984436
1088 01:21:28.984518 Set Vref, RX VrefLevel [Byte0]: 69
1089 01:21:28.987592 [Byte1]: 69
1090 01:21:28.992105
1091 01:21:28.992188 Set Vref, RX VrefLevel [Byte0]: 70
1092 01:21:28.995430 [Byte1]: 70
1093 01:21:28.999827
1094 01:21:28.999962 Set Vref, RX VrefLevel [Byte0]: 71
1095 01:21:29.002934 [Byte1]: 71
1096 01:21:29.007453
1097 01:21:29.007535 Set Vref, RX VrefLevel [Byte0]: 72
1098 01:21:29.010744 [Byte1]: 72
1099 01:21:29.014942
1100 01:21:29.015025 Final RX Vref Byte 0 = 56 to rank0
1101 01:21:29.018657 Final RX Vref Byte 1 = 60 to rank0
1102 01:21:29.021673 Final RX Vref Byte 0 = 56 to rank1
1103 01:21:29.024569 Final RX Vref Byte 1 = 60 to rank1==
1104 01:21:29.027876 Dram Type= 6, Freq= 0, CH_0, rank 0
1105 01:21:29.035069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1106 01:21:29.035152 ==
1107 01:21:29.035218 DQS Delay:
1108 01:21:29.035279 DQS0 = 0, DQS1 = 0
1109 01:21:29.037847 DQM Delay:
1110 01:21:29.037929 DQM0 = 88, DQM1 = 76
1111 01:21:29.041359 DQ Delay:
1112 01:21:29.044753 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1113 01:21:29.048107 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1114 01:21:29.051263 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =72
1115 01:21:29.054944 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1116 01:21:29.055027
1117 01:21:29.055092
1118 01:21:29.060981 [DQSOSCAuto] RK0, (LSB)MR18= 0x2923, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 399 ps
1119 01:21:29.064625 CH0 RK0: MR19=606, MR18=2923
1120 01:21:29.070878 CH0_RK0: MR19=0x606, MR18=0x2923, DQSOSC=399, MR23=63, INC=92, DEC=61
1121 01:21:29.070962
1122 01:21:29.074336 ----->DramcWriteLeveling(PI) begin...
1123 01:21:29.074420 ==
1124 01:21:29.077834 Dram Type= 6, Freq= 0, CH_0, rank 1
1125 01:21:29.080929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1126 01:21:29.081012 ==
1127 01:21:29.084793 Write leveling (Byte 0): 31 => 31
1128 01:21:29.087842 Write leveling (Byte 1): 29 => 29
1129 01:21:29.091279 DramcWriteLeveling(PI) end<-----
1130 01:21:29.091362
1131 01:21:29.091426 ==
1132 01:21:29.094413 Dram Type= 6, Freq= 0, CH_0, rank 1
1133 01:21:29.097627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1134 01:21:29.097710 ==
1135 01:21:29.101395 [Gating] SW mode calibration
1136 01:21:29.107799 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1137 01:21:29.114849 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1138 01:21:29.117351 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1139 01:21:29.123963 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1140 01:21:29.127625 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1141 01:21:29.171588 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1142 01:21:29.171919 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1143 01:21:29.171995 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1144 01:21:29.172058 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1145 01:21:29.172500 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 01:21:29.172837 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 01:21:29.173125 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 01:21:29.173200 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 01:21:29.173700 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 01:21:29.173996 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 01:21:29.215811 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 01:21:29.216160 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 01:21:29.216247 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 01:21:29.216340 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1155 01:21:29.216434 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1156 01:21:29.216716 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1157 01:21:29.216985 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 01:21:29.217081 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 01:21:29.217592 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 01:21:29.218189 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 01:21:29.222494 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 01:21:29.225855 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 01:21:29.229525 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 01:21:29.232737 0 9 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
1165 01:21:29.235831 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1166 01:21:29.242456 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1167 01:21:29.245600 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1168 01:21:29.249486 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1169 01:21:29.255465 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1170 01:21:29.258778 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1171 01:21:29.262476 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
1172 01:21:29.268597 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (1 0)
1173 01:21:29.271871 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 01:21:29.275468 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 01:21:29.282107 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 01:21:29.285502 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 01:21:29.289101 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 01:21:29.295430 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 01:21:29.298932 0 11 4 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
1180 01:21:29.302069 0 11 8 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
1181 01:21:29.308851 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1182 01:21:29.312161 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1183 01:21:29.315362 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1184 01:21:29.318750 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 01:21:29.326238 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 01:21:29.329864 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 01:21:29.333001 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1188 01:21:29.336657 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1189 01:21:29.343431 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1190 01:21:29.347400 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1191 01:21:29.350404 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 01:21:29.353954 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 01:21:29.360998 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 01:21:29.363703 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 01:21:29.367330 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 01:21:29.373935 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 01:21:29.376833 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 01:21:29.380265 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 01:21:29.386853 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 01:21:29.390352 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 01:21:29.393423 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 01:21:29.400365 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 01:21:29.403535 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 01:21:29.407071 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1205 01:21:29.409933 Total UI for P1: 0, mck2ui 16
1206 01:21:29.413380 best dqsien dly found for B0: ( 0, 14, 6)
1207 01:21:29.420226 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 01:21:29.423795 Total UI for P1: 0, mck2ui 16
1209 01:21:29.426984 best dqsien dly found for B1: ( 0, 14, 8)
1210 01:21:29.430081 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1211 01:21:29.433066 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1212 01:21:29.433148
1213 01:21:29.436615 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1214 01:21:29.439767 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1215 01:21:29.442931 [Gating] SW calibration Done
1216 01:21:29.443013 ==
1217 01:21:29.446138 Dram Type= 6, Freq= 0, CH_0, rank 1
1218 01:21:29.449552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1219 01:21:29.449649 ==
1220 01:21:29.453180 RX Vref Scan: 0
1221 01:21:29.453261
1222 01:21:29.453326 RX Vref 0 -> 0, step: 1
1223 01:21:29.453386
1224 01:21:29.456394 RX Delay -130 -> 252, step: 16
1225 01:21:29.463228 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1226 01:21:29.466215 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1227 01:21:29.470093 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1228 01:21:29.473496 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1229 01:21:29.476511 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1230 01:21:29.479584 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1231 01:21:29.486391 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1232 01:21:29.489812 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1233 01:21:29.493650 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1234 01:21:29.496565 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1235 01:21:29.499764 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1236 01:21:29.506314 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1237 01:21:29.509875 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1238 01:21:29.513367 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1239 01:21:29.516296 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1240 01:21:29.523043 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1241 01:21:29.523125 ==
1242 01:21:29.526322 Dram Type= 6, Freq= 0, CH_0, rank 1
1243 01:21:29.529379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1244 01:21:29.529463 ==
1245 01:21:29.529528 DQS Delay:
1246 01:21:29.533067 DQS0 = 0, DQS1 = 0
1247 01:21:29.533150 DQM Delay:
1248 01:21:29.536191 DQM0 = 85, DQM1 = 77
1249 01:21:29.536273 DQ Delay:
1250 01:21:29.539586 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1251 01:21:29.543140 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1252 01:21:29.546618 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1253 01:21:29.549652 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1254 01:21:29.549734
1255 01:21:29.549798
1256 01:21:29.549858 ==
1257 01:21:29.552704 Dram Type= 6, Freq= 0, CH_0, rank 1
1258 01:21:29.556481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1259 01:21:29.556563 ==
1260 01:21:29.556628
1261 01:21:29.559405
1262 01:21:29.559486 TX Vref Scan disable
1263 01:21:29.562561 == TX Byte 0 ==
1264 01:21:29.566493 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1265 01:21:29.569587 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1266 01:21:29.572916 == TX Byte 1 ==
1267 01:21:29.576527 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1268 01:21:29.579733 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1269 01:21:29.579841 ==
1270 01:21:29.582455 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 01:21:29.589222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1272 01:21:29.589304 ==
1273 01:21:29.601044 TX Vref=22, minBit 0, minWin=27, winSum=443
1274 01:21:29.604425 TX Vref=24, minBit 2, minWin=27, winSum=446
1275 01:21:29.607585 TX Vref=26, minBit 1, minWin=27, winSum=448
1276 01:21:29.611146 TX Vref=28, minBit 2, minWin=27, winSum=454
1277 01:21:29.614514 TX Vref=30, minBit 1, minWin=27, winSum=448
1278 01:21:29.617821 TX Vref=32, minBit 1, minWin=27, winSum=449
1279 01:21:29.624176 [TxChooseVref] Worse bit 2, Min win 27, Win sum 454, Final Vref 28
1280 01:21:29.624259
1281 01:21:29.627872 Final TX Range 1 Vref 28
1282 01:21:29.627994
1283 01:21:29.628059 ==
1284 01:21:29.631757 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 01:21:29.634113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 01:21:29.634195 ==
1287 01:21:29.637423
1288 01:21:29.637504
1289 01:21:29.637569 TX Vref Scan disable
1290 01:21:29.640953 == TX Byte 0 ==
1291 01:21:29.644367 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1292 01:21:29.647648 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1293 01:21:29.651040 == TX Byte 1 ==
1294 01:21:29.654649 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1295 01:21:29.661107 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1296 01:21:29.661189
1297 01:21:29.661253 [DATLAT]
1298 01:21:29.661314 Freq=800, CH0 RK1
1299 01:21:29.661372
1300 01:21:29.664324 DATLAT Default: 0xa
1301 01:21:29.664406 0, 0xFFFF, sum = 0
1302 01:21:29.667726 1, 0xFFFF, sum = 0
1303 01:21:29.667812 2, 0xFFFF, sum = 0
1304 01:21:29.670807 3, 0xFFFF, sum = 0
1305 01:21:29.670890 4, 0xFFFF, sum = 0
1306 01:21:29.674213 5, 0xFFFF, sum = 0
1307 01:21:29.677940 6, 0xFFFF, sum = 0
1308 01:21:29.678024 7, 0xFFFF, sum = 0
1309 01:21:29.680721 8, 0xFFFF, sum = 0
1310 01:21:29.680805 9, 0x0, sum = 1
1311 01:21:29.680872 10, 0x0, sum = 2
1312 01:21:29.684401 11, 0x0, sum = 3
1313 01:21:29.684484 12, 0x0, sum = 4
1314 01:21:29.687464 best_step = 10
1315 01:21:29.687545
1316 01:21:29.687609 ==
1317 01:21:29.691137 Dram Type= 6, Freq= 0, CH_0, rank 1
1318 01:21:29.694513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1319 01:21:29.694595 ==
1320 01:21:29.697597 RX Vref Scan: 0
1321 01:21:29.697678
1322 01:21:29.697742 RX Vref 0 -> 0, step: 1
1323 01:21:29.697802
1324 01:21:29.700664 RX Delay -95 -> 252, step: 8
1325 01:21:29.708042 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1326 01:21:29.711176 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1327 01:21:29.714182 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1328 01:21:29.717585 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1329 01:21:29.723800 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1330 01:21:29.727629 iDelay=209, Bit 5, Center 76 (-31 ~ 184) 216
1331 01:21:29.730591 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1332 01:21:29.734077 iDelay=209, Bit 7, Center 92 (-15 ~ 200) 216
1333 01:21:29.737178 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1334 01:21:29.743971 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1335 01:21:29.747540 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1336 01:21:29.750737 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1337 01:21:29.754000 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1338 01:21:29.757634 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1339 01:21:29.764005 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1340 01:21:29.767358 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1341 01:21:29.767440 ==
1342 01:21:29.770572 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 01:21:29.773591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 01:21:29.773678 ==
1345 01:21:29.777424 DQS Delay:
1346 01:21:29.777505 DQS0 = 0, DQS1 = 0
1347 01:21:29.777570 DQM Delay:
1348 01:21:29.780717 DQM0 = 85, DQM1 = 77
1349 01:21:29.780798 DQ Delay:
1350 01:21:29.783594 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1351 01:21:29.787161 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =92
1352 01:21:29.790523 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =72
1353 01:21:29.793569 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1354 01:21:29.793651
1355 01:21:29.793715
1356 01:21:29.803483 [DQSOSCAuto] RK1, (LSB)MR18= 0x2421, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1357 01:21:29.806790 CH0 RK1: MR19=606, MR18=2421
1358 01:21:29.810300 CH0_RK1: MR19=0x606, MR18=0x2421, DQSOSC=400, MR23=63, INC=92, DEC=61
1359 01:21:29.813208 [RxdqsGatingPostProcess] freq 800
1360 01:21:29.819793 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1361 01:21:29.823434 Pre-setting of DQS Precalculation
1362 01:21:29.827003 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1363 01:21:29.827110 ==
1364 01:21:29.830346 Dram Type= 6, Freq= 0, CH_1, rank 0
1365 01:21:29.836757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1366 01:21:29.836839 ==
1367 01:21:29.840317 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1368 01:21:29.846741 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1369 01:21:29.855872 [CA 0] Center 36 (6~67) winsize 62
1370 01:21:29.859389 [CA 1] Center 37 (6~68) winsize 63
1371 01:21:29.862790 [CA 2] Center 35 (5~65) winsize 61
1372 01:21:29.866299 [CA 3] Center 34 (4~65) winsize 62
1373 01:21:29.869634 [CA 4] Center 34 (4~65) winsize 62
1374 01:21:29.872693 [CA 5] Center 33 (3~64) winsize 62
1375 01:21:29.872775
1376 01:21:29.875811 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1377 01:21:29.875949
1378 01:21:29.879354 [CATrainingPosCal] consider 1 rank data
1379 01:21:29.882726 u2DelayCellTimex100 = 270/100 ps
1380 01:21:29.885789 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1381 01:21:29.892668 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1382 01:21:29.895804 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1383 01:21:29.899238 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1384 01:21:29.902693 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1385 01:21:29.906014 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1386 01:21:29.906127
1387 01:21:29.909074 CA PerBit enable=1, Macro0, CA PI delay=33
1388 01:21:29.909154
1389 01:21:29.912568 [CBTSetCACLKResult] CA Dly = 33
1390 01:21:29.912648 CS Dly: 4 (0~35)
1391 01:21:29.915664 ==
1392 01:21:29.919199 Dram Type= 6, Freq= 0, CH_1, rank 1
1393 01:21:29.922082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1394 01:21:29.922163 ==
1395 01:21:29.925570 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1396 01:21:29.932032 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1397 01:21:29.942326 [CA 0] Center 36 (6~67) winsize 62
1398 01:21:29.945355 [CA 1] Center 37 (6~68) winsize 63
1399 01:21:29.948659 [CA 2] Center 34 (4~65) winsize 62
1400 01:21:29.952106 [CA 3] Center 34 (3~65) winsize 63
1401 01:21:29.955647 [CA 4] Center 34 (4~65) winsize 62
1402 01:21:29.958787 [CA 5] Center 33 (3~64) winsize 62
1403 01:21:29.958869
1404 01:21:29.962284 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1405 01:21:29.962416
1406 01:21:29.965394 [CATrainingPosCal] consider 2 rank data
1407 01:21:29.968640 u2DelayCellTimex100 = 270/100 ps
1408 01:21:29.972184 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1409 01:21:29.978950 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1410 01:21:29.982840 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1411 01:21:29.986245 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1412 01:21:29.990000 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1413 01:21:29.993894 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1414 01:21:29.993976
1415 01:21:29.997606 CA PerBit enable=1, Macro0, CA PI delay=33
1416 01:21:29.997687
1417 01:21:29.997751 [CBTSetCACLKResult] CA Dly = 33
1418 01:21:30.001167 CS Dly: 5 (0~37)
1419 01:21:30.001248
1420 01:21:30.004847 ----->DramcWriteLeveling(PI) begin...
1421 01:21:30.004929 ==
1422 01:21:30.008671 Dram Type= 6, Freq= 0, CH_1, rank 0
1423 01:21:30.012385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1424 01:21:30.012467 ==
1425 01:21:30.016041 Write leveling (Byte 0): 26 => 26
1426 01:21:30.019140 Write leveling (Byte 1): 26 => 26
1427 01:21:30.019222 DramcWriteLeveling(PI) end<-----
1428 01:21:30.019287
1429 01:21:30.022453 ==
1430 01:21:30.025669 Dram Type= 6, Freq= 0, CH_1, rank 0
1431 01:21:30.029136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1432 01:21:30.029218 ==
1433 01:21:30.032407 [Gating] SW mode calibration
1434 01:21:30.039487 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1435 01:21:30.042479 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1436 01:21:30.049716 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1437 01:21:30.052494 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1438 01:21:30.055745 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1439 01:21:30.062413 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1440 01:21:30.066127 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 01:21:30.068715 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 01:21:30.075392 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 01:21:30.078822 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 01:21:30.082044 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 01:21:30.088652 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 01:21:30.091998 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 01:21:30.095472 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 01:21:30.101935 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 01:21:30.105198 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 01:21:30.108434 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 01:21:30.115080 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 01:21:30.118451 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 01:21:30.121651 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1454 01:21:30.128234 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1455 01:21:30.131789 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 01:21:30.135353 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 01:21:30.141912 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 01:21:30.144744 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 01:21:30.148680 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 01:21:30.154917 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 01:21:30.158294 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 01:21:30.161570 0 9 8 | B1->B0 | 3131 3333 | 0 1 | (0 0) (1 1)
1463 01:21:30.168463 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1464 01:21:30.171341 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1465 01:21:30.174676 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1466 01:21:30.181469 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1467 01:21:30.184774 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1468 01:21:30.187827 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 01:21:30.194328 0 10 4 | B1->B0 | 3232 3232 | 1 0 | (1 1) (0 1)
1470 01:21:30.197857 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1471 01:21:30.201113 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 01:21:30.207834 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 01:21:30.211113 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 01:21:30.214293 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 01:21:30.221009 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 01:21:30.224507 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 01:21:30.227906 0 11 4 | B1->B0 | 2727 2f2f | 0 0 | (0 0) (1 1)
1478 01:21:30.234316 0 11 8 | B1->B0 | 3939 4444 | 0 1 | (0 0) (0 0)
1479 01:21:30.237407 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1480 01:21:30.241105 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1481 01:21:30.247459 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1482 01:21:30.250833 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1483 01:21:30.254196 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1484 01:21:30.260764 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 01:21:30.264124 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1486 01:21:30.267081 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1487 01:21:30.270644 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1488 01:21:30.277495 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1489 01:21:30.280466 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1490 01:21:30.283793 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1491 01:21:30.290445 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 01:21:30.293569 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 01:21:30.296966 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 01:21:30.303613 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 01:21:30.306867 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 01:21:30.310378 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 01:21:30.317447 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 01:21:30.320403 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 01:21:30.323746 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 01:21:30.330157 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 01:21:30.333372 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1502 01:21:30.337314 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 01:21:30.340213 Total UI for P1: 0, mck2ui 16
1504 01:21:30.343829 best dqsien dly found for B0: ( 0, 14, 4)
1505 01:21:30.346722 Total UI for P1: 0, mck2ui 16
1506 01:21:30.350205 best dqsien dly found for B1: ( 0, 14, 6)
1507 01:21:30.353723 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1508 01:21:30.356988 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1509 01:21:30.357059
1510 01:21:30.363528 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1511 01:21:30.366513 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1512 01:21:30.366611 [Gating] SW calibration Done
1513 01:21:30.369855 ==
1514 01:21:30.373336 Dram Type= 6, Freq= 0, CH_1, rank 0
1515 01:21:30.376866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1516 01:21:30.376965 ==
1517 01:21:30.377057 RX Vref Scan: 0
1518 01:21:30.377144
1519 01:21:30.380344 RX Vref 0 -> 0, step: 1
1520 01:21:30.380435
1521 01:21:30.383387 RX Delay -130 -> 252, step: 16
1522 01:21:30.386491 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1523 01:21:30.390269 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1524 01:21:30.396588 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1525 01:21:30.399648 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1526 01:21:30.403335 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1527 01:21:30.406574 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1528 01:21:30.409891 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1529 01:21:30.416186 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1530 01:21:30.420022 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1531 01:21:30.422881 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1532 01:21:30.426531 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1533 01:21:30.429590 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1534 01:21:30.436115 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1535 01:21:30.439230 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1536 01:21:30.442546 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1537 01:21:30.446319 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1538 01:21:30.446416 ==
1539 01:21:30.449478 Dram Type= 6, Freq= 0, CH_1, rank 0
1540 01:21:30.455944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1541 01:21:30.456019 ==
1542 01:21:30.456081 DQS Delay:
1543 01:21:30.459752 DQS0 = 0, DQS1 = 0
1544 01:21:30.459852 DQM Delay:
1545 01:21:30.459935 DQM0 = 84, DQM1 = 79
1546 01:21:30.462995 DQ Delay:
1547 01:21:30.466020 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1548 01:21:30.469701 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1549 01:21:30.473181 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1550 01:21:30.475996 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1551 01:21:30.476069
1552 01:21:30.476132
1553 01:21:30.476193 ==
1554 01:21:30.479558 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 01:21:30.482487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 01:21:30.482588 ==
1557 01:21:30.482678
1558 01:21:30.482765
1559 01:21:30.486278 TX Vref Scan disable
1560 01:21:30.486377 == TX Byte 0 ==
1561 01:21:30.493174 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1562 01:21:30.495983 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1563 01:21:30.496058 == TX Byte 1 ==
1564 01:21:30.502843 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1565 01:21:30.505987 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1566 01:21:30.506086 ==
1567 01:21:30.509403 Dram Type= 6, Freq= 0, CH_1, rank 0
1568 01:21:30.512436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1569 01:21:30.512512 ==
1570 01:21:30.526490 TX Vref=22, minBit 0, minWin=27, winSum=441
1571 01:21:30.530361 TX Vref=24, minBit 2, minWin=27, winSum=448
1572 01:21:30.532984 TX Vref=26, minBit 4, minWin=27, winSum=449
1573 01:21:30.536358 TX Vref=28, minBit 4, minWin=27, winSum=453
1574 01:21:30.539659 TX Vref=30, minBit 0, minWin=28, winSum=457
1575 01:21:30.546479 TX Vref=32, minBit 0, minWin=27, winSum=453
1576 01:21:30.549837 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
1577 01:21:30.549915
1578 01:21:30.553111 Final TX Range 1 Vref 30
1579 01:21:30.553183
1580 01:21:30.553244 ==
1581 01:21:30.556475 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 01:21:30.559545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 01:21:30.559627 ==
1584 01:21:30.563568
1585 01:21:30.563649
1586 01:21:30.563715 TX Vref Scan disable
1587 01:21:30.566967 == TX Byte 0 ==
1588 01:21:30.570102 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1589 01:21:30.573585 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1590 01:21:30.576775 == TX Byte 1 ==
1591 01:21:30.580007 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1592 01:21:30.583255 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1593 01:21:30.583337
1594 01:21:30.586578 [DATLAT]
1595 01:21:30.586659 Freq=800, CH1 RK0
1596 01:21:30.586725
1597 01:21:30.590018 DATLAT Default: 0xa
1598 01:21:30.590099 0, 0xFFFF, sum = 0
1599 01:21:30.593412 1, 0xFFFF, sum = 0
1600 01:21:30.593496 2, 0xFFFF, sum = 0
1601 01:21:30.596710 3, 0xFFFF, sum = 0
1602 01:21:30.596799 4, 0xFFFF, sum = 0
1603 01:21:30.599998 5, 0xFFFF, sum = 0
1604 01:21:30.600081 6, 0xFFFF, sum = 0
1605 01:21:30.603585 7, 0xFFFF, sum = 0
1606 01:21:30.603667 8, 0xFFFF, sum = 0
1607 01:21:30.607014 9, 0x0, sum = 1
1608 01:21:30.607098 10, 0x0, sum = 2
1609 01:21:30.610314 11, 0x0, sum = 3
1610 01:21:30.610397 12, 0x0, sum = 4
1611 01:21:30.613243 best_step = 10
1612 01:21:30.613323
1613 01:21:30.613386 ==
1614 01:21:30.616760 Dram Type= 6, Freq= 0, CH_1, rank 0
1615 01:21:30.620034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1616 01:21:30.620116 ==
1617 01:21:30.623441 RX Vref Scan: 1
1618 01:21:30.623522
1619 01:21:30.623585 Set Vref Range= 32 -> 127
1620 01:21:30.623645
1621 01:21:30.626445 RX Vref 32 -> 127, step: 1
1622 01:21:30.626526
1623 01:21:30.629779 RX Delay -95 -> 252, step: 8
1624 01:21:30.629862
1625 01:21:30.633257 Set Vref, RX VrefLevel [Byte0]: 32
1626 01:21:30.636440 [Byte1]: 32
1627 01:21:30.636534
1628 01:21:30.639781 Set Vref, RX VrefLevel [Byte0]: 33
1629 01:21:30.643247 [Byte1]: 33
1630 01:21:30.646636
1631 01:21:30.646738 Set Vref, RX VrefLevel [Byte0]: 34
1632 01:21:30.650009 [Byte1]: 34
1633 01:21:30.654449
1634 01:21:30.654559 Set Vref, RX VrefLevel [Byte0]: 35
1635 01:21:30.657815 [Byte1]: 35
1636 01:21:30.661754
1637 01:21:30.661884 Set Vref, RX VrefLevel [Byte0]: 36
1638 01:21:30.665568 [Byte1]: 36
1639 01:21:30.669997
1640 01:21:30.672801 Set Vref, RX VrefLevel [Byte0]: 37
1641 01:21:30.673054 [Byte1]: 37
1642 01:21:30.677786
1643 01:21:30.678077 Set Vref, RX VrefLevel [Byte0]: 38
1644 01:21:30.680829 [Byte1]: 38
1645 01:21:30.685026
1646 01:21:30.685377 Set Vref, RX VrefLevel [Byte0]: 39
1647 01:21:30.688046 [Byte1]: 39
1648 01:21:30.692842
1649 01:21:30.693247 Set Vref, RX VrefLevel [Byte0]: 40
1650 01:21:30.695847 [Byte1]: 40
1651 01:21:30.700188
1652 01:21:30.700634 Set Vref, RX VrefLevel [Byte0]: 41
1653 01:21:30.703299 [Byte1]: 41
1654 01:21:30.707541
1655 01:21:30.708127 Set Vref, RX VrefLevel [Byte0]: 42
1656 01:21:30.711378 [Byte1]: 42
1657 01:21:30.715750
1658 01:21:30.716209 Set Vref, RX VrefLevel [Byte0]: 43
1659 01:21:30.718887 [Byte1]: 43
1660 01:21:30.723122
1661 01:21:30.723530 Set Vref, RX VrefLevel [Byte0]: 44
1662 01:21:30.726325 [Byte1]: 44
1663 01:21:30.730344
1664 01:21:30.730709 Set Vref, RX VrefLevel [Byte0]: 45
1665 01:21:30.734204 [Byte1]: 45
1666 01:21:30.738039
1667 01:21:30.738448 Set Vref, RX VrefLevel [Byte0]: 46
1668 01:21:30.741623 [Byte1]: 46
1669 01:21:30.745847
1670 01:21:30.746224 Set Vref, RX VrefLevel [Byte0]: 47
1671 01:21:30.748996 [Byte1]: 47
1672 01:21:30.753380
1673 01:21:30.753742 Set Vref, RX VrefLevel [Byte0]: 48
1674 01:21:30.756682 [Byte1]: 48
1675 01:21:30.760810
1676 01:21:30.761264 Set Vref, RX VrefLevel [Byte0]: 49
1677 01:21:30.764608 [Byte1]: 49
1678 01:21:30.768580
1679 01:21:30.769108 Set Vref, RX VrefLevel [Byte0]: 50
1680 01:21:30.771878 [Byte1]: 50
1681 01:21:30.776342
1682 01:21:30.776882 Set Vref, RX VrefLevel [Byte0]: 51
1683 01:21:30.779378 [Byte1]: 51
1684 01:21:30.783938
1685 01:21:30.784365 Set Vref, RX VrefLevel [Byte0]: 52
1686 01:21:30.787018 [Byte1]: 52
1687 01:21:30.791177
1688 01:21:30.791641 Set Vref, RX VrefLevel [Byte0]: 53
1689 01:21:30.794524 [Byte1]: 53
1690 01:21:30.799527
1691 01:21:30.800144 Set Vref, RX VrefLevel [Byte0]: 54
1692 01:21:30.802206 [Byte1]: 54
1693 01:21:30.806586
1694 01:21:30.807148 Set Vref, RX VrefLevel [Byte0]: 55
1695 01:21:30.809976 [Byte1]: 55
1696 01:21:30.814329
1697 01:21:30.814955 Set Vref, RX VrefLevel [Byte0]: 56
1698 01:21:30.817466 [Byte1]: 56
1699 01:21:30.822169
1700 01:21:30.822654 Set Vref, RX VrefLevel [Byte0]: 57
1701 01:21:30.825220 [Byte1]: 57
1702 01:21:30.829341
1703 01:21:30.829905 Set Vref, RX VrefLevel [Byte0]: 58
1704 01:21:30.832996 [Byte1]: 58
1705 01:21:30.837438
1706 01:21:30.837869 Set Vref, RX VrefLevel [Byte0]: 59
1707 01:21:30.840098 [Byte1]: 59
1708 01:21:30.844901
1709 01:21:30.845485 Set Vref, RX VrefLevel [Byte0]: 60
1710 01:21:30.847686 [Byte1]: 60
1711 01:21:30.852344
1712 01:21:30.853004 Set Vref, RX VrefLevel [Byte0]: 61
1713 01:21:30.855619 [Byte1]: 61
1714 01:21:30.860167
1715 01:21:30.860831 Set Vref, RX VrefLevel [Byte0]: 62
1716 01:21:30.862729 [Byte1]: 62
1717 01:21:30.867005
1718 01:21:30.871311 Set Vref, RX VrefLevel [Byte0]: 63
1719 01:21:30.874154 [Byte1]: 63
1720 01:21:30.874702
1721 01:21:30.876968 Set Vref, RX VrefLevel [Byte0]: 64
1722 01:21:30.881017 [Byte1]: 64
1723 01:21:30.881585
1724 01:21:30.883866 Set Vref, RX VrefLevel [Byte0]: 65
1725 01:21:30.887283 [Byte1]: 65
1726 01:21:30.887730
1727 01:21:30.890446 Set Vref, RX VrefLevel [Byte0]: 66
1728 01:21:30.893922 [Byte1]: 66
1729 01:21:30.897798
1730 01:21:30.898221 Set Vref, RX VrefLevel [Byte0]: 67
1731 01:21:30.901138 [Byte1]: 67
1732 01:21:30.905505
1733 01:21:30.905930 Set Vref, RX VrefLevel [Byte0]: 68
1734 01:21:30.908715 [Byte1]: 68
1735 01:21:30.912759
1736 01:21:30.913179 Set Vref, RX VrefLevel [Byte0]: 69
1737 01:21:30.916288 [Byte1]: 69
1738 01:21:30.920899
1739 01:21:30.921316 Set Vref, RX VrefLevel [Byte0]: 70
1740 01:21:30.924151 [Byte1]: 70
1741 01:21:30.928466
1742 01:21:30.928927 Set Vref, RX VrefLevel [Byte0]: 71
1743 01:21:30.931732 [Byte1]: 71
1744 01:21:30.935440
1745 01:21:30.935859 Set Vref, RX VrefLevel [Byte0]: 72
1746 01:21:30.938722 [Byte1]: 72
1747 01:21:30.943557
1748 01:21:30.944015 Set Vref, RX VrefLevel [Byte0]: 73
1749 01:21:30.946607 [Byte1]: 73
1750 01:21:30.951037
1751 01:21:30.951456 Set Vref, RX VrefLevel [Byte0]: 74
1752 01:21:30.953897 [Byte1]: 74
1753 01:21:30.958477
1754 01:21:30.958894 Set Vref, RX VrefLevel [Byte0]: 75
1755 01:21:30.961819 [Byte1]: 75
1756 01:21:30.966247
1757 01:21:30.966666 Final RX Vref Byte 0 = 59 to rank0
1758 01:21:30.969851 Final RX Vref Byte 1 = 52 to rank0
1759 01:21:30.973132 Final RX Vref Byte 0 = 59 to rank1
1760 01:21:30.975828 Final RX Vref Byte 1 = 52 to rank1==
1761 01:21:30.979444 Dram Type= 6, Freq= 0, CH_1, rank 0
1762 01:21:30.986035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1763 01:21:30.986459 ==
1764 01:21:30.986807 DQS Delay:
1765 01:21:30.987117 DQS0 = 0, DQS1 = 0
1766 01:21:30.989484 DQM Delay:
1767 01:21:30.989910 DQM0 = 86, DQM1 = 80
1768 01:21:30.992651 DQ Delay:
1769 01:21:30.996479 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1770 01:21:30.999625 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =80
1771 01:21:31.002524 DQ8 =64, DQ9 =72, DQ10 =80, DQ11 =76
1772 01:21:31.005675 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
1773 01:21:31.006093
1774 01:21:31.006423
1775 01:21:31.012167 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b2e, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1776 01:21:31.015618 CH1 RK0: MR19=606, MR18=1B2E
1777 01:21:31.022064 CH1_RK0: MR19=0x606, MR18=0x1B2E, DQSOSC=398, MR23=63, INC=93, DEC=62
1778 01:21:31.022484
1779 01:21:31.025888 ----->DramcWriteLeveling(PI) begin...
1780 01:21:31.026333 ==
1781 01:21:31.028674 Dram Type= 6, Freq= 0, CH_1, rank 1
1782 01:21:31.031973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1783 01:21:31.032415 ==
1784 01:21:31.035688 Write leveling (Byte 0): 27 => 27
1785 01:21:31.038934 Write leveling (Byte 1): 27 => 27
1786 01:21:31.042012 DramcWriteLeveling(PI) end<-----
1787 01:21:31.042463
1788 01:21:31.042811 ==
1789 01:21:31.045697 Dram Type= 6, Freq= 0, CH_1, rank 1
1790 01:21:31.048529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 01:21:31.048957 ==
1792 01:21:31.052184 [Gating] SW mode calibration
1793 01:21:31.058862 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1794 01:21:31.065090 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1795 01:21:31.068827 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1796 01:21:31.074990 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1797 01:21:31.078463 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1798 01:21:31.082441 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1799 01:21:31.088620 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 01:21:31.092021 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 01:21:31.094944 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 01:21:31.101743 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 01:21:31.105252 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 01:21:31.108221 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 01:21:31.114880 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 01:21:31.118548 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 01:21:31.121542 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 01:21:31.127795 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 01:21:31.131056 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 01:21:31.134524 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 01:21:31.141090 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1812 01:21:31.144465 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1813 01:21:31.147923 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 01:21:31.154307 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 01:21:31.157881 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 01:21:31.160908 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 01:21:31.164293 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 01:21:31.170754 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 01:21:31.174007 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 01:21:31.177479 0 9 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
1821 01:21:31.184160 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1822 01:21:31.187580 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1823 01:21:31.190868 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1824 01:21:31.197593 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 01:21:31.200602 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 01:21:31.204309 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 01:21:31.210735 0 10 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1828 01:21:31.213964 0 10 4 | B1->B0 | 3232 2626 | 0 1 | (0 0) (1 0)
1829 01:21:31.217482 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1830 01:21:31.224100 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 01:21:31.227030 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 01:21:31.230753 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 01:21:31.237190 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 01:21:31.240747 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 01:21:31.243688 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 01:21:31.250479 0 11 4 | B1->B0 | 2525 3d3d | 1 0 | (0 0) (0 0)
1837 01:21:31.253848 0 11 8 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1838 01:21:31.257753 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1839 01:21:31.263736 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1840 01:21:31.267001 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 01:21:31.270409 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 01:21:31.277080 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 01:21:31.280387 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1844 01:21:31.283837 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1845 01:21:31.290263 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1846 01:21:31.293702 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1847 01:21:31.297298 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 01:21:31.303353 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 01:21:31.306499 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 01:21:31.309790 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 01:21:31.316361 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 01:21:31.319870 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 01:21:31.323692 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 01:21:31.329662 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 01:21:31.333158 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 01:21:31.336659 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 01:21:31.343291 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 01:21:31.346718 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 01:21:31.349977 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1860 01:21:31.356416 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1861 01:21:31.356951 Total UI for P1: 0, mck2ui 16
1862 01:21:31.362903 best dqsien dly found for B0: ( 0, 14, 0)
1863 01:21:31.366625 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1864 01:21:31.369663 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 01:21:31.372841 Total UI for P1: 0, mck2ui 16
1866 01:21:31.376229 best dqsien dly found for B1: ( 0, 14, 8)
1867 01:21:31.379539 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1868 01:21:31.383241 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1869 01:21:31.383795
1870 01:21:31.386395 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1871 01:21:31.392713 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1872 01:21:31.393255 [Gating] SW calibration Done
1873 01:21:31.393737 ==
1874 01:21:31.396126 Dram Type= 6, Freq= 0, CH_1, rank 1
1875 01:21:31.402716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1876 01:21:31.403241 ==
1877 01:21:31.403649 RX Vref Scan: 0
1878 01:21:31.404192
1879 01:21:31.406332 RX Vref 0 -> 0, step: 1
1880 01:21:31.406843
1881 01:21:31.409465 RX Delay -130 -> 252, step: 16
1882 01:21:31.412509 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1883 01:21:31.415848 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1884 01:21:31.419232 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1885 01:21:31.426357 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1886 01:21:31.429494 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1887 01:21:31.432657 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1888 01:21:31.435522 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1889 01:21:31.438982 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1890 01:21:31.446028 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1891 01:21:31.449324 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1892 01:21:31.452240 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1893 01:21:31.455694 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1894 01:21:31.459116 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1895 01:21:31.465951 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1896 01:21:31.469510 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1897 01:21:31.472130 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1898 01:21:31.472714 ==
1899 01:21:31.476070 Dram Type= 6, Freq= 0, CH_1, rank 1
1900 01:21:31.479527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1901 01:21:31.482463 ==
1902 01:21:31.482892 DQS Delay:
1903 01:21:31.483229 DQS0 = 0, DQS1 = 0
1904 01:21:31.485584 DQM Delay:
1905 01:21:31.486005 DQM0 = 84, DQM1 = 83
1906 01:21:31.488801 DQ Delay:
1907 01:21:31.489221 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =77
1908 01:21:31.492413 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1909 01:21:31.495937 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1910 01:21:31.498735 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1911 01:21:31.501937
1912 01:21:31.502361
1913 01:21:31.502696 ==
1914 01:21:31.505297 Dram Type= 6, Freq= 0, CH_1, rank 1
1915 01:21:31.508885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1916 01:21:31.509317 ==
1917 01:21:31.509655
1918 01:21:31.509969
1919 01:21:31.511836 TX Vref Scan disable
1920 01:21:31.512311 == TX Byte 0 ==
1921 01:21:31.518751 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1922 01:21:31.521846 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1923 01:21:31.522287 == TX Byte 1 ==
1924 01:21:31.528418 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1925 01:21:31.532147 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1926 01:21:31.532557 ==
1927 01:21:31.535338 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 01:21:31.538408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 01:21:31.538833 ==
1930 01:21:31.551997 TX Vref=22, minBit 6, minWin=27, winSum=448
1931 01:21:31.555524 TX Vref=24, minBit 6, minWin=27, winSum=450
1932 01:21:31.558362 TX Vref=26, minBit 1, minWin=27, winSum=452
1933 01:21:31.561851 TX Vref=28, minBit 0, minWin=28, winSum=454
1934 01:21:31.565490 TX Vref=30, minBit 0, minWin=28, winSum=456
1935 01:21:31.572371 TX Vref=32, minBit 5, minWin=27, winSum=453
1936 01:21:31.575471 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
1937 01:21:31.576085
1938 01:21:31.578430 Final TX Range 1 Vref 30
1939 01:21:31.578854
1940 01:21:31.579278 ==
1941 01:21:31.581663 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 01:21:31.585185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 01:21:31.588214 ==
1944 01:21:31.588634
1945 01:21:31.588963
1946 01:21:31.589274 TX Vref Scan disable
1947 01:21:31.591837 == TX Byte 0 ==
1948 01:21:31.595287 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1949 01:21:31.598582 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1950 01:21:31.601815 == TX Byte 1 ==
1951 01:21:31.605330 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1952 01:21:31.608724 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1953 01:21:31.612271
1954 01:21:31.613007 [DATLAT]
1955 01:21:31.613598 Freq=800, CH1 RK1
1956 01:21:31.613945
1957 01:21:31.614930 DATLAT Default: 0xa
1958 01:21:31.615353 0, 0xFFFF, sum = 0
1959 01:21:31.618611 1, 0xFFFF, sum = 0
1960 01:21:31.619043 2, 0xFFFF, sum = 0
1961 01:21:31.621549 3, 0xFFFF, sum = 0
1962 01:21:31.625245 4, 0xFFFF, sum = 0
1963 01:21:31.625677 5, 0xFFFF, sum = 0
1964 01:21:31.628407 6, 0xFFFF, sum = 0
1965 01:21:31.628834 7, 0xFFFF, sum = 0
1966 01:21:31.631958 8, 0xFFFF, sum = 0
1967 01:21:31.632392 9, 0x0, sum = 1
1968 01:21:31.635146 10, 0x0, sum = 2
1969 01:21:31.635626 11, 0x0, sum = 3
1970 01:21:31.636122 12, 0x0, sum = 4
1971 01:21:31.638696 best_step = 10
1972 01:21:31.639117
1973 01:21:31.639451 ==
1974 01:21:31.641499 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 01:21:31.644914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 01:21:31.645341 ==
1977 01:21:31.648362 RX Vref Scan: 0
1978 01:21:31.648784
1979 01:21:31.649123 RX Vref 0 -> 0, step: 1
1980 01:21:31.649437
1981 01:21:31.651618 RX Delay -95 -> 252, step: 8
1982 01:21:31.659173 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1983 01:21:31.661744 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1984 01:21:31.665110 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1985 01:21:31.668315 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1986 01:21:31.671921 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1987 01:21:31.678814 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1988 01:21:31.681763 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1989 01:21:31.684958 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1990 01:21:31.688639 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1991 01:21:31.691548 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1992 01:21:31.698176 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1993 01:21:31.701600 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1994 01:21:31.705235 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1995 01:21:31.708275 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1996 01:21:31.714741 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1997 01:21:31.718169 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1998 01:21:31.718597 ==
1999 01:21:31.721162 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 01:21:31.724694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 01:21:31.725156 ==
2002 01:21:31.728012 DQS Delay:
2003 01:21:31.728400 DQS0 = 0, DQS1 = 0
2004 01:21:31.728872 DQM Delay:
2005 01:21:31.731365 DQM0 = 85, DQM1 = 81
2006 01:21:31.731817 DQ Delay:
2007 01:21:31.734361 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
2008 01:21:31.737958 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2009 01:21:31.741490 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =76
2010 01:21:31.744345 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2011 01:21:31.744718
2012 01:21:31.745052
2013 01:21:31.754411 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2014 01:21:31.754826 CH1 RK1: MR19=606, MR18=1F3A
2015 01:21:31.761066 CH1_RK1: MR19=0x606, MR18=0x1F3A, DQSOSC=395, MR23=63, INC=94, DEC=63
2016 01:21:31.764322 [RxdqsGatingPostProcess] freq 800
2017 01:21:31.770900 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2018 01:21:31.774174 Pre-setting of DQS Precalculation
2019 01:21:31.777488 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2020 01:21:31.787585 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2021 01:21:31.793826 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2022 01:21:31.793911
2023 01:21:31.793996
2024 01:21:31.796981 [Calibration Summary] 1600 Mbps
2025 01:21:31.797065 CH 0, Rank 0
2026 01:21:31.801113 SW Impedance : PASS
2027 01:21:31.801197 DUTY Scan : NO K
2028 01:21:31.804183 ZQ Calibration : PASS
2029 01:21:31.807240 Jitter Meter : NO K
2030 01:21:31.807325 CBT Training : PASS
2031 01:21:31.810393 Write leveling : PASS
2032 01:21:31.814236 RX DQS gating : PASS
2033 01:21:31.814321 RX DQ/DQS(RDDQC) : PASS
2034 01:21:31.817325 TX DQ/DQS : PASS
2035 01:21:31.817410 RX DATLAT : PASS
2036 01:21:31.820512 RX DQ/DQS(Engine): PASS
2037 01:21:31.823993 TX OE : NO K
2038 01:21:31.824077 All Pass.
2039 01:21:31.824161
2040 01:21:31.824241 CH 0, Rank 1
2041 01:21:31.827273 SW Impedance : PASS
2042 01:21:31.830815 DUTY Scan : NO K
2043 01:21:31.830924 ZQ Calibration : PASS
2044 01:21:31.833482 Jitter Meter : NO K
2045 01:21:31.837235 CBT Training : PASS
2046 01:21:31.837319 Write leveling : PASS
2047 01:21:31.840753 RX DQS gating : PASS
2048 01:21:31.844047 RX DQ/DQS(RDDQC) : PASS
2049 01:21:31.844130 TX DQ/DQS : PASS
2050 01:21:31.847052 RX DATLAT : PASS
2051 01:21:31.850461 RX DQ/DQS(Engine): PASS
2052 01:21:31.850545 TX OE : NO K
2053 01:21:31.854024 All Pass.
2054 01:21:31.854108
2055 01:21:31.854191 CH 1, Rank 0
2056 01:21:31.857130 SW Impedance : PASS
2057 01:21:31.857214 DUTY Scan : NO K
2058 01:21:31.860041 ZQ Calibration : PASS
2059 01:21:31.863411 Jitter Meter : NO K
2060 01:21:31.863495 CBT Training : PASS
2061 01:21:31.866569 Write leveling : PASS
2062 01:21:31.870621 RX DQS gating : PASS
2063 01:21:31.870706 RX DQ/DQS(RDDQC) : PASS
2064 01:21:31.873649 TX DQ/DQS : PASS
2065 01:21:31.873734 RX DATLAT : PASS
2066 01:21:31.876574 RX DQ/DQS(Engine): PASS
2067 01:21:31.880658 TX OE : NO K
2068 01:21:31.880743 All Pass.
2069 01:21:31.880828
2070 01:21:31.880908 CH 1, Rank 1
2071 01:21:31.883770 SW Impedance : PASS
2072 01:21:31.887033 DUTY Scan : NO K
2073 01:21:31.887117 ZQ Calibration : PASS
2074 01:21:31.890104 Jitter Meter : NO K
2075 01:21:31.893677 CBT Training : PASS
2076 01:21:31.893761 Write leveling : PASS
2077 01:21:31.896953 RX DQS gating : PASS
2078 01:21:31.900043 RX DQ/DQS(RDDQC) : PASS
2079 01:21:31.900127 TX DQ/DQS : PASS
2080 01:21:31.903768 RX DATLAT : PASS
2081 01:21:31.906861 RX DQ/DQS(Engine): PASS
2082 01:21:31.906944 TX OE : NO K
2083 01:21:31.910101 All Pass.
2084 01:21:31.910185
2085 01:21:31.910269 DramC Write-DBI off
2086 01:21:31.913152 PER_BANK_REFRESH: Hybrid Mode
2087 01:21:31.913237 TX_TRACKING: ON
2088 01:21:31.916702 [GetDramInforAfterCalByMRR] Vendor 6.
2089 01:21:31.923398 [GetDramInforAfterCalByMRR] Revision 606.
2090 01:21:31.926878 [GetDramInforAfterCalByMRR] Revision 2 0.
2091 01:21:31.926962 MR0 0x3b3b
2092 01:21:31.927046 MR8 0x5151
2093 01:21:31.930288 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2094 01:21:31.930372
2095 01:21:31.933279 MR0 0x3b3b
2096 01:21:31.933363 MR8 0x5151
2097 01:21:31.936504 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2098 01:21:31.936589
2099 01:21:31.946544 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2100 01:21:31.949567 [FAST_K] Save calibration result to emmc
2101 01:21:31.952771 [FAST_K] Save calibration result to emmc
2102 01:21:31.956551 dram_init: config_dvfs: 1
2103 01:21:31.959780 dramc_set_vcore_voltage set vcore to 662500
2104 01:21:31.963006 Read voltage for 1200, 2
2105 01:21:31.963089 Vio18 = 0
2106 01:21:31.963174 Vcore = 662500
2107 01:21:31.966444 Vdram = 0
2108 01:21:31.966529 Vddq = 0
2109 01:21:31.966612 Vmddr = 0
2110 01:21:31.973254 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2111 01:21:31.976127 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2112 01:21:31.979569 MEM_TYPE=3, freq_sel=15
2113 01:21:31.982356 sv_algorithm_assistance_LP4_1600
2114 01:21:31.985772 ============ PULL DRAM RESETB DOWN ============
2115 01:21:31.989144 ========== PULL DRAM RESETB DOWN end =========
2116 01:21:31.995674 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2117 01:21:31.999317 ===================================
2118 01:21:32.002570 LPDDR4 DRAM CONFIGURATION
2119 01:21:32.005703 ===================================
2120 01:21:32.005787 EX_ROW_EN[0] = 0x0
2121 01:21:32.009066 EX_ROW_EN[1] = 0x0
2122 01:21:32.009150 LP4Y_EN = 0x0
2123 01:21:32.012400 WORK_FSP = 0x0
2124 01:21:32.012485 WL = 0x4
2125 01:21:32.015876 RL = 0x4
2126 01:21:32.015968 BL = 0x2
2127 01:21:32.018855 RPST = 0x0
2128 01:21:32.018939 RD_PRE = 0x0
2129 01:21:32.022237 WR_PRE = 0x1
2130 01:21:32.022322 WR_PST = 0x0
2131 01:21:32.025687 DBI_WR = 0x0
2132 01:21:32.025770 DBI_RD = 0x0
2133 01:21:32.029096 OTF = 0x1
2134 01:21:32.032442 ===================================
2135 01:21:32.035529 ===================================
2136 01:21:32.035638 ANA top config
2137 01:21:32.038972 ===================================
2138 01:21:32.042275 DLL_ASYNC_EN = 0
2139 01:21:32.045589 ALL_SLAVE_EN = 0
2140 01:21:32.048939 NEW_RANK_MODE = 1
2141 01:21:32.052456 DLL_IDLE_MODE = 1
2142 01:21:32.052540 LP45_APHY_COMB_EN = 1
2143 01:21:32.055351 TX_ODT_DIS = 1
2144 01:21:32.058510 NEW_8X_MODE = 1
2145 01:21:32.062166 ===================================
2146 01:21:32.065420 ===================================
2147 01:21:32.069010 data_rate = 2400
2148 01:21:32.072117 CKR = 1
2149 01:21:32.072201 DQ_P2S_RATIO = 8
2150 01:21:32.075296 ===================================
2151 01:21:32.078660 CA_P2S_RATIO = 8
2152 01:21:32.081933 DQ_CA_OPEN = 0
2153 01:21:32.085098 DQ_SEMI_OPEN = 0
2154 01:21:32.088356 CA_SEMI_OPEN = 0
2155 01:21:32.091850 CA_FULL_RATE = 0
2156 01:21:32.091993 DQ_CKDIV4_EN = 0
2157 01:21:32.095289 CA_CKDIV4_EN = 0
2158 01:21:32.098714 CA_PREDIV_EN = 0
2159 01:21:32.101505 PH8_DLY = 17
2160 01:21:32.104624 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2161 01:21:32.108519 DQ_AAMCK_DIV = 4
2162 01:21:32.108623 CA_AAMCK_DIV = 4
2163 01:21:32.111411 CA_ADMCK_DIV = 4
2164 01:21:32.114632 DQ_TRACK_CA_EN = 0
2165 01:21:32.118411 CA_PICK = 1200
2166 01:21:32.121776 CA_MCKIO = 1200
2167 01:21:32.124751 MCKIO_SEMI = 0
2168 01:21:32.127817 PLL_FREQ = 2366
2169 01:21:32.131589 DQ_UI_PI_RATIO = 32
2170 01:21:32.131721 CA_UI_PI_RATIO = 0
2171 01:21:32.134493 ===================================
2172 01:21:32.138127 ===================================
2173 01:21:32.141543 memory_type:LPDDR4
2174 01:21:32.144489 GP_NUM : 10
2175 01:21:32.144573 SRAM_EN : 1
2176 01:21:32.148018 MD32_EN : 0
2177 01:21:32.151101 ===================================
2178 01:21:32.154651 [ANA_INIT] >>>>>>>>>>>>>>
2179 01:21:32.158094 <<<<<< [CONFIGURE PHASE]: ANA_TX
2180 01:21:32.161892 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2181 01:21:32.164782 ===================================
2182 01:21:32.164866 data_rate = 2400,PCW = 0X5b00
2183 01:21:32.168022 ===================================
2184 01:21:32.171125 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2185 01:21:32.177840 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2186 01:21:32.184026 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2187 01:21:32.187767 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2188 01:21:32.190887 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2189 01:21:32.194283 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2190 01:21:32.197650 [ANA_INIT] flow start
2191 01:21:32.200713 [ANA_INIT] PLL >>>>>>>>
2192 01:21:32.200814 [ANA_INIT] PLL <<<<<<<<
2193 01:21:32.204222 [ANA_INIT] MIDPI >>>>>>>>
2194 01:21:32.207435 [ANA_INIT] MIDPI <<<<<<<<
2195 01:21:32.207533 [ANA_INIT] DLL >>>>>>>>
2196 01:21:32.210565 [ANA_INIT] DLL <<<<<<<<
2197 01:21:32.214037 [ANA_INIT] flow end
2198 01:21:32.217261 ============ LP4 DIFF to SE enter ============
2199 01:21:32.220573 ============ LP4 DIFF to SE exit ============
2200 01:21:32.224055 [ANA_INIT] <<<<<<<<<<<<<
2201 01:21:32.227250 [Flow] Enable top DCM control >>>>>
2202 01:21:32.230833 [Flow] Enable top DCM control <<<<<
2203 01:21:32.234165 Enable DLL master slave shuffle
2204 01:21:32.237532 ==============================================================
2205 01:21:32.240955 Gating Mode config
2206 01:21:32.247073 ==============================================================
2207 01:21:32.247158 Config description:
2208 01:21:32.257126 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2209 01:21:32.263739 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2210 01:21:32.270511 SELPH_MODE 0: By rank 1: By Phase
2211 01:21:32.273571 ==============================================================
2212 01:21:32.276974 GAT_TRACK_EN = 1
2213 01:21:32.280233 RX_GATING_MODE = 2
2214 01:21:32.283515 RX_GATING_TRACK_MODE = 2
2215 01:21:32.286636 SELPH_MODE = 1
2216 01:21:32.290247 PICG_EARLY_EN = 1
2217 01:21:32.293146 VALID_LAT_VALUE = 1
2218 01:21:32.297106 ==============================================================
2219 01:21:32.299771 Enter into Gating configuration >>>>
2220 01:21:32.303103 Exit from Gating configuration <<<<
2221 01:21:32.306401 Enter into DVFS_PRE_config >>>>>
2222 01:21:32.319811 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2223 01:21:32.323016 Exit from DVFS_PRE_config <<<<<
2224 01:21:32.323142 Enter into PICG configuration >>>>
2225 01:21:32.326677 Exit from PICG configuration <<<<
2226 01:21:32.329835 [RX_INPUT] configuration >>>>>
2227 01:21:32.333159 [RX_INPUT] configuration <<<<<
2228 01:21:32.339588 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2229 01:21:32.343302 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2230 01:21:32.349489 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2231 01:21:32.356657 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2232 01:21:32.362762 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2233 01:21:32.369422 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2234 01:21:32.372965 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2235 01:21:32.376492 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2236 01:21:32.379297 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2237 01:21:32.386149 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2238 01:21:32.389567 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2239 01:21:32.392666 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2240 01:21:32.395973 ===================================
2241 01:21:32.399251 LPDDR4 DRAM CONFIGURATION
2242 01:21:32.402792 ===================================
2243 01:21:32.405984 EX_ROW_EN[0] = 0x0
2244 01:21:32.406065 EX_ROW_EN[1] = 0x0
2245 01:21:32.409479 LP4Y_EN = 0x0
2246 01:21:32.409560 WORK_FSP = 0x0
2247 01:21:32.412640 WL = 0x4
2248 01:21:32.412801 RL = 0x4
2249 01:21:32.415789 BL = 0x2
2250 01:21:32.415870 RPST = 0x0
2251 01:21:32.419342 RD_PRE = 0x0
2252 01:21:32.419423 WR_PRE = 0x1
2253 01:21:32.422784 WR_PST = 0x0
2254 01:21:32.422864 DBI_WR = 0x0
2255 01:21:32.425707 DBI_RD = 0x0
2256 01:21:32.425787 OTF = 0x1
2257 01:21:32.429095 ===================================
2258 01:21:32.435750 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2259 01:21:32.438873 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2260 01:21:32.442554 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2261 01:21:32.445488 ===================================
2262 01:21:32.448771 LPDDR4 DRAM CONFIGURATION
2263 01:21:32.452165 ===================================
2264 01:21:32.455723 EX_ROW_EN[0] = 0x10
2265 01:21:32.455803 EX_ROW_EN[1] = 0x0
2266 01:21:32.458804 LP4Y_EN = 0x0
2267 01:21:32.458884 WORK_FSP = 0x0
2268 01:21:32.462110 WL = 0x4
2269 01:21:32.462190 RL = 0x4
2270 01:21:32.465404 BL = 0x2
2271 01:21:32.465485 RPST = 0x0
2272 01:21:32.469061 RD_PRE = 0x0
2273 01:21:32.469141 WR_PRE = 0x1
2274 01:21:32.472029 WR_PST = 0x0
2275 01:21:32.472110 DBI_WR = 0x0
2276 01:21:32.475553 DBI_RD = 0x0
2277 01:21:32.475634 OTF = 0x1
2278 01:21:32.478938 ===================================
2279 01:21:32.486114 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2280 01:21:32.486195 ==
2281 01:21:32.488850 Dram Type= 6, Freq= 0, CH_0, rank 0
2282 01:21:32.495147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2283 01:21:32.495230 ==
2284 01:21:32.495294 [Duty_Offset_Calibration]
2285 01:21:32.498715 B0:2 B1:0 CA:4
2286 01:21:32.498796
2287 01:21:32.502125 [DutyScan_Calibration_Flow] k_type=0
2288 01:21:32.510551
2289 01:21:32.510636 ==CLK 0==
2290 01:21:32.513306 Final CLK duty delay cell = -4
2291 01:21:32.516669 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2292 01:21:32.520063 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2293 01:21:32.523349 [-4] AVG Duty = 4937%(X100)
2294 01:21:32.523429
2295 01:21:32.526399 CH0 CLK Duty spec in!! Max-Min= 187%
2296 01:21:32.529605 [DutyScan_Calibration_Flow] ====Done====
2297 01:21:32.529686
2298 01:21:32.533023 [DutyScan_Calibration_Flow] k_type=1
2299 01:21:32.549072
2300 01:21:32.549152 ==DQS 0 ==
2301 01:21:32.552165 Final DQS duty delay cell = -4
2302 01:21:32.555513 [-4] MAX Duty = 4969%(X100), DQS PI = 14
2303 01:21:32.558444 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2304 01:21:32.561918 [-4] AVG Duty = 4922%(X100)
2305 01:21:32.561999
2306 01:21:32.562062 ==DQS 1 ==
2307 01:21:32.565486 Final DQS duty delay cell = 0
2308 01:21:32.568945 [0] MAX Duty = 5125%(X100), DQS PI = 52
2309 01:21:32.572081 [0] MIN Duty = 5000%(X100), DQS PI = 0
2310 01:21:32.575229 [0] AVG Duty = 5062%(X100)
2311 01:21:32.575310
2312 01:21:32.578629 CH0 DQS 0 Duty spec in!! Max-Min= 93%
2313 01:21:32.578709
2314 01:21:32.582026 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2315 01:21:32.585259 [DutyScan_Calibration_Flow] ====Done====
2316 01:21:32.585340
2317 01:21:32.588948 [DutyScan_Calibration_Flow] k_type=3
2318 01:21:32.605561
2319 01:21:32.605642 ==DQM 0 ==
2320 01:21:32.609181 Final DQM duty delay cell = 0
2321 01:21:32.612216 [0] MAX Duty = 5125%(X100), DQS PI = 20
2322 01:21:32.615643 [0] MIN Duty = 4844%(X100), DQS PI = 50
2323 01:21:32.618953 [0] AVG Duty = 4984%(X100)
2324 01:21:32.619034
2325 01:21:32.619097 ==DQM 1 ==
2326 01:21:32.621993 Final DQM duty delay cell = 0
2327 01:21:32.625706 [0] MAX Duty = 4969%(X100), DQS PI = 2
2328 01:21:32.629078 [0] MIN Duty = 4875%(X100), DQS PI = 20
2329 01:21:32.632223 [0] AVG Duty = 4922%(X100)
2330 01:21:32.632304
2331 01:21:32.635694 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2332 01:21:32.635775
2333 01:21:32.638549 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2334 01:21:32.642475 [DutyScan_Calibration_Flow] ====Done====
2335 01:21:32.642556
2336 01:21:32.645480 [DutyScan_Calibration_Flow] k_type=2
2337 01:21:32.661919
2338 01:21:32.662000 ==DQ 0 ==
2339 01:21:32.665682 Final DQ duty delay cell = 0
2340 01:21:32.668378 [0] MAX Duty = 5125%(X100), DQS PI = 16
2341 01:21:32.671802 [0] MIN Duty = 4969%(X100), DQS PI = 58
2342 01:21:32.671943 [0] AVG Duty = 5047%(X100)
2343 01:21:32.675237
2344 01:21:32.675317 ==DQ 1 ==
2345 01:21:32.679061 Final DQ duty delay cell = 0
2346 01:21:32.682469 [0] MAX Duty = 5156%(X100), DQS PI = 4
2347 01:21:32.684899 [0] MIN Duty = 4907%(X100), DQS PI = 18
2348 01:21:32.684979 [0] AVG Duty = 5031%(X100)
2349 01:21:32.688483
2350 01:21:32.691783 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2351 01:21:32.691895
2352 01:21:32.694715 CH0 DQ 1 Duty spec in!! Max-Min= 249%
2353 01:21:32.698635 [DutyScan_Calibration_Flow] ====Done====
2354 01:21:32.698715 ==
2355 01:21:32.701648 Dram Type= 6, Freq= 0, CH_1, rank 0
2356 01:21:32.705031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2357 01:21:32.705113 ==
2358 01:21:32.708098 [Duty_Offset_Calibration]
2359 01:21:32.708178 B0:0 B1:-1 CA:3
2360 01:21:32.708241
2361 01:21:32.711708 [DutyScan_Calibration_Flow] k_type=0
2362 01:21:32.721171
2363 01:21:32.721251 ==CLK 0==
2364 01:21:32.724535 Final CLK duty delay cell = -4
2365 01:21:32.728043 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2366 01:21:32.731398 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2367 01:21:32.734416 [-4] AVG Duty = 4938%(X100)
2368 01:21:32.734497
2369 01:21:32.737762 CH1 CLK Duty spec in!! Max-Min= 124%
2370 01:21:32.741123 [DutyScan_Calibration_Flow] ====Done====
2371 01:21:32.741203
2372 01:21:32.744560 [DutyScan_Calibration_Flow] k_type=1
2373 01:21:32.760697
2374 01:21:32.760778 ==DQS 0 ==
2375 01:21:32.764448 Final DQS duty delay cell = 0
2376 01:21:32.767538 [0] MAX Duty = 5187%(X100), DQS PI = 28
2377 01:21:32.770806 [0] MIN Duty = 4938%(X100), DQS PI = 38
2378 01:21:32.773907 [0] AVG Duty = 5062%(X100)
2379 01:21:32.773988
2380 01:21:32.774051 ==DQS 1 ==
2381 01:21:32.777884 Final DQS duty delay cell = 0
2382 01:21:32.780815 [0] MAX Duty = 5156%(X100), DQS PI = 8
2383 01:21:32.783930 [0] MIN Duty = 5000%(X100), DQS PI = 26
2384 01:21:32.787052 [0] AVG Duty = 5078%(X100)
2385 01:21:32.787131
2386 01:21:32.790359 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2387 01:21:32.790440
2388 01:21:32.793650 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2389 01:21:32.797018 [DutyScan_Calibration_Flow] ====Done====
2390 01:21:32.797099
2391 01:21:32.800611 [DutyScan_Calibration_Flow] k_type=3
2392 01:21:32.817459
2393 01:21:32.817539 ==DQM 0 ==
2394 01:21:32.820480 Final DQM duty delay cell = 0
2395 01:21:32.823715 [0] MAX Duty = 5031%(X100), DQS PI = 26
2396 01:21:32.827171 [0] MIN Duty = 4813%(X100), DQS PI = 38
2397 01:21:32.830452 [0] AVG Duty = 4922%(X100)
2398 01:21:32.830533
2399 01:21:32.830595 ==DQM 1 ==
2400 01:21:32.833557 Final DQM duty delay cell = 0
2401 01:21:32.837179 [0] MAX Duty = 5000%(X100), DQS PI = 34
2402 01:21:32.840576 [0] MIN Duty = 4813%(X100), DQS PI = 0
2403 01:21:32.843698 [0] AVG Duty = 4906%(X100)
2404 01:21:32.843778
2405 01:21:32.846833 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2406 01:21:32.846914
2407 01:21:32.850224 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2408 01:21:32.853976 [DutyScan_Calibration_Flow] ====Done====
2409 01:21:32.854056
2410 01:21:32.856660 [DutyScan_Calibration_Flow] k_type=2
2411 01:21:32.872782
2412 01:21:32.872863 ==DQ 0 ==
2413 01:21:32.876004 Final DQ duty delay cell = -4
2414 01:21:32.879845 [-4] MAX Duty = 5000%(X100), DQS PI = 30
2415 01:21:32.882761 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2416 01:21:32.885947 [-4] AVG Duty = 4922%(X100)
2417 01:21:32.886026
2418 01:21:32.886088 ==DQ 1 ==
2419 01:21:32.889506 Final DQ duty delay cell = 0
2420 01:21:32.892571 [0] MAX Duty = 5031%(X100), DQS PI = 34
2421 01:21:32.896140 [0] MIN Duty = 4844%(X100), DQS PI = 62
2422 01:21:32.899200 [0] AVG Duty = 4937%(X100)
2423 01:21:32.899279
2424 01:21:32.902677 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2425 01:21:32.902757
2426 01:21:32.906754 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2427 01:21:32.909406 [DutyScan_Calibration_Flow] ====Done====
2428 01:21:32.912484 nWR fixed to 30
2429 01:21:32.916191 [ModeRegInit_LP4] CH0 RK0
2430 01:21:32.916271 [ModeRegInit_LP4] CH0 RK1
2431 01:21:32.919036 [ModeRegInit_LP4] CH1 RK0
2432 01:21:32.922415 [ModeRegInit_LP4] CH1 RK1
2433 01:21:32.922494 match AC timing 7
2434 01:21:32.929444 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2435 01:21:32.932658 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2436 01:21:32.935573 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2437 01:21:32.942070 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2438 01:21:32.945772 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2439 01:21:32.945852 ==
2440 01:21:32.948667 Dram Type= 6, Freq= 0, CH_0, rank 0
2441 01:21:32.952065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2442 01:21:32.952145 ==
2443 01:21:32.959081 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2444 01:21:32.965638 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2445 01:21:32.973392 [CA 0] Center 39 (9~70) winsize 62
2446 01:21:32.976326 [CA 1] Center 39 (9~70) winsize 62
2447 01:21:32.979772 [CA 2] Center 35 (5~66) winsize 62
2448 01:21:32.982979 [CA 3] Center 35 (5~66) winsize 62
2449 01:21:32.986490 [CA 4] Center 33 (3~64) winsize 62
2450 01:21:32.989710 [CA 5] Center 33 (3~63) winsize 61
2451 01:21:32.989790
2452 01:21:32.993378 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2453 01:21:32.993459
2454 01:21:32.996358 [CATrainingPosCal] consider 1 rank data
2455 01:21:32.999619 u2DelayCellTimex100 = 270/100 ps
2456 01:21:33.002720 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2457 01:21:33.009398 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2458 01:21:33.013583 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2459 01:21:33.015996 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2460 01:21:33.019347 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2461 01:21:33.022813 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2462 01:21:33.022901
2463 01:21:33.025855 CA PerBit enable=1, Macro0, CA PI delay=33
2464 01:21:33.025936
2465 01:21:33.029085 [CBTSetCACLKResult] CA Dly = 33
2466 01:21:33.032676 CS Dly: 7 (0~38)
2467 01:21:33.032757 ==
2468 01:21:33.035910 Dram Type= 6, Freq= 0, CH_0, rank 1
2469 01:21:33.039124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2470 01:21:33.039207 ==
2471 01:21:33.045853 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2472 01:21:33.048703 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2473 01:21:33.059218 [CA 0] Center 39 (9~70) winsize 62
2474 01:21:33.062362 [CA 1] Center 39 (9~70) winsize 62
2475 01:21:33.065922 [CA 2] Center 35 (5~66) winsize 62
2476 01:21:33.068900 [CA 3] Center 35 (5~66) winsize 62
2477 01:21:33.072745 [CA 4] Center 34 (4~65) winsize 62
2478 01:21:33.075691 [CA 5] Center 33 (3~63) winsize 61
2479 01:21:33.075773
2480 01:21:33.079340 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2481 01:21:33.079444
2482 01:21:33.082340 [CATrainingPosCal] consider 2 rank data
2483 01:21:33.086069 u2DelayCellTimex100 = 270/100 ps
2484 01:21:33.088964 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2485 01:21:33.095522 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2486 01:21:33.098985 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2487 01:21:33.102316 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2488 01:21:33.105593 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2489 01:21:33.108804 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2490 01:21:33.108885
2491 01:21:33.111878 CA PerBit enable=1, Macro0, CA PI delay=33
2492 01:21:33.112021
2493 01:21:33.115078 [CBTSetCACLKResult] CA Dly = 33
2494 01:21:33.115206 CS Dly: 8 (0~40)
2495 01:21:33.118763
2496 01:21:33.121768 ----->DramcWriteLeveling(PI) begin...
2497 01:21:33.121881 ==
2498 01:21:33.125046 Dram Type= 6, Freq= 0, CH_0, rank 0
2499 01:21:33.128632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2500 01:21:33.128722 ==
2501 01:21:33.131591 Write leveling (Byte 0): 33 => 33
2502 01:21:33.135195 Write leveling (Byte 1): 26 => 26
2503 01:21:33.138735 DramcWriteLeveling(PI) end<-----
2504 01:21:33.138827
2505 01:21:33.138890 ==
2506 01:21:33.141779 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 01:21:33.145145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 01:21:33.145231 ==
2509 01:21:33.148975 [Gating] SW mode calibration
2510 01:21:33.155331 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2511 01:21:33.161500 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2512 01:21:33.164844 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2513 01:21:33.168398 0 15 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2514 01:21:33.175110 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2515 01:21:33.178747 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2516 01:21:33.181753 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2517 01:21:33.188393 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 01:21:33.191733 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2519 01:21:33.195095 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2520 01:21:33.201443 1 0 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
2521 01:21:33.204666 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2522 01:21:33.208137 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 01:21:33.211331 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 01:21:33.218389 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 01:21:33.221441 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 01:21:33.224916 1 0 24 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
2527 01:21:33.231478 1 0 28 | B1->B0 | 2323 4545 | 0 1 | (0 0) (0 0)
2528 01:21:33.234961 1 1 0 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2529 01:21:33.238053 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2530 01:21:33.244383 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 01:21:33.248164 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 01:21:33.251365 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 01:21:33.258311 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 01:21:33.261105 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2535 01:21:33.264586 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2536 01:21:33.271578 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2537 01:21:33.274663 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2538 01:21:33.278017 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 01:21:33.284438 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 01:21:33.287869 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 01:21:33.291117 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 01:21:33.297783 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 01:21:33.301447 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 01:21:33.304471 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 01:21:33.310661 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 01:21:33.314496 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 01:21:33.317383 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 01:21:33.323848 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 01:21:33.327339 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 01:21:33.330841 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2551 01:21:33.337733 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2552 01:21:33.340828 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2553 01:21:33.343931 Total UI for P1: 0, mck2ui 16
2554 01:21:33.347475 best dqsien dly found for B0: ( 1, 3, 26)
2555 01:21:33.350475 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 01:21:33.353722 Total UI for P1: 0, mck2ui 16
2557 01:21:33.356905 best dqsien dly found for B1: ( 1, 4, 0)
2558 01:21:33.360184 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2559 01:21:33.363776 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2560 01:21:33.363860
2561 01:21:33.370560 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2562 01:21:33.373468 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2563 01:21:33.373552 [Gating] SW calibration Done
2564 01:21:33.377154 ==
2565 01:21:33.377239 Dram Type= 6, Freq= 0, CH_0, rank 0
2566 01:21:33.383590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2567 01:21:33.383675 ==
2568 01:21:33.383760 RX Vref Scan: 0
2569 01:21:33.383864
2570 01:21:33.386836 RX Vref 0 -> 0, step: 1
2571 01:21:33.386920
2572 01:21:33.390271 RX Delay -40 -> 252, step: 8
2573 01:21:33.393715 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2574 01:21:33.397203 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2575 01:21:33.400191 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2576 01:21:33.406687 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2577 01:21:33.410194 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2578 01:21:33.413467 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2579 01:21:33.416859 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2580 01:21:33.420286 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2581 01:21:33.426773 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2582 01:21:33.430034 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2583 01:21:33.433675 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2584 01:21:33.436748 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2585 01:21:33.440264 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2586 01:21:33.446612 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2587 01:21:33.449911 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2588 01:21:33.453419 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2589 01:21:33.453503 ==
2590 01:21:33.456656 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 01:21:33.460036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 01:21:33.463006 ==
2593 01:21:33.463090 DQS Delay:
2594 01:21:33.463174 DQS0 = 0, DQS1 = 0
2595 01:21:33.466503 DQM Delay:
2596 01:21:33.466586 DQM0 = 117, DQM1 = 107
2597 01:21:33.469616 DQ Delay:
2598 01:21:33.473146 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =111
2599 01:21:33.476684 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2600 01:21:33.479393 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2601 01:21:33.482783 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2602 01:21:33.482867
2603 01:21:33.482953
2604 01:21:33.483033 ==
2605 01:21:33.486027 Dram Type= 6, Freq= 0, CH_0, rank 0
2606 01:21:33.489822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2607 01:21:33.489906 ==
2608 01:21:33.489990
2609 01:21:33.492772
2610 01:21:33.492855 TX Vref Scan disable
2611 01:21:33.495959 == TX Byte 0 ==
2612 01:21:33.499087 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2613 01:21:33.502579 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2614 01:21:33.506148 == TX Byte 1 ==
2615 01:21:33.509574 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2616 01:21:33.512426 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2617 01:21:33.512510 ==
2618 01:21:33.515959 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 01:21:33.522618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 01:21:33.522704 ==
2621 01:21:33.534658 TX Vref=22, minBit 4, minWin=24, winSum=405
2622 01:21:33.537019 TX Vref=24, minBit 1, minWin=25, winSum=415
2623 01:21:33.540488 TX Vref=26, minBit 1, minWin=25, winSum=419
2624 01:21:33.543818 TX Vref=28, minBit 1, minWin=26, winSum=425
2625 01:21:33.547369 TX Vref=30, minBit 4, minWin=26, winSum=429
2626 01:21:33.554167 TX Vref=32, minBit 1, minWin=26, winSum=425
2627 01:21:33.556861 [TxChooseVref] Worse bit 4, Min win 26, Win sum 429, Final Vref 30
2628 01:21:33.556945
2629 01:21:33.560607 Final TX Range 1 Vref 30
2630 01:21:33.560691
2631 01:21:33.560775 ==
2632 01:21:33.563795 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 01:21:33.566943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 01:21:33.567028 ==
2635 01:21:33.570362
2636 01:21:33.570478
2637 01:21:33.570562 TX Vref Scan disable
2638 01:21:33.573768 == TX Byte 0 ==
2639 01:21:33.577341 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2640 01:21:33.583449 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2641 01:21:33.583534 == TX Byte 1 ==
2642 01:21:33.587220 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2643 01:21:33.593450 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2644 01:21:33.593535
2645 01:21:33.593619 [DATLAT]
2646 01:21:33.593700 Freq=1200, CH0 RK0
2647 01:21:33.593778
2648 01:21:33.596899 DATLAT Default: 0xd
2649 01:21:33.596991 0, 0xFFFF, sum = 0
2650 01:21:33.600302 1, 0xFFFF, sum = 0
2651 01:21:33.603343 2, 0xFFFF, sum = 0
2652 01:21:33.603452 3, 0xFFFF, sum = 0
2653 01:21:33.606768 4, 0xFFFF, sum = 0
2654 01:21:33.606859 5, 0xFFFF, sum = 0
2655 01:21:33.610024 6, 0xFFFF, sum = 0
2656 01:21:33.610124 7, 0xFFFF, sum = 0
2657 01:21:33.613809 8, 0xFFFF, sum = 0
2658 01:21:33.613882 9, 0xFFFF, sum = 0
2659 01:21:33.616664 10, 0xFFFF, sum = 0
2660 01:21:33.616751 11, 0xFFFF, sum = 0
2661 01:21:33.619989 12, 0x0, sum = 1
2662 01:21:33.620064 13, 0x0, sum = 2
2663 01:21:33.623130 14, 0x0, sum = 3
2664 01:21:33.623234 15, 0x0, sum = 4
2665 01:21:33.626814 best_step = 13
2666 01:21:33.626919
2667 01:21:33.627006 ==
2668 01:21:33.630089 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 01:21:33.633821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 01:21:33.633902 ==
2671 01:21:33.633967 RX Vref Scan: 1
2672 01:21:33.636642
2673 01:21:33.636718 Set Vref Range= 32 -> 127
2674 01:21:33.636780
2675 01:21:33.639674 RX Vref 32 -> 127, step: 1
2676 01:21:33.639776
2677 01:21:33.643096 RX Delay -21 -> 252, step: 4
2678 01:21:33.643170
2679 01:21:33.646925 Set Vref, RX VrefLevel [Byte0]: 32
2680 01:21:33.649966 [Byte1]: 32
2681 01:21:33.650043
2682 01:21:33.653438 Set Vref, RX VrefLevel [Byte0]: 33
2683 01:21:33.656495 [Byte1]: 33
2684 01:21:33.660346
2685 01:21:33.660446 Set Vref, RX VrefLevel [Byte0]: 34
2686 01:21:33.663971 [Byte1]: 34
2687 01:21:33.668404
2688 01:21:33.668477 Set Vref, RX VrefLevel [Byte0]: 35
2689 01:21:33.671776 [Byte1]: 35
2690 01:21:33.675757
2691 01:21:33.675867 Set Vref, RX VrefLevel [Byte0]: 36
2692 01:21:33.679728 [Byte1]: 36
2693 01:21:33.683858
2694 01:21:33.683963 Set Vref, RX VrefLevel [Byte0]: 37
2695 01:21:33.687400 [Byte1]: 37
2696 01:21:33.692044
2697 01:21:33.692133 Set Vref, RX VrefLevel [Byte0]: 38
2698 01:21:33.695594 [Byte1]: 38
2699 01:21:33.699936
2700 01:21:33.700013 Set Vref, RX VrefLevel [Byte0]: 39
2701 01:21:33.703648 [Byte1]: 39
2702 01:21:33.707677
2703 01:21:33.707748 Set Vref, RX VrefLevel [Byte0]: 40
2704 01:21:33.710954 [Byte1]: 40
2705 01:21:33.715590
2706 01:21:33.715688 Set Vref, RX VrefLevel [Byte0]: 41
2707 01:21:33.718917 [Byte1]: 41
2708 01:21:33.723390
2709 01:21:33.723474 Set Vref, RX VrefLevel [Byte0]: 42
2710 01:21:33.726792 [Byte1]: 42
2711 01:21:33.731282
2712 01:21:33.731356 Set Vref, RX VrefLevel [Byte0]: 43
2713 01:21:33.734951 [Byte1]: 43
2714 01:21:33.739433
2715 01:21:33.739540 Set Vref, RX VrefLevel [Byte0]: 44
2716 01:21:33.742801 [Byte1]: 44
2717 01:21:33.747270
2718 01:21:33.747352 Set Vref, RX VrefLevel [Byte0]: 45
2719 01:21:33.750877 [Byte1]: 45
2720 01:21:33.755376
2721 01:21:33.755474 Set Vref, RX VrefLevel [Byte0]: 46
2722 01:21:33.758509 [Byte1]: 46
2723 01:21:33.763561
2724 01:21:33.763659 Set Vref, RX VrefLevel [Byte0]: 47
2725 01:21:33.766829 [Byte1]: 47
2726 01:21:33.771374
2727 01:21:33.771444 Set Vref, RX VrefLevel [Byte0]: 48
2728 01:21:33.774617 [Byte1]: 48
2729 01:21:33.779149
2730 01:21:33.779240 Set Vref, RX VrefLevel [Byte0]: 49
2731 01:21:33.782605 [Byte1]: 49
2732 01:21:33.786831
2733 01:21:33.786935 Set Vref, RX VrefLevel [Byte0]: 50
2734 01:21:33.790505 [Byte1]: 50
2735 01:21:33.794974
2736 01:21:33.795080 Set Vref, RX VrefLevel [Byte0]: 51
2737 01:21:33.798159 [Byte1]: 51
2738 01:21:33.802924
2739 01:21:33.802998 Set Vref, RX VrefLevel [Byte0]: 52
2740 01:21:33.806555 [Byte1]: 52
2741 01:21:33.810808
2742 01:21:33.810910 Set Vref, RX VrefLevel [Byte0]: 53
2743 01:21:33.813901 [Byte1]: 53
2744 01:21:33.818721
2745 01:21:33.818817 Set Vref, RX VrefLevel [Byte0]: 54
2746 01:21:33.822061 [Byte1]: 54
2747 01:21:33.826701
2748 01:21:33.826786 Set Vref, RX VrefLevel [Byte0]: 55
2749 01:21:33.829975 [Byte1]: 55
2750 01:21:33.834657
2751 01:21:33.834732 Set Vref, RX VrefLevel [Byte0]: 56
2752 01:21:33.838347 [Byte1]: 56
2753 01:21:33.842456
2754 01:21:33.842527 Set Vref, RX VrefLevel [Byte0]: 57
2755 01:21:33.845941 [Byte1]: 57
2756 01:21:33.850331
2757 01:21:33.850402 Set Vref, RX VrefLevel [Byte0]: 58
2758 01:21:33.853704 [Byte1]: 58
2759 01:21:33.858317
2760 01:21:33.858385 Set Vref, RX VrefLevel [Byte0]: 59
2761 01:21:33.861671 [Byte1]: 59
2762 01:21:33.866153
2763 01:21:33.866229 Set Vref, RX VrefLevel [Byte0]: 60
2764 01:21:33.869812 [Byte1]: 60
2765 01:21:33.874184
2766 01:21:33.874253 Set Vref, RX VrefLevel [Byte0]: 61
2767 01:21:33.877542 [Byte1]: 61
2768 01:21:33.882462
2769 01:21:33.882538 Set Vref, RX VrefLevel [Byte0]: 62
2770 01:21:33.885327 [Byte1]: 62
2771 01:21:33.890176
2772 01:21:33.890250 Set Vref, RX VrefLevel [Byte0]: 63
2773 01:21:33.893720 [Byte1]: 63
2774 01:21:33.897914
2775 01:21:33.897983 Set Vref, RX VrefLevel [Byte0]: 64
2776 01:21:33.901129 [Byte1]: 64
2777 01:21:33.905821
2778 01:21:33.905892 Set Vref, RX VrefLevel [Byte0]: 65
2779 01:21:33.909345 [Byte1]: 65
2780 01:21:33.913743
2781 01:21:33.913817 Set Vref, RX VrefLevel [Byte0]: 66
2782 01:21:33.917172 [Byte1]: 66
2783 01:21:33.921760
2784 01:21:33.921829 Set Vref, RX VrefLevel [Byte0]: 67
2785 01:21:33.925001 [Byte1]: 67
2786 01:21:33.929680
2787 01:21:33.929749 Set Vref, RX VrefLevel [Byte0]: 68
2788 01:21:33.932854 [Byte1]: 68
2789 01:21:33.937576
2790 01:21:33.937646 Set Vref, RX VrefLevel [Byte0]: 69
2791 01:21:33.940868 [Byte1]: 69
2792 01:21:33.945468
2793 01:21:33.945541 Final RX Vref Byte 0 = 53 to rank0
2794 01:21:33.948978 Final RX Vref Byte 1 = 45 to rank0
2795 01:21:33.952102 Final RX Vref Byte 0 = 53 to rank1
2796 01:21:33.955437 Final RX Vref Byte 1 = 45 to rank1==
2797 01:21:33.959042 Dram Type= 6, Freq= 0, CH_0, rank 0
2798 01:21:33.966092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2799 01:21:33.966164 ==
2800 01:21:33.966225 DQS Delay:
2801 01:21:33.966283 DQS0 = 0, DQS1 = 0
2802 01:21:33.968805 DQM Delay:
2803 01:21:33.968877 DQM0 = 117, DQM1 = 102
2804 01:21:33.972074 DQ Delay:
2805 01:21:33.975165 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2806 01:21:33.978552 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2807 01:21:33.981784 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2808 01:21:33.985497 DQ12 =110, DQ13 =108, DQ14 =112, DQ15 =110
2809 01:21:33.985571
2810 01:21:33.985632
2811 01:21:33.991839 [DQSOSCAuto] RK0, (LSB)MR18= 0x1fd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
2812 01:21:33.995788 CH0 RK0: MR19=403, MR18=1FD
2813 01:21:34.002223 CH0_RK0: MR19=0x403, MR18=0x1FD, DQSOSC=409, MR23=63, INC=39, DEC=26
2814 01:21:34.002301
2815 01:21:34.005398 ----->DramcWriteLeveling(PI) begin...
2816 01:21:34.005476 ==
2817 01:21:34.008627 Dram Type= 6, Freq= 0, CH_0, rank 1
2818 01:21:34.011842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2819 01:21:34.015212 ==
2820 01:21:34.015283 Write leveling (Byte 0): 33 => 33
2821 01:21:34.018398 Write leveling (Byte 1): 27 => 27
2822 01:21:34.021827 DramcWriteLeveling(PI) end<-----
2823 01:21:34.021900
2824 01:21:34.021961 ==
2825 01:21:34.025207 Dram Type= 6, Freq= 0, CH_0, rank 1
2826 01:21:34.031831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2827 01:21:34.031943 ==
2828 01:21:34.032010 [Gating] SW mode calibration
2829 01:21:34.041515 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2830 01:21:34.044918 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2831 01:21:34.051549 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2832 01:21:34.054582 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2833 01:21:34.057691 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2834 01:21:34.064229 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2835 01:21:34.067832 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 01:21:34.071015 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 01:21:34.077812 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 0)
2838 01:21:34.081248 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
2839 01:21:34.084508 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2840 01:21:34.090632 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2841 01:21:34.093861 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 01:21:34.097477 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 01:21:34.104175 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 01:21:34.107249 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 01:21:34.110322 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2846 01:21:34.117381 1 0 28 | B1->B0 | 2929 4646 | 1 0 | (0 0) (0 0)
2847 01:21:34.120203 1 1 0 | B1->B0 | 3534 4646 | 1 0 | (0 0) (0 0)
2848 01:21:34.123722 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2849 01:21:34.130967 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 01:21:34.133494 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 01:21:34.136743 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 01:21:34.143354 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 01:21:34.146794 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2854 01:21:34.149912 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2855 01:21:34.156373 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2856 01:21:34.160003 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 01:21:34.163316 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 01:21:34.169731 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 01:21:34.173588 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 01:21:34.176604 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 01:21:34.182956 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 01:21:34.186461 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 01:21:34.189466 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 01:21:34.196202 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 01:21:34.199508 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 01:21:34.203325 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 01:21:34.209924 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 01:21:34.213088 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 01:21:34.216153 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2870 01:21:34.222579 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2871 01:21:34.225958 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2872 01:21:34.229571 Total UI for P1: 0, mck2ui 16
2873 01:21:34.232758 best dqsien dly found for B0: ( 1, 3, 26)
2874 01:21:34.236531 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 01:21:34.239539 Total UI for P1: 0, mck2ui 16
2876 01:21:34.242796 best dqsien dly found for B1: ( 1, 4, 0)
2877 01:21:34.246301 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2878 01:21:34.249127 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2879 01:21:34.249196
2880 01:21:34.252499 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2881 01:21:34.259294 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2882 01:21:34.259366 [Gating] SW calibration Done
2883 01:21:34.259431 ==
2884 01:21:34.262402 Dram Type= 6, Freq= 0, CH_0, rank 1
2885 01:21:34.269019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2886 01:21:34.269094 ==
2887 01:21:34.269155 RX Vref Scan: 0
2888 01:21:34.269213
2889 01:21:34.272383 RX Vref 0 -> 0, step: 1
2890 01:21:34.272458
2891 01:21:34.276042 RX Delay -40 -> 252, step: 8
2892 01:21:34.279380 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2893 01:21:34.282108 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2894 01:21:34.285749 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2895 01:21:34.292241 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2896 01:21:34.295539 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2897 01:21:34.298857 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2898 01:21:34.302063 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2899 01:21:34.305632 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2900 01:21:34.312132 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2901 01:21:34.315538 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2902 01:21:34.318709 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2903 01:21:34.322424 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2904 01:21:34.325345 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2905 01:21:34.332581 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2906 01:21:34.335252 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2907 01:21:34.338834 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2908 01:21:34.338919 ==
2909 01:21:34.342260 Dram Type= 6, Freq= 0, CH_0, rank 1
2910 01:21:34.345999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 01:21:34.346081 ==
2912 01:21:34.348753 DQS Delay:
2913 01:21:34.348833 DQS0 = 0, DQS1 = 0
2914 01:21:34.352042 DQM Delay:
2915 01:21:34.352122 DQM0 = 115, DQM1 = 106
2916 01:21:34.355566 DQ Delay:
2917 01:21:34.358401 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2918 01:21:34.361852 DQ4 =119, DQ5 =103, DQ6 =127, DQ7 =119
2919 01:21:34.365265 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2920 01:21:34.367947 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2921 01:21:34.368043
2922 01:21:34.368107
2923 01:21:34.368166 ==
2924 01:21:34.371769 Dram Type= 6, Freq= 0, CH_0, rank 1
2925 01:21:34.374931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2926 01:21:34.375016 ==
2927 01:21:34.375080
2928 01:21:34.375138
2929 01:21:34.378500 TX Vref Scan disable
2930 01:21:34.381644 == TX Byte 0 ==
2931 01:21:34.384619 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2932 01:21:34.388086 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2933 01:21:34.391250 == TX Byte 1 ==
2934 01:21:34.395150 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2935 01:21:34.398315 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2936 01:21:34.398415 ==
2937 01:21:34.401208 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 01:21:34.407922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 01:21:34.408000 ==
2940 01:21:34.418552 TX Vref=22, minBit 3, minWin=25, winSum=417
2941 01:21:34.422052 TX Vref=24, minBit 12, minWin=25, winSum=420
2942 01:21:34.425946 TX Vref=26, minBit 10, minWin=25, winSum=427
2943 01:21:34.428973 TX Vref=28, minBit 4, minWin=26, winSum=427
2944 01:21:34.432008 TX Vref=30, minBit 14, minWin=25, winSum=426
2945 01:21:34.438648 TX Vref=32, minBit 13, minWin=25, winSum=424
2946 01:21:34.441940 [TxChooseVref] Worse bit 4, Min win 26, Win sum 427, Final Vref 28
2947 01:21:34.442029
2948 01:21:34.445322 Final TX Range 1 Vref 28
2949 01:21:34.445397
2950 01:21:34.445467 ==
2951 01:21:34.448752 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 01:21:34.451860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 01:21:34.455117 ==
2954 01:21:34.455220
2955 01:21:34.455308
2956 01:21:34.455394 TX Vref Scan disable
2957 01:21:34.458669 == TX Byte 0 ==
2958 01:21:34.462411 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2959 01:21:34.466019 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2960 01:21:34.469545 == TX Byte 1 ==
2961 01:21:34.472641 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2962 01:21:34.475506 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2963 01:21:34.478941
2964 01:21:34.479043 [DATLAT]
2965 01:21:34.479133 Freq=1200, CH0 RK1
2966 01:21:34.479229
2967 01:21:34.482179 DATLAT Default: 0xd
2968 01:21:34.482260 0, 0xFFFF, sum = 0
2969 01:21:34.485589 1, 0xFFFF, sum = 0
2970 01:21:34.485664 2, 0xFFFF, sum = 0
2971 01:21:34.488683 3, 0xFFFF, sum = 0
2972 01:21:34.488757 4, 0xFFFF, sum = 0
2973 01:21:34.492439 5, 0xFFFF, sum = 0
2974 01:21:34.495453 6, 0xFFFF, sum = 0
2975 01:21:34.495532 7, 0xFFFF, sum = 0
2976 01:21:34.498631 8, 0xFFFF, sum = 0
2977 01:21:34.498702 9, 0xFFFF, sum = 0
2978 01:21:34.502137 10, 0xFFFF, sum = 0
2979 01:21:34.502209 11, 0xFFFF, sum = 0
2980 01:21:34.505510 12, 0x0, sum = 1
2981 01:21:34.505586 13, 0x0, sum = 2
2982 01:21:34.508615 14, 0x0, sum = 3
2983 01:21:34.508687 15, 0x0, sum = 4
2984 01:21:34.508750 best_step = 13
2985 01:21:34.512112
2986 01:21:34.512186 ==
2987 01:21:34.515276 Dram Type= 6, Freq= 0, CH_0, rank 1
2988 01:21:34.518521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2989 01:21:34.518595 ==
2990 01:21:34.518662 RX Vref Scan: 0
2991 01:21:34.518720
2992 01:21:34.522257 RX Vref 0 -> 0, step: 1
2993 01:21:34.522326
2994 01:21:34.525415 RX Delay -21 -> 252, step: 4
2995 01:21:34.528970 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
2996 01:21:34.535392 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
2997 01:21:34.538944 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
2998 01:21:34.542029 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
2999 01:21:34.545175 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3000 01:21:34.548706 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3001 01:21:34.555059 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3002 01:21:34.558601 iDelay=195, Bit 7, Center 120 (55 ~ 186) 132
3003 01:21:34.561661 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3004 01:21:34.565077 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3005 01:21:34.568558 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3006 01:21:34.575186 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3007 01:21:34.578283 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3008 01:21:34.581952 iDelay=195, Bit 13, Center 108 (43 ~ 174) 132
3009 01:21:34.585217 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3010 01:21:34.588738 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3011 01:21:34.591882 ==
3012 01:21:34.591995 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 01:21:34.598914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 01:21:34.598993 ==
3015 01:21:34.599055 DQS Delay:
3016 01:21:34.601801 DQS0 = 0, DQS1 = 0
3017 01:21:34.601876 DQM Delay:
3018 01:21:34.605146 DQM0 = 115, DQM1 = 104
3019 01:21:34.605216 DQ Delay:
3020 01:21:34.608534 DQ0 =114, DQ1 =116, DQ2 =112, DQ3 =112
3021 01:21:34.612161 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =120
3022 01:21:34.614791 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
3023 01:21:34.618076 DQ12 =110, DQ13 =108, DQ14 =116, DQ15 =112
3024 01:21:34.618149
3025 01:21:34.618210
3026 01:21:34.628454 [DQSOSCAuto] RK1, (LSB)MR18= 0xfaf8, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 412 ps
3027 01:21:34.628547 CH0 RK1: MR19=303, MR18=FAF8
3028 01:21:34.634552 CH0_RK1: MR19=0x303, MR18=0xFAF8, DQSOSC=412, MR23=63, INC=38, DEC=25
3029 01:21:34.638177 [RxdqsGatingPostProcess] freq 1200
3030 01:21:34.644964 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3031 01:21:34.648200 best DQS0 dly(2T, 0.5T) = (0, 11)
3032 01:21:34.651323 best DQS1 dly(2T, 0.5T) = (0, 12)
3033 01:21:34.654616 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3034 01:21:34.657649 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3035 01:21:34.661073 best DQS0 dly(2T, 0.5T) = (0, 11)
3036 01:21:34.664381 best DQS1 dly(2T, 0.5T) = (0, 12)
3037 01:21:34.668076 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3038 01:21:34.671766 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3039 01:21:34.671848 Pre-setting of DQS Precalculation
3040 01:21:34.677800 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3041 01:21:34.677882 ==
3042 01:21:34.681072 Dram Type= 6, Freq= 0, CH_1, rank 0
3043 01:21:34.684547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 01:21:34.684628 ==
3045 01:21:34.691060 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3046 01:21:34.697848 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3047 01:21:34.705176 [CA 0] Center 38 (8~68) winsize 61
3048 01:21:34.708315 [CA 1] Center 37 (7~68) winsize 62
3049 01:21:34.712021 [CA 2] Center 35 (5~65) winsize 61
3050 01:21:34.714980 [CA 3] Center 34 (5~64) winsize 60
3051 01:21:34.718347 [CA 4] Center 34 (4~65) winsize 62
3052 01:21:34.721668 [CA 5] Center 34 (4~64) winsize 61
3053 01:21:34.721739
3054 01:21:34.725237 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3055 01:21:34.725309
3056 01:21:34.728260 [CATrainingPosCal] consider 1 rank data
3057 01:21:34.731596 u2DelayCellTimex100 = 270/100 ps
3058 01:21:34.734929 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3059 01:21:34.738506 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3060 01:21:34.744953 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3061 01:21:34.748328 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
3062 01:21:34.751508 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3063 01:21:34.754745 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3064 01:21:34.754817
3065 01:21:34.757936 CA PerBit enable=1, Macro0, CA PI delay=34
3066 01:21:34.758007
3067 01:21:34.761302 [CBTSetCACLKResult] CA Dly = 34
3068 01:21:34.761376 CS Dly: 5 (0~36)
3069 01:21:34.764724 ==
3070 01:21:34.767786 Dram Type= 6, Freq= 0, CH_1, rank 1
3071 01:21:34.771651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3072 01:21:34.771729 ==
3073 01:21:34.777789 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3074 01:21:34.781482 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3075 01:21:34.791006 [CA 0] Center 38 (8~68) winsize 61
3076 01:21:34.794123 [CA 1] Center 38 (7~69) winsize 63
3077 01:21:34.797029 [CA 2] Center 35 (5~65) winsize 61
3078 01:21:34.800618 [CA 3] Center 33 (3~64) winsize 62
3079 01:21:34.804041 [CA 4] Center 34 (4~64) winsize 61
3080 01:21:34.807100 [CA 5] Center 33 (3~63) winsize 61
3081 01:21:34.807169
3082 01:21:34.810379 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3083 01:21:34.810454
3084 01:21:34.813942 [CATrainingPosCal] consider 2 rank data
3085 01:21:34.817130 u2DelayCellTimex100 = 270/100 ps
3086 01:21:34.821277 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3087 01:21:34.827391 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3088 01:21:34.830790 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3089 01:21:34.833762 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3090 01:21:34.837120 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3091 01:21:34.840229 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3092 01:21:34.840301
3093 01:21:34.843794 CA PerBit enable=1, Macro0, CA PI delay=33
3094 01:21:34.843916
3095 01:21:34.847266 [CBTSetCACLKResult] CA Dly = 33
3096 01:21:34.847342 CS Dly: 6 (0~39)
3097 01:21:34.849948
3098 01:21:34.854109 ----->DramcWriteLeveling(PI) begin...
3099 01:21:34.854182 ==
3100 01:21:34.856650 Dram Type= 6, Freq= 0, CH_1, rank 0
3101 01:21:34.860163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3102 01:21:34.860235 ==
3103 01:21:34.863367 Write leveling (Byte 0): 25 => 25
3104 01:21:34.867029 Write leveling (Byte 1): 27 => 27
3105 01:21:34.869958 DramcWriteLeveling(PI) end<-----
3106 01:21:34.870037
3107 01:21:34.870099 ==
3108 01:21:34.873888 Dram Type= 6, Freq= 0, CH_1, rank 0
3109 01:21:34.876796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3110 01:21:34.876895 ==
3111 01:21:34.880388 [Gating] SW mode calibration
3112 01:21:34.887104 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3113 01:21:34.893435 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3114 01:21:34.896566 0 15 0 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
3115 01:21:34.900635 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3116 01:21:34.906877 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 01:21:34.909908 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 01:21:34.912958 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 01:21:34.919704 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 01:21:34.923162 0 15 24 | B1->B0 | 3434 3232 | 0 0 | (0 1) (0 0)
3121 01:21:34.926625 0 15 28 | B1->B0 | 2b2b 2525 | 0 0 | (1 0) (1 0)
3122 01:21:34.933098 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3123 01:21:34.936275 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3124 01:21:34.939803 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 01:21:34.946591 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 01:21:34.949561 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 01:21:34.953409 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 01:21:34.959581 1 0 24 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
3129 01:21:34.963011 1 0 28 | B1->B0 | 4141 4545 | 0 0 | (1 1) (0 0)
3130 01:21:34.966359 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3131 01:21:34.969385 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 01:21:34.976049 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 01:21:34.979693 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 01:21:34.982750 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 01:21:34.989157 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 01:21:34.993110 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 01:21:34.996082 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3138 01:21:35.002616 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 01:21:35.006286 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 01:21:35.009364 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 01:21:35.016325 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 01:21:35.019160 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 01:21:35.022831 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 01:21:35.029338 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 01:21:35.032378 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 01:21:35.035699 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 01:21:35.042564 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 01:21:35.045356 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 01:21:35.049130 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 01:21:35.055503 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 01:21:35.058674 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 01:21:35.061852 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3153 01:21:35.068424 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3154 01:21:35.072310 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 01:21:35.075513 Total UI for P1: 0, mck2ui 16
3156 01:21:35.078623 best dqsien dly found for B0: ( 1, 3, 26)
3157 01:21:35.081606 Total UI for P1: 0, mck2ui 16
3158 01:21:35.085174 best dqsien dly found for B1: ( 1, 3, 28)
3159 01:21:35.088424 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3160 01:21:35.092155 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3161 01:21:35.092234
3162 01:21:35.094892 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3163 01:21:35.098519 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3164 01:21:35.101530 [Gating] SW calibration Done
3165 01:21:35.101620 ==
3166 01:21:35.104917 Dram Type= 6, Freq= 0, CH_1, rank 0
3167 01:21:35.111718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3168 01:21:35.111817 ==
3169 01:21:35.111911 RX Vref Scan: 0
3170 01:21:35.112014
3171 01:21:35.114860 RX Vref 0 -> 0, step: 1
3172 01:21:35.114928
3173 01:21:35.118568 RX Delay -40 -> 252, step: 8
3174 01:21:35.121267 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3175 01:21:35.124989 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3176 01:21:35.128124 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3177 01:21:35.135016 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3178 01:21:35.138265 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3179 01:21:35.141487 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3180 01:21:35.144568 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3181 01:21:35.147758 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3182 01:21:35.151714 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3183 01:21:35.158124 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3184 01:21:35.161697 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3185 01:21:35.164965 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3186 01:21:35.167685 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3187 01:21:35.174501 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3188 01:21:35.178092 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3189 01:21:35.181600 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3190 01:21:35.181674 ==
3191 01:21:35.184354 Dram Type= 6, Freq= 0, CH_1, rank 0
3192 01:21:35.187971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3193 01:21:35.188043 ==
3194 01:21:35.191151 DQS Delay:
3195 01:21:35.191231 DQS0 = 0, DQS1 = 0
3196 01:21:35.194566 DQM Delay:
3197 01:21:35.194637 DQM0 = 115, DQM1 = 112
3198 01:21:35.194698 DQ Delay:
3199 01:21:35.200935 DQ0 =123, DQ1 =107, DQ2 =107, DQ3 =115
3200 01:21:35.204625 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3201 01:21:35.208198 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3202 01:21:35.210843 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3203 01:21:35.210913
3204 01:21:35.210974
3205 01:21:35.211030 ==
3206 01:21:35.214948 Dram Type= 6, Freq= 0, CH_1, rank 0
3207 01:21:35.217520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3208 01:21:35.217592 ==
3209 01:21:35.217652
3210 01:21:35.217709
3211 01:21:35.221030 TX Vref Scan disable
3212 01:21:35.223999 == TX Byte 0 ==
3213 01:21:35.227373 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3214 01:21:35.231294 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3215 01:21:35.234335 == TX Byte 1 ==
3216 01:21:35.237344 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3217 01:21:35.240706 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3218 01:21:35.240796 ==
3219 01:21:35.243887 Dram Type= 6, Freq= 0, CH_1, rank 0
3220 01:21:35.250606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3221 01:21:35.250687 ==
3222 01:21:35.260750 TX Vref=22, minBit 9, minWin=23, winSum=409
3223 01:21:35.264347 TX Vref=24, minBit 3, minWin=25, winSum=417
3224 01:21:35.267579 TX Vref=26, minBit 9, minWin=25, winSum=423
3225 01:21:35.271059 TX Vref=28, minBit 9, minWin=24, winSum=422
3226 01:21:35.274238 TX Vref=30, minBit 9, minWin=24, winSum=422
3227 01:21:35.280512 TX Vref=32, minBit 2, minWin=26, winSum=430
3228 01:21:35.283841 [TxChooseVref] Worse bit 2, Min win 26, Win sum 430, Final Vref 32
3229 01:21:35.283959
3230 01:21:35.287621 Final TX Range 1 Vref 32
3231 01:21:35.287693
3232 01:21:35.287753 ==
3233 01:21:35.290715 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 01:21:35.293626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3235 01:21:35.296743 ==
3236 01:21:35.296823
3237 01:21:35.296890
3238 01:21:35.296947 TX Vref Scan disable
3239 01:21:35.300307 == TX Byte 0 ==
3240 01:21:35.303783 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3241 01:21:35.310269 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3242 01:21:35.310349 == TX Byte 1 ==
3243 01:21:35.313684 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3244 01:21:35.320403 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3245 01:21:35.320478
3246 01:21:35.320545 [DATLAT]
3247 01:21:35.320605 Freq=1200, CH1 RK0
3248 01:21:35.320660
3249 01:21:35.323365 DATLAT Default: 0xd
3250 01:21:35.327048 0, 0xFFFF, sum = 0
3251 01:21:35.327120 1, 0xFFFF, sum = 0
3252 01:21:35.330513 2, 0xFFFF, sum = 0
3253 01:21:35.330582 3, 0xFFFF, sum = 0
3254 01:21:35.333605 4, 0xFFFF, sum = 0
3255 01:21:35.333689 5, 0xFFFF, sum = 0
3256 01:21:35.337365 6, 0xFFFF, sum = 0
3257 01:21:35.337435 7, 0xFFFF, sum = 0
3258 01:21:35.340185 8, 0xFFFF, sum = 0
3259 01:21:35.340259 9, 0xFFFF, sum = 0
3260 01:21:35.343787 10, 0xFFFF, sum = 0
3261 01:21:35.343866 11, 0xFFFF, sum = 0
3262 01:21:35.346752 12, 0x0, sum = 1
3263 01:21:35.346828 13, 0x0, sum = 2
3264 01:21:35.350315 14, 0x0, sum = 3
3265 01:21:35.350384 15, 0x0, sum = 4
3266 01:21:35.353392 best_step = 13
3267 01:21:35.353466
3268 01:21:35.353524 ==
3269 01:21:35.356467 Dram Type= 6, Freq= 0, CH_1, rank 0
3270 01:21:35.359788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3271 01:21:35.359862 ==
3272 01:21:35.359926 RX Vref Scan: 1
3273 01:21:35.363533
3274 01:21:35.363599 Set Vref Range= 32 -> 127
3275 01:21:35.363661
3276 01:21:35.366809 RX Vref 32 -> 127, step: 1
3277 01:21:35.366885
3278 01:21:35.369703 RX Delay -13 -> 252, step: 4
3279 01:21:35.369779
3280 01:21:35.373429 Set Vref, RX VrefLevel [Byte0]: 32
3281 01:21:35.376609 [Byte1]: 32
3282 01:21:35.376677
3283 01:21:35.379795 Set Vref, RX VrefLevel [Byte0]: 33
3284 01:21:35.383132 [Byte1]: 33
3285 01:21:35.387160
3286 01:21:35.387232 Set Vref, RX VrefLevel [Byte0]: 34
3287 01:21:35.390326 [Byte1]: 34
3288 01:21:35.395049
3289 01:21:35.395127 Set Vref, RX VrefLevel [Byte0]: 35
3290 01:21:35.398378 [Byte1]: 35
3291 01:21:35.402567
3292 01:21:35.405888 Set Vref, RX VrefLevel [Byte0]: 36
3293 01:21:35.408882 [Byte1]: 36
3294 01:21:35.408960
3295 01:21:35.412237 Set Vref, RX VrefLevel [Byte0]: 37
3296 01:21:35.415621 [Byte1]: 37
3297 01:21:35.415697
3298 01:21:35.419312 Set Vref, RX VrefLevel [Byte0]: 38
3299 01:21:35.422350 [Byte1]: 38
3300 01:21:35.426182
3301 01:21:35.426254 Set Vref, RX VrefLevel [Byte0]: 39
3302 01:21:35.429355 [Byte1]: 39
3303 01:21:35.434254
3304 01:21:35.434338 Set Vref, RX VrefLevel [Byte0]: 40
3305 01:21:35.437634 [Byte1]: 40
3306 01:21:35.441912
3307 01:21:35.441984 Set Vref, RX VrefLevel [Byte0]: 41
3308 01:21:35.445510 [Byte1]: 41
3309 01:21:35.449917
3310 01:21:35.449994 Set Vref, RX VrefLevel [Byte0]: 42
3311 01:21:35.453396 [Byte1]: 42
3312 01:21:35.458277
3313 01:21:35.458356 Set Vref, RX VrefLevel [Byte0]: 43
3314 01:21:35.461427 [Byte1]: 43
3315 01:21:35.465854
3316 01:21:35.465931 Set Vref, RX VrefLevel [Byte0]: 44
3317 01:21:35.468792 [Byte1]: 44
3318 01:21:35.473234
3319 01:21:35.473311 Set Vref, RX VrefLevel [Byte0]: 45
3320 01:21:35.477178 [Byte1]: 45
3321 01:21:35.481190
3322 01:21:35.481267 Set Vref, RX VrefLevel [Byte0]: 46
3323 01:21:35.484914 [Byte1]: 46
3324 01:21:35.489127
3325 01:21:35.489244 Set Vref, RX VrefLevel [Byte0]: 47
3326 01:21:35.492783 [Byte1]: 47
3327 01:21:35.497299
3328 01:21:35.497370 Set Vref, RX VrefLevel [Byte0]: 48
3329 01:21:35.500313 [Byte1]: 48
3330 01:21:35.505363
3331 01:21:35.505439 Set Vref, RX VrefLevel [Byte0]: 49
3332 01:21:35.508869 [Byte1]: 49
3333 01:21:35.513156
3334 01:21:35.513229 Set Vref, RX VrefLevel [Byte0]: 50
3335 01:21:35.516328 [Byte1]: 50
3336 01:21:35.520739
3337 01:21:35.520819 Set Vref, RX VrefLevel [Byte0]: 51
3338 01:21:35.523906 [Byte1]: 51
3339 01:21:35.528796
3340 01:21:35.528868 Set Vref, RX VrefLevel [Byte0]: 52
3341 01:21:35.532395 [Byte1]: 52
3342 01:21:35.536503
3343 01:21:35.536574 Set Vref, RX VrefLevel [Byte0]: 53
3344 01:21:35.539860 [Byte1]: 53
3345 01:21:35.544567
3346 01:21:35.544639 Set Vref, RX VrefLevel [Byte0]: 54
3347 01:21:35.547844 [Byte1]: 54
3348 01:21:35.552251
3349 01:21:35.552319 Set Vref, RX VrefLevel [Byte0]: 55
3350 01:21:35.555622 [Byte1]: 55
3351 01:21:35.560332
3352 01:21:35.560402 Set Vref, RX VrefLevel [Byte0]: 56
3353 01:21:35.563762 [Byte1]: 56
3354 01:21:35.568014
3355 01:21:35.568094 Set Vref, RX VrefLevel [Byte0]: 57
3356 01:21:35.571213 [Byte1]: 57
3357 01:21:35.575848
3358 01:21:35.575974 Set Vref, RX VrefLevel [Byte0]: 58
3359 01:21:35.579196 [Byte1]: 58
3360 01:21:35.584047
3361 01:21:35.584122 Set Vref, RX VrefLevel [Byte0]: 59
3362 01:21:35.586918 [Byte1]: 59
3363 01:21:35.591836
3364 01:21:35.591959 Set Vref, RX VrefLevel [Byte0]: 60
3365 01:21:35.595121 [Byte1]: 60
3366 01:21:35.599495
3367 01:21:35.599567 Set Vref, RX VrefLevel [Byte0]: 61
3368 01:21:35.602864 [Byte1]: 61
3369 01:21:35.607203
3370 01:21:35.607273 Set Vref, RX VrefLevel [Byte0]: 62
3371 01:21:35.610633 [Byte1]: 62
3372 01:21:35.615151
3373 01:21:35.615229 Set Vref, RX VrefLevel [Byte0]: 63
3374 01:21:35.618377 [Byte1]: 63
3375 01:21:35.623520
3376 01:21:35.623598 Set Vref, RX VrefLevel [Byte0]: 64
3377 01:21:35.626487 [Byte1]: 64
3378 01:21:35.631242
3379 01:21:35.631314 Set Vref, RX VrefLevel [Byte0]: 65
3380 01:21:35.634361 [Byte1]: 65
3381 01:21:35.638835
3382 01:21:35.638907 Final RX Vref Byte 0 = 53 to rank0
3383 01:21:35.642267 Final RX Vref Byte 1 = 53 to rank0
3384 01:21:35.645432 Final RX Vref Byte 0 = 53 to rank1
3385 01:21:35.648761 Final RX Vref Byte 1 = 53 to rank1==
3386 01:21:35.652648 Dram Type= 6, Freq= 0, CH_1, rank 0
3387 01:21:35.659107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3388 01:21:35.659181 ==
3389 01:21:35.659243 DQS Delay:
3390 01:21:35.659301 DQS0 = 0, DQS1 = 0
3391 01:21:35.661926 DQM Delay:
3392 01:21:35.662001 DQM0 = 114, DQM1 = 113
3393 01:21:35.665266 DQ Delay:
3394 01:21:35.668584 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =114
3395 01:21:35.671721 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3396 01:21:35.675070 DQ8 =100, DQ9 =104, DQ10 =112, DQ11 =108
3397 01:21:35.678288 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =122
3398 01:21:35.678370
3399 01:21:35.678432
3400 01:21:35.688369 [DQSOSCAuto] RK0, (LSB)MR18= 0xf300, (MSB)MR19= 0x304, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3401 01:21:35.688454 CH1 RK0: MR19=304, MR18=F300
3402 01:21:35.695168 CH1_RK0: MR19=0x304, MR18=0xF300, DQSOSC=410, MR23=63, INC=39, DEC=26
3403 01:21:35.695246
3404 01:21:35.698659 ----->DramcWriteLeveling(PI) begin...
3405 01:21:35.698737 ==
3406 01:21:35.701989 Dram Type= 6, Freq= 0, CH_1, rank 1
3407 01:21:35.708425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3408 01:21:35.708506 ==
3409 01:21:35.711860 Write leveling (Byte 0): 26 => 26
3410 01:21:35.714991 Write leveling (Byte 1): 27 => 27
3411 01:21:35.715067 DramcWriteLeveling(PI) end<-----
3412 01:21:35.718459
3413 01:21:35.718529 ==
3414 01:21:35.721780 Dram Type= 6, Freq= 0, CH_1, rank 1
3415 01:21:35.725478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3416 01:21:35.725550 ==
3417 01:21:35.728317 [Gating] SW mode calibration
3418 01:21:35.734943 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3419 01:21:35.738396 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3420 01:21:35.744998 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3421 01:21:35.749207 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3422 01:21:35.751091 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3423 01:21:35.757972 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3424 01:21:35.761051 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3425 01:21:35.764493 0 15 20 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3426 01:21:35.771004 0 15 24 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 1)
3427 01:21:35.774426 0 15 28 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
3428 01:21:35.777641 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3429 01:21:35.784573 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3430 01:21:35.788113 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3431 01:21:35.791422 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3432 01:21:35.798044 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3433 01:21:35.800915 1 0 20 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
3434 01:21:35.804532 1 0 24 | B1->B0 | 2525 4444 | 0 1 | (0 0) (1 1)
3435 01:21:35.810922 1 0 28 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
3436 01:21:35.814675 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3437 01:21:35.817790 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3438 01:21:35.824346 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3439 01:21:35.827511 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3440 01:21:35.831164 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3441 01:21:35.837365 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3442 01:21:35.840519 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3443 01:21:35.843771 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3444 01:21:35.850532 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3445 01:21:35.853916 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3446 01:21:35.856986 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3447 01:21:35.863790 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3448 01:21:35.867043 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3449 01:21:35.870217 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3450 01:21:35.877024 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 01:21:35.880109 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 01:21:35.883348 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 01:21:35.890138 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 01:21:35.893313 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 01:21:35.896659 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 01:21:35.902847 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 01:21:35.906115 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3458 01:21:35.909854 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3459 01:21:35.916003 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3460 01:21:35.919385 Total UI for P1: 0, mck2ui 16
3461 01:21:35.922599 best dqsien dly found for B0: ( 1, 3, 22)
3462 01:21:35.926038 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 01:21:35.929591 Total UI for P1: 0, mck2ui 16
3464 01:21:35.932660 best dqsien dly found for B1: ( 1, 3, 28)
3465 01:21:35.936176 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3466 01:21:35.938945 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3467 01:21:35.939019
3468 01:21:35.942434 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3469 01:21:35.949558 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3470 01:21:35.949641 [Gating] SW calibration Done
3471 01:21:35.949703 ==
3472 01:21:35.952597 Dram Type= 6, Freq= 0, CH_1, rank 1
3473 01:21:35.958710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3474 01:21:35.958785 ==
3475 01:21:35.958846 RX Vref Scan: 0
3476 01:21:35.958912
3477 01:21:35.962042 RX Vref 0 -> 0, step: 1
3478 01:21:35.962118
3479 01:21:35.965395 RX Delay -40 -> 252, step: 8
3480 01:21:35.968514 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3481 01:21:35.971946 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3482 01:21:35.975370 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3483 01:21:35.981800 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3484 01:21:35.985312 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3485 01:21:35.988281 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3486 01:21:35.991757 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3487 01:21:35.995066 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3488 01:21:36.001809 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3489 01:21:36.005331 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3490 01:21:36.008491 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3491 01:21:36.011531 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3492 01:21:36.014786 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3493 01:21:36.021417 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3494 01:21:36.024683 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3495 01:21:36.028282 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3496 01:21:36.028355 ==
3497 01:21:36.031322 Dram Type= 6, Freq= 0, CH_1, rank 1
3498 01:21:36.037753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3499 01:21:36.037837 ==
3500 01:21:36.037901 DQS Delay:
3501 01:21:36.037959 DQS0 = 0, DQS1 = 0
3502 01:21:36.041250 DQM Delay:
3503 01:21:36.041327 DQM0 = 115, DQM1 = 111
3504 01:21:36.044772 DQ Delay:
3505 01:21:36.047475 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3506 01:21:36.050909 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =119
3507 01:21:36.054211 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3508 01:21:36.057794 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3509 01:21:36.057866
3510 01:21:36.057931
3511 01:21:36.057989 ==
3512 01:21:36.061363 Dram Type= 6, Freq= 0, CH_1, rank 1
3513 01:21:36.064454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3514 01:21:36.064526 ==
3515 01:21:36.067329
3516 01:21:36.067401
3517 01:21:36.067462 TX Vref Scan disable
3518 01:21:36.070894 == TX Byte 0 ==
3519 01:21:36.074232 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3520 01:21:36.077604 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3521 01:21:36.080716 == TX Byte 1 ==
3522 01:21:36.083873 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3523 01:21:36.087288 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3524 01:21:36.090842 ==
3525 01:21:36.090925 Dram Type= 6, Freq= 0, CH_1, rank 1
3526 01:21:36.097049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3527 01:21:36.097132 ==
3528 01:21:36.107808 TX Vref=22, minBit 9, minWin=24, winSum=416
3529 01:21:36.111181 TX Vref=24, minBit 4, minWin=25, winSum=421
3530 01:21:36.114592 TX Vref=26, minBit 9, minWin=25, winSum=426
3531 01:21:36.117676 TX Vref=28, minBit 3, minWin=25, winSum=427
3532 01:21:36.121343 TX Vref=30, minBit 9, minWin=25, winSum=430
3533 01:21:36.127830 TX Vref=32, minBit 9, minWin=25, winSum=428
3534 01:21:36.130722 [TxChooseVref] Worse bit 9, Min win 25, Win sum 430, Final Vref 30
3535 01:21:36.130795
3536 01:21:36.134355 Final TX Range 1 Vref 30
3537 01:21:36.134427
3538 01:21:36.134487 ==
3539 01:21:36.137180 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 01:21:36.144059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 01:21:36.144133 ==
3542 01:21:36.144201
3543 01:21:36.144259
3544 01:21:36.144314 TX Vref Scan disable
3545 01:21:36.147644 == TX Byte 0 ==
3546 01:21:36.150774 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3547 01:21:36.157389 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3548 01:21:36.157463 == TX Byte 1 ==
3549 01:21:36.160868 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3550 01:21:36.167539 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3551 01:21:36.167621
3552 01:21:36.167683 [DATLAT]
3553 01:21:36.167741 Freq=1200, CH1 RK1
3554 01:21:36.167803
3555 01:21:36.170621 DATLAT Default: 0xd
3556 01:21:36.173778 0, 0xFFFF, sum = 0
3557 01:21:36.173850 1, 0xFFFF, sum = 0
3558 01:21:36.177732 2, 0xFFFF, sum = 0
3559 01:21:36.177832 3, 0xFFFF, sum = 0
3560 01:21:36.180356 4, 0xFFFF, sum = 0
3561 01:21:36.180430 5, 0xFFFF, sum = 0
3562 01:21:36.183720 6, 0xFFFF, sum = 0
3563 01:21:36.183823 7, 0xFFFF, sum = 0
3564 01:21:36.187261 8, 0xFFFF, sum = 0
3565 01:21:36.187339 9, 0xFFFF, sum = 0
3566 01:21:36.191009 10, 0xFFFF, sum = 0
3567 01:21:36.191087 11, 0xFFFF, sum = 0
3568 01:21:36.193505 12, 0x0, sum = 1
3569 01:21:36.193577 13, 0x0, sum = 2
3570 01:21:36.197408 14, 0x0, sum = 3
3571 01:21:36.197479 15, 0x0, sum = 4
3572 01:21:36.200062 best_step = 13
3573 01:21:36.200138
3574 01:21:36.200197 ==
3575 01:21:36.203210 Dram Type= 6, Freq= 0, CH_1, rank 1
3576 01:21:36.206773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3577 01:21:36.206851 ==
3578 01:21:36.210117 RX Vref Scan: 0
3579 01:21:36.210187
3580 01:21:36.210245 RX Vref 0 -> 0, step: 1
3581 01:21:36.210301
3582 01:21:36.213442 RX Delay -13 -> 252, step: 4
3583 01:21:36.220493 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3584 01:21:36.223442 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3585 01:21:36.226442 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3586 01:21:36.230098 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3587 01:21:36.236036 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3588 01:21:36.239463 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3589 01:21:36.243141 iDelay=195, Bit 6, Center 120 (51 ~ 190) 140
3590 01:21:36.246318 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3591 01:21:36.249493 iDelay=195, Bit 8, Center 102 (43 ~ 162) 120
3592 01:21:36.256001 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3593 01:21:36.259062 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3594 01:21:36.262332 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3595 01:21:36.265808 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3596 01:21:36.269138 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3597 01:21:36.275714 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3598 01:21:36.279360 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3599 01:21:36.279436 ==
3600 01:21:36.282489 Dram Type= 6, Freq= 0, CH_1, rank 1
3601 01:21:36.286083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3602 01:21:36.286193 ==
3603 01:21:36.288919 DQS Delay:
3604 01:21:36.288991 DQS0 = 0, DQS1 = 0
3605 01:21:36.291960 DQM Delay:
3606 01:21:36.292069 DQM0 = 115, DQM1 = 112
3607 01:21:36.292161 DQ Delay:
3608 01:21:36.295318 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =112
3609 01:21:36.302296 DQ4 =116, DQ5 =124, DQ6 =120, DQ7 =112
3610 01:21:36.305283 DQ8 =102, DQ9 =104, DQ10 =114, DQ11 =106
3611 01:21:36.308944 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =120
3612 01:21:36.309016
3613 01:21:36.309077
3614 01:21:36.315610 [DQSOSCAuto] RK1, (LSB)MR18= 0xf304, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
3615 01:21:36.318385 CH1 RK1: MR19=304, MR18=F304
3616 01:21:36.325506 CH1_RK1: MR19=0x304, MR18=0xF304, DQSOSC=408, MR23=63, INC=39, DEC=26
3617 01:21:36.328355 [RxdqsGatingPostProcess] freq 1200
3618 01:21:36.335274 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3619 01:21:36.338181 best DQS0 dly(2T, 0.5T) = (0, 11)
3620 01:21:36.338253 best DQS1 dly(2T, 0.5T) = (0, 11)
3621 01:21:36.341614 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3622 01:21:36.344839 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3623 01:21:36.348020 best DQS0 dly(2T, 0.5T) = (0, 11)
3624 01:21:36.351402 best DQS1 dly(2T, 0.5T) = (0, 11)
3625 01:21:36.354608 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3626 01:21:36.358350 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3627 01:21:36.361795 Pre-setting of DQS Precalculation
3628 01:21:36.367510 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3629 01:21:36.374264 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3630 01:21:36.381582 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3631 01:21:36.381662
3632 01:21:36.381723
3633 01:21:36.384070 [Calibration Summary] 2400 Mbps
3634 01:21:36.384144 CH 0, Rank 0
3635 01:21:36.387281 SW Impedance : PASS
3636 01:21:36.390770 DUTY Scan : NO K
3637 01:21:36.390884 ZQ Calibration : PASS
3638 01:21:36.394096 Jitter Meter : NO K
3639 01:21:36.397381 CBT Training : PASS
3640 01:21:36.397461 Write leveling : PASS
3641 01:21:36.400703 RX DQS gating : PASS
3642 01:21:36.403815 RX DQ/DQS(RDDQC) : PASS
3643 01:21:36.403954 TX DQ/DQS : PASS
3644 01:21:36.407311 RX DATLAT : PASS
3645 01:21:36.410594 RX DQ/DQS(Engine): PASS
3646 01:21:36.410668 TX OE : NO K
3647 01:21:36.413834 All Pass.
3648 01:21:36.413907
3649 01:21:36.413968 CH 0, Rank 1
3650 01:21:36.416787 SW Impedance : PASS
3651 01:21:36.416863 DUTY Scan : NO K
3652 01:21:36.420556 ZQ Calibration : PASS
3653 01:21:36.423774 Jitter Meter : NO K
3654 01:21:36.423869 CBT Training : PASS
3655 01:21:36.427126 Write leveling : PASS
3656 01:21:36.430604 RX DQS gating : PASS
3657 01:21:36.430685 RX DQ/DQS(RDDQC) : PASS
3658 01:21:36.433372 TX DQ/DQS : PASS
3659 01:21:36.436749 RX DATLAT : PASS
3660 01:21:36.436831 RX DQ/DQS(Engine): PASS
3661 01:21:36.440210 TX OE : NO K
3662 01:21:36.440291 All Pass.
3663 01:21:36.440356
3664 01:21:36.443542 CH 1, Rank 0
3665 01:21:36.443623 SW Impedance : PASS
3666 01:21:36.447095 DUTY Scan : NO K
3667 01:21:36.450493 ZQ Calibration : PASS
3668 01:21:36.450575 Jitter Meter : NO K
3669 01:21:36.453512 CBT Training : PASS
3670 01:21:36.453594 Write leveling : PASS
3671 01:21:36.457030 RX DQS gating : PASS
3672 01:21:36.459836 RX DQ/DQS(RDDQC) : PASS
3673 01:21:36.459957 TX DQ/DQS : PASS
3674 01:21:36.463320 RX DATLAT : PASS
3675 01:21:36.466438 RX DQ/DQS(Engine): PASS
3676 01:21:36.466536 TX OE : NO K
3677 01:21:36.470068 All Pass.
3678 01:21:36.470150
3679 01:21:36.470215 CH 1, Rank 1
3680 01:21:36.473451 SW Impedance : PASS
3681 01:21:36.473533 DUTY Scan : NO K
3682 01:21:36.476597 ZQ Calibration : PASS
3683 01:21:36.479689 Jitter Meter : NO K
3684 01:21:36.479787 CBT Training : PASS
3685 01:21:36.483573 Write leveling : PASS
3686 01:21:36.486441 RX DQS gating : PASS
3687 01:21:36.486523 RX DQ/DQS(RDDQC) : PASS
3688 01:21:36.489479 TX DQ/DQS : PASS
3689 01:21:36.492997 RX DATLAT : PASS
3690 01:21:36.493078 RX DQ/DQS(Engine): PASS
3691 01:21:36.496148 TX OE : NO K
3692 01:21:36.496248 All Pass.
3693 01:21:36.496346
3694 01:21:36.499642 DramC Write-DBI off
3695 01:21:36.502738 PER_BANK_REFRESH: Hybrid Mode
3696 01:21:36.502820 TX_TRACKING: ON
3697 01:21:36.512772 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3698 01:21:36.515744 [FAST_K] Save calibration result to emmc
3699 01:21:36.519381 dramc_set_vcore_voltage set vcore to 650000
3700 01:21:36.522454 Read voltage for 600, 5
3701 01:21:36.522536 Vio18 = 0
3702 01:21:36.525764 Vcore = 650000
3703 01:21:36.525846 Vdram = 0
3704 01:21:36.525910 Vddq = 0
3705 01:21:36.525970 Vmddr = 0
3706 01:21:36.532217 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3707 01:21:36.538657 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3708 01:21:36.538741 MEM_TYPE=3, freq_sel=19
3709 01:21:36.542147 sv_algorithm_assistance_LP4_1600
3710 01:21:36.545764 ============ PULL DRAM RESETB DOWN ============
3711 01:21:36.552353 ========== PULL DRAM RESETB DOWN end =========
3712 01:21:36.555606 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3713 01:21:36.558589 ===================================
3714 01:21:36.562154 LPDDR4 DRAM CONFIGURATION
3715 01:21:36.565457 ===================================
3716 01:21:36.565542 EX_ROW_EN[0] = 0x0
3717 01:21:36.568609 EX_ROW_EN[1] = 0x0
3718 01:21:36.568691 LP4Y_EN = 0x0
3719 01:21:36.571647 WORK_FSP = 0x0
3720 01:21:36.574893 WL = 0x2
3721 01:21:36.574976 RL = 0x2
3722 01:21:36.578453 BL = 0x2
3723 01:21:36.578551 RPST = 0x0
3724 01:21:36.581829 RD_PRE = 0x0
3725 01:21:36.581911 WR_PRE = 0x1
3726 01:21:36.584829 WR_PST = 0x0
3727 01:21:36.584912 DBI_WR = 0x0
3728 01:21:36.588700 DBI_RD = 0x0
3729 01:21:36.588781 OTF = 0x1
3730 01:21:36.591639 ===================================
3731 01:21:36.594918 ===================================
3732 01:21:36.598557 ANA top config
3733 01:21:36.601608 ===================================
3734 01:21:36.601689 DLL_ASYNC_EN = 0
3735 01:21:36.604794 ALL_SLAVE_EN = 1
3736 01:21:36.608579 NEW_RANK_MODE = 1
3737 01:21:36.611576 DLL_IDLE_MODE = 1
3738 01:21:36.611658 LP45_APHY_COMB_EN = 1
3739 01:21:36.614945 TX_ODT_DIS = 1
3740 01:21:36.617882 NEW_8X_MODE = 1
3741 01:21:36.621304 ===================================
3742 01:21:36.624677 ===================================
3743 01:21:36.627600 data_rate = 1200
3744 01:21:36.630852 CKR = 1
3745 01:21:36.634205 DQ_P2S_RATIO = 8
3746 01:21:36.637593 ===================================
3747 01:21:36.641364 CA_P2S_RATIO = 8
3748 01:21:36.641446 DQ_CA_OPEN = 0
3749 01:21:36.644307 DQ_SEMI_OPEN = 0
3750 01:21:36.648014 CA_SEMI_OPEN = 0
3751 01:21:36.650574 CA_FULL_RATE = 0
3752 01:21:36.654191 DQ_CKDIV4_EN = 1
3753 01:21:36.658049 CA_CKDIV4_EN = 1
3754 01:21:36.658131 CA_PREDIV_EN = 0
3755 01:21:36.660599 PH8_DLY = 0
3756 01:21:36.663819 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3757 01:21:36.667285 DQ_AAMCK_DIV = 4
3758 01:21:36.670427 CA_AAMCK_DIV = 4
3759 01:21:36.673698 CA_ADMCK_DIV = 4
3760 01:21:36.673780 DQ_TRACK_CA_EN = 0
3761 01:21:36.677092 CA_PICK = 600
3762 01:21:36.680481 CA_MCKIO = 600
3763 01:21:36.683807 MCKIO_SEMI = 0
3764 01:21:36.686742 PLL_FREQ = 2288
3765 01:21:36.690245 DQ_UI_PI_RATIO = 32
3766 01:21:36.693906 CA_UI_PI_RATIO = 0
3767 01:21:36.697032 ===================================
3768 01:21:36.699798 ===================================
3769 01:21:36.699926 memory_type:LPDDR4
3770 01:21:36.703196 GP_NUM : 10
3771 01:21:36.706753 SRAM_EN : 1
3772 01:21:36.706853 MD32_EN : 0
3773 01:21:36.710062 ===================================
3774 01:21:36.713337 [ANA_INIT] >>>>>>>>>>>>>>
3775 01:21:36.716352 <<<<<< [CONFIGURE PHASE]: ANA_TX
3776 01:21:36.719708 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3777 01:21:36.723287 ===================================
3778 01:21:36.726324 data_rate = 1200,PCW = 0X5800
3779 01:21:36.729498 ===================================
3780 01:21:36.733168 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3781 01:21:36.736031 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3782 01:21:36.742621 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3783 01:21:36.749430 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3784 01:21:36.753146 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3785 01:21:36.755723 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3786 01:21:36.755806 [ANA_INIT] flow start
3787 01:21:36.759746 [ANA_INIT] PLL >>>>>>>>
3788 01:21:36.762311 [ANA_INIT] PLL <<<<<<<<
3789 01:21:36.762393 [ANA_INIT] MIDPI >>>>>>>>
3790 01:21:36.765719 [ANA_INIT] MIDPI <<<<<<<<
3791 01:21:36.768942 [ANA_INIT] DLL >>>>>>>>
3792 01:21:36.769024 [ANA_INIT] flow end
3793 01:21:36.775718 ============ LP4 DIFF to SE enter ============
3794 01:21:36.779152 ============ LP4 DIFF to SE exit ============
3795 01:21:36.782416 [ANA_INIT] <<<<<<<<<<<<<
3796 01:21:36.785640 [Flow] Enable top DCM control >>>>>
3797 01:21:36.789193 [Flow] Enable top DCM control <<<<<
3798 01:21:36.789279 Enable DLL master slave shuffle
3799 01:21:36.795276 ==============================================================
3800 01:21:36.799033 Gating Mode config
3801 01:21:36.802286 ==============================================================
3802 01:21:36.805270 Config description:
3803 01:21:36.815027 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3804 01:21:36.821659 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3805 01:21:36.825698 SELPH_MODE 0: By rank 1: By Phase
3806 01:21:36.831790 ==============================================================
3807 01:21:36.835398 GAT_TRACK_EN = 1
3808 01:21:36.838101 RX_GATING_MODE = 2
3809 01:21:36.841660 RX_GATING_TRACK_MODE = 2
3810 01:21:36.844792 SELPH_MODE = 1
3811 01:21:36.847912 PICG_EARLY_EN = 1
3812 01:21:36.851153 VALID_LAT_VALUE = 1
3813 01:21:36.854772 ==============================================================
3814 01:21:36.857953 Enter into Gating configuration >>>>
3815 01:21:36.861510 Exit from Gating configuration <<<<
3816 01:21:36.864585 Enter into DVFS_PRE_config >>>>>
3817 01:21:36.874457 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3818 01:21:36.877857 Exit from DVFS_PRE_config <<<<<
3819 01:21:36.881354 Enter into PICG configuration >>>>
3820 01:21:36.884291 Exit from PICG configuration <<<<
3821 01:21:36.887570 [RX_INPUT] configuration >>>>>
3822 01:21:36.891035 [RX_INPUT] configuration <<<<<
3823 01:21:36.897817 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3824 01:21:36.900847 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3825 01:21:36.907373 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3826 01:21:36.913887 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3827 01:21:36.920294 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3828 01:21:36.926825 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3829 01:21:36.930172 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3830 01:21:36.933256 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3831 01:21:36.940198 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3832 01:21:36.943496 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3833 01:21:36.946890 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3834 01:21:36.950028 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3835 01:21:36.953079 ===================================
3836 01:21:36.956600 LPDDR4 DRAM CONFIGURATION
3837 01:21:36.960128 ===================================
3838 01:21:36.963224 EX_ROW_EN[0] = 0x0
3839 01:21:36.963306 EX_ROW_EN[1] = 0x0
3840 01:21:36.966440 LP4Y_EN = 0x0
3841 01:21:36.966521 WORK_FSP = 0x0
3842 01:21:36.969488 WL = 0x2
3843 01:21:36.969569 RL = 0x2
3844 01:21:36.972897 BL = 0x2
3845 01:21:36.972979 RPST = 0x0
3846 01:21:36.976532 RD_PRE = 0x0
3847 01:21:36.979258 WR_PRE = 0x1
3848 01:21:36.979340 WR_PST = 0x0
3849 01:21:36.982425 DBI_WR = 0x0
3850 01:21:36.982508 DBI_RD = 0x0
3851 01:21:36.986023 OTF = 0x1
3852 01:21:36.989392 ===================================
3853 01:21:36.992881 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3854 01:21:36.996247 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3855 01:21:37.002368 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3856 01:21:37.005646 ===================================
3857 01:21:37.005731 LPDDR4 DRAM CONFIGURATION
3858 01:21:37.009010 ===================================
3859 01:21:37.012556 EX_ROW_EN[0] = 0x10
3860 01:21:37.012638 EX_ROW_EN[1] = 0x0
3861 01:21:37.015356 LP4Y_EN = 0x0
3862 01:21:37.015437 WORK_FSP = 0x0
3863 01:21:37.019210 WL = 0x2
3864 01:21:37.022278 RL = 0x2
3865 01:21:37.022360 BL = 0x2
3866 01:21:37.025391 RPST = 0x0
3867 01:21:37.025473 RD_PRE = 0x0
3868 01:21:37.028689 WR_PRE = 0x1
3869 01:21:37.028771 WR_PST = 0x0
3870 01:21:37.032059 DBI_WR = 0x0
3871 01:21:37.032141 DBI_RD = 0x0
3872 01:21:37.035528 OTF = 0x1
3873 01:21:37.038950 ===================================
3874 01:21:37.044902 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3875 01:21:37.048424 nWR fixed to 30
3876 01:21:37.048509 [ModeRegInit_LP4] CH0 RK0
3877 01:21:37.051477 [ModeRegInit_LP4] CH0 RK1
3878 01:21:37.055241 [ModeRegInit_LP4] CH1 RK0
3879 01:21:37.058218 [ModeRegInit_LP4] CH1 RK1
3880 01:21:37.058322 match AC timing 17
3881 01:21:37.064745 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3882 01:21:37.068247 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3883 01:21:37.071786 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3884 01:21:37.078141 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3885 01:21:37.081137 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3886 01:21:37.081219 ==
3887 01:21:37.084495 Dram Type= 6, Freq= 0, CH_0, rank 0
3888 01:21:37.087674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3889 01:21:37.087756 ==
3890 01:21:37.094490 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3891 01:21:37.101311 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3892 01:21:37.104609 [CA 0] Center 36 (6~67) winsize 62
3893 01:21:37.107822 [CA 1] Center 36 (5~67) winsize 63
3894 01:21:37.110616 [CA 2] Center 34 (4~65) winsize 62
3895 01:21:37.114270 [CA 3] Center 34 (3~65) winsize 63
3896 01:21:37.117475 [CA 4] Center 33 (3~64) winsize 62
3897 01:21:37.120346 [CA 5] Center 33 (3~64) winsize 62
3898 01:21:37.120428
3899 01:21:37.124083 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3900 01:21:37.124165
3901 01:21:37.127541 [CATrainingPosCal] consider 1 rank data
3902 01:21:37.130521 u2DelayCellTimex100 = 270/100 ps
3903 01:21:37.133703 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3904 01:21:37.137155 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3905 01:21:37.140583 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3906 01:21:37.143775 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3907 01:21:37.150171 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3908 01:21:37.153604 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3909 01:21:37.153685
3910 01:21:37.157019 CA PerBit enable=1, Macro0, CA PI delay=33
3911 01:21:37.157100
3912 01:21:37.160333 [CBTSetCACLKResult] CA Dly = 33
3913 01:21:37.160415 CS Dly: 4 (0~35)
3914 01:21:37.160479 ==
3915 01:21:37.163262 Dram Type= 6, Freq= 0, CH_0, rank 1
3916 01:21:37.170255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3917 01:21:37.170337 ==
3918 01:21:37.173133 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3919 01:21:37.180365 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3920 01:21:37.183681 [CA 0] Center 36 (6~67) winsize 62
3921 01:21:37.186565 [CA 1] Center 36 (6~67) winsize 62
3922 01:21:37.190257 [CA 2] Center 34 (4~65) winsize 62
3923 01:21:37.193255 [CA 3] Center 34 (4~65) winsize 62
3924 01:21:37.196396 [CA 4] Center 33 (3~64) winsize 62
3925 01:21:37.199495 [CA 5] Center 33 (3~64) winsize 62
3926 01:21:37.199576
3927 01:21:37.202837 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3928 01:21:37.202919
3929 01:21:37.206471 [CATrainingPosCal] consider 2 rank data
3930 01:21:37.209736 u2DelayCellTimex100 = 270/100 ps
3931 01:21:37.212721 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3932 01:21:37.219935 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3933 01:21:37.222829 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3934 01:21:37.226323 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3935 01:21:37.229361 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3936 01:21:37.232724 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3937 01:21:37.232805
3938 01:21:37.235733 CA PerBit enable=1, Macro0, CA PI delay=33
3939 01:21:37.235814
3940 01:21:37.239204 [CBTSetCACLKResult] CA Dly = 33
3941 01:21:37.242482 CS Dly: 5 (0~38)
3942 01:21:37.242563
3943 01:21:37.245797 ----->DramcWriteLeveling(PI) begin...
3944 01:21:37.245879 ==
3945 01:21:37.249184 Dram Type= 6, Freq= 0, CH_0, rank 0
3946 01:21:37.252176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3947 01:21:37.252258 ==
3948 01:21:37.255495 Write leveling (Byte 0): 34 => 34
3949 01:21:37.258961 Write leveling (Byte 1): 30 => 30
3950 01:21:37.262115 DramcWriteLeveling(PI) end<-----
3951 01:21:37.262195
3952 01:21:37.262259 ==
3953 01:21:37.265362 Dram Type= 6, Freq= 0, CH_0, rank 0
3954 01:21:37.268722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3955 01:21:37.268804 ==
3956 01:21:37.272160 [Gating] SW mode calibration
3957 01:21:37.278593 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3958 01:21:37.285179 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3959 01:21:37.288714 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3960 01:21:37.291856 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3961 01:21:37.298146 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3962 01:21:37.301531 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
3963 01:21:37.308260 0 9 16 | B1->B0 | 2b2b 2525 | 0 0 | (0 0) (0 0)
3964 01:21:37.311206 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3965 01:21:37.314560 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3966 01:21:37.320962 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3967 01:21:37.324356 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3968 01:21:37.328515 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3969 01:21:37.334319 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3970 01:21:37.337750 0 10 12 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (0 0)
3971 01:21:37.340891 0 10 16 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
3972 01:21:37.347785 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3973 01:21:37.350833 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3974 01:21:37.354218 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3975 01:21:37.360709 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3976 01:21:37.363802 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3977 01:21:37.367603 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3978 01:21:37.374089 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3979 01:21:37.377249 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3980 01:21:37.380616 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3981 01:21:37.386938 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3982 01:21:37.390029 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3983 01:21:37.393775 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 01:21:37.400406 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 01:21:37.403319 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 01:21:37.406960 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 01:21:37.413389 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 01:21:37.416404 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 01:21:37.419768 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 01:21:37.426536 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 01:21:37.429799 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 01:21:37.433189 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 01:21:37.439454 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 01:21:37.442992 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3995 01:21:37.446428 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3996 01:21:37.449547 Total UI for P1: 0, mck2ui 16
3997 01:21:37.452932 best dqsien dly found for B0: ( 0, 13, 12)
3998 01:21:37.459512 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 01:21:37.459593 Total UI for P1: 0, mck2ui 16
4000 01:21:37.462893 best dqsien dly found for B1: ( 0, 13, 16)
4001 01:21:37.469418 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4002 01:21:37.472785 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4003 01:21:37.472870
4004 01:21:37.476155 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4005 01:21:37.479053 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4006 01:21:37.482411 [Gating] SW calibration Done
4007 01:21:37.482493 ==
4008 01:21:37.486036 Dram Type= 6, Freq= 0, CH_0, rank 0
4009 01:21:37.489058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4010 01:21:37.489140 ==
4011 01:21:37.492392 RX Vref Scan: 0
4012 01:21:37.492472
4013 01:21:37.492536 RX Vref 0 -> 0, step: 1
4014 01:21:37.492596
4015 01:21:37.495758 RX Delay -230 -> 252, step: 16
4016 01:21:37.502516 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4017 01:21:37.505213 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4018 01:21:37.508855 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4019 01:21:37.512446 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4020 01:21:37.518305 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4021 01:21:37.522357 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4022 01:21:37.525238 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4023 01:21:37.528149 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4024 01:21:37.531853 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4025 01:21:37.538114 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4026 01:21:37.541792 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4027 01:21:37.545091 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4028 01:21:37.547946 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4029 01:21:37.554998 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4030 01:21:37.557849 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4031 01:21:37.561095 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4032 01:21:37.561176 ==
4033 01:21:37.564571 Dram Type= 6, Freq= 0, CH_0, rank 0
4034 01:21:37.571172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4035 01:21:37.571254 ==
4036 01:21:37.571319 DQS Delay:
4037 01:21:37.574763 DQS0 = 0, DQS1 = 0
4038 01:21:37.574844 DQM Delay:
4039 01:21:37.574909 DQM0 = 41, DQM1 = 35
4040 01:21:37.577755 DQ Delay:
4041 01:21:37.580848 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4042 01:21:37.583889 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4043 01:21:37.587368 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4044 01:21:37.590680 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4045 01:21:37.590761
4046 01:21:37.590825
4047 01:21:37.590884 ==
4048 01:21:37.594125 Dram Type= 6, Freq= 0, CH_0, rank 0
4049 01:21:37.597571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4050 01:21:37.597653 ==
4051 01:21:37.597717
4052 01:21:37.597776
4053 01:21:37.600759 TX Vref Scan disable
4054 01:21:37.604223 == TX Byte 0 ==
4055 01:21:37.607521 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4056 01:21:37.610533 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4057 01:21:37.613733 == TX Byte 1 ==
4058 01:21:37.617057 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4059 01:21:37.620482 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4060 01:21:37.620565 ==
4061 01:21:37.623651 Dram Type= 6, Freq= 0, CH_0, rank 0
4062 01:21:37.630298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4063 01:21:37.630380 ==
4064 01:21:37.630444
4065 01:21:37.630502
4066 01:21:37.630560 TX Vref Scan disable
4067 01:21:37.634451 == TX Byte 0 ==
4068 01:21:37.637789 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4069 01:21:37.644597 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4070 01:21:37.644679 == TX Byte 1 ==
4071 01:21:37.648016 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4072 01:21:37.654751 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4073 01:21:37.654834
4074 01:21:37.654898 [DATLAT]
4075 01:21:37.654958 Freq=600, CH0 RK0
4076 01:21:37.655016
4077 01:21:37.657320 DATLAT Default: 0x9
4078 01:21:37.660944 0, 0xFFFF, sum = 0
4079 01:21:37.661028 1, 0xFFFF, sum = 0
4080 01:21:37.664321 2, 0xFFFF, sum = 0
4081 01:21:37.664419 3, 0xFFFF, sum = 0
4082 01:21:37.667662 4, 0xFFFF, sum = 0
4083 01:21:37.667763 5, 0xFFFF, sum = 0
4084 01:21:37.670662 6, 0xFFFF, sum = 0
4085 01:21:37.670745 7, 0xFFFF, sum = 0
4086 01:21:37.674410 8, 0x0, sum = 1
4087 01:21:37.674493 9, 0x0, sum = 2
4088 01:21:37.677024 10, 0x0, sum = 3
4089 01:21:37.677107 11, 0x0, sum = 4
4090 01:21:37.677173 best_step = 9
4091 01:21:37.677233
4092 01:21:37.680615 ==
4093 01:21:37.683659 Dram Type= 6, Freq= 0, CH_0, rank 0
4094 01:21:37.687113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4095 01:21:37.687197 ==
4096 01:21:37.687262 RX Vref Scan: 1
4097 01:21:37.687322
4098 01:21:37.690483 RX Vref 0 -> 0, step: 1
4099 01:21:37.690565
4100 01:21:37.693677 RX Delay -179 -> 252, step: 8
4101 01:21:37.693759
4102 01:21:37.697770 Set Vref, RX VrefLevel [Byte0]: 53
4103 01:21:37.700289 [Byte1]: 45
4104 01:21:37.700371
4105 01:21:37.703345 Final RX Vref Byte 0 = 53 to rank0
4106 01:21:37.706828 Final RX Vref Byte 1 = 45 to rank0
4107 01:21:37.710332 Final RX Vref Byte 0 = 53 to rank1
4108 01:21:37.713521 Final RX Vref Byte 1 = 45 to rank1==
4109 01:21:37.716772 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 01:21:37.720524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 01:21:37.723595 ==
4112 01:21:37.723677 DQS Delay:
4113 01:21:37.723741 DQS0 = 0, DQS1 = 0
4114 01:21:37.726846 DQM Delay:
4115 01:21:37.726927 DQM0 = 41, DQM1 = 33
4116 01:21:37.730093 DQ Delay:
4117 01:21:37.733715 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4118 01:21:37.733799 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44
4119 01:21:37.736280 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4120 01:21:37.743209 DQ12 =44, DQ13 =36, DQ14 =44, DQ15 =40
4121 01:21:37.743291
4122 01:21:37.743355
4123 01:21:37.749470 [DQSOSCAuto] RK0, (LSB)MR18= 0x4940, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4124 01:21:37.752886 CH0 RK0: MR19=808, MR18=4940
4125 01:21:37.759844 CH0_RK0: MR19=0x808, MR18=0x4940, DQSOSC=396, MR23=63, INC=167, DEC=111
4126 01:21:37.759973
4127 01:21:37.762529 ----->DramcWriteLeveling(PI) begin...
4128 01:21:37.762612 ==
4129 01:21:37.766332 Dram Type= 6, Freq= 0, CH_0, rank 1
4130 01:21:37.769628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4131 01:21:37.769710 ==
4132 01:21:37.772325 Write leveling (Byte 0): 36 => 36
4133 01:21:37.775604 Write leveling (Byte 1): 31 => 31
4134 01:21:37.779214 DramcWriteLeveling(PI) end<-----
4135 01:21:37.779295
4136 01:21:37.779359 ==
4137 01:21:37.782468 Dram Type= 6, Freq= 0, CH_0, rank 1
4138 01:21:37.786114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 01:21:37.789135 ==
4140 01:21:37.789217 [Gating] SW mode calibration
4141 01:21:37.798898 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4142 01:21:37.802070 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4143 01:21:37.806231 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4144 01:21:37.812151 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4145 01:21:37.815475 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4146 01:21:37.818462 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
4147 01:21:37.825502 0 9 16 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (0 0)
4148 01:21:37.828924 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4149 01:21:37.831951 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4150 01:21:37.838518 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4151 01:21:37.841808 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4152 01:21:37.845217 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4153 01:21:37.851813 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4154 01:21:37.855050 0 10 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
4155 01:21:37.858350 0 10 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
4156 01:21:37.864838 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4157 01:21:37.868306 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4158 01:21:37.871188 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4159 01:21:37.877501 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4160 01:21:37.880855 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4161 01:21:37.884166 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4162 01:21:37.890934 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4163 01:21:37.894038 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4164 01:21:37.897475 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4165 01:21:37.903941 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4166 01:21:37.907104 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4167 01:21:37.914052 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4168 01:21:37.917546 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 01:21:37.920245 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 01:21:37.924039 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 01:21:37.930334 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 01:21:37.933507 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 01:21:37.936878 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 01:21:37.943611 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 01:21:37.946790 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 01:21:37.953212 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 01:21:37.956764 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 01:21:37.959958 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4179 01:21:37.966876 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 01:21:37.966958 Total UI for P1: 0, mck2ui 16
4181 01:21:37.969849 best dqsien dly found for B0: ( 0, 13, 12)
4182 01:21:37.973048 Total UI for P1: 0, mck2ui 16
4183 01:21:37.976589 best dqsien dly found for B1: ( 0, 13, 12)
4184 01:21:37.982968 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4185 01:21:37.986376 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4186 01:21:37.986458
4187 01:21:37.989497 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4188 01:21:37.992738 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4189 01:21:37.996335 [Gating] SW calibration Done
4190 01:21:37.996417 ==
4191 01:21:37.999783 Dram Type= 6, Freq= 0, CH_0, rank 1
4192 01:21:38.002510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4193 01:21:38.002591 ==
4194 01:21:38.005810 RX Vref Scan: 0
4195 01:21:38.005891
4196 01:21:38.005955 RX Vref 0 -> 0, step: 1
4197 01:21:38.006016
4198 01:21:38.009264 RX Delay -230 -> 252, step: 16
4199 01:21:38.015816 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4200 01:21:38.019296 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4201 01:21:38.022342 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4202 01:21:38.025734 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4203 01:21:38.029041 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4204 01:21:38.035867 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4205 01:21:38.039053 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4206 01:21:38.042096 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4207 01:21:38.045446 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4208 01:21:38.051902 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4209 01:21:38.055372 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4210 01:21:38.058505 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4211 01:21:38.061724 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4212 01:21:38.068355 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4213 01:21:38.071482 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4214 01:21:38.074869 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4215 01:21:38.074984 ==
4216 01:21:38.078105 Dram Type= 6, Freq= 0, CH_0, rank 1
4217 01:21:38.085062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4218 01:21:38.085144 ==
4219 01:21:38.085208 DQS Delay:
4220 01:21:38.085267 DQS0 = 0, DQS1 = 0
4221 01:21:38.088587 DQM Delay:
4222 01:21:38.088672 DQM0 = 43, DQM1 = 35
4223 01:21:38.091731 DQ Delay:
4224 01:21:38.094655 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4225 01:21:38.098109 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4226 01:21:38.101402 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4227 01:21:38.105883 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4228 01:21:38.105964
4229 01:21:38.106027
4230 01:21:38.106086 ==
4231 01:21:38.107762 Dram Type= 6, Freq= 0, CH_0, rank 1
4232 01:21:38.110993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4233 01:21:38.111074 ==
4234 01:21:38.111137
4235 01:21:38.111196
4236 01:21:38.114403 TX Vref Scan disable
4237 01:21:38.117852 == TX Byte 0 ==
4238 01:21:38.121174 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4239 01:21:38.124248 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4240 01:21:38.127429 == TX Byte 1 ==
4241 01:21:38.131069 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4242 01:21:38.134305 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4243 01:21:38.134385 ==
4244 01:21:38.137334 Dram Type= 6, Freq= 0, CH_0, rank 1
4245 01:21:38.140713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4246 01:21:38.144188 ==
4247 01:21:38.144268
4248 01:21:38.144331
4249 01:21:38.144389 TX Vref Scan disable
4250 01:21:38.148442 == TX Byte 0 ==
4251 01:21:38.151150 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4252 01:21:38.157823 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4253 01:21:38.157905 == TX Byte 1 ==
4254 01:21:38.161639 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4255 01:21:38.168161 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4256 01:21:38.168242
4257 01:21:38.168305 [DATLAT]
4258 01:21:38.168364 Freq=600, CH0 RK1
4259 01:21:38.168420
4260 01:21:38.171548 DATLAT Default: 0x9
4261 01:21:38.171628 0, 0xFFFF, sum = 0
4262 01:21:38.174897 1, 0xFFFF, sum = 0
4263 01:21:38.177901 2, 0xFFFF, sum = 0
4264 01:21:38.177983 3, 0xFFFF, sum = 0
4265 01:21:38.181059 4, 0xFFFF, sum = 0
4266 01:21:38.181141 5, 0xFFFF, sum = 0
4267 01:21:38.184463 6, 0xFFFF, sum = 0
4268 01:21:38.184545 7, 0xFFFF, sum = 0
4269 01:21:38.187755 8, 0x0, sum = 1
4270 01:21:38.187866 9, 0x0, sum = 2
4271 01:21:38.191328 10, 0x0, sum = 3
4272 01:21:38.191409 11, 0x0, sum = 4
4273 01:21:38.191473 best_step = 9
4274 01:21:38.191532
4275 01:21:38.193893 ==
4276 01:21:38.197437 Dram Type= 6, Freq= 0, CH_0, rank 1
4277 01:21:38.201038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4278 01:21:38.201119 ==
4279 01:21:38.201183 RX Vref Scan: 0
4280 01:21:38.201242
4281 01:21:38.204393 RX Vref 0 -> 0, step: 1
4282 01:21:38.204473
4283 01:21:38.207369 RX Delay -179 -> 252, step: 8
4284 01:21:38.213839 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4285 01:21:38.217680 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4286 01:21:38.220736 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4287 01:21:38.224097 iDelay=197, Bit 3, Center 36 (-115 ~ 188) 304
4288 01:21:38.227675 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4289 01:21:38.233760 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4290 01:21:38.237267 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4291 01:21:38.240605 iDelay=197, Bit 7, Center 44 (-107 ~ 196) 304
4292 01:21:38.243636 iDelay=197, Bit 8, Center 28 (-123 ~ 180) 304
4293 01:21:38.250172 iDelay=197, Bit 9, Center 20 (-131 ~ 172) 304
4294 01:21:38.253251 iDelay=197, Bit 10, Center 36 (-115 ~ 188) 304
4295 01:21:38.256809 iDelay=197, Bit 11, Center 24 (-123 ~ 172) 296
4296 01:21:38.260033 iDelay=197, Bit 12, Center 36 (-115 ~ 188) 304
4297 01:21:38.266307 iDelay=197, Bit 13, Center 40 (-107 ~ 188) 296
4298 01:21:38.269861 iDelay=197, Bit 14, Center 48 (-99 ~ 196) 296
4299 01:21:38.273259 iDelay=197, Bit 15, Center 40 (-107 ~ 188) 296
4300 01:21:38.273340 ==
4301 01:21:38.276337 Dram Type= 6, Freq= 0, CH_0, rank 1
4302 01:21:38.282956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4303 01:21:38.283038 ==
4304 01:21:38.283101 DQS Delay:
4305 01:21:38.283160 DQS0 = 0, DQS1 = 0
4306 01:21:38.286373 DQM Delay:
4307 01:21:38.286454 DQM0 = 40, DQM1 = 34
4308 01:21:38.289506 DQ Delay:
4309 01:21:38.292828 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4310 01:21:38.296450 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =44
4311 01:21:38.299466 DQ8 =28, DQ9 =20, DQ10 =36, DQ11 =24
4312 01:21:38.302617 DQ12 =36, DQ13 =40, DQ14 =48, DQ15 =40
4313 01:21:38.302699
4314 01:21:38.302762
4315 01:21:38.309479 [DQSOSCAuto] RK1, (LSB)MR18= 0x433e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4316 01:21:38.312723 CH0 RK1: MR19=808, MR18=433E
4317 01:21:38.318971 CH0_RK1: MR19=0x808, MR18=0x433E, DQSOSC=397, MR23=63, INC=166, DEC=110
4318 01:21:38.322536 [RxdqsGatingPostProcess] freq 600
4319 01:21:38.325278 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4320 01:21:38.328564 Pre-setting of DQS Precalculation
4321 01:21:38.335506 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4322 01:21:38.335590 ==
4323 01:21:38.338417 Dram Type= 6, Freq= 0, CH_1, rank 0
4324 01:21:38.341793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4325 01:21:38.341891 ==
4326 01:21:38.348583 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4327 01:21:38.355004 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4328 01:21:38.358474 [CA 0] Center 35 (5~66) winsize 62
4329 01:21:38.361601 [CA 1] Center 35 (5~66) winsize 62
4330 01:21:38.365086 [CA 2] Center 34 (4~65) winsize 62
4331 01:21:38.368465 [CA 3] Center 34 (3~65) winsize 63
4332 01:21:38.371695 [CA 4] Center 34 (4~65) winsize 62
4333 01:21:38.374686 [CA 5] Center 34 (3~65) winsize 63
4334 01:21:38.374767
4335 01:21:38.378074 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4336 01:21:38.378156
4337 01:21:38.381686 [CATrainingPosCal] consider 1 rank data
4338 01:21:38.384535 u2DelayCellTimex100 = 270/100 ps
4339 01:21:38.388039 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4340 01:21:38.391134 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4341 01:21:38.394529 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4342 01:21:38.397913 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4343 01:21:38.401178 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4344 01:21:38.404276 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4345 01:21:38.407421
4346 01:21:38.410908 CA PerBit enable=1, Macro0, CA PI delay=34
4347 01:21:38.410990
4348 01:21:38.414005 [CBTSetCACLKResult] CA Dly = 34
4349 01:21:38.414087 CS Dly: 4 (0~35)
4350 01:21:38.414151 ==
4351 01:21:38.417734 Dram Type= 6, Freq= 0, CH_1, rank 1
4352 01:21:38.420879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4353 01:21:38.424469 ==
4354 01:21:38.427298 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4355 01:21:38.434053 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4356 01:21:38.437339 [CA 0] Center 36 (6~66) winsize 61
4357 01:21:38.440640 [CA 1] Center 35 (5~66) winsize 62
4358 01:21:38.443771 [CA 2] Center 34 (4~65) winsize 62
4359 01:21:38.447164 [CA 3] Center 34 (3~65) winsize 63
4360 01:21:38.450417 [CA 4] Center 34 (4~65) winsize 62
4361 01:21:38.453449 [CA 5] Center 34 (3~65) winsize 63
4362 01:21:38.453531
4363 01:21:38.456749 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4364 01:21:38.456831
4365 01:21:38.460295 [CATrainingPosCal] consider 2 rank data
4366 01:21:38.463508 u2DelayCellTimex100 = 270/100 ps
4367 01:21:38.466724 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4368 01:21:38.469875 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4369 01:21:38.476801 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4370 01:21:38.480171 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4371 01:21:38.483123 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4372 01:21:38.486360 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4373 01:21:38.486442
4374 01:21:38.489619 CA PerBit enable=1, Macro0, CA PI delay=34
4375 01:21:38.489701
4376 01:21:38.492961 [CBTSetCACLKResult] CA Dly = 34
4377 01:21:38.493042 CS Dly: 4 (0~36)
4378 01:21:38.496297
4379 01:21:38.499648 ----->DramcWriteLeveling(PI) begin...
4380 01:21:38.499732 ==
4381 01:21:38.503069 Dram Type= 6, Freq= 0, CH_1, rank 0
4382 01:21:38.505966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4383 01:21:38.506049 ==
4384 01:21:38.509375 Write leveling (Byte 0): 28 => 28
4385 01:21:38.512763 Write leveling (Byte 1): 28 => 28
4386 01:21:38.516205 DramcWriteLeveling(PI) end<-----
4387 01:21:38.516287
4388 01:21:38.516351 ==
4389 01:21:38.519619 Dram Type= 6, Freq= 0, CH_1, rank 0
4390 01:21:38.522606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4391 01:21:38.522688 ==
4392 01:21:38.526214 [Gating] SW mode calibration
4393 01:21:38.532347 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4394 01:21:38.539032 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4395 01:21:38.542088 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4396 01:21:38.545842 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4397 01:21:38.552195 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4398 01:21:38.555432 0 9 12 | B1->B0 | 3131 2e2e | 0 0 | (0 0) (0 0)
4399 01:21:38.558881 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4400 01:21:38.565168 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4401 01:21:38.568495 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4402 01:21:38.571858 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4403 01:21:38.578384 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4404 01:21:38.581756 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 01:21:38.584958 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 01:21:38.591621 0 10 12 | B1->B0 | 3232 3a3a | 0 1 | (0 0) (0 0)
4407 01:21:38.594610 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4408 01:21:38.597866 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4409 01:21:38.604913 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4410 01:21:38.608234 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4411 01:21:38.611422 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4412 01:21:38.617897 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 01:21:38.621392 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 01:21:38.624246 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4415 01:21:38.630915 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4416 01:21:38.634286 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4417 01:21:38.640999 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 01:21:38.644337 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 01:21:38.647027 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 01:21:38.654199 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 01:21:38.657301 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 01:21:38.660731 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 01:21:38.667180 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 01:21:38.670186 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 01:21:38.673863 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 01:21:38.680649 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 01:21:38.683419 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 01:21:38.686609 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 01:21:38.693534 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 01:21:38.696649 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 01:21:38.700030 Total UI for P1: 0, mck2ui 16
4432 01:21:38.703358 best dqsien dly found for B0: ( 0, 13, 10)
4433 01:21:38.706610 Total UI for P1: 0, mck2ui 16
4434 01:21:38.709796 best dqsien dly found for B1: ( 0, 13, 10)
4435 01:21:38.713017 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4436 01:21:38.716281 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4437 01:21:38.716363
4438 01:21:38.719699 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4439 01:21:38.723343 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4440 01:21:38.726713 [Gating] SW calibration Done
4441 01:21:38.726794 ==
4442 01:21:38.729756 Dram Type= 6, Freq= 0, CH_1, rank 0
4443 01:21:38.733046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 01:21:38.736136 ==
4445 01:21:38.736217 RX Vref Scan: 0
4446 01:21:38.736281
4447 01:21:38.739563 RX Vref 0 -> 0, step: 1
4448 01:21:38.739644
4449 01:21:38.742939 RX Delay -230 -> 252, step: 16
4450 01:21:38.746156 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4451 01:21:38.749256 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4452 01:21:38.752621 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4453 01:21:38.759138 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4454 01:21:38.762700 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4455 01:21:38.765489 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4456 01:21:38.769082 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4457 01:21:38.775449 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4458 01:21:38.778804 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4459 01:21:38.782088 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4460 01:21:38.785820 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4461 01:21:38.792562 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4462 01:21:38.795011 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4463 01:21:38.799083 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4464 01:21:38.801992 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4465 01:21:38.808546 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4466 01:21:38.808630 ==
4467 01:21:38.811495 Dram Type= 6, Freq= 0, CH_1, rank 0
4468 01:21:38.814936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4469 01:21:38.815018 ==
4470 01:21:38.815082 DQS Delay:
4471 01:21:38.818221 DQS0 = 0, DQS1 = 0
4472 01:21:38.818302 DQM Delay:
4473 01:21:38.821415 DQM0 = 42, DQM1 = 38
4474 01:21:38.821496 DQ Delay:
4475 01:21:38.824611 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4476 01:21:38.828233 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4477 01:21:38.831690 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4478 01:21:38.834976 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4479 01:21:38.835058
4480 01:21:38.835121
4481 01:21:38.835180 ==
4482 01:21:38.838135 Dram Type= 6, Freq= 0, CH_1, rank 0
4483 01:21:38.841242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 01:21:38.841328 ==
4485 01:21:38.844846
4486 01:21:38.844920
4487 01:21:38.844982 TX Vref Scan disable
4488 01:21:38.847743 == TX Byte 0 ==
4489 01:21:38.850933 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4490 01:21:38.854726 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4491 01:21:38.857875 == TX Byte 1 ==
4492 01:21:38.861200 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4493 01:21:38.864384 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4494 01:21:38.867370 ==
4495 01:21:38.870851 Dram Type= 6, Freq= 0, CH_1, rank 0
4496 01:21:38.874154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4497 01:21:38.874252 ==
4498 01:21:38.874317
4499 01:21:38.874377
4500 01:21:38.877687 TX Vref Scan disable
4501 01:21:38.877769 == TX Byte 0 ==
4502 01:21:38.883948 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4503 01:21:38.887462 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4504 01:21:38.890413 == TX Byte 1 ==
4505 01:21:38.893591 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4506 01:21:38.897055 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4507 01:21:38.897137
4508 01:21:38.897202 [DATLAT]
4509 01:21:38.900202 Freq=600, CH1 RK0
4510 01:21:38.900284
4511 01:21:38.903594 DATLAT Default: 0x9
4512 01:21:38.903716 0, 0xFFFF, sum = 0
4513 01:21:38.907090 1, 0xFFFF, sum = 0
4514 01:21:38.907173 2, 0xFFFF, sum = 0
4515 01:21:38.909958 3, 0xFFFF, sum = 0
4516 01:21:38.910041 4, 0xFFFF, sum = 0
4517 01:21:38.913848 5, 0xFFFF, sum = 0
4518 01:21:38.913963 6, 0xFFFF, sum = 0
4519 01:21:38.916539 7, 0xFFFF, sum = 0
4520 01:21:38.916621 8, 0x0, sum = 1
4521 01:21:38.920005 9, 0x0, sum = 2
4522 01:21:38.920087 10, 0x0, sum = 3
4523 01:21:38.923453 11, 0x0, sum = 4
4524 01:21:38.923535 best_step = 9
4525 01:21:38.923599
4526 01:21:38.923659 ==
4527 01:21:38.926359 Dram Type= 6, Freq= 0, CH_1, rank 0
4528 01:21:38.930303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4529 01:21:38.930385 ==
4530 01:21:38.933111 RX Vref Scan: 1
4531 01:21:38.933192
4532 01:21:38.936521 RX Vref 0 -> 0, step: 1
4533 01:21:38.936602
4534 01:21:38.936665 RX Delay -179 -> 252, step: 8
4535 01:21:38.936724
4536 01:21:38.940039 Set Vref, RX VrefLevel [Byte0]: 53
4537 01:21:38.943360 [Byte1]: 53
4538 01:21:38.947821
4539 01:21:38.947940 Final RX Vref Byte 0 = 53 to rank0
4540 01:21:38.950979 Final RX Vref Byte 1 = 53 to rank0
4541 01:21:38.954508 Final RX Vref Byte 0 = 53 to rank1
4542 01:21:38.957789 Final RX Vref Byte 1 = 53 to rank1==
4543 01:21:38.960971 Dram Type= 6, Freq= 0, CH_1, rank 0
4544 01:21:38.967532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4545 01:21:38.967614 ==
4546 01:21:38.967679 DQS Delay:
4547 01:21:38.970932 DQS0 = 0, DQS1 = 0
4548 01:21:38.971014 DQM Delay:
4549 01:21:38.971078 DQM0 = 41, DQM1 = 34
4550 01:21:38.974090 DQ Delay:
4551 01:21:38.977587 DQ0 =48, DQ1 =36, DQ2 =32, DQ3 =40
4552 01:21:38.980476 DQ4 =36, DQ5 =48, DQ6 =56, DQ7 =36
4553 01:21:38.983748 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4554 01:21:38.987034 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4555 01:21:38.987115
4556 01:21:38.987179
4557 01:21:38.993777 [DQSOSCAuto] RK0, (LSB)MR18= 0x2640, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
4558 01:21:38.997077 CH1 RK0: MR19=808, MR18=2640
4559 01:21:39.003614 CH1_RK0: MR19=0x808, MR18=0x2640, DQSOSC=397, MR23=63, INC=166, DEC=110
4560 01:21:39.003696
4561 01:21:39.006899 ----->DramcWriteLeveling(PI) begin...
4562 01:21:39.006981 ==
4563 01:21:39.010480 Dram Type= 6, Freq= 0, CH_1, rank 1
4564 01:21:39.013899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 01:21:39.013982 ==
4566 01:21:39.016816 Write leveling (Byte 0): 27 => 27
4567 01:21:39.019914 Write leveling (Byte 1): 30 => 30
4568 01:21:39.023276 DramcWriteLeveling(PI) end<-----
4569 01:21:39.023357
4570 01:21:39.023420 ==
4571 01:21:39.026436 Dram Type= 6, Freq= 0, CH_1, rank 1
4572 01:21:39.033511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 01:21:39.033593 ==
4574 01:21:39.036177 [Gating] SW mode calibration
4575 01:21:39.042912 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4576 01:21:39.046330 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4577 01:21:39.052928 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4578 01:21:39.056206 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4579 01:21:39.059560 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4580 01:21:39.065828 0 9 12 | B1->B0 | 2f2f 2d2d | 0 0 | (0 0) (0 0)
4581 01:21:39.069482 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4582 01:21:39.072773 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4583 01:21:39.079290 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4584 01:21:39.083072 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4585 01:21:39.086227 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4586 01:21:39.092556 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4587 01:21:39.095441 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4588 01:21:39.099327 0 10 12 | B1->B0 | 3131 3d3d | 1 0 | (0 0) (0 0)
4589 01:21:39.105498 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4590 01:21:39.108737 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4591 01:21:39.112292 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4592 01:21:39.118844 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4593 01:21:39.122191 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4594 01:21:39.125274 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4595 01:21:39.132013 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4596 01:21:39.135311 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4597 01:21:39.138600 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4598 01:21:39.144720 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4599 01:21:39.148110 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4600 01:21:39.151599 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4601 01:21:39.157903 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4602 01:21:39.161299 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4603 01:21:39.164864 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 01:21:39.171350 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 01:21:39.174383 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 01:21:39.177890 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 01:21:39.184356 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 01:21:39.187419 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 01:21:39.190936 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 01:21:39.197495 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 01:21:39.200884 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 01:21:39.204272 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 01:21:39.207138 Total UI for P1: 0, mck2ui 16
4614 01:21:39.211075 best dqsien dly found for B0: ( 0, 13, 10)
4615 01:21:39.214144 Total UI for P1: 0, mck2ui 16
4616 01:21:39.217069 best dqsien dly found for B1: ( 0, 13, 10)
4617 01:21:39.220563 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4618 01:21:39.223753 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4619 01:21:39.227194
4620 01:21:39.230676 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4621 01:21:39.233662 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4622 01:21:39.237031 [Gating] SW calibration Done
4623 01:21:39.237112 ==
4624 01:21:39.240305 Dram Type= 6, Freq= 0, CH_1, rank 1
4625 01:21:39.243578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4626 01:21:39.243662 ==
4627 01:21:39.246517 RX Vref Scan: 0
4628 01:21:39.246598
4629 01:21:39.246662 RX Vref 0 -> 0, step: 1
4630 01:21:39.246722
4631 01:21:39.249939 RX Delay -230 -> 252, step: 16
4632 01:21:39.253284 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4633 01:21:39.259861 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4634 01:21:39.263093 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4635 01:21:39.266879 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4636 01:21:39.269804 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4637 01:21:39.276165 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4638 01:21:39.279728 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4639 01:21:39.283238 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4640 01:21:39.286067 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4641 01:21:39.289789 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4642 01:21:39.296548 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4643 01:21:39.299172 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4644 01:21:39.303237 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4645 01:21:39.305947 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4646 01:21:39.312699 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4647 01:21:39.315833 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4648 01:21:39.315921 ==
4649 01:21:39.319268 Dram Type= 6, Freq= 0, CH_1, rank 1
4650 01:21:39.322693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4651 01:21:39.322776 ==
4652 01:21:39.325540 DQS Delay:
4653 01:21:39.325622 DQS0 = 0, DQS1 = 0
4654 01:21:39.329209 DQM Delay:
4655 01:21:39.329290 DQM0 = 43, DQM1 = 41
4656 01:21:39.329355 DQ Delay:
4657 01:21:39.332280 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4658 01:21:39.335495 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4659 01:21:39.338581 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4660 01:21:39.342015 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4661 01:21:39.342099
4662 01:21:39.345426
4663 01:21:39.345508 ==
4664 01:21:39.348861 Dram Type= 6, Freq= 0, CH_1, rank 1
4665 01:21:39.351771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4666 01:21:39.351859 ==
4667 01:21:39.351931
4668 01:21:39.351991
4669 01:21:39.355284 TX Vref Scan disable
4670 01:21:39.355366 == TX Byte 0 ==
4671 01:21:39.361648 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4672 01:21:39.365124 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4673 01:21:39.365207 == TX Byte 1 ==
4674 01:21:39.371717 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4675 01:21:39.375479 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4676 01:21:39.375561 ==
4677 01:21:39.378762 Dram Type= 6, Freq= 0, CH_1, rank 1
4678 01:21:39.381975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4679 01:21:39.382058 ==
4680 01:21:39.382122
4681 01:21:39.382181
4682 01:21:39.384801 TX Vref Scan disable
4683 01:21:39.388157 == TX Byte 0 ==
4684 01:21:39.391471 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4685 01:21:39.398290 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4686 01:21:39.398406 == TX Byte 1 ==
4687 01:21:39.401710 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4688 01:21:39.408018 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4689 01:21:39.408101
4690 01:21:39.408166 [DATLAT]
4691 01:21:39.408226 Freq=600, CH1 RK1
4692 01:21:39.408285
4693 01:21:39.411010 DATLAT Default: 0x9
4694 01:21:39.414562 0, 0xFFFF, sum = 0
4695 01:21:39.414645 1, 0xFFFF, sum = 0
4696 01:21:39.417811 2, 0xFFFF, sum = 0
4697 01:21:39.417894 3, 0xFFFF, sum = 0
4698 01:21:39.420819 4, 0xFFFF, sum = 0
4699 01:21:39.420902 5, 0xFFFF, sum = 0
4700 01:21:39.424405 6, 0xFFFF, sum = 0
4701 01:21:39.424489 7, 0xFFFF, sum = 0
4702 01:21:39.427729 8, 0x0, sum = 1
4703 01:21:39.427812 9, 0x0, sum = 2
4704 01:21:39.430763 10, 0x0, sum = 3
4705 01:21:39.430846 11, 0x0, sum = 4
4706 01:21:39.430911 best_step = 9
4707 01:21:39.430971
4708 01:21:39.434521 ==
4709 01:21:39.437807 Dram Type= 6, Freq= 0, CH_1, rank 1
4710 01:21:39.440655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4711 01:21:39.440737 ==
4712 01:21:39.440802 RX Vref Scan: 0
4713 01:21:39.440862
4714 01:21:39.444367 RX Vref 0 -> 0, step: 1
4715 01:21:39.444469
4716 01:21:39.447510 RX Delay -179 -> 252, step: 8
4717 01:21:39.454082 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4718 01:21:39.457316 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4719 01:21:39.460400 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4720 01:21:39.463861 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4721 01:21:39.470373 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4722 01:21:39.473598 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4723 01:21:39.476616 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4724 01:21:39.480090 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4725 01:21:39.483496 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4726 01:21:39.490489 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4727 01:21:39.493528 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4728 01:21:39.496477 iDelay=205, Bit 11, Center 28 (-131 ~ 188) 320
4729 01:21:39.499936 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4730 01:21:39.506375 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4731 01:21:39.509859 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4732 01:21:39.513136 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4733 01:21:39.513217 ==
4734 01:21:39.516695 Dram Type= 6, Freq= 0, CH_1, rank 1
4735 01:21:39.523529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4736 01:21:39.523611 ==
4737 01:21:39.523676 DQS Delay:
4738 01:21:39.526614 DQS0 = 0, DQS1 = 0
4739 01:21:39.526696 DQM Delay:
4740 01:21:39.526760 DQM0 = 37, DQM1 = 35
4741 01:21:39.529763 DQ Delay:
4742 01:21:39.532808 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =32
4743 01:21:39.536492 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4744 01:21:39.539450 DQ8 =20, DQ9 =24, DQ10 =40, DQ11 =28
4745 01:21:39.543273 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =44
4746 01:21:39.543355
4747 01:21:39.543419
4748 01:21:39.549212 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c50, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
4749 01:21:39.552639 CH1 RK1: MR19=808, MR18=2C50
4750 01:21:39.559059 CH1_RK1: MR19=0x808, MR18=0x2C50, DQSOSC=394, MR23=63, INC=168, DEC=112
4751 01:21:39.562524 [RxdqsGatingPostProcess] freq 600
4752 01:21:39.569062 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4753 01:21:39.569144 Pre-setting of DQS Precalculation
4754 01:21:39.575596 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4755 01:21:39.582486 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4756 01:21:39.589001 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4757 01:21:39.589111
4758 01:21:39.589203
4759 01:21:39.592095 [Calibration Summary] 1200 Mbps
4760 01:21:39.595701 CH 0, Rank 0
4761 01:21:39.595781 SW Impedance : PASS
4762 01:21:39.598661 DUTY Scan : NO K
4763 01:21:39.598743 ZQ Calibration : PASS
4764 01:21:39.602267 Jitter Meter : NO K
4765 01:21:39.605265 CBT Training : PASS
4766 01:21:39.605347 Write leveling : PASS
4767 01:21:39.608497 RX DQS gating : PASS
4768 01:21:39.611716 RX DQ/DQS(RDDQC) : PASS
4769 01:21:39.611796 TX DQ/DQS : PASS
4770 01:21:39.614955 RX DATLAT : PASS
4771 01:21:39.618181 RX DQ/DQS(Engine): PASS
4772 01:21:39.618264 TX OE : NO K
4773 01:21:39.621901 All Pass.
4774 01:21:39.621997
4775 01:21:39.622062 CH 0, Rank 1
4776 01:21:39.624899 SW Impedance : PASS
4777 01:21:39.624980 DUTY Scan : NO K
4778 01:21:39.628510 ZQ Calibration : PASS
4779 01:21:39.631443 Jitter Meter : NO K
4780 01:21:39.631541 CBT Training : PASS
4781 01:21:39.635093 Write leveling : PASS
4782 01:21:39.637963 RX DQS gating : PASS
4783 01:21:39.638045 RX DQ/DQS(RDDQC) : PASS
4784 01:21:39.641213 TX DQ/DQS : PASS
4785 01:21:39.644902 RX DATLAT : PASS
4786 01:21:39.644984 RX DQ/DQS(Engine): PASS
4787 01:21:39.648080 TX OE : NO K
4788 01:21:39.648162 All Pass.
4789 01:21:39.648228
4790 01:21:39.651079 CH 1, Rank 0
4791 01:21:39.651160 SW Impedance : PASS
4792 01:21:39.654820 DUTY Scan : NO K
4793 01:21:39.657725 ZQ Calibration : PASS
4794 01:21:39.657807 Jitter Meter : NO K
4795 01:21:39.661037 CBT Training : PASS
4796 01:21:39.664092 Write leveling : PASS
4797 01:21:39.664199 RX DQS gating : PASS
4798 01:21:39.667490 RX DQ/DQS(RDDQC) : PASS
4799 01:21:39.670864 TX DQ/DQS : PASS
4800 01:21:39.670947 RX DATLAT : PASS
4801 01:21:39.674288 RX DQ/DQS(Engine): PASS
4802 01:21:39.677448 TX OE : NO K
4803 01:21:39.677530 All Pass.
4804 01:21:39.677595
4805 01:21:39.677655 CH 1, Rank 1
4806 01:21:39.681049 SW Impedance : PASS
4807 01:21:39.684017 DUTY Scan : NO K
4808 01:21:39.684099 ZQ Calibration : PASS
4809 01:21:39.687105 Jitter Meter : NO K
4810 01:21:39.690399 CBT Training : PASS
4811 01:21:39.690481 Write leveling : PASS
4812 01:21:39.693782 RX DQS gating : PASS
4813 01:21:39.693864 RX DQ/DQS(RDDQC) : PASS
4814 01:21:39.697034 TX DQ/DQS : PASS
4815 01:21:39.700736 RX DATLAT : PASS
4816 01:21:39.700850 RX DQ/DQS(Engine): PASS
4817 01:21:39.703769 TX OE : NO K
4818 01:21:39.703851 All Pass.
4819 01:21:39.703957
4820 01:21:39.707212 DramC Write-DBI off
4821 01:21:39.710248 PER_BANK_REFRESH: Hybrid Mode
4822 01:21:39.710361 TX_TRACKING: ON
4823 01:21:39.720395 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4824 01:21:39.723628 [FAST_K] Save calibration result to emmc
4825 01:21:39.726705 dramc_set_vcore_voltage set vcore to 662500
4826 01:21:39.730056 Read voltage for 933, 3
4827 01:21:39.730137 Vio18 = 0
4828 01:21:39.733280 Vcore = 662500
4829 01:21:39.733361 Vdram = 0
4830 01:21:39.733425 Vddq = 0
4831 01:21:39.733484 Vmddr = 0
4832 01:21:39.739630 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4833 01:21:39.746714 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4834 01:21:39.746828 MEM_TYPE=3, freq_sel=17
4835 01:21:39.749437 sv_algorithm_assistance_LP4_1600
4836 01:21:39.756070 ============ PULL DRAM RESETB DOWN ============
4837 01:21:39.759265 ========== PULL DRAM RESETB DOWN end =========
4838 01:21:39.762564 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4839 01:21:39.766261 ===================================
4840 01:21:39.769666 LPDDR4 DRAM CONFIGURATION
4841 01:21:39.772428 ===================================
4842 01:21:39.772518 EX_ROW_EN[0] = 0x0
4843 01:21:39.775772 EX_ROW_EN[1] = 0x0
4844 01:21:39.779686 LP4Y_EN = 0x0
4845 01:21:39.779792 WORK_FSP = 0x0
4846 01:21:39.782614 WL = 0x3
4847 01:21:39.782695 RL = 0x3
4848 01:21:39.785682 BL = 0x2
4849 01:21:39.785763 RPST = 0x0
4850 01:21:39.789296 RD_PRE = 0x0
4851 01:21:39.789376 WR_PRE = 0x1
4852 01:21:39.792641 WR_PST = 0x0
4853 01:21:39.792721 DBI_WR = 0x0
4854 01:21:39.795766 DBI_RD = 0x0
4855 01:21:39.795872 OTF = 0x1
4856 01:21:39.798927 ===================================
4857 01:21:39.802311 ===================================
4858 01:21:39.805317 ANA top config
4859 01:21:39.808400 ===================================
4860 01:21:39.811823 DLL_ASYNC_EN = 0
4861 01:21:39.811959 ALL_SLAVE_EN = 1
4862 01:21:39.815562 NEW_RANK_MODE = 1
4863 01:21:39.818480 DLL_IDLE_MODE = 1
4864 01:21:39.821620 LP45_APHY_COMB_EN = 1
4865 01:21:39.824824 TX_ODT_DIS = 1
4866 01:21:39.824905 NEW_8X_MODE = 1
4867 01:21:39.828245 ===================================
4868 01:21:39.831888 ===================================
4869 01:21:39.834841 data_rate = 1866
4870 01:21:39.838424 CKR = 1
4871 01:21:39.841568 DQ_P2S_RATIO = 8
4872 01:21:39.845139 ===================================
4873 01:21:39.847996 CA_P2S_RATIO = 8
4874 01:21:39.851695 DQ_CA_OPEN = 0
4875 01:21:39.851776 DQ_SEMI_OPEN = 0
4876 01:21:39.854678 CA_SEMI_OPEN = 0
4877 01:21:39.858294 CA_FULL_RATE = 0
4878 01:21:39.861615 DQ_CKDIV4_EN = 1
4879 01:21:39.864457 CA_CKDIV4_EN = 1
4880 01:21:39.867770 CA_PREDIV_EN = 0
4881 01:21:39.867877 PH8_DLY = 0
4882 01:21:39.871317 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4883 01:21:39.874290 DQ_AAMCK_DIV = 4
4884 01:21:39.878065 CA_AAMCK_DIV = 4
4885 01:21:39.881426 CA_ADMCK_DIV = 4
4886 01:21:39.884646 DQ_TRACK_CA_EN = 0
4887 01:21:39.887772 CA_PICK = 933
4888 01:21:39.887852 CA_MCKIO = 933
4889 01:21:39.890732 MCKIO_SEMI = 0
4890 01:21:39.894083 PLL_FREQ = 3732
4891 01:21:39.897651 DQ_UI_PI_RATIO = 32
4892 01:21:39.900814 CA_UI_PI_RATIO = 0
4893 01:21:39.904293 ===================================
4894 01:21:39.907573 ===================================
4895 01:21:39.910437 memory_type:LPDDR4
4896 01:21:39.910520 GP_NUM : 10
4897 01:21:39.914020 SRAM_EN : 1
4898 01:21:39.914101 MD32_EN : 0
4899 01:21:39.917227 ===================================
4900 01:21:39.920506 [ANA_INIT] >>>>>>>>>>>>>>
4901 01:21:39.923773 <<<<<< [CONFIGURE PHASE]: ANA_TX
4902 01:21:39.927053 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4903 01:21:39.930593 ===================================
4904 01:21:39.933465 data_rate = 1866,PCW = 0X8f00
4905 01:21:39.937286 ===================================
4906 01:21:39.940410 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4907 01:21:39.946910 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4908 01:21:39.950127 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4909 01:21:39.956873 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4910 01:21:39.959910 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4911 01:21:39.963416 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4912 01:21:39.963498 [ANA_INIT] flow start
4913 01:21:39.966721 [ANA_INIT] PLL >>>>>>>>
4914 01:21:39.970152 [ANA_INIT] PLL <<<<<<<<
4915 01:21:39.973021 [ANA_INIT] MIDPI >>>>>>>>
4916 01:21:39.973104 [ANA_INIT] MIDPI <<<<<<<<
4917 01:21:39.976343 [ANA_INIT] DLL >>>>>>>>
4918 01:21:39.979948 [ANA_INIT] flow end
4919 01:21:39.983011 ============ LP4 DIFF to SE enter ============
4920 01:21:39.986544 ============ LP4 DIFF to SE exit ============
4921 01:21:39.989779 [ANA_INIT] <<<<<<<<<<<<<
4922 01:21:39.992914 [Flow] Enable top DCM control >>>>>
4923 01:21:39.996309 [Flow] Enable top DCM control <<<<<
4924 01:21:39.999811 Enable DLL master slave shuffle
4925 01:21:40.002395 ==============================================================
4926 01:21:40.005654 Gating Mode config
4927 01:21:40.012276 ==============================================================
4928 01:21:40.012358 Config description:
4929 01:21:40.022428 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4930 01:21:40.029290 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4931 01:21:40.035655 SELPH_MODE 0: By rank 1: By Phase
4932 01:21:40.038995 ==============================================================
4933 01:21:40.042128 GAT_TRACK_EN = 1
4934 01:21:40.045412 RX_GATING_MODE = 2
4935 01:21:40.048844 RX_GATING_TRACK_MODE = 2
4936 01:21:40.051761 SELPH_MODE = 1
4937 01:21:40.055264 PICG_EARLY_EN = 1
4938 01:21:40.058751 VALID_LAT_VALUE = 1
4939 01:21:40.062315 ==============================================================
4940 01:21:40.065371 Enter into Gating configuration >>>>
4941 01:21:40.068166 Exit from Gating configuration <<<<
4942 01:21:40.071693 Enter into DVFS_PRE_config >>>>>
4943 01:21:40.084468 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4944 01:21:40.088018 Exit from DVFS_PRE_config <<<<<
4945 01:21:40.091218 Enter into PICG configuration >>>>
4946 01:21:40.094763 Exit from PICG configuration <<<<
4947 01:21:40.097946 [RX_INPUT] configuration >>>>>
4948 01:21:40.098020 [RX_INPUT] configuration <<<<<
4949 01:21:40.104289 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4950 01:21:40.111340 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4951 01:21:40.114580 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4952 01:21:40.120717 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4953 01:21:40.127800 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4954 01:21:40.134328 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4955 01:21:40.137282 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4956 01:21:40.140980 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4957 01:21:40.147234 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4958 01:21:40.150451 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4959 01:21:40.154102 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4960 01:21:40.160402 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4961 01:21:40.163836 ===================================
4962 01:21:40.163926 LPDDR4 DRAM CONFIGURATION
4963 01:21:40.167122 ===================================
4964 01:21:40.170524 EX_ROW_EN[0] = 0x0
4965 01:21:40.173438 EX_ROW_EN[1] = 0x0
4966 01:21:40.173519 LP4Y_EN = 0x0
4967 01:21:40.176692 WORK_FSP = 0x0
4968 01:21:40.176772 WL = 0x3
4969 01:21:40.180206 RL = 0x3
4970 01:21:40.180286 BL = 0x2
4971 01:21:40.183666 RPST = 0x0
4972 01:21:40.183746 RD_PRE = 0x0
4973 01:21:40.186754 WR_PRE = 0x1
4974 01:21:40.186835 WR_PST = 0x0
4975 01:21:40.189944 DBI_WR = 0x0
4976 01:21:40.190025 DBI_RD = 0x0
4977 01:21:40.192975 OTF = 0x1
4978 01:21:40.196861 ===================================
4979 01:21:40.199784 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4980 01:21:40.203117 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4981 01:21:40.209634 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4982 01:21:40.213143 ===================================
4983 01:21:40.213224 LPDDR4 DRAM CONFIGURATION
4984 01:21:40.216694 ===================================
4985 01:21:40.219583 EX_ROW_EN[0] = 0x10
4986 01:21:40.222881 EX_ROW_EN[1] = 0x0
4987 01:21:40.222962 LP4Y_EN = 0x0
4988 01:21:40.226052 WORK_FSP = 0x0
4989 01:21:40.226132 WL = 0x3
4990 01:21:40.229346 RL = 0x3
4991 01:21:40.229427 BL = 0x2
4992 01:21:40.232864 RPST = 0x0
4993 01:21:40.232945 RD_PRE = 0x0
4994 01:21:40.235869 WR_PRE = 0x1
4995 01:21:40.235984 WR_PST = 0x0
4996 01:21:40.239118 DBI_WR = 0x0
4997 01:21:40.239197 DBI_RD = 0x0
4998 01:21:40.242663 OTF = 0x1
4999 01:21:40.245818 ===================================
5000 01:21:40.252785 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5001 01:21:40.256123 nWR fixed to 30
5002 01:21:40.258924 [ModeRegInit_LP4] CH0 RK0
5003 01:21:40.259004 [ModeRegInit_LP4] CH0 RK1
5004 01:21:40.262396 [ModeRegInit_LP4] CH1 RK0
5005 01:21:40.265448 [ModeRegInit_LP4] CH1 RK1
5006 01:21:40.265529 match AC timing 9
5007 01:21:40.271833 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5008 01:21:40.275014 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5009 01:21:40.278342 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5010 01:21:40.285347 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5011 01:21:40.288208 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5012 01:21:40.288289 ==
5013 01:21:40.291773 Dram Type= 6, Freq= 0, CH_0, rank 0
5014 01:21:40.295011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5015 01:21:40.298681 ==
5016 01:21:40.301449 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5017 01:21:40.308284 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5018 01:21:40.312034 [CA 0] Center 37 (7~68) winsize 62
5019 01:21:40.314733 [CA 1] Center 37 (7~68) winsize 62
5020 01:21:40.318377 [CA 2] Center 34 (4~64) winsize 61
5021 01:21:40.321147 [CA 3] Center 34 (4~65) winsize 62
5022 01:21:40.324483 [CA 4] Center 33 (3~64) winsize 62
5023 01:21:40.327777 [CA 5] Center 32 (2~63) winsize 62
5024 01:21:40.327858
5025 01:21:40.331029 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5026 01:21:40.331111
5027 01:21:40.334397 [CATrainingPosCal] consider 1 rank data
5028 01:21:40.338175 u2DelayCellTimex100 = 270/100 ps
5029 01:21:40.341432 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5030 01:21:40.344721 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5031 01:21:40.348342 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5032 01:21:40.354300 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5033 01:21:40.357720 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5034 01:21:40.361105 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5035 01:21:40.361186
5036 01:21:40.364676 CA PerBit enable=1, Macro0, CA PI delay=32
5037 01:21:40.364756
5038 01:21:40.367460 [CBTSetCACLKResult] CA Dly = 32
5039 01:21:40.367541 CS Dly: 5 (0~36)
5040 01:21:40.367604 ==
5041 01:21:40.370689 Dram Type= 6, Freq= 0, CH_0, rank 1
5042 01:21:40.377287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5043 01:21:40.377403 ==
5044 01:21:40.380947 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5045 01:21:40.387427 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5046 01:21:40.390614 [CA 0] Center 38 (7~69) winsize 63
5047 01:21:40.394064 [CA 1] Center 37 (7~68) winsize 62
5048 01:21:40.397595 [CA 2] Center 34 (4~65) winsize 62
5049 01:21:40.400802 [CA 3] Center 34 (4~65) winsize 62
5050 01:21:40.403827 [CA 4] Center 33 (3~64) winsize 62
5051 01:21:40.407376 [CA 5] Center 32 (2~63) winsize 62
5052 01:21:40.407456
5053 01:21:40.410770 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5054 01:21:40.410850
5055 01:21:40.413966 [CATrainingPosCal] consider 2 rank data
5056 01:21:40.416956 u2DelayCellTimex100 = 270/100 ps
5057 01:21:40.420451 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5058 01:21:40.427518 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5059 01:21:40.430021 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5060 01:21:40.433303 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5061 01:21:40.436742 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5062 01:21:40.439860 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5063 01:21:40.439982
5064 01:21:40.443237 CA PerBit enable=1, Macro0, CA PI delay=32
5065 01:21:40.443317
5066 01:21:40.446821 [CBTSetCACLKResult] CA Dly = 32
5067 01:21:40.450028 CS Dly: 6 (0~39)
5068 01:21:40.450110
5069 01:21:40.453258 ----->DramcWriteLeveling(PI) begin...
5070 01:21:40.453341 ==
5071 01:21:40.456396 Dram Type= 6, Freq= 0, CH_0, rank 0
5072 01:21:40.460128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5073 01:21:40.460210 ==
5074 01:21:40.462536 Write leveling (Byte 0): 30 => 30
5075 01:21:40.466324 Write leveling (Byte 1): 28 => 28
5076 01:21:40.469508 DramcWriteLeveling(PI) end<-----
5077 01:21:40.469589
5078 01:21:40.469652 ==
5079 01:21:40.472757 Dram Type= 6, Freq= 0, CH_0, rank 0
5080 01:21:40.476026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5081 01:21:40.476107 ==
5082 01:21:40.479190 [Gating] SW mode calibration
5083 01:21:40.486219 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5084 01:21:40.492207 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5085 01:21:40.496268 0 14 0 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
5086 01:21:40.502366 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5087 01:21:40.505303 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5088 01:21:40.509450 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5089 01:21:40.515542 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5090 01:21:40.518502 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5091 01:21:40.522012 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5092 01:21:40.528393 0 14 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
5093 01:21:40.532003 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
5094 01:21:40.535519 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5095 01:21:40.541576 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5096 01:21:40.544959 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5097 01:21:40.548528 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5098 01:21:40.554838 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5099 01:21:40.558290 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5100 01:21:40.561460 0 15 28 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
5101 01:21:40.568264 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5102 01:21:40.571359 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5103 01:21:40.574508 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5104 01:21:40.581394 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5105 01:21:40.584312 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5106 01:21:40.587834 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5107 01:21:40.594240 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5108 01:21:40.597752 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5109 01:21:40.601114 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5110 01:21:40.607426 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5111 01:21:40.610662 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5112 01:21:40.613845 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5113 01:21:40.620394 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5114 01:21:40.623777 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 01:21:40.627104 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 01:21:40.633778 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 01:21:40.637560 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 01:21:40.640561 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 01:21:40.647075 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 01:21:40.650240 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 01:21:40.653931 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 01:21:40.660131 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 01:21:40.663477 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 01:21:40.667239 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 01:21:40.673386 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5126 01:21:40.676883 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 01:21:40.680062 Total UI for P1: 0, mck2ui 16
5128 01:21:40.683125 best dqsien dly found for B0: ( 1, 3, 0)
5129 01:21:40.686321 Total UI for P1: 0, mck2ui 16
5130 01:21:40.689590 best dqsien dly found for B1: ( 1, 3, 0)
5131 01:21:40.693162 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5132 01:21:40.696070 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5133 01:21:40.696151
5134 01:21:40.699252 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5135 01:21:40.702761 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5136 01:21:40.706457 [Gating] SW calibration Done
5137 01:21:40.706538 ==
5138 01:21:40.709351 Dram Type= 6, Freq= 0, CH_0, rank 0
5139 01:21:40.716327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5140 01:21:40.716409 ==
5141 01:21:40.716474 RX Vref Scan: 0
5142 01:21:40.716533
5143 01:21:40.719105 RX Vref 0 -> 0, step: 1
5144 01:21:40.719186
5145 01:21:40.722456 RX Delay -80 -> 252, step: 8
5146 01:21:40.726030 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5147 01:21:40.729029 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5148 01:21:40.732387 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5149 01:21:40.735688 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5150 01:21:40.742287 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5151 01:21:40.745575 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5152 01:21:40.748904 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5153 01:21:40.752672 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5154 01:21:40.755794 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5155 01:21:40.758706 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5156 01:21:40.765482 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5157 01:21:40.769131 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5158 01:21:40.771976 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5159 01:21:40.775416 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5160 01:21:40.778582 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5161 01:21:40.784944 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5162 01:21:40.785025 ==
5163 01:21:40.788559 Dram Type= 6, Freq= 0, CH_0, rank 0
5164 01:21:40.791849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5165 01:21:40.791976 ==
5166 01:21:40.792042 DQS Delay:
5167 01:21:40.794812 DQS0 = 0, DQS1 = 0
5168 01:21:40.794892 DQM Delay:
5169 01:21:40.798089 DQM0 = 98, DQM1 = 89
5170 01:21:40.798170 DQ Delay:
5171 01:21:40.801322 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5172 01:21:40.804824 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5173 01:21:40.808310 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5174 01:21:40.811301 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5175 01:21:40.811382
5176 01:21:40.811446
5177 01:21:40.811504 ==
5178 01:21:40.815148 Dram Type= 6, Freq= 0, CH_0, rank 0
5179 01:21:40.818423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5180 01:21:40.821144 ==
5181 01:21:40.821224
5182 01:21:40.821288
5183 01:21:40.821346 TX Vref Scan disable
5184 01:21:40.824334 == TX Byte 0 ==
5185 01:21:40.827568 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5186 01:21:40.834129 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5187 01:21:40.834209 == TX Byte 1 ==
5188 01:21:40.837578 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5189 01:21:40.844158 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5190 01:21:40.844239 ==
5191 01:21:40.847291 Dram Type= 6, Freq= 0, CH_0, rank 0
5192 01:21:40.851082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5193 01:21:40.851163 ==
5194 01:21:40.851227
5195 01:21:40.851287
5196 01:21:40.854636 TX Vref Scan disable
5197 01:21:40.854717 == TX Byte 0 ==
5198 01:21:40.860840 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5199 01:21:40.863875 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5200 01:21:40.867051 == TX Byte 1 ==
5201 01:21:40.870777 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5202 01:21:40.873657 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5203 01:21:40.873738
5204 01:21:40.873800 [DATLAT]
5205 01:21:40.877166 Freq=933, CH0 RK0
5206 01:21:40.877246
5207 01:21:40.880838 DATLAT Default: 0xd
5208 01:21:40.880945 0, 0xFFFF, sum = 0
5209 01:21:40.883961 1, 0xFFFF, sum = 0
5210 01:21:40.884072 2, 0xFFFF, sum = 0
5211 01:21:40.886992 3, 0xFFFF, sum = 0
5212 01:21:40.887074 4, 0xFFFF, sum = 0
5213 01:21:40.890211 5, 0xFFFF, sum = 0
5214 01:21:40.890319 6, 0xFFFF, sum = 0
5215 01:21:40.893644 7, 0xFFFF, sum = 0
5216 01:21:40.893746 8, 0xFFFF, sum = 0
5217 01:21:40.896556 9, 0xFFFF, sum = 0
5218 01:21:40.896652 10, 0x0, sum = 1
5219 01:21:40.900368 11, 0x0, sum = 2
5220 01:21:40.900450 12, 0x0, sum = 3
5221 01:21:40.903493 13, 0x0, sum = 4
5222 01:21:40.903575 best_step = 11
5223 01:21:40.903638
5224 01:21:40.903696 ==
5225 01:21:40.907220 Dram Type= 6, Freq= 0, CH_0, rank 0
5226 01:21:40.909835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5227 01:21:40.913140 ==
5228 01:21:40.913219 RX Vref Scan: 1
5229 01:21:40.913282
5230 01:21:40.916668 RX Vref 0 -> 0, step: 1
5231 01:21:40.916774
5232 01:21:40.920036 RX Delay -61 -> 252, step: 4
5233 01:21:40.920116
5234 01:21:40.922840 Set Vref, RX VrefLevel [Byte0]: 53
5235 01:21:40.926443 [Byte1]: 45
5236 01:21:40.926523
5237 01:21:40.929465 Final RX Vref Byte 0 = 53 to rank0
5238 01:21:40.932746 Final RX Vref Byte 1 = 45 to rank0
5239 01:21:40.936095 Final RX Vref Byte 0 = 53 to rank1
5240 01:21:40.939786 Final RX Vref Byte 1 = 45 to rank1==
5241 01:21:40.942417 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 01:21:40.945806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 01:21:40.945886 ==
5244 01:21:40.949093 DQS Delay:
5245 01:21:40.949172 DQS0 = 0, DQS1 = 0
5246 01:21:40.952546 DQM Delay:
5247 01:21:40.952626 DQM0 = 99, DQM1 = 86
5248 01:21:40.952689 DQ Delay:
5249 01:21:40.955693 DQ0 =100, DQ1 =98, DQ2 =96, DQ3 =96
5250 01:21:40.958968 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =106
5251 01:21:40.962304 DQ8 =76, DQ9 =72, DQ10 =86, DQ11 =82
5252 01:21:40.965920 DQ12 =94, DQ13 =92, DQ14 =96, DQ15 =94
5253 01:21:40.966000
5254 01:21:40.969354
5255 01:21:40.975347 [DQSOSCAuto] RK0, (LSB)MR18= 0x140e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
5256 01:21:40.978632 CH0 RK0: MR19=505, MR18=140E
5257 01:21:40.985262 CH0_RK0: MR19=0x505, MR18=0x140E, DQSOSC=415, MR23=63, INC=62, DEC=41
5258 01:21:40.985343
5259 01:21:40.988627 ----->DramcWriteLeveling(PI) begin...
5260 01:21:40.988727 ==
5261 01:21:40.992429 Dram Type= 6, Freq= 0, CH_0, rank 1
5262 01:21:40.995566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5263 01:21:40.995646 ==
5264 01:21:40.998728 Write leveling (Byte 0): 31 => 31
5265 01:21:41.001812 Write leveling (Byte 1): 29 => 29
5266 01:21:41.005117 DramcWriteLeveling(PI) end<-----
5267 01:21:41.005197
5268 01:21:41.005259 ==
5269 01:21:41.008536 Dram Type= 6, Freq= 0, CH_0, rank 1
5270 01:21:41.012271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 01:21:41.012378 ==
5272 01:21:41.015085 [Gating] SW mode calibration
5273 01:21:41.021893 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5274 01:21:41.028260 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5275 01:21:41.031796 0 14 0 | B1->B0 | 2727 3434 | 0 0 | (0 0) (1 1)
5276 01:21:41.038122 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5277 01:21:41.042204 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5278 01:21:41.045146 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5279 01:21:41.051121 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5280 01:21:41.054407 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5281 01:21:41.058069 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5282 01:21:41.064627 0 14 28 | B1->B0 | 3333 2b2b | 0 0 | (0 0) (0 1)
5283 01:21:41.067916 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (0 0) (0 0)
5284 01:21:41.070826 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5285 01:21:41.077944 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5286 01:21:41.080953 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5287 01:21:41.084143 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5288 01:21:41.090708 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5289 01:21:41.094598 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5290 01:21:41.097001 0 15 28 | B1->B0 | 2525 3939 | 0 0 | (0 0) (0 0)
5291 01:21:41.103772 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5292 01:21:41.106916 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5293 01:21:41.110151 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5294 01:21:41.116768 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5295 01:21:41.120181 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5296 01:21:41.123599 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5297 01:21:41.129880 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5298 01:21:41.133105 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5299 01:21:41.136822 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5300 01:21:41.143218 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5301 01:21:41.146421 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5302 01:21:41.149915 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5303 01:21:41.156658 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5304 01:21:41.159728 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5305 01:21:41.162830 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5306 01:21:41.169299 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 01:21:41.172919 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 01:21:41.175951 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 01:21:41.183089 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 01:21:41.185726 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 01:21:41.189448 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 01:21:41.196081 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 01:21:41.199221 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 01:21:41.202314 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5315 01:21:41.205802 Total UI for P1: 0, mck2ui 16
5316 01:21:41.209099 best dqsien dly found for B0: ( 1, 2, 26)
5317 01:21:41.215637 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5318 01:21:41.218604 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 01:21:41.222605 Total UI for P1: 0, mck2ui 16
5320 01:21:41.225706 best dqsien dly found for B1: ( 1, 3, 0)
5321 01:21:41.228888 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5322 01:21:41.231832 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5323 01:21:41.231978
5324 01:21:41.235000 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5325 01:21:41.238783 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5326 01:21:41.242404 [Gating] SW calibration Done
5327 01:21:41.242486 ==
5328 01:21:41.244882 Dram Type= 6, Freq= 0, CH_0, rank 1
5329 01:21:41.251631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5330 01:21:41.251713 ==
5331 01:21:41.251777 RX Vref Scan: 0
5332 01:21:41.251837
5333 01:21:41.254845 RX Vref 0 -> 0, step: 1
5334 01:21:41.254915
5335 01:21:41.258523 RX Delay -80 -> 252, step: 8
5336 01:21:41.261282 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5337 01:21:41.264674 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5338 01:21:41.267778 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5339 01:21:41.271293 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5340 01:21:41.277710 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5341 01:21:41.281275 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5342 01:21:41.284443 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5343 01:21:41.287703 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5344 01:21:41.291444 iDelay=200, Bit 8, Center 79 (-8 ~ 167) 176
5345 01:21:41.294478 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5346 01:21:41.301129 iDelay=200, Bit 10, Center 87 (0 ~ 175) 176
5347 01:21:41.304211 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5348 01:21:41.308142 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5349 01:21:41.310968 iDelay=200, Bit 13, Center 95 (8 ~ 183) 176
5350 01:21:41.313958 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5351 01:21:41.320430 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5352 01:21:41.320511 ==
5353 01:21:41.324060 Dram Type= 6, Freq= 0, CH_0, rank 1
5354 01:21:41.327426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5355 01:21:41.327507 ==
5356 01:21:41.327571 DQS Delay:
5357 01:21:41.330416 DQS0 = 0, DQS1 = 0
5358 01:21:41.330505 DQM Delay:
5359 01:21:41.333697 DQM0 = 97, DQM1 = 87
5360 01:21:41.333777 DQ Delay:
5361 01:21:41.336910 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5362 01:21:41.340342 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5363 01:21:41.343780 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5364 01:21:41.347456 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =91
5365 01:21:41.347536
5366 01:21:41.347599
5367 01:21:41.347657 ==
5368 01:21:41.350818 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 01:21:41.354069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 01:21:41.354150 ==
5371 01:21:41.356871
5372 01:21:41.356950
5373 01:21:41.357014 TX Vref Scan disable
5374 01:21:41.359890 == TX Byte 0 ==
5375 01:21:41.363550 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5376 01:21:41.366762 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5377 01:21:41.370378 == TX Byte 1 ==
5378 01:21:41.373477 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5379 01:21:41.376685 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5380 01:21:41.379760 ==
5381 01:21:41.383313 Dram Type= 6, Freq= 0, CH_0, rank 1
5382 01:21:41.386279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5383 01:21:41.386360 ==
5384 01:21:41.386424
5385 01:21:41.386482
5386 01:21:41.390009 TX Vref Scan disable
5387 01:21:41.390092 == TX Byte 0 ==
5388 01:21:41.396166 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5389 01:21:41.399842 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5390 01:21:41.399964 == TX Byte 1 ==
5391 01:21:41.406643 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5392 01:21:41.409895 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5393 01:21:41.409976
5394 01:21:41.410040 [DATLAT]
5395 01:21:41.412650 Freq=933, CH0 RK1
5396 01:21:41.412741
5397 01:21:41.412805 DATLAT Default: 0xb
5398 01:21:41.415845 0, 0xFFFF, sum = 0
5399 01:21:41.415959 1, 0xFFFF, sum = 0
5400 01:21:41.419033 2, 0xFFFF, sum = 0
5401 01:21:41.422721 3, 0xFFFF, sum = 0
5402 01:21:41.422802 4, 0xFFFF, sum = 0
5403 01:21:41.425847 5, 0xFFFF, sum = 0
5404 01:21:41.425929 6, 0xFFFF, sum = 0
5405 01:21:41.429325 7, 0xFFFF, sum = 0
5406 01:21:41.429407 8, 0xFFFF, sum = 0
5407 01:21:41.432062 9, 0xFFFF, sum = 0
5408 01:21:41.432148 10, 0x0, sum = 1
5409 01:21:41.435544 11, 0x0, sum = 2
5410 01:21:41.435653 12, 0x0, sum = 3
5411 01:21:41.438931 13, 0x0, sum = 4
5412 01:21:41.439013 best_step = 11
5413 01:21:41.439076
5414 01:21:41.439135 ==
5415 01:21:41.442095 Dram Type= 6, Freq= 0, CH_0, rank 1
5416 01:21:41.445612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5417 01:21:41.445693 ==
5418 01:21:41.449050 RX Vref Scan: 0
5419 01:21:41.449130
5420 01:21:41.452178 RX Vref 0 -> 0, step: 1
5421 01:21:41.452258
5422 01:21:41.452321 RX Delay -61 -> 252, step: 4
5423 01:21:41.460030 iDelay=195, Bit 0, Center 94 (7 ~ 182) 176
5424 01:21:41.463641 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5425 01:21:41.466668 iDelay=195, Bit 2, Center 92 (3 ~ 182) 180
5426 01:21:41.469730 iDelay=195, Bit 3, Center 96 (7 ~ 186) 180
5427 01:21:41.473111 iDelay=195, Bit 4, Center 102 (11 ~ 194) 184
5428 01:21:41.479816 iDelay=195, Bit 5, Center 88 (-1 ~ 178) 180
5429 01:21:41.482783 iDelay=195, Bit 6, Center 108 (23 ~ 194) 172
5430 01:21:41.486460 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5431 01:21:41.489626 iDelay=195, Bit 8, Center 78 (-9 ~ 166) 176
5432 01:21:41.492637 iDelay=195, Bit 9, Center 74 (-13 ~ 162) 176
5433 01:21:41.499412 iDelay=195, Bit 10, Center 88 (3 ~ 174) 172
5434 01:21:41.502875 iDelay=195, Bit 11, Center 80 (-5 ~ 166) 172
5435 01:21:41.506282 iDelay=195, Bit 12, Center 92 (7 ~ 178) 172
5436 01:21:41.509379 iDelay=195, Bit 13, Center 92 (7 ~ 178) 172
5437 01:21:41.512671 iDelay=195, Bit 14, Center 98 (15 ~ 182) 168
5438 01:21:41.515846 iDelay=195, Bit 15, Center 94 (11 ~ 178) 168
5439 01:21:41.519348 ==
5440 01:21:41.522684 Dram Type= 6, Freq= 0, CH_0, rank 1
5441 01:21:41.525508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5442 01:21:41.525590 ==
5443 01:21:41.525653 DQS Delay:
5444 01:21:41.528767 DQS0 = 0, DQS1 = 0
5445 01:21:41.528902 DQM Delay:
5446 01:21:41.532443 DQM0 = 97, DQM1 = 87
5447 01:21:41.532542 DQ Delay:
5448 01:21:41.535819 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =96
5449 01:21:41.538728 DQ4 =102, DQ5 =88, DQ6 =108, DQ7 =104
5450 01:21:41.542548 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =80
5451 01:21:41.545553 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =94
5452 01:21:41.545634
5453 01:21:41.545697
5454 01:21:41.552120 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 417 ps
5455 01:21:41.555240 CH0 RK1: MR19=505, MR18=E0B
5456 01:21:41.562414 CH0_RK1: MR19=0x505, MR18=0xE0B, DQSOSC=417, MR23=63, INC=62, DEC=41
5457 01:21:41.565337 [RxdqsGatingPostProcess] freq 933
5458 01:21:41.572092 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5459 01:21:41.575331 best DQS0 dly(2T, 0.5T) = (0, 11)
5460 01:21:41.575412 best DQS1 dly(2T, 0.5T) = (0, 11)
5461 01:21:41.578544 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5462 01:21:41.581667 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5463 01:21:41.585322 best DQS0 dly(2T, 0.5T) = (0, 10)
5464 01:21:41.588625 best DQS1 dly(2T, 0.5T) = (0, 11)
5465 01:21:41.591934 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5466 01:21:41.595046 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5467 01:21:41.598376 Pre-setting of DQS Precalculation
5468 01:21:41.604830 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5469 01:21:41.604911 ==
5470 01:21:41.608265 Dram Type= 6, Freq= 0, CH_1, rank 0
5471 01:21:41.611495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5472 01:21:41.611601 ==
5473 01:21:41.617963 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5474 01:21:41.624669 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5475 01:21:41.627542 [CA 0] Center 36 (6~67) winsize 62
5476 01:21:41.630951 [CA 1] Center 36 (6~67) winsize 62
5477 01:21:41.634166 [CA 2] Center 34 (4~65) winsize 62
5478 01:21:41.637339 [CA 3] Center 33 (3~64) winsize 62
5479 01:21:41.640544 [CA 4] Center 34 (4~65) winsize 62
5480 01:21:41.644201 [CA 5] Center 33 (3~64) winsize 62
5481 01:21:41.644282
5482 01:21:41.647414 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5483 01:21:41.647495
5484 01:21:41.650761 [CATrainingPosCal] consider 1 rank data
5485 01:21:41.654065 u2DelayCellTimex100 = 270/100 ps
5486 01:21:41.657150 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5487 01:21:41.660754 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5488 01:21:41.664024 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5489 01:21:41.666947 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5490 01:21:41.670424 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5491 01:21:41.673882 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5492 01:21:41.673963
5493 01:21:41.680450 CA PerBit enable=1, Macro0, CA PI delay=33
5494 01:21:41.680532
5495 01:21:41.683372 [CBTSetCACLKResult] CA Dly = 33
5496 01:21:41.683453 CS Dly: 5 (0~36)
5497 01:21:41.683517 ==
5498 01:21:41.686803 Dram Type= 6, Freq= 0, CH_1, rank 1
5499 01:21:41.690091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5500 01:21:41.690174 ==
5501 01:21:41.696564 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5502 01:21:41.703359 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5503 01:21:41.706608 [CA 0] Center 36 (6~66) winsize 61
5504 01:21:41.710094 [CA 1] Center 36 (6~67) winsize 62
5505 01:21:41.712991 [CA 2] Center 34 (4~65) winsize 62
5506 01:21:41.716245 [CA 3] Center 33 (3~64) winsize 62
5507 01:21:41.719358 [CA 4] Center 34 (4~64) winsize 61
5508 01:21:41.722859 [CA 5] Center 33 (3~64) winsize 62
5509 01:21:41.722940
5510 01:21:41.726609 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5511 01:21:41.726697
5512 01:21:41.729514 [CATrainingPosCal] consider 2 rank data
5513 01:21:41.732680 u2DelayCellTimex100 = 270/100 ps
5514 01:21:41.736592 CA0 delay=36 (6~66),Diff = 3 PI (18 cell)
5515 01:21:41.739151 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5516 01:21:41.742517 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5517 01:21:41.749084 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5518 01:21:41.752744 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5519 01:21:41.756062 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5520 01:21:41.756144
5521 01:21:41.759117 CA PerBit enable=1, Macro0, CA PI delay=33
5522 01:21:41.759198
5523 01:21:41.762775 [CBTSetCACLKResult] CA Dly = 33
5524 01:21:41.762856 CS Dly: 6 (0~38)
5525 01:21:41.762919
5526 01:21:41.765437 ----->DramcWriteLeveling(PI) begin...
5527 01:21:41.768926 ==
5528 01:21:41.772445 Dram Type= 6, Freq= 0, CH_1, rank 0
5529 01:21:41.775478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5530 01:21:41.775559 ==
5531 01:21:41.778842 Write leveling (Byte 0): 28 => 28
5532 01:21:41.782333 Write leveling (Byte 1): 30 => 30
5533 01:21:41.785493 DramcWriteLeveling(PI) end<-----
5534 01:21:41.785573
5535 01:21:41.785636 ==
5536 01:21:41.788676 Dram Type= 6, Freq= 0, CH_1, rank 0
5537 01:21:41.791875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5538 01:21:41.791994 ==
5539 01:21:41.795539 [Gating] SW mode calibration
5540 01:21:41.801921 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5541 01:21:41.808082 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5542 01:21:41.811674 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5543 01:21:41.815091 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5544 01:21:41.821331 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5545 01:21:41.824638 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5546 01:21:41.827809 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5547 01:21:41.834827 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5548 01:21:41.838025 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5549 01:21:41.840894 0 14 28 | B1->B0 | 2d2d 2626 | 0 0 | (0 0) (0 0)
5550 01:21:41.847993 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
5551 01:21:41.850888 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5552 01:21:41.854584 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5553 01:21:41.861109 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5554 01:21:41.864606 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5555 01:21:41.867457 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5556 01:21:41.874024 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5557 01:21:41.877459 0 15 28 | B1->B0 | 3333 3a3a | 1 1 | (0 0) (0 0)
5558 01:21:41.880636 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5559 01:21:41.887288 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5560 01:21:41.890919 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5561 01:21:41.893962 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5562 01:21:41.900387 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5563 01:21:41.903839 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5564 01:21:41.906912 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 01:21:41.913548 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5566 01:21:41.916773 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 01:21:41.921032 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 01:21:41.926549 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 01:21:41.930251 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 01:21:41.933220 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 01:21:41.940012 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 01:21:41.943210 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 01:21:41.946599 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 01:21:41.953043 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 01:21:41.956142 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 01:21:41.959391 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 01:21:41.966389 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 01:21:41.969187 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 01:21:41.972922 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 01:21:41.979165 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 01:21:41.982763 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5582 01:21:41.986101 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 01:21:41.989044 Total UI for P1: 0, mck2ui 16
5584 01:21:41.992644 best dqsien dly found for B0: ( 1, 2, 28)
5585 01:21:41.995712 Total UI for P1: 0, mck2ui 16
5586 01:21:41.999027 best dqsien dly found for B1: ( 1, 2, 28)
5587 01:21:42.002332 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5588 01:21:42.009565 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5589 01:21:42.009671
5590 01:21:42.012104 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5591 01:21:42.015981 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5592 01:21:42.018678 [Gating] SW calibration Done
5593 01:21:42.018784 ==
5594 01:21:42.021959 Dram Type= 6, Freq= 0, CH_1, rank 0
5595 01:21:42.025061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5596 01:21:42.025141 ==
5597 01:21:42.028707 RX Vref Scan: 0
5598 01:21:42.028785
5599 01:21:42.028868 RX Vref 0 -> 0, step: 1
5600 01:21:42.028966
5601 01:21:42.031533 RX Delay -80 -> 252, step: 8
5602 01:21:42.035010 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5603 01:21:42.041705 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5604 01:21:42.045132 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5605 01:21:42.048131 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5606 01:21:42.051369 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5607 01:21:42.054539 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5608 01:21:42.061355 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5609 01:21:42.064693 iDelay=208, Bit 7, Center 91 (0 ~ 183) 184
5610 01:21:42.067826 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5611 01:21:42.071205 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5612 01:21:42.074572 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5613 01:21:42.077402 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5614 01:21:42.084038 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5615 01:21:42.087342 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5616 01:21:42.090534 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5617 01:21:42.094415 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5618 01:21:42.094496 ==
5619 01:21:42.097841 Dram Type= 6, Freq= 0, CH_1, rank 0
5620 01:21:42.104505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5621 01:21:42.104587 ==
5622 01:21:42.104651 DQS Delay:
5623 01:21:42.107562 DQS0 = 0, DQS1 = 0
5624 01:21:42.107643 DQM Delay:
5625 01:21:42.107706 DQM0 = 100, DQM1 = 96
5626 01:21:42.110730 DQ Delay:
5627 01:21:42.113667 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =103
5628 01:21:42.117382 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =91
5629 01:21:42.120420 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5630 01:21:42.123621 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5631 01:21:42.123702
5632 01:21:42.123765
5633 01:21:42.123824 ==
5634 01:21:42.127170 Dram Type= 6, Freq= 0, CH_1, rank 0
5635 01:21:42.130583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5636 01:21:42.130664 ==
5637 01:21:42.130727
5638 01:21:42.133653
5639 01:21:42.133733 TX Vref Scan disable
5640 01:21:42.136955 == TX Byte 0 ==
5641 01:21:42.140386 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5642 01:21:42.143246 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5643 01:21:42.146449 == TX Byte 1 ==
5644 01:21:42.149787 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5645 01:21:42.153429 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5646 01:21:42.153539 ==
5647 01:21:42.156477 Dram Type= 6, Freq= 0, CH_1, rank 0
5648 01:21:42.163206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5649 01:21:42.163287 ==
5650 01:21:42.163351
5651 01:21:42.163409
5652 01:21:42.163466 TX Vref Scan disable
5653 01:21:42.167177 == TX Byte 0 ==
5654 01:21:42.170768 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5655 01:21:42.177344 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5656 01:21:42.177425 == TX Byte 1 ==
5657 01:21:42.181040 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5658 01:21:42.187715 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5659 01:21:42.187797
5660 01:21:42.187860 [DATLAT]
5661 01:21:42.187928 Freq=933, CH1 RK0
5662 01:21:42.187996
5663 01:21:42.190356 DATLAT Default: 0xd
5664 01:21:42.190436 0, 0xFFFF, sum = 0
5665 01:21:42.193821 1, 0xFFFF, sum = 0
5666 01:21:42.197000 2, 0xFFFF, sum = 0
5667 01:21:42.197081 3, 0xFFFF, sum = 0
5668 01:21:42.200238 4, 0xFFFF, sum = 0
5669 01:21:42.200320 5, 0xFFFF, sum = 0
5670 01:21:42.203690 6, 0xFFFF, sum = 0
5671 01:21:42.203772 7, 0xFFFF, sum = 0
5672 01:21:42.207014 8, 0xFFFF, sum = 0
5673 01:21:42.207096 9, 0xFFFF, sum = 0
5674 01:21:42.210624 10, 0x0, sum = 1
5675 01:21:42.210705 11, 0x0, sum = 2
5676 01:21:42.213625 12, 0x0, sum = 3
5677 01:21:42.213707 13, 0x0, sum = 4
5678 01:21:42.213771 best_step = 11
5679 01:21:42.216914
5680 01:21:42.216994 ==
5681 01:21:42.220406 Dram Type= 6, Freq= 0, CH_1, rank 0
5682 01:21:42.223848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5683 01:21:42.223977 ==
5684 01:21:42.224041 RX Vref Scan: 1
5685 01:21:42.224100
5686 01:21:42.227369 RX Vref 0 -> 0, step: 1
5687 01:21:42.227450
5688 01:21:42.230028 RX Delay -53 -> 252, step: 4
5689 01:21:42.230108
5690 01:21:42.233287 Set Vref, RX VrefLevel [Byte0]: 53
5691 01:21:42.236566 [Byte1]: 53
5692 01:21:42.239846
5693 01:21:42.239976 Final RX Vref Byte 0 = 53 to rank0
5694 01:21:42.243125 Final RX Vref Byte 1 = 53 to rank0
5695 01:21:42.246585 Final RX Vref Byte 0 = 53 to rank1
5696 01:21:42.249798 Final RX Vref Byte 1 = 53 to rank1==
5697 01:21:42.253001 Dram Type= 6, Freq= 0, CH_1, rank 0
5698 01:21:42.260133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5699 01:21:42.260214 ==
5700 01:21:42.260278 DQS Delay:
5701 01:21:42.263131 DQS0 = 0, DQS1 = 0
5702 01:21:42.263211 DQM Delay:
5703 01:21:42.263274 DQM0 = 98, DQM1 = 94
5704 01:21:42.266298 DQ Delay:
5705 01:21:42.269665 DQ0 =104, DQ1 =94, DQ2 =88, DQ3 =98
5706 01:21:42.272873 DQ4 =94, DQ5 =108, DQ6 =110, DQ7 =92
5707 01:21:42.276324 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5708 01:21:42.279660 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =104
5709 01:21:42.279766
5710 01:21:42.279856
5711 01:21:42.285873 [DQSOSCAuto] RK0, (LSB)MR18= 0x111, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 421 ps
5712 01:21:42.289300 CH1 RK0: MR19=505, MR18=111
5713 01:21:42.296263 CH1_RK0: MR19=0x505, MR18=0x111, DQSOSC=416, MR23=63, INC=62, DEC=41
5714 01:21:42.296346
5715 01:21:42.299785 ----->DramcWriteLeveling(PI) begin...
5716 01:21:42.299927 ==
5717 01:21:42.302466 Dram Type= 6, Freq= 0, CH_1, rank 1
5718 01:21:42.306086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5719 01:21:42.306167 ==
5720 01:21:42.309009 Write leveling (Byte 0): 27 => 27
5721 01:21:42.312667 Write leveling (Byte 1): 27 => 27
5722 01:21:42.315560 DramcWriteLeveling(PI) end<-----
5723 01:21:42.315640
5724 01:21:42.315704 ==
5725 01:21:42.318761 Dram Type= 6, Freq= 0, CH_1, rank 1
5726 01:21:42.325901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5727 01:21:42.325982 ==
5728 01:21:42.326046 [Gating] SW mode calibration
5729 01:21:42.335612 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5730 01:21:42.338474 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5731 01:21:42.345476 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5732 01:21:42.349290 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5733 01:21:42.351751 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5734 01:21:42.358472 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5735 01:21:42.361509 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5736 01:21:42.364670 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5737 01:21:42.371360 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
5738 01:21:42.375433 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5739 01:21:42.377977 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5740 01:21:42.384949 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5741 01:21:42.388001 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5742 01:21:42.391428 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5743 01:21:42.397682 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5744 01:21:42.401398 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5745 01:21:42.404076 0 15 24 | B1->B0 | 2424 3535 | 1 1 | (0 0) (0 0)
5746 01:21:42.411127 0 15 28 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
5747 01:21:42.414373 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5748 01:21:42.417567 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5749 01:21:42.424531 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5750 01:21:42.427146 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5751 01:21:42.430777 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5752 01:21:42.437463 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5753 01:21:42.440683 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5754 01:21:42.443641 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5755 01:21:42.450487 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5756 01:21:42.453792 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5757 01:21:42.456576 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5758 01:21:42.463387 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5759 01:21:42.466621 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5760 01:21:42.469744 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5761 01:21:42.476392 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 01:21:42.479617 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 01:21:42.483417 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 01:21:42.489637 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 01:21:42.492996 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 01:21:42.496535 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 01:21:42.503141 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 01:21:42.506409 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 01:21:42.509506 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5770 01:21:42.516486 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5771 01:21:42.516568 Total UI for P1: 0, mck2ui 16
5772 01:21:42.522887 best dqsien dly found for B0: ( 1, 2, 24)
5773 01:21:42.526488 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 01:21:42.529666 Total UI for P1: 0, mck2ui 16
5775 01:21:42.532849 best dqsien dly found for B1: ( 1, 2, 26)
5776 01:21:42.536146 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5777 01:21:42.539343 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5778 01:21:42.539424
5779 01:21:42.542420 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5780 01:21:42.546100 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5781 01:21:42.549036 [Gating] SW calibration Done
5782 01:21:42.549117 ==
5783 01:21:42.552398 Dram Type= 6, Freq= 0, CH_1, rank 1
5784 01:21:42.555865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5785 01:21:42.559156 ==
5786 01:21:42.559237 RX Vref Scan: 0
5787 01:21:42.559300
5788 01:21:42.562684 RX Vref 0 -> 0, step: 1
5789 01:21:42.562765
5790 01:21:42.565911 RX Delay -80 -> 252, step: 8
5791 01:21:42.568753 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5792 01:21:42.572150 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5793 01:21:42.575581 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5794 01:21:42.579135 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5795 01:21:42.585040 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5796 01:21:42.589139 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5797 01:21:42.591754 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5798 01:21:42.595847 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5799 01:21:42.598609 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5800 01:21:42.601772 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5801 01:21:42.608229 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5802 01:21:42.611705 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5803 01:21:42.614883 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5804 01:21:42.618390 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5805 01:21:42.621864 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5806 01:21:42.628249 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5807 01:21:42.628322 ==
5808 01:21:42.631630 Dram Type= 6, Freq= 0, CH_1, rank 1
5809 01:21:42.634454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5810 01:21:42.634549 ==
5811 01:21:42.634619 DQS Delay:
5812 01:21:42.637809 DQS0 = 0, DQS1 = 0
5813 01:21:42.637878 DQM Delay:
5814 01:21:42.641010 DQM0 = 97, DQM1 = 94
5815 01:21:42.641084 DQ Delay:
5816 01:21:42.644445 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5817 01:21:42.647629 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5818 01:21:42.651033 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5819 01:21:42.654279 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5820 01:21:42.654374
5821 01:21:42.654462
5822 01:21:42.654546 ==
5823 01:21:42.657633 Dram Type= 6, Freq= 0, CH_1, rank 1
5824 01:21:42.664214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5825 01:21:42.664286 ==
5826 01:21:42.664350
5827 01:21:42.664407
5828 01:21:42.664463 TX Vref Scan disable
5829 01:21:42.667507 == TX Byte 0 ==
5830 01:21:42.670874 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5831 01:21:42.677280 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5832 01:21:42.677356 == TX Byte 1 ==
5833 01:21:42.680742 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5834 01:21:42.687673 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5835 01:21:42.687757 ==
5836 01:21:42.690940 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 01:21:42.693686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 01:21:42.693778 ==
5839 01:21:42.693844
5840 01:21:42.693904
5841 01:21:42.696843 TX Vref Scan disable
5842 01:21:42.700368 == TX Byte 0 ==
5843 01:21:42.703587 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5844 01:21:42.706882 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5845 01:21:42.710327 == TX Byte 1 ==
5846 01:21:42.713579 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5847 01:21:42.717113 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5848 01:21:42.717195
5849 01:21:42.717258 [DATLAT]
5850 01:21:42.720045 Freq=933, CH1 RK1
5851 01:21:42.720126
5852 01:21:42.723245 DATLAT Default: 0xb
5853 01:21:42.723327 0, 0xFFFF, sum = 0
5854 01:21:42.727247 1, 0xFFFF, sum = 0
5855 01:21:42.727330 2, 0xFFFF, sum = 0
5856 01:21:42.730170 3, 0xFFFF, sum = 0
5857 01:21:42.730253 4, 0xFFFF, sum = 0
5858 01:21:42.733416 5, 0xFFFF, sum = 0
5859 01:21:42.733498 6, 0xFFFF, sum = 0
5860 01:21:42.736594 7, 0xFFFF, sum = 0
5861 01:21:42.736677 8, 0xFFFF, sum = 0
5862 01:21:42.739978 9, 0xFFFF, sum = 0
5863 01:21:42.740063 10, 0x0, sum = 1
5864 01:21:42.743228 11, 0x0, sum = 2
5865 01:21:42.743310 12, 0x0, sum = 3
5866 01:21:42.746804 13, 0x0, sum = 4
5867 01:21:42.746886 best_step = 11
5868 01:21:42.746950
5869 01:21:42.747009 ==
5870 01:21:42.750182 Dram Type= 6, Freq= 0, CH_1, rank 1
5871 01:21:42.756470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5872 01:21:42.756552 ==
5873 01:21:42.756616 RX Vref Scan: 0
5874 01:21:42.756676
5875 01:21:42.759399 RX Vref 0 -> 0, step: 1
5876 01:21:42.759479
5877 01:21:42.762846 RX Delay -53 -> 252, step: 4
5878 01:21:42.765909 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5879 01:21:42.769284 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5880 01:21:42.775798 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5881 01:21:42.779365 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5882 01:21:42.782866 iDelay=199, Bit 4, Center 98 (3 ~ 194) 192
5883 01:21:42.785803 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5884 01:21:42.789459 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5885 01:21:42.792775 iDelay=199, Bit 7, Center 96 (3 ~ 190) 188
5886 01:21:42.798857 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5887 01:21:42.802497 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5888 01:21:42.805393 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5889 01:21:42.808702 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5890 01:21:42.811852 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5891 01:21:42.818869 iDelay=199, Bit 13, Center 102 (11 ~ 194) 184
5892 01:21:42.822108 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5893 01:21:42.825196 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5894 01:21:42.825277 ==
5895 01:21:42.828486 Dram Type= 6, Freq= 0, CH_1, rank 1
5896 01:21:42.831788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5897 01:21:42.834943 ==
5898 01:21:42.835024 DQS Delay:
5899 01:21:42.835088 DQS0 = 0, DQS1 = 0
5900 01:21:42.838454 DQM Delay:
5901 01:21:42.838534 DQM0 = 98, DQM1 = 93
5902 01:21:42.842031 DQ Delay:
5903 01:21:42.845159 DQ0 =102, DQ1 =94, DQ2 =90, DQ3 =94
5904 01:21:42.847904 DQ4 =98, DQ5 =106, DQ6 =106, DQ7 =96
5905 01:21:42.851305 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =86
5906 01:21:42.854851 DQ12 =100, DQ13 =102, DQ14 =98, DQ15 =102
5907 01:21:42.854932
5908 01:21:42.854996
5909 01:21:42.861217 [DQSOSCAuto] RK1, (LSB)MR18= 0x71e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 419 ps
5910 01:21:42.864728 CH1 RK1: MR19=505, MR18=71E
5911 01:21:42.871312 CH1_RK1: MR19=0x505, MR18=0x71E, DQSOSC=412, MR23=63, INC=63, DEC=42
5912 01:21:42.874763 [RxdqsGatingPostProcess] freq 933
5913 01:21:42.877799 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5914 01:21:42.881141 best DQS0 dly(2T, 0.5T) = (0, 10)
5915 01:21:42.884613 best DQS1 dly(2T, 0.5T) = (0, 10)
5916 01:21:42.887510 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5917 01:21:42.891559 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5918 01:21:42.894460 best DQS0 dly(2T, 0.5T) = (0, 10)
5919 01:21:42.897280 best DQS1 dly(2T, 0.5T) = (0, 10)
5920 01:21:42.901276 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5921 01:21:42.904172 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5922 01:21:42.907587 Pre-setting of DQS Precalculation
5923 01:21:42.913866 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5924 01:21:42.920946 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5925 01:21:42.926943 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5926 01:21:42.927025
5927 01:21:42.927088
5928 01:21:42.930849 [Calibration Summary] 1866 Mbps
5929 01:21:42.930929 CH 0, Rank 0
5930 01:21:42.933943 SW Impedance : PASS
5931 01:21:42.936970 DUTY Scan : NO K
5932 01:21:42.937051 ZQ Calibration : PASS
5933 01:21:42.940282 Jitter Meter : NO K
5934 01:21:42.944018 CBT Training : PASS
5935 01:21:42.944099 Write leveling : PASS
5936 01:21:42.947080 RX DQS gating : PASS
5937 01:21:42.950183 RX DQ/DQS(RDDQC) : PASS
5938 01:21:42.950264 TX DQ/DQS : PASS
5939 01:21:42.953303 RX DATLAT : PASS
5940 01:21:42.953384 RX DQ/DQS(Engine): PASS
5941 01:21:42.956413 TX OE : NO K
5942 01:21:42.956494 All Pass.
5943 01:21:42.956558
5944 01:21:42.960004 CH 0, Rank 1
5945 01:21:42.960085 SW Impedance : PASS
5946 01:21:42.963603 DUTY Scan : NO K
5947 01:21:42.966552 ZQ Calibration : PASS
5948 01:21:42.966633 Jitter Meter : NO K
5949 01:21:42.969684 CBT Training : PASS
5950 01:21:42.973017 Write leveling : PASS
5951 01:21:42.973098 RX DQS gating : PASS
5952 01:21:42.976446 RX DQ/DQS(RDDQC) : PASS
5953 01:21:42.980157 TX DQ/DQS : PASS
5954 01:21:42.980238 RX DATLAT : PASS
5955 01:21:42.983132 RX DQ/DQS(Engine): PASS
5956 01:21:42.986053 TX OE : NO K
5957 01:21:42.986134 All Pass.
5958 01:21:42.986198
5959 01:21:42.986257 CH 1, Rank 0
5960 01:21:42.989436 SW Impedance : PASS
5961 01:21:42.992750 DUTY Scan : NO K
5962 01:21:42.992831 ZQ Calibration : PASS
5963 01:21:42.996286 Jitter Meter : NO K
5964 01:21:42.999420 CBT Training : PASS
5965 01:21:42.999500 Write leveling : PASS
5966 01:21:43.003560 RX DQS gating : PASS
5967 01:21:43.006063 RX DQ/DQS(RDDQC) : PASS
5968 01:21:43.006144 TX DQ/DQS : PASS
5969 01:21:43.009527 RX DATLAT : PASS
5970 01:21:43.012823 RX DQ/DQS(Engine): PASS
5971 01:21:43.012904 TX OE : NO K
5972 01:21:43.015782 All Pass.
5973 01:21:43.015863
5974 01:21:43.015962 CH 1, Rank 1
5975 01:21:43.019470 SW Impedance : PASS
5976 01:21:43.019551 DUTY Scan : NO K
5977 01:21:43.022739 ZQ Calibration : PASS
5978 01:21:43.025823 Jitter Meter : NO K
5979 01:21:43.025904 CBT Training : PASS
5980 01:21:43.029246 Write leveling : PASS
5981 01:21:43.032522 RX DQS gating : PASS
5982 01:21:43.032603 RX DQ/DQS(RDDQC) : PASS
5983 01:21:43.035572 TX DQ/DQS : PASS
5984 01:21:43.038680 RX DATLAT : PASS
5985 01:21:43.038761 RX DQ/DQS(Engine): PASS
5986 01:21:43.042032 TX OE : NO K
5987 01:21:43.042114 All Pass.
5988 01:21:43.042178
5989 01:21:43.045652 DramC Write-DBI off
5990 01:21:43.048950 PER_BANK_REFRESH: Hybrid Mode
5991 01:21:43.049031 TX_TRACKING: ON
5992 01:21:43.058465 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5993 01:21:43.062297 [FAST_K] Save calibration result to emmc
5994 01:21:43.065255 dramc_set_vcore_voltage set vcore to 650000
5995 01:21:43.068572 Read voltage for 400, 6
5996 01:21:43.068653 Vio18 = 0
5997 01:21:43.068717 Vcore = 650000
5998 01:21:43.071456 Vdram = 0
5999 01:21:43.071536 Vddq = 0
6000 01:21:43.071600 Vmddr = 0
6001 01:21:43.078066 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6002 01:21:43.081615 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6003 01:21:43.085138 MEM_TYPE=3, freq_sel=20
6004 01:21:43.087829 sv_algorithm_assistance_LP4_800
6005 01:21:43.091414 ============ PULL DRAM RESETB DOWN ============
6006 01:21:43.094736 ========== PULL DRAM RESETB DOWN end =========
6007 01:21:43.101450 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6008 01:21:43.104394 ===================================
6009 01:21:43.108047 LPDDR4 DRAM CONFIGURATION
6010 01:21:43.111238 ===================================
6011 01:21:43.111319 EX_ROW_EN[0] = 0x0
6012 01:21:43.114671 EX_ROW_EN[1] = 0x0
6013 01:21:43.114752 LP4Y_EN = 0x0
6014 01:21:43.117604 WORK_FSP = 0x0
6015 01:21:43.117685 WL = 0x2
6016 01:21:43.121301 RL = 0x2
6017 01:21:43.121381 BL = 0x2
6018 01:21:43.124298 RPST = 0x0
6019 01:21:43.124379 RD_PRE = 0x0
6020 01:21:43.127460 WR_PRE = 0x1
6021 01:21:43.127540 WR_PST = 0x0
6022 01:21:43.130844 DBI_WR = 0x0
6023 01:21:43.134183 DBI_RD = 0x0
6024 01:21:43.134273 OTF = 0x1
6025 01:21:43.137390 ===================================
6026 01:21:43.140945 ===================================
6027 01:21:43.141026 ANA top config
6028 01:21:43.144152 ===================================
6029 01:21:43.147182 DLL_ASYNC_EN = 0
6030 01:21:43.150947 ALL_SLAVE_EN = 1
6031 01:21:43.153947 NEW_RANK_MODE = 1
6032 01:21:43.157319 DLL_IDLE_MODE = 1
6033 01:21:43.157400 LP45_APHY_COMB_EN = 1
6034 01:21:43.160200 TX_ODT_DIS = 1
6035 01:21:43.163868 NEW_8X_MODE = 1
6036 01:21:43.167160 ===================================
6037 01:21:43.170390 ===================================
6038 01:21:43.173618 data_rate = 800
6039 01:21:43.176918 CKR = 1
6040 01:21:43.180616 DQ_P2S_RATIO = 4
6041 01:21:43.183416 ===================================
6042 01:21:43.183497 CA_P2S_RATIO = 4
6043 01:21:43.186776 DQ_CA_OPEN = 0
6044 01:21:43.190012 DQ_SEMI_OPEN = 1
6045 01:21:43.193801 CA_SEMI_OPEN = 1
6046 01:21:43.196944 CA_FULL_RATE = 0
6047 01:21:43.200062 DQ_CKDIV4_EN = 0
6048 01:21:43.200173 CA_CKDIV4_EN = 1
6049 01:21:43.203305 CA_PREDIV_EN = 0
6050 01:21:43.206470 PH8_DLY = 0
6051 01:21:43.210102 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6052 01:21:43.213404 DQ_AAMCK_DIV = 0
6053 01:21:43.216602 CA_AAMCK_DIV = 0
6054 01:21:43.216684 CA_ADMCK_DIV = 4
6055 01:21:43.219425 DQ_TRACK_CA_EN = 0
6056 01:21:43.223266 CA_PICK = 800
6057 01:21:43.226489 CA_MCKIO = 400
6058 01:21:43.229994 MCKIO_SEMI = 400
6059 01:21:43.233172 PLL_FREQ = 3016
6060 01:21:43.236668 DQ_UI_PI_RATIO = 32
6061 01:21:43.239264 CA_UI_PI_RATIO = 32
6062 01:21:43.242776 ===================================
6063 01:21:43.245939 ===================================
6064 01:21:43.246021 memory_type:LPDDR4
6065 01:21:43.249621 GP_NUM : 10
6066 01:21:43.252916 SRAM_EN : 1
6067 01:21:43.252997 MD32_EN : 0
6068 01:21:43.256043 ===================================
6069 01:21:43.259508 [ANA_INIT] >>>>>>>>>>>>>>
6070 01:21:43.262531 <<<<<< [CONFIGURE PHASE]: ANA_TX
6071 01:21:43.265711 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6072 01:21:43.269541 ===================================
6073 01:21:43.272408 data_rate = 800,PCW = 0X7400
6074 01:21:43.275470 ===================================
6075 01:21:43.278830 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6076 01:21:43.281927 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6077 01:21:43.295339 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6078 01:21:43.298769 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6079 01:21:43.301876 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6080 01:21:43.305130 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6081 01:21:43.308419 [ANA_INIT] flow start
6082 01:21:43.311806 [ANA_INIT] PLL >>>>>>>>
6083 01:21:43.311938 [ANA_INIT] PLL <<<<<<<<
6084 01:21:43.314848 [ANA_INIT] MIDPI >>>>>>>>
6085 01:21:43.318481 [ANA_INIT] MIDPI <<<<<<<<
6086 01:21:43.318576 [ANA_INIT] DLL >>>>>>>>
6087 01:21:43.322034 [ANA_INIT] flow end
6088 01:21:43.324706 ============ LP4 DIFF to SE enter ============
6089 01:21:43.331486 ============ LP4 DIFF to SE exit ============
6090 01:21:43.331568 [ANA_INIT] <<<<<<<<<<<<<
6091 01:21:43.334677 [Flow] Enable top DCM control >>>>>
6092 01:21:43.338143 [Flow] Enable top DCM control <<<<<
6093 01:21:43.341143 Enable DLL master slave shuffle
6094 01:21:43.348016 ==============================================================
6095 01:21:43.348095 Gating Mode config
6096 01:21:43.354886 ==============================================================
6097 01:21:43.357970 Config description:
6098 01:21:43.367612 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6099 01:21:43.374527 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6100 01:21:43.377898 SELPH_MODE 0: By rank 1: By Phase
6101 01:21:43.384217 ==============================================================
6102 01:21:43.387443 GAT_TRACK_EN = 0
6103 01:21:43.390667 RX_GATING_MODE = 2
6104 01:21:43.390774 RX_GATING_TRACK_MODE = 2
6105 01:21:43.393845 SELPH_MODE = 1
6106 01:21:43.397084 PICG_EARLY_EN = 1
6107 01:21:43.400557 VALID_LAT_VALUE = 1
6108 01:21:43.407030 ==============================================================
6109 01:21:43.410591 Enter into Gating configuration >>>>
6110 01:21:43.413880 Exit from Gating configuration <<<<
6111 01:21:43.416968 Enter into DVFS_PRE_config >>>>>
6112 01:21:43.427227 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6113 01:21:43.430226 Exit from DVFS_PRE_config <<<<<
6114 01:21:43.433423 Enter into PICG configuration >>>>
6115 01:21:43.436968 Exit from PICG configuration <<<<
6116 01:21:43.440713 [RX_INPUT] configuration >>>>>
6117 01:21:43.443683 [RX_INPUT] configuration <<<<<
6118 01:21:43.446552 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6119 01:21:43.453883 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6120 01:21:43.459803 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6121 01:21:43.466343 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6122 01:21:43.472922 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6123 01:21:43.479564 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6124 01:21:43.482913 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6125 01:21:43.485815 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6126 01:21:43.489549 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6127 01:21:43.496284 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6128 01:21:43.499332 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6129 01:21:43.502795 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6130 01:21:43.506355 ===================================
6131 01:21:43.508917 LPDDR4 DRAM CONFIGURATION
6132 01:21:43.512522 ===================================
6133 01:21:43.512603 EX_ROW_EN[0] = 0x0
6134 01:21:43.515697 EX_ROW_EN[1] = 0x0
6135 01:21:43.518905 LP4Y_EN = 0x0
6136 01:21:43.518986 WORK_FSP = 0x0
6137 01:21:43.522039 WL = 0x2
6138 01:21:43.522120 RL = 0x2
6139 01:21:43.525239 BL = 0x2
6140 01:21:43.525320 RPST = 0x0
6141 01:21:43.528515 RD_PRE = 0x0
6142 01:21:43.528596 WR_PRE = 0x1
6143 01:21:43.531843 WR_PST = 0x0
6144 01:21:43.531948 DBI_WR = 0x0
6145 01:21:43.535540 DBI_RD = 0x0
6146 01:21:43.535621 OTF = 0x1
6147 01:21:43.538490 ===================================
6148 01:21:43.542063 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6149 01:21:43.548739 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6150 01:21:43.551919 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6151 01:21:43.555223 ===================================
6152 01:21:43.558662 LPDDR4 DRAM CONFIGURATION
6153 01:21:43.561521 ===================================
6154 01:21:43.561602 EX_ROW_EN[0] = 0x10
6155 01:21:43.564702 EX_ROW_EN[1] = 0x0
6156 01:21:43.567863 LP4Y_EN = 0x0
6157 01:21:43.567979 WORK_FSP = 0x0
6158 01:21:43.571372 WL = 0x2
6159 01:21:43.571452 RL = 0x2
6160 01:21:43.574662 BL = 0x2
6161 01:21:43.574742 RPST = 0x0
6162 01:21:43.578103 RD_PRE = 0x0
6163 01:21:43.578184 WR_PRE = 0x1
6164 01:21:43.581244 WR_PST = 0x0
6165 01:21:43.581340 DBI_WR = 0x0
6166 01:21:43.584287 DBI_RD = 0x0
6167 01:21:43.584397 OTF = 0x1
6168 01:21:43.587606 ===================================
6169 01:21:43.594599 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6170 01:21:43.599097 nWR fixed to 30
6171 01:21:43.602687 [ModeRegInit_LP4] CH0 RK0
6172 01:21:43.602768 [ModeRegInit_LP4] CH0 RK1
6173 01:21:43.606197 [ModeRegInit_LP4] CH1 RK0
6174 01:21:43.609006 [ModeRegInit_LP4] CH1 RK1
6175 01:21:43.609086 match AC timing 19
6176 01:21:43.615649 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6177 01:21:43.618943 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6178 01:21:43.622366 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6179 01:21:43.628529 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6180 01:21:43.631831 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6181 01:21:43.631938 ==
6182 01:21:43.634901 Dram Type= 6, Freq= 0, CH_0, rank 0
6183 01:21:43.638367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6184 01:21:43.641938 ==
6185 01:21:43.645041 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6186 01:21:43.651372 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6187 01:21:43.654991 [CA 0] Center 36 (8~64) winsize 57
6188 01:21:43.658270 [CA 1] Center 36 (8~64) winsize 57
6189 01:21:43.661853 [CA 2] Center 36 (8~64) winsize 57
6190 01:21:43.664719 [CA 3] Center 36 (8~64) winsize 57
6191 01:21:43.667974 [CA 4] Center 36 (8~64) winsize 57
6192 01:21:43.671185 [CA 5] Center 36 (8~64) winsize 57
6193 01:21:43.671282
6194 01:21:43.674506 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6195 01:21:43.674604
6196 01:21:43.677808 [CATrainingPosCal] consider 1 rank data
6197 01:21:43.681558 u2DelayCellTimex100 = 270/100 ps
6198 01:21:43.684386 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6199 01:21:43.687913 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6200 01:21:43.691034 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6201 01:21:43.694338 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6202 01:21:43.697823 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6203 01:21:43.701099 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6204 01:21:43.701182
6205 01:21:43.707842 CA PerBit enable=1, Macro0, CA PI delay=36
6206 01:21:43.707947
6207 01:21:43.710656 [CBTSetCACLKResult] CA Dly = 36
6208 01:21:43.710737 CS Dly: 1 (0~32)
6209 01:21:43.710801 ==
6210 01:21:43.714168 Dram Type= 6, Freq= 0, CH_0, rank 1
6211 01:21:43.717624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6212 01:21:43.717706 ==
6213 01:21:43.724095 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6214 01:21:43.730804 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6215 01:21:43.733964 [CA 0] Center 36 (8~64) winsize 57
6216 01:21:43.737013 [CA 1] Center 36 (8~64) winsize 57
6217 01:21:43.740552 [CA 2] Center 36 (8~64) winsize 57
6218 01:21:43.743854 [CA 3] Center 36 (8~64) winsize 57
6219 01:21:43.747187 [CA 4] Center 36 (8~64) winsize 57
6220 01:21:43.750415 [CA 5] Center 36 (8~64) winsize 57
6221 01:21:43.750495
6222 01:21:43.753596 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6223 01:21:43.753677
6224 01:21:43.757028 [CATrainingPosCal] consider 2 rank data
6225 01:21:43.760277 u2DelayCellTimex100 = 270/100 ps
6226 01:21:43.763563 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 01:21:43.766725 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 01:21:43.769926 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 01:21:43.773522 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 01:21:43.776842 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 01:21:43.779896 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 01:21:43.779991
6233 01:21:43.786571 CA PerBit enable=1, Macro0, CA PI delay=36
6234 01:21:43.786652
6235 01:21:43.786727 [CBTSetCACLKResult] CA Dly = 36
6236 01:21:43.789959 CS Dly: 1 (0~32)
6237 01:21:43.790039
6238 01:21:43.792760 ----->DramcWriteLeveling(PI) begin...
6239 01:21:43.792842 ==
6240 01:21:43.796595 Dram Type= 6, Freq= 0, CH_0, rank 0
6241 01:21:43.800257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6242 01:21:43.800337 ==
6243 01:21:43.802957 Write leveling (Byte 0): 40 => 8
6244 01:21:43.806547 Write leveling (Byte 1): 40 => 8
6245 01:21:43.809288 DramcWriteLeveling(PI) end<-----
6246 01:21:43.809373
6247 01:21:43.809437 ==
6248 01:21:43.813014 Dram Type= 6, Freq= 0, CH_0, rank 0
6249 01:21:43.819381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6250 01:21:43.819463 ==
6251 01:21:43.819527 [Gating] SW mode calibration
6252 01:21:43.829402 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6253 01:21:43.832164 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6254 01:21:43.839241 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6255 01:21:43.842416 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6256 01:21:43.845501 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6257 01:21:43.852115 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6258 01:21:43.855589 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6259 01:21:43.859247 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6260 01:21:43.865072 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6261 01:21:43.868711 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6262 01:21:43.871672 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6263 01:21:43.875206 Total UI for P1: 0, mck2ui 16
6264 01:21:43.878550 best dqsien dly found for B0: ( 0, 14, 24)
6265 01:21:43.881872 Total UI for P1: 0, mck2ui 16
6266 01:21:43.884915 best dqsien dly found for B1: ( 0, 14, 24)
6267 01:21:43.888010 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6268 01:21:43.891384 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6269 01:21:43.891466
6270 01:21:43.897783 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6271 01:21:43.901080 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6272 01:21:43.904749 [Gating] SW calibration Done
6273 01:21:43.904830 ==
6274 01:21:43.907801 Dram Type= 6, Freq= 0, CH_0, rank 0
6275 01:21:43.911399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6276 01:21:43.911481 ==
6277 01:21:43.911545 RX Vref Scan: 0
6278 01:21:43.911604
6279 01:21:43.914463 RX Vref 0 -> 0, step: 1
6280 01:21:43.914543
6281 01:21:43.917421 RX Delay -410 -> 252, step: 16
6282 01:21:43.921263 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6283 01:21:43.928096 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6284 01:21:43.931183 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6285 01:21:43.934173 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6286 01:21:43.937276 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6287 01:21:43.944030 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6288 01:21:43.947649 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6289 01:21:43.950716 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6290 01:21:43.953825 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6291 01:21:43.960669 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6292 01:21:43.964162 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6293 01:21:43.966874 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6294 01:21:43.974189 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6295 01:21:43.977136 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6296 01:21:43.980591 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6297 01:21:43.983364 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6298 01:21:43.986745 ==
6299 01:21:43.986825 Dram Type= 6, Freq= 0, CH_0, rank 0
6300 01:21:43.993005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6301 01:21:43.993089 ==
6302 01:21:43.993153 DQS Delay:
6303 01:21:43.996748 DQS0 = 35, DQS1 = 59
6304 01:21:43.996829 DQM Delay:
6305 01:21:43.999528 DQM0 = 4, DQM1 = 18
6306 01:21:43.999609 DQ Delay:
6307 01:21:44.002955 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6308 01:21:44.006198 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6309 01:21:44.009748 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =16
6310 01:21:44.012911 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6311 01:21:44.012991
6312 01:21:44.013055
6313 01:21:44.013113 ==
6314 01:21:44.016098 Dram Type= 6, Freq= 0, CH_0, rank 0
6315 01:21:44.019763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 01:21:44.019844 ==
6317 01:21:44.019949
6318 01:21:44.020009
6319 01:21:44.022753 TX Vref Scan disable
6320 01:21:44.022833 == TX Byte 0 ==
6321 01:21:44.029723 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6322 01:21:44.032539 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6323 01:21:44.032620 == TX Byte 1 ==
6324 01:21:44.039319 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6325 01:21:44.042945 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6326 01:21:44.043026 ==
6327 01:21:44.046063 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 01:21:44.049416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 01:21:44.049498 ==
6330 01:21:44.049562
6331 01:21:44.049621
6332 01:21:44.052240 TX Vref Scan disable
6333 01:21:44.055477 == TX Byte 0 ==
6334 01:21:44.058994 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6335 01:21:44.062464 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6336 01:21:44.062545 == TX Byte 1 ==
6337 01:21:44.069324 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6338 01:21:44.072341 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6339 01:21:44.072422
6340 01:21:44.072486 [DATLAT]
6341 01:21:44.075774 Freq=400, CH0 RK0
6342 01:21:44.075855
6343 01:21:44.075925 DATLAT Default: 0xf
6344 01:21:44.078572 0, 0xFFFF, sum = 0
6345 01:21:44.078654 1, 0xFFFF, sum = 0
6346 01:21:44.082424 2, 0xFFFF, sum = 0
6347 01:21:44.082583 3, 0xFFFF, sum = 0
6348 01:21:44.085670 4, 0xFFFF, sum = 0
6349 01:21:44.088767 5, 0xFFFF, sum = 0
6350 01:21:44.088849 6, 0xFFFF, sum = 0
6351 01:21:44.092443 7, 0xFFFF, sum = 0
6352 01:21:44.092526 8, 0xFFFF, sum = 0
6353 01:21:44.095180 9, 0xFFFF, sum = 0
6354 01:21:44.095262 10, 0xFFFF, sum = 0
6355 01:21:44.098718 11, 0xFFFF, sum = 0
6356 01:21:44.098800 12, 0xFFFF, sum = 0
6357 01:21:44.102075 13, 0x0, sum = 1
6358 01:21:44.102158 14, 0x0, sum = 2
6359 01:21:44.105272 15, 0x0, sum = 3
6360 01:21:44.105355 16, 0x0, sum = 4
6361 01:21:44.108686 best_step = 14
6362 01:21:44.108767
6363 01:21:44.108831 ==
6364 01:21:44.111793 Dram Type= 6, Freq= 0, CH_0, rank 0
6365 01:21:44.115478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6366 01:21:44.115560 ==
6367 01:21:44.118054 RX Vref Scan: 1
6368 01:21:44.118134
6369 01:21:44.118198 RX Vref 0 -> 0, step: 1
6370 01:21:44.118258
6371 01:21:44.121359 RX Delay -359 -> 252, step: 8
6372 01:21:44.121440
6373 01:21:44.124804 Set Vref, RX VrefLevel [Byte0]: 53
6374 01:21:44.127956 [Byte1]: 45
6375 01:21:44.133032
6376 01:21:44.133113 Final RX Vref Byte 0 = 53 to rank0
6377 01:21:44.135708 Final RX Vref Byte 1 = 45 to rank0
6378 01:21:44.139140 Final RX Vref Byte 0 = 53 to rank1
6379 01:21:44.142528 Final RX Vref Byte 1 = 45 to rank1==
6380 01:21:44.145694 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 01:21:44.153035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 01:21:44.153117 ==
6383 01:21:44.153182 DQS Delay:
6384 01:21:44.155413 DQS0 = 44, DQS1 = 56
6385 01:21:44.155494 DQM Delay:
6386 01:21:44.155559 DQM0 = 10, DQM1 = 13
6387 01:21:44.158770 DQ Delay:
6388 01:21:44.162145 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6389 01:21:44.165395 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6390 01:21:44.168578 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6391 01:21:44.172046 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6392 01:21:44.172127
6393 01:21:44.172192
6394 01:21:44.178725 [DQSOSCAuto] RK0, (LSB)MR18= 0x9185, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
6395 01:21:44.181833 CH0 RK0: MR19=C0C, MR18=9185
6396 01:21:44.188589 CH0_RK0: MR19=0xC0C, MR18=0x9185, DQSOSC=391, MR23=63, INC=386, DEC=257
6397 01:21:44.188671 ==
6398 01:21:44.191651 Dram Type= 6, Freq= 0, CH_0, rank 1
6399 01:21:44.194864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 01:21:44.194946 ==
6401 01:21:44.198333 [Gating] SW mode calibration
6402 01:21:44.204946 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6403 01:21:44.211208 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6404 01:21:44.214610 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6405 01:21:44.221453 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6406 01:21:44.224705 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6407 01:21:44.227761 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6408 01:21:44.230918 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6409 01:21:44.238040 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6410 01:21:44.240842 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6411 01:21:44.244106 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6412 01:21:44.250918 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6413 01:21:44.254459 Total UI for P1: 0, mck2ui 16
6414 01:21:44.257396 best dqsien dly found for B0: ( 0, 14, 24)
6415 01:21:44.260540 Total UI for P1: 0, mck2ui 16
6416 01:21:44.264300 best dqsien dly found for B1: ( 0, 14, 24)
6417 01:21:44.267454 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6418 01:21:44.270777 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6419 01:21:44.270858
6420 01:21:44.273795 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6421 01:21:44.276971 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6422 01:21:44.280747 [Gating] SW calibration Done
6423 01:21:44.280828 ==
6424 01:21:44.283700 Dram Type= 6, Freq= 0, CH_0, rank 1
6425 01:21:44.287280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6426 01:21:44.290492 ==
6427 01:21:44.290573 RX Vref Scan: 0
6428 01:21:44.290637
6429 01:21:44.293615 RX Vref 0 -> 0, step: 1
6430 01:21:44.293696
6431 01:21:44.297078 RX Delay -410 -> 252, step: 16
6432 01:21:44.300365 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6433 01:21:44.303984 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6434 01:21:44.306939 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6435 01:21:44.313333 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6436 01:21:44.316780 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6437 01:21:44.319687 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6438 01:21:44.323590 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6439 01:21:44.329672 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6440 01:21:44.332917 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6441 01:21:44.336891 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6442 01:21:44.343192 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6443 01:21:44.346107 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6444 01:21:44.349359 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6445 01:21:44.352715 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6446 01:21:44.359528 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6447 01:21:44.362699 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6448 01:21:44.362780 ==
6449 01:21:44.365784 Dram Type= 6, Freq= 0, CH_0, rank 1
6450 01:21:44.369561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6451 01:21:44.369642 ==
6452 01:21:44.372798 DQS Delay:
6453 01:21:44.372880 DQS0 = 35, DQS1 = 51
6454 01:21:44.376113 DQM Delay:
6455 01:21:44.376194 DQM0 = 6, DQM1 = 10
6456 01:21:44.376259 DQ Delay:
6457 01:21:44.379083 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6458 01:21:44.382456 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6459 01:21:44.385559 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6460 01:21:44.389148 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6461 01:21:44.389229
6462 01:21:44.389292
6463 01:21:44.389351 ==
6464 01:21:44.392064 Dram Type= 6, Freq= 0, CH_0, rank 1
6465 01:21:44.399033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 01:21:44.399116 ==
6467 01:21:44.399180
6468 01:21:44.399239
6469 01:21:44.399296 TX Vref Scan disable
6470 01:21:44.402084 == TX Byte 0 ==
6471 01:21:44.405314 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6472 01:21:44.408944 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6473 01:21:44.411874 == TX Byte 1 ==
6474 01:21:44.415562 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6475 01:21:44.418958 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6476 01:21:44.419040 ==
6477 01:21:44.421690 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 01:21:44.428688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 01:21:44.428769 ==
6480 01:21:44.428834
6481 01:21:44.428893
6482 01:21:44.431712 TX Vref Scan disable
6483 01:21:44.431793 == TX Byte 0 ==
6484 01:21:44.435040 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6485 01:21:44.441377 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6486 01:21:44.441458 == TX Byte 1 ==
6487 01:21:44.444877 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6488 01:21:44.451183 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6489 01:21:44.451265
6490 01:21:44.451328 [DATLAT]
6491 01:21:44.451388 Freq=400, CH0 RK1
6492 01:21:44.451445
6493 01:21:44.454653 DATLAT Default: 0xe
6494 01:21:44.454734 0, 0xFFFF, sum = 0
6495 01:21:44.457837 1, 0xFFFF, sum = 0
6496 01:21:44.457920 2, 0xFFFF, sum = 0
6497 01:21:44.461178 3, 0xFFFF, sum = 0
6498 01:21:44.464614 4, 0xFFFF, sum = 0
6499 01:21:44.464697 5, 0xFFFF, sum = 0
6500 01:21:44.468035 6, 0xFFFF, sum = 0
6501 01:21:44.468117 7, 0xFFFF, sum = 0
6502 01:21:44.470919 8, 0xFFFF, sum = 0
6503 01:21:44.471001 9, 0xFFFF, sum = 0
6504 01:21:44.474615 10, 0xFFFF, sum = 0
6505 01:21:44.474698 11, 0xFFFF, sum = 0
6506 01:21:44.477496 12, 0xFFFF, sum = 0
6507 01:21:44.477578 13, 0x0, sum = 1
6508 01:21:44.481007 14, 0x0, sum = 2
6509 01:21:44.481089 15, 0x0, sum = 3
6510 01:21:44.484181 16, 0x0, sum = 4
6511 01:21:44.484264 best_step = 14
6512 01:21:44.484342
6513 01:21:44.484405 ==
6514 01:21:44.487657 Dram Type= 6, Freq= 0, CH_0, rank 1
6515 01:21:44.494165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6516 01:21:44.494248 ==
6517 01:21:44.494312 RX Vref Scan: 0
6518 01:21:44.494372
6519 01:21:44.497602 RX Vref 0 -> 0, step: 1
6520 01:21:44.497684
6521 01:21:44.501255 RX Delay -343 -> 252, step: 8
6522 01:21:44.507707 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6523 01:21:44.511023 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6524 01:21:44.514089 iDelay=209, Bit 2, Center -36 (-271 ~ 200) 472
6525 01:21:44.516992 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6526 01:21:44.524118 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6527 01:21:44.527245 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6528 01:21:44.530639 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6529 01:21:44.533605 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6530 01:21:44.540561 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6531 01:21:44.544003 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6532 01:21:44.546980 iDelay=209, Bit 10, Center -40 (-279 ~ 200) 480
6533 01:21:44.550264 iDelay=209, Bit 11, Center -52 (-287 ~ 184) 472
6534 01:21:44.556856 iDelay=209, Bit 12, Center -44 (-287 ~ 200) 488
6535 01:21:44.560058 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6536 01:21:44.563749 iDelay=209, Bit 14, Center -32 (-271 ~ 208) 480
6537 01:21:44.570174 iDelay=209, Bit 15, Center -40 (-279 ~ 200) 480
6538 01:21:44.570280 ==
6539 01:21:44.573172 Dram Type= 6, Freq= 0, CH_0, rank 1
6540 01:21:44.576435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6541 01:21:44.576510 ==
6542 01:21:44.576574 DQS Delay:
6543 01:21:44.579861 DQS0 = 44, DQS1 = 60
6544 01:21:44.579996 DQM Delay:
6545 01:21:44.583562 DQM0 = 10, DQM1 = 15
6546 01:21:44.583695 DQ Delay:
6547 01:21:44.586600 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6548 01:21:44.590169 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6549 01:21:44.593309 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6550 01:21:44.596481 DQ12 =16, DQ13 =20, DQ14 =28, DQ15 =20
6551 01:21:44.596563
6552 01:21:44.596626
6553 01:21:44.603388 [DQSOSCAuto] RK1, (LSB)MR18= 0x857e, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6554 01:21:44.606406 CH0 RK1: MR19=C0C, MR18=857E
6555 01:21:44.612957 CH0_RK1: MR19=0xC0C, MR18=0x857E, DQSOSC=393, MR23=63, INC=382, DEC=254
6556 01:21:44.616159 [RxdqsGatingPostProcess] freq 400
6557 01:21:44.622801 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6558 01:21:44.625899 best DQS0 dly(2T, 0.5T) = (0, 10)
6559 01:21:44.625980 best DQS1 dly(2T, 0.5T) = (0, 10)
6560 01:21:44.629076 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6561 01:21:44.632777 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6562 01:21:44.636033 best DQS0 dly(2T, 0.5T) = (0, 10)
6563 01:21:44.639432 best DQS1 dly(2T, 0.5T) = (0, 10)
6564 01:21:44.642739 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6565 01:21:44.645780 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6566 01:21:44.649354 Pre-setting of DQS Precalculation
6567 01:21:44.655338 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6568 01:21:44.655420 ==
6569 01:21:44.659026 Dram Type= 6, Freq= 0, CH_1, rank 0
6570 01:21:44.662201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6571 01:21:44.662282 ==
6572 01:21:44.668973 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6573 01:21:44.675603 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6574 01:21:44.678653 [CA 0] Center 36 (8~64) winsize 57
6575 01:21:44.678735 [CA 1] Center 36 (8~64) winsize 57
6576 01:21:44.682091 [CA 2] Center 36 (8~64) winsize 57
6577 01:21:44.685079 [CA 3] Center 36 (8~64) winsize 57
6578 01:21:44.688267 [CA 4] Center 36 (8~64) winsize 57
6579 01:21:44.692003 [CA 5] Center 36 (8~64) winsize 57
6580 01:21:44.692085
6581 01:21:44.695113 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6582 01:21:44.695195
6583 01:21:44.701890 [CATrainingPosCal] consider 1 rank data
6584 01:21:44.701972 u2DelayCellTimex100 = 270/100 ps
6585 01:21:44.708272 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6586 01:21:44.711356 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6587 01:21:44.715099 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6588 01:21:44.718319 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6589 01:21:44.721225 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6590 01:21:44.724502 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6591 01:21:44.724583
6592 01:21:44.727965 CA PerBit enable=1, Macro0, CA PI delay=36
6593 01:21:44.728047
6594 01:21:44.731231 [CBTSetCACLKResult] CA Dly = 36
6595 01:21:44.734253 CS Dly: 1 (0~32)
6596 01:21:44.734333 ==
6597 01:21:44.738380 Dram Type= 6, Freq= 0, CH_1, rank 1
6598 01:21:44.740863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6599 01:21:44.740945 ==
6600 01:21:44.747794 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6601 01:21:44.754506 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6602 01:21:44.754587 [CA 0] Center 36 (8~64) winsize 57
6603 01:21:44.758097 [CA 1] Center 36 (8~64) winsize 57
6604 01:21:44.761393 [CA 2] Center 36 (8~64) winsize 57
6605 01:21:44.764019 [CA 3] Center 36 (8~64) winsize 57
6606 01:21:44.767486 [CA 4] Center 36 (8~64) winsize 57
6607 01:21:44.771087 [CA 5] Center 36 (8~64) winsize 57
6608 01:21:44.771168
6609 01:21:44.773691 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6610 01:21:44.773801
6611 01:21:44.780708 [CATrainingPosCal] consider 2 rank data
6612 01:21:44.780789 u2DelayCellTimex100 = 270/100 ps
6613 01:21:44.786739 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 01:21:44.790791 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 01:21:44.794040 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 01:21:44.796789 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 01:21:44.800152 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 01:21:44.803512 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 01:21:44.803593
6620 01:21:44.806831 CA PerBit enable=1, Macro0, CA PI delay=36
6621 01:21:44.806912
6622 01:21:44.809695 [CBTSetCACLKResult] CA Dly = 36
6623 01:21:44.813215 CS Dly: 1 (0~32)
6624 01:21:44.813298
6625 01:21:44.816847 ----->DramcWriteLeveling(PI) begin...
6626 01:21:44.816930 ==
6627 01:21:44.820318 Dram Type= 6, Freq= 0, CH_1, rank 0
6628 01:21:44.823253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6629 01:21:44.823335 ==
6630 01:21:44.826266 Write leveling (Byte 0): 40 => 8
6631 01:21:44.829715 Write leveling (Byte 1): 40 => 8
6632 01:21:44.833457 DramcWriteLeveling(PI) end<-----
6633 01:21:44.833539
6634 01:21:44.833602 ==
6635 01:21:44.836343 Dram Type= 6, Freq= 0, CH_1, rank 0
6636 01:21:44.840079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 01:21:44.840161 ==
6638 01:21:44.842589 [Gating] SW mode calibration
6639 01:21:44.849365 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6640 01:21:44.856554 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6641 01:21:44.859389 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6642 01:21:44.865809 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6643 01:21:44.868989 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6644 01:21:44.872418 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6645 01:21:44.878909 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6646 01:21:44.882444 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6647 01:21:44.885370 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6648 01:21:44.892375 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6649 01:21:44.895265 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6650 01:21:44.898653 Total UI for P1: 0, mck2ui 16
6651 01:21:44.902017 best dqsien dly found for B0: ( 0, 14, 24)
6652 01:21:44.905103 Total UI for P1: 0, mck2ui 16
6653 01:21:44.908449 best dqsien dly found for B1: ( 0, 14, 24)
6654 01:21:44.911859 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6655 01:21:44.915038 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6656 01:21:44.915119
6657 01:21:44.918126 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6658 01:21:44.922236 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6659 01:21:44.924800 [Gating] SW calibration Done
6660 01:21:44.924881 ==
6661 01:21:44.928140 Dram Type= 6, Freq= 0, CH_1, rank 0
6662 01:21:44.931669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6663 01:21:44.935129 ==
6664 01:21:44.935210 RX Vref Scan: 0
6665 01:21:44.935305
6666 01:21:44.938177 RX Vref 0 -> 0, step: 1
6667 01:21:44.938259
6668 01:21:44.941682 RX Delay -410 -> 252, step: 16
6669 01:21:44.944782 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6670 01:21:44.948108 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6671 01:21:44.951607 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6672 01:21:44.957745 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6673 01:21:44.961021 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6674 01:21:44.964849 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6675 01:21:44.967679 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6676 01:21:44.974587 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6677 01:21:44.977952 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6678 01:21:44.981220 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6679 01:21:44.987572 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6680 01:21:44.991186 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6681 01:21:44.994129 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6682 01:21:44.997703 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6683 01:21:45.004202 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6684 01:21:45.007377 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6685 01:21:45.007457 ==
6686 01:21:45.010858 Dram Type= 6, Freq= 0, CH_1, rank 0
6687 01:21:45.014129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6688 01:21:45.014212 ==
6689 01:21:45.017280 DQS Delay:
6690 01:21:45.017361 DQS0 = 35, DQS1 = 51
6691 01:21:45.020470 DQM Delay:
6692 01:21:45.020551 DQM0 = 6, DQM1 = 13
6693 01:21:45.020615 DQ Delay:
6694 01:21:45.024159 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6695 01:21:45.027575 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6696 01:21:45.030171 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6697 01:21:45.033769 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6698 01:21:45.033851
6699 01:21:45.033914
6700 01:21:45.033973 ==
6701 01:21:45.037280 Dram Type= 6, Freq= 0, CH_1, rank 0
6702 01:21:45.043476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 01:21:45.043558 ==
6704 01:21:45.043641
6705 01:21:45.043745
6706 01:21:45.043833 TX Vref Scan disable
6707 01:21:45.046751 == TX Byte 0 ==
6708 01:21:45.050139 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6709 01:21:45.053347 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6710 01:21:45.056333 == TX Byte 1 ==
6711 01:21:45.059597 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6712 01:21:45.063150 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6713 01:21:45.066153 ==
6714 01:21:45.069565 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 01:21:45.072882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 01:21:45.072964 ==
6717 01:21:45.073028
6718 01:21:45.073086
6719 01:21:45.075788 TX Vref Scan disable
6720 01:21:45.075918 == TX Byte 0 ==
6721 01:21:45.079237 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6722 01:21:45.086046 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6723 01:21:45.086142 == TX Byte 1 ==
6724 01:21:45.089403 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6725 01:21:45.096294 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6726 01:21:45.096376
6727 01:21:45.096440 [DATLAT]
6728 01:21:45.096500 Freq=400, CH1 RK0
6729 01:21:45.096558
6730 01:21:45.099387 DATLAT Default: 0xf
6731 01:21:45.102689 0, 0xFFFF, sum = 0
6732 01:21:45.102772 1, 0xFFFF, sum = 0
6733 01:21:45.105549 2, 0xFFFF, sum = 0
6734 01:21:45.105632 3, 0xFFFF, sum = 0
6735 01:21:45.109228 4, 0xFFFF, sum = 0
6736 01:21:45.109311 5, 0xFFFF, sum = 0
6737 01:21:45.112399 6, 0xFFFF, sum = 0
6738 01:21:45.112481 7, 0xFFFF, sum = 0
6739 01:21:45.115759 8, 0xFFFF, sum = 0
6740 01:21:45.115842 9, 0xFFFF, sum = 0
6741 01:21:45.118935 10, 0xFFFF, sum = 0
6742 01:21:45.119018 11, 0xFFFF, sum = 0
6743 01:21:45.122054 12, 0xFFFF, sum = 0
6744 01:21:45.122136 13, 0x0, sum = 1
6745 01:21:45.125324 14, 0x0, sum = 2
6746 01:21:45.125407 15, 0x0, sum = 3
6747 01:21:45.129534 16, 0x0, sum = 4
6748 01:21:45.129616 best_step = 14
6749 01:21:45.129679
6750 01:21:45.129738 ==
6751 01:21:45.132037 Dram Type= 6, Freq= 0, CH_1, rank 0
6752 01:21:45.139099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6753 01:21:45.139181 ==
6754 01:21:45.139245 RX Vref Scan: 1
6755 01:21:45.139304
6756 01:21:45.142440 RX Vref 0 -> 0, step: 1
6757 01:21:45.142521
6758 01:21:45.145099 RX Delay -343 -> 252, step: 8
6759 01:21:45.145181
6760 01:21:45.148569 Set Vref, RX VrefLevel [Byte0]: 53
6761 01:21:45.151790 [Byte1]: 53
6762 01:21:45.151871
6763 01:21:45.155808 Final RX Vref Byte 0 = 53 to rank0
6764 01:21:45.158286 Final RX Vref Byte 1 = 53 to rank0
6765 01:21:45.161678 Final RX Vref Byte 0 = 53 to rank1
6766 01:21:45.165138 Final RX Vref Byte 1 = 53 to rank1==
6767 01:21:45.168442 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 01:21:45.175095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 01:21:45.175176 ==
6770 01:21:45.175241 DQS Delay:
6771 01:21:45.178085 DQS0 = 44, DQS1 = 52
6772 01:21:45.178167 DQM Delay:
6773 01:21:45.178231 DQM0 = 11, DQM1 = 11
6774 01:21:45.181332 DQ Delay:
6775 01:21:45.184759 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6776 01:21:45.184841 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6777 01:21:45.187841 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6778 01:21:45.191868 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6779 01:21:45.191985
6780 01:21:45.194875
6781 01:21:45.201514 [DQSOSCAuto] RK0, (LSB)MR18= 0x668d, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 396 ps
6782 01:21:45.204879 CH1 RK0: MR19=C0C, MR18=668D
6783 01:21:45.210998 CH1_RK0: MR19=0xC0C, MR18=0x668D, DQSOSC=392, MR23=63, INC=384, DEC=256
6784 01:21:45.211080 ==
6785 01:21:45.214363 Dram Type= 6, Freq= 0, CH_1, rank 1
6786 01:21:45.217793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 01:21:45.217875 ==
6788 01:21:45.221257 [Gating] SW mode calibration
6789 01:21:45.227493 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6790 01:21:45.234334 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6791 01:21:45.237444 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6792 01:21:45.240540 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6793 01:21:45.247758 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6794 01:21:45.250744 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6795 01:21:45.253829 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6796 01:21:45.260172 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6797 01:21:45.263494 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6798 01:21:45.267113 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6799 01:21:45.273612 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6800 01:21:45.276634 Total UI for P1: 0, mck2ui 16
6801 01:21:45.280546 best dqsien dly found for B0: ( 0, 14, 24)
6802 01:21:45.283157 Total UI for P1: 0, mck2ui 16
6803 01:21:45.286480 best dqsien dly found for B1: ( 0, 14, 24)
6804 01:21:45.290244 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6805 01:21:45.293526 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6806 01:21:45.293607
6807 01:21:45.296844 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6808 01:21:45.299776 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6809 01:21:45.303016 [Gating] SW calibration Done
6810 01:21:45.303097 ==
6811 01:21:45.306412 Dram Type= 6, Freq= 0, CH_1, rank 1
6812 01:21:45.310126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6813 01:21:45.310207 ==
6814 01:21:45.313098 RX Vref Scan: 0
6815 01:21:45.313179
6816 01:21:45.316092 RX Vref 0 -> 0, step: 1
6817 01:21:45.316173
6818 01:21:45.316237 RX Delay -410 -> 252, step: 16
6819 01:21:45.323288 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6820 01:21:45.326396 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6821 01:21:45.329496 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6822 01:21:45.336074 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6823 01:21:45.339640 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6824 01:21:45.342556 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6825 01:21:45.346274 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6826 01:21:45.352936 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6827 01:21:45.356162 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6828 01:21:45.359542 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6829 01:21:45.362452 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6830 01:21:45.369409 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6831 01:21:45.372504 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6832 01:21:45.375668 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6833 01:21:45.382419 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6834 01:21:45.385664 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6835 01:21:45.385761 ==
6836 01:21:45.388593 Dram Type= 6, Freq= 0, CH_1, rank 1
6837 01:21:45.392033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6838 01:21:45.392116 ==
6839 01:21:45.395226 DQS Delay:
6840 01:21:45.395306 DQS0 = 43, DQS1 = 51
6841 01:21:45.395370 DQM Delay:
6842 01:21:45.398627 DQM0 = 10, DQM1 = 13
6843 01:21:45.398708 DQ Delay:
6844 01:21:45.401764 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6845 01:21:45.404979 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6846 01:21:45.408256 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6847 01:21:45.411821 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6848 01:21:45.411925
6849 01:21:45.411990
6850 01:21:45.412050 ==
6851 01:21:45.415608 Dram Type= 6, Freq= 0, CH_1, rank 1
6852 01:21:45.418166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 01:21:45.421948 ==
6854 01:21:45.422029
6855 01:21:45.422093
6856 01:21:45.422152 TX Vref Scan disable
6857 01:21:45.425316 == TX Byte 0 ==
6858 01:21:45.428451 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6859 01:21:45.431426 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6860 01:21:45.435233 == TX Byte 1 ==
6861 01:21:45.437965 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6862 01:21:45.441447 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6863 01:21:45.441529 ==
6864 01:21:45.444758 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 01:21:45.451637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 01:21:45.451719 ==
6867 01:21:45.451783
6868 01:21:45.451843
6869 01:21:45.451909 TX Vref Scan disable
6870 01:21:45.454607 == TX Byte 0 ==
6871 01:21:45.457825 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6872 01:21:45.460898 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6873 01:21:45.464081 == TX Byte 1 ==
6874 01:21:45.467432 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6875 01:21:45.470845 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6876 01:21:45.470927
6877 01:21:45.474322 [DATLAT]
6878 01:21:45.474403 Freq=400, CH1 RK1
6879 01:21:45.474467
6880 01:21:45.477822 DATLAT Default: 0xe
6881 01:21:45.477903 0, 0xFFFF, sum = 0
6882 01:21:45.480430 1, 0xFFFF, sum = 0
6883 01:21:45.480512 2, 0xFFFF, sum = 0
6884 01:21:45.484180 3, 0xFFFF, sum = 0
6885 01:21:45.484262 4, 0xFFFF, sum = 0
6886 01:21:45.486920 5, 0xFFFF, sum = 0
6887 01:21:45.490781 6, 0xFFFF, sum = 0
6888 01:21:45.490864 7, 0xFFFF, sum = 0
6889 01:21:45.493586 8, 0xFFFF, sum = 0
6890 01:21:45.493670 9, 0xFFFF, sum = 0
6891 01:21:45.497130 10, 0xFFFF, sum = 0
6892 01:21:45.497213 11, 0xFFFF, sum = 0
6893 01:21:45.500501 12, 0xFFFF, sum = 0
6894 01:21:45.500583 13, 0x0, sum = 1
6895 01:21:45.503289 14, 0x0, sum = 2
6896 01:21:45.503371 15, 0x0, sum = 3
6897 01:21:45.506670 16, 0x0, sum = 4
6898 01:21:45.506752 best_step = 14
6899 01:21:45.506816
6900 01:21:45.506920 ==
6901 01:21:45.510107 Dram Type= 6, Freq= 0, CH_1, rank 1
6902 01:21:45.516536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6903 01:21:45.516618 ==
6904 01:21:45.516682 RX Vref Scan: 0
6905 01:21:45.516741
6906 01:21:45.519740 RX Vref 0 -> 0, step: 1
6907 01:21:45.519821
6908 01:21:45.523373 RX Delay -343 -> 252, step: 8
6909 01:21:45.530085 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6910 01:21:45.533190 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6911 01:21:45.536014 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6912 01:21:45.539580 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6913 01:21:45.546292 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6914 01:21:45.549280 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6915 01:21:45.552877 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6916 01:21:45.555866 iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488
6917 01:21:45.562468 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6918 01:21:45.565812 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6919 01:21:45.568932 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6920 01:21:45.572741 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6921 01:21:45.578731 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6922 01:21:45.582581 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6923 01:21:45.585803 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6924 01:21:45.592487 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6925 01:21:45.592569 ==
6926 01:21:45.595294 Dram Type= 6, Freq= 0, CH_1, rank 1
6927 01:21:45.598915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6928 01:21:45.598997 ==
6929 01:21:45.599061 DQS Delay:
6930 01:21:45.602828 DQS0 = 48, DQS1 = 52
6931 01:21:45.602909 DQM Delay:
6932 01:21:45.605319 DQM0 = 12, DQM1 = 9
6933 01:21:45.605400 DQ Delay:
6934 01:21:45.608940 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
6935 01:21:45.611795 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =12
6936 01:21:45.615131 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6937 01:21:45.618771 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6938 01:21:45.618853
6939 01:21:45.618917
6940 01:21:45.625413 [DQSOSCAuto] RK1, (LSB)MR18= 0x6aa1, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
6941 01:21:45.628531 CH1 RK1: MR19=C0C, MR18=6AA1
6942 01:21:45.634925 CH1_RK1: MR19=0xC0C, MR18=0x6AA1, DQSOSC=389, MR23=63, INC=390, DEC=260
6943 01:21:45.638456 [RxdqsGatingPostProcess] freq 400
6944 01:21:45.644744 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6945 01:21:45.647822 best DQS0 dly(2T, 0.5T) = (0, 10)
6946 01:21:45.651312 best DQS1 dly(2T, 0.5T) = (0, 10)
6947 01:21:45.654449 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6948 01:21:45.658197 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6949 01:21:45.660975 best DQS0 dly(2T, 0.5T) = (0, 10)
6950 01:21:45.661063 best DQS1 dly(2T, 0.5T) = (0, 10)
6951 01:21:45.664744 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6952 01:21:45.667701 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6953 01:21:45.670841 Pre-setting of DQS Precalculation
6954 01:21:45.677891 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6955 01:21:45.684156 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6956 01:21:45.691109 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6957 01:21:45.691191
6958 01:21:45.691254
6959 01:21:45.694049 [Calibration Summary] 800 Mbps
6960 01:21:45.697995 CH 0, Rank 0
6961 01:21:45.698077 SW Impedance : PASS
6962 01:21:45.700896 DUTY Scan : NO K
6963 01:21:45.704662 ZQ Calibration : PASS
6964 01:21:45.704743 Jitter Meter : NO K
6965 01:21:45.707028 CBT Training : PASS
6966 01:21:45.707109 Write leveling : PASS
6967 01:21:45.710353 RX DQS gating : PASS
6968 01:21:45.714192 RX DQ/DQS(RDDQC) : PASS
6969 01:21:45.714274 TX DQ/DQS : PASS
6970 01:21:45.717148 RX DATLAT : PASS
6971 01:21:45.720691 RX DQ/DQS(Engine): PASS
6972 01:21:45.720772 TX OE : NO K
6973 01:21:45.723536 All Pass.
6974 01:21:45.723617
6975 01:21:45.723681 CH 0, Rank 1
6976 01:21:45.726796 SW Impedance : PASS
6977 01:21:45.726882 DUTY Scan : NO K
6978 01:21:45.730824 ZQ Calibration : PASS
6979 01:21:45.733844 Jitter Meter : NO K
6980 01:21:45.733939 CBT Training : PASS
6981 01:21:45.736694 Write leveling : NO K
6982 01:21:45.740619 RX DQS gating : PASS
6983 01:21:45.740721 RX DQ/DQS(RDDQC) : PASS
6984 01:21:45.743363 TX DQ/DQS : PASS
6985 01:21:45.746799 RX DATLAT : PASS
6986 01:21:45.746919 RX DQ/DQS(Engine): PASS
6987 01:21:45.750208 TX OE : NO K
6988 01:21:45.750330 All Pass.
6989 01:21:45.750425
6990 01:21:45.753759 CH 1, Rank 0
6991 01:21:45.753901 SW Impedance : PASS
6992 01:21:45.756907 DUTY Scan : NO K
6993 01:21:45.759918 ZQ Calibration : PASS
6994 01:21:45.760070 Jitter Meter : NO K
6995 01:21:45.763198 CBT Training : PASS
6996 01:21:45.766672 Write leveling : PASS
6997 01:21:45.766880 RX DQS gating : PASS
6998 01:21:45.769620 RX DQ/DQS(RDDQC) : PASS
6999 01:21:45.772976 TX DQ/DQS : PASS
7000 01:21:45.773218 RX DATLAT : PASS
7001 01:21:45.776462 RX DQ/DQS(Engine): PASS
7002 01:21:45.779630 TX OE : NO K
7003 01:21:45.780060 All Pass.
7004 01:21:45.780305
7005 01:21:45.780525 CH 1, Rank 1
7006 01:21:45.783583 SW Impedance : PASS
7007 01:21:45.786316 DUTY Scan : NO K
7008 01:21:45.786832 ZQ Calibration : PASS
7009 01:21:45.789792 Jitter Meter : NO K
7010 01:21:45.793031 CBT Training : PASS
7011 01:21:45.793449 Write leveling : NO K
7012 01:21:45.796207 RX DQS gating : PASS
7013 01:21:45.799980 RX DQ/DQS(RDDQC) : PASS
7014 01:21:45.800428 TX DQ/DQS : PASS
7015 01:21:45.803189 RX DATLAT : PASS
7016 01:21:45.805924 RX DQ/DQS(Engine): PASS
7017 01:21:45.806407 TX OE : NO K
7018 01:21:45.806748 All Pass.
7019 01:21:45.809377
7020 01:21:45.809795 DramC Write-DBI off
7021 01:21:45.813009 PER_BANK_REFRESH: Hybrid Mode
7022 01:21:45.813527 TX_TRACKING: ON
7023 01:21:45.822753 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7024 01:21:45.826035 [FAST_K] Save calibration result to emmc
7025 01:21:45.829112 dramc_set_vcore_voltage set vcore to 725000
7026 01:21:45.832529 Read voltage for 1600, 0
7027 01:21:45.832947 Vio18 = 0
7028 01:21:45.835970 Vcore = 725000
7029 01:21:45.836392 Vdram = 0
7030 01:21:45.836802 Vddq = 0
7031 01:21:45.838791 Vmddr = 0
7032 01:21:45.842601 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7033 01:21:45.848894 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7034 01:21:45.849331 MEM_TYPE=3, freq_sel=13
7035 01:21:45.852380 sv_algorithm_assistance_LP4_3733
7036 01:21:45.858978 ============ PULL DRAM RESETB DOWN ============
7037 01:21:45.862136 ========== PULL DRAM RESETB DOWN end =========
7038 01:21:45.865564 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7039 01:21:45.868610 ===================================
7040 01:21:45.871965 LPDDR4 DRAM CONFIGURATION
7041 01:21:45.875431 ===================================
7042 01:21:45.878619 EX_ROW_EN[0] = 0x0
7043 01:21:45.879131 EX_ROW_EN[1] = 0x0
7044 01:21:45.881832 LP4Y_EN = 0x0
7045 01:21:45.882374 WORK_FSP = 0x1
7046 01:21:45.885056 WL = 0x5
7047 01:21:45.885573 RL = 0x5
7048 01:21:45.888490 BL = 0x2
7049 01:21:45.888904 RPST = 0x0
7050 01:21:45.891511 RD_PRE = 0x0
7051 01:21:45.892048 WR_PRE = 0x1
7052 01:21:45.894824 WR_PST = 0x1
7053 01:21:45.895239 DBI_WR = 0x0
7054 01:21:45.897928 DBI_RD = 0x0
7055 01:21:45.898344 OTF = 0x1
7056 01:21:45.901947 ===================================
7057 01:21:45.904896 ===================================
7058 01:21:45.908450 ANA top config
7059 01:21:45.911516 ===================================
7060 01:21:45.914718 DLL_ASYNC_EN = 0
7061 01:21:45.915227 ALL_SLAVE_EN = 0
7062 01:21:45.917709 NEW_RANK_MODE = 1
7063 01:21:45.921158 DLL_IDLE_MODE = 1
7064 01:21:45.924374 LP45_APHY_COMB_EN = 1
7065 01:21:45.928015 TX_ODT_DIS = 0
7066 01:21:45.928532 NEW_8X_MODE = 1
7067 01:21:45.931146 ===================================
7068 01:21:45.934730 ===================================
7069 01:21:45.937289 data_rate = 3200
7070 01:21:45.941336 CKR = 1
7071 01:21:45.944619 DQ_P2S_RATIO = 8
7072 01:21:45.947779 ===================================
7073 01:21:45.951384 CA_P2S_RATIO = 8
7074 01:21:45.954468 DQ_CA_OPEN = 0
7075 01:21:45.955002 DQ_SEMI_OPEN = 0
7076 01:21:45.957356 CA_SEMI_OPEN = 0
7077 01:21:45.960822 CA_FULL_RATE = 0
7078 01:21:45.964069 DQ_CKDIV4_EN = 0
7079 01:21:45.967322 CA_CKDIV4_EN = 0
7080 01:21:45.970273 CA_PREDIV_EN = 0
7081 01:21:45.974447 PH8_DLY = 12
7082 01:21:45.974996 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7083 01:21:45.976937 DQ_AAMCK_DIV = 4
7084 01:21:45.980243 CA_AAMCK_DIV = 4
7085 01:21:45.983733 CA_ADMCK_DIV = 4
7086 01:21:45.986829 DQ_TRACK_CA_EN = 0
7087 01:21:45.990228 CA_PICK = 1600
7088 01:21:45.993512 CA_MCKIO = 1600
7089 01:21:45.993952 MCKIO_SEMI = 0
7090 01:21:45.996730 PLL_FREQ = 3068
7091 01:21:46.000019 DQ_UI_PI_RATIO = 32
7092 01:21:46.003540 CA_UI_PI_RATIO = 0
7093 01:21:46.007004 ===================================
7094 01:21:46.010266 ===================================
7095 01:21:46.013467 memory_type:LPDDR4
7096 01:21:46.013983 GP_NUM : 10
7097 01:21:46.016773 SRAM_EN : 1
7098 01:21:46.020266 MD32_EN : 0
7099 01:21:46.023218 ===================================
7100 01:21:46.023742 [ANA_INIT] >>>>>>>>>>>>>>
7101 01:21:46.027022 <<<<<< [CONFIGURE PHASE]: ANA_TX
7102 01:21:46.029694 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7103 01:21:46.033372 ===================================
7104 01:21:46.036332 data_rate = 3200,PCW = 0X7600
7105 01:21:46.039734 ===================================
7106 01:21:46.042683 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7107 01:21:46.049502 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7108 01:21:46.052726 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7109 01:21:46.059994 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7110 01:21:46.062399 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7111 01:21:46.066115 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7112 01:21:46.069490 [ANA_INIT] flow start
7113 01:21:46.070004 [ANA_INIT] PLL >>>>>>>>
7114 01:21:46.072806 [ANA_INIT] PLL <<<<<<<<
7115 01:21:46.076100 [ANA_INIT] MIDPI >>>>>>>>
7116 01:21:46.076522 [ANA_INIT] MIDPI <<<<<<<<
7117 01:21:46.079176 [ANA_INIT] DLL >>>>>>>>
7118 01:21:46.082548 [ANA_INIT] DLL <<<<<<<<
7119 01:21:46.082965 [ANA_INIT] flow end
7120 01:21:46.089007 ============ LP4 DIFF to SE enter ============
7121 01:21:46.092392 ============ LP4 DIFF to SE exit ============
7122 01:21:46.095744 [ANA_INIT] <<<<<<<<<<<<<
7123 01:21:46.098630 [Flow] Enable top DCM control >>>>>
7124 01:21:46.102340 [Flow] Enable top DCM control <<<<<
7125 01:21:46.102857 Enable DLL master slave shuffle
7126 01:21:46.108582 ==============================================================
7127 01:21:46.111878 Gating Mode config
7128 01:21:46.115499 ==============================================================
7129 01:21:46.118985 Config description:
7130 01:21:46.128862 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7131 01:21:46.135269 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7132 01:21:46.139454 SELPH_MODE 0: By rank 1: By Phase
7133 01:21:46.145357 ==============================================================
7134 01:21:46.147930 GAT_TRACK_EN = 1
7135 01:21:46.151347 RX_GATING_MODE = 2
7136 01:21:46.154831 RX_GATING_TRACK_MODE = 2
7137 01:21:46.158280 SELPH_MODE = 1
7138 01:21:46.161989 PICG_EARLY_EN = 1
7139 01:21:46.162505 VALID_LAT_VALUE = 1
7140 01:21:46.167906 ==============================================================
7141 01:21:46.171168 Enter into Gating configuration >>>>
7142 01:21:46.174399 Exit from Gating configuration <<<<
7143 01:21:46.177946 Enter into DVFS_PRE_config >>>>>
7144 01:21:46.190812 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7145 01:21:46.191344 Exit from DVFS_PRE_config <<<<<
7146 01:21:46.194298 Enter into PICG configuration >>>>
7147 01:21:46.197538 Exit from PICG configuration <<<<
7148 01:21:46.200956 [RX_INPUT] configuration >>>>>
7149 01:21:46.204203 [RX_INPUT] configuration <<<<<
7150 01:21:46.211159 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7151 01:21:46.214552 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7152 01:21:46.220519 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7153 01:21:46.227136 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7154 01:21:46.233713 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7155 01:21:46.240564 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7156 01:21:46.243938 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7157 01:21:46.246649 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7158 01:21:46.253223 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7159 01:21:46.256891 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7160 01:21:46.259967 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7161 01:21:46.263558 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7162 01:21:46.266586 ===================================
7163 01:21:46.269809 LPDDR4 DRAM CONFIGURATION
7164 01:21:46.273037 ===================================
7165 01:21:46.276475 EX_ROW_EN[0] = 0x0
7166 01:21:46.276942 EX_ROW_EN[1] = 0x0
7167 01:21:46.279711 LP4Y_EN = 0x0
7168 01:21:46.280312 WORK_FSP = 0x1
7169 01:21:46.283077 WL = 0x5
7170 01:21:46.283679 RL = 0x5
7171 01:21:46.286073 BL = 0x2
7172 01:21:46.286537 RPST = 0x0
7173 01:21:46.289817 RD_PRE = 0x0
7174 01:21:46.292519 WR_PRE = 0x1
7175 01:21:46.292936 WR_PST = 0x1
7176 01:21:46.295977 DBI_WR = 0x0
7177 01:21:46.296398 DBI_RD = 0x0
7178 01:21:46.299146 OTF = 0x1
7179 01:21:46.302370 ===================================
7180 01:21:46.305673 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7181 01:21:46.309559 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7182 01:21:46.312410 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7183 01:21:46.316046 ===================================
7184 01:21:46.319575 LPDDR4 DRAM CONFIGURATION
7185 01:21:46.322518 ===================================
7186 01:21:46.325663 EX_ROW_EN[0] = 0x10
7187 01:21:46.326181 EX_ROW_EN[1] = 0x0
7188 01:21:46.328891 LP4Y_EN = 0x0
7189 01:21:46.329405 WORK_FSP = 0x1
7190 01:21:46.332304 WL = 0x5
7191 01:21:46.335518 RL = 0x5
7192 01:21:46.336096 BL = 0x2
7193 01:21:46.339103 RPST = 0x0
7194 01:21:46.339519 RD_PRE = 0x0
7195 01:21:46.341767 WR_PRE = 0x1
7196 01:21:46.342189 WR_PST = 0x1
7197 01:21:46.345005 DBI_WR = 0x0
7198 01:21:46.345421 DBI_RD = 0x0
7199 01:21:46.348544 OTF = 0x1
7200 01:21:46.351985 ===================================
7201 01:21:46.358569 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7202 01:21:46.359081 ==
7203 01:21:46.362288 Dram Type= 6, Freq= 0, CH_0, rank 0
7204 01:21:46.365489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7205 01:21:46.366002 ==
7206 01:21:46.368842 [Duty_Offset_Calibration]
7207 01:21:46.369354 B0:2 B1:0 CA:4
7208 01:21:46.369686
7209 01:21:46.371467 [DutyScan_Calibration_Flow] k_type=0
7210 01:21:46.380838
7211 01:21:46.381248 ==CLK 0==
7212 01:21:46.384511 Final CLK duty delay cell = -4
7213 01:21:46.387694 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7214 01:21:46.390868 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7215 01:21:46.394218 [-4] AVG Duty = 4937%(X100)
7216 01:21:46.394694
7217 01:21:46.397396 CH0 CLK Duty spec in!! Max-Min= 187%
7218 01:21:46.400827 [DutyScan_Calibration_Flow] ====Done====
7219 01:21:46.401242
7220 01:21:46.403980 [DutyScan_Calibration_Flow] k_type=1
7221 01:21:46.421865
7222 01:21:46.422384 ==DQS 0 ==
7223 01:21:46.424509 Final DQS duty delay cell = 0
7224 01:21:46.427779 [0] MAX Duty = 5218%(X100), DQS PI = 38
7225 01:21:46.431111 [0] MIN Duty = 5093%(X100), DQS PI = 12
7226 01:21:46.434561 [0] AVG Duty = 5155%(X100)
7227 01:21:46.435069
7228 01:21:46.435399 ==DQS 1 ==
7229 01:21:46.437919 Final DQS duty delay cell = 0
7230 01:21:46.441261 [0] MAX Duty = 5187%(X100), DQS PI = 0
7231 01:21:46.444481 [0] MIN Duty = 4938%(X100), DQS PI = 58
7232 01:21:46.447840 [0] AVG Duty = 5062%(X100)
7233 01:21:46.448384
7234 01:21:46.451124 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7235 01:21:46.451675
7236 01:21:46.454845 CH0 DQS 1 Duty spec in!! Max-Min= 249%
7237 01:21:46.457643 [DutyScan_Calibration_Flow] ====Done====
7238 01:21:46.458152
7239 01:21:46.461008 [DutyScan_Calibration_Flow] k_type=3
7240 01:21:46.478793
7241 01:21:46.479340 ==DQM 0 ==
7242 01:21:46.481950 Final DQM duty delay cell = 0
7243 01:21:46.485003 [0] MAX Duty = 5124%(X100), DQS PI = 22
7244 01:21:46.488599 [0] MIN Duty = 4875%(X100), DQS PI = 54
7245 01:21:46.491695 [0] AVG Duty = 4999%(X100)
7246 01:21:46.492294
7247 01:21:46.492663 ==DQM 1 ==
7248 01:21:46.494796 Final DQM duty delay cell = 0
7249 01:21:46.498319 [0] MAX Duty = 5000%(X100), DQS PI = 4
7250 01:21:46.501529 [0] MIN Duty = 4844%(X100), DQS PI = 16
7251 01:21:46.505332 [0] AVG Duty = 4922%(X100)
7252 01:21:46.505888
7253 01:21:46.508479 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7254 01:21:46.508938
7255 01:21:46.511209 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7256 01:21:46.515104 [DutyScan_Calibration_Flow] ====Done====
7257 01:21:46.515718
7258 01:21:46.517926 [DutyScan_Calibration_Flow] k_type=2
7259 01:21:46.535763
7260 01:21:46.536357 ==DQ 0 ==
7261 01:21:46.538908 Final DQ duty delay cell = 0
7262 01:21:46.542508 [0] MAX Duty = 5156%(X100), DQS PI = 26
7263 01:21:46.545543 [0] MIN Duty = 4938%(X100), DQS PI = 12
7264 01:21:46.548856 [0] AVG Duty = 5047%(X100)
7265 01:21:46.549317
7266 01:21:46.549683 ==DQ 1 ==
7267 01:21:46.552135 Final DQ duty delay cell = 0
7268 01:21:46.555494 [0] MAX Duty = 5187%(X100), DQS PI = 2
7269 01:21:46.558812 [0] MIN Duty = 4907%(X100), DQS PI = 32
7270 01:21:46.559415 [0] AVG Duty = 5047%(X100)
7271 01:21:46.562771
7272 01:21:46.565143 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7273 01:21:46.565606
7274 01:21:46.568794 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7275 01:21:46.571819 [DutyScan_Calibration_Flow] ====Done====
7276 01:21:46.572260 ==
7277 01:21:46.575772 Dram Type= 6, Freq= 0, CH_1, rank 0
7278 01:21:46.578072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7279 01:21:46.578496 ==
7280 01:21:46.581636 [Duty_Offset_Calibration]
7281 01:21:46.582150 B0:0 B1:-1 CA:3
7282 01:21:46.582488
7283 01:21:46.584829 [DutyScan_Calibration_Flow] k_type=0
7284 01:21:46.595113
7285 01:21:46.595626 ==CLK 0==
7286 01:21:46.598278 Final CLK duty delay cell = -4
7287 01:21:46.602580 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7288 01:21:46.605349 [-4] MIN Duty = 4875%(X100), DQS PI = 12
7289 01:21:46.608279 [-4] AVG Duty = 4937%(X100)
7290 01:21:46.608760
7291 01:21:46.611632 CH1 CLK Duty spec in!! Max-Min= 125%
7292 01:21:46.615549 [DutyScan_Calibration_Flow] ====Done====
7293 01:21:46.616165
7294 01:21:46.618195 [DutyScan_Calibration_Flow] k_type=1
7295 01:21:46.634725
7296 01:21:46.635302 ==DQS 0 ==
7297 01:21:46.637680 Final DQS duty delay cell = 0
7298 01:21:46.640593 [0] MAX Duty = 5250%(X100), DQS PI = 28
7299 01:21:46.643965 [0] MIN Duty = 4907%(X100), DQS PI = 58
7300 01:21:46.647310 [0] AVG Duty = 5078%(X100)
7301 01:21:46.647771
7302 01:21:46.648186 ==DQS 1 ==
7303 01:21:46.650954 Final DQS duty delay cell = -4
7304 01:21:46.654235 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7305 01:21:46.657363 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7306 01:21:46.660647 [-4] AVG Duty = 4906%(X100)
7307 01:21:46.661114
7308 01:21:46.663593 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7309 01:21:46.664080
7310 01:21:46.667653 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7311 01:21:46.670099 [DutyScan_Calibration_Flow] ====Done====
7312 01:21:46.670546
7313 01:21:46.673610 [DutyScan_Calibration_Flow] k_type=3
7314 01:21:46.691629
7315 01:21:46.692241 ==DQM 0 ==
7316 01:21:46.695102 Final DQM duty delay cell = 0
7317 01:21:46.698046 [0] MAX Duty = 5031%(X100), DQS PI = 30
7318 01:21:46.701445 [0] MIN Duty = 4750%(X100), DQS PI = 40
7319 01:21:46.704801 [0] AVG Duty = 4890%(X100)
7320 01:21:46.705271
7321 01:21:46.705643 ==DQM 1 ==
7322 01:21:46.707868 Final DQM duty delay cell = 0
7323 01:21:46.711553 [0] MAX Duty = 4969%(X100), DQS PI = 30
7324 01:21:46.714362 [0] MIN Duty = 4813%(X100), DQS PI = 0
7325 01:21:46.718065 [0] AVG Duty = 4891%(X100)
7326 01:21:46.718583
7327 01:21:46.721205 CH1 DQM 0 Duty spec in!! Max-Min= 281%
7328 01:21:46.721761
7329 01:21:46.724480 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7330 01:21:46.727748 [DutyScan_Calibration_Flow] ====Done====
7331 01:21:46.728321
7332 01:21:46.731696 [DutyScan_Calibration_Flow] k_type=2
7333 01:21:46.747809
7334 01:21:46.748409 ==DQ 0 ==
7335 01:21:46.751296 Final DQ duty delay cell = -4
7336 01:21:46.754324 [-4] MAX Duty = 4938%(X100), DQS PI = 8
7337 01:21:46.757234 [-4] MIN Duty = 4813%(X100), DQS PI = 20
7338 01:21:46.760945 [-4] AVG Duty = 4875%(X100)
7339 01:21:46.761497
7340 01:21:46.761875 ==DQ 1 ==
7341 01:21:46.764307 Final DQ duty delay cell = 0
7342 01:21:46.767507 [0] MAX Duty = 5062%(X100), DQS PI = 32
7343 01:21:46.770232 [0] MIN Duty = 4844%(X100), DQS PI = 60
7344 01:21:46.773860 [0] AVG Duty = 4953%(X100)
7345 01:21:46.774413
7346 01:21:46.776827 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7347 01:21:46.777294
7348 01:21:46.780590 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7349 01:21:46.783580 [DutyScan_Calibration_Flow] ====Done====
7350 01:21:46.786674 nWR fixed to 30
7351 01:21:46.790327 [ModeRegInit_LP4] CH0 RK0
7352 01:21:46.790801 [ModeRegInit_LP4] CH0 RK1
7353 01:21:46.793404 [ModeRegInit_LP4] CH1 RK0
7354 01:21:46.797091 [ModeRegInit_LP4] CH1 RK1
7355 01:21:46.797736 match AC timing 5
7356 01:21:46.803438 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7357 01:21:46.806754 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7358 01:21:46.810285 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7359 01:21:46.816943 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7360 01:21:46.819995 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7361 01:21:46.820431 [MiockJmeterHQA]
7362 01:21:46.823423
7363 01:21:46.823801 [DramcMiockJmeter] u1RxGatingPI = 0
7364 01:21:46.826758 0 : 4363, 4138
7365 01:21:46.827190 4 : 4253, 4027
7366 01:21:46.829990 8 : 4253, 4027
7367 01:21:46.830521 12 : 4255, 4030
7368 01:21:46.833097 16 : 4253, 4026
7369 01:21:46.833530 20 : 4363, 4137
7370 01:21:46.836259 24 : 4363, 4137
7371 01:21:46.836693 28 : 4252, 4027
7372 01:21:46.837126 32 : 4252, 4027
7373 01:21:46.839501 36 : 4255, 4029
7374 01:21:46.840114 40 : 4363, 4138
7375 01:21:46.843215 44 : 4252, 4026
7376 01:21:46.843662 48 : 4366, 4139
7377 01:21:46.846079 52 : 4255, 4029
7378 01:21:46.846516 56 : 4363, 4140
7379 01:21:46.849517 60 : 4250, 4027
7380 01:21:46.849998 64 : 4252, 4029
7381 01:21:46.850670 68 : 4360, 4138
7382 01:21:46.852844 72 : 4250, 4027
7383 01:21:46.853275 76 : 4361, 4137
7384 01:21:46.856111 80 : 4363, 4139
7385 01:21:46.856661 84 : 4253, 4029
7386 01:21:46.859712 88 : 4253, 4029
7387 01:21:46.860220 92 : 4360, 4138
7388 01:21:46.862951 96 : 4250, 2717
7389 01:21:46.863380 100 : 4363, 0
7390 01:21:46.863727 104 : 4252, 0
7391 01:21:46.866345 108 : 4363, 0
7392 01:21:46.866774 112 : 4360, 0
7393 01:21:46.867117 116 : 4363, 0
7394 01:21:46.869410 120 : 4250, 0
7395 01:21:46.869841 124 : 4250, 0
7396 01:21:46.872732 128 : 4250, 0
7397 01:21:46.873176 132 : 4253, 0
7398 01:21:46.873518 136 : 4250, 0
7399 01:21:46.875740 140 : 4250, 0
7400 01:21:46.876247 144 : 4255, 0
7401 01:21:46.879231 148 : 4361, 0
7402 01:21:46.879827 152 : 4361, 0
7403 01:21:46.880233 156 : 4250, 0
7404 01:21:46.882430 160 : 4250, 0
7405 01:21:46.882857 164 : 4360, 0
7406 01:21:46.885846 168 : 4250, 0
7407 01:21:46.886281 172 : 4250, 0
7408 01:21:46.886643 176 : 4250, 0
7409 01:21:46.889418 180 : 4250, 0
7410 01:21:46.889990 184 : 4253, 0
7411 01:21:46.892323 188 : 4250, 0
7412 01:21:46.892756 192 : 4250, 0
7413 01:21:46.893202 196 : 4255, 0
7414 01:21:46.896058 200 : 4361, 0
7415 01:21:46.896489 204 : 4361, 0
7416 01:21:46.899005 208 : 4250, 0
7417 01:21:46.899436 212 : 4250, 0
7418 01:21:46.899777 216 : 4360, 0
7419 01:21:46.902154 220 : 4250, 867
7420 01:21:46.902582 224 : 4250, 4021
7421 01:21:46.905824 228 : 4250, 4027
7422 01:21:46.906254 232 : 4250, 4027
7423 01:21:46.909125 236 : 4250, 4026
7424 01:21:46.909556 240 : 4360, 4138
7425 01:21:46.912728 244 : 4250, 4027
7426 01:21:46.913164 248 : 4250, 4027
7427 01:21:46.916148 252 : 4250, 4026
7428 01:21:46.916727 256 : 4363, 4139
7429 01:21:46.917158 260 : 4363, 4138
7430 01:21:46.918840 264 : 4250, 4027
7431 01:21:46.919276 268 : 4250, 4027
7432 01:21:46.922136 272 : 4250, 4027
7433 01:21:46.922575 276 : 4250, 4027
7434 01:21:46.925413 280 : 4250, 4027
7435 01:21:46.925847 284 : 4252, 4029
7436 01:21:46.928584 288 : 4250, 4027
7437 01:21:46.929017 292 : 4360, 4138
7438 01:21:46.932776 296 : 4250, 4027
7439 01:21:46.933313 300 : 4249, 4027
7440 01:21:46.935268 304 : 4250, 4026
7441 01:21:46.935706 308 : 4360, 4138
7442 01:21:46.938320 312 : 4360, 4138
7443 01:21:46.938757 316 : 4250, 4027
7444 01:21:46.941790 320 : 4363, 4140
7445 01:21:46.942327 324 : 4250, 4027
7446 01:21:46.945110 328 : 4250, 4027
7447 01:21:46.945547 332 : 4250, 3851
7448 01:21:46.946082 336 : 4252, 1631
7449 01:21:46.948194
7450 01:21:46.948624 MIOCK jitter meter ch=0
7451 01:21:46.949058
7452 01:21:46.951791 1T = (336-100) = 236 dly cells
7453 01:21:46.958253 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7454 01:21:46.958784 ==
7455 01:21:46.961281 Dram Type= 6, Freq= 0, CH_0, rank 0
7456 01:21:46.964806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7457 01:21:46.965343 ==
7458 01:21:46.971028 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7459 01:21:46.974911 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7460 01:21:46.977691 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7461 01:21:46.984482 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7462 01:21:46.994131 [CA 0] Center 44 (14~74) winsize 61
7463 01:21:46.997398 [CA 1] Center 43 (13~74) winsize 62
7464 01:21:47.000709 [CA 2] Center 39 (10~68) winsize 59
7465 01:21:47.003984 [CA 3] Center 38 (9~68) winsize 60
7466 01:21:47.007101 [CA 4] Center 36 (6~66) winsize 61
7467 01:21:47.010334 [CA 5] Center 36 (6~66) winsize 61
7468 01:21:47.010764
7469 01:21:47.013617 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7470 01:21:47.014061
7471 01:21:47.020529 [CATrainingPosCal] consider 1 rank data
7472 01:21:47.021064 u2DelayCellTimex100 = 275/100 ps
7473 01:21:47.027277 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7474 01:21:47.030046 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7475 01:21:47.034032 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7476 01:21:47.037392 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7477 01:21:47.039771 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
7478 01:21:47.043303 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7479 01:21:47.043845
7480 01:21:47.046650 CA PerBit enable=1, Macro0, CA PI delay=36
7481 01:21:47.047079
7482 01:21:47.050798 [CBTSetCACLKResult] CA Dly = 36
7483 01:21:47.053353 CS Dly: 11 (0~42)
7484 01:21:47.056861 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7485 01:21:47.060229 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7486 01:21:47.063250 ==
7487 01:21:47.066586 Dram Type= 6, Freq= 0, CH_0, rank 1
7488 01:21:47.069662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7489 01:21:47.070117 ==
7490 01:21:47.073347 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7491 01:21:47.079410 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7492 01:21:47.083037 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7493 01:21:47.089042 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7494 01:21:47.097968 [CA 0] Center 44 (14~75) winsize 62
7495 01:21:47.100804 [CA 1] Center 44 (14~74) winsize 61
7496 01:21:47.104373 [CA 2] Center 39 (10~69) winsize 60
7497 01:21:47.107396 [CA 3] Center 39 (10~68) winsize 59
7498 01:21:47.111020 [CA 4] Center 37 (7~67) winsize 61
7499 01:21:47.114424 [CA 5] Center 36 (7~66) winsize 60
7500 01:21:47.115052
7501 01:21:47.117518 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7502 01:21:47.121044
7503 01:21:47.124277 [CATrainingPosCal] consider 2 rank data
7504 01:21:47.124795 u2DelayCellTimex100 = 275/100 ps
7505 01:21:47.130797 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7506 01:21:47.134121 CA1 delay=44 (14~74),Diff = 8 PI (28 cell)
7507 01:21:47.137154 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7508 01:21:47.140260 CA3 delay=39 (10~68),Diff = 3 PI (10 cell)
7509 01:21:47.143667 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7510 01:21:47.146907 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7511 01:21:47.147322
7512 01:21:47.150189 CA PerBit enable=1, Macro0, CA PI delay=36
7513 01:21:47.153594
7514 01:21:47.154008 [CBTSetCACLKResult] CA Dly = 36
7515 01:21:47.157361 CS Dly: 11 (0~43)
7516 01:21:47.160443 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7517 01:21:47.163547 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7518 01:21:47.166941
7519 01:21:47.170132 ----->DramcWriteLeveling(PI) begin...
7520 01:21:47.170682 ==
7521 01:21:47.173724 Dram Type= 6, Freq= 0, CH_0, rank 0
7522 01:21:47.176973 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7523 01:21:47.177555 ==
7524 01:21:47.179961 Write leveling (Byte 0): 35 => 35
7525 01:21:47.183210 Write leveling (Byte 1): 27 => 27
7526 01:21:47.186668 DramcWriteLeveling(PI) end<-----
7527 01:21:47.187188
7528 01:21:47.187582 ==
7529 01:21:47.189565 Dram Type= 6, Freq= 0, CH_0, rank 0
7530 01:21:47.192859 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7531 01:21:47.193319 ==
7532 01:21:47.196222 [Gating] SW mode calibration
7533 01:21:47.202833 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7534 01:21:47.209170 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7535 01:21:47.212835 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7536 01:21:47.215831 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7537 01:21:47.222920 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7538 01:21:47.226094 1 4 12 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
7539 01:21:47.229826 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7540 01:21:47.236042 1 4 20 | B1->B0 | 2928 3434 | 1 1 | (0 0) (1 1)
7541 01:21:47.239205 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7542 01:21:47.242364 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7543 01:21:47.249267 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7544 01:21:47.252186 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7545 01:21:47.255858 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7546 01:21:47.262262 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
7547 01:21:47.265484 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7548 01:21:47.269089 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
7549 01:21:47.275585 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
7550 01:21:47.278945 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7551 01:21:47.281901 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7552 01:21:47.288865 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7553 01:21:47.292181 1 6 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
7554 01:21:47.294736 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
7555 01:21:47.301358 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7556 01:21:47.304550 1 6 20 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
7557 01:21:47.311934 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7558 01:21:47.314840 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7559 01:21:47.317813 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7560 01:21:47.324269 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7561 01:21:47.327582 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7562 01:21:47.331200 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7563 01:21:47.337573 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7564 01:21:47.341004 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7565 01:21:47.344406 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7566 01:21:47.351093 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7567 01:21:47.354256 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 01:21:47.357457 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 01:21:47.363545 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 01:21:47.368311 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 01:21:47.370486 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 01:21:47.376971 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 01:21:47.379964 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 01:21:47.383569 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 01:21:47.389872 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 01:21:47.393577 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 01:21:47.396746 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 01:21:47.403102 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7579 01:21:47.406819 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7580 01:21:47.409935 Total UI for P1: 0, mck2ui 16
7581 01:21:47.413802 best dqsien dly found for B0: ( 1, 9, 12)
7582 01:21:47.416188 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7583 01:21:47.423259 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7584 01:21:47.426433 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7585 01:21:47.429685 Total UI for P1: 0, mck2ui 16
7586 01:21:47.433074 best dqsien dly found for B1: ( 1, 9, 22)
7587 01:21:47.436511 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7588 01:21:47.439367 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7589 01:21:47.439792
7590 01:21:47.443159 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7591 01:21:47.445950 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7592 01:21:47.449362 [Gating] SW calibration Done
7593 01:21:47.449790 ==
7594 01:21:47.452575 Dram Type= 6, Freq= 0, CH_0, rank 0
7595 01:21:47.459788 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7596 01:21:47.460351 ==
7597 01:21:47.460687 RX Vref Scan: 0
7598 01:21:47.460996
7599 01:21:47.462430 RX Vref 0 -> 0, step: 1
7600 01:21:47.462844
7601 01:21:47.465994 RX Delay 0 -> 252, step: 8
7602 01:21:47.469646 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7603 01:21:47.472725 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7604 01:21:47.476282 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7605 01:21:47.479178 iDelay=192, Bit 3, Center 131 (80 ~ 183) 104
7606 01:21:47.485655 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7607 01:21:47.488725 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7608 01:21:47.492454 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7609 01:21:47.495682 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7610 01:21:47.498995 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7611 01:21:47.505300 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7612 01:21:47.508893 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7613 01:21:47.512174 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7614 01:21:47.515486 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7615 01:21:47.522414 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7616 01:21:47.525270 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7617 01:21:47.529155 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7618 01:21:47.529669 ==
7619 01:21:47.532297 Dram Type= 6, Freq= 0, CH_0, rank 0
7620 01:21:47.535377 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7621 01:21:47.536089 ==
7622 01:21:47.538124 DQS Delay:
7623 01:21:47.538539 DQS0 = 0, DQS1 = 0
7624 01:21:47.541349 DQM Delay:
7625 01:21:47.541820 DQM0 = 132, DQM1 = 127
7626 01:21:47.542154 DQ Delay:
7627 01:21:47.548382 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
7628 01:21:47.551267 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7629 01:21:47.554796 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
7630 01:21:47.558176 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7631 01:21:47.558706
7632 01:21:47.559039
7633 01:21:47.559344 ==
7634 01:21:47.561478 Dram Type= 6, Freq= 0, CH_0, rank 0
7635 01:21:47.564585 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7636 01:21:47.565159 ==
7637 01:21:47.565503
7638 01:21:47.565881
7639 01:21:47.567990 TX Vref Scan disable
7640 01:21:47.571322 == TX Byte 0 ==
7641 01:21:47.574890 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7642 01:21:47.577771 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7643 01:21:47.580721 == TX Byte 1 ==
7644 01:21:47.584539 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7645 01:21:47.587912 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7646 01:21:47.588512 ==
7647 01:21:47.591301 Dram Type= 6, Freq= 0, CH_0, rank 0
7648 01:21:47.597429 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7649 01:21:47.597856 ==
7650 01:21:47.610079
7651 01:21:47.613252 TX Vref early break, caculate TX vref
7652 01:21:47.616381 TX Vref=16, minBit 4, minWin=22, winSum=364
7653 01:21:47.619547 TX Vref=18, minBit 6, minWin=22, winSum=379
7654 01:21:47.623321 TX Vref=20, minBit 1, minWin=23, winSum=394
7655 01:21:47.626116 TX Vref=22, minBit 1, minWin=23, winSum=398
7656 01:21:47.630424 TX Vref=24, minBit 7, minWin=24, winSum=409
7657 01:21:47.636388 TX Vref=26, minBit 1, minWin=25, winSum=417
7658 01:21:47.639608 TX Vref=28, minBit 7, minWin=25, winSum=424
7659 01:21:47.643159 TX Vref=30, minBit 2, minWin=25, winSum=423
7660 01:21:47.645772 TX Vref=32, minBit 4, minWin=24, winSum=409
7661 01:21:47.649464 TX Vref=34, minBit 1, minWin=24, winSum=400
7662 01:21:47.655820 [TxChooseVref] Worse bit 7, Min win 25, Win sum 424, Final Vref 28
7663 01:21:47.656421
7664 01:21:47.659262 Final TX Range 0 Vref 28
7665 01:21:47.659777
7666 01:21:47.660171 ==
7667 01:21:47.662614 Dram Type= 6, Freq= 0, CH_0, rank 0
7668 01:21:47.665761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7669 01:21:47.666205 ==
7670 01:21:47.666542
7671 01:21:47.666851
7672 01:21:47.669226 TX Vref Scan disable
7673 01:21:47.675843 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7674 01:21:47.676399 == TX Byte 0 ==
7675 01:21:47.678976 u2DelayCellOfst[0]=10 cells (3 PI)
7676 01:21:47.682308 u2DelayCellOfst[1]=14 cells (4 PI)
7677 01:21:47.686168 u2DelayCellOfst[2]=10 cells (3 PI)
7678 01:21:47.688797 u2DelayCellOfst[3]=10 cells (3 PI)
7679 01:21:47.692310 u2DelayCellOfst[4]=10 cells (3 PI)
7680 01:21:47.695647 u2DelayCellOfst[5]=0 cells (0 PI)
7681 01:21:47.698926 u2DelayCellOfst[6]=17 cells (5 PI)
7682 01:21:47.701979 u2DelayCellOfst[7]=14 cells (4 PI)
7683 01:21:47.705001 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7684 01:21:47.708723 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7685 01:21:47.712082 == TX Byte 1 ==
7686 01:21:47.715828 u2DelayCellOfst[8]=0 cells (0 PI)
7687 01:21:47.718291 u2DelayCellOfst[9]=0 cells (0 PI)
7688 01:21:47.722142 u2DelayCellOfst[10]=7 cells (2 PI)
7689 01:21:47.725319 u2DelayCellOfst[11]=3 cells (1 PI)
7690 01:21:47.725862 u2DelayCellOfst[12]=10 cells (3 PI)
7691 01:21:47.728622 u2DelayCellOfst[13]=10 cells (3 PI)
7692 01:21:47.731967 u2DelayCellOfst[14]=14 cells (4 PI)
7693 01:21:47.734785 u2DelayCellOfst[15]=10 cells (3 PI)
7694 01:21:47.741608 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7695 01:21:47.745321 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7696 01:21:47.748287 DramC Write-DBI on
7697 01:21:47.748838 ==
7698 01:21:47.751448 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 01:21:47.754865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 01:21:47.755471 ==
7701 01:21:47.755846
7702 01:21:47.756398
7703 01:21:47.758389 TX Vref Scan disable
7704 01:21:47.758943 == TX Byte 0 ==
7705 01:21:47.764380 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7706 01:21:47.764849 == TX Byte 1 ==
7707 01:21:47.767738 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7708 01:21:47.770871 DramC Write-DBI off
7709 01:21:47.771295
7710 01:21:47.771632 [DATLAT]
7711 01:21:47.774386 Freq=1600, CH0 RK0
7712 01:21:47.774808
7713 01:21:47.775147 DATLAT Default: 0xf
7714 01:21:47.778275 0, 0xFFFF, sum = 0
7715 01:21:47.778798 1, 0xFFFF, sum = 0
7716 01:21:47.780911 2, 0xFFFF, sum = 0
7717 01:21:47.784086 3, 0xFFFF, sum = 0
7718 01:21:47.784598 4, 0xFFFF, sum = 0
7719 01:21:47.787576 5, 0xFFFF, sum = 0
7720 01:21:47.788129 6, 0xFFFF, sum = 0
7721 01:21:47.791397 7, 0xFFFF, sum = 0
7722 01:21:47.791821 8, 0xFFFF, sum = 0
7723 01:21:47.794107 9, 0xFFFF, sum = 0
7724 01:21:47.794532 10, 0xFFFF, sum = 0
7725 01:21:47.797696 11, 0xFFFF, sum = 0
7726 01:21:47.798124 12, 0xFFFF, sum = 0
7727 01:21:47.800419 13, 0xFFFF, sum = 0
7728 01:21:47.800857 14, 0x0, sum = 1
7729 01:21:47.804135 15, 0x0, sum = 2
7730 01:21:47.804560 16, 0x0, sum = 3
7731 01:21:47.807765 17, 0x0, sum = 4
7732 01:21:47.808230 best_step = 15
7733 01:21:47.808563
7734 01:21:47.808872 ==
7735 01:21:47.810836 Dram Type= 6, Freq= 0, CH_0, rank 0
7736 01:21:47.817402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7737 01:21:47.817881 ==
7738 01:21:47.818215 RX Vref Scan: 1
7739 01:21:47.818524
7740 01:21:47.820492 Set Vref Range= 24 -> 127
7741 01:21:47.820906
7742 01:21:47.824078 RX Vref 24 -> 127, step: 1
7743 01:21:47.824593
7744 01:21:47.826788 RX Delay 11 -> 252, step: 4
7745 01:21:47.827204
7746 01:21:47.830324 Set Vref, RX VrefLevel [Byte0]: 24
7747 01:21:47.833950 [Byte1]: 24
7748 01:21:47.834525
7749 01:21:47.837398 Set Vref, RX VrefLevel [Byte0]: 25
7750 01:21:47.840116 [Byte1]: 25
7751 01:21:47.840669
7752 01:21:47.843320 Set Vref, RX VrefLevel [Byte0]: 26
7753 01:21:47.847199 [Byte1]: 26
7754 01:21:47.849947
7755 01:21:47.850452 Set Vref, RX VrefLevel [Byte0]: 27
7756 01:21:47.853377 [Byte1]: 27
7757 01:21:47.858130
7758 01:21:47.858657 Set Vref, RX VrefLevel [Byte0]: 28
7759 01:21:47.861403 [Byte1]: 28
7760 01:21:47.865103
7761 01:21:47.865524 Set Vref, RX VrefLevel [Byte0]: 29
7762 01:21:47.868765 [Byte1]: 29
7763 01:21:47.872826
7764 01:21:47.873440 Set Vref, RX VrefLevel [Byte0]: 30
7765 01:21:47.876188 [Byte1]: 30
7766 01:21:47.880317
7767 01:21:47.880730 Set Vref, RX VrefLevel [Byte0]: 31
7768 01:21:47.883357 [Byte1]: 31
7769 01:21:47.888055
7770 01:21:47.888591 Set Vref, RX VrefLevel [Byte0]: 32
7771 01:21:47.891411 [Byte1]: 32
7772 01:21:47.895509
7773 01:21:47.895963 Set Vref, RX VrefLevel [Byte0]: 33
7774 01:21:47.898940 [Byte1]: 33
7775 01:21:47.903195
7776 01:21:47.903610 Set Vref, RX VrefLevel [Byte0]: 34
7777 01:21:47.906240 [Byte1]: 34
7778 01:21:47.910733
7779 01:21:47.911145 Set Vref, RX VrefLevel [Byte0]: 35
7780 01:21:47.914369 [Byte1]: 35
7781 01:21:47.918311
7782 01:21:47.918761 Set Vref, RX VrefLevel [Byte0]: 36
7783 01:21:47.921857 [Byte1]: 36
7784 01:21:47.926076
7785 01:21:47.926634 Set Vref, RX VrefLevel [Byte0]: 37
7786 01:21:47.929345 [Byte1]: 37
7787 01:21:47.933564
7788 01:21:47.933998 Set Vref, RX VrefLevel [Byte0]: 38
7789 01:21:47.936930 [Byte1]: 38
7790 01:21:47.941552
7791 01:21:47.941982 Set Vref, RX VrefLevel [Byte0]: 39
7792 01:21:47.944205 [Byte1]: 39
7793 01:21:47.948613
7794 01:21:47.949085 Set Vref, RX VrefLevel [Byte0]: 40
7795 01:21:47.952015 [Byte1]: 40
7796 01:21:47.956422
7797 01:21:47.957031 Set Vref, RX VrefLevel [Byte0]: 41
7798 01:21:47.959606 [Byte1]: 41
7799 01:21:47.963803
7800 01:21:47.964305 Set Vref, RX VrefLevel [Byte0]: 42
7801 01:21:47.967163 [Byte1]: 42
7802 01:21:47.972006
7803 01:21:47.972502 Set Vref, RX VrefLevel [Byte0]: 43
7804 01:21:47.975054 [Byte1]: 43
7805 01:21:47.979397
7806 01:21:47.979873 Set Vref, RX VrefLevel [Byte0]: 44
7807 01:21:47.982509 [Byte1]: 44
7808 01:21:47.986854
7809 01:21:47.987279 Set Vref, RX VrefLevel [Byte0]: 45
7810 01:21:47.990018 [Byte1]: 45
7811 01:21:47.994461
7812 01:21:47.995015 Set Vref, RX VrefLevel [Byte0]: 46
7813 01:21:47.998160 [Byte1]: 46
7814 01:21:48.002568
7815 01:21:48.003004 Set Vref, RX VrefLevel [Byte0]: 47
7816 01:21:48.005557 [Byte1]: 47
7817 01:21:48.009666
7818 01:21:48.010119 Set Vref, RX VrefLevel [Byte0]: 48
7819 01:21:48.013008 [Byte1]: 48
7820 01:21:48.017705
7821 01:21:48.018125 Set Vref, RX VrefLevel [Byte0]: 49
7822 01:21:48.020638 [Byte1]: 49
7823 01:21:48.025252
7824 01:21:48.025670 Set Vref, RX VrefLevel [Byte0]: 50
7825 01:21:48.028061 [Byte1]: 50
7826 01:21:48.032535
7827 01:21:48.033232 Set Vref, RX VrefLevel [Byte0]: 51
7828 01:21:48.035722 [Byte1]: 51
7829 01:21:48.040399
7830 01:21:48.040818 Set Vref, RX VrefLevel [Byte0]: 52
7831 01:21:48.043385 [Byte1]: 52
7832 01:21:48.048073
7833 01:21:48.048502 Set Vref, RX VrefLevel [Byte0]: 53
7834 01:21:48.051024 [Byte1]: 53
7835 01:21:48.055839
7836 01:21:48.056309 Set Vref, RX VrefLevel [Byte0]: 54
7837 01:21:48.058820 [Byte1]: 54
7838 01:21:48.063022
7839 01:21:48.063515 Set Vref, RX VrefLevel [Byte0]: 55
7840 01:21:48.066693 [Byte1]: 55
7841 01:21:48.070637
7842 01:21:48.071053 Set Vref, RX VrefLevel [Byte0]: 56
7843 01:21:48.074220 [Byte1]: 56
7844 01:21:48.078087
7845 01:21:48.078503 Set Vref, RX VrefLevel [Byte0]: 57
7846 01:21:48.081716 [Byte1]: 57
7847 01:21:48.085634
7848 01:21:48.086063 Set Vref, RX VrefLevel [Byte0]: 58
7849 01:21:48.089284 [Byte1]: 58
7850 01:21:48.093413
7851 01:21:48.093832 Set Vref, RX VrefLevel [Byte0]: 59
7852 01:21:48.096735 [Byte1]: 59
7853 01:21:48.101315
7854 01:21:48.101729 Set Vref, RX VrefLevel [Byte0]: 60
7855 01:21:48.104484 [Byte1]: 60
7856 01:21:48.108358
7857 01:21:48.108772 Set Vref, RX VrefLevel [Byte0]: 61
7858 01:21:48.112149 [Byte1]: 61
7859 01:21:48.116218
7860 01:21:48.116634 Set Vref, RX VrefLevel [Byte0]: 62
7861 01:21:48.122769 [Byte1]: 62
7862 01:21:48.123317
7863 01:21:48.125968 Set Vref, RX VrefLevel [Byte0]: 63
7864 01:21:48.129658 [Byte1]: 63
7865 01:21:48.130169
7866 01:21:48.132997 Set Vref, RX VrefLevel [Byte0]: 64
7867 01:21:48.135775 [Byte1]: 64
7868 01:21:48.138970
7869 01:21:48.139521 Set Vref, RX VrefLevel [Byte0]: 65
7870 01:21:48.142451 [Byte1]: 65
7871 01:21:48.146582
7872 01:21:48.147023 Set Vref, RX VrefLevel [Byte0]: 66
7873 01:21:48.149768 [Byte1]: 66
7874 01:21:48.154535
7875 01:21:48.155048 Set Vref, RX VrefLevel [Byte0]: 67
7876 01:21:48.157490 [Byte1]: 67
7877 01:21:48.162059
7878 01:21:48.162616 Set Vref, RX VrefLevel [Byte0]: 68
7879 01:21:48.165656 [Byte1]: 68
7880 01:21:48.169995
7881 01:21:48.170539 Set Vref, RX VrefLevel [Byte0]: 69
7882 01:21:48.172889 [Byte1]: 69
7883 01:21:48.176969
7884 01:21:48.177468 Set Vref, RX VrefLevel [Byte0]: 70
7885 01:21:48.180742 [Byte1]: 70
7886 01:21:48.184704
7887 01:21:48.188116 Set Vref, RX VrefLevel [Byte0]: 71
7888 01:21:48.191303 [Byte1]: 71
7889 01:21:48.191815
7890 01:21:48.194919 Set Vref, RX VrefLevel [Byte0]: 72
7891 01:21:48.197643 [Byte1]: 72
7892 01:21:48.198064
7893 01:21:48.200843 Set Vref, RX VrefLevel [Byte0]: 73
7894 01:21:48.204100 [Byte1]: 73
7895 01:21:48.207879
7896 01:21:48.208346 Set Vref, RX VrefLevel [Byte0]: 74
7897 01:21:48.211312 [Byte1]: 74
7898 01:21:48.215963
7899 01:21:48.216470 Set Vref, RX VrefLevel [Byte0]: 75
7900 01:21:48.218609 [Byte1]: 75
7901 01:21:48.222849
7902 01:21:48.223348 Final RX Vref Byte 0 = 57 to rank0
7903 01:21:48.226199 Final RX Vref Byte 1 = 59 to rank0
7904 01:21:48.229481 Final RX Vref Byte 0 = 57 to rank1
7905 01:21:48.232429 Final RX Vref Byte 1 = 59 to rank1==
7906 01:21:48.236456 Dram Type= 6, Freq= 0, CH_0, rank 0
7907 01:21:48.242791 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7908 01:21:48.243282 ==
7909 01:21:48.243617 DQS Delay:
7910 01:21:48.245932 DQS0 = 0, DQS1 = 0
7911 01:21:48.246423 DQM Delay:
7912 01:21:48.246758 DQM0 = 128, DQM1 = 124
7913 01:21:48.249440 DQ Delay:
7914 01:21:48.252844 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7915 01:21:48.255944 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
7916 01:21:48.259050 DQ8 =112, DQ9 =112, DQ10 =124, DQ11 =120
7917 01:21:48.262520 DQ12 =132, DQ13 =128, DQ14 =134, DQ15 =130
7918 01:21:48.263065
7919 01:21:48.263409
7920 01:21:48.263720
7921 01:21:48.265640 [DramC_TX_OE_Calibration] TA2
7922 01:21:48.268947 Original DQ_B0 (3 6) =30, OEN = 27
7923 01:21:48.272456 Original DQ_B1 (3 6) =30, OEN = 27
7924 01:21:48.275465 24, 0x0, End_B0=24 End_B1=24
7925 01:21:48.278837 25, 0x0, End_B0=25 End_B1=25
7926 01:21:48.279332 26, 0x0, End_B0=26 End_B1=26
7927 01:21:48.282345 27, 0x0, End_B0=27 End_B1=27
7928 01:21:48.285577 28, 0x0, End_B0=28 End_B1=28
7929 01:21:48.288797 29, 0x0, End_B0=29 End_B1=29
7930 01:21:48.289220 30, 0x0, End_B0=30 End_B1=30
7931 01:21:48.291945 31, 0x5151, End_B0=30 End_B1=30
7932 01:21:48.295640 Byte0 end_step=30 best_step=27
7933 01:21:48.298615 Byte1 end_step=30 best_step=27
7934 01:21:48.301619 Byte0 TX OE(2T, 0.5T) = (3, 3)
7935 01:21:48.305250 Byte1 TX OE(2T, 0.5T) = (3, 3)
7936 01:21:48.305711
7937 01:21:48.306048
7938 01:21:48.311500 [DQSOSCAuto] RK0, (LSB)MR18= 0x1411, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 399 ps
7939 01:21:48.315253 CH0 RK0: MR19=303, MR18=1411
7940 01:21:48.321588 CH0_RK0: MR19=0x303, MR18=0x1411, DQSOSC=399, MR23=63, INC=23, DEC=15
7941 01:21:48.322025
7942 01:21:48.324692 ----->DramcWriteLeveling(PI) begin...
7943 01:21:48.325211 ==
7944 01:21:48.327854 Dram Type= 6, Freq= 0, CH_0, rank 1
7945 01:21:48.331779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7946 01:21:48.332234 ==
7947 01:21:48.335480 Write leveling (Byte 0): 36 => 36
7948 01:21:48.337772 Write leveling (Byte 1): 27 => 27
7949 01:21:48.341369 DramcWriteLeveling(PI) end<-----
7950 01:21:48.341880
7951 01:21:48.342215 ==
7952 01:21:48.344514 Dram Type= 6, Freq= 0, CH_0, rank 1
7953 01:21:48.351440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7954 01:21:48.351861 ==
7955 01:21:48.352240 [Gating] SW mode calibration
7956 01:21:48.361016 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7957 01:21:48.364241 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7958 01:21:48.371334 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7959 01:21:48.374276 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7960 01:21:48.377597 1 4 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
7961 01:21:48.384251 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
7962 01:21:48.387392 1 4 16 | B1->B0 | 2626 3434 | 1 1 | (0 0) (1 1)
7963 01:21:48.390701 1 4 20 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
7964 01:21:48.397321 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7965 01:21:48.400372 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7966 01:21:48.403867 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7967 01:21:48.410726 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7968 01:21:48.413922 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7969 01:21:48.416839 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7970 01:21:48.423727 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7971 01:21:48.426886 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
7972 01:21:48.430841 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7973 01:21:48.436573 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7974 01:21:48.440261 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7975 01:21:48.443493 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7976 01:21:48.450148 1 6 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
7977 01:21:48.453554 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7978 01:21:48.456581 1 6 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
7979 01:21:48.463218 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7980 01:21:48.466232 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7981 01:21:48.470040 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7982 01:21:48.476553 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7983 01:21:48.480198 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7984 01:21:48.482814 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7985 01:21:48.489790 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7986 01:21:48.492793 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7987 01:21:48.496241 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7988 01:21:48.503028 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 01:21:48.506863 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 01:21:48.509290 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 01:21:48.515748 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 01:21:48.519176 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 01:21:48.522704 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 01:21:48.529164 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 01:21:48.532747 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 01:21:48.535581 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 01:21:48.542441 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 01:21:48.545727 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 01:21:48.548991 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 01:21:48.555475 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8001 01:21:48.556070 Total UI for P1: 0, mck2ui 16
8002 01:21:48.562233 best dqsien dly found for B0: ( 1, 9, 6)
8003 01:21:48.565050 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8004 01:21:48.569114 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8005 01:21:48.575325 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8006 01:21:48.578485 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 01:21:48.581761 Total UI for P1: 0, mck2ui 16
8008 01:21:48.585200 best dqsien dly found for B1: ( 1, 9, 18)
8009 01:21:48.588836 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8010 01:21:48.591744 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8011 01:21:48.592325
8012 01:21:48.594644 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8013 01:21:48.598101 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8014 01:21:48.601600 [Gating] SW calibration Done
8015 01:21:48.602021 ==
8016 01:21:48.604600 Dram Type= 6, Freq= 0, CH_0, rank 1
8017 01:21:48.608261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8018 01:21:48.611454 ==
8019 01:21:48.611925 RX Vref Scan: 0
8020 01:21:48.612276
8021 01:21:48.614884 RX Vref 0 -> 0, step: 1
8022 01:21:48.615301
8023 01:21:48.615633 RX Delay 0 -> 252, step: 8
8024 01:21:48.621284 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8025 01:21:48.624716 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8026 01:21:48.628049 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8027 01:21:48.631232 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8028 01:21:48.637789 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8029 01:21:48.640838 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8030 01:21:48.644536 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8031 01:21:48.647190 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8032 01:21:48.650736 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8033 01:21:48.657522 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8034 01:21:48.660667 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8035 01:21:48.664044 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8036 01:21:48.667377 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8037 01:21:48.670528 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8038 01:21:48.677796 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8039 01:21:48.680749 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8040 01:21:48.681018 ==
8041 01:21:48.683488 Dram Type= 6, Freq= 0, CH_0, rank 1
8042 01:21:48.687084 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8043 01:21:48.687311 ==
8044 01:21:48.689944 DQS Delay:
8045 01:21:48.690167 DQS0 = 0, DQS1 = 0
8046 01:21:48.693408 DQM Delay:
8047 01:21:48.693630 DQM0 = 131, DQM1 = 127
8048 01:21:48.693807 DQ Delay:
8049 01:21:48.696624 DQ0 =127, DQ1 =135, DQ2 =127, DQ3 =127
8050 01:21:48.704179 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =143
8051 01:21:48.707239 DQ8 =119, DQ9 =111, DQ10 =131, DQ11 =119
8052 01:21:48.710358 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8053 01:21:48.710712
8054 01:21:48.710994
8055 01:21:48.711257 ==
8056 01:21:48.713336 Dram Type= 6, Freq= 0, CH_0, rank 1
8057 01:21:48.716398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8058 01:21:48.716927 ==
8059 01:21:48.717264
8060 01:21:48.717572
8061 01:21:48.720041 TX Vref Scan disable
8062 01:21:48.723301 == TX Byte 0 ==
8063 01:21:48.727174 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8064 01:21:48.730533 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8065 01:21:48.733453 == TX Byte 1 ==
8066 01:21:48.736517 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8067 01:21:48.740000 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8068 01:21:48.740424 ==
8069 01:21:48.743315 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 01:21:48.749907 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 01:21:48.750474 ==
8072 01:21:48.762320
8073 01:21:48.765491 TX Vref early break, caculate TX vref
8074 01:21:48.768844 TX Vref=16, minBit 0, minWin=22, winSum=378
8075 01:21:48.772441 TX Vref=18, minBit 8, minWin=23, winSum=389
8076 01:21:48.775261 TX Vref=20, minBit 2, minWin=24, winSum=399
8077 01:21:48.778661 TX Vref=22, minBit 4, minWin=24, winSum=405
8078 01:21:48.782032 TX Vref=24, minBit 1, minWin=25, winSum=414
8079 01:21:48.788858 TX Vref=26, minBit 1, minWin=25, winSum=421
8080 01:21:48.791788 TX Vref=28, minBit 4, minWin=25, winSum=418
8081 01:21:48.795329 TX Vref=30, minBit 8, minWin=25, winSum=416
8082 01:21:48.798351 TX Vref=32, minBit 1, minWin=24, winSum=407
8083 01:21:48.801391 TX Vref=34, minBit 0, minWin=24, winSum=397
8084 01:21:48.808336 [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 26
8085 01:21:48.808875
8086 01:21:48.811469 Final TX Range 0 Vref 26
8087 01:21:48.811977
8088 01:21:48.812359 ==
8089 01:21:48.814425 Dram Type= 6, Freq= 0, CH_0, rank 1
8090 01:21:48.818015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8091 01:21:48.818545 ==
8092 01:21:48.818885
8093 01:21:48.819197
8094 01:21:48.821215 TX Vref Scan disable
8095 01:21:48.827799 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8096 01:21:48.828266 == TX Byte 0 ==
8097 01:21:48.831164 u2DelayCellOfst[0]=10 cells (3 PI)
8098 01:21:48.834477 u2DelayCellOfst[1]=14 cells (4 PI)
8099 01:21:48.837677 u2DelayCellOfst[2]=7 cells (2 PI)
8100 01:21:48.840902 u2DelayCellOfst[3]=10 cells (3 PI)
8101 01:21:48.844124 u2DelayCellOfst[4]=7 cells (2 PI)
8102 01:21:48.847305 u2DelayCellOfst[5]=0 cells (0 PI)
8103 01:21:48.850712 u2DelayCellOfst[6]=14 cells (4 PI)
8104 01:21:48.854640 u2DelayCellOfst[7]=14 cells (4 PI)
8105 01:21:48.857101 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8106 01:21:48.860805 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8107 01:21:48.864046 == TX Byte 1 ==
8108 01:21:48.867277 u2DelayCellOfst[8]=0 cells (0 PI)
8109 01:21:48.870231 u2DelayCellOfst[9]=0 cells (0 PI)
8110 01:21:48.873419 u2DelayCellOfst[10]=3 cells (1 PI)
8111 01:21:48.876754 u2DelayCellOfst[11]=3 cells (1 PI)
8112 01:21:48.880055 u2DelayCellOfst[12]=10 cells (3 PI)
8113 01:21:48.883655 u2DelayCellOfst[13]=10 cells (3 PI)
8114 01:21:48.887259 u2DelayCellOfst[14]=17 cells (5 PI)
8115 01:21:48.890560 u2DelayCellOfst[15]=14 cells (4 PI)
8116 01:21:48.893178 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8117 01:21:48.897288 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8118 01:21:48.899674 DramC Write-DBI on
8119 01:21:48.900182 ==
8120 01:21:48.903276 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 01:21:48.906493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 01:21:48.906919 ==
8123 01:21:48.907253
8124 01:21:48.907564
8125 01:21:48.909474 TX Vref Scan disable
8126 01:21:48.912740 == TX Byte 0 ==
8127 01:21:48.916410 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8128 01:21:48.916829 == TX Byte 1 ==
8129 01:21:48.922998 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8130 01:21:48.923546 DramC Write-DBI off
8131 01:21:48.923922
8132 01:21:48.924249 [DATLAT]
8133 01:21:48.926357 Freq=1600, CH0 RK1
8134 01:21:48.926996
8135 01:21:48.929201 DATLAT Default: 0xf
8136 01:21:48.929652 0, 0xFFFF, sum = 0
8137 01:21:48.932627 1, 0xFFFF, sum = 0
8138 01:21:48.933164 2, 0xFFFF, sum = 0
8139 01:21:48.936317 3, 0xFFFF, sum = 0
8140 01:21:48.936745 4, 0xFFFF, sum = 0
8141 01:21:48.939934 5, 0xFFFF, sum = 0
8142 01:21:48.940441 6, 0xFFFF, sum = 0
8143 01:21:48.943268 7, 0xFFFF, sum = 0
8144 01:21:48.943795 8, 0xFFFF, sum = 0
8145 01:21:48.945911 9, 0xFFFF, sum = 0
8146 01:21:48.946474 10, 0xFFFF, sum = 0
8147 01:21:48.949060 11, 0xFFFF, sum = 0
8148 01:21:48.949487 12, 0xFFFF, sum = 0
8149 01:21:48.952502 13, 0xFFFF, sum = 0
8150 01:21:48.953048 14, 0x0, sum = 1
8151 01:21:48.955795 15, 0x0, sum = 2
8152 01:21:48.956266 16, 0x0, sum = 3
8153 01:21:48.958902 17, 0x0, sum = 4
8154 01:21:48.959328 best_step = 15
8155 01:21:48.959799
8156 01:21:48.960167 ==
8157 01:21:48.962343 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 01:21:48.968843 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 01:21:48.969264 ==
8160 01:21:48.969749 RX Vref Scan: 0
8161 01:21:48.970081
8162 01:21:48.971854 RX Vref 0 -> 0, step: 1
8163 01:21:48.972304
8164 01:21:48.975522 RX Delay 11 -> 252, step: 4
8165 01:21:48.979034 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8166 01:21:48.981720 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8167 01:21:48.988772 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8168 01:21:48.991639 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8169 01:21:48.995486 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8170 01:21:48.998251 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8171 01:21:49.001970 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8172 01:21:49.008110 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8173 01:21:49.011315 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8174 01:21:49.014845 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8175 01:21:49.018066 iDelay=191, Bit 10, Center 126 (71 ~ 182) 112
8176 01:21:49.025042 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8177 01:21:49.028154 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8178 01:21:49.031116 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8179 01:21:49.034172 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8180 01:21:49.041055 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8181 01:21:49.041516 ==
8182 01:21:49.044228 Dram Type= 6, Freq= 0, CH_0, rank 1
8183 01:21:49.047740 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8184 01:21:49.048317 ==
8185 01:21:49.048664 DQS Delay:
8186 01:21:49.050580 DQS0 = 0, DQS1 = 0
8187 01:21:49.051031 DQM Delay:
8188 01:21:49.054478 DQM0 = 128, DQM1 = 124
8189 01:21:49.054991 DQ Delay:
8190 01:21:49.057217 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8191 01:21:49.060536 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =134
8192 01:21:49.064260 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8193 01:21:49.067392 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =132
8194 01:21:49.067864
8195 01:21:49.070958
8196 01:21:49.071523
8197 01:21:49.071867 [DramC_TX_OE_Calibration] TA2
8198 01:21:49.073530 Original DQ_B0 (3 6) =30, OEN = 27
8199 01:21:49.077118 Original DQ_B1 (3 6) =30, OEN = 27
8200 01:21:49.080385 24, 0x0, End_B0=24 End_B1=24
8201 01:21:49.083581 25, 0x0, End_B0=25 End_B1=25
8202 01:21:49.086711 26, 0x0, End_B0=26 End_B1=26
8203 01:21:49.087169 27, 0x0, End_B0=27 End_B1=27
8204 01:21:49.090157 28, 0x0, End_B0=28 End_B1=28
8205 01:21:49.093946 29, 0x0, End_B0=29 End_B1=29
8206 01:21:49.096773 30, 0x0, End_B0=30 End_B1=30
8207 01:21:49.100202 31, 0x4141, End_B0=30 End_B1=30
8208 01:21:49.100669 Byte0 end_step=30 best_step=27
8209 01:21:49.103298 Byte1 end_step=30 best_step=27
8210 01:21:49.106672 Byte0 TX OE(2T, 0.5T) = (3, 3)
8211 01:21:49.109705 Byte1 TX OE(2T, 0.5T) = (3, 3)
8212 01:21:49.110125
8213 01:21:49.110457
8214 01:21:49.119478 [DQSOSCAuto] RK1, (LSB)MR18= 0xf0d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 402 ps
8215 01:21:49.119968 CH0 RK1: MR19=303, MR18=F0D
8216 01:21:49.126278 CH0_RK1: MR19=0x303, MR18=0xF0D, DQSOSC=402, MR23=63, INC=22, DEC=15
8217 01:21:49.129988 [RxdqsGatingPostProcess] freq 1600
8218 01:21:49.136392 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8219 01:21:49.140005 best DQS0 dly(2T, 0.5T) = (1, 1)
8220 01:21:49.142984 best DQS1 dly(2T, 0.5T) = (1, 1)
8221 01:21:49.146320 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8222 01:21:49.149227 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8223 01:21:49.149647 best DQS0 dly(2T, 0.5T) = (1, 1)
8224 01:21:49.152478 best DQS1 dly(2T, 0.5T) = (1, 1)
8225 01:21:49.155778 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8226 01:21:49.159249 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8227 01:21:49.162774 Pre-setting of DQS Precalculation
8228 01:21:49.168996 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8229 01:21:49.169431 ==
8230 01:21:49.172647 Dram Type= 6, Freq= 0, CH_1, rank 0
8231 01:21:49.176062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8232 01:21:49.176485 ==
8233 01:21:49.182530 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8234 01:21:49.185477 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8235 01:21:49.189046 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8236 01:21:49.195240 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8237 01:21:49.204331 [CA 0] Center 42 (12~72) winsize 61
8238 01:21:49.207505 [CA 1] Center 42 (12~72) winsize 61
8239 01:21:49.210986 [CA 2] Center 38 (9~67) winsize 59
8240 01:21:49.214272 [CA 3] Center 37 (8~66) winsize 59
8241 01:21:49.217423 [CA 4] Center 38 (8~68) winsize 61
8242 01:21:49.220928 [CA 5] Center 36 (7~66) winsize 60
8243 01:21:49.221434
8244 01:21:49.224307 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8245 01:21:49.224872
8246 01:21:49.230800 [CATrainingPosCal] consider 1 rank data
8247 01:21:49.231222 u2DelayCellTimex100 = 275/100 ps
8248 01:21:49.237379 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8249 01:21:49.240756 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8250 01:21:49.244018 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8251 01:21:49.247232 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8252 01:21:49.251002 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8253 01:21:49.253610 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8254 01:21:49.254083
8255 01:21:49.256861 CA PerBit enable=1, Macro0, CA PI delay=36
8256 01:21:49.257280
8257 01:21:49.260316 [CBTSetCACLKResult] CA Dly = 36
8258 01:21:49.263690 CS Dly: 8 (0~39)
8259 01:21:49.266590 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8260 01:21:49.269869 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8261 01:21:49.270427 ==
8262 01:21:49.273611 Dram Type= 6, Freq= 0, CH_1, rank 1
8263 01:21:49.280124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8264 01:21:49.280817 ==
8265 01:21:49.283227 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8266 01:21:49.289990 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8267 01:21:49.293758 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8268 01:21:49.299961 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8269 01:21:49.307817 [CA 0] Center 42 (12~72) winsize 61
8270 01:21:49.310638 [CA 1] Center 43 (14~72) winsize 59
8271 01:21:49.314099 [CA 2] Center 38 (9~67) winsize 59
8272 01:21:49.317990 [CA 3] Center 36 (7~66) winsize 60
8273 01:21:49.320508 [CA 4] Center 37 (8~67) winsize 60
8274 01:21:49.323714 [CA 5] Center 36 (7~66) winsize 60
8275 01:21:49.324206
8276 01:21:49.327684 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8277 01:21:49.328245
8278 01:21:49.333851 [CATrainingPosCal] consider 2 rank data
8279 01:21:49.334268 u2DelayCellTimex100 = 275/100 ps
8280 01:21:49.340362 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8281 01:21:49.343786 CA1 delay=43 (14~72),Diff = 7 PI (24 cell)
8282 01:21:49.347191 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8283 01:21:49.350630 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8284 01:21:49.353965 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8285 01:21:49.357272 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8286 01:21:49.357832
8287 01:21:49.360374 CA PerBit enable=1, Macro0, CA PI delay=36
8288 01:21:49.360949
8289 01:21:49.363575 [CBTSetCACLKResult] CA Dly = 36
8290 01:21:49.366996 CS Dly: 10 (0~43)
8291 01:21:49.370077 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8292 01:21:49.373265 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8293 01:21:49.373684
8294 01:21:49.377822 ----->DramcWriteLeveling(PI) begin...
8295 01:21:49.378343 ==
8296 01:21:49.380386 Dram Type= 6, Freq= 0, CH_1, rank 0
8297 01:21:49.386785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8298 01:21:49.387303 ==
8299 01:21:49.389873 Write leveling (Byte 0): 22 => 22
8300 01:21:49.393298 Write leveling (Byte 1): 26 => 26
8301 01:21:49.396579 DramcWriteLeveling(PI) end<-----
8302 01:21:49.397135
8303 01:21:49.397507 ==
8304 01:21:49.399733 Dram Type= 6, Freq= 0, CH_1, rank 0
8305 01:21:49.403287 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 01:21:49.403757 ==
8307 01:21:49.406234 [Gating] SW mode calibration
8308 01:21:49.412706 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8309 01:21:49.419986 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8310 01:21:49.422492 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8311 01:21:49.426229 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8312 01:21:49.432468 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8313 01:21:49.435848 1 4 12 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
8314 01:21:49.439213 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8315 01:21:49.445700 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8316 01:21:49.449663 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8317 01:21:49.452334 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8318 01:21:49.459432 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8319 01:21:49.462502 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8320 01:21:49.465714 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8321 01:21:49.472823 1 5 12 | B1->B0 | 3434 2424 | 0 0 | (0 0) (1 0)
8322 01:21:49.475402 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8323 01:21:49.478646 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 01:21:49.485468 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 01:21:49.488693 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 01:21:49.491779 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 01:21:49.498181 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 01:21:49.501275 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8329 01:21:49.504640 1 6 12 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
8330 01:21:49.511412 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8331 01:21:49.514568 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8332 01:21:49.518570 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8333 01:21:49.525441 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8334 01:21:49.528153 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8335 01:21:49.531242 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8336 01:21:49.538146 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 01:21:49.541281 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8338 01:21:49.544436 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8339 01:21:49.550956 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8340 01:21:49.554374 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 01:21:49.557342 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 01:21:49.564115 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 01:21:49.567172 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 01:21:49.570521 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 01:21:49.577401 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 01:21:49.580840 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 01:21:49.583839 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 01:21:49.590285 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 01:21:49.594500 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 01:21:49.597056 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 01:21:49.604204 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 01:21:49.606820 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8353 01:21:49.610345 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8354 01:21:49.613180 Total UI for P1: 0, mck2ui 16
8355 01:21:49.616539 best dqsien dly found for B0: ( 1, 9, 8)
8356 01:21:49.623345 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8357 01:21:49.626524 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8358 01:21:49.629674 Total UI for P1: 0, mck2ui 16
8359 01:21:49.633367 best dqsien dly found for B1: ( 1, 9, 14)
8360 01:21:49.636431 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8361 01:21:49.639815 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8362 01:21:49.640399
8363 01:21:49.642952 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8364 01:21:49.646517 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8365 01:21:49.649538 [Gating] SW calibration Done
8366 01:21:49.649953 ==
8367 01:21:49.652905 Dram Type= 6, Freq= 0, CH_1, rank 0
8368 01:21:49.659398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8369 01:21:49.659970 ==
8370 01:21:49.660319 RX Vref Scan: 0
8371 01:21:49.660687
8372 01:21:49.662713 RX Vref 0 -> 0, step: 1
8373 01:21:49.663135
8374 01:21:49.665725 RX Delay 0 -> 252, step: 8
8375 01:21:49.669420 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8376 01:21:49.672785 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8377 01:21:49.675689 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8378 01:21:49.679228 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8379 01:21:49.685988 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8380 01:21:49.688918 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8381 01:21:49.692307 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8382 01:21:49.695996 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8383 01:21:49.698794 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8384 01:21:49.705547 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8385 01:21:49.708771 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8386 01:21:49.711986 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8387 01:21:49.715856 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8388 01:21:49.722201 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8389 01:21:49.725252 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8390 01:21:49.728458 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8391 01:21:49.728981 ==
8392 01:21:49.731611 Dram Type= 6, Freq= 0, CH_1, rank 0
8393 01:21:49.735010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8394 01:21:49.738878 ==
8395 01:21:49.739395 DQS Delay:
8396 01:21:49.739742 DQS0 = 0, DQS1 = 0
8397 01:21:49.741932 DQM Delay:
8398 01:21:49.742445 DQM0 = 135, DQM1 = 129
8399 01:21:49.744960 DQ Delay:
8400 01:21:49.748427 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8401 01:21:49.751881 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =127
8402 01:21:49.754818 DQ8 =111, DQ9 =119, DQ10 =127, DQ11 =123
8403 01:21:49.758089 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8404 01:21:49.758609
8405 01:21:49.758947
8406 01:21:49.759259 ==
8407 01:21:49.761720 Dram Type= 6, Freq= 0, CH_1, rank 0
8408 01:21:49.764789 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8409 01:21:49.767850 ==
8410 01:21:49.768336
8411 01:21:49.768672
8412 01:21:49.768984 TX Vref Scan disable
8413 01:21:49.770963 == TX Byte 0 ==
8414 01:21:49.774189 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8415 01:21:49.778247 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8416 01:21:49.781170 == TX Byte 1 ==
8417 01:21:49.784454 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8418 01:21:49.787495 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8419 01:21:49.791049 ==
8420 01:21:49.794208 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 01:21:49.797125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 01:21:49.797708 ==
8423 01:21:49.809663
8424 01:21:49.813045 TX Vref early break, caculate TX vref
8425 01:21:49.816283 TX Vref=16, minBit 8, minWin=21, winSum=366
8426 01:21:49.820003 TX Vref=18, minBit 8, minWin=21, winSum=375
8427 01:21:49.822743 TX Vref=20, minBit 8, minWin=23, winSum=387
8428 01:21:49.826165 TX Vref=22, minBit 8, minWin=23, winSum=398
8429 01:21:49.829642 TX Vref=24, minBit 1, minWin=24, winSum=405
8430 01:21:49.836272 TX Vref=26, minBit 8, minWin=24, winSum=415
8431 01:21:49.839264 TX Vref=28, minBit 10, minWin=25, winSum=420
8432 01:21:49.843058 TX Vref=30, minBit 9, minWin=24, winSum=422
8433 01:21:49.845671 TX Vref=32, minBit 0, minWin=24, winSum=406
8434 01:21:49.849472 TX Vref=34, minBit 15, minWin=23, winSum=399
8435 01:21:49.855746 [TxChooseVref] Worse bit 10, Min win 25, Win sum 420, Final Vref 28
8436 01:21:49.856331
8437 01:21:49.858976 Final TX Range 0 Vref 28
8438 01:21:49.859428
8439 01:21:49.859841 ==
8440 01:21:49.862315 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 01:21:49.865865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 01:21:49.866371 ==
8443 01:21:49.866699
8444 01:21:49.869207
8445 01:21:49.869616 TX Vref Scan disable
8446 01:21:49.875786 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8447 01:21:49.876333 == TX Byte 0 ==
8448 01:21:49.879143 u2DelayCellOfst[0]=17 cells (5 PI)
8449 01:21:49.882017 u2DelayCellOfst[1]=14 cells (4 PI)
8450 01:21:49.885415 u2DelayCellOfst[2]=0 cells (0 PI)
8451 01:21:49.888337 u2DelayCellOfst[3]=7 cells (2 PI)
8452 01:21:49.891931 u2DelayCellOfst[4]=10 cells (3 PI)
8453 01:21:49.895811 u2DelayCellOfst[5]=17 cells (5 PI)
8454 01:21:49.898316 u2DelayCellOfst[6]=17 cells (5 PI)
8455 01:21:49.902011 u2DelayCellOfst[7]=7 cells (2 PI)
8456 01:21:49.905505 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8457 01:21:49.908420 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8458 01:21:49.911628 == TX Byte 1 ==
8459 01:21:49.915357 u2DelayCellOfst[8]=0 cells (0 PI)
8460 01:21:49.918549 u2DelayCellOfst[9]=3 cells (1 PI)
8461 01:21:49.921561 u2DelayCellOfst[10]=14 cells (4 PI)
8462 01:21:49.924984 u2DelayCellOfst[11]=3 cells (1 PI)
8463 01:21:49.928287 u2DelayCellOfst[12]=14 cells (4 PI)
8464 01:21:49.931722 u2DelayCellOfst[13]=17 cells (5 PI)
8465 01:21:49.932183 u2DelayCellOfst[14]=17 cells (5 PI)
8466 01:21:49.934686 u2DelayCellOfst[15]=17 cells (5 PI)
8467 01:21:49.941189 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8468 01:21:49.944788 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8469 01:21:49.947806 DramC Write-DBI on
8470 01:21:49.948450 ==
8471 01:21:49.950973 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 01:21:49.954221 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 01:21:49.954649 ==
8474 01:21:49.954987
8475 01:21:49.955298
8476 01:21:49.957916 TX Vref Scan disable
8477 01:21:49.958339 == TX Byte 0 ==
8478 01:21:49.964034 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8479 01:21:49.964546 == TX Byte 1 ==
8480 01:21:49.967755 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8481 01:21:49.970690 DramC Write-DBI off
8482 01:21:49.971208
8483 01:21:49.971550 [DATLAT]
8484 01:21:49.973938 Freq=1600, CH1 RK0
8485 01:21:49.974512
8486 01:21:49.974864 DATLAT Default: 0xf
8487 01:21:49.977243 0, 0xFFFF, sum = 0
8488 01:21:49.980793 1, 0xFFFF, sum = 0
8489 01:21:49.981309 2, 0xFFFF, sum = 0
8490 01:21:49.983920 3, 0xFFFF, sum = 0
8491 01:21:49.984401 4, 0xFFFF, sum = 0
8492 01:21:49.987477 5, 0xFFFF, sum = 0
8493 01:21:49.987962 6, 0xFFFF, sum = 0
8494 01:21:49.990789 7, 0xFFFF, sum = 0
8495 01:21:49.991217 8, 0xFFFF, sum = 0
8496 01:21:49.993669 9, 0xFFFF, sum = 0
8497 01:21:49.994192 10, 0xFFFF, sum = 0
8498 01:21:49.997189 11, 0xFFFF, sum = 0
8499 01:21:49.997619 12, 0xFFFF, sum = 0
8500 01:21:50.000544 13, 0xFFFF, sum = 0
8501 01:21:50.001000 14, 0x0, sum = 1
8502 01:21:50.003780 15, 0x0, sum = 2
8503 01:21:50.004332 16, 0x0, sum = 3
8504 01:21:50.007123 17, 0x0, sum = 4
8505 01:21:50.007630 best_step = 15
8506 01:21:50.008011
8507 01:21:50.008332 ==
8508 01:21:50.010543 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 01:21:50.016866 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 01:21:50.017297 ==
8511 01:21:50.017632 RX Vref Scan: 1
8512 01:21:50.017945
8513 01:21:50.019922 Set Vref Range= 24 -> 127
8514 01:21:50.020363
8515 01:21:50.024020 RX Vref 24 -> 127, step: 1
8516 01:21:50.024499
8517 01:21:50.027103 RX Delay 11 -> 252, step: 4
8518 01:21:50.027627
8519 01:21:50.030294 Set Vref, RX VrefLevel [Byte0]: 24
8520 01:21:50.033677 [Byte1]: 24
8521 01:21:50.034204
8522 01:21:50.037374 Set Vref, RX VrefLevel [Byte0]: 25
8523 01:21:50.039915 [Byte1]: 25
8524 01:21:50.040346
8525 01:21:50.043363 Set Vref, RX VrefLevel [Byte0]: 26
8526 01:21:50.046422 [Byte1]: 26
8527 01:21:50.049635
8528 01:21:50.050057 Set Vref, RX VrefLevel [Byte0]: 27
8529 01:21:50.052809 [Byte1]: 27
8530 01:21:50.057443
8531 01:21:50.057865 Set Vref, RX VrefLevel [Byte0]: 28
8532 01:21:50.060885 [Byte1]: 28
8533 01:21:50.065103
8534 01:21:50.065591 Set Vref, RX VrefLevel [Byte0]: 29
8535 01:21:50.068001 [Byte1]: 29
8536 01:21:50.072403
8537 01:21:50.072870 Set Vref, RX VrefLevel [Byte0]: 30
8538 01:21:50.075969 [Byte1]: 30
8539 01:21:50.080219
8540 01:21:50.080779 Set Vref, RX VrefLevel [Byte0]: 31
8541 01:21:50.083362 [Byte1]: 31
8542 01:21:50.087856
8543 01:21:50.088325 Set Vref, RX VrefLevel [Byte0]: 32
8544 01:21:50.090994 [Byte1]: 32
8545 01:21:50.095475
8546 01:21:50.096151 Set Vref, RX VrefLevel [Byte0]: 33
8547 01:21:50.098601 [Byte1]: 33
8548 01:21:50.102843
8549 01:21:50.103347 Set Vref, RX VrefLevel [Byte0]: 34
8550 01:21:50.106351 [Byte1]: 34
8551 01:21:50.110686
8552 01:21:50.111107 Set Vref, RX VrefLevel [Byte0]: 35
8553 01:21:50.113983 [Byte1]: 35
8554 01:21:50.117861
8555 01:21:50.118274 Set Vref, RX VrefLevel [Byte0]: 36
8556 01:21:50.121356 [Byte1]: 36
8557 01:21:50.125927
8558 01:21:50.126461 Set Vref, RX VrefLevel [Byte0]: 37
8559 01:21:50.129138 [Byte1]: 37
8560 01:21:50.133505
8561 01:21:50.134038 Set Vref, RX VrefLevel [Byte0]: 38
8562 01:21:50.136873 [Byte1]: 38
8563 01:21:50.141399
8564 01:21:50.141810 Set Vref, RX VrefLevel [Byte0]: 39
8565 01:21:50.144146 [Byte1]: 39
8566 01:21:50.148568
8567 01:21:50.148981 Set Vref, RX VrefLevel [Byte0]: 40
8568 01:21:50.152162 [Byte1]: 40
8569 01:21:50.156225
8570 01:21:50.156641 Set Vref, RX VrefLevel [Byte0]: 41
8571 01:21:50.159614 [Byte1]: 41
8572 01:21:50.164378
8573 01:21:50.164884 Set Vref, RX VrefLevel [Byte0]: 42
8574 01:21:50.167291 [Byte1]: 42
8575 01:21:50.171645
8576 01:21:50.172126 Set Vref, RX VrefLevel [Byte0]: 43
8577 01:21:50.174872 [Byte1]: 43
8578 01:21:50.179418
8579 01:21:50.180054 Set Vref, RX VrefLevel [Byte0]: 44
8580 01:21:50.182800 [Byte1]: 44
8581 01:21:50.187033
8582 01:21:50.187560 Set Vref, RX VrefLevel [Byte0]: 45
8583 01:21:50.190071 [Byte1]: 45
8584 01:21:50.194348
8585 01:21:50.194774 Set Vref, RX VrefLevel [Byte0]: 46
8586 01:21:50.197558 [Byte1]: 46
8587 01:21:50.201718
8588 01:21:50.202140 Set Vref, RX VrefLevel [Byte0]: 47
8589 01:21:50.205178 [Byte1]: 47
8590 01:21:50.209715
8591 01:21:50.210150 Set Vref, RX VrefLevel [Byte0]: 48
8592 01:21:50.213257 [Byte1]: 48
8593 01:21:50.217601
8594 01:21:50.218024 Set Vref, RX VrefLevel [Byte0]: 49
8595 01:21:50.220435 [Byte1]: 49
8596 01:21:50.225000
8597 01:21:50.225421 Set Vref, RX VrefLevel [Byte0]: 50
8598 01:21:50.228014 [Byte1]: 50
8599 01:21:50.232900
8600 01:21:50.233394 Set Vref, RX VrefLevel [Byte0]: 51
8601 01:21:50.235685 [Byte1]: 51
8602 01:21:50.240197
8603 01:21:50.240617 Set Vref, RX VrefLevel [Byte0]: 52
8604 01:21:50.243234 [Byte1]: 52
8605 01:21:50.247539
8606 01:21:50.248123 Set Vref, RX VrefLevel [Byte0]: 53
8607 01:21:50.251045 [Byte1]: 53
8608 01:21:50.255204
8609 01:21:50.255707 Set Vref, RX VrefLevel [Byte0]: 54
8610 01:21:50.258890 [Byte1]: 54
8611 01:21:50.262804
8612 01:21:50.263223 Set Vref, RX VrefLevel [Byte0]: 55
8613 01:21:50.266017 [Byte1]: 55
8614 01:21:50.270845
8615 01:21:50.271264 Set Vref, RX VrefLevel [Byte0]: 56
8616 01:21:50.274076 [Byte1]: 56
8617 01:21:50.278165
8618 01:21:50.278680 Set Vref, RX VrefLevel [Byte0]: 57
8619 01:21:50.281914 [Byte1]: 57
8620 01:21:50.286043
8621 01:21:50.286564 Set Vref, RX VrefLevel [Byte0]: 58
8622 01:21:50.289264 [Byte1]: 58
8623 01:21:50.293780
8624 01:21:50.294204 Set Vref, RX VrefLevel [Byte0]: 59
8625 01:21:50.296424 [Byte1]: 59
8626 01:21:50.301324
8627 01:21:50.301819 Set Vref, RX VrefLevel [Byte0]: 60
8628 01:21:50.304553 [Byte1]: 60
8629 01:21:50.308836
8630 01:21:50.309413 Set Vref, RX VrefLevel [Byte0]: 61
8631 01:21:50.312183 [Byte1]: 61
8632 01:21:50.316163
8633 01:21:50.316586 Set Vref, RX VrefLevel [Byte0]: 62
8634 01:21:50.319308 [Byte1]: 62
8635 01:21:50.323728
8636 01:21:50.324276 Set Vref, RX VrefLevel [Byte0]: 63
8637 01:21:50.326981 [Byte1]: 63
8638 01:21:50.331249
8639 01:21:50.331750 Set Vref, RX VrefLevel [Byte0]: 64
8640 01:21:50.334817 [Byte1]: 64
8641 01:21:50.338880
8642 01:21:50.339301 Set Vref, RX VrefLevel [Byte0]: 65
8643 01:21:50.342082 [Byte1]: 65
8644 01:21:50.346541
8645 01:21:50.347026 Set Vref, RX VrefLevel [Byte0]: 66
8646 01:21:50.349987 [Byte1]: 66
8647 01:21:50.354319
8648 01:21:50.354739 Set Vref, RX VrefLevel [Byte0]: 67
8649 01:21:50.357511 [Byte1]: 67
8650 01:21:50.361645
8651 01:21:50.362067 Set Vref, RX VrefLevel [Byte0]: 68
8652 01:21:50.365192 [Byte1]: 68
8653 01:21:50.369645
8654 01:21:50.370068 Set Vref, RX VrefLevel [Byte0]: 69
8655 01:21:50.372316 [Byte1]: 69
8656 01:21:50.377015
8657 01:21:50.377436 Set Vref, RX VrefLevel [Byte0]: 70
8658 01:21:50.380463 [Byte1]: 70
8659 01:21:50.385072
8660 01:21:50.385589 Set Vref, RX VrefLevel [Byte0]: 71
8661 01:21:50.388054 [Byte1]: 71
8662 01:21:50.392327
8663 01:21:50.392775 Set Vref, RX VrefLevel [Byte0]: 72
8664 01:21:50.395581 [Byte1]: 72
8665 01:21:50.400023
8666 01:21:50.400450 Set Vref, RX VrefLevel [Byte0]: 73
8667 01:21:50.403238 [Byte1]: 73
8668 01:21:50.407104
8669 01:21:50.407516 Final RX Vref Byte 0 = 60 to rank0
8670 01:21:50.410747 Final RX Vref Byte 1 = 62 to rank0
8671 01:21:50.413898 Final RX Vref Byte 0 = 60 to rank1
8672 01:21:50.417349 Final RX Vref Byte 1 = 62 to rank1==
8673 01:21:50.420646 Dram Type= 6, Freq= 0, CH_1, rank 0
8674 01:21:50.426878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8675 01:21:50.427313 ==
8676 01:21:50.427647 DQS Delay:
8677 01:21:50.430391 DQS0 = 0, DQS1 = 0
8678 01:21:50.431080 DQM Delay:
8679 01:21:50.434158 DQM0 = 132, DQM1 = 128
8680 01:21:50.434578 DQ Delay:
8681 01:21:50.436719 DQ0 =138, DQ1 =130, DQ2 =118, DQ3 =130
8682 01:21:50.440179 DQ4 =130, DQ5 =142, DQ6 =146, DQ7 =126
8683 01:21:50.443723 DQ8 =112, DQ9 =118, DQ10 =128, DQ11 =120
8684 01:21:50.446649 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8685 01:21:50.447065
8686 01:21:50.447398
8687 01:21:50.447701
8688 01:21:50.450467 [DramC_TX_OE_Calibration] TA2
8689 01:21:50.453622 Original DQ_B0 (3 6) =30, OEN = 27
8690 01:21:50.456766 Original DQ_B1 (3 6) =30, OEN = 27
8691 01:21:50.460055 24, 0x0, End_B0=24 End_B1=24
8692 01:21:50.463563 25, 0x0, End_B0=25 End_B1=25
8693 01:21:50.464043 26, 0x0, End_B0=26 End_B1=26
8694 01:21:50.466429 27, 0x0, End_B0=27 End_B1=27
8695 01:21:50.469982 28, 0x0, End_B0=28 End_B1=28
8696 01:21:50.473668 29, 0x0, End_B0=29 End_B1=29
8697 01:21:50.476157 30, 0x0, End_B0=30 End_B1=30
8698 01:21:50.476642 31, 0x4141, End_B0=30 End_B1=30
8699 01:21:50.479849 Byte0 end_step=30 best_step=27
8700 01:21:50.482915 Byte1 end_step=30 best_step=27
8701 01:21:50.486486 Byte0 TX OE(2T, 0.5T) = (3, 3)
8702 01:21:50.489546 Byte1 TX OE(2T, 0.5T) = (3, 3)
8703 01:21:50.490179
8704 01:21:50.490524
8705 01:21:50.496049 [DQSOSCAuto] RK0, (LSB)MR18= 0xc16, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
8706 01:21:50.499198 CH1 RK0: MR19=303, MR18=C16
8707 01:21:50.505811 CH1_RK0: MR19=0x303, MR18=0xC16, DQSOSC=398, MR23=63, INC=23, DEC=15
8708 01:21:50.506234
8709 01:21:50.509009 ----->DramcWriteLeveling(PI) begin...
8710 01:21:50.509434 ==
8711 01:21:50.512444 Dram Type= 6, Freq= 0, CH_1, rank 1
8712 01:21:50.515822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8713 01:21:50.516269 ==
8714 01:21:50.519057 Write leveling (Byte 0): 25 => 25
8715 01:21:50.522139 Write leveling (Byte 1): 27 => 27
8716 01:21:50.525363 DramcWriteLeveling(PI) end<-----
8717 01:21:50.525783
8718 01:21:50.526116 ==
8719 01:21:50.529263 Dram Type= 6, Freq= 0, CH_1, rank 1
8720 01:21:50.535567 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8721 01:21:50.536156 ==
8722 01:21:50.536512 [Gating] SW mode calibration
8723 01:21:50.545701 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8724 01:21:50.548590 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8725 01:21:50.555123 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8726 01:21:50.558504 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8727 01:21:50.561640 1 4 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8728 01:21:50.568372 1 4 12 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
8729 01:21:50.571528 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8730 01:21:50.574768 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8731 01:21:50.581234 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8732 01:21:50.584425 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8733 01:21:50.588382 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8734 01:21:50.594717 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8735 01:21:50.597855 1 5 8 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
8736 01:21:50.601128 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (0 1) (0 0)
8737 01:21:50.608118 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8738 01:21:50.610881 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8739 01:21:50.614482 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8740 01:21:50.620827 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8741 01:21:50.623992 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8742 01:21:50.627570 1 6 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8743 01:21:50.634328 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8744 01:21:50.637580 1 6 12 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
8745 01:21:50.640996 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8746 01:21:50.647620 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8747 01:21:50.650742 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8748 01:21:50.654199 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8749 01:21:50.660691 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8750 01:21:50.663821 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8751 01:21:50.667339 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8752 01:21:50.673615 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8753 01:21:50.677054 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8754 01:21:50.680543 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8755 01:21:50.686842 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8756 01:21:50.690584 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8757 01:21:50.693558 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8758 01:21:50.700113 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8759 01:21:50.703274 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 01:21:50.706310 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 01:21:50.713025 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 01:21:50.716264 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 01:21:50.719562 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 01:21:50.726027 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 01:21:50.729578 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 01:21:50.733051 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8767 01:21:50.739561 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8768 01:21:50.743343 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8769 01:21:50.746481 Total UI for P1: 0, mck2ui 16
8770 01:21:50.749254 best dqsien dly found for B0: ( 1, 9, 6)
8771 01:21:50.752830 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8772 01:21:50.759293 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 01:21:50.759855 Total UI for P1: 0, mck2ui 16
8774 01:21:50.766500 best dqsien dly found for B1: ( 1, 9, 14)
8775 01:21:50.769476 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8776 01:21:50.772380 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8777 01:21:50.772849
8778 01:21:50.775939 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8779 01:21:50.779279 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8780 01:21:50.782314 [Gating] SW calibration Done
8781 01:21:50.782736 ==
8782 01:21:50.785492 Dram Type= 6, Freq= 0, CH_1, rank 1
8783 01:21:50.789045 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8784 01:21:50.789472 ==
8785 01:21:50.792017 RX Vref Scan: 0
8786 01:21:50.792441
8787 01:21:50.792778 RX Vref 0 -> 0, step: 1
8788 01:21:50.793155
8789 01:21:50.795571 RX Delay 0 -> 252, step: 8
8790 01:21:50.799004 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8791 01:21:50.805115 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8792 01:21:50.808981 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8793 01:21:50.811858 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8794 01:21:50.815430 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8795 01:21:50.818578 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8796 01:21:50.825233 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8797 01:21:50.828556 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8798 01:21:50.831681 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8799 01:21:50.835512 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8800 01:21:50.841373 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8801 01:21:50.844937 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8802 01:21:50.848285 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8803 01:21:50.851518 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8804 01:21:50.855198 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8805 01:21:50.861106 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8806 01:21:50.861595 ==
8807 01:21:50.864566 Dram Type= 6, Freq= 0, CH_1, rank 1
8808 01:21:50.868360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8809 01:21:50.868789 ==
8810 01:21:50.869127 DQS Delay:
8811 01:21:50.871113 DQS0 = 0, DQS1 = 0
8812 01:21:50.871649 DQM Delay:
8813 01:21:50.874991 DQM0 = 135, DQM1 = 130
8814 01:21:50.875515 DQ Delay:
8815 01:21:50.877813 DQ0 =143, DQ1 =135, DQ2 =119, DQ3 =131
8816 01:21:50.881205 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =135
8817 01:21:50.884455 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8818 01:21:50.890965 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8819 01:21:50.891525
8820 01:21:50.891916
8821 01:21:50.892264 ==
8822 01:21:50.894344 Dram Type= 6, Freq= 0, CH_1, rank 1
8823 01:21:50.897222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8824 01:21:50.897649 ==
8825 01:21:50.897986
8826 01:21:50.898298
8827 01:21:50.900985 TX Vref Scan disable
8828 01:21:50.901408 == TX Byte 0 ==
8829 01:21:50.907543 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8830 01:21:50.910945 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8831 01:21:50.911445 == TX Byte 1 ==
8832 01:21:50.917001 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8833 01:21:50.920406 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8834 01:21:50.920831 ==
8835 01:21:50.923587 Dram Type= 6, Freq= 0, CH_1, rank 1
8836 01:21:50.926825 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8837 01:21:50.927250 ==
8838 01:21:50.942084
8839 01:21:50.945546 TX Vref early break, caculate TX vref
8840 01:21:50.948874 TX Vref=16, minBit 9, minWin=21, winSum=377
8841 01:21:50.952208 TX Vref=18, minBit 9, minWin=22, winSum=382
8842 01:21:50.955434 TX Vref=20, minBit 9, minWin=22, winSum=391
8843 01:21:50.958682 TX Vref=22, minBit 9, minWin=23, winSum=401
8844 01:21:50.961770 TX Vref=24, minBit 9, minWin=23, winSum=406
8845 01:21:50.968731 TX Vref=26, minBit 9, minWin=25, winSum=416
8846 01:21:50.971385 TX Vref=28, minBit 9, minWin=25, winSum=418
8847 01:21:50.975198 TX Vref=30, minBit 9, minWin=24, winSum=418
8848 01:21:50.977884 TX Vref=32, minBit 8, minWin=24, winSum=410
8849 01:21:50.981707 TX Vref=34, minBit 5, minWin=24, winSum=402
8850 01:21:50.988225 TX Vref=36, minBit 8, minWin=23, winSum=394
8851 01:21:50.991127 [TxChooseVref] Worse bit 9, Min win 25, Win sum 418, Final Vref 28
8852 01:21:50.991597
8853 01:21:50.994375 Final TX Range 0 Vref 28
8854 01:21:50.994842
8855 01:21:50.995211 ==
8856 01:21:50.997966 Dram Type= 6, Freq= 0, CH_1, rank 1
8857 01:21:51.001296 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8858 01:21:51.004829 ==
8859 01:21:51.005251
8860 01:21:51.005587
8861 01:21:51.005901 TX Vref Scan disable
8862 01:21:51.011202 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8863 01:21:51.011625 == TX Byte 0 ==
8864 01:21:51.014811 u2DelayCellOfst[0]=14 cells (4 PI)
8865 01:21:51.018159 u2DelayCellOfst[1]=10 cells (3 PI)
8866 01:21:51.021303 u2DelayCellOfst[2]=0 cells (0 PI)
8867 01:21:51.024881 u2DelayCellOfst[3]=7 cells (2 PI)
8868 01:21:51.027971 u2DelayCellOfst[4]=7 cells (2 PI)
8869 01:21:51.031096 u2DelayCellOfst[5]=14 cells (4 PI)
8870 01:21:51.034806 u2DelayCellOfst[6]=17 cells (5 PI)
8871 01:21:51.038512 u2DelayCellOfst[7]=7 cells (2 PI)
8872 01:21:51.041279 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8873 01:21:51.044078 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8874 01:21:51.047782 == TX Byte 1 ==
8875 01:21:51.050730 u2DelayCellOfst[8]=0 cells (0 PI)
8876 01:21:51.054575 u2DelayCellOfst[9]=3 cells (1 PI)
8877 01:21:51.057651 u2DelayCellOfst[10]=10 cells (3 PI)
8878 01:21:51.060734 u2DelayCellOfst[11]=7 cells (2 PI)
8879 01:21:51.064218 u2DelayCellOfst[12]=17 cells (5 PI)
8880 01:21:51.067047 u2DelayCellOfst[13]=17 cells (5 PI)
8881 01:21:51.070563 u2DelayCellOfst[14]=17 cells (5 PI)
8882 01:21:51.071008 u2DelayCellOfst[15]=17 cells (5 PI)
8883 01:21:51.077220 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8884 01:21:51.080529 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8885 01:21:51.083991 DramC Write-DBI on
8886 01:21:51.084521 ==
8887 01:21:51.087534 Dram Type= 6, Freq= 0, CH_1, rank 1
8888 01:21:51.090454 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8889 01:21:51.091023 ==
8890 01:21:51.091397
8891 01:21:51.091740
8892 01:21:51.093737 TX Vref Scan disable
8893 01:21:51.094200 == TX Byte 0 ==
8894 01:21:51.100452 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8895 01:21:51.101010 == TX Byte 1 ==
8896 01:21:51.104115 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8897 01:21:51.106718 DramC Write-DBI off
8898 01:21:51.107184
8899 01:21:51.107552 [DATLAT]
8900 01:21:51.109969 Freq=1600, CH1 RK1
8901 01:21:51.110435
8902 01:21:51.110806 DATLAT Default: 0xf
8903 01:21:51.113787 0, 0xFFFF, sum = 0
8904 01:21:51.117096 1, 0xFFFF, sum = 0
8905 01:21:51.117695 2, 0xFFFF, sum = 0
8906 01:21:51.120425 3, 0xFFFF, sum = 0
8907 01:21:51.120913 4, 0xFFFF, sum = 0
8908 01:21:51.123535 5, 0xFFFF, sum = 0
8909 01:21:51.123989 6, 0xFFFF, sum = 0
8910 01:21:51.126791 7, 0xFFFF, sum = 0
8911 01:21:51.127315 8, 0xFFFF, sum = 0
8912 01:21:51.130661 9, 0xFFFF, sum = 0
8913 01:21:51.131234 10, 0xFFFF, sum = 0
8914 01:21:51.133238 11, 0xFFFF, sum = 0
8915 01:21:51.133708 12, 0xFFFF, sum = 0
8916 01:21:51.136743 13, 0xFFFF, sum = 0
8917 01:21:51.137216 14, 0x0, sum = 1
8918 01:21:51.139775 15, 0x0, sum = 2
8919 01:21:51.140302 16, 0x0, sum = 3
8920 01:21:51.142753 17, 0x0, sum = 4
8921 01:21:51.143177 best_step = 15
8922 01:21:51.143505
8923 01:21:51.143812 ==
8924 01:21:51.146535 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 01:21:51.153181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 01:21:51.153604 ==
8927 01:21:51.153938 RX Vref Scan: 0
8928 01:21:51.154246
8929 01:21:51.156207 RX Vref 0 -> 0, step: 1
8930 01:21:51.156717
8931 01:21:51.159618 RX Delay 19 -> 252, step: 4
8932 01:21:51.162848 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8933 01:21:51.166810 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8934 01:21:51.169458 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8935 01:21:51.175820 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8936 01:21:51.179311 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8937 01:21:51.182862 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8938 01:21:51.185910 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8939 01:21:51.189342 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8940 01:21:51.195992 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8941 01:21:51.199148 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8942 01:21:51.202178 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8943 01:21:51.205422 iDelay=195, Bit 11, Center 122 (71 ~ 174) 104
8944 01:21:51.212026 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8945 01:21:51.215484 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8946 01:21:51.219061 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8947 01:21:51.222361 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8948 01:21:51.222828 ==
8949 01:21:51.225684 Dram Type= 6, Freq= 0, CH_1, rank 1
8950 01:21:51.232127 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8951 01:21:51.232571 ==
8952 01:21:51.232907 DQS Delay:
8953 01:21:51.235598 DQS0 = 0, DQS1 = 0
8954 01:21:51.236160 DQM Delay:
8955 01:21:51.238621 DQM0 = 134, DQM1 = 128
8956 01:21:51.239193 DQ Delay:
8957 01:21:51.241950 DQ0 =136, DQ1 =132, DQ2 =122, DQ3 =132
8958 01:21:51.244928 DQ4 =132, DQ5 =146, DQ6 =142, DQ7 =130
8959 01:21:51.247950 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =122
8960 01:21:51.251806 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
8961 01:21:51.252419
8962 01:21:51.252789
8963 01:21:51.253129
8964 01:21:51.255078 [DramC_TX_OE_Calibration] TA2
8965 01:21:51.258045 Original DQ_B0 (3 6) =30, OEN = 27
8966 01:21:51.261854 Original DQ_B1 (3 6) =30, OEN = 27
8967 01:21:51.265280 24, 0x0, End_B0=24 End_B1=24
8968 01:21:51.268448 25, 0x0, End_B0=25 End_B1=25
8969 01:21:51.269017 26, 0x0, End_B0=26 End_B1=26
8970 01:21:51.271349 27, 0x0, End_B0=27 End_B1=27
8971 01:21:51.274747 28, 0x0, End_B0=28 End_B1=28
8972 01:21:51.278454 29, 0x0, End_B0=29 End_B1=29
8973 01:21:51.281453 30, 0x0, End_B0=30 End_B1=30
8974 01:21:51.282025 31, 0x4141, End_B0=30 End_B1=30
8975 01:21:51.284645 Byte0 end_step=30 best_step=27
8976 01:21:51.288019 Byte1 end_step=30 best_step=27
8977 01:21:51.291474 Byte0 TX OE(2T, 0.5T) = (3, 3)
8978 01:21:51.294077 Byte1 TX OE(2T, 0.5T) = (3, 3)
8979 01:21:51.294542
8980 01:21:51.294904
8981 01:21:51.300891 [DQSOSCAuto] RK1, (LSB)MR18= 0xc19, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 403 ps
8982 01:21:51.304574 CH1 RK1: MR19=303, MR18=C19
8983 01:21:51.310584 CH1_RK1: MR19=0x303, MR18=0xC19, DQSOSC=397, MR23=63, INC=23, DEC=15
8984 01:21:51.314342 [RxdqsGatingPostProcess] freq 1600
8985 01:21:51.320735 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8986 01:21:51.321255 best DQS0 dly(2T, 0.5T) = (1, 1)
8987 01:21:51.324202 best DQS1 dly(2T, 0.5T) = (1, 1)
8988 01:21:51.327029 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8989 01:21:51.330591 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8990 01:21:51.333577 best DQS0 dly(2T, 0.5T) = (1, 1)
8991 01:21:51.337397 best DQS1 dly(2T, 0.5T) = (1, 1)
8992 01:21:51.340457 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8993 01:21:51.344027 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8994 01:21:51.346867 Pre-setting of DQS Precalculation
8995 01:21:51.349778 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8996 01:21:51.360353 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8997 01:21:51.366742 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8998 01:21:51.367311
8999 01:21:51.367686
9000 01:21:51.369852 [Calibration Summary] 3200 Mbps
9001 01:21:51.370320 CH 0, Rank 0
9002 01:21:51.372829 SW Impedance : PASS
9003 01:21:51.376341 DUTY Scan : NO K
9004 01:21:51.376765 ZQ Calibration : PASS
9005 01:21:51.379800 Jitter Meter : NO K
9006 01:21:51.383442 CBT Training : PASS
9007 01:21:51.384016 Write leveling : PASS
9008 01:21:51.385769 RX DQS gating : PASS
9009 01:21:51.389231 RX DQ/DQS(RDDQC) : PASS
9010 01:21:51.389764 TX DQ/DQS : PASS
9011 01:21:51.392735 RX DATLAT : PASS
9012 01:21:51.393161 RX DQ/DQS(Engine): PASS
9013 01:21:51.395691 TX OE : PASS
9014 01:21:51.396146 All Pass.
9015 01:21:51.396484
9016 01:21:51.399507 CH 0, Rank 1
9017 01:21:51.400217 SW Impedance : PASS
9018 01:21:51.402631 DUTY Scan : NO K
9019 01:21:51.405758 ZQ Calibration : PASS
9020 01:21:51.406187 Jitter Meter : NO K
9021 01:21:51.409316 CBT Training : PASS
9022 01:21:51.413313 Write leveling : PASS
9023 01:21:51.413838 RX DQS gating : PASS
9024 01:21:51.415677 RX DQ/DQS(RDDQC) : PASS
9025 01:21:51.419274 TX DQ/DQS : PASS
9026 01:21:51.419719 RX DATLAT : PASS
9027 01:21:51.422357 RX DQ/DQS(Engine): PASS
9028 01:21:51.425555 TX OE : PASS
9029 01:21:51.425979 All Pass.
9030 01:21:51.426312
9031 01:21:51.426624 CH 1, Rank 0
9032 01:21:51.428705 SW Impedance : PASS
9033 01:21:51.432264 DUTY Scan : NO K
9034 01:21:51.432687 ZQ Calibration : PASS
9035 01:21:51.435778 Jitter Meter : NO K
9036 01:21:51.439007 CBT Training : PASS
9037 01:21:51.439537 Write leveling : PASS
9038 01:21:51.442261 RX DQS gating : PASS
9039 01:21:51.445478 RX DQ/DQS(RDDQC) : PASS
9040 01:21:51.445903 TX DQ/DQS : PASS
9041 01:21:51.448495 RX DATLAT : PASS
9042 01:21:51.451824 RX DQ/DQS(Engine): PASS
9043 01:21:51.452293 TX OE : PASS
9044 01:21:51.455327 All Pass.
9045 01:21:51.455745
9046 01:21:51.456125 CH 1, Rank 1
9047 01:21:51.458440 SW Impedance : PASS
9048 01:21:51.458863 DUTY Scan : NO K
9049 01:21:51.461762 ZQ Calibration : PASS
9050 01:21:51.465003 Jitter Meter : NO K
9051 01:21:51.465424 CBT Training : PASS
9052 01:21:51.468088 Write leveling : PASS
9053 01:21:51.471717 RX DQS gating : PASS
9054 01:21:51.472242 RX DQ/DQS(RDDQC) : PASS
9055 01:21:51.474766 TX DQ/DQS : PASS
9056 01:21:51.475188 RX DATLAT : PASS
9057 01:21:51.478063 RX DQ/DQS(Engine): PASS
9058 01:21:51.481520 TX OE : PASS
9059 01:21:51.481944 All Pass.
9060 01:21:51.482280
9061 01:21:51.484815 DramC Write-DBI on
9062 01:21:51.485236 PER_BANK_REFRESH: Hybrid Mode
9063 01:21:51.487934 TX_TRACKING: ON
9064 01:21:51.497784 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9065 01:21:51.504545 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9066 01:21:51.511235 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9067 01:21:51.514529 [FAST_K] Save calibration result to emmc
9068 01:21:51.517529 sync common calibartion params.
9069 01:21:51.520684 sync cbt_mode0:1, 1:1
9070 01:21:51.523991 dram_init: ddr_geometry: 2
9071 01:21:51.524417 dram_init: ddr_geometry: 2
9072 01:21:51.528120 dram_init: ddr_geometry: 2
9073 01:21:51.530595 0:dram_rank_size:100000000
9074 01:21:51.533746 1:dram_rank_size:100000000
9075 01:21:51.537549 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9076 01:21:51.540550 DFS_SHUFFLE_HW_MODE: ON
9077 01:21:51.543987 dramc_set_vcore_voltage set vcore to 725000
9078 01:21:51.546885 Read voltage for 1600, 0
9079 01:21:51.547308 Vio18 = 0
9080 01:21:51.547637 Vcore = 725000
9081 01:21:51.550327 Vdram = 0
9082 01:21:51.550748 Vddq = 0
9083 01:21:51.551084 Vmddr = 0
9084 01:21:51.553487 switch to 3200 Mbps bootup
9085 01:21:51.557484 [DramcRunTimeConfig]
9086 01:21:51.557908 PHYPLL
9087 01:21:51.558246 DPM_CONTROL_AFTERK: ON
9088 01:21:51.559984 PER_BANK_REFRESH: ON
9089 01:21:51.563779 REFRESH_OVERHEAD_REDUCTION: ON
9090 01:21:51.567166 CMD_PICG_NEW_MODE: OFF
9091 01:21:51.567587 XRTWTW_NEW_MODE: ON
9092 01:21:51.569884 XRTRTR_NEW_MODE: ON
9093 01:21:51.570322 TX_TRACKING: ON
9094 01:21:51.573458 RDSEL_TRACKING: OFF
9095 01:21:51.574019 DQS Precalculation for DVFS: ON
9096 01:21:51.577005 RX_TRACKING: OFF
9097 01:21:51.577427 HW_GATING DBG: ON
9098 01:21:51.580417 ZQCS_ENABLE_LP4: ON
9099 01:21:51.584462 RX_PICG_NEW_MODE: ON
9100 01:21:51.584978 TX_PICG_NEW_MODE: ON
9101 01:21:51.586610 ENABLE_RX_DCM_DPHY: ON
9102 01:21:51.589982 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9103 01:21:51.590499 DUMMY_READ_FOR_TRACKING: OFF
9104 01:21:51.593694 !!! SPM_CONTROL_AFTERK: OFF
9105 01:21:51.596905 !!! SPM could not control APHY
9106 01:21:51.600566 IMPEDANCE_TRACKING: ON
9107 01:21:51.601133 TEMP_SENSOR: ON
9108 01:21:51.603248 HW_SAVE_FOR_SR: OFF
9109 01:21:51.606594 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9110 01:21:51.609982 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9111 01:21:51.610500 Read ODT Tracking: ON
9112 01:21:51.613139 Refresh Rate DeBounce: ON
9113 01:21:51.616191 DFS_NO_QUEUE_FLUSH: ON
9114 01:21:51.619980 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9115 01:21:51.620491 ENABLE_DFS_RUNTIME_MRW: OFF
9116 01:21:51.622968 DDR_RESERVE_NEW_MODE: ON
9117 01:21:51.626367 MR_CBT_SWITCH_FREQ: ON
9118 01:21:51.626793 =========================
9119 01:21:51.646871 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9120 01:21:51.649509 dram_init: ddr_geometry: 2
9121 01:21:51.668072 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9122 01:21:51.671810 dram_init: dram init end (result: 0)
9123 01:21:51.677802 DRAM-K: Full calibration passed in 24433 msecs
9124 01:21:51.681527 MRC: failed to locate region type 0.
9125 01:21:51.682099 DRAM rank0 size:0x100000000,
9126 01:21:51.684564 DRAM rank1 size=0x100000000
9127 01:21:51.694558 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9128 01:21:51.701310 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9129 01:21:51.710604 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9130 01:21:51.717612 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9131 01:21:51.718176 DRAM rank0 size:0x100000000,
9132 01:21:51.720337 DRAM rank1 size=0x100000000
9133 01:21:51.720801 CBMEM:
9134 01:21:51.723779 IMD: root @ 0xfffff000 254 entries.
9135 01:21:51.727317 IMD: root @ 0xffffec00 62 entries.
9136 01:21:51.733834 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9137 01:21:51.737051 WARNING: RO_VPD is uninitialized or empty.
9138 01:21:51.740414 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9139 01:21:51.748382 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9140 01:21:51.760929 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9141 01:21:51.772211 BS: romstage times (exec / console): total (unknown) / 23962 ms
9142 01:21:51.772783
9143 01:21:51.773160
9144 01:21:51.782149 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9145 01:21:51.785417 ARM64: Exception handlers installed.
9146 01:21:51.788559 ARM64: Testing exception
9147 01:21:51.791460 ARM64: Done test exception
9148 01:21:51.791952 Enumerating buses...
9149 01:21:51.795082 Show all devs... Before device enumeration.
9150 01:21:51.798447 Root Device: enabled 1
9151 01:21:51.801443 CPU_CLUSTER: 0: enabled 1
9152 01:21:51.801909 CPU: 00: enabled 1
9153 01:21:51.804882 Compare with tree...
9154 01:21:51.805448 Root Device: enabled 1
9155 01:21:51.808369 CPU_CLUSTER: 0: enabled 1
9156 01:21:51.811316 CPU: 00: enabled 1
9157 01:21:51.811880 Root Device scanning...
9158 01:21:51.814980 scan_static_bus for Root Device
9159 01:21:51.818159 CPU_CLUSTER: 0 enabled
9160 01:21:51.821391 scan_static_bus for Root Device done
9161 01:21:51.824413 scan_bus: bus Root Device finished in 8 msecs
9162 01:21:51.824927 done
9163 01:21:51.830868 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9164 01:21:51.834319 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9165 01:21:51.840954 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9166 01:21:51.847752 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9167 01:21:51.848356 Allocating resources...
9168 01:21:51.850844 Reading resources...
9169 01:21:51.853884 Root Device read_resources bus 0 link: 0
9170 01:21:51.857433 DRAM rank0 size:0x100000000,
9171 01:21:51.860589 DRAM rank1 size=0x100000000
9172 01:21:51.863563 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9173 01:21:51.867138 CPU: 00 missing read_resources
9174 01:21:51.870478 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9175 01:21:51.873992 Root Device read_resources bus 0 link: 0 done
9176 01:21:51.877043 Done reading resources.
9177 01:21:51.880370 Show resources in subtree (Root Device)...After reading.
9178 01:21:51.883248 Root Device child on link 0 CPU_CLUSTER: 0
9179 01:21:51.890546 CPU_CLUSTER: 0 child on link 0 CPU: 00
9180 01:21:51.896814 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9181 01:21:51.900332 CPU: 00
9182 01:21:51.903131 Root Device assign_resources, bus 0 link: 0
9183 01:21:51.906678 CPU_CLUSTER: 0 missing set_resources
9184 01:21:51.909969 Root Device assign_resources, bus 0 link: 0 done
9185 01:21:51.913298 Done setting resources.
9186 01:21:51.916157 Show resources in subtree (Root Device)...After assigning values.
9187 01:21:51.923204 Root Device child on link 0 CPU_CLUSTER: 0
9188 01:21:51.926260 CPU_CLUSTER: 0 child on link 0 CPU: 00
9189 01:21:51.932621 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9190 01:21:51.936342 CPU: 00
9191 01:21:51.936975 Done allocating resources.
9192 01:21:51.942861 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9193 01:21:51.946358 Enabling resources...
9194 01:21:51.946871 done.
9195 01:21:51.949498 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9196 01:21:51.953004 Initializing devices...
9197 01:21:51.953440 Root Device init
9198 01:21:51.956228 init hardware done!
9199 01:21:51.959389 0x00000018: ctrlr->caps
9200 01:21:51.959962 52.000 MHz: ctrlr->f_max
9201 01:21:51.962284 0.400 MHz: ctrlr->f_min
9202 01:21:51.966019 0x40ff8080: ctrlr->voltages
9203 01:21:51.966544 sclk: 390625
9204 01:21:51.966897 Bus Width = 1
9205 01:21:51.969382 sclk: 390625
9206 01:21:51.969806 Bus Width = 1
9207 01:21:51.972526 Early init status = 3
9208 01:21:51.975661 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9209 01:21:51.980637 in-header: 03 fc 00 00 01 00 00 00
9210 01:21:51.984024 in-data: 00
9211 01:21:51.987193 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9212 01:21:51.992564 in-header: 03 fd 00 00 00 00 00 00
9213 01:21:51.996494 in-data:
9214 01:21:51.999278 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9215 01:21:52.003549 in-header: 03 fc 00 00 01 00 00 00
9216 01:21:52.007500 in-data: 00
9217 01:21:52.010454 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9218 01:21:52.015981 in-header: 03 fd 00 00 00 00 00 00
9219 01:21:52.019352 in-data:
9220 01:21:52.022838 [SSUSB] Setting up USB HOST controller...
9221 01:21:52.026184 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9222 01:21:52.029427 [SSUSB] phy power-on done.
9223 01:21:52.032439 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9224 01:21:52.038880 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9225 01:21:52.042095 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9226 01:21:52.048928 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9227 01:21:52.055528 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9228 01:21:52.062399 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9229 01:21:52.068716 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9230 01:21:52.075653 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9231 01:21:52.079059 SPM: binary array size = 0x9dc
9232 01:21:52.081964 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9233 01:21:52.088551 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9234 01:21:52.095008 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9235 01:21:52.101536 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9236 01:21:52.105020 configure_display: Starting display init
9237 01:21:52.139608 anx7625_power_on_init: Init interface.
9238 01:21:52.143044 anx7625_disable_pd_protocol: Disabled PD feature.
9239 01:21:52.146001 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9240 01:21:52.173972 anx7625_start_dp_work: Secure OCM version=00
9241 01:21:52.177083 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9242 01:21:52.192256 sp_tx_get_edid_block: EDID Block = 1
9243 01:21:52.294723 Extracted contents:
9244 01:21:52.297403 header: 00 ff ff ff ff ff ff 00
9245 01:21:52.301055 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9246 01:21:52.304265 version: 01 04
9247 01:21:52.307702 basic params: 95 1f 11 78 0a
9248 01:21:52.311031 chroma info: 76 90 94 55 54 90 27 21 50 54
9249 01:21:52.314433 established: 00 00 00
9250 01:21:52.320764 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9251 01:21:52.327344 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9252 01:21:52.330916 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9253 01:21:52.337113 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9254 01:21:52.343962 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9255 01:21:52.347513 extensions: 00
9256 01:21:52.348114 checksum: fb
9257 01:21:52.348483
9258 01:21:52.353991 Manufacturer: IVO Model 57d Serial Number 0
9259 01:21:52.354550 Made week 0 of 2020
9260 01:21:52.356960 EDID version: 1.4
9261 01:21:52.357423 Digital display
9262 01:21:52.360352 6 bits per primary color channel
9263 01:21:52.363597 DisplayPort interface
9264 01:21:52.364093 Maximum image size: 31 cm x 17 cm
9265 01:21:52.366736 Gamma: 220%
9266 01:21:52.367296 Check DPMS levels
9267 01:21:52.373168 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9268 01:21:52.376952 First detailed timing is preferred timing
9269 01:21:52.380535 Established timings supported:
9270 01:21:52.381099 Standard timings supported:
9271 01:21:52.383396 Detailed timings
9272 01:21:52.387227 Hex of detail: 383680a07038204018303c0035ae10000019
9273 01:21:52.393116 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9274 01:21:52.396550 0780 0798 07c8 0820 hborder 0
9275 01:21:52.400223 0438 043b 0447 0458 vborder 0
9276 01:21:52.402930 -hsync -vsync
9277 01:21:52.403395 Did detailed timing
9278 01:21:52.409472 Hex of detail: 000000000000000000000000000000000000
9279 01:21:52.412869 Manufacturer-specified data, tag 0
9280 01:21:52.416258 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9281 01:21:52.419740 ASCII string: InfoVision
9282 01:21:52.422954 Hex of detail: 000000fe00523134304e574635205248200a
9283 01:21:52.426040 ASCII string: R140NWF5 RH
9284 01:21:52.426519 Checksum
9285 01:21:52.429540 Checksum: 0xfb (valid)
9286 01:21:52.432629 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9287 01:21:52.436155 DSI data_rate: 832800000 bps
9288 01:21:52.442261 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9289 01:21:52.446318 anx7625_parse_edid: pixelclock(138800).
9290 01:21:52.449148 hactive(1920), hsync(48), hfp(24), hbp(88)
9291 01:21:52.452527 vactive(1080), vsync(12), vfp(3), vbp(17)
9292 01:21:52.455511 anx7625_dsi_config: config dsi.
9293 01:21:52.462225 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9294 01:21:52.476783 anx7625_dsi_config: success to config DSI
9295 01:21:52.480163 anx7625_dp_start: MIPI phy setup OK.
9296 01:21:52.483334 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9297 01:21:52.486330 mtk_ddp_mode_set invalid vrefresh 60
9298 01:21:52.489589 main_disp_path_setup
9299 01:21:52.490049 ovl_layer_smi_id_en
9300 01:21:52.492833 ovl_layer_smi_id_en
9301 01:21:52.493388 ccorr_config
9302 01:21:52.493757 aal_config
9303 01:21:52.496279 gamma_config
9304 01:21:52.496838 postmask_config
9305 01:21:52.499571 dither_config
9306 01:21:52.503316 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9307 01:21:52.509637 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9308 01:21:52.512602 Root Device init finished in 555 msecs
9309 01:21:52.516104 CPU_CLUSTER: 0 init
9310 01:21:52.522390 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9311 01:21:52.528907 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9312 01:21:52.529371 APU_MBOX 0x190000b0 = 0x10001
9313 01:21:52.532472 APU_MBOX 0x190001b0 = 0x10001
9314 01:21:52.535918 APU_MBOX 0x190005b0 = 0x10001
9315 01:21:52.539010 APU_MBOX 0x190006b0 = 0x10001
9316 01:21:52.545914 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9317 01:21:52.555554 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9318 01:21:52.567970 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9319 01:21:52.574446 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9320 01:21:52.586161 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9321 01:21:52.595122 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9322 01:21:52.598611 CPU_CLUSTER: 0 init finished in 81 msecs
9323 01:21:52.601645 Devices initialized
9324 01:21:52.605276 Show all devs... After init.
9325 01:21:52.605724 Root Device: enabled 1
9326 01:21:52.608433 CPU_CLUSTER: 0: enabled 1
9327 01:21:52.611748 CPU: 00: enabled 1
9328 01:21:52.615510 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9329 01:21:52.618680 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9330 01:21:52.621478 ELOG: NV offset 0x57f000 size 0x1000
9331 01:21:52.628121 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9332 01:21:52.635443 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9333 01:21:52.638090 ELOG: Event(17) added with size 13 at 2024-04-23 01:21:52 UTC
9334 01:21:52.645043 out: cmd=0x121: 03 db 21 01 00 00 00 00
9335 01:21:52.648155 in-header: 03 1f 00 00 2c 00 00 00
9336 01:21:52.657772 in-data: 40 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9337 01:21:52.664538 ELOG: Event(A1) added with size 10 at 2024-04-23 01:21:52 UTC
9338 01:21:52.671001 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9339 01:21:52.677723 ELOG: Event(A0) added with size 9 at 2024-04-23 01:21:52 UTC
9340 01:21:52.680792 elog_add_boot_reason: Logged dev mode boot
9341 01:21:52.687197 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9342 01:21:52.687624 Finalize devices...
9343 01:21:52.691138 Devices finalized
9344 01:21:52.694109 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9345 01:21:52.697220 Writing coreboot table at 0xffe64000
9346 01:21:52.700739 0. 000000000010a000-0000000000113fff: RAMSTAGE
9347 01:21:52.707319 1. 0000000040000000-00000000400fffff: RAM
9348 01:21:52.710781 2. 0000000040100000-000000004032afff: RAMSTAGE
9349 01:21:52.713613 3. 000000004032b000-00000000545fffff: RAM
9350 01:21:52.717160 4. 0000000054600000-000000005465ffff: BL31
9351 01:21:52.720572 5. 0000000054660000-00000000ffe63fff: RAM
9352 01:21:52.727014 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9353 01:21:52.730140 7. 0000000100000000-000000023fffffff: RAM
9354 01:21:52.733576 Passing 5 GPIOs to payload:
9355 01:21:52.736881 NAME | PORT | POLARITY | VALUE
9356 01:21:52.743369 EC in RW | 0x000000aa | low | undefined
9357 01:21:52.746633 EC interrupt | 0x00000005 | low | undefined
9358 01:21:52.754065 TPM interrupt | 0x000000ab | high | undefined
9359 01:21:52.756490 SD card detect | 0x00000011 | high | undefined
9360 01:21:52.760338 speaker enable | 0x00000093 | high | undefined
9361 01:21:52.763045 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9362 01:21:52.767280 in-header: 03 f9 00 00 02 00 00 00
9363 01:21:52.770148 in-data: 02 00
9364 01:21:52.772923 ADC[4]: Raw value=902955 ID=7
9365 01:21:52.776695 ADC[3]: Raw value=213916 ID=1
9366 01:21:52.777251 RAM Code: 0x71
9367 01:21:52.780065 ADC[6]: Raw value=75000 ID=0
9368 01:21:52.783581 ADC[5]: Raw value=213546 ID=1
9369 01:21:52.784194 SKU Code: 0x1
9370 01:21:52.790096 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum c8cd
9371 01:21:52.790660 coreboot table: 964 bytes.
9372 01:21:52.793264 IMD ROOT 0. 0xfffff000 0x00001000
9373 01:21:52.796310 IMD SMALL 1. 0xffffe000 0x00001000
9374 01:21:52.799561 RO MCACHE 2. 0xffffc000 0x00001104
9375 01:21:52.803336 CONSOLE 3. 0xfff7c000 0x00080000
9376 01:21:52.806363 FMAP 4. 0xfff7b000 0x00000452
9377 01:21:52.809699 TIME STAMP 5. 0xfff7a000 0x00000910
9378 01:21:52.812665 VBOOT WORK 6. 0xfff66000 0x00014000
9379 01:21:52.816248 RAMOOPS 7. 0xffe66000 0x00100000
9380 01:21:52.819185 COREBOOT 8. 0xffe64000 0x00002000
9381 01:21:52.822528 IMD small region:
9382 01:21:52.826238 IMD ROOT 0. 0xffffec00 0x00000400
9383 01:21:52.828867 VPD 1. 0xffffeb80 0x0000006c
9384 01:21:52.832448 MMC STATUS 2. 0xffffeb60 0x00000004
9385 01:21:52.839139 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9386 01:21:52.839663 Probing TPM: done!
9387 01:21:52.845909 Connected to device vid:did:rid of 1ae0:0028:00
9388 01:21:52.852380 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9389 01:21:52.855976 Initialized TPM device CR50 revision 0
9390 01:21:52.859396 Checking cr50 for pending updates
9391 01:21:52.865051 Reading cr50 TPM mode
9392 01:21:52.873828 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9393 01:21:52.880236 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9394 01:21:52.920282 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9395 01:21:52.923126 Checking segment from ROM address 0x40100000
9396 01:21:52.930044 Checking segment from ROM address 0x4010001c
9397 01:21:52.933780 Loading segment from ROM address 0x40100000
9398 01:21:52.934450 code (compression=0)
9399 01:21:52.943445 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9400 01:21:52.949744 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9401 01:21:52.950210 it's not compressed!
9402 01:21:52.956501 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9403 01:21:52.963460 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9404 01:21:52.980696 Loading segment from ROM address 0x4010001c
9405 01:21:52.981255 Entry Point 0x80000000
9406 01:21:52.984125 Loaded segments
9407 01:21:52.987447 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9408 01:21:52.994408 Jumping to boot code at 0x80000000(0xffe64000)
9409 01:21:53.001106 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9410 01:21:53.007371 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9411 01:21:53.014999 read SPI 0x8eb68 0x74a8: 3222 us, 9268 KB/s, 74.144 Mbps
9412 01:21:53.018133 Checking segment from ROM address 0x40100000
9413 01:21:53.022230 Checking segment from ROM address 0x4010001c
9414 01:21:53.028567 Loading segment from ROM address 0x40100000
9415 01:21:53.029215 code (compression=1)
9416 01:21:53.035319 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9417 01:21:53.044788 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9418 01:21:53.045340 using LZMA
9419 01:21:53.054005 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9420 01:21:53.060308 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9421 01:21:53.063923 Loading segment from ROM address 0x4010001c
9422 01:21:53.064487 Entry Point 0x54601000
9423 01:21:53.067018 Loaded segments
9424 01:21:53.070157 NOTICE: MT8192 bl31_setup
9425 01:21:53.076728 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9426 01:21:53.080642 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9427 01:21:53.083767 WARNING: region 0:
9428 01:21:53.087277 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9429 01:21:53.087832 WARNING: region 1:
9430 01:21:53.093826 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9431 01:21:53.096842 WARNING: region 2:
9432 01:21:53.100555 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9433 01:21:53.104172 WARNING: region 3:
9434 01:21:53.106781 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9435 01:21:53.110250 WARNING: region 4:
9436 01:21:53.116927 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9437 01:21:53.117493 WARNING: region 5:
9438 01:21:53.120195 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9439 01:21:53.123582 WARNING: region 6:
9440 01:21:53.126949 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9441 01:21:53.130019 WARNING: region 7:
9442 01:21:53.133797 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9443 01:21:53.140665 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9444 01:21:53.143243 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9445 01:21:53.146701 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9446 01:21:53.153829 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9447 01:21:53.157482 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9448 01:21:53.159832 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9449 01:21:53.166697 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9450 01:21:53.170282 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9451 01:21:53.177052 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9452 01:21:53.179866 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9453 01:21:53.183618 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9454 01:21:53.190446 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9455 01:21:53.193522 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9456 01:21:53.196958 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9457 01:21:53.203375 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9458 01:21:53.206605 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9459 01:21:53.212989 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9460 01:21:53.216240 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9461 01:21:53.219488 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9462 01:21:53.226588 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9463 01:21:53.229577 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9464 01:21:53.236347 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9465 01:21:53.240314 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9466 01:21:53.243489 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9467 01:21:53.249703 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9468 01:21:53.253341 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9469 01:21:53.259919 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9470 01:21:53.262636 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9471 01:21:53.269348 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9472 01:21:53.272318 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9473 01:21:53.275969 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9474 01:21:53.282219 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9475 01:21:53.285584 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9476 01:21:53.289248 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9477 01:21:53.292227 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9478 01:21:53.299076 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9479 01:21:53.302141 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9480 01:21:53.305227 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9481 01:21:53.308770 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9482 01:21:53.315515 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9483 01:21:53.318597 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9484 01:21:53.321664 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9485 01:21:53.325679 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9486 01:21:53.332377 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9487 01:21:53.335135 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9488 01:21:53.338295 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9489 01:21:53.345157 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9490 01:21:53.348783 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9491 01:21:53.352057 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9492 01:21:53.358200 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9493 01:21:53.361585 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9494 01:21:53.368578 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9495 01:21:53.371986 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9496 01:21:53.375170 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9497 01:21:53.381451 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9498 01:21:53.385262 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9499 01:21:53.392034 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9500 01:21:53.395238 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9501 01:21:53.401778 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9502 01:21:53.405331 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9503 01:21:53.408412 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9504 01:21:53.414584 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9505 01:21:53.418201 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9506 01:21:53.424592 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9507 01:21:53.428426 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9508 01:21:53.435173 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9509 01:21:53.438024 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9510 01:21:53.444579 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9511 01:21:53.448397 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9512 01:21:53.451646 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9513 01:21:53.457864 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9514 01:21:53.461278 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9515 01:21:53.468011 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9516 01:21:53.471194 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9517 01:21:53.477989 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9518 01:21:53.481623 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9519 01:21:53.487591 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9520 01:21:53.491186 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9521 01:21:53.494444 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9522 01:21:53.501192 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9523 01:21:53.504202 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9524 01:21:53.511003 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9525 01:21:53.514015 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9526 01:21:53.520621 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9527 01:21:53.523782 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9528 01:21:53.530646 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9529 01:21:53.533702 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9530 01:21:53.537615 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9531 01:21:53.543951 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9532 01:21:53.547113 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9533 01:21:53.554064 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9534 01:21:53.556874 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9535 01:21:53.563531 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9536 01:21:53.567165 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9537 01:21:53.573769 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9538 01:21:53.576703 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9539 01:21:53.580014 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9540 01:21:53.587280 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9541 01:21:53.590452 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9542 01:21:53.593991 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9543 01:21:53.597097 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9544 01:21:53.603768 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9545 01:21:53.606939 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9546 01:21:53.613710 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9547 01:21:53.617076 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9548 01:21:53.620303 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9549 01:21:53.626951 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9550 01:21:53.630407 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9551 01:21:53.636276 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9552 01:21:53.640195 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9553 01:21:53.643676 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9554 01:21:53.650348 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9555 01:21:53.652953 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9556 01:21:53.659683 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9557 01:21:53.663277 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9558 01:21:53.666181 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9559 01:21:53.673075 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9560 01:21:53.676083 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9561 01:21:53.679369 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9562 01:21:53.687021 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9563 01:21:53.689262 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9564 01:21:53.692753 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9565 01:21:53.696232 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9566 01:21:53.702014 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9567 01:21:53.705676 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9568 01:21:53.708996 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9569 01:21:53.715995 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9570 01:21:53.719173 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9571 01:21:53.725501 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9572 01:21:53.728952 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9573 01:21:53.731982 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9574 01:21:53.738616 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9575 01:21:53.741898 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9576 01:21:53.748495 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9577 01:21:53.751371 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9578 01:21:53.757890 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9579 01:21:53.761685 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9580 01:21:53.764634 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9581 01:21:53.771215 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9582 01:21:53.774635 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9583 01:21:53.781442 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9584 01:21:53.784840 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9585 01:21:53.787819 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9586 01:21:53.794611 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9587 01:21:53.797649 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9588 01:21:53.800659 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9589 01:21:53.807291 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9590 01:21:53.810975 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9591 01:21:53.817521 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9592 01:21:53.820722 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9593 01:21:53.824116 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9594 01:21:53.831096 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9595 01:21:53.834540 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9596 01:21:53.840922 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9597 01:21:53.844209 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9598 01:21:53.847967 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9599 01:21:53.854675 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9600 01:21:53.857496 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9601 01:21:53.863798 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9602 01:21:53.867776 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9603 01:21:53.870754 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9604 01:21:53.877165 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9605 01:21:53.880557 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9606 01:21:53.886927 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9607 01:21:53.890154 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9608 01:21:53.894246 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9609 01:21:53.900043 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9610 01:21:53.903449 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9611 01:21:53.909935 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9612 01:21:53.913112 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9613 01:21:53.919756 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9614 01:21:53.922927 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9615 01:21:53.926242 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9616 01:21:53.932710 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9617 01:21:53.936096 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9618 01:21:53.942701 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9619 01:21:53.946123 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9620 01:21:53.949357 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9621 01:21:53.956156 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9622 01:21:53.958948 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9623 01:21:53.965962 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9624 01:21:53.969499 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9625 01:21:53.972861 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9626 01:21:53.979765 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9627 01:21:53.983081 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9628 01:21:53.989384 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9629 01:21:53.992002 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9630 01:21:53.995831 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9631 01:21:54.002620 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9632 01:21:54.005717 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9633 01:21:54.012149 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9634 01:21:54.015401 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9635 01:21:54.021733 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9636 01:21:54.025444 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9637 01:21:54.028823 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9638 01:21:54.034826 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9639 01:21:54.038143 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9640 01:21:54.044510 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9641 01:21:54.048261 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9642 01:21:54.054459 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9643 01:21:54.057944 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9644 01:21:54.061306 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9645 01:21:54.067585 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9646 01:21:54.071506 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9647 01:21:54.077625 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9648 01:21:54.080865 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9649 01:21:54.087793 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9650 01:21:54.091375 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9651 01:21:54.094526 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9652 01:21:54.100734 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9653 01:21:54.104474 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9654 01:21:54.110969 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9655 01:21:54.113961 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9656 01:21:54.120807 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9657 01:21:54.124054 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9658 01:21:54.127426 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9659 01:21:54.133727 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9660 01:21:54.137042 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9661 01:21:54.143557 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9662 01:21:54.146964 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9663 01:21:54.153377 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9664 01:21:54.156710 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9665 01:21:54.159820 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9666 01:21:54.166583 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9667 01:21:54.169988 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9668 01:21:54.176325 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9669 01:21:54.179580 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9670 01:21:54.186400 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9671 01:21:54.190239 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9672 01:21:54.192555 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9673 01:21:54.196427 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9674 01:21:54.202925 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9675 01:21:54.206080 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9676 01:21:54.209235 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9677 01:21:54.215621 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9678 01:21:54.219308 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9679 01:21:54.222086 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9680 01:21:54.228955 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9681 01:21:54.232233 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9682 01:21:54.238779 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9683 01:21:54.242040 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9684 01:21:54.245852 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9685 01:21:54.252038 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9686 01:21:54.255495 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9687 01:21:54.258980 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9688 01:21:54.264852 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9689 01:21:54.268712 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9690 01:21:54.275143 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9691 01:21:54.278375 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9692 01:21:54.281403 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9693 01:21:54.288173 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9694 01:21:54.292006 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9695 01:21:54.298200 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9696 01:21:54.301494 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9697 01:21:54.304439 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9698 01:21:54.311144 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9699 01:21:54.314269 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9700 01:21:54.317899 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9701 01:21:54.324224 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9702 01:21:54.327835 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9703 01:21:54.331140 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9704 01:21:54.337496 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9705 01:21:54.340552 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9706 01:21:54.347346 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9707 01:21:54.350821 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9708 01:21:54.354134 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9709 01:21:54.360988 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9710 01:21:54.364111 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9711 01:21:54.368326 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9712 01:21:54.374541 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9713 01:21:54.376927 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9714 01:21:54.380113 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9715 01:21:54.383583 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9716 01:21:54.386857 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9717 01:21:54.393714 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9718 01:21:54.396600 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9719 01:21:54.400275 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9720 01:21:54.407420 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9721 01:21:54.410195 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9722 01:21:54.412973 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9723 01:21:54.416467 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9724 01:21:54.422906 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9725 01:21:54.426212 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9726 01:21:54.433052 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9727 01:21:54.436014 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9728 01:21:54.442915 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9729 01:21:54.446468 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9730 01:21:54.449953 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9731 01:21:54.456307 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9732 01:21:54.459553 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9733 01:21:54.465951 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9734 01:21:54.469269 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9735 01:21:54.472277 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9736 01:21:54.479378 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9737 01:21:54.482466 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9738 01:21:54.488878 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9739 01:21:54.491805 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9740 01:21:54.499102 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9741 01:21:54.501727 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9742 01:21:54.505654 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9743 01:21:54.511725 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9744 01:21:54.514738 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9745 01:21:54.521628 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9746 01:21:54.524718 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9747 01:21:54.531983 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9748 01:21:54.534429 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9749 01:21:54.538403 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9750 01:21:54.544715 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9751 01:21:54.547474 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9752 01:21:54.554329 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9753 01:21:54.557961 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9754 01:21:54.564846 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9755 01:21:54.567598 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9756 01:21:54.570993 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9757 01:21:54.577437 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9758 01:21:54.580608 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9759 01:21:54.587564 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9760 01:21:54.590855 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9761 01:21:54.597774 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9762 01:21:54.600802 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9763 01:21:54.603749 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9764 01:21:54.610137 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9765 01:21:54.613221 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9766 01:21:54.620481 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9767 01:21:54.623329 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9768 01:21:54.629763 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9769 01:21:54.632917 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9770 01:21:54.636531 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9771 01:21:54.643624 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9772 01:21:54.646510 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9773 01:21:54.652855 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9774 01:21:54.656233 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9775 01:21:54.659479 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9776 01:21:54.666174 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9777 01:21:54.669072 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9778 01:21:54.675846 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9779 01:21:54.678824 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9780 01:21:54.682845 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9781 01:21:54.689635 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9782 01:21:54.692725 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9783 01:21:54.699216 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9784 01:21:54.702509 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9785 01:21:54.708586 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9786 01:21:54.712067 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9787 01:21:54.719351 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9788 01:21:54.722337 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9789 01:21:54.725084 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9790 01:21:54.732056 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9791 01:21:54.735152 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9792 01:21:54.742008 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9793 01:21:54.745119 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9794 01:21:54.748076 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9795 01:21:54.754793 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9796 01:21:54.758072 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9797 01:21:54.764869 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9798 01:21:54.768610 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9799 01:21:54.774855 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9800 01:21:54.777752 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9801 01:21:54.784369 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9802 01:21:54.788171 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9803 01:21:54.790860 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9804 01:21:54.797890 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9805 01:21:54.801021 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9806 01:21:54.807686 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9807 01:21:54.811101 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9808 01:21:54.817115 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9809 01:21:54.820744 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9810 01:21:54.827170 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9811 01:21:54.830820 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9812 01:21:54.833459 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9813 01:21:54.839947 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9814 01:21:54.843301 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9815 01:21:54.850085 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9816 01:21:54.853340 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9817 01:21:54.859798 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9818 01:21:54.863330 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9819 01:21:54.869578 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9820 01:21:54.873242 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9821 01:21:54.876794 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9822 01:21:54.882900 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9823 01:21:54.886338 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9824 01:21:54.892956 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9825 01:21:54.896239 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9826 01:21:54.902592 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9827 01:21:54.906629 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9828 01:21:54.912390 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9829 01:21:54.915630 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9830 01:21:54.922153 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9831 01:21:54.925468 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9832 01:21:54.929140 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9833 01:21:54.935662 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9834 01:21:54.938910 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9835 01:21:54.945724 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9836 01:21:54.948844 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9837 01:21:54.955170 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9838 01:21:54.958315 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9839 01:21:54.965019 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9840 01:21:54.968942 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9841 01:21:54.971942 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9842 01:21:54.978506 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9843 01:21:54.982203 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9844 01:21:54.988418 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9845 01:21:54.991549 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9846 01:21:54.995291 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9847 01:21:55.001940 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9848 01:21:55.004904 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9849 01:21:55.011525 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9850 01:21:55.014268 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9851 01:21:55.021531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9852 01:21:55.024495 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9853 01:21:55.030920 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9854 01:21:55.034922 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9855 01:21:55.040786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9856 01:21:55.044043 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9857 01:21:55.050878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9858 01:21:55.054016 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9859 01:21:55.061068 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9860 01:21:55.064566 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9861 01:21:55.070731 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9862 01:21:55.073491 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9863 01:21:55.079943 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9864 01:21:55.083718 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9865 01:21:55.090387 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9866 01:21:55.093474 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9867 01:21:55.100534 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9868 01:21:55.103915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9869 01:21:55.110244 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9870 01:21:55.113350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9871 01:21:55.119826 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9872 01:21:55.126816 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9873 01:21:55.129787 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9874 01:21:55.136224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9875 01:21:55.139480 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9876 01:21:55.146134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9877 01:21:55.149949 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9878 01:21:55.150465 INFO: [APUAPC] vio 0
9879 01:21:55.156725 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9880 01:21:55.160209 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9881 01:21:55.163693 INFO: [APUAPC] D0_APC_0: 0x400510
9882 01:21:55.166927 INFO: [APUAPC] D0_APC_1: 0x0
9883 01:21:55.170477 INFO: [APUAPC] D0_APC_2: 0x1540
9884 01:21:55.173753 INFO: [APUAPC] D0_APC_3: 0x0
9885 01:21:55.176714 INFO: [APUAPC] D1_APC_0: 0xffffffff
9886 01:21:55.180313 INFO: [APUAPC] D1_APC_1: 0xffffffff
9887 01:21:55.183509 INFO: [APUAPC] D1_APC_2: 0x3fffff
9888 01:21:55.186732 INFO: [APUAPC] D1_APC_3: 0x0
9889 01:21:55.190049 INFO: [APUAPC] D2_APC_0: 0xffffffff
9890 01:21:55.193505 INFO: [APUAPC] D2_APC_1: 0xffffffff
9891 01:21:55.196675 INFO: [APUAPC] D2_APC_2: 0x3fffff
9892 01:21:55.199853 INFO: [APUAPC] D2_APC_3: 0x0
9893 01:21:55.202930 INFO: [APUAPC] D3_APC_0: 0xffffffff
9894 01:21:55.206335 INFO: [APUAPC] D3_APC_1: 0xffffffff
9895 01:21:55.209325 INFO: [APUAPC] D3_APC_2: 0x3fffff
9896 01:21:55.212965 INFO: [APUAPC] D3_APC_3: 0x0
9897 01:21:55.216015 INFO: [APUAPC] D4_APC_0: 0xffffffff
9898 01:21:55.219755 INFO: [APUAPC] D4_APC_1: 0xffffffff
9899 01:21:55.223027 INFO: [APUAPC] D4_APC_2: 0x3fffff
9900 01:21:55.226019 INFO: [APUAPC] D4_APC_3: 0x0
9901 01:21:55.229519 INFO: [APUAPC] D5_APC_0: 0xffffffff
9902 01:21:55.233003 INFO: [APUAPC] D5_APC_1: 0xffffffff
9903 01:21:55.236382 INFO: [APUAPC] D5_APC_2: 0x3fffff
9904 01:21:55.239351 INFO: [APUAPC] D5_APC_3: 0x0
9905 01:21:55.242493 INFO: [APUAPC] D6_APC_0: 0xffffffff
9906 01:21:55.246379 INFO: [APUAPC] D6_APC_1: 0xffffffff
9907 01:21:55.249911 INFO: [APUAPC] D6_APC_2: 0x3fffff
9908 01:21:55.250432 INFO: [APUAPC] D6_APC_3: 0x0
9909 01:21:55.256160 INFO: [APUAPC] D7_APC_0: 0xffffffff
9910 01:21:55.259494 INFO: [APUAPC] D7_APC_1: 0xffffffff
9911 01:21:55.262683 INFO: [APUAPC] D7_APC_2: 0x3fffff
9912 01:21:55.263201 INFO: [APUAPC] D7_APC_3: 0x0
9913 01:21:55.266135 INFO: [APUAPC] D8_APC_0: 0xffffffff
9914 01:21:55.272472 INFO: [APUAPC] D8_APC_1: 0xffffffff
9915 01:21:55.275415 INFO: [APUAPC] D8_APC_2: 0x3fffff
9916 01:21:55.275960 INFO: [APUAPC] D8_APC_3: 0x0
9917 01:21:55.278893 INFO: [APUAPC] D9_APC_0: 0xffffffff
9918 01:21:55.282501 INFO: [APUAPC] D9_APC_1: 0xffffffff
9919 01:21:55.285633 INFO: [APUAPC] D9_APC_2: 0x3fffff
9920 01:21:55.288906 INFO: [APUAPC] D9_APC_3: 0x0
9921 01:21:55.291859 INFO: [APUAPC] D10_APC_0: 0xffffffff
9922 01:21:55.295378 INFO: [APUAPC] D10_APC_1: 0xffffffff
9923 01:21:55.298954 INFO: [APUAPC] D10_APC_2: 0x3fffff
9924 01:21:55.302652 INFO: [APUAPC] D10_APC_3: 0x0
9925 01:21:55.305371 INFO: [APUAPC] D11_APC_0: 0xffffffff
9926 01:21:55.308599 INFO: [APUAPC] D11_APC_1: 0xffffffff
9927 01:21:55.315064 INFO: [APUAPC] D11_APC_2: 0x3fffff
9928 01:21:55.315549 INFO: [APUAPC] D11_APC_3: 0x0
9929 01:21:55.321752 INFO: [APUAPC] D12_APC_0: 0xffffffff
9930 01:21:55.325551 INFO: [APUAPC] D12_APC_1: 0xffffffff
9931 01:21:55.328651 INFO: [APUAPC] D12_APC_2: 0x3fffff
9932 01:21:55.329073 INFO: [APUAPC] D12_APC_3: 0x0
9933 01:21:55.334838 INFO: [APUAPC] D13_APC_0: 0xffffffff
9934 01:21:55.338092 INFO: [APUAPC] D13_APC_1: 0xffffffff
9935 01:21:55.341784 INFO: [APUAPC] D13_APC_2: 0x3fffff
9936 01:21:55.345084 INFO: [APUAPC] D13_APC_3: 0x0
9937 01:21:55.348392 INFO: [APUAPC] D14_APC_0: 0xffffffff
9938 01:21:55.351249 INFO: [APUAPC] D14_APC_1: 0xffffffff
9939 01:21:55.354689 INFO: [APUAPC] D14_APC_2: 0x3fffff
9940 01:21:55.357799 INFO: [APUAPC] D14_APC_3: 0x0
9941 01:21:55.361197 INFO: [APUAPC] D15_APC_0: 0xffffffff
9942 01:21:55.364928 INFO: [APUAPC] D15_APC_1: 0xffffffff
9943 01:21:55.367575 INFO: [APUAPC] D15_APC_2: 0x3fffff
9944 01:21:55.371069 INFO: [APUAPC] D15_APC_3: 0x0
9945 01:21:55.374667 INFO: [APUAPC] APC_CON: 0x4
9946 01:21:55.375188 INFO: [NOCDAPC] D0_APC_0: 0x0
9947 01:21:55.377564 INFO: [NOCDAPC] D0_APC_1: 0x0
9948 01:21:55.381007 INFO: [NOCDAPC] D1_APC_0: 0x0
9949 01:21:55.383921 INFO: [NOCDAPC] D1_APC_1: 0xfff
9950 01:21:55.387568 INFO: [NOCDAPC] D2_APC_0: 0x0
9951 01:21:55.391148 INFO: [NOCDAPC] D2_APC_1: 0xfff
9952 01:21:55.393820 INFO: [NOCDAPC] D3_APC_0: 0x0
9953 01:21:55.397339 INFO: [NOCDAPC] D3_APC_1: 0xfff
9954 01:21:55.400634 INFO: [NOCDAPC] D4_APC_0: 0x0
9955 01:21:55.403756 INFO: [NOCDAPC] D4_APC_1: 0xfff
9956 01:21:55.407385 INFO: [NOCDAPC] D5_APC_0: 0x0
9957 01:21:55.410521 INFO: [NOCDAPC] D5_APC_1: 0xfff
9958 01:21:55.410942 INFO: [NOCDAPC] D6_APC_0: 0x0
9959 01:21:55.413516 INFO: [NOCDAPC] D6_APC_1: 0xfff
9960 01:21:55.417221 INFO: [NOCDAPC] D7_APC_0: 0x0
9961 01:21:55.420319 INFO: [NOCDAPC] D7_APC_1: 0xfff
9962 01:21:55.423632 INFO: [NOCDAPC] D8_APC_0: 0x0
9963 01:21:55.426459 INFO: [NOCDAPC] D8_APC_1: 0xfff
9964 01:21:55.430333 INFO: [NOCDAPC] D9_APC_0: 0x0
9965 01:21:55.433153 INFO: [NOCDAPC] D9_APC_1: 0xfff
9966 01:21:55.436736 INFO: [NOCDAPC] D10_APC_0: 0x0
9967 01:21:55.439825 INFO: [NOCDAPC] D10_APC_1: 0xfff
9968 01:21:55.443606 INFO: [NOCDAPC] D11_APC_0: 0x0
9969 01:21:55.446915 INFO: [NOCDAPC] D11_APC_1: 0xfff
9970 01:21:55.449742 INFO: [NOCDAPC] D12_APC_0: 0x0
9971 01:21:55.453102 INFO: [NOCDAPC] D12_APC_1: 0xfff
9972 01:21:55.453618 INFO: [NOCDAPC] D13_APC_0: 0x0
9973 01:21:55.456719 INFO: [NOCDAPC] D13_APC_1: 0xfff
9974 01:21:55.459583 INFO: [NOCDAPC] D14_APC_0: 0x0
9975 01:21:55.463135 INFO: [NOCDAPC] D14_APC_1: 0xfff
9976 01:21:55.466385 INFO: [NOCDAPC] D15_APC_0: 0x0
9977 01:21:55.469838 INFO: [NOCDAPC] D15_APC_1: 0xfff
9978 01:21:55.472965 INFO: [NOCDAPC] APC_CON: 0x4
9979 01:21:55.476270 INFO: [APUAPC] set_apusys_apc done
9980 01:21:55.479438 INFO: [DEVAPC] devapc_init done
9981 01:21:55.482844 INFO: GICv3 without legacy support detected.
9982 01:21:55.489623 INFO: ARM GICv3 driver initialized in EL3
9983 01:21:55.492516 INFO: Maximum SPI INTID supported: 639
9984 01:21:55.496086 INFO: BL31: Initializing runtime services
9985 01:21:55.502631 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9986 01:21:55.503196 INFO: SPM: enable CPC mode
9987 01:21:55.508897 INFO: mcdi ready for mcusys-off-idle and system suspend
9988 01:21:55.512369 INFO: BL31: Preparing for EL3 exit to normal world
9989 01:21:55.518966 INFO: Entry point address = 0x80000000
9990 01:21:55.519530 INFO: SPSR = 0x8
9991 01:21:55.525503
9992 01:21:55.526057
9993 01:21:55.526427
9994 01:21:55.528149 Starting depthcharge on Spherion...
9995 01:21:55.528672
9996 01:21:55.529043 Wipe memory regions:
9997 01:21:55.529387
9998 01:21:55.532099 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9999 01:21:55.532828 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10000 01:21:55.533282 Setting prompt string to ['asurada:']
10001 01:21:55.533693 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10002 01:21:55.534411 [0x00000040000000, 0x00000054600000)
10003 01:21:55.654136
10004 01:21:55.654699 [0x00000054660000, 0x00000080000000)
10005 01:21:55.914914
10006 01:21:55.915473 [0x000000821a7280, 0x000000ffe64000)
10007 01:21:56.659440
10008 01:21:56.660033 [0x00000100000000, 0x00000240000000)
10009 01:21:58.549492
10010 01:21:58.552591 Initializing XHCI USB controller at 0x11200000.
10011 01:21:59.592269
10012 01:21:59.595101 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10013 01:21:59.595530
10014 01:21:59.595862
10015 01:21:59.596222
10016 01:21:59.596964 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10018 01:21:59.698115 asurada: tftpboot 192.168.201.1 13468767/tftp-deploy-31iv6vbn/kernel/image.itb 13468767/tftp-deploy-31iv6vbn/kernel/cmdline
10019 01:21:59.698707 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10020 01:21:59.699110 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10021 01:21:59.704279 tftpboot 192.168.201.1 13468767/tftp-deploy-31iv6vbn/kernel/image.ittp-deploy-31iv6vbn/kernel/cmdline
10022 01:21:59.704837
10023 01:21:59.705198 Waiting for link
10024 01:21:59.864290
10025 01:21:59.865098 R8152: Initializing
10026 01:21:59.865596
10027 01:21:59.867713 Version 6 (ocp_data = 5c30)
10028 01:21:59.868176
10029 01:21:59.870867 R8152: Done initializing
10030 01:21:59.871289
10031 01:21:59.871620 Adding net device
10032 01:22:01.833612
10033 01:22:01.834361 done.
10034 01:22:01.834939
10035 01:22:01.835282 MAC: 00:24:32:30:7c:7b
10036 01:22:01.835594
10037 01:22:01.836261 Sending DHCP discover... done.
10038 01:22:01.836612
10039 01:22:01.839219 Waiting for reply... done.
10040 01:22:01.839662
10041 01:22:01.842387 Sending DHCP request... done.
10042 01:22:01.842807
10043 01:22:01.849007 Waiting for reply... done.
10044 01:22:01.849576
10045 01:22:01.850052 My ip is 192.168.201.14
10046 01:22:01.850510
10047 01:22:01.852056 The DHCP server ip is 192.168.201.1
10048 01:22:01.852566
10049 01:22:01.858828 TFTP server IP predefined by user: 192.168.201.1
10050 01:22:01.859253
10051 01:22:01.865394 Bootfile predefined by user: 13468767/tftp-deploy-31iv6vbn/kernel/image.itb
10052 01:22:01.865957
10053 01:22:01.868582 Sending tftp read request... done.
10054 01:22:01.869004
10055 01:22:01.869334 Waiting for the transfer...
10056 01:22:01.871862
10057 01:22:02.456880 00000000 ################################################################
10058 01:22:02.457027
10059 01:22:03.056923 00080000 ################################################################
10060 01:22:03.057072
10061 01:22:03.658818 00100000 ################################################################
10062 01:22:03.658964
10063 01:22:04.311172 00180000 ################################################################
10064 01:22:04.311684
10065 01:22:04.969415 00200000 ################################################################
10066 01:22:04.969911
10067 01:22:05.630263 00280000 ################################################################
10068 01:22:05.630762
10069 01:22:06.265320 00300000 ################################################################
10070 01:22:06.265466
10071 01:22:06.870402 00380000 ################################################################
10072 01:22:06.870538
10073 01:22:07.463919 00400000 ################################################################
10074 01:22:07.464054
10075 01:22:08.028823 00480000 ################################################################
10076 01:22:08.028970
10077 01:22:08.573869 00500000 ################################################################
10078 01:22:08.574019
10079 01:22:09.165879 00580000 ################################################################
10080 01:22:09.166024
10081 01:22:09.755166 00600000 ################################################################
10082 01:22:09.755319
10083 01:22:10.345454 00680000 ################################################################
10084 01:22:10.345589
10085 01:22:10.938513 00700000 ################################################################
10086 01:22:10.938655
10087 01:22:11.503419 00780000 ################################################################
10088 01:22:11.503552
10089 01:22:12.143157 00800000 ################################################################
10090 01:22:12.143468
10091 01:22:12.698095 00880000 ################################################################
10092 01:22:12.698240
10093 01:22:13.253504 00900000 ################################################################
10094 01:22:13.253644
10095 01:22:13.824031 00980000 ################################################################
10096 01:22:13.824182
10097 01:22:14.388289 00a00000 ################################################################
10098 01:22:14.388432
10099 01:22:14.940200 00a80000 ################################################################
10100 01:22:14.940339
10101 01:22:15.524440 00b00000 ################################################################
10102 01:22:15.524586
10103 01:22:16.120348 00b80000 ################################################################
10104 01:22:16.120494
10105 01:22:16.776732 00c00000 ################################################################
10106 01:22:16.776880
10107 01:22:17.436189 00c80000 ################################################################
10108 01:22:17.436697
10109 01:22:18.102209 00d00000 ################################################################
10110 01:22:18.102711
10111 01:22:18.756339 00d80000 ################################################################
10112 01:22:18.756838
10113 01:22:19.415548 00e00000 ################################################################
10114 01:22:19.416089
10115 01:22:20.067693 00e80000 ################################################################
10116 01:22:20.067867
10117 01:22:20.662528 00f00000 ################################################################
10118 01:22:20.662669
10119 01:22:21.233283 00f80000 ################################################################
10120 01:22:21.233434
10121 01:22:21.792551 01000000 ################################################################
10122 01:22:21.792701
10123 01:22:22.360522 01080000 ################################################################
10124 01:22:22.360669
10125 01:22:22.937453 01100000 ################################################################
10126 01:22:22.937604
10127 01:22:23.477779 01180000 ################################################################
10128 01:22:23.477938
10129 01:22:24.045317 01200000 ################################################################
10130 01:22:24.045471
10131 01:22:24.616236 01280000 ################################################################
10132 01:22:24.616385
10133 01:22:25.197911 01300000 ################################################################
10134 01:22:25.198054
10135 01:22:25.811708 01380000 ################################################################
10136 01:22:25.811855
10137 01:22:26.408752 01400000 ################################################################
10138 01:22:26.408900
10139 01:22:27.062393 01480000 ################################################################
10140 01:22:27.062905
10141 01:22:27.735918 01500000 ################################################################
10142 01:22:27.736547
10143 01:22:28.388705 01580000 ################################################################
10144 01:22:28.389269
10145 01:22:29.047172 01600000 ################################################################
10146 01:22:29.047692
10147 01:22:29.692316 01680000 ################################################################
10148 01:22:29.692818
10149 01:22:30.370793 01700000 ################################################################
10150 01:22:30.371335
10151 01:22:31.015517 01780000 ################################################################
10152 01:22:31.015663
10153 01:22:31.649711 01800000 ################################################################
10154 01:22:31.649858
10155 01:22:32.287395 01880000 ################################################################
10156 01:22:32.287990
10157 01:22:32.955376 01900000 ################################################################
10158 01:22:32.956042
10159 01:22:33.624498 01980000 ################################################################
10160 01:22:33.625006
10161 01:22:34.297419 01a00000 ################################################################
10162 01:22:34.297928
10163 01:22:34.948617 01a80000 ################################################################
10164 01:22:34.948764
10165 01:22:35.605883 01b00000 ################################################################
10166 01:22:35.606391
10167 01:22:36.255629 01b80000 ################################################################
10168 01:22:36.256207
10169 01:22:36.921811 01c00000 ################################################################
10170 01:22:36.922324
10171 01:22:37.598893 01c80000 ################################################################
10172 01:22:37.599400
10173 01:22:38.239955 01d00000 ################################################################
10174 01:22:38.240469
10175 01:22:38.905068 01d80000 ################################################################
10176 01:22:38.905572
10177 01:22:39.559344 01e00000 ################################################################
10178 01:22:39.559849
10179 01:22:40.226685 01e80000 ################################################################
10180 01:22:40.227193
10181 01:22:40.896878 01f00000 ################################################################
10182 01:22:40.897433
10183 01:22:41.570200 01f80000 ################################################################
10184 01:22:41.570754
10185 01:22:42.254179 02000000 ################################################################
10186 01:22:42.254692
10187 01:22:42.934631 02080000 ################################################################
10188 01:22:42.935145
10189 01:22:43.614134 02100000 ################################################################
10190 01:22:43.614790
10191 01:22:44.292828 02180000 ################################################################
10192 01:22:44.293343
10193 01:22:44.974447 02200000 ################################################################
10194 01:22:44.974963
10195 01:22:45.658672 02280000 ################################################################
10196 01:22:45.659182
10197 01:22:46.339932 02300000 ################################################################
10198 01:22:46.340442
10199 01:22:46.996314 02380000 ################################################################
10200 01:22:46.996834
10201 01:22:47.676426 02400000 ################################################################
10202 01:22:47.676948
10203 01:22:48.298380 02480000 ################################################################
10204 01:22:48.298525
10205 01:22:48.940259 02500000 ################################################################
10206 01:22:48.940767
10207 01:22:49.593604 02580000 ################################################################
10208 01:22:49.593742
10209 01:22:50.200984 02600000 ################################################################
10210 01:22:50.201130
10211 01:22:50.807130 02680000 ################################################################
10212 01:22:50.807279
10213 01:22:51.384950 02700000 ################################################################
10214 01:22:51.385097
10215 01:22:51.979834 02780000 ################################################################
10216 01:22:51.980388
10217 01:22:52.648214 02800000 ################################################################
10218 01:22:52.648718
10219 01:22:53.311238 02880000 ################################################################
10220 01:22:53.311746
10221 01:22:53.962918 02900000 ################################################################
10222 01:22:53.963056
10223 01:22:54.549767 02980000 ################################################################
10224 01:22:54.549910
10225 01:22:55.135366 02a00000 ################################################################
10226 01:22:55.135518
10227 01:22:55.804013 02a80000 ################################################################
10228 01:22:55.804531
10229 01:22:56.492232 02b00000 ################################################################
10230 01:22:56.492764
10231 01:22:57.082798 02b80000 ################################################################
10232 01:22:57.082937
10233 01:22:57.705843 02c00000 ################################################################
10234 01:22:57.706408
10235 01:22:58.320657 02c80000 ################################################################
10236 01:22:58.320806
10237 01:22:58.962261 02d00000 ################################################################
10238 01:22:58.962776
10239 01:22:59.637060 02d80000 ################################################################
10240 01:22:59.637574
10241 01:23:00.323163 02e00000 ################################################################
10242 01:23:00.323675
10243 01:23:01.007686 02e80000 ################################################################
10244 01:23:01.008224
10245 01:23:01.695002 02f00000 ################################################################
10246 01:23:01.695515
10247 01:23:02.351724 02f80000 ################################################################
10248 01:23:02.352263
10249 01:23:03.033202 03000000 ################################################################
10250 01:23:03.033772
10251 01:23:03.696021 03080000 ################################################################
10252 01:23:03.696537
10253 01:23:04.355925 03100000 ################################################################
10254 01:23:04.356435
10255 01:23:05.020191 03180000 ################################################################
10256 01:23:05.020336
10257 01:23:05.617117 03200000 ################################################################
10258 01:23:05.617682
10259 01:23:06.296237 03280000 ################################################################
10260 01:23:06.296807
10261 01:23:06.958364 03300000 ################################################################
10262 01:23:06.958877
10263 01:23:07.226304 03380000 ########################## done.
10264 01:23:07.226804
10265 01:23:07.229357 The bootfile was 54206966 bytes long.
10266 01:23:07.229900
10267 01:23:07.232606 Sending tftp read request... done.
10268 01:23:07.233033
10269 01:23:07.236342 Waiting for the transfer...
10270 01:23:07.236767
10271 01:23:07.237104 00000000 # done.
10272 01:23:07.237428
10273 01:23:07.242959 Command line loaded dynamically from TFTP file: 13468767/tftp-deploy-31iv6vbn/kernel/cmdline
10274 01:23:07.246773
10275 01:23:07.259644 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10276 01:23:07.260278
10277 01:23:07.260627 Loading FIT.
10278 01:23:07.260944
10279 01:23:07.262817 Image ramdisk-1 has 41247649 bytes.
10280 01:23:07.263293
10281 01:23:07.266308 Image fdt-1 has 47230 bytes.
10282 01:23:07.266828
10283 01:23:07.269285 Image kernel-1 has 12910050 bytes.
10284 01:23:07.269712
10285 01:23:07.275961 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10286 01:23:07.276480
10287 01:23:07.295766 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10288 01:23:07.296264
10289 01:23:07.299236 Choosing best match conf-1 for compat google,spherion-rev2.
10290 01:23:07.304520
10291 01:23:07.309100 Connected to device vid:did:rid of 1ae0:0028:00
10292 01:23:07.316121
10293 01:23:07.318552 tpm_get_response: command 0x17b, return code 0x0
10294 01:23:07.318981
10295 01:23:07.321939 ec_init: CrosEC protocol v3 supported (256, 248)
10296 01:23:07.326210
10297 01:23:07.329812 tpm_cleanup: add release locality here.
10298 01:23:07.330339
10299 01:23:07.330722 Shutting down all USB controllers.
10300 01:23:07.333053
10301 01:23:07.333472 Removing current net device
10302 01:23:07.333809
10303 01:23:07.339391 Exiting depthcharge with code 4 at timestamp: 101070645
10304 01:23:07.339822
10305 01:23:07.342677 LZMA decompressing kernel-1 to 0x821a6718
10306 01:23:07.343104
10307 01:23:07.346324 LZMA decompressing kernel-1 to 0x40000000
10308 01:23:08.940017
10309 01:23:08.940525 jumping to kernel
10310 01:23:08.942391 end: 2.2.4 bootloader-commands (duration 00:01:13) [common]
10311 01:23:08.942884 start: 2.2.5 auto-login-action (timeout 00:03:12) [common]
10312 01:23:08.943364 Setting prompt string to ['Linux version [0-9]']
10313 01:23:08.943728 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10314 01:23:08.944180 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10315 01:23:09.021625
10316 01:23:09.024841 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10317 01:23:09.028527 start: 2.2.5.1 login-action (timeout 00:03:12) [common]
10318 01:23:09.028989 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10319 01:23:09.029346 Setting prompt string to []
10320 01:23:09.029733 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10321 01:23:09.030100 Using line separator: #'\n'#
10322 01:23:09.030404 No login prompt set.
10323 01:23:09.030712 Parsing kernel messages
10324 01:23:09.030995 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10325 01:23:09.031512 [login-action] Waiting for messages, (timeout 00:03:12)
10326 01:23:09.031838 Waiting using forced prompt support (timeout 00:01:36)
10327 01:23:09.048647 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j174389-arm64-gcc-10-defconfig-arm64-chromebook-96m9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024
10328 01:23:09.051266 [ 0.000000] random: crng init done
10329 01:23:09.057971 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10330 01:23:09.061081 [ 0.000000] efi: UEFI not found.
10331 01:23:09.067741 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10332 01:23:09.077963 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10333 01:23:09.087459 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10334 01:23:09.094354 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10335 01:23:09.100433 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10336 01:23:09.107275 [ 0.000000] printk: bootconsole [mtk8250] enabled
10337 01:23:09.113949 [ 0.000000] NUMA: No NUMA configuration found
10338 01:23:09.120566 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10339 01:23:09.126726 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10340 01:23:09.127159 [ 0.000000] Zone ranges:
10341 01:23:09.133401 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10342 01:23:09.136845 [ 0.000000] DMA32 empty
10343 01:23:09.143510 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10344 01:23:09.146649 [ 0.000000] Movable zone start for each node
10345 01:23:09.149790 [ 0.000000] Early memory node ranges
10346 01:23:09.156358 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10347 01:23:09.162948 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10348 01:23:09.169779 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10349 01:23:09.176461 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10350 01:23:09.182934 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10351 01:23:09.189333 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10352 01:23:09.247078 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10353 01:23:09.253283 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10354 01:23:09.260216 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10355 01:23:09.263301 [ 0.000000] psci: probing for conduit method from DT.
10356 01:23:09.269739 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10357 01:23:09.273070 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10358 01:23:09.279588 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10359 01:23:09.283180 [ 0.000000] psci: SMC Calling Convention v1.2
10360 01:23:09.289371 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10361 01:23:09.293236 [ 0.000000] Detected VIPT I-cache on CPU0
10362 01:23:09.300088 [ 0.000000] CPU features: detected: GIC system register CPU interface
10363 01:23:09.306104 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10364 01:23:09.312555 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10365 01:23:09.318997 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10366 01:23:09.328868 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10367 01:23:09.335649 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10368 01:23:09.339363 [ 0.000000] alternatives: applying boot alternatives
10369 01:23:09.345540 [ 0.000000] Fallback order for Node 0: 0
10370 01:23:09.352409 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10371 01:23:09.355454 [ 0.000000] Policy zone: Normal
10372 01:23:09.369180 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10373 01:23:09.378206 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10374 01:23:09.391123 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10375 01:23:09.400740 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10376 01:23:09.407506 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10377 01:23:09.411080 <6>[ 0.000000] software IO TLB: area num 8.
10378 01:23:09.467683 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10379 01:23:09.617587 <6>[ 0.000000] Memory: 7924228K/8385536K available (18048K kernel code, 4118K rwdata, 22292K rodata, 8448K init, 616K bss, 428540K reserved, 32768K cma-reserved)
10380 01:23:09.623995 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10381 01:23:09.630217 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10382 01:23:09.633237 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10383 01:23:09.640642 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10384 01:23:09.646913 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10385 01:23:09.650422 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10386 01:23:09.660367 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10387 01:23:09.666965 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10388 01:23:09.673196 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10389 01:23:09.679391 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10390 01:23:09.683081 <6>[ 0.000000] GICv3: 608 SPIs implemented
10391 01:23:09.686474 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10392 01:23:09.692680 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10393 01:23:09.695870 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10394 01:23:09.703229 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10395 01:23:09.716318 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10396 01:23:09.729382 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10397 01:23:09.735780 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10398 01:23:09.744412 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10399 01:23:09.757403 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10400 01:23:09.763468 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10401 01:23:09.770254 <6>[ 0.009185] Console: colour dummy device 80x25
10402 01:23:09.780429 <6>[ 0.013904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10403 01:23:09.786946 <6>[ 0.024345] pid_max: default: 32768 minimum: 301
10404 01:23:09.790372 <6>[ 0.029246] LSM: Security Framework initializing
10405 01:23:09.796472 <6>[ 0.034185] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10406 01:23:09.806756 <6>[ 0.041998] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10407 01:23:09.816558 <6>[ 0.051413] cblist_init_generic: Setting adjustable number of callback queues.
10408 01:23:09.820232 <6>[ 0.058856] cblist_init_generic: Setting shift to 3 and lim to 1.
10409 01:23:09.829315 <6>[ 0.065235] cblist_init_generic: Setting adjustable number of callback queues.
10410 01:23:09.836404 <6>[ 0.072709] cblist_init_generic: Setting shift to 3 and lim to 1.
10411 01:23:09.839587 <6>[ 0.079109] rcu: Hierarchical SRCU implementation.
10412 01:23:09.845742 <6>[ 0.084155] rcu: Max phase no-delay instances is 1000.
10413 01:23:09.852797 <6>[ 0.091183] EFI services will not be available.
10414 01:23:09.856015 <6>[ 0.096166] smp: Bringing up secondary CPUs ...
10415 01:23:09.864787 <6>[ 0.101215] Detected VIPT I-cache on CPU1
10416 01:23:09.871440 <6>[ 0.101285] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10417 01:23:09.877583 <6>[ 0.101316] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10418 01:23:09.880744 <6>[ 0.101646] Detected VIPT I-cache on CPU2
10419 01:23:09.890945 <6>[ 0.101693] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10420 01:23:09.897644 <6>[ 0.101709] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10421 01:23:09.901021 <6>[ 0.101964] Detected VIPT I-cache on CPU3
10422 01:23:09.907353 <6>[ 0.102010] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10423 01:23:09.914050 <6>[ 0.102024] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10424 01:23:09.920560 <6>[ 0.102328] CPU features: detected: Spectre-v4
10425 01:23:09.923478 <6>[ 0.102334] CPU features: detected: Spectre-BHB
10426 01:23:09.926941 <6>[ 0.102339] Detected PIPT I-cache on CPU4
10427 01:23:09.933566 <6>[ 0.102396] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10428 01:23:09.940389 <6>[ 0.102414] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10429 01:23:09.947029 <6>[ 0.102705] Detected PIPT I-cache on CPU5
10430 01:23:09.953725 <6>[ 0.102767] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10431 01:23:09.960126 <6>[ 0.102783] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10432 01:23:09.964179 <6>[ 0.103062] Detected PIPT I-cache on CPU6
10433 01:23:09.970091 <6>[ 0.103127] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10434 01:23:09.979881 <6>[ 0.103143] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10435 01:23:09.983143 <6>[ 0.103439] Detected PIPT I-cache on CPU7
10436 01:23:09.989468 <6>[ 0.103504] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10437 01:23:09.996075 <6>[ 0.103520] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10438 01:23:09.999494 <6>[ 0.103566] smp: Brought up 1 node, 8 CPUs
10439 01:23:10.005996 <6>[ 0.244869] SMP: Total of 8 processors activated.
10440 01:23:10.012729 <6>[ 0.249791] CPU features: detected: 32-bit EL0 Support
10441 01:23:10.019347 <6>[ 0.255154] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10442 01:23:10.025629 <6>[ 0.263955] CPU features: detected: Common not Private translations
10443 01:23:10.032420 <6>[ 0.270431] CPU features: detected: CRC32 instructions
10444 01:23:10.039331 <6>[ 0.275783] CPU features: detected: RCpc load-acquire (LDAPR)
10445 01:23:10.042507 <6>[ 0.281742] CPU features: detected: LSE atomic instructions
10446 01:23:10.048884 <6>[ 0.287524] CPU features: detected: Privileged Access Never
10447 01:23:10.055839 <6>[ 0.293304] CPU features: detected: RAS Extension Support
10448 01:23:10.062031 <6>[ 0.298912] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10449 01:23:10.065214 <6>[ 0.306133] CPU: All CPU(s) started at EL2
10450 01:23:10.072100 <6>[ 0.310477] alternatives: applying system-wide alternatives
10451 01:23:10.082603 <6>[ 0.321337] devtmpfs: initialized
10452 01:23:10.097751 <6>[ 0.330270] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10453 01:23:10.104704 <6>[ 0.340233] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10454 01:23:10.111416 <6>[ 0.348484] pinctrl core: initialized pinctrl subsystem
10455 01:23:10.114462 <6>[ 0.355128] DMI not present or invalid.
10456 01:23:10.121266 <6>[ 0.359543] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10457 01:23:10.131272 <6>[ 0.366370] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10458 01:23:10.137757 <6>[ 0.373960] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10459 01:23:10.147864 <6>[ 0.382193] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10460 01:23:10.150777 <6>[ 0.390433] audit: initializing netlink subsys (disabled)
10461 01:23:10.160622 <5>[ 0.396129] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10462 01:23:10.166996 <6>[ 0.396826] thermal_sys: Registered thermal governor 'step_wise'
10463 01:23:10.173968 <6>[ 0.404096] thermal_sys: Registered thermal governor 'power_allocator'
10464 01:23:10.177480 <6>[ 0.410350] cpuidle: using governor menu
10465 01:23:10.184077 <6>[ 0.421306] NET: Registered PF_QIPCRTR protocol family
10466 01:23:10.190318 <6>[ 0.426794] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10467 01:23:10.196955 <6>[ 0.433896] ASID allocator initialised with 32768 entries
10468 01:23:10.199996 <6>[ 0.440465] Serial: AMBA PL011 UART driver
10469 01:23:10.210557 <4>[ 0.449206] Trying to register duplicate clock ID: 134
10470 01:23:10.264414 <6>[ 0.506802] KASLR enabled
10471 01:23:10.279418 <6>[ 0.514519] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10472 01:23:10.285694 <6>[ 0.521534] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10473 01:23:10.291941 <6>[ 0.528022] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10474 01:23:10.298342 <6>[ 0.535026] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10475 01:23:10.304986 <6>[ 0.541514] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10476 01:23:10.311302 <6>[ 0.548519] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10477 01:23:10.318100 <6>[ 0.555004] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10478 01:23:10.324615 <6>[ 0.562005] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10479 01:23:10.327832 <6>[ 0.569522] ACPI: Interpreter disabled.
10480 01:23:10.336867 <6>[ 0.575940] iommu: Default domain type: Translated
10481 01:23:10.343324 <6>[ 0.581052] iommu: DMA domain TLB invalidation policy: strict mode
10482 01:23:10.346568 <5>[ 0.587706] SCSI subsystem initialized
10483 01:23:10.353419 <6>[ 0.591868] usbcore: registered new interface driver usbfs
10484 01:23:10.359990 <6>[ 0.597598] usbcore: registered new interface driver hub
10485 01:23:10.363137 <6>[ 0.603149] usbcore: registered new device driver usb
10486 01:23:10.370870 <6>[ 0.609241] pps_core: LinuxPPS API ver. 1 registered
10487 01:23:10.380191 <6>[ 0.614437] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10488 01:23:10.383245 <6>[ 0.623781] PTP clock support registered
10489 01:23:10.386975 <6>[ 0.628026] EDAC MC: Ver: 3.0.0
10490 01:23:10.394235 <6>[ 0.633174] FPGA manager framework
10491 01:23:10.400957 <6>[ 0.636854] Advanced Linux Sound Architecture Driver Initialized.
10492 01:23:10.404248 <6>[ 0.643624] vgaarb: loaded
10493 01:23:10.410954 <6>[ 0.646791] clocksource: Switched to clocksource arch_sys_counter
10494 01:23:10.414217 <5>[ 0.653239] VFS: Disk quotas dquot_6.6.0
10495 01:23:10.420596 <6>[ 0.657427] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10496 01:23:10.424021 <6>[ 0.664617] pnp: PnP ACPI: disabled
10497 01:23:10.432410 <6>[ 0.671324] NET: Registered PF_INET protocol family
10498 01:23:10.442384 <6>[ 0.676928] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10499 01:23:10.453684 <6>[ 0.689249] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10500 01:23:10.464010 <6>[ 0.698063] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10501 01:23:10.470383 <6>[ 0.706034] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10502 01:23:10.480110 <6>[ 0.714733] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10503 01:23:10.486876 <6>[ 0.724478] TCP: Hash tables configured (established 65536 bind 65536)
10504 01:23:10.493139 <6>[ 0.731341] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10505 01:23:10.503114 <6>[ 0.738541] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10506 01:23:10.509540 <6>[ 0.746240] NET: Registered PF_UNIX/PF_LOCAL protocol family
10507 01:23:10.516786 <6>[ 0.752402] RPC: Registered named UNIX socket transport module.
10508 01:23:10.519304 <6>[ 0.758558] RPC: Registered udp transport module.
10509 01:23:10.525830 <6>[ 0.763491] RPC: Registered tcp transport module.
10510 01:23:10.532493 <6>[ 0.768422] RPC: Registered tcp NFSv4.1 backchannel transport module.
10511 01:23:10.535501 <6>[ 0.775089] PCI: CLS 0 bytes, default 64
10512 01:23:10.538988 <6>[ 0.779490] Unpacking initramfs...
10513 01:23:10.555502 <6>[ 0.791407] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10514 01:23:10.566084 <6>[ 0.800072] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10515 01:23:10.569302 <6>[ 0.808932] kvm [1]: IPA Size Limit: 40 bits
10516 01:23:10.575591 <6>[ 0.813461] kvm [1]: GICv3: no GICV resource entry
10517 01:23:10.579287 <6>[ 0.818482] kvm [1]: disabling GICv2 emulation
10518 01:23:10.585364 <6>[ 0.823169] kvm [1]: GIC system register CPU interface enabled
10519 01:23:10.591766 <6>[ 0.830838] kvm [1]: vgic interrupt IRQ18
10520 01:23:10.595229 <6>[ 0.835204] kvm [1]: VHE mode initialized successfully
10521 01:23:10.602737 <5>[ 0.841598] Initialise system trusted keyrings
10522 01:23:10.609021 <6>[ 0.846411] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10523 01:23:10.617611 <6>[ 0.856373] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10524 01:23:10.623950 <5>[ 0.862757] NFS: Registering the id_resolver key type
10525 01:23:10.627232 <5>[ 0.868058] Key type id_resolver registered
10526 01:23:10.633799 <5>[ 0.872470] Key type id_legacy registered
10527 01:23:10.640366 <6>[ 0.876747] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10528 01:23:10.647095 <6>[ 0.883669] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10529 01:23:10.653592 <6>[ 0.891377] 9p: Installing v9fs 9p2000 file system support
10530 01:23:10.690355 <5>[ 0.929160] Key type asymmetric registered
10531 01:23:10.693877 <5>[ 0.933490] Asymmetric key parser 'x509' registered
10532 01:23:10.703812 <6>[ 0.938623] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10533 01:23:10.706706 <6>[ 0.946239] io scheduler mq-deadline registered
10534 01:23:10.710431 <6>[ 0.951014] io scheduler kyber registered
10535 01:23:10.729127 <6>[ 0.967987] EINJ: ACPI disabled.
10536 01:23:10.761177 <4>[ 0.993450] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10537 01:23:10.771199 <4>[ 1.004061] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10538 01:23:10.785881 <6>[ 1.024715] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10539 01:23:10.793429 <6>[ 1.032584] printk: console [ttyS0] disabled
10540 01:23:10.821899 <6>[ 1.057212] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10541 01:23:10.827925 <6>[ 1.066681] printk: console [ttyS0] enabled
10542 01:23:10.831500 <6>[ 1.066681] printk: console [ttyS0] enabled
10543 01:23:10.838043 <6>[ 1.075575] printk: bootconsole [mtk8250] disabled
10544 01:23:10.841790 <6>[ 1.075575] printk: bootconsole [mtk8250] disabled
10545 01:23:10.848016 <6>[ 1.086576] SuperH (H)SCI(F) driver initialized
10546 01:23:10.852121 <6>[ 1.091833] msm_serial: driver initialized
10547 01:23:10.864812 <6>[ 1.100718] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10548 01:23:10.875022 <6>[ 1.109266] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10549 01:23:10.881566 <6>[ 1.117808] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10550 01:23:10.891950 <6>[ 1.126434] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10551 01:23:10.898146 <6>[ 1.135139] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10552 01:23:10.908424 <6>[ 1.143858] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10553 01:23:10.918524 <6>[ 1.152398] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10554 01:23:10.925011 <6>[ 1.161191] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10555 01:23:10.934987 <6>[ 1.169732] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10556 01:23:10.945767 <6>[ 1.185209] loop: module loaded
10557 01:23:10.952604 <6>[ 1.191313] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10558 01:23:10.975590 <4>[ 1.214537] mtk-pmic-keys: Failed to locate of_node [id: -1]
10559 01:23:10.982540 <6>[ 1.221378] megasas: 07.719.03.00-rc1
10560 01:23:10.992105 <6>[ 1.231137] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10561 01:23:10.999597 <6>[ 1.238200] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10562 01:23:11.016474 <6>[ 1.254768] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10563 01:23:11.071915 <6>[ 1.304370] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10564 01:23:12.273699 <6>[ 2.513216] Freeing initrd memory: 40276K
10565 01:23:12.285651 <6>[ 2.524911] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10566 01:23:12.296911 <6>[ 2.536090] tun: Universal TUN/TAP device driver, 1.6
10567 01:23:12.300376 <6>[ 2.542151] thunder_xcv, ver 1.0
10568 01:23:12.303603 <6>[ 2.545659] thunder_bgx, ver 1.0
10569 01:23:12.306856 <6>[ 2.549157] nicpf, ver 1.0
10570 01:23:12.317199 <6>[ 2.553186] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10571 01:23:12.321029 <6>[ 2.560661] hns3: Copyright (c) 2017 Huawei Corporation.
10572 01:23:12.323959 <6>[ 2.566252] hclge is initializing
10573 01:23:12.331091 <6>[ 2.569833] e1000: Intel(R) PRO/1000 Network Driver
10574 01:23:12.337309 <6>[ 2.574963] e1000: Copyright (c) 1999-2006 Intel Corporation.
10575 01:23:12.340739 <6>[ 2.580975] e1000e: Intel(R) PRO/1000 Network Driver
10576 01:23:12.347433 <6>[ 2.586191] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10577 01:23:12.353706 <6>[ 2.592375] igb: Intel(R) Gigabit Ethernet Network Driver
10578 01:23:12.360441 <6>[ 2.598025] igb: Copyright (c) 2007-2014 Intel Corporation.
10579 01:23:12.366894 <6>[ 2.603862] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10580 01:23:12.373344 <6>[ 2.610379] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10581 01:23:12.376651 <6>[ 2.616842] sky2: driver version 1.30
10582 01:23:12.383718 <6>[ 2.621837] VFIO - User Level meta-driver version: 0.3
10583 01:23:12.390816 <6>[ 2.630086] usbcore: registered new interface driver usb-storage
10584 01:23:12.397413 <6>[ 2.636551] usbcore: registered new device driver onboard-usb-hub
10585 01:23:12.406776 <6>[ 2.645697] mt6397-rtc mt6359-rtc: registered as rtc0
10586 01:23:12.416388 <6>[ 2.651162] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-23T01:23:12 UTC (1713835392)
10587 01:23:12.419325 <6>[ 2.660728] i2c_dev: i2c /dev entries driver
10588 01:23:12.436748 <6>[ 2.672586] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10589 01:23:12.443274 <4>[ 2.681318] cpu cpu0: supply cpu not found, using dummy regulator
10590 01:23:12.450055 <4>[ 2.687741] cpu cpu1: supply cpu not found, using dummy regulator
10591 01:23:12.456549 <4>[ 2.694149] cpu cpu2: supply cpu not found, using dummy regulator
10592 01:23:12.462799 <4>[ 2.700548] cpu cpu3: supply cpu not found, using dummy regulator
10593 01:23:12.469743 <4>[ 2.706959] cpu cpu4: supply cpu not found, using dummy regulator
10594 01:23:12.476353 <4>[ 2.713360] cpu cpu5: supply cpu not found, using dummy regulator
10595 01:23:12.482512 <4>[ 2.719758] cpu cpu6: supply cpu not found, using dummy regulator
10596 01:23:12.489461 <4>[ 2.726156] cpu cpu7: supply cpu not found, using dummy regulator
10597 01:23:12.507430 <6>[ 2.746808] cpu cpu0: EM: created perf domain
10598 01:23:12.510658 <6>[ 2.751744] cpu cpu4: EM: created perf domain
10599 01:23:12.518563 <6>[ 2.757373] sdhci: Secure Digital Host Controller Interface driver
10600 01:23:12.524957 <6>[ 2.763805] sdhci: Copyright(c) Pierre Ossman
10601 01:23:12.531921 <6>[ 2.768764] Synopsys Designware Multimedia Card Interface Driver
10602 01:23:12.538077 <6>[ 2.775394] sdhci-pltfm: SDHCI platform and OF driver helper
10603 01:23:12.541476 <6>[ 2.775466] mmc0: CQHCI version 5.10
10604 01:23:12.548019 <6>[ 2.785759] ledtrig-cpu: registered to indicate activity on CPUs
10605 01:23:12.554798 <6>[ 2.792918] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10606 01:23:12.561223 <6>[ 2.799980] usbcore: registered new interface driver usbhid
10607 01:23:12.564485 <6>[ 2.805808] usbhid: USB HID core driver
10608 01:23:12.571017 <6>[ 2.810012] spi_master spi0: will run message pump with realtime priority
10609 01:23:12.618890 <6>[ 2.851581] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10610 01:23:12.638694 <6>[ 2.867407] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10611 01:23:12.645157 <6>[ 2.882333] cros-ec-spi spi0.0: Chrome EC device registered
10612 01:23:12.648264 <6>[ 2.888416] mmc0: Command Queue Engine enabled
10613 01:23:12.655665 <6>[ 2.893200] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10614 01:23:12.662015 <6>[ 2.900482] mmcblk0: mmc0:0001 DA4128 116 GiB
10615 01:23:12.672064 <6>[ 2.902702] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10616 01:23:12.675494 <6>[ 2.911325] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10617 01:23:12.681733 <6>[ 2.915661] NET: Registered PF_PACKET protocol family
10618 01:23:12.688019 <6>[ 2.921968] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10619 01:23:12.691328 <6>[ 2.925805] 9pnet: Installing 9P2000 support
10620 01:23:12.695613 <6>[ 2.931576] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10621 01:23:12.701828 <5>[ 2.935498] Key type dns_resolver registered
10622 01:23:12.708019 <6>[ 2.941351] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10623 01:23:12.711710 <6>[ 2.945741] registered taskstats version 1
10624 01:23:12.717741 <5>[ 2.956147] Loading compiled-in X.509 certificates
10625 01:23:12.745945 <4>[ 2.978207] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10626 01:23:12.755462 <4>[ 2.988914] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10627 01:23:12.762745 <3>[ 2.999440] debugfs: File 'uA_load' in directory '/' already present!
10628 01:23:12.769514 <3>[ 3.006139] debugfs: File 'min_uV' in directory '/' already present!
10629 01:23:12.775971 <3>[ 3.012806] debugfs: File 'max_uV' in directory '/' already present!
10630 01:23:12.781843 <3>[ 3.019419] debugfs: File 'constraint_flags' in directory '/' already present!
10631 01:23:12.793256 <3>[ 3.029037] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10632 01:23:12.802552 <6>[ 3.041298] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10633 01:23:12.809129 <6>[ 3.048100] xhci-mtk 11200000.usb: xHCI Host Controller
10634 01:23:12.815245 <6>[ 3.053607] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10635 01:23:12.825417 <6>[ 3.061452] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10636 01:23:12.832322 <6>[ 3.070891] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10637 01:23:12.838892 <6>[ 3.076978] xhci-mtk 11200000.usb: xHCI Host Controller
10638 01:23:12.845561 <6>[ 3.082458] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10639 01:23:12.852106 <6>[ 3.090104] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10640 01:23:12.858662 <6>[ 3.097924] hub 1-0:1.0: USB hub found
10641 01:23:12.862246 <6>[ 3.101955] hub 1-0:1.0: 1 port detected
10642 01:23:12.871778 <6>[ 3.106225] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10643 01:23:12.875406 <6>[ 3.115079] hub 2-0:1.0: USB hub found
10644 01:23:12.878680 <6>[ 3.119101] hub 2-0:1.0: 1 port detected
10645 01:23:12.887769 <6>[ 3.126568] mtk-msdc 11f70000.mmc: Got CD GPIO
10646 01:23:12.898380 <6>[ 3.133506] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10647 01:23:12.905197 <6>[ 3.141549] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10648 01:23:12.914312 <4>[ 3.149453] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10649 01:23:12.924326 <6>[ 3.158981] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10650 01:23:12.930948 <6>[ 3.167062] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10651 01:23:12.937305 <6>[ 3.175066] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10652 01:23:12.947111 <6>[ 3.182987] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10653 01:23:12.953631 <6>[ 3.190805] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10654 01:23:12.963707 <6>[ 3.198622] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10655 01:23:12.974184 <6>[ 3.209077] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10656 01:23:12.980765 <6>[ 3.217436] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10657 01:23:12.989821 <6>[ 3.225777] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10658 01:23:12.999674 <6>[ 3.234122] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10659 01:23:13.006642 <6>[ 3.242460] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10660 01:23:13.016556 <6>[ 3.250805] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10661 01:23:13.022857 <6>[ 3.259142] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10662 01:23:13.033385 <6>[ 3.267480] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10663 01:23:13.039229 <6>[ 3.275818] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10664 01:23:13.049196 <6>[ 3.284154] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10665 01:23:13.055851 <6>[ 3.292491] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10666 01:23:13.065759 <6>[ 3.300830] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10667 01:23:13.072168 <6>[ 3.309167] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10668 01:23:13.082375 <6>[ 3.317506] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10669 01:23:13.088560 <6>[ 3.325844] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10670 01:23:13.095584 <6>[ 3.334646] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10671 01:23:13.102693 <6>[ 3.341827] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10672 01:23:13.109682 <6>[ 3.348579] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10673 01:23:13.119190 <6>[ 3.355350] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10674 01:23:13.125814 <6>[ 3.362274] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10675 01:23:13.132762 <6>[ 3.369121] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10676 01:23:13.142359 <6>[ 3.378253] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10677 01:23:13.152474 <6>[ 3.387372] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10678 01:23:13.162987 <6>[ 3.396665] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10679 01:23:13.172227 <6>[ 3.406134] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10680 01:23:13.182273 <6>[ 3.415609] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10681 01:23:13.188628 <6>[ 3.424728] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10682 01:23:13.198840 <6>[ 3.434195] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10683 01:23:13.208637 <6>[ 3.443316] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10684 01:23:13.218532 <6>[ 3.452611] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10685 01:23:13.228632 <6>[ 3.462771] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10686 01:23:13.239058 <6>[ 3.474815] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10687 01:23:13.291132 <6>[ 3.527063] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10688 01:23:13.445640 <6>[ 3.685066] hub 1-1:1.0: USB hub found
10689 01:23:13.448687 <6>[ 3.689574] hub 1-1:1.0: 4 ports detected
10690 01:23:13.458912 <6>[ 3.698346] hub 1-1:1.0: USB hub found
10691 01:23:13.462698 <6>[ 3.702709] hub 1-1:1.0: 4 ports detected
10692 01:23:13.571738 <6>[ 3.807431] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10693 01:23:13.597711 <6>[ 3.836933] hub 2-1:1.0: USB hub found
10694 01:23:13.600879 <6>[ 3.841422] hub 2-1:1.0: 3 ports detected
10695 01:23:13.610245 <6>[ 3.849524] hub 2-1:1.0: USB hub found
10696 01:23:13.613131 <6>[ 3.853968] hub 2-1:1.0: 3 ports detected
10697 01:23:13.787212 <6>[ 4.023105] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10698 01:23:13.919662 <6>[ 4.158955] hub 1-1.4:1.0: USB hub found
10699 01:23:13.922823 <6>[ 4.163611] hub 1-1.4:1.0: 2 ports detected
10700 01:23:13.931745 <6>[ 4.171383] hub 1-1.4:1.0: USB hub found
10701 01:23:13.935469 <6>[ 4.175935] hub 1-1.4:1.0: 2 ports detected
10702 01:23:14.003696 <6>[ 4.239236] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10703 01:23:14.231129 <6>[ 4.467110] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10704 01:23:14.422971 <6>[ 4.659080] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10705 01:23:25.516561 <6>[ 15.760106] ALSA device list:
10706 01:23:25.522591 <6>[ 15.763404] No soundcards found.
10707 01:23:25.530743 <6>[ 15.771370] Freeing unused kernel memory: 8448K
10708 01:23:25.534033 <6>[ 15.776924] Run /init as init process
10709 01:23:25.565626 <6>[ 15.806084] NET: Registered PF_INET6 protocol family
10710 01:23:25.572480 <6>[ 15.812381] Segment Routing with IPv6
10711 01:23:25.575376 <6>[ 15.816319] In-situ OAM (IOAM) with IPv6
10712 01:23:25.620642 <30>[ 15.831129] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10713 01:23:25.622945 <30>[ 15.864326] systemd[1]: Detected architecture arm64.
10714 01:23:25.623411
10715 01:23:25.630333 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10716 01:23:25.630892
10717 01:23:25.631258
10718 01:23:25.642539 <30>[ 15.883232] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10719 01:23:25.779114 <30>[ 16.016466] systemd[1]: Queued start job for default target graphical.target.
10720 01:23:25.815962 <30>[ 16.052815] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10721 01:23:25.822173 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10722 01:23:25.822721
10723 01:23:25.842780 <30>[ 16.079801] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10724 01:23:25.852276 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10725 01:23:25.852831
10726 01:23:25.870849 <30>[ 16.108062] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10727 01:23:25.880205 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10728 01:23:25.880758
10729 01:23:25.899159 <30>[ 16.136248] systemd[1]: Created slice user.slice - User and Session Slice.
10730 01:23:25.905281 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10731 01:23:25.905837
10732 01:23:25.925598 <30>[ 16.159147] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10733 01:23:25.932085 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10734 01:23:25.932658
10735 01:23:25.954141 <30>[ 16.187630] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10736 01:23:25.960498 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10737 01:23:25.961068
10738 01:23:25.987830 <30>[ 16.215458] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10739 01:23:25.998125 <30>[ 16.235400] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10740 01:23:26.004452 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10741 01:23:26.005073
10742 01:23:26.021890 <30>[ 16.259398] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10743 01:23:26.032046 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10744 01:23:26.032615
10745 01:23:26.050549 <30>[ 16.287528] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10746 01:23:26.060388 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10747 01:23:26.060986
10748 01:23:26.074944 <30>[ 16.315620] systemd[1]: Reached target paths.target - Path Units.
10749 01:23:26.082195 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10750 01:23:26.084882
10751 01:23:26.102548 <30>[ 16.339522] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10752 01:23:26.108436 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10753 01:23:26.108908
10754 01:23:26.122550 <30>[ 16.363122] systemd[1]: Reached target slices.target - Slice Units.
10755 01:23:26.132871 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10756 01:23:26.133439
10757 01:23:26.146841 <30>[ 16.387571] systemd[1]: Reached target swap.target - Swaps.
10758 01:23:26.153110 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10759 01:23:26.153662
10760 01:23:26.174049 <30>[ 16.411227] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10761 01:23:26.183786 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10762 01:23:26.184424
10763 01:23:26.201821 <30>[ 16.439600] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10764 01:23:26.211778 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10765 01:23:26.212398
10766 01:23:26.232050 <30>[ 16.469332] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10767 01:23:26.242225 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10768 01:23:26.242982
10769 01:23:26.258474 <30>[ 16.495922] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10770 01:23:26.268674 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10771 01:23:26.269246
10772 01:23:26.286539 <30>[ 16.523723] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10773 01:23:26.292727 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10774 01:23:26.293194
10775 01:23:26.310429 <30>[ 16.547796] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10776 01:23:26.320389 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10777 01:23:26.320957
10778 01:23:26.339339 <30>[ 16.576494] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10779 01:23:26.348803 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10780 01:23:26.349440
10781 01:23:26.366577 <30>[ 16.603593] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10782 01:23:26.375950 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10783 01:23:26.376528
10784 01:23:26.434044 <30>[ 16.671350] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10785 01:23:26.440343 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10786 01:23:26.440883
10787 01:23:26.453210 <30>[ 16.690831] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10788 01:23:26.459984 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10789 01:23:26.460425
10790 01:23:26.481461 <30>[ 16.719134] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10791 01:23:26.487812 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10792 01:23:26.488317
10793 01:23:26.512114 <30>[ 16.743343] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10794 01:23:26.526491 <30>[ 16.763764] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10795 01:23:26.536043 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10796 01:23:26.536632
10797 01:23:26.578111 <30>[ 16.815525] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10798 01:23:26.585069 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10799 01:23:26.585497
10800 01:23:26.610729 <30>[ 16.848096] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10801 01:23:26.624375 Starting [0;1;39mmodpr<6>[ 16.859294] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10802 01:23:26.627924 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10803 01:23:26.628499
10804 01:23:26.651391 <30>[ 16.888664] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10805 01:23:26.658014 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10806 01:23:26.658570
10807 01:23:26.714437 <30>[ 16.951669] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10808 01:23:26.723816 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10809 01:23:26.724405
10810 01:23:26.746539 <30>[ 16.984091] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10811 01:23:26.753288 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10812 01:23:26.753849
10813 01:23:26.781885 <30>[ 17.019667] systemd[1]: Starting systemd-journald.service - Journal Service...
10814 01:23:26.788693 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10815 01:23:26.789156
10816 01:23:26.808455 <30>[ 17.046265] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10817 01:23:26.815674 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10818 01:23:26.816309
10819 01:23:26.841803 <30>[ 17.076264] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10820 01:23:26.848848 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10821 01:23:26.849413
10822 01:23:26.868748 <30>[ 17.106145] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10823 01:23:26.878282 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10824 01:23:26.878834
10825 01:23:26.900813 <30>[ 17.138301] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10826 01:23:26.907345 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10827 01:23:26.907955
10828 01:23:26.931831 <30>[ 17.168959] systemd[1]: Started systemd-journald.service - Journal Service.
10829 01:23:26.938112 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10830 01:23:26.938673
10831 01:23:26.960427 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10832 01:23:26.960987
10833 01:23:26.978161 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10834 01:23:26.978713
10835 01:23:26.997893 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10836 01:23:26.998446
10837 01:23:27.014616 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10838 01:23:27.015202
10839 01:23:27.041470 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10840 01:23:27.042032
10841 01:23:27.064227 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10842 01:23:27.064790
10843 01:23:27.085228 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10844 01:23:27.085788
10845 01:23:27.105552 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10846 01:23:27.106125
10847 01:23:27.123240 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10848 01:23:27.123780
10849 01:23:27.143970 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10850 01:23:27.144528
10851 01:23:27.163372 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10852 01:23:27.163881
10853 01:23:27.185283 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10854 01:23:27.185852
10855 01:23:27.198487 See 'systemctl status systemd-remount-fs.service' for details.
10856 01:23:27.199047
10857 01:23:27.209014 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10858 01:23:27.209563
10859 01:23:27.228103 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10860 01:23:27.228661
10861 01:23:27.286585 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10862 01:23:27.287148
10863 01:23:27.308495 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10864 01:23:27.309063
10865 01:23:27.319654 <46>[ 17.556908] systemd-journald[180]: Received client request to flush runtime journal.
10866 01:23:27.331254 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10867 01:23:27.331828
10868 01:23:27.352843 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10869 01:23:27.353396
10870 01:23:27.374765 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10871 01:23:27.375330
10872 01:23:27.400418 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10873 01:23:27.400967
10874 01:23:27.419747 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10875 01:23:27.420354
10876 01:23:27.439442 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10877 01:23:27.440053
10878 01:23:27.459593 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10879 01:23:27.460208
10880 01:23:27.478075 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10881 01:23:27.478638
10882 01:23:27.525817 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10883 01:23:27.526370
10884 01:23:27.549274 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10885 01:23:27.549851
10886 01:23:27.566056 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10887 01:23:27.566625
10888 01:23:27.581323 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10889 01:23:27.581748
10890 01:23:27.630479 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10891 01:23:27.631021
10892 01:23:27.654267 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10893 01:23:27.654785
10894 01:23:27.679402 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10895 01:23:27.679986
10896 01:23:27.700634 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10897 01:23:27.701197
10898 01:23:27.745397 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10899 01:23:27.745918
10900 01:23:27.919731 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10901 01:23:27.920360
10902 01:23:27.948881 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10903 01:23:27.949451
10904 01:23:27.980582 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10905 01:23:27.981153
10906 01:23:28.000015 <5>[ 18.237788] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10907 01:23:28.019539 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10908 01:23:28.020137
10909 01:23:28.040414 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10910 01:23:28.040991
10911 01:23:28.053944 <5>[ 18.291545] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10912 01:23:28.060716 <5>[ 18.299650] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10913 01:23:28.073900 [[0;32m OK [<4>[ 18.309123] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10914 01:23:28.080783 0m] Reached targ<6>[ 18.319727] cfg80211: failed to load regulatory.db
10915 01:23:28.084377 et [0;1;39msysinit.target[0m - System Initialization.
10916 01:23:28.084903
10917 01:23:28.095840 <6>[ 18.333537] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10918 01:23:28.102449 <6>[ 18.341412] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10919 01:23:28.112654 <6>[ 18.346315] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10920 01:23:28.119220 <6>[ 18.350642] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10921 01:23:28.132310 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary <6>[ 18.372707] remoteproc remoteproc0: scp is available
10922 01:23:28.142510 <3>[ 18.377379] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10923 01:23:28.143015 Directories.
10924 01:23:28.143348
10925 01:23:28.149220 <6>[ 18.378996] remoteproc remoteproc0: powering up scp
10926 01:23:28.156131 <3>[ 18.386926] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10927 01:23:28.165672 <6>[ 18.393280] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10928 01:23:28.172328 <3>[ 18.401363] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10929 01:23:28.178383 <6>[ 18.410320] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10930 01:23:28.185156 <6>[ 18.414874] usbcore: registered new device driver r8152-cfgselector
10931 01:23:28.192281 <3>[ 18.421419] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10932 01:23:28.197986 <6>[ 18.427685] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10933 01:23:28.208544 <3>[ 18.430111] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10934 01:23:28.215053 <4>[ 18.439784] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10935 01:23:28.224431 <3>[ 18.445835] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10936 01:23:28.230970 <3>[ 18.445841] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10937 01:23:28.238578 <3>[ 18.445844] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10938 01:23:28.248596 <4>[ 18.456596] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10939 01:23:28.252159 <4>[ 18.456596] Fallback method does not support PEC.
10940 01:23:28.258622 <6>[ 18.468607] mc: Linux media interface: v0.10
10941 01:23:28.264987 <4>[ 18.472049] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10942 01:23:28.275636 <3>[ 18.472090] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10943 01:23:28.281187 <3>[ 18.476895] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10944 01:23:28.288304 <3>[ 18.476915] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10945 01:23:28.298475 <3>[ 18.476921] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10946 01:23:28.305665 <3>[ 18.484379] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10947 01:23:28.315550 <3>[ 18.486066] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 01:23:28.321954 <6>[ 18.492769] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10949 01:23:28.328084 <6>[ 18.492784] pci_bus 0000:00: root bus resource [bus 00-ff]
10950 01:23:28.335542 <6>[ 18.492806] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10951 01:23:28.344841 <6>[ 18.492813] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10952 01:23:28.351806 <6>[ 18.492916] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10953 01:23:28.358600 <6>[ 18.492950] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10954 01:23:28.361839 <6>[ 18.493071] pci 0000:00:00.0: supports D1 D2
10955 01:23:28.372132 <6>[ 18.493077] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10956 01:23:28.378676 <3>[ 18.499401] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10957 01:23:28.385270 <6>[ 18.518518] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10958 01:23:28.395243 <3>[ 18.519342] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10959 01:23:28.401809 <3>[ 18.519368] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10960 01:23:28.411599 <3>[ 18.519373] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10961 01:23:28.417825 <3>[ 18.524131] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10962 01:23:28.428253 <6>[ 18.527494] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10963 01:23:28.434669 <6>[ 18.531048] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10964 01:23:28.444906 <6>[ 18.535721] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10965 01:23:28.454919 <3>[ 18.540817] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 01:23:28.461498 <3>[ 18.541602] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10967 01:23:28.470709 <6>[ 18.544163] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10968 01:23:28.478227 <6>[ 18.548757] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10969 01:23:28.485109 <6>[ 18.548767] remoteproc remoteproc0: remote processor scp is now up
10970 01:23:28.492716 <6>[ 18.548773] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10971 01:23:28.495939 <6>[ 18.562124] videodev: Linux video capture interface: v2.00
10972 01:23:28.505854 <6>[ 18.568451] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10973 01:23:28.513029 <6>[ 18.595249] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10974 01:23:28.523161 <6>[ 18.597414] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10975 01:23:28.529712 <3>[ 18.604769] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10976 01:23:28.539568 <6>[ 18.607533] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10977 01:23:28.543047 <6>[ 18.609937] pci 0000:01:00.0: supports D1 D2
10978 01:23:28.552978 <6>[ 18.633463] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10979 01:23:28.559652 <6>[ 18.640671] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10980 01:23:28.563552 <6>[ 18.641443] Bluetooth: Core ver 2.22
10981 01:23:28.572818 <4>[ 18.652374] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10982 01:23:28.580236 <6>[ 18.652656] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10983 01:23:28.586351 <6>[ 18.654922] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10984 01:23:28.596599 <6>[ 18.654962] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10985 01:23:28.603345 <6>[ 18.654965] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10986 01:23:28.610636 <6>[ 18.654975] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10987 01:23:28.620387 <6>[ 18.654988] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10988 01:23:28.627027 <6>[ 18.655000] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10989 01:23:28.634124 <6>[ 18.655012] pci 0000:00:00.0: PCI bridge to [bus 01]
10990 01:23:28.640926 <6>[ 18.655018] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10991 01:23:28.647662 <6>[ 18.655167] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10992 01:23:28.653994 <6>[ 18.656023] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10993 01:23:28.657837 <6>[ 18.656995] NET: Registered PF_BLUETOOTH protocol family
10994 01:23:28.664475 <6>[ 18.657380] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10995 01:23:28.671303 <4>[ 18.665654] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10996 01:23:28.678546 <6>[ 18.675112] Bluetooth: HCI device and connection manager initialized
10997 01:23:28.685082 <6>[ 18.675144] Bluetooth: HCI socket layer initialized
10998 01:23:28.691631 <6>[ 18.676478] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10999 01:23:28.702061 <6>[ 18.678971] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11000 01:23:28.708588 <6>[ 18.679115] usbcore: registered new interface driver uvcvideo
11001 01:23:28.715769 <6>[ 18.708935] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11002 01:23:28.722500 <6>[ 18.715813] Bluetooth: L2CAP socket layer initialized
11003 01:23:28.725481 <6>[ 18.730957] r8152 2-1.3:1.0 eth0: v1.12.13
11004 01:23:28.735386 <3>[ 18.733652] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11005 01:23:28.741735 <3>[ 18.734443] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11006 01:23:28.751480 <3>[ 18.735243] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11007 01:23:28.758334 <6>[ 18.737793] Bluetooth: SCO socket layer initialized
11008 01:23:28.764762 <3>[ 18.760720] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11009 01:23:28.771244 <6>[ 18.768055] usbcore: registered new interface driver r8152
11010 01:23:28.777991 <6>[ 18.771557] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11011 01:23:28.784622 <6>[ 18.771650] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11012 01:23:28.791299 <6>[ 18.785830] usbcore: registered new interface driver btusb
11013 01:23:28.800840 <4>[ 18.786436] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11014 01:23:28.808115 <3>[ 18.786443] Bluetooth: hci0: Failed to load firmware file (-2)
11015 01:23:28.814688 <3>[ 18.786445] Bluetooth: hci0: Failed to set up firmware (-2)
11016 01:23:28.824715 <4>[ 18.786447] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11017 01:23:28.827631 <6>[ 18.790853] mt7921e 0000:01:00.0: ASIC revision: 79610010
11018 01:23:28.837274 <3>[ 18.808344] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11019 01:23:28.844322 <6>[ 18.817872] usbcore: registered new interface driver cdc_ether
11020 01:23:28.854262 <3>[ 18.847930] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11021 01:23:28.857246 <6>[ 18.857040] usbcore: registered new interface driver r8153_ecm
11022 01:23:28.867049 <6>[ 18.904909] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11023 01:23:28.870460 <6>[ 18.904909]
11024 01:23:28.873506 <6>[ 18.943536] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
11025 01:23:28.883621 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11026 01:23:28.884087
11027 01:23:28.901701 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11028 01:23:28.902319
11029 01:23:28.917930 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11030 01:23:28.918449
11031 01:23:28.938481 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11032 01:23:28.939050
11033 01:23:28.961581 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11034 01:23:28.962142
11035 01:23:28.973531 <6>[ 19.211458] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11036 01:23:28.980288 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11037 01:23:28.980829
11038 01:23:29.031579 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11039 01:23:29.032230
11040 01:23:29.059390 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11041 01:23:29.059982
11042 01:23:29.079250 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11043 01:23:29.079812
11044 01:23:29.099343 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11045 01:23:29.099950
11046 01:23:29.157995 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11047 01:23:29.158557
11048 01:23:29.181985 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11049 01:23:29.182569
11050 01:23:29.197807 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11051 01:23:29.198357
11052 01:23:29.215207 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11053 01:23:29.215778
11054 01:23:29.234806 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11055 01:23:29.235372
11056 01:23:29.287257 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11057 01:23:29.287856
11058 01:23:29.312058 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11059 01:23:29.312634
11060 01:23:29.335205 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11061 01:23:29.335777
11062 01:23:29.357068 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11063 01:23:29.357634
11064 01:23:29.403787 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11065 01:23:29.404629
11066 01:23:29.443865 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11067 01:23:29.444466
11068 01:23:29.462507 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11069 01:23:29.463069
11070 01:23:29.478513 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11071 01:23:29.479075
11072 01:23:29.498487 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11073 01:23:29.499047
11074 01:23:29.550890 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11075 01:23:29.551526
11076 01:23:29.576088 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11077 01:23:29.576591
11078 01:23:29.598213 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11079 01:23:29.598708
11080 01:23:29.639431 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11081 01:23:29.640035
11082 01:23:29.688291
11083 01:23:29.688889
11084 01:23:29.691973 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11085 01:23:29.692595
11086 01:23:29.695178 debian-bookworm-arm64 login: root (automatic login)
11087 01:23:29.695732
11088 01:23:29.696267
11089 01:23:29.714688 Linux debian-bookworm-arm64 6.1.86-cip19 #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024 aarch64
11090 01:23:29.715265
11091 01:23:29.721467 The programs included with the Debian GNU/Linux system are free software;
11092 01:23:29.727627 the exact distribution terms for each program are described in the
11093 01:23:29.731784 individual files in /usr/share/doc/*/copyright.
11094 01:23:29.732338
11095 01:23:29.738093 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11096 01:23:29.741189 permitted by applicable law.
11097 01:23:29.742606 Matched prompt #10: / #
11099 01:23:29.743591 Setting prompt string to ['/ #']
11100 01:23:29.744040 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11102 01:23:29.745001 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11103 01:23:29.745430 start: 2.2.6 expect-shell-connection (timeout 00:02:51) [common]
11104 01:23:29.745778 Setting prompt string to ['/ #']
11105 01:23:29.746080 Forcing a shell prompt, looking for ['/ #']
11107 01:23:29.796826 / #
11108 01:23:29.797481 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11109 01:23:29.797954 Waiting using forced prompt support (timeout 00:02:30)
11110 01:23:29.803456
11111 01:23:29.804487 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11112 01:23:29.805063 start: 2.2.7 export-device-env (timeout 00:02:51) [common]
11113 01:23:29.805567 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11114 01:23:29.806076 end: 2.2 depthcharge-retry (duration 00:02:09) [common]
11115 01:23:29.806557 end: 2 depthcharge-action (duration 00:02:09) [common]
11116 01:23:29.807039 start: 3 lava-test-retry (timeout 00:07:30) [common]
11117 01:23:29.807505 start: 3.1 lava-test-shell (timeout 00:07:30) [common]
11118 01:23:29.807947 Using namespace: common
11120 01:23:29.909117 / # #
11121 01:23:29.909749 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11122 01:23:29.910317 <6>[ 20.075276] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11123 01:23:29.915464 #
11124 01:23:29.916384 Using /lava-13468767
11126 01:23:30.017519 / # export SHELL=/bin/sh
11127 01:23:30.023921 export SHELL=/bin/sh
11129 01:23:30.125470 / # . /lava-13468767/environment
11130 01:23:30.126176 <6>[ 20.301585] r8152 2-1.3:1.0 enx002432307c7b: carrier on
11131 01:23:30.132166 . /lava-13468767/environment
11133 01:23:30.234201 / # /lava-13468767/bin/lava-test-runner /lava-13468767/0
11134 01:23:30.234835 Test shell timeout: 10s (minimum of the action and connection timeout)
11135 01:23:30.241113 /lava-13468767/bin/lava-test-runner /lava-13468767/0
11136 01:23:30.264956 + export TESTRUN_ID=0_v4l2-compliance-uvc
11137 01:23:30.268164 + cd /lava-13468767/0/tests/0_v4l2-compliance-uvc
11138 01:23:30.268641 + cat uuid
11139 01:23:30.271682 + UUID=13468767_1.5.2.3.1
11140 01:23:30.272307 + set +x
11141 01:23:30.278256 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 13468767_1.5.2.3.1>
11142 01:23:30.279115 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 13468767_1.5.2.3.1
11143 01:23:30.279523 Starting test lava.0_v4l2-compliance-uvc (13468767_1.5.2.3.1)
11144 01:23:30.280011 Skipping test definition patterns.
11145 01:23:30.281864 + /usr/bin/v4l2-parser.sh -d uvcvideo
11146 01:23:30.288050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11147 01:23:30.288653 device: /dev/video0
11148 01:23:30.289344 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11150 01:23:30.524137 <6>[ 20.762198] IPv6: ADDRCONF(NETDEV_CHANGE): enx002432307c7b: link becomes ready
11151 01:23:36.773630 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11152 01:23:36.785723 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11153 01:23:36.795735
11154 01:23:36.813948 Compliance test for uvcvideo device /dev/video0:
11155 01:23:36.821122
11156 01:23:36.832604 Driver Info:
11157 01:23:36.843629 Driver name : uvcvideo
11158 01:23:36.863591 Card type : HD User Facing: HD User Facing
11159 01:23:36.876265 Bus info : usb-11200000.usb-1.4.1
11160 01:23:36.883877 Driver version : 6.1.86
11161 01:23:36.893936 Capabilities : 0x84a00001
11162 01:23:36.907235 Metadata Capture
11163 01:23:36.918207 Streaming
11164 01:23:36.927836 Extended Pix Format
11165 01:23:36.943181 Device Capabilities
11166 01:23:36.952643 Device Caps : 0x04200001
11167 01:23:36.967520 Streaming
11168 01:23:36.978559 Extended Pix Format
11169 01:23:36.990514 Media Driver Info:
11170 01:23:37.001110 Driver name : uvcvideo
11171 01:23:37.016397 Model : HD User Facing: HD User Facing
11172 01:23:37.026920 Serial : 200901010001
11173 01:23:37.043186 Bus info : usb-11200000.usb-1.4.1
11174 01:23:37.052741 Media version : 6.1.86
11175 01:23:37.069659 Hardware revision: 0x00009758 (38744)
11176 01:23:37.079055 Driver version : 6.1.86
11177 01:23:37.089946 Interface Info:
11178 01:23:37.105002 <LAVA_SIGNAL_TESTSET START Interface-Info>
11179 01:23:37.105568 ID : 0x03000002
11180 01:23:37.106182 Received signal: <TESTSET> START Interface-Info
11181 01:23:37.106564 Starting test_set Interface-Info
11182 01:23:37.116335 Type : V4L Video
11183 01:23:37.127287 Entity Info:
11184 01:23:37.133451 <LAVA_SIGNAL_TESTSET STOP>
11185 01:23:37.134248 Received signal: <TESTSET> STOP
11186 01:23:37.134619 Closing test_set Interface-Info
11187 01:23:37.143238 <LAVA_SIGNAL_TESTSET START Entity-Info>
11188 01:23:37.143950 Received signal: <TESTSET> START Entity-Info
11189 01:23:37.144489 Starting test_set Entity-Info
11190 01:23:37.146217 ID : 0x00000001 (1)
11191 01:23:37.157201 Name : HD User Facing: HD User Facing
11192 01:23:37.164563 Function : V4L2 I/O
11193 01:23:37.175401 Flags : default
11194 01:23:37.185589 Pad 0x01000007 : 0: Sink
11195 01:23:37.206399 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11196 01:23:37.206927
11197 01:23:37.219590 Required ioctls:
11198 01:23:37.227651 <LAVA_SIGNAL_TESTSET STOP>
11199 01:23:37.228534 Received signal: <TESTSET> STOP
11200 01:23:37.228988 Closing test_set Entity-Info
11201 01:23:37.236828 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11202 01:23:37.237682 Received signal: <TESTSET> START Required-ioctls
11203 01:23:37.238078 Starting test_set Required-ioctls
11204 01:23:37.239748 test MC information (see 'Media Driver Info' above): OK
11205 01:23:37.269251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11206 01:23:37.270104 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11208 01:23:37.272201 test VIDIOC_QUERYCAP: OK
11209 01:23:37.291592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11210 01:23:37.292507 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11212 01:23:37.294533 test invalid ioctls: OK
11213 01:23:37.316698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11214 01:23:37.317313
11215 01:23:37.317966 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11217 01:23:37.328685 Allow for multiple opens:
11218 01:23:37.336569 <LAVA_SIGNAL_TESTSET STOP>
11219 01:23:37.337429 Received signal: <TESTSET> STOP
11220 01:23:37.337821 Closing test_set Required-ioctls
11221 01:23:37.345675 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11222 01:23:37.346502 Received signal: <TESTSET> START Allow-for-multiple-opens
11223 01:23:37.346931 Starting test_set Allow-for-multiple-opens
11224 01:23:37.349181 test second /dev/video0 open: OK
11225 01:23:37.370328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11226 01:23:37.371195 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11228 01:23:37.373708 test VIDIOC_QUERYCAP: OK
11229 01:23:37.394843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11230 01:23:37.395667 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11232 01:23:37.398114 test VIDIOC_G/S_PRIORITY: OK
11233 01:23:37.419205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11234 01:23:37.420172 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11236 01:23:37.422185 test for unlimited opens: OK
11237 01:23:37.443555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11238 01:23:37.444358
11239 01:23:37.445016 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11241 01:23:37.454942 Debug ioctls:
11242 01:23:37.462297 <LAVA_SIGNAL_TESTSET STOP>
11243 01:23:37.463142 Received signal: <TESTSET> STOP
11244 01:23:37.463549 Closing test_set Allow-for-multiple-opens
11245 01:23:37.472339 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11246 01:23:37.473186 Received signal: <TESTSET> START Debug-ioctls
11247 01:23:37.473577 Starting test_set Debug-ioctls
11248 01:23:37.475399 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11249 01:23:37.498077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11250 01:23:37.498915 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11252 01:23:37.504609 test VIDIOC_LOG_STATUS: OK (Not Supported)
11253 01:23:37.522351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11254 01:23:37.522921
11255 01:23:37.523560 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11257 01:23:37.531276 Input ioctls:
11258 01:23:37.542986 <LAVA_SIGNAL_TESTSET STOP>
11259 01:23:37.543839 Received signal: <TESTSET> STOP
11260 01:23:37.544333 Closing test_set Debug-ioctls
11261 01:23:37.551345 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11262 01:23:37.552080 Received signal: <TESTSET> START Input-ioctls
11263 01:23:37.552481 Starting test_set Input-ioctls
11264 01:23:37.554995 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11265 01:23:37.582038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11266 01:23:37.582886 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11268 01:23:37.585051 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11269 01:23:37.603692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11270 01:23:37.604591 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11272 01:23:37.610431 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11273 01:23:37.628090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11274 01:23:37.628932 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11276 01:23:37.634566 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11277 01:23:37.653803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11278 01:23:37.654652 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11280 01:23:37.656553 test VIDIOC_G/S/ENUMINPUT: OK
11281 01:23:37.679112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11282 01:23:37.680009 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11284 01:23:37.681839 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11285 01:23:37.702947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11286 01:23:37.703796 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11288 01:23:37.706047 Inputs: 1 Audio Inputs: 0 Tuners: 0
11289 01:23:37.713318
11290 01:23:37.732393 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11291 01:23:37.754679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11292 01:23:37.755519 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11294 01:23:37.761268 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11295 01:23:37.780368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11296 01:23:37.781204 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11298 01:23:37.784262 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11299 01:23:37.806943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11300 01:23:37.807814 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11302 01:23:37.813025 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11303 01:23:37.831544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11304 01:23:37.832423 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11306 01:23:37.838453 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11307 01:23:37.859105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11308 01:23:37.860012 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11310 01:23:37.862111
11311 01:23:37.878545 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11312 01:23:37.900589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11313 01:23:37.901424 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11315 01:23:37.907071 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11316 01:23:37.930478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11317 01:23:37.931289 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11319 01:23:37.934430 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11320 01:23:37.952362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11321 01:23:37.953191 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11323 01:23:37.955282 test VIDIOC_G/S_EDID: OK (Not Supported)
11324 01:23:37.977654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11325 01:23:37.978220
11326 01:23:37.978855 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11328 01:23:37.987628 Control ioctls (Input 0):
11329 01:23:38.005723 <LAVA_SIGNAL_TESTSET STOP>
11330 01:23:38.006551 Received signal: <TESTSET> STOP
11331 01:23:38.006932 Closing test_set Input-ioctls
11332 01:23:38.016395 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11333 01:23:38.017258 Received signal: <TESTSET> START Control-ioctls-Input-0
11334 01:23:38.017663 Starting test_set Control-ioctls-Input-0
11335 01:23:38.019302 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11336 01:23:38.043474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11337 01:23:38.044063 test VIDIOC_QUERYCTRL: OK
11338 01:23:38.044704 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11340 01:23:38.063529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11341 01:23:38.064405 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11343 01:23:38.066587 test VIDIOC_G/S_CTRL: OK
11344 01:23:38.087948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11345 01:23:38.088814 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11347 01:23:38.091169 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11348 01:23:38.112036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11349 01:23:38.112874 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11351 01:23:38.118209 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11352 01:23:38.138419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11353 01:23:38.139251 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11355 01:23:38.141761 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11356 01:23:38.161117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11357 01:23:38.161968 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11359 01:23:38.164455 Standard Controls: 16 Private Controls: 0
11360 01:23:38.172461
11361 01:23:38.183571 Format ioctls (Input 0):
11362 01:23:38.191330 <LAVA_SIGNAL_TESTSET STOP>
11363 01:23:38.192272 Received signal: <TESTSET> STOP
11364 01:23:38.192830 Closing test_set Control-ioctls-Input-0
11365 01:23:38.200739 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11366 01:23:38.201412 Received signal: <TESTSET> START Format-ioctls-Input-0
11367 01:23:38.201795 Starting test_set Format-ioctls-Input-0
11368 01:23:38.203739 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11369 01:23:38.230172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11370 01:23:38.230868 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11372 01:23:38.233359 test VIDIOC_G/S_PARM: OK
11373 01:23:38.252327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11374 01:23:38.253005 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11376 01:23:38.255357 test VIDIOC_G_FBUF: OK (Not Supported)
11377 01:23:38.279253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11378 01:23:38.279961 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11380 01:23:38.282241 test VIDIOC_G_FMT: OK
11381 01:23:38.304730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11382 01:23:38.305500 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11384 01:23:38.307967 test VIDIOC_TRY_FMT: OK
11385 01:23:38.329229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11386 01:23:38.330006 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11388 01:23:38.336736 warn: v4l2-test-formats.cpp(1046): Could not set fmt2
11389 01:23:38.340628 test VIDIOC_S_FMT: OK
11390 01:23:38.366029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11391 01:23:38.366871 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11393 01:23:38.369713 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11394 01:23:38.394211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11395 01:23:38.395051 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11397 01:23:38.396736 test Cropping: OK (Not Supported)
11398 01:23:38.419393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11399 01:23:38.420254 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11401 01:23:38.422542 test Composing: OK (Not Supported)
11402 01:23:38.445463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11403 01:23:38.446298 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11405 01:23:38.448756 test Scaling: OK (Not Supported)
11406 01:23:38.471388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11407 01:23:38.471999
11408 01:23:38.472648 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11410 01:23:38.486877 Codec ioctls (Input 0):
11411 01:23:38.494612 <LAVA_SIGNAL_TESTSET STOP>
11412 01:23:38.495445 Received signal: <TESTSET> STOP
11413 01:23:38.495827 Closing test_set Format-ioctls-Input-0
11414 01:23:38.504263 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11415 01:23:38.505168 Received signal: <TESTSET> START Codec-ioctls-Input-0
11416 01:23:38.505632 Starting test_set Codec-ioctls-Input-0
11417 01:23:38.507570 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11418 01:23:38.526471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11419 01:23:38.527322 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11421 01:23:38.533148 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11422 01:23:38.554019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11423 01:23:38.554931 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11425 01:23:38.560145 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11426 01:23:38.578808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11427 01:23:38.579372
11428 01:23:38.580020 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11430 01:23:38.587057 Buffer ioctls (Input 0):
11431 01:23:38.593457 <LAVA_SIGNAL_TESTSET STOP>
11432 01:23:38.594293 Received signal: <TESTSET> STOP
11433 01:23:38.594676 Closing test_set Codec-ioctls-Input-0
11434 01:23:38.603699 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11435 01:23:38.604676 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11436 01:23:38.605095 Starting test_set Buffer-ioctls-Input-0
11437 01:23:38.606870 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11438 01:23:38.631602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11439 01:23:38.632448 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11441 01:23:38.635138 test CREATE_BUFS maximum buffers: OK
11442 01:23:38.653326 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11444 01:23:38.656371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11445 01:23:38.656874 test VIDIOC_EXPBUF: OK
11446 01:23:38.678260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11447 01:23:38.679098 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11449 01:23:38.681458 test Requests: OK (Not Supported)
11450 01:23:38.701341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11451 01:23:38.701885
11452 01:23:38.702562 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11454 01:23:38.711146 Test input 0:
11455 01:23:38.719762
11456 01:23:38.731166 Streaming ioctls:
11457 01:23:38.749725 <LAVA_SIGNAL_TESTSET STOP>
11458 01:23:38.750559 Received signal: <TESTSET> STOP
11459 01:23:38.750946 Closing test_set Buffer-ioctls-Input-0
11460 01:23:38.759428 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11461 01:23:38.760289 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11462 01:23:38.760682 Starting test_set Streaming-ioctls_Test-input-0
11463 01:23:38.762943 test read/write: OK (Not Supported)
11464 01:23:38.784119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11465 01:23:38.784951 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11467 01:23:38.787585 test blocking wait: OK
11468 01:23:38.812752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11469 01:23:38.813645 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11471 01:23:38.819129 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11472 01:23:38.824960 test MMAP (no poll): FAIL
11473 01:23:38.847987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11474 01:23:38.848705 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11476 01:23:38.854301 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11477 01:23:38.859799 test MMAP (select): FAIL
11478 01:23:38.887409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11479 01:23:38.888085 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11481 01:23:38.893735 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11482 01:23:38.898979 test MMAP (epoll): FAIL
11483 01:23:38.923971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11484 01:23:38.924493
11485 01:23:38.925092 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11487 01:23:38.938512
11488 01:23:39.114469
11489 01:23:39.122027 test USERPTR (no poll): OK
11490 01:23:39.147104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11491 01:23:39.147678
11492 01:23:39.148361 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11494 01:23:39.161449
11495 01:23:39.343141
11496 01:23:39.351118 test USERPTR (select): OK
11497 01:23:39.375318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11498 01:23:39.376018 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11500 01:23:39.381789 test DMABUF: Cannot test, specify --expbuf-device
11501 01:23:39.388362
11502 01:23:39.408290 Total for uvcvideo device /dev/video0: 54, Succeeded: 51, Failed: 3, Warnings: 3
11503 01:23:39.411809 <LAVA_TEST_RUNNER EXIT>
11504 01:23:39.412588 ok: lava_test_shell seems to have completed
11505 01:23:39.412957 Marking unfinished test run as failed
11507 01:23:39.419193 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls-Input-0
Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11508 01:23:39.419820 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11509 01:23:39.420295 end: 3 lava-test-retry (duration 00:00:10) [common]
11510 01:23:39.420728 start: 4 finalize (timeout 00:07:20) [common]
11511 01:23:39.421220 start: 4.1 power-off (timeout 00:00:30) [common]
11512 01:23:39.422038 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11513 01:23:39.507123 >> Command sent successfully.
11514 01:23:39.511743 Returned 0 in 0 seconds
11515 01:23:39.612806 end: 4.1 power-off (duration 00:00:00) [common]
11517 01:23:39.614361 start: 4.2 read-feedback (timeout 00:07:20) [common]
11518 01:23:39.615626 Listened to connection for namespace 'common' for up to 1s
11519 01:23:40.616154 Finalising connection for namespace 'common'
11520 01:23:40.616809 Disconnecting from shell: Finalise
11521 01:23:40.617214 / #
11522 01:23:40.718345 end: 4.2 read-feedback (duration 00:00:01) [common]
11523 01:23:40.719069 end: 4 finalize (duration 00:00:01) [common]
11524 01:23:40.719746 Cleaning after the job
11525 01:23:40.720312 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468767/tftp-deploy-31iv6vbn/ramdisk
11526 01:23:40.739684 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468767/tftp-deploy-31iv6vbn/kernel
11527 01:23:40.770907 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468767/tftp-deploy-31iv6vbn/dtb
11528 01:23:40.771208 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468767/tftp-deploy-31iv6vbn/modules
11529 01:23:40.778468 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13468767
11530 01:23:40.840117 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13468767
11531 01:23:40.840294 Job finished correctly