Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 24
- Errors: 0
- Kernel Errors: 35
- Boot result: PASS
1 01:16:32.950358 lava-dispatcher, installed at version: 2024.01
2 01:16:32.950582 start: 0 validate
3 01:16:32.950713 Start time: 2024-04-23 01:16:32.950705+00:00 (UTC)
4 01:16:32.950847 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:16:32.950980 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 01:16:33.206368 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:16:33.206540 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:16:33.460485 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:16:33.460694 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:16:33.713707 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:16:33.713888 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 01:16:33.967819 validate duration: 1.02
14 01:16:33.968137 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:16:33.968244 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:16:33.968329 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:16:33.968452 Not decompressing ramdisk as can be used compressed.
18 01:16:33.968535 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 01:16:33.968598 saving as /var/lib/lava/dispatcher/tmp/13468749/tftp-deploy-6yq5_lze/ramdisk/rootfs.cpio.gz
20 01:16:33.968660 total size: 47897469 (45 MB)
21 01:16:33.971216 progress 0 % (0 MB)
22 01:16:33.984850 progress 5 % (2 MB)
23 01:16:33.998397 progress 10 % (4 MB)
24 01:16:34.011578 progress 15 % (6 MB)
25 01:16:34.023661 progress 20 % (9 MB)
26 01:16:34.035812 progress 25 % (11 MB)
27 01:16:34.047957 progress 30 % (13 MB)
28 01:16:34.060087 progress 35 % (16 MB)
29 01:16:34.072073 progress 40 % (18 MB)
30 01:16:34.084085 progress 45 % (20 MB)
31 01:16:34.096090 progress 50 % (22 MB)
32 01:16:34.108223 progress 55 % (25 MB)
33 01:16:34.120521 progress 60 % (27 MB)
34 01:16:34.132631 progress 65 % (29 MB)
35 01:16:34.144841 progress 70 % (32 MB)
36 01:16:34.156953 progress 75 % (34 MB)
37 01:16:34.169081 progress 80 % (36 MB)
38 01:16:34.181191 progress 85 % (38 MB)
39 01:16:34.193178 progress 90 % (41 MB)
40 01:16:34.204973 progress 95 % (43 MB)
41 01:16:34.216826 progress 100 % (45 MB)
42 01:16:34.217076 45 MB downloaded in 0.25 s (183.88 MB/s)
43 01:16:34.217256 end: 1.1.1 http-download (duration 00:00:00) [common]
45 01:16:34.217499 end: 1.1 download-retry (duration 00:00:00) [common]
46 01:16:34.217585 start: 1.2 download-retry (timeout 00:10:00) [common]
47 01:16:34.217670 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 01:16:34.217813 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 01:16:34.217887 saving as /var/lib/lava/dispatcher/tmp/13468749/tftp-deploy-6yq5_lze/kernel/Image
50 01:16:34.217949 total size: 54352384 (51 MB)
51 01:16:34.218010 No compression specified
52 01:16:34.219154 progress 0 % (0 MB)
53 01:16:34.232843 progress 5 % (2 MB)
54 01:16:34.246627 progress 10 % (5 MB)
55 01:16:34.260469 progress 15 % (7 MB)
56 01:16:34.274280 progress 20 % (10 MB)
57 01:16:34.287991 progress 25 % (12 MB)
58 01:16:34.301676 progress 30 % (15 MB)
59 01:16:34.315314 progress 35 % (18 MB)
60 01:16:34.329063 progress 40 % (20 MB)
61 01:16:34.342891 progress 45 % (23 MB)
62 01:16:34.356606 progress 50 % (25 MB)
63 01:16:34.370341 progress 55 % (28 MB)
64 01:16:34.384267 progress 60 % (31 MB)
65 01:16:34.398049 progress 65 % (33 MB)
66 01:16:34.411813 progress 70 % (36 MB)
67 01:16:34.425717 progress 75 % (38 MB)
68 01:16:34.439475 progress 80 % (41 MB)
69 01:16:34.453444 progress 85 % (44 MB)
70 01:16:34.467296 progress 90 % (46 MB)
71 01:16:34.480813 progress 95 % (49 MB)
72 01:16:34.494297 progress 100 % (51 MB)
73 01:16:34.494614 51 MB downloaded in 0.28 s (187.36 MB/s)
74 01:16:34.494769 end: 1.2.1 http-download (duration 00:00:00) [common]
76 01:16:34.495006 end: 1.2 download-retry (duration 00:00:00) [common]
77 01:16:34.495092 start: 1.3 download-retry (timeout 00:09:59) [common]
78 01:16:34.495186 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 01:16:34.495329 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 01:16:34.495404 saving as /var/lib/lava/dispatcher/tmp/13468749/tftp-deploy-6yq5_lze/dtb/mt8192-asurada-spherion-r0.dtb
81 01:16:34.495465 total size: 47230 (0 MB)
82 01:16:34.495527 No compression specified
83 01:16:34.496613 progress 69 % (0 MB)
84 01:16:34.496881 progress 100 % (0 MB)
85 01:16:34.497036 0 MB downloaded in 0.00 s (28.72 MB/s)
86 01:16:34.497159 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:16:34.497381 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:16:34.497464 start: 1.4 download-retry (timeout 00:09:59) [common]
90 01:16:34.497546 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 01:16:34.497657 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 01:16:34.497725 saving as /var/lib/lava/dispatcher/tmp/13468749/tftp-deploy-6yq5_lze/modules/modules.tar
93 01:16:34.497784 total size: 8638160 (8 MB)
94 01:16:34.497845 Using unxz to decompress xz
95 01:16:34.502159 progress 0 % (0 MB)
96 01:16:34.521160 progress 5 % (0 MB)
97 01:16:34.545542 progress 10 % (0 MB)
98 01:16:34.569245 progress 15 % (1 MB)
99 01:16:34.592194 progress 20 % (1 MB)
100 01:16:34.617290 progress 25 % (2 MB)
101 01:16:34.644398 progress 30 % (2 MB)
102 01:16:34.668617 progress 35 % (2 MB)
103 01:16:34.694376 progress 40 % (3 MB)
104 01:16:34.718738 progress 45 % (3 MB)
105 01:16:34.743609 progress 50 % (4 MB)
106 01:16:34.768019 progress 55 % (4 MB)
107 01:16:34.795537 progress 60 % (4 MB)
108 01:16:34.820354 progress 65 % (5 MB)
109 01:16:34.845222 progress 70 % (5 MB)
110 01:16:34.869449 progress 75 % (6 MB)
111 01:16:34.894047 progress 80 % (6 MB)
112 01:16:34.921691 progress 85 % (7 MB)
113 01:16:34.947755 progress 90 % (7 MB)
114 01:16:34.976436 progress 95 % (7 MB)
115 01:16:35.002241 progress 100 % (8 MB)
116 01:16:35.007929 8 MB downloaded in 0.51 s (16.15 MB/s)
117 01:16:35.008182 end: 1.4.1 http-download (duration 00:00:01) [common]
119 01:16:35.008448 end: 1.4 download-retry (duration 00:00:01) [common]
120 01:16:35.008540 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 01:16:35.008635 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 01:16:35.008716 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:16:35.008807 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 01:16:35.009031 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7
125 01:16:35.009166 makedir: /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/bin
126 01:16:35.009267 makedir: /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/tests
127 01:16:35.009364 makedir: /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/results
128 01:16:35.009481 Creating /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/bin/lava-add-keys
129 01:16:35.009627 Creating /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/bin/lava-add-sources
130 01:16:35.009759 Creating /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/bin/lava-background-process-start
131 01:16:35.009891 Creating /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/bin/lava-background-process-stop
132 01:16:35.010031 Creating /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/bin/lava-common-functions
133 01:16:35.010194 Creating /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/bin/lava-echo-ipv4
134 01:16:35.010320 Creating /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/bin/lava-install-packages
135 01:16:35.010443 Creating /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/bin/lava-installed-packages
136 01:16:35.010566 Creating /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/bin/lava-os-build
137 01:16:35.010688 Creating /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/bin/lava-probe-channel
138 01:16:35.010813 Creating /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/bin/lava-probe-ip
139 01:16:35.010937 Creating /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/bin/lava-target-ip
140 01:16:35.011060 Creating /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/bin/lava-target-mac
141 01:16:35.011182 Creating /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/bin/lava-target-storage
142 01:16:35.011310 Creating /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/bin/lava-test-case
143 01:16:35.011434 Creating /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/bin/lava-test-event
144 01:16:35.011561 Creating /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/bin/lava-test-feedback
145 01:16:35.011683 Creating /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/bin/lava-test-raise
146 01:16:35.011809 Creating /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/bin/lava-test-reference
147 01:16:35.011932 Creating /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/bin/lava-test-runner
148 01:16:35.012054 Creating /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/bin/lava-test-set
149 01:16:35.012178 Creating /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/bin/lava-test-shell
150 01:16:35.012303 Updating /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/bin/lava-install-packages (oe)
151 01:16:35.012452 Updating /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/bin/lava-installed-packages (oe)
152 01:16:35.012571 Creating /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/environment
153 01:16:35.012669 LAVA metadata
154 01:16:35.012743 - LAVA_JOB_ID=13468749
155 01:16:35.012807 - LAVA_DISPATCHER_IP=192.168.201.1
156 01:16:35.012910 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 01:16:35.012991 skipped lava-vland-overlay
158 01:16:35.013071 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 01:16:35.013153 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 01:16:35.013213 skipped lava-multinode-overlay
161 01:16:35.013288 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 01:16:35.013387 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 01:16:35.013469 Loading test definitions
164 01:16:35.013559 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 01:16:35.013635 Using /lava-13468749 at stage 0
166 01:16:35.013946 uuid=13468749_1.5.2.3.1 testdef=None
167 01:16:35.014062 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 01:16:35.014163 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 01:16:35.014681 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 01:16:35.014902 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 01:16:35.015541 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 01:16:35.015773 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 01:16:35.016376 runner path: /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/0/tests/0_igt-gpu-panfrost test_uuid 13468749_1.5.2.3.1
176 01:16:35.016533 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 01:16:35.016737 Creating lava-test-runner.conf files
179 01:16:35.016799 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13468749/lava-overlay-4wrwaia7/lava-13468749/0 for stage 0
180 01:16:35.016887 - 0_igt-gpu-panfrost
181 01:16:35.016981 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 01:16:35.017064 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 01:16:35.024257 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 01:16:35.024368 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 01:16:35.024456 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 01:16:35.024543 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 01:16:35.024629 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 01:16:36.746531 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 01:16:36.746913 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 01:16:36.747026 extracting modules file /var/lib/lava/dispatcher/tmp/13468749/tftp-deploy-6yq5_lze/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13468749/extract-overlay-ramdisk-_c31ijlf/ramdisk
191 01:16:36.963205 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 01:16:36.963377 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 01:16:36.963473 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13468749/compress-overlay-r7uv2vrc/overlay-1.5.2.4.tar.gz to ramdisk
194 01:16:36.963549 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13468749/compress-overlay-r7uv2vrc/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13468749/extract-overlay-ramdisk-_c31ijlf/ramdisk
195 01:16:36.969968 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 01:16:36.970151 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 01:16:36.970246 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 01:16:36.970337 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 01:16:36.970420 Building ramdisk /var/lib/lava/dispatcher/tmp/13468749/extract-overlay-ramdisk-_c31ijlf/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13468749/extract-overlay-ramdisk-_c31ijlf/ramdisk
200 01:16:38.172101 >> 466207 blocks
201 01:16:44.337569 rename /var/lib/lava/dispatcher/tmp/13468749/extract-overlay-ramdisk-_c31ijlf/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13468749/tftp-deploy-6yq5_lze/ramdisk/ramdisk.cpio.gz
202 01:16:44.338005 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 01:16:44.338177 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 01:16:44.338279 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 01:16:44.338387 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13468749/tftp-deploy-6yq5_lze/kernel/Image'
206 01:16:57.232978 Returned 0 in 12 seconds
207 01:16:57.333591 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13468749/tftp-deploy-6yq5_lze/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13468749/tftp-deploy-6yq5_lze/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13468749/tftp-deploy-6yq5_lze/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13468749/tftp-deploy-6yq5_lze/kernel/image.itb
208 01:16:58.179421 output: FIT description: Kernel Image image with one or more FDT blobs
209 01:16:58.179793 output: Created: Tue Apr 23 02:16:58 2024
210 01:16:58.179867 output: Image 0 (kernel-1)
211 01:16:58.179934 output: Description:
212 01:16:58.179995 output: Created: Tue Apr 23 02:16:58 2024
213 01:16:58.180057 output: Type: Kernel Image
214 01:16:58.180119 output: Compression: lzma compressed
215 01:16:58.180179 output: Data Size: 12910050 Bytes = 12607.47 KiB = 12.31 MiB
216 01:16:58.180238 output: Architecture: AArch64
217 01:16:58.180297 output: OS: Linux
218 01:16:58.180356 output: Load Address: 0x00000000
219 01:16:58.180415 output: Entry Point: 0x00000000
220 01:16:58.180472 output: Hash algo: crc32
221 01:16:58.180580 output: Hash value: 1126c3f9
222 01:16:58.180653 output: Image 1 (fdt-1)
223 01:16:58.180708 output: Description: mt8192-asurada-spherion-r0
224 01:16:58.180763 output: Created: Tue Apr 23 02:16:58 2024
225 01:16:58.180816 output: Type: Flat Device Tree
226 01:16:58.180869 output: Compression: uncompressed
227 01:16:58.180922 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
228 01:16:58.180975 output: Architecture: AArch64
229 01:16:58.181027 output: Hash algo: crc32
230 01:16:58.181080 output: Hash value: 4bf0d1ac
231 01:16:58.181132 output: Image 2 (ramdisk-1)
232 01:16:58.181185 output: Description: unavailable
233 01:16:58.181237 output: Created: Tue Apr 23 02:16:58 2024
234 01:16:58.181290 output: Type: RAMDisk Image
235 01:16:58.181342 output: Compression: Unknown Compression
236 01:16:58.181395 output: Data Size: 61032760 Bytes = 59602.30 KiB = 58.21 MiB
237 01:16:58.181448 output: Architecture: AArch64
238 01:16:58.181501 output: OS: Linux
239 01:16:58.181553 output: Load Address: unavailable
240 01:16:58.181605 output: Entry Point: unavailable
241 01:16:58.181658 output: Hash algo: crc32
242 01:16:58.181709 output: Hash value: b74047ce
243 01:16:58.181762 output: Default Configuration: 'conf-1'
244 01:16:58.181814 output: Configuration 0 (conf-1)
245 01:16:58.181867 output: Description: mt8192-asurada-spherion-r0
246 01:16:58.181919 output: Kernel: kernel-1
247 01:16:58.181971 output: Init Ramdisk: ramdisk-1
248 01:16:58.182029 output: FDT: fdt-1
249 01:16:58.182117 output: Loadables: kernel-1
250 01:16:58.182170 output:
251 01:16:58.182374 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 01:16:58.182473 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 01:16:58.182572 end: 1.5 prepare-tftp-overlay (duration 00:00:23) [common]
254 01:16:58.182662 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
255 01:16:58.182742 No LXC device requested
256 01:16:58.182822 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 01:16:58.182909 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
258 01:16:58.182989 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 01:16:58.183057 Checking files for TFTP limit of 4294967296 bytes.
260 01:16:58.183552 end: 1 tftp-deploy (duration 00:00:24) [common]
261 01:16:58.183656 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 01:16:58.183749 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 01:16:58.183874 substitutions:
264 01:16:58.183940 - {DTB}: 13468749/tftp-deploy-6yq5_lze/dtb/mt8192-asurada-spherion-r0.dtb
265 01:16:58.184004 - {INITRD}: 13468749/tftp-deploy-6yq5_lze/ramdisk/ramdisk.cpio.gz
266 01:16:58.184063 - {KERNEL}: 13468749/tftp-deploy-6yq5_lze/kernel/Image
267 01:16:58.184120 - {LAVA_MAC}: None
268 01:16:58.184176 - {PRESEED_CONFIG}: None
269 01:16:58.184231 - {PRESEED_LOCAL}: None
270 01:16:58.184285 - {RAMDISK}: 13468749/tftp-deploy-6yq5_lze/ramdisk/ramdisk.cpio.gz
271 01:16:58.184340 - {ROOT_PART}: None
272 01:16:58.184394 - {ROOT}: None
273 01:16:58.184448 - {SERVER_IP}: 192.168.201.1
274 01:16:58.184501 - {TEE}: None
275 01:16:58.184554 Parsed boot commands:
276 01:16:58.184608 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 01:16:58.184785 Parsed boot commands: tftpboot 192.168.201.1 13468749/tftp-deploy-6yq5_lze/kernel/image.itb 13468749/tftp-deploy-6yq5_lze/kernel/cmdline
278 01:16:58.184875 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 01:16:58.184958 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 01:16:58.185049 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 01:16:58.185134 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 01:16:58.185203 Not connected, no need to disconnect.
283 01:16:58.185277 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 01:16:58.185356 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 01:16:58.185421 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 01:16:58.189259 Setting prompt string to ['lava-test: # ']
287 01:16:58.189618 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 01:16:58.189729 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 01:16:58.189826 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 01:16:58.189935 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 01:16:58.190158 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
292 01:17:03.332888 >> Command sent successfully.
293 01:17:03.339846 Returned 0 in 5 seconds
294 01:17:03.440917 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 01:17:03.442451 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 01:17:03.442996 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 01:17:03.443481 Setting prompt string to 'Starting depthcharge on Spherion...'
299 01:17:03.443854 Changing prompt to 'Starting depthcharge on Spherion...'
300 01:17:03.444232 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 01:17:03.445598 [Enter `^Ec?' for help]
302 01:17:03.614106
303 01:17:03.614835
304 01:17:03.615265 F0: 102B 0000
305 01:17:03.615637
306 01:17:03.615989 F3: 1001 0000 [0200]
307 01:17:03.616338
308 01:17:03.617518 F3: 1001 0000
309 01:17:03.618180
310 01:17:03.618572 F7: 102D 0000
311 01:17:03.618924
312 01:17:03.621525 F1: 0000 0000
313 01:17:03.622241
314 01:17:03.622649 V0: 0000 0000 [0001]
315 01:17:03.623005
316 01:17:03.623344 00: 0007 8000
317 01:17:03.623691
318 01:17:03.625191 01: 0000 0000
319 01:17:03.625772
320 01:17:03.626185 BP: 0C00 0209 [0000]
321 01:17:03.626536
322 01:17:03.629092 G0: 1182 0000
323 01:17:03.629712
324 01:17:03.630139 EC: 0000 0021 [4000]
325 01:17:03.630500
326 01:17:03.632330 S7: 0000 0000 [0000]
327 01:17:03.632869
328 01:17:03.633252 CC: 0000 0000 [0001]
329 01:17:03.633603
330 01:17:03.635645 T0: 0000 0040 [010F]
331 01:17:03.636207
332 01:17:03.636590 Jump to BL
333 01:17:03.636941
334 01:17:03.660968
335 01:17:03.661492
336 01:17:03.661916
337 01:17:03.667994 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 01:17:03.671493 ARM64: Exception handlers installed.
339 01:17:03.675050 ARM64: Testing exception
340 01:17:03.678707 ARM64: Done test exception
341 01:17:03.685867 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 01:17:03.696436 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 01:17:03.703833 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 01:17:03.714261 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 01:17:03.720709 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 01:17:03.726972 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 01:17:03.738132 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 01:17:03.744455 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 01:17:03.763837 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 01:17:03.766706 WDT: Last reset was cold boot
351 01:17:03.770209 SPI1(PAD0) initialized at 2873684 Hz
352 01:17:03.773580 SPI5(PAD0) initialized at 992727 Hz
353 01:17:03.776911 VBOOT: Loading verstage.
354 01:17:03.783512 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 01:17:03.786535 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 01:17:03.790148 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 01:17:03.793936 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 01:17:03.801418 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 01:17:03.808052 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 01:17:03.818712 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 01:17:03.819284
362 01:17:03.819659
363 01:17:03.829612 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 01:17:03.832548 ARM64: Exception handlers installed.
365 01:17:03.835940 ARM64: Testing exception
366 01:17:03.836510 ARM64: Done test exception
367 01:17:03.842628 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 01:17:03.846284 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 01:17:03.859691 Probing TPM: . done!
370 01:17:03.860278 TPM ready after 0 ms
371 01:17:03.866327 Connected to device vid:did:rid of 1ae0:0028:00
372 01:17:03.873559 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
373 01:17:03.921892 Initialized TPM device CR50 revision 0
374 01:17:03.936952 tlcl_send_startup: Startup return code is 0
375 01:17:03.937551 TPM: setup succeeded
376 01:17:03.947638 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 01:17:03.956029 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 01:17:03.965901 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 01:17:03.975058 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 01:17:03.978442 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 01:17:03.981834 in-header: 03 07 00 00 08 00 00 00
382 01:17:03.985255 in-data: aa e4 47 04 13 02 00 00
383 01:17:03.988130 Chrome EC: UHEPI supported
384 01:17:03.994768 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 01:17:03.998480 in-header: 03 95 00 00 08 00 00 00
386 01:17:04.002132 in-data: 18 20 20 08 00 00 00 00
387 01:17:04.002612 Phase 1
388 01:17:04.005701 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 01:17:04.013054 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 01:17:04.016690 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 01:17:04.020586 Recovery requested (1009000e)
392 01:17:04.029668 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 01:17:04.035492 tlcl_extend: response is 0
394 01:17:04.044713 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 01:17:04.050273 tlcl_extend: response is 0
396 01:17:04.057488 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 01:17:04.077732 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 01:17:04.085305 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 01:17:04.085739
400 01:17:04.086111
401 01:17:04.092222 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 01:17:04.095724 ARM64: Exception handlers installed.
403 01:17:04.100044 ARM64: Testing exception
404 01:17:04.103218 ARM64: Done test exception
405 01:17:04.122708 pmic_efuse_setting: Set efuses in 11 msecs
406 01:17:04.126456 pmwrap_interface_init: Select PMIF_VLD_RDY
407 01:17:04.132686 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 01:17:04.136258 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 01:17:04.142741 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 01:17:04.146013 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 01:17:04.152812 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 01:17:04.155881 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 01:17:04.162966 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 01:17:04.165890 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 01:17:04.169365 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 01:17:04.175758 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 01:17:04.179264 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 01:17:04.182606 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 01:17:04.188870 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 01:17:04.195503 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 01:17:04.199619 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 01:17:04.206687 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 01:17:04.213855 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 01:17:04.217826 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 01:17:04.224608 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 01:17:04.227798 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 01:17:04.234979 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 01:17:04.238620 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 01:17:04.246265 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 01:17:04.249509 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 01:17:04.257084 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 01:17:04.260953 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 01:17:04.267830 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 01:17:04.271706 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 01:17:04.275290 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 01:17:04.283188 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 01:17:04.286508 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 01:17:04.290488 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 01:17:04.297528 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 01:17:04.301413 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 01:17:04.305069 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 01:17:04.312171 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 01:17:04.315617 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 01:17:04.322954 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 01:17:04.326486 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 01:17:04.330159 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 01:17:04.333945 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 01:17:04.340792 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 01:17:04.344665 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 01:17:04.348064 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 01:17:04.351943 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 01:17:04.355298 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 01:17:04.359211 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 01:17:04.366518 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 01:17:04.369973 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 01:17:04.373802 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 01:17:04.377820 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 01:17:04.384646 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 01:17:04.395390 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 01:17:04.399030 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 01:17:04.406189 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 01:17:04.413501 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 01:17:04.420852 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 01:17:04.424403 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 01:17:04.427550 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 01:17:04.436167 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x13
467 01:17:04.439708 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 01:17:04.447630 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 01:17:04.451338 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 01:17:04.460434 [RTC]rtc_get_frequency_meter,154: input=15, output=764
471 01:17:04.469438 [RTC]rtc_get_frequency_meter,154: input=23, output=949
472 01:17:04.479194 [RTC]rtc_get_frequency_meter,154: input=19, output=856
473 01:17:04.488419 [RTC]rtc_get_frequency_meter,154: input=17, output=809
474 01:17:04.498577 [RTC]rtc_get_frequency_meter,154: input=16, output=787
475 01:17:04.507707 [RTC]rtc_get_frequency_meter,154: input=16, output=787
476 01:17:04.517377 [RTC]rtc_get_frequency_meter,154: input=17, output=810
477 01:17:04.520949 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 01:17:04.528520 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 01:17:04.532166 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 01:17:04.536365 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 01:17:04.539894 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 01:17:04.544003 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 01:17:04.546962 ADC[4]: Raw value=670063 ID=5
484 01:17:04.547436 ADC[3]: Raw value=212549 ID=1
485 01:17:04.550868 RAM Code: 0x51
486 01:17:04.554776 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 01:17:04.558507 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 01:17:04.565679 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
489 01:17:04.573194 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
490 01:17:04.576939 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 01:17:04.580306 in-header: 03 07 00 00 08 00 00 00
492 01:17:04.584073 in-data: aa e4 47 04 13 02 00 00
493 01:17:04.588088 Chrome EC: UHEPI supported
494 01:17:04.591068 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 01:17:04.594923 in-header: 03 95 00 00 08 00 00 00
496 01:17:04.598700 in-data: 18 20 20 08 00 00 00 00
497 01:17:04.602656 MRC: failed to locate region type 0.
498 01:17:04.609636 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 01:17:04.613599 DRAM-K: Running full calibration
500 01:17:04.617397 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
501 01:17:04.620961 header.status = 0x0
502 01:17:04.625064 header.version = 0x6 (expected: 0x6)
503 01:17:04.628177 header.size = 0xd00 (expected: 0xd00)
504 01:17:04.628647 header.flags = 0x0
505 01:17:04.635225 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 01:17:04.652860 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 01:17:04.659740 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 01:17:04.663978 dram_init: ddr_geometry: 0
509 01:17:04.664585 [EMI] MDL number = 0
510 01:17:04.667049 [EMI] Get MDL freq = 0
511 01:17:04.667520 dram_init: ddr_type: 0
512 01:17:04.670989 is_discrete_lpddr4: 1
513 01:17:04.674778 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 01:17:04.675337
515 01:17:04.675707
516 01:17:04.676045 [Bian_co] ETT version 0.0.0.1
517 01:17:04.682014 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
518 01:17:04.682736
519 01:17:04.685519 dramc_set_vcore_voltage set vcore to 650000
520 01:17:04.685993 Read voltage for 800, 4
521 01:17:04.689178 Vio18 = 0
522 01:17:04.689600 Vcore = 650000
523 01:17:04.689938 Vdram = 0
524 01:17:04.692894 Vddq = 0
525 01:17:04.693317 Vmddr = 0
526 01:17:04.693650 dram_init: config_dvfs: 1
527 01:17:04.699900 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 01:17:04.703787 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 01:17:04.707828 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 01:17:04.711149 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 01:17:04.714655 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 01:17:04.718727 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 01:17:04.721977 MEM_TYPE=3, freq_sel=18
534 01:17:04.725747 sv_algorithm_assistance_LP4_1600
535 01:17:04.729425 ============ PULL DRAM RESETB DOWN ============
536 01:17:04.732895 ========== PULL DRAM RESETB DOWN end =========
537 01:17:04.739834 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 01:17:04.740394 ===================================
539 01:17:04.743429 LPDDR4 DRAM CONFIGURATION
540 01:17:04.747305 ===================================
541 01:17:04.747877 EX_ROW_EN[0] = 0x0
542 01:17:04.750989 EX_ROW_EN[1] = 0x0
543 01:17:04.751506 LP4Y_EN = 0x0
544 01:17:04.754740 WORK_FSP = 0x0
545 01:17:04.755207 WL = 0x2
546 01:17:04.758168 RL = 0x2
547 01:17:04.758648 BL = 0x2
548 01:17:04.761831 RPST = 0x0
549 01:17:04.762341 RD_PRE = 0x0
550 01:17:04.765625 WR_PRE = 0x1
551 01:17:04.766140 WR_PST = 0x0
552 01:17:04.768847 DBI_WR = 0x0
553 01:17:04.769322 DBI_RD = 0x0
554 01:17:04.772582 OTF = 0x1
555 01:17:04.776414 ===================================
556 01:17:04.776655 ===================================
557 01:17:04.779892 ANA top config
558 01:17:04.783889 ===================================
559 01:17:04.784083 DLL_ASYNC_EN = 0
560 01:17:04.787531 ALL_SLAVE_EN = 1
561 01:17:04.790993 NEW_RANK_MODE = 1
562 01:17:04.794754 DLL_IDLE_MODE = 1
563 01:17:04.794947 LP45_APHY_COMB_EN = 1
564 01:17:04.798406 TX_ODT_DIS = 1
565 01:17:04.801899 NEW_8X_MODE = 1
566 01:17:04.804823 ===================================
567 01:17:04.808199 ===================================
568 01:17:04.811658 data_rate = 1600
569 01:17:04.811852 CKR = 1
570 01:17:04.814882 DQ_P2S_RATIO = 8
571 01:17:04.818218 ===================================
572 01:17:04.821646 CA_P2S_RATIO = 8
573 01:17:04.825881 DQ_CA_OPEN = 0
574 01:17:04.829628 DQ_SEMI_OPEN = 0
575 01:17:04.830220 CA_SEMI_OPEN = 0
576 01:17:04.833260 CA_FULL_RATE = 0
577 01:17:04.837172 DQ_CKDIV4_EN = 1
578 01:17:04.837712 CA_CKDIV4_EN = 1
579 01:17:04.840655 CA_PREDIV_EN = 0
580 01:17:04.844298 PH8_DLY = 0
581 01:17:04.847488 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 01:17:04.850817 DQ_AAMCK_DIV = 4
583 01:17:04.851289 CA_AAMCK_DIV = 4
584 01:17:04.854472 CA_ADMCK_DIV = 4
585 01:17:04.857861 DQ_TRACK_CA_EN = 0
586 01:17:04.860873 CA_PICK = 800
587 01:17:04.864208 CA_MCKIO = 800
588 01:17:04.867722 MCKIO_SEMI = 0
589 01:17:04.871421 PLL_FREQ = 3068
590 01:17:04.872021 DQ_UI_PI_RATIO = 32
591 01:17:04.874794 CA_UI_PI_RATIO = 0
592 01:17:04.877984 ===================================
593 01:17:04.881102 ===================================
594 01:17:04.884615 memory_type:LPDDR4
595 01:17:04.885098 GP_NUM : 10
596 01:17:04.888608 SRAM_EN : 1
597 01:17:04.892245 MD32_EN : 0
598 01:17:04.892991 ===================================
599 01:17:04.896077 [ANA_INIT] >>>>>>>>>>>>>>
600 01:17:04.899667 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 01:17:04.903059 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 01:17:04.907216 ===================================
603 01:17:04.907689 data_rate = 1600,PCW = 0X7600
604 01:17:04.910964 ===================================
605 01:17:04.914279 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 01:17:04.921500 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 01:17:04.925153 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 01:17:04.931440 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 01:17:04.934612 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 01:17:04.938179 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 01:17:04.938833 [ANA_INIT] flow start
612 01:17:04.941625 [ANA_INIT] PLL >>>>>>>>
613 01:17:04.944762 [ANA_INIT] PLL <<<<<<<<
614 01:17:04.948273 [ANA_INIT] MIDPI >>>>>>>>
615 01:17:04.948849 [ANA_INIT] MIDPI <<<<<<<<
616 01:17:04.951649 [ANA_INIT] DLL >>>>>>>>
617 01:17:04.952118 [ANA_INIT] flow end
618 01:17:04.958179 ============ LP4 DIFF to SE enter ============
619 01:17:04.961412 ============ LP4 DIFF to SE exit ============
620 01:17:04.964668 [ANA_INIT] <<<<<<<<<<<<<
621 01:17:04.967760 [Flow] Enable top DCM control >>>>>
622 01:17:04.971250 [Flow] Enable top DCM control <<<<<
623 01:17:04.974941 Enable DLL master slave shuffle
624 01:17:04.978061 ==============================================================
625 01:17:04.981271 Gating Mode config
626 01:17:04.984186 ==============================================================
627 01:17:04.987978 Config description:
628 01:17:04.997853 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 01:17:05.004605 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 01:17:05.007703 SELPH_MODE 0: By rank 1: By Phase
631 01:17:05.014910 ==============================================================
632 01:17:05.017942 GAT_TRACK_EN = 1
633 01:17:05.020938 RX_GATING_MODE = 2
634 01:17:05.024312 RX_GATING_TRACK_MODE = 2
635 01:17:05.027743 SELPH_MODE = 1
636 01:17:05.028208 PICG_EARLY_EN = 1
637 01:17:05.031415 VALID_LAT_VALUE = 1
638 01:17:05.037790 ==============================================================
639 01:17:05.041561 Enter into Gating configuration >>>>
640 01:17:05.044436 Exit from Gating configuration <<<<
641 01:17:05.047907 Enter into DVFS_PRE_config >>>>>
642 01:17:05.058159 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 01:17:05.061210 Exit from DVFS_PRE_config <<<<<
644 01:17:05.064570 Enter into PICG configuration >>>>
645 01:17:05.067797 Exit from PICG configuration <<<<
646 01:17:05.071148 [RX_INPUT] configuration >>>>>
647 01:17:05.074644 [RX_INPUT] configuration <<<<<
648 01:17:05.077919 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 01:17:05.084717 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 01:17:05.090863 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 01:17:05.097794 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 01:17:05.104646 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 01:17:05.107608 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 01:17:05.114155 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 01:17:05.117430 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 01:17:05.121014 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 01:17:05.124344 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 01:17:05.130917 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 01:17:05.135010 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 01:17:05.137332 ===================================
661 01:17:05.141015 LPDDR4 DRAM CONFIGURATION
662 01:17:05.144226 ===================================
663 01:17:05.144701 EX_ROW_EN[0] = 0x0
664 01:17:05.147680 EX_ROW_EN[1] = 0x0
665 01:17:05.148258 LP4Y_EN = 0x0
666 01:17:05.150654 WORK_FSP = 0x0
667 01:17:05.151122 WL = 0x2
668 01:17:05.154741 RL = 0x2
669 01:17:05.155324 BL = 0x2
670 01:17:05.157514 RPST = 0x0
671 01:17:05.157985 RD_PRE = 0x0
672 01:17:05.160863 WR_PRE = 0x1
673 01:17:05.161330 WR_PST = 0x0
674 01:17:05.164007 DBI_WR = 0x0
675 01:17:05.167848 DBI_RD = 0x0
676 01:17:05.168321 OTF = 0x1
677 01:17:05.170545 ===================================
678 01:17:05.174265 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 01:17:05.177662 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 01:17:05.184087 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 01:17:05.187722 ===================================
682 01:17:05.188206 LPDDR4 DRAM CONFIGURATION
683 01:17:05.190689 ===================================
684 01:17:05.193971 EX_ROW_EN[0] = 0x10
685 01:17:05.197806 EX_ROW_EN[1] = 0x0
686 01:17:05.198454 LP4Y_EN = 0x0
687 01:17:05.201085 WORK_FSP = 0x0
688 01:17:05.201666 WL = 0x2
689 01:17:05.204099 RL = 0x2
690 01:17:05.204677 BL = 0x2
691 01:17:05.207763 RPST = 0x0
692 01:17:05.208237 RD_PRE = 0x0
693 01:17:05.210583 WR_PRE = 0x1
694 01:17:05.211054 WR_PST = 0x0
695 01:17:05.214455 DBI_WR = 0x0
696 01:17:05.215068 DBI_RD = 0x0
697 01:17:05.217559 OTF = 0x1
698 01:17:05.220596 ===================================
699 01:17:05.227310 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 01:17:05.230783 nWR fixed to 40
701 01:17:05.233946 [ModeRegInit_LP4] CH0 RK0
702 01:17:05.234601 [ModeRegInit_LP4] CH0 RK1
703 01:17:05.237585 [ModeRegInit_LP4] CH1 RK0
704 01:17:05.240612 [ModeRegInit_LP4] CH1 RK1
705 01:17:05.241101 match AC timing 12
706 01:17:05.247267 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
707 01:17:05.250565 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 01:17:05.254391 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 01:17:05.260559 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 01:17:05.263659 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 01:17:05.264134 [EMI DOE] emi_dcm 0
712 01:17:05.270459 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 01:17:05.270936 ==
714 01:17:05.273823 Dram Type= 6, Freq= 0, CH_0, rank 0
715 01:17:05.276954 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
716 01:17:05.277450 ==
717 01:17:05.283787 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 01:17:05.286923 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 01:17:05.297850 [CA 0] Center 37 (7~68) winsize 62
720 01:17:05.301129 [CA 1] Center 37 (7~68) winsize 62
721 01:17:05.304242 [CA 2] Center 35 (5~66) winsize 62
722 01:17:05.307383 [CA 3] Center 35 (5~66) winsize 62
723 01:17:05.310786 [CA 4] Center 34 (4~65) winsize 62
724 01:17:05.314293 [CA 5] Center 34 (3~65) winsize 63
725 01:17:05.314766
726 01:17:05.317406 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 01:17:05.317876
728 01:17:05.320854 [CATrainingPosCal] consider 1 rank data
729 01:17:05.324296 u2DelayCellTimex100 = 270/100 ps
730 01:17:05.327316 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
731 01:17:05.330924 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
732 01:17:05.337370 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
733 01:17:05.340669 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
734 01:17:05.344006 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
735 01:17:05.347561 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
736 01:17:05.348037
737 01:17:05.351179 CA PerBit enable=1, Macro0, CA PI delay=34
738 01:17:05.351649
739 01:17:05.354107 [CBTSetCACLKResult] CA Dly = 34
740 01:17:05.354677 CS Dly: 6 (0~37)
741 01:17:05.357615 ==
742 01:17:05.358247 Dram Type= 6, Freq= 0, CH_0, rank 1
743 01:17:05.363926 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
744 01:17:05.364494 ==
745 01:17:05.367739 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 01:17:05.374098 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 01:17:05.383471 [CA 0] Center 37 (6~68) winsize 63
748 01:17:05.386866 [CA 1] Center 37 (6~68) winsize 63
749 01:17:05.390538 [CA 2] Center 35 (4~66) winsize 63
750 01:17:05.393339 [CA 3] Center 34 (4~65) winsize 62
751 01:17:05.396666 [CA 4] Center 33 (3~64) winsize 62
752 01:17:05.399929 [CA 5] Center 33 (3~64) winsize 62
753 01:17:05.400399
754 01:17:05.403688 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 01:17:05.404262
756 01:17:05.406528 [CATrainingPosCal] consider 2 rank data
757 01:17:05.409813 u2DelayCellTimex100 = 270/100 ps
758 01:17:05.413549 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 01:17:05.420187 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 01:17:05.423108 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 01:17:05.426487 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
762 01:17:05.429947 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
763 01:17:05.433169 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 01:17:05.433639
765 01:17:05.436948 CA PerBit enable=1, Macro0, CA PI delay=33
766 01:17:05.437523
767 01:17:05.440289 [CBTSetCACLKResult] CA Dly = 33
768 01:17:05.440759 CS Dly: 6 (0~38)
769 01:17:05.442897
770 01:17:05.446412 ----->DramcWriteLeveling(PI) begin...
771 01:17:05.446971 ==
772 01:17:05.449598 Dram Type= 6, Freq= 0, CH_0, rank 0
773 01:17:05.453105 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
774 01:17:05.453681 ==
775 01:17:05.456534 Write leveling (Byte 0): 30 => 30
776 01:17:05.459862 Write leveling (Byte 1): 30 => 30
777 01:17:05.463176 DramcWriteLeveling(PI) end<-----
778 01:17:05.463645
779 01:17:05.464011 ==
780 01:17:05.466680 Dram Type= 6, Freq= 0, CH_0, rank 0
781 01:17:05.470299 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 01:17:05.470777 ==
783 01:17:05.474008 [Gating] SW mode calibration
784 01:17:05.481137 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 01:17:05.484462 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 01:17:05.488120 0 6 0 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
787 01:17:05.494927 0 6 4 | B1->B0 | 2d2d 2424 | 1 1 | (1 0) (1 0)
788 01:17:05.498386 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 01:17:05.501789 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 01:17:05.508609 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 01:17:05.511918 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 01:17:05.515014 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 01:17:05.521754 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 01:17:05.524858 0 7 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
795 01:17:05.528204 0 7 4 | B1->B0 | 3636 3f3f | 1 0 | (0 0) (0 0)
796 01:17:05.532172 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 01:17:05.538194 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 01:17:05.541825 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 01:17:05.544997 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 01:17:05.551993 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 01:17:05.555176 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 01:17:05.558358 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
803 01:17:05.564991 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
804 01:17:05.568584 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 01:17:05.571662 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 01:17:05.578455 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 01:17:05.581563 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 01:17:05.584919 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 01:17:05.591464 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 01:17:05.594821 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 01:17:05.598190 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 01:17:05.605025 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 01:17:05.608117 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 01:17:05.611531 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 01:17:05.618274 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 01:17:05.621619 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 01:17:05.624614 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
818 01:17:05.631215 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
819 01:17:05.634723 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
820 01:17:05.638117 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
821 01:17:05.641831 Total UI for P1: 0, mck2ui 16
822 01:17:05.644434 best dqsien dly found for B0: ( 0, 10, 4)
823 01:17:05.648039 Total UI for P1: 0, mck2ui 16
824 01:17:05.651117 best dqsien dly found for B1: ( 0, 10, 4)
825 01:17:05.654547 best DQS0 dly(MCK, UI, PI) = (0, 10, 4)
826 01:17:05.657791 best DQS1 dly(MCK, UI, PI) = (0, 10, 4)
827 01:17:05.658338
828 01:17:05.661164 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 4)
829 01:17:05.668125 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 4)
830 01:17:05.668673 [Gating] SW calibration Done
831 01:17:05.669024 ==
832 01:17:05.671057 Dram Type= 6, Freq= 0, CH_0, rank 0
833 01:17:05.678176 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
834 01:17:05.678718 ==
835 01:17:05.679064 RX Vref Scan: 0
836 01:17:05.679385
837 01:17:05.681033 RX Vref 0 -> 0, step: 1
838 01:17:05.681457
839 01:17:05.684579 RX Delay -130 -> 252, step: 16
840 01:17:05.687727 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
841 01:17:05.690997 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
842 01:17:05.694528 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
843 01:17:05.701437 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
844 01:17:05.704596 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
845 01:17:05.707815 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
846 01:17:05.711063 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
847 01:17:05.714359 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
848 01:17:05.721405 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
849 01:17:05.724917 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
850 01:17:05.727838 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
851 01:17:05.731268 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
852 01:17:05.734825 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
853 01:17:05.741148 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
854 01:17:05.744180 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
855 01:17:05.747687 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
856 01:17:05.748163 ==
857 01:17:05.751073 Dram Type= 6, Freq= 0, CH_0, rank 0
858 01:17:05.754290 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
859 01:17:05.754762 ==
860 01:17:05.757600 DQS Delay:
861 01:17:05.758187 DQS0 = 0, DQS1 = 0
862 01:17:05.760870 DQM Delay:
863 01:17:05.761340 DQM0 = 83, DQM1 = 74
864 01:17:05.761721 DQ Delay:
865 01:17:05.764634 DQ0 =77, DQ1 =85, DQ2 =85, DQ3 =77
866 01:17:05.767922 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
867 01:17:05.771354 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
868 01:17:05.774877 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
869 01:17:05.775405
870 01:17:05.775784
871 01:17:05.776130 ==
872 01:17:05.777987 Dram Type= 6, Freq= 0, CH_0, rank 0
873 01:17:05.784303 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
874 01:17:05.784884 ==
875 01:17:05.785261
876 01:17:05.785609
877 01:17:05.787665 TX Vref Scan disable
878 01:17:05.788346 == TX Byte 0 ==
879 01:17:05.790933 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
880 01:17:05.797691 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
881 01:17:05.798204 == TX Byte 1 ==
882 01:17:05.801241 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
883 01:17:05.807785 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
884 01:17:05.808361 ==
885 01:17:05.810912 Dram Type= 6, Freq= 0, CH_0, rank 0
886 01:17:05.813959 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
887 01:17:05.814489 ==
888 01:17:05.827411 TX Vref=22, minBit 3, minWin=27, winSum=445
889 01:17:05.830555 TX Vref=24, minBit 3, minWin=27, winSum=449
890 01:17:05.834127 TX Vref=26, minBit 2, minWin=28, winSum=456
891 01:17:05.837399 TX Vref=28, minBit 2, minWin=28, winSum=457
892 01:17:05.840568 TX Vref=30, minBit 2, minWin=28, winSum=459
893 01:17:05.843775 TX Vref=32, minBit 0, minWin=28, winSum=454
894 01:17:05.850722 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 30
895 01:17:05.851197
896 01:17:05.853794 Final TX Range 1 Vref 30
897 01:17:05.854246
898 01:17:05.854588 ==
899 01:17:05.857322 Dram Type= 6, Freq= 0, CH_0, rank 0
900 01:17:05.860383 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
901 01:17:05.860815 ==
902 01:17:05.861161
903 01:17:05.863686
904 01:17:05.864206 TX Vref Scan disable
905 01:17:05.866948 == TX Byte 0 ==
906 01:17:05.870309 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
907 01:17:05.876923 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
908 01:17:05.877441 == TX Byte 1 ==
909 01:17:05.880092 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
910 01:17:05.886903 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
911 01:17:05.887432
912 01:17:05.887778 [DATLAT]
913 01:17:05.888169 Freq=800, CH0 RK0
914 01:17:05.888665
915 01:17:05.889923 DATLAT Default: 0xa
916 01:17:05.890399 0, 0xFFFF, sum = 0
917 01:17:05.893250 1, 0xFFFF, sum = 0
918 01:17:05.896774 2, 0xFFFF, sum = 0
919 01:17:05.897208 3, 0xFFFF, sum = 0
920 01:17:05.899830 4, 0xFFFF, sum = 0
921 01:17:05.900264 5, 0xFFFF, sum = 0
922 01:17:05.903404 6, 0xFFFF, sum = 0
923 01:17:05.903945 7, 0xFFFF, sum = 0
924 01:17:05.906595 8, 0x0, sum = 1
925 01:17:05.907113 9, 0x0, sum = 2
926 01:17:05.910106 10, 0x0, sum = 3
927 01:17:05.910638 11, 0x0, sum = 4
928 01:17:05.910985 best_step = 9
929 01:17:05.911303
930 01:17:05.913204 ==
931 01:17:05.913629 Dram Type= 6, Freq= 0, CH_0, rank 0
932 01:17:05.920067 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
933 01:17:05.920601 ==
934 01:17:05.920947 RX Vref Scan: 1
935 01:17:05.921268
936 01:17:05.922863 Set Vref Range= 32 -> 127
937 01:17:05.923287
938 01:17:05.926464 RX Vref 32 -> 127, step: 1
939 01:17:05.926971
940 01:17:05.929720 RX Delay -111 -> 252, step: 8
941 01:17:05.930351
942 01:17:05.933221 Set Vref, RX VrefLevel [Byte0]: 32
943 01:17:05.936239 [Byte1]: 32
944 01:17:05.936712
945 01:17:05.939943 Set Vref, RX VrefLevel [Byte0]: 33
946 01:17:05.943185 [Byte1]: 33
947 01:17:05.943652
948 01:17:05.946875 Set Vref, RX VrefLevel [Byte0]: 34
949 01:17:05.949899 [Byte1]: 34
950 01:17:05.953239
951 01:17:05.953791 Set Vref, RX VrefLevel [Byte0]: 35
952 01:17:05.956846 [Byte1]: 35
953 01:17:05.961224
954 01:17:05.961694 Set Vref, RX VrefLevel [Byte0]: 36
955 01:17:05.964244 [Byte1]: 36
956 01:17:05.968833
957 01:17:05.969449 Set Vref, RX VrefLevel [Byte0]: 37
958 01:17:05.972381 [Byte1]: 37
959 01:17:05.976201
960 01:17:05.976746 Set Vref, RX VrefLevel [Byte0]: 38
961 01:17:05.979603 [Byte1]: 38
962 01:17:05.983831
963 01:17:05.984300 Set Vref, RX VrefLevel [Byte0]: 39
964 01:17:05.987364 [Byte1]: 39
965 01:17:05.991342
966 01:17:05.991811 Set Vref, RX VrefLevel [Byte0]: 40
967 01:17:05.994819 [Byte1]: 40
968 01:17:05.998971
969 01:17:05.999438 Set Vref, RX VrefLevel [Byte0]: 41
970 01:17:06.002367 [Byte1]: 41
971 01:17:06.006669
972 01:17:06.007139 Set Vref, RX VrefLevel [Byte0]: 42
973 01:17:06.010077 [Byte1]: 42
974 01:17:06.014653
975 01:17:06.015216 Set Vref, RX VrefLevel [Byte0]: 43
976 01:17:06.018013 [Byte1]: 43
977 01:17:06.022012
978 01:17:06.022520 Set Vref, RX VrefLevel [Byte0]: 44
979 01:17:06.025532 [Byte1]: 44
980 01:17:06.029801
981 01:17:06.030338 Set Vref, RX VrefLevel [Byte0]: 45
982 01:17:06.033258 [Byte1]: 45
983 01:17:06.037358
984 01:17:06.037860 Set Vref, RX VrefLevel [Byte0]: 46
985 01:17:06.040679 [Byte1]: 46
986 01:17:06.044931
987 01:17:06.045436 Set Vref, RX VrefLevel [Byte0]: 47
988 01:17:06.048106 [Byte1]: 47
989 01:17:06.053086
990 01:17:06.053632 Set Vref, RX VrefLevel [Byte0]: 48
991 01:17:06.056552 [Byte1]: 48
992 01:17:06.060141
993 01:17:06.060626 Set Vref, RX VrefLevel [Byte0]: 49
994 01:17:06.063607 [Byte1]: 49
995 01:17:06.067946
996 01:17:06.068428 Set Vref, RX VrefLevel [Byte0]: 50
997 01:17:06.071261 [Byte1]: 50
998 01:17:06.075697
999 01:17:06.076284 Set Vref, RX VrefLevel [Byte0]: 51
1000 01:17:06.078799 [Byte1]: 51
1001 01:17:06.083066
1002 01:17:06.083609 Set Vref, RX VrefLevel [Byte0]: 52
1003 01:17:06.086563 [Byte1]: 52
1004 01:17:06.090804
1005 01:17:06.091274 Set Vref, RX VrefLevel [Byte0]: 53
1006 01:17:06.094154 [Byte1]: 53
1007 01:17:06.098510
1008 01:17:06.098976 Set Vref, RX VrefLevel [Byte0]: 54
1009 01:17:06.101648 [Byte1]: 54
1010 01:17:06.106114
1011 01:17:06.106582 Set Vref, RX VrefLevel [Byte0]: 55
1012 01:17:06.109494 [Byte1]: 55
1013 01:17:06.113978
1014 01:17:06.114605 Set Vref, RX VrefLevel [Byte0]: 56
1015 01:17:06.117057 [Byte1]: 56
1016 01:17:06.121684
1017 01:17:06.122186 Set Vref, RX VrefLevel [Byte0]: 57
1018 01:17:06.125131 [Byte1]: 57
1019 01:17:06.129649
1020 01:17:06.130284 Set Vref, RX VrefLevel [Byte0]: 58
1021 01:17:06.133323 [Byte1]: 58
1022 01:17:06.137732
1023 01:17:06.138449 Set Vref, RX VrefLevel [Byte0]: 59
1024 01:17:06.140566 [Byte1]: 59
1025 01:17:06.144603
1026 01:17:06.145064 Set Vref, RX VrefLevel [Byte0]: 60
1027 01:17:06.147906 [Byte1]: 60
1028 01:17:06.152188
1029 01:17:06.152733 Set Vref, RX VrefLevel [Byte0]: 61
1030 01:17:06.155404 [Byte1]: 61
1031 01:17:06.159936
1032 01:17:06.160488 Set Vref, RX VrefLevel [Byte0]: 62
1033 01:17:06.163465 [Byte1]: 62
1034 01:17:06.167237
1035 01:17:06.167781 Set Vref, RX VrefLevel [Byte0]: 63
1036 01:17:06.170471 [Byte1]: 63
1037 01:17:06.175182
1038 01:17:06.175709 Set Vref, RX VrefLevel [Byte0]: 64
1039 01:17:06.178191 [Byte1]: 64
1040 01:17:06.182856
1041 01:17:06.183338 Set Vref, RX VrefLevel [Byte0]: 65
1042 01:17:06.185817 [Byte1]: 65
1043 01:17:06.190175
1044 01:17:06.190800 Set Vref, RX VrefLevel [Byte0]: 66
1045 01:17:06.193600 [Byte1]: 66
1046 01:17:06.197811
1047 01:17:06.198321 Set Vref, RX VrefLevel [Byte0]: 67
1048 01:17:06.201403 [Byte1]: 67
1049 01:17:06.205753
1050 01:17:06.206261 Set Vref, RX VrefLevel [Byte0]: 68
1051 01:17:06.209056 [Byte1]: 68
1052 01:17:06.212978
1053 01:17:06.213437 Set Vref, RX VrefLevel [Byte0]: 69
1054 01:17:06.216538 [Byte1]: 69
1055 01:17:06.220951
1056 01:17:06.221483 Set Vref, RX VrefLevel [Byte0]: 70
1057 01:17:06.224411 [Byte1]: 70
1058 01:17:06.228471
1059 01:17:06.228935 Set Vref, RX VrefLevel [Byte0]: 71
1060 01:17:06.231982 [Byte1]: 71
1061 01:17:06.236511
1062 01:17:06.237191 Set Vref, RX VrefLevel [Byte0]: 72
1063 01:17:06.239841 [Byte1]: 72
1064 01:17:06.243505
1065 01:17:06.244084 Set Vref, RX VrefLevel [Byte0]: 73
1066 01:17:06.246954 [Byte1]: 73
1067 01:17:06.251519
1068 01:17:06.252037 Set Vref, RX VrefLevel [Byte0]: 74
1069 01:17:06.254464 [Byte1]: 74
1070 01:17:06.259583
1071 01:17:06.260233 Set Vref, RX VrefLevel [Byte0]: 75
1072 01:17:06.262384 [Byte1]: 75
1073 01:17:06.266514
1074 01:17:06.267081 Set Vref, RX VrefLevel [Byte0]: 76
1075 01:17:06.270245 [Byte1]: 76
1076 01:17:06.274070
1077 01:17:06.274506 Set Vref, RX VrefLevel [Byte0]: 77
1078 01:17:06.277441 [Byte1]: 77
1079 01:17:06.282103
1080 01:17:06.282570 Final RX Vref Byte 0 = 54 to rank0
1081 01:17:06.285451 Final RX Vref Byte 1 = 56 to rank0
1082 01:17:06.288491 Final RX Vref Byte 0 = 54 to rank1
1083 01:17:06.292210 Final RX Vref Byte 1 = 56 to rank1==
1084 01:17:06.295102 Dram Type= 6, Freq= 0, CH_0, rank 0
1085 01:17:06.302175 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1086 01:17:06.302633 ==
1087 01:17:06.302969 DQS Delay:
1088 01:17:06.303283 DQS0 = 0, DQS1 = 0
1089 01:17:06.305348 DQM Delay:
1090 01:17:06.305874 DQM0 = 83, DQM1 = 74
1091 01:17:06.308560 DQ Delay:
1092 01:17:06.311918 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1093 01:17:06.312374 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1094 01:17:06.315591 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1095 01:17:06.318603 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1096 01:17:06.322062
1097 01:17:06.322491
1098 01:17:06.328374 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e2e, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
1099 01:17:06.331884 CH0 RK0: MR19=606, MR18=2E2E
1100 01:17:06.338523 CH0_RK0: MR19=0x606, MR18=0x2E2E, DQSOSC=398, MR23=63, INC=93, DEC=62
1101 01:17:06.338982
1102 01:17:06.342116 ----->DramcWriteLeveling(PI) begin...
1103 01:17:06.342587 ==
1104 01:17:06.345098 Dram Type= 6, Freq= 0, CH_0, rank 1
1105 01:17:06.348512 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1106 01:17:06.349166 ==
1107 01:17:06.351765 Write leveling (Byte 0): 29 => 29
1108 01:17:06.355431 Write leveling (Byte 1): 29 => 29
1109 01:17:06.358490 DramcWriteLeveling(PI) end<-----
1110 01:17:06.358912
1111 01:17:06.359246 ==
1112 01:17:06.361720 Dram Type= 6, Freq= 0, CH_0, rank 1
1113 01:17:06.365113 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1114 01:17:06.365645 ==
1115 01:17:06.368203 [Gating] SW mode calibration
1116 01:17:06.374750 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1117 01:17:06.381579 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1118 01:17:06.384960 0 6 0 | B1->B0 | 2f2f 3030 | 1 0 | (1 0) (0 1)
1119 01:17:06.388034 0 6 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1120 01:17:06.395109 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1121 01:17:06.398212 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1122 01:17:06.401388 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1123 01:17:06.408384 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1124 01:17:06.411385 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1125 01:17:06.414960 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1126 01:17:06.421510 0 7 0 | B1->B0 | 2828 3131 | 0 0 | (0 0) (0 0)
1127 01:17:06.424904 0 7 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1128 01:17:06.427985 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1129 01:17:06.435016 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1130 01:17:06.438345 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1131 01:17:06.441495 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1132 01:17:06.448326 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1133 01:17:06.451642 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1134 01:17:06.454708 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1135 01:17:06.461187 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 01:17:06.464757 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 01:17:06.468056 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1138 01:17:06.474496 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1139 01:17:06.477945 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1140 01:17:06.481369 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1141 01:17:06.487902 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1142 01:17:06.491318 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1143 01:17:06.494601 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1144 01:17:06.497703 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1145 01:17:06.504349 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1146 01:17:06.507674 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1147 01:17:06.511208 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1148 01:17:06.518410 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1149 01:17:06.521135 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1150 01:17:06.524508 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1151 01:17:06.531101 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1152 01:17:06.534498 Total UI for P1: 0, mck2ui 16
1153 01:17:06.538086 best dqsien dly found for B1: ( 0, 10, 0)
1154 01:17:06.582124 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1155 01:17:06.582712 Total UI for P1: 0, mck2ui 16
1156 01:17:06.583100 best dqsien dly found for B0: ( 0, 10, 2)
1157 01:17:06.583450 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1158 01:17:06.583813 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1159 01:17:06.584172
1160 01:17:06.584496 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1161 01:17:06.585165 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1162 01:17:06.585512 [Gating] SW calibration Done
1163 01:17:06.585831 ==
1164 01:17:06.586189 Dram Type= 6, Freq= 0, CH_0, rank 1
1165 01:17:06.586506 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1166 01:17:06.586822 ==
1167 01:17:06.587131 RX Vref Scan: 0
1168 01:17:06.587440
1169 01:17:06.587748 RX Vref 0 -> 0, step: 1
1170 01:17:06.588053
1171 01:17:06.588359 RX Delay -130 -> 252, step: 16
1172 01:17:06.610264 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1173 01:17:06.610834 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1174 01:17:06.611216 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1175 01:17:06.611917 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1176 01:17:06.612282 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1177 01:17:06.612621 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1178 01:17:06.612947 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1179 01:17:06.614374 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1180 01:17:06.614844 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1181 01:17:06.620771 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1182 01:17:06.624185 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1183 01:17:06.627603 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1184 01:17:06.631109 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1185 01:17:06.634288 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1186 01:17:06.641503 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1187 01:17:06.644621 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1188 01:17:06.645088 ==
1189 01:17:06.647650 Dram Type= 6, Freq= 0, CH_0, rank 1
1190 01:17:06.651122 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1191 01:17:06.651564 ==
1192 01:17:06.654382 DQS Delay:
1193 01:17:06.654845 DQS0 = 0, DQS1 = 0
1194 01:17:06.655218 DQM Delay:
1195 01:17:06.657859 DQM0 = 82, DQM1 = 74
1196 01:17:06.658484 DQ Delay:
1197 01:17:06.660939 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1198 01:17:06.664133 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1199 01:17:06.668096 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1200 01:17:06.671042 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1201 01:17:06.671511
1202 01:17:06.671891
1203 01:17:06.672418 ==
1204 01:17:06.674151 Dram Type= 6, Freq= 0, CH_0, rank 1
1205 01:17:06.680781 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1206 01:17:06.681300 ==
1207 01:17:06.681681
1208 01:17:06.682347
1209 01:17:06.682706 TX Vref Scan disable
1210 01:17:06.684422 == TX Byte 0 ==
1211 01:17:06.688219 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1212 01:17:06.694500 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1213 01:17:06.694926 == TX Byte 1 ==
1214 01:17:06.697497 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1215 01:17:06.704106 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1216 01:17:06.704530 ==
1217 01:17:06.707729 Dram Type= 6, Freq= 0, CH_0, rank 1
1218 01:17:06.710958 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1219 01:17:06.711386 ==
1220 01:17:06.723083 TX Vref=22, minBit 0, minWin=27, winSum=449
1221 01:17:06.726516 TX Vref=24, minBit 0, minWin=27, winSum=452
1222 01:17:06.730213 TX Vref=26, minBit 2, minWin=28, winSum=455
1223 01:17:06.733572 TX Vref=28, minBit 2, minWin=28, winSum=458
1224 01:17:06.737040 TX Vref=30, minBit 2, minWin=28, winSum=461
1225 01:17:06.740886 TX Vref=32, minBit 0, minWin=28, winSum=457
1226 01:17:06.747495 [TxChooseVref] Worse bit 2, Min win 28, Win sum 461, Final Vref 30
1227 01:17:06.747923
1228 01:17:06.750608 Final TX Range 1 Vref 30
1229 01:17:06.751075
1230 01:17:06.751444 ==
1231 01:17:06.754083 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 01:17:06.757017 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1233 01:17:06.757485 ==
1234 01:17:06.757827
1235 01:17:06.758177
1236 01:17:06.760309 TX Vref Scan disable
1237 01:17:06.763629 == TX Byte 0 ==
1238 01:17:06.767044 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1239 01:17:06.770503 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1240 01:17:06.773650 == TX Byte 1 ==
1241 01:17:06.777066 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1242 01:17:06.780499 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1243 01:17:06.781071
1244 01:17:06.783973 [DATLAT]
1245 01:17:06.784542 Freq=800, CH0 RK1
1246 01:17:06.784919
1247 01:17:06.787236 DATLAT Default: 0x9
1248 01:17:06.787699 0, 0xFFFF, sum = 0
1249 01:17:06.790265 1, 0xFFFF, sum = 0
1250 01:17:06.790860 2, 0xFFFF, sum = 0
1251 01:17:06.793448 3, 0xFFFF, sum = 0
1252 01:17:06.793963 4, 0xFFFF, sum = 0
1253 01:17:06.796557 5, 0xFFFF, sum = 0
1254 01:17:06.797057 6, 0xFFFF, sum = 0
1255 01:17:06.800129 7, 0xFFFF, sum = 0
1256 01:17:06.800606 8, 0x0, sum = 1
1257 01:17:06.803770 9, 0x0, sum = 2
1258 01:17:06.804504 10, 0x0, sum = 3
1259 01:17:06.806698 11, 0x0, sum = 4
1260 01:17:06.807174 best_step = 9
1261 01:17:06.807545
1262 01:17:06.807890 ==
1263 01:17:06.810135 Dram Type= 6, Freq= 0, CH_0, rank 1
1264 01:17:06.813655 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1265 01:17:06.816730 ==
1266 01:17:06.817205 RX Vref Scan: 0
1267 01:17:06.817575
1268 01:17:06.820081 RX Vref 0 -> 0, step: 1
1269 01:17:06.820600
1270 01:17:06.823528 RX Delay -111 -> 252, step: 8
1271 01:17:06.826711 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1272 01:17:06.830260 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1273 01:17:06.833641 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1274 01:17:06.840206 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1275 01:17:06.843794 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1276 01:17:06.847178 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1277 01:17:06.849981 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1278 01:17:06.853558 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1279 01:17:06.860451 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1280 01:17:06.863637 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1281 01:17:06.867098 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1282 01:17:06.870068 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1283 01:17:06.873311 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1284 01:17:06.880088 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1285 01:17:06.883272 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1286 01:17:06.886677 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1287 01:17:06.887215 ==
1288 01:17:06.889872 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 01:17:06.893236 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1290 01:17:06.896753 ==
1291 01:17:06.897218 DQS Delay:
1292 01:17:06.897586 DQS0 = 0, DQS1 = 0
1293 01:17:06.899886 DQM Delay:
1294 01:17:06.900346 DQM0 = 86, DQM1 = 75
1295 01:17:06.903157 DQ Delay:
1296 01:17:06.903616 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1297 01:17:06.906470 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1298 01:17:06.910191 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1299 01:17:06.912758 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1300 01:17:06.913290
1301 01:17:06.916294
1302 01:17:06.922900 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f3f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1303 01:17:06.926139 CH0 RK1: MR19=606, MR18=3F3F
1304 01:17:06.933346 CH0_RK1: MR19=0x606, MR18=0x3F3F, DQSOSC=393, MR23=63, INC=95, DEC=63
1305 01:17:06.936432 [RxdqsGatingPostProcess] freq 800
1306 01:17:06.939414 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1307 01:17:06.943524 Pre-setting of DQS Precalculation
1308 01:17:06.946143 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1309 01:17:06.949686 ==
1310 01:17:06.952992 Dram Type= 6, Freq= 0, CH_1, rank 0
1311 01:17:06.955898 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1312 01:17:06.956363 ==
1313 01:17:06.959374 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1314 01:17:06.966011 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1315 01:17:06.975880 [CA 0] Center 37 (6~68) winsize 63
1316 01:17:06.979356 [CA 1] Center 37 (6~68) winsize 63
1317 01:17:06.982548 [CA 2] Center 34 (4~65) winsize 62
1318 01:17:06.985731 [CA 3] Center 34 (4~65) winsize 62
1319 01:17:06.989129 [CA 4] Center 33 (3~64) winsize 62
1320 01:17:06.992742 [CA 5] Center 33 (3~64) winsize 62
1321 01:17:06.993290
1322 01:17:06.995565 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1323 01:17:06.996024
1324 01:17:06.999277 [CATrainingPosCal] consider 1 rank data
1325 01:17:07.002201 u2DelayCellTimex100 = 270/100 ps
1326 01:17:07.006091 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1327 01:17:07.008933 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1328 01:17:07.015844 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1329 01:17:07.019207 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1330 01:17:07.022725 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1331 01:17:07.025746 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1332 01:17:07.026239
1333 01:17:07.029891 CA PerBit enable=1, Macro0, CA PI delay=33
1334 01:17:07.030494
1335 01:17:07.032712 [CBTSetCACLKResult] CA Dly = 33
1336 01:17:07.033265 CS Dly: 4 (0~35)
1337 01:17:07.033629 ==
1338 01:17:07.035650 Dram Type= 6, Freq= 0, CH_1, rank 1
1339 01:17:07.042663 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1340 01:17:07.043522 ==
1341 01:17:07.045661 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1342 01:17:07.052326 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1343 01:17:07.061829 [CA 0] Center 37 (6~68) winsize 63
1344 01:17:07.065218 [CA 1] Center 37 (6~68) winsize 63
1345 01:17:07.068717 [CA 2] Center 34 (4~65) winsize 62
1346 01:17:07.071967 [CA 3] Center 34 (4~65) winsize 62
1347 01:17:07.074945 [CA 4] Center 33 (3~64) winsize 62
1348 01:17:07.078424 [CA 5] Center 33 (3~64) winsize 62
1349 01:17:07.079169
1350 01:17:07.081374 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1351 01:17:07.082092
1352 01:17:07.085051 [CATrainingPosCal] consider 2 rank data
1353 01:17:07.088302 u2DelayCellTimex100 = 270/100 ps
1354 01:17:07.091742 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1355 01:17:07.094794 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1356 01:17:07.101426 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1357 01:17:07.105122 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1358 01:17:07.108238 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1359 01:17:07.111370 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1360 01:17:07.111832
1361 01:17:07.115052 CA PerBit enable=1, Macro0, CA PI delay=33
1362 01:17:07.115510
1363 01:17:07.118131 [CBTSetCACLKResult] CA Dly = 33
1364 01:17:07.118615 CS Dly: 4 (0~36)
1365 01:17:07.118981
1366 01:17:07.121643 ----->DramcWriteLeveling(PI) begin...
1367 01:17:07.125011 ==
1368 01:17:07.128402 Dram Type= 6, Freq= 0, CH_1, rank 0
1369 01:17:07.131414 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1370 01:17:07.131877 ==
1371 01:17:07.134690 Write leveling (Byte 0): 28 => 28
1372 01:17:07.137967 Write leveling (Byte 1): 23 => 23
1373 01:17:07.141335 DramcWriteLeveling(PI) end<-----
1374 01:17:07.141827
1375 01:17:07.142216 ==
1376 01:17:07.144766 Dram Type= 6, Freq= 0, CH_1, rank 0
1377 01:17:07.148088 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1378 01:17:07.148608 ==
1379 01:17:07.151562 [Gating] SW mode calibration
1380 01:17:07.157781 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1381 01:17:07.161525 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1382 01:17:07.167839 0 6 0 | B1->B0 | 3030 2626 | 1 0 | (0 0) (0 0)
1383 01:17:07.171446 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1384 01:17:07.174504 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1385 01:17:07.181334 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1386 01:17:07.184603 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1387 01:17:07.187963 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1388 01:17:07.194889 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1389 01:17:07.197790 0 6 28 | B1->B0 | 2525 2b2b | 0 0 | (0 0) (0 0)
1390 01:17:07.201533 0 7 0 | B1->B0 | 2f2f 4545 | 0 1 | (1 1) (0 0)
1391 01:17:07.207910 0 7 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1392 01:17:07.211481 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1393 01:17:07.214639 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1394 01:17:07.221237 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1395 01:17:07.224670 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1396 01:17:07.227865 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1397 01:17:07.234594 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1398 01:17:07.238542 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1399 01:17:07.241558 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 01:17:07.248050 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1401 01:17:07.251365 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1402 01:17:07.254964 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1403 01:17:07.261460 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1404 01:17:07.265159 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1405 01:17:07.268064 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1406 01:17:07.271141 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1407 01:17:07.278094 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1408 01:17:07.281319 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1409 01:17:07.284606 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1410 01:17:07.291511 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1411 01:17:07.294568 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1412 01:17:07.297937 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1413 01:17:07.305147 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1414 01:17:07.307864 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1415 01:17:07.311586 Total UI for P1: 0, mck2ui 16
1416 01:17:07.314850 best dqsien dly found for B0: ( 0, 9, 28)
1417 01:17:07.318078 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1418 01:17:07.321242 Total UI for P1: 0, mck2ui 16
1419 01:17:07.324605 best dqsien dly found for B1: ( 0, 10, 0)
1420 01:17:07.328236 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1421 01:17:07.331209 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1422 01:17:07.331668
1423 01:17:07.337651 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1424 01:17:07.341096 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1425 01:17:07.344376 [Gating] SW calibration Done
1426 01:17:07.344830 ==
1427 01:17:07.348160 Dram Type= 6, Freq= 0, CH_1, rank 0
1428 01:17:07.350961 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1429 01:17:07.351423 ==
1430 01:17:07.351789 RX Vref Scan: 0
1431 01:17:07.352128
1432 01:17:07.354384 RX Vref 0 -> 0, step: 1
1433 01:17:07.354843
1434 01:17:07.358172 RX Delay -130 -> 252, step: 16
1435 01:17:07.361149 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1436 01:17:07.364686 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1437 01:17:07.371209 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1438 01:17:07.374841 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1439 01:17:07.378740 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1440 01:17:07.382111 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1441 01:17:07.385787 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1442 01:17:07.389261 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1443 01:17:07.392868 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1444 01:17:07.396467 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1445 01:17:07.400405 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1446 01:17:07.404006 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1447 01:17:07.411090 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1448 01:17:07.414560 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1449 01:17:07.417420 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1450 01:17:07.421068 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1451 01:17:07.421482 ==
1452 01:17:07.424120 Dram Type= 6, Freq= 0, CH_1, rank 0
1453 01:17:07.430852 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1454 01:17:07.431272 ==
1455 01:17:07.431599 DQS Delay:
1456 01:17:07.431905 DQS0 = 0, DQS1 = 0
1457 01:17:07.434514 DQM Delay:
1458 01:17:07.434929 DQM0 = 81, DQM1 = 73
1459 01:17:07.437604 DQ Delay:
1460 01:17:07.440844 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1461 01:17:07.443861 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1462 01:17:07.444277 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1463 01:17:07.450889 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1464 01:17:07.451304
1465 01:17:07.451630
1466 01:17:07.451933 ==
1467 01:17:07.454120 Dram Type= 6, Freq= 0, CH_1, rank 0
1468 01:17:07.457598 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1469 01:17:07.458158 ==
1470 01:17:07.458501
1471 01:17:07.458807
1472 01:17:07.460902 TX Vref Scan disable
1473 01:17:07.461452 == TX Byte 0 ==
1474 01:17:07.467244 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1475 01:17:07.470794 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1476 01:17:07.471252 == TX Byte 1 ==
1477 01:17:07.477335 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1478 01:17:07.480933 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1479 01:17:07.481456 ==
1480 01:17:07.484322 Dram Type= 6, Freq= 0, CH_1, rank 0
1481 01:17:07.487294 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1482 01:17:07.487710 ==
1483 01:17:07.501833 TX Vref=22, minBit 3, minWin=27, winSum=448
1484 01:17:07.505295 TX Vref=24, minBit 3, minWin=27, winSum=448
1485 01:17:07.508406 TX Vref=26, minBit 3, minWin=27, winSum=452
1486 01:17:07.511324 TX Vref=28, minBit 0, minWin=28, winSum=461
1487 01:17:07.515152 TX Vref=30, minBit 0, minWin=28, winSum=460
1488 01:17:07.521798 TX Vref=32, minBit 0, minWin=28, winSum=458
1489 01:17:07.525031 [TxChooseVref] Worse bit 0, Min win 28, Win sum 461, Final Vref 28
1490 01:17:07.525778
1491 01:17:07.528568 Final TX Range 1 Vref 28
1492 01:17:07.529122
1493 01:17:07.529492 ==
1494 01:17:07.531499 Dram Type= 6, Freq= 0, CH_1, rank 0
1495 01:17:07.534746 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1496 01:17:07.535231 ==
1497 01:17:07.537881
1498 01:17:07.538403
1499 01:17:07.538769 TX Vref Scan disable
1500 01:17:07.541740 == TX Byte 0 ==
1501 01:17:07.545128 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1502 01:17:07.551459 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1503 01:17:07.551924 == TX Byte 1 ==
1504 01:17:07.554821 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1505 01:17:07.558389 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1506 01:17:07.561766
1507 01:17:07.562366 [DATLAT]
1508 01:17:07.562738 Freq=800, CH1 RK0
1509 01:17:07.563084
1510 01:17:07.565363 DATLAT Default: 0xa
1511 01:17:07.565927 0, 0xFFFF, sum = 0
1512 01:17:07.567995 1, 0xFFFF, sum = 0
1513 01:17:07.568466 2, 0xFFFF, sum = 0
1514 01:17:07.571660 3, 0xFFFF, sum = 0
1515 01:17:07.574631 4, 0xFFFF, sum = 0
1516 01:17:07.575099 5, 0xFFFF, sum = 0
1517 01:17:07.578537 6, 0xFFFF, sum = 0
1518 01:17:07.579005 7, 0xFFFF, sum = 0
1519 01:17:07.581332 8, 0x0, sum = 1
1520 01:17:07.581895 9, 0x0, sum = 2
1521 01:17:07.582303 10, 0x0, sum = 3
1522 01:17:07.584750 11, 0x0, sum = 4
1523 01:17:07.585220 best_step = 9
1524 01:17:07.585595
1525 01:17:07.585940 ==
1526 01:17:07.587689 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 01:17:07.594628 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1528 01:17:07.595236 ==
1529 01:17:07.595614 RX Vref Scan: 1
1530 01:17:07.595966
1531 01:17:07.598150 Set Vref Range= 32 -> 127
1532 01:17:07.598691
1533 01:17:07.601534 RX Vref 32 -> 127, step: 1
1534 01:17:07.601995
1535 01:17:07.605042 RX Delay -111 -> 252, step: 8
1536 01:17:07.605598
1537 01:17:07.608169 Set Vref, RX VrefLevel [Byte0]: 32
1538 01:17:07.611397 [Byte1]: 32
1539 01:17:07.611873
1540 01:17:07.614476 Set Vref, RX VrefLevel [Byte0]: 33
1541 01:17:07.617963 [Byte1]: 33
1542 01:17:07.618473
1543 01:17:07.621166 Set Vref, RX VrefLevel [Byte0]: 34
1544 01:17:07.624666 [Byte1]: 34
1545 01:17:07.628141
1546 01:17:07.628711 Set Vref, RX VrefLevel [Byte0]: 35
1547 01:17:07.631543 [Byte1]: 35
1548 01:17:07.636033
1549 01:17:07.636580 Set Vref, RX VrefLevel [Byte0]: 36
1550 01:17:07.638636 [Byte1]: 36
1551 01:17:07.643059
1552 01:17:07.643646 Set Vref, RX VrefLevel [Byte0]: 37
1553 01:17:07.646639 [Byte1]: 37
1554 01:17:07.651030
1555 01:17:07.651585 Set Vref, RX VrefLevel [Byte0]: 38
1556 01:17:07.653833 [Byte1]: 38
1557 01:17:07.658465
1558 01:17:07.658928 Set Vref, RX VrefLevel [Byte0]: 39
1559 01:17:07.661634 [Byte1]: 39
1560 01:17:07.666008
1561 01:17:07.666628 Set Vref, RX VrefLevel [Byte0]: 40
1562 01:17:07.669624 [Byte1]: 40
1563 01:17:07.673623
1564 01:17:07.674156 Set Vref, RX VrefLevel [Byte0]: 41
1565 01:17:07.677083 [Byte1]: 41
1566 01:17:07.681421
1567 01:17:07.681955 Set Vref, RX VrefLevel [Byte0]: 42
1568 01:17:07.684456 [Byte1]: 42
1569 01:17:07.688993
1570 01:17:07.689456 Set Vref, RX VrefLevel [Byte0]: 43
1571 01:17:07.692444 [Byte1]: 43
1572 01:17:07.696553
1573 01:17:07.697130 Set Vref, RX VrefLevel [Byte0]: 44
1574 01:17:07.699839 [Byte1]: 44
1575 01:17:07.704991
1576 01:17:07.705542 Set Vref, RX VrefLevel [Byte0]: 45
1577 01:17:07.707461 [Byte1]: 45
1578 01:17:07.712114
1579 01:17:07.712719 Set Vref, RX VrefLevel [Byte0]: 46
1580 01:17:07.715357 [Byte1]: 46
1581 01:17:07.719839
1582 01:17:07.720393 Set Vref, RX VrefLevel [Byte0]: 47
1583 01:17:07.722900 [Byte1]: 47
1584 01:17:07.726950
1585 01:17:07.727410 Set Vref, RX VrefLevel [Byte0]: 48
1586 01:17:07.730517 [Byte1]: 48
1587 01:17:07.734800
1588 01:17:07.735353 Set Vref, RX VrefLevel [Byte0]: 49
1589 01:17:07.738208 [Byte1]: 49
1590 01:17:07.742623
1591 01:17:07.743181 Set Vref, RX VrefLevel [Byte0]: 50
1592 01:17:07.745714 [Byte1]: 50
1593 01:17:07.750583
1594 01:17:07.751049 Set Vref, RX VrefLevel [Byte0]: 51
1595 01:17:07.753900 [Byte1]: 51
1596 01:17:07.757664
1597 01:17:07.758163 Set Vref, RX VrefLevel [Byte0]: 52
1598 01:17:07.761124 [Byte1]: 52
1599 01:17:07.765172
1600 01:17:07.765635 Set Vref, RX VrefLevel [Byte0]: 53
1601 01:17:07.768720 [Byte1]: 53
1602 01:17:07.773196
1603 01:17:07.773659 Set Vref, RX VrefLevel [Byte0]: 54
1604 01:17:07.776317 [Byte1]: 54
1605 01:17:07.780719
1606 01:17:07.781153 Set Vref, RX VrefLevel [Byte0]: 55
1607 01:17:07.783865 [Byte1]: 55
1608 01:17:07.788302
1609 01:17:07.788721 Set Vref, RX VrefLevel [Byte0]: 56
1610 01:17:07.791558 [Byte1]: 56
1611 01:17:07.796308
1612 01:17:07.796727 Set Vref, RX VrefLevel [Byte0]: 57
1613 01:17:07.799331 [Byte1]: 57
1614 01:17:07.803640
1615 01:17:07.804063 Set Vref, RX VrefLevel [Byte0]: 58
1616 01:17:07.807230 [Byte1]: 58
1617 01:17:07.811262
1618 01:17:07.811681 Set Vref, RX VrefLevel [Byte0]: 59
1619 01:17:07.814485 [Byte1]: 59
1620 01:17:07.818712
1621 01:17:07.819133 Set Vref, RX VrefLevel [Byte0]: 60
1622 01:17:07.821969 [Byte1]: 60
1623 01:17:07.826364
1624 01:17:07.826788 Set Vref, RX VrefLevel [Byte0]: 61
1625 01:17:07.829878 [Byte1]: 61
1626 01:17:07.834211
1627 01:17:07.834628 Set Vref, RX VrefLevel [Byte0]: 62
1628 01:17:07.837706 [Byte1]: 62
1629 01:17:07.842130
1630 01:17:07.842687 Set Vref, RX VrefLevel [Byte0]: 63
1631 01:17:07.844982 [Byte1]: 63
1632 01:17:07.849562
1633 01:17:07.849987 Set Vref, RX VrefLevel [Byte0]: 64
1634 01:17:07.852642 [Byte1]: 64
1635 01:17:07.857322
1636 01:17:07.857837 Set Vref, RX VrefLevel [Byte0]: 65
1637 01:17:07.860683 [Byte1]: 65
1638 01:17:07.864673
1639 01:17:07.865094 Set Vref, RX VrefLevel [Byte0]: 66
1640 01:17:07.868327 [Byte1]: 66
1641 01:17:07.872616
1642 01:17:07.873035 Set Vref, RX VrefLevel [Byte0]: 67
1643 01:17:07.876310 [Byte1]: 67
1644 01:17:07.880687
1645 01:17:07.881228 Set Vref, RX VrefLevel [Byte0]: 68
1646 01:17:07.883521 [Byte1]: 68
1647 01:17:07.887763
1648 01:17:07.888301 Set Vref, RX VrefLevel [Byte0]: 69
1649 01:17:07.891256 [Byte1]: 69
1650 01:17:07.895409
1651 01:17:07.895970 Set Vref, RX VrefLevel [Byte0]: 70
1652 01:17:07.898643 [Byte1]: 70
1653 01:17:07.903060
1654 01:17:07.903527 Set Vref, RX VrefLevel [Byte0]: 71
1655 01:17:07.906204 [Byte1]: 71
1656 01:17:07.910932
1657 01:17:07.911479 Set Vref, RX VrefLevel [Byte0]: 72
1658 01:17:07.913987 [Byte1]: 72
1659 01:17:07.918577
1660 01:17:07.919115 Set Vref, RX VrefLevel [Byte0]: 73
1661 01:17:07.921604 [Byte1]: 73
1662 01:17:07.925855
1663 01:17:07.926426 Set Vref, RX VrefLevel [Byte0]: 74
1664 01:17:07.929259 [Byte1]: 74
1665 01:17:07.933466
1666 01:17:07.933946 Set Vref, RX VrefLevel [Byte0]: 75
1667 01:17:07.937248 [Byte1]: 75
1668 01:17:07.941527
1669 01:17:07.942113 Set Vref, RX VrefLevel [Byte0]: 76
1670 01:17:07.944524 [Byte1]: 76
1671 01:17:07.949348
1672 01:17:07.949875 Set Vref, RX VrefLevel [Byte0]: 77
1673 01:17:07.952379 [Byte1]: 77
1674 01:17:07.956879
1675 01:17:07.957403 Set Vref, RX VrefLevel [Byte0]: 78
1676 01:17:07.960044 [Byte1]: 78
1677 01:17:07.964093
1678 01:17:07.964518 Final RX Vref Byte 0 = 60 to rank0
1679 01:17:07.967548 Final RX Vref Byte 1 = 56 to rank0
1680 01:17:07.970786 Final RX Vref Byte 0 = 60 to rank1
1681 01:17:07.974380 Final RX Vref Byte 1 = 56 to rank1==
1682 01:17:07.977764 Dram Type= 6, Freq= 0, CH_1, rank 0
1683 01:17:07.984486 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1684 01:17:07.985045 ==
1685 01:17:07.985422 DQS Delay:
1686 01:17:07.985770 DQS0 = 0, DQS1 = 0
1687 01:17:07.987995 DQM Delay:
1688 01:17:07.988558 DQM0 = 81, DQM1 = 74
1689 01:17:07.990948 DQ Delay:
1690 01:17:07.994276 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1691 01:17:07.994742 DQ4 =80, DQ5 =96, DQ6 =88, DQ7 =76
1692 01:17:07.997654 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
1693 01:17:08.000915 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =84
1694 01:17:08.004670
1695 01:17:08.005088
1696 01:17:08.010980 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e4e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1697 01:17:08.014422 CH1 RK0: MR19=606, MR18=4E4E
1698 01:17:08.020869 CH1_RK0: MR19=0x606, MR18=0x4E4E, DQSOSC=390, MR23=63, INC=97, DEC=64
1699 01:17:08.021294
1700 01:17:08.024179 ----->DramcWriteLeveling(PI) begin...
1701 01:17:08.024616 ==
1702 01:17:08.027570 Dram Type= 6, Freq= 0, CH_1, rank 1
1703 01:17:08.031200 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1704 01:17:08.031747 ==
1705 01:17:08.034133 Write leveling (Byte 0): 24 => 24
1706 01:17:08.037472 Write leveling (Byte 1): 23 => 23
1707 01:17:08.041163 DramcWriteLeveling(PI) end<-----
1708 01:17:08.041690
1709 01:17:08.042065 ==
1710 01:17:08.044156 Dram Type= 6, Freq= 0, CH_1, rank 1
1711 01:17:08.047488 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1712 01:17:08.047908 ==
1713 01:17:08.050815 [Gating] SW mode calibration
1714 01:17:08.057275 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1715 01:17:08.064268 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1716 01:17:08.067609 0 6 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
1717 01:17:08.070964 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1718 01:17:08.077475 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1719 01:17:08.080557 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1720 01:17:08.084213 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1721 01:17:08.090643 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1722 01:17:08.094410 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1723 01:17:08.097352 0 6 28 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
1724 01:17:08.103768 0 7 0 | B1->B0 | 3737 4545 | 0 0 | (0 0) (0 0)
1725 01:17:08.107591 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1726 01:17:08.110433 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1727 01:17:08.117369 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1728 01:17:08.120568 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1729 01:17:08.123789 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1730 01:17:08.130788 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1731 01:17:08.133884 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1732 01:17:08.137473 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1733 01:17:08.144181 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1734 01:17:08.147251 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1735 01:17:08.150537 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1736 01:17:08.157006 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1737 01:17:08.160512 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1738 01:17:08.163629 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1739 01:17:08.167001 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1740 01:17:08.173893 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1741 01:17:08.177186 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1742 01:17:08.180547 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1743 01:17:08.186822 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1744 01:17:08.190241 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1745 01:17:08.193580 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1746 01:17:08.200521 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1747 01:17:08.203621 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1748 01:17:08.207437 Total UI for P1: 0, mck2ui 16
1749 01:17:08.210417 best dqsien dly found for B0: ( 0, 9, 24)
1750 01:17:08.213640 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1751 01:17:08.220085 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1752 01:17:08.220559 Total UI for P1: 0, mck2ui 16
1753 01:17:08.226753 best dqsien dly found for B1: ( 0, 10, 0)
1754 01:17:08.230155 best DQS0 dly(MCK, UI, PI) = (0, 9, 24)
1755 01:17:08.233731 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1756 01:17:08.234166
1757 01:17:08.237156 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 24)
1758 01:17:08.240085 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1759 01:17:08.243890 [Gating] SW calibration Done
1760 01:17:08.244303 ==
1761 01:17:08.247192 Dram Type= 6, Freq= 0, CH_1, rank 1
1762 01:17:08.250538 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1763 01:17:08.251080 ==
1764 01:17:08.253704 RX Vref Scan: 0
1765 01:17:08.254275
1766 01:17:08.254658 RX Vref 0 -> 0, step: 1
1767 01:17:08.255007
1768 01:17:08.256842 RX Delay -130 -> 252, step: 16
1769 01:17:08.263476 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1770 01:17:08.267208 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1771 01:17:08.270257 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1772 01:17:08.273611 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1773 01:17:08.276880 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1774 01:17:08.279914 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1775 01:17:08.286741 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1776 01:17:08.290123 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1777 01:17:08.293947 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1778 01:17:08.296543 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1779 01:17:08.299986 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1780 01:17:08.307322 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1781 01:17:08.310427 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1782 01:17:08.313654 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1783 01:17:08.316666 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1784 01:17:08.323209 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1785 01:17:08.323710 ==
1786 01:17:08.326671 Dram Type= 6, Freq= 0, CH_1, rank 1
1787 01:17:08.330146 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1788 01:17:08.330703 ==
1789 01:17:08.331074 DQS Delay:
1790 01:17:08.333757 DQS0 = 0, DQS1 = 0
1791 01:17:08.334380 DQM Delay:
1792 01:17:08.336943 DQM0 = 85, DQM1 = 74
1793 01:17:08.337513 DQ Delay:
1794 01:17:08.340143 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1795 01:17:08.343532 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1796 01:17:08.346810 DQ8 =53, DQ9 =69, DQ10 =69, DQ11 =69
1797 01:17:08.350082 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1798 01:17:08.350783
1799 01:17:08.351160
1800 01:17:08.351508 ==
1801 01:17:08.353285 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 01:17:08.356823 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1803 01:17:08.357380 ==
1804 01:17:08.357751
1805 01:17:08.360044
1806 01:17:08.360589 TX Vref Scan disable
1807 01:17:08.363720 == TX Byte 0 ==
1808 01:17:08.366688 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1809 01:17:08.370093 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1810 01:17:08.373297 == TX Byte 1 ==
1811 01:17:08.376519 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1812 01:17:08.380140 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1813 01:17:08.380612 ==
1814 01:17:08.383358 Dram Type= 6, Freq= 0, CH_1, rank 1
1815 01:17:08.389891 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1816 01:17:08.390480 ==
1817 01:17:08.401457 TX Vref=22, minBit 2, minWin=27, winSum=447
1818 01:17:08.404909 TX Vref=24, minBit 0, minWin=28, winSum=451
1819 01:17:08.408174 TX Vref=26, minBit 0, minWin=28, winSum=460
1820 01:17:08.411448 TX Vref=28, minBit 9, minWin=27, winSum=457
1821 01:17:08.414889 TX Vref=30, minBit 0, minWin=28, winSum=458
1822 01:17:08.418077 TX Vref=32, minBit 9, minWin=27, winSum=453
1823 01:17:08.424826 [TxChooseVref] Worse bit 0, Min win 28, Win sum 460, Final Vref 26
1824 01:17:08.425295
1825 01:17:08.428254 Final TX Range 1 Vref 26
1826 01:17:08.428723
1827 01:17:08.429093 ==
1828 01:17:08.431346 Dram Type= 6, Freq= 0, CH_1, rank 1
1829 01:17:08.434816 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1830 01:17:08.435287 ==
1831 01:17:08.435660
1832 01:17:08.437859
1833 01:17:08.438375 TX Vref Scan disable
1834 01:17:08.441472 == TX Byte 0 ==
1835 01:17:08.444836 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1836 01:17:08.448167 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1837 01:17:08.451363 == TX Byte 1 ==
1838 01:17:08.454830 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1839 01:17:08.457888 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1840 01:17:08.461638
1841 01:17:08.462198 [DATLAT]
1842 01:17:08.462578 Freq=800, CH1 RK1
1843 01:17:08.462923
1844 01:17:08.464885 DATLAT Default: 0x9
1845 01:17:08.465439 0, 0xFFFF, sum = 0
1846 01:17:08.468312 1, 0xFFFF, sum = 0
1847 01:17:08.468779 2, 0xFFFF, sum = 0
1848 01:17:08.471343 3, 0xFFFF, sum = 0
1849 01:17:08.471809 4, 0xFFFF, sum = 0
1850 01:17:08.474525 5, 0xFFFF, sum = 0
1851 01:17:08.474988 6, 0xFFFF, sum = 0
1852 01:17:08.478259 7, 0xFFFF, sum = 0
1853 01:17:08.478846 8, 0x0, sum = 1
1854 01:17:08.481734 9, 0x0, sum = 2
1855 01:17:08.482270 10, 0x0, sum = 3
1856 01:17:08.484623 11, 0x0, sum = 4
1857 01:17:08.485085 best_step = 9
1858 01:17:08.485447
1859 01:17:08.485784 ==
1860 01:17:08.488451 Dram Type= 6, Freq= 0, CH_1, rank 1
1861 01:17:08.495042 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1862 01:17:08.495630 ==
1863 01:17:08.496004 RX Vref Scan: 0
1864 01:17:08.496343
1865 01:17:08.498501 RX Vref 0 -> 0, step: 1
1866 01:17:08.499061
1867 01:17:08.501213 RX Delay -111 -> 252, step: 8
1868 01:17:08.504563 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1869 01:17:08.508083 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1870 01:17:08.515083 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1871 01:17:08.518088 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1872 01:17:08.521651 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1873 01:17:08.524860 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
1874 01:17:08.527966 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1875 01:17:08.531313 iDelay=209, Bit 7, Center 80 (-39 ~ 200) 240
1876 01:17:08.538073 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1877 01:17:08.541522 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
1878 01:17:08.544726 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1879 01:17:08.548300 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1880 01:17:08.551368 iDelay=209, Bit 12, Center 88 (-31 ~ 208) 240
1881 01:17:08.558049 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1882 01:17:08.561109 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1883 01:17:08.564925 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1884 01:17:08.565489 ==
1885 01:17:08.567928 Dram Type= 6, Freq= 0, CH_1, rank 1
1886 01:17:08.571845 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1887 01:17:08.574900 ==
1888 01:17:08.575461 DQS Delay:
1889 01:17:08.575833 DQS0 = 0, DQS1 = 0
1890 01:17:08.577996 DQM Delay:
1891 01:17:08.578688 DQM0 = 84, DQM1 = 75
1892 01:17:08.581458 DQ Delay:
1893 01:17:08.582016 DQ0 =88, DQ1 =80, DQ2 =76, DQ3 =80
1894 01:17:08.584753 DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =80
1895 01:17:08.587897 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1896 01:17:08.591210 DQ12 =88, DQ13 =84, DQ14 =80, DQ15 =84
1897 01:17:08.591772
1898 01:17:08.594729
1899 01:17:08.601425 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1900 01:17:08.604519 CH1 RK1: MR19=606, MR18=3A3A
1901 01:17:08.611510 CH1_RK1: MR19=0x606, MR18=0x3A3A, DQSOSC=395, MR23=63, INC=94, DEC=63
1902 01:17:08.612071 [RxdqsGatingPostProcess] freq 800
1903 01:17:08.617760 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1904 01:17:08.621422 Pre-setting of DQS Precalculation
1905 01:17:08.624833 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1906 01:17:08.634715 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1907 01:17:08.641298 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1908 01:17:08.641862
1909 01:17:08.642349
1910 01:17:08.644679 [Calibration Summary] 1600 Mbps
1911 01:17:08.645234 CH 0, Rank 0
1912 01:17:08.647863 SW Impedance : PASS
1913 01:17:08.648427 DUTY Scan : NO K
1914 01:17:08.650889 ZQ Calibration : PASS
1915 01:17:08.654250 Jitter Meter : NO K
1916 01:17:08.654715 CBT Training : PASS
1917 01:17:08.658193 Write leveling : PASS
1918 01:17:08.660890 RX DQS gating : PASS
1919 01:17:08.661353 RX DQ/DQS(RDDQC) : PASS
1920 01:17:08.664594 TX DQ/DQS : PASS
1921 01:17:08.667784 RX DATLAT : PASS
1922 01:17:08.668338 RX DQ/DQS(Engine): PASS
1923 01:17:08.670936 TX OE : NO K
1924 01:17:08.671466 All Pass.
1925 01:17:08.672000
1926 01:17:08.674562 CH 0, Rank 1
1927 01:17:08.675114 SW Impedance : PASS
1928 01:17:08.677802 DUTY Scan : NO K
1929 01:17:08.680962 ZQ Calibration : PASS
1930 01:17:08.681424 Jitter Meter : NO K
1931 01:17:08.684506 CBT Training : PASS
1932 01:17:08.687355 Write leveling : PASS
1933 01:17:08.687812 RX DQS gating : PASS
1934 01:17:08.690785 RX DQ/DQS(RDDQC) : PASS
1935 01:17:08.694540 TX DQ/DQS : PASS
1936 01:17:08.695097 RX DATLAT : PASS
1937 01:17:08.697617 RX DQ/DQS(Engine): PASS
1938 01:17:08.698096 TX OE : NO K
1939 01:17:08.700472 All Pass.
1940 01:17:08.700931
1941 01:17:08.701294 CH 1, Rank 0
1942 01:17:08.703953 SW Impedance : PASS
1943 01:17:08.704556 DUTY Scan : NO K
1944 01:17:08.707414 ZQ Calibration : PASS
1945 01:17:08.710621 Jitter Meter : NO K
1946 01:17:08.711076 CBT Training : PASS
1947 01:17:08.714451 Write leveling : PASS
1948 01:17:08.717412 RX DQS gating : PASS
1949 01:17:08.717870 RX DQ/DQS(RDDQC) : PASS
1950 01:17:08.720571 TX DQ/DQS : PASS
1951 01:17:08.723886 RX DATLAT : PASS
1952 01:17:08.724351 RX DQ/DQS(Engine): PASS
1953 01:17:08.726923 TX OE : NO K
1954 01:17:08.727395 All Pass.
1955 01:17:08.727766
1956 01:17:08.730477 CH 1, Rank 1
1957 01:17:08.730940 SW Impedance : PASS
1958 01:17:08.733604 DUTY Scan : NO K
1959 01:17:08.737477 ZQ Calibration : PASS
1960 01:17:08.738072 Jitter Meter : NO K
1961 01:17:08.740647 CBT Training : PASS
1962 01:17:08.743978 Write leveling : PASS
1963 01:17:08.744538 RX DQS gating : PASS
1964 01:17:08.747097 RX DQ/DQS(RDDQC) : PASS
1965 01:17:08.750583 TX DQ/DQS : PASS
1966 01:17:08.751142 RX DATLAT : PASS
1967 01:17:08.753904 RX DQ/DQS(Engine): PASS
1968 01:17:08.754514 TX OE : NO K
1969 01:17:08.757019 All Pass.
1970 01:17:08.757572
1971 01:17:08.757942 DramC Write-DBI off
1972 01:17:08.760392 PER_BANK_REFRESH: Hybrid Mode
1973 01:17:08.763732 TX_TRACKING: ON
1974 01:17:08.766759 [GetDramInforAfterCalByMRR] Vendor 6.
1975 01:17:08.770279 [GetDramInforAfterCalByMRR] Revision 606.
1976 01:17:08.773654 [GetDramInforAfterCalByMRR] Revision 2 0.
1977 01:17:08.774273 MR0 0x3939
1978 01:17:08.777037 MR8 0x1111
1979 01:17:08.780638 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1980 01:17:08.781141
1981 01:17:08.781515 MR0 0x3939
1982 01:17:08.781859 MR8 0x1111
1983 01:17:08.784028 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1984 01:17:08.784586
1985 01:17:08.793861 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1986 01:17:08.797008 [FAST_K] Save calibration result to emmc
1987 01:17:08.800176 [FAST_K] Save calibration result to emmc
1988 01:17:08.803638 dram_init: config_dvfs: 1
1989 01:17:08.806583 dramc_set_vcore_voltage set vcore to 662500
1990 01:17:08.810408 Read voltage for 1200, 2
1991 01:17:08.810968 Vio18 = 0
1992 01:17:08.813528 Vcore = 662500
1993 01:17:08.814138 Vdram = 0
1994 01:17:08.814557 Vddq = 0
1995 01:17:08.814906 Vmddr = 0
1996 01:17:08.820014 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1997 01:17:08.823411 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1998 01:17:08.826780 MEM_TYPE=3, freq_sel=15
1999 01:17:08.829977 sv_algorithm_assistance_LP4_1600
2000 01:17:08.833677 ============ PULL DRAM RESETB DOWN ============
2001 01:17:08.840040 ========== PULL DRAM RESETB DOWN end =========
2002 01:17:08.843563 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2003 01:17:08.846803 ===================================
2004 01:17:08.850555 LPDDR4 DRAM CONFIGURATION
2005 01:17:08.853542 ===================================
2006 01:17:08.854008 EX_ROW_EN[0] = 0x0
2007 01:17:08.856884 EX_ROW_EN[1] = 0x0
2008 01:17:08.857441 LP4Y_EN = 0x0
2009 01:17:08.860430 WORK_FSP = 0x0
2010 01:17:08.860992 WL = 0x4
2011 01:17:08.863621 RL = 0x4
2012 01:17:08.864176 BL = 0x2
2013 01:17:08.866868 RPST = 0x0
2014 01:17:08.867487 RD_PRE = 0x0
2015 01:17:08.870098 WR_PRE = 0x1
2016 01:17:08.870648 WR_PST = 0x0
2017 01:17:08.873636 DBI_WR = 0x0
2018 01:17:08.874230 DBI_RD = 0x0
2019 01:17:08.876494 OTF = 0x1
2020 01:17:08.879839 ===================================
2021 01:17:08.883479 ===================================
2022 01:17:08.884039 ANA top config
2023 01:17:08.886844 ===================================
2024 01:17:08.890139 DLL_ASYNC_EN = 0
2025 01:17:08.893502 ALL_SLAVE_EN = 0
2026 01:17:08.896666 NEW_RANK_MODE = 1
2027 01:17:08.897182 DLL_IDLE_MODE = 1
2028 01:17:08.899917 LP45_APHY_COMB_EN = 1
2029 01:17:08.903390 TX_ODT_DIS = 1
2030 01:17:08.906619 NEW_8X_MODE = 1
2031 01:17:08.910162 ===================================
2032 01:17:08.913848 ===================================
2033 01:17:08.917008 data_rate = 2400
2034 01:17:08.917483 CKR = 1
2035 01:17:08.920226 DQ_P2S_RATIO = 8
2036 01:17:08.923498 ===================================
2037 01:17:08.926919 CA_P2S_RATIO = 8
2038 01:17:08.930007 DQ_CA_OPEN = 0
2039 01:17:08.933232 DQ_SEMI_OPEN = 0
2040 01:17:08.936716 CA_SEMI_OPEN = 0
2041 01:17:08.937175 CA_FULL_RATE = 0
2042 01:17:08.939918 DQ_CKDIV4_EN = 0
2043 01:17:08.943534 CA_CKDIV4_EN = 0
2044 01:17:08.946599 CA_PREDIV_EN = 0
2045 01:17:08.949742 PH8_DLY = 17
2046 01:17:08.953581 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2047 01:17:08.954173 DQ_AAMCK_DIV = 4
2048 01:17:08.956516 CA_AAMCK_DIV = 4
2049 01:17:08.959765 CA_ADMCK_DIV = 4
2050 01:17:08.962951 DQ_TRACK_CA_EN = 0
2051 01:17:08.966813 CA_PICK = 1200
2052 01:17:08.969676 CA_MCKIO = 1200
2053 01:17:08.973002 MCKIO_SEMI = 0
2054 01:17:08.973425 PLL_FREQ = 2366
2055 01:17:08.976578 DQ_UI_PI_RATIO = 32
2056 01:17:08.979746 CA_UI_PI_RATIO = 0
2057 01:17:08.983460 ===================================
2058 01:17:08.986535 ===================================
2059 01:17:08.989721 memory_type:LPDDR4
2060 01:17:08.990175 GP_NUM : 10
2061 01:17:08.993226 SRAM_EN : 1
2062 01:17:08.996825 MD32_EN : 0
2063 01:17:08.999901 ===================================
2064 01:17:09.000324 [ANA_INIT] >>>>>>>>>>>>>>
2065 01:17:09.003346 <<<<<< [CONFIGURE PHASE]: ANA_TX
2066 01:17:09.006863 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2067 01:17:09.009853 ===================================
2068 01:17:09.013591 data_rate = 2400,PCW = 0X5b00
2069 01:17:09.016805 ===================================
2070 01:17:09.019894 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2071 01:17:09.026721 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2072 01:17:09.030068 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2073 01:17:09.036749 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2074 01:17:09.040215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2075 01:17:09.043582 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2076 01:17:09.044147 [ANA_INIT] flow start
2077 01:17:09.046645 [ANA_INIT] PLL >>>>>>>>
2078 01:17:09.049876 [ANA_INIT] PLL <<<<<<<<
2079 01:17:09.053565 [ANA_INIT] MIDPI >>>>>>>>
2080 01:17:09.054135 [ANA_INIT] MIDPI <<<<<<<<
2081 01:17:09.056700 [ANA_INIT] DLL >>>>>>>>
2082 01:17:09.059766 [ANA_INIT] DLL <<<<<<<<
2083 01:17:09.060192 [ANA_INIT] flow end
2084 01:17:09.063320 ============ LP4 DIFF to SE enter ============
2085 01:17:09.069767 ============ LP4 DIFF to SE exit ============
2086 01:17:09.070396 [ANA_INIT] <<<<<<<<<<<<<
2087 01:17:09.073210 [Flow] Enable top DCM control >>>>>
2088 01:17:09.076428 [Flow] Enable top DCM control <<<<<
2089 01:17:09.079804 Enable DLL master slave shuffle
2090 01:17:09.086743 ==============================================================
2091 01:17:09.087262 Gating Mode config
2092 01:17:09.093402 ==============================================================
2093 01:17:09.096897 Config description:
2094 01:17:09.106634 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2095 01:17:09.113363 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2096 01:17:09.116374 SELPH_MODE 0: By rank 1: By Phase
2097 01:17:09.123109 ==============================================================
2098 01:17:09.126371 GAT_TRACK_EN = 1
2099 01:17:09.129603 RX_GATING_MODE = 2
2100 01:17:09.130113 RX_GATING_TRACK_MODE = 2
2101 01:17:09.133180 SELPH_MODE = 1
2102 01:17:09.136744 PICG_EARLY_EN = 1
2103 01:17:09.139845 VALID_LAT_VALUE = 1
2104 01:17:09.146369 ==============================================================
2105 01:17:09.149789 Enter into Gating configuration >>>>
2106 01:17:09.153151 Exit from Gating configuration <<<<
2107 01:17:09.156737 Enter into DVFS_PRE_config >>>>>
2108 01:17:09.166415 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2109 01:17:09.169906 Exit from DVFS_PRE_config <<<<<
2110 01:17:09.173376 Enter into PICG configuration >>>>
2111 01:17:09.176789 Exit from PICG configuration <<<<
2112 01:17:09.179652 [RX_INPUT] configuration >>>>>
2113 01:17:09.182915 [RX_INPUT] configuration <<<<<
2114 01:17:09.186246 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2115 01:17:09.193344 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2116 01:17:09.199626 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2117 01:17:09.202915 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2118 01:17:09.209498 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2119 01:17:09.216860 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2120 01:17:09.219703 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2121 01:17:09.223099 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2122 01:17:09.229973 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2123 01:17:09.232863 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2124 01:17:09.236532 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2125 01:17:09.242868 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2126 01:17:09.246382 ===================================
2127 01:17:09.246955 LPDDR4 DRAM CONFIGURATION
2128 01:17:09.250007 ===================================
2129 01:17:09.252773 EX_ROW_EN[0] = 0x0
2130 01:17:09.253348 EX_ROW_EN[1] = 0x0
2131 01:17:09.256239 LP4Y_EN = 0x0
2132 01:17:09.259369 WORK_FSP = 0x0
2133 01:17:09.259931 WL = 0x4
2134 01:17:09.262644 RL = 0x4
2135 01:17:09.263100 BL = 0x2
2136 01:17:09.266194 RPST = 0x0
2137 01:17:09.266755 RD_PRE = 0x0
2138 01:17:09.269478 WR_PRE = 0x1
2139 01:17:09.270154 WR_PST = 0x0
2140 01:17:09.272567 DBI_WR = 0x0
2141 01:17:09.273073 DBI_RD = 0x0
2142 01:17:09.276255 OTF = 0x1
2143 01:17:09.279404 ===================================
2144 01:17:09.282676 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2145 01:17:09.286230 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2146 01:17:09.289639 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2147 01:17:09.293085 ===================================
2148 01:17:09.296440 LPDDR4 DRAM CONFIGURATION
2149 01:17:09.299397 ===================================
2150 01:17:09.302928 EX_ROW_EN[0] = 0x10
2151 01:17:09.303386 EX_ROW_EN[1] = 0x0
2152 01:17:09.306285 LP4Y_EN = 0x0
2153 01:17:09.306982 WORK_FSP = 0x0
2154 01:17:09.309443 WL = 0x4
2155 01:17:09.309897 RL = 0x4
2156 01:17:09.313099 BL = 0x2
2157 01:17:09.313653 RPST = 0x0
2158 01:17:09.316473 RD_PRE = 0x0
2159 01:17:09.319288 WR_PRE = 0x1
2160 01:17:09.319748 WR_PST = 0x0
2161 01:17:09.322681 DBI_WR = 0x0
2162 01:17:09.323140 DBI_RD = 0x0
2163 01:17:09.326159 OTF = 0x1
2164 01:17:09.329526 ===================================
2165 01:17:09.332883 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2166 01:17:09.336129 ==
2167 01:17:09.336706 Dram Type= 6, Freq= 0, CH_0, rank 0
2168 01:17:09.342621 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2169 01:17:09.343086 ==
2170 01:17:09.345937 [Duty_Offset_Calibration]
2171 01:17:09.346440 B0:0 B1:2 CA:1
2172 01:17:09.346808
2173 01:17:09.349030 [DutyScan_Calibration_Flow] k_type=0
2174 01:17:09.358972
2175 01:17:09.359533 ==CLK 0==
2176 01:17:09.362476 Final CLK duty delay cell = 0
2177 01:17:09.365878 [0] MAX Duty = 5093%(X100), DQS PI = 12
2178 01:17:09.369032 [0] MIN Duty = 4938%(X100), DQS PI = 54
2179 01:17:09.369592 [0] AVG Duty = 5015%(X100)
2180 01:17:09.371949
2181 01:17:09.375132 CH0 CLK Duty spec in!! Max-Min= 155%
2182 01:17:09.378452 [DutyScan_Calibration_Flow] ====Done====
2183 01:17:09.379059
2184 01:17:09.381658 [DutyScan_Calibration_Flow] k_type=1
2185 01:17:09.398261
2186 01:17:09.398873 ==DQS 0 ==
2187 01:17:09.401157 Final DQS duty delay cell = 0
2188 01:17:09.404651 [0] MAX Duty = 5125%(X100), DQS PI = 30
2189 01:17:09.407875 [0] MIN Duty = 5031%(X100), DQS PI = 6
2190 01:17:09.411191 [0] AVG Duty = 5078%(X100)
2191 01:17:09.411655
2192 01:17:09.412023 ==DQS 1 ==
2193 01:17:09.414385 Final DQS duty delay cell = 0
2194 01:17:09.418209 [0] MAX Duty = 5062%(X100), DQS PI = 58
2195 01:17:09.421611 [0] MIN Duty = 4906%(X100), DQS PI = 16
2196 01:17:09.424609 [0] AVG Duty = 4984%(X100)
2197 01:17:09.425189
2198 01:17:09.427772 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2199 01:17:09.428239
2200 01:17:09.431405 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2201 01:17:09.434395 [DutyScan_Calibration_Flow] ====Done====
2202 01:17:09.434854
2203 01:17:09.437949 [DutyScan_Calibration_Flow] k_type=3
2204 01:17:09.455759
2205 01:17:09.456318 ==DQM 0 ==
2206 01:17:09.458544 Final DQM duty delay cell = 0
2207 01:17:09.462544 [0] MAX Duty = 5156%(X100), DQS PI = 20
2208 01:17:09.465943 [0] MIN Duty = 4969%(X100), DQS PI = 40
2209 01:17:09.468631 [0] AVG Duty = 5062%(X100)
2210 01:17:09.469205
2211 01:17:09.469578 ==DQM 1 ==
2212 01:17:09.472145 Final DQM duty delay cell = 4
2213 01:17:09.475579 [4] MAX Duty = 5187%(X100), DQS PI = 54
2214 01:17:09.478210 [4] MIN Duty = 5000%(X100), DQS PI = 18
2215 01:17:09.482177 [4] AVG Duty = 5093%(X100)
2216 01:17:09.482733
2217 01:17:09.485095 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2218 01:17:09.485660
2219 01:17:09.488513 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2220 01:17:09.491905 [DutyScan_Calibration_Flow] ====Done====
2221 01:17:09.492544
2222 01:17:09.495020 [DutyScan_Calibration_Flow] k_type=2
2223 01:17:09.510412
2224 01:17:09.510970 ==DQ 0 ==
2225 01:17:09.513647 Final DQ duty delay cell = -4
2226 01:17:09.516727 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2227 01:17:09.520176 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2228 01:17:09.523328 [-4] AVG Duty = 4937%(X100)
2229 01:17:09.523789
2230 01:17:09.524157 ==DQ 1 ==
2231 01:17:09.526580 Final DQ duty delay cell = -4
2232 01:17:09.530107 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2233 01:17:09.533311 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2234 01:17:09.536830 [-4] AVG Duty = 4984%(X100)
2235 01:17:09.537378
2236 01:17:09.540239 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2237 01:17:09.540793
2238 01:17:09.543582 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2239 01:17:09.546706 [DutyScan_Calibration_Flow] ====Done====
2240 01:17:09.547257 ==
2241 01:17:09.550453 Dram Type= 6, Freq= 0, CH_1, rank 0
2242 01:17:09.553647 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2243 01:17:09.554293 ==
2244 01:17:09.557233 [Duty_Offset_Calibration]
2245 01:17:09.557785 B0:0 B1:4 CA:-5
2246 01:17:09.558227
2247 01:17:09.559659 [DutyScan_Calibration_Flow] k_type=0
2248 01:17:09.570561
2249 01:17:09.571159 ==CLK 0==
2250 01:17:09.574085 Final CLK duty delay cell = 0
2251 01:17:09.577440 [0] MAX Duty = 5094%(X100), DQS PI = 24
2252 01:17:09.580861 [0] MIN Duty = 4876%(X100), DQS PI = 52
2253 01:17:09.581415 [0] AVG Duty = 4985%(X100)
2254 01:17:09.584014
2255 01:17:09.584476 CH1 CLK Duty spec in!! Max-Min= 218%
2256 01:17:09.590705 [DutyScan_Calibration_Flow] ====Done====
2257 01:17:09.591264
2258 01:17:09.593753 [DutyScan_Calibration_Flow] k_type=1
2259 01:17:09.609194
2260 01:17:09.609832 ==DQS 0 ==
2261 01:17:09.612701 Final DQS duty delay cell = 0
2262 01:17:09.615846 [0] MAX Duty = 5125%(X100), DQS PI = 16
2263 01:17:09.619105 [0] MIN Duty = 4875%(X100), DQS PI = 40
2264 01:17:09.622205 [0] AVG Duty = 5000%(X100)
2265 01:17:09.622675
2266 01:17:09.623045 ==DQS 1 ==
2267 01:17:09.625769 Final DQS duty delay cell = -4
2268 01:17:09.629448 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2269 01:17:09.632551 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2270 01:17:09.635767 [-4] AVG Duty = 4953%(X100)
2271 01:17:09.636391
2272 01:17:09.639393 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2273 01:17:09.639857
2274 01:17:09.642395 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2275 01:17:09.645815 [DutyScan_Calibration_Flow] ====Done====
2276 01:17:09.646425
2277 01:17:09.648825 [DutyScan_Calibration_Flow] k_type=3
2278 01:17:09.664807
2279 01:17:09.665366 ==DQM 0 ==
2280 01:17:09.667389 Final DQM duty delay cell = -4
2281 01:17:09.670703 [-4] MAX Duty = 5093%(X100), DQS PI = 32
2282 01:17:09.674724 [-4] MIN Duty = 4844%(X100), DQS PI = 42
2283 01:17:09.677781 [-4] AVG Duty = 4968%(X100)
2284 01:17:09.678384
2285 01:17:09.678754 ==DQM 1 ==
2286 01:17:09.680888 Final DQM duty delay cell = -4
2287 01:17:09.684373 [-4] MAX Duty = 5062%(X100), DQS PI = 2
2288 01:17:09.687532 [-4] MIN Duty = 4875%(X100), DQS PI = 58
2289 01:17:09.691019 [-4] AVG Duty = 4968%(X100)
2290 01:17:09.691588
2291 01:17:09.694223 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2292 01:17:09.694698
2293 01:17:09.697224 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2294 01:17:09.700458 [DutyScan_Calibration_Flow] ====Done====
2295 01:17:09.700917
2296 01:17:09.703696 [DutyScan_Calibration_Flow] k_type=2
2297 01:17:09.721404
2298 01:17:09.721831 ==DQ 0 ==
2299 01:17:09.725325 Final DQ duty delay cell = 0
2300 01:17:09.728160 [0] MAX Duty = 5062%(X100), DQS PI = 0
2301 01:17:09.731280 [0] MIN Duty = 4969%(X100), DQS PI = 42
2302 01:17:09.731757 [0] AVG Duty = 5015%(X100)
2303 01:17:09.732116
2304 01:17:09.734738 ==DQ 1 ==
2305 01:17:09.737998 Final DQ duty delay cell = 0
2306 01:17:09.741419 [0] MAX Duty = 5000%(X100), DQS PI = 8
2307 01:17:09.744670 [0] MIN Duty = 4875%(X100), DQS PI = 0
2308 01:17:09.745091 [0] AVG Duty = 4937%(X100)
2309 01:17:09.745428
2310 01:17:09.747823 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2311 01:17:09.748245
2312 01:17:09.751115 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2313 01:17:09.758014 [DutyScan_Calibration_Flow] ====Done====
2314 01:17:09.761293 nWR fixed to 30
2315 01:17:09.761713 [ModeRegInit_LP4] CH0 RK0
2316 01:17:09.764412 [ModeRegInit_LP4] CH0 RK1
2317 01:17:09.767775 [ModeRegInit_LP4] CH1 RK0
2318 01:17:09.768200 [ModeRegInit_LP4] CH1 RK1
2319 01:17:09.771071 match AC timing 6
2320 01:17:09.774519 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2321 01:17:09.777813 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2322 01:17:09.784759 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2323 01:17:09.788032 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2324 01:17:09.794904 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2325 01:17:09.795426 ==
2326 01:17:09.797959 Dram Type= 6, Freq= 0, CH_0, rank 0
2327 01:17:09.801507 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2328 01:17:09.802062 ==
2329 01:17:09.807825 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2330 01:17:09.810944 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2331 01:17:09.821146 [CA 0] Center 39 (9~70) winsize 62
2332 01:17:09.824571 [CA 1] Center 39 (9~70) winsize 62
2333 01:17:09.827237 [CA 2] Center 36 (5~67) winsize 63
2334 01:17:09.830722 [CA 3] Center 35 (4~66) winsize 63
2335 01:17:09.834659 [CA 4] Center 34 (3~65) winsize 63
2336 01:17:09.837464 [CA 5] Center 33 (3~64) winsize 62
2337 01:17:09.837888
2338 01:17:09.840854 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2339 01:17:09.841361
2340 01:17:09.844158 [CATrainingPosCal] consider 1 rank data
2341 01:17:09.847473 u2DelayCellTimex100 = 270/100 ps
2342 01:17:09.850942 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2343 01:17:09.854453 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2344 01:17:09.860569 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2345 01:17:09.863936 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2346 01:17:09.867204 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2347 01:17:09.870570 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2348 01:17:09.870985
2349 01:17:09.874122 CA PerBit enable=1, Macro0, CA PI delay=33
2350 01:17:09.874537
2351 01:17:09.877407 [CBTSetCACLKResult] CA Dly = 33
2352 01:17:09.877826 CS Dly: 7 (0~38)
2353 01:17:09.880345 ==
2354 01:17:09.883995 Dram Type= 6, Freq= 0, CH_0, rank 1
2355 01:17:09.886808 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2356 01:17:09.887105 ==
2357 01:17:09.890385 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2358 01:17:09.896929 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2359 01:17:09.905960 [CA 0] Center 39 (8~70) winsize 63
2360 01:17:09.909063 [CA 1] Center 39 (8~70) winsize 63
2361 01:17:09.912530 [CA 2] Center 36 (5~67) winsize 63
2362 01:17:09.915665 [CA 3] Center 35 (4~66) winsize 63
2363 01:17:09.918904 [CA 4] Center 33 (3~64) winsize 62
2364 01:17:09.922190 [CA 5] Center 34 (3~65) winsize 63
2365 01:17:09.922305
2366 01:17:09.925541 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2367 01:17:09.925653
2368 01:17:09.929089 [CATrainingPosCal] consider 2 rank data
2369 01:17:09.932431 u2DelayCellTimex100 = 270/100 ps
2370 01:17:09.935549 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2371 01:17:09.939065 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2372 01:17:09.945611 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2373 01:17:09.949102 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2374 01:17:09.952581 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2375 01:17:09.955825 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2376 01:17:09.955951
2377 01:17:09.959077 CA PerBit enable=1, Macro0, CA PI delay=33
2378 01:17:09.959201
2379 01:17:09.962535 [CBTSetCACLKResult] CA Dly = 33
2380 01:17:09.962660 CS Dly: 7 (0~39)
2381 01:17:09.962759
2382 01:17:09.965709 ----->DramcWriteLeveling(PI) begin...
2383 01:17:09.968999 ==
2384 01:17:09.972279 Dram Type= 6, Freq= 0, CH_0, rank 0
2385 01:17:09.975714 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2386 01:17:09.975872 ==
2387 01:17:09.979349 Write leveling (Byte 0): 26 => 26
2388 01:17:09.982823 Write leveling (Byte 1): 26 => 26
2389 01:17:09.985642 DramcWriteLeveling(PI) end<-----
2390 01:17:09.985798
2391 01:17:09.985920 ==
2392 01:17:09.988830 Dram Type= 6, Freq= 0, CH_0, rank 0
2393 01:17:09.992243 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2394 01:17:09.992400 ==
2395 01:17:09.995598 [Gating] SW mode calibration
2396 01:17:10.002559 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2397 01:17:10.008996 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2398 01:17:10.012438 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2399 01:17:10.015638 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2400 01:17:10.018918 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2401 01:17:10.025930 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2402 01:17:10.028988 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2403 01:17:10.032313 0 11 20 | B1->B0 | 3232 2c2c | 1 1 | (0 1) (1 0)
2404 01:17:10.038796 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2405 01:17:10.042152 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2406 01:17:10.045434 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2407 01:17:10.052423 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2408 01:17:10.055744 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2409 01:17:10.058868 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2410 01:17:10.065592 0 12 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2411 01:17:10.068931 0 12 20 | B1->B0 | 3030 3b3b | 1 0 | (0 0) (0 0)
2412 01:17:10.072089 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2413 01:17:10.078548 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2414 01:17:10.082378 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2415 01:17:10.085461 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2416 01:17:10.092143 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2417 01:17:10.095296 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2418 01:17:10.098928 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2419 01:17:10.105637 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2420 01:17:10.108734 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2421 01:17:10.112070 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2422 01:17:10.118740 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2423 01:17:10.121969 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2424 01:17:10.125781 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2425 01:17:10.132538 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2426 01:17:10.135808 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2427 01:17:10.138787 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2428 01:17:10.142241 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2429 01:17:10.149074 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2430 01:17:10.152321 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2431 01:17:10.155560 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2432 01:17:10.162454 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2433 01:17:10.165957 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2434 01:17:10.168832 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2435 01:17:10.175716 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2436 01:17:10.179288 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2437 01:17:10.182197 Total UI for P1: 0, mck2ui 16
2438 01:17:10.185950 best dqsien dly found for B0: ( 0, 15, 18)
2439 01:17:10.189212 Total UI for P1: 0, mck2ui 16
2440 01:17:10.192241 best dqsien dly found for B1: ( 0, 15, 18)
2441 01:17:10.195504 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2442 01:17:10.199225 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2443 01:17:10.199752
2444 01:17:10.202267 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2445 01:17:10.205791 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2446 01:17:10.208778 [Gating] SW calibration Done
2447 01:17:10.209195 ==
2448 01:17:10.212162 Dram Type= 6, Freq= 0, CH_0, rank 0
2449 01:17:10.218830 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2450 01:17:10.219415 ==
2451 01:17:10.219759 RX Vref Scan: 0
2452 01:17:10.220073
2453 01:17:10.222369 RX Vref 0 -> 0, step: 1
2454 01:17:10.222788
2455 01:17:10.225573 RX Delay -40 -> 252, step: 8
2456 01:17:10.228729 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2457 01:17:10.232052 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2458 01:17:10.235539 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2459 01:17:10.238994 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2460 01:17:10.245706 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2461 01:17:10.248778 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2462 01:17:10.252091 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2463 01:17:10.255425 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2464 01:17:10.259268 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2465 01:17:10.262505 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2466 01:17:10.269279 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2467 01:17:10.272567 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2468 01:17:10.275455 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2469 01:17:10.279446 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2470 01:17:10.285784 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2471 01:17:10.289350 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2472 01:17:10.289909 ==
2473 01:17:10.292565 Dram Type= 6, Freq= 0, CH_0, rank 0
2474 01:17:10.295555 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2475 01:17:10.296022 ==
2476 01:17:10.298879 DQS Delay:
2477 01:17:10.299455 DQS0 = 0, DQS1 = 0
2478 01:17:10.299832 DQM Delay:
2479 01:17:10.302351 DQM0 = 115, DQM1 = 106
2480 01:17:10.302817 DQ Delay:
2481 01:17:10.305658 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2482 01:17:10.309325 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2483 01:17:10.312345 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2484 01:17:10.318614 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2485 01:17:10.319164
2486 01:17:10.319628
2487 01:17:10.319977 ==
2488 01:17:10.322136 Dram Type= 6, Freq= 0, CH_0, rank 0
2489 01:17:10.325797 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2490 01:17:10.326433 ==
2491 01:17:10.326811
2492 01:17:10.327224
2493 01:17:10.328811 TX Vref Scan disable
2494 01:17:10.329292 == TX Byte 0 ==
2495 01:17:10.335492 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2496 01:17:10.338699 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2497 01:17:10.339226 == TX Byte 1 ==
2498 01:17:10.345471 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2499 01:17:10.348701 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2500 01:17:10.349120 ==
2501 01:17:10.352006 Dram Type= 6, Freq= 0, CH_0, rank 0
2502 01:17:10.355099 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2503 01:17:10.355522 ==
2504 01:17:10.367498 TX Vref=22, minBit 4, minWin=24, winSum=407
2505 01:17:10.371010 TX Vref=24, minBit 10, minWin=25, winSum=415
2506 01:17:10.374698 TX Vref=26, minBit 1, minWin=26, winSum=423
2507 01:17:10.377847 TX Vref=28, minBit 2, minWin=26, winSum=428
2508 01:17:10.381034 TX Vref=30, minBit 4, minWin=26, winSum=426
2509 01:17:10.387604 TX Vref=32, minBit 5, minWin=26, winSum=427
2510 01:17:10.390830 [TxChooseVref] Worse bit 2, Min win 26, Win sum 428, Final Vref 28
2511 01:17:10.391250
2512 01:17:10.394635 Final TX Range 1 Vref 28
2513 01:17:10.395163
2514 01:17:10.395587 ==
2515 01:17:10.397733 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 01:17:10.401073 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2517 01:17:10.401631 ==
2518 01:17:10.404228
2519 01:17:10.404686
2520 01:17:10.405066 TX Vref Scan disable
2521 01:17:10.407546 == TX Byte 0 ==
2522 01:17:10.410908 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2523 01:17:10.414101 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2524 01:17:10.417630 == TX Byte 1 ==
2525 01:17:10.420823 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2526 01:17:10.423935 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2527 01:17:10.427181
2528 01:17:10.427658 [DATLAT]
2529 01:17:10.428025 Freq=1200, CH0 RK0
2530 01:17:10.428376
2531 01:17:10.430677 DATLAT Default: 0xd
2532 01:17:10.431135 0, 0xFFFF, sum = 0
2533 01:17:10.433790 1, 0xFFFF, sum = 0
2534 01:17:10.434282 2, 0xFFFF, sum = 0
2535 01:17:10.437523 3, 0xFFFF, sum = 0
2536 01:17:10.440849 4, 0xFFFF, sum = 0
2537 01:17:10.441374 5, 0xFFFF, sum = 0
2538 01:17:10.444019 6, 0xFFFF, sum = 0
2539 01:17:10.444440 7, 0xFFFF, sum = 0
2540 01:17:10.447608 8, 0xFFFF, sum = 0
2541 01:17:10.448139 9, 0xFFFF, sum = 0
2542 01:17:10.450762 10, 0xFFFF, sum = 0
2543 01:17:10.451186 11, 0x0, sum = 1
2544 01:17:10.454004 12, 0x0, sum = 2
2545 01:17:10.454574 13, 0x0, sum = 3
2546 01:17:10.457594 14, 0x0, sum = 4
2547 01:17:10.458160 best_step = 12
2548 01:17:10.458504
2549 01:17:10.458817 ==
2550 01:17:10.460747 Dram Type= 6, Freq= 0, CH_0, rank 0
2551 01:17:10.464287 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2552 01:17:10.464809 ==
2553 01:17:10.467725 RX Vref Scan: 1
2554 01:17:10.468243
2555 01:17:10.470375 Set Vref Range= 32 -> 127
2556 01:17:10.470790
2557 01:17:10.471119 RX Vref 32 -> 127, step: 1
2558 01:17:10.471431
2559 01:17:10.474658 RX Delay -21 -> 252, step: 4
2560 01:17:10.475186
2561 01:17:10.477344 Set Vref, RX VrefLevel [Byte0]: 32
2562 01:17:10.480339 [Byte1]: 32
2563 01:17:10.484244
2564 01:17:10.484834 Set Vref, RX VrefLevel [Byte0]: 33
2565 01:17:10.487381 [Byte1]: 33
2566 01:17:10.492219
2567 01:17:10.492742 Set Vref, RX VrefLevel [Byte0]: 34
2568 01:17:10.495608 [Byte1]: 34
2569 01:17:10.500083
2570 01:17:10.500609 Set Vref, RX VrefLevel [Byte0]: 35
2571 01:17:10.503166 [Byte1]: 35
2572 01:17:10.507954
2573 01:17:10.508473 Set Vref, RX VrefLevel [Byte0]: 36
2574 01:17:10.511115 [Byte1]: 36
2575 01:17:10.515975
2576 01:17:10.516497 Set Vref, RX VrefLevel [Byte0]: 37
2577 01:17:10.518920 [Byte1]: 37
2578 01:17:10.523655
2579 01:17:10.524073 Set Vref, RX VrefLevel [Byte0]: 38
2580 01:17:10.527085 [Byte1]: 38
2581 01:17:10.531658
2582 01:17:10.532180 Set Vref, RX VrefLevel [Byte0]: 39
2583 01:17:10.534802 [Byte1]: 39
2584 01:17:10.539469
2585 01:17:10.540033 Set Vref, RX VrefLevel [Byte0]: 40
2586 01:17:10.543284 [Byte1]: 40
2587 01:17:10.547711
2588 01:17:10.548275 Set Vref, RX VrefLevel [Byte0]: 41
2589 01:17:10.550686 [Byte1]: 41
2590 01:17:10.555364
2591 01:17:10.555935 Set Vref, RX VrefLevel [Byte0]: 42
2592 01:17:10.558787 [Byte1]: 42
2593 01:17:10.563673
2594 01:17:10.564250 Set Vref, RX VrefLevel [Byte0]: 43
2595 01:17:10.566757 [Byte1]: 43
2596 01:17:10.571841
2597 01:17:10.572398 Set Vref, RX VrefLevel [Byte0]: 44
2598 01:17:10.574519 [Byte1]: 44
2599 01:17:10.579409
2600 01:17:10.579964 Set Vref, RX VrefLevel [Byte0]: 45
2601 01:17:10.582955 [Byte1]: 45
2602 01:17:10.587341
2603 01:17:10.587896 Set Vref, RX VrefLevel [Byte0]: 46
2604 01:17:10.590700 [Byte1]: 46
2605 01:17:10.595124
2606 01:17:10.595687 Set Vref, RX VrefLevel [Byte0]: 47
2607 01:17:10.598875 [Byte1]: 47
2608 01:17:10.603337
2609 01:17:10.603898 Set Vref, RX VrefLevel [Byte0]: 48
2610 01:17:10.606409 [Byte1]: 48
2611 01:17:10.611264
2612 01:17:10.611813 Set Vref, RX VrefLevel [Byte0]: 49
2613 01:17:10.614574 [Byte1]: 49
2614 01:17:10.618957
2615 01:17:10.619703 Set Vref, RX VrefLevel [Byte0]: 50
2616 01:17:10.622219 [Byte1]: 50
2617 01:17:10.626749
2618 01:17:10.627332 Set Vref, RX VrefLevel [Byte0]: 51
2619 01:17:10.630119 [Byte1]: 51
2620 01:17:10.634721
2621 01:17:10.635185 Set Vref, RX VrefLevel [Byte0]: 52
2622 01:17:10.637810 [Byte1]: 52
2623 01:17:10.642745
2624 01:17:10.643298 Set Vref, RX VrefLevel [Byte0]: 53
2625 01:17:10.646216 [Byte1]: 53
2626 01:17:10.650526
2627 01:17:10.650993 Set Vref, RX VrefLevel [Byte0]: 54
2628 01:17:10.653596 [Byte1]: 54
2629 01:17:10.658637
2630 01:17:10.659190 Set Vref, RX VrefLevel [Byte0]: 55
2631 01:17:10.662476 [Byte1]: 55
2632 01:17:10.666556
2633 01:17:10.667120 Set Vref, RX VrefLevel [Byte0]: 56
2634 01:17:10.669568 [Byte1]: 56
2635 01:17:10.674443
2636 01:17:10.675002 Set Vref, RX VrefLevel [Byte0]: 57
2637 01:17:10.677449 [Byte1]: 57
2638 01:17:10.683001
2639 01:17:10.683556 Set Vref, RX VrefLevel [Byte0]: 58
2640 01:17:10.685235 [Byte1]: 58
2641 01:17:10.690495
2642 01:17:10.691050 Set Vref, RX VrefLevel [Byte0]: 59
2643 01:17:10.693641 [Byte1]: 59
2644 01:17:10.698525
2645 01:17:10.699082 Set Vref, RX VrefLevel [Byte0]: 60
2646 01:17:10.701501 [Byte1]: 60
2647 01:17:10.705852
2648 01:17:10.706364 Set Vref, RX VrefLevel [Byte0]: 61
2649 01:17:10.709506 [Byte1]: 61
2650 01:17:10.714493
2651 01:17:10.715062 Set Vref, RX VrefLevel [Byte0]: 62
2652 01:17:10.717214 [Byte1]: 62
2653 01:17:10.721986
2654 01:17:10.722597 Set Vref, RX VrefLevel [Byte0]: 63
2655 01:17:10.725459 [Byte1]: 63
2656 01:17:10.729861
2657 01:17:10.730478 Set Vref, RX VrefLevel [Byte0]: 64
2658 01:17:10.736119 [Byte1]: 64
2659 01:17:10.736585
2660 01:17:10.739370 Set Vref, RX VrefLevel [Byte0]: 65
2661 01:17:10.742814 [Byte1]: 65
2662 01:17:10.743373
2663 01:17:10.746365 Set Vref, RX VrefLevel [Byte0]: 66
2664 01:17:10.750219 [Byte1]: 66
2665 01:17:10.753557
2666 01:17:10.754157 Final RX Vref Byte 0 = 46 to rank0
2667 01:17:10.757093 Final RX Vref Byte 1 = 51 to rank0
2668 01:17:10.760200 Final RX Vref Byte 0 = 46 to rank1
2669 01:17:10.763795 Final RX Vref Byte 1 = 51 to rank1==
2670 01:17:10.766766 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 01:17:10.773765 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2672 01:17:10.774376 ==
2673 01:17:10.774759 DQS Delay:
2674 01:17:10.775111 DQS0 = 0, DQS1 = 0
2675 01:17:10.776835 DQM Delay:
2676 01:17:10.777300 DQM0 = 113, DQM1 = 106
2677 01:17:10.779991 DQ Delay:
2678 01:17:10.783538 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2679 01:17:10.786746 DQ4 =118, DQ5 =104, DQ6 =124, DQ7 =120
2680 01:17:10.790236 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =100
2681 01:17:10.793572 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =118
2682 01:17:10.794166
2683 01:17:10.794542
2684 01:17:10.800211 [DQSOSCAuto] RK0, (LSB)MR18= 0x505, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
2685 01:17:10.803405 CH0 RK0: MR19=404, MR18=505
2686 01:17:10.810301 CH0_RK0: MR19=0x404, MR18=0x505, DQSOSC=408, MR23=63, INC=39, DEC=26
2687 01:17:10.810871
2688 01:17:10.813640 ----->DramcWriteLeveling(PI) begin...
2689 01:17:10.814227 ==
2690 01:17:10.816768 Dram Type= 6, Freq= 0, CH_0, rank 1
2691 01:17:10.820383 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2692 01:17:10.820948 ==
2693 01:17:10.823456 Write leveling (Byte 0): 27 => 27
2694 01:17:10.826592 Write leveling (Byte 1): 24 => 24
2695 01:17:10.830169 DramcWriteLeveling(PI) end<-----
2696 01:17:10.830700
2697 01:17:10.831069 ==
2698 01:17:10.833356 Dram Type= 6, Freq= 0, CH_0, rank 1
2699 01:17:10.840008 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2700 01:17:10.840568 ==
2701 01:17:10.840948 [Gating] SW mode calibration
2702 01:17:10.850002 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2703 01:17:10.853145 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2704 01:17:10.856868 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2705 01:17:10.863665 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2706 01:17:10.866634 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2707 01:17:10.870128 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2708 01:17:10.876602 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2709 01:17:10.879569 0 11 20 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2710 01:17:10.883035 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2711 01:17:10.889822 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2712 01:17:10.892893 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2713 01:17:10.896221 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2714 01:17:10.903183 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2715 01:17:10.906198 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2716 01:17:10.909792 0 12 16 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (1 1)
2717 01:17:10.916347 0 12 20 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
2718 01:17:10.919931 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2719 01:17:10.923029 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2720 01:17:10.929790 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2721 01:17:10.933490 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2722 01:17:10.936124 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2723 01:17:10.942878 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2724 01:17:10.946338 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2725 01:17:10.949987 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2726 01:17:10.956345 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2727 01:17:10.959963 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2728 01:17:10.962714 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2729 01:17:10.969678 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2730 01:17:10.973243 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2731 01:17:10.976234 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2732 01:17:10.979452 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2733 01:17:10.986224 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2734 01:17:10.989455 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2735 01:17:10.992892 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2736 01:17:10.999566 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2737 01:17:11.003012 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2738 01:17:11.006157 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2739 01:17:11.012818 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2740 01:17:11.016070 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2741 01:17:11.019449 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2742 01:17:11.022841 Total UI for P1: 0, mck2ui 16
2743 01:17:11.026144 best dqsien dly found for B0: ( 0, 15, 16)
2744 01:17:11.032745 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2745 01:17:11.033318 Total UI for P1: 0, mck2ui 16
2746 01:17:11.039179 best dqsien dly found for B1: ( 0, 15, 18)
2747 01:17:11.042727 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2748 01:17:11.046174 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2749 01:17:11.046750
2750 01:17:11.049379 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2751 01:17:11.052895 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2752 01:17:11.056077 [Gating] SW calibration Done
2753 01:17:11.056646 ==
2754 01:17:11.059206 Dram Type= 6, Freq= 0, CH_0, rank 1
2755 01:17:11.062609 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2756 01:17:11.063090 ==
2757 01:17:11.065898 RX Vref Scan: 0
2758 01:17:11.066523
2759 01:17:11.067013 RX Vref 0 -> 0, step: 1
2760 01:17:11.067467
2761 01:17:11.069417 RX Delay -40 -> 252, step: 8
2762 01:17:11.076109 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2763 01:17:11.079256 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2764 01:17:11.082938 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2765 01:17:11.086145 iDelay=200, Bit 3, Center 107 (40 ~ 175) 136
2766 01:17:11.089769 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2767 01:17:11.092918 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2768 01:17:11.099323 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2769 01:17:11.102581 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2770 01:17:11.105751 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2771 01:17:11.109120 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2772 01:17:11.112664 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2773 01:17:11.119653 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2774 01:17:11.122521 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2775 01:17:11.125810 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2776 01:17:11.129181 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2777 01:17:11.132396 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2778 01:17:11.135800 ==
2779 01:17:11.138919 Dram Type= 6, Freq= 0, CH_0, rank 1
2780 01:17:11.142447 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2781 01:17:11.142928 ==
2782 01:17:11.143411 DQS Delay:
2783 01:17:11.146087 DQS0 = 0, DQS1 = 0
2784 01:17:11.146661 DQM Delay:
2785 01:17:11.148982 DQM0 = 114, DQM1 = 106
2786 01:17:11.149557 DQ Delay:
2787 01:17:11.152376 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =107
2788 01:17:11.155821 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2789 01:17:11.159217 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2790 01:17:11.162313 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2791 01:17:11.162885
2792 01:17:11.163372
2793 01:17:11.163823 ==
2794 01:17:11.165379 Dram Type= 6, Freq= 0, CH_0, rank 1
2795 01:17:11.172442 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2796 01:17:11.173021 ==
2797 01:17:11.173513
2798 01:17:11.173967
2799 01:17:11.174436 TX Vref Scan disable
2800 01:17:11.175537 == TX Byte 0 ==
2801 01:17:11.179356 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2802 01:17:11.185333 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2803 01:17:11.185804 == TX Byte 1 ==
2804 01:17:11.189103 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2805 01:17:11.196077 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2806 01:17:11.196639 ==
2807 01:17:11.198690 Dram Type= 6, Freq= 0, CH_0, rank 1
2808 01:17:11.201917 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2809 01:17:11.202427 ==
2810 01:17:11.213523 TX Vref=22, minBit 8, minWin=24, winSum=416
2811 01:17:11.216771 TX Vref=24, minBit 8, minWin=25, winSum=422
2812 01:17:11.220407 TX Vref=26, minBit 9, minWin=25, winSum=426
2813 01:17:11.223563 TX Vref=28, minBit 8, minWin=25, winSum=428
2814 01:17:11.226687 TX Vref=30, minBit 8, minWin=25, winSum=430
2815 01:17:11.233698 TX Vref=32, minBit 8, minWin=25, winSum=430
2816 01:17:11.236952 [TxChooseVref] Worse bit 8, Min win 25, Win sum 430, Final Vref 30
2817 01:17:11.237522
2818 01:17:11.240653 Final TX Range 1 Vref 30
2819 01:17:11.241213
2820 01:17:11.241584 ==
2821 01:17:11.243364 Dram Type= 6, Freq= 0, CH_0, rank 1
2822 01:17:11.246642 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2823 01:17:11.247206 ==
2824 01:17:11.249969
2825 01:17:11.250575
2826 01:17:11.250945 TX Vref Scan disable
2827 01:17:11.253423 == TX Byte 0 ==
2828 01:17:11.256838 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2829 01:17:11.263376 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2830 01:17:11.263950 == TX Byte 1 ==
2831 01:17:11.266731 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2832 01:17:11.273601 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2833 01:17:11.274213
2834 01:17:11.274589 [DATLAT]
2835 01:17:11.274933 Freq=1200, CH0 RK1
2836 01:17:11.275268
2837 01:17:11.276838 DATLAT Default: 0xc
2838 01:17:11.277305 0, 0xFFFF, sum = 0
2839 01:17:11.279673 1, 0xFFFF, sum = 0
2840 01:17:11.283093 2, 0xFFFF, sum = 0
2841 01:17:11.283666 3, 0xFFFF, sum = 0
2842 01:17:11.286943 4, 0xFFFF, sum = 0
2843 01:17:11.287507 5, 0xFFFF, sum = 0
2844 01:17:11.290172 6, 0xFFFF, sum = 0
2845 01:17:11.290765 7, 0xFFFF, sum = 0
2846 01:17:11.293322 8, 0xFFFF, sum = 0
2847 01:17:11.293794 9, 0xFFFF, sum = 0
2848 01:17:11.296554 10, 0xFFFF, sum = 0
2849 01:17:11.297238 11, 0x0, sum = 1
2850 01:17:11.299854 12, 0x0, sum = 2
2851 01:17:11.300516 13, 0x0, sum = 3
2852 01:17:11.302969 14, 0x0, sum = 4
2853 01:17:11.303541 best_step = 12
2854 01:17:11.303915
2855 01:17:11.304369 ==
2856 01:17:11.306258 Dram Type= 6, Freq= 0, CH_0, rank 1
2857 01:17:11.309918 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2858 01:17:11.310540 ==
2859 01:17:11.312911 RX Vref Scan: 0
2860 01:17:11.313374
2861 01:17:11.316401 RX Vref 0 -> 0, step: 1
2862 01:17:11.316865
2863 01:17:11.317239 RX Delay -21 -> 252, step: 4
2864 01:17:11.323793 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2865 01:17:11.327045 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2866 01:17:11.330297 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2867 01:17:11.333507 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2868 01:17:11.337005 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2869 01:17:11.343599 iDelay=195, Bit 5, Center 106 (35 ~ 178) 144
2870 01:17:11.347199 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2871 01:17:11.350118 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
2872 01:17:11.353418 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
2873 01:17:11.357204 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2874 01:17:11.363440 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
2875 01:17:11.367142 iDelay=195, Bit 11, Center 98 (35 ~ 162) 128
2876 01:17:11.369992 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
2877 01:17:11.373474 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
2878 01:17:11.376915 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
2879 01:17:11.383311 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
2880 01:17:11.383885 ==
2881 01:17:11.386664 Dram Type= 6, Freq= 0, CH_0, rank 1
2882 01:17:11.390190 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2883 01:17:11.390754 ==
2884 01:17:11.391190 DQS Delay:
2885 01:17:11.393322 DQS0 = 0, DQS1 = 0
2886 01:17:11.393785 DQM Delay:
2887 01:17:11.396729 DQM0 = 114, DQM1 = 106
2888 01:17:11.397195 DQ Delay:
2889 01:17:11.400303 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2890 01:17:11.403279 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =124
2891 01:17:11.406761 DQ8 =94, DQ9 =90, DQ10 =108, DQ11 =98
2892 01:17:11.409769 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =116
2893 01:17:11.410229
2894 01:17:11.413253
2895 01:17:11.420259 [DQSOSCAuto] RK1, (LSB)MR18= 0xf0f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2896 01:17:11.423372 CH0 RK1: MR19=404, MR18=F0F
2897 01:17:11.426417 CH0_RK1: MR19=0x404, MR18=0xF0F, DQSOSC=404, MR23=63, INC=40, DEC=26
2898 01:17:11.430235 [RxdqsGatingPostProcess] freq 1200
2899 01:17:11.436958 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2900 01:17:11.439715 Pre-setting of DQS Precalculation
2901 01:17:11.443061 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2902 01:17:11.446719 ==
2903 01:17:11.447281 Dram Type= 6, Freq= 0, CH_1, rank 0
2904 01:17:11.453712 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2905 01:17:11.454327 ==
2906 01:17:11.456517 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2907 01:17:11.463487 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2908 01:17:11.472420 [CA 0] Center 37 (7~68) winsize 62
2909 01:17:11.475638 [CA 1] Center 37 (7~68) winsize 62
2910 01:17:11.478889 [CA 2] Center 34 (4~65) winsize 62
2911 01:17:11.481887 [CA 3] Center 33 (3~64) winsize 62
2912 01:17:11.485527 [CA 4] Center 32 (2~63) winsize 62
2913 01:17:11.489120 [CA 5] Center 32 (2~63) winsize 62
2914 01:17:11.489678
2915 01:17:11.492009 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2916 01:17:11.492474
2917 01:17:11.495571 [CATrainingPosCal] consider 1 rank data
2918 01:17:11.498643 u2DelayCellTimex100 = 270/100 ps
2919 01:17:11.502379 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2920 01:17:11.508903 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2921 01:17:11.512928 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2922 01:17:11.515328 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2923 01:17:11.518879 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2924 01:17:11.521856 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2925 01:17:11.522474
2926 01:17:11.525366 CA PerBit enable=1, Macro0, CA PI delay=32
2927 01:17:11.525938
2928 01:17:11.528526 [CBTSetCACLKResult] CA Dly = 32
2929 01:17:11.529097 CS Dly: 6 (0~37)
2930 01:17:11.531582 ==
2931 01:17:11.535115 Dram Type= 6, Freq= 0, CH_1, rank 1
2932 01:17:11.538557 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2933 01:17:11.539019 ==
2934 01:17:11.541710 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2935 01:17:11.548788 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2936 01:17:11.557667 [CA 0] Center 37 (7~68) winsize 62
2937 01:17:11.561120 [CA 1] Center 37 (7~68) winsize 62
2938 01:17:11.563784 [CA 2] Center 34 (3~65) winsize 63
2939 01:17:11.567307 [CA 3] Center 33 (3~64) winsize 62
2940 01:17:11.570908 [CA 4] Center 32 (2~63) winsize 62
2941 01:17:11.574491 [CA 5] Center 32 (1~63) winsize 63
2942 01:17:11.575049
2943 01:17:11.577270 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2944 01:17:11.577737
2945 01:17:11.580609 [CATrainingPosCal] consider 2 rank data
2946 01:17:11.584140 u2DelayCellTimex100 = 270/100 ps
2947 01:17:11.587544 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2948 01:17:11.590976 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2949 01:17:11.597506 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2950 01:17:11.600941 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2951 01:17:11.603787 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2952 01:17:11.607375 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2953 01:17:11.607937
2954 01:17:11.610956 CA PerBit enable=1, Macro0, CA PI delay=32
2955 01:17:11.611513
2956 01:17:11.614132 [CBTSetCACLKResult] CA Dly = 32
2957 01:17:11.614681 CS Dly: 6 (0~38)
2958 01:17:11.615058
2959 01:17:11.617251 ----->DramcWriteLeveling(PI) begin...
2960 01:17:11.620824 ==
2961 01:17:11.624272 Dram Type= 6, Freq= 0, CH_1, rank 0
2962 01:17:11.627588 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2963 01:17:11.628154 ==
2964 01:17:11.630348 Write leveling (Byte 0): 20 => 20
2965 01:17:11.634192 Write leveling (Byte 1): 22 => 22
2966 01:17:11.637447 DramcWriteLeveling(PI) end<-----
2967 01:17:11.638004
2968 01:17:11.638447 ==
2969 01:17:11.640694 Dram Type= 6, Freq= 0, CH_1, rank 0
2970 01:17:11.644298 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2971 01:17:11.644864 ==
2972 01:17:11.647051 [Gating] SW mode calibration
2973 01:17:11.654112 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2974 01:17:11.660745 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2975 01:17:11.664001 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2976 01:17:11.667179 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2977 01:17:11.670563 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2978 01:17:11.677184 0 11 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2979 01:17:11.680589 0 11 16 | B1->B0 | 2f2f 2929 | 1 0 | (1 0) (1 0)
2980 01:17:11.683824 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2981 01:17:11.690362 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2982 01:17:11.693706 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2983 01:17:11.697461 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2984 01:17:11.703783 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2985 01:17:11.706998 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2986 01:17:11.710454 0 12 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2987 01:17:11.717121 0 12 16 | B1->B0 | 3131 4444 | 0 0 | (1 1) (0 0)
2988 01:17:11.720497 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2989 01:17:11.723555 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2990 01:17:11.730282 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2991 01:17:11.733452 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2992 01:17:11.737271 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2993 01:17:11.743522 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2994 01:17:11.746945 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2995 01:17:11.750300 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2996 01:17:11.757151 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2997 01:17:11.760577 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2998 01:17:11.763736 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2999 01:17:11.770231 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3000 01:17:11.773526 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3001 01:17:11.777097 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3002 01:17:11.780190 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3003 01:17:11.786864 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3004 01:17:11.790481 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3005 01:17:11.793648 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3006 01:17:11.800541 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3007 01:17:11.804013 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3008 01:17:11.807066 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3009 01:17:11.813740 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3010 01:17:11.817083 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3011 01:17:11.820125 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3012 01:17:11.826831 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3013 01:17:11.830020 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3014 01:17:11.833592 Total UI for P1: 0, mck2ui 16
3015 01:17:11.837278 best dqsien dly found for B0: ( 0, 15, 16)
3016 01:17:11.840228 Total UI for P1: 0, mck2ui 16
3017 01:17:11.843491 best dqsien dly found for B1: ( 0, 15, 18)
3018 01:17:11.846901 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3019 01:17:11.850288 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3020 01:17:11.850841
3021 01:17:11.853549 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3022 01:17:11.856876 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3023 01:17:11.860159 [Gating] SW calibration Done
3024 01:17:11.860715 ==
3025 01:17:11.863743 Dram Type= 6, Freq= 0, CH_1, rank 0
3026 01:17:11.870214 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3027 01:17:11.870769 ==
3028 01:17:11.871140 RX Vref Scan: 0
3029 01:17:11.871486
3030 01:17:11.873502 RX Vref 0 -> 0, step: 1
3031 01:17:11.874100
3032 01:17:11.876598 RX Delay -40 -> 252, step: 8
3033 01:17:11.879630 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3034 01:17:11.883784 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3035 01:17:11.886646 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3036 01:17:11.890104 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3037 01:17:11.896660 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3038 01:17:11.899980 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3039 01:17:11.903081 iDelay=208, Bit 6, Center 119 (40 ~ 199) 160
3040 01:17:11.906961 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3041 01:17:11.909928 iDelay=208, Bit 8, Center 91 (24 ~ 159) 136
3042 01:17:11.916684 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3043 01:17:11.919968 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3044 01:17:11.923533 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3045 01:17:11.926459 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3046 01:17:11.929980 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3047 01:17:11.936431 iDelay=208, Bit 14, Center 115 (48 ~ 183) 136
3048 01:17:11.940348 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3049 01:17:11.940904 ==
3050 01:17:11.942966 Dram Type= 6, Freq= 0, CH_1, rank 0
3051 01:17:11.946329 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3052 01:17:11.946850 ==
3053 01:17:11.950223 DQS Delay:
3054 01:17:11.950831 DQS0 = 0, DQS1 = 0
3055 01:17:11.951209 DQM Delay:
3056 01:17:11.953207 DQM0 = 116, DQM1 = 107
3057 01:17:11.953670 DQ Delay:
3058 01:17:11.956247 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3059 01:17:11.960020 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3060 01:17:11.963833 DQ8 =91, DQ9 =95, DQ10 =111, DQ11 =95
3061 01:17:11.966538 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =119
3062 01:17:11.970210
3063 01:17:11.970760
3064 01:17:11.971133 ==
3065 01:17:11.973540 Dram Type= 6, Freq= 0, CH_1, rank 0
3066 01:17:11.976277 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3067 01:17:11.976743 ==
3068 01:17:11.977109
3069 01:17:11.977452
3070 01:17:11.979613 TX Vref Scan disable
3071 01:17:11.980131 == TX Byte 0 ==
3072 01:17:11.986512 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3073 01:17:11.990425 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3074 01:17:11.990987 == TX Byte 1 ==
3075 01:17:11.996696 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3076 01:17:11.999544 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3077 01:17:12.000010 ==
3078 01:17:12.003171 Dram Type= 6, Freq= 0, CH_1, rank 0
3079 01:17:12.006168 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3080 01:17:12.006642 ==
3081 01:17:12.018924 TX Vref=22, minBit 0, minWin=25, winSum=413
3082 01:17:12.021895 TX Vref=24, minBit 7, minWin=25, winSum=419
3083 01:17:12.025073 TX Vref=26, minBit 0, minWin=26, winSum=422
3084 01:17:12.028669 TX Vref=28, minBit 0, minWin=26, winSum=427
3085 01:17:12.032315 TX Vref=30, minBit 8, minWin=26, winSum=429
3086 01:17:12.038595 TX Vref=32, minBit 0, minWin=26, winSum=428
3087 01:17:12.042375 [TxChooseVref] Worse bit 8, Min win 26, Win sum 429, Final Vref 30
3088 01:17:12.042951
3089 01:17:12.045118 Final TX Range 1 Vref 30
3090 01:17:12.045676
3091 01:17:12.046075 ==
3092 01:17:12.048676 Dram Type= 6, Freq= 0, CH_1, rank 0
3093 01:17:12.051913 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3094 01:17:12.052475 ==
3095 01:17:12.054915
3096 01:17:12.055368
3097 01:17:12.055728 TX Vref Scan disable
3098 01:17:12.058263 == TX Byte 0 ==
3099 01:17:12.061733 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3100 01:17:12.065372 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3101 01:17:12.068655 == TX Byte 1 ==
3102 01:17:12.071535 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3103 01:17:12.074976 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3104 01:17:12.078464
3105 01:17:12.078917 [DATLAT]
3106 01:17:12.079276 Freq=1200, CH1 RK0
3107 01:17:12.079619
3108 01:17:12.081505 DATLAT Default: 0xd
3109 01:17:12.081977 0, 0xFFFF, sum = 0
3110 01:17:12.085108 1, 0xFFFF, sum = 0
3111 01:17:12.085572 2, 0xFFFF, sum = 0
3112 01:17:12.088651 3, 0xFFFF, sum = 0
3113 01:17:12.089118 4, 0xFFFF, sum = 0
3114 01:17:12.091707 5, 0xFFFF, sum = 0
3115 01:17:12.095322 6, 0xFFFF, sum = 0
3116 01:17:12.095890 7, 0xFFFF, sum = 0
3117 01:17:12.098202 8, 0xFFFF, sum = 0
3118 01:17:12.098664 9, 0xFFFF, sum = 0
3119 01:17:12.101625 10, 0xFFFF, sum = 0
3120 01:17:12.102226 11, 0x0, sum = 1
3121 01:17:12.105123 12, 0x0, sum = 2
3122 01:17:12.105686 13, 0x0, sum = 3
3123 01:17:12.106105 14, 0x0, sum = 4
3124 01:17:12.108206 best_step = 12
3125 01:17:12.108660
3126 01:17:12.109175 ==
3127 01:17:12.111904 Dram Type= 6, Freq= 0, CH_1, rank 0
3128 01:17:12.114935 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3129 01:17:12.115515 ==
3130 01:17:12.118713 RX Vref Scan: 1
3131 01:17:12.119266
3132 01:17:12.121688 Set Vref Range= 32 -> 127
3133 01:17:12.122350
3134 01:17:12.122838 RX Vref 32 -> 127, step: 1
3135 01:17:12.123194
3136 01:17:12.124875 RX Delay -21 -> 252, step: 4
3137 01:17:12.125332
3138 01:17:12.128248 Set Vref, RX VrefLevel [Byte0]: 32
3139 01:17:12.131272 [Byte1]: 32
3140 01:17:12.135059
3141 01:17:12.135512 Set Vref, RX VrefLevel [Byte0]: 33
3142 01:17:12.138234 [Byte1]: 33
3143 01:17:12.142998
3144 01:17:12.143549 Set Vref, RX VrefLevel [Byte0]: 34
3145 01:17:12.146161 [Byte1]: 34
3146 01:17:12.151062
3147 01:17:12.151616 Set Vref, RX VrefLevel [Byte0]: 35
3148 01:17:12.154186 [Byte1]: 35
3149 01:17:12.158938
3150 01:17:12.159499 Set Vref, RX VrefLevel [Byte0]: 36
3151 01:17:12.162220 [Byte1]: 36
3152 01:17:12.166652
3153 01:17:12.167211 Set Vref, RX VrefLevel [Byte0]: 37
3154 01:17:12.170187 [Byte1]: 37
3155 01:17:12.174974
3156 01:17:12.175531 Set Vref, RX VrefLevel [Byte0]: 38
3157 01:17:12.177917 [Byte1]: 38
3158 01:17:12.182402
3159 01:17:12.182859 Set Vref, RX VrefLevel [Byte0]: 39
3160 01:17:12.186235 [Byte1]: 39
3161 01:17:12.190534
3162 01:17:12.191086 Set Vref, RX VrefLevel [Byte0]: 40
3163 01:17:12.193931 [Byte1]: 40
3164 01:17:12.198578
3165 01:17:12.199131 Set Vref, RX VrefLevel [Byte0]: 41
3166 01:17:12.201717 [Byte1]: 41
3167 01:17:12.206250
3168 01:17:12.206799 Set Vref, RX VrefLevel [Byte0]: 42
3169 01:17:12.209639 [Byte1]: 42
3170 01:17:12.214233
3171 01:17:12.214804 Set Vref, RX VrefLevel [Byte0]: 43
3172 01:17:12.217317 [Byte1]: 43
3173 01:17:12.222404
3174 01:17:12.223201 Set Vref, RX VrefLevel [Byte0]: 44
3175 01:17:12.225553 [Byte1]: 44
3176 01:17:12.230337
3177 01:17:12.230888 Set Vref, RX VrefLevel [Byte0]: 45
3178 01:17:12.233499 [Byte1]: 45
3179 01:17:12.237982
3180 01:17:12.238507 Set Vref, RX VrefLevel [Byte0]: 46
3181 01:17:12.241593 [Byte1]: 46
3182 01:17:12.246261
3183 01:17:12.246833 Set Vref, RX VrefLevel [Byte0]: 47
3184 01:17:12.249263 [Byte1]: 47
3185 01:17:12.253878
3186 01:17:12.254501 Set Vref, RX VrefLevel [Byte0]: 48
3187 01:17:12.257044 [Byte1]: 48
3188 01:17:12.261950
3189 01:17:12.262571 Set Vref, RX VrefLevel [Byte0]: 49
3190 01:17:12.265458 [Byte1]: 49
3191 01:17:12.270338
3192 01:17:12.270920 Set Vref, RX VrefLevel [Byte0]: 50
3193 01:17:12.273066 [Byte1]: 50
3194 01:17:12.277802
3195 01:17:12.278411 Set Vref, RX VrefLevel [Byte0]: 51
3196 01:17:12.280967 [Byte1]: 51
3197 01:17:12.285698
3198 01:17:12.286333 Set Vref, RX VrefLevel [Byte0]: 52
3199 01:17:12.288888 [Byte1]: 52
3200 01:17:12.293540
3201 01:17:12.294147 Set Vref, RX VrefLevel [Byte0]: 53
3202 01:17:12.297204 [Byte1]: 53
3203 01:17:12.301487
3204 01:17:12.302097 Set Vref, RX VrefLevel [Byte0]: 54
3205 01:17:12.304733 [Byte1]: 54
3206 01:17:12.309057
3207 01:17:12.309535 Set Vref, RX VrefLevel [Byte0]: 55
3208 01:17:12.312809 [Byte1]: 55
3209 01:17:12.317128
3210 01:17:12.317697 Set Vref, RX VrefLevel [Byte0]: 56
3211 01:17:12.320579 [Byte1]: 56
3212 01:17:12.324830
3213 01:17:12.325309 Set Vref, RX VrefLevel [Byte0]: 57
3214 01:17:12.328762 [Byte1]: 57
3215 01:17:12.332844
3216 01:17:12.333334 Set Vref, RX VrefLevel [Byte0]: 58
3217 01:17:12.336037 [Byte1]: 58
3218 01:17:12.341109
3219 01:17:12.341677 Set Vref, RX VrefLevel [Byte0]: 59
3220 01:17:12.344295 [Byte1]: 59
3221 01:17:12.349120
3222 01:17:12.349691 Set Vref, RX VrefLevel [Byte0]: 60
3223 01:17:12.352108 [Byte1]: 60
3224 01:17:12.356860
3225 01:17:12.357331 Set Vref, RX VrefLevel [Byte0]: 61
3226 01:17:12.360086 [Byte1]: 61
3227 01:17:12.365075
3228 01:17:12.365658 Set Vref, RX VrefLevel [Byte0]: 62
3229 01:17:12.368061 [Byte1]: 62
3230 01:17:12.372620
3231 01:17:12.373194 Set Vref, RX VrefLevel [Byte0]: 63
3232 01:17:12.375814 [Byte1]: 63
3233 01:17:12.380751
3234 01:17:12.381325 Set Vref, RX VrefLevel [Byte0]: 64
3235 01:17:12.384148 [Byte1]: 64
3236 01:17:12.388229
3237 01:17:12.388724 Set Vref, RX VrefLevel [Byte0]: 65
3238 01:17:12.392058 [Byte1]: 65
3239 01:17:12.396724
3240 01:17:12.397295 Set Vref, RX VrefLevel [Byte0]: 66
3241 01:17:12.399373 [Byte1]: 66
3242 01:17:12.404382
3243 01:17:12.404953 Set Vref, RX VrefLevel [Byte0]: 67
3244 01:17:12.407980 [Byte1]: 67
3245 01:17:12.413040
3246 01:17:12.413616 Final RX Vref Byte 0 = 56 to rank0
3247 01:17:12.415228 Final RX Vref Byte 1 = 51 to rank0
3248 01:17:12.418500 Final RX Vref Byte 0 = 56 to rank1
3249 01:17:12.421827 Final RX Vref Byte 1 = 51 to rank1==
3250 01:17:12.424995 Dram Type= 6, Freq= 0, CH_1, rank 0
3251 01:17:12.431820 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3252 01:17:12.432381 ==
3253 01:17:12.432870 DQS Delay:
3254 01:17:12.435035 DQS0 = 0, DQS1 = 0
3255 01:17:12.435514 DQM Delay:
3256 01:17:12.435993 DQM0 = 115, DQM1 = 105
3257 01:17:12.438598 DQ Delay:
3258 01:17:12.441788 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3259 01:17:12.445217 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3260 01:17:12.448219 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3261 01:17:12.451416 DQ12 =112, DQ13 =116, DQ14 =114, DQ15 =116
3262 01:17:12.451893
3263 01:17:12.452373
3264 01:17:12.461814 [DQSOSCAuto] RK0, (LSB)MR18= 0x1111, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
3265 01:17:12.462421 CH1 RK0: MR19=404, MR18=1111
3266 01:17:12.468129 CH1_RK0: MR19=0x404, MR18=0x1111, DQSOSC=403, MR23=63, INC=40, DEC=26
3267 01:17:12.468690
3268 01:17:12.471935 ----->DramcWriteLeveling(PI) begin...
3269 01:17:12.472419 ==
3270 01:17:12.474737 Dram Type= 6, Freq= 0, CH_1, rank 1
3271 01:17:12.481367 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3272 01:17:12.481850 ==
3273 01:17:12.485035 Write leveling (Byte 0): 22 => 22
3274 01:17:12.485769 Write leveling (Byte 1): 22 => 22
3275 01:17:12.488253 DramcWriteLeveling(PI) end<-----
3276 01:17:12.489095
3277 01:17:12.489760 ==
3278 01:17:12.491622 Dram Type= 6, Freq= 0, CH_1, rank 1
3279 01:17:12.498188 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3280 01:17:12.498613 ==
3281 01:17:12.501459 [Gating] SW mode calibration
3282 01:17:12.508232 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3283 01:17:12.511827 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3284 01:17:12.518287 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3285 01:17:12.521269 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3286 01:17:12.524673 0 11 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3287 01:17:12.531276 0 11 12 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0)
3288 01:17:12.534836 0 11 16 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
3289 01:17:12.537944 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3290 01:17:12.544762 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3291 01:17:12.548016 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3292 01:17:12.551316 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3293 01:17:12.557914 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3294 01:17:12.561056 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3295 01:17:12.564433 0 12 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
3296 01:17:12.571275 0 12 16 | B1->B0 | 3434 4545 | 1 0 | (0 0) (0 0)
3297 01:17:12.574119 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3298 01:17:12.577685 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3299 01:17:12.581044 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3300 01:17:12.587648 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3301 01:17:12.591312 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3302 01:17:12.594300 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3303 01:17:12.600978 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3304 01:17:12.604676 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3305 01:17:12.607962 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3306 01:17:12.614310 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3307 01:17:12.617577 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3308 01:17:12.621009 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3309 01:17:12.627584 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3310 01:17:12.631380 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3311 01:17:12.634229 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3312 01:17:12.641200 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3313 01:17:12.644426 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3314 01:17:12.647866 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3315 01:17:12.654349 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3316 01:17:12.657620 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3317 01:17:12.661122 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3318 01:17:12.667317 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3319 01:17:12.671064 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3320 01:17:12.674313 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3321 01:17:12.677854 Total UI for P1: 0, mck2ui 16
3322 01:17:12.680633 best dqsien dly found for B0: ( 0, 15, 12)
3323 01:17:12.687811 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3324 01:17:12.688268 Total UI for P1: 0, mck2ui 16
3325 01:17:12.690572 best dqsien dly found for B1: ( 0, 15, 16)
3326 01:17:12.697776 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3327 01:17:12.701008 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3328 01:17:12.701564
3329 01:17:12.704241 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3330 01:17:12.707427 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3331 01:17:12.710692 [Gating] SW calibration Done
3332 01:17:12.711148 ==
3333 01:17:12.714579 Dram Type= 6, Freq= 0, CH_1, rank 1
3334 01:17:12.717498 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3335 01:17:12.718100 ==
3336 01:17:12.720837 RX Vref Scan: 0
3337 01:17:12.721384
3338 01:17:12.721747 RX Vref 0 -> 0, step: 1
3339 01:17:12.722135
3340 01:17:12.724118 RX Delay -40 -> 252, step: 8
3341 01:17:12.727036 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3342 01:17:12.734009 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
3343 01:17:12.737266 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3344 01:17:12.740874 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3345 01:17:12.744322 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3346 01:17:12.747523 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3347 01:17:12.754180 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3348 01:17:12.757190 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3349 01:17:12.760507 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3350 01:17:12.763934 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3351 01:17:12.767016 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3352 01:17:12.770400 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3353 01:17:12.777452 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3354 01:17:12.780444 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3355 01:17:12.783869 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3356 01:17:12.787167 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3357 01:17:12.787628 ==
3358 01:17:12.790553 Dram Type= 6, Freq= 0, CH_1, rank 1
3359 01:17:12.797403 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3360 01:17:12.797969 ==
3361 01:17:12.798400 DQS Delay:
3362 01:17:12.800825 DQS0 = 0, DQS1 = 0
3363 01:17:12.801383 DQM Delay:
3364 01:17:12.803982 DQM0 = 116, DQM1 = 107
3365 01:17:12.804537 DQ Delay:
3366 01:17:12.807110 DQ0 =119, DQ1 =115, DQ2 =107, DQ3 =115
3367 01:17:12.810854 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3368 01:17:12.813758 DQ8 =95, DQ9 =91, DQ10 =111, DQ11 =99
3369 01:17:12.817131 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =111
3370 01:17:12.817688
3371 01:17:12.818087
3372 01:17:12.818435 ==
3373 01:17:12.820387 Dram Type= 6, Freq= 0, CH_1, rank 1
3374 01:17:12.823840 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3375 01:17:12.826871 ==
3376 01:17:12.827473
3377 01:17:12.827850
3378 01:17:12.828191 TX Vref Scan disable
3379 01:17:12.830539 == TX Byte 0 ==
3380 01:17:12.833647 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3381 01:17:12.836856 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3382 01:17:12.840371 == TX Byte 1 ==
3383 01:17:12.844182 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3384 01:17:12.846675 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3385 01:17:12.850140 ==
3386 01:17:12.850600 Dram Type= 6, Freq= 0, CH_1, rank 1
3387 01:17:12.856542 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3388 01:17:12.856957 ==
3389 01:17:12.867627 TX Vref=22, minBit 8, minWin=25, winSum=418
3390 01:17:12.871228 TX Vref=24, minBit 9, minWin=25, winSum=424
3391 01:17:12.874497 TX Vref=26, minBit 3, minWin=26, winSum=428
3392 01:17:12.877506 TX Vref=28, minBit 3, minWin=26, winSum=433
3393 01:17:12.880781 TX Vref=30, minBit 9, minWin=26, winSum=432
3394 01:17:12.884746 TX Vref=32, minBit 0, minWin=26, winSum=430
3395 01:17:12.890783 [TxChooseVref] Worse bit 3, Min win 26, Win sum 433, Final Vref 28
3396 01:17:12.891250
3397 01:17:12.894530 Final TX Range 1 Vref 28
3398 01:17:12.895086
3399 01:17:12.895452 ==
3400 01:17:12.897756 Dram Type= 6, Freq= 0, CH_1, rank 1
3401 01:17:12.901435 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3402 01:17:12.902012 ==
3403 01:17:12.902428
3404 01:17:12.904429
3405 01:17:12.904887 TX Vref Scan disable
3406 01:17:12.907717 == TX Byte 0 ==
3407 01:17:12.911278 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3408 01:17:12.914128 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3409 01:17:12.917616 == TX Byte 1 ==
3410 01:17:12.921227 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3411 01:17:12.924469 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3412 01:17:12.925026
3413 01:17:12.927532 [DATLAT]
3414 01:17:12.928099 Freq=1200, CH1 RK1
3415 01:17:12.928475
3416 01:17:12.931056 DATLAT Default: 0xc
3417 01:17:12.931517 0, 0xFFFF, sum = 0
3418 01:17:12.934620 1, 0xFFFF, sum = 0
3419 01:17:12.935082 2, 0xFFFF, sum = 0
3420 01:17:12.937765 3, 0xFFFF, sum = 0
3421 01:17:12.938268 4, 0xFFFF, sum = 0
3422 01:17:12.941327 5, 0xFFFF, sum = 0
3423 01:17:12.941903 6, 0xFFFF, sum = 0
3424 01:17:12.944740 7, 0xFFFF, sum = 0
3425 01:17:12.945307 8, 0xFFFF, sum = 0
3426 01:17:12.947681 9, 0xFFFF, sum = 0
3427 01:17:12.948149 10, 0xFFFF, sum = 0
3428 01:17:12.951193 11, 0x0, sum = 1
3429 01:17:12.951661 12, 0x0, sum = 2
3430 01:17:12.954986 13, 0x0, sum = 3
3431 01:17:12.955607 14, 0x0, sum = 4
3432 01:17:12.958301 best_step = 12
3433 01:17:12.958858
3434 01:17:12.959223 ==
3435 01:17:12.961356 Dram Type= 6, Freq= 0, CH_1, rank 1
3436 01:17:12.964505 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3437 01:17:12.965066 ==
3438 01:17:12.967864 RX Vref Scan: 0
3439 01:17:12.968432
3440 01:17:12.968804 RX Vref 0 -> 0, step: 1
3441 01:17:12.969233
3442 01:17:12.971121 RX Delay -29 -> 252, step: 4
3443 01:17:12.977985 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3444 01:17:12.981026 iDelay=199, Bit 1, Center 112 (43 ~ 182) 140
3445 01:17:12.984379 iDelay=199, Bit 2, Center 106 (39 ~ 174) 136
3446 01:17:12.987889 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3447 01:17:12.991065 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3448 01:17:12.998153 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3449 01:17:13.001046 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3450 01:17:13.005213 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3451 01:17:13.007702 iDelay=199, Bit 8, Center 88 (19 ~ 158) 140
3452 01:17:13.011181 iDelay=199, Bit 9, Center 92 (23 ~ 162) 140
3453 01:17:13.017793 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3454 01:17:13.020890 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3455 01:17:13.024639 iDelay=199, Bit 12, Center 114 (43 ~ 186) 144
3456 01:17:13.027735 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3457 01:17:13.031242 iDelay=199, Bit 14, Center 114 (47 ~ 182) 136
3458 01:17:13.037641 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3459 01:17:13.038249 ==
3460 01:17:13.041012 Dram Type= 6, Freq= 0, CH_1, rank 1
3461 01:17:13.044299 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3462 01:17:13.044762 ==
3463 01:17:13.045129 DQS Delay:
3464 01:17:13.047892 DQS0 = 0, DQS1 = 0
3465 01:17:13.048459 DQM Delay:
3466 01:17:13.051109 DQM0 = 114, DQM1 = 104
3467 01:17:13.051681 DQ Delay:
3468 01:17:13.054680 DQ0 =114, DQ1 =112, DQ2 =106, DQ3 =112
3469 01:17:13.058199 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3470 01:17:13.060928 DQ8 =88, DQ9 =92, DQ10 =106, DQ11 =98
3471 01:17:13.064592 DQ12 =114, DQ13 =114, DQ14 =114, DQ15 =110
3472 01:17:13.065154
3473 01:17:13.065526
3474 01:17:13.074453 [DQSOSCAuto] RK1, (LSB)MR18= 0x707, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
3475 01:17:13.077744 CH1 RK1: MR19=404, MR18=707
3476 01:17:13.081012 CH1_RK1: MR19=0x404, MR18=0x707, DQSOSC=407, MR23=63, INC=39, DEC=26
3477 01:17:13.084175 [RxdqsGatingPostProcess] freq 1200
3478 01:17:13.090849 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3479 01:17:13.094399 Pre-setting of DQS Precalculation
3480 01:17:13.097878 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3481 01:17:13.107968 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3482 01:17:13.114590 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3483 01:17:13.115057
3484 01:17:13.115422
3485 01:17:13.117759 [Calibration Summary] 2400 Mbps
3486 01:17:13.118261 CH 0, Rank 0
3487 01:17:13.121188 SW Impedance : PASS
3488 01:17:13.121751 DUTY Scan : NO K
3489 01:17:13.124295 ZQ Calibration : PASS
3490 01:17:13.127561 Jitter Meter : NO K
3491 01:17:13.128153 CBT Training : PASS
3492 01:17:13.130574 Write leveling : PASS
3493 01:17:13.134385 RX DQS gating : PASS
3494 01:17:13.134950 RX DQ/DQS(RDDQC) : PASS
3495 01:17:13.137910 TX DQ/DQS : PASS
3496 01:17:13.140564 RX DATLAT : PASS
3497 01:17:13.141043 RX DQ/DQS(Engine): PASS
3498 01:17:13.144451 TX OE : NO K
3499 01:17:13.145022 All Pass.
3500 01:17:13.145393
3501 01:17:13.147457 CH 0, Rank 1
3502 01:17:13.148022 SW Impedance : PASS
3503 01:17:13.151154 DUTY Scan : NO K
3504 01:17:13.153975 ZQ Calibration : PASS
3505 01:17:13.154591 Jitter Meter : NO K
3506 01:17:13.157499 CBT Training : PASS
3507 01:17:13.158112 Write leveling : PASS
3508 01:17:13.160811 RX DQS gating : PASS
3509 01:17:13.164286 RX DQ/DQS(RDDQC) : PASS
3510 01:17:13.164848 TX DQ/DQS : PASS
3511 01:17:13.167329 RX DATLAT : PASS
3512 01:17:13.170639 RX DQ/DQS(Engine): PASS
3513 01:17:13.171204 TX OE : NO K
3514 01:17:13.174326 All Pass.
3515 01:17:13.174896
3516 01:17:13.175262 CH 1, Rank 0
3517 01:17:13.177295 SW Impedance : PASS
3518 01:17:13.177869 DUTY Scan : NO K
3519 01:17:13.180662 ZQ Calibration : PASS
3520 01:17:13.183867 Jitter Meter : NO K
3521 01:17:13.184333 CBT Training : PASS
3522 01:17:13.187129 Write leveling : PASS
3523 01:17:13.190481 RX DQS gating : PASS
3524 01:17:13.190992 RX DQ/DQS(RDDQC) : PASS
3525 01:17:13.193867 TX DQ/DQS : PASS
3526 01:17:13.197375 RX DATLAT : PASS
3527 01:17:13.198110 RX DQ/DQS(Engine): PASS
3528 01:17:13.201047 TX OE : NO K
3529 01:17:13.201674 All Pass.
3530 01:17:13.202093
3531 01:17:13.203703 CH 1, Rank 1
3532 01:17:13.204159 SW Impedance : PASS
3533 01:17:13.207023 DUTY Scan : NO K
3534 01:17:13.207489 ZQ Calibration : PASS
3535 01:17:13.210382 Jitter Meter : NO K
3536 01:17:13.213804 CBT Training : PASS
3537 01:17:13.214409 Write leveling : PASS
3538 01:17:13.217326 RX DQS gating : PASS
3539 01:17:13.220467 RX DQ/DQS(RDDQC) : PASS
3540 01:17:13.221030 TX DQ/DQS : PASS
3541 01:17:13.223938 RX DATLAT : PASS
3542 01:17:13.226893 RX DQ/DQS(Engine): PASS
3543 01:17:13.227425 TX OE : NO K
3544 01:17:13.230134 All Pass.
3545 01:17:13.230642
3546 01:17:13.231013 DramC Write-DBI off
3547 01:17:13.233522 PER_BANK_REFRESH: Hybrid Mode
3548 01:17:13.234019 TX_TRACKING: ON
3549 01:17:13.243636 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3550 01:17:13.246709 [FAST_K] Save calibration result to emmc
3551 01:17:13.250414 dramc_set_vcore_voltage set vcore to 650000
3552 01:17:13.253314 Read voltage for 600, 5
3553 01:17:13.253873 Vio18 = 0
3554 01:17:13.256626 Vcore = 650000
3555 01:17:13.257185 Vdram = 0
3556 01:17:13.257623 Vddq = 0
3557 01:17:13.260352 Vmddr = 0
3558 01:17:13.263624 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3559 01:17:13.270185 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3560 01:17:13.270750 MEM_TYPE=3, freq_sel=19
3561 01:17:13.273124 sv_algorithm_assistance_LP4_1600
3562 01:17:13.280047 ============ PULL DRAM RESETB DOWN ============
3563 01:17:13.282870 ========== PULL DRAM RESETB DOWN end =========
3564 01:17:13.286241 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3565 01:17:13.289770 ===================================
3566 01:17:13.293306 LPDDR4 DRAM CONFIGURATION
3567 01:17:13.296473 ===================================
3568 01:17:13.299804 EX_ROW_EN[0] = 0x0
3569 01:17:13.300358 EX_ROW_EN[1] = 0x0
3570 01:17:13.303149 LP4Y_EN = 0x0
3571 01:17:13.303613 WORK_FSP = 0x0
3572 01:17:13.306694 WL = 0x2
3573 01:17:13.307259 RL = 0x2
3574 01:17:13.309747 BL = 0x2
3575 01:17:13.310358 RPST = 0x0
3576 01:17:13.313054 RD_PRE = 0x0
3577 01:17:13.313608 WR_PRE = 0x1
3578 01:17:13.316295 WR_PST = 0x0
3579 01:17:13.316847 DBI_WR = 0x0
3580 01:17:13.319918 DBI_RD = 0x0
3581 01:17:13.320476 OTF = 0x1
3582 01:17:13.323175 ===================================
3583 01:17:13.326441 ===================================
3584 01:17:13.329185 ANA top config
3585 01:17:13.332937 ===================================
3586 01:17:13.336039 DLL_ASYNC_EN = 0
3587 01:17:13.336521 ALL_SLAVE_EN = 1
3588 01:17:13.339150 NEW_RANK_MODE = 1
3589 01:17:13.342467 DLL_IDLE_MODE = 1
3590 01:17:13.345651 LP45_APHY_COMB_EN = 1
3591 01:17:13.349170 TX_ODT_DIS = 1
3592 01:17:13.349725 NEW_8X_MODE = 1
3593 01:17:13.352414 ===================================
3594 01:17:13.355691 ===================================
3595 01:17:13.359230 data_rate = 1200
3596 01:17:13.362380 CKR = 1
3597 01:17:13.365627 DQ_P2S_RATIO = 8
3598 01:17:13.369245 ===================================
3599 01:17:13.372347 CA_P2S_RATIO = 8
3600 01:17:13.375901 DQ_CA_OPEN = 0
3601 01:17:13.376461 DQ_SEMI_OPEN = 0
3602 01:17:13.378657 CA_SEMI_OPEN = 0
3603 01:17:13.381879 CA_FULL_RATE = 0
3604 01:17:13.385580 DQ_CKDIV4_EN = 1
3605 01:17:13.389022 CA_CKDIV4_EN = 1
3606 01:17:13.391968 CA_PREDIV_EN = 0
3607 01:17:13.392429 PH8_DLY = 0
3608 01:17:13.395446 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3609 01:17:13.398994 DQ_AAMCK_DIV = 4
3610 01:17:13.402258 CA_AAMCK_DIV = 4
3611 01:17:13.405300 CA_ADMCK_DIV = 4
3612 01:17:13.408970 DQ_TRACK_CA_EN = 0
3613 01:17:13.411851 CA_PICK = 600
3614 01:17:13.412315 CA_MCKIO = 600
3615 01:17:13.415269 MCKIO_SEMI = 0
3616 01:17:13.418193 PLL_FREQ = 2288
3617 01:17:13.421551 DQ_UI_PI_RATIO = 32
3618 01:17:13.424967 CA_UI_PI_RATIO = 0
3619 01:17:13.428167 ===================================
3620 01:17:13.431441 ===================================
3621 01:17:13.434751 memory_type:LPDDR4
3622 01:17:13.435208 GP_NUM : 10
3623 01:17:13.437894 SRAM_EN : 1
3624 01:17:13.438403 MD32_EN : 0
3625 01:17:13.441519 ===================================
3626 01:17:13.445013 [ANA_INIT] >>>>>>>>>>>>>>
3627 01:17:13.448101 <<<<<< [CONFIGURE PHASE]: ANA_TX
3628 01:17:13.451332 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3629 01:17:13.454489 ===================================
3630 01:17:13.457771 data_rate = 1200,PCW = 0X5800
3631 01:17:13.461608 ===================================
3632 01:17:13.464706 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3633 01:17:13.471417 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3634 01:17:13.474526 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3635 01:17:13.481081 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3636 01:17:13.484227 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3637 01:17:13.488130 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3638 01:17:13.488702 [ANA_INIT] flow start
3639 01:17:13.491101 [ANA_INIT] PLL >>>>>>>>
3640 01:17:13.494329 [ANA_INIT] PLL <<<<<<<<
3641 01:17:13.494894 [ANA_INIT] MIDPI >>>>>>>>
3642 01:17:13.497809 [ANA_INIT] MIDPI <<<<<<<<
3643 01:17:13.501053 [ANA_INIT] DLL >>>>>>>>
3644 01:17:13.501615 [ANA_INIT] flow end
3645 01:17:13.507352 ============ LP4 DIFF to SE enter ============
3646 01:17:13.510962 ============ LP4 DIFF to SE exit ============
3647 01:17:13.514203 [ANA_INIT] <<<<<<<<<<<<<
3648 01:17:13.517886 [Flow] Enable top DCM control >>>>>
3649 01:17:13.520838 [Flow] Enable top DCM control <<<<<
3650 01:17:13.521402 Enable DLL master slave shuffle
3651 01:17:13.527335 ==============================================================
3652 01:17:13.530895 Gating Mode config
3653 01:17:13.533829 ==============================================================
3654 01:17:13.537159 Config description:
3655 01:17:13.546903 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3656 01:17:13.553943 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3657 01:17:13.556868 SELPH_MODE 0: By rank 1: By Phase
3658 01:17:13.563826 ==============================================================
3659 01:17:13.566787 GAT_TRACK_EN = 1
3660 01:17:13.570221 RX_GATING_MODE = 2
3661 01:17:13.573281 RX_GATING_TRACK_MODE = 2
3662 01:17:13.576837 SELPH_MODE = 1
3663 01:17:13.579878 PICG_EARLY_EN = 1
3664 01:17:13.583492 VALID_LAT_VALUE = 1
3665 01:17:13.586613 ==============================================================
3666 01:17:13.590268 Enter into Gating configuration >>>>
3667 01:17:13.592936 Exit from Gating configuration <<<<
3668 01:17:13.596468 Enter into DVFS_PRE_config >>>>>
3669 01:17:13.609591 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3670 01:17:13.610228 Exit from DVFS_PRE_config <<<<<
3671 01:17:13.612852 Enter into PICG configuration >>>>
3672 01:17:13.616156 Exit from PICG configuration <<<<
3673 01:17:13.619731 [RX_INPUT] configuration >>>>>
3674 01:17:13.622504 [RX_INPUT] configuration <<<<<
3675 01:17:13.628990 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3676 01:17:13.632441 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3677 01:17:13.639140 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3678 01:17:13.646192 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3679 01:17:13.652607 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3680 01:17:13.658877 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3681 01:17:13.662221 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3682 01:17:13.666197 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3683 01:17:13.668933 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3684 01:17:13.675553 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3685 01:17:13.678940 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3686 01:17:13.682578 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3687 01:17:13.685839 ===================================
3688 01:17:13.688794 LPDDR4 DRAM CONFIGURATION
3689 01:17:13.692523 ===================================
3690 01:17:13.695637 EX_ROW_EN[0] = 0x0
3691 01:17:13.696101 EX_ROW_EN[1] = 0x0
3692 01:17:13.698783 LP4Y_EN = 0x0
3693 01:17:13.699250 WORK_FSP = 0x0
3694 01:17:13.702167 WL = 0x2
3695 01:17:13.702738 RL = 0x2
3696 01:17:13.705085 BL = 0x2
3697 01:17:13.705549 RPST = 0x0
3698 01:17:13.708833 RD_PRE = 0x0
3699 01:17:13.709403 WR_PRE = 0x1
3700 01:17:13.711917 WR_PST = 0x0
3701 01:17:13.712382 DBI_WR = 0x0
3702 01:17:13.715650 DBI_RD = 0x0
3703 01:17:13.716217 OTF = 0x1
3704 01:17:13.718873 ===================================
3705 01:17:13.725238 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3706 01:17:13.728432 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3707 01:17:13.732049 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3708 01:17:13.734956 ===================================
3709 01:17:13.738476 LPDDR4 DRAM CONFIGURATION
3710 01:17:13.741605 ===================================
3711 01:17:13.745054 EX_ROW_EN[0] = 0x10
3712 01:17:13.745608 EX_ROW_EN[1] = 0x0
3713 01:17:13.748102 LP4Y_EN = 0x0
3714 01:17:13.748563 WORK_FSP = 0x0
3715 01:17:13.751746 WL = 0x2
3716 01:17:13.752314 RL = 0x2
3717 01:17:13.754708 BL = 0x2
3718 01:17:13.755232 RPST = 0x0
3719 01:17:13.757982 RD_PRE = 0x0
3720 01:17:13.758565 WR_PRE = 0x1
3721 01:17:13.761969 WR_PST = 0x0
3722 01:17:13.762585 DBI_WR = 0x0
3723 01:17:13.764551 DBI_RD = 0x0
3724 01:17:13.768377 OTF = 0x1
3725 01:17:13.771222 ===================================
3726 01:17:13.774723 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3727 01:17:13.779814 nWR fixed to 30
3728 01:17:13.783448 [ModeRegInit_LP4] CH0 RK0
3729 01:17:13.784018 [ModeRegInit_LP4] CH0 RK1
3730 01:17:13.786146 [ModeRegInit_LP4] CH1 RK0
3731 01:17:13.789596 [ModeRegInit_LP4] CH1 RK1
3732 01:17:13.790211 match AC timing 16
3733 01:17:13.796044 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3734 01:17:13.799318 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3735 01:17:13.802937 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3736 01:17:13.809685 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3737 01:17:13.812714 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3738 01:17:13.813192 ==
3739 01:17:13.815892 Dram Type= 6, Freq= 0, CH_0, rank 0
3740 01:17:13.819453 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3741 01:17:13.820033 ==
3742 01:17:13.826238 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3743 01:17:13.832678 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3744 01:17:13.835851 [CA 0] Center 35 (5~66) winsize 62
3745 01:17:13.839199 [CA 1] Center 35 (5~66) winsize 62
3746 01:17:13.842418 [CA 2] Center 34 (4~65) winsize 62
3747 01:17:13.845911 [CA 3] Center 34 (4~65) winsize 62
3748 01:17:13.849269 [CA 4] Center 33 (3~64) winsize 62
3749 01:17:13.852549 [CA 5] Center 33 (3~64) winsize 62
3750 01:17:13.853116
3751 01:17:13.856032 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3752 01:17:13.856605
3753 01:17:13.858982 [CATrainingPosCal] consider 1 rank data
3754 01:17:13.862656 u2DelayCellTimex100 = 270/100 ps
3755 01:17:13.865964 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3756 01:17:13.869432 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3757 01:17:13.872155 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3758 01:17:13.875988 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3759 01:17:13.882205 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3760 01:17:13.885118 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3761 01:17:13.885611
3762 01:17:13.888867 CA PerBit enable=1, Macro0, CA PI delay=33
3763 01:17:13.889429
3764 01:17:13.892245 [CBTSetCACLKResult] CA Dly = 33
3765 01:17:13.892917 CS Dly: 6 (0~37)
3766 01:17:13.893298 ==
3767 01:17:13.895415 Dram Type= 6, Freq= 0, CH_0, rank 1
3768 01:17:13.902074 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3769 01:17:13.902644 ==
3770 01:17:13.905470 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3771 01:17:13.911854 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3772 01:17:13.915076 [CA 0] Center 35 (5~66) winsize 62
3773 01:17:13.918243 [CA 1] Center 35 (5~66) winsize 62
3774 01:17:13.922120 [CA 2] Center 34 (4~65) winsize 62
3775 01:17:13.925075 [CA 3] Center 34 (3~65) winsize 63
3776 01:17:13.928327 [CA 4] Center 33 (3~64) winsize 62
3777 01:17:13.931641 [CA 5] Center 33 (3~64) winsize 62
3778 01:17:13.932102
3779 01:17:13.934730 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3780 01:17:13.935214
3781 01:17:13.938283 [CATrainingPosCal] consider 2 rank data
3782 01:17:13.941386 u2DelayCellTimex100 = 270/100 ps
3783 01:17:13.944952 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3784 01:17:13.948407 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3785 01:17:13.954737 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3786 01:17:13.958193 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3787 01:17:13.961443 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3788 01:17:13.965066 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3789 01:17:13.965626
3790 01:17:13.968300 CA PerBit enable=1, Macro0, CA PI delay=33
3791 01:17:13.968860
3792 01:17:13.971413 [CBTSetCACLKResult] CA Dly = 33
3793 01:17:13.971951 CS Dly: 5 (0~36)
3794 01:17:13.972322
3795 01:17:13.977830 ----->DramcWriteLeveling(PI) begin...
3796 01:17:13.978483 ==
3797 01:17:13.981666 Dram Type= 6, Freq= 0, CH_0, rank 0
3798 01:17:13.984437 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3799 01:17:13.984999 ==
3800 01:17:13.987706 Write leveling (Byte 0): 30 => 30
3801 01:17:13.991274 Write leveling (Byte 1): 29 => 29
3802 01:17:13.994254 DramcWriteLeveling(PI) end<-----
3803 01:17:13.994719
3804 01:17:13.995087 ==
3805 01:17:13.997683 Dram Type= 6, Freq= 0, CH_0, rank 0
3806 01:17:14.001334 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3807 01:17:14.001895 ==
3808 01:17:14.004340 [Gating] SW mode calibration
3809 01:17:14.010912 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3810 01:17:14.017587 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3811 01:17:14.020971 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3812 01:17:14.024092 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3813 01:17:14.030998 0 5 8 | B1->B0 | 3333 3030 | 1 1 | (1 0) (0 0)
3814 01:17:14.034145 0 5 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3815 01:17:14.037107 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3816 01:17:14.043799 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3817 01:17:14.047410 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3818 01:17:14.050363 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3819 01:17:14.057584 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3820 01:17:14.060583 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3821 01:17:14.063962 0 6 8 | B1->B0 | 2d2d 3333 | 0 0 | (0 0) (0 0)
3822 01:17:14.070566 0 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3823 01:17:14.073661 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3824 01:17:14.076774 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3825 01:17:14.083584 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3826 01:17:14.086893 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3827 01:17:14.090327 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3828 01:17:14.097043 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3829 01:17:14.100059 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3830 01:17:14.103449 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3831 01:17:14.110390 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3832 01:17:14.113469 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3833 01:17:14.117176 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3834 01:17:14.123749 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3835 01:17:14.126801 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3836 01:17:14.129861 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3837 01:17:14.133454 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3838 01:17:14.139860 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3839 01:17:14.142917 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3840 01:17:14.149963 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3841 01:17:14.153115 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3842 01:17:14.156362 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3843 01:17:14.159659 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3844 01:17:14.166568 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3845 01:17:14.169652 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3846 01:17:14.172957 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3847 01:17:14.176057 Total UI for P1: 0, mck2ui 16
3848 01:17:14.179623 best dqsien dly found for B0: ( 0, 9, 10)
3849 01:17:14.186218 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3850 01:17:14.189509 Total UI for P1: 0, mck2ui 16
3851 01:17:14.192803 best dqsien dly found for B1: ( 0, 9, 12)
3852 01:17:14.196141 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
3853 01:17:14.199374 best DQS1 dly(MCK, UI, PI) = (0, 9, 12)
3854 01:17:14.199939
3855 01:17:14.202674 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
3856 01:17:14.205927 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 12)
3857 01:17:14.209395 [Gating] SW calibration Done
3858 01:17:14.210008 ==
3859 01:17:14.212419 Dram Type= 6, Freq= 0, CH_0, rank 0
3860 01:17:14.216182 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3861 01:17:14.216749 ==
3862 01:17:14.219284 RX Vref Scan: 0
3863 01:17:14.219746
3864 01:17:14.222383 RX Vref 0 -> 0, step: 1
3865 01:17:14.222846
3866 01:17:14.223209 RX Delay -230 -> 252, step: 16
3867 01:17:14.229493 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3868 01:17:14.232619 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3869 01:17:14.236159 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3870 01:17:14.239178 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3871 01:17:14.245692 iDelay=218, Bit 4, Center 41 (-134 ~ 217) 352
3872 01:17:14.249085 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3873 01:17:14.252465 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3874 01:17:14.255808 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3875 01:17:14.262285 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3876 01:17:14.265511 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3877 01:17:14.268640 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3878 01:17:14.272147 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3879 01:17:14.278671 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3880 01:17:14.281959 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3881 01:17:14.285470 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3882 01:17:14.288658 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3883 01:17:14.289221 ==
3884 01:17:14.291945 Dram Type= 6, Freq= 0, CH_0, rank 0
3885 01:17:14.298659 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3886 01:17:14.299227 ==
3887 01:17:14.299596 DQS Delay:
3888 01:17:14.301483 DQS0 = 0, DQS1 = 0
3889 01:17:14.301943 DQM Delay:
3890 01:17:14.302431 DQM0 = 37, DQM1 = 33
3891 01:17:14.305109 DQ Delay:
3892 01:17:14.308273 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3893 01:17:14.311473 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
3894 01:17:14.314663 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3895 01:17:14.318471 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3896 01:17:14.318932
3897 01:17:14.319296
3898 01:17:14.319641 ==
3899 01:17:14.321126 Dram Type= 6, Freq= 0, CH_0, rank 0
3900 01:17:14.325114 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3901 01:17:14.325691 ==
3902 01:17:14.326099
3903 01:17:14.326449
3904 01:17:14.328062 TX Vref Scan disable
3905 01:17:14.331347 == TX Byte 0 ==
3906 01:17:14.334598 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3907 01:17:14.337728 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3908 01:17:14.341567 == TX Byte 1 ==
3909 01:17:14.345034 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3910 01:17:14.347839 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3911 01:17:14.348260 ==
3912 01:17:14.351256 Dram Type= 6, Freq= 0, CH_0, rank 0
3913 01:17:14.357698 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3914 01:17:14.358266 ==
3915 01:17:14.358610
3916 01:17:14.358922
3917 01:17:14.359217 TX Vref Scan disable
3918 01:17:14.361732 == TX Byte 0 ==
3919 01:17:14.364957 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3920 01:17:14.371778 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3921 01:17:14.372311 == TX Byte 1 ==
3922 01:17:14.375223 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3923 01:17:14.381468 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3924 01:17:14.381992
3925 01:17:14.382533 [DATLAT]
3926 01:17:14.382872 Freq=600, CH0 RK0
3927 01:17:14.383180
3928 01:17:14.385192 DATLAT Default: 0x9
3929 01:17:14.385746 0, 0xFFFF, sum = 0
3930 01:17:14.388477 1, 0xFFFF, sum = 0
3931 01:17:14.391525 2, 0xFFFF, sum = 0
3932 01:17:14.391950 3, 0xFFFF, sum = 0
3933 01:17:14.394804 4, 0xFFFF, sum = 0
3934 01:17:14.395330 5, 0xFFFF, sum = 0
3935 01:17:14.398179 6, 0xFFFF, sum = 0
3936 01:17:14.398701 7, 0x0, sum = 1
3937 01:17:14.401294 8, 0x0, sum = 2
3938 01:17:14.401717 9, 0x0, sum = 3
3939 01:17:14.402092 10, 0x0, sum = 4
3940 01:17:14.404283 best_step = 8
3941 01:17:14.404697
3942 01:17:14.405063 ==
3943 01:17:14.408204 Dram Type= 6, Freq= 0, CH_0, rank 0
3944 01:17:14.410908 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3945 01:17:14.411446 ==
3946 01:17:14.414362 RX Vref Scan: 1
3947 01:17:14.414776
3948 01:17:14.415107 RX Vref 0 -> 0, step: 1
3949 01:17:14.417813
3950 01:17:14.418373 RX Delay -195 -> 252, step: 8
3951 01:17:14.418712
3952 01:17:14.421055 Set Vref, RX VrefLevel [Byte0]: 46
3953 01:17:14.424621 [Byte1]: 51
3954 01:17:14.428770
3955 01:17:14.429287 Final RX Vref Byte 0 = 46 to rank0
3956 01:17:14.431918 Final RX Vref Byte 1 = 51 to rank0
3957 01:17:14.435337 Final RX Vref Byte 0 = 46 to rank1
3958 01:17:14.438810 Final RX Vref Byte 1 = 51 to rank1==
3959 01:17:14.441701 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 01:17:14.448692 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3961 01:17:14.449167 ==
3962 01:17:14.449666 DQS Delay:
3963 01:17:14.452069 DQS0 = 0, DQS1 = 0
3964 01:17:14.452592 DQM Delay:
3965 01:17:14.452925 DQM0 = 40, DQM1 = 30
3966 01:17:14.455003 DQ Delay:
3967 01:17:14.458138 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =36
3968 01:17:14.461766 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
3969 01:17:14.465150 DQ8 =20, DQ9 =12, DQ10 =32, DQ11 =20
3970 01:17:14.468460 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
3971 01:17:14.468990
3972 01:17:14.469326
3973 01:17:14.475077 [DQSOSCAuto] RK0, (LSB)MR18= 0x4949, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
3974 01:17:14.478167 CH0 RK0: MR19=808, MR18=4949
3975 01:17:14.484945 CH0_RK0: MR19=0x808, MR18=0x4949, DQSOSC=396, MR23=63, INC=167, DEC=111
3976 01:17:14.485366
3977 01:17:14.488343 ----->DramcWriteLeveling(PI) begin...
3978 01:17:14.488877 ==
3979 01:17:14.491695 Dram Type= 6, Freq= 0, CH_0, rank 1
3980 01:17:14.494614 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3981 01:17:14.495040 ==
3982 01:17:14.498121 Write leveling (Byte 0): 30 => 30
3983 01:17:14.501966 Write leveling (Byte 1): 28 => 28
3984 01:17:14.504791 DramcWriteLeveling(PI) end<-----
3985 01:17:14.505206
3986 01:17:14.505536 ==
3987 01:17:14.507998 Dram Type= 6, Freq= 0, CH_0, rank 1
3988 01:17:14.511530 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3989 01:17:14.512054 ==
3990 01:17:14.514621 [Gating] SW mode calibration
3991 01:17:14.521324 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3992 01:17:14.528219 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3993 01:17:14.531196 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3994 01:17:14.537647 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3995 01:17:14.541160 0 5 8 | B1->B0 | 3232 3030 | 1 1 | (1 0) (1 0)
3996 01:17:14.544096 0 5 12 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
3997 01:17:14.550922 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 01:17:14.554486 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 01:17:14.557736 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 01:17:14.563963 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 01:17:14.567759 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 01:17:14.571017 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 01:17:14.577349 0 6 8 | B1->B0 | 2828 3333 | 0 0 | (0 0) (0 0)
4004 01:17:14.580630 0 6 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
4005 01:17:14.584451 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 01:17:14.590815 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 01:17:14.593644 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 01:17:14.597126 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 01:17:14.603820 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 01:17:14.607288 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 01:17:14.610867 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4012 01:17:14.617367 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 01:17:14.620140 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 01:17:14.623785 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 01:17:14.630206 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 01:17:14.633823 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 01:17:14.636806 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 01:17:14.643646 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 01:17:14.646727 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 01:17:14.650426 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 01:17:14.656737 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 01:17:14.660013 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 01:17:14.663221 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 01:17:14.669761 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 01:17:14.673402 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 01:17:14.676540 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 01:17:14.683283 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 01:17:14.683717 Total UI for P1: 0, mck2ui 16
4029 01:17:14.690172 best dqsien dly found for B0: ( 0, 9, 6)
4030 01:17:14.690699 Total UI for P1: 0, mck2ui 16
4031 01:17:14.692968 best dqsien dly found for B1: ( 0, 9, 6)
4032 01:17:14.700123 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4033 01:17:14.703051 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4034 01:17:14.703470
4035 01:17:14.706118 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4036 01:17:14.709317 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4037 01:17:14.712992 [Gating] SW calibration Done
4038 01:17:14.713450 ==
4039 01:17:14.716116 Dram Type= 6, Freq= 0, CH_0, rank 1
4040 01:17:14.719515 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4041 01:17:14.720033 ==
4042 01:17:14.722787 RX Vref Scan: 0
4043 01:17:14.723306
4044 01:17:14.723639 RX Vref 0 -> 0, step: 1
4045 01:17:14.723949
4046 01:17:14.726208 RX Delay -230 -> 252, step: 16
4047 01:17:14.729485 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4048 01:17:14.735967 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4049 01:17:14.739247 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4050 01:17:14.742519 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4051 01:17:14.745817 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4052 01:17:14.752333 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4053 01:17:14.755654 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4054 01:17:14.759187 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4055 01:17:14.762551 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4056 01:17:14.765708 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4057 01:17:14.772498 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4058 01:17:14.775715 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4059 01:17:14.779139 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4060 01:17:14.782744 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4061 01:17:14.788793 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4062 01:17:14.792237 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4063 01:17:14.792659 ==
4064 01:17:14.795339 Dram Type= 6, Freq= 0, CH_0, rank 1
4065 01:17:14.798800 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4066 01:17:14.799220 ==
4067 01:17:14.801916 DQS Delay:
4068 01:17:14.802364 DQS0 = 0, DQS1 = 0
4069 01:17:14.805910 DQM Delay:
4070 01:17:14.806373 DQM0 = 41, DQM1 = 33
4071 01:17:14.806706 DQ Delay:
4072 01:17:14.808762 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4073 01:17:14.811734 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4074 01:17:14.815322 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4075 01:17:14.818433 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4076 01:17:14.818851
4077 01:17:14.819178
4078 01:17:14.822356 ==
4079 01:17:14.822773 Dram Type= 6, Freq= 0, CH_0, rank 1
4080 01:17:14.828893 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4081 01:17:14.829421 ==
4082 01:17:14.829759
4083 01:17:14.830106
4084 01:17:14.832038 TX Vref Scan disable
4085 01:17:14.832457 == TX Byte 0 ==
4086 01:17:14.838510 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4087 01:17:14.842092 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4088 01:17:14.842528 == TX Byte 1 ==
4089 01:17:14.848182 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4090 01:17:14.851594 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4091 01:17:14.852014 ==
4092 01:17:14.854727 Dram Type= 6, Freq= 0, CH_0, rank 1
4093 01:17:14.858474 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4094 01:17:14.859004 ==
4095 01:17:14.859390
4096 01:17:14.859712
4097 01:17:14.861319 TX Vref Scan disable
4098 01:17:14.865089 == TX Byte 0 ==
4099 01:17:14.868166 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4100 01:17:14.871337 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4101 01:17:14.875145 == TX Byte 1 ==
4102 01:17:14.878378 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4103 01:17:14.881507 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4104 01:17:14.882064
4105 01:17:14.884969 [DATLAT]
4106 01:17:14.885486 Freq=600, CH0 RK1
4107 01:17:14.885825
4108 01:17:14.887660 DATLAT Default: 0x8
4109 01:17:14.888075 0, 0xFFFF, sum = 0
4110 01:17:14.891088 1, 0xFFFF, sum = 0
4111 01:17:14.891511 2, 0xFFFF, sum = 0
4112 01:17:14.894682 3, 0xFFFF, sum = 0
4113 01:17:14.895267 4, 0xFFFF, sum = 0
4114 01:17:14.898196 5, 0xFFFF, sum = 0
4115 01:17:14.898718 6, 0xFFFF, sum = 0
4116 01:17:14.901002 7, 0x0, sum = 1
4117 01:17:14.901439 8, 0x0, sum = 2
4118 01:17:14.904335 9, 0x0, sum = 3
4119 01:17:14.904808 10, 0x0, sum = 4
4120 01:17:14.907925 best_step = 8
4121 01:17:14.908445
4122 01:17:14.908778 ==
4123 01:17:14.911001 Dram Type= 6, Freq= 0, CH_0, rank 1
4124 01:17:14.914776 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4125 01:17:14.915195 ==
4126 01:17:14.917907 RX Vref Scan: 0
4127 01:17:14.918477
4128 01:17:14.918814 RX Vref 0 -> 0, step: 1
4129 01:17:14.919121
4130 01:17:14.921058 RX Delay -195 -> 252, step: 8
4131 01:17:14.928175 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4132 01:17:14.930957 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4133 01:17:14.934531 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4134 01:17:14.937751 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4135 01:17:14.944641 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4136 01:17:14.947903 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4137 01:17:14.950922 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4138 01:17:14.954403 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4139 01:17:14.960722 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4140 01:17:14.964276 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4141 01:17:14.967128 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4142 01:17:14.970661 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4143 01:17:14.974187 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4144 01:17:14.980865 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4145 01:17:14.983978 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4146 01:17:14.987257 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4147 01:17:14.987678 ==
4148 01:17:14.990954 Dram Type= 6, Freq= 0, CH_0, rank 1
4149 01:17:14.997269 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4150 01:17:14.997794 ==
4151 01:17:14.998164 DQS Delay:
4152 01:17:15.000373 DQS0 = 0, DQS1 = 0
4153 01:17:15.000791 DQM Delay:
4154 01:17:15.001123 DQM0 = 41, DQM1 = 32
4155 01:17:15.003816 DQ Delay:
4156 01:17:15.007512 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4157 01:17:15.010427 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4158 01:17:15.013487 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4159 01:17:15.016932 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4160 01:17:15.017346
4161 01:17:15.017678
4162 01:17:15.024097 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c6c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4163 01:17:15.026955 CH0 RK1: MR19=808, MR18=6C6C
4164 01:17:15.033702 CH0_RK1: MR19=0x808, MR18=0x6C6C, DQSOSC=389, MR23=63, INC=173, DEC=115
4165 01:17:15.036935 [RxdqsGatingPostProcess] freq 600
4166 01:17:15.039960 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4167 01:17:15.043352 Pre-setting of DQS Precalculation
4168 01:17:15.050372 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4169 01:17:15.050894 ==
4170 01:17:15.053341 Dram Type= 6, Freq= 0, CH_1, rank 0
4171 01:17:15.057123 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4172 01:17:15.057663 ==
4173 01:17:15.063546 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4174 01:17:15.070007 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4175 01:17:15.072939 [CA 0] Center 35 (5~66) winsize 62
4176 01:17:15.076622 [CA 1] Center 35 (5~66) winsize 62
4177 01:17:15.080142 [CA 2] Center 33 (3~64) winsize 62
4178 01:17:15.082969 [CA 3] Center 33 (3~64) winsize 62
4179 01:17:15.086374 [CA 4] Center 33 (2~64) winsize 63
4180 01:17:15.090011 [CA 5] Center 33 (2~64) winsize 63
4181 01:17:15.090575
4182 01:17:15.093143 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4183 01:17:15.093661
4184 01:17:15.096154 [CATrainingPosCal] consider 1 rank data
4185 01:17:15.099894 u2DelayCellTimex100 = 270/100 ps
4186 01:17:15.103051 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4187 01:17:15.106010 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4188 01:17:15.109618 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4189 01:17:15.112675 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4190 01:17:15.116736 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4191 01:17:15.120108 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4192 01:17:15.120631
4193 01:17:15.126180 CA PerBit enable=1, Macro0, CA PI delay=33
4194 01:17:15.126700
4195 01:17:15.127031 [CBTSetCACLKResult] CA Dly = 33
4196 01:17:15.129551 CS Dly: 4 (0~35)
4197 01:17:15.130112 ==
4198 01:17:15.133146 Dram Type= 6, Freq= 0, CH_1, rank 1
4199 01:17:15.136074 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4200 01:17:15.136499 ==
4201 01:17:15.142786 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4202 01:17:15.149063 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4203 01:17:15.152935 [CA 0] Center 35 (5~66) winsize 62
4204 01:17:15.155745 [CA 1] Center 34 (4~65) winsize 62
4205 01:17:15.158971 [CA 2] Center 33 (3~64) winsize 62
4206 01:17:15.162742 [CA 3] Center 33 (3~64) winsize 62
4207 01:17:15.166264 [CA 4] Center 33 (2~64) winsize 63
4208 01:17:15.169397 [CA 5] Center 33 (2~64) winsize 63
4209 01:17:15.169812
4210 01:17:15.172467 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4211 01:17:15.172982
4212 01:17:15.175717 [CATrainingPosCal] consider 2 rank data
4213 01:17:15.178917 u2DelayCellTimex100 = 270/100 ps
4214 01:17:15.182387 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4215 01:17:15.185758 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4216 01:17:15.189050 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4217 01:17:15.192604 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4218 01:17:15.195381 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4219 01:17:15.202204 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4220 01:17:15.202732
4221 01:17:15.205536 CA PerBit enable=1, Macro0, CA PI delay=33
4222 01:17:15.205955
4223 01:17:15.208941 [CBTSetCACLKResult] CA Dly = 33
4224 01:17:15.209460 CS Dly: 4 (0~36)
4225 01:17:15.209793
4226 01:17:15.211968 ----->DramcWriteLeveling(PI) begin...
4227 01:17:15.212494 ==
4228 01:17:15.215851 Dram Type= 6, Freq= 0, CH_1, rank 0
4229 01:17:15.222272 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4230 01:17:15.222804 ==
4231 01:17:15.225401 Write leveling (Byte 0): 27 => 27
4232 01:17:15.225922 Write leveling (Byte 1): 27 => 27
4233 01:17:15.228698 DramcWriteLeveling(PI) end<-----
4234 01:17:15.229218
4235 01:17:15.232179 ==
4236 01:17:15.232700 Dram Type= 6, Freq= 0, CH_1, rank 0
4237 01:17:15.238429 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4238 01:17:15.238853 ==
4239 01:17:15.241819 [Gating] SW mode calibration
4240 01:17:15.248386 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4241 01:17:15.251899 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4242 01:17:15.258279 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4243 01:17:15.261749 0 5 4 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
4244 01:17:15.264994 0 5 8 | B1->B0 | 3333 2626 | 1 1 | (1 0) (0 0)
4245 01:17:15.271532 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4246 01:17:15.275293 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4247 01:17:15.278296 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 01:17:15.284893 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 01:17:15.288159 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 01:17:15.291502 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 01:17:15.298399 0 6 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
4252 01:17:15.301643 0 6 8 | B1->B0 | 3333 3f3f | 0 0 | (0 0) (0 0)
4253 01:17:15.304671 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 01:17:15.311708 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 01:17:15.314696 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 01:17:15.318100 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 01:17:15.325148 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 01:17:15.328432 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 01:17:15.330890 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 01:17:15.337865 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4261 01:17:15.341083 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4262 01:17:15.344094 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 01:17:15.350888 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 01:17:15.354202 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 01:17:15.357609 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 01:17:15.364222 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 01:17:15.367785 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 01:17:15.370678 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 01:17:15.378175 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 01:17:15.380656 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 01:17:15.383728 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 01:17:15.390724 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 01:17:15.393866 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 01:17:15.397008 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 01:17:15.403496 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4276 01:17:15.406771 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4277 01:17:15.410678 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4278 01:17:15.413606 Total UI for P1: 0, mck2ui 16
4279 01:17:15.417093 best dqsien dly found for B0: ( 0, 9, 6)
4280 01:17:15.420244 Total UI for P1: 0, mck2ui 16
4281 01:17:15.424271 best dqsien dly found for B1: ( 0, 9, 10)
4282 01:17:15.426664 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4283 01:17:15.430147 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4284 01:17:15.430664
4285 01:17:15.433306 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4286 01:17:15.439750 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4287 01:17:15.440260 [Gating] SW calibration Done
4288 01:17:15.440598 ==
4289 01:17:15.443540 Dram Type= 6, Freq= 0, CH_1, rank 0
4290 01:17:15.450277 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4291 01:17:15.450815 ==
4292 01:17:15.451154 RX Vref Scan: 0
4293 01:17:15.451465
4294 01:17:15.453279 RX Vref 0 -> 0, step: 1
4295 01:17:15.453689
4296 01:17:15.456472 RX Delay -230 -> 252, step: 16
4297 01:17:15.459514 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4298 01:17:15.463051 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4299 01:17:15.469548 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4300 01:17:15.472932 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4301 01:17:15.476535 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4302 01:17:15.479944 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4303 01:17:15.482992 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4304 01:17:15.489437 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4305 01:17:15.492549 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4306 01:17:15.496216 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4307 01:17:15.499444 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4308 01:17:15.505943 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4309 01:17:15.509195 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4310 01:17:15.512630 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4311 01:17:15.515985 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4312 01:17:15.522361 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4313 01:17:15.522926 ==
4314 01:17:15.525429 Dram Type= 6, Freq= 0, CH_1, rank 0
4315 01:17:15.529529 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4316 01:17:15.530153 ==
4317 01:17:15.530535 DQS Delay:
4318 01:17:15.532340 DQS0 = 0, DQS1 = 0
4319 01:17:15.532801 DQM Delay:
4320 01:17:15.536065 DQM0 = 38, DQM1 = 32
4321 01:17:15.536628 DQ Delay:
4322 01:17:15.539049 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4323 01:17:15.542441 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4324 01:17:15.545751 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4325 01:17:15.548756 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4326 01:17:15.549222
4327 01:17:15.549587
4328 01:17:15.549926 ==
4329 01:17:15.552172 Dram Type= 6, Freq= 0, CH_1, rank 0
4330 01:17:15.555191 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4331 01:17:15.558706 ==
4332 01:17:15.559165
4333 01:17:15.559537
4334 01:17:15.559897 TX Vref Scan disable
4335 01:17:15.561997 == TX Byte 0 ==
4336 01:17:15.565439 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4337 01:17:15.571913 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4338 01:17:15.572479 == TX Byte 1 ==
4339 01:17:15.575582 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4340 01:17:15.581877 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4341 01:17:15.582482 ==
4342 01:17:15.585363 Dram Type= 6, Freq= 0, CH_1, rank 0
4343 01:17:15.588466 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4344 01:17:15.589035 ==
4345 01:17:15.589404
4346 01:17:15.589743
4347 01:17:15.591529 TX Vref Scan disable
4348 01:17:15.594923 == TX Byte 0 ==
4349 01:17:15.598643 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4350 01:17:15.601761 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4351 01:17:15.605155 == TX Byte 1 ==
4352 01:17:15.608395 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4353 01:17:15.611659 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4354 01:17:15.612123
4355 01:17:15.612484 [DATLAT]
4356 01:17:15.614630 Freq=600, CH1 RK0
4357 01:17:15.615093
4358 01:17:15.618104 DATLAT Default: 0x9
4359 01:17:15.618691 0, 0xFFFF, sum = 0
4360 01:17:15.621760 1, 0xFFFF, sum = 0
4361 01:17:15.622391 2, 0xFFFF, sum = 0
4362 01:17:15.624977 3, 0xFFFF, sum = 0
4363 01:17:15.625548 4, 0xFFFF, sum = 0
4364 01:17:15.628218 5, 0xFFFF, sum = 0
4365 01:17:15.628786 6, 0xFFFF, sum = 0
4366 01:17:15.631541 7, 0x0, sum = 1
4367 01:17:15.632011 8, 0x0, sum = 2
4368 01:17:15.634625 9, 0x0, sum = 3
4369 01:17:15.635095 10, 0x0, sum = 4
4370 01:17:15.635470 best_step = 8
4371 01:17:15.635818
4372 01:17:15.638184 ==
4373 01:17:15.641404 Dram Type= 6, Freq= 0, CH_1, rank 0
4374 01:17:15.644311 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4375 01:17:15.644781 ==
4376 01:17:15.645153 RX Vref Scan: 1
4377 01:17:15.645498
4378 01:17:15.647638 RX Vref 0 -> 0, step: 1
4379 01:17:15.648104
4380 01:17:15.651161 RX Delay -195 -> 252, step: 8
4381 01:17:15.651646
4382 01:17:15.654387 Set Vref, RX VrefLevel [Byte0]: 56
4383 01:17:15.658184 [Byte1]: 51
4384 01:17:15.658753
4385 01:17:15.661144 Final RX Vref Byte 0 = 56 to rank0
4386 01:17:15.664439 Final RX Vref Byte 1 = 51 to rank0
4387 01:17:15.667554 Final RX Vref Byte 0 = 56 to rank1
4388 01:17:15.671054 Final RX Vref Byte 1 = 51 to rank1==
4389 01:17:15.674152 Dram Type= 6, Freq= 0, CH_1, rank 0
4390 01:17:15.677593 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4391 01:17:15.680873 ==
4392 01:17:15.681430 DQS Delay:
4393 01:17:15.681803 DQS0 = 0, DQS1 = 0
4394 01:17:15.684034 DQM Delay:
4395 01:17:15.684492 DQM0 = 37, DQM1 = 30
4396 01:17:15.687453 DQ Delay:
4397 01:17:15.691165 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4398 01:17:15.691628 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4399 01:17:15.694426 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4400 01:17:15.697571 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4401 01:17:15.700643
4402 01:17:15.701197
4403 01:17:15.707399 [DQSOSCAuto] RK0, (LSB)MR18= 0x7878, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
4404 01:17:15.710856 CH1 RK0: MR19=808, MR18=7878
4405 01:17:15.717518 CH1_RK0: MR19=0x808, MR18=0x7878, DQSOSC=387, MR23=63, INC=175, DEC=116
4406 01:17:15.718139
4407 01:17:15.720679 ----->DramcWriteLeveling(PI) begin...
4408 01:17:15.721147 ==
4409 01:17:15.723708 Dram Type= 6, Freq= 0, CH_1, rank 1
4410 01:17:15.727174 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4411 01:17:15.727743 ==
4412 01:17:15.730704 Write leveling (Byte 0): 27 => 27
4413 01:17:15.734014 Write leveling (Byte 1): 26 => 26
4414 01:17:15.736823 DramcWriteLeveling(PI) end<-----
4415 01:17:15.737283
4416 01:17:15.737647 ==
4417 01:17:15.739998 Dram Type= 6, Freq= 0, CH_1, rank 1
4418 01:17:15.743518 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4419 01:17:15.744248 ==
4420 01:17:15.746882 [Gating] SW mode calibration
4421 01:17:15.753666 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4422 01:17:15.759958 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4423 01:17:15.763362 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4424 01:17:15.770375 0 5 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4425 01:17:15.773052 0 5 8 | B1->B0 | 3030 2424 | 0 0 | (0 0) (0 0)
4426 01:17:15.776800 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 01:17:15.783432 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 01:17:15.786481 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 01:17:15.789907 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 01:17:15.796283 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 01:17:15.799861 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 01:17:15.803323 0 6 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
4433 01:17:15.809977 0 6 8 | B1->B0 | 3131 4242 | 0 1 | (1 1) (0 0)
4434 01:17:15.812924 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 01:17:15.816832 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 01:17:15.822780 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 01:17:15.826075 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 01:17:15.829972 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 01:17:15.836136 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 01:17:15.839403 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 01:17:15.842882 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4442 01:17:15.849397 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 01:17:15.852623 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 01:17:15.855687 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 01:17:15.862501 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 01:17:15.865841 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 01:17:15.868869 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 01:17:15.875540 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 01:17:15.878734 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 01:17:15.882219 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 01:17:15.888783 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 01:17:15.892410 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 01:17:15.895456 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 01:17:15.902262 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 01:17:15.905842 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 01:17:15.908537 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4457 01:17:15.912035 Total UI for P1: 0, mck2ui 16
4458 01:17:15.915885 best dqsien dly found for B0: ( 0, 9, 2)
4459 01:17:15.918332 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4460 01:17:15.925108 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 01:17:15.928616 Total UI for P1: 0, mck2ui 16
4462 01:17:15.931953 best dqsien dly found for B1: ( 0, 9, 6)
4463 01:17:15.934895 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4464 01:17:15.938613 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4465 01:17:15.939178
4466 01:17:15.941560 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4467 01:17:15.944999 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4468 01:17:15.948682 [Gating] SW calibration Done
4469 01:17:15.949250 ==
4470 01:17:15.951449 Dram Type= 6, Freq= 0, CH_1, rank 1
4471 01:17:15.955065 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4472 01:17:15.955627 ==
4473 01:17:15.958342 RX Vref Scan: 0
4474 01:17:15.958803
4475 01:17:15.961920 RX Vref 0 -> 0, step: 1
4476 01:17:15.962517
4477 01:17:15.962889 RX Delay -230 -> 252, step: 16
4478 01:17:15.968694 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4479 01:17:15.971573 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4480 01:17:15.974757 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4481 01:17:15.977722 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4482 01:17:15.984835 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4483 01:17:15.988046 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4484 01:17:15.991602 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4485 01:17:15.994706 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4486 01:17:15.998075 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4487 01:17:16.004443 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4488 01:17:16.007963 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4489 01:17:16.011269 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4490 01:17:16.014701 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4491 01:17:16.021288 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4492 01:17:16.024327 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4493 01:17:16.028109 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4494 01:17:16.028667 ==
4495 01:17:16.031360 Dram Type= 6, Freq= 0, CH_1, rank 1
4496 01:17:16.037443 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4497 01:17:16.038002 ==
4498 01:17:16.038422 DQS Delay:
4499 01:17:16.038767 DQS0 = 0, DQS1 = 0
4500 01:17:16.040808 DQM Delay:
4501 01:17:16.041365 DQM0 = 41, DQM1 = 36
4502 01:17:16.043866 DQ Delay:
4503 01:17:16.047126 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4504 01:17:16.050694 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4505 01:17:16.053837 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4506 01:17:16.057475 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4507 01:17:16.058089
4508 01:17:16.058474
4509 01:17:16.058818 ==
4510 01:17:16.060618 Dram Type= 6, Freq= 0, CH_1, rank 1
4511 01:17:16.063895 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4512 01:17:16.064456 ==
4513 01:17:16.064829
4514 01:17:16.065174
4515 01:17:16.066901 TX Vref Scan disable
4516 01:17:16.070637 == TX Byte 0 ==
4517 01:17:16.073583 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4518 01:17:16.077046 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4519 01:17:16.080263 == TX Byte 1 ==
4520 01:17:16.083657 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4521 01:17:16.086677 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4522 01:17:16.087233 ==
4523 01:17:16.090069 Dram Type= 6, Freq= 0, CH_1, rank 1
4524 01:17:16.093505 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4525 01:17:16.096728 ==
4526 01:17:16.097284
4527 01:17:16.097650
4528 01:17:16.098005 TX Vref Scan disable
4529 01:17:16.100682 == TX Byte 0 ==
4530 01:17:16.103717 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4531 01:17:16.110736 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4532 01:17:16.111290 == TX Byte 1 ==
4533 01:17:16.113932 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4534 01:17:16.120580 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4535 01:17:16.121135
4536 01:17:16.121571 [DATLAT]
4537 01:17:16.121920 Freq=600, CH1 RK1
4538 01:17:16.122315
4539 01:17:16.123336 DATLAT Default: 0x8
4540 01:17:16.127107 0, 0xFFFF, sum = 0
4541 01:17:16.127674 1, 0xFFFF, sum = 0
4542 01:17:16.130221 2, 0xFFFF, sum = 0
4543 01:17:16.130788 3, 0xFFFF, sum = 0
4544 01:17:16.133619 4, 0xFFFF, sum = 0
4545 01:17:16.134234 5, 0xFFFF, sum = 0
4546 01:17:16.136819 6, 0xFFFF, sum = 0
4547 01:17:16.137284 7, 0x0, sum = 1
4548 01:17:16.140005 8, 0x0, sum = 2
4549 01:17:16.140507 9, 0x0, sum = 3
4550 01:17:16.140882 10, 0x0, sum = 4
4551 01:17:16.143388 best_step = 8
4552 01:17:16.143854
4553 01:17:16.144223 ==
4554 01:17:16.146553 Dram Type= 6, Freq= 0, CH_1, rank 1
4555 01:17:16.149744 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4556 01:17:16.150258 ==
4557 01:17:16.153104 RX Vref Scan: 0
4558 01:17:16.153569
4559 01:17:16.153934 RX Vref 0 -> 0, step: 1
4560 01:17:16.156772
4561 01:17:16.157336 RX Delay -195 -> 252, step: 8
4562 01:17:16.163854 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4563 01:17:16.167315 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4564 01:17:16.170572 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4565 01:17:16.174112 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4566 01:17:16.181204 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4567 01:17:16.183954 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4568 01:17:16.187130 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4569 01:17:16.190251 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4570 01:17:16.197253 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4571 01:17:16.200386 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4572 01:17:16.203609 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4573 01:17:16.206901 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4574 01:17:16.213913 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4575 01:17:16.216888 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4576 01:17:16.220448 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4577 01:17:16.223619 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4578 01:17:16.224083 ==
4579 01:17:16.227254 Dram Type= 6, Freq= 0, CH_1, rank 1
4580 01:17:16.233506 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4581 01:17:16.234123 ==
4582 01:17:16.234506 DQS Delay:
4583 01:17:16.237039 DQS0 = 0, DQS1 = 0
4584 01:17:16.237604 DQM Delay:
4585 01:17:16.237977 DQM0 = 37, DQM1 = 29
4586 01:17:16.239939 DQ Delay:
4587 01:17:16.243182 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4588 01:17:16.246695 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4589 01:17:16.249974 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4590 01:17:16.253113 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4591 01:17:16.253571
4592 01:17:16.253931
4593 01:17:16.259498 [DQSOSCAuto] RK1, (LSB)MR18= 0x5b5b, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4594 01:17:16.263035 CH1 RK1: MR19=808, MR18=5B5B
4595 01:17:16.269750 CH1_RK1: MR19=0x808, MR18=0x5B5B, DQSOSC=392, MR23=63, INC=170, DEC=113
4596 01:17:16.273149 [RxdqsGatingPostProcess] freq 600
4597 01:17:16.279729 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4598 01:17:16.280278 Pre-setting of DQS Precalculation
4599 01:17:16.286261 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4600 01:17:16.292809 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4601 01:17:16.299292 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4602 01:17:16.299843
4603 01:17:16.300211
4604 01:17:16.302846 [Calibration Summary] 1200 Mbps
4605 01:17:16.306291 CH 0, Rank 0
4606 01:17:16.306859 SW Impedance : PASS
4607 01:17:16.308965 DUTY Scan : NO K
4608 01:17:16.312564 ZQ Calibration : PASS
4609 01:17:16.313133 Jitter Meter : NO K
4610 01:17:16.315624 CBT Training : PASS
4611 01:17:16.316087 Write leveling : PASS
4612 01:17:16.319026 RX DQS gating : PASS
4613 01:17:16.322558 RX DQ/DQS(RDDQC) : PASS
4614 01:17:16.323157 TX DQ/DQS : PASS
4615 01:17:16.325902 RX DATLAT : PASS
4616 01:17:16.329059 RX DQ/DQS(Engine): PASS
4617 01:17:16.329624 TX OE : NO K
4618 01:17:16.332448 All Pass.
4619 01:17:16.333011
4620 01:17:16.333383 CH 0, Rank 1
4621 01:17:16.335418 SW Impedance : PASS
4622 01:17:16.335899 DUTY Scan : NO K
4623 01:17:16.338572 ZQ Calibration : PASS
4624 01:17:16.341981 Jitter Meter : NO K
4625 01:17:16.342491 CBT Training : PASS
4626 01:17:16.345508 Write leveling : PASS
4627 01:17:16.348617 RX DQS gating : PASS
4628 01:17:16.349086 RX DQ/DQS(RDDQC) : PASS
4629 01:17:16.352508 TX DQ/DQS : PASS
4630 01:17:16.355146 RX DATLAT : PASS
4631 01:17:16.355613 RX DQ/DQS(Engine): PASS
4632 01:17:16.358550 TX OE : NO K
4633 01:17:16.359019 All Pass.
4634 01:17:16.359485
4635 01:17:16.361910 CH 1, Rank 0
4636 01:17:16.362434 SW Impedance : PASS
4637 01:17:16.364918 DUTY Scan : NO K
4638 01:17:16.368850 ZQ Calibration : PASS
4639 01:17:16.369374 Jitter Meter : NO K
4640 01:17:16.372364 CBT Training : PASS
4641 01:17:16.375034 Write leveling : PASS
4642 01:17:16.375455 RX DQS gating : PASS
4643 01:17:16.378144 RX DQ/DQS(RDDQC) : PASS
4644 01:17:16.381796 TX DQ/DQS : PASS
4645 01:17:16.382374 RX DATLAT : PASS
4646 01:17:16.385114 RX DQ/DQS(Engine): PASS
4647 01:17:16.385651 TX OE : NO K
4648 01:17:16.388469 All Pass.
4649 01:17:16.388889
4650 01:17:16.389223 CH 1, Rank 1
4651 01:17:16.391322 SW Impedance : PASS
4652 01:17:16.394683 DUTY Scan : NO K
4653 01:17:16.395105 ZQ Calibration : PASS
4654 01:17:16.398610 Jitter Meter : NO K
4655 01:17:16.399217 CBT Training : PASS
4656 01:17:16.401713 Write leveling : PASS
4657 01:17:16.405010 RX DQS gating : PASS
4658 01:17:16.405538 RX DQ/DQS(RDDQC) : PASS
4659 01:17:16.408107 TX DQ/DQS : PASS
4660 01:17:16.411261 RX DATLAT : PASS
4661 01:17:16.411788 RX DQ/DQS(Engine): PASS
4662 01:17:16.414622 TX OE : NO K
4663 01:17:16.415158 All Pass.
4664 01:17:16.415501
4665 01:17:16.417908 DramC Write-DBI off
4666 01:17:16.421153 PER_BANK_REFRESH: Hybrid Mode
4667 01:17:16.421670 TX_TRACKING: ON
4668 01:17:16.431431 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4669 01:17:16.434273 [FAST_K] Save calibration result to emmc
4670 01:17:16.437880 dramc_set_vcore_voltage set vcore to 662500
4671 01:17:16.440787 Read voltage for 933, 3
4672 01:17:16.441211 Vio18 = 0
4673 01:17:16.441548 Vcore = 662500
4674 01:17:16.444490 Vdram = 0
4675 01:17:16.445018 Vddq = 0
4676 01:17:16.445357 Vmddr = 0
4677 01:17:16.450806 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4678 01:17:16.454013 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4679 01:17:16.457805 MEM_TYPE=3, freq_sel=17
4680 01:17:16.461183 sv_algorithm_assistance_LP4_1600
4681 01:17:16.463939 ============ PULL DRAM RESETB DOWN ============
4682 01:17:16.470846 ========== PULL DRAM RESETB DOWN end =========
4683 01:17:16.474403 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4684 01:17:16.477453 ===================================
4685 01:17:16.481215 LPDDR4 DRAM CONFIGURATION
4686 01:17:16.484208 ===================================
4687 01:17:16.484777 EX_ROW_EN[0] = 0x0
4688 01:17:16.487258 EX_ROW_EN[1] = 0x0
4689 01:17:16.487679 LP4Y_EN = 0x0
4690 01:17:16.490603 WORK_FSP = 0x0
4691 01:17:16.491023 WL = 0x3
4692 01:17:16.494551 RL = 0x3
4693 01:17:16.495067 BL = 0x2
4694 01:17:16.497360 RPST = 0x0
4695 01:17:16.497871 RD_PRE = 0x0
4696 01:17:16.500562 WR_PRE = 0x1
4697 01:17:16.504091 WR_PST = 0x0
4698 01:17:16.504785 DBI_WR = 0x0
4699 01:17:16.507062 DBI_RD = 0x0
4700 01:17:16.507521 OTF = 0x1
4701 01:17:16.510653 ===================================
4702 01:17:16.514264 ===================================
4703 01:17:16.514818 ANA top config
4704 01:17:16.517522 ===================================
4705 01:17:16.520177 DLL_ASYNC_EN = 0
4706 01:17:16.523650 ALL_SLAVE_EN = 1
4707 01:17:16.526847 NEW_RANK_MODE = 1
4708 01:17:16.530396 DLL_IDLE_MODE = 1
4709 01:17:16.530859 LP45_APHY_COMB_EN = 1
4710 01:17:16.533648 TX_ODT_DIS = 1
4711 01:17:16.536622 NEW_8X_MODE = 1
4712 01:17:16.540090 ===================================
4713 01:17:16.543580 ===================================
4714 01:17:16.546871 data_rate = 1866
4715 01:17:16.550237 CKR = 1
4716 01:17:16.553887 DQ_P2S_RATIO = 8
4717 01:17:16.556842 ===================================
4718 01:17:16.557401 CA_P2S_RATIO = 8
4719 01:17:16.560015 DQ_CA_OPEN = 0
4720 01:17:16.563330 DQ_SEMI_OPEN = 0
4721 01:17:16.566582 CA_SEMI_OPEN = 0
4722 01:17:16.569933 CA_FULL_RATE = 0
4723 01:17:16.573389 DQ_CKDIV4_EN = 1
4724 01:17:16.573940 CA_CKDIV4_EN = 1
4725 01:17:16.576629 CA_PREDIV_EN = 0
4726 01:17:16.579913 PH8_DLY = 0
4727 01:17:16.582981 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4728 01:17:16.586844 DQ_AAMCK_DIV = 4
4729 01:17:16.589948 CA_AAMCK_DIV = 4
4730 01:17:16.590450 CA_ADMCK_DIV = 4
4731 01:17:16.593423 DQ_TRACK_CA_EN = 0
4732 01:17:16.596349 CA_PICK = 933
4733 01:17:16.599882 CA_MCKIO = 933
4734 01:17:16.603023 MCKIO_SEMI = 0
4735 01:17:16.606480 PLL_FREQ = 3732
4736 01:17:16.609535 DQ_UI_PI_RATIO = 32
4737 01:17:16.610125 CA_UI_PI_RATIO = 0
4738 01:17:16.612904 ===================================
4739 01:17:16.616229 ===================================
4740 01:17:16.619407 memory_type:LPDDR4
4741 01:17:16.622717 GP_NUM : 10
4742 01:17:16.623275 SRAM_EN : 1
4743 01:17:16.626721 MD32_EN : 0
4744 01:17:16.629469 ===================================
4745 01:17:16.633368 [ANA_INIT] >>>>>>>>>>>>>>
4746 01:17:16.636205 <<<<<< [CONFIGURE PHASE]: ANA_TX
4747 01:17:16.639428 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4748 01:17:16.642607 ===================================
4749 01:17:16.643072 data_rate = 1866,PCW = 0X8f00
4750 01:17:16.646248 ===================================
4751 01:17:16.649322 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4752 01:17:16.656251 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4753 01:17:16.662826 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4754 01:17:16.665804 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4755 01:17:16.669131 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4756 01:17:16.672452 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4757 01:17:16.675561 [ANA_INIT] flow start
4758 01:17:16.679024 [ANA_INIT] PLL >>>>>>>>
4759 01:17:16.679597 [ANA_INIT] PLL <<<<<<<<
4760 01:17:16.682283 [ANA_INIT] MIDPI >>>>>>>>
4761 01:17:16.685656 [ANA_INIT] MIDPI <<<<<<<<
4762 01:17:16.686271 [ANA_INIT] DLL >>>>>>>>
4763 01:17:16.688840 [ANA_INIT] flow end
4764 01:17:16.692215 ============ LP4 DIFF to SE enter ============
4765 01:17:16.695551 ============ LP4 DIFF to SE exit ============
4766 01:17:16.698743 [ANA_INIT] <<<<<<<<<<<<<
4767 01:17:16.701966 [Flow] Enable top DCM control >>>>>
4768 01:17:16.705592 [Flow] Enable top DCM control <<<<<
4769 01:17:16.708733 Enable DLL master slave shuffle
4770 01:17:16.715595 ==============================================================
4771 01:17:16.716156 Gating Mode config
4772 01:17:16.721693 ==============================================================
4773 01:17:16.725836 Config description:
4774 01:17:16.731729 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4775 01:17:16.738458 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4776 01:17:16.745158 SELPH_MODE 0: By rank 1: By Phase
4777 01:17:16.751918 ==============================================================
4778 01:17:16.752488 GAT_TRACK_EN = 1
4779 01:17:16.754724 RX_GATING_MODE = 2
4780 01:17:16.758511 RX_GATING_TRACK_MODE = 2
4781 01:17:16.761642 SELPH_MODE = 1
4782 01:17:16.764730 PICG_EARLY_EN = 1
4783 01:17:16.768065 VALID_LAT_VALUE = 1
4784 01:17:16.774733 ==============================================================
4785 01:17:16.778373 Enter into Gating configuration >>>>
4786 01:17:16.781616 Exit from Gating configuration <<<<
4787 01:17:16.784993 Enter into DVFS_PRE_config >>>>>
4788 01:17:16.794987 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4789 01:17:16.798199 Exit from DVFS_PRE_config <<<<<
4790 01:17:16.801149 Enter into PICG configuration >>>>
4791 01:17:16.804949 Exit from PICG configuration <<<<
4792 01:17:16.808383 [RX_INPUT] configuration >>>>>
4793 01:17:16.811338 [RX_INPUT] configuration <<<<<
4794 01:17:16.814844 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4795 01:17:16.821598 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4796 01:17:16.828021 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4797 01:17:16.830936 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4798 01:17:16.837501 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4799 01:17:16.844132 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4800 01:17:16.847386 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4801 01:17:16.854207 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4802 01:17:16.857774 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4803 01:17:16.860763 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4804 01:17:16.864029 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4805 01:17:16.870531 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4806 01:17:16.874172 ===================================
4807 01:17:16.874734 LPDDR4 DRAM CONFIGURATION
4808 01:17:16.877575 ===================================
4809 01:17:16.880540 EX_ROW_EN[0] = 0x0
4810 01:17:16.884002 EX_ROW_EN[1] = 0x0
4811 01:17:16.884571 LP4Y_EN = 0x0
4812 01:17:16.887079 WORK_FSP = 0x0
4813 01:17:16.887646 WL = 0x3
4814 01:17:16.890525 RL = 0x3
4815 01:17:16.890988 BL = 0x2
4816 01:17:16.893922 RPST = 0x0
4817 01:17:16.894525 RD_PRE = 0x0
4818 01:17:16.897045 WR_PRE = 0x1
4819 01:17:16.897631 WR_PST = 0x0
4820 01:17:16.900361 DBI_WR = 0x0
4821 01:17:16.900931 DBI_RD = 0x0
4822 01:17:16.903569 OTF = 0x1
4823 01:17:16.906943 ===================================
4824 01:17:16.910210 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4825 01:17:16.913573 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4826 01:17:16.920315 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4827 01:17:16.923527 ===================================
4828 01:17:16.923996 LPDDR4 DRAM CONFIGURATION
4829 01:17:16.926607 ===================================
4830 01:17:16.930464 EX_ROW_EN[0] = 0x10
4831 01:17:16.933475 EX_ROW_EN[1] = 0x0
4832 01:17:16.934095 LP4Y_EN = 0x0
4833 01:17:16.936549 WORK_FSP = 0x0
4834 01:17:16.937013 WL = 0x3
4835 01:17:16.940422 RL = 0x3
4836 01:17:16.941009 BL = 0x2
4837 01:17:16.943297 RPST = 0x0
4838 01:17:16.943868 RD_PRE = 0x0
4839 01:17:16.946519 WR_PRE = 0x1
4840 01:17:16.946994 WR_PST = 0x0
4841 01:17:16.950116 DBI_WR = 0x0
4842 01:17:16.950829 DBI_RD = 0x0
4843 01:17:16.953109 OTF = 0x1
4844 01:17:16.956565 ===================================
4845 01:17:16.962954 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4846 01:17:16.966533 nWR fixed to 30
4847 01:17:16.969757 [ModeRegInit_LP4] CH0 RK0
4848 01:17:16.970259 [ModeRegInit_LP4] CH0 RK1
4849 01:17:16.972935 [ModeRegInit_LP4] CH1 RK0
4850 01:17:16.976347 [ModeRegInit_LP4] CH1 RK1
4851 01:17:16.976760 match AC timing 8
4852 01:17:16.982864 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4853 01:17:16.986528 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4854 01:17:16.989581 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4855 01:17:16.996052 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4856 01:17:16.999498 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4857 01:17:16.999919 ==
4858 01:17:17.002951 Dram Type= 6, Freq= 0, CH_0, rank 0
4859 01:17:17.005911 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4860 01:17:17.006371 ==
4861 01:17:17.012866 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4862 01:17:17.019313 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4863 01:17:17.022624 [CA 0] Center 38 (8~69) winsize 62
4864 01:17:17.025883 [CA 1] Center 38 (8~69) winsize 62
4865 01:17:17.028954 [CA 2] Center 36 (6~67) winsize 62
4866 01:17:17.032527 [CA 3] Center 36 (6~66) winsize 61
4867 01:17:17.035979 [CA 4] Center 35 (5~65) winsize 61
4868 01:17:17.038975 [CA 5] Center 34 (4~65) winsize 62
4869 01:17:17.039395
4870 01:17:17.042230 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4871 01:17:17.042652
4872 01:17:17.045818 [CATrainingPosCal] consider 1 rank data
4873 01:17:17.048901 u2DelayCellTimex100 = 270/100 ps
4874 01:17:17.051898 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4875 01:17:17.055503 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4876 01:17:17.058824 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4877 01:17:17.062253 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4878 01:17:17.068703 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4879 01:17:17.072123 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4880 01:17:17.072689
4881 01:17:17.075283 CA PerBit enable=1, Macro0, CA PI delay=34
4882 01:17:17.075750
4883 01:17:17.078611 [CBTSetCACLKResult] CA Dly = 34
4884 01:17:17.079077 CS Dly: 7 (0~38)
4885 01:17:17.079447 ==
4886 01:17:17.082243 Dram Type= 6, Freq= 0, CH_0, rank 1
4887 01:17:17.088326 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4888 01:17:17.088944 ==
4889 01:17:17.091573 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4890 01:17:17.098342 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4891 01:17:17.101454 [CA 0] Center 38 (8~69) winsize 62
4892 01:17:17.104813 [CA 1] Center 38 (8~69) winsize 62
4893 01:17:17.108535 [CA 2] Center 36 (6~67) winsize 62
4894 01:17:17.111858 [CA 3] Center 35 (5~66) winsize 62
4895 01:17:17.115029 [CA 4] Center 34 (4~65) winsize 62
4896 01:17:17.118158 [CA 5] Center 34 (4~65) winsize 62
4897 01:17:17.118630
4898 01:17:17.121457 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4899 01:17:17.121926
4900 01:17:17.125158 [CATrainingPosCal] consider 2 rank data
4901 01:17:17.128100 u2DelayCellTimex100 = 270/100 ps
4902 01:17:17.131594 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4903 01:17:17.134732 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4904 01:17:17.138152 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4905 01:17:17.144653 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4906 01:17:17.148220 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4907 01:17:17.151337 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4908 01:17:17.151845
4909 01:17:17.154507 CA PerBit enable=1, Macro0, CA PI delay=34
4910 01:17:17.154930
4911 01:17:17.158344 [CBTSetCACLKResult] CA Dly = 34
4912 01:17:17.158767 CS Dly: 7 (0~38)
4913 01:17:17.159105
4914 01:17:17.161380 ----->DramcWriteLeveling(PI) begin...
4915 01:17:17.164881 ==
4916 01:17:17.168094 Dram Type= 6, Freq= 0, CH_0, rank 0
4917 01:17:17.171313 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4918 01:17:17.171741 ==
4919 01:17:17.174632 Write leveling (Byte 0): 30 => 30
4920 01:17:17.178270 Write leveling (Byte 1): 26 => 26
4921 01:17:17.181262 DramcWriteLeveling(PI) end<-----
4922 01:17:17.181775
4923 01:17:17.182190 ==
4924 01:17:17.184210 Dram Type= 6, Freq= 0, CH_0, rank 0
4925 01:17:17.187734 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4926 01:17:17.188271 ==
4927 01:17:17.190989 [Gating] SW mode calibration
4928 01:17:17.197565 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4929 01:17:17.204389 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4930 01:17:17.207585 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4931 01:17:17.210990 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4932 01:17:17.217405 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4933 01:17:17.221116 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4934 01:17:17.224728 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4935 01:17:17.231224 0 10 20 | B1->B0 | 3333 3030 | 0 0 | (0 0) (0 0)
4936 01:17:17.234566 0 10 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4937 01:17:17.237357 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4938 01:17:17.243936 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4939 01:17:17.247403 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4940 01:17:17.250788 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4941 01:17:17.257292 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4942 01:17:17.260671 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4943 01:17:17.263624 0 11 20 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
4944 01:17:17.270748 0 11 24 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
4945 01:17:17.273597 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4946 01:17:17.277092 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4947 01:17:17.280407 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4948 01:17:17.287000 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4949 01:17:17.290334 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4950 01:17:17.293868 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4951 01:17:17.300397 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4952 01:17:17.303491 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4953 01:17:17.307021 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4954 01:17:17.313764 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4955 01:17:17.316805 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4956 01:17:17.320158 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4957 01:17:17.326641 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4958 01:17:17.330116 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4959 01:17:17.333305 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4960 01:17:17.339938 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4961 01:17:17.343157 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4962 01:17:17.346419 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4963 01:17:17.353232 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4964 01:17:17.356586 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4965 01:17:17.359749 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4966 01:17:17.366511 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4967 01:17:17.370143 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4968 01:17:17.373292 Total UI for P1: 0, mck2ui 16
4969 01:17:17.376281 best dqsien dly found for B0: ( 0, 14, 18)
4970 01:17:17.379864 Total UI for P1: 0, mck2ui 16
4971 01:17:17.382976 best dqsien dly found for B1: ( 0, 14, 16)
4972 01:17:17.386321 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
4973 01:17:17.389595 best DQS1 dly(MCK, UI, PI) = (0, 14, 16)
4974 01:17:17.390099
4975 01:17:17.392928 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
4976 01:17:17.396022 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 16)
4977 01:17:17.399732 [Gating] SW calibration Done
4978 01:17:17.400311 ==
4979 01:17:17.402911 Dram Type= 6, Freq= 0, CH_0, rank 0
4980 01:17:17.410016 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4981 01:17:17.410627 ==
4982 01:17:17.410999 RX Vref Scan: 0
4983 01:17:17.411350
4984 01:17:17.412888 RX Vref 0 -> 0, step: 1
4985 01:17:17.413434
4986 01:17:17.415988 RX Delay -80 -> 252, step: 8
4987 01:17:17.419274 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4988 01:17:17.423119 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4989 01:17:17.426236 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
4990 01:17:17.429377 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
4991 01:17:17.435872 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4992 01:17:17.439086 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4993 01:17:17.442335 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
4994 01:17:17.446010 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
4995 01:17:17.448942 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
4996 01:17:17.455701 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
4997 01:17:17.459064 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
4998 01:17:17.462553 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
4999 01:17:17.465490 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5000 01:17:17.468903 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5001 01:17:17.475777 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5002 01:17:17.478892 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5003 01:17:17.479458 ==
5004 01:17:17.482003 Dram Type= 6, Freq= 0, CH_0, rank 0
5005 01:17:17.485587 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5006 01:17:17.486199 ==
5007 01:17:17.486580 DQS Delay:
5008 01:17:17.488680 DQS0 = 0, DQS1 = 0
5009 01:17:17.489248 DQM Delay:
5010 01:17:17.491810 DQM0 = 96, DQM1 = 87
5011 01:17:17.492275 DQ Delay:
5012 01:17:17.495385 DQ0 =91, DQ1 =95, DQ2 =95, DQ3 =87
5013 01:17:17.498416 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5014 01:17:17.501988 DQ8 =79, DQ9 =75, DQ10 =83, DQ11 =79
5015 01:17:17.505021 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5016 01:17:17.505581
5017 01:17:17.505951
5018 01:17:17.506370 ==
5019 01:17:17.508467 Dram Type= 6, Freq= 0, CH_0, rank 0
5020 01:17:17.514977 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5021 01:17:17.515550 ==
5022 01:17:17.515922
5023 01:17:17.516268
5024 01:17:17.516596 TX Vref Scan disable
5025 01:17:17.518420 == TX Byte 0 ==
5026 01:17:17.521518 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5027 01:17:17.527778 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5028 01:17:17.528348 == TX Byte 1 ==
5029 01:17:17.531165 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5030 01:17:17.537892 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5031 01:17:17.538525 ==
5032 01:17:17.541099 Dram Type= 6, Freq= 0, CH_0, rank 0
5033 01:17:17.544654 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5034 01:17:17.545125 ==
5035 01:17:17.545493
5036 01:17:17.545832
5037 01:17:17.548105 TX Vref Scan disable
5038 01:17:17.548623 == TX Byte 0 ==
5039 01:17:17.554705 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5040 01:17:17.558078 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5041 01:17:17.558642 == TX Byte 1 ==
5042 01:17:17.564399 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5043 01:17:17.567954 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5044 01:17:17.568513
5045 01:17:17.568884 [DATLAT]
5046 01:17:17.571369 Freq=933, CH0 RK0
5047 01:17:17.571929
5048 01:17:17.572300 DATLAT Default: 0xd
5049 01:17:17.574070 0, 0xFFFF, sum = 0
5050 01:17:17.577764 1, 0xFFFF, sum = 0
5051 01:17:17.578372 2, 0xFFFF, sum = 0
5052 01:17:17.580997 3, 0xFFFF, sum = 0
5053 01:17:17.581557 4, 0xFFFF, sum = 0
5054 01:17:17.584373 5, 0xFFFF, sum = 0
5055 01:17:17.584942 6, 0xFFFF, sum = 0
5056 01:17:17.587342 7, 0xFFFF, sum = 0
5057 01:17:17.587813 8, 0xFFFF, sum = 0
5058 01:17:17.590657 9, 0xFFFF, sum = 0
5059 01:17:17.591132 10, 0x0, sum = 1
5060 01:17:17.594265 11, 0x0, sum = 2
5061 01:17:17.594830 12, 0x0, sum = 3
5062 01:17:17.597321 13, 0x0, sum = 4
5063 01:17:17.597794 best_step = 11
5064 01:17:17.598204
5065 01:17:17.598549 ==
5066 01:17:17.600549 Dram Type= 6, Freq= 0, CH_0, rank 0
5067 01:17:17.604328 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5068 01:17:17.604891 ==
5069 01:17:17.607389 RX Vref Scan: 1
5070 01:17:17.607950
5071 01:17:17.610836 RX Vref 0 -> 0, step: 1
5072 01:17:17.611404
5073 01:17:17.611783 RX Delay -61 -> 252, step: 4
5074 01:17:17.614008
5075 01:17:17.614513 Set Vref, RX VrefLevel [Byte0]: 46
5076 01:17:17.617290 [Byte1]: 51
5077 01:17:17.622397
5078 01:17:17.622864 Final RX Vref Byte 0 = 46 to rank0
5079 01:17:17.625699 Final RX Vref Byte 1 = 51 to rank0
5080 01:17:17.628981 Final RX Vref Byte 0 = 46 to rank1
5081 01:17:17.632176 Final RX Vref Byte 1 = 51 to rank1==
5082 01:17:17.635683 Dram Type= 6, Freq= 0, CH_0, rank 0
5083 01:17:17.642279 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5084 01:17:17.642867 ==
5085 01:17:17.643245 DQS Delay:
5086 01:17:17.643592 DQS0 = 0, DQS1 = 0
5087 01:17:17.645242 DQM Delay:
5088 01:17:17.645756 DQM0 = 97, DQM1 = 88
5089 01:17:17.648692 DQ Delay:
5090 01:17:17.652145 DQ0 =94, DQ1 =98, DQ2 =96, DQ3 =96
5091 01:17:17.655127 DQ4 =98, DQ5 =90, DQ6 =104, DQ7 =106
5092 01:17:17.658327 DQ8 =78, DQ9 =72, DQ10 =88, DQ11 =80
5093 01:17:17.662050 DQ12 =94, DQ13 =96, DQ14 =98, DQ15 =100
5094 01:17:17.662654
5095 01:17:17.663023
5096 01:17:17.669050 [DQSOSCAuto] RK0, (LSB)MR18= 0x2323, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5097 01:17:17.671815 CH0 RK0: MR19=505, MR18=2323
5098 01:17:17.678919 CH0_RK0: MR19=0x505, MR18=0x2323, DQSOSC=410, MR23=63, INC=64, DEC=42
5099 01:17:17.679547
5100 01:17:17.681966 ----->DramcWriteLeveling(PI) begin...
5101 01:17:17.682578 ==
5102 01:17:17.685221 Dram Type= 6, Freq= 0, CH_0, rank 1
5103 01:17:17.688128 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5104 01:17:17.688645 ==
5105 01:17:17.691552 Write leveling (Byte 0): 28 => 28
5106 01:17:17.694877 Write leveling (Byte 1): 26 => 26
5107 01:17:17.698529 DramcWriteLeveling(PI) end<-----
5108 01:17:17.699087
5109 01:17:17.699455 ==
5110 01:17:17.701580 Dram Type= 6, Freq= 0, CH_0, rank 1
5111 01:17:17.705117 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5112 01:17:17.708346 ==
5113 01:17:17.708903 [Gating] SW mode calibration
5114 01:17:17.718183 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5115 01:17:17.721556 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5116 01:17:17.724726 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 01:17:17.731581 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 01:17:17.734437 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 01:17:17.737870 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 01:17:17.744365 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 01:17:17.747604 0 10 20 | B1->B0 | 3434 2f2f | 0 0 | (1 0) (1 0)
5122 01:17:17.751142 0 10 24 | B1->B0 | 2b2b 2525 | 0 0 | (0 0) (0 0)
5123 01:17:17.757756 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 01:17:17.760818 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 01:17:17.764079 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 01:17:17.770888 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 01:17:17.774182 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 01:17:17.777541 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 01:17:17.784290 0 11 20 | B1->B0 | 2e2e 3a3a | 1 0 | (0 0) (0 0)
5130 01:17:17.787492 0 11 24 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
5131 01:17:17.790825 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 01:17:17.797427 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 01:17:17.800700 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 01:17:17.803700 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 01:17:17.810626 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 01:17:17.813573 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 01:17:17.817369 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5138 01:17:17.823350 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5139 01:17:17.826943 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 01:17:17.830383 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 01:17:17.836765 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 01:17:17.839708 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 01:17:17.843011 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 01:17:17.849891 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 01:17:17.853389 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 01:17:17.856410 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 01:17:17.863340 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 01:17:17.866761 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 01:17:17.869818 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 01:17:17.876467 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 01:17:17.879858 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 01:17:17.882732 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 01:17:17.889957 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5154 01:17:17.892942 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 01:17:17.896319 Total UI for P1: 0, mck2ui 16
5156 01:17:17.899396 best dqsien dly found for B0: ( 0, 14, 20)
5157 01:17:17.903002 Total UI for P1: 0, mck2ui 16
5158 01:17:17.906445 best dqsien dly found for B1: ( 0, 14, 20)
5159 01:17:17.909485 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5160 01:17:17.913011 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5161 01:17:17.913577
5162 01:17:17.916027 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5163 01:17:17.919174 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5164 01:17:17.922937 [Gating] SW calibration Done
5165 01:17:17.923497 ==
5166 01:17:17.925940 Dram Type= 6, Freq= 0, CH_0, rank 1
5167 01:17:17.932606 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5168 01:17:17.933170 ==
5169 01:17:17.933545 RX Vref Scan: 0
5170 01:17:17.933893
5171 01:17:17.935978 RX Vref 0 -> 0, step: 1
5172 01:17:17.936536
5173 01:17:17.939226 RX Delay -80 -> 252, step: 8
5174 01:17:17.942963 iDelay=200, Bit 0, Center 91 (-8 ~ 191) 200
5175 01:17:17.945606 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5176 01:17:17.949150 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5177 01:17:17.952125 iDelay=200, Bit 3, Center 87 (-8 ~ 183) 192
5178 01:17:17.956056 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5179 01:17:17.962302 iDelay=200, Bit 5, Center 91 (-8 ~ 191) 200
5180 01:17:17.965954 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5181 01:17:17.968896 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5182 01:17:17.972309 iDelay=200, Bit 8, Center 71 (-24 ~ 167) 192
5183 01:17:17.975387 iDelay=200, Bit 9, Center 71 (-24 ~ 167) 192
5184 01:17:17.982215 iDelay=200, Bit 10, Center 83 (-16 ~ 183) 200
5185 01:17:17.985638 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5186 01:17:17.988881 iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200
5187 01:17:17.991781 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5188 01:17:17.995416 iDelay=200, Bit 14, Center 91 (-8 ~ 191) 200
5189 01:17:18.002082 iDelay=200, Bit 15, Center 91 (-8 ~ 191) 200
5190 01:17:18.002654 ==
5191 01:17:18.004882 Dram Type= 6, Freq= 0, CH_0, rank 1
5192 01:17:18.009015 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5193 01:17:18.009587 ==
5194 01:17:18.009960 DQS Delay:
5195 01:17:18.011771 DQS0 = 0, DQS1 = 0
5196 01:17:18.012232 DQM Delay:
5197 01:17:18.014937 DQM0 = 96, DQM1 = 83
5198 01:17:18.015502 DQ Delay:
5199 01:17:18.018760 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =87
5200 01:17:18.021782 DQ4 =99, DQ5 =91, DQ6 =103, DQ7 =103
5201 01:17:18.024899 DQ8 =71, DQ9 =71, DQ10 =83, DQ11 =79
5202 01:17:18.028661 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5203 01:17:18.029227
5204 01:17:18.029602
5205 01:17:18.029940 ==
5206 01:17:18.032053 Dram Type= 6, Freq= 0, CH_0, rank 1
5207 01:17:18.034830 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5208 01:17:18.038500 ==
5209 01:17:18.039055
5210 01:17:18.039429
5211 01:17:18.039775 TX Vref Scan disable
5212 01:17:18.041644 == TX Byte 0 ==
5213 01:17:18.044833 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5214 01:17:18.048215 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5215 01:17:18.051386 == TX Byte 1 ==
5216 01:17:18.054915 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5217 01:17:18.058237 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5218 01:17:18.061975 ==
5219 01:17:18.064591 Dram Type= 6, Freq= 0, CH_0, rank 1
5220 01:17:18.068168 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5221 01:17:18.068730 ==
5222 01:17:18.069097
5223 01:17:18.069442
5224 01:17:18.071267 TX Vref Scan disable
5225 01:17:18.071726 == TX Byte 0 ==
5226 01:17:18.078056 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5227 01:17:18.081336 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5228 01:17:18.081891 == TX Byte 1 ==
5229 01:17:18.088028 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5230 01:17:18.091224 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5231 01:17:18.091782
5232 01:17:18.092146 [DATLAT]
5233 01:17:18.094537 Freq=933, CH0 RK1
5234 01:17:18.094999
5235 01:17:18.095360 DATLAT Default: 0xb
5236 01:17:18.097682 0, 0xFFFF, sum = 0
5237 01:17:18.098183 1, 0xFFFF, sum = 0
5238 01:17:18.100826 2, 0xFFFF, sum = 0
5239 01:17:18.101451 3, 0xFFFF, sum = 0
5240 01:17:18.104345 4, 0xFFFF, sum = 0
5241 01:17:18.107488 5, 0xFFFF, sum = 0
5242 01:17:18.107959 6, 0xFFFF, sum = 0
5243 01:17:18.111195 7, 0xFFFF, sum = 0
5244 01:17:18.111761 8, 0xFFFF, sum = 0
5245 01:17:18.114489 9, 0xFFFF, sum = 0
5246 01:17:18.115050 10, 0x0, sum = 1
5247 01:17:18.117755 11, 0x0, sum = 2
5248 01:17:18.118361 12, 0x0, sum = 3
5249 01:17:18.118744 13, 0x0, sum = 4
5250 01:17:18.121477 best_step = 11
5251 01:17:18.122065
5252 01:17:18.122440 ==
5253 01:17:18.124248 Dram Type= 6, Freq= 0, CH_0, rank 1
5254 01:17:18.127736 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5255 01:17:18.128229 ==
5256 01:17:18.130796 RX Vref Scan: 0
5257 01:17:18.131255
5258 01:17:18.131618 RX Vref 0 -> 0, step: 1
5259 01:17:18.134603
5260 01:17:18.135157 RX Delay -69 -> 252, step: 4
5261 01:17:18.141909 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5262 01:17:18.144992 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5263 01:17:18.148132 iDelay=199, Bit 2, Center 96 (7 ~ 186) 180
5264 01:17:18.151907 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5265 01:17:18.154846 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5266 01:17:18.161784 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5267 01:17:18.165040 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5268 01:17:18.168400 iDelay=199, Bit 7, Center 108 (19 ~ 198) 180
5269 01:17:18.171464 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5270 01:17:18.175054 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5271 01:17:18.178302 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5272 01:17:18.184995 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5273 01:17:18.188057 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5274 01:17:18.191393 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5275 01:17:18.194604 iDelay=199, Bit 14, Center 96 (3 ~ 190) 188
5276 01:17:18.197892 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5277 01:17:18.198400 ==
5278 01:17:18.201393 Dram Type= 6, Freq= 0, CH_0, rank 1
5279 01:17:18.208048 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5280 01:17:18.208612 ==
5281 01:17:18.208981 DQS Delay:
5282 01:17:18.211115 DQS0 = 0, DQS1 = 0
5283 01:17:18.211634 DQM Delay:
5284 01:17:18.214320 DQM0 = 97, DQM1 = 86
5285 01:17:18.214776 DQ Delay:
5286 01:17:18.218126 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =92
5287 01:17:18.221140 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =108
5288 01:17:18.224605 DQ8 =76, DQ9 =72, DQ10 =86, DQ11 =78
5289 01:17:18.227703 DQ12 =94, DQ13 =92, DQ14 =96, DQ15 =94
5290 01:17:18.228261
5291 01:17:18.228627
5292 01:17:18.234054 [DQSOSCAuto] RK1, (LSB)MR18= 0x2525, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5293 01:17:18.237390 CH0 RK1: MR19=505, MR18=2525
5294 01:17:18.243852 CH0_RK1: MR19=0x505, MR18=0x2525, DQSOSC=410, MR23=63, INC=64, DEC=42
5295 01:17:18.247292 [RxdqsGatingPostProcess] freq 933
5296 01:17:18.253609 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5297 01:17:18.257183 Pre-setting of DQS Precalculation
5298 01:17:18.260578 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5299 01:17:18.261001 ==
5300 01:17:18.263631 Dram Type= 6, Freq= 0, CH_1, rank 0
5301 01:17:18.266876 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5302 01:17:18.267116 ==
5303 01:17:18.273549 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5304 01:17:18.280289 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5305 01:17:18.283598 [CA 0] Center 37 (7~68) winsize 62
5306 01:17:18.286900 [CA 1] Center 37 (6~68) winsize 63
5307 01:17:18.290365 [CA 2] Center 34 (4~65) winsize 62
5308 01:17:18.293708 [CA 3] Center 34 (4~65) winsize 62
5309 01:17:18.296944 [CA 4] Center 33 (2~64) winsize 63
5310 01:17:18.300438 [CA 5] Center 33 (2~64) winsize 63
5311 01:17:18.301071
5312 01:17:18.303387 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5313 01:17:18.303823
5314 01:17:18.306658 [CATrainingPosCal] consider 1 rank data
5315 01:17:18.310093 u2DelayCellTimex100 = 270/100 ps
5316 01:17:18.313842 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5317 01:17:18.316724 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5318 01:17:18.320023 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5319 01:17:18.323164 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5320 01:17:18.326843 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5321 01:17:18.333682 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5322 01:17:18.334247
5323 01:17:18.336784 CA PerBit enable=1, Macro0, CA PI delay=33
5324 01:17:18.337339
5325 01:17:18.339963 [CBTSetCACLKResult] CA Dly = 33
5326 01:17:18.340516 CS Dly: 5 (0~36)
5327 01:17:18.340879 ==
5328 01:17:18.343059 Dram Type= 6, Freq= 0, CH_1, rank 1
5329 01:17:18.350133 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5330 01:17:18.350692 ==
5331 01:17:18.352994 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5332 01:17:18.359605 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5333 01:17:18.362726 [CA 0] Center 37 (6~68) winsize 63
5334 01:17:18.365977 [CA 1] Center 37 (6~68) winsize 63
5335 01:17:18.369684 [CA 2] Center 34 (4~65) winsize 62
5336 01:17:18.372823 [CA 3] Center 34 (4~65) winsize 62
5337 01:17:18.376364 [CA 4] Center 33 (2~64) winsize 63
5338 01:17:18.379338 [CA 5] Center 32 (2~63) winsize 62
5339 01:17:18.379942
5340 01:17:18.382584 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5341 01:17:18.383045
5342 01:17:18.386274 [CATrainingPosCal] consider 2 rank data
5343 01:17:18.389372 u2DelayCellTimex100 = 270/100 ps
5344 01:17:18.393024 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5345 01:17:18.396012 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5346 01:17:18.402570 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5347 01:17:18.405695 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5348 01:17:18.409428 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5349 01:17:18.413057 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5350 01:17:18.413617
5351 01:17:18.415937 CA PerBit enable=1, Macro0, CA PI delay=32
5352 01:17:18.416485
5353 01:17:18.418902 [CBTSetCACLKResult] CA Dly = 32
5354 01:17:18.419359 CS Dly: 5 (0~37)
5355 01:17:18.422369
5356 01:17:18.425808 ----->DramcWriteLeveling(PI) begin...
5357 01:17:18.426420 ==
5358 01:17:18.429436 Dram Type= 6, Freq= 0, CH_1, rank 0
5359 01:17:18.432420 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5360 01:17:18.432973 ==
5361 01:17:18.435830 Write leveling (Byte 0): 21 => 21
5362 01:17:18.438940 Write leveling (Byte 1): 28 => 28
5363 01:17:18.442384 DramcWriteLeveling(PI) end<-----
5364 01:17:18.442934
5365 01:17:18.443297 ==
5366 01:17:18.445323 Dram Type= 6, Freq= 0, CH_1, rank 0
5367 01:17:18.448898 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5368 01:17:18.449453 ==
5369 01:17:18.452204 [Gating] SW mode calibration
5370 01:17:18.458753 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5371 01:17:18.465521 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5372 01:17:18.468891 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 01:17:18.472158 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5374 01:17:18.478455 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5375 01:17:18.482117 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5376 01:17:18.485435 0 10 16 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
5377 01:17:18.491517 0 10 20 | B1->B0 | 3434 2727 | 1 0 | (1 0) (1 0)
5378 01:17:18.494658 0 10 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5379 01:17:18.498341 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 01:17:18.504966 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 01:17:18.508421 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 01:17:18.511318 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5383 01:17:18.518015 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5384 01:17:18.521324 0 11 16 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5385 01:17:18.524666 0 11 20 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
5386 01:17:18.531221 0 11 24 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5387 01:17:18.534814 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 01:17:18.537902 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 01:17:18.544549 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 01:17:18.547765 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 01:17:18.550949 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 01:17:18.557631 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 01:17:18.560840 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5394 01:17:18.564174 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 01:17:18.570928 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 01:17:18.574149 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 01:17:18.577289 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 01:17:18.583952 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 01:17:18.587304 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 01:17:18.590722 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 01:17:18.597536 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 01:17:18.600564 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 01:17:18.603534 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 01:17:18.610280 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 01:17:18.613547 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 01:17:18.617343 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 01:17:18.623708 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 01:17:18.626909 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5409 01:17:18.630766 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5410 01:17:18.633662 Total UI for P1: 0, mck2ui 16
5411 01:17:18.636987 best dqsien dly found for B0: ( 0, 14, 16)
5412 01:17:18.643558 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5413 01:17:18.644114 Total UI for P1: 0, mck2ui 16
5414 01:17:18.650323 best dqsien dly found for B1: ( 0, 14, 18)
5415 01:17:18.653194 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5416 01:17:18.656374 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5417 01:17:18.656924
5418 01:17:18.659824 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5419 01:17:18.663158 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5420 01:17:18.666507 [Gating] SW calibration Done
5421 01:17:18.667057 ==
5422 01:17:18.669680 Dram Type= 6, Freq= 0, CH_1, rank 0
5423 01:17:18.672805 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5424 01:17:18.673359 ==
5425 01:17:18.676186 RX Vref Scan: 0
5426 01:17:18.676738
5427 01:17:18.679914 RX Vref 0 -> 0, step: 1
5428 01:17:18.680466
5429 01:17:18.680834 RX Delay -80 -> 252, step: 8
5430 01:17:18.686292 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5431 01:17:18.689559 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5432 01:17:18.692913 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5433 01:17:18.696077 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5434 01:17:18.699638 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5435 01:17:18.702912 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5436 01:17:18.709543 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5437 01:17:18.712848 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5438 01:17:18.716150 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5439 01:17:18.719605 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5440 01:17:18.722624 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5441 01:17:18.729383 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5442 01:17:18.732442 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5443 01:17:18.735911 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5444 01:17:18.739187 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5445 01:17:18.742453 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5446 01:17:18.743001 ==
5447 01:17:18.745745 Dram Type= 6, Freq= 0, CH_1, rank 0
5448 01:17:18.752179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5449 01:17:18.752732 ==
5450 01:17:18.753105 DQS Delay:
5451 01:17:18.755287 DQS0 = 0, DQS1 = 0
5452 01:17:18.755745 DQM Delay:
5453 01:17:18.758596 DQM0 = 94, DQM1 = 86
5454 01:17:18.759056 DQ Delay:
5455 01:17:18.761898 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5456 01:17:18.765362 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5457 01:17:18.768606 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =79
5458 01:17:18.771992 DQ12 =91, DQ13 =99, DQ14 =91, DQ15 =95
5459 01:17:18.772543
5460 01:17:18.773055
5461 01:17:18.773528 ==
5462 01:17:18.775332 Dram Type= 6, Freq= 0, CH_1, rank 0
5463 01:17:18.778916 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5464 01:17:18.779472 ==
5465 01:17:18.779834
5466 01:17:18.780166
5467 01:17:18.781542 TX Vref Scan disable
5468 01:17:18.785386 == TX Byte 0 ==
5469 01:17:18.788381 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5470 01:17:18.791672 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5471 01:17:18.794776 == TX Byte 1 ==
5472 01:17:18.798633 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5473 01:17:18.802130 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5474 01:17:18.802679 ==
5475 01:17:18.804596 Dram Type= 6, Freq= 0, CH_1, rank 0
5476 01:17:18.812006 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5477 01:17:18.812560 ==
5478 01:17:18.812968
5479 01:17:18.813317
5480 01:17:18.813635 TX Vref Scan disable
5481 01:17:18.815745 == TX Byte 0 ==
5482 01:17:18.819066 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5483 01:17:18.825677 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5484 01:17:18.826272 == TX Byte 1 ==
5485 01:17:18.828899 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5486 01:17:18.835722 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5487 01:17:18.836273
5488 01:17:18.836636 [DATLAT]
5489 01:17:18.836970 Freq=933, CH1 RK0
5490 01:17:18.837294
5491 01:17:18.838964 DATLAT Default: 0xd
5492 01:17:18.839416 0, 0xFFFF, sum = 0
5493 01:17:18.842458 1, 0xFFFF, sum = 0
5494 01:17:18.843022 2, 0xFFFF, sum = 0
5495 01:17:18.845470 3, 0xFFFF, sum = 0
5496 01:17:18.848662 4, 0xFFFF, sum = 0
5497 01:17:18.849240 5, 0xFFFF, sum = 0
5498 01:17:18.851801 6, 0xFFFF, sum = 0
5499 01:17:18.852264 7, 0xFFFF, sum = 0
5500 01:17:18.855025 8, 0xFFFF, sum = 0
5501 01:17:18.855487 9, 0xFFFF, sum = 0
5502 01:17:18.858716 10, 0x0, sum = 1
5503 01:17:18.859311 11, 0x0, sum = 2
5504 01:17:18.861936 12, 0x0, sum = 3
5505 01:17:18.862457 13, 0x0, sum = 4
5506 01:17:18.862828 best_step = 11
5507 01:17:18.863167
5508 01:17:18.865485 ==
5509 01:17:18.868515 Dram Type= 6, Freq= 0, CH_1, rank 0
5510 01:17:18.871706 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5511 01:17:18.872261 ==
5512 01:17:18.872626 RX Vref Scan: 1
5513 01:17:18.872969
5514 01:17:18.875768 RX Vref 0 -> 0, step: 1
5515 01:17:18.876317
5516 01:17:18.878565 RX Delay -69 -> 252, step: 4
5517 01:17:18.879022
5518 01:17:18.882000 Set Vref, RX VrefLevel [Byte0]: 56
5519 01:17:18.885233 [Byte1]: 51
5520 01:17:18.885784
5521 01:17:18.888499 Final RX Vref Byte 0 = 56 to rank0
5522 01:17:18.891909 Final RX Vref Byte 1 = 51 to rank0
5523 01:17:18.894979 Final RX Vref Byte 0 = 56 to rank1
5524 01:17:18.898127 Final RX Vref Byte 1 = 51 to rank1==
5525 01:17:18.901462 Dram Type= 6, Freq= 0, CH_1, rank 0
5526 01:17:18.908436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5527 01:17:18.908990 ==
5528 01:17:18.909364 DQS Delay:
5529 01:17:18.909706 DQS0 = 0, DQS1 = 0
5530 01:17:18.911481 DQM Delay:
5531 01:17:18.912035 DQM0 = 94, DQM1 = 88
5532 01:17:18.915274 DQ Delay:
5533 01:17:18.918267 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5534 01:17:18.921366 DQ4 =94, DQ5 =104, DQ6 =100, DQ7 =92
5535 01:17:18.924739 DQ8 =72, DQ9 =78, DQ10 =90, DQ11 =80
5536 01:17:18.928150 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5537 01:17:18.928698
5538 01:17:18.929061
5539 01:17:18.934982 [DQSOSCAuto] RK0, (LSB)MR18= 0x3232, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5540 01:17:18.937798 CH1 RK0: MR19=505, MR18=3232
5541 01:17:18.944904 CH1_RK0: MR19=0x505, MR18=0x3232, DQSOSC=406, MR23=63, INC=65, DEC=43
5542 01:17:18.945480
5543 01:17:18.947911 ----->DramcWriteLeveling(PI) begin...
5544 01:17:18.948376 ==
5545 01:17:18.950918 Dram Type= 6, Freq= 0, CH_1, rank 1
5546 01:17:18.954534 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5547 01:17:18.955081 ==
5548 01:17:18.957944 Write leveling (Byte 0): 22 => 22
5549 01:17:18.961076 Write leveling (Byte 1): 22 => 22
5550 01:17:18.964727 DramcWriteLeveling(PI) end<-----
5551 01:17:18.965278
5552 01:17:18.965637 ==
5553 01:17:18.967533 Dram Type= 6, Freq= 0, CH_1, rank 1
5554 01:17:18.970774 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5555 01:17:18.971232 ==
5556 01:17:18.974304 [Gating] SW mode calibration
5557 01:17:18.981001 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5558 01:17:18.987773 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5559 01:17:18.990846 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 01:17:18.997407 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 01:17:19.000915 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 01:17:19.004021 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 01:17:19.010921 0 10 16 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
5564 01:17:19.014177 0 10 20 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
5565 01:17:19.017652 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 01:17:19.023944 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 01:17:19.027260 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 01:17:19.031021 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 01:17:19.037403 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 01:17:19.040510 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 01:17:19.043892 0 11 16 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
5572 01:17:19.050208 0 11 20 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
5573 01:17:19.053757 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 01:17:19.057137 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 01:17:19.063566 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 01:17:19.066618 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 01:17:19.070130 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 01:17:19.076808 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 01:17:19.080147 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5580 01:17:19.083502 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5581 01:17:19.089999 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 01:17:19.093767 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 01:17:19.096815 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 01:17:19.103259 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 01:17:19.106327 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 01:17:19.109774 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 01:17:19.116708 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 01:17:19.119721 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 01:17:19.122988 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 01:17:19.126850 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 01:17:19.133337 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 01:17:19.136508 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 01:17:19.139627 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 01:17:19.146193 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 01:17:19.149620 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5596 01:17:19.153066 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 01:17:19.156107 Total UI for P1: 0, mck2ui 16
5598 01:17:19.159336 best dqsien dly found for B0: ( 0, 14, 16)
5599 01:17:19.162823 Total UI for P1: 0, mck2ui 16
5600 01:17:19.166006 best dqsien dly found for B1: ( 0, 14, 18)
5601 01:17:19.169159 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5602 01:17:19.175885 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5603 01:17:19.176431
5604 01:17:19.179370 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5605 01:17:19.182572 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5606 01:17:19.186209 [Gating] SW calibration Done
5607 01:17:19.186762 ==
5608 01:17:19.188982 Dram Type= 6, Freq= 0, CH_1, rank 1
5609 01:17:19.192545 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5610 01:17:19.193109 ==
5611 01:17:19.195584 RX Vref Scan: 0
5612 01:17:19.196043
5613 01:17:19.196407 RX Vref 0 -> 0, step: 1
5614 01:17:19.196748
5615 01:17:19.199338 RX Delay -80 -> 252, step: 8
5616 01:17:19.202635 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5617 01:17:19.206117 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5618 01:17:19.212463 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5619 01:17:19.215825 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5620 01:17:19.218782 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5621 01:17:19.222364 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5622 01:17:19.225784 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5623 01:17:19.232372 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5624 01:17:19.235723 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5625 01:17:19.238902 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5626 01:17:19.242456 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5627 01:17:19.245992 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5628 01:17:19.252222 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5629 01:17:19.255573 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5630 01:17:19.259008 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5631 01:17:19.262281 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5632 01:17:19.262842 ==
5633 01:17:19.265188 Dram Type= 6, Freq= 0, CH_1, rank 1
5634 01:17:19.268628 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5635 01:17:19.272224 ==
5636 01:17:19.272785 DQS Delay:
5637 01:17:19.273154 DQS0 = 0, DQS1 = 0
5638 01:17:19.275038 DQM Delay:
5639 01:17:19.275499 DQM0 = 95, DQM1 = 85
5640 01:17:19.278751 DQ Delay:
5641 01:17:19.279387 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =91
5642 01:17:19.281837 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5643 01:17:19.285216 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =75
5644 01:17:19.291740 DQ12 =91, DQ13 =95, DQ14 =91, DQ15 =91
5645 01:17:19.292305
5646 01:17:19.292674
5647 01:17:19.293009 ==
5648 01:17:19.294875 Dram Type= 6, Freq= 0, CH_1, rank 1
5649 01:17:19.298405 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5650 01:17:19.298969 ==
5651 01:17:19.299341
5652 01:17:19.299681
5653 01:17:19.301395 TX Vref Scan disable
5654 01:17:19.301856 == TX Byte 0 ==
5655 01:17:19.308626 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5656 01:17:19.311512 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5657 01:17:19.311975 == TX Byte 1 ==
5658 01:17:19.317877 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5659 01:17:19.321549 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5660 01:17:19.322054 ==
5661 01:17:19.325056 Dram Type= 6, Freq= 0, CH_1, rank 1
5662 01:17:19.328357 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5663 01:17:19.328993 ==
5664 01:17:19.329374
5665 01:17:19.329715
5666 01:17:19.331154 TX Vref Scan disable
5667 01:17:19.334417 == TX Byte 0 ==
5668 01:17:19.337952 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5669 01:17:19.341239 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5670 01:17:19.344699 == TX Byte 1 ==
5671 01:17:19.347935 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5672 01:17:19.351310 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5673 01:17:19.354282
5674 01:17:19.354744 [DATLAT]
5675 01:17:19.355105 Freq=933, CH1 RK1
5676 01:17:19.355450
5677 01:17:19.357652 DATLAT Default: 0xb
5678 01:17:19.358240 0, 0xFFFF, sum = 0
5679 01:17:19.361360 1, 0xFFFF, sum = 0
5680 01:17:19.361924 2, 0xFFFF, sum = 0
5681 01:17:19.364119 3, 0xFFFF, sum = 0
5682 01:17:19.364834 4, 0xFFFF, sum = 0
5683 01:17:19.367639 5, 0xFFFF, sum = 0
5684 01:17:19.370758 6, 0xFFFF, sum = 0
5685 01:17:19.371222 7, 0xFFFF, sum = 0
5686 01:17:19.373977 8, 0xFFFF, sum = 0
5687 01:17:19.374475 9, 0xFFFF, sum = 0
5688 01:17:19.377889 10, 0x0, sum = 1
5689 01:17:19.378520 11, 0x0, sum = 2
5690 01:17:19.378897 12, 0x0, sum = 3
5691 01:17:19.380994 13, 0x0, sum = 4
5692 01:17:19.381559 best_step = 11
5693 01:17:19.381926
5694 01:17:19.384906 ==
5695 01:17:19.385484 Dram Type= 6, Freq= 0, CH_1, rank 1
5696 01:17:19.390899 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5697 01:17:19.391388 ==
5698 01:17:19.391756 RX Vref Scan: 0
5699 01:17:19.392098
5700 01:17:19.393759 RX Vref 0 -> 0, step: 1
5701 01:17:19.394254
5702 01:17:19.397313 RX Delay -69 -> 252, step: 4
5703 01:17:19.400563 iDelay=203, Bit 0, Center 94 (3 ~ 186) 184
5704 01:17:19.407267 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5705 01:17:19.410406 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5706 01:17:19.413772 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5707 01:17:19.417066 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5708 01:17:19.420393 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5709 01:17:19.427099 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5710 01:17:19.430368 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5711 01:17:19.433511 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5712 01:17:19.437304 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5713 01:17:19.440052 iDelay=203, Bit 10, Center 86 (-5 ~ 178) 184
5714 01:17:19.443437 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5715 01:17:19.450246 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5716 01:17:19.453671 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5717 01:17:19.456708 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5718 01:17:19.460105 iDelay=203, Bit 15, Center 98 (11 ~ 186) 176
5719 01:17:19.460564 ==
5720 01:17:19.463409 Dram Type= 6, Freq= 0, CH_1, rank 1
5721 01:17:19.470670 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5722 01:17:19.471213 ==
5723 01:17:19.471556 DQS Delay:
5724 01:17:19.471874 DQS0 = 0, DQS1 = 0
5725 01:17:19.473228 DQM Delay:
5726 01:17:19.473644 DQM0 = 95, DQM1 = 87
5727 01:17:19.477058 DQ Delay:
5728 01:17:19.480293 DQ0 =94, DQ1 =90, DQ2 =88, DQ3 =92
5729 01:17:19.483508 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5730 01:17:19.486953 DQ8 =74, DQ9 =74, DQ10 =86, DQ11 =80
5731 01:17:19.490171 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =98
5732 01:17:19.490693
5733 01:17:19.491032
5734 01:17:19.496497 [DQSOSCAuto] RK1, (LSB)MR18= 0x2020, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5735 01:17:19.500087 CH1 RK1: MR19=505, MR18=2020
5736 01:17:19.506668 CH1_RK1: MR19=0x505, MR18=0x2020, DQSOSC=411, MR23=63, INC=64, DEC=42
5737 01:17:19.509730 [RxdqsGatingPostProcess] freq 933
5738 01:17:19.512914 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5739 01:17:19.516733 Pre-setting of DQS Precalculation
5740 01:17:19.523325 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5741 01:17:19.529843 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5742 01:17:19.536570 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5743 01:17:19.537090
5744 01:17:19.537419
5745 01:17:19.539326 [Calibration Summary] 1866 Mbps
5746 01:17:19.539740 CH 0, Rank 0
5747 01:17:19.542887 SW Impedance : PASS
5748 01:17:19.545970 DUTY Scan : NO K
5749 01:17:19.546516 ZQ Calibration : PASS
5750 01:17:19.549218 Jitter Meter : NO K
5751 01:17:19.552584 CBT Training : PASS
5752 01:17:19.553097 Write leveling : PASS
5753 01:17:19.555982 RX DQS gating : PASS
5754 01:17:19.559769 RX DQ/DQS(RDDQC) : PASS
5755 01:17:19.560288 TX DQ/DQS : PASS
5756 01:17:19.562982 RX DATLAT : PASS
5757 01:17:19.565740 RX DQ/DQS(Engine): PASS
5758 01:17:19.566190 TX OE : NO K
5759 01:17:19.569449 All Pass.
5760 01:17:19.569976
5761 01:17:19.570367 CH 0, Rank 1
5762 01:17:19.572564 SW Impedance : PASS
5763 01:17:19.573080 DUTY Scan : NO K
5764 01:17:19.575883 ZQ Calibration : PASS
5765 01:17:19.579289 Jitter Meter : NO K
5766 01:17:19.579806 CBT Training : PASS
5767 01:17:19.583203 Write leveling : PASS
5768 01:17:19.585639 RX DQS gating : PASS
5769 01:17:19.586080 RX DQ/DQS(RDDQC) : PASS
5770 01:17:19.589287 TX DQ/DQS : PASS
5771 01:17:19.589805 RX DATLAT : PASS
5772 01:17:19.592325 RX DQ/DQS(Engine): PASS
5773 01:17:19.595921 TX OE : NO K
5774 01:17:19.596397 All Pass.
5775 01:17:19.596745
5776 01:17:19.597057 CH 1, Rank 0
5777 01:17:19.599331 SW Impedance : PASS
5778 01:17:19.602368 DUTY Scan : NO K
5779 01:17:19.602783 ZQ Calibration : PASS
5780 01:17:19.605832 Jitter Meter : NO K
5781 01:17:19.609127 CBT Training : PASS
5782 01:17:19.609641 Write leveling : PASS
5783 01:17:19.612237 RX DQS gating : PASS
5784 01:17:19.616156 RX DQ/DQS(RDDQC) : PASS
5785 01:17:19.616673 TX DQ/DQS : PASS
5786 01:17:19.618707 RX DATLAT : PASS
5787 01:17:19.622214 RX DQ/DQS(Engine): PASS
5788 01:17:19.622629 TX OE : NO K
5789 01:17:19.625614 All Pass.
5790 01:17:19.626081
5791 01:17:19.626426 CH 1, Rank 1
5792 01:17:19.628912 SW Impedance : PASS
5793 01:17:19.629344 DUTY Scan : NO K
5794 01:17:19.632446 ZQ Calibration : PASS
5795 01:17:19.635734 Jitter Meter : NO K
5796 01:17:19.636251 CBT Training : PASS
5797 01:17:19.638836 Write leveling : PASS
5798 01:17:19.642363 RX DQS gating : PASS
5799 01:17:19.642899 RX DQ/DQS(RDDQC) : PASS
5800 01:17:19.645341 TX DQ/DQS : PASS
5801 01:17:19.648971 RX DATLAT : PASS
5802 01:17:19.649489 RX DQ/DQS(Engine): PASS
5803 01:17:19.652049 TX OE : NO K
5804 01:17:19.652573 All Pass.
5805 01:17:19.652905
5806 01:17:19.655931 DramC Write-DBI off
5807 01:17:19.659117 PER_BANK_REFRESH: Hybrid Mode
5808 01:17:19.659638 TX_TRACKING: ON
5809 01:17:19.668993 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5810 01:17:19.671725 [FAST_K] Save calibration result to emmc
5811 01:17:19.675287 dramc_set_vcore_voltage set vcore to 650000
5812 01:17:19.678470 Read voltage for 400, 6
5813 01:17:19.678989 Vio18 = 0
5814 01:17:19.679324 Vcore = 650000
5815 01:17:19.681792 Vdram = 0
5816 01:17:19.682249 Vddq = 0
5817 01:17:19.682584 Vmddr = 0
5818 01:17:19.688687 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5819 01:17:19.691776 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5820 01:17:19.694987 MEM_TYPE=3, freq_sel=20
5821 01:17:19.698343 sv_algorithm_assistance_LP4_800
5822 01:17:19.701909 ============ PULL DRAM RESETB DOWN ============
5823 01:17:19.705254 ========== PULL DRAM RESETB DOWN end =========
5824 01:17:19.711910 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5825 01:17:19.714755 ===================================
5826 01:17:19.715273 LPDDR4 DRAM CONFIGURATION
5827 01:17:19.718111 ===================================
5828 01:17:19.721750 EX_ROW_EN[0] = 0x0
5829 01:17:19.724649 EX_ROW_EN[1] = 0x0
5830 01:17:19.725161 LP4Y_EN = 0x0
5831 01:17:19.727776 WORK_FSP = 0x0
5832 01:17:19.728194 WL = 0x2
5833 01:17:19.731162 RL = 0x2
5834 01:17:19.731673 BL = 0x2
5835 01:17:19.734840 RPST = 0x0
5836 01:17:19.735355 RD_PRE = 0x0
5837 01:17:19.737712 WR_PRE = 0x1
5838 01:17:19.738260 WR_PST = 0x0
5839 01:17:19.741147 DBI_WR = 0x0
5840 01:17:19.741660 DBI_RD = 0x0
5841 01:17:19.744547 OTF = 0x1
5842 01:17:19.747472 ===================================
5843 01:17:19.750907 ===================================
5844 01:17:19.751398 ANA top config
5845 01:17:19.754449 ===================================
5846 01:17:19.757836 DLL_ASYNC_EN = 0
5847 01:17:19.760879 ALL_SLAVE_EN = 1
5848 01:17:19.764242 NEW_RANK_MODE = 1
5849 01:17:19.764759 DLL_IDLE_MODE = 1
5850 01:17:19.767256 LP45_APHY_COMB_EN = 1
5851 01:17:19.770686 TX_ODT_DIS = 1
5852 01:17:19.774158 NEW_8X_MODE = 1
5853 01:17:19.777413 ===================================
5854 01:17:19.780810 ===================================
5855 01:17:19.784273 data_rate = 800
5856 01:17:19.787370 CKR = 1
5857 01:17:19.787790 DQ_P2S_RATIO = 4
5858 01:17:19.790958 ===================================
5859 01:17:19.794156 CA_P2S_RATIO = 4
5860 01:17:19.797208 DQ_CA_OPEN = 0
5861 01:17:19.800819 DQ_SEMI_OPEN = 1
5862 01:17:19.803855 CA_SEMI_OPEN = 1
5863 01:17:19.804274 CA_FULL_RATE = 0
5864 01:17:19.807525 DQ_CKDIV4_EN = 0
5865 01:17:19.810738 CA_CKDIV4_EN = 1
5866 01:17:19.814197 CA_PREDIV_EN = 0
5867 01:17:19.817441 PH8_DLY = 0
5868 01:17:19.820824 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5869 01:17:19.821335 DQ_AAMCK_DIV = 0
5870 01:17:19.824142 CA_AAMCK_DIV = 0
5871 01:17:19.827271 CA_ADMCK_DIV = 4
5872 01:17:19.830535 DQ_TRACK_CA_EN = 0
5873 01:17:19.833689 CA_PICK = 800
5874 01:17:19.837091 CA_MCKIO = 400
5875 01:17:19.840424 MCKIO_SEMI = 400
5876 01:17:19.843654 PLL_FREQ = 3016
5877 01:17:19.844075 DQ_UI_PI_RATIO = 32
5878 01:17:19.847190 CA_UI_PI_RATIO = 32
5879 01:17:19.850400 ===================================
5880 01:17:19.853859 ===================================
5881 01:17:19.856863 memory_type:LPDDR4
5882 01:17:19.860090 GP_NUM : 10
5883 01:17:19.860604 SRAM_EN : 1
5884 01:17:19.863413 MD32_EN : 0
5885 01:17:19.866582 ===================================
5886 01:17:19.869884 [ANA_INIT] >>>>>>>>>>>>>>
5887 01:17:19.870338 <<<<<< [CONFIGURE PHASE]: ANA_TX
5888 01:17:19.876824 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5889 01:17:19.877361 ===================================
5890 01:17:19.880015 data_rate = 800,PCW = 0X7400
5891 01:17:19.883314 ===================================
5892 01:17:19.886372 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5893 01:17:19.893266 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5894 01:17:19.902941 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5895 01:17:19.909893 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5896 01:17:19.913038 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5897 01:17:19.916155 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5898 01:17:19.919584 [ANA_INIT] flow start
5899 01:17:19.920136 [ANA_INIT] PLL >>>>>>>>
5900 01:17:19.923203 [ANA_INIT] PLL <<<<<<<<
5901 01:17:19.926671 [ANA_INIT] MIDPI >>>>>>>>
5902 01:17:19.927225 [ANA_INIT] MIDPI <<<<<<<<
5903 01:17:19.929853 [ANA_INIT] DLL >>>>>>>>
5904 01:17:19.933007 [ANA_INIT] flow end
5905 01:17:19.936074 ============ LP4 DIFF to SE enter ============
5906 01:17:19.939625 ============ LP4 DIFF to SE exit ============
5907 01:17:19.943252 [ANA_INIT] <<<<<<<<<<<<<
5908 01:17:19.945933 [Flow] Enable top DCM control >>>>>
5909 01:17:19.949220 [Flow] Enable top DCM control <<<<<
5910 01:17:19.952720 Enable DLL master slave shuffle
5911 01:17:19.956163 ==============================================================
5912 01:17:19.959080 Gating Mode config
5913 01:17:19.966212 ==============================================================
5914 01:17:19.966767 Config description:
5915 01:17:19.976171 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5916 01:17:19.982272 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5917 01:17:19.985941 SELPH_MODE 0: By rank 1: By Phase
5918 01:17:19.992769 ==============================================================
5919 01:17:19.995737 GAT_TRACK_EN = 0
5920 01:17:19.999061 RX_GATING_MODE = 2
5921 01:17:20.002432 RX_GATING_TRACK_MODE = 2
5922 01:17:20.005393 SELPH_MODE = 1
5923 01:17:20.008850 PICG_EARLY_EN = 1
5924 01:17:30.462578 VALID_LAT_VALUE = 1
5925 01:17:30.462717 ==============================================================
5926 01:17:30.462786 Enter into Gating configuration >>>>
5927 01:17:30.462846 Exit from Gating configuration <<<<
5928 01:17:30.462904 Enter into DVFS_PRE_config >>>>>
5929 01:17:30.462961 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5930 01:17:30.463019 Exit from DVFS_PRE_config <<<<<
5931 01:17:30.463074 Enter into PICG configuration >>>>
5932 01:17:30.463128 Exit from PICG configuration <<<<
5933 01:17:30.463182 [RX_INPUT] configuration >>>>>
5934 01:17:30.463235 [RX_INPUT] configuration <<<<<
5935 01:17:30.463300 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5936 01:17:30.463355 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5937 01:17:30.463409 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5938 01:17:30.463462 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5939 01:17:30.463515 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5940 01:17:30.463568 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5941 01:17:30.463620 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5942 01:17:30.463672 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5943 01:17:30.463724 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5944 01:17:30.463776 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5945 01:17:30.463828 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5946 01:17:30.463880 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5947 01:17:30.463932 ===================================
5948 01:17:30.463984 LPDDR4 DRAM CONFIGURATION
5949 01:17:30.464036 ===================================
5950 01:17:30.464088 EX_ROW_EN[0] = 0x0
5951 01:17:30.464140 EX_ROW_EN[1] = 0x0
5952 01:17:30.464192 LP4Y_EN = 0x0
5953 01:17:30.464243 WORK_FSP = 0x0
5954 01:17:30.464294 WL = 0x2
5955 01:17:30.464345 RL = 0x2
5956 01:17:30.464397 BL = 0x2
5957 01:17:30.464447 RPST = 0x0
5958 01:17:30.464499 RD_PRE = 0x0
5959 01:17:30.464550 WR_PRE = 0x1
5960 01:17:30.464601 WR_PST = 0x0
5961 01:17:30.464652 DBI_WR = 0x0
5962 01:17:30.464703 DBI_RD = 0x0
5963 01:17:30.464754 OTF = 0x1
5964 01:17:30.464806 ===================================
5965 01:17:30.464858 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5966 01:17:30.464910 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5967 01:17:30.464961 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5968 01:17:30.465012 ===================================
5969 01:17:30.465063 LPDDR4 DRAM CONFIGURATION
5970 01:17:30.465115 ===================================
5971 01:17:30.465167 EX_ROW_EN[0] = 0x10
5972 01:17:30.465218 EX_ROW_EN[1] = 0x0
5973 01:17:30.465269 LP4Y_EN = 0x0
5974 01:17:30.465320 WORK_FSP = 0x0
5975 01:17:30.465387 WL = 0x2
5976 01:17:30.465442 RL = 0x2
5977 01:17:30.465496 BL = 0x2
5978 01:17:30.465551 RPST = 0x0
5979 01:17:30.465605 RD_PRE = 0x0
5980 01:17:30.465660 WR_PRE = 0x1
5981 01:17:30.465714 WR_PST = 0x0
5982 01:17:30.465769 DBI_WR = 0x0
5983 01:17:30.465823 DBI_RD = 0x0
5984 01:17:30.465878 OTF = 0x1
5985 01:17:30.465932 ===================================
5986 01:17:30.465987 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5987 01:17:30.466049 nWR fixed to 30
5988 01:17:30.466106 [ModeRegInit_LP4] CH0 RK0
5989 01:17:30.466160 [ModeRegInit_LP4] CH0 RK1
5990 01:17:30.466215 [ModeRegInit_LP4] CH1 RK0
5991 01:17:30.466270 [ModeRegInit_LP4] CH1 RK1
5992 01:17:30.466324 match AC timing 18
5993 01:17:30.466379 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5994 01:17:30.466434 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5995 01:17:30.466490 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5996 01:17:30.466545 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5997 01:17:30.466600 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5998 01:17:30.466655 ==
5999 01:17:30.466710 Dram Type= 6, Freq= 0, CH_0, rank 0
6000 01:17:30.466766 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6001 01:17:30.466822 ==
6002 01:17:30.466876 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6003 01:17:30.466933 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6004 01:17:30.466989 [CA 0] Center 36 (8~64) winsize 57
6005 01:17:30.467044 [CA 1] Center 36 (8~64) winsize 57
6006 01:17:30.467098 [CA 2] Center 36 (8~64) winsize 57
6007 01:17:30.467153 [CA 3] Center 36 (8~64) winsize 57
6008 01:17:30.467208 [CA 4] Center 36 (8~64) winsize 57
6009 01:17:30.467263 [CA 5] Center 36 (8~64) winsize 57
6010 01:17:30.467317
6011 01:17:30.467384 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6012 01:17:30.467435
6013 01:17:30.467486 [CATrainingPosCal] consider 1 rank data
6014 01:17:30.467537 u2DelayCellTimex100 = 270/100 ps
6015 01:17:30.467588 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6016 01:17:30.467640 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6017 01:17:30.467691 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6018 01:17:30.467743 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6019 01:17:30.467794 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6020 01:17:30.467845 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6021 01:17:30.467896
6022 01:17:30.467947 CA PerBit enable=1, Macro0, CA PI delay=36
6023 01:17:30.467998
6024 01:17:30.468049 [CBTSetCACLKResult] CA Dly = 36
6025 01:17:30.468100 CS Dly: 1 (0~32)
6026 01:17:30.468151 ==
6027 01:17:30.468203 Dram Type= 6, Freq= 0, CH_0, rank 1
6028 01:17:30.468254 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6029 01:17:30.468306 ==
6030 01:17:30.468357 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6031 01:17:30.468409 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6032 01:17:30.468461 [CA 0] Center 36 (8~64) winsize 57
6033 01:17:30.468513 [CA 1] Center 36 (8~64) winsize 57
6034 01:17:30.468564 [CA 2] Center 36 (8~64) winsize 57
6035 01:17:30.468615 [CA 3] Center 36 (8~64) winsize 57
6036 01:17:30.468666 [CA 4] Center 36 (8~64) winsize 57
6037 01:17:30.468717 [CA 5] Center 36 (8~64) winsize 57
6038 01:17:30.468767
6039 01:17:30.468818 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6040 01:17:30.468869
6041 01:17:30.469115 [CATrainingPosCal] consider 2 rank data
6042 01:17:30.469173 u2DelayCellTimex100 = 270/100 ps
6043 01:17:30.469226 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6044 01:17:30.469278 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6045 01:17:30.469330 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6046 01:17:30.469382 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6047 01:17:30.469434 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6048 01:17:30.469485 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6049 01:17:30.469537
6050 01:17:30.469588 CA PerBit enable=1, Macro0, CA PI delay=36
6051 01:17:30.469639
6052 01:17:30.469690 [CBTSetCACLKResult] CA Dly = 36
6053 01:17:30.469741 CS Dly: 1 (0~32)
6054 01:17:30.469793
6055 01:17:30.469844 ----->DramcWriteLeveling(PI) begin...
6056 01:17:30.469897 ==
6057 01:17:30.469948 Dram Type= 6, Freq= 0, CH_0, rank 0
6058 01:17:30.470000 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6059 01:17:30.470090 ==
6060 01:17:30.470141 Write leveling (Byte 0): 32 => 0
6061 01:17:30.470192 Write leveling (Byte 1): 32 => 0
6062 01:17:30.470243 DramcWriteLeveling(PI) end<-----
6063 01:17:30.470294
6064 01:17:30.470345 ==
6065 01:17:30.470396 Dram Type= 6, Freq= 0, CH_0, rank 0
6066 01:17:30.470447 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6067 01:17:30.470500 ==
6068 01:17:30.470551 [Gating] SW mode calibration
6069 01:17:30.470603 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6070 01:17:30.470656 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6071 01:17:30.470708 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6072 01:17:30.470760 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6073 01:17:30.470811 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6074 01:17:30.470863 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6075 01:17:30.470915 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6076 01:17:30.470966 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6077 01:17:30.471017 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6078 01:17:30.471069 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6079 01:17:30.471120 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6080 01:17:30.471171 Total UI for P1: 0, mck2ui 16
6081 01:17:30.471223 best dqsien dly found for B0: ( 0, 10, 16)
6082 01:17:30.471275 Total UI for P1: 0, mck2ui 16
6083 01:17:30.471327 best dqsien dly found for B1: ( 0, 10, 24)
6084 01:17:30.471379 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6085 01:17:30.471431 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6086 01:17:30.471484
6087 01:17:30.471536 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6088 01:17:30.471588 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6089 01:17:30.471640 [Gating] SW calibration Done
6090 01:17:30.471692 ==
6091 01:17:30.471765 Dram Type= 6, Freq= 0, CH_0, rank 0
6092 01:17:30.471831 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6093 01:17:30.471884 ==
6094 01:17:30.471937 RX Vref Scan: 0
6095 01:17:30.471988
6096 01:17:30.472040 RX Vref 0 -> 0, step: 1
6097 01:17:30.472092
6098 01:17:30.472144 RX Delay -410 -> 252, step: 16
6099 01:17:30.472195 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6100 01:17:30.472248 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6101 01:17:30.472300 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6102 01:17:30.472352 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6103 01:17:30.472405 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6104 01:17:30.472457 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6105 01:17:30.472509 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6106 01:17:30.472561 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6107 01:17:30.472612 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6108 01:17:30.472664 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6109 01:17:30.472716 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6110 01:17:30.472768 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6111 01:17:30.472820 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6112 01:17:30.472872 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6113 01:17:30.472924 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6114 01:17:30.472976 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6115 01:17:30.473028 ==
6116 01:17:30.473080 Dram Type= 6, Freq= 0, CH_0, rank 0
6117 01:17:30.473133 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6118 01:17:30.473185 ==
6119 01:17:30.473237 DQS Delay:
6120 01:17:30.473289 DQS0 = 51, DQS1 = 59
6121 01:17:30.473342 DQM Delay:
6122 01:17:30.473394 DQM0 = 12, DQM1 = 16
6123 01:17:30.473446 DQ Delay:
6124 01:17:30.473498 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6125 01:17:30.473550 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6126 01:17:30.473602 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6127 01:17:30.473654 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6128 01:17:30.473706
6129 01:17:30.473757
6130 01:17:30.473809 ==
6131 01:17:30.473861 Dram Type= 6, Freq= 0, CH_0, rank 0
6132 01:17:30.473914 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6133 01:17:30.473966 ==
6134 01:17:30.474018
6135 01:17:30.474110
6136 01:17:30.474162 TX Vref Scan disable
6137 01:17:30.474214 == TX Byte 0 ==
6138 01:17:30.474266 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6139 01:17:30.474319 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6140 01:17:30.474371 == TX Byte 1 ==
6141 01:17:30.474423 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6142 01:17:30.474475 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6143 01:17:30.474527 ==
6144 01:17:30.474580 Dram Type= 6, Freq= 0, CH_0, rank 0
6145 01:17:30.474634 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6146 01:17:30.474687 ==
6147 01:17:30.474739
6148 01:17:30.474791
6149 01:17:30.474843 TX Vref Scan disable
6150 01:17:30.474895 == TX Byte 0 ==
6151 01:17:30.474947 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6152 01:17:30.474999 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6153 01:17:30.475052 == TX Byte 1 ==
6154 01:17:30.475104 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6155 01:17:30.475156 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6156 01:17:30.475208
6157 01:17:30.475260 [DATLAT]
6158 01:17:30.475312 Freq=400, CH0 RK0
6159 01:17:30.475363
6160 01:17:30.475415 DATLAT Default: 0xf
6161 01:17:30.475467 0, 0xFFFF, sum = 0
6162 01:17:30.475520 1, 0xFFFF, sum = 0
6163 01:17:30.475574 2, 0xFFFF, sum = 0
6164 01:17:30.475627 3, 0xFFFF, sum = 0
6165 01:17:30.475679 4, 0xFFFF, sum = 0
6166 01:17:30.475731 5, 0xFFFF, sum = 0
6167 01:17:30.475784 6, 0xFFFF, sum = 0
6168 01:17:30.475836 7, 0xFFFF, sum = 0
6169 01:17:30.475889 8, 0xFFFF, sum = 0
6170 01:17:30.475942 9, 0xFFFF, sum = 0
6171 01:17:30.475995 10, 0xFFFF, sum = 0
6172 01:17:30.476048 11, 0xFFFF, sum = 0
6173 01:17:30.476101 12, 0x0, sum = 1
6174 01:17:30.476153 13, 0x0, sum = 2
6175 01:17:30.476206 14, 0x0, sum = 3
6176 01:17:30.476258 15, 0x0, sum = 4
6177 01:17:30.476311 best_step = 13
6178 01:17:30.476363
6179 01:17:30.476415 ==
6180 01:17:30.476657 Dram Type= 6, Freq= 0, CH_0, rank 0
6181 01:17:30.476715 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6182 01:17:30.476803 ==
6183 01:17:30.476856 RX Vref Scan: 1
6184 01:17:30.476909
6185 01:17:30.476961 RX Vref 0 -> 0, step: 1
6186 01:17:30.477014
6187 01:17:30.477065 RX Delay -359 -> 252, step: 8
6188 01:17:30.477118
6189 01:17:30.477170 Set Vref, RX VrefLevel [Byte0]: 46
6190 01:17:30.477223 [Byte1]: 51
6191 01:17:30.477275
6192 01:17:30.477327 Final RX Vref Byte 0 = 46 to rank0
6193 01:17:30.477380 Final RX Vref Byte 1 = 51 to rank0
6194 01:17:30.477432 Final RX Vref Byte 0 = 46 to rank1
6195 01:17:30.477485 Final RX Vref Byte 1 = 51 to rank1==
6196 01:17:30.477537 Dram Type= 6, Freq= 0, CH_0, rank 0
6197 01:17:30.477590 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6198 01:17:30.477642 ==
6199 01:17:30.477694 DQS Delay:
6200 01:17:30.477747 DQS0 = 52, DQS1 = 68
6201 01:17:30.477799 DQM Delay:
6202 01:17:30.477851 DQM0 = 9, DQM1 = 17
6203 01:17:30.477903 DQ Delay:
6204 01:17:30.477955 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =4
6205 01:17:30.478008 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6206 01:17:30.478099 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6207 01:17:30.478151 DQ12 =28, DQ13 =24, DQ14 =28, DQ15 =28
6208 01:17:30.478203
6209 01:17:30.478256
6210 01:17:30.478308 [DQSOSCAuto] RK0, (LSB)MR18= 0x9393, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
6211 01:17:30.478362 CH0 RK0: MR19=C0C, MR18=9393
6212 01:17:30.478414 CH0_RK0: MR19=0xC0C, MR18=0x9393, DQSOSC=391, MR23=63, INC=386, DEC=257
6213 01:17:30.478467 ==
6214 01:17:30.478520 Dram Type= 6, Freq= 0, CH_0, rank 1
6215 01:17:30.478572 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6216 01:17:30.478625 ==
6217 01:17:30.478677 [Gating] SW mode calibration
6218 01:17:30.478730 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6219 01:17:30.478783 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6220 01:17:30.478836 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6221 01:17:30.478888 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6222 01:17:30.478941 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6223 01:17:30.478994 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6224 01:17:30.479046 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6225 01:17:30.479098 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6226 01:17:30.479150 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6227 01:17:30.479202 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6228 01:17:30.479254 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6229 01:17:30.479306 Total UI for P1: 0, mck2ui 16
6230 01:17:30.479358 best dqsien dly found for B0: ( 0, 10, 16)
6231 01:17:30.479423 Total UI for P1: 0, mck2ui 16
6232 01:17:30.479477 best dqsien dly found for B1: ( 0, 10, 24)
6233 01:17:30.479530 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6234 01:17:30.479582 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6235 01:17:30.479634
6236 01:17:30.479685 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6237 01:17:30.479737 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6238 01:17:30.479789 [Gating] SW calibration Done
6239 01:17:30.479841 ==
6240 01:17:30.479893 Dram Type= 6, Freq= 0, CH_0, rank 1
6241 01:17:30.479946 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6242 01:17:30.479998 ==
6243 01:17:30.480051 RX Vref Scan: 0
6244 01:17:30.480103
6245 01:17:30.480154 RX Vref 0 -> 0, step: 1
6246 01:17:30.480206
6247 01:17:30.480258 RX Delay -410 -> 252, step: 16
6248 01:17:30.480310 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6249 01:17:30.480362 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6250 01:17:30.480415 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6251 01:17:30.480467 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6252 01:17:30.480519 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6253 01:17:30.480571 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6254 01:17:30.480623 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6255 01:17:30.480676 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6256 01:17:30.480728 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6257 01:17:30.480779 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6258 01:17:30.480831 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6259 01:17:30.480884 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6260 01:17:30.480936 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6261 01:17:30.480988 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6262 01:17:30.481040 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6263 01:17:30.481092 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6264 01:17:30.481144 ==
6265 01:17:30.481196 Dram Type= 6, Freq= 0, CH_0, rank 1
6266 01:17:30.481248 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6267 01:17:30.481300 ==
6268 01:17:30.481352 DQS Delay:
6269 01:17:30.481405 DQS0 = 43, DQS1 = 59
6270 01:17:30.481457 DQM Delay:
6271 01:17:30.481509 DQM0 = 7, DQM1 = 15
6272 01:17:30.481561 DQ Delay:
6273 01:17:30.481612 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6274 01:17:30.481664 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6275 01:17:30.481716 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6276 01:17:30.481768 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6277 01:17:30.481820
6278 01:17:30.481871
6279 01:17:30.481923 ==
6280 01:17:30.482005 Dram Type= 6, Freq= 0, CH_0, rank 1
6281 01:17:30.482127 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6282 01:17:30.482216 ==
6283 01:17:30.482305
6284 01:17:30.482396
6285 01:17:30.482491 TX Vref Scan disable
6286 01:17:30.482591 == TX Byte 0 ==
6287 01:17:30.482689 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6288 01:17:30.482789 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6289 01:17:30.482886 == TX Byte 1 ==
6290 01:17:30.482983 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6291 01:17:30.483082 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6292 01:17:30.483178 ==
6293 01:17:30.483275 Dram Type= 6, Freq= 0, CH_0, rank 1
6294 01:17:30.483372 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6295 01:17:30.483467 ==
6296 01:17:30.483561
6297 01:17:30.483655
6298 01:17:30.483749 TX Vref Scan disable
6299 01:17:30.483843 == TX Byte 0 ==
6300 01:17:30.483936 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6301 01:17:30.484032 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6302 01:17:30.484125 == TX Byte 1 ==
6303 01:17:30.484220 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6304 01:17:30.484316 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6305 01:17:30.484410
6306 01:17:30.484504 [DATLAT]
6307 01:17:30.484597 Freq=400, CH0 RK1
6308 01:17:30.484692
6309 01:17:30.484786 DATLAT Default: 0xd
6310 01:17:30.484880 0, 0xFFFF, sum = 0
6311 01:17:30.484977 1, 0xFFFF, sum = 0
6312 01:17:30.485072 2, 0xFFFF, sum = 0
6313 01:17:30.485168 3, 0xFFFF, sum = 0
6314 01:17:30.485265 4, 0xFFFF, sum = 0
6315 01:17:30.485361 5, 0xFFFF, sum = 0
6316 01:17:30.485663 6, 0xFFFF, sum = 0
6317 01:17:30.485768 7, 0xFFFF, sum = 0
6318 01:17:30.485869 8, 0xFFFF, sum = 0
6319 01:17:30.485965 9, 0xFFFF, sum = 0
6320 01:17:30.486100 10, 0xFFFF, sum = 0
6321 01:17:30.486198 11, 0xFFFF, sum = 0
6322 01:17:30.486294 12, 0x0, sum = 1
6323 01:17:30.486391 13, 0x0, sum = 2
6324 01:17:30.486488 14, 0x0, sum = 3
6325 01:17:30.486583 15, 0x0, sum = 4
6326 01:17:30.486678 best_step = 13
6327 01:17:30.486773
6328 01:17:30.486867 ==
6329 01:17:30.486964 Dram Type= 6, Freq= 0, CH_0, rank 1
6330 01:17:30.487060 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6331 01:17:30.487155 ==
6332 01:17:30.487250 RX Vref Scan: 0
6333 01:17:30.487346
6334 01:17:30.487439 RX Vref 0 -> 0, step: 1
6335 01:17:30.487533
6336 01:17:30.487627 RX Delay -359 -> 252, step: 8
6337 01:17:30.487722 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6338 01:17:30.487819 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6339 01:17:30.487889 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6340 01:17:30.487946 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6341 01:17:30.488000 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6342 01:17:30.488053 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6343 01:17:30.488106 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6344 01:17:30.488158 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6345 01:17:30.488209 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6346 01:17:30.488261 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6347 01:17:30.488312 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6348 01:17:30.488364 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6349 01:17:30.488415 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6350 01:17:30.488467 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6351 01:17:30.488518 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6352 01:17:30.488569 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6353 01:17:30.488621 ==
6354 01:17:30.488672 Dram Type= 6, Freq= 0, CH_0, rank 1
6355 01:17:30.488724 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6356 01:17:30.488776 ==
6357 01:17:30.488827 DQS Delay:
6358 01:17:30.488879 DQS0 = 52, DQS1 = 64
6359 01:17:30.488930 DQM Delay:
6360 01:17:30.488981 DQM0 = 10, DQM1 = 14
6361 01:17:30.489033 DQ Delay:
6362 01:17:30.489085 DQ0 =4, DQ1 =12, DQ2 =8, DQ3 =4
6363 01:17:30.489137 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6364 01:17:30.489189 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6365 01:17:30.489241 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6366 01:17:30.489292
6367 01:17:30.489343
6368 01:17:30.489394 [DQSOSCAuto] RK1, (LSB)MR18= 0xc4c4, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 385 ps
6369 01:17:30.489447 CH0 RK1: MR19=C0C, MR18=C4C4
6370 01:17:30.489499 CH0_RK1: MR19=0xC0C, MR18=0xC4C4, DQSOSC=385, MR23=63, INC=398, DEC=265
6371 01:17:30.489551 [RxdqsGatingPostProcess] freq 400
6372 01:17:30.489602 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6373 01:17:30.489654 Pre-setting of DQS Precalculation
6374 01:17:30.489705 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6375 01:17:30.489758 ==
6376 01:17:30.489809 Dram Type= 6, Freq= 0, CH_1, rank 0
6377 01:17:30.489861 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6378 01:17:30.489912 ==
6379 01:17:30.489963 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6380 01:17:30.490015 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6381 01:17:30.490106 [CA 0] Center 36 (8~64) winsize 57
6382 01:17:30.490191 [CA 1] Center 36 (8~64) winsize 57
6383 01:17:30.490247 [CA 2] Center 36 (8~64) winsize 57
6384 01:17:30.490299 [CA 3] Center 36 (8~64) winsize 57
6385 01:17:30.490351 [CA 4] Center 36 (8~64) winsize 57
6386 01:17:30.490403 [CA 5] Center 36 (8~64) winsize 57
6387 01:17:30.490454
6388 01:17:30.490505 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6389 01:17:30.490557
6390 01:17:30.490608 [CATrainingPosCal] consider 1 rank data
6391 01:17:30.490660 u2DelayCellTimex100 = 270/100 ps
6392 01:17:30.490711 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6393 01:17:30.490763 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6394 01:17:30.490815 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6395 01:17:30.490866 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6396 01:17:30.490917 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6397 01:17:30.490969 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6398 01:17:30.491020
6399 01:17:30.491071 CA PerBit enable=1, Macro0, CA PI delay=36
6400 01:17:30.491123
6401 01:17:30.491174 [CBTSetCACLKResult] CA Dly = 36
6402 01:17:30.491226 CS Dly: 1 (0~32)
6403 01:17:30.491285 ==
6404 01:17:30.491337 Dram Type= 6, Freq= 0, CH_1, rank 1
6405 01:17:30.491389 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6406 01:17:30.491441 ==
6407 01:17:30.491492 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6408 01:17:30.491544 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6409 01:17:30.491597 [CA 0] Center 36 (8~64) winsize 57
6410 01:17:30.491649 [CA 1] Center 36 (8~64) winsize 57
6411 01:17:30.491701 [CA 2] Center 36 (8~64) winsize 57
6412 01:17:30.491752 [CA 3] Center 36 (8~64) winsize 57
6413 01:17:30.491803 [CA 4] Center 36 (8~64) winsize 57
6414 01:17:30.491856 [CA 5] Center 36 (8~64) winsize 57
6415 01:17:30.491907
6416 01:17:30.491958 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6417 01:17:30.492009
6418 01:17:30.492060 [CATrainingPosCal] consider 2 rank data
6419 01:17:30.492112 u2DelayCellTimex100 = 270/100 ps
6420 01:17:30.492163 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6421 01:17:30.492214 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6422 01:17:30.492266 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6423 01:17:30.492317 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6424 01:17:30.492368 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6425 01:17:30.492419 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6426 01:17:30.492470
6427 01:17:30.492521 CA PerBit enable=1, Macro0, CA PI delay=36
6428 01:17:30.492573
6429 01:17:30.492623 [CBTSetCACLKResult] CA Dly = 36
6430 01:17:30.492674 CS Dly: 1 (0~32)
6431 01:17:30.492726
6432 01:17:30.492777 ----->DramcWriteLeveling(PI) begin...
6433 01:17:30.492830 ==
6434 01:17:30.492881 Dram Type= 6, Freq= 0, CH_1, rank 0
6435 01:17:30.492932 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6436 01:17:30.492984 ==
6437 01:17:30.493035 Write leveling (Byte 0): 32 => 0
6438 01:17:30.493086 Write leveling (Byte 1): 32 => 0
6439 01:17:30.493137 DramcWriteLeveling(PI) end<-----
6440 01:17:30.493188
6441 01:17:30.493239 ==
6442 01:17:30.493289 Dram Type= 6, Freq= 0, CH_1, rank 0
6443 01:17:30.493340 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6444 01:17:30.493394 ==
6445 01:17:30.493463 [Gating] SW mode calibration
6446 01:17:30.493748 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6447 01:17:30.493844 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6448 01:17:30.493899 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6449 01:17:30.493953 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6450 01:17:30.494006 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6451 01:17:30.494099 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6452 01:17:30.494152 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6453 01:17:30.494206 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6454 01:17:30.494258 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6455 01:17:30.494310 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6456 01:17:30.494362 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6457 01:17:30.494414 Total UI for P1: 0, mck2ui 16
6458 01:17:30.494467 best dqsien dly found for B0: ( 0, 10, 16)
6459 01:17:30.494519 Total UI for P1: 0, mck2ui 16
6460 01:17:30.494571 best dqsien dly found for B1: ( 0, 10, 16)
6461 01:17:30.494622 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6462 01:17:30.494674 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6463 01:17:30.494726
6464 01:17:30.494777 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6465 01:17:30.494828 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6466 01:17:30.494879 [Gating] SW calibration Done
6467 01:17:30.494930 ==
6468 01:17:30.494982 Dram Type= 6, Freq= 0, CH_1, rank 0
6469 01:17:30.495033 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6470 01:17:30.495085 ==
6471 01:17:30.495136 RX Vref Scan: 0
6472 01:17:30.495188
6473 01:17:30.495239 RX Vref 0 -> 0, step: 1
6474 01:17:30.495290
6475 01:17:30.495342 RX Delay -410 -> 252, step: 16
6476 01:17:30.495393 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6477 01:17:30.495445 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6478 01:17:30.495496 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6479 01:17:30.495547 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6480 01:17:30.495598 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6481 01:17:30.495650 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6482 01:17:30.495701 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6483 01:17:30.495752 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6484 01:17:30.495803 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6485 01:17:30.495854 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6486 01:17:30.495905 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6487 01:17:30.495956 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6488 01:17:30.496007 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6489 01:17:30.496058 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6490 01:17:30.496110 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6491 01:17:30.496161 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6492 01:17:30.496211 ==
6493 01:17:30.496263 Dram Type= 6, Freq= 0, CH_1, rank 0
6494 01:17:30.496313 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6495 01:17:30.496365 ==
6496 01:17:30.496416 DQS Delay:
6497 01:17:30.496467 DQS0 = 43, DQS1 = 59
6498 01:17:30.496519 DQM Delay:
6499 01:17:30.496570 DQM0 = 7, DQM1 = 16
6500 01:17:30.496621 DQ Delay:
6501 01:17:30.496673 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6502 01:17:30.496724 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6503 01:17:30.496775 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6504 01:17:30.496826 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =32
6505 01:17:30.496877
6506 01:17:30.496927
6507 01:17:30.496978 ==
6508 01:17:30.497029 Dram Type= 6, Freq= 0, CH_1, rank 0
6509 01:17:30.497080 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6510 01:17:30.497132 ==
6511 01:17:30.497183
6512 01:17:30.497233
6513 01:17:30.497284 TX Vref Scan disable
6514 01:17:30.497334 == TX Byte 0 ==
6515 01:17:30.497386 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6516 01:17:30.497437 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6517 01:17:30.497488 == TX Byte 1 ==
6518 01:17:30.497540 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6519 01:17:30.497591 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6520 01:17:30.497643 ==
6521 01:17:30.497694 Dram Type= 6, Freq= 0, CH_1, rank 0
6522 01:17:30.497746 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6523 01:17:30.497798 ==
6524 01:17:30.497849
6525 01:17:30.497899
6526 01:17:30.497950 TX Vref Scan disable
6527 01:17:30.498001 == TX Byte 0 ==
6528 01:17:30.498109 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6529 01:17:30.498176 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6530 01:17:30.498228 == TX Byte 1 ==
6531 01:17:30.498280 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6532 01:17:30.498333 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6533 01:17:30.498385
6534 01:17:30.498436 [DATLAT]
6535 01:17:30.498488 Freq=400, CH1 RK0
6536 01:17:30.498540
6537 01:17:30.498591 DATLAT Default: 0xf
6538 01:17:30.498642 0, 0xFFFF, sum = 0
6539 01:17:30.498695 1, 0xFFFF, sum = 0
6540 01:17:30.498748 2, 0xFFFF, sum = 0
6541 01:17:30.498800 3, 0xFFFF, sum = 0
6542 01:17:30.498852 4, 0xFFFF, sum = 0
6543 01:17:30.498904 5, 0xFFFF, sum = 0
6544 01:17:30.498957 6, 0xFFFF, sum = 0
6545 01:17:30.499009 7, 0xFFFF, sum = 0
6546 01:17:30.499061 8, 0xFFFF, sum = 0
6547 01:17:30.499113 9, 0xFFFF, sum = 0
6548 01:17:30.499165 10, 0xFFFF, sum = 0
6549 01:17:30.499217 11, 0xFFFF, sum = 0
6550 01:17:30.499269 12, 0x0, sum = 1
6551 01:17:30.499321 13, 0x0, sum = 2
6552 01:17:30.499374 14, 0x0, sum = 3
6553 01:17:30.499426 15, 0x0, sum = 4
6554 01:17:30.499478 best_step = 13
6555 01:17:30.499529
6556 01:17:30.499580 ==
6557 01:17:30.499631 Dram Type= 6, Freq= 0, CH_1, rank 0
6558 01:17:30.499683 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6559 01:17:30.499734 ==
6560 01:17:30.499786 RX Vref Scan: 1
6561 01:17:30.499837
6562 01:17:30.499887 RX Vref 0 -> 0, step: 1
6563 01:17:30.499939
6564 01:17:30.499991 RX Delay -359 -> 252, step: 8
6565 01:17:30.500042
6566 01:17:30.500093 Set Vref, RX VrefLevel [Byte0]: 56
6567 01:17:30.500145 [Byte1]: 51
6568 01:17:30.500196
6569 01:17:30.500247 Final RX Vref Byte 0 = 56 to rank0
6570 01:17:30.500298 Final RX Vref Byte 1 = 51 to rank0
6571 01:17:30.500350 Final RX Vref Byte 0 = 56 to rank1
6572 01:17:30.500402 Final RX Vref Byte 1 = 51 to rank1==
6573 01:17:30.500454 Dram Type= 6, Freq= 0, CH_1, rank 0
6574 01:17:30.500505 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6575 01:17:30.500557 ==
6576 01:17:30.500609 DQS Delay:
6577 01:17:30.500660 DQS0 = 48, DQS1 = 64
6578 01:17:30.500712 DQM Delay:
6579 01:17:30.500763 DQM0 = 7, DQM1 = 15
6580 01:17:30.500814 DQ Delay:
6581 01:17:30.500865 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6582 01:17:30.500916 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6583 01:17:30.500967 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6584 01:17:30.501018 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6585 01:17:30.501070
6586 01:17:30.501120
6587 01:17:30.501171 [DQSOSCAuto] RK0, (LSB)MR18= 0xdbdb, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6588 01:17:30.501415 CH1 RK0: MR19=C0C, MR18=DBDB
6589 01:17:30.501474 CH1_RK0: MR19=0xC0C, MR18=0xDBDB, DQSOSC=382, MR23=63, INC=404, DEC=269
6590 01:17:30.501528 ==
6591 01:17:30.501581 Dram Type= 6, Freq= 0, CH_1, rank 1
6592 01:17:30.501651 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6593 01:17:30.501705 ==
6594 01:17:30.501758 [Gating] SW mode calibration
6595 01:17:30.501811 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6596 01:17:30.501877 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6597 01:17:30.501930 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6598 01:17:30.501982 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6599 01:17:30.502039 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6600 01:17:30.502092 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
6601 01:17:30.502143 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6602 01:17:30.502195 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6603 01:17:30.502247 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6604 01:17:30.502299 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6605 01:17:30.502350 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6606 01:17:30.502402 Total UI for P1: 0, mck2ui 16
6607 01:17:30.502453 best dqsien dly found for B0: ( 0, 10, 16)
6608 01:17:30.502505 Total UI for P1: 0, mck2ui 16
6609 01:17:30.502557 best dqsien dly found for B1: ( 0, 10, 16)
6610 01:17:30.502609 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6611 01:17:30.502660 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6612 01:17:30.502711
6613 01:17:30.502762 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6614 01:17:30.502814 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6615 01:17:30.502866 [Gating] SW calibration Done
6616 01:17:30.502917 ==
6617 01:17:30.502969 Dram Type= 6, Freq= 0, CH_1, rank 1
6618 01:17:30.503020 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6619 01:17:30.503072 ==
6620 01:17:30.503123 RX Vref Scan: 0
6621 01:17:30.503174
6622 01:17:30.503225 RX Vref 0 -> 0, step: 1
6623 01:17:30.503277
6624 01:17:30.503328 RX Delay -410 -> 252, step: 16
6625 01:17:30.503379 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6626 01:17:30.503431 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6627 01:17:30.503483 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6628 01:17:30.503534 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6629 01:17:30.503585 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6630 01:17:30.503650 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6631 01:17:30.503703 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6632 01:17:30.503755 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6633 01:17:30.503807 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6634 01:17:30.503859 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6635 01:17:30.503936 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6636 01:17:30.504015 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6637 01:17:30.504079 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6638 01:17:30.504141 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6639 01:17:30.504194 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6640 01:17:30.504246 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6641 01:17:30.504298 ==
6642 01:17:30.504361 Dram Type= 6, Freq= 0, CH_1, rank 1
6643 01:17:30.504449 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6644 01:17:30.504530 ==
6645 01:17:30.504611 DQS Delay:
6646 01:17:30.504691 DQS0 = 43, DQS1 = 59
6647 01:17:30.504771 DQM Delay:
6648 01:17:30.504851 DQM0 = 10, DQM1 = 18
6649 01:17:30.504931 DQ Delay:
6650 01:17:30.505011 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6651 01:17:30.505092 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6652 01:17:30.505172 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6653 01:17:30.505255 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6654 01:17:30.505338
6655 01:17:30.505418
6656 01:17:30.505497 ==
6657 01:17:30.505578 Dram Type= 6, Freq= 0, CH_1, rank 1
6658 01:17:30.505658 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6659 01:17:30.505739 ==
6660 01:17:30.505819
6661 01:17:30.505898
6662 01:17:30.505978 TX Vref Scan disable
6663 01:17:30.506090 == TX Byte 0 ==
6664 01:17:30.506144 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6665 01:17:30.506197 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6666 01:17:30.506249 == TX Byte 1 ==
6667 01:17:30.506301 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6668 01:17:30.506354 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6669 01:17:30.506405 ==
6670 01:17:30.506457 Dram Type= 6, Freq= 0, CH_1, rank 1
6671 01:17:30.506509 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6672 01:17:30.506561 ==
6673 01:17:30.506612
6674 01:17:30.506663
6675 01:17:30.506713 TX Vref Scan disable
6676 01:17:30.506765 == TX Byte 0 ==
6677 01:17:30.506816 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6678 01:17:30.506868 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6679 01:17:30.506919 == TX Byte 1 ==
6680 01:17:30.506970 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6681 01:17:30.507022 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6682 01:17:30.507073
6683 01:17:30.507124 [DATLAT]
6684 01:17:30.507175 Freq=400, CH1 RK1
6685 01:17:30.507227
6686 01:17:30.507280 DATLAT Default: 0xd
6687 01:17:30.507350 0, 0xFFFF, sum = 0
6688 01:17:30.507404 1, 0xFFFF, sum = 0
6689 01:17:30.507457 2, 0xFFFF, sum = 0
6690 01:17:30.507509 3, 0xFFFF, sum = 0
6691 01:17:30.507562 4, 0xFFFF, sum = 0
6692 01:17:30.507614 5, 0xFFFF, sum = 0
6693 01:17:30.507666 6, 0xFFFF, sum = 0
6694 01:17:30.507719 7, 0xFFFF, sum = 0
6695 01:17:30.507770 8, 0xFFFF, sum = 0
6696 01:17:30.507822 9, 0xFFFF, sum = 0
6697 01:17:30.507875 10, 0xFFFF, sum = 0
6698 01:17:30.507928 11, 0xFFFF, sum = 0
6699 01:17:30.507980 12, 0x0, sum = 1
6700 01:17:30.508032 13, 0x0, sum = 2
6701 01:17:30.508085 14, 0x0, sum = 3
6702 01:17:30.508137 15, 0x0, sum = 4
6703 01:17:30.508189 best_step = 13
6704 01:17:30.508241
6705 01:17:30.508292 ==
6706 01:17:30.508343 Dram Type= 6, Freq= 0, CH_1, rank 1
6707 01:17:30.508395 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6708 01:17:30.508447 ==
6709 01:17:30.508498 RX Vref Scan: 0
6710 01:17:30.508550
6711 01:17:30.508600 RX Vref 0 -> 0, step: 1
6712 01:17:30.508652
6713 01:17:30.508703 RX Delay -359 -> 252, step: 8
6714 01:17:30.508754 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6715 01:17:30.508806 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6716 01:17:30.508858 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6717 01:17:30.508909 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6718 01:17:30.508961 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6719 01:17:30.509012 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6720 01:17:30.509063 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6721 01:17:30.509115 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6722 01:17:30.509357 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6723 01:17:30.509416 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6724 01:17:30.509469 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6725 01:17:30.509522 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6726 01:17:30.509574 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6727 01:17:30.509625 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6728 01:17:30.509677 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6729 01:17:30.509729 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6730 01:17:30.509781 ==
6731 01:17:30.509832 Dram Type= 6, Freq= 0, CH_1, rank 1
6732 01:17:30.509884 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6733 01:17:30.509936 ==
6734 01:17:30.509988 DQS Delay:
6735 01:17:30.510067 DQS0 = 48, DQS1 = 64
6736 01:17:30.510134 DQM Delay:
6737 01:17:30.510186 DQM0 = 9, DQM1 = 15
6738 01:17:30.510239 DQ Delay:
6739 01:17:30.510290 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6740 01:17:30.510342 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6741 01:17:30.510393 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6742 01:17:30.510445 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6743 01:17:30.510496
6744 01:17:30.510546
6745 01:17:30.510597 [DQSOSCAuto] RK1, (LSB)MR18= 0xa9a9, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6746 01:17:30.510650 CH1 RK1: MR19=C0C, MR18=A9A9
6747 01:17:30.510701 CH1_RK1: MR19=0xC0C, MR18=0xA9A9, DQSOSC=388, MR23=63, INC=392, DEC=261
6748 01:17:30.510753 [RxdqsGatingPostProcess] freq 400
6749 01:17:30.510805 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6750 01:17:30.510857 Pre-setting of DQS Precalculation
6751 01:17:30.510909 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6752 01:17:30.510960 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6753 01:17:30.511012 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6754 01:17:30.511064
6755 01:17:30.511116
6756 01:17:30.511167 [Calibration Summary] 800 Mbps
6757 01:17:30.511218 CH 0, Rank 0
6758 01:17:30.511269 SW Impedance : PASS
6759 01:17:30.511321 DUTY Scan : NO K
6760 01:17:30.511373 ZQ Calibration : PASS
6761 01:17:30.511424 Jitter Meter : NO K
6762 01:17:30.511475 CBT Training : PASS
6763 01:17:30.511527 Write leveling : PASS
6764 01:17:30.511579 RX DQS gating : PASS
6765 01:17:30.511630 RX DQ/DQS(RDDQC) : PASS
6766 01:17:30.511681 TX DQ/DQS : PASS
6767 01:17:30.511733 RX DATLAT : PASS
6768 01:17:30.511784 RX DQ/DQS(Engine): PASS
6769 01:17:30.511835 TX OE : NO K
6770 01:17:30.511886 All Pass.
6771 01:17:30.511938
6772 01:17:30.511989 CH 0, Rank 1
6773 01:17:30.512041 SW Impedance : PASS
6774 01:17:30.512092 DUTY Scan : NO K
6775 01:17:30.512143 ZQ Calibration : PASS
6776 01:17:30.512194 Jitter Meter : NO K
6777 01:17:30.512246 CBT Training : PASS
6778 01:17:30.512297 Write leveling : NO K
6779 01:17:30.512349 RX DQS gating : PASS
6780 01:17:30.512400 RX DQ/DQS(RDDQC) : PASS
6781 01:17:30.512451 TX DQ/DQS : PASS
6782 01:17:30.512502 RX DATLAT : PASS
6783 01:17:30.512554 RX DQ/DQS(Engine): PASS
6784 01:17:30.512605 TX OE : NO K
6785 01:17:30.512656 All Pass.
6786 01:17:30.512707
6787 01:17:30.512758 CH 1, Rank 0
6788 01:17:30.512809 SW Impedance : PASS
6789 01:17:30.512860 DUTY Scan : NO K
6790 01:17:30.512911 ZQ Calibration : PASS
6791 01:17:30.512963 Jitter Meter : NO K
6792 01:17:30.513013 CBT Training : PASS
6793 01:17:30.513065 Write leveling : PASS
6794 01:17:30.513116 RX DQS gating : PASS
6795 01:17:30.513167 RX DQ/DQS(RDDQC) : PASS
6796 01:17:30.513218 TX DQ/DQS : PASS
6797 01:17:30.513269 RX DATLAT : PASS
6798 01:17:30.513325 RX DQ/DQS(Engine): PASS
6799 01:17:30.513379 TX OE : NO K
6800 01:17:30.513431 All Pass.
6801 01:17:30.513483
6802 01:17:30.513534 CH 1, Rank 1
6803 01:17:30.513586 SW Impedance : PASS
6804 01:17:30.513637 DUTY Scan : NO K
6805 01:17:30.513688 ZQ Calibration : PASS
6806 01:17:30.513740 Jitter Meter : NO K
6807 01:17:30.513791 CBT Training : PASS
6808 01:17:30.513842 Write leveling : NO K
6809 01:17:30.513892 RX DQS gating : PASS
6810 01:17:30.513943 RX DQ/DQS(RDDQC) : PASS
6811 01:17:30.513994 TX DQ/DQS : PASS
6812 01:17:30.514089 RX DATLAT : PASS
6813 01:17:30.514169 RX DQ/DQS(Engine): PASS
6814 01:17:30.514220 TX OE : NO K
6815 01:17:30.514272 All Pass.
6816 01:17:30.514323
6817 01:17:30.514374 DramC Write-DBI off
6818 01:17:30.514439 PER_BANK_REFRESH: Hybrid Mode
6819 01:17:30.514496 TX_TRACKING: ON
6820 01:17:30.514560 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6821 01:17:30.514616 [FAST_K] Save calibration result to emmc
6822 01:17:30.514668 dramc_set_vcore_voltage set vcore to 725000
6823 01:17:30.514721 Read voltage for 1600, 0
6824 01:17:30.514773 Vio18 = 0
6825 01:17:30.514834 Vcore = 725000
6826 01:17:30.514900 Vdram = 0
6827 01:17:30.514954 Vddq = 0
6828 01:17:30.515042 Vmddr = 0
6829 01:17:30.515125 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6830 01:17:30.515217 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6831 01:17:30.515307 MEM_TYPE=3, freq_sel=13
6832 01:17:30.515429 sv_algorithm_assistance_LP4_3733
6833 01:17:30.515528 ============ PULL DRAM RESETB DOWN ============
6834 01:17:30.515612 ========== PULL DRAM RESETB DOWN end =========
6835 01:17:30.515695 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6836 01:17:30.515777 ===================================
6837 01:17:30.515858 LPDDR4 DRAM CONFIGURATION
6838 01:17:30.515939 ===================================
6839 01:17:30.516020 EX_ROW_EN[0] = 0x0
6840 01:17:30.516101 EX_ROW_EN[1] = 0x0
6841 01:17:30.516181 LP4Y_EN = 0x0
6842 01:17:30.516265 WORK_FSP = 0x1
6843 01:17:30.516345 WL = 0x5
6844 01:17:30.516426 RL = 0x5
6845 01:17:30.516506 BL = 0x2
6846 01:17:30.516586 RPST = 0x0
6847 01:17:30.516666 RD_PRE = 0x0
6848 01:17:30.516746 WR_PRE = 0x1
6849 01:17:30.516826 WR_PST = 0x1
6850 01:17:30.516906 DBI_WR = 0x0
6851 01:17:30.516986 DBI_RD = 0x0
6852 01:17:30.517066 OTF = 0x1
6853 01:17:30.517147 ===================================
6854 01:17:30.517229 ===================================
6855 01:17:30.517309 ANA top config
6856 01:17:30.517390 ===================================
6857 01:17:30.517470 DLL_ASYNC_EN = 0
6858 01:17:30.517551 ALL_SLAVE_EN = 0
6859 01:17:30.517631 NEW_RANK_MODE = 1
6860 01:17:30.517713 DLL_IDLE_MODE = 1
6861 01:17:30.517794 LP45_APHY_COMB_EN = 1
6862 01:17:30.517875 TX_ODT_DIS = 0
6863 01:17:30.517956 NEW_8X_MODE = 1
6864 01:17:30.518061 ===================================
6865 01:17:30.518129 ===================================
6866 01:17:30.518182 data_rate = 3200
6867 01:17:30.518430 CKR = 1
6868 01:17:30.518491 DQ_P2S_RATIO = 8
6869 01:17:30.518544 ===================================
6870 01:17:30.518597 CA_P2S_RATIO = 8
6871 01:17:30.518649 DQ_CA_OPEN = 0
6872 01:17:30.518700 DQ_SEMI_OPEN = 0
6873 01:17:30.518752 CA_SEMI_OPEN = 0
6874 01:17:30.518804 CA_FULL_RATE = 0
6875 01:17:30.518855 DQ_CKDIV4_EN = 0
6876 01:17:30.518906 CA_CKDIV4_EN = 0
6877 01:17:30.518958 CA_PREDIV_EN = 0
6878 01:17:30.519009 PH8_DLY = 12
6879 01:17:30.519061 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6880 01:17:30.519112 DQ_AAMCK_DIV = 4
6881 01:17:30.519164 CA_AAMCK_DIV = 4
6882 01:17:30.519215 CA_ADMCK_DIV = 4
6883 01:17:30.519266 DQ_TRACK_CA_EN = 0
6884 01:17:30.519388 CA_PICK = 1600
6885 01:17:30.519441 CA_MCKIO = 1600
6886 01:17:30.519493 MCKIO_SEMI = 0
6887 01:17:30.519544 PLL_FREQ = 3068
6888 01:17:30.519596 DQ_UI_PI_RATIO = 32
6889 01:17:30.519647 CA_UI_PI_RATIO = 0
6890 01:17:30.519699 ===================================
6891 01:17:30.519751 ===================================
6892 01:17:30.519802 memory_type:LPDDR4
6893 01:17:30.519854 GP_NUM : 10
6894 01:17:30.519906 SRAM_EN : 1
6895 01:17:30.519957 MD32_EN : 0
6896 01:17:30.520008 ===================================
6897 01:17:30.520060 [ANA_INIT] >>>>>>>>>>>>>>
6898 01:17:30.520111 <<<<<< [CONFIGURE PHASE]: ANA_TX
6899 01:17:30.520164 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6900 01:17:30.520217 ===================================
6901 01:17:30.520268 data_rate = 3200,PCW = 0X7600
6902 01:17:30.520320 ===================================
6903 01:17:30.520372 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6904 01:17:30.520424 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6905 01:17:30.520476 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6906 01:17:30.520528 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6907 01:17:30.520580 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6908 01:17:30.520632 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6909 01:17:30.520683 [ANA_INIT] flow start
6910 01:17:30.520735 [ANA_INIT] PLL >>>>>>>>
6911 01:17:30.520787 [ANA_INIT] PLL <<<<<<<<
6912 01:17:30.520839 [ANA_INIT] MIDPI >>>>>>>>
6913 01:17:30.520890 [ANA_INIT] MIDPI <<<<<<<<
6914 01:17:30.520941 [ANA_INIT] DLL >>>>>>>>
6915 01:17:30.520993 [ANA_INIT] DLL <<<<<<<<
6916 01:17:30.521051 [ANA_INIT] flow end
6917 01:17:30.521110 ============ LP4 DIFF to SE enter ============
6918 01:17:30.521163 ============ LP4 DIFF to SE exit ============
6919 01:17:30.521216 [ANA_INIT] <<<<<<<<<<<<<
6920 01:17:30.521268 [Flow] Enable top DCM control >>>>>
6921 01:17:30.521320 [Flow] Enable top DCM control <<<<<
6922 01:17:30.521371 Enable DLL master slave shuffle
6923 01:17:30.521423 ==============================================================
6924 01:17:30.521475 Gating Mode config
6925 01:17:30.521527 ==============================================================
6926 01:17:30.521578 Config description:
6927 01:17:30.521630 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6928 01:17:30.521683 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6929 01:17:30.521735 SELPH_MODE 0: By rank 1: By Phase
6930 01:17:30.521787 ==============================================================
6931 01:17:30.521839 GAT_TRACK_EN = 1
6932 01:17:30.521890 RX_GATING_MODE = 2
6933 01:17:30.521942 RX_GATING_TRACK_MODE = 2
6934 01:17:30.521993 SELPH_MODE = 1
6935 01:17:30.522059 PICG_EARLY_EN = 1
6936 01:17:30.988632 VALID_LAT_VALUE = 1
6937 01:17:30.989118 ==============================================================
6938 01:17:30.989449 Enter into Gating configuration >>>>
6939 01:17:30.989758 Exit from Gating configuration <<<<
6940 01:17:30.990080 Enter into DVFS_PRE_config >>>>>
6941 01:17:30.990379 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6942 01:17:30.990671 Exit from DVFS_PRE_config <<<<<
6943 01:17:30.990974 Enter into PICG configuration >>>>
6944 01:17:30.991293 Exit from PICG configuration <<<<
6945 01:17:30.991572 [RX_INPUT] configuration >>>>>
6946 01:17:30.991846 [RX_INPUT] configuration <<<<<
6947 01:17:30.992120 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6948 01:17:30.992393 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6949 01:17:30.992668 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6950 01:17:30.992941 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6951 01:17:30.993214 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6952 01:17:30.993483 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6953 01:17:30.993755 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6954 01:17:30.994041 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6955 01:17:30.994319 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6956 01:17:30.994588 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6957 01:17:30.994856 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6958 01:17:30.995124 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6959 01:17:30.995393 ===================================
6960 01:17:30.995661 LPDDR4 DRAM CONFIGURATION
6961 01:17:30.995936 ===================================
6962 01:17:30.996206 EX_ROW_EN[0] = 0x0
6963 01:17:30.996478 EX_ROW_EN[1] = 0x0
6964 01:17:30.996747 LP4Y_EN = 0x0
6965 01:17:30.997014 WORK_FSP = 0x1
6966 01:17:30.997279 WL = 0x5
6967 01:17:30.997547 RL = 0x5
6968 01:17:30.997813 BL = 0x2
6969 01:17:30.998096 RPST = 0x0
6970 01:17:30.998367 RD_PRE = 0x0
6971 01:17:30.998632 WR_PRE = 0x1
6972 01:17:30.999293 WR_PST = 0x1
6973 01:17:30.999601 DBI_WR = 0x0
6974 01:17:30.999878 DBI_RD = 0x0
6975 01:17:31.000151 OTF = 0x1
6976 01:17:31.000420 ===================================
6977 01:17:31.000693 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6978 01:17:31.000962 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6979 01:17:31.001231 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6980 01:17:31.001500 ===================================
6981 01:17:31.001771 LPDDR4 DRAM CONFIGURATION
6982 01:17:31.002061 ===================================
6983 01:17:31.002336 EX_ROW_EN[0] = 0x10
6984 01:17:31.002602 EX_ROW_EN[1] = 0x0
6985 01:17:31.002865 LP4Y_EN = 0x0
6986 01:17:31.003128 WORK_FSP = 0x1
6987 01:17:31.003394 WL = 0x5
6988 01:17:31.003658 RL = 0x5
6989 01:17:31.003936 BL = 0x2
6990 01:17:31.004235 RPST = 0x0
6991 01:17:31.004502 RD_PRE = 0x0
6992 01:17:31.004766 WR_PRE = 0x1
6993 01:17:31.005029 WR_PST = 0x1
6994 01:17:31.005309 DBI_WR = 0x0
6995 01:17:31.005538 DBI_RD = 0x0
6996 01:17:31.005727 OTF = 0x1
6997 01:17:31.005918 ===================================
6998 01:17:31.006138 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6999 01:17:31.006334 ==
7000 01:17:31.006524 Dram Type= 6, Freq= 0, CH_0, rank 0
7001 01:17:31.006716 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7002 01:17:31.006908 ==
7003 01:17:31.007111 [Duty_Offset_Calibration]
7004 01:17:31.007414 B0:0 B1:2 CA:1
7005 01:17:31.007645
7006 01:17:31.007840 [DutyScan_Calibration_Flow] k_type=0
7007 01:17:31.008033
7008 01:17:31.008223 ==CLK 0==
7009 01:17:31.008414 Final CLK duty delay cell = 0
7010 01:17:31.008607 [0] MAX Duty = 5156%(X100), DQS PI = 22
7011 01:17:31.008799 [0] MIN Duty = 4938%(X100), DQS PI = 52
7012 01:17:31.008990 [0] AVG Duty = 5047%(X100)
7013 01:17:31.009181
7014 01:17:31.009392 CH0 CLK Duty spec in!! Max-Min= 218%
7015 01:17:31.009590 [DutyScan_Calibration_Flow] ====Done====
7016 01:17:31.009782
7017 01:17:31.009970 [DutyScan_Calibration_Flow] k_type=1
7018 01:17:31.010194
7019 01:17:31.010394 ==DQS 0 ==
7020 01:17:31.010540 Final DQS duty delay cell = 0
7021 01:17:31.010685 [0] MAX Duty = 5125%(X100), DQS PI = 32
7022 01:17:31.010829 [0] MIN Duty = 5000%(X100), DQS PI = 8
7023 01:17:31.010972 [0] AVG Duty = 5062%(X100)
7024 01:17:31.011115
7025 01:17:31.011256 ==DQS 1 ==
7026 01:17:31.011398 Final DQS duty delay cell = 0
7027 01:17:31.011542 [0] MAX Duty = 5031%(X100), DQS PI = 6
7028 01:17:31.011684 [0] MIN Duty = 4876%(X100), DQS PI = 16
7029 01:17:31.011827 [0] AVG Duty = 4953%(X100)
7030 01:17:31.011968
7031 01:17:31.012110 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7032 01:17:31.012251
7033 01:17:31.012394 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7034 01:17:31.012537 [DutyScan_Calibration_Flow] ====Done====
7035 01:17:31.012687
7036 01:17:31.012829 [DutyScan_Calibration_Flow] k_type=3
7037 01:17:31.012971
7038 01:17:31.013111 ==DQM 0 ==
7039 01:17:31.013252 Final DQM duty delay cell = 0
7040 01:17:31.013424 [0] MAX Duty = 5187%(X100), DQS PI = 22
7041 01:17:31.013617 [0] MIN Duty = 4907%(X100), DQS PI = 42
7042 01:17:31.013831 [0] AVG Duty = 5047%(X100)
7043 01:17:31.013985
7044 01:17:31.014156 ==DQM 1 ==
7045 01:17:31.014303 Final DQM duty delay cell = 0
7046 01:17:31.014448 [0] MAX Duty = 5031%(X100), DQS PI = 52
7047 01:17:31.014594 [0] MIN Duty = 4782%(X100), DQS PI = 14
7048 01:17:31.014738 [0] AVG Duty = 4906%(X100)
7049 01:17:31.014882
7050 01:17:31.015023 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7051 01:17:31.015166
7052 01:17:31.015308 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7053 01:17:31.015446 [DutyScan_Calibration_Flow] ====Done====
7054 01:17:31.015560
7055 01:17:31.015673 [DutyScan_Calibration_Flow] k_type=2
7056 01:17:31.015787
7057 01:17:31.015901 ==DQ 0 ==
7058 01:17:31.016016 Final DQ duty delay cell = 0
7059 01:17:31.016131 [0] MAX Duty = 5218%(X100), DQS PI = 18
7060 01:17:31.016247 [0] MIN Duty = 4938%(X100), DQS PI = 56
7061 01:17:31.016362 [0] AVG Duty = 5078%(X100)
7062 01:17:31.016482
7063 01:17:31.016596 ==DQ 1 ==
7064 01:17:31.016711 Final DQ duty delay cell = -4
7065 01:17:31.016826 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7066 01:17:31.016941 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7067 01:17:31.017055 [-4] AVG Duty = 4953%(X100)
7068 01:17:31.017180
7069 01:17:31.017390 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7070 01:17:31.017519
7071 01:17:31.017637 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7072 01:17:31.017753 [DutyScan_Calibration_Flow] ====Done====
7073 01:17:31.017870 ==
7074 01:17:31.017985 Dram Type= 6, Freq= 0, CH_1, rank 0
7075 01:17:31.018120 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7076 01:17:31.018239 ==
7077 01:17:31.018354 [Duty_Offset_Calibration]
7078 01:17:31.018471 B0:0 B1:5 CA:-5
7079 01:17:31.018586
7080 01:17:31.018700 [DutyScan_Calibration_Flow] k_type=0
7081 01:17:31.018816
7082 01:17:31.018931 ==CLK 0==
7083 01:17:31.019047 Final CLK duty delay cell = 0
7084 01:17:31.019164 [0] MAX Duty = 5156%(X100), DQS PI = 22
7085 01:17:31.019279 [0] MIN Duty = 4906%(X100), DQS PI = 52
7086 01:17:31.019395 [0] AVG Duty = 5031%(X100)
7087 01:17:31.019508
7088 01:17:31.019622 CH1 CLK Duty spec in!! Max-Min= 250%
7089 01:17:31.019737 [DutyScan_Calibration_Flow] ====Done====
7090 01:17:31.019851
7091 01:17:31.019965 [DutyScan_Calibration_Flow] k_type=1
7092 01:17:31.020079
7093 01:17:31.020193 ==DQS 0 ==
7094 01:17:31.020309 Final DQS duty delay cell = 0
7095 01:17:31.020422 [0] MAX Duty = 5187%(X100), DQS PI = 20
7096 01:17:31.020518 [0] MIN Duty = 4876%(X100), DQS PI = 44
7097 01:17:31.020613 [0] AVG Duty = 5031%(X100)
7098 01:17:31.020708
7099 01:17:31.020803 ==DQS 1 ==
7100 01:17:31.020898 Final DQS duty delay cell = -4
7101 01:17:31.020993 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7102 01:17:31.021090 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7103 01:17:31.021186 [-4] AVG Duty = 4922%(X100)
7104 01:17:31.021282
7105 01:17:31.021377 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7106 01:17:31.021473
7107 01:17:31.021568 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7108 01:17:31.021663 [DutyScan_Calibration_Flow] ====Done====
7109 01:17:31.021758
7110 01:17:31.021853 [DutyScan_Calibration_Flow] k_type=3
7111 01:17:31.021950
7112 01:17:31.022057 ==DQM 0 ==
7113 01:17:31.022155 Final DQM duty delay cell = -4
7114 01:17:31.022251 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7115 01:17:31.022348 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7116 01:17:31.022444 [-4] AVG Duty = 4937%(X100)
7117 01:17:31.022541
7118 01:17:31.022637 ==DQM 1 ==
7119 01:17:31.022732 Final DQM duty delay cell = -4
7120 01:17:31.022829 [-4] MAX Duty = 5062%(X100), DQS PI = 16
7121 01:17:31.022925 [-4] MIN Duty = 4907%(X100), DQS PI = 36
7122 01:17:31.023020 [-4] AVG Duty = 4984%(X100)
7123 01:17:31.023116
7124 01:17:31.023211 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7125 01:17:31.023307
7126 01:17:31.023403 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7127 01:17:31.023499 [DutyScan_Calibration_Flow] ====Done====
7128 01:17:31.023597
7129 01:17:31.023693 [DutyScan_Calibration_Flow] k_type=2
7130 01:17:31.023789
7131 01:17:31.023885 ==DQ 0 ==
7132 01:17:31.023982 Final DQ duty delay cell = 0
7133 01:17:31.024317 [0] MAX Duty = 5093%(X100), DQS PI = 18
7134 01:17:31.024433 [0] MIN Duty = 4938%(X100), DQS PI = 48
7135 01:17:31.024534 [0] AVG Duty = 5015%(X100)
7136 01:17:31.024632
7137 01:17:31.024729 ==DQ 1 ==
7138 01:17:31.024825 Final DQ duty delay cell = 0
7139 01:17:31.024923 [0] MAX Duty = 5031%(X100), DQS PI = 4
7140 01:17:31.025021 [0] MIN Duty = 4844%(X100), DQS PI = 28
7141 01:17:31.025119 [0] AVG Duty = 4937%(X100)
7142 01:17:31.025217
7143 01:17:31.025314 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7144 01:17:31.025415
7145 01:17:31.025498 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7146 01:17:31.025582 [DutyScan_Calibration_Flow] ====Done====
7147 01:17:31.025665 nWR fixed to 30
7148 01:17:31.025750 [ModeRegInit_LP4] CH0 RK0
7149 01:17:31.025834 [ModeRegInit_LP4] CH0 RK1
7150 01:17:31.025918 [ModeRegInit_LP4] CH1 RK0
7151 01:17:31.026002 [ModeRegInit_LP4] CH1 RK1
7152 01:17:31.026101 match AC timing 4
7153 01:17:31.026186 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7154 01:17:31.026271 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7155 01:17:31.026355 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7156 01:17:31.026439 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7157 01:17:31.026523 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7158 01:17:31.026607 [MiockJmeterHQA]
7159 01:17:31.026690
7160 01:17:31.026773 [DramcMiockJmeter] u1RxGatingPI = 0
7161 01:17:31.026856 0 : 4252, 4027
7162 01:17:31.026942 4 : 4252, 4027
7163 01:17:31.027028 8 : 4363, 4137
7164 01:17:31.027112 12 : 4257, 4029
7165 01:17:31.027198 16 : 4252, 4027
7166 01:17:31.027284 20 : 4363, 4137
7167 01:17:31.027369 24 : 4363, 4137
7168 01:17:31.027453 28 : 4252, 4027
7169 01:17:31.027538 32 : 4255, 4030
7170 01:17:31.027623 36 : 4253, 4026
7171 01:17:31.027708 40 : 4361, 4137
7172 01:17:31.027791 44 : 4252, 4027
7173 01:17:31.027877 48 : 4361, 4137
7174 01:17:31.027961 52 : 4250, 4027
7175 01:17:31.028045 56 : 4250, 4026
7176 01:17:31.028130 60 : 4250, 4027
7177 01:17:31.028214 64 : 4250, 4027
7178 01:17:31.028299 68 : 4361, 4137
7179 01:17:31.028382 72 : 4250, 4027
7180 01:17:31.028467 76 : 4360, 4137
7181 01:17:31.028551 80 : 4250, 4027
7182 01:17:31.028635 84 : 4250, 4027
7183 01:17:31.028719 88 : 4250, 4026
7184 01:17:31.028804 92 : 4360, 4138
7185 01:17:31.028889 96 : 4250, 4027
7186 01:17:31.028976 100 : 4361, 1819
7187 01:17:31.029062 104 : 4361, 0
7188 01:17:31.029146 108 : 4250, 0
7189 01:17:31.029231 112 : 4250, 0
7190 01:17:31.029315 116 : 4250, 0
7191 01:17:31.029399 120 : 4361, 0
7192 01:17:31.029483 124 : 4360, 0
7193 01:17:31.029567 128 : 4253, 0
7194 01:17:31.029651 132 : 4250, 0
7195 01:17:31.029736 136 : 4250, 0
7196 01:17:31.029820 140 : 4250, 0
7197 01:17:31.029904 144 : 4250, 0
7198 01:17:31.029991 148 : 4250, 0
7199 01:17:31.030122 152 : 4250, 0
7200 01:17:31.030236 156 : 4250, 0
7201 01:17:31.030323 160 : 4361, 0
7202 01:17:31.030414 164 : 4250, 0
7203 01:17:31.030488 168 : 4250, 0
7204 01:17:31.030562 172 : 4361, 0
7205 01:17:31.030636 176 : 4360, 0
7206 01:17:31.030710 180 : 4250, 0
7207 01:17:31.030784 184 : 4250, 0
7208 01:17:31.030858 188 : 4250, 0
7209 01:17:31.030931 192 : 4250, 0
7210 01:17:31.031005 196 : 4250, 0
7211 01:17:31.031079 200 : 4250, 0
7212 01:17:31.031152 204 : 4250, 0
7213 01:17:31.031225 208 : 4250, 0
7214 01:17:31.031298 212 : 4361, 0
7215 01:17:31.031372 216 : 4250, 0
7216 01:17:31.031446 220 : 4253, 805
7217 01:17:31.031521 224 : 4366, 4125
7218 01:17:31.031596 228 : 4250, 4027
7219 01:17:31.031670 232 : 4250, 4026
7220 01:17:31.031745 236 : 4250, 4027
7221 01:17:31.031819 240 : 4250, 4027
7222 01:17:31.031893 244 : 4252, 4029
7223 01:17:31.031966 248 : 4250, 4027
7224 01:17:31.032040 252 : 4250, 4027
7225 01:17:31.032114 256 : 4250, 4027
7226 01:17:31.032188 260 : 4250, 4026
7227 01:17:31.032261 264 : 4361, 4137
7228 01:17:31.032335 268 : 4360, 4138
7229 01:17:31.032409 272 : 4247, 4024
7230 01:17:31.032483 276 : 4360, 4137
7231 01:17:31.032557 280 : 4361, 4137
7232 01:17:31.032630 284 : 4250, 4027
7233 01:17:31.032704 288 : 4250, 4027
7234 01:17:31.032777 292 : 4250, 4027
7235 01:17:31.032850 296 : 4250, 4026
7236 01:17:31.032924 300 : 4250, 4027
7237 01:17:31.032998 304 : 4250, 4027
7238 01:17:31.033073 308 : 4250, 4027
7239 01:17:31.033147 312 : 4250, 4026
7240 01:17:31.033220 316 : 4361, 4137
7241 01:17:31.033294 320 : 4361, 4138
7242 01:17:31.033368 324 : 4250, 4027
7243 01:17:31.033445 328 : 4360, 4137
7244 01:17:31.033520 332 : 4361, 4137
7245 01:17:31.033593 336 : 4250, 3729
7246 01:17:31.033667 340 : 4252, 1921
7247 01:17:31.033741
7248 01:17:31.033813 MIOCK jitter meter ch=0
7249 01:17:31.033886
7250 01:17:31.033958 1T = (340-100) = 240 dly cells
7251 01:17:31.034043 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7252 01:17:31.034119 ==
7253 01:17:31.034193 Dram Type= 6, Freq= 0, CH_0, rank 0
7254 01:17:31.034266 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7255 01:17:31.034340 ==
7256 01:17:31.034413 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7257 01:17:31.034486 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7258 01:17:31.034560 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7259 01:17:31.034632 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7260 01:17:31.034706 [CA 0] Center 42 (12~72) winsize 61
7261 01:17:31.034780 [CA 1] Center 41 (11~72) winsize 62
7262 01:17:31.034853 [CA 2] Center 37 (7~67) winsize 61
7263 01:17:31.034926 [CA 3] Center 37 (7~67) winsize 61
7264 01:17:31.035011 [CA 4] Center 35 (5~66) winsize 62
7265 01:17:31.035085 [CA 5] Center 35 (5~65) winsize 61
7266 01:17:31.035159
7267 01:17:31.035231 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7268 01:17:31.035304
7269 01:17:31.035384 [CATrainingPosCal] consider 1 rank data
7270 01:17:31.035449 u2DelayCellTimex100 = 271/100 ps
7271 01:17:31.035515 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7272 01:17:31.035580 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7273 01:17:31.035644 CA2 delay=37 (7~67),Diff = 2 PI (7 cell)
7274 01:17:31.035709 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7275 01:17:31.035774 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7276 01:17:31.035839 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7277 01:17:31.035904
7278 01:17:31.035968 CA PerBit enable=1, Macro0, CA PI delay=35
7279 01:17:31.036033
7280 01:17:31.036097 [CBTSetCACLKResult] CA Dly = 35
7281 01:17:31.036162 CS Dly: 11 (0~42)
7282 01:17:31.036227 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7283 01:17:31.036293 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7284 01:17:31.036358 ==
7285 01:17:31.036423 Dram Type= 6, Freq= 0, CH_0, rank 1
7286 01:17:31.036489 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7287 01:17:31.036555 ==
7288 01:17:31.036620 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7289 01:17:31.036686 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7290 01:17:31.036751 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7291 01:17:31.036815 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7292 01:17:31.036881 [CA 0] Center 42 (12~73) winsize 62
7293 01:17:31.036946 [CA 1] Center 42 (12~73) winsize 62
7294 01:17:31.037009 [CA 2] Center 38 (9~68) winsize 60
7295 01:17:31.037073 [CA 3] Center 38 (9~68) winsize 60
7296 01:17:31.037137 [CA 4] Center 36 (6~66) winsize 61
7297 01:17:31.037200 [CA 5] Center 36 (6~66) winsize 61
7298 01:17:31.037264
7299 01:17:31.037328 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7300 01:17:31.037392
7301 01:17:31.037659 [CATrainingPosCal] consider 2 rank data
7302 01:17:31.037731 u2DelayCellTimex100 = 271/100 ps
7303 01:17:31.037797 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7304 01:17:31.037865 CA1 delay=42 (12~72),Diff = 7 PI (25 cell)
7305 01:17:31.037930 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7306 01:17:31.037994 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7307 01:17:31.038070 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7308 01:17:31.038135 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7309 01:17:31.038199
7310 01:17:31.038262 CA PerBit enable=1, Macro0, CA PI delay=35
7311 01:17:31.038326
7312 01:17:31.038389 [CBTSetCACLKResult] CA Dly = 35
7313 01:17:31.038453 CS Dly: 11 (0~42)
7314 01:17:31.038517 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7315 01:17:31.038582 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7316 01:17:31.038646
7317 01:17:31.038709 ----->DramcWriteLeveling(PI) begin...
7318 01:17:31.038774 ==
7319 01:17:31.038838 Dram Type= 6, Freq= 0, CH_0, rank 0
7320 01:17:31.038902 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7321 01:17:31.038981 ==
7322 01:17:31.039073 Write leveling (Byte 0): 30 => 30
7323 01:17:31.039164 Write leveling (Byte 1): 26 => 26
7324 01:17:31.039231 DramcWriteLeveling(PI) end<-----
7325 01:17:31.039296
7326 01:17:31.039360 ==
7327 01:17:31.039424 Dram Type= 6, Freq= 0, CH_0, rank 0
7328 01:17:31.039489 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7329 01:17:31.039554 ==
7330 01:17:31.039619 [Gating] SW mode calibration
7331 01:17:31.039684 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7332 01:17:31.039750 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7333 01:17:31.039815 0 12 0 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
7334 01:17:31.039882 0 12 4 | B1->B0 | 2322 3434 | 1 0 | (0 0) (0 0)
7335 01:17:31.039947 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7336 01:17:31.040011 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7337 01:17:31.040076 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7338 01:17:31.040140 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7339 01:17:31.040204 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7340 01:17:31.040268 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7341 01:17:31.040331 0 13 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
7342 01:17:31.040402 0 13 4 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
7343 01:17:31.040460 0 13 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
7344 01:17:31.040518 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7345 01:17:31.040576 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7346 01:17:31.040633 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7347 01:17:31.040691 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7348 01:17:31.040749 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7349 01:17:31.040807 0 14 0 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
7350 01:17:31.040865 0 14 4 | B1->B0 | 3838 4646 | 0 0 | (1 1) (0 0)
7351 01:17:31.040923 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7352 01:17:31.040980 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7353 01:17:31.041038 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7354 01:17:31.041097 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7355 01:17:31.041154 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7356 01:17:31.041211 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7357 01:17:31.041269 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7358 01:17:31.041326 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7359 01:17:31.041383 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7360 01:17:31.041441 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7361 01:17:31.041499 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7362 01:17:31.041556 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7363 01:17:31.041614 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7364 01:17:31.041672 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7365 01:17:31.041730 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7366 01:17:31.041787 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7367 01:17:31.041845 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7368 01:17:31.041903 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7369 01:17:31.041961 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7370 01:17:31.042018 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7371 01:17:31.042084 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7372 01:17:31.042142 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7373 01:17:31.042200 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7374 01:17:31.042258 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7375 01:17:31.042315 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7376 01:17:31.042373 Total UI for P1: 0, mck2ui 16
7377 01:17:31.042431 best dqsien dly found for B0: ( 1, 1, 0)
7378 01:17:31.042490 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7379 01:17:31.042548 Total UI for P1: 0, mck2ui 16
7380 01:17:31.042606 best dqsien dly found for B1: ( 1, 1, 6)
7381 01:17:31.042664 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7382 01:17:31.042722 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7383 01:17:31.042779
7384 01:17:31.042837 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7385 01:17:31.042894 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7386 01:17:31.042952 [Gating] SW calibration Done
7387 01:17:31.043009 ==
7388 01:17:31.043066 Dram Type= 6, Freq= 0, CH_0, rank 0
7389 01:17:31.043124 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7390 01:17:31.043183 ==
7391 01:17:31.043241 RX Vref Scan: 0
7392 01:17:31.043298
7393 01:17:31.043355 RX Vref 0 -> 0, step: 1
7394 01:17:31.043412
7395 01:17:31.043469 RX Delay 0 -> 252, step: 8
7396 01:17:31.043526 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7397 01:17:31.043583 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7398 01:17:31.043641 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7399 01:17:31.043698 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7400 01:17:31.043755 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7401 01:17:31.043813 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
7402 01:17:31.044069 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7403 01:17:31.044138 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7404 01:17:31.044199 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7405 01:17:31.044258 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7406 01:17:31.044316 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7407 01:17:31.044374 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7408 01:17:31.044432 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7409 01:17:31.044490 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7410 01:17:31.044548 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7411 01:17:31.044606 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7412 01:17:31.044663 ==
7413 01:17:31.044721 Dram Type= 6, Freq= 0, CH_0, rank 0
7414 01:17:31.044779 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7415 01:17:31.044837 ==
7416 01:17:31.044895 DQS Delay:
7417 01:17:31.044952 DQS0 = 0, DQS1 = 0
7418 01:17:31.045010 DQM Delay:
7419 01:17:31.045067 DQM0 = 130, DQM1 = 124
7420 01:17:31.045124 DQ Delay:
7421 01:17:31.045182 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7422 01:17:31.045240 DQ4 =135, DQ5 =115, DQ6 =139, DQ7 =139
7423 01:17:31.045297 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
7424 01:17:31.045367 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7425 01:17:31.045419
7426 01:17:31.045470
7427 01:17:31.045522 ==
7428 01:17:31.045574 Dram Type= 6, Freq= 0, CH_0, rank 0
7429 01:17:31.045626 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7430 01:17:31.045679 ==
7431 01:17:31.045731
7432 01:17:31.045783
7433 01:17:31.045835 TX Vref Scan disable
7434 01:17:31.045887 == TX Byte 0 ==
7435 01:17:31.045939 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7436 01:17:31.045992 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7437 01:17:31.046056 == TX Byte 1 ==
7438 01:17:31.046109 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7439 01:17:31.046162 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7440 01:17:31.046214 ==
7441 01:17:31.046266 Dram Type= 6, Freq= 0, CH_0, rank 0
7442 01:17:31.046319 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7443 01:17:31.046372 ==
7444 01:17:31.046425
7445 01:17:31.046477 TX Vref early break, caculate TX vref
7446 01:17:31.046531 TX Vref=16, minBit 10, minWin=21, winSum=368
7447 01:17:31.046583 TX Vref=18, minBit 8, minWin=22, winSum=381
7448 01:17:31.046636 TX Vref=20, minBit 9, minWin=22, winSum=387
7449 01:17:31.046687 TX Vref=22, minBit 8, minWin=23, winSum=395
7450 01:17:31.046740 TX Vref=24, minBit 9, minWin=24, winSum=402
7451 01:17:31.046792 TX Vref=26, minBit 8, minWin=24, winSum=412
7452 01:17:31.046845 TX Vref=28, minBit 0, minWin=25, winSum=414
7453 01:17:31.046898 TX Vref=30, minBit 6, minWin=24, winSum=408
7454 01:17:31.046951 TX Vref=32, minBit 0, minWin=24, winSum=401
7455 01:17:31.047003 TX Vref=34, minBit 8, minWin=23, winSum=390
7456 01:17:31.047056 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 28
7457 01:17:31.047109
7458 01:17:31.047162 Final TX Range 0 Vref 28
7459 01:17:31.047215
7460 01:17:31.047267 ==
7461 01:17:31.047320 Dram Type= 6, Freq= 0, CH_0, rank 0
7462 01:17:31.047372 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7463 01:17:31.047426 ==
7464 01:17:31.047478
7465 01:17:31.047530
7466 01:17:31.047581 TX Vref Scan disable
7467 01:17:31.047634 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7468 01:17:31.047686 == TX Byte 0 ==
7469 01:17:31.047739 u2DelayCellOfst[0]=14 cells (4 PI)
7470 01:17:31.047791 u2DelayCellOfst[1]=18 cells (5 PI)
7471 01:17:31.047844 u2DelayCellOfst[2]=14 cells (4 PI)
7472 01:17:31.047896 u2DelayCellOfst[3]=14 cells (4 PI)
7473 01:17:31.047948 u2DelayCellOfst[4]=7 cells (2 PI)
7474 01:17:31.048001 u2DelayCellOfst[5]=0 cells (0 PI)
7475 01:17:31.048053 u2DelayCellOfst[6]=18 cells (5 PI)
7476 01:17:31.048105 u2DelayCellOfst[7]=18 cells (5 PI)
7477 01:17:31.048157 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7478 01:17:31.048210 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7479 01:17:31.048263 == TX Byte 1 ==
7480 01:17:31.048316 u2DelayCellOfst[8]=3 cells (1 PI)
7481 01:17:31.048368 u2DelayCellOfst[9]=0 cells (0 PI)
7482 01:17:31.048421 u2DelayCellOfst[10]=10 cells (3 PI)
7483 01:17:31.048473 u2DelayCellOfst[11]=7 cells (2 PI)
7484 01:17:31.048526 u2DelayCellOfst[12]=18 cells (5 PI)
7485 01:17:31.048578 u2DelayCellOfst[13]=18 cells (5 PI)
7486 01:17:31.048630 u2DelayCellOfst[14]=18 cells (5 PI)
7487 01:17:31.048682 u2DelayCellOfst[15]=14 cells (4 PI)
7488 01:17:31.048735 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7489 01:17:31.048787 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7490 01:17:31.048839 DramC Write-DBI on
7491 01:17:31.048892 ==
7492 01:17:31.048944 Dram Type= 6, Freq= 0, CH_0, rank 0
7493 01:17:31.048997 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7494 01:17:31.049050 ==
7495 01:17:31.049102
7496 01:17:31.049153
7497 01:17:31.049205 TX Vref Scan disable
7498 01:17:31.049257 == TX Byte 0 ==
7499 01:17:31.049310 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7500 01:17:31.049362 == TX Byte 1 ==
7501 01:17:31.049415 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7502 01:17:31.049467 DramC Write-DBI off
7503 01:17:31.049520
7504 01:17:31.049572 [DATLAT]
7505 01:17:31.049624 Freq=1600, CH0 RK0
7506 01:17:31.049676
7507 01:17:31.049728 DATLAT Default: 0xf
7508 01:17:31.049780 0, 0xFFFF, sum = 0
7509 01:17:31.049834 1, 0xFFFF, sum = 0
7510 01:17:31.049888 2, 0xFFFF, sum = 0
7511 01:17:31.049941 3, 0xFFFF, sum = 0
7512 01:17:31.049994 4, 0xFFFF, sum = 0
7513 01:17:31.050055 5, 0xFFFF, sum = 0
7514 01:17:31.050110 6, 0xFFFF, sum = 0
7515 01:17:31.050162 7, 0xFFFF, sum = 0
7516 01:17:31.050215 8, 0xFFFF, sum = 0
7517 01:17:31.050268 9, 0xFFFF, sum = 0
7518 01:17:31.050335 10, 0xFFFF, sum = 0
7519 01:17:31.050387 11, 0xFFFF, sum = 0
7520 01:17:31.050439 12, 0xFFF, sum = 0
7521 01:17:31.050490 13, 0x0, sum = 1
7522 01:17:31.050541 14, 0x0, sum = 2
7523 01:17:31.050593 15, 0x0, sum = 3
7524 01:17:31.050645 16, 0x0, sum = 4
7525 01:17:31.050697 best_step = 14
7526 01:17:31.050748
7527 01:17:31.050799 ==
7528 01:17:31.050851 Dram Type= 6, Freq= 0, CH_0, rank 0
7529 01:17:31.050902 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7530 01:17:31.050954 ==
7531 01:17:31.051005 RX Vref Scan: 1
7532 01:17:31.051056
7533 01:17:31.051107 Set Vref Range= 24 -> 127
7534 01:17:31.051158
7535 01:17:31.051208 RX Vref 24 -> 127, step: 1
7536 01:17:31.051260
7537 01:17:31.051330 RX Delay 11 -> 252, step: 4
7538 01:17:31.051383
7539 01:17:31.051433 Set Vref, RX VrefLevel [Byte0]: 24
7540 01:17:31.051485 [Byte1]: 24
7541 01:17:31.051537
7542 01:17:31.051588 Set Vref, RX VrefLevel [Byte0]: 25
7543 01:17:31.051640 [Byte1]: 25
7544 01:17:31.051691
7545 01:17:31.051742 Set Vref, RX VrefLevel [Byte0]: 26
7546 01:17:31.051793 [Byte1]: 26
7547 01:17:31.051844
7548 01:17:31.051895 Set Vref, RX VrefLevel [Byte0]: 27
7549 01:17:31.051946 [Byte1]: 27
7550 01:17:31.051997
7551 01:17:31.052048 Set Vref, RX VrefLevel [Byte0]: 28
7552 01:17:31.052099 [Byte1]: 28
7553 01:17:31.052150
7554 01:17:31.052391 Set Vref, RX VrefLevel [Byte0]: 29
7555 01:17:31.052449 [Byte1]: 29
7556 01:17:31.052501
7557 01:17:31.052553 Set Vref, RX VrefLevel [Byte0]: 30
7558 01:17:31.052605 [Byte1]: 30
7559 01:17:31.052657
7560 01:17:31.052708 Set Vref, RX VrefLevel [Byte0]: 31
7561 01:17:31.052759 [Byte1]: 31
7562 01:17:31.052810
7563 01:17:31.052862 Set Vref, RX VrefLevel [Byte0]: 32
7564 01:17:31.052914 [Byte1]: 32
7565 01:17:31.052965
7566 01:17:31.053016 Set Vref, RX VrefLevel [Byte0]: 33
7567 01:17:31.053078 [Byte1]: 33
7568 01:17:31.053133
7569 01:17:31.053184 Set Vref, RX VrefLevel [Byte0]: 34
7570 01:17:31.053236 [Byte1]: 34
7571 01:17:31.053300
7572 01:17:31.053364 Set Vref, RX VrefLevel [Byte0]: 35
7573 01:17:31.053423 [Byte1]: 35
7574 01:17:31.053489
7575 01:17:31.053556 Set Vref, RX VrefLevel [Byte0]: 36
7576 01:17:31.053615 [Byte1]: 36
7577 01:17:31.053677
7578 01:17:31.053736 Set Vref, RX VrefLevel [Byte0]: 37
7579 01:17:31.053792 [Byte1]: 37
7580 01:17:31.053861
7581 01:17:31.053918 Set Vref, RX VrefLevel [Byte0]: 38
7582 01:17:31.053981 [Byte1]: 38
7583 01:17:31.054064
7584 01:17:31.054130 Set Vref, RX VrefLevel [Byte0]: 39
7585 01:17:31.054182 [Byte1]: 39
7586 01:17:31.054233
7587 01:17:31.054284 Set Vref, RX VrefLevel [Byte0]: 40
7588 01:17:31.054336 [Byte1]: 40
7589 01:17:31.054388
7590 01:17:31.054439 Set Vref, RX VrefLevel [Byte0]: 41
7591 01:17:31.054491 [Byte1]: 41
7592 01:17:31.054542
7593 01:17:31.054593 Set Vref, RX VrefLevel [Byte0]: 42
7594 01:17:31.054644 [Byte1]: 42
7595 01:17:31.054695
7596 01:17:31.054745 Set Vref, RX VrefLevel [Byte0]: 43
7597 01:17:31.054797 [Byte1]: 43
7598 01:17:31.054848
7599 01:17:31.054898 Set Vref, RX VrefLevel [Byte0]: 44
7600 01:17:31.054950 [Byte1]: 44
7601 01:17:31.055000
7602 01:17:31.055052 Set Vref, RX VrefLevel [Byte0]: 45
7603 01:17:31.055103 [Byte1]: 45
7604 01:17:31.055154
7605 01:17:31.055204 Set Vref, RX VrefLevel [Byte0]: 46
7606 01:17:31.055256 [Byte1]: 46
7607 01:17:31.055332
7608 01:17:31.055413 Set Vref, RX VrefLevel [Byte0]: 47
7609 01:17:31.055494 [Byte1]: 47
7610 01:17:31.055574
7611 01:17:31.055654 Set Vref, RX VrefLevel [Byte0]: 48
7612 01:17:31.055734 [Byte1]: 48
7613 01:17:31.055815
7614 01:17:31.055895 Set Vref, RX VrefLevel [Byte0]: 49
7615 01:17:31.055976 [Byte1]: 49
7616 01:17:31.056055
7617 01:17:31.056135 Set Vref, RX VrefLevel [Byte0]: 50
7618 01:17:31.056215 [Byte1]: 50
7619 01:17:31.056294
7620 01:17:31.056374 Set Vref, RX VrefLevel [Byte0]: 51
7621 01:17:31.056454 [Byte1]: 51
7622 01:17:31.056534
7623 01:17:31.056614 Set Vref, RX VrefLevel [Byte0]: 52
7624 01:17:31.056694 [Byte1]: 52
7625 01:17:31.056773
7626 01:17:31.056853 Set Vref, RX VrefLevel [Byte0]: 53
7627 01:17:31.056934 [Byte1]: 53
7628 01:17:31.057013
7629 01:17:31.057093 Set Vref, RX VrefLevel [Byte0]: 54
7630 01:17:31.057173 [Byte1]: 54
7631 01:17:31.057252
7632 01:17:31.057332 Set Vref, RX VrefLevel [Byte0]: 55
7633 01:17:31.057412 [Byte1]: 55
7634 01:17:31.057492
7635 01:17:31.057571 Set Vref, RX VrefLevel [Byte0]: 56
7636 01:17:31.057652 [Byte1]: 56
7637 01:17:31.057731
7638 01:17:31.057811 Set Vref, RX VrefLevel [Byte0]: 57
7639 01:17:31.057891 [Byte1]: 57
7640 01:17:31.057970
7641 01:17:31.058083 Set Vref, RX VrefLevel [Byte0]: 58
7642 01:17:31.058178 [Byte1]: 58
7643 01:17:31.058257
7644 01:17:31.058337 Set Vref, RX VrefLevel [Byte0]: 59
7645 01:17:31.058418 [Byte1]: 59
7646 01:17:31.058497
7647 01:17:31.058577 Set Vref, RX VrefLevel [Byte0]: 60
7648 01:17:31.058657 [Byte1]: 60
7649 01:17:31.058737
7650 01:17:31.058817 Set Vref, RX VrefLevel [Byte0]: 61
7651 01:17:31.058897 [Byte1]: 61
7652 01:17:31.058977
7653 01:17:31.059057 Set Vref, RX VrefLevel [Byte0]: 62
7654 01:17:31.059137 [Byte1]: 62
7655 01:17:31.059218
7656 01:17:31.059303 Set Vref, RX VrefLevel [Byte0]: 63
7657 01:17:31.059395 [Byte1]: 63
7658 01:17:31.059451
7659 01:17:31.059503 Set Vref, RX VrefLevel [Byte0]: 64
7660 01:17:31.059554 [Byte1]: 64
7661 01:17:31.059606
7662 01:17:31.059657 Set Vref, RX VrefLevel [Byte0]: 65
7663 01:17:31.059709 [Byte1]: 65
7664 01:17:31.059759
7665 01:17:31.059810 Set Vref, RX VrefLevel [Byte0]: 66
7666 01:17:31.059861 [Byte1]: 66
7667 01:17:31.059912
7668 01:17:31.059963 Set Vref, RX VrefLevel [Byte0]: 67
7669 01:17:31.060014 [Byte1]: 67
7670 01:17:31.060065
7671 01:17:31.060116 Set Vref, RX VrefLevel [Byte0]: 68
7672 01:17:31.060167 [Byte1]: 68
7673 01:17:31.060218
7674 01:17:31.060269 Set Vref, RX VrefLevel [Byte0]: 69
7675 01:17:31.060320 [Byte1]: 69
7676 01:17:31.060371
7677 01:17:31.060422 Set Vref, RX VrefLevel [Byte0]: 70
7678 01:17:31.060473 [Byte1]: 70
7679 01:17:31.060524
7680 01:17:31.060574 Final RX Vref Byte 0 = 54 to rank0
7681 01:17:31.060625 Final RX Vref Byte 1 = 54 to rank0
7682 01:17:31.060676 Final RX Vref Byte 0 = 54 to rank1
7683 01:17:31.060728 Final RX Vref Byte 1 = 54 to rank1==
7684 01:17:31.060779 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 01:17:31.060831 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7686 01:17:31.060883 ==
7687 01:17:31.060934 DQS Delay:
7688 01:17:31.060986 DQS0 = 0, DQS1 = 0
7689 01:17:31.061037 DQM Delay:
7690 01:17:31.061089 DQM0 = 126, DQM1 = 120
7691 01:17:31.061140 DQ Delay:
7692 01:17:31.061192 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7693 01:17:31.061244 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7694 01:17:31.061295 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
7695 01:17:31.061347 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7696 01:17:31.061398
7697 01:17:31.061450
7698 01:17:31.061501
7699 01:17:31.061552 [DramC_TX_OE_Calibration] TA2
7700 01:17:31.061604 Original DQ_B0 (3 6) =30, OEN = 27
7701 01:17:31.061656 Original DQ_B1 (3 6) =30, OEN = 27
7702 01:17:31.061708 24, 0x0, End_B0=24 End_B1=24
7703 01:17:31.061761 25, 0x0, End_B0=25 End_B1=25
7704 01:17:31.061813 26, 0x0, End_B0=26 End_B1=26
7705 01:17:31.061865 27, 0x0, End_B0=27 End_B1=27
7706 01:17:31.061917 28, 0x0, End_B0=28 End_B1=28
7707 01:17:31.061969 29, 0x0, End_B0=29 End_B1=29
7708 01:17:31.062021 30, 0x0, End_B0=30 End_B1=30
7709 01:17:31.062116 31, 0x4545, End_B0=30 End_B1=30
7710 01:17:31.062169 Byte0 end_step=30 best_step=27
7711 01:17:31.062220 Byte1 end_step=30 best_step=27
7712 01:17:31.062462 Byte0 TX OE(2T, 0.5T) = (3, 3)
7713 01:17:31.062520 Byte1 TX OE(2T, 0.5T) = (3, 3)
7714 01:17:31.062572
7715 01:17:31.062624
7716 01:17:31.062675 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
7717 01:17:31.062728 CH0 RK0: MR19=303, MR18=1B1B
7718 01:17:31.062780 CH0_RK0: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
7719 01:17:31.062832
7720 01:17:31.062884 ----->DramcWriteLeveling(PI) begin...
7721 01:17:31.062936 ==
7722 01:17:31.062988 Dram Type= 6, Freq= 0, CH_0, rank 1
7723 01:17:31.063039 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7724 01:17:31.063091 ==
7725 01:17:31.063142 Write leveling (Byte 0): 29 => 29
7726 01:17:31.063194 Write leveling (Byte 1): 26 => 26
7727 01:17:31.063245 DramcWriteLeveling(PI) end<-----
7728 01:17:31.063297
7729 01:17:31.063348 ==
7730 01:17:31.063400 Dram Type= 6, Freq= 0, CH_0, rank 1
7731 01:17:31.063451 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7732 01:17:31.063503 ==
7733 01:17:31.063555 [Gating] SW mode calibration
7734 01:17:31.063606 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7735 01:17:31.063658 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7736 01:17:31.063710 0 12 0 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7737 01:17:31.063762 0 12 4 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)
7738 01:17:31.063821 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7739 01:17:31.063877 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7740 01:17:31.063929 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7741 01:17:31.063987 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7742 01:17:31.064055 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7743 01:17:31.064113 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7744 01:17:31.064171 0 13 0 | B1->B0 | 3434 2e2e | 1 1 | (1 0) (1 0)
7745 01:17:31.064225 0 13 4 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
7746 01:17:31.064310 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7747 01:17:31.064393 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7748 01:17:31.064478 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7749 01:17:31.064565 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7750 01:17:31.064650 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7751 01:17:31.064732 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7752 01:17:31.064813 0 14 0 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7753 01:17:31.064894 0 14 4 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
7754 01:17:31.064975 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7755 01:17:31.065056 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7756 01:17:31.065137 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7757 01:17:31.065218 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7758 01:17:31.065299 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7759 01:17:31.065388 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7760 01:17:31.065475 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7761 01:17:31.065561 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7762 01:17:31.065649 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7763 01:17:31.065734 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7764 01:17:31.065821 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7765 01:17:31.065904 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7766 01:17:31.065985 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7767 01:17:31.066123 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7768 01:17:31.066211 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7769 01:17:31.066297 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7770 01:17:31.066379 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7771 01:17:31.066461 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7772 01:17:31.066542 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7773 01:17:31.066623 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7774 01:17:31.066704 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7775 01:17:31.066785 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7776 01:17:31.066866 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7777 01:17:31.066947 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7778 01:17:31.067029 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7779 01:17:31.067109 Total UI for P1: 0, mck2ui 16
7780 01:17:31.067191 best dqsien dly found for B0: ( 1, 0, 30)
7781 01:17:31.067272 Total UI for P1: 0, mck2ui 16
7782 01:17:31.067354 best dqsien dly found for B1: ( 1, 1, 2)
7783 01:17:31.067435 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7784 01:17:31.067516 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7785 01:17:31.067596
7786 01:17:31.067676 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7787 01:17:31.067757 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7788 01:17:31.067838 [Gating] SW calibration Done
7789 01:17:31.067918 ==
7790 01:17:31.067999 Dram Type= 6, Freq= 0, CH_0, rank 1
7791 01:17:31.068080 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7792 01:17:31.068161 ==
7793 01:17:31.068242 RX Vref Scan: 0
7794 01:17:31.068322
7795 01:17:31.068402 RX Vref 0 -> 0, step: 1
7796 01:17:31.068482
7797 01:17:31.068562 RX Delay 0 -> 252, step: 8
7798 01:17:31.068643 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7799 01:17:31.068724 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7800 01:17:31.068805 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7801 01:17:31.068886 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7802 01:17:31.068966 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7803 01:17:31.069047 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7804 01:17:31.069128 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7805 01:17:31.069208 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7806 01:17:31.069289 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7807 01:17:31.069370 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7808 01:17:31.069451 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7809 01:17:31.069532 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7810 01:17:31.069613 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7811 01:17:31.069888 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7812 01:17:31.069976 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
7813 01:17:31.070102 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7814 01:17:31.070183 ==
7815 01:17:31.070265 Dram Type= 6, Freq= 0, CH_0, rank 1
7816 01:17:31.070346 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7817 01:17:31.070427 ==
7818 01:17:31.070507 DQS Delay:
7819 01:17:31.070587 DQS0 = 0, DQS1 = 0
7820 01:17:31.070668 DQM Delay:
7821 01:17:31.070748 DQM0 = 130, DQM1 = 123
7822 01:17:31.070828 DQ Delay:
7823 01:17:31.070909 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =123
7824 01:17:31.070990 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7825 01:17:31.071070 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7826 01:17:31.071151 DQ12 =131, DQ13 =131, DQ14 =131, DQ15 =131
7827 01:17:31.071231
7828 01:17:31.071310
7829 01:17:31.071389 ==
7830 01:17:31.071470 Dram Type= 6, Freq= 0, CH_0, rank 1
7831 01:17:31.071551 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7832 01:17:31.071631 ==
7833 01:17:31.071711
7834 01:17:31.071791
7835 01:17:31.071870 TX Vref Scan disable
7836 01:17:31.071950 == TX Byte 0 ==
7837 01:17:31.072031 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7838 01:17:31.072113 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7839 01:17:31.072193 == TX Byte 1 ==
7840 01:17:31.072274 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7841 01:17:31.072355 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7842 01:17:31.072435 ==
7843 01:17:31.072516 Dram Type= 6, Freq= 0, CH_0, rank 1
7844 01:17:31.072597 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7845 01:17:31.072677 ==
7846 01:17:31.072757
7847 01:17:31.072837 TX Vref early break, caculate TX vref
7848 01:17:31.072920 TX Vref=16, minBit 1, minWin=22, winSum=369
7849 01:17:31.073001 TX Vref=18, minBit 1, minWin=23, winSum=384
7850 01:17:31.073083 TX Vref=20, minBit 8, minWin=23, winSum=388
7851 01:17:31.073164 TX Vref=22, minBit 8, minWin=23, winSum=399
7852 01:17:31.073245 TX Vref=24, minBit 1, minWin=24, winSum=403
7853 01:17:31.073326 TX Vref=26, minBit 8, minWin=24, winSum=414
7854 01:17:31.073407 TX Vref=28, minBit 8, minWin=24, winSum=410
7855 01:17:31.073487 TX Vref=30, minBit 8, minWin=24, winSum=409
7856 01:17:31.073568 TX Vref=32, minBit 1, minWin=24, winSum=400
7857 01:17:31.073650 TX Vref=34, minBit 6, minWin=23, winSum=393
7858 01:17:31.073730 TX Vref=36, minBit 8, minWin=22, winSum=385
7859 01:17:31.073812 [TxChooseVref] Worse bit 8, Min win 24, Win sum 414, Final Vref 26
7860 01:17:31.073892
7861 01:17:31.073972 Final TX Range 0 Vref 26
7862 01:17:31.074090
7863 01:17:31.074145 ==
7864 01:17:31.074197 Dram Type= 6, Freq= 0, CH_0, rank 1
7865 01:17:31.074249 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7866 01:17:31.074302 ==
7867 01:17:31.074352
7868 01:17:31.074403
7869 01:17:31.074454 TX Vref Scan disable
7870 01:17:31.074505 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7871 01:17:31.074557 == TX Byte 0 ==
7872 01:17:31.074608 u2DelayCellOfst[0]=14 cells (4 PI)
7873 01:17:31.074660 u2DelayCellOfst[1]=18 cells (5 PI)
7874 01:17:31.074711 u2DelayCellOfst[2]=14 cells (4 PI)
7875 01:17:31.074762 u2DelayCellOfst[3]=10 cells (3 PI)
7876 01:17:31.074813 u2DelayCellOfst[4]=10 cells (3 PI)
7877 01:17:31.074876 u2DelayCellOfst[5]=0 cells (0 PI)
7878 01:17:31.074929 u2DelayCellOfst[6]=18 cells (5 PI)
7879 01:17:31.074981 u2DelayCellOfst[7]=18 cells (5 PI)
7880 01:17:31.075032 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7881 01:17:31.075084 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7882 01:17:31.075135 == TX Byte 1 ==
7883 01:17:31.075187 u2DelayCellOfst[8]=3 cells (1 PI)
7884 01:17:31.075238 u2DelayCellOfst[9]=0 cells (0 PI)
7885 01:17:31.075289 u2DelayCellOfst[10]=10 cells (3 PI)
7886 01:17:31.075341 u2DelayCellOfst[11]=3 cells (1 PI)
7887 01:17:31.075393 u2DelayCellOfst[12]=14 cells (4 PI)
7888 01:17:31.075444 u2DelayCellOfst[13]=14 cells (4 PI)
7889 01:17:31.075503 u2DelayCellOfst[14]=18 cells (5 PI)
7890 01:17:31.075566 u2DelayCellOfst[15]=14 cells (4 PI)
7891 01:17:31.075630 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7892 01:17:31.075683 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7893 01:17:31.075741 DramC Write-DBI on
7894 01:17:31.075793 ==
7895 01:17:31.075845 Dram Type= 6, Freq= 0, CH_0, rank 1
7896 01:17:31.075897 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7897 01:17:31.075951 ==
7898 01:17:31.076003
7899 01:17:31.076054
7900 01:17:31.076105 TX Vref Scan disable
7901 01:17:31.076157 == TX Byte 0 ==
7902 01:17:31.076208 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7903 01:17:31.076260 == TX Byte 1 ==
7904 01:17:31.076311 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7905 01:17:31.076362 DramC Write-DBI off
7906 01:17:31.076413
7907 01:17:31.076464 [DATLAT]
7908 01:17:31.076516 Freq=1600, CH0 RK1
7909 01:17:31.076567
7910 01:17:31.076618 DATLAT Default: 0xe
7911 01:17:31.076670 0, 0xFFFF, sum = 0
7912 01:17:31.076722 1, 0xFFFF, sum = 0
7913 01:17:31.076775 2, 0xFFFF, sum = 0
7914 01:17:31.076827 3, 0xFFFF, sum = 0
7915 01:17:31.076879 4, 0xFFFF, sum = 0
7916 01:17:31.076931 5, 0xFFFF, sum = 0
7917 01:17:31.076983 6, 0xFFFF, sum = 0
7918 01:17:31.077035 7, 0xFFFF, sum = 0
7919 01:17:31.077087 8, 0xFFFF, sum = 0
7920 01:17:31.077139 9, 0xFFFF, sum = 0
7921 01:17:31.077191 10, 0xFFFF, sum = 0
7922 01:17:31.077242 11, 0xFFFF, sum = 0
7923 01:17:31.077295 12, 0x8FFF, sum = 0
7924 01:17:31.077347 13, 0x0, sum = 1
7925 01:17:31.077399 14, 0x0, sum = 2
7926 01:17:31.077450 15, 0x0, sum = 3
7927 01:17:31.077502 16, 0x0, sum = 4
7928 01:17:31.077553 best_step = 14
7929 01:17:31.077604
7930 01:17:31.077655 ==
7931 01:17:32.290424 Dram Type= 6, Freq= 0, CH_0, rank 1
7932 01:17:32.290948 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7933 01:17:32.291316 ==
7934 01:17:32.291655 RX Vref Scan: 0
7935 01:17:32.291981
7936 01:17:32.292296 RX Vref 0 -> 0, step: 1
7937 01:17:32.292610
7938 01:17:32.292917 RX Delay 11 -> 252, step: 4
7939 01:17:32.293221 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7940 01:17:32.293594 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
7941 01:17:32.293908 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7942 01:17:32.294242 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7943 01:17:32.294544 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7944 01:17:32.294879 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7945 01:17:32.295184 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
7946 01:17:32.295483 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7947 01:17:32.295775 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7948 01:17:32.296067 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7949 01:17:32.296362 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7950 01:17:32.296658 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7951 01:17:32.296955 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7952 01:17:32.297251 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7953 01:17:32.297548 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
7954 01:17:32.298280 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7955 01:17:32.298620 ==
7956 01:17:32.298926 Dram Type= 6, Freq= 0, CH_0, rank 1
7957 01:17:32.299225 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7958 01:17:32.299526 ==
7959 01:17:32.299820 DQS Delay:
7960 01:17:32.300116 DQS0 = 0, DQS1 = 0
7961 01:17:32.300415 DQM Delay:
7962 01:17:32.300710 DQM0 = 127, DQM1 = 120
7963 01:17:32.301004 DQ Delay:
7964 01:17:32.301297 DQ0 =122, DQ1 =130, DQ2 =126, DQ3 =122
7965 01:17:32.301594 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =138
7966 01:17:32.301888 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7967 01:17:32.302209 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
7968 01:17:32.302505
7969 01:17:32.302796
7970 01:17:32.303088
7971 01:17:32.303384 [DramC_TX_OE_Calibration] TA2
7972 01:17:32.303679 Original DQ_B0 (3 6) =30, OEN = 27
7973 01:17:32.303975 Original DQ_B1 (3 6) =30, OEN = 27
7974 01:17:32.304273 24, 0x0, End_B0=24 End_B1=24
7975 01:17:32.304575 25, 0x0, End_B0=25 End_B1=25
7976 01:17:32.304876 26, 0x0, End_B0=26 End_B1=26
7977 01:17:32.305174 27, 0x0, End_B0=27 End_B1=27
7978 01:17:32.305472 28, 0x0, End_B0=28 End_B1=28
7979 01:17:32.305770 29, 0x0, End_B0=29 End_B1=29
7980 01:17:32.306088 30, 0x0, End_B0=30 End_B1=30
7981 01:17:32.306452 31, 0x4141, End_B0=30 End_B1=30
7982 01:17:32.306768 Byte0 end_step=30 best_step=27
7983 01:17:32.307119 Byte1 end_step=30 best_step=27
7984 01:17:32.307419 Byte0 TX OE(2T, 0.5T) = (3, 3)
7985 01:17:32.307714 Byte1 TX OE(2T, 0.5T) = (3, 3)
7986 01:17:32.308005
7987 01:17:32.308297
7988 01:17:32.308590 [DQSOSCAuto] RK1, (LSB)MR18= 0x2323, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
7989 01:17:32.308889 CH0 RK1: MR19=303, MR18=2323
7990 01:17:32.309187 CH0_RK1: MR19=0x303, MR18=0x2323, DQSOSC=392, MR23=63, INC=24, DEC=16
7991 01:17:32.309487 [RxdqsGatingPostProcess] freq 1600
7992 01:17:32.309779 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7993 01:17:32.310111 Pre-setting of DQS Precalculation
7994 01:17:32.310417 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7995 01:17:32.310713 ==
7996 01:17:32.311004 Dram Type= 6, Freq= 0, CH_1, rank 0
7997 01:17:32.311300 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7998 01:17:32.311595 ==
7999 01:17:32.311885 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8000 01:17:32.312179 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8001 01:17:32.312474 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8002 01:17:32.312767 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8003 01:17:32.313085 [CA 0] Center 40 (11~70) winsize 60
8004 01:17:32.313551 [CA 1] Center 41 (11~71) winsize 61
8005 01:17:32.313952 [CA 2] Center 36 (7~66) winsize 60
8006 01:17:32.314285 [CA 3] Center 35 (6~65) winsize 60
8007 01:17:32.314583 [CA 4] Center 34 (4~64) winsize 61
8008 01:17:32.314876 [CA 5] Center 34 (4~64) winsize 61
8009 01:17:32.315170
8010 01:17:32.315435 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8011 01:17:32.315644
8012 01:17:32.315846 [CATrainingPosCal] consider 1 rank data
8013 01:17:32.316055 u2DelayCellTimex100 = 271/100 ps
8014 01:17:32.316262 CA0 delay=40 (11~70),Diff = 6 PI (21 cell)
8015 01:17:32.316470 CA1 delay=41 (11~71),Diff = 7 PI (25 cell)
8016 01:17:32.316674 CA2 delay=36 (7~66),Diff = 2 PI (7 cell)
8017 01:17:32.316880 CA3 delay=35 (6~65),Diff = 1 PI (3 cell)
8018 01:17:32.317087 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8019 01:17:32.317294 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
8020 01:17:32.317497
8021 01:17:32.317701 CA PerBit enable=1, Macro0, CA PI delay=34
8022 01:17:32.317907
8023 01:17:32.318129 [CBTSetCACLKResult] CA Dly = 34
8024 01:17:32.318339 CS Dly: 8 (0~39)
8025 01:17:32.318548 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8026 01:17:32.318758 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8027 01:17:32.318964 ==
8028 01:17:32.319169 Dram Type= 6, Freq= 0, CH_1, rank 1
8029 01:17:32.319373 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8030 01:17:32.319581 ==
8031 01:17:32.319788 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8032 01:17:32.319996 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8033 01:17:32.320202 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8034 01:17:32.320407 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8035 01:17:32.320560 [CA 0] Center 41 (11~71) winsize 61
8036 01:17:32.320710 [CA 1] Center 40 (10~71) winsize 62
8037 01:17:32.320859 [CA 2] Center 36 (7~66) winsize 60
8038 01:17:32.321012 [CA 3] Center 35 (6~65) winsize 60
8039 01:17:32.321162 [CA 4] Center 34 (4~64) winsize 61
8040 01:17:32.321313 [CA 5] Center 34 (4~64) winsize 61
8041 01:17:32.321462
8042 01:17:32.321612 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8043 01:17:32.321765
8044 01:17:32.321916 [CATrainingPosCal] consider 2 rank data
8045 01:17:32.322082 u2DelayCellTimex100 = 271/100 ps
8046 01:17:32.322288 CA0 delay=40 (11~70),Diff = 6 PI (21 cell)
8047 01:17:32.322545 CA1 delay=41 (11~71),Diff = 7 PI (25 cell)
8048 01:17:32.322711 CA2 delay=36 (7~66),Diff = 2 PI (7 cell)
8049 01:17:32.322866 CA3 delay=35 (6~65),Diff = 1 PI (3 cell)
8050 01:17:32.323019 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8051 01:17:32.323173 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
8052 01:17:32.323347
8053 01:17:32.323633 CA PerBit enable=1, Macro0, CA PI delay=34
8054 01:17:32.323805
8055 01:17:32.323962 [CBTSetCACLKResult] CA Dly = 34
8056 01:17:32.324116 CS Dly: 9 (0~41)
8057 01:17:32.324270 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8058 01:17:32.324426 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8059 01:17:32.324579
8060 01:17:32.324730 ----->DramcWriteLeveling(PI) begin...
8061 01:17:32.324888 ==
8062 01:17:32.325041 Dram Type= 6, Freq= 0, CH_1, rank 0
8063 01:17:32.325196 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8064 01:17:32.325355 ==
8065 01:17:32.325477 Write leveling (Byte 0): 24 => 24
8066 01:17:32.325599 Write leveling (Byte 1): 21 => 21
8067 01:17:32.325718 DramcWriteLeveling(PI) end<-----
8068 01:17:32.325839
8069 01:17:32.325959 ==
8070 01:17:32.326104 Dram Type= 6, Freq= 0, CH_1, rank 0
8071 01:17:32.326228 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8072 01:17:32.326350 ==
8073 01:17:32.326470 [Gating] SW mode calibration
8074 01:17:32.326592 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8075 01:17:32.326714 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8076 01:17:32.326837 0 12 0 | B1->B0 | 2524 3333 | 1 0 | (0 0) (0 0)
8077 01:17:32.326957 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8078 01:17:32.327331 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8079 01:17:32.327470 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8080 01:17:32.327596 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8081 01:17:32.327722 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8082 01:17:32.327846 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8083 01:17:32.327970 0 12 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
8084 01:17:32.328092 0 13 0 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
8085 01:17:32.328215 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8086 01:17:32.328337 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8087 01:17:32.328458 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8088 01:17:32.328580 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8089 01:17:32.328702 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8090 01:17:32.328824 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8091 01:17:32.328946 0 13 28 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
8092 01:17:32.329069 0 14 0 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
8093 01:17:32.329192 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8094 01:17:32.329314 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8095 01:17:32.329437 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8096 01:17:32.329559 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8097 01:17:32.329681 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8098 01:17:32.329804 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8099 01:17:32.329926 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8100 01:17:32.330069 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8101 01:17:32.330195 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8102 01:17:32.330330 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 01:17:32.330432 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 01:17:32.330534 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 01:17:32.330635 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 01:17:32.330736 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 01:17:32.330836 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 01:17:32.330937 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 01:17:32.331038 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 01:17:32.331139 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 01:17:32.331240 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 01:17:32.331341 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 01:17:32.331441 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 01:17:32.331543 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8115 01:17:32.331645 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8116 01:17:32.331747 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8117 01:17:32.331847 Total UI for P1: 0, mck2ui 16
8118 01:17:32.331949 best dqsien dly found for B0: ( 1, 0, 26)
8119 01:17:32.332051 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8120 01:17:32.332153 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8121 01:17:32.332254 Total UI for P1: 0, mck2ui 16
8122 01:17:32.332356 best dqsien dly found for B1: ( 1, 1, 2)
8123 01:17:32.332459 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8124 01:17:32.332560 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8125 01:17:32.332660
8126 01:17:32.332761 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8127 01:17:32.332863 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8128 01:17:32.332964 [Gating] SW calibration Done
8129 01:17:32.333064 ==
8130 01:17:32.333165 Dram Type= 6, Freq= 0, CH_1, rank 0
8131 01:17:32.333267 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8132 01:17:32.333369 ==
8133 01:17:32.333470 RX Vref Scan: 0
8134 01:17:32.333571
8135 01:17:32.333671 RX Vref 0 -> 0, step: 1
8136 01:17:32.333771
8137 01:17:32.333872 RX Delay 0 -> 252, step: 8
8138 01:17:32.333973 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8139 01:17:32.334092 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8140 01:17:32.334195 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8141 01:17:32.334297 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8142 01:17:32.334398 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8143 01:17:32.334499 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8144 01:17:32.334601 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8145 01:17:32.334702 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8146 01:17:32.334804 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8147 01:17:32.334905 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8148 01:17:32.335006 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8149 01:17:32.335107 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8150 01:17:32.335208 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8151 01:17:32.335308 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8152 01:17:32.335415 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8153 01:17:32.335502 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8154 01:17:32.335589 ==
8155 01:17:32.335675 Dram Type= 6, Freq= 0, CH_1, rank 0
8156 01:17:32.335761 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8157 01:17:32.335848 ==
8158 01:17:32.335935 DQS Delay:
8159 01:17:32.336021 DQS0 = 0, DQS1 = 0
8160 01:17:32.336107 DQM Delay:
8161 01:17:32.336192 DQM0 = 130, DQM1 = 126
8162 01:17:32.336278 DQ Delay:
8163 01:17:32.336365 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8164 01:17:32.336450 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8165 01:17:32.336536 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =115
8166 01:17:32.336622 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8167 01:17:32.336708
8168 01:17:32.336792
8169 01:17:32.336878 ==
8170 01:17:32.336965 Dram Type= 6, Freq= 0, CH_1, rank 0
8171 01:17:32.337051 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8172 01:17:32.337138 ==
8173 01:17:32.337224
8174 01:17:32.337309
8175 01:17:32.337395 TX Vref Scan disable
8176 01:17:32.337482 == TX Byte 0 ==
8177 01:17:32.337568 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8178 01:17:32.337654 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8179 01:17:32.337741 == TX Byte 1 ==
8180 01:17:32.337827 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8181 01:17:32.337914 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8182 01:17:32.338000 ==
8183 01:17:32.338101 Dram Type= 6, Freq= 0, CH_1, rank 0
8184 01:17:32.338405 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8185 01:17:32.338503 ==
8186 01:17:32.338592
8187 01:17:32.338680 TX Vref early break, caculate TX vref
8188 01:17:32.338767 TX Vref=16, minBit 0, minWin=22, winSum=373
8189 01:17:32.338854 TX Vref=18, minBit 3, minWin=22, winSum=380
8190 01:17:32.338947 TX Vref=20, minBit 0, minWin=23, winSum=388
8191 01:17:32.339035 TX Vref=22, minBit 0, minWin=24, winSum=400
8192 01:17:32.339122 TX Vref=24, minBit 0, minWin=24, winSum=409
8193 01:17:32.339209 TX Vref=26, minBit 0, minWin=24, winSum=414
8194 01:17:32.339296 TX Vref=28, minBit 1, minWin=25, winSum=421
8195 01:17:32.339383 TX Vref=30, minBit 1, minWin=25, winSum=411
8196 01:17:32.339469 TX Vref=32, minBit 0, minWin=24, winSum=403
8197 01:17:32.339556 TX Vref=34, minBit 0, minWin=24, winSum=399
8198 01:17:32.339643 TX Vref=36, minBit 2, minWin=23, winSum=386
8199 01:17:32.339730 [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 28
8200 01:17:32.339818
8201 01:17:32.339904 Final TX Range 0 Vref 28
8202 01:17:32.339991
8203 01:17:32.340078 ==
8204 01:17:32.340187 Dram Type= 6, Freq= 0, CH_1, rank 0
8205 01:17:32.340276 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8206 01:17:32.340375 ==
8207 01:17:32.340452
8208 01:17:32.340526
8209 01:17:32.340601 TX Vref Scan disable
8210 01:17:32.340677 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8211 01:17:32.340753 == TX Byte 0 ==
8212 01:17:32.340829 u2DelayCellOfst[0]=14 cells (4 PI)
8213 01:17:32.340905 u2DelayCellOfst[1]=7 cells (2 PI)
8214 01:17:32.340981 u2DelayCellOfst[2]=0 cells (0 PI)
8215 01:17:32.341068 u2DelayCellOfst[3]=7 cells (2 PI)
8216 01:17:32.341144 u2DelayCellOfst[4]=7 cells (2 PI)
8217 01:17:32.341219 u2DelayCellOfst[5]=14 cells (4 PI)
8218 01:17:32.341295 u2DelayCellOfst[6]=18 cells (5 PI)
8219 01:17:32.341370 u2DelayCellOfst[7]=7 cells (2 PI)
8220 01:17:32.341446 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8221 01:17:32.341522 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8222 01:17:32.341597 == TX Byte 1 ==
8223 01:17:32.341672 u2DelayCellOfst[8]=0 cells (0 PI)
8224 01:17:32.341747 u2DelayCellOfst[9]=3 cells (1 PI)
8225 01:17:32.341822 u2DelayCellOfst[10]=7 cells (2 PI)
8226 01:17:32.341898 u2DelayCellOfst[11]=0 cells (0 PI)
8227 01:17:32.341973 u2DelayCellOfst[12]=14 cells (4 PI)
8228 01:17:32.342061 u2DelayCellOfst[13]=18 cells (5 PI)
8229 01:17:32.342139 u2DelayCellOfst[14]=18 cells (5 PI)
8230 01:17:32.342215 u2DelayCellOfst[15]=14 cells (4 PI)
8231 01:17:32.342290 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8232 01:17:32.342367 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8233 01:17:32.342443 DramC Write-DBI on
8234 01:17:32.342518 ==
8235 01:17:32.342593 Dram Type= 6, Freq= 0, CH_1, rank 0
8236 01:17:32.342669 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8237 01:17:32.342745 ==
8238 01:17:32.342820
8239 01:17:32.342895
8240 01:17:32.342969 TX Vref Scan disable
8241 01:17:32.343045 == TX Byte 0 ==
8242 01:17:32.343120 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8243 01:17:32.343196 == TX Byte 1 ==
8244 01:17:32.343271 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8245 01:17:32.343347 DramC Write-DBI off
8246 01:17:32.343422
8247 01:17:32.343496 [DATLAT]
8248 01:17:32.343572 Freq=1600, CH1 RK0
8249 01:17:32.343647
8250 01:17:32.343721 DATLAT Default: 0xf
8251 01:17:32.343797 0, 0xFFFF, sum = 0
8252 01:17:32.343874 1, 0xFFFF, sum = 0
8253 01:17:32.343950 2, 0xFFFF, sum = 0
8254 01:17:32.344025 3, 0xFFFF, sum = 0
8255 01:17:32.344101 4, 0xFFFF, sum = 0
8256 01:17:32.344177 5, 0xFFFF, sum = 0
8257 01:17:32.344252 6, 0xFFFF, sum = 0
8258 01:17:32.344328 7, 0xFFFF, sum = 0
8259 01:17:32.344405 8, 0xFFFF, sum = 0
8260 01:17:32.344481 9, 0xFFFF, sum = 0
8261 01:17:32.344556 10, 0xFFFF, sum = 0
8262 01:17:32.344632 11, 0xFFFF, sum = 0
8263 01:17:32.344709 12, 0xF7F, sum = 0
8264 01:17:32.344785 13, 0x0, sum = 1
8265 01:17:32.344861 14, 0x0, sum = 2
8266 01:17:32.344937 15, 0x0, sum = 3
8267 01:17:32.345013 16, 0x0, sum = 4
8268 01:17:32.345088 best_step = 14
8269 01:17:32.345162
8270 01:17:32.345238 ==
8271 01:17:32.345326 Dram Type= 6, Freq= 0, CH_1, rank 0
8272 01:17:32.345393 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8273 01:17:32.345461 ==
8274 01:17:32.345528 RX Vref Scan: 1
8275 01:17:32.345594
8276 01:17:32.345661 Set Vref Range= 24 -> 127
8277 01:17:32.345727
8278 01:17:32.345793 RX Vref 24 -> 127, step: 1
8279 01:17:32.345860
8280 01:17:32.345926 RX Delay 11 -> 252, step: 4
8281 01:17:32.345991
8282 01:17:32.346063 Set Vref, RX VrefLevel [Byte0]: 24
8283 01:17:32.346132 [Byte1]: 24
8284 01:17:32.346200
8285 01:17:32.346266 Set Vref, RX VrefLevel [Byte0]: 25
8286 01:17:32.346332 [Byte1]: 25
8287 01:17:32.346398
8288 01:17:32.346464 Set Vref, RX VrefLevel [Byte0]: 26
8289 01:17:32.346530 [Byte1]: 26
8290 01:17:32.346596
8291 01:17:32.346662 Set Vref, RX VrefLevel [Byte0]: 27
8292 01:17:32.346728 [Byte1]: 27
8293 01:17:32.346795
8294 01:17:32.346861 Set Vref, RX VrefLevel [Byte0]: 28
8295 01:17:32.346927 [Byte1]: 28
8296 01:17:32.346992
8297 01:17:32.347058 Set Vref, RX VrefLevel [Byte0]: 29
8298 01:17:32.347124 [Byte1]: 29
8299 01:17:32.347189
8300 01:17:32.347255 Set Vref, RX VrefLevel [Byte0]: 30
8301 01:17:32.347321 [Byte1]: 30
8302 01:17:32.347386
8303 01:17:32.347451 Set Vref, RX VrefLevel [Byte0]: 31
8304 01:17:32.347517 [Byte1]: 31
8305 01:17:32.347584
8306 01:17:32.347649 Set Vref, RX VrefLevel [Byte0]: 32
8307 01:17:32.347715 [Byte1]: 32
8308 01:17:32.347780
8309 01:17:32.347846 Set Vref, RX VrefLevel [Byte0]: 33
8310 01:17:32.347912 [Byte1]: 33
8311 01:17:32.347977
8312 01:17:32.348042 Set Vref, RX VrefLevel [Byte0]: 34
8313 01:17:32.348107 [Byte1]: 34
8314 01:17:32.348173
8315 01:17:32.348238 Set Vref, RX VrefLevel [Byte0]: 35
8316 01:17:32.348304 [Byte1]: 35
8317 01:17:32.348369
8318 01:17:32.348435 Set Vref, RX VrefLevel [Byte0]: 36
8319 01:17:32.348501 [Byte1]: 36
8320 01:17:32.348567
8321 01:17:32.348631 Set Vref, RX VrefLevel [Byte0]: 37
8322 01:17:32.348697 [Byte1]: 37
8323 01:17:32.348763
8324 01:17:32.348841 Set Vref, RX VrefLevel [Byte0]: 38
8325 01:17:32.348908 [Byte1]: 38
8326 01:17:32.348974
8327 01:17:32.349039 Set Vref, RX VrefLevel [Byte0]: 39
8328 01:17:32.349105 [Byte1]: 39
8329 01:17:32.349171
8330 01:17:32.349235 Set Vref, RX VrefLevel [Byte0]: 40
8331 01:17:32.349301 [Byte1]: 40
8332 01:17:32.349366
8333 01:17:32.349432 Set Vref, RX VrefLevel [Byte0]: 41
8334 01:17:32.349497 [Byte1]: 41
8335 01:17:32.349563
8336 01:17:32.349628 Set Vref, RX VrefLevel [Byte0]: 42
8337 01:17:32.349696 [Byte1]: 42
8338 01:17:32.349762
8339 01:17:32.349827 Set Vref, RX VrefLevel [Byte0]: 43
8340 01:17:32.349893 [Byte1]: 43
8341 01:17:32.349959
8342 01:17:32.350238 Set Vref, RX VrefLevel [Byte0]: 44
8343 01:17:32.350317 [Byte1]: 44
8344 01:17:32.350391
8345 01:17:32.350451 Set Vref, RX VrefLevel [Byte0]: 45
8346 01:17:32.350510 [Byte1]: 45
8347 01:17:32.350570
8348 01:17:32.350628 Set Vref, RX VrefLevel [Byte0]: 46
8349 01:17:32.350688 [Byte1]: 46
8350 01:17:32.350748
8351 01:17:32.350807 Set Vref, RX VrefLevel [Byte0]: 47
8352 01:17:32.350866 [Byte1]: 47
8353 01:17:32.350926
8354 01:17:32.350985 Set Vref, RX VrefLevel [Byte0]: 48
8355 01:17:32.351044 [Byte1]: 48
8356 01:17:32.351103
8357 01:17:32.351163 Set Vref, RX VrefLevel [Byte0]: 49
8358 01:17:32.351222 [Byte1]: 49
8359 01:17:32.351281
8360 01:17:32.351339 Set Vref, RX VrefLevel [Byte0]: 50
8361 01:17:32.351399 [Byte1]: 50
8362 01:17:32.351458
8363 01:17:32.351517 Set Vref, RX VrefLevel [Byte0]: 51
8364 01:17:32.351576 [Byte1]: 51
8365 01:17:32.351635
8366 01:17:32.351693 Set Vref, RX VrefLevel [Byte0]: 52
8367 01:17:32.351753 [Byte1]: 52
8368 01:17:32.351811
8369 01:17:32.351870 Set Vref, RX VrefLevel [Byte0]: 53
8370 01:17:32.351929 [Byte1]: 53
8371 01:17:32.351988
8372 01:17:32.352047 Set Vref, RX VrefLevel [Byte0]: 54
8373 01:17:32.352106 [Byte1]: 54
8374 01:17:32.352165
8375 01:17:32.352223 Set Vref, RX VrefLevel [Byte0]: 55
8376 01:17:32.352283 [Byte1]: 55
8377 01:17:32.352341
8378 01:17:32.352399 Set Vref, RX VrefLevel [Byte0]: 56
8379 01:17:32.352459 [Byte1]: 56
8380 01:17:32.352518
8381 01:17:32.352576 Set Vref, RX VrefLevel [Byte0]: 57
8382 01:17:32.352635 [Byte1]: 57
8383 01:17:32.352694
8384 01:17:32.352752 Set Vref, RX VrefLevel [Byte0]: 58
8385 01:17:32.352812 [Byte1]: 58
8386 01:17:32.352870
8387 01:17:32.352928 Set Vref, RX VrefLevel [Byte0]: 59
8388 01:17:32.352987 [Byte1]: 59
8389 01:17:32.353047
8390 01:17:32.353106 Set Vref, RX VrefLevel [Byte0]: 60
8391 01:17:32.353164 [Byte1]: 60
8392 01:17:32.353223
8393 01:17:32.353281 Set Vref, RX VrefLevel [Byte0]: 61
8394 01:17:32.353340 [Byte1]: 61
8395 01:17:32.353399
8396 01:17:32.353457 Set Vref, RX VrefLevel [Byte0]: 62
8397 01:17:32.353516 [Byte1]: 62
8398 01:17:32.353575
8399 01:17:32.353633 Set Vref, RX VrefLevel [Byte0]: 63
8400 01:17:32.353693 [Byte1]: 63
8401 01:17:32.353752
8402 01:17:32.353810 Set Vref, RX VrefLevel [Byte0]: 64
8403 01:17:32.353869 [Byte1]: 64
8404 01:17:32.353927
8405 01:17:32.353985 Set Vref, RX VrefLevel [Byte0]: 65
8406 01:17:32.354061 [Byte1]: 65
8407 01:17:32.354124
8408 01:17:32.354183 Set Vref, RX VrefLevel [Byte0]: 66
8409 01:17:32.354243 [Byte1]: 66
8410 01:17:32.354302
8411 01:17:32.354361 Set Vref, RX VrefLevel [Byte0]: 67
8412 01:17:32.354420 [Byte1]: 67
8413 01:17:32.354479
8414 01:17:32.354538 Set Vref, RX VrefLevel [Byte0]: 68
8415 01:17:32.354597 [Byte1]: 68
8416 01:17:32.354656
8417 01:17:32.354714 Set Vref, RX VrefLevel [Byte0]: 69
8418 01:17:32.354773 [Byte1]: 69
8419 01:17:32.354832
8420 01:17:32.354890 Set Vref, RX VrefLevel [Byte0]: 70
8421 01:17:32.354951 [Byte1]: 70
8422 01:17:32.355010
8423 01:17:32.355069 Set Vref, RX VrefLevel [Byte0]: 71
8424 01:17:32.355128 [Byte1]: 71
8425 01:17:32.355186
8426 01:17:32.355245 Set Vref, RX VrefLevel [Byte0]: 72
8427 01:17:32.355304 [Byte1]: 72
8428 01:17:32.355372
8429 01:17:32.355425 Set Vref, RX VrefLevel [Byte0]: 73
8430 01:17:32.355479 [Byte1]: 73
8431 01:17:32.355533
8432 01:17:32.355586 Set Vref, RX VrefLevel [Byte0]: 74
8433 01:17:32.355639 [Byte1]: 74
8434 01:17:32.355692
8435 01:17:32.355746 Set Vref, RX VrefLevel [Byte0]: 75
8436 01:17:32.355799 [Byte1]: 75
8437 01:17:32.355852
8438 01:17:32.355905 Final RX Vref Byte 0 = 63 to rank0
8439 01:17:32.355958 Final RX Vref Byte 1 = 52 to rank0
8440 01:17:32.356012 Final RX Vref Byte 0 = 63 to rank1
8441 01:17:32.356067 Final RX Vref Byte 1 = 52 to rank1==
8442 01:17:32.356120 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 01:17:32.356174 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8444 01:17:32.356229 ==
8445 01:17:32.356283 DQS Delay:
8446 01:17:32.356337 DQS0 = 0, DQS1 = 0
8447 01:17:32.356390 DQM Delay:
8448 01:17:32.356443 DQM0 = 128, DQM1 = 123
8449 01:17:32.356497 DQ Delay:
8450 01:17:32.356551 DQ0 =132, DQ1 =122, DQ2 =116, DQ3 =126
8451 01:17:32.356604 DQ4 =130, DQ5 =140, DQ6 =138, DQ7 =126
8452 01:17:32.356657 DQ8 =106, DQ9 =114, DQ10 =124, DQ11 =112
8453 01:17:32.356711 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =134
8454 01:17:32.356764
8455 01:17:32.356817
8456 01:17:32.356869
8457 01:17:32.356923 [DramC_TX_OE_Calibration] TA2
8458 01:17:32.356976 Original DQ_B0 (3 6) =30, OEN = 27
8459 01:17:32.357031 Original DQ_B1 (3 6) =30, OEN = 27
8460 01:17:32.357084 24, 0x0, End_B0=24 End_B1=24
8461 01:17:32.357138 25, 0x0, End_B0=25 End_B1=25
8462 01:17:32.357193 26, 0x0, End_B0=26 End_B1=26
8463 01:17:32.357249 27, 0x0, End_B0=27 End_B1=27
8464 01:17:32.357303 28, 0x0, End_B0=28 End_B1=28
8465 01:17:32.357358 29, 0x0, End_B0=29 End_B1=29
8466 01:17:32.357412 30, 0x0, End_B0=30 End_B1=30
8467 01:17:32.357467 31, 0x4141, End_B0=30 End_B1=30
8468 01:17:32.357522 Byte0 end_step=30 best_step=27
8469 01:17:32.357575 Byte1 end_step=30 best_step=27
8470 01:17:32.357629 Byte0 TX OE(2T, 0.5T) = (3, 3)
8471 01:17:32.357683 Byte1 TX OE(2T, 0.5T) = (3, 3)
8472 01:17:32.357736
8473 01:17:32.357789
8474 01:17:32.357842 [DQSOSCAuto] RK0, (LSB)MR18= 0x2727, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
8475 01:17:32.357897 CH1 RK0: MR19=303, MR18=2727
8476 01:17:32.357951 CH1_RK0: MR19=0x303, MR18=0x2727, DQSOSC=390, MR23=63, INC=24, DEC=16
8477 01:17:32.358006
8478 01:17:32.358064 ----->DramcWriteLeveling(PI) begin...
8479 01:17:32.358119 ==
8480 01:17:32.358173 Dram Type= 6, Freq= 0, CH_1, rank 1
8481 01:17:32.358226 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8482 01:17:32.358280 ==
8483 01:17:32.358334 Write leveling (Byte 0): 20 => 20
8484 01:17:32.358387 Write leveling (Byte 1): 20 => 20
8485 01:17:32.358441 DramcWriteLeveling(PI) end<-----
8486 01:17:32.358495
8487 01:17:32.358548 ==
8488 01:17:32.358601 Dram Type= 6, Freq= 0, CH_1, rank 1
8489 01:17:32.358654 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8490 01:17:32.358708 ==
8491 01:17:32.358762 [Gating] SW mode calibration
8492 01:17:32.358816 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8493 01:17:32.358871 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8494 01:17:32.359117 0 12 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8495 01:17:32.359178 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8496 01:17:32.359233 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8497 01:17:32.359288 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8498 01:17:32.359342 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8499 01:17:32.359396 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8500 01:17:32.359450 0 12 24 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
8501 01:17:32.359505 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8502 01:17:32.359560 0 13 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8503 01:17:32.359614 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8504 01:17:32.359668 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8505 01:17:32.359721 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8506 01:17:32.359775 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8507 01:17:32.359829 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8508 01:17:32.359883 0 13 24 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
8509 01:17:32.359937 0 13 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8510 01:17:32.359991 0 14 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8511 01:17:32.360045 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8512 01:17:32.360099 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8513 01:17:32.360153 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8514 01:17:32.360207 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8515 01:17:32.360261 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8516 01:17:32.360314 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8517 01:17:32.360379 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8518 01:17:32.360431 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8519 01:17:32.360482 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8520 01:17:32.360533 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8521 01:17:32.360584 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8522 01:17:32.360636 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8523 01:17:32.360687 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8524 01:17:32.360738 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8525 01:17:32.360789 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8526 01:17:32.360840 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8527 01:17:32.360891 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8528 01:17:32.360942 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8529 01:17:32.360993 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8530 01:17:32.361044 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8531 01:17:32.361096 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8532 01:17:32.361147 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8533 01:17:32.361198 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8534 01:17:32.361250 Total UI for P1: 0, mck2ui 16
8535 01:17:32.361302 best dqsien dly found for B0: ( 1, 0, 22)
8536 01:17:32.361354 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8537 01:17:32.361405 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8538 01:17:32.361456 Total UI for P1: 0, mck2ui 16
8539 01:17:32.361508 best dqsien dly found for B1: ( 1, 0, 30)
8540 01:17:32.361559 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8541 01:17:32.361611 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8542 01:17:32.361661
8543 01:17:32.361712 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8544 01:17:32.361764 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8545 01:17:32.361815 [Gating] SW calibration Done
8546 01:17:32.361866 ==
8547 01:17:32.361918 Dram Type= 6, Freq= 0, CH_1, rank 1
8548 01:17:32.361970 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8549 01:17:32.362031 ==
8550 01:17:32.362114 RX Vref Scan: 0
8551 01:17:32.362166
8552 01:17:32.362217 RX Vref 0 -> 0, step: 1
8553 01:17:32.362269
8554 01:17:32.362319 RX Delay 0 -> 252, step: 8
8555 01:17:32.362371 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8556 01:17:32.362423 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8557 01:17:32.362474 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8558 01:17:32.362525 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8559 01:17:32.362576 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8560 01:17:32.362627 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8561 01:17:32.362678 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8562 01:17:32.362729 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8563 01:17:32.362781 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8564 01:17:32.362831 iDelay=200, Bit 9, Center 111 (48 ~ 175) 128
8565 01:17:32.362882 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8566 01:17:32.362933 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8567 01:17:32.362984 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8568 01:17:32.363035 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8569 01:17:32.363103 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8570 01:17:32.363168 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8571 01:17:32.363221 ==
8572 01:17:32.363274 Dram Type= 6, Freq= 0, CH_1, rank 1
8573 01:17:32.363326 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8574 01:17:32.363378 ==
8575 01:17:32.363429 DQS Delay:
8576 01:17:32.363480 DQS0 = 0, DQS1 = 0
8577 01:17:32.363532 DQM Delay:
8578 01:17:32.363583 DQM0 = 130, DQM1 = 124
8579 01:17:32.363635 DQ Delay:
8580 01:17:32.363686 DQ0 =131, DQ1 =127, DQ2 =119, DQ3 =127
8581 01:17:32.363737 DQ4 =127, DQ5 =143, DQ6 =139, DQ7 =127
8582 01:17:32.363788 DQ8 =107, DQ9 =111, DQ10 =127, DQ11 =115
8583 01:17:32.363839 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8584 01:17:32.363890
8585 01:17:32.363941
8586 01:17:32.363992 ==
8587 01:17:32.364043 Dram Type= 6, Freq= 0, CH_1, rank 1
8588 01:17:32.364095 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8589 01:17:32.364147 ==
8590 01:17:32.364198
8591 01:17:32.364249
8592 01:17:32.364300 TX Vref Scan disable
8593 01:17:32.364352 == TX Byte 0 ==
8594 01:17:32.364403 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8595 01:17:32.364454 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8596 01:17:32.364506 == TX Byte 1 ==
8597 01:17:32.364556 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8598 01:17:32.364608 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8599 01:17:32.364659 ==
8600 01:17:32.364900 Dram Type= 6, Freq= 0, CH_1, rank 1
8601 01:17:32.364957 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8602 01:17:32.365011 ==
8603 01:17:32.365062
8604 01:17:32.365114 TX Vref early break, caculate TX vref
8605 01:17:32.365182 TX Vref=16, minBit 0, minWin=23, winSum=380
8606 01:17:32.365277 TX Vref=18, minBit 1, minWin=23, winSum=390
8607 01:17:32.365329 TX Vref=20, minBit 0, minWin=24, winSum=400
8608 01:17:32.365381 TX Vref=22, minBit 4, minWin=24, winSum=409
8609 01:17:32.365461 TX Vref=24, minBit 3, minWin=24, winSum=412
8610 01:17:32.365513 TX Vref=26, minBit 0, minWin=25, winSum=422
8611 01:17:32.365564 TX Vref=28, minBit 0, minWin=26, winSum=427
8612 01:17:32.365616 TX Vref=30, minBit 5, minWin=25, winSum=421
8613 01:17:32.365668 TX Vref=32, minBit 1, minWin=25, winSum=416
8614 01:17:32.365720 TX Vref=34, minBit 0, minWin=24, winSum=405
8615 01:17:32.365771 TX Vref=36, minBit 0, minWin=24, winSum=397
8616 01:17:32.365823 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
8617 01:17:32.365875
8618 01:17:32.365926 Final TX Range 0 Vref 28
8619 01:17:32.365978
8620 01:17:32.366051 ==
8621 01:17:32.366117 Dram Type= 6, Freq= 0, CH_1, rank 1
8622 01:17:32.366168 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8623 01:17:32.366220 ==
8624 01:17:32.366270
8625 01:17:32.366321
8626 01:17:32.366371 TX Vref Scan disable
8627 01:17:32.366422 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8628 01:17:32.366474 == TX Byte 0 ==
8629 01:17:32.366524 u2DelayCellOfst[0]=14 cells (4 PI)
8630 01:17:32.366576 u2DelayCellOfst[1]=10 cells (3 PI)
8631 01:17:32.366627 u2DelayCellOfst[2]=0 cells (0 PI)
8632 01:17:32.366678 u2DelayCellOfst[3]=7 cells (2 PI)
8633 01:17:32.366729 u2DelayCellOfst[4]=7 cells (2 PI)
8634 01:17:32.366780 u2DelayCellOfst[5]=14 cells (4 PI)
8635 01:17:32.366831 u2DelayCellOfst[6]=14 cells (4 PI)
8636 01:17:32.366882 u2DelayCellOfst[7]=7 cells (2 PI)
8637 01:17:32.366933 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8638 01:17:32.366985 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8639 01:17:32.367036 == TX Byte 1 ==
8640 01:17:32.367087 u2DelayCellOfst[8]=0 cells (0 PI)
8641 01:17:32.367138 u2DelayCellOfst[9]=3 cells (1 PI)
8642 01:17:32.367189 u2DelayCellOfst[10]=10 cells (3 PI)
8643 01:17:32.367240 u2DelayCellOfst[11]=3 cells (1 PI)
8644 01:17:32.367291 u2DelayCellOfst[12]=14 cells (4 PI)
8645 01:17:32.367342 u2DelayCellOfst[13]=18 cells (5 PI)
8646 01:17:32.367393 u2DelayCellOfst[14]=18 cells (5 PI)
8647 01:17:32.367444 u2DelayCellOfst[15]=18 cells (5 PI)
8648 01:17:32.367495 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8649 01:17:32.367546 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8650 01:17:32.367598 DramC Write-DBI on
8651 01:17:32.367649 ==
8652 01:17:32.367700 Dram Type= 6, Freq= 0, CH_1, rank 1
8653 01:17:32.367752 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8654 01:17:32.367804 ==
8655 01:17:32.367855
8656 01:17:32.367905
8657 01:17:32.367956 TX Vref Scan disable
8658 01:17:32.368008 == TX Byte 0 ==
8659 01:17:32.368063 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8660 01:17:32.368114 == TX Byte 1 ==
8661 01:17:32.368166 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8662 01:17:32.368217 DramC Write-DBI off
8663 01:17:32.368289
8664 01:17:32.368343 [DATLAT]
8665 01:17:32.368408 Freq=1600, CH1 RK1
8666 01:17:32.368461
8667 01:17:32.368512 DATLAT Default: 0xe
8668 01:17:32.368564 0, 0xFFFF, sum = 0
8669 01:17:32.368633 1, 0xFFFF, sum = 0
8670 01:17:32.368701 2, 0xFFFF, sum = 0
8671 01:17:32.368756 3, 0xFFFF, sum = 0
8672 01:17:32.368808 4, 0xFFFF, sum = 0
8673 01:17:32.368860 5, 0xFFFF, sum = 0
8674 01:17:32.368913 6, 0xFFFF, sum = 0
8675 01:17:32.368965 7, 0xFFFF, sum = 0
8676 01:17:32.369017 8, 0xFFFF, sum = 0
8677 01:17:32.369069 9, 0xFFFF, sum = 0
8678 01:17:32.369121 10, 0xFFFF, sum = 0
8679 01:17:32.369174 11, 0xFFFF, sum = 0
8680 01:17:32.369225 12, 0xF7F, sum = 0
8681 01:17:32.369277 13, 0x0, sum = 1
8682 01:17:32.369329 14, 0x0, sum = 2
8683 01:17:32.369382 15, 0x0, sum = 3
8684 01:17:32.369433 16, 0x0, sum = 4
8685 01:17:32.369485 best_step = 14
8686 01:17:32.369536
8687 01:17:32.369587 ==
8688 01:17:32.369638 Dram Type= 6, Freq= 0, CH_1, rank 1
8689 01:17:32.369689 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8690 01:17:32.369741 ==
8691 01:17:32.369793 RX Vref Scan: 0
8692 01:17:32.369844
8693 01:17:32.369895 RX Vref 0 -> 0, step: 1
8694 01:17:32.369947
8695 01:17:32.369997 RX Delay 3 -> 252, step: 4
8696 01:17:32.370057 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8697 01:17:32.370110 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8698 01:17:32.370162 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8699 01:17:32.370214 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8700 01:17:32.370266 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8701 01:17:32.370317 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8702 01:17:32.370368 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8703 01:17:32.370419 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8704 01:17:32.370471 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8705 01:17:32.370521 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8706 01:17:32.370572 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8707 01:17:32.370623 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8708 01:17:32.370674 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8709 01:17:32.370726 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8710 01:17:32.370777 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8711 01:17:32.370828 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8712 01:17:32.370880 ==
8713 01:17:32.370931 Dram Type= 6, Freq= 0, CH_1, rank 1
8714 01:17:32.370982 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8715 01:17:32.371033 ==
8716 01:17:32.371084 DQS Delay:
8717 01:17:32.371135 DQS0 = 0, DQS1 = 0
8718 01:17:32.371187 DQM Delay:
8719 01:17:32.371238 DQM0 = 127, DQM1 = 122
8720 01:17:32.371289 DQ Delay:
8721 01:17:32.371340 DQ0 =128, DQ1 =122, DQ2 =118, DQ3 =124
8722 01:17:32.371392 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8723 01:17:32.371443 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =112
8724 01:17:32.371494 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8725 01:17:32.371546
8726 01:17:32.371597
8727 01:17:32.371647
8728 01:17:32.371698 [DramC_TX_OE_Calibration] TA2
8729 01:17:32.371749 Original DQ_B0 (3 6) =30, OEN = 27
8730 01:17:32.371801 Original DQ_B1 (3 6) =30, OEN = 27
8731 01:17:32.371853 24, 0x0, End_B0=24 End_B1=24
8732 01:17:32.371905 25, 0x0, End_B0=25 End_B1=25
8733 01:17:32.371958 26, 0x0, End_B0=26 End_B1=26
8734 01:17:32.372010 27, 0x0, End_B0=27 End_B1=27
8735 01:17:32.372062 28, 0x0, End_B0=28 End_B1=28
8736 01:17:32.372114 29, 0x0, End_B0=29 End_B1=29
8737 01:17:32.372167 30, 0x0, End_B0=30 End_B1=30
8738 01:17:32.372219 31, 0x4141, End_B0=30 End_B1=30
8739 01:17:32.372271 Byte0 end_step=30 best_step=27
8740 01:17:32.372323 Byte1 end_step=30 best_step=27
8741 01:17:32.372566 Byte0 TX OE(2T, 0.5T) = (3, 3)
8742 01:17:32.372626 Byte1 TX OE(2T, 0.5T) = (3, 3)
8743 01:17:32.372679
8744 01:17:32.372730
8745 01:17:32.372782 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
8746 01:17:32.372850 CH1 RK1: MR19=303, MR18=1B1B
8747 01:17:32.372903 CH1_RK1: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
8748 01:17:32.372957 [RxdqsGatingPostProcess] freq 1600
8749 01:17:32.373009 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8750 01:17:32.373076 Pre-setting of DQS Precalculation
8751 01:17:32.373128 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8752 01:17:32.373180 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8753 01:17:32.373232 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8754 01:17:32.373283
8755 01:17:32.373334
8756 01:17:32.373385 [Calibration Summary] 3200 Mbps
8757 01:17:32.373436 CH 0, Rank 0
8758 01:17:32.373487 SW Impedance : PASS
8759 01:17:32.373538 DUTY Scan : NO K
8760 01:17:32.373590 ZQ Calibration : PASS
8761 01:17:32.373641 Jitter Meter : NO K
8762 01:17:32.373697 CBT Training : PASS
8763 01:17:32.373749 Write leveling : PASS
8764 01:17:32.373801 RX DQS gating : PASS
8765 01:17:32.373853 RX DQ/DQS(RDDQC) : PASS
8766 01:17:32.373904 TX DQ/DQS : PASS
8767 01:17:32.373955 RX DATLAT : PASS
8768 01:17:32.374028 RX DQ/DQS(Engine): PASS
8769 01:17:32.374135 TX OE : PASS
8770 01:17:32.374199 All Pass.
8771 01:17:32.374258
8772 01:17:32.374313 CH 0, Rank 1
8773 01:17:32.374365 SW Impedance : PASS
8774 01:17:32.374417 DUTY Scan : NO K
8775 01:17:32.374469 ZQ Calibration : PASS
8776 01:17:32.374520 Jitter Meter : NO K
8777 01:17:32.374572 CBT Training : PASS
8778 01:17:32.374624 Write leveling : PASS
8779 01:17:32.374675 RX DQS gating : PASS
8780 01:17:32.374727 RX DQ/DQS(RDDQC) : PASS
8781 01:17:32.374778 TX DQ/DQS : PASS
8782 01:17:32.374830 RX DATLAT : PASS
8783 01:17:32.374882 RX DQ/DQS(Engine): PASS
8784 01:17:32.374933 TX OE : PASS
8785 01:17:32.374984 All Pass.
8786 01:17:32.375035
8787 01:17:32.375085 CH 1, Rank 0
8788 01:17:32.375137 SW Impedance : PASS
8789 01:17:32.375188 DUTY Scan : NO K
8790 01:17:32.375238 ZQ Calibration : PASS
8791 01:17:32.375289 Jitter Meter : NO K
8792 01:17:32.375340 CBT Training : PASS
8793 01:17:32.375391 Write leveling : PASS
8794 01:17:32.375442 RX DQS gating : PASS
8795 01:17:32.375494 RX DQ/DQS(RDDQC) : PASS
8796 01:17:32.375544 TX DQ/DQS : PASS
8797 01:17:32.375596 RX DATLAT : PASS
8798 01:17:32.375654 RX DQ/DQS(Engine): PASS
8799 01:17:32.375714 TX OE : PASS
8800 01:17:32.375766 All Pass.
8801 01:17:32.375818
8802 01:17:32.375869 CH 1, Rank 1
8803 01:17:32.375920 SW Impedance : PASS
8804 01:17:32.375971 DUTY Scan : NO K
8805 01:17:32.376022 ZQ Calibration : PASS
8806 01:17:32.376073 Jitter Meter : NO K
8807 01:17:32.376124 CBT Training : PASS
8808 01:17:32.376175 Write leveling : PASS
8809 01:17:32.376226 RX DQS gating : PASS
8810 01:17:32.376277 RX DQ/DQS(RDDQC) : PASS
8811 01:17:32.376327 TX DQ/DQS : PASS
8812 01:17:32.376378 RX DATLAT : PASS
8813 01:17:32.376429 RX DQ/DQS(Engine): PASS
8814 01:17:32.376480 TX OE : PASS
8815 01:17:32.376530 All Pass.
8816 01:17:32.376581
8817 01:17:32.376632 DramC Write-DBI on
8818 01:17:32.376684 PER_BANK_REFRESH: Hybrid Mode
8819 01:17:32.376735 TX_TRACKING: ON
8820 01:17:32.376787 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8821 01:17:32.376840 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8822 01:17:32.376892 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8823 01:17:32.376944 [FAST_K] Save calibration result to emmc
8824 01:17:32.376996 sync common calibartion params.
8825 01:17:32.377047 sync cbt_mode0:0, 1:0
8826 01:17:32.377098 dram_init: ddr_geometry: 0
8827 01:17:32.377149 dram_init: ddr_geometry: 0
8828 01:17:32.377200 dram_init: ddr_geometry: 0
8829 01:17:32.377251 0:dram_rank_size:80000000
8830 01:17:32.377303 1:dram_rank_size:80000000
8831 01:17:32.377356 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8832 01:17:32.377407 DFS_SHUFFLE_HW_MODE: ON
8833 01:17:32.377459 dramc_set_vcore_voltage set vcore to 725000
8834 01:17:32.377510 Read voltage for 1600, 0
8835 01:17:32.377561 Vio18 = 0
8836 01:17:32.377611 Vcore = 725000
8837 01:17:32.377662 Vdram = 0
8838 01:17:32.377713 Vddq = 0
8839 01:17:32.377765 Vmddr = 0
8840 01:17:32.377816 switch to 3200 Mbps bootup
8841 01:17:32.377867 [DramcRunTimeConfig]
8842 01:17:32.377918 PHYPLL
8843 01:17:32.377969 DPM_CONTROL_AFTERK: ON
8844 01:17:32.378020 PER_BANK_REFRESH: ON
8845 01:17:32.378086 REFRESH_OVERHEAD_REDUCTION: ON
8846 01:17:32.378138 CMD_PICG_NEW_MODE: OFF
8847 01:17:32.378189 XRTWTW_NEW_MODE: ON
8848 01:17:32.378240 XRTRTR_NEW_MODE: ON
8849 01:17:32.378291 TX_TRACKING: ON
8850 01:17:32.378342 RDSEL_TRACKING: OFF
8851 01:17:32.378393 DQS Precalculation for DVFS: ON
8852 01:17:32.378445 RX_TRACKING: OFF
8853 01:17:32.378496 HW_GATING DBG: ON
8854 01:17:32.378547 ZQCS_ENABLE_LP4: ON
8855 01:17:32.378598 RX_PICG_NEW_MODE: ON
8856 01:17:32.378649 TX_PICG_NEW_MODE: ON
8857 01:17:32.378700 ENABLE_RX_DCM_DPHY: ON
8858 01:17:32.378751 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8859 01:17:32.378802 DUMMY_READ_FOR_TRACKING: OFF
8860 01:17:32.378853 !!! SPM_CONTROL_AFTERK: OFF
8861 01:17:32.378913 !!! SPM could not control APHY
8862 01:17:32.378966 IMPEDANCE_TRACKING: ON
8863 01:17:32.379017 TEMP_SENSOR: ON
8864 01:17:32.379069 HW_SAVE_FOR_SR: OFF
8865 01:17:32.379120 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8866 01:17:32.379171 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8867 01:17:32.379222 Read ODT Tracking: ON
8868 01:17:32.379273 Refresh Rate DeBounce: ON
8869 01:17:32.379325 DFS_NO_QUEUE_FLUSH: ON
8870 01:17:32.379376 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8871 01:17:32.379427 ENABLE_DFS_RUNTIME_MRW: OFF
8872 01:17:32.379479 DDR_RESERVE_NEW_MODE: ON
8873 01:17:32.379530 MR_CBT_SWITCH_FREQ: ON
8874 01:17:32.379581 =========================
8875 01:17:32.379633 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8876 01:17:32.379685 dram_init: ddr_geometry: 0
8877 01:17:32.379736 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8878 01:17:32.379788 dram_init: dram init end (result: 0)
8879 01:17:32.379840 DRAM-K: Full calibration passed in 23466 msecs
8880 01:17:32.379891 MRC: failed to locate region type 0.
8881 01:17:32.379942 DRAM rank0 size:0x80000000,
8882 01:17:32.379994 DRAM rank1 size=0x80000000
8883 01:17:32.380045 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8884 01:17:32.380289 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8885 01:17:32.380348 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8886 01:17:32.380402 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8887 01:17:32.380454 DRAM rank0 size:0x80000000,
8888 01:17:32.380506 DRAM rank1 size=0x80000000
8889 01:17:32.380557 CBMEM:
8890 01:17:32.380609 IMD: root @ 0xfffff000 254 entries.
8891 01:17:32.380661 IMD: root @ 0xffffec00 62 entries.
8892 01:17:32.380713 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8893 01:17:32.380765 WARNING: RO_VPD is uninitialized or empty.
8894 01:17:32.380817 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8895 01:17:32.380872 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8896 01:17:32.380925 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8897 01:17:32.380978 BS: romstage times (exec / console): total (unknown) / 22998 ms
8898 01:17:32.381030
8899 01:17:32.381081
8900 01:17:32.381133 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8901 01:17:32.381185 ARM64: Exception handlers installed.
8902 01:17:32.381237 ARM64: Testing exception
8903 01:17:32.381289 ARM64: Done test exception
8904 01:17:32.381340 Enumerating buses...
8905 01:17:32.381391 Show all devs... Before device enumeration.
8906 01:17:32.381442 Root Device: enabled 1
8907 01:17:32.381494 CPU_CLUSTER: 0: enabled 1
8908 01:17:32.381545 CPU: 00: enabled 1
8909 01:17:32.381595 Compare with tree...
8910 01:17:32.381647 Root Device: enabled 1
8911 01:17:32.381698 CPU_CLUSTER: 0: enabled 1
8912 01:17:32.381750 CPU: 00: enabled 1
8913 01:17:32.381801 Root Device scanning...
8914 01:17:32.381852 scan_static_bus for Root Device
8915 01:17:32.381904 CPU_CLUSTER: 0 enabled
8916 01:17:32.381955 scan_static_bus for Root Device done
8917 01:17:32.382006 scan_bus: bus Root Device finished in 8 msecs
8918 01:17:32.382117 done
8919 01:17:32.382198 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8920 01:17:32.382280 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8921 01:17:32.382366 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8922 01:17:32.382423 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8923 01:17:32.382476 Allocating resources...
8924 01:17:32.382528 Reading resources...
8925 01:17:32.382579 Root Device read_resources bus 0 link: 0
8926 01:17:32.382631 DRAM rank0 size:0x80000000,
8927 01:17:32.382683 DRAM rank1 size=0x80000000
8928 01:17:32.382734 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8929 01:17:32.382786 CPU: 00 missing read_resources
8930 01:17:32.382837 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8931 01:17:32.382889 Root Device read_resources bus 0 link: 0 done
8932 01:17:32.382941 Done reading resources.
8933 01:17:32.382993 Show resources in subtree (Root Device)...After reading.
8934 01:17:32.383044 Root Device child on link 0 CPU_CLUSTER: 0
8935 01:17:32.978265 CPU_CLUSTER: 0 child on link 0 CPU: 00
8936 01:17:32.978394 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8937 01:17:32.978461 CPU: 00
8938 01:17:32.978520 Root Device assign_resources, bus 0 link: 0
8939 01:17:32.978578 CPU_CLUSTER: 0 missing set_resources
8940 01:17:32.978634 Root Device assign_resources, bus 0 link: 0 done
8941 01:17:32.978690 Done setting resources.
8942 01:17:32.978745 Show resources in subtree (Root Device)...After assigning values.
8943 01:17:32.978800 Root Device child on link 0 CPU_CLUSTER: 0
8944 01:17:32.978854 CPU_CLUSTER: 0 child on link 0 CPU: 00
8945 01:17:32.978907 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8946 01:17:32.978960 CPU: 00
8947 01:17:32.979013 Done allocating resources.
8948 01:17:32.979066 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8949 01:17:32.979119 Enabling resources...
8950 01:17:32.979171 done.
8951 01:17:32.979222 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8952 01:17:32.979274 Initializing devices...
8953 01:17:32.979327 Root Device init
8954 01:17:32.979379 init hardware done!
8955 01:17:32.979431 0x00000018: ctrlr->caps
8956 01:17:32.979484 52.000 MHz: ctrlr->f_max
8957 01:17:32.979538 0.400 MHz: ctrlr->f_min
8958 01:17:32.979592 0x40ff8080: ctrlr->voltages
8959 01:17:32.979645 sclk: 390625
8960 01:17:32.979700 Bus Width = 1
8961 01:17:32.979753 sclk: 390625
8962 01:17:32.979804 Bus Width = 1
8963 01:17:32.979855 Early init status = 3
8964 01:17:32.979906 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8965 01:17:32.979959 in-header: 03 fc 00 00 01 00 00 00
8966 01:17:32.980011 in-data: 00
8967 01:17:32.980062 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8968 01:17:32.980114 in-header: 03 fd 00 00 00 00 00 00
8969 01:17:32.980165 in-data:
8970 01:17:32.980216 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8971 01:17:32.980269 in-header: 03 fc 00 00 01 00 00 00
8972 01:17:32.980320 in-data: 00
8973 01:17:32.980371 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8974 01:17:32.980423 in-header: 03 fd 00 00 00 00 00 00
8975 01:17:32.980473 in-data:
8976 01:17:32.980524 [SSUSB] Setting up USB HOST controller...
8977 01:17:32.980576 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8978 01:17:32.980628 [SSUSB] phy power-on done.
8979 01:17:32.980679 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8980 01:17:32.980732 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8981 01:17:32.980784 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8982 01:17:32.980836 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8983 01:17:32.980889 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8984 01:17:32.980941 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8985 01:17:32.980993 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8986 01:17:32.981045 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
8987 01:17:32.981096 SPM: binary array size = 0x9dc
8988 01:17:32.981356 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8989 01:17:32.981416 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8990 01:17:32.981470 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8991 01:17:32.981522 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8992 01:17:32.981574 configure_display: Starting display init
8993 01:17:32.981626 anx7625_power_on_init: Init interface.
8994 01:17:32.981678 anx7625_disable_pd_protocol: Disabled PD feature.
8995 01:17:32.981730 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8996 01:17:32.981781 anx7625_start_dp_work: Secure OCM version=00
8997 01:17:32.981832 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8998 01:17:32.981884 sp_tx_get_edid_block: EDID Block = 1
8999 01:17:32.981936 Extracted contents:
9000 01:17:32.981987 header: 00 ff ff ff ff ff ff 00
9001 01:17:32.982048 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9002 01:17:32.982141 version: 01 04
9003 01:17:32.982195 basic params: 95 1f 11 78 0a
9004 01:17:32.982246 chroma info: 76 90 94 55 54 90 27 21 50 54
9005 01:17:32.982298 established: 00 00 00
9006 01:17:32.982350 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9007 01:17:32.982402 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9008 01:17:32.982454 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9009 01:17:32.982506 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9010 01:17:32.982558 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9011 01:17:32.982609 extensions: 00
9012 01:17:32.982661 checksum: fb
9013 01:17:32.982713
9014 01:17:32.982764 Manufacturer: IVO Model 57d Serial Number 0
9015 01:17:32.982816 Made week 0 of 2020
9016 01:17:32.982867 EDID version: 1.4
9017 01:17:32.982918 Digital display
9018 01:17:32.982969 6 bits per primary color channel
9019 01:17:32.983022 DisplayPort interface
9020 01:17:32.983073 Maximum image size: 31 cm x 17 cm
9021 01:17:32.983124 Gamma: 220%
9022 01:17:32.983175 Check DPMS levels
9023 01:17:32.983226 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9024 01:17:32.983278 First detailed timing is preferred timing
9025 01:17:32.983330 Established timings supported:
9026 01:17:32.983382 Standard timings supported:
9027 01:17:32.983446 Detailed timings
9028 01:17:32.983499 Hex of detail: 383680a07038204018303c0035ae10000019
9029 01:17:32.983551 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9030 01:17:32.983604 0780 0798 07c8 0820 hborder 0
9031 01:17:32.983656 0438 043b 0447 0458 vborder 0
9032 01:17:32.983756 -hsync -vsync
9033 01:17:32.983809 Did detailed timing
9034 01:17:32.983861 Hex of detail: 000000000000000000000000000000000000
9035 01:17:32.983918 Manufacturer-specified data, tag 0
9036 01:17:32.983970 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9037 01:17:32.984021 ASCII string: InfoVision
9038 01:17:32.984073 Hex of detail: 000000fe00523134304e574635205248200a
9039 01:17:32.984124 ASCII string: R140NWF5 RH
9040 01:17:32.984176 Checksum
9041 01:17:32.984227 Checksum: 0xfb (valid)
9042 01:17:32.984278 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9043 01:17:32.984330 DSI data_rate: 832800000 bps
9044 01:17:32.984381 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9045 01:17:32.984433 anx7625_parse_edid: pixelclock(138800).
9046 01:17:32.984484 hactive(1920), hsync(48), hfp(24), hbp(88)
9047 01:17:32.984537 vactive(1080), vsync(12), vfp(3), vbp(17)
9048 01:17:32.984589 anx7625_dsi_config: config dsi.
9049 01:17:32.984640 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9050 01:17:32.984699 anx7625_dsi_config: success to config DSI
9051 01:17:32.984752 anx7625_dp_start: MIPI phy setup OK.
9052 01:17:32.984805 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9053 01:17:32.984857 mtk_ddp_mode_set invalid vrefresh 60
9054 01:17:32.984908 main_disp_path_setup
9055 01:17:32.984960 ovl_layer_smi_id_en
9056 01:17:32.985012 ovl_layer_smi_id_en
9057 01:17:32.985063 ccorr_config
9058 01:17:32.985114 aal_config
9059 01:17:32.985165 gamma_config
9060 01:17:32.985217 postmask_config
9061 01:17:32.985269 dither_config
9062 01:17:32.985321 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9063 01:17:32.985374 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9064 01:17:32.985426 Root Device init finished in 551 msecs
9065 01:17:32.985478 CPU_CLUSTER: 0 init
9066 01:17:32.985530 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9067 01:17:32.985583 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9068 01:17:32.985636 APU_MBOX 0x190000b0 = 0x10001
9069 01:17:32.985687 APU_MBOX 0x190001b0 = 0x10001
9070 01:17:32.985739 APU_MBOX 0x190005b0 = 0x10001
9071 01:17:32.985791 APU_MBOX 0x190006b0 = 0x10001
9072 01:17:32.985844 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9073 01:17:32.985897 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9074 01:17:32.985949 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9075 01:17:32.986002 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9076 01:17:32.986093 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9077 01:17:32.986146 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9078 01:17:32.986199 CPU_CLUSTER: 0 init finished in 81 msecs
9079 01:17:32.986250 Devices initialized
9080 01:17:32.986302 Show all devs... After init.
9081 01:17:32.986354 Root Device: enabled 1
9082 01:17:32.986406 CPU_CLUSTER: 0: enabled 1
9083 01:17:32.986458 CPU: 00: enabled 1
9084 01:17:32.986509 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9085 01:17:32.986562 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9086 01:17:32.986614 ELOG: NV offset 0x57f000 size 0x1000
9087 01:17:32.986666 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9088 01:17:32.986910 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9089 01:17:32.986978 ELOG: Event(17) added with size 13 at 2024-04-23 01:17:27 UTC
9090 01:17:32.987033 out: cmd=0x121: 03 db 21 01 00 00 00 00
9091 01:17:32.987087 in-header: 03 c6 00 00 2c 00 00 00
9092 01:17:32.987141 in-data: 9d 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9093 01:17:32.987198 ELOG: Event(A1) added with size 10 at 2024-04-23 01:17:27 UTC
9094 01:17:32.987251 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9095 01:17:32.987304 ELOG: Event(A0) added with size 9 at 2024-04-23 01:17:27 UTC
9096 01:17:32.987357 elog_add_boot_reason: Logged dev mode boot
9097 01:17:32.987409 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9098 01:17:32.987462 Finalize devices...
9099 01:17:32.987515 Devices finalized
9100 01:17:32.987574 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9101 01:17:32.987626 Writing coreboot table at 0xffe64000
9102 01:17:32.987678 0. 000000000010a000-0000000000113fff: RAMSTAGE
9103 01:17:32.987730 1. 0000000040000000-00000000400fffff: RAM
9104 01:17:32.987782 2. 0000000040100000-000000004032afff: RAMSTAGE
9105 01:17:32.987834 3. 000000004032b000-00000000545fffff: RAM
9106 01:17:32.987886 4. 0000000054600000-000000005465ffff: BL31
9107 01:17:32.987938 5. 0000000054660000-00000000ffe63fff: RAM
9108 01:17:32.987990 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9109 01:17:32.988042 7. 0000000100000000-000000013fffffff: RAM
9110 01:17:32.988094 Passing 5 GPIOs to payload:
9111 01:17:32.988146 NAME | PORT | POLARITY | VALUE
9112 01:17:32.988199 EC in RW | 0x000000aa | low | undefined
9113 01:17:32.988251 EC interrupt | 0x00000005 | low | undefined
9114 01:17:32.988304 TPM interrupt | 0x000000ab | high | undefined
9115 01:17:32.988356 SD card detect | 0x00000011 | high | undefined
9116 01:17:32.988409 speaker enable | 0x00000093 | high | undefined
9117 01:17:32.988461 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9118 01:17:32.988514 in-header: 03 f8 00 00 02 00 00 00
9119 01:17:32.988565 in-data: 03 00
9120 01:17:32.988617 ADC[4]: Raw value=668958 ID=5
9121 01:17:32.988669 ADC[3]: Raw value=212180 ID=1
9122 01:17:32.988721 RAM Code: 0x51
9123 01:17:32.988772 ADC[6]: Raw value=74410 ID=0
9124 01:17:32.988824 ADC[5]: Raw value=211444 ID=1
9125 01:17:32.988875 SKU Code: 0x1
9126 01:17:32.988927 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum dd9a
9127 01:17:32.988978 coreboot table: 964 bytes.
9128 01:17:32.989030 IMD ROOT 0. 0xfffff000 0x00001000
9129 01:17:32.989082 IMD SMALL 1. 0xffffe000 0x00001000
9130 01:17:32.989134 RO MCACHE 2. 0xffffc000 0x00001104
9131 01:17:32.989186 CONSOLE 3. 0xfff7c000 0x00080000
9132 01:17:32.989238 FMAP 4. 0xfff7b000 0x00000452
9133 01:17:32.989291 TIME STAMP 5. 0xfff7a000 0x00000910
9134 01:17:32.989343 VBOOT WORK 6. 0xfff66000 0x00014000
9135 01:17:32.989395 RAMOOPS 7. 0xffe66000 0x00100000
9136 01:17:32.989446 COREBOOT 8. 0xffe64000 0x00002000
9137 01:17:32.989497 IMD small region:
9138 01:17:32.989549 IMD ROOT 0. 0xffffec00 0x00000400
9139 01:17:32.989601 VPD 1. 0xffffeb80 0x0000006c
9140 01:17:32.989652 MMC STATUS 2. 0xffffeb60 0x00000004
9141 01:17:32.989710 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9142 01:17:32.989785 Probing TPM: done!
9143 01:17:32.989885 Connected to device vid:did:rid of 1ae0:0028:00
9144 01:17:32.989974 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9145 01:17:32.990088 Initialized TPM device CR50 revision 0
9146 01:17:32.990143 Checking cr50 for pending updates
9147 01:17:32.990196 Reading cr50 TPM mode
9148 01:17:32.990255 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9149 01:17:32.990340 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9150 01:17:32.990423 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9151 01:17:32.990505 Checking segment from ROM address 0x40100000
9152 01:17:32.990583 Checking segment from ROM address 0x4010001c
9153 01:17:32.990638 Loading segment from ROM address 0x40100000
9154 01:17:32.990691 code (compression=0)
9155 01:17:32.990744 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9156 01:17:32.990797 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9157 01:17:32.990850 it's not compressed!
9158 01:17:32.990909 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9159 01:17:32.990962 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9160 01:17:32.991014 Loading segment from ROM address 0x4010001c
9161 01:17:32.991067 Entry Point 0x80000000
9162 01:17:32.991119 Loaded segments
9163 01:17:32.991171 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9164 01:17:32.991224 Jumping to boot code at 0x80000000(0xffe64000)
9165 01:17:32.991277 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9166 01:17:32.991329 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9167 01:17:32.991391 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9168 01:17:32.991445 Checking segment from ROM address 0x40100000
9169 01:17:32.991497 Checking segment from ROM address 0x4010001c
9170 01:17:32.991560 Loading segment from ROM address 0x40100000
9171 01:17:32.991619 code (compression=1)
9172 01:17:32.991672 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9173 01:17:32.991725 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9174 01:17:32.991777 using LZMA
9175 01:17:32.992022 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9176 01:17:32.992080 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9177 01:17:32.992134 Loading segment from ROM address 0x4010001c
9178 01:17:32.992210 Entry Point 0x54601000
9179 01:17:32.992292 Loaded segments
9180 01:17:32.992373 NOTICE: MT8192 bl31_setup
9181 01:17:32.992456 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9182 01:17:32.992540 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9183 01:17:32.992625 WARNING: region 0:
9184 01:17:32.992709 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9185 01:17:32.992795 WARNING: region 1:
9186 01:17:32.992877 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9187 01:17:32.992959 WARNING: region 2:
9188 01:17:32.993041 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9189 01:17:32.993122 WARNING: region 3:
9190 01:17:32.993203 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9191 01:17:32.993286 WARNING: region 4:
9192 01:17:32.993371 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9193 01:17:32.993455 WARNING: region 5:
9194 01:17:32.993537 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9195 01:17:32.993617 WARNING: region 6:
9196 01:17:32.993690 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9197 01:17:32.993744 WARNING: region 7:
9198 01:17:32.993805 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9199 01:17:32.993866 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9200 01:17:32.993949 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9201 01:17:32.994038 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9202 01:17:32.994121 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9203 01:17:32.994207 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9204 01:17:32.994291 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9205 01:17:32.994378 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9206 01:17:32.994460 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9207 01:17:32.994541 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9208 01:17:32.994630 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9209 01:17:32.994686 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9210 01:17:32.994738 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9211 01:17:32.994808 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9212 01:17:32.994892 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9213 01:17:32.994974 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9214 01:17:32.995056 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9215 01:17:32.995140 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9216 01:17:32.995222 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9217 01:17:32.995303 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9218 01:17:32.995384 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9219 01:17:32.995465 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9220 01:17:32.995543 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9221 01:17:32.995598 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9222 01:17:32.995650 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9223 01:17:32.995703 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9224 01:17:32.995755 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9225 01:17:32.995807 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9226 01:17:32.995864 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9227 01:17:32.995917 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9228 01:17:32.996003 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9229 01:17:32.996085 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9230 01:17:32.996170 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9231 01:17:32.996263 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9232 01:17:32.996356 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9233 01:17:32.996440 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9234 01:17:32.996522 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9235 01:17:32.996604 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9236 01:17:32.996685 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9237 01:17:32.996767 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9238 01:17:32.996848 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9239 01:17:32.996929 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9240 01:17:32.997010 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9241 01:17:32.997091 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9242 01:17:32.997173 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9243 01:17:32.997254 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9244 01:17:32.997335 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9245 01:17:32.997416 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9246 01:17:32.997497 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9247 01:17:32.997578 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9248 01:17:32.997660 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9249 01:17:32.997741 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9250 01:17:32.997822 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9251 01:17:32.997904 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9252 01:17:32.997985 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9253 01:17:32.998098 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9254 01:17:32.998152 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9255 01:17:32.998205 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9256 01:17:32.998258 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9257 01:17:32.998310 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9258 01:17:32.998362 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9259 01:17:32.998606 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9260 01:17:32.998664 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9261 01:17:32.998717 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9262 01:17:32.998770 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9263 01:17:32.998823 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9264 01:17:32.998876 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9265 01:17:32.998927 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9266 01:17:32.998980 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9267 01:17:32.999031 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9268 01:17:32.999083 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9269 01:17:32.999135 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9270 01:17:32.999187 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9271 01:17:32.999239 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9272 01:17:32.999291 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9273 01:17:32.999343 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9274 01:17:32.999395 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9275 01:17:32.999447 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9276 01:17:32.999499 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9277 01:17:32.999551 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9278 01:17:32.999602 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9279 01:17:32.999654 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9280 01:17:32.999706 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9281 01:17:32.999758 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9282 01:17:32.999810 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9283 01:17:32.999862 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9284 01:17:32.999914 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9285 01:17:32.999966 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9286 01:17:33.000018 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9287 01:17:33.000070 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9288 01:17:33.000122 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9289 01:17:33.000175 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9290 01:17:33.000227 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9291 01:17:33.000278 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9292 01:17:33.000330 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9293 01:17:33.000383 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9294 01:17:33.000435 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9295 01:17:33.000486 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9296 01:17:33.000538 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9297 01:17:33.000589 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9298 01:17:33.000640 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9299 01:17:33.000690 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9300 01:17:33.000742 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9301 01:17:33.000793 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9302 01:17:33.000844 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9303 01:17:33.000896 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9304 01:17:33.000948 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9305 01:17:33.000999 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9306 01:17:33.001050 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9307 01:17:33.001102 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9308 01:17:33.001153 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9309 01:17:33.001205 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9310 01:17:33.001256 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9311 01:17:33.001308 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9312 01:17:33.001359 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9313 01:17:33.001410 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9314 01:17:33.001461 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9315 01:17:33.001513 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9316 01:17:33.001564 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9317 01:17:33.001615 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9318 01:17:33.001666 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9319 01:17:33.001717 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9320 01:17:33.001768 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9321 01:17:33.001819 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9322 01:17:33.001870 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9323 01:17:33.001922 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9324 01:17:33.001973 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9325 01:17:33.002032 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9326 01:17:33.002118 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9327 01:17:33.002170 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9328 01:17:33.002222 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9329 01:17:33.002274 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9330 01:17:33.002325 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9331 01:17:33.002377 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9332 01:17:33.002428 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9333 01:17:33.002479 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9334 01:17:33.002531 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9335 01:17:33.002772 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9336 01:17:33.002830 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9337 01:17:33.002884 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9338 01:17:33.002936 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9339 01:17:33.002988 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9340 01:17:33.003039 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9341 01:17:33.003091 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9342 01:17:33.003142 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9343 01:17:33.003194 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9344 01:17:33.003246 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9345 01:17:33.003297 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9346 01:17:33.003349 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9347 01:17:33.003400 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9348 01:17:33.003451 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9349 01:17:33.003502 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9350 01:17:33.003554 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9351 01:17:33.003605 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9352 01:17:33.003656 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9353 01:17:33.003708 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9354 01:17:33.003760 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9355 01:17:33.003811 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9356 01:17:33.003862 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9357 01:17:33.003914 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9358 01:17:33.003966 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9359 01:17:33.004018 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9360 01:17:33.004069 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9361 01:17:33.004121 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9362 01:17:33.004172 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9363 01:17:33.004223 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9364 01:17:33.004274 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9365 01:17:33.004350 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9366 01:17:33.004415 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9367 01:17:33.004466 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9368 01:17:33.004518 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9369 01:17:33.004569 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9370 01:17:33.004620 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9371 01:17:33.004671 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9372 01:17:33.004722 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9373 01:17:33.004774 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9374 01:17:33.004825 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9375 01:17:33.004877 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9376 01:17:33.004928 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9377 01:17:33.004979 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9378 01:17:33.005031 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9379 01:17:33.005082 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9380 01:17:33.005133 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9381 01:17:33.005184 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9382 01:17:33.005235 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9383 01:17:33.005286 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9384 01:17:33.005337 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9385 01:17:33.005387 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9386 01:17:33.005439 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9387 01:17:33.005490 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9388 01:17:33.005541 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9389 01:17:33.005592 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9390 01:17:33.005643 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9391 01:17:33.005695 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9392 01:17:33.005746 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9393 01:17:33.005799 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9394 01:17:33.005850 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9395 01:17:33.005902 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9396 01:17:33.005954 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9397 01:17:33.006005 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9398 01:17:33.006100 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9399 01:17:33.006152 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9400 01:17:33.006204 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9401 01:17:33.006255 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9402 01:17:33.006307 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9403 01:17:33.006358 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9404 01:17:33.006410 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9405 01:17:33.006461 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9406 01:17:33.006512 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9407 01:17:33.006563 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9408 01:17:33.006615 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9409 01:17:33.006665 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9410 01:17:33.006717 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9411 01:17:33.006957 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9412 01:17:33.007014 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9413 01:17:33.007067 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9414 01:17:33.007119 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9415 01:17:33.007170 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9416 01:17:33.007222 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9417 01:17:33.007273 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9418 01:17:33.007325 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9419 01:17:33.007377 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9420 01:17:33.007428 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9421 01:17:33.007479 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9422 01:17:33.007530 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9423 01:17:33.007582 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9424 01:17:33.007644 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9425 01:17:33.007697 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9426 01:17:33.007749 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9427 01:17:33.007800 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9428 01:17:33.007852 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9429 01:17:33.007903 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9430 01:17:33.007954 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9431 01:17:33.008005 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9432 01:17:33.008057 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9433 01:17:33.008107 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9434 01:17:33.008159 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9435 01:17:33.008210 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9436 01:17:33.008261 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9437 01:17:33.008312 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9438 01:17:33.008363 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9439 01:17:33.008414 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9440 01:17:33.008465 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9441 01:17:33.008517 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9442 01:17:33.008568 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9443 01:17:33.008619 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9444 01:17:33.008671 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9445 01:17:33.008722 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9446 01:17:33.008773 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9447 01:17:33.008825 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9448 01:17:33.008876 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9449 01:17:33.008927 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9450 01:17:33.008978 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9451 01:17:33.009030 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9452 01:17:33.009081 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9453 01:17:33.009132 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9454 01:17:33.009183 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9455 01:17:33.009234 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9456 01:17:33.009285 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9457 01:17:33.009336 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9458 01:17:33.009388 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9459 01:17:33.009439 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9460 01:17:33.009491 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9461 01:17:33.009542 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9462 01:17:33.009593 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9463 01:17:33.009645 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9464 01:17:33.009697 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9465 01:17:33.009748 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9466 01:17:33.009799 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9467 01:17:33.009850 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9468 01:17:33.009901 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9469 01:17:33.009953 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9470 01:17:33.010004 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9471 01:17:33.010097 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9472 01:17:33.010150 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9473 01:17:33.010201 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9474 01:17:33.010253 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9475 01:17:33.010305 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9476 01:17:33.010356 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9477 01:17:33.010408 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9478 01:17:33.010459 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9479 01:17:33.010510 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9480 01:17:33.010562 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9481 01:17:33.010613 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9482 01:17:33.010664 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9483 01:17:33.010716 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9484 01:17:33.010767 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9485 01:17:33.010819 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9486 01:17:33.010870 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9487 01:17:33.010921 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9488 01:17:33.010972 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9489 01:17:33.011024 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9490 01:17:33.011267 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9491 01:17:33.011327 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9492 01:17:33.011380 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9493 01:17:33.011432 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9494 01:17:33.011484 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9495 01:17:33.011535 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9496 01:17:33.011587 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9497 01:17:33.011639 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9498 01:17:33.011690 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9499 01:17:33.011742 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9500 01:17:33.011794 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9501 01:17:33.011846 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9502 01:17:33.011897 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9503 01:17:33.011948 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9504 01:17:33.011999 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9505 01:17:33.012050 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9506 01:17:33.012101 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9507 01:17:33.012153 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9508 01:17:33.012204 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9509 01:17:33.012255 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9510 01:17:33.012326 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9511 01:17:33.012391 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9512 01:17:33.012443 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9513 01:17:33.012495 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9514 01:17:33.012546 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9515 01:17:33.012597 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9516 01:17:33.012648 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9517 01:17:33.012699 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9518 01:17:33.012750 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9519 01:17:33.012802 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9520 01:17:33.012853 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9521 01:17:33.012904 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9522 01:17:33.012956 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9523 01:17:33.013008 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9524 01:17:33.013060 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9525 01:17:33.013111 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9526 01:17:33.013162 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9527 01:17:33.013213 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9528 01:17:33.013264 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9529 01:17:33.013315 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9530 01:17:33.013367 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9531 01:17:33.013418 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9532 01:17:33.013469 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9533 01:17:33.013521 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9534 01:17:33.013572 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9535 01:17:33.013623 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9536 01:17:33.013675 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9537 01:17:33.013726 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9538 01:17:33.013777 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9539 01:17:33.013828 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9540 01:17:33.013879 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9541 01:17:33.013930 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9542 01:17:33.013982 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9543 01:17:33.014047 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9544 01:17:33.014137 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9545 01:17:33.014189 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9546 01:17:33.014240 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9547 01:17:33.014291 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9548 01:17:33.014342 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9549 01:17:33.014394 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9550 01:17:33.014445 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9551 01:17:33.014496 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9552 01:17:33.014548 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9553 01:17:33.014599 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9554 01:17:33.014650 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9555 01:17:33.014702 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9556 01:17:33.014753 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9557 01:17:33.014805 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9558 01:17:33.014857 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9559 01:17:33.014908 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9560 01:17:33.014959 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9561 01:17:33.015011 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9562 01:17:33.015062 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9563 01:17:33.015114 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9564 01:17:33.015165 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9565 01:17:33.015405 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9566 01:17:33.015463 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9567 01:17:33.015516 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9568 01:17:33.015567 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9569 01:17:33.015619 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9570 01:17:33.015671 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9571 01:17:33.015722 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9572 01:17:33.015774 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9573 01:17:33.015825 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9574 01:17:33.015888 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9575 01:17:33.015944 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9576 01:17:33.016006 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9577 01:17:33.016072 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9578 01:17:33.016134 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9579 01:17:33.016222 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9580 01:17:33.016315 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9581 01:17:33.016401 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9582 01:17:33.016489 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9583 01:17:33.016579 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9584 01:17:33.016666 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9585 01:17:33.016748 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9586 01:17:33.016830 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9587 01:17:33.016911 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9588 01:17:33.016992 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9589 01:17:33.017073 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9590 01:17:33.017154 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9591 01:17:33.017235 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9592 01:17:33.017316 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9593 01:17:33.017397 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9594 01:17:33.017478 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9595 01:17:33.017559 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9596 01:17:33.017640 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9597 01:17:33.017721 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9598 01:17:33.017801 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9599 01:17:33.017882 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9600 01:17:33.017963 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9601 01:17:33.018077 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9602 01:17:33.018173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9603 01:17:33.018255 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9604 01:17:33.018336 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9605 01:17:33.018418 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9606 01:17:33.018499 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9607 01:17:33.018580 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9608 01:17:33.018661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9609 01:17:33.018742 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9610 01:17:33.018823 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9611 01:17:33.018904 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9612 01:17:33.018985 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9613 01:17:33.019066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9614 01:17:33.019147 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9615 01:17:33.019228 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9616 01:17:33.019309 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9617 01:17:33.019390 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9618 01:17:33.019471 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9619 01:17:33.019553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9620 01:17:33.019634 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9621 01:17:33.019715 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9622 01:17:33.019796 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9623 01:17:33.019877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9624 01:17:33.019958 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9625 01:17:33.020039 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9626 01:17:33.020120 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9627 01:17:33.020201 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9628 01:17:33.020282 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9629 01:17:33.020363 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9630 01:17:33.020444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9631 01:17:33.020525 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9632 01:17:33.020606 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9633 01:17:33.020687 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9634 01:17:33.020767 INFO: [APUAPC] vio 0
9635 01:17:33.020848 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9636 01:17:33.020929 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9637 01:17:33.021009 INFO: [APUAPC] D0_APC_0: 0x400510
9638 01:17:33.021089 INFO: [APUAPC] D0_APC_1: 0x0
9639 01:17:33.021170 INFO: [APUAPC] D0_APC_2: 0x1540
9640 01:17:33.021443 INFO: [APUAPC] D0_APC_3: 0x0
9641 01:17:33.021527 INFO: [APUAPC] D1_APC_0: 0xffffffff
9642 01:17:33.021609 INFO: [APUAPC] D1_APC_1: 0xffffffff
9643 01:17:33.021690 INFO: [APUAPC] D1_APC_2: 0x3fffff
9644 01:17:33.021770 INFO: [APUAPC] D1_APC_3: 0x0
9645 01:17:33.021850 INFO: [APUAPC] D2_APC_0: 0xffffffff
9646 01:17:33.021931 INFO: [APUAPC] D2_APC_1: 0xffffffff
9647 01:17:33.022011 INFO: [APUAPC] D2_APC_2: 0x3fffff
9648 01:17:33.022136 INFO: [APUAPC] D2_APC_3: 0x0
9649 01:17:33.022217 INFO: [APUAPC] D3_APC_0: 0xffffffff
9650 01:17:33.022298 INFO: [APUAPC] D3_APC_1: 0xffffffff
9651 01:17:33.022378 INFO: [APUAPC] D3_APC_2: 0x3fffff
9652 01:17:33.022458 INFO: [APUAPC] D3_APC_3: 0x0
9653 01:17:33.022539 INFO: [APUAPC] D4_APC_0: 0xffffffff
9654 01:17:33.022620 INFO: [APUAPC] D4_APC_1: 0xffffffff
9655 01:17:33.022701 INFO: [APUAPC] D4_APC_2: 0x3fffff
9656 01:17:33.022781 INFO: [APUAPC] D4_APC_3: 0x0
9657 01:17:33.022861 INFO: [APUAPC] D5_APC_0: 0xffffffff
9658 01:17:33.022941 INFO: [APUAPC] D5_APC_1: 0xffffffff
9659 01:17:33.023022 INFO: [APUAPC] D5_APC_2: 0x3fffff
9660 01:17:33.023102 INFO: [APUAPC] D5_APC_3: 0x0
9661 01:17:33.023182 INFO: [APUAPC] D6_APC_0: 0xffffffff
9662 01:17:33.023262 INFO: [APUAPC] D6_APC_1: 0xffffffff
9663 01:17:33.023342 INFO: [APUAPC] D6_APC_2: 0x3fffff
9664 01:17:33.023422 INFO: [APUAPC] D6_APC_3: 0x0
9665 01:17:33.023502 INFO: [APUAPC] D7_APC_0: 0xffffffff
9666 01:17:33.023583 INFO: [APUAPC] D7_APC_1: 0xffffffff
9667 01:17:33.023663 INFO: [APUAPC] D7_APC_2: 0x3fffff
9668 01:17:33.023743 INFO: [APUAPC] D7_APC_3: 0x0
9669 01:17:33.023823 INFO: [APUAPC] D8_APC_0: 0xffffffff
9670 01:17:33.023904 INFO: [APUAPC] D8_APC_1: 0xffffffff
9671 01:17:33.023984 INFO: [APUAPC] D8_APC_2: 0x3fffff
9672 01:17:33.024064 INFO: [APUAPC] D8_APC_3: 0x0
9673 01:17:33.024144 INFO: [APUAPC] D9_APC_0: 0xffffffff
9674 01:17:33.024224 INFO: [APUAPC] D9_APC_1: 0xffffffff
9675 01:17:33.024305 INFO: [APUAPC] D9_APC_2: 0x3fffff
9676 01:17:33.024385 INFO: [APUAPC] D9_APC_3: 0x0
9677 01:17:33.024465 INFO: [APUAPC] D10_APC_0: 0xffffffff
9678 01:17:33.024545 INFO: [APUAPC] D10_APC_1: 0xffffffff
9679 01:17:33.024626 INFO: [APUAPC] D10_APC_2: 0x3fffff
9680 01:17:33.024706 INFO: [APUAPC] D10_APC_3: 0x0
9681 01:17:33.024786 INFO: [APUAPC] D11_APC_0: 0xffffffff
9682 01:17:33.024866 INFO: [APUAPC] D11_APC_1: 0xffffffff
9683 01:17:33.024947 INFO: [APUAPC] D11_APC_2: 0x3fffff
9684 01:17:33.025027 INFO: [APUAPC] D11_APC_3: 0x0
9685 01:17:33.025107 INFO: [APUAPC] D12_APC_0: 0xffffffff
9686 01:17:33.025188 INFO: [APUAPC] D12_APC_1: 0xffffffff
9687 01:17:33.025268 INFO: [APUAPC] D12_APC_2: 0x3fffff
9688 01:17:33.025351 INFO: [APUAPC] D12_APC_3: 0x0
9689 01:17:33.025432 INFO: [APUAPC] D13_APC_0: 0xffffffff
9690 01:17:33.025517 INFO: [APUAPC] D13_APC_1: 0xffffffff
9691 01:17:33.025613 INFO: [APUAPC] D13_APC_2: 0x3fffff
9692 01:17:33.025698 INFO: [APUAPC] D13_APC_3: 0x0
9693 01:17:33.025780 INFO: [APUAPC] D14_APC_0: 0xffffffff
9694 01:17:33.025860 INFO: [APUAPC] D14_APC_1: 0xffffffff
9695 01:17:33.025941 INFO: [APUAPC] D14_APC_2: 0x3fffff
9696 01:17:33.026021 INFO: [APUAPC] D14_APC_3: 0x0
9697 01:17:33.026115 INFO: [APUAPC] D15_APC_0: 0xffffffff
9698 01:17:33.026167 INFO: [APUAPC] D15_APC_1: 0xffffffff
9699 01:17:33.026219 INFO: [APUAPC] D15_APC_2: 0x3fffff
9700 01:17:33.026270 INFO: [APUAPC] D15_APC_3: 0x0
9701 01:17:33.026322 INFO: [APUAPC] APC_CON: 0x4
9702 01:17:33.026373 INFO: [NOCDAPC] D0_APC_0: 0x0
9703 01:17:33.026428 INFO: [NOCDAPC] D0_APC_1: 0x0
9704 01:17:33.026479 INFO: [NOCDAPC] D1_APC_0: 0x0
9705 01:17:33.026530 INFO: [NOCDAPC] D1_APC_1: 0xfff
9706 01:17:33.026581 INFO: [NOCDAPC] D2_APC_0: 0x0
9707 01:17:33.026633 INFO: [NOCDAPC] D2_APC_1: 0xfff
9708 01:17:33.026684 INFO: [NOCDAPC] D3_APC_0: 0x0
9709 01:17:33.026735 INFO: [NOCDAPC] D3_APC_1: 0xfff
9710 01:17:33.026809 INFO: [NOCDAPC] D4_APC_0: 0x0
9711 01:17:33.026911 INFO: [NOCDAPC] D4_APC_1: 0xfff
9712 01:17:33.026978 INFO: [NOCDAPC] D5_APC_0: 0x0
9713 01:17:33.027033 INFO: [NOCDAPC] D5_APC_1: 0xfff
9714 01:17:33.027098 INFO: [NOCDAPC] D6_APC_0: 0x0
9715 01:17:33.027157 INFO: [NOCDAPC] D6_APC_1: 0xfff
9716 01:17:33.027210 INFO: [NOCDAPC] D7_APC_0: 0x0
9717 01:17:33.027269 INFO: [NOCDAPC] D7_APC_1: 0xfff
9718 01:17:33.027353 INFO: [NOCDAPC] D8_APC_0: 0x0
9719 01:17:33.027440 INFO: [NOCDAPC] D8_APC_1: 0xfff
9720 01:17:33.027523 INFO: [NOCDAPC] D9_APC_0: 0x0
9721 01:17:33.027604 INFO: [NOCDAPC] D9_APC_1: 0xfff
9722 01:17:33.027692 INFO: [NOCDAPC] D10_APC_0: 0x0
9723 01:17:33.027777 INFO: [NOCDAPC] D10_APC_1: 0xfff
9724 01:17:33.027863 INFO: [NOCDAPC] D11_APC_0: 0x0
9725 01:17:33.027949 INFO: [NOCDAPC] D11_APC_1: 0xfff
9726 01:17:33.028031 INFO: [NOCDAPC] D12_APC_0: 0x0
9727 01:17:33.028116 INFO: [NOCDAPC] D12_APC_1: 0xfff
9728 01:17:33.028202 INFO: [NOCDAPC] D13_APC_0: 0x0
9729 01:17:33.028288 INFO: [NOCDAPC] D13_APC_1: 0xfff
9730 01:17:33.028374 INFO: [NOCDAPC] D14_APC_0: 0x0
9731 01:17:33.028459 INFO: [NOCDAPC] D14_APC_1: 0xfff
9732 01:17:33.028541 INFO: [NOCDAPC] D15_APC_0: 0x0
9733 01:17:33.028622 INFO: [NOCDAPC] D15_APC_1: 0xfff
9734 01:17:33.028702 INFO: [NOCDAPC] APC_CON: 0x4
9735 01:17:33.028782 INFO: [APUAPC] set_apusys_apc done
9736 01:17:33.028862 INFO: [DEVAPC] devapc_init done
9737 01:17:33.028943 INFO: GICv3 without legacy support detected.
9738 01:17:33.029024 INFO: ARM GICv3 driver initialized in EL3
9739 01:17:33.029105 INFO: Maximum SPI INTID supported: 639
9740 01:17:33.029186 INFO: BL31: Initializing runtime services
9741 01:17:33.029268 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9742 01:17:33.029349 INFO: SPM: enable CPC mode
9743 01:17:33.029431 INFO: mcdi ready for mcusys-off-idle and system suspend
9744 01:17:33.029513 INFO: BL31: Preparing for EL3 exit to normal world
9745 01:17:33.029593 INFO: Entry point address = 0x80000000
9746 01:17:33.029674 INFO: SPSR = 0x8
9747 01:17:33.029753
9748 01:17:33.029833
9749 01:17:33.029912
9750 01:17:33.029993 Starting depthcharge on Spherion...
9751 01:17:33.030121
9752 01:17:33.030814 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
9753 01:17:33.030936 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
9754 01:17:33.031043 Setting prompt string to ['asurada:']
9755 01:17:33.031145 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
9756 01:17:33.031332 Wipe memory regions:
9757 01:17:33.031423
9758 01:17:33.031509 [0x00000040000000, 0x00000054600000)
9759 01:17:33.031593
9760 01:17:33.031676 [0x00000054660000, 0x00000080000000)
9761 01:17:33.031757
9762 01:17:33.031838 [0x000000821a7280, 0x000000ffe64000)
9763 01:17:33.065932
9764 01:17:33.066011 [0x00000100000000, 0x00000140000000)
9765 01:17:33.447309
9766 01:17:33.450347 Initializing XHCI USB controller at 0x11200000.
9767 01:17:34.488733
9768 01:17:34.491916 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9769 01:17:34.492522
9770 01:17:34.492898
9771 01:17:34.493240
9772 01:17:34.494074 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9774 01:17:34.595349 asurada: tftpboot 192.168.201.1 13468749/tftp-deploy-6yq5_lze/kernel/image.itb 13468749/tftp-deploy-6yq5_lze/kernel/cmdline
9775 01:17:34.596009 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9776 01:17:34.596480 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9777 01:17:34.601089 tftpboot 192.168.201.1 13468749/tftp-deploy-6yq5_lze/kernel/image.itp-deploy-6yq5_lze/kernel/cmdline
9778 01:17:34.601666
9779 01:17:34.602080 Waiting for link
9780 01:17:34.761476
9781 01:17:34.762090 R8152: Initializing
9782 01:17:34.762487
9783 01:17:34.764657 Version 9 (ocp_data = 6010)
9784 01:17:34.765227
9785 01:17:34.768028 R8152: Done initializing
9786 01:17:34.768609
9787 01:17:34.768986 Adding net device
9788 01:17:36.776227
9789 01:17:36.776753 done.
9790 01:17:36.777094
9791 01:17:36.777409 MAC: 00:e0:4c:68:03:bd
9792 01:17:36.777717
9793 01:17:36.779336 Sending DHCP discover... done.
9794 01:17:36.779812
9795 01:17:45.673790 Waiting for reply... done.
9796 01:17:45.674400
9797 01:17:45.674781 Sending DHCP request... done.
9798 01:17:45.677639
9799 01:17:45.683120 Waiting for reply... done.
9800 01:17:45.683692
9801 01:17:45.684071 My ip is 192.168.201.16
9802 01:17:45.684419
9803 01:17:45.686210 The DHCP server ip is 192.168.201.1
9804 01:17:45.686608
9805 01:17:45.693271 TFTP server IP predefined by user: 192.168.201.1
9806 01:17:45.693856
9807 01:17:45.699747 Bootfile predefined by user: 13468749/tftp-deploy-6yq5_lze/kernel/image.itb
9808 01:17:45.700321
9809 01:17:45.700766 Sending tftp read request... done.
9810 01:17:45.702617
9811 01:17:45.709000 Waiting for the transfer...
9812 01:17:45.709573
9813 01:17:46.095186 00000000 ################################################################
9814 01:17:46.095905
9815 01:17:46.373031 00080000 ################################################################
9816 01:17:46.373199
9817 01:17:46.639907 00100000 ################################################################
9818 01:17:46.640044
9819 01:17:46.924390 00180000 ################################################################
9820 01:17:46.924554
9821 01:17:47.196405 00200000 ################################################################
9822 01:17:47.196575
9823 01:17:47.485892 00280000 ################################################################
9824 01:17:47.486057
9825 01:17:47.779894 00300000 ################################################################
9826 01:17:47.780030
9827 01:17:48.076370 00380000 ################################################################
9828 01:17:48.076505
9829 01:17:48.342643 00400000 ################################################################
9830 01:17:48.342789
9831 01:17:48.611208 00480000 ################################################################
9832 01:17:48.611358
9833 01:17:48.898533 00500000 ################################################################
9834 01:17:48.898679
9835 01:17:49.193463 00580000 ################################################################
9836 01:17:49.193600
9837 01:17:49.473950 00600000 ################################################################
9838 01:17:49.474103
9839 01:17:49.761917 00680000 ################################################################
9840 01:17:49.762082
9841 01:17:50.056122 00700000 ################################################################
9842 01:17:50.056259
9843 01:17:50.317093 00780000 ################################################################
9844 01:17:50.317230
9845 01:17:50.600499 00800000 ################################################################
9846 01:17:50.600647
9847 01:17:50.852482 00880000 ################################################################
9848 01:17:50.852620
9849 01:17:51.123569 00900000 ################################################################
9850 01:17:51.123707
9851 01:17:51.414846 00980000 ################################################################
9852 01:17:51.414987
9853 01:17:51.693603 00a00000 ################################################################
9854 01:17:51.693753
9855 01:17:51.957357 00a80000 ################################################################
9856 01:17:51.957498
9857 01:17:52.230499 00b00000 ################################################################
9858 01:17:52.230639
9859 01:17:52.480815 00b80000 ################################################################
9860 01:17:52.480951
9861 01:17:52.731656 00c00000 ################################################################
9862 01:17:52.731795
9863 01:17:53.009259 00c80000 ################################################################
9864 01:17:53.009406
9865 01:17:53.301210 00d00000 ################################################################
9866 01:17:53.301345
9867 01:17:53.577859 00d80000 ################################################################
9868 01:17:53.577995
9869 01:17:53.856006 00e00000 ################################################################
9870 01:17:53.856143
9871 01:17:54.106094 00e80000 ################################################################
9872 01:17:54.106231
9873 01:17:54.367903 00f00000 ################################################################
9874 01:17:54.368064
9875 01:17:54.631175 00f80000 ################################################################
9876 01:17:54.631307
9877 01:17:54.882724 01000000 ################################################################
9878 01:17:54.882856
9879 01:17:55.154184 01080000 ################################################################
9880 01:17:55.154330
9881 01:17:55.417858 01100000 ################################################################
9882 01:17:55.417999
9883 01:17:55.688288 01180000 ################################################################
9884 01:17:55.688427
9885 01:17:55.978721 01200000 ################################################################
9886 01:17:55.978860
9887 01:17:56.256040 01280000 ################################################################
9888 01:17:56.256182
9889 01:17:56.523589 01300000 ################################################################
9890 01:17:56.523726
9891 01:17:56.816447 01380000 ################################################################
9892 01:17:56.816588
9893 01:17:57.113732 01400000 ################################################################
9894 01:17:57.113871
9895 01:17:57.391334 01480000 ################################################################
9896 01:17:57.391482
9897 01:17:57.684634 01500000 ################################################################
9898 01:17:57.684798
9899 01:17:57.966860 01580000 ################################################################
9900 01:17:57.966997
9901 01:17:58.236878 01600000 ################################################################
9902 01:17:58.237038
9903 01:17:58.507918 01680000 ################################################################
9904 01:17:58.508066
9905 01:17:58.761715 01700000 ################################################################
9906 01:17:58.761879
9907 01:17:59.035150 01780000 ################################################################
9908 01:17:59.035317
9909 01:17:59.287378 01800000 ################################################################
9910 01:17:59.287514
9911 01:17:59.571301 01880000 ################################################################
9912 01:17:59.571463
9913 01:17:59.849951 01900000 ################################################################
9914 01:17:59.850132
9915 01:18:00.145848 01980000 ################################################################
9916 01:18:00.145986
9917 01:18:00.436774 01a00000 ################################################################
9918 01:18:00.436910
9919 01:18:00.704138 01a80000 ################################################################
9920 01:18:00.704276
9921 01:18:00.954096 01b00000 ################################################################
9922 01:18:00.954235
9923 01:18:01.204336 01b80000 ################################################################
9924 01:18:01.204470
9925 01:18:01.470381 01c00000 ################################################################
9926 01:18:01.470514
9927 01:18:01.737260 01c80000 ################################################################
9928 01:18:01.737424
9929 01:18:02.002301 01d00000 ################################################################
9930 01:18:02.002434
9931 01:18:02.257628 01d80000 ################################################################
9932 01:18:02.257762
9933 01:18:02.540970 01e00000 ################################################################
9934 01:18:02.541116
9935 01:18:02.837504 01e80000 ################################################################
9936 01:18:02.837644
9937 01:18:03.116776 01f00000 ################################################################
9938 01:18:03.116918
9939 01:18:03.399493 01f80000 ################################################################
9940 01:18:03.399635
9941 01:18:03.692935 02000000 ################################################################
9942 01:18:03.693074
9943 01:18:03.960420 02080000 ################################################################
9944 01:18:03.960554
9945 01:18:04.223427 02100000 ################################################################
9946 01:18:04.223566
9947 01:18:04.481612 02180000 ################################################################
9948 01:18:04.481749
9949 01:18:04.742363 02200000 ################################################################
9950 01:18:04.742501
9951 01:18:05.009967 02280000 ################################################################
9952 01:18:05.010116
9953 01:18:05.285539 02300000 ################################################################
9954 01:18:05.285678
9955 01:18:05.554965 02380000 ################################################################
9956 01:18:05.555105
9957 01:18:05.805594 02400000 ################################################################
9958 01:18:05.805726
9959 01:18:06.084125 02480000 ################################################################
9960 01:18:06.084266
9961 01:18:06.379857 02500000 ################################################################
9962 01:18:06.379997
9963 01:18:06.654074 02580000 ################################################################
9964 01:18:06.654283
9965 01:18:06.950372 02600000 ################################################################
9966 01:18:06.950512
9967 01:18:07.247104 02680000 ################################################################
9968 01:18:07.247245
9969 01:18:07.506952 02700000 ################################################################
9970 01:18:07.507078
9971 01:18:07.789406 02780000 ################################################################
9972 01:18:07.789549
9973 01:18:08.071345 02800000 ################################################################
9974 01:18:08.071480
9975 01:18:08.336798 02880000 ################################################################
9976 01:18:08.336929
9977 01:18:08.604615 02900000 ################################################################
9978 01:18:08.604763
9979 01:18:08.869894 02980000 ################################################################
9980 01:18:08.870043
9981 01:18:09.161249 02a00000 ################################################################
9982 01:18:09.161386
9983 01:18:09.454268 02a80000 ################################################################
9984 01:18:09.454402
9985 01:18:09.725072 02b00000 ################################################################
9986 01:18:09.725205
9987 01:18:09.986274 02b80000 ################################################################
9988 01:18:09.986411
9989 01:18:10.256872 02c00000 ################################################################
9990 01:18:10.257004
9991 01:18:10.518031 02c80000 ################################################################
9992 01:18:10.518174
9993 01:18:10.810389 02d00000 ################################################################
9994 01:18:10.810530
9995 01:18:11.072294 02d80000 ################################################################
9996 01:18:11.072433
9997 01:18:11.356877 02e00000 ################################################################
9998 01:18:11.357016
9999 01:18:11.627403 02e80000 ################################################################
10000 01:18:11.627538
10001 01:18:11.883043 02f00000 ################################################################
10002 01:18:11.883173
10003 01:18:12.136318 02f80000 ################################################################
10004 01:18:12.136458
10005 01:18:12.398510 03000000 ################################################################
10006 01:18:12.398657
10007 01:18:12.648838 03080000 ################################################################
10008 01:18:12.648973
10009 01:18:12.924903 03100000 ################################################################
10010 01:18:12.925046
10011 01:18:13.204242 03180000 ################################################################
10012 01:18:13.204411
10013 01:18:13.461569 03200000 ################################################################
10014 01:18:13.461711
10015 01:18:13.749609 03280000 ################################################################
10016 01:18:13.749746
10017 01:18:14.038896 03300000 ################################################################
10018 01:18:14.039028
10019 01:18:14.309169 03380000 ################################################################
10020 01:18:14.309302
10021 01:18:14.583232 03400000 ################################################################
10022 01:18:14.583373
10023 01:18:14.841967 03480000 ################################################################
10024 01:18:14.842144
10025 01:18:15.093145 03500000 ################################################################
10026 01:18:15.093278
10027 01:18:15.357556 03580000 ################################################################
10028 01:18:15.357729
10029 01:18:15.652021 03600000 ################################################################
10030 01:18:15.652164
10031 01:18:15.908677 03680000 ################################################################
10032 01:18:15.908813
10033 01:18:16.160946 03700000 ################################################################
10034 01:18:16.161079
10035 01:18:16.457919 03780000 ################################################################
10036 01:18:16.458062
10037 01:18:16.751527 03800000 ################################################################
10038 01:18:16.751670
10039 01:18:17.028437 03880000 ################################################################
10040 01:18:17.028598
10041 01:18:17.322922 03900000 ################################################################
10042 01:18:17.323060
10043 01:18:17.619880 03980000 ################################################################
10044 01:18:17.620021
10045 01:18:17.892768 03a00000 ################################################################
10046 01:18:17.892933
10047 01:18:18.178896 03a80000 ################################################################
10048 01:18:18.179031
10049 01:18:18.475699 03b00000 ################################################################
10050 01:18:18.475835
10051 01:18:18.776427 03b80000 ################################################################
10052 01:18:18.776567
10053 01:18:19.053459 03c00000 ################################################################
10054 01:18:19.053606
10055 01:18:19.335769 03c80000 ################################################################
10056 01:18:19.335907
10057 01:18:19.624673 03d00000 ################################################################
10058 01:18:19.624808
10059 01:18:19.922347 03d80000 ################################################################
10060 01:18:19.922482
10061 01:18:20.216508 03e00000 ################################################################
10062 01:18:20.216648
10063 01:18:20.509912 03e80000 ################################################################
10064 01:18:20.510135
10065 01:18:20.797333 03f00000 ################################################################
10066 01:18:20.797473
10067 01:18:21.094152 03f80000 ################################################################
10068 01:18:21.094287
10069 01:18:21.389542 04000000 ################################################################
10070 01:18:21.389690
10071 01:18:21.673121 04080000 ################################################################
10072 01:18:21.673264
10073 01:18:21.970121 04100000 ################################################################
10074 01:18:21.970259
10075 01:18:22.266122 04180000 ################################################################
10076 01:18:22.266260
10077 01:18:22.554208 04200000 ################################################################
10078 01:18:22.554376
10079 01:18:22.844951 04280000 ################################################################
10080 01:18:22.845112
10081 01:18:23.141228 04300000 ################################################################
10082 01:18:23.141389
10083 01:18:23.435901 04380000 ################################################################
10084 01:18:23.436044
10085 01:18:23.730156 04400000 ################################################################
10086 01:18:23.730328
10087 01:18:24.024634 04480000 ################################################################
10088 01:18:24.024773
10089 01:18:24.321606 04500000 ################################################################
10090 01:18:24.321743
10091 01:18:24.607705 04580000 ################################################################
10092 01:18:24.607842
10093 01:18:24.903211 04600000 ################################################################
10094 01:18:24.903355
10095 01:18:24.940517 04680000 ######### done.
10096 01:18:24.940605
10097 01:18:24.943993 The bootfile was 73992074 bytes long.
10098 01:18:24.944082
10099 01:18:24.947030 Sending tftp read request... done.
10100 01:18:24.947118
10101 01:18:24.950310 Waiting for the transfer...
10102 01:18:24.950404
10103 01:18:24.950479 00000000 # done.
10104 01:18:24.950551
10105 01:18:24.960462 Command line loaded dynamically from TFTP file: 13468749/tftp-deploy-6yq5_lze/kernel/cmdline
10106 01:18:24.960654
10107 01:18:24.973713 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10108 01:18:24.973952
10109 01:18:24.974117 Loading FIT.
10110 01:18:24.974248
10111 01:18:24.976795 Image ramdisk-1 has 61032760 bytes.
10112 01:18:24.977031
10113 01:18:24.980186 Image fdt-1 has 47230 bytes.
10114 01:18:24.980443
10115 01:18:24.983614 Image kernel-1 has 12910050 bytes.
10116 01:18:24.983900
10117 01:18:24.990198 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10118 01:18:24.990528
10119 01:18:25.010133 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10120 01:18:25.010705
10121 01:18:25.013592 Choosing best match conf-1 for compat google,spherion-rev3.
10122 01:18:25.018863
10123 01:18:25.023373 Connected to device vid:did:rid of 1ae0:0028:00
10124 01:18:25.030484
10125 01:18:25.033953 tpm_get_response: command 0x17b, return code 0x0
10126 01:18:25.034559
10127 01:18:25.037392 ec_init: CrosEC protocol v3 supported (256, 248)
10128 01:18:25.040836
10129 01:18:25.044272 tpm_cleanup: add release locality here.
10130 01:18:25.044744
10131 01:18:25.045117 Shutting down all USB controllers.
10132 01:18:25.047373
10133 01:18:25.047883 Removing current net device
10134 01:18:25.048450
10135 01:18:25.054119 Exiting depthcharge with code 4 at timestamp: 81389972
10136 01:18:25.054596
10137 01:18:25.057634 LZMA decompressing kernel-1 to 0x821a6718
10138 01:18:25.058202
10139 01:18:25.060651 LZMA decompressing kernel-1 to 0x40000000
10140 01:18:26.654657
10141 01:18:26.655231 jumping to kernel
10142 01:18:26.657650 end: 2.2.4 bootloader-commands (duration 00:00:54) [common]
10143 01:18:26.658227 start: 2.2.5 auto-login-action (timeout 00:03:32) [common]
10144 01:18:26.658645 Setting prompt string to ['Linux version [0-9]']
10145 01:18:26.659023 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10146 01:18:26.659232 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10147 01:18:26.706122
10148 01:18:26.709471 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10149 01:18:26.712982 start: 2.2.5.1 login-action (timeout 00:03:31) [common]
10150 01:18:26.713363 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10151 01:18:26.713605 Setting prompt string to []
10152 01:18:26.713864 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10153 01:18:26.714137 Using line separator: #'\n'#
10154 01:18:26.714343 No login prompt set.
10155 01:18:26.714548 Parsing kernel messages
10156 01:18:26.714736 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10157 01:18:26.715062 [login-action] Waiting for messages, (timeout 00:03:31)
10158 01:18:26.715359 Waiting using forced prompt support (timeout 00:01:46)
10159 01:18:26.732625 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j174389-arm64-gcc-10-defconfig-arm64-chromebook-96m9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024
10160 01:18:26.735759 [ 0.000000] random: crng init done
10161 01:18:26.742663 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10162 01:18:26.745525 [ 0.000000] efi: UEFI not found.
10163 01:18:26.752123 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10164 01:18:26.762421 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10165 01:18:26.768598 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10166 01:18:26.778675 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10167 01:18:26.785451 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10168 01:18:26.792032 [ 0.000000] printk: bootconsole [mtk8250] enabled
10169 01:18:26.799120 [ 0.000000] NUMA: No NUMA configuration found
10170 01:18:26.805406 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10171 01:18:26.808550 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10172 01:18:26.812053 [ 0.000000] Zone ranges:
10173 01:18:26.818733 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10174 01:18:26.821755 [ 0.000000] DMA32 empty
10175 01:18:26.828552 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10176 01:18:26.831801 [ 0.000000] Movable zone start for each node
10177 01:18:26.834919 [ 0.000000] Early memory node ranges
10178 01:18:26.841566 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10179 01:18:26.849152 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10180 01:18:26.854685 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10181 01:18:26.861152 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10182 01:18:26.867682 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10183 01:18:26.874504 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10184 01:18:26.905339 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10185 01:18:26.911481 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10186 01:18:26.918712 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10187 01:18:26.921508 [ 0.000000] psci: probing for conduit method from DT.
10188 01:18:26.928416 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10189 01:18:26.931345 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10190 01:18:26.937920 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10191 01:18:26.941313 [ 0.000000] psci: SMC Calling Convention v1.2
10192 01:18:26.947973 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10193 01:18:26.951257 [ 0.000000] Detected VIPT I-cache on CPU0
10194 01:18:26.957904 [ 0.000000] CPU features: detected: GIC system register CPU interface
10195 01:18:26.964785 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10196 01:18:26.970813 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10197 01:18:26.977318 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10198 01:18:26.987758 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10199 01:18:26.994544 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10200 01:18:26.997328 [ 0.000000] alternatives: applying boot alternatives
10201 01:18:27.004110 [ 0.000000] Fallback order for Node 0: 0
10202 01:18:27.010545 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10203 01:18:27.013725 [ 0.000000] Policy zone: Normal
10204 01:18:27.026873 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10205 01:18:27.036960 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10206 01:18:27.048162 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10207 01:18:27.057398 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10208 01:18:27.064550 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10209 01:18:27.067624 <6>[ 0.000000] software IO TLB: area num 8.
10210 01:18:27.123271 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10211 01:18:27.205079 <6>[ 0.000000] Memory: 3790488K/4191232K available (18048K kernel code, 4118K rwdata, 22292K rodata, 8448K init, 616K bss, 367976K reserved, 32768K cma-reserved)
10212 01:18:27.211193 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10213 01:18:27.217884 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10214 01:18:27.221118 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10215 01:18:27.227320 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10216 01:18:27.234093 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10217 01:18:27.237610 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10218 01:18:27.247183 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10219 01:18:27.254347 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10220 01:18:27.260455 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10221 01:18:27.266920 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10222 01:18:27.270833 <6>[ 0.000000] GICv3: 608 SPIs implemented
10223 01:18:27.274062 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10224 01:18:27.280491 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10225 01:18:27.283550 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10226 01:18:27.290787 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10227 01:18:27.303465 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10228 01:18:27.316431 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10229 01:18:27.323106 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10230 01:18:27.331035 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10231 01:18:27.344312 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10232 01:18:27.350488 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10233 01:18:27.357429 <6>[ 0.009175] Console: colour dummy device 80x25
10234 01:18:27.367565 <6>[ 0.013904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10235 01:18:27.374139 <6>[ 0.024346] pid_max: default: 32768 minimum: 301
10236 01:18:27.377192 <6>[ 0.029218] LSM: Security Framework initializing
10237 01:18:27.383928 <6>[ 0.034131] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10238 01:18:27.393681 <6>[ 0.041785] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10239 01:18:27.400216 <6>[ 0.051067] cblist_init_generic: Setting adjustable number of callback queues.
10240 01:18:27.407244 <6>[ 0.058555] cblist_init_generic: Setting shift to 3 and lim to 1.
10241 01:18:27.417046 <6>[ 0.064933] cblist_init_generic: Setting adjustable number of callback queues.
10242 01:18:27.420397 <6>[ 0.072359] cblist_init_generic: Setting shift to 3 and lim to 1.
10243 01:18:27.426844 <6>[ 0.078758] rcu: Hierarchical SRCU implementation.
10244 01:18:27.433616 <6>[ 0.083804] rcu: Max phase no-delay instances is 1000.
10245 01:18:27.440267 <6>[ 0.090832] EFI services will not be available.
10246 01:18:27.443270 <6>[ 0.095815] smp: Bringing up secondary CPUs ...
10247 01:18:27.451884 <6>[ 0.100891] Detected VIPT I-cache on CPU1
10248 01:18:27.458078 <6>[ 0.100958] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10249 01:18:27.464408 <6>[ 0.100989] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10250 01:18:27.467542 <6>[ 0.101315] Detected VIPT I-cache on CPU2
10251 01:18:27.477314 <6>[ 0.101364] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10252 01:18:27.483921 <6>[ 0.101379] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10253 01:18:27.487254 <6>[ 0.101635] Detected VIPT I-cache on CPU3
10254 01:18:27.494012 <6>[ 0.101680] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10255 01:18:27.500891 <6>[ 0.101694] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10256 01:18:27.503955 <6>[ 0.101994] CPU features: detected: Spectre-v4
10257 01:18:27.510757 <6>[ 0.102000] CPU features: detected: Spectre-BHB
10258 01:18:27.514122 <6>[ 0.102005] Detected PIPT I-cache on CPU4
10259 01:18:27.520537 <6>[ 0.102064] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10260 01:18:27.527374 <6>[ 0.102082] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10261 01:18:27.533610 <6>[ 0.102372] Detected PIPT I-cache on CPU5
10262 01:18:27.540247 <6>[ 0.102435] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10263 01:18:27.546995 <6>[ 0.102451] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10264 01:18:27.550223 <6>[ 0.102732] Detected PIPT I-cache on CPU6
10265 01:18:27.560102 <6>[ 0.102798] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10266 01:18:27.566660 <6>[ 0.102814] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10267 01:18:27.570076 <6>[ 0.103114] Detected PIPT I-cache on CPU7
10268 01:18:27.576576 <6>[ 0.103182] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10269 01:18:27.583231 <6>[ 0.103199] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10270 01:18:27.586515 <6>[ 0.103245] smp: Brought up 1 node, 8 CPUs
10271 01:18:27.593200 <6>[ 0.244527] SMP: Total of 8 processors activated.
10272 01:18:27.596417 <6>[ 0.249448] CPU features: detected: 32-bit EL0 Support
10273 01:18:27.606498 <6>[ 0.254811] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10274 01:18:27.612945 <6>[ 0.263666] CPU features: detected: Common not Private translations
10275 01:18:27.619540 <6>[ 0.270142] CPU features: detected: CRC32 instructions
10276 01:18:27.626063 <6>[ 0.275526] CPU features: detected: RCpc load-acquire (LDAPR)
10277 01:18:27.629173 <6>[ 0.281486] CPU features: detected: LSE atomic instructions
10278 01:18:27.635576 <6>[ 0.287303] CPU features: detected: Privileged Access Never
10279 01:18:27.641915 <6>[ 0.293083] CPU features: detected: RAS Extension Support
10280 01:18:27.648972 <6>[ 0.298726] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10281 01:18:27.652056 <6>[ 0.305945] CPU: All CPU(s) started at EL2
10282 01:18:27.658876 <6>[ 0.310289] alternatives: applying system-wide alternatives
10283 01:18:27.668222 <6>[ 0.320241] devtmpfs: initialized
10284 01:18:27.679919 <6>[ 0.328560] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10285 01:18:27.690317 <6>[ 0.338517] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10286 01:18:27.696740 <6>[ 0.346749] pinctrl core: initialized pinctrl subsystem
10287 01:18:27.699787 <6>[ 0.353614] DMI not present or invalid.
10288 01:18:27.706369 <6>[ 0.358018] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10289 01:18:27.716563 <6>[ 0.364882] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10290 01:18:27.723204 <6>[ 0.372326] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10291 01:18:27.733136 <6>[ 0.380418] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10292 01:18:27.735917 <6>[ 0.388569] audit: initializing netlink subsys (disabled)
10293 01:18:27.746020 <5>[ 0.394263] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10294 01:18:27.752723 <6>[ 0.395004] thermal_sys: Registered thermal governor 'step_wise'
10295 01:18:27.759035 <6>[ 0.402228] thermal_sys: Registered thermal governor 'power_allocator'
10296 01:18:27.762439 <6>[ 0.408486] cpuidle: using governor menu
10297 01:18:27.769050 <6>[ 0.419443] NET: Registered PF_QIPCRTR protocol family
10298 01:18:27.775761 <6>[ 0.424931] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10299 01:18:27.782169 <6>[ 0.432034] ASID allocator initialised with 32768 entries
10300 01:18:27.785531 <6>[ 0.438638] Serial: AMBA PL011 UART driver
10301 01:18:27.795850 <4>[ 0.447704] Trying to register duplicate clock ID: 134
10302 01:18:27.852659 <6>[ 0.507897] KASLR enabled
10303 01:18:27.867032 <6>[ 0.515630] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10304 01:18:27.873857 <6>[ 0.522643] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10305 01:18:27.880425 <6>[ 0.529131] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10306 01:18:27.886672 <6>[ 0.536136] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10307 01:18:27.893468 <6>[ 0.542620] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10308 01:18:27.899857 <6>[ 0.549627] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10309 01:18:27.906369 <6>[ 0.556118] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10310 01:18:27.912902 <6>[ 0.563118] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10311 01:18:27.916368 <6>[ 0.570630] ACPI: Interpreter disabled.
10312 01:18:27.925190 <6>[ 0.577116] iommu: Default domain type: Translated
10313 01:18:27.931875 <6>[ 0.582225] iommu: DMA domain TLB invalidation policy: strict mode
10314 01:18:27.935278 <5>[ 0.588880] SCSI subsystem initialized
10315 01:18:27.941856 <6>[ 0.593040] usbcore: registered new interface driver usbfs
10316 01:18:27.947864 <6>[ 0.598771] usbcore: registered new interface driver hub
10317 01:18:27.951465 <6>[ 0.604321] usbcore: registered new device driver usb
10318 01:18:27.958138 <6>[ 0.610452] pps_core: LinuxPPS API ver. 1 registered
10319 01:18:27.968141 <6>[ 0.615647] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10320 01:18:27.971312 <6>[ 0.624990] PTP clock support registered
10321 01:18:27.974885 <6>[ 0.629231] EDAC MC: Ver: 3.0.0
10322 01:18:27.982310 <6>[ 0.634411] FPGA manager framework
10323 01:18:27.988970 <6>[ 0.638090] Advanced Linux Sound Architecture Driver Initialized.
10324 01:18:27.992207 <6>[ 0.644871] vgaarb: loaded
10325 01:18:27.998998 <6>[ 0.648038] clocksource: Switched to clocksource arch_sys_counter
10326 01:18:28.002334 <5>[ 0.654481] VFS: Disk quotas dquot_6.6.0
10327 01:18:28.009071 <6>[ 0.658667] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10328 01:18:28.011781 <6>[ 0.665854] pnp: PnP ACPI: disabled
10329 01:18:28.020154 <6>[ 0.672489] NET: Registered PF_INET protocol family
10330 01:18:28.026833 <6>[ 0.677872] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10331 01:18:28.039148 <6>[ 0.687884] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10332 01:18:28.049099 <6>[ 0.696668] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10333 01:18:28.055717 <6>[ 0.704635] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10334 01:18:28.062278 <6>[ 0.713034] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10335 01:18:28.073315 <6>[ 0.721691] TCP: Hash tables configured (established 32768 bind 32768)
10336 01:18:28.079620 <6>[ 0.728547] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10337 01:18:28.086173 <6>[ 0.735568] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10338 01:18:28.092807 <6>[ 0.743091] NET: Registered PF_UNIX/PF_LOCAL protocol family
10339 01:18:28.099458 <6>[ 0.749232] RPC: Registered named UNIX socket transport module.
10340 01:18:28.102692 <6>[ 0.755386] RPC: Registered udp transport module.
10341 01:18:28.109062 <6>[ 0.760317] RPC: Registered tcp transport module.
10342 01:18:28.115727 <6>[ 0.765247] RPC: Registered tcp NFSv4.1 backchannel transport module.
10343 01:18:28.119047 <6>[ 0.771909] PCI: CLS 0 bytes, default 64
10344 01:18:28.122254 <6>[ 0.776192] Unpacking initramfs...
10345 01:18:28.132352 <6>[ 0.780252] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10346 01:18:28.138845 <6>[ 0.788918] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10347 01:18:28.145365 <6>[ 0.797782] kvm [1]: IPA Size Limit: 40 bits
10348 01:18:28.148632 <6>[ 0.802307] kvm [1]: GICv3: no GICV resource entry
10349 01:18:28.155862 <6>[ 0.807327] kvm [1]: disabling GICv2 emulation
10350 01:18:28.161933 <6>[ 0.812014] kvm [1]: GIC system register CPU interface enabled
10351 01:18:28.165564 <6>[ 0.818179] kvm [1]: vgic interrupt IRQ18
10352 01:18:28.172007 <6>[ 0.822534] kvm [1]: VHE mode initialized successfully
10353 01:18:28.175418 <5>[ 0.829038] Initialise system trusted keyrings
10354 01:18:28.182123 <6>[ 0.833829] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10355 01:18:28.191834 <6>[ 0.843855] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10356 01:18:28.198567 <5>[ 0.850230] NFS: Registering the id_resolver key type
10357 01:18:28.201853 <5>[ 0.855523] Key type id_resolver registered
10358 01:18:28.208325 <5>[ 0.859937] Key type id_legacy registered
10359 01:18:28.215053 <6>[ 0.864214] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10360 01:18:28.221730 <6>[ 0.871137] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10361 01:18:28.227989 <6>[ 0.878850] 9p: Installing v9fs 9p2000 file system support
10362 01:18:28.265827 <5>[ 0.917623] Key type asymmetric registered
10363 01:18:28.268973 <5>[ 0.921953] Asymmetric key parser 'x509' registered
10364 01:18:28.278932 <6>[ 0.927083] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10365 01:18:28.282127 <6>[ 0.934695] io scheduler mq-deadline registered
10366 01:18:28.285367 <6>[ 0.939453] io scheduler kyber registered
10367 01:18:28.304478 <6>[ 0.956659] EINJ: ACPI disabled.
10368 01:18:28.337743 <4>[ 0.982909] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10369 01:18:28.347258 <4>[ 0.993616] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10370 01:18:28.362512 <6>[ 1.014557] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10371 01:18:28.370541 <6>[ 1.022504] printk: console [ttyS0] disabled
10372 01:18:28.398357 <6>[ 1.047134] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10373 01:18:28.405006 <6>[ 1.056608] printk: console [ttyS0] enabled
10374 01:18:28.408493 <6>[ 1.056608] printk: console [ttyS0] enabled
10375 01:18:28.414909 <6>[ 1.065502] printk: bootconsole [mtk8250] disabled
10376 01:18:28.418020 <6>[ 1.065502] printk: bootconsole [mtk8250] disabled
10377 01:18:28.424488 <6>[ 1.076621] SuperH (H)SCI(F) driver initialized
10378 01:18:28.428159 <6>[ 1.081929] msm_serial: driver initialized
10379 01:18:28.442567 <6>[ 1.090958] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10380 01:18:28.452493 <6>[ 1.099512] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10381 01:18:28.459200 <6>[ 1.108060] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10382 01:18:28.469112 <6>[ 1.116688] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10383 01:18:28.478676 <6>[ 1.125394] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10384 01:18:28.485526 <6>[ 1.134108] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10385 01:18:28.495465 <6>[ 1.142655] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10386 01:18:28.502339 <6>[ 1.151452] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10387 01:18:28.511870 <6>[ 1.159994] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10388 01:18:28.523755 <6>[ 1.175731] loop: module loaded
10389 01:18:28.530206 <6>[ 1.181670] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10390 01:18:28.553380 <4>[ 1.205216] mtk-pmic-keys: Failed to locate of_node [id: -1]
10391 01:18:28.560046 <6>[ 1.212093] megasas: 07.719.03.00-rc1
10392 01:18:28.569672 <6>[ 1.221961] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10393 01:18:28.579764 <6>[ 1.231423] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10394 01:18:28.596684 <6>[ 1.248139] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10395 01:18:28.653185 <6>[ 1.298217] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10396 01:18:30.842256 <6>[ 3.494102] Freeing initrd memory: 59600K
10397 01:18:30.854313 <6>[ 3.505842] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10398 01:18:30.865194 <6>[ 3.517081] tun: Universal TUN/TAP device driver, 1.6
10399 01:18:30.868490 <6>[ 3.523187] thunder_xcv, ver 1.0
10400 01:18:30.871719 <6>[ 3.526695] thunder_bgx, ver 1.0
10401 01:18:30.875002 <6>[ 3.530191] nicpf, ver 1.0
10402 01:18:30.885452 <6>[ 3.534253] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10403 01:18:30.889002 <6>[ 3.541730] hns3: Copyright (c) 2017 Huawei Corporation.
10404 01:18:30.895515 <6>[ 3.547318] hclge is initializing
10405 01:18:30.898925 <6>[ 3.550898] e1000: Intel(R) PRO/1000 Network Driver
10406 01:18:30.905670 <6>[ 3.556030] e1000: Copyright (c) 1999-2006 Intel Corporation.
10407 01:18:30.909131 <6>[ 3.562042] e1000e: Intel(R) PRO/1000 Network Driver
10408 01:18:30.915377 <6>[ 3.567258] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10409 01:18:30.921930 <6>[ 3.573445] igb: Intel(R) Gigabit Ethernet Network Driver
10410 01:18:30.928710 <6>[ 3.579095] igb: Copyright (c) 2007-2014 Intel Corporation.
10411 01:18:30.934943 <6>[ 3.584932] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10412 01:18:30.941854 <6>[ 3.591450] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10413 01:18:30.945106 <6>[ 3.597922] sky2: driver version 1.30
10414 01:18:30.951858 <6>[ 3.602945] VFIO - User Level meta-driver version: 0.3
10415 01:18:30.959152 <6>[ 3.611244] usbcore: registered new interface driver usb-storage
10416 01:18:30.965690 <6>[ 3.617698] usbcore: registered new device driver onboard-usb-hub
10417 01:18:30.974714 <6>[ 3.626942] mt6397-rtc mt6359-rtc: registered as rtc0
10418 01:18:30.984834 <6>[ 3.632409] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-23T01:18:29 UTC (1713835109)
10419 01:18:30.988186 <6>[ 3.641996] i2c_dev: i2c /dev entries driver
10420 01:18:31.005262 <6>[ 3.653973] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10421 01:18:31.011986 <4>[ 3.662715] cpu cpu0: supply cpu not found, using dummy regulator
10422 01:18:31.018615 <4>[ 3.669140] cpu cpu1: supply cpu not found, using dummy regulator
10423 01:18:31.025563 <4>[ 3.675544] cpu cpu2: supply cpu not found, using dummy regulator
10424 01:18:31.031546 <4>[ 3.681949] cpu cpu3: supply cpu not found, using dummy regulator
10425 01:18:31.038331 <4>[ 3.688358] cpu cpu4: supply cpu not found, using dummy regulator
10426 01:18:31.045185 <4>[ 3.694757] cpu cpu5: supply cpu not found, using dummy regulator
10427 01:18:31.051664 <4>[ 3.701153] cpu cpu6: supply cpu not found, using dummy regulator
10428 01:18:31.058124 <4>[ 3.707553] cpu cpu7: supply cpu not found, using dummy regulator
10429 01:18:31.075888 <6>[ 3.728170] cpu cpu0: EM: created perf domain
10430 01:18:31.079132 <6>[ 3.733099] cpu cpu4: EM: created perf domain
10431 01:18:31.086885 <6>[ 3.738666] sdhci: Secure Digital Host Controller Interface driver
10432 01:18:31.093102 <6>[ 3.745095] sdhci: Copyright(c) Pierre Ossman
10433 01:18:31.099833 <6>[ 3.750018] Synopsys Designware Multimedia Card Interface Driver
10434 01:18:31.106386 <6>[ 3.756613] sdhci-pltfm: SDHCI platform and OF driver helper
10435 01:18:31.109869 <6>[ 3.756653] mmc0: CQHCI version 5.10
10436 01:18:31.116486 <6>[ 3.766592] ledtrig-cpu: registered to indicate activity on CPUs
10437 01:18:31.123231 <6>[ 3.773556] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10438 01:18:31.129627 <6>[ 3.780581] usbcore: registered new interface driver usbhid
10439 01:18:31.132968 <6>[ 3.786405] usbhid: USB HID core driver
10440 01:18:31.139310 <6>[ 3.790610] spi_master spi0: will run message pump with realtime priority
10441 01:18:31.183110 <6>[ 3.828641] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10442 01:18:31.202286 <6>[ 3.843622] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10443 01:18:31.204940 <6>[ 3.858082] mmc0: Command Queue Engine enabled
10444 01:18:31.211839 <6>[ 3.862862] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10445 01:18:31.218363 <6>[ 3.869651] cros-ec-spi spi0.0: Chrome EC device registered
10446 01:18:31.221817 <6>[ 3.870384] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10447 01:18:31.234296 <6>[ 3.886177] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10448 01:18:31.241545 <6>[ 3.893362] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10449 01:18:31.248113 <6>[ 3.899345] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10450 01:18:31.254641 <6>[ 3.905321] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10451 01:18:31.270258 <6>[ 3.919195] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10452 01:18:31.277940 <6>[ 3.930097] NET: Registered PF_PACKET protocol family
10453 01:18:31.281149 <6>[ 3.935487] 9pnet: Installing 9P2000 support
10454 01:18:31.287863 <5>[ 3.940060] Key type dns_resolver registered
10455 01:18:31.291787 <6>[ 3.945020] registered taskstats version 1
10456 01:18:31.297890 <5>[ 3.949403] Loading compiled-in X.509 certificates
10457 01:18:31.327475 <4>[ 3.972981] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10458 01:18:31.337256 <4>[ 3.983884] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10459 01:18:31.344112 <3>[ 3.994446] debugfs: File 'uA_load' in directory '/' already present!
10460 01:18:31.350759 <3>[ 4.001153] debugfs: File 'min_uV' in directory '/' already present!
10461 01:18:31.357117 <3>[ 4.007766] debugfs: File 'max_uV' in directory '/' already present!
10462 01:18:31.363923 <3>[ 4.014373] debugfs: File 'constraint_flags' in directory '/' already present!
10463 01:18:31.375848 <3>[ 4.024529] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10464 01:18:31.389575 <6>[ 4.040964] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10465 01:18:31.395695 <6>[ 4.047750] xhci-mtk 11200000.usb: xHCI Host Controller
10466 01:18:31.402137 <6>[ 4.053263] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10467 01:18:31.412592 <6>[ 4.061123] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10468 01:18:31.419173 <6>[ 4.070553] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10469 01:18:31.425376 <6>[ 4.076701] xhci-mtk 11200000.usb: xHCI Host Controller
10470 01:18:31.432243 <6>[ 4.082195] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10471 01:18:31.438745 <6>[ 4.089861] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10472 01:18:31.445872 <6>[ 4.097888] hub 1-0:1.0: USB hub found
10473 01:18:31.449188 <6>[ 4.101924] hub 1-0:1.0: 1 port detected
10474 01:18:31.459067 <6>[ 4.106237] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10475 01:18:31.462594 <6>[ 4.115023] hub 2-0:1.0: USB hub found
10476 01:18:31.465545 <6>[ 4.119050] hub 2-0:1.0: 1 port detected
10477 01:18:31.474707 <6>[ 4.126829] mtk-msdc 11f70000.mmc: Got CD GPIO
10478 01:18:31.487340 <6>[ 4.136124] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10479 01:18:31.494229 <6>[ 4.144156] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10480 01:18:31.503804 <4>[ 4.152089] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10481 01:18:31.513671 <6>[ 4.161628] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10482 01:18:31.520451 <6>[ 4.169706] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10483 01:18:31.526930 <6>[ 4.177733] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10484 01:18:31.537074 <6>[ 4.185652] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10485 01:18:31.543197 <6>[ 4.193469] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10486 01:18:31.553541 <6>[ 4.201286] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10487 01:18:31.563419 <6>[ 4.211698] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10488 01:18:31.570292 <6>[ 4.220062] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10489 01:18:31.579639 <6>[ 4.228408] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10490 01:18:31.586218 <6>[ 4.236746] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10491 01:18:31.596353 <6>[ 4.245089] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10492 01:18:31.606356 <6>[ 4.253426] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10493 01:18:31.612673 <6>[ 4.261763] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10494 01:18:31.622756 <6>[ 4.270100] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10495 01:18:31.629306 <6>[ 4.278438] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10496 01:18:31.638901 <6>[ 4.286775] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10497 01:18:31.645793 <6>[ 4.295112] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10498 01:18:31.655515 <6>[ 4.303450] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10499 01:18:31.662283 <6>[ 4.311787] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10500 01:18:31.672106 <6>[ 4.320124] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10501 01:18:31.678972 <6>[ 4.328463] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10502 01:18:31.685355 <6>[ 4.337199] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10503 01:18:31.692344 <6>[ 4.344337] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10504 01:18:31.698680 <6>[ 4.351078] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10505 01:18:31.709850 <6>[ 4.357820] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10506 01:18:31.715921 <6>[ 4.364726] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10507 01:18:31.721936 <6>[ 4.371562] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10508 01:18:31.732071 <6>[ 4.380691] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10509 01:18:31.741857 <6>[ 4.389809] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10510 01:18:31.751853 <6>[ 4.399101] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10511 01:18:31.761939 <6>[ 4.408568] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10512 01:18:31.768327 <6>[ 4.418034] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10513 01:18:31.778545 <6>[ 4.427153] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10514 01:18:31.788070 <6>[ 4.436622] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10515 01:18:31.798404 <6>[ 4.445741] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10516 01:18:31.808235 <6>[ 4.455035] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10517 01:18:31.817709 <6>[ 4.465195] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10518 01:18:31.827963 <6>[ 4.476983] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10519 01:18:31.875240 <6>[ 4.524184] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10520 01:18:32.029999 <6>[ 4.682091] hub 1-1:1.0: USB hub found
10521 01:18:32.033601 <6>[ 4.686626] hub 1-1:1.0: 4 ports detected
10522 01:18:32.043847 <6>[ 4.695610] hub 1-1:1.0: USB hub found
10523 01:18:32.046909 <6>[ 4.699970] hub 1-1:1.0: 4 ports detected
10524 01:18:32.155884 <6>[ 4.804638] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10525 01:18:32.182124 <6>[ 4.833941] hub 2-1:1.0: USB hub found
10526 01:18:32.184891 <6>[ 4.838436] hub 2-1:1.0: 3 ports detected
10527 01:18:32.194729 <6>[ 4.846456] hub 2-1:1.0: USB hub found
10528 01:18:32.197521 <6>[ 4.850926] hub 2-1:1.0: 3 ports detected
10529 01:18:32.371473 <6>[ 5.020348] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10530 01:18:32.504235 <6>[ 5.156084] hub 1-1.4:1.0: USB hub found
10531 01:18:32.507547 <6>[ 5.160746] hub 1-1.4:1.0: 2 ports detected
10532 01:18:32.516119 <6>[ 5.168237] hub 1-1.4:1.0: USB hub found
10533 01:18:32.519320 <6>[ 5.172807] hub 1-1.4:1.0: 2 ports detected
10534 01:18:32.587343 <6>[ 5.236437] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10535 01:18:32.815427 <6>[ 5.464345] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10536 01:18:33.007153 <6>[ 5.656192] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10537 01:18:44.100335 <6>[ 16.757355] ALSA device list:
10538 01:18:44.106902 <6>[ 16.760644] No soundcards found.
10539 01:18:44.114627 <6>[ 16.768473] Freeing unused kernel memory: 8448K
10540 01:18:44.118016 <6>[ 16.773855] Run /init as init process
10541 01:18:44.167536 <6>[ 16.821553] NET: Registered PF_INET6 protocol family
10542 01:18:44.174007 <6>[ 16.827896] Segment Routing with IPv6
10543 01:18:44.177482 <6>[ 16.831850] In-situ OAM (IOAM) with IPv6
10544 01:18:44.221074 <30>[ 16.848339] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10545 01:18:44.227669 <30>[ 16.881540] systemd[1]: Detected architecture arm64.
10546 01:18:44.228223
10547 01:18:44.234531 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10548 01:18:44.235080
10549 01:18:44.235441
10550 01:18:44.250744 <30>[ 16.904599] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10551 01:18:44.429654 <30>[ 17.080222] systemd[1]: Queued start job for default target graphical.target.
10552 01:18:44.467933 <30>[ 17.118384] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10553 01:18:44.474537 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10554 01:18:44.475025
10555 01:18:44.494937 <30>[ 17.145048] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10556 01:18:44.504628 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10557 01:18:44.505192
10558 01:18:44.522985 <30>[ 17.173324] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10559 01:18:44.532903 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10560 01:18:44.533474
10561 01:18:44.551401 <30>[ 17.201470] systemd[1]: Created slice user.slice - User and Session Slice.
10562 01:18:44.557941 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10563 01:18:44.558544
10564 01:18:44.577648 <30>[ 17.224410] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10565 01:18:44.583936 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10566 01:18:44.584500
10567 01:18:44.605798 <30>[ 17.252829] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10568 01:18:44.612429 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10569 01:18:44.612993
10570 01:18:44.639587 <30>[ 17.280318] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10571 01:18:44.649782 <30>[ 17.300122] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10572 01:18:44.656343 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10573 01:18:44.656892
10574 01:18:44.674005 <30>[ 17.324255] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10575 01:18:44.680595 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10576 01:18:44.681162
10577 01:18:44.698275 <30>[ 17.348332] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10578 01:18:44.707941 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10579 01:18:44.708498
10580 01:18:44.722976 <30>[ 17.376420] systemd[1]: Reached target paths.target - Path Units.
10581 01:18:44.729468 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10582 01:18:44.732610
10583 01:18:44.750646 <30>[ 17.400768] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10584 01:18:44.757561 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10585 01:18:44.758189
10586 01:18:44.770714 <30>[ 17.424319] systemd[1]: Reached target slices.target - Slice Units.
10587 01:18:44.780632 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10588 01:18:44.781190
10589 01:18:44.795236 <30>[ 17.448798] systemd[1]: Reached target swap.target - Swaps.
10590 01:18:44.801659 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10591 01:18:44.802261
10592 01:18:44.822634 <30>[ 17.472848] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10593 01:18:44.832373 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10594 01:18:44.832925
10595 01:18:44.850750 <30>[ 17.500808] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10596 01:18:44.860585 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10597 01:18:44.861156
10598 01:18:44.880282 <30>[ 17.530498] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10599 01:18:44.889985 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10600 01:18:44.890595
10601 01:18:44.906899 <30>[ 17.557033] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10602 01:18:44.916604 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10603 01:18:44.917227
10604 01:18:44.935545 <30>[ 17.585629] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10605 01:18:44.941665 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10606 01:18:44.942168
10607 01:18:44.962445 <30>[ 17.612993] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10608 01:18:44.972992 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10609 01:18:44.973558
10610 01:18:44.990251 <30>[ 17.640808] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10611 01:18:45.000265 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10612 01:18:45.000893
10613 01:18:45.042142 <30>[ 17.692417] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10614 01:18:45.048526 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10615 01:18:45.049103
10616 01:18:45.070093 <30>[ 17.720511] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10617 01:18:45.076512 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10618 01:18:45.077068
10619 01:18:45.097911 <30>[ 17.748013] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10620 01:18:45.104430 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10621 01:18:45.104984
10622 01:18:45.128775 <30>[ 17.772785] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10623 01:18:45.166759 <30>[ 17.816854] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10624 01:18:45.176127 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10625 01:18:45.176671
10626 01:18:45.198788 <30>[ 17.849327] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10627 01:18:45.205605 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10628 01:18:45.206215
10629 01:18:45.230834 <30>[ 17.881143] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10630 01:18:45.247157 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod..<6>[ 17.895363] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10631 01:18:45.247714 .
10632 01:18:45.248196
10633 01:18:45.294674 <30>[ 17.944765] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10634 01:18:45.301200 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10635 01:18:45.301759
10636 01:18:45.322819 <30>[ 17.973146] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10637 01:18:45.332650 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10638 01:18:45.333204
10639 01:18:45.394346 <30>[ 18.044886] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10640 01:18:45.401015 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10641 01:18:45.401575
10642 01:18:45.430794 <30>[ 18.081161] systemd[1]: Starting systemd-journald.service - Journal Service...
10643 01:18:45.437372 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10644 01:18:45.437935
10645 01:18:45.456575 <30>[ 18.106918] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10646 01:18:45.463091 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10647 01:18:45.463563
10648 01:18:45.493432 <30>[ 18.140731] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10649 01:18:45.500457 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10650 01:18:45.501030
10651 01:18:45.521063 <30>[ 18.171546] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10652 01:18:45.531032 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10653 01:18:45.531506
10654 01:18:45.554380 <30>[ 18.204898] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10655 01:18:45.564481 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10656 01:18:45.565070
10657 01:18:45.589692 <30>[ 18.240391] systemd[1]: Started systemd-journald.service - Journal Service.
10658 01:18:45.596387 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10659 01:18:45.596858
10660 01:18:45.616720 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10661 01:18:45.617288
10662 01:18:45.634531 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10663 01:18:45.635084
10664 01:18:45.654819 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10665 01:18:45.655388
10666 01:18:45.675099 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10667 01:18:45.675667
10668 01:18:45.696826 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10669 01:18:45.697430
10670 01:18:45.717454 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10671 01:18:45.718061
10672 01:18:45.736510 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10673 01:18:45.737069
10674 01:18:45.756841 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10675 01:18:45.757434
10676 01:18:45.776285 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10677 01:18:45.776847
10678 01:18:45.795662 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10679 01:18:45.796233
10680 01:18:45.815457 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10681 01:18:45.816046
10682 01:18:45.836438 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10683 01:18:45.837010
10684 01:18:45.842922 See 'systemctl status systemd-remount-fs.service' for details.
10685 01:18:45.843479
10686 01:18:45.863046 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10687 01:18:45.863606
10688 01:18:45.884536 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10689 01:18:45.885108
10690 01:18:45.938757 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10691 01:18:45.939461
10692 01:18:45.965045 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10693 01:18:45.965605
10694 01:18:45.975178 <46>[ 18.625684] systemd-journald[183]: Received client request to flush runtime journal.
10695 01:18:45.988972 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10696 01:18:45.989535
10697 01:18:46.011353 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10698 01:18:46.011899
10699 01:18:46.039424 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10700 01:18:46.039974
10701 01:18:46.068712 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10702 01:18:46.069274
10703 01:18:46.087617 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10704 01:18:46.088179
10705 01:18:46.107389 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10706 01:18:46.107952
10707 01:18:46.127191 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10708 01:18:46.127888
10709 01:18:46.147236 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10710 01:18:46.147795
10711 01:18:46.210652 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10712 01:18:46.211207
10713 01:18:46.228995 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10714 01:18:46.229548
10715 01:18:46.246305 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10716 01:18:46.246869
10717 01:18:46.261936 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10718 01:18:46.262529
10719 01:18:46.282346 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10720 01:18:46.282894
10721 01:18:46.307054 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10722 01:18:46.307617
10723 01:18:46.329105 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10724 01:18:46.329671
10725 01:18:46.354356 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10726 01:18:46.354914
10727 01:18:46.381450 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10728 01:18:46.382019
10729 01:18:46.402473 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10730 01:18:46.403040
10731 01:18:46.426064 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10732 01:18:46.426639
10733 01:18:46.473808 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10734 01:18:46.474425
10735 01:18:46.496222 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10736 01:18:46.496808
10737 01:18:46.594750 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10738 01:18:46.595312
10739 01:18:46.614644 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10740 01:18:46.615218
10741 01:18:46.634297 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10742 01:18:46.634859
10743 01:18:46.650965 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10744 01:18:46.651542
10745 01:18:46.670570 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10746 01:18:46.671118
10747 01:18:46.692046 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bu<6>[ 19.344593] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10748 01:18:46.704759 s System Message<6>[ 19.352577] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10749 01:18:46.711376 <3>[ 19.361735] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10750 01:18:46.711842 Bus Socket.
10751 01:18:46.712203
10752 01:18:46.721705 <6>[ 19.362777] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10753 01:18:46.731120 <3>[ 19.370652] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10754 01:18:46.737977 <6>[ 19.376704] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10755 01:18:46.741313 <6>[ 19.378913] remoteproc remoteproc0: scp is available
10756 01:18:46.748309 <6>[ 19.378963] remoteproc remoteproc0: powering up scp
10757 01:18:46.754686 <6>[ 19.378969] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10758 01:18:46.761347 <6>[ 19.378982] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10759 01:18:46.767655 <4>[ 19.402514] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10760 01:18:46.777648 <3>[ 19.408105] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10761 01:18:46.784383 <4>[ 19.416480] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10762 01:18:46.794102 <3>[ 19.421763] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10763 01:18:46.797770 <6>[ 19.428777] mc: Linux media interface: v0.10
10764 01:18:46.804145 <3>[ 19.436247] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10765 01:18:46.814175 <3>[ 19.436254] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10766 01:18:46.820792 <3>[ 19.436260] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10767 01:18:46.830435 <3>[ 19.436263] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10768 01:18:46.836944 <6>[ 19.437520] usbcore: registered new device driver r8152-cfgselector
10769 01:18:46.843985 <6>[ 19.447970] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10770 01:18:46.853714 <3>[ 19.453996] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10771 01:18:46.860719 <4>[ 19.485957] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10772 01:18:46.866960 <4>[ 19.485957] Fallback method does not support PEC.
10773 01:18:46.874205 <3>[ 19.489012] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10774 01:18:46.881098 <6>[ 19.504796] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10775 01:18:46.887920 <6>[ 19.505414] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10776 01:18:46.894306 <6>[ 19.505419] pci_bus 0000:00: root bus resource [bus 00-ff]
10777 01:18:46.900656 <6>[ 19.505423] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10778 01:18:46.910715 <6>[ 19.505425] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10779 01:18:46.917518 <6>[ 19.505453] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10780 01:18:46.924514 <6>[ 19.505466] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10781 01:18:46.930680 <6>[ 19.505535] pci 0000:00:00.0: supports D1 D2
10782 01:18:46.937812 <6>[ 19.505536] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10783 01:18:46.943825 <6>[ 19.506460] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10784 01:18:46.950430 <6>[ 19.506536] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10785 01:18:46.957093 <6>[ 19.506561] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10786 01:18:46.967358 <6>[ 19.506577] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10787 01:18:46.973585 <6>[ 19.506592] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10788 01:18:46.976846 <6>[ 19.506698] pci 0000:01:00.0: supports D1 D2
10789 01:18:46.983431 <6>[ 19.506700] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10790 01:18:46.994141 <6>[ 19.511175] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10791 01:18:46.997680 <6>[ 19.511183] remoteproc remoteproc0: remote processor scp is now up
10792 01:18:47.007523 <3>[ 19.511197] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10793 01:18:47.014391 <6>[ 19.516078] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10794 01:18:47.021150 <6>[ 19.516108] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10795 01:18:47.031176 <6>[ 19.516112] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10796 01:18:47.037757 <6>[ 19.516123] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10797 01:18:47.047350 <6>[ 19.516136] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10798 01:18:47.054330 <6>[ 19.516148] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10799 01:18:47.060658 <6>[ 19.516161] pci 0000:00:00.0: PCI bridge to [bus 01]
10800 01:18:47.067102 <6>[ 19.516167] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10801 01:18:47.073785 <6>[ 19.516297] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10802 01:18:47.081025 <6>[ 19.516742] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10803 01:18:47.087744 <6>[ 19.517277] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10804 01:18:47.094771 <3>[ 19.531114] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10805 01:18:47.105488 <6>[ 19.532449] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10806 01:18:47.112298 <6>[ 19.532867] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10807 01:18:47.122369 <6>[ 19.532952] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10808 01:18:47.132294 <3>[ 19.533469] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10809 01:18:47.138632 <3>[ 19.533512] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10810 01:18:47.145418 <3>[ 19.533516] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10811 01:18:47.155256 <3>[ 19.533518] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10812 01:18:47.162644 <3>[ 19.533523] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10813 01:18:47.172176 <3>[ 19.533526] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10814 01:18:47.179250 <3>[ 19.533551] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10815 01:18:47.189330 <6>[ 19.595259] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10816 01:18:47.196339 <6>[ 19.604837] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10817 01:18:47.206099 <4>[ 19.606867] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10818 01:18:47.212766 <4>[ 19.606880] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10819 01:18:47.222772 <3>[ 19.658040] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10820 01:18:47.233320 <3>[ 19.658680] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10821 01:18:47.236479 <6>[ 19.659310] videodev: Linux video capture interface: v2.00
10822 01:18:47.246611 <5>[ 19.669480] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10823 01:18:47.250394 <6>[ 19.682860] r8152 2-1.3:1.0 eth0: v1.12.13
10824 01:18:47.259633 <6>[ 19.682997] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10825 01:18:47.263067 <6>[ 19.698802] Bluetooth: Core ver 2.22
10826 01:18:47.270190 <5>[ 19.703417] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10827 01:18:47.276315 <5>[ 19.703631] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10828 01:18:47.286149 <4>[ 19.703692] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10829 01:18:47.292645 <6>[ 19.703697] cfg80211: failed to load regulatory.db
10830 01:18:47.295919 <6>[ 19.705994] usbcore: registered new interface driver r8152
10831 01:18:47.302796 <6>[ 19.713943] NET: Registered PF_BLUETOOTH protocol family
10832 01:18:47.309127 <6>[ 19.715320] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10833 01:18:47.323118 <6>[ 19.716616] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10834 01:18:47.326726 <6>[ 19.716774] usbcore: registered new interface driver uvcvideo
10835 01:18:47.333495 <6>[ 19.739617] usbcore: registered new interface driver cdc_ether
10836 01:18:47.340572 <6>[ 19.745338] Bluetooth: HCI device and connection manager initialized
10837 01:18:47.347093 <6>[ 19.754766] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10838 01:18:47.357414 <3>[ 19.756487] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10839 01:18:47.364303 <3>[ 19.757277] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10840 01:18:47.370905 <6>[ 19.764190] Bluetooth: HCI socket layer initialized
10841 01:18:47.374482 <6>[ 19.764359] usbcore: registered new interface driver r8153_ecm
10842 01:18:47.384997 <3>[ 19.765971] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10843 01:18:47.394990 <3>[ 19.786580] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10844 01:18:47.398115 <6>[ 19.789652] Bluetooth: L2CAP socket layer initialized
10845 01:18:47.404849 <6>[ 19.789671] Bluetooth: SCO socket layer initialized
10846 01:18:47.411580 <6>[ 19.801663] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10847 01:18:47.418089 <6>[ 19.806203] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10848 01:18:47.424670 <6>[ 19.814043] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10849 01:18:47.431184 <3>[ 19.821998] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10850 01:18:47.441255 <3>[ 19.841299] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10851 01:18:47.448008 <6>[ 19.856472] usbcore: registered new interface driver btusb
10852 01:18:47.458125 <4>[ 19.857563] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10853 01:18:47.464709 <3>[ 19.857572] Bluetooth: hci0: Failed to load firmware file (-2)
10854 01:18:47.470994 <3>[ 19.857573] Bluetooth: hci0: Failed to set up firmware (-2)
10855 01:18:47.480954 <4>[ 19.857577] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10856 01:18:47.484147 <6>[ 19.864234] mt7921e 0000:01:00.0: ASIC revision: 79610010
10857 01:18:47.494068 <3>[ 19.884662] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10858 01:18:47.504397 <6>[ 19.959306] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10859 01:18:47.505084 <6>[ 19.959306]
10860 01:18:47.510506 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10861 01:18:47.511066
10862 01:18:47.530140 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10863 01:18:47.530697
10864 01:18:47.587700 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10865 01:18:47.588262
10866 01:18:47.620238 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10867 01:18:47.620800
10868 01:18:47.643610 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10869 01:18:47.644164
10870 01:18:47.666395 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10871 01:18:47.666964
10872 01:18:47.704474 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10873 01:18:47.705047
10874 01:18:47.762248 <46>[ 20.399763] systemd-journald[183]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.1 (1537 of 2047 items, 524288 file size, 341 bytes per hash table item), suggesting rotation.
10875 01:18:47.772390 <6>[ 20.423381] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10876 01:18:47.792250 <46>[ 20.436085] systemd-journald[183]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
10877 01:18:47.805593 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10878 01:18:47.806083
10879 01:18:47.825501 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10880 01:18:47.826109
10881 01:18:47.842546 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10882 01:18:47.843018
10883 01:18:47.862890 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10884 01:18:47.863445
10885 01:18:47.931138 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10886 01:18:47.931692
10887 01:18:47.953154 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10888 01:18:47.953724
10889 01:18:47.970598 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10890 01:18:47.971142
10891 01:18:47.987041 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10892 01:18:47.987596
10893 01:18:48.006777 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10894 01:18:48.007332
10895 01:18:48.059923 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10896 01:18:48.060489
10897 01:18:48.084614 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10898 01:18:48.085191
10899 01:18:48.109614 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10900 01:18:48.110244
10901 01:18:48.167970 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10902 01:18:48.168522
10903 01:18:48.188435 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10904 01:18:48.189005
10905 01:18:48.214608 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10906 01:18:48.215194
10907 01:18:48.266811
10908 01:18:48.267366
10909 01:18:48.270464 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10910 01:18:48.271021
10911 01:18:48.273541 debian-bookworm-arm64 login: root (automatic login)
10912 01:18:48.274155
10913 01:18:48.274579
10914 01:18:48.288910 Linux debian-bookworm-arm64 6.1.86-cip19 #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024 aarch64
10915 01:18:48.289471
10916 01:18:48.295523 The programs included with the Debian GNU/Linux system are free software;
10917 01:18:48.302060 the exact distribution terms for each program are described in the
10918 01:18:48.305406 individual files in /usr/share/doc/*/copyright.
10919 01:18:48.305960
10920 01:18:48.311868 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10921 01:18:48.314920 permitted by applicable law.
10922 01:18:48.316333 Matched prompt #10: / #
10924 01:18:48.317437 Setting prompt string to ['/ #']
10925 01:18:48.317903 end: 2.2.5.1 login-action (duration 00:00:22) [common]
10927 01:18:48.319002 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
10928 01:18:48.319482 start: 2.2.6 expect-shell-connection (timeout 00:03:10) [common]
10929 01:18:48.319873 Setting prompt string to ['/ #']
10930 01:18:48.320232 Forcing a shell prompt, looking for ['/ #']
10932 01:18:48.371150 / #
10933 01:18:48.371811 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10934 01:18:48.372350 Waiting using forced prompt support (timeout 00:02:30)
10935 01:18:48.377506
10936 01:18:48.378321 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10937 01:18:48.378827 start: 2.2.7 export-device-env (timeout 00:03:10) [common]
10938 01:18:48.379398 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10939 01:18:48.379875 end: 2.2 depthcharge-retry (duration 00:01:50) [common]
10940 01:18:48.380323 end: 2 depthcharge-action (duration 00:01:50) [common]
10941 01:18:48.380798 start: 3 lava-test-retry (timeout 00:07:46) [common]
10942 01:18:48.381254 start: 3.1 lava-test-shell (timeout 00:07:46) [common]
10943 01:18:48.381663 Using namespace: common
10945 01:18:48.482926 / # #
10946 01:18:48.483575 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10947 01:18:48.489283 #
10948 01:18:48.490190 Using /lava-13468749
10950 01:18:48.591579 / # export SHELL=/bin/sh
10951 01:18:48.597753 export SHELL=/bin/sh
10953 01:18:48.699632 / # . /lava-13468749/environment
10954 01:18:48.700432 <6>[ 21.304525] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10955 01:18:48.705839 . /lava-13468749/environment
10957 01:18:48.848182 / # /lava-13468749/bin/lava-test-runner /lava-13468749/0
10958 01:18:48.848837 Test shell timeout: 10s (minimum of the action and connection timeout)
10959 01:18:48.854245 /lava-13468749/bin/lava-test-runner /lava-13468749/0
10960 01:18:48.880689 + export TESTRUN_ID=0_igt-gpu-pa<8>[ 21.532913] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 13468749_1.5.2.3.1>
10961 01:18:48.881577 Received signal: <STARTRUN> 0_igt-gpu-panfrost 13468749_1.5.2.3.1
10962 01:18:48.882142 Starting test lava.0_igt-gpu-panfrost (13468749_1.5.2.3.1)
10963 01:18:48.882602 Skipping test definition patterns.
10964 01:18:48.883747 nfrost
10965 01:18:48.887218 + cd /lava-13468749/0/tests/0_igt-gpu-panfrost
10966 01:18:48.887684 + cat uuid
10967 01:18:48.890871 + UUID=13468749_1.5.2.3.1
10968 01:18:48.891546 + set +x
10969 01:18:48.903810 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param <8>[ 21.557513] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
10970 01:18:48.904589 Received signal: <TESTSET> START panfrost_gem_new
10971 01:18:48.905010 Starting test_set panfrost_gem_new
10972 01:18:48.907076 panfrost_prime panfrost_submit
10973 01:18:48.922518 <14>[ 21.576660] [IGT] panfrost_gem_new: executing
10974 01:18:48.929516 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 21.583615] [IGT] panfrost_gem_new: exiting, ret=77
10975 01:18:48.932488 h64) (Linux: 6.1.86-cip19 aarch64)
10976 01:18:48.945753 Using IGT_SRANDOM=1713835127 for randomisati<8>[ 21.596186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
10977 01:18:48.946368 on
10978 01:18:48.947022 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
10980 01:18:48.952226 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10981 01:18:48.955570 Test requirement: !(fd<0)
10982 01:18:48.961808 No known gpu found for chipset <14>[ 21.615401] [IGT] panfrost_gem_new: executing
10983 01:18:48.965420 flags 0x32 (panfrost)
10984 01:18:48.968418 Last errn<14>[ 21.622778] [IGT] panfrost_gem_new: exiting, ret=77
10985 01:18:48.971631 o: 2, No such file or directory
10986 01:18:48.981912 [1mSubtest gem-new-4096: SKIP <8>[ 21.634433] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
10987 01:18:48.982451 (0.000s)[0m
10988 01:18:48.983091 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
10990 01:18:48.988684 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
10991 01:18:48.995355 Using IGT_SRANDOM=1713835127 for randomisation
10992 01:18:49.001798 Test requirement not met in fu<14>[ 21.654019] [IGT] panfrost_gem_new: executing
10993 01:18:49.008476 nction drm_open_driver, file ../<14>[ 21.661822] [IGT] panfrost_gem_new: exiting, ret=77
10994 01:18:49.012137 lib/drmtest.c:694:
10995 01:18:49.012697 Test requirement: !(fd<0)
10996 01:18:49.021480 No known gpu foun<8>[ 21.673210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
10997 01:18:49.022371 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
10999 01:18:49.027888 d for chipset flags 0x32 (panfro<8>[ 21.682180] <LAVA_SIGNAL_TESTSET STOP>
11000 01:18:49.028363 st)
11001 01:18:49.028990 Received signal: <TESTSET> STOP
11002 01:18:49.029370 Closing test_set panfrost_gem_new
11003 01:18:49.031157 Last errno: 2, No such file or directory
11004 01:18:49.034717 [1mSubtest gem-new-0: SKIP (0.000s)[0m
11005 01:18:49.041663 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11006 01:18:49.047996 Received signal: <TESTSET> START panfrost_get_param
11007 01:18:49.048535 Starting test_set panfrost_get_param
11008 01:18:49.050908 Using IGT_SRANDOM=1<8>[ 21.701694] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11009 01:18:49.051379 713835127 for randomisation
11010 01:18:49.057640 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11011 01:18:49.061213 Test requirement: !(fd<0)
11012 01:18:49.067810 No known gpu found for chipset flags 0x32 (panfrost)
11013 01:18:49.071297 <14>[ 21.724798] [IGT] panfrost_get_param: executing
11014 01:18:49.077492 Last errno: 2, No such file or d<14>[ 21.732299] [IGT] panfrost_get_param: exiting, ret=77
11015 01:18:49.080967 irectory
11016 01:18:49.084317 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
11017 01:18:49.090956 IGT-Ver<8>[ 21.742821] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11018 01:18:49.091796 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11020 01:18:49.097644 sion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11021 01:18:49.100711 Using IGT_SRANDOM=1713835127 for randomisation
11022 01:18:49.110803 Test requirement not met in functio<14>[ 21.763270] [IGT] panfrost_get_param: executing
11023 01:18:49.117154 n drm_open_driver, file ../lib/d<14>[ 21.770108] [IGT] panfrost_get_param: exiting, ret=77
11024 01:18:49.117622 rmtest.c:694:
11025 01:18:49.120577 Test requirement: !(fd<0)
11026 01:18:49.130329 No known gpu found for<8>[ 21.782149] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11027 01:18:49.131173 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11029 01:18:49.134064 chipset flags 0x32 (panfrost)
11030 01:18:49.137304 Last errno: 2, No such file or directory
11031 01:18:49.140344 [1mSubtest base-params: SKIP (0.000s)[0m
11032 01:18:49.147338 IGT-Version: 1.28-ga44ebfe<14>[ 21.801632] [IGT] panfrost_get_param: executing
11033 01:18:49.156840 (aarch64) (Linux: 6.1.86-cip19 <14>[ 21.808479] [IGT] panfrost_get_param: exiting, ret=77
11034 01:18:49.157298 aarch64)
11035 01:18:49.160347 Using IGT_SRANDOM=1713835127 for randomisation
11036 01:18:49.167147 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11038 01:18:49.170146 Test r<8>[ 21.820385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11039 01:18:49.176712 equirement not met in function d<8>[ 21.830323] <LAVA_SIGNAL_TESTSET STOP>
11040 01:18:49.177525 Received signal: <TESTSET> STOP
11041 01:18:49.177914 Closing test_set panfrost_get_param
11042 01:18:49.179955 rm_open_driver, file ../lib/drmtest.c:694:
11043 01:18:49.180427 Test requirement: !(fd<0)
11044 01:18:49.186812 No known gpu found for chipset flags 0x32 (panfrost)
11045 01:18:49.190139 Last errno: 2, No such file or directory
11046 01:18:49.197170 [1mSubte<8>[ 21.849782] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11047 01:18:49.198000 Received signal: <TESTSET> START panfrost_prime
11048 01:18:49.198448 Starting test_set panfrost_prime
11049 01:18:49.199740 st get-bad-param: SKIP (0.000s)[0m
11050 01:18:49.206750 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11051 01:18:49.210107 Using IGT_SRANDOM=1713835127 for randomisation
11052 01:18:49.213333 Test re<14>[ 21.868224] [IGT] panfrost_prime: executing
11053 01:18:49.223031 quirement not met in function dr<14>[ 21.875403] [IGT] panfrost_prime: exiting, ret=77
11054 01:18:49.226574 m_open_driver, file ../lib/drmtest.c:694:
11055 01:18:49.236172 Test requirement: !(f<8>[ 21.887177] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11056 01:18:49.236733 d<0)
11057 01:18:49.237382 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11059 01:18:49.243254 No known gpu found for chi<8>[ 21.896946] <LAVA_SIGNAL_TESTSET STOP>
11060 01:18:49.244097 Received signal: <TESTSET> STOP
11061 01:18:49.244485 Closing test_set panfrost_prime
11062 01:18:49.246509 pset flags 0x32 (panfrost)
11063 01:18:49.249688 Last errno: 2, No such file or directory
11064 01:18:49.252984 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
11065 01:18:49.262805 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 <8>[ 21.915992] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11066 01:18:49.263370 aarch64)
11067 01:18:49.264017 Received signal: <TESTSET> START panfrost_submit
11068 01:18:49.264406 Starting test_set panfrost_submit
11069 01:18:49.269359 Using IGT_SRANDOM=1713835127 for randomisation
11070 01:18:49.275565 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11071 01:18:49.278969 Test requirement: !(fd<0)
11072 01:18:49.285681 No known gpu found for chipset flags 0x32<14>[ 21.939131] [IGT] panfrost_submit: executing
11073 01:18:49.286342 (panfrost)
11074 01:18:49.292564 Last errno: 2, No s<14>[ 21.947109] [IGT] panfrost_submit: exiting, ret=77
11075 01:18:49.295375 uch file or directory
11076 01:18:49.305592 [1mSubtest gem-prime-import: SKIP (0.000<8>[ 21.958420] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11077 01:18:49.306170 s)[0m
11078 01:18:49.306811 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11080 01:18:49.312629 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11081 01:18:49.315583 Using IGT_SRANDOM=1713835127 for randomisation
11082 01:18:49.325297 Test requirement not met in function drm_open_driver<14>[ 21.979617] [IGT] panfrost_submit: executing
11083 01:18:49.328964 , file ../lib/drmtest.c:694:
11084 01:18:49.335461 Te<14>[ 21.986915] [IGT] panfrost_submit: exiting, ret=77
11085 01:18:49.336015 st requirement: !(fd<0)
11086 01:18:49.341994 No known gpu found for chipset flags 0x32 (panfrost)
11087 01:18:49.348665 L<8>[ 21.999126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11088 01:18:49.349509 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11090 01:18:49.352082 ast errno: 2, No such file or directory
11091 01:18:49.355305 [1mSubtest pan-submit: SKIP (0.000s)[0m
11092 01:18:49.362193 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11093 01:18:49.368608 Using IG<14>[ 22.021683] [IGT] panfrost_submit: executing
11094 01:18:49.375273 T_SRANDOM=1713835127 for randomi<14>[ 22.028561] [IGT] panfrost_submit: exiting, ret=77
11095 01:18:49.375841 sation
11096 01:18:49.388135 Test requirement not met in function drm_open_driver, fi<8>[ 22.039545] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11097 01:18:49.388885 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11099 01:18:49.391415 le ../lib/drmtest.c:694:
11100 01:18:49.394693 Test requirement: !(fd<0)
11101 01:18:49.398188 No known gpu found for chipset flags 0x32 (panfrost)
11102 01:18:49.408025 Last errno: 2, No such file or direct<14>[ 22.060755] [IGT] panfrost_submit: executing
11103 01:18:49.408575 ory
11104 01:18:49.414204 [1mSubtest pan-submit-erro<14>[ 22.067489] [IGT] panfrost_submit: exiting, ret=77
11105 01:18:49.417581 r-no-jc: SKIP (0.000s)[0m
11106 01:18:49.431228 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-<8>[ 22.079598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11107 01:18:49.431870 cip19 aarch64)
11108 01:18:49.432526 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11110 01:18:49.434372 Using IGT_SRANDOM=1713835127 for randomisation
11111 01:18:49.444239 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11112 01:18:49.447622 Test requireme<14>[ 22.102964] [IGT] panfrost_submit: executing
11113 01:18:49.451173 nt: !(fd<0)
11114 01:18:49.457588 No known gpu found <14>[ 22.109720] [IGT] panfrost_submit: exiting, ret=77
11115 01:18:49.460919 for chipset flags 0x32 (panfrost)
11116 01:18:49.470953 Last errno: 2, No such file o<8>[ 22.121354] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11117 01:18:49.471514 r directory
11118 01:18:49.472160 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11120 01:18:49.477574 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
11121 01:18:49.483781 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11122 01:18:49.487658 Using IGT_SRANDOM=1713835127 for randomisation
11123 01:18:49.494016 Test requirement <14>[ 22.147235] [IGT] panfrost_submit: executing
11124 01:18:49.500654 not met in function drm_open_dri<14>[ 22.154984] [IGT] panfrost_submit: exiting, ret=77
11125 01:18:49.504013 ver, file ../lib/drmtest.c:694:
11126 01:18:49.513836 Test requiremen<8>[ 22.165020] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11127 01:18:49.514689 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11129 01:18:49.516972 t: !(fd<0)
11130 01:18:49.520286 No known gpu found for chipset flags 0x32 (panfrost)
11131 01:18:49.523892 Last errno: 2, No such file or directory
11132 01:18:49.530192 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
11133 01:18:49.536965 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11134 01:18:49.540151 Using IGT_SRANDOM=1713835127 for randomisation
11135 01:18:49.543339 <14>[ 22.198062] [IGT] panfrost_submit: executing
11136 01:18:49.553848 Test requirement not met in function drm_open_dr<14>[ 22.206792] [IGT] panfrost_submit: exiting, ret=77
11137 01:18:49.556983 iver, file ../lib/drmtest.c:694:
11138 01:18:49.560342 Test requirement: !(fd<0)
11139 01:18:49.566697 No <8>[ 22.217963] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11140 01:18:49.567560 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11142 01:18:49.569831 known gpu found for chipset flags 0x32 (panfrost)
11143 01:18:49.573302 Last errno: 2, No such file or directory
11144 01:18:49.579569 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
11145 01:18:49.586469 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11146 01:18:49.589782 Using IGT_SRANDOM=1713835128 for randomisation
11147 01:18:49.596478 Test requirem<14>[ 22.249338] [IGT] panfrost_submit: executing
11148 01:18:49.606192 ent not met in function drm_open_driver, file ..<14>[ 22.258262] [IGT] panfrost_submit: exiting, ret=77
11149 01:18:49.606760 /lib/drmtest.c:694:
11150 01:18:49.609754 Test requirement: !(fd<0)
11151 01:18:49.619367 No known gpu found for chipset flags 0x32 (panfr<8>[ 22.271217] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11152 01:18:49.620244 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11154 01:18:49.622504 ost)
11155 01:18:49.625861 Last errno: 2, No such file or directory
11156 01:18:49.629611 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
11157 01:18:49.639358 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)<14>[ 22.294781] [IGT] panfrost_submit: executing
11158 01:18:49.639929
11159 01:18:49.649062 Using IGT_SRANDOM=1713835128 f<14>[ 22.301764] [IGT] panfrost_submit: exiting, ret=77
11160 01:18:49.649617 or randomisation
11161 01:18:49.662254 Test requirement not met in function drm_open_<8>[ 22.313345] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11162 01:18:49.663097 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11164 01:18:49.666396 Received signal: <TESTSET> STOP
11165 01:18:49.666957 Closing test_set panfrost_submit
11166 01:18:49.669476 driver, file ../<8>[ 22.322712] <LAVA_SIGNAL_TESTSET STOP>
11167 01:18:49.676014 lib/drmtest.c:69<8>[ 22.327482] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 13468749_1.5.2.3.1>
11168 01:18:49.676564 4:
11169 01:18:49.677210 Received signal: <ENDRUN> 0_igt-gpu-panfrost 13468749_1.5.2.3.1
11170 01:18:49.677642 Ending use of test pattern.
11171 01:18:49.678002 Ending test lava.0_igt-gpu-panfrost (13468749_1.5.2.3.1), duration 0.80
11173 01:18:49.679747 Test requirement: !(fd<0)
11174 01:18:49.682370 No known gpu found for chipset flags 0x32 (panfrost)
11175 01:18:49.685599 Last errno: 2, No such file or directory
11176 01:18:49.688796 [1mSubtest pan-reset: SKIP (0.000s)[0m
11177 01:18:49.695497 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11178 01:18:49.699193 Using IGT_SRANDOM=1713835128 for randomisation
11179 01:18:49.708596 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11180 01:18:49.709152 Test requirement: !(fd<0)
11181 01:18:49.715708 No known gpu found for chipset flags 0x32 (panfrost)
11182 01:18:49.718997 Last errno: 2, No such file or directory
11183 01:18:49.722181 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11184 01:18:49.728925 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11185 01:18:49.731950 Using IGT_SRANDOM=1713835128 for randomisation
11186 01:18:49.738970 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11187 01:18:49.741970 Test requirement: !(fd<0)
11188 01:18:49.748264 No known gpu found for chipset flags 0x32 (panfrost)
11189 01:18:49.751971 Last errno: 2, No such file or directory
11190 01:18:49.755216 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11191 01:18:49.755782 + set +x
11192 01:18:49.758381 <LAVA_TEST_RUNNER EXIT>
11193 01:18:49.759127 ok: lava_test_shell seems to have completed
11194 01:18:49.760892 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11195 01:18:49.761429 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11196 01:18:49.761897 end: 3 lava-test-retry (duration 00:00:01) [common]
11197 01:18:49.762432 start: 4 finalize (timeout 00:07:44) [common]
11198 01:18:49.762922 start: 4.1 power-off (timeout 00:00:30) [common]
11199 01:18:49.763731 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11200 01:18:49.854789 >> Command sent successfully.
11201 01:18:49.865723 Returned 0 in 0 seconds
11202 01:18:49.967163 end: 4.1 power-off (duration 00:00:00) [common]
11204 01:18:49.968730 start: 4.2 read-feedback (timeout 00:07:44) [common]
11205 01:18:49.970087 Listened to connection for namespace 'common' for up to 1s
11206 01:18:50.970449 Finalising connection for namespace 'common'
11207 01:18:50.971148 Disconnecting from shell: Finalise
11208 01:18:50.971575 / #
11209 01:18:51.072726 end: 4.2 read-feedback (duration 00:00:01) [common]
11210 01:18:51.073435 end: 4 finalize (duration 00:00:01) [common]
11211 01:18:51.074140 Cleaning after the job
11212 01:18:51.074665 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468749/tftp-deploy-6yq5_lze/ramdisk
11213 01:18:51.105155 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468749/tftp-deploy-6yq5_lze/kernel
11214 01:18:51.122009 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468749/tftp-deploy-6yq5_lze/dtb
11215 01:18:51.122333 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468749/tftp-deploy-6yq5_lze/modules
11216 01:18:51.130908 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13468749
11217 01:18:51.241299 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13468749
11218 01:18:51.241483 Job finished correctly