Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 25
- Errors: 0
- Kernel Errors: 32
- Boot result: PASS
1 01:23:40.719078 lava-dispatcher, installed at version: 2024.01
2 01:23:40.719278 start: 0 validate
3 01:23:40.719404 Start time: 2024-04-23 01:23:40.719397+00:00 (UTC)
4 01:23:40.719528 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:23:40.719657 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:23:40.979716 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:23:40.980430 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:23:41.239280 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:23:41.239985 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:23:41.498707 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:23:41.499459 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:23:41.756947 Using caching service: 'http://localhost/cache/?uri=%s'
13 01:23:41.757745 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 01:23:42.021645 validate duration: 1.30
16 01:23:42.021893 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:23:42.021986 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:23:42.022070 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:23:42.022190 Not decompressing ramdisk as can be used compressed.
20 01:23:42.022276 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 01:23:42.022338 saving as /var/lib/lava/dispatcher/tmp/13468798/tftp-deploy-usmeg6ua/ramdisk/initrd.cpio.gz
22 01:23:42.022401 total size: 5628169 (5 MB)
23 01:23:42.023434 progress 0 % (0 MB)
24 01:23:42.025062 progress 5 % (0 MB)
25 01:23:42.026621 progress 10 % (0 MB)
26 01:23:42.027981 progress 15 % (0 MB)
27 01:23:42.029513 progress 20 % (1 MB)
28 01:23:42.030883 progress 25 % (1 MB)
29 01:23:42.032403 progress 30 % (1 MB)
30 01:23:42.033905 progress 35 % (1 MB)
31 01:23:42.035260 progress 40 % (2 MB)
32 01:23:42.036791 progress 45 % (2 MB)
33 01:23:42.038165 progress 50 % (2 MB)
34 01:23:42.039683 progress 55 % (2 MB)
35 01:23:42.041204 progress 60 % (3 MB)
36 01:23:42.042565 progress 65 % (3 MB)
37 01:23:42.044095 progress 70 % (3 MB)
38 01:23:42.045493 progress 75 % (4 MB)
39 01:23:42.047006 progress 80 % (4 MB)
40 01:23:42.048360 progress 85 % (4 MB)
41 01:23:42.049896 progress 90 % (4 MB)
42 01:23:42.051411 progress 95 % (5 MB)
43 01:23:42.052781 progress 100 % (5 MB)
44 01:23:42.052985 5 MB downloaded in 0.03 s (175.50 MB/s)
45 01:23:42.053131 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:23:42.053384 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:23:42.053470 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:23:42.053554 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:23:42.053683 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 01:23:42.053755 saving as /var/lib/lava/dispatcher/tmp/13468798/tftp-deploy-usmeg6ua/kernel/Image
52 01:23:42.053815 total size: 54352384 (51 MB)
53 01:23:42.053876 No compression specified
54 01:23:42.054939 progress 0 % (0 MB)
55 01:23:42.068463 progress 5 % (2 MB)
56 01:23:42.082328 progress 10 % (5 MB)
57 01:23:42.096015 progress 15 % (7 MB)
58 01:23:42.109706 progress 20 % (10 MB)
59 01:23:42.123385 progress 25 % (12 MB)
60 01:23:42.137168 progress 30 % (15 MB)
61 01:23:42.150828 progress 35 % (18 MB)
62 01:23:42.164311 progress 40 % (20 MB)
63 01:23:42.178076 progress 45 % (23 MB)
64 01:23:42.191796 progress 50 % (25 MB)
65 01:23:42.205227 progress 55 % (28 MB)
66 01:23:42.218682 progress 60 % (31 MB)
67 01:23:42.232119 progress 65 % (33 MB)
68 01:23:42.245826 progress 70 % (36 MB)
69 01:23:42.259472 progress 75 % (38 MB)
70 01:23:42.272884 progress 80 % (41 MB)
71 01:23:42.286548 progress 85 % (44 MB)
72 01:23:42.300285 progress 90 % (46 MB)
73 01:23:42.313653 progress 95 % (49 MB)
74 01:23:42.326851 progress 100 % (51 MB)
75 01:23:42.327056 51 MB downloaded in 0.27 s (189.71 MB/s)
76 01:23:42.327201 end: 1.2.1 http-download (duration 00:00:00) [common]
78 01:23:42.327436 end: 1.2 download-retry (duration 00:00:00) [common]
79 01:23:42.327521 start: 1.3 download-retry (timeout 00:10:00) [common]
80 01:23:42.327609 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 01:23:42.327742 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 01:23:42.327810 saving as /var/lib/lava/dispatcher/tmp/13468798/tftp-deploy-usmeg6ua/dtb/mt8192-asurada-spherion-r0.dtb
83 01:23:42.327870 total size: 47230 (0 MB)
84 01:23:42.327930 No compression specified
85 01:23:42.329036 progress 69 % (0 MB)
86 01:23:42.329318 progress 100 % (0 MB)
87 01:23:42.329554 0 MB downloaded in 0.00 s (26.78 MB/s)
88 01:23:42.329673 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:23:42.329890 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:23:42.329973 start: 1.4 download-retry (timeout 00:10:00) [common]
92 01:23:42.330054 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 01:23:42.330161 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 01:23:42.330227 saving as /var/lib/lava/dispatcher/tmp/13468798/tftp-deploy-usmeg6ua/nfsrootfs/full.rootfs.tar
95 01:23:42.330288 total size: 120894716 (115 MB)
96 01:23:42.330348 Using unxz to decompress xz
97 01:23:42.334249 progress 0 % (0 MB)
98 01:23:42.672545 progress 5 % (5 MB)
99 01:23:43.037303 progress 10 % (11 MB)
100 01:23:43.387763 progress 15 % (17 MB)
101 01:23:43.713647 progress 20 % (23 MB)
102 01:23:44.004938 progress 25 % (28 MB)
103 01:23:44.356522 progress 30 % (34 MB)
104 01:23:44.685621 progress 35 % (40 MB)
105 01:23:44.847702 progress 40 % (46 MB)
106 01:23:45.023717 progress 45 % (51 MB)
107 01:23:45.335484 progress 50 % (57 MB)
108 01:23:45.705273 progress 55 % (63 MB)
109 01:23:46.040530 progress 60 % (69 MB)
110 01:23:46.377774 progress 65 % (74 MB)
111 01:23:46.716713 progress 70 % (80 MB)
112 01:23:47.066574 progress 75 % (86 MB)
113 01:23:47.399526 progress 80 % (92 MB)
114 01:23:47.738111 progress 85 % (98 MB)
115 01:23:48.085999 progress 90 % (103 MB)
116 01:23:48.405243 progress 95 % (109 MB)
117 01:23:48.758167 progress 100 % (115 MB)
118 01:23:48.763523 115 MB downloaded in 6.43 s (17.92 MB/s)
119 01:23:48.763783 end: 1.4.1 http-download (duration 00:00:06) [common]
121 01:23:48.764047 end: 1.4 download-retry (duration 00:00:06) [common]
122 01:23:48.764137 start: 1.5 download-retry (timeout 00:09:53) [common]
123 01:23:48.764224 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 01:23:48.764372 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 01:23:48.764446 saving as /var/lib/lava/dispatcher/tmp/13468798/tftp-deploy-usmeg6ua/modules/modules.tar
126 01:23:48.764520 total size: 8638160 (8 MB)
127 01:23:48.764585 Using unxz to decompress xz
128 01:23:48.768678 progress 0 % (0 MB)
129 01:23:48.787636 progress 5 % (0 MB)
130 01:23:48.811724 progress 10 % (0 MB)
131 01:23:48.834953 progress 15 % (1 MB)
132 01:23:48.857491 progress 20 % (1 MB)
133 01:23:48.881448 progress 25 % (2 MB)
134 01:23:48.906548 progress 30 % (2 MB)
135 01:23:48.929909 progress 35 % (2 MB)
136 01:23:48.954639 progress 40 % (3 MB)
137 01:23:48.977758 progress 45 % (3 MB)
138 01:23:49.002049 progress 50 % (4 MB)
139 01:23:49.025927 progress 55 % (4 MB)
140 01:23:49.052990 progress 60 % (4 MB)
141 01:23:49.076977 progress 65 % (5 MB)
142 01:23:49.100963 progress 70 % (5 MB)
143 01:23:49.124384 progress 75 % (6 MB)
144 01:23:49.148607 progress 80 % (6 MB)
145 01:23:49.175505 progress 85 % (7 MB)
146 01:23:49.200938 progress 90 % (7 MB)
147 01:23:49.228848 progress 95 % (7 MB)
148 01:23:49.254708 progress 100 % (8 MB)
149 01:23:49.260311 8 MB downloaded in 0.50 s (16.62 MB/s)
150 01:23:49.260563 end: 1.5.1 http-download (duration 00:00:00) [common]
152 01:23:49.260857 end: 1.5 download-retry (duration 00:00:00) [common]
153 01:23:49.260962 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 01:23:49.261068 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 01:23:52.659165 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13468798/extract-nfsrootfs-v8wz2pm6
156 01:23:52.659370 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 01:23:52.659467 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 01:23:52.659630 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged
159 01:23:52.659755 makedir: /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin
160 01:23:52.659851 makedir: /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/tests
161 01:23:52.659946 makedir: /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/results
162 01:23:52.660043 Creating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-add-keys
163 01:23:52.660184 Creating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-add-sources
164 01:23:52.660310 Creating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-background-process-start
165 01:23:52.660446 Creating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-background-process-stop
166 01:23:52.660579 Creating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-common-functions
167 01:23:52.660701 Creating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-echo-ipv4
168 01:23:52.660824 Creating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-install-packages
169 01:23:52.660944 Creating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-installed-packages
170 01:23:52.661064 Creating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-os-build
171 01:23:52.661184 Creating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-probe-channel
172 01:23:52.661304 Creating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-probe-ip
173 01:23:52.661521 Creating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-target-ip
174 01:23:52.661647 Creating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-target-mac
175 01:23:52.661771 Creating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-target-storage
176 01:23:52.661895 Creating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-test-case
177 01:23:52.662020 Creating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-test-event
178 01:23:52.662139 Creating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-test-feedback
179 01:23:52.662260 Creating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-test-raise
180 01:23:52.662380 Creating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-test-reference
181 01:23:52.662502 Creating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-test-runner
182 01:23:52.662623 Creating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-test-set
183 01:23:52.662743 Creating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-test-shell
184 01:23:52.662866 Updating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-add-keys (debian)
185 01:23:52.663012 Updating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-add-sources (debian)
186 01:23:52.663148 Updating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-install-packages (debian)
187 01:23:52.663281 Updating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-installed-packages (debian)
188 01:23:52.663413 Updating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/bin/lava-os-build (debian)
189 01:23:52.663529 Creating /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/environment
190 01:23:52.663620 LAVA metadata
191 01:23:52.663687 - LAVA_JOB_ID=13468798
192 01:23:52.663749 - LAVA_DISPATCHER_IP=192.168.201.1
193 01:23:52.663848 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 01:23:52.663913 skipped lava-vland-overlay
195 01:23:52.663985 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 01:23:52.664063 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 01:23:52.664122 skipped lava-multinode-overlay
198 01:23:52.664191 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 01:23:52.664278 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 01:23:52.664349 Loading test definitions
201 01:23:52.664433 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 01:23:52.664501 Using /lava-13468798 at stage 0
203 01:23:52.664767 uuid=13468798_1.6.2.3.1 testdef=None
204 01:23:52.664853 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 01:23:52.664935 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 01:23:52.665416 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 01:23:52.665632 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 01:23:52.666171 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 01:23:52.666393 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 01:23:52.666908 runner path: /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/0/tests/0_timesync-off test_uuid 13468798_1.6.2.3.1
213 01:23:52.667061 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 01:23:52.667278 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 01:23:52.667349 Using /lava-13468798 at stage 0
217 01:23:52.667441 Fetching tests from https://github.com/kernelci/test-definitions.git
218 01:23:52.667525 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/0/tests/1_kselftest-arm64'
219 01:23:55.318101 Running '/usr/bin/git checkout kernelci.org
220 01:23:55.463773 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 01:23:55.464496 uuid=13468798_1.6.2.3.5 testdef=None
222 01:23:55.464651 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 01:23:55.465063 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 01:23:55.465921 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 01:23:55.466178 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 01:23:55.467250 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 01:23:55.467508 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 01:23:55.468498 runner path: /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/0/tests/1_kselftest-arm64 test_uuid 13468798_1.6.2.3.5
232 01:23:55.468588 BOARD='mt8192-asurada-spherion-r0'
233 01:23:55.468651 BRANCH='cip'
234 01:23:55.468709 SKIPFILE='/dev/null'
235 01:23:55.468766 SKIP_INSTALL='True'
236 01:23:55.468821 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 01:23:55.468877 TST_CASENAME=''
238 01:23:55.468931 TST_CMDFILES='arm64'
239 01:23:55.469067 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 01:23:55.469267 Creating lava-test-runner.conf files
242 01:23:55.469333 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13468798/lava-overlay-1oxvsged/lava-13468798/0 for stage 0
243 01:23:55.469460 - 0_timesync-off
244 01:23:55.469527 - 1_kselftest-arm64
245 01:23:55.469620 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 01:23:55.469708 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 01:24:02.979214 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 01:24:02.979374 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 01:24:02.979466 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 01:24:02.979563 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 01:24:02.979653 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 01:24:03.141120 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 01:24:03.141549 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 01:24:03.141658 extracting modules file /var/lib/lava/dispatcher/tmp/13468798/tftp-deploy-usmeg6ua/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13468798/extract-nfsrootfs-v8wz2pm6
255 01:24:03.354223 extracting modules file /var/lib/lava/dispatcher/tmp/13468798/tftp-deploy-usmeg6ua/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13468798/extract-overlay-ramdisk-eqkekm0b/ramdisk
256 01:24:03.571420 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 01:24:03.571596 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 01:24:03.571686 [common] Applying overlay to NFS
259 01:24:03.571754 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13468798/compress-overlay-4v65xqog/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13468798/extract-nfsrootfs-v8wz2pm6
260 01:24:04.483681 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 01:24:04.483848 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 01:24:04.483944 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 01:24:04.484029 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 01:24:04.484105 Building ramdisk /var/lib/lava/dispatcher/tmp/13468798/extract-overlay-ramdisk-eqkekm0b/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13468798/extract-overlay-ramdisk-eqkekm0b/ramdisk
265 01:24:04.826043 >> 130624 blocks
266 01:24:06.818492 rename /var/lib/lava/dispatcher/tmp/13468798/extract-overlay-ramdisk-eqkekm0b/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13468798/tftp-deploy-usmeg6ua/ramdisk/ramdisk.cpio.gz
267 01:24:06.818929 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 01:24:06.819056 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 01:24:06.819156 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 01:24:06.819262 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13468798/tftp-deploy-usmeg6ua/kernel/Image'
271 01:24:19.535287 Returned 0 in 12 seconds
272 01:24:19.636415 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13468798/tftp-deploy-usmeg6ua/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13468798/tftp-deploy-usmeg6ua/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13468798/tftp-deploy-usmeg6ua/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13468798/tftp-deploy-usmeg6ua/kernel/image.itb
273 01:24:19.988560 output: FIT description: Kernel Image image with one or more FDT blobs
274 01:24:19.988939 output: Created: Tue Apr 23 02:24:19 2024
275 01:24:19.989016 output: Image 0 (kernel-1)
276 01:24:19.989081 output: Description:
277 01:24:19.989145 output: Created: Tue Apr 23 02:24:19 2024
278 01:24:19.989212 output: Type: Kernel Image
279 01:24:19.989272 output: Compression: lzma compressed
280 01:24:19.989339 output: Data Size: 12910050 Bytes = 12607.47 KiB = 12.31 MiB
281 01:24:19.989444 output: Architecture: AArch64
282 01:24:19.989503 output: OS: Linux
283 01:24:19.989558 output: Load Address: 0x00000000
284 01:24:19.989612 output: Entry Point: 0x00000000
285 01:24:19.989669 output: Hash algo: crc32
286 01:24:19.989726 output: Hash value: 1126c3f9
287 01:24:19.989785 output: Image 1 (fdt-1)
288 01:24:19.989842 output: Description: mt8192-asurada-spherion-r0
289 01:24:19.989896 output: Created: Tue Apr 23 02:24:19 2024
290 01:24:19.989949 output: Type: Flat Device Tree
291 01:24:19.990002 output: Compression: uncompressed
292 01:24:19.990054 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
293 01:24:19.990107 output: Architecture: AArch64
294 01:24:19.990160 output: Hash algo: crc32
295 01:24:19.990213 output: Hash value: 4bf0d1ac
296 01:24:19.990267 output: Image 2 (ramdisk-1)
297 01:24:19.990330 output: Description: unavailable
298 01:24:19.990383 output: Created: Tue Apr 23 02:24:19 2024
299 01:24:19.990437 output: Type: RAMDisk Image
300 01:24:19.990489 output: Compression: Unknown Compression
301 01:24:19.990542 output: Data Size: 18779757 Bytes = 18339.61 KiB = 17.91 MiB
302 01:24:19.990595 output: Architecture: AArch64
303 01:24:19.990648 output: OS: Linux
304 01:24:19.990701 output: Load Address: unavailable
305 01:24:19.990754 output: Entry Point: unavailable
306 01:24:19.990807 output: Hash algo: crc32
307 01:24:19.990860 output: Hash value: 41cf3929
308 01:24:19.990913 output: Default Configuration: 'conf-1'
309 01:24:19.990965 output: Configuration 0 (conf-1)
310 01:24:19.991018 output: Description: mt8192-asurada-spherion-r0
311 01:24:19.991071 output: Kernel: kernel-1
312 01:24:19.991124 output: Init Ramdisk: ramdisk-1
313 01:24:19.991177 output: FDT: fdt-1
314 01:24:19.991230 output: Loadables: kernel-1
315 01:24:19.991283 output:
316 01:24:19.991486 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 01:24:19.991583 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 01:24:19.991689 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 01:24:19.991783 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:22) [common]
320 01:24:19.991863 No LXC device requested
321 01:24:19.991944 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 01:24:19.992031 start: 1.8 deploy-device-env (timeout 00:09:22) [common]
323 01:24:19.992110 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 01:24:19.992179 Checking files for TFTP limit of 4294967296 bytes.
325 01:24:19.992685 end: 1 tftp-deploy (duration 00:00:38) [common]
326 01:24:19.992795 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 01:24:19.992885 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 01:24:19.993014 substitutions:
329 01:24:19.993086 - {DTB}: 13468798/tftp-deploy-usmeg6ua/dtb/mt8192-asurada-spherion-r0.dtb
330 01:24:19.993150 - {INITRD}: 13468798/tftp-deploy-usmeg6ua/ramdisk/ramdisk.cpio.gz
331 01:24:19.993209 - {KERNEL}: 13468798/tftp-deploy-usmeg6ua/kernel/Image
332 01:24:19.993267 - {LAVA_MAC}: None
333 01:24:19.993325 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13468798/extract-nfsrootfs-v8wz2pm6
334 01:24:19.993433 - {NFS_SERVER_IP}: 192.168.201.1
335 01:24:19.993490 - {PRESEED_CONFIG}: None
336 01:24:19.993545 - {PRESEED_LOCAL}: None
337 01:24:19.993601 - {RAMDISK}: 13468798/tftp-deploy-usmeg6ua/ramdisk/ramdisk.cpio.gz
338 01:24:19.993657 - {ROOT_PART}: None
339 01:24:19.993712 - {ROOT}: None
340 01:24:19.993768 - {SERVER_IP}: 192.168.201.1
341 01:24:19.993823 - {TEE}: None
342 01:24:19.993877 Parsed boot commands:
343 01:24:19.993931 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 01:24:19.994110 Parsed boot commands: tftpboot 192.168.201.1 13468798/tftp-deploy-usmeg6ua/kernel/image.itb 13468798/tftp-deploy-usmeg6ua/kernel/cmdline
345 01:24:19.994199 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 01:24:19.994288 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 01:24:19.994380 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 01:24:19.994467 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 01:24:19.994541 Not connected, no need to disconnect.
350 01:24:19.994616 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 01:24:19.994697 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 01:24:19.994766 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
353 01:24:19.998629 Setting prompt string to ['lava-test: # ']
354 01:24:19.998988 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 01:24:19.999099 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 01:24:19.999218 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 01:24:19.999343 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 01:24:19.999565 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
359 01:24:25.153086 >> Command sent successfully.
360 01:24:25.163984 Returned 0 in 5 seconds
361 01:24:25.265309 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 01:24:25.266963 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 01:24:25.267643 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 01:24:25.268151 Setting prompt string to 'Starting depthcharge on Spherion...'
366 01:24:25.268542 Changing prompt to 'Starting depthcharge on Spherion...'
367 01:24:25.268931 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 01:24:25.270278 [Enter `^Ec?' for help]
369 01:24:25.430098
370 01:24:25.430670
371 01:24:25.431077 F0: 102B 0000
372 01:24:25.431443
373 01:24:25.431800 F3: 1001 0000 [0200]
374 01:24:25.433909
375 01:24:25.434385 F3: 1001 0000
376 01:24:25.434758
377 01:24:25.435103 F7: 102D 0000
378 01:24:25.435448
379 01:24:25.436850 F1: 0000 0000
380 01:24:25.437317
381 01:24:25.437735 V0: 0000 0000 [0001]
382 01:24:25.438088
383 01:24:25.440032 00: 0007 8000
384 01:24:25.440477
385 01:24:25.440813 01: 0000 0000
386 01:24:25.441138
387 01:24:25.443134 BP: 0C00 0209 [0000]
388 01:24:25.443659
389 01:24:25.444002 G0: 1182 0000
390 01:24:25.444315
391 01:24:25.446719 EC: 0000 0021 [4000]
392 01:24:25.447144
393 01:24:25.447485 S7: 0000 0000 [0000]
394 01:24:25.447860
395 01:24:25.450153 CC: 0000 0000 [0001]
396 01:24:25.450620
397 01:24:25.450967 T0: 0000 0040 [010F]
398 01:24:25.451285
399 01:24:25.451584 Jump to BL
400 01:24:25.451901
401 01:24:25.477424
402 01:24:25.477979
403 01:24:25.478352
404 01:24:25.483251 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 01:24:25.487042 ARM64: Exception handlers installed.
406 01:24:25.490759 ARM64: Testing exception
407 01:24:25.494310 ARM64: Done test exception
408 01:24:25.500972 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 01:24:25.511388 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 01:24:25.518025 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 01:24:25.527607 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 01:24:25.534414 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 01:24:25.545000 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 01:24:25.555208 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 01:24:25.561042 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 01:24:25.579886 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 01:24:25.583426 WDT: Last reset was cold boot
418 01:24:25.586419 SPI1(PAD0) initialized at 2873684 Hz
419 01:24:25.589646 SPI5(PAD0) initialized at 992727 Hz
420 01:24:25.593079 VBOOT: Loading verstage.
421 01:24:25.599773 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 01:24:25.603240 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 01:24:25.606278 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 01:24:25.609547 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 01:24:25.617291 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 01:24:25.623862 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 01:24:25.635156 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 01:24:25.635720
429 01:24:25.636094
430 01:24:25.644788 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 01:24:25.648581 ARM64: Exception handlers installed.
432 01:24:25.651690 ARM64: Testing exception
433 01:24:25.652280 ARM64: Done test exception
434 01:24:25.657841 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 01:24:25.661268 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 01:24:25.676102 Probing TPM: . done!
437 01:24:25.676664 TPM ready after 0 ms
438 01:24:25.681286 Connected to device vid:did:rid of 1ae0:0028:00
439 01:24:25.692427 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 01:24:25.745929 Initialized TPM device CR50 revision 0
441 01:24:25.757371 tlcl_send_startup: Startup return code is 0
442 01:24:25.757818 TPM: setup succeeded
443 01:24:25.769194 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 01:24:25.778201 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 01:24:25.790031 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 01:24:25.800120 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 01:24:25.803096 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 01:24:25.809920 in-header: 03 07 00 00 08 00 00 00
449 01:24:25.813550 in-data: aa e4 47 04 13 02 00 00
450 01:24:25.817367 Chrome EC: UHEPI supported
451 01:24:25.824970 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 01:24:25.828115 in-header: 03 ad 00 00 08 00 00 00
453 01:24:25.831560 in-data: 00 20 20 08 00 00 00 00
454 01:24:25.832084 Phase 1
455 01:24:25.834692 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 01:24:25.841900 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 01:24:25.845851 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 01:24:25.849237 Recovery requested (1009000e)
459 01:24:25.858969 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 01:24:25.864728 tlcl_extend: response is 0
461 01:24:25.874981 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 01:24:25.881049 tlcl_extend: response is 0
463 01:24:25.888677 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 01:24:25.907721 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 01:24:25.914980 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 01:24:25.915598
467 01:24:25.915977
468 01:24:25.924997 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 01:24:25.928591 ARM64: Exception handlers installed.
470 01:24:25.929058 ARM64: Testing exception
471 01:24:25.931971 ARM64: Done test exception
472 01:24:25.953739 pmic_efuse_setting: Set efuses in 11 msecs
473 01:24:25.956741 pmwrap_interface_init: Select PMIF_VLD_RDY
474 01:24:25.964263 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 01:24:25.966747 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 01:24:25.974236 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 01:24:25.977495 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 01:24:25.981666 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 01:24:25.985055 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 01:24:25.991979 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 01:24:25.995836 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 01:24:25.999010 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 01:24:26.006212 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 01:24:26.010173 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 01:24:26.013399 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 01:24:26.020281 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 01:24:26.024064 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 01:24:26.031419 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 01:24:26.038493 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 01:24:26.041976 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 01:24:26.049042 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 01:24:26.052546 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 01:24:26.060416 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 01:24:26.063868 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 01:24:26.071079 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 01:24:26.074921 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 01:24:26.082282 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 01:24:26.085682 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 01:24:26.093297 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 01:24:26.097449 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 01:24:26.104202 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 01:24:26.107684 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 01:24:26.111211 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 01:24:26.118712 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 01:24:26.122238 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 01:24:26.126140 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 01:24:26.133550 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 01:24:26.136725 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 01:24:26.140538 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 01:24:26.148323 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 01:24:26.151650 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 01:24:26.155654 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 01:24:26.163148 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 01:24:26.166367 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 01:24:26.170537 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 01:24:26.173874 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 01:24:26.177464 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 01:24:26.185424 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 01:24:26.188503 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 01:24:26.192591 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 01:24:26.196061 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 01:24:26.199295 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 01:24:26.202691 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 01:24:26.206643 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 01:24:26.217435 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 01:24:26.224368 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 01:24:26.227952 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 01:24:26.238884 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 01:24:26.246024 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 01:24:26.249817 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 01:24:26.253526 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 01:24:26.260726 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 01:24:26.267555 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0xf
534 01:24:26.271652 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 01:24:26.275200 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
536 01:24:26.282250 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 01:24:26.290758 [RTC]rtc_get_frequency_meter,154: input=15, output=834
538 01:24:26.299949 [RTC]rtc_get_frequency_meter,154: input=7, output=708
539 01:24:26.309758 [RTC]rtc_get_frequency_meter,154: input=11, output=770
540 01:24:26.319239 [RTC]rtc_get_frequency_meter,154: input=13, output=803
541 01:24:26.328364 [RTC]rtc_get_frequency_meter,154: input=12, output=787
542 01:24:26.338263 [RTC]rtc_get_frequency_meter,154: input=12, output=786
543 01:24:26.348190 [RTC]rtc_get_frequency_meter,154: input=13, output=802
544 01:24:26.350869 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
545 01:24:26.358613 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
546 01:24:26.361938 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 01:24:26.365577 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 01:24:26.368964 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 01:24:26.372779 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 01:24:26.376802 ADC[4]: Raw value=904509 ID=7
551 01:24:26.380057 ADC[3]: Raw value=213652 ID=1
552 01:24:26.380639 RAM Code: 0x71
553 01:24:26.383471 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 01:24:26.390346 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 01:24:26.397768 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 01:24:26.405106 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 01:24:26.408358 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 01:24:26.412419 in-header: 03 07 00 00 08 00 00 00
559 01:24:26.416232 in-data: aa e4 47 04 13 02 00 00
560 01:24:26.416775 Chrome EC: UHEPI supported
561 01:24:26.423244 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 01:24:26.427303 in-header: 03 ed 00 00 08 00 00 00
563 01:24:26.430601 in-data: 80 20 60 08 00 00 00 00
564 01:24:26.434314 MRC: failed to locate region type 0.
565 01:24:26.441844 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 01:24:26.445057 DRAM-K: Running full calibration
567 01:24:26.449194 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 01:24:26.452029 header.status = 0x0
569 01:24:26.456145 header.version = 0x6 (expected: 0x6)
570 01:24:26.459643 header.size = 0xd00 (expected: 0xd00)
571 01:24:26.460111 header.flags = 0x0
572 01:24:26.466708 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 01:24:26.484568 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 01:24:26.492084 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 01:24:26.495478 dram_init: ddr_geometry: 2
576 01:24:26.496066 [EMI] MDL number = 2
577 01:24:26.499087 [EMI] Get MDL freq = 0
578 01:24:26.499679 dram_init: ddr_type: 0
579 01:24:26.502572 is_discrete_lpddr4: 1
580 01:24:26.506298 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 01:24:26.506876
582 01:24:26.507250
583 01:24:26.509819 [Bian_co] ETT version 0.0.0.1
584 01:24:26.513881 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 01:24:26.514477
586 01:24:26.517454 dramc_set_vcore_voltage set vcore to 650000
587 01:24:26.520333 Read voltage for 800, 4
588 01:24:26.520875 Vio18 = 0
589 01:24:26.521251 Vcore = 650000
590 01:24:26.524325 Vdram = 0
591 01:24:26.524817 Vddq = 0
592 01:24:26.525222 Vmddr = 0
593 01:24:26.528062 dram_init: config_dvfs: 1
594 01:24:26.531896 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 01:24:26.539262 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 01:24:26.539859 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
597 01:24:26.546220 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
598 01:24:26.550528 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
599 01:24:26.554228 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
600 01:24:26.554833 MEM_TYPE=3, freq_sel=18
601 01:24:26.557843 sv_algorithm_assistance_LP4_1600
602 01:24:26.561411 ============ PULL DRAM RESETB DOWN ============
603 01:24:26.564733 ========== PULL DRAM RESETB DOWN end =========
604 01:24:26.571098 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 01:24:26.574458 ===================================
606 01:24:26.574931 LPDDR4 DRAM CONFIGURATION
607 01:24:26.578108 ===================================
608 01:24:26.581027 EX_ROW_EN[0] = 0x0
609 01:24:26.584395 EX_ROW_EN[1] = 0x0
610 01:24:26.584860 LP4Y_EN = 0x0
611 01:24:26.587445 WORK_FSP = 0x0
612 01:24:26.587924 WL = 0x2
613 01:24:26.591462 RL = 0x2
614 01:24:26.592045 BL = 0x2
615 01:24:26.594241 RPST = 0x0
616 01:24:26.594708 RD_PRE = 0x0
617 01:24:26.601708 WR_PRE = 0x1
618 01:24:26.602340 WR_PST = 0x0
619 01:24:26.603087 DBI_WR = 0x0
620 01:24:26.603549 DBI_RD = 0x0
621 01:24:26.603974 OTF = 0x1
622 01:24:26.607385 ===================================
623 01:24:26.610988 ===================================
624 01:24:26.611459 ANA top config
625 01:24:26.614034 ===================================
626 01:24:26.617413 DLL_ASYNC_EN = 0
627 01:24:26.620560 ALL_SLAVE_EN = 1
628 01:24:26.623682 NEW_RANK_MODE = 1
629 01:24:26.624173 DLL_IDLE_MODE = 1
630 01:24:26.627438 LP45_APHY_COMB_EN = 1
631 01:24:26.631056 TX_ODT_DIS = 1
632 01:24:26.634039 NEW_8X_MODE = 1
633 01:24:26.637143 ===================================
634 01:24:26.640500 ===================================
635 01:24:26.644326 data_rate = 1600
636 01:24:26.646928 CKR = 1
637 01:24:26.647510 DQ_P2S_RATIO = 8
638 01:24:26.650420 ===================================
639 01:24:26.653627 CA_P2S_RATIO = 8
640 01:24:26.656623 DQ_CA_OPEN = 0
641 01:24:26.660410 DQ_SEMI_OPEN = 0
642 01:24:26.663264 CA_SEMI_OPEN = 0
643 01:24:26.667287 CA_FULL_RATE = 0
644 01:24:26.667860 DQ_CKDIV4_EN = 1
645 01:24:26.670186 CA_CKDIV4_EN = 1
646 01:24:26.673442 CA_PREDIV_EN = 0
647 01:24:26.676763 PH8_DLY = 0
648 01:24:26.680033 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 01:24:26.683232 DQ_AAMCK_DIV = 4
650 01:24:26.683704 CA_AAMCK_DIV = 4
651 01:24:26.686819 CA_ADMCK_DIV = 4
652 01:24:26.689977 DQ_TRACK_CA_EN = 0
653 01:24:26.693796 CA_PICK = 800
654 01:24:26.696565 CA_MCKIO = 800
655 01:24:26.700661 MCKIO_SEMI = 0
656 01:24:26.702958 PLL_FREQ = 3068
657 01:24:26.703429 DQ_UI_PI_RATIO = 32
658 01:24:26.706664 CA_UI_PI_RATIO = 0
659 01:24:26.710538 ===================================
660 01:24:26.713513 ===================================
661 01:24:26.717508 memory_type:LPDDR4
662 01:24:26.718200 GP_NUM : 10
663 01:24:26.720844 SRAM_EN : 1
664 01:24:26.721425 MD32_EN : 0
665 01:24:26.724351 ===================================
666 01:24:26.728191 [ANA_INIT] >>>>>>>>>>>>>>
667 01:24:26.732021 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 01:24:26.735826 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 01:24:26.738857 ===================================
670 01:24:26.739341 data_rate = 1600,PCW = 0X7600
671 01:24:26.742593 ===================================
672 01:24:26.745843 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 01:24:26.752753 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 01:24:26.759253 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 01:24:26.762158 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 01:24:26.766033 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 01:24:26.768999 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 01:24:26.772200 [ANA_INIT] flow start
679 01:24:26.772666 [ANA_INIT] PLL >>>>>>>>
680 01:24:26.775414 [ANA_INIT] PLL <<<<<<<<
681 01:24:26.779543 [ANA_INIT] MIDPI >>>>>>>>
682 01:24:26.782157 [ANA_INIT] MIDPI <<<<<<<<
683 01:24:26.782627 [ANA_INIT] DLL >>>>>>>>
684 01:24:26.785900 [ANA_INIT] flow end
685 01:24:26.789565 ============ LP4 DIFF to SE enter ============
686 01:24:26.792388 ============ LP4 DIFF to SE exit ============
687 01:24:26.795796 [ANA_INIT] <<<<<<<<<<<<<
688 01:24:26.799396 [Flow] Enable top DCM control >>>>>
689 01:24:26.801932 [Flow] Enable top DCM control <<<<<
690 01:24:26.805802 Enable DLL master slave shuffle
691 01:24:26.812512 ==============================================================
692 01:24:26.813079 Gating Mode config
693 01:24:26.818608 ==============================================================
694 01:24:26.819184 Config description:
695 01:24:26.828386 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 01:24:26.835239 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 01:24:26.841587 SELPH_MODE 0: By rank 1: By Phase
698 01:24:26.844577 ==============================================================
699 01:24:26.848148 GAT_TRACK_EN = 1
700 01:24:26.851440 RX_GATING_MODE = 2
701 01:24:26.855114 RX_GATING_TRACK_MODE = 2
702 01:24:26.858141 SELPH_MODE = 1
703 01:24:26.861383 PICG_EARLY_EN = 1
704 01:24:26.864639 VALID_LAT_VALUE = 1
705 01:24:26.871449 ==============================================================
706 01:24:26.874383 Enter into Gating configuration >>>>
707 01:24:26.878190 Exit from Gating configuration <<<<
708 01:24:26.881150 Enter into DVFS_PRE_config >>>>>
709 01:24:26.891467 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 01:24:26.894588 Exit from DVFS_PRE_config <<<<<
711 01:24:26.897637 Enter into PICG configuration >>>>
712 01:24:26.901293 Exit from PICG configuration <<<<
713 01:24:26.904594 [RX_INPUT] configuration >>>>>
714 01:24:26.905017 [RX_INPUT] configuration <<<<<
715 01:24:26.911395 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 01:24:26.917398 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 01:24:26.921174 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 01:24:26.928148 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 01:24:26.934812 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 01:24:26.941471 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 01:24:26.944814 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 01:24:26.947782 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 01:24:26.954815 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 01:24:26.958012 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 01:24:26.961619 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 01:24:26.964648 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 01:24:26.967950 ===================================
728 01:24:26.971780 LPDDR4 DRAM CONFIGURATION
729 01:24:26.974761 ===================================
730 01:24:26.977765 EX_ROW_EN[0] = 0x0
731 01:24:26.978190 EX_ROW_EN[1] = 0x0
732 01:24:26.981370 LP4Y_EN = 0x0
733 01:24:26.981900 WORK_FSP = 0x0
734 01:24:26.984657 WL = 0x2
735 01:24:26.985081 RL = 0x2
736 01:24:26.987521 BL = 0x2
737 01:24:26.987943 RPST = 0x0
738 01:24:26.991363 RD_PRE = 0x0
739 01:24:26.994798 WR_PRE = 0x1
740 01:24:26.995227 WR_PST = 0x0
741 01:24:26.997892 DBI_WR = 0x0
742 01:24:26.998412 DBI_RD = 0x0
743 01:24:27.001411 OTF = 0x1
744 01:24:27.004743 ===================================
745 01:24:27.008318 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 01:24:27.011654 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 01:24:27.014344 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 01:24:27.017770 ===================================
749 01:24:27.021481 LPDDR4 DRAM CONFIGURATION
750 01:24:27.024508 ===================================
751 01:24:27.027862 EX_ROW_EN[0] = 0x10
752 01:24:27.028385 EX_ROW_EN[1] = 0x0
753 01:24:27.031248 LP4Y_EN = 0x0
754 01:24:27.031897 WORK_FSP = 0x0
755 01:24:27.034785 WL = 0x2
756 01:24:27.035302 RL = 0x2
757 01:24:27.038250 BL = 0x2
758 01:24:27.038779 RPST = 0x0
759 01:24:27.041357 RD_PRE = 0x0
760 01:24:27.041885 WR_PRE = 0x1
761 01:24:27.044610 WR_PST = 0x0
762 01:24:27.045037 DBI_WR = 0x0
763 01:24:27.048196 DBI_RD = 0x0
764 01:24:27.048718 OTF = 0x1
765 01:24:27.051302 ===================================
766 01:24:27.057786 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 01:24:27.063059 nWR fixed to 40
768 01:24:27.065771 [ModeRegInit_LP4] CH0 RK0
769 01:24:27.066286 [ModeRegInit_LP4] CH0 RK1
770 01:24:27.069639 [ModeRegInit_LP4] CH1 RK0
771 01:24:27.072964 [ModeRegInit_LP4] CH1 RK1
772 01:24:27.073467 match AC timing 13
773 01:24:27.079609 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 01:24:27.082382 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 01:24:27.085913 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 01:24:27.092251 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 01:24:27.095524 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 01:24:27.099253 [EMI DOE] emi_dcm 0
779 01:24:27.102189 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 01:24:27.102825 ==
781 01:24:27.105805 Dram Type= 6, Freq= 0, CH_0, rank 0
782 01:24:27.108825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 01:24:27.109525 ==
784 01:24:27.115397 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 01:24:27.122286 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 01:24:27.130341 [CA 0] Center 37 (7~68) winsize 62
787 01:24:27.133481 [CA 1] Center 37 (6~68) winsize 63
788 01:24:27.136716 [CA 2] Center 34 (4~65) winsize 62
789 01:24:27.140456 [CA 3] Center 34 (4~65) winsize 62
790 01:24:27.143717 [CA 4] Center 33 (3~64) winsize 62
791 01:24:27.146526 [CA 5] Center 33 (3~64) winsize 62
792 01:24:27.147002
793 01:24:27.150228 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 01:24:27.150791
795 01:24:27.153148 [CATrainingPosCal] consider 1 rank data
796 01:24:27.156722 u2DelayCellTimex100 = 270/100 ps
797 01:24:27.159879 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 01:24:27.166644 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 01:24:27.169313 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 01:24:27.173077 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 01:24:27.176475 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 01:24:27.179647 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 01:24:27.180114
804 01:24:27.183309 CA PerBit enable=1, Macro0, CA PI delay=33
805 01:24:27.183913
806 01:24:27.186056 [CBTSetCACLKResult] CA Dly = 33
807 01:24:27.189603 CS Dly: 6 (0~37)
808 01:24:27.190167 ==
809 01:24:27.192567 Dram Type= 6, Freq= 0, CH_0, rank 1
810 01:24:27.196432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 01:24:27.197009 ==
812 01:24:27.203002 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 01:24:27.206067 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 01:24:27.216260 [CA 0] Center 37 (6~68) winsize 63
815 01:24:27.219775 [CA 1] Center 37 (7~68) winsize 62
816 01:24:27.222711 [CA 2] Center 34 (4~65) winsize 62
817 01:24:27.225997 [CA 3] Center 34 (4~65) winsize 62
818 01:24:27.229432 [CA 4] Center 33 (3~64) winsize 62
819 01:24:27.233447 [CA 5] Center 33 (2~64) winsize 63
820 01:24:27.234011
821 01:24:27.236190 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 01:24:27.236753
823 01:24:27.239234 [CATrainingPosCal] consider 2 rank data
824 01:24:27.242690 u2DelayCellTimex100 = 270/100 ps
825 01:24:27.246180 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 01:24:27.252828 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 01:24:27.256164 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 01:24:27.259327 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 01:24:27.262828 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 01:24:27.266311 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 01:24:27.266878
832 01:24:27.270033 CA PerBit enable=1, Macro0, CA PI delay=33
833 01:24:27.270591
834 01:24:27.272589 [CBTSetCACLKResult] CA Dly = 33
835 01:24:27.275984 CS Dly: 6 (0~38)
836 01:24:27.276449
837 01:24:27.279131 ----->DramcWriteLeveling(PI) begin...
838 01:24:27.279711 ==
839 01:24:27.283259 Dram Type= 6, Freq= 0, CH_0, rank 0
840 01:24:27.286792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 01:24:27.287264 ==
842 01:24:27.289854 Write leveling (Byte 0): 30 => 30
843 01:24:27.293427 Write leveling (Byte 1): 27 => 27
844 01:24:27.293899 DramcWriteLeveling(PI) end<-----
845 01:24:27.294273
846 01:24:27.294617 ==
847 01:24:27.297380 Dram Type= 6, Freq= 0, CH_0, rank 0
848 01:24:27.303616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 01:24:27.304190 ==
850 01:24:27.304567 [Gating] SW mode calibration
851 01:24:27.314096 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 01:24:27.317860 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 01:24:27.321150 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 01:24:27.327969 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 01:24:27.331110 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 01:24:27.335097 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 01:24:27.341370 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 01:24:27.344914 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 01:24:27.347753 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 01:24:27.351252 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 01:24:27.357974 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 01:24:27.361113 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 01:24:27.364808 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 01:24:27.371313 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 01:24:27.374198 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 01:24:27.378367 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 01:24:27.384645 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 01:24:27.388085 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 01:24:27.390930 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 01:24:27.397454 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 01:24:27.400823 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
872 01:24:27.404204 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 01:24:27.411196 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 01:24:27.414733 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 01:24:27.417505 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 01:24:27.423941 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 01:24:27.427340 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 01:24:27.430315 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 01:24:27.437175 0 9 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
880 01:24:27.440782 0 9 12 | B1->B0 | 2c2b 3434 | 1 1 | (0 0) (1 1)
881 01:24:27.443747 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 01:24:27.450259 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 01:24:27.454004 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 01:24:27.456873 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 01:24:27.463694 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 01:24:27.467625 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
887 01:24:27.470570 0 10 8 | B1->B0 | 3434 2626 | 0 0 | (1 0) (0 0)
888 01:24:27.476563 0 10 12 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
889 01:24:27.480811 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 01:24:27.483712 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 01:24:27.490108 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 01:24:27.493744 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 01:24:27.497063 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 01:24:27.503658 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 01:24:27.506466 0 11 8 | B1->B0 | 2424 3838 | 0 0 | (0 0) (0 0)
896 01:24:27.510283 0 11 12 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
897 01:24:27.516807 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 01:24:27.520073 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 01:24:27.523522 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 01:24:27.529973 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 01:24:27.533585 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 01:24:27.536721 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 01:24:27.542787 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 01:24:27.546311 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 01:24:27.549944 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 01:24:27.556486 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 01:24:27.559884 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 01:24:27.563109 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 01:24:27.569313 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 01:24:27.572941 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 01:24:27.576167 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 01:24:27.582924 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 01:24:27.585987 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 01:24:27.589374 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 01:24:27.596520 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 01:24:27.599500 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 01:24:27.602408 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 01:24:27.606046 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 01:24:27.612957 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 01:24:27.616100 Total UI for P1: 0, mck2ui 16
921 01:24:27.619216 best dqsien dly found for B0: ( 0, 14, 6)
922 01:24:27.622852 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
923 01:24:27.625785 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
924 01:24:27.632605 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
925 01:24:27.636597 Total UI for P1: 0, mck2ui 16
926 01:24:27.639257 best dqsien dly found for B1: ( 0, 14, 12)
927 01:24:27.642451 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
928 01:24:27.646276 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
929 01:24:27.646842
930 01:24:27.649433 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
931 01:24:27.652685 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
932 01:24:27.655888 [Gating] SW calibration Done
933 01:24:27.656448 ==
934 01:24:27.659330 Dram Type= 6, Freq= 0, CH_0, rank 0
935 01:24:27.662857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
936 01:24:27.663422 ==
937 01:24:27.665909 RX Vref Scan: 0
938 01:24:27.666373
939 01:24:27.666742 RX Vref 0 -> 0, step: 1
940 01:24:27.669373
941 01:24:27.669933 RX Delay -130 -> 252, step: 16
942 01:24:27.675733 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
943 01:24:27.678855 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
944 01:24:27.683099 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
945 01:24:27.685587 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
946 01:24:27.688727 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
947 01:24:27.696197 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
948 01:24:27.699215 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
949 01:24:27.702512 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
950 01:24:27.705433 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
951 01:24:27.708895 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
952 01:24:27.715259 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
953 01:24:27.719124 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
954 01:24:27.722189 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
955 01:24:27.725476 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
956 01:24:27.729096 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
957 01:24:27.735678 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
958 01:24:27.736223 ==
959 01:24:27.738794 Dram Type= 6, Freq= 0, CH_0, rank 0
960 01:24:27.741873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 01:24:27.742346 ==
962 01:24:27.742752 DQS Delay:
963 01:24:27.745724 DQS0 = 0, DQS1 = 0
964 01:24:27.746277 DQM Delay:
965 01:24:27.748853 DQM0 = 86, DQM1 = 74
966 01:24:27.749321 DQ Delay:
967 01:24:27.752003 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
968 01:24:27.755893 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
969 01:24:27.758776 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
970 01:24:27.761978 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
971 01:24:27.762543
972 01:24:27.762916
973 01:24:27.763256 ==
974 01:24:27.765757 Dram Type= 6, Freq= 0, CH_0, rank 0
975 01:24:27.768928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
976 01:24:27.771834 ==
977 01:24:27.772393
978 01:24:27.772760
979 01:24:27.773104 TX Vref Scan disable
980 01:24:27.774871 == TX Byte 0 ==
981 01:24:27.778212 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
982 01:24:27.785317 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
983 01:24:27.785939 == TX Byte 1 ==
984 01:24:27.788530 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
985 01:24:27.794892 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
986 01:24:27.795443 ==
987 01:24:27.798004 Dram Type= 6, Freq= 0, CH_0, rank 0
988 01:24:27.801471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
989 01:24:27.801945 ==
990 01:24:27.814212 TX Vref=22, minBit 15, minWin=26, winSum=438
991 01:24:27.817561 TX Vref=24, minBit 4, minWin=27, winSum=442
992 01:24:27.820543 TX Vref=26, minBit 13, minWin=27, winSum=447
993 01:24:27.823928 TX Vref=28, minBit 5, minWin=27, winSum=449
994 01:24:27.827718 TX Vref=30, minBit 10, minWin=27, winSum=446
995 01:24:27.833939 TX Vref=32, minBit 11, minWin=26, winSum=441
996 01:24:27.838040 [TxChooseVref] Worse bit 5, Min win 27, Win sum 449, Final Vref 28
997 01:24:27.838612
998 01:24:27.840921 Final TX Range 1 Vref 28
999 01:24:27.841430
1000 01:24:27.841806 ==
1001 01:24:27.843867 Dram Type= 6, Freq= 0, CH_0, rank 0
1002 01:24:27.848078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1003 01:24:27.850868 ==
1004 01:24:27.851340
1005 01:24:27.851709
1006 01:24:27.852054 TX Vref Scan disable
1007 01:24:27.854951 == TX Byte 0 ==
1008 01:24:27.858176 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1009 01:24:27.861323 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1010 01:24:27.864747 == TX Byte 1 ==
1011 01:24:27.867706 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1012 01:24:27.874713 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1013 01:24:27.875307
1014 01:24:27.875687 [DATLAT]
1015 01:24:27.876032 Freq=800, CH0 RK0
1016 01:24:27.876359
1017 01:24:27.877786 DATLAT Default: 0xa
1018 01:24:27.878250 0, 0xFFFF, sum = 0
1019 01:24:27.881162 1, 0xFFFF, sum = 0
1020 01:24:27.884329 2, 0xFFFF, sum = 0
1021 01:24:27.884890 3, 0xFFFF, sum = 0
1022 01:24:27.887456 4, 0xFFFF, sum = 0
1023 01:24:27.887932 5, 0xFFFF, sum = 0
1024 01:24:27.890383 6, 0xFFFF, sum = 0
1025 01:24:27.890892 7, 0xFFFF, sum = 0
1026 01:24:27.893907 8, 0xFFFF, sum = 0
1027 01:24:27.894371 9, 0x0, sum = 1
1028 01:24:27.897547 10, 0x0, sum = 2
1029 01:24:27.898015 11, 0x0, sum = 3
1030 01:24:27.900613 12, 0x0, sum = 4
1031 01:24:27.901189 best_step = 10
1032 01:24:27.901623
1033 01:24:27.901970 ==
1034 01:24:27.904158 Dram Type= 6, Freq= 0, CH_0, rank 0
1035 01:24:27.907087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1036 01:24:27.907552 ==
1037 01:24:27.910932 RX Vref Scan: 1
1038 01:24:27.911480
1039 01:24:27.914299 Set Vref Range= 32 -> 127
1040 01:24:27.914855
1041 01:24:27.915224 RX Vref 32 -> 127, step: 1
1042 01:24:27.915567
1043 01:24:27.917522 RX Delay -95 -> 252, step: 8
1044 01:24:27.918068
1045 01:24:27.920607 Set Vref, RX VrefLevel [Byte0]: 32
1046 01:24:27.924271 [Byte1]: 32
1047 01:24:27.924825
1048 01:24:27.927359 Set Vref, RX VrefLevel [Byte0]: 33
1049 01:24:27.930482 [Byte1]: 33
1050 01:24:27.934981
1051 01:24:27.935529 Set Vref, RX VrefLevel [Byte0]: 34
1052 01:24:27.938124 [Byte1]: 34
1053 01:24:27.942711
1054 01:24:27.943261 Set Vref, RX VrefLevel [Byte0]: 35
1055 01:24:27.945789 [Byte1]: 35
1056 01:24:27.950550
1057 01:24:27.951117 Set Vref, RX VrefLevel [Byte0]: 36
1058 01:24:27.953575 [Byte1]: 36
1059 01:24:27.957961
1060 01:24:27.958510 Set Vref, RX VrefLevel [Byte0]: 37
1061 01:24:27.961474 [Byte1]: 37
1062 01:24:27.965236
1063 01:24:27.965756 Set Vref, RX VrefLevel [Byte0]: 38
1064 01:24:27.969698 [Byte1]: 38
1065 01:24:27.973275
1066 01:24:27.973782 Set Vref, RX VrefLevel [Byte0]: 39
1067 01:24:27.976819 [Byte1]: 39
1068 01:24:27.980439
1069 01:24:27.981026 Set Vref, RX VrefLevel [Byte0]: 40
1070 01:24:27.984030 [Byte1]: 40
1071 01:24:27.988037
1072 01:24:27.988508 Set Vref, RX VrefLevel [Byte0]: 41
1073 01:24:27.991154 [Byte1]: 41
1074 01:24:27.995339
1075 01:24:27.995796 Set Vref, RX VrefLevel [Byte0]: 42
1076 01:24:27.998933 [Byte1]: 42
1077 01:24:28.003346
1078 01:24:28.004027 Set Vref, RX VrefLevel [Byte0]: 43
1079 01:24:28.006393 [Byte1]: 43
1080 01:24:28.011048
1081 01:24:28.011563 Set Vref, RX VrefLevel [Byte0]: 44
1082 01:24:28.013990 [Byte1]: 44
1083 01:24:28.018340
1084 01:24:28.018754 Set Vref, RX VrefLevel [Byte0]: 45
1085 01:24:28.021869 [Byte1]: 45
1086 01:24:28.025832
1087 01:24:28.026292 Set Vref, RX VrefLevel [Byte0]: 46
1088 01:24:28.028977 [Byte1]: 46
1089 01:24:28.033687
1090 01:24:28.034400 Set Vref, RX VrefLevel [Byte0]: 47
1091 01:24:28.037118 [Byte1]: 47
1092 01:24:28.040879
1093 01:24:28.041293 Set Vref, RX VrefLevel [Byte0]: 48
1094 01:24:28.044344 [Byte1]: 48
1095 01:24:28.048720
1096 01:24:28.049138 Set Vref, RX VrefLevel [Byte0]: 49
1097 01:24:28.052385 [Byte1]: 49
1098 01:24:28.056562
1099 01:24:28.057088 Set Vref, RX VrefLevel [Byte0]: 50
1100 01:24:28.059465 [Byte1]: 50
1101 01:24:28.063541
1102 01:24:28.063959 Set Vref, RX VrefLevel [Byte0]: 51
1103 01:24:28.067178 [Byte1]: 51
1104 01:24:28.071381
1105 01:24:28.071797 Set Vref, RX VrefLevel [Byte0]: 52
1106 01:24:28.074675 [Byte1]: 52
1107 01:24:28.079122
1108 01:24:28.079638 Set Vref, RX VrefLevel [Byte0]: 53
1109 01:24:28.082041 [Byte1]: 53
1110 01:24:28.086441
1111 01:24:28.086858 Set Vref, RX VrefLevel [Byte0]: 54
1112 01:24:28.089899 [Byte1]: 54
1113 01:24:28.094102
1114 01:24:28.094530 Set Vref, RX VrefLevel [Byte0]: 55
1115 01:24:28.097222 [Byte1]: 55
1116 01:24:28.101827
1117 01:24:28.102242 Set Vref, RX VrefLevel [Byte0]: 56
1118 01:24:28.105068 [Byte1]: 56
1119 01:24:28.109071
1120 01:24:28.109547 Set Vref, RX VrefLevel [Byte0]: 57
1121 01:24:28.112513 [Byte1]: 57
1122 01:24:28.116932
1123 01:24:28.117392 Set Vref, RX VrefLevel [Byte0]: 58
1124 01:24:28.120130 [Byte1]: 58
1125 01:24:28.124396
1126 01:24:28.124813 Set Vref, RX VrefLevel [Byte0]: 59
1127 01:24:28.127844 [Byte1]: 59
1128 01:24:28.132167
1129 01:24:28.132710 Set Vref, RX VrefLevel [Byte0]: 60
1130 01:24:28.135512 [Byte1]: 60
1131 01:24:28.139986
1132 01:24:28.140495 Set Vref, RX VrefLevel [Byte0]: 61
1133 01:24:28.143180 [Byte1]: 61
1134 01:24:28.147372
1135 01:24:28.147891 Set Vref, RX VrefLevel [Byte0]: 62
1136 01:24:28.150628 [Byte1]: 62
1137 01:24:28.155111
1138 01:24:28.155527 Set Vref, RX VrefLevel [Byte0]: 63
1139 01:24:28.158297 [Byte1]: 63
1140 01:24:28.162712
1141 01:24:28.163127 Set Vref, RX VrefLevel [Byte0]: 64
1142 01:24:28.165707 [Byte1]: 64
1143 01:24:28.170293
1144 01:24:28.170710 Set Vref, RX VrefLevel [Byte0]: 65
1145 01:24:28.173866 [Byte1]: 65
1146 01:24:28.177845
1147 01:24:28.178266 Set Vref, RX VrefLevel [Byte0]: 66
1148 01:24:28.180948 [Byte1]: 66
1149 01:24:28.185635
1150 01:24:28.186158 Set Vref, RX VrefLevel [Byte0]: 67
1151 01:24:28.189127 [Byte1]: 67
1152 01:24:28.192840
1153 01:24:28.193616 Set Vref, RX VrefLevel [Byte0]: 68
1154 01:24:28.196207 [Byte1]: 68
1155 01:24:28.200381
1156 01:24:28.200798 Set Vref, RX VrefLevel [Byte0]: 69
1157 01:24:28.203969 [Byte1]: 69
1158 01:24:28.208308
1159 01:24:28.208738 Set Vref, RX VrefLevel [Byte0]: 70
1160 01:24:28.211440 [Byte1]: 70
1161 01:24:28.215823
1162 01:24:28.216237 Set Vref, RX VrefLevel [Byte0]: 71
1163 01:24:28.219224 [Byte1]: 71
1164 01:24:28.223613
1165 01:24:28.224300 Set Vref, RX VrefLevel [Byte0]: 72
1166 01:24:28.226409 [Byte1]: 72
1167 01:24:28.230817
1168 01:24:28.231237 Set Vref, RX VrefLevel [Byte0]: 73
1169 01:24:28.234358 [Byte1]: 73
1170 01:24:28.238831
1171 01:24:28.239351 Set Vref, RX VrefLevel [Byte0]: 74
1172 01:24:28.241630 [Byte1]: 74
1173 01:24:28.246023
1174 01:24:28.246536 Set Vref, RX VrefLevel [Byte0]: 75
1175 01:24:28.249563 [Byte1]: 75
1176 01:24:28.253783
1177 01:24:28.254212 Set Vref, RX VrefLevel [Byte0]: 76
1178 01:24:28.257286 [Byte1]: 76
1179 01:24:28.261234
1180 01:24:28.261706 Set Vref, RX VrefLevel [Byte0]: 77
1181 01:24:28.264469 [Byte1]: 77
1182 01:24:28.268675
1183 01:24:28.269105 Set Vref, RX VrefLevel [Byte0]: 78
1184 01:24:28.272426 [Byte1]: 78
1185 01:24:28.276648
1186 01:24:28.277084 Set Vref, RX VrefLevel [Byte0]: 79
1187 01:24:28.279804 [Byte1]: 79
1188 01:24:28.283869
1189 01:24:28.284285 Set Vref, RX VrefLevel [Byte0]: 80
1190 01:24:28.287379 [Byte1]: 80
1191 01:24:28.291846
1192 01:24:28.292370 Set Vref, RX VrefLevel [Byte0]: 81
1193 01:24:28.294860 [Byte1]: 81
1194 01:24:28.299676
1195 01:24:28.300184 Final RX Vref Byte 0 = 61 to rank0
1196 01:24:28.302580 Final RX Vref Byte 1 = 54 to rank0
1197 01:24:28.305752 Final RX Vref Byte 0 = 61 to rank1
1198 01:24:28.309421 Final RX Vref Byte 1 = 54 to rank1==
1199 01:24:28.312496 Dram Type= 6, Freq= 0, CH_0, rank 0
1200 01:24:28.319267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1201 01:24:28.319821 ==
1202 01:24:28.320191 DQS Delay:
1203 01:24:28.322525 DQS0 = 0, DQS1 = 0
1204 01:24:28.322986 DQM Delay:
1205 01:24:28.323350 DQM0 = 86, DQM1 = 76
1206 01:24:28.325715 DQ Delay:
1207 01:24:28.329084 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =80
1208 01:24:28.332477 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1209 01:24:28.335696 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1210 01:24:28.339202 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1211 01:24:28.339756
1212 01:24:28.340122
1213 01:24:28.345674 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f20, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
1214 01:24:28.389950 CH0 RK0: MR19=606, MR18=3F20
1215 01:24:28.390879 CH0_RK0: MR19=0x606, MR18=0x3F20, DQSOSC=393, MR23=63, INC=95, DEC=63
1216 01:24:28.391291
1217 01:24:28.391642 ----->DramcWriteLeveling(PI) begin...
1218 01:24:28.391984 ==
1219 01:24:28.392306 Dram Type= 6, Freq= 0, CH_0, rank 1
1220 01:24:28.392626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1221 01:24:28.392941 ==
1222 01:24:28.393318 Write leveling (Byte 0): 31 => 31
1223 01:24:28.393701 Write leveling (Byte 1): 31 => 31
1224 01:24:28.394015 DramcWriteLeveling(PI) end<-----
1225 01:24:28.394322
1226 01:24:28.394630 ==
1227 01:24:28.394934 Dram Type= 6, Freq= 0, CH_0, rank 1
1228 01:24:28.395240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1229 01:24:28.395545 ==
1230 01:24:28.395946 [Gating] SW mode calibration
1231 01:24:28.410194 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1232 01:24:28.411106 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1233 01:24:28.411516 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1234 01:24:28.411870 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1235 01:24:28.414203 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1236 01:24:28.417230 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 01:24:28.420685 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 01:24:28.424148 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 01:24:28.430782 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 01:24:28.433618 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 01:24:28.437665 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 01:24:28.443654 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 01:24:28.447186 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 01:24:28.450597 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 01:24:28.456787 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 01:24:28.460144 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 01:24:28.464043 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 01:24:28.470331 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 01:24:28.473453 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 01:24:28.476582 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1251 01:24:28.483050 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1252 01:24:28.486125 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1253 01:24:28.489452 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 01:24:28.496601 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 01:24:28.499807 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 01:24:28.503075 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 01:24:28.509699 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 01:24:28.512801 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 01:24:28.516335 0 9 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
1260 01:24:28.522613 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1261 01:24:28.526552 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1262 01:24:28.529697 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1263 01:24:28.533048 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1264 01:24:28.540374 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1265 01:24:28.543838 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1266 01:24:28.547640 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1267 01:24:28.550975 0 10 8 | B1->B0 | 3333 2b2b | 0 0 | (0 1) (1 0)
1268 01:24:28.557434 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1269 01:24:28.561418 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1270 01:24:28.564637 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1271 01:24:28.568394 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1272 01:24:28.574739 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1273 01:24:28.578266 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1274 01:24:28.581121 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1275 01:24:28.588281 0 11 8 | B1->B0 | 2d2d 3838 | 0 0 | (0 0) (0 0)
1276 01:24:28.591337 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1277 01:24:28.594644 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1278 01:24:28.601494 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1279 01:24:28.604831 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1280 01:24:28.607579 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1281 01:24:28.614494 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1282 01:24:28.617604 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1283 01:24:28.620833 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1284 01:24:28.627459 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 01:24:28.631240 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 01:24:28.634306 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 01:24:28.641303 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 01:24:28.644579 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 01:24:28.647749 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 01:24:28.654078 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 01:24:28.657781 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 01:24:28.660587 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 01:24:28.668260 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 01:24:28.671243 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1295 01:24:28.674283 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1296 01:24:28.680536 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1297 01:24:28.684161 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1298 01:24:28.687450 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1299 01:24:28.693848 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1300 01:24:28.694399 Total UI for P1: 0, mck2ui 16
1301 01:24:28.700747 best dqsien dly found for B0: ( 0, 14, 6)
1302 01:24:28.703935 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1303 01:24:28.706855 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1304 01:24:28.710556 Total UI for P1: 0, mck2ui 16
1305 01:24:28.713644 best dqsien dly found for B1: ( 0, 14, 10)
1306 01:24:28.716694 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1307 01:24:28.720690 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1308 01:24:28.721260
1309 01:24:28.727081 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1310 01:24:28.729991 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1311 01:24:28.730531 [Gating] SW calibration Done
1312 01:24:28.733326 ==
1313 01:24:28.736758 Dram Type= 6, Freq= 0, CH_0, rank 1
1314 01:24:28.740391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1315 01:24:28.740947 ==
1316 01:24:28.741314 RX Vref Scan: 0
1317 01:24:28.741682
1318 01:24:28.743962 RX Vref 0 -> 0, step: 1
1319 01:24:28.744522
1320 01:24:28.746527 RX Delay -130 -> 252, step: 16
1321 01:24:28.749913 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1322 01:24:28.753418 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1323 01:24:28.760140 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1324 01:24:28.763006 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1325 01:24:28.767021 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1326 01:24:28.770135 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1327 01:24:28.772957 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1328 01:24:28.779686 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1329 01:24:28.782639 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1330 01:24:28.785943 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1331 01:24:28.789560 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1332 01:24:28.793217 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1333 01:24:28.799446 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1334 01:24:28.802823 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1335 01:24:28.806054 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1336 01:24:28.809559 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1337 01:24:28.810033 ==
1338 01:24:28.813193 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 01:24:28.819933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 01:24:28.820502 ==
1341 01:24:28.820988 DQS Delay:
1342 01:24:28.822346 DQS0 = 0, DQS1 = 0
1343 01:24:28.822815 DQM Delay:
1344 01:24:28.823289 DQM0 = 85, DQM1 = 79
1345 01:24:28.826094 DQ Delay:
1346 01:24:28.829585 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1347 01:24:28.832700 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1348 01:24:28.836254 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1349 01:24:28.839365 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1350 01:24:28.839950
1351 01:24:28.840438
1352 01:24:28.840893 ==
1353 01:24:28.842190 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 01:24:28.846074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 01:24:28.846644 ==
1356 01:24:28.847134
1357 01:24:28.847583
1358 01:24:28.849232 TX Vref Scan disable
1359 01:24:28.852482 == TX Byte 0 ==
1360 01:24:28.855465 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1361 01:24:28.859226 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1362 01:24:28.862341 == TX Byte 1 ==
1363 01:24:28.865111 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1364 01:24:28.868419 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1365 01:24:28.868843 ==
1366 01:24:28.871779 Dram Type= 6, Freq= 0, CH_0, rank 1
1367 01:24:28.875087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 01:24:28.878428 ==
1369 01:24:28.889656 TX Vref=22, minBit 8, minWin=27, winSum=447
1370 01:24:28.892948 TX Vref=24, minBit 9, minWin=27, winSum=447
1371 01:24:28.896285 TX Vref=26, minBit 3, minWin=27, winSum=447
1372 01:24:28.900240 TX Vref=28, minBit 8, minWin=27, winSum=446
1373 01:24:28.902748 TX Vref=30, minBit 9, minWin=27, winSum=447
1374 01:24:28.909456 TX Vref=32, minBit 9, minWin=27, winSum=445
1375 01:24:28.913115 [TxChooseVref] Worse bit 8, Min win 27, Win sum 447, Final Vref 22
1376 01:24:28.913623
1377 01:24:28.916169 Final TX Range 1 Vref 22
1378 01:24:28.916622
1379 01:24:28.916975 ==
1380 01:24:28.919921 Dram Type= 6, Freq= 0, CH_0, rank 1
1381 01:24:28.923003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 01:24:28.923520 ==
1383 01:24:28.926071
1384 01:24:28.926476
1385 01:24:28.926796 TX Vref Scan disable
1386 01:24:28.929791 == TX Byte 0 ==
1387 01:24:28.933758 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1388 01:24:28.936640 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1389 01:24:28.939902 == TX Byte 1 ==
1390 01:24:28.942812 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1391 01:24:28.949570 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1392 01:24:28.950118
1393 01:24:28.950479 [DATLAT]
1394 01:24:28.950817 Freq=800, CH0 RK1
1395 01:24:28.951137
1396 01:24:28.953014 DATLAT Default: 0xa
1397 01:24:28.953504 0, 0xFFFF, sum = 0
1398 01:24:28.956650 1, 0xFFFF, sum = 0
1399 01:24:28.957200 2, 0xFFFF, sum = 0
1400 01:24:28.959583 3, 0xFFFF, sum = 0
1401 01:24:28.963387 4, 0xFFFF, sum = 0
1402 01:24:28.963847 5, 0xFFFF, sum = 0
1403 01:24:28.966105 6, 0xFFFF, sum = 0
1404 01:24:28.966564 7, 0xFFFF, sum = 0
1405 01:24:28.970097 8, 0xFFFF, sum = 0
1406 01:24:28.970651 9, 0x0, sum = 1
1407 01:24:28.971020 10, 0x0, sum = 2
1408 01:24:28.973439 11, 0x0, sum = 3
1409 01:24:28.973992 12, 0x0, sum = 4
1410 01:24:28.976710 best_step = 10
1411 01:24:28.977254
1412 01:24:28.977662 ==
1413 01:24:28.979686 Dram Type= 6, Freq= 0, CH_0, rank 1
1414 01:24:28.983305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1415 01:24:28.983763 ==
1416 01:24:28.986549 RX Vref Scan: 0
1417 01:24:28.986998
1418 01:24:28.987356 RX Vref 0 -> 0, step: 1
1419 01:24:28.987691
1420 01:24:28.989556 RX Delay -95 -> 252, step: 8
1421 01:24:28.996169 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1422 01:24:29.000276 iDelay=209, Bit 1, Center 88 (-31 ~ 208) 240
1423 01:24:29.003234 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1424 01:24:29.006553 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1425 01:24:29.013500 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1426 01:24:29.016328 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1427 01:24:29.019536 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1428 01:24:29.023323 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1429 01:24:29.026049 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1430 01:24:29.029406 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1431 01:24:29.036765 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1432 01:24:29.039348 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1433 01:24:29.043041 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1434 01:24:29.046236 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
1435 01:24:29.052716 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1436 01:24:29.056155 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1437 01:24:29.056714 ==
1438 01:24:29.059231 Dram Type= 6, Freq= 0, CH_0, rank 1
1439 01:24:29.062540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 01:24:29.063002 ==
1441 01:24:29.065895 DQS Delay:
1442 01:24:29.066360 DQS0 = 0, DQS1 = 0
1443 01:24:29.066720 DQM Delay:
1444 01:24:29.069168 DQM0 = 84, DQM1 = 75
1445 01:24:29.069778 DQ Delay:
1446 01:24:29.072568 DQ0 =80, DQ1 =88, DQ2 =80, DQ3 =84
1447 01:24:29.075681 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1448 01:24:29.079291 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1449 01:24:29.082404 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1450 01:24:29.082865
1451 01:24:29.083228
1452 01:24:29.092312 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c04, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
1453 01:24:29.092777 CH0 RK1: MR19=606, MR18=3C04
1454 01:24:29.098907 CH0_RK1: MR19=0x606, MR18=0x3C04, DQSOSC=394, MR23=63, INC=95, DEC=63
1455 01:24:29.102613 [RxdqsGatingPostProcess] freq 800
1456 01:24:29.109129 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1457 01:24:29.112340 Pre-setting of DQS Precalculation
1458 01:24:29.115374 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1459 01:24:29.115937 ==
1460 01:24:29.119131 Dram Type= 6, Freq= 0, CH_1, rank 0
1461 01:24:29.125563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1462 01:24:29.126111 ==
1463 01:24:29.128596 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1464 01:24:29.135542 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1465 01:24:29.145031 [CA 0] Center 36 (6~67) winsize 62
1466 01:24:29.148588 [CA 1] Center 36 (6~67) winsize 62
1467 01:24:29.151797 [CA 2] Center 34 (4~65) winsize 62
1468 01:24:29.154877 [CA 3] Center 34 (3~65) winsize 63
1469 01:24:29.158281 [CA 4] Center 34 (4~65) winsize 62
1470 01:24:29.161426 [CA 5] Center 34 (3~65) winsize 63
1471 01:24:29.161973
1472 01:24:29.164729 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1473 01:24:29.165200
1474 01:24:29.168416 [CATrainingPosCal] consider 1 rank data
1475 01:24:29.171520 u2DelayCellTimex100 = 270/100 ps
1476 01:24:29.175039 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1477 01:24:29.181528 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1478 01:24:29.184512 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1479 01:24:29.188126 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1480 01:24:29.190909 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1481 01:24:29.194801 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1482 01:24:29.195370
1483 01:24:29.198104 CA PerBit enable=1, Macro0, CA PI delay=34
1484 01:24:29.198592
1485 01:24:29.201536 [CBTSetCACLKResult] CA Dly = 34
1486 01:24:29.202090 CS Dly: 5 (0~36)
1487 01:24:29.202571 ==
1488 01:24:29.205137 Dram Type= 6, Freq= 0, CH_1, rank 1
1489 01:24:29.208503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1490 01:24:29.212699 ==
1491 01:24:29.216371 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1492 01:24:29.222908 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1493 01:24:29.231472 [CA 0] Center 36 (6~67) winsize 62
1494 01:24:29.234569 [CA 1] Center 37 (6~68) winsize 63
1495 01:24:29.237987 [CA 2] Center 34 (4~65) winsize 62
1496 01:24:29.241789 [CA 3] Center 34 (3~65) winsize 63
1497 01:24:29.245073 [CA 4] Center 34 (4~65) winsize 62
1498 01:24:29.248105 [CA 5] Center 34 (4~64) winsize 61
1499 01:24:29.248673
1500 01:24:29.250925 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1501 01:24:29.251387
1502 01:24:29.254651 [CATrainingPosCal] consider 2 rank data
1503 01:24:29.257710 u2DelayCellTimex100 = 270/100 ps
1504 01:24:29.260950 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1505 01:24:29.264523 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1506 01:24:29.268025 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1507 01:24:29.274318 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1508 01:24:29.277600 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1509 01:24:29.281245 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1510 01:24:29.281992
1511 01:24:29.284151 CA PerBit enable=1, Macro0, CA PI delay=34
1512 01:24:29.284620
1513 01:24:29.287598 [CBTSetCACLKResult] CA Dly = 34
1514 01:24:29.288065 CS Dly: 6 (0~38)
1515 01:24:29.288536
1516 01:24:29.290748 ----->DramcWriteLeveling(PI) begin...
1517 01:24:29.293841 ==
1518 01:24:29.297622 Dram Type= 6, Freq= 0, CH_1, rank 0
1519 01:24:29.300776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1520 01:24:29.301250 ==
1521 01:24:29.304174 Write leveling (Byte 0): 26 => 26
1522 01:24:29.306912 Write leveling (Byte 1): 29 => 29
1523 01:24:29.310920 DramcWriteLeveling(PI) end<-----
1524 01:24:29.311541
1525 01:24:29.312019 ==
1526 01:24:29.314529 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 01:24:29.317366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 01:24:29.317802 ==
1529 01:24:29.320342 [Gating] SW mode calibration
1530 01:24:29.327487 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1531 01:24:29.333779 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1532 01:24:29.336738 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1533 01:24:29.340686 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1534 01:24:29.347003 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1535 01:24:29.350121 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 01:24:29.353600 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 01:24:29.360134 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 01:24:29.363387 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 01:24:29.367155 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 01:24:29.370314 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 01:24:29.376699 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 01:24:29.379876 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 01:24:29.383688 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 01:24:29.390081 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 01:24:29.393061 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 01:24:29.396414 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 01:24:29.403409 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 01:24:29.406710 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1549 01:24:29.410025 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1550 01:24:29.416599 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1551 01:24:29.420133 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 01:24:29.422864 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 01:24:29.429622 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 01:24:29.433589 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 01:24:29.436199 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 01:24:29.442889 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 01:24:29.446758 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 01:24:29.449741 0 9 8 | B1->B0 | 2f2f 3131 | 0 0 | (0 0) (0 0)
1559 01:24:29.456954 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1560 01:24:29.459825 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1561 01:24:29.462911 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1562 01:24:29.469301 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1563 01:24:29.472926 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1564 01:24:29.476114 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1565 01:24:29.482520 0 10 4 | B1->B0 | 3434 3333 | 0 0 | (0 1) (0 1)
1566 01:24:29.485859 0 10 8 | B1->B0 | 2828 2727 | 1 0 | (1 0) (0 0)
1567 01:24:29.489145 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1568 01:24:29.496054 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1569 01:24:29.499469 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1570 01:24:29.502716 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1571 01:24:29.509141 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1572 01:24:29.512946 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1573 01:24:29.516040 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1574 01:24:29.522815 0 11 8 | B1->B0 | 3b3b 3b3b | 0 0 | (0 0) (0 0)
1575 01:24:29.525601 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1576 01:24:29.528999 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1577 01:24:29.535601 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1578 01:24:29.539713 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1579 01:24:29.542017 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1580 01:24:29.549043 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1581 01:24:29.552431 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1582 01:24:29.555303 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1583 01:24:29.561853 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 01:24:29.565655 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 01:24:29.569033 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 01:24:29.575586 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 01:24:29.578535 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 01:24:29.582308 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 01:24:29.588546 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 01:24:29.591966 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 01:24:29.595125 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 01:24:29.601801 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1593 01:24:29.605260 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1594 01:24:29.608443 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1595 01:24:29.612052 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1596 01:24:29.618746 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1597 01:24:29.621518 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1598 01:24:29.625214 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1599 01:24:29.628822 Total UI for P1: 0, mck2ui 16
1600 01:24:29.632036 best dqsien dly found for B0: ( 0, 14, 4)
1601 01:24:29.638116 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1602 01:24:29.641756 Total UI for P1: 0, mck2ui 16
1603 01:24:29.644723 best dqsien dly found for B1: ( 0, 14, 8)
1604 01:24:29.648660 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1605 01:24:29.651382 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1606 01:24:29.651853
1607 01:24:29.654965 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1608 01:24:29.658060 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1609 01:24:29.661660 [Gating] SW calibration Done
1610 01:24:29.662226 ==
1611 01:24:29.664536 Dram Type= 6, Freq= 0, CH_1, rank 0
1612 01:24:29.668522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1613 01:24:29.669089 ==
1614 01:24:29.671632 RX Vref Scan: 0
1615 01:24:29.672193
1616 01:24:29.675389 RX Vref 0 -> 0, step: 1
1617 01:24:29.675955
1618 01:24:29.676433 RX Delay -130 -> 252, step: 16
1619 01:24:29.681365 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1620 01:24:29.685013 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1621 01:24:29.688478 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1622 01:24:29.691364 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1623 01:24:29.694543 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1624 01:24:29.701060 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1625 01:24:29.704398 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1626 01:24:29.707550 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1627 01:24:29.711054 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1628 01:24:29.714300 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1629 01:24:29.720783 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1630 01:24:29.724457 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1631 01:24:29.727299 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1632 01:24:29.730767 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1633 01:24:29.736737 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1634 01:24:29.740565 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1635 01:24:29.741117 ==
1636 01:24:29.743636 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 01:24:29.747020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 01:24:29.747497 ==
1639 01:24:29.750150 DQS Delay:
1640 01:24:29.750608 DQS0 = 0, DQS1 = 0
1641 01:24:29.753490 DQM Delay:
1642 01:24:29.753903 DQM0 = 89, DQM1 = 78
1643 01:24:29.754230 DQ Delay:
1644 01:24:29.756911 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1645 01:24:29.760052 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1646 01:24:29.763899 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1647 01:24:29.766514 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1648 01:24:29.766927
1649 01:24:29.767256
1650 01:24:29.770264 ==
1651 01:24:29.773829 Dram Type= 6, Freq= 0, CH_1, rank 0
1652 01:24:29.776844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1653 01:24:29.777390 ==
1654 01:24:29.777763
1655 01:24:29.778088
1656 01:24:29.779877 TX Vref Scan disable
1657 01:24:29.780304 == TX Byte 0 ==
1658 01:24:29.783424 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1659 01:24:29.790517 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1660 01:24:29.790935 == TX Byte 1 ==
1661 01:24:29.793869 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1662 01:24:29.800283 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1663 01:24:29.800694 ==
1664 01:24:29.803278 Dram Type= 6, Freq= 0, CH_1, rank 0
1665 01:24:29.806822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1666 01:24:29.807236 ==
1667 01:24:29.819723 TX Vref=22, minBit 8, minWin=26, winSum=438
1668 01:24:29.822790 TX Vref=24, minBit 1, minWin=27, winSum=442
1669 01:24:29.826481 TX Vref=26, minBit 0, minWin=27, winSum=447
1670 01:24:29.829593 TX Vref=28, minBit 10, minWin=27, winSum=449
1671 01:24:29.832777 TX Vref=30, minBit 13, minWin=27, winSum=449
1672 01:24:29.839183 TX Vref=32, minBit 9, minWin=26, winSum=442
1673 01:24:29.842720 [TxChooseVref] Worse bit 10, Min win 27, Win sum 449, Final Vref 28
1674 01:24:29.842908
1675 01:24:29.846099 Final TX Range 1 Vref 28
1676 01:24:29.846246
1677 01:24:29.846340 ==
1678 01:24:29.849246 Dram Type= 6, Freq= 0, CH_1, rank 0
1679 01:24:29.855880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1680 01:24:29.856027 ==
1681 01:24:29.856100
1682 01:24:29.856167
1683 01:24:29.856230 TX Vref Scan disable
1684 01:24:29.859822 == TX Byte 0 ==
1685 01:24:29.862622 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1686 01:24:29.870038 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1687 01:24:29.870127 == TX Byte 1 ==
1688 01:24:29.873049 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1689 01:24:29.880094 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1690 01:24:29.880269
1691 01:24:29.880355 [DATLAT]
1692 01:24:29.880433 Freq=800, CH1 RK0
1693 01:24:29.880507
1694 01:24:29.882852 DATLAT Default: 0xa
1695 01:24:29.883026 0, 0xFFFF, sum = 0
1696 01:24:29.886052 1, 0xFFFF, sum = 0
1697 01:24:29.889494 2, 0xFFFF, sum = 0
1698 01:24:29.889699 3, 0xFFFF, sum = 0
1699 01:24:29.892678 4, 0xFFFF, sum = 0
1700 01:24:29.892842 5, 0xFFFF, sum = 0
1701 01:24:29.896024 6, 0xFFFF, sum = 0
1702 01:24:29.896256 7, 0xFFFF, sum = 0
1703 01:24:29.899094 8, 0xFFFF, sum = 0
1704 01:24:29.899315 9, 0x0, sum = 1
1705 01:24:29.902902 10, 0x0, sum = 2
1706 01:24:29.903141 11, 0x0, sum = 3
1707 01:24:29.905980 12, 0x0, sum = 4
1708 01:24:29.906227 best_step = 10
1709 01:24:29.906413
1710 01:24:29.906581 ==
1711 01:24:29.909355 Dram Type= 6, Freq= 0, CH_1, rank 0
1712 01:24:29.912916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1713 01:24:29.913192 ==
1714 01:24:29.916244 RX Vref Scan: 1
1715 01:24:29.916565
1716 01:24:29.919288 Set Vref Range= 32 -> 127
1717 01:24:29.919572
1718 01:24:29.919912 RX Vref 32 -> 127, step: 1
1719 01:24:29.920153
1720 01:24:29.922369 RX Delay -95 -> 252, step: 8
1721 01:24:29.922640
1722 01:24:29.926459 Set Vref, RX VrefLevel [Byte0]: 32
1723 01:24:29.929265 [Byte1]: 32
1724 01:24:29.932804
1725 01:24:29.933395 Set Vref, RX VrefLevel [Byte0]: 33
1726 01:24:29.936157 [Byte1]: 33
1727 01:24:29.940793
1728 01:24:29.941392 Set Vref, RX VrefLevel [Byte0]: 34
1729 01:24:29.943962 [Byte1]: 34
1730 01:24:29.947741
1731 01:24:29.948200 Set Vref, RX VrefLevel [Byte0]: 35
1732 01:24:29.951598 [Byte1]: 35
1733 01:24:29.955783
1734 01:24:29.956238 Set Vref, RX VrefLevel [Byte0]: 36
1735 01:24:29.959211 [Byte1]: 36
1736 01:24:29.963180
1737 01:24:29.963654 Set Vref, RX VrefLevel [Byte0]: 37
1738 01:24:29.966221 [Byte1]: 37
1739 01:24:29.970890
1740 01:24:29.971436 Set Vref, RX VrefLevel [Byte0]: 38
1741 01:24:29.974235 [Byte1]: 38
1742 01:24:29.978368
1743 01:24:29.978918 Set Vref, RX VrefLevel [Byte0]: 39
1744 01:24:29.982296 [Byte1]: 39
1745 01:24:29.986080
1746 01:24:29.986675 Set Vref, RX VrefLevel [Byte0]: 40
1747 01:24:29.989584 [Byte1]: 40
1748 01:24:29.993680
1749 01:24:29.994130 Set Vref, RX VrefLevel [Byte0]: 41
1750 01:24:29.997130 [Byte1]: 41
1751 01:24:30.001057
1752 01:24:30.001545 Set Vref, RX VrefLevel [Byte0]: 42
1753 01:24:30.004628 [Byte1]: 42
1754 01:24:30.008912
1755 01:24:30.009505 Set Vref, RX VrefLevel [Byte0]: 43
1756 01:24:30.012423 [Byte1]: 43
1757 01:24:30.016833
1758 01:24:30.017435 Set Vref, RX VrefLevel [Byte0]: 44
1759 01:24:30.019979 [Byte1]: 44
1760 01:24:30.024244
1761 01:24:30.024794 Set Vref, RX VrefLevel [Byte0]: 45
1762 01:24:30.027211 [Byte1]: 45
1763 01:24:30.031489
1764 01:24:30.031936 Set Vref, RX VrefLevel [Byte0]: 46
1765 01:24:30.035126 [Byte1]: 46
1766 01:24:30.039259
1767 01:24:30.039711 Set Vref, RX VrefLevel [Byte0]: 47
1768 01:24:30.043188 [Byte1]: 47
1769 01:24:30.046885
1770 01:24:30.047335 Set Vref, RX VrefLevel [Byte0]: 48
1771 01:24:30.049707 [Byte1]: 48
1772 01:24:30.054353
1773 01:24:30.054948 Set Vref, RX VrefLevel [Byte0]: 49
1774 01:24:30.057872 [Byte1]: 49
1775 01:24:30.062399
1776 01:24:30.062949 Set Vref, RX VrefLevel [Byte0]: 50
1777 01:24:30.065438 [Byte1]: 50
1778 01:24:30.069972
1779 01:24:30.070519 Set Vref, RX VrefLevel [Byte0]: 51
1780 01:24:30.073286 [Byte1]: 51
1781 01:24:30.077494
1782 01:24:30.077948 Set Vref, RX VrefLevel [Byte0]: 52
1783 01:24:30.080830 [Byte1]: 52
1784 01:24:30.085049
1785 01:24:30.085644 Set Vref, RX VrefLevel [Byte0]: 53
1786 01:24:30.087902 [Byte1]: 53
1787 01:24:30.092475
1788 01:24:30.093026 Set Vref, RX VrefLevel [Byte0]: 54
1789 01:24:30.096056 [Byte1]: 54
1790 01:24:30.100079
1791 01:24:30.100530 Set Vref, RX VrefLevel [Byte0]: 55
1792 01:24:30.103473 [Byte1]: 55
1793 01:24:30.107928
1794 01:24:30.108501 Set Vref, RX VrefLevel [Byte0]: 56
1795 01:24:30.110735 [Byte1]: 56
1796 01:24:30.115208
1797 01:24:30.115759 Set Vref, RX VrefLevel [Byte0]: 57
1798 01:24:30.118728 [Byte1]: 57
1799 01:24:30.122896
1800 01:24:30.123450 Set Vref, RX VrefLevel [Byte0]: 58
1801 01:24:30.125886 [Byte1]: 58
1802 01:24:30.130496
1803 01:24:30.131085 Set Vref, RX VrefLevel [Byte0]: 59
1804 01:24:30.134021 [Byte1]: 59
1805 01:24:30.138097
1806 01:24:30.138544 Set Vref, RX VrefLevel [Byte0]: 60
1807 01:24:30.141137 [Byte1]: 60
1808 01:24:30.145798
1809 01:24:30.146347 Set Vref, RX VrefLevel [Byte0]: 61
1810 01:24:30.149320 [Byte1]: 61
1811 01:24:30.153197
1812 01:24:30.153846 Set Vref, RX VrefLevel [Byte0]: 62
1813 01:24:30.156507 [Byte1]: 62
1814 01:24:30.161044
1815 01:24:30.161635 Set Vref, RX VrefLevel [Byte0]: 63
1816 01:24:30.164096 [Byte1]: 63
1817 01:24:30.168731
1818 01:24:30.169275 Set Vref, RX VrefLevel [Byte0]: 64
1819 01:24:30.171900 [Byte1]: 64
1820 01:24:30.175948
1821 01:24:30.176493 Set Vref, RX VrefLevel [Byte0]: 65
1822 01:24:30.179095 [Byte1]: 65
1823 01:24:30.183613
1824 01:24:30.184177 Set Vref, RX VrefLevel [Byte0]: 66
1825 01:24:30.186797 [Byte1]: 66
1826 01:24:30.191349
1827 01:24:30.191802 Set Vref, RX VrefLevel [Byte0]: 67
1828 01:24:30.194270 [Byte1]: 67
1829 01:24:30.198978
1830 01:24:30.199527 Set Vref, RX VrefLevel [Byte0]: 68
1831 01:24:30.201716 [Byte1]: 68
1832 01:24:30.206519
1833 01:24:30.207065 Set Vref, RX VrefLevel [Byte0]: 69
1834 01:24:30.209378 [Byte1]: 69
1835 01:24:30.214034
1836 01:24:30.214583 Set Vref, RX VrefLevel [Byte0]: 70
1837 01:24:30.217516 [Byte1]: 70
1838 01:24:30.221431
1839 01:24:30.221881 Set Vref, RX VrefLevel [Byte0]: 71
1840 01:24:30.224820 [Byte1]: 71
1841 01:24:30.229322
1842 01:24:30.229921 Set Vref, RX VrefLevel [Byte0]: 72
1843 01:24:30.232761 [Byte1]: 72
1844 01:24:30.236914
1845 01:24:30.237505 Set Vref, RX VrefLevel [Byte0]: 73
1846 01:24:30.239877 [Byte1]: 73
1847 01:24:30.244640
1848 01:24:30.245229 Set Vref, RX VrefLevel [Byte0]: 74
1849 01:24:30.247772 [Byte1]: 74
1850 01:24:30.251978
1851 01:24:30.252554 Set Vref, RX VrefLevel [Byte0]: 75
1852 01:24:30.255351 [Byte1]: 75
1853 01:24:30.259530
1854 01:24:30.260083 Set Vref, RX VrefLevel [Byte0]: 76
1855 01:24:30.263177 [Byte1]: 76
1856 01:24:30.267219
1857 01:24:30.267697 Set Vref, RX VrefLevel [Byte0]: 77
1858 01:24:30.270300 [Byte1]: 77
1859 01:24:30.274519
1860 01:24:30.275088 Final RX Vref Byte 0 = 63 to rank0
1861 01:24:30.278207 Final RX Vref Byte 1 = 65 to rank0
1862 01:24:30.281385 Final RX Vref Byte 0 = 63 to rank1
1863 01:24:30.285179 Final RX Vref Byte 1 = 65 to rank1==
1864 01:24:30.287957 Dram Type= 6, Freq= 0, CH_1, rank 0
1865 01:24:30.294178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1866 01:24:30.294636 ==
1867 01:24:30.294996 DQS Delay:
1868 01:24:30.297585 DQS0 = 0, DQS1 = 0
1869 01:24:30.298144 DQM Delay:
1870 01:24:30.298587 DQM0 = 86, DQM1 = 78
1871 01:24:30.300719 DQ Delay:
1872 01:24:30.304188 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
1873 01:24:30.307708 DQ4 =80, DQ5 =100, DQ6 =96, DQ7 =80
1874 01:24:30.310633 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
1875 01:24:30.316657 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
1876 01:24:30.317310
1877 01:24:30.317742
1878 01:24:30.321023 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b17, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
1879 01:24:30.323877 CH1 RK0: MR19=606, MR18=2B17
1880 01:24:30.330585 CH1_RK0: MR19=0x606, MR18=0x2B17, DQSOSC=398, MR23=63, INC=93, DEC=62
1881 01:24:30.331160
1882 01:24:30.334218 ----->DramcWriteLeveling(PI) begin...
1883 01:24:30.334774 ==
1884 01:24:30.337490 Dram Type= 6, Freq= 0, CH_1, rank 1
1885 01:24:30.340901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1886 01:24:30.341403 ==
1887 01:24:30.344468 Write leveling (Byte 0): 28 => 28
1888 01:24:30.347479 Write leveling (Byte 1): 29 => 29
1889 01:24:30.350686 DramcWriteLeveling(PI) end<-----
1890 01:24:30.351135
1891 01:24:30.351490 ==
1892 01:24:30.353953 Dram Type= 6, Freq= 0, CH_1, rank 1
1893 01:24:30.357621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1894 01:24:30.358110 ==
1895 01:24:30.360910 [Gating] SW mode calibration
1896 01:24:30.367308 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1897 01:24:30.374282 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1898 01:24:30.377233 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1899 01:24:30.383881 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1900 01:24:30.387073 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 01:24:30.390509 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 01:24:30.397322 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 01:24:30.400291 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 01:24:30.403688 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 01:24:30.410110 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 01:24:30.413536 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 01:24:30.416866 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 01:24:30.423927 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 01:24:30.426679 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 01:24:30.429911 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 01:24:30.436638 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 01:24:30.440237 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 01:24:30.443040 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 01:24:30.449662 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 01:24:30.453407 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1916 01:24:30.456128 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1917 01:24:30.463181 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 01:24:30.466625 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 01:24:30.469360 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 01:24:30.475782 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 01:24:30.479360 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 01:24:30.482956 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 01:24:30.489014 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 01:24:30.492195 0 9 8 | B1->B0 | 3333 2828 | 1 1 | (0 0) (0 0)
1925 01:24:30.495605 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1926 01:24:30.502295 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1927 01:24:30.505642 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1928 01:24:30.508957 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1929 01:24:30.515410 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1930 01:24:30.519306 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1931 01:24:30.522099 0 10 4 | B1->B0 | 3131 3434 | 0 1 | (0 1) (1 0)
1932 01:24:30.528687 0 10 8 | B1->B0 | 2626 2e2e | 0 1 | (1 0) (1 0)
1933 01:24:30.531821 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1934 01:24:30.535674 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1935 01:24:30.541872 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1936 01:24:30.545560 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1937 01:24:30.548568 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1938 01:24:30.555160 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1939 01:24:30.558541 0 11 4 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1940 01:24:30.561974 0 11 8 | B1->B0 | 4343 3838 | 0 0 | (1 1) (0 0)
1941 01:24:30.568357 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1942 01:24:30.571952 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1943 01:24:30.575741 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1944 01:24:30.581871 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1945 01:24:30.585434 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1946 01:24:30.588714 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1947 01:24:30.595049 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1948 01:24:30.598518 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1949 01:24:30.601466 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 01:24:30.605125 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 01:24:30.611594 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 01:24:30.615038 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 01:24:30.618072 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1954 01:24:30.625023 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1955 01:24:30.628504 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1956 01:24:30.631820 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1957 01:24:30.638352 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1958 01:24:30.641558 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1959 01:24:30.645051 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1960 01:24:30.651461 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1961 01:24:30.654958 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1962 01:24:30.658186 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1963 01:24:30.664629 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1964 01:24:30.667826 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1965 01:24:30.671155 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1966 01:24:30.674708 Total UI for P1: 0, mck2ui 16
1967 01:24:30.677941 best dqsien dly found for B0: ( 0, 14, 6)
1968 01:24:30.681273 Total UI for P1: 0, mck2ui 16
1969 01:24:30.684682 best dqsien dly found for B1: ( 0, 14, 8)
1970 01:24:30.687983 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1971 01:24:30.691301 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1972 01:24:30.691841
1973 01:24:30.697925 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1974 01:24:30.700846 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1975 01:24:30.704187 [Gating] SW calibration Done
1976 01:24:30.704732 ==
1977 01:24:30.707652 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 01:24:30.710636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 01:24:30.711093 ==
1980 01:24:30.711452 RX Vref Scan: 0
1981 01:24:30.711788
1982 01:24:30.714091 RX Vref 0 -> 0, step: 1
1983 01:24:30.714540
1984 01:24:30.717146 RX Delay -130 -> 252, step: 16
1985 01:24:30.720630 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1986 01:24:30.723729 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1987 01:24:30.730650 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1988 01:24:30.734049 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1989 01:24:30.737168 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1990 01:24:30.740867 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1991 01:24:30.744169 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1992 01:24:30.750928 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1993 01:24:30.754378 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1994 01:24:30.757571 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1995 01:24:30.761068 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1996 01:24:30.763864 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1997 01:24:30.770689 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1998 01:24:30.774037 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1999 01:24:30.777722 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
2000 01:24:30.780840 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
2001 01:24:30.781460 ==
2002 01:24:30.784041 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 01:24:30.791131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 01:24:30.791680 ==
2005 01:24:30.792043 DQS Delay:
2006 01:24:30.793868 DQS0 = 0, DQS1 = 0
2007 01:24:30.794318 DQM Delay:
2008 01:24:30.794679 DQM0 = 87, DQM1 = 79
2009 01:24:30.797245 DQ Delay:
2010 01:24:30.800805 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
2011 01:24:30.804241 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2012 01:24:30.807226 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
2013 01:24:30.810261 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2014 01:24:30.810718
2015 01:24:30.811076
2016 01:24:30.811406 ==
2017 01:24:30.813311 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 01:24:30.816778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 01:24:30.817363 ==
2020 01:24:30.817739
2021 01:24:30.818068
2022 01:24:30.820507 TX Vref Scan disable
2023 01:24:30.823701 == TX Byte 0 ==
2024 01:24:30.826523 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2025 01:24:30.830200 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2026 01:24:30.833082 == TX Byte 1 ==
2027 01:24:30.836865 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2028 01:24:30.839783 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2029 01:24:30.840248 ==
2030 01:24:30.843811 Dram Type= 6, Freq= 0, CH_1, rank 1
2031 01:24:30.846610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2032 01:24:30.850064 ==
2033 01:24:30.861777 TX Vref=22, minBit 15, minWin=26, winSum=442
2034 01:24:30.864874 TX Vref=24, minBit 1, minWin=27, winSum=447
2035 01:24:30.868028 TX Vref=26, minBit 8, minWin=27, winSum=451
2036 01:24:30.871415 TX Vref=28, minBit 8, minWin=27, winSum=450
2037 01:24:30.874404 TX Vref=30, minBit 8, minWin=27, winSum=449
2038 01:24:30.881410 TX Vref=32, minBit 8, minWin=27, winSum=449
2039 01:24:30.884244 [TxChooseVref] Worse bit 8, Min win 27, Win sum 451, Final Vref 26
2040 01:24:30.884795
2041 01:24:30.887428 Final TX Range 1 Vref 26
2042 01:24:30.887979
2043 01:24:30.888344 ==
2044 01:24:30.890901 Dram Type= 6, Freq= 0, CH_1, rank 1
2045 01:24:30.897549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2046 01:24:30.898097 ==
2047 01:24:30.898466
2048 01:24:30.898803
2049 01:24:30.899124 TX Vref Scan disable
2050 01:24:30.901191 == TX Byte 0 ==
2051 01:24:30.905158 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2052 01:24:30.911144 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2053 01:24:30.911684 == TX Byte 1 ==
2054 01:24:30.914384 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2055 01:24:30.921045 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2056 01:24:30.921625
2057 01:24:30.921995 [DATLAT]
2058 01:24:30.922337 Freq=800, CH1 RK1
2059 01:24:30.922770
2060 01:24:30.924626 DATLAT Default: 0xa
2061 01:24:30.925177 0, 0xFFFF, sum = 0
2062 01:24:30.928180 1, 0xFFFF, sum = 0
2063 01:24:30.930771 2, 0xFFFF, sum = 0
2064 01:24:30.931233 3, 0xFFFF, sum = 0
2065 01:24:30.934024 4, 0xFFFF, sum = 0
2066 01:24:30.934490 5, 0xFFFF, sum = 0
2067 01:24:30.937515 6, 0xFFFF, sum = 0
2068 01:24:30.937978 7, 0xFFFF, sum = 0
2069 01:24:30.941116 8, 0xFFFF, sum = 0
2070 01:24:30.941727 9, 0x0, sum = 1
2071 01:24:30.944214 10, 0x0, sum = 2
2072 01:24:30.944782 11, 0x0, sum = 3
2073 01:24:30.945158 12, 0x0, sum = 4
2074 01:24:30.947500 best_step = 10
2075 01:24:30.947966
2076 01:24:30.948327 ==
2077 01:24:30.951036 Dram Type= 6, Freq= 0, CH_1, rank 1
2078 01:24:30.954816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2079 01:24:30.955402 ==
2080 01:24:30.957575 RX Vref Scan: 0
2081 01:24:30.958192
2082 01:24:30.960620 RX Vref 0 -> 0, step: 1
2083 01:24:30.961073
2084 01:24:30.961482 RX Delay -95 -> 252, step: 8
2085 01:24:30.968112 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2086 01:24:30.971459 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2087 01:24:30.974710 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2088 01:24:30.977999 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
2089 01:24:30.984411 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2090 01:24:30.987911 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2091 01:24:30.990944 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2092 01:24:30.994552 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2093 01:24:30.997509 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2094 01:24:31.004583 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2095 01:24:31.007776 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2096 01:24:31.010904 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
2097 01:24:31.014191 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2098 01:24:31.017644 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2099 01:24:31.023808 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2100 01:24:31.027432 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2101 01:24:31.027980 ==
2102 01:24:31.030297 Dram Type= 6, Freq= 0, CH_1, rank 1
2103 01:24:31.033707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2104 01:24:31.034166 ==
2105 01:24:31.037433 DQS Delay:
2106 01:24:31.037992 DQS0 = 0, DQS1 = 0
2107 01:24:31.040414 DQM Delay:
2108 01:24:31.040867 DQM0 = 87, DQM1 = 79
2109 01:24:31.041231 DQ Delay:
2110 01:24:31.043474 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2111 01:24:31.047209 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2112 01:24:31.050415 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =72
2113 01:24:31.054027 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2114 01:24:31.054579
2115 01:24:31.054945
2116 01:24:31.063830 [DQSOSCAuto] RK1, (LSB)MR18= 0x170f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
2117 01:24:31.067032 CH1 RK1: MR19=606, MR18=170F
2118 01:24:31.070512 CH1_RK1: MR19=0x606, MR18=0x170F, DQSOSC=404, MR23=63, INC=90, DEC=60
2119 01:24:31.073469 [RxdqsGatingPostProcess] freq 800
2120 01:24:31.080689 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2121 01:24:31.083823 Pre-setting of DQS Precalculation
2122 01:24:31.087202 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2123 01:24:31.096564 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2124 01:24:31.103464 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2125 01:24:31.104021
2126 01:24:31.104386
2127 01:24:31.106779 [Calibration Summary] 1600 Mbps
2128 01:24:31.107326 CH 0, Rank 0
2129 01:24:31.110479 SW Impedance : PASS
2130 01:24:31.110949 DUTY Scan : NO K
2131 01:24:31.113207 ZQ Calibration : PASS
2132 01:24:31.116376 Jitter Meter : NO K
2133 01:24:31.116830 CBT Training : PASS
2134 01:24:31.120015 Write leveling : PASS
2135 01:24:31.123618 RX DQS gating : PASS
2136 01:24:31.124071 RX DQ/DQS(RDDQC) : PASS
2137 01:24:31.126872 TX DQ/DQS : PASS
2138 01:24:31.130066 RX DATLAT : PASS
2139 01:24:31.130525 RX DQ/DQS(Engine): PASS
2140 01:24:31.133178 TX OE : NO K
2141 01:24:31.133659 All Pass.
2142 01:24:31.134022
2143 01:24:31.137181 CH 0, Rank 1
2144 01:24:31.137783 SW Impedance : PASS
2145 01:24:31.139955 DUTY Scan : NO K
2146 01:24:31.143296 ZQ Calibration : PASS
2147 01:24:31.143847 Jitter Meter : NO K
2148 01:24:31.146961 CBT Training : PASS
2149 01:24:31.149938 Write leveling : PASS
2150 01:24:31.150411 RX DQS gating : PASS
2151 01:24:31.153274 RX DQ/DQS(RDDQC) : PASS
2152 01:24:31.153872 TX DQ/DQS : PASS
2153 01:24:31.156475 RX DATLAT : PASS
2154 01:24:31.160041 RX DQ/DQS(Engine): PASS
2155 01:24:31.160604 TX OE : NO K
2156 01:24:31.162958 All Pass.
2157 01:24:31.163413
2158 01:24:31.163773 CH 1, Rank 0
2159 01:24:31.166247 SW Impedance : PASS
2160 01:24:31.166704 DUTY Scan : NO K
2161 01:24:31.169450 ZQ Calibration : PASS
2162 01:24:31.173062 Jitter Meter : NO K
2163 01:24:31.173665 CBT Training : PASS
2164 01:24:31.176592 Write leveling : PASS
2165 01:24:31.179843 RX DQS gating : PASS
2166 01:24:31.180394 RX DQ/DQS(RDDQC) : PASS
2167 01:24:31.183173 TX DQ/DQS : PASS
2168 01:24:31.186725 RX DATLAT : PASS
2169 01:24:31.187275 RX DQ/DQS(Engine): PASS
2170 01:24:31.189519 TX OE : NO K
2171 01:24:31.189976 All Pass.
2172 01:24:31.190338
2173 01:24:31.192622 CH 1, Rank 1
2174 01:24:31.193082 SW Impedance : PASS
2175 01:24:31.196573 DUTY Scan : NO K
2176 01:24:31.199170 ZQ Calibration : PASS
2177 01:24:31.199626 Jitter Meter : NO K
2178 01:24:31.203216 CBT Training : PASS
2179 01:24:31.206018 Write leveling : PASS
2180 01:24:31.206472 RX DQS gating : PASS
2181 01:24:31.209547 RX DQ/DQS(RDDQC) : PASS
2182 01:24:31.210005 TX DQ/DQS : PASS
2183 01:24:31.212820 RX DATLAT : PASS
2184 01:24:31.216356 RX DQ/DQS(Engine): PASS
2185 01:24:31.216875 TX OE : NO K
2186 01:24:31.219471 All Pass.
2187 01:24:31.220016
2188 01:24:31.220374 DramC Write-DBI off
2189 01:24:31.223030 PER_BANK_REFRESH: Hybrid Mode
2190 01:24:31.226015 TX_TRACKING: ON
2191 01:24:31.229679 [GetDramInforAfterCalByMRR] Vendor 6.
2192 01:24:31.232523 [GetDramInforAfterCalByMRR] Revision 606.
2193 01:24:31.235917 [GetDramInforAfterCalByMRR] Revision 2 0.
2194 01:24:31.236467 MR0 0x3b3b
2195 01:24:31.236834 MR8 0x5151
2196 01:24:31.242381 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2197 01:24:31.242940
2198 01:24:31.243306 MR0 0x3b3b
2199 01:24:31.243642 MR8 0x5151
2200 01:24:31.245991 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2201 01:24:31.246542
2202 01:24:31.255978 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2203 01:24:31.259015 [FAST_K] Save calibration result to emmc
2204 01:24:31.262535 [FAST_K] Save calibration result to emmc
2205 01:24:31.266275 dram_init: config_dvfs: 1
2206 01:24:31.268863 dramc_set_vcore_voltage set vcore to 662500
2207 01:24:31.272414 Read voltage for 1200, 2
2208 01:24:31.272964 Vio18 = 0
2209 01:24:31.276066 Vcore = 662500
2210 01:24:31.276621 Vdram = 0
2211 01:24:31.276988 Vddq = 0
2212 01:24:31.277323 Vmddr = 0
2213 01:24:31.282517 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2214 01:24:31.285494 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2215 01:24:31.289019 MEM_TYPE=3, freq_sel=15
2216 01:24:31.292436 sv_algorithm_assistance_LP4_1600
2217 01:24:31.295632 ============ PULL DRAM RESETB DOWN ============
2218 01:24:31.302064 ========== PULL DRAM RESETB DOWN end =========
2219 01:24:31.306001 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2220 01:24:31.309601 ===================================
2221 01:24:31.312145 LPDDR4 DRAM CONFIGURATION
2222 01:24:31.315995 ===================================
2223 01:24:31.316547 EX_ROW_EN[0] = 0x0
2224 01:24:31.319497 EX_ROW_EN[1] = 0x0
2225 01:24:31.320044 LP4Y_EN = 0x0
2226 01:24:31.322773 WORK_FSP = 0x0
2227 01:24:31.323322 WL = 0x4
2228 01:24:31.325663 RL = 0x4
2229 01:24:31.326114 BL = 0x2
2230 01:24:31.329173 RPST = 0x0
2231 01:24:31.329912 RD_PRE = 0x0
2232 01:24:31.332284 WR_PRE = 0x1
2233 01:24:31.332750 WR_PST = 0x0
2234 01:24:31.335523 DBI_WR = 0x0
2235 01:24:31.338781 DBI_RD = 0x0
2236 01:24:31.339230 OTF = 0x1
2237 01:24:31.342505 ===================================
2238 01:24:31.345852 ===================================
2239 01:24:31.346403 ANA top config
2240 01:24:31.348900 ===================================
2241 01:24:31.352133 DLL_ASYNC_EN = 0
2242 01:24:31.355853 ALL_SLAVE_EN = 0
2243 01:24:31.358653 NEW_RANK_MODE = 1
2244 01:24:31.362272 DLL_IDLE_MODE = 1
2245 01:24:31.362724 LP45_APHY_COMB_EN = 1
2246 01:24:31.365408 TX_ODT_DIS = 1
2247 01:24:31.368941 NEW_8X_MODE = 1
2248 01:24:31.372170 ===================================
2249 01:24:31.375805 ===================================
2250 01:24:31.379083 data_rate = 2400
2251 01:24:31.382035 CKR = 1
2252 01:24:31.382489 DQ_P2S_RATIO = 8
2253 01:24:31.385521 ===================================
2254 01:24:31.388969 CA_P2S_RATIO = 8
2255 01:24:31.391987 DQ_CA_OPEN = 0
2256 01:24:31.395350 DQ_SEMI_OPEN = 0
2257 01:24:31.399214 CA_SEMI_OPEN = 0
2258 01:24:31.402222 CA_FULL_RATE = 0
2259 01:24:31.402680 DQ_CKDIV4_EN = 0
2260 01:24:31.405115 CA_CKDIV4_EN = 0
2261 01:24:31.408871 CA_PREDIV_EN = 0
2262 01:24:31.411675 PH8_DLY = 17
2263 01:24:31.415390 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2264 01:24:31.418587 DQ_AAMCK_DIV = 4
2265 01:24:31.419132 CA_AAMCK_DIV = 4
2266 01:24:31.421796 CA_ADMCK_DIV = 4
2267 01:24:31.425485 DQ_TRACK_CA_EN = 0
2268 01:24:31.428508 CA_PICK = 1200
2269 01:24:31.431969 CA_MCKIO = 1200
2270 01:24:31.435376 MCKIO_SEMI = 0
2271 01:24:31.438419 PLL_FREQ = 2366
2272 01:24:31.438991 DQ_UI_PI_RATIO = 32
2273 01:24:31.441479 CA_UI_PI_RATIO = 0
2274 01:24:31.445287 ===================================
2275 01:24:31.448606 ===================================
2276 01:24:31.451601 memory_type:LPDDR4
2277 01:24:31.455452 GP_NUM : 10
2278 01:24:31.456002 SRAM_EN : 1
2279 01:24:31.458524 MD32_EN : 0
2280 01:24:31.461618 ===================================
2281 01:24:31.465065 [ANA_INIT] >>>>>>>>>>>>>>
2282 01:24:31.467989 <<<<<< [CONFIGURE PHASE]: ANA_TX
2283 01:24:31.471777 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2284 01:24:31.474887 ===================================
2285 01:24:31.475441 data_rate = 2400,PCW = 0X5b00
2286 01:24:31.478097 ===================================
2287 01:24:31.481361 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2288 01:24:31.487991 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2289 01:24:31.494900 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2290 01:24:31.497664 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2291 01:24:31.501271 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2292 01:24:31.504326 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2293 01:24:31.508106 [ANA_INIT] flow start
2294 01:24:31.508657 [ANA_INIT] PLL >>>>>>>>
2295 01:24:31.510845 [ANA_INIT] PLL <<<<<<<<
2296 01:24:31.514115 [ANA_INIT] MIDPI >>>>>>>>
2297 01:24:31.517985 [ANA_INIT] MIDPI <<<<<<<<
2298 01:24:31.518578 [ANA_INIT] DLL >>>>>>>>
2299 01:24:31.521318 [ANA_INIT] DLL <<<<<<<<
2300 01:24:31.524557 [ANA_INIT] flow end
2301 01:24:31.527355 ============ LP4 DIFF to SE enter ============
2302 01:24:31.531158 ============ LP4 DIFF to SE exit ============
2303 01:24:31.534360 [ANA_INIT] <<<<<<<<<<<<<
2304 01:24:31.537941 [Flow] Enable top DCM control >>>>>
2305 01:24:31.541137 [Flow] Enable top DCM control <<<<<
2306 01:24:31.543754 Enable DLL master slave shuffle
2307 01:24:31.547037 ==============================================================
2308 01:24:31.550614 Gating Mode config
2309 01:24:31.557036 ==============================================================
2310 01:24:31.557770 Config description:
2311 01:24:31.567509 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2312 01:24:31.573711 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2313 01:24:31.577076 SELPH_MODE 0: By rank 1: By Phase
2314 01:24:31.583781 ==============================================================
2315 01:24:31.586803 GAT_TRACK_EN = 1
2316 01:24:31.590091 RX_GATING_MODE = 2
2317 01:24:31.593528 RX_GATING_TRACK_MODE = 2
2318 01:24:31.597316 SELPH_MODE = 1
2319 01:24:31.600283 PICG_EARLY_EN = 1
2320 01:24:31.603396 VALID_LAT_VALUE = 1
2321 01:24:31.607189 ==============================================================
2322 01:24:31.610160 Enter into Gating configuration >>>>
2323 01:24:31.613353 Exit from Gating configuration <<<<
2324 01:24:31.616674 Enter into DVFS_PRE_config >>>>>
2325 01:24:31.629986 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2326 01:24:31.633065 Exit from DVFS_PRE_config <<<<<
2327 01:24:31.633794 Enter into PICG configuration >>>>
2328 01:24:31.636445 Exit from PICG configuration <<<<
2329 01:24:31.639400 [RX_INPUT] configuration >>>>>
2330 01:24:31.643472 [RX_INPUT] configuration <<<<<
2331 01:24:31.649647 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2332 01:24:31.653681 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2333 01:24:31.659597 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2334 01:24:31.666726 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2335 01:24:31.672689 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2336 01:24:31.679086 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2337 01:24:31.682917 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2338 01:24:31.686321 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2339 01:24:31.692396 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2340 01:24:31.695728 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2341 01:24:31.699202 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2342 01:24:31.702895 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2343 01:24:31.705703 ===================================
2344 01:24:31.709099 LPDDR4 DRAM CONFIGURATION
2345 01:24:31.712169 ===================================
2346 01:24:31.715273 EX_ROW_EN[0] = 0x0
2347 01:24:31.715731 EX_ROW_EN[1] = 0x0
2348 01:24:31.719278 LP4Y_EN = 0x0
2349 01:24:31.719733 WORK_FSP = 0x0
2350 01:24:31.722150 WL = 0x4
2351 01:24:31.722604 RL = 0x4
2352 01:24:31.725692 BL = 0x2
2353 01:24:31.726152 RPST = 0x0
2354 01:24:31.729555 RD_PRE = 0x0
2355 01:24:31.730068 WR_PRE = 0x1
2356 01:24:31.732573 WR_PST = 0x0
2357 01:24:31.733238 DBI_WR = 0x0
2358 01:24:31.735648 DBI_RD = 0x0
2359 01:24:31.738690 OTF = 0x1
2360 01:24:31.742229 ===================================
2361 01:24:31.745699 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2362 01:24:31.749052 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2363 01:24:31.752093 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2364 01:24:31.755159 ===================================
2365 01:24:31.758607 LPDDR4 DRAM CONFIGURATION
2366 01:24:31.761894 ===================================
2367 01:24:31.765315 EX_ROW_EN[0] = 0x10
2368 01:24:31.765761 EX_ROW_EN[1] = 0x0
2369 01:24:31.768728 LP4Y_EN = 0x0
2370 01:24:31.769022 WORK_FSP = 0x0
2371 01:24:31.771755 WL = 0x4
2372 01:24:31.772050 RL = 0x4
2373 01:24:31.775553 BL = 0x2
2374 01:24:31.775943 RPST = 0x0
2375 01:24:31.778466 RD_PRE = 0x0
2376 01:24:31.778872 WR_PRE = 0x1
2377 01:24:31.781809 WR_PST = 0x0
2378 01:24:31.782202 DBI_WR = 0x0
2379 01:24:31.785001 DBI_RD = 0x0
2380 01:24:31.788442 OTF = 0x1
2381 01:24:31.791990 ===================================
2382 01:24:31.794872 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2383 01:24:31.798230 ==
2384 01:24:31.798528 Dram Type= 6, Freq= 0, CH_0, rank 0
2385 01:24:31.804819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2386 01:24:31.805117 ==
2387 01:24:31.808193 [Duty_Offset_Calibration]
2388 01:24:31.808584 B0:1 B1:-1 CA:0
2389 01:24:31.808825
2390 01:24:31.811393 [DutyScan_Calibration_Flow] k_type=0
2391 01:24:31.822245
2392 01:24:31.822734 ==CLK 0==
2393 01:24:31.824350 Final CLK duty delay cell = 0
2394 01:24:31.827879 [0] MAX Duty = 5094%(X100), DQS PI = 16
2395 01:24:31.831653 [0] MIN Duty = 4875%(X100), DQS PI = 8
2396 01:24:31.832226 [0] AVG Duty = 4984%(X100)
2397 01:24:31.834292
2398 01:24:31.837644 CH0 CLK Duty spec in!! Max-Min= 219%
2399 01:24:31.840809 [DutyScan_Calibration_Flow] ====Done====
2400 01:24:31.841265
2401 01:24:31.844001 [DutyScan_Calibration_Flow] k_type=1
2402 01:24:31.859495
2403 01:24:31.860055 ==DQS 0 ==
2404 01:24:31.862657 Final DQS duty delay cell = -4
2405 01:24:31.866029 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2406 01:24:31.869292 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2407 01:24:31.873000 [-4] AVG Duty = 4968%(X100)
2408 01:24:31.873602
2409 01:24:31.873967 ==DQS 1 ==
2410 01:24:31.876001 Final DQS duty delay cell = 0
2411 01:24:31.879414 [0] MAX Duty = 5124%(X100), DQS PI = 6
2412 01:24:31.882714 [0] MIN Duty = 5000%(X100), DQS PI = 22
2413 01:24:31.885548 [0] AVG Duty = 5062%(X100)
2414 01:24:31.886011
2415 01:24:31.889074 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2416 01:24:31.889670
2417 01:24:31.892380 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2418 01:24:31.895608 [DutyScan_Calibration_Flow] ====Done====
2419 01:24:31.896233
2420 01:24:31.898824 [DutyScan_Calibration_Flow] k_type=3
2421 01:24:31.917227
2422 01:24:31.917833 ==DQM 0 ==
2423 01:24:31.921071 Final DQM duty delay cell = 0
2424 01:24:31.923512 [0] MAX Duty = 5062%(X100), DQS PI = 24
2425 01:24:31.927036 [0] MIN Duty = 4875%(X100), DQS PI = 8
2426 01:24:31.930380 [0] AVG Duty = 4968%(X100)
2427 01:24:31.930952
2428 01:24:31.931320 ==DQM 1 ==
2429 01:24:31.933313 Final DQM duty delay cell = 4
2430 01:24:31.937228 [4] MAX Duty = 5187%(X100), DQS PI = 32
2431 01:24:31.940453 [4] MIN Duty = 5000%(X100), DQS PI = 22
2432 01:24:31.943621 [4] AVG Duty = 5093%(X100)
2433 01:24:31.944177
2434 01:24:31.947037 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2435 01:24:31.947495
2436 01:24:31.950421 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2437 01:24:31.953520 [DutyScan_Calibration_Flow] ====Done====
2438 01:24:31.954073
2439 01:24:31.957030 [DutyScan_Calibration_Flow] k_type=2
2440 01:24:31.972107
2441 01:24:31.972659 ==DQ 0 ==
2442 01:24:31.975257 Final DQ duty delay cell = -4
2443 01:24:31.978428 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2444 01:24:31.981987 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2445 01:24:31.985454 [-4] AVG Duty = 4969%(X100)
2446 01:24:31.986011
2447 01:24:31.986469 ==DQ 1 ==
2448 01:24:31.988466 Final DQ duty delay cell = -4
2449 01:24:31.991906 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2450 01:24:31.995507 [-4] MIN Duty = 4876%(X100), DQS PI = 14
2451 01:24:31.998643 [-4] AVG Duty = 4922%(X100)
2452 01:24:31.999100
2453 01:24:32.001923 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2454 01:24:32.002381
2455 01:24:32.005066 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2456 01:24:32.008579 [DutyScan_Calibration_Flow] ====Done====
2457 01:24:32.009142 ==
2458 01:24:32.012360 Dram Type= 6, Freq= 0, CH_1, rank 0
2459 01:24:32.015159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2460 01:24:32.015619 ==
2461 01:24:32.018279 [Duty_Offset_Calibration]
2462 01:24:32.018843 B0:-1 B1:1 CA:1
2463 01:24:32.021263
2464 01:24:32.025065 [DutyScan_Calibration_Flow] k_type=0
2465 01:24:32.032531
2466 01:24:32.033083 ==CLK 0==
2467 01:24:32.036049 Final CLK duty delay cell = 0
2468 01:24:32.039577 [0] MAX Duty = 5156%(X100), DQS PI = 20
2469 01:24:32.042807 [0] MIN Duty = 4969%(X100), DQS PI = 62
2470 01:24:32.043266 [0] AVG Duty = 5062%(X100)
2471 01:24:32.045755
2472 01:24:32.049416 CH1 CLK Duty spec in!! Max-Min= 187%
2473 01:24:32.052283 [DutyScan_Calibration_Flow] ====Done====
2474 01:24:32.052967
2475 01:24:32.055728 [DutyScan_Calibration_Flow] k_type=1
2476 01:24:32.072336
2477 01:24:32.072909 ==DQS 0 ==
2478 01:24:32.075120 Final DQS duty delay cell = 0
2479 01:24:32.078240 [0] MAX Duty = 5125%(X100), DQS PI = 48
2480 01:24:32.082010 [0] MIN Duty = 4875%(X100), DQS PI = 8
2481 01:24:32.085083 [0] AVG Duty = 5000%(X100)
2482 01:24:32.085710
2483 01:24:32.086196 ==DQS 1 ==
2484 01:24:32.088380 Final DQS duty delay cell = 0
2485 01:24:32.091662 [0] MAX Duty = 5062%(X100), DQS PI = 12
2486 01:24:32.094897 [0] MIN Duty = 4969%(X100), DQS PI = 56
2487 01:24:32.098380 [0] AVG Duty = 5015%(X100)
2488 01:24:32.098908
2489 01:24:32.101291 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2490 01:24:32.101807
2491 01:24:32.104499 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2492 01:24:32.108274 [DutyScan_Calibration_Flow] ====Done====
2493 01:24:32.108840
2494 01:24:32.111480 [DutyScan_Calibration_Flow] k_type=3
2495 01:24:32.127640
2496 01:24:32.128213 ==DQM 0 ==
2497 01:24:32.131140 Final DQM duty delay cell = -4
2498 01:24:32.133968 [-4] MAX Duty = 5031%(X100), DQS PI = 16
2499 01:24:32.137218 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2500 01:24:32.141316 [-4] AVG Duty = 4937%(X100)
2501 01:24:32.141938
2502 01:24:32.142430 ==DQM 1 ==
2503 01:24:32.143758 Final DQM duty delay cell = 0
2504 01:24:32.147159 [0] MAX Duty = 5125%(X100), DQS PI = 2
2505 01:24:32.150196 [0] MIN Duty = 4969%(X100), DQS PI = 28
2506 01:24:32.153787 [0] AVG Duty = 5047%(X100)
2507 01:24:32.154355
2508 01:24:32.157199 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2509 01:24:32.157844
2510 01:24:32.160153 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2511 01:24:32.163891 [DutyScan_Calibration_Flow] ====Done====
2512 01:24:32.164364
2513 01:24:32.166906 [DutyScan_Calibration_Flow] k_type=2
2514 01:24:32.184722
2515 01:24:32.185288 ==DQ 0 ==
2516 01:24:32.187509 Final DQ duty delay cell = 0
2517 01:24:32.190750 [0] MAX Duty = 5187%(X100), DQS PI = 30
2518 01:24:32.194227 [0] MIN Duty = 4907%(X100), DQS PI = 6
2519 01:24:32.194803 [0] AVG Duty = 5047%(X100)
2520 01:24:32.195290
2521 01:24:32.197769 ==DQ 1 ==
2522 01:24:32.200205 Final DQ duty delay cell = 0
2523 01:24:32.204161 [0] MAX Duty = 5124%(X100), DQS PI = 10
2524 01:24:32.207249 [0] MIN Duty = 4969%(X100), DQS PI = 36
2525 01:24:32.207707 [0] AVG Duty = 5046%(X100)
2526 01:24:32.210413
2527 01:24:32.213479 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2528 01:24:32.213942
2529 01:24:32.216954 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2530 01:24:32.220288 [DutyScan_Calibration_Flow] ====Done====
2531 01:24:32.224780 nWR fixed to 30
2532 01:24:32.225381 [ModeRegInit_LP4] CH0 RK0
2533 01:24:32.226948 [ModeRegInit_LP4] CH0 RK1
2534 01:24:32.230135 [ModeRegInit_LP4] CH1 RK0
2535 01:24:32.234021 [ModeRegInit_LP4] CH1 RK1
2536 01:24:32.234551 match AC timing 7
2537 01:24:32.240185 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2538 01:24:32.243551 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2539 01:24:32.246802 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2540 01:24:32.253622 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2541 01:24:32.256979 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2542 01:24:32.257575 ==
2543 01:24:32.260558 Dram Type= 6, Freq= 0, CH_0, rank 0
2544 01:24:32.263552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2545 01:24:32.264107 ==
2546 01:24:32.269927 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2547 01:24:32.276753 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2548 01:24:32.284070 [CA 0] Center 39 (9~70) winsize 62
2549 01:24:32.287556 [CA 1] Center 39 (9~69) winsize 61
2550 01:24:32.291053 [CA 2] Center 35 (5~66) winsize 62
2551 01:24:32.294733 [CA 3] Center 35 (5~66) winsize 62
2552 01:24:32.297964 [CA 4] Center 33 (4~63) winsize 60
2553 01:24:32.300668 [CA 5] Center 33 (3~63) winsize 61
2554 01:24:32.301175
2555 01:24:32.304295 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2556 01:24:32.304894
2557 01:24:32.307288 [CATrainingPosCal] consider 1 rank data
2558 01:24:32.310795 u2DelayCellTimex100 = 270/100 ps
2559 01:24:32.313869 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2560 01:24:32.317024 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2561 01:24:32.324494 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2562 01:24:32.327548 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2563 01:24:32.330522 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2564 01:24:32.334049 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2565 01:24:32.334511
2566 01:24:32.337481 CA PerBit enable=1, Macro0, CA PI delay=33
2567 01:24:32.338043
2568 01:24:32.340486 [CBTSetCACLKResult] CA Dly = 33
2569 01:24:32.340947 CS Dly: 8 (0~39)
2570 01:24:32.343695 ==
2571 01:24:32.344155 Dram Type= 6, Freq= 0, CH_0, rank 1
2572 01:24:32.350765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2573 01:24:32.351328 ==
2574 01:24:32.353860 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2575 01:24:32.360412 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2576 01:24:32.370242 [CA 0] Center 39 (9~70) winsize 62
2577 01:24:32.373391 [CA 1] Center 39 (9~70) winsize 62
2578 01:24:32.376383 [CA 2] Center 35 (5~66) winsize 62
2579 01:24:32.379373 [CA 3] Center 34 (4~65) winsize 62
2580 01:24:32.382992 [CA 4] Center 33 (3~64) winsize 62
2581 01:24:32.386061 [CA 5] Center 33 (3~63) winsize 61
2582 01:24:32.386521
2583 01:24:32.389919 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2584 01:24:32.390477
2585 01:24:32.393146 [CATrainingPosCal] consider 2 rank data
2586 01:24:32.396112 u2DelayCellTimex100 = 270/100 ps
2587 01:24:32.399572 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2588 01:24:32.405855 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2589 01:24:32.409681 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2590 01:24:32.412611 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2591 01:24:32.416034 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2592 01:24:32.419605 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2593 01:24:32.420158
2594 01:24:32.422292 CA PerBit enable=1, Macro0, CA PI delay=33
2595 01:24:32.422752
2596 01:24:32.425869 [CBTSetCACLKResult] CA Dly = 33
2597 01:24:32.428814 CS Dly: 9 (0~41)
2598 01:24:32.429271
2599 01:24:32.433038 ----->DramcWriteLeveling(PI) begin...
2600 01:24:32.433652 ==
2601 01:24:32.435795 Dram Type= 6, Freq= 0, CH_0, rank 0
2602 01:24:32.438640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2603 01:24:32.439105 ==
2604 01:24:32.442670 Write leveling (Byte 0): 35 => 35
2605 01:24:32.445795 Write leveling (Byte 1): 29 => 29
2606 01:24:32.448785 DramcWriteLeveling(PI) end<-----
2607 01:24:32.449386
2608 01:24:32.449775 ==
2609 01:24:32.452527 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 01:24:32.455966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 01:24:32.456532 ==
2612 01:24:32.458890 [Gating] SW mode calibration
2613 01:24:32.465798 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2614 01:24:32.471981 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2615 01:24:32.475250 0 15 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2616 01:24:32.478668 0 15 4 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
2617 01:24:32.485128 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2618 01:24:32.488600 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2619 01:24:32.492188 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2620 01:24:32.498329 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2621 01:24:32.501667 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2622 01:24:32.504943 0 15 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
2623 01:24:32.511592 1 0 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
2624 01:24:32.515088 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2625 01:24:32.518202 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2626 01:24:32.525059 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2627 01:24:32.527773 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2628 01:24:32.531261 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2629 01:24:32.537955 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2630 01:24:32.541023 1 0 28 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
2631 01:24:32.544217 1 1 0 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2632 01:24:32.550964 1 1 4 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
2633 01:24:32.554583 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2634 01:24:32.560744 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2635 01:24:32.564106 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2636 01:24:32.567037 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2637 01:24:32.574239 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2638 01:24:32.577095 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2639 01:24:32.581122 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2640 01:24:32.584388 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2641 01:24:32.590662 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 01:24:32.594288 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 01:24:32.600313 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 01:24:32.603373 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2645 01:24:32.607231 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2646 01:24:32.613590 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2647 01:24:32.616688 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2648 01:24:32.620169 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2649 01:24:32.626452 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2650 01:24:32.629708 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2651 01:24:32.633514 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2652 01:24:32.639823 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2653 01:24:32.643072 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2654 01:24:32.646344 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2655 01:24:32.653429 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2656 01:24:32.654048 Total UI for P1: 0, mck2ui 16
2657 01:24:32.659896 best dqsien dly found for B0: ( 1, 3, 28)
2658 01:24:32.662887 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2659 01:24:32.666639 Total UI for P1: 0, mck2ui 16
2660 01:24:32.669531 best dqsien dly found for B1: ( 1, 4, 0)
2661 01:24:32.672487 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2662 01:24:32.676338 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2663 01:24:32.676897
2664 01:24:32.679366 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2665 01:24:32.682577 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2666 01:24:32.685868 [Gating] SW calibration Done
2667 01:24:32.686327 ==
2668 01:24:32.689616 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 01:24:32.693005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 01:24:32.693607 ==
2671 01:24:32.696169 RX Vref Scan: 0
2672 01:24:32.696746
2673 01:24:32.699311 RX Vref 0 -> 0, step: 1
2674 01:24:32.699772
2675 01:24:32.700137 RX Delay -40 -> 252, step: 8
2676 01:24:32.705923 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2677 01:24:32.708883 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2678 01:24:32.712291 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2679 01:24:32.715542 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2680 01:24:32.722108 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2681 01:24:32.725364 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2682 01:24:32.728683 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2683 01:24:32.732424 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2684 01:24:32.735175 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2685 01:24:32.738559 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2686 01:24:32.744923 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2687 01:24:32.748406 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2688 01:24:32.751475 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2689 01:24:32.754870 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2690 01:24:32.761424 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2691 01:24:32.764728 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2692 01:24:32.765260 ==
2693 01:24:32.767934 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 01:24:32.771577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 01:24:32.772028 ==
2696 01:24:32.774416 DQS Delay:
2697 01:24:32.774825 DQS0 = 0, DQS1 = 0
2698 01:24:32.775147 DQM Delay:
2699 01:24:32.777698 DQM0 = 119, DQM1 = 106
2700 01:24:32.778227 DQ Delay:
2701 01:24:32.781086 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2702 01:24:32.787995 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2703 01:24:32.791097 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2704 01:24:32.794301 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2705 01:24:32.794713
2706 01:24:32.795036
2707 01:24:32.795338 ==
2708 01:24:32.797457 Dram Type= 6, Freq= 0, CH_0, rank 0
2709 01:24:32.800776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2710 01:24:32.801192 ==
2711 01:24:32.801698
2712 01:24:32.802177
2713 01:24:32.804395 TX Vref Scan disable
2714 01:24:32.807926 == TX Byte 0 ==
2715 01:24:32.810950 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2716 01:24:32.814479 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2717 01:24:32.817834 == TX Byte 1 ==
2718 01:24:32.821031 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2719 01:24:32.824364 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2720 01:24:32.824782 ==
2721 01:24:32.827605 Dram Type= 6, Freq= 0, CH_0, rank 0
2722 01:24:32.830729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2723 01:24:32.833861 ==
2724 01:24:32.844802 TX Vref=22, minBit 4, minWin=25, winSum=414
2725 01:24:32.848015 TX Vref=24, minBit 1, minWin=26, winSum=422
2726 01:24:32.851118 TX Vref=26, minBit 3, minWin=26, winSum=430
2727 01:24:32.854768 TX Vref=28, minBit 6, minWin=26, winSum=429
2728 01:24:32.857872 TX Vref=30, minBit 5, minWin=26, winSum=430
2729 01:24:32.864800 TX Vref=32, minBit 10, minWin=26, winSum=432
2730 01:24:32.867767 [TxChooseVref] Worse bit 10, Min win 26, Win sum 432, Final Vref 32
2731 01:24:32.868316
2732 01:24:32.870926 Final TX Range 1 Vref 32
2733 01:24:32.871383
2734 01:24:32.871742 ==
2735 01:24:32.874482 Dram Type= 6, Freq= 0, CH_0, rank 0
2736 01:24:32.880681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2737 01:24:32.881231 ==
2738 01:24:32.881639
2739 01:24:32.881973
2740 01:24:32.882290 TX Vref Scan disable
2741 01:24:32.884830 == TX Byte 0 ==
2742 01:24:32.888129 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2743 01:24:32.891095 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2744 01:24:32.894364 == TX Byte 1 ==
2745 01:24:32.898214 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2746 01:24:32.904390 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2747 01:24:32.904994
2748 01:24:32.905581 [DATLAT]
2749 01:24:32.905943 Freq=1200, CH0 RK0
2750 01:24:32.906281
2751 01:24:32.908034 DATLAT Default: 0xd
2752 01:24:32.908511 0, 0xFFFF, sum = 0
2753 01:24:32.911326 1, 0xFFFF, sum = 0
2754 01:24:32.914300 2, 0xFFFF, sum = 0
2755 01:24:32.914764 3, 0xFFFF, sum = 0
2756 01:24:32.917511 4, 0xFFFF, sum = 0
2757 01:24:32.917976 5, 0xFFFF, sum = 0
2758 01:24:32.921019 6, 0xFFFF, sum = 0
2759 01:24:32.921635 7, 0xFFFF, sum = 0
2760 01:24:32.924068 8, 0xFFFF, sum = 0
2761 01:24:32.924624 9, 0xFFFF, sum = 0
2762 01:24:32.927795 10, 0xFFFF, sum = 0
2763 01:24:32.928353 11, 0xFFFF, sum = 0
2764 01:24:32.930712 12, 0x0, sum = 1
2765 01:24:32.931176 13, 0x0, sum = 2
2766 01:24:32.934068 14, 0x0, sum = 3
2767 01:24:32.934626 15, 0x0, sum = 4
2768 01:24:32.937417 best_step = 13
2769 01:24:32.937974
2770 01:24:32.938341 ==
2771 01:24:32.941087 Dram Type= 6, Freq= 0, CH_0, rank 0
2772 01:24:32.944403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2773 01:24:32.944958 ==
2774 01:24:32.945323 RX Vref Scan: 1
2775 01:24:32.947723
2776 01:24:32.948266 Set Vref Range= 32 -> 127
2777 01:24:32.948634
2778 01:24:32.950352 RX Vref 32 -> 127, step: 1
2779 01:24:32.950809
2780 01:24:32.953976 RX Delay -21 -> 252, step: 4
2781 01:24:32.954537
2782 01:24:32.957726 Set Vref, RX VrefLevel [Byte0]: 32
2783 01:24:32.960783 [Byte1]: 32
2784 01:24:32.961350
2785 01:24:32.963864 Set Vref, RX VrefLevel [Byte0]: 33
2786 01:24:32.967364 [Byte1]: 33
2787 01:24:32.970970
2788 01:24:32.971533 Set Vref, RX VrefLevel [Byte0]: 34
2789 01:24:32.974315 [Byte1]: 34
2790 01:24:32.979180
2791 01:24:32.979744 Set Vref, RX VrefLevel [Byte0]: 35
2792 01:24:32.982270 [Byte1]: 35
2793 01:24:32.986799
2794 01:24:32.987338 Set Vref, RX VrefLevel [Byte0]: 36
2795 01:24:32.990429 [Byte1]: 36
2796 01:24:32.994987
2797 01:24:32.995533 Set Vref, RX VrefLevel [Byte0]: 37
2798 01:24:32.998307 [Byte1]: 37
2799 01:24:33.002881
2800 01:24:33.003439 Set Vref, RX VrefLevel [Byte0]: 38
2801 01:24:33.005805 [Byte1]: 38
2802 01:24:33.010945
2803 01:24:33.011525 Set Vref, RX VrefLevel [Byte0]: 39
2804 01:24:33.013987 [Byte1]: 39
2805 01:24:33.018446
2806 01:24:33.018899 Set Vref, RX VrefLevel [Byte0]: 40
2807 01:24:33.021588 [Byte1]: 40
2808 01:24:33.026534
2809 01:24:33.027084 Set Vref, RX VrefLevel [Byte0]: 41
2810 01:24:33.029896 [Byte1]: 41
2811 01:24:33.034576
2812 01:24:33.035129 Set Vref, RX VrefLevel [Byte0]: 42
2813 01:24:33.037429 [Byte1]: 42
2814 01:24:33.041939
2815 01:24:33.042394 Set Vref, RX VrefLevel [Byte0]: 43
2816 01:24:33.045499 [Byte1]: 43
2817 01:24:33.050576
2818 01:24:33.051126 Set Vref, RX VrefLevel [Byte0]: 44
2819 01:24:33.053880 [Byte1]: 44
2820 01:24:33.058689
2821 01:24:33.059268 Set Vref, RX VrefLevel [Byte0]: 45
2822 01:24:33.061963 [Byte1]: 45
2823 01:24:33.065871
2824 01:24:33.066325 Set Vref, RX VrefLevel [Byte0]: 46
2825 01:24:33.069618 [Byte1]: 46
2826 01:24:33.073918
2827 01:24:33.074373 Set Vref, RX VrefLevel [Byte0]: 47
2828 01:24:33.077380 [Byte1]: 47
2829 01:24:33.082328
2830 01:24:33.082878 Set Vref, RX VrefLevel [Byte0]: 48
2831 01:24:33.085762 [Byte1]: 48
2832 01:24:33.089928
2833 01:24:33.090478 Set Vref, RX VrefLevel [Byte0]: 49
2834 01:24:33.093498 [Byte1]: 49
2835 01:24:33.097882
2836 01:24:33.098429 Set Vref, RX VrefLevel [Byte0]: 50
2837 01:24:33.101091 [Byte1]: 50
2838 01:24:33.105663
2839 01:24:33.106279 Set Vref, RX VrefLevel [Byte0]: 51
2840 01:24:33.109080 [Byte1]: 51
2841 01:24:33.113783
2842 01:24:33.114489 Set Vref, RX VrefLevel [Byte0]: 52
2843 01:24:33.117208 [Byte1]: 52
2844 01:24:33.122035
2845 01:24:33.122582 Set Vref, RX VrefLevel [Byte0]: 53
2846 01:24:33.125064 [Byte1]: 53
2847 01:24:33.129324
2848 01:24:33.129814 Set Vref, RX VrefLevel [Byte0]: 54
2849 01:24:33.132860 [Byte1]: 54
2850 01:24:33.137523
2851 01:24:33.138062 Set Vref, RX VrefLevel [Byte0]: 55
2852 01:24:33.140513 [Byte1]: 55
2853 01:24:33.145448
2854 01:24:33.145989 Set Vref, RX VrefLevel [Byte0]: 56
2855 01:24:33.148485 [Byte1]: 56
2856 01:24:33.153023
2857 01:24:33.153615 Set Vref, RX VrefLevel [Byte0]: 57
2858 01:24:33.156831 [Byte1]: 57
2859 01:24:33.161187
2860 01:24:33.161782 Set Vref, RX VrefLevel [Byte0]: 58
2861 01:24:33.164439 [Byte1]: 58
2862 01:24:33.169240
2863 01:24:33.169815 Set Vref, RX VrefLevel [Byte0]: 59
2864 01:24:33.173027 [Byte1]: 59
2865 01:24:33.177373
2866 01:24:33.177927 Set Vref, RX VrefLevel [Byte0]: 60
2867 01:24:33.180779 [Byte1]: 60
2868 01:24:33.185163
2869 01:24:33.185773 Set Vref, RX VrefLevel [Byte0]: 61
2870 01:24:33.188201 [Byte1]: 61
2871 01:24:33.192937
2872 01:24:33.193541 Set Vref, RX VrefLevel [Byte0]: 62
2873 01:24:33.196384 [Byte1]: 62
2874 01:24:33.201096
2875 01:24:33.201696 Set Vref, RX VrefLevel [Byte0]: 63
2876 01:24:33.203968 [Byte1]: 63
2877 01:24:33.208586
2878 01:24:33.209042 Set Vref, RX VrefLevel [Byte0]: 64
2879 01:24:33.212297 [Byte1]: 64
2880 01:24:33.216911
2881 01:24:33.217415 Set Vref, RX VrefLevel [Byte0]: 65
2882 01:24:33.219826 [Byte1]: 65
2883 01:24:33.224606
2884 01:24:33.225179 Set Vref, RX VrefLevel [Byte0]: 66
2885 01:24:33.228204 [Byte1]: 66
2886 01:24:33.232936
2887 01:24:33.233537 Set Vref, RX VrefLevel [Byte0]: 67
2888 01:24:33.236226 [Byte1]: 67
2889 01:24:33.241050
2890 01:24:33.241665 Set Vref, RX VrefLevel [Byte0]: 68
2891 01:24:33.244208 [Byte1]: 68
2892 01:24:33.248721
2893 01:24:33.249268 Set Vref, RX VrefLevel [Byte0]: 69
2894 01:24:33.251656 [Byte1]: 69
2895 01:24:33.256874
2896 01:24:33.257450 Set Vref, RX VrefLevel [Byte0]: 70
2897 01:24:33.259826 [Byte1]: 70
2898 01:24:33.263861
2899 01:24:33.264313 Set Vref, RX VrefLevel [Byte0]: 71
2900 01:24:33.267686 [Byte1]: 71
2901 01:24:33.271866
2902 01:24:33.272317 Set Vref, RX VrefLevel [Byte0]: 72
2903 01:24:33.275860 [Byte1]: 72
2904 01:24:33.280110
2905 01:24:33.280659 Set Vref, RX VrefLevel [Byte0]: 73
2906 01:24:33.283317 [Byte1]: 73
2907 01:24:33.288206
2908 01:24:33.288753 Final RX Vref Byte 0 = 65 to rank0
2909 01:24:33.291464 Final RX Vref Byte 1 = 49 to rank0
2910 01:24:33.294815 Final RX Vref Byte 0 = 65 to rank1
2911 01:24:33.298185 Final RX Vref Byte 1 = 49 to rank1==
2912 01:24:33.301434 Dram Type= 6, Freq= 0, CH_0, rank 0
2913 01:24:33.307837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2914 01:24:33.308291 ==
2915 01:24:33.308652 DQS Delay:
2916 01:24:33.311127 DQS0 = 0, DQS1 = 0
2917 01:24:33.311676 DQM Delay:
2918 01:24:33.312042 DQM0 = 118, DQM1 = 106
2919 01:24:33.314663 DQ Delay:
2920 01:24:33.317852 DQ0 =116, DQ1 =118, DQ2 =116, DQ3 =116
2921 01:24:33.320764 DQ4 =120, DQ5 =112, DQ6 =126, DQ7 =124
2922 01:24:33.324574 DQ8 =96, DQ9 =92, DQ10 =108, DQ11 =100
2923 01:24:33.327749 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =116
2924 01:24:33.328302
2925 01:24:33.328924
2926 01:24:33.337320 [DQSOSCAuto] RK0, (LSB)MR18= 0xbf8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 405 ps
2927 01:24:33.337965 CH0 RK0: MR19=403, MR18=BF8
2928 01:24:33.344180 CH0_RK0: MR19=0x403, MR18=0xBF8, DQSOSC=405, MR23=63, INC=39, DEC=26
2929 01:24:33.344719
2930 01:24:33.347583 ----->DramcWriteLeveling(PI) begin...
2931 01:24:33.348137 ==
2932 01:24:33.351139 Dram Type= 6, Freq= 0, CH_0, rank 1
2933 01:24:33.354358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2934 01:24:33.357862 ==
2935 01:24:33.358411 Write leveling (Byte 0): 33 => 33
2936 01:24:33.360946 Write leveling (Byte 1): 29 => 29
2937 01:24:33.364222 DramcWriteLeveling(PI) end<-----
2938 01:24:33.364685
2939 01:24:33.365040 ==
2940 01:24:33.367651 Dram Type= 6, Freq= 0, CH_0, rank 1
2941 01:24:33.374420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2942 01:24:33.374882 ==
2943 01:24:33.375251 [Gating] SW mode calibration
2944 01:24:33.384398 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2945 01:24:33.387737 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2946 01:24:33.394672 0 15 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
2947 01:24:33.397464 0 15 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
2948 01:24:33.400515 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2949 01:24:33.403776 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2950 01:24:33.410722 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2951 01:24:33.414248 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2952 01:24:33.417432 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2953 01:24:33.423964 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2954 01:24:33.427452 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
2955 01:24:33.430294 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2956 01:24:33.437061 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2957 01:24:33.440508 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2958 01:24:33.444254 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2959 01:24:33.450569 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2960 01:24:33.453899 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2961 01:24:33.457119 1 0 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2962 01:24:33.463948 1 1 0 | B1->B0 | 2e2e 4242 | 0 0 | (0 0) (0 0)
2963 01:24:33.467636 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2964 01:24:33.470742 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2965 01:24:33.477243 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 01:24:33.480194 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 01:24:33.483382 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2968 01:24:33.489989 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2969 01:24:33.493446 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2970 01:24:33.496942 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2971 01:24:33.503439 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2972 01:24:33.506803 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2973 01:24:33.509884 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 01:24:33.516529 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 01:24:33.520129 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 01:24:33.523105 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 01:24:33.530186 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 01:24:33.533127 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 01:24:33.536284 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 01:24:33.542985 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 01:24:33.546306 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 01:24:33.549592 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 01:24:33.556229 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 01:24:33.559033 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2985 01:24:33.562893 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2986 01:24:33.569278 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2987 01:24:33.569777 Total UI for P1: 0, mck2ui 16
2988 01:24:33.576389 best dqsien dly found for B0: ( 1, 3, 26)
2989 01:24:33.579365 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2990 01:24:33.582648 Total UI for P1: 0, mck2ui 16
2991 01:24:33.585854 best dqsien dly found for B1: ( 1, 4, 0)
2992 01:24:33.589451 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2993 01:24:33.592940 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2994 01:24:33.593543
2995 01:24:33.595761 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2996 01:24:33.598851 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2997 01:24:33.602710 [Gating] SW calibration Done
2998 01:24:33.603284 ==
2999 01:24:33.605676 Dram Type= 6, Freq= 0, CH_0, rank 1
3000 01:24:33.608974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3001 01:24:33.612614 ==
3002 01:24:33.613153 RX Vref Scan: 0
3003 01:24:33.613640
3004 01:24:33.616038 RX Vref 0 -> 0, step: 1
3005 01:24:33.616607
3006 01:24:33.618923 RX Delay -40 -> 252, step: 8
3007 01:24:33.622083 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3008 01:24:33.625857 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
3009 01:24:33.628945 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3010 01:24:33.632186 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3011 01:24:33.638942 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
3012 01:24:33.642122 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3013 01:24:33.645572 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3014 01:24:33.649190 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3015 01:24:33.652561 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3016 01:24:33.658723 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3017 01:24:33.662323 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3018 01:24:33.665299 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3019 01:24:33.668875 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3020 01:24:33.672380 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3021 01:24:33.679044 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3022 01:24:33.681804 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3023 01:24:33.682255 ==
3024 01:24:33.685726 Dram Type= 6, Freq= 0, CH_0, rank 1
3025 01:24:33.688761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3026 01:24:33.689217 ==
3027 01:24:33.692141 DQS Delay:
3028 01:24:33.692692 DQS0 = 0, DQS1 = 0
3029 01:24:33.693055 DQM Delay:
3030 01:24:33.695306 DQM0 = 116, DQM1 = 108
3031 01:24:33.695851 DQ Delay:
3032 01:24:33.698566 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
3033 01:24:33.701702 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
3034 01:24:33.705138 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3035 01:24:33.711800 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
3036 01:24:33.712255
3037 01:24:33.712611
3038 01:24:33.712943 ==
3039 01:24:33.714974 Dram Type= 6, Freq= 0, CH_0, rank 1
3040 01:24:33.718578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 01:24:33.719035 ==
3042 01:24:33.719392
3043 01:24:33.719725
3044 01:24:33.721514 TX Vref Scan disable
3045 01:24:33.721966 == TX Byte 0 ==
3046 01:24:33.728721 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3047 01:24:33.731576 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3048 01:24:33.732163 == TX Byte 1 ==
3049 01:24:33.737933 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3050 01:24:33.741539 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3051 01:24:33.742092 ==
3052 01:24:33.745161 Dram Type= 6, Freq= 0, CH_0, rank 1
3053 01:24:33.748270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3054 01:24:33.748823 ==
3055 01:24:33.761701 TX Vref=22, minBit 3, minWin=25, winSum=416
3056 01:24:33.764915 TX Vref=24, minBit 1, minWin=26, winSum=427
3057 01:24:33.768587 TX Vref=26, minBit 8, minWin=26, winSum=430
3058 01:24:33.771396 TX Vref=28, minBit 13, minWin=26, winSum=433
3059 01:24:33.774447 TX Vref=30, minBit 8, minWin=26, winSum=432
3060 01:24:33.781325 TX Vref=32, minBit 10, minWin=26, winSum=434
3061 01:24:33.784544 [TxChooseVref] Worse bit 10, Min win 26, Win sum 434, Final Vref 32
3062 01:24:33.784999
3063 01:24:33.788301 Final TX Range 1 Vref 32
3064 01:24:33.788851
3065 01:24:33.789210 ==
3066 01:24:33.791668 Dram Type= 6, Freq= 0, CH_0, rank 1
3067 01:24:33.794976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 01:24:33.797689 ==
3069 01:24:33.798163
3070 01:24:33.798517
3071 01:24:33.798845 TX Vref Scan disable
3072 01:24:33.801092 == TX Byte 0 ==
3073 01:24:33.804643 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3074 01:24:33.811085 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3075 01:24:33.811542 == TX Byte 1 ==
3076 01:24:33.814780 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3077 01:24:33.821419 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3078 01:24:33.821972
3079 01:24:33.822331 [DATLAT]
3080 01:24:33.822662 Freq=1200, CH0 RK1
3081 01:24:33.822980
3082 01:24:33.824810 DATLAT Default: 0xd
3083 01:24:33.825258 0, 0xFFFF, sum = 0
3084 01:24:33.827569 1, 0xFFFF, sum = 0
3085 01:24:33.831434 2, 0xFFFF, sum = 0
3086 01:24:33.832060 3, 0xFFFF, sum = 0
3087 01:24:33.834538 4, 0xFFFF, sum = 0
3088 01:24:33.835100 5, 0xFFFF, sum = 0
3089 01:24:33.837876 6, 0xFFFF, sum = 0
3090 01:24:33.838331 7, 0xFFFF, sum = 0
3091 01:24:33.841365 8, 0xFFFF, sum = 0
3092 01:24:33.841829 9, 0xFFFF, sum = 0
3093 01:24:33.844581 10, 0xFFFF, sum = 0
3094 01:24:33.845043 11, 0xFFFF, sum = 0
3095 01:24:33.847767 12, 0x0, sum = 1
3096 01:24:33.848359 13, 0x0, sum = 2
3097 01:24:33.850776 14, 0x0, sum = 3
3098 01:24:33.851235 15, 0x0, sum = 4
3099 01:24:33.854303 best_step = 13
3100 01:24:33.854814
3101 01:24:33.855383 ==
3102 01:24:33.857399 Dram Type= 6, Freq= 0, CH_0, rank 1
3103 01:24:33.861315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3104 01:24:33.861922 ==
3105 01:24:33.862288 RX Vref Scan: 0
3106 01:24:33.864320
3107 01:24:33.864955 RX Vref 0 -> 0, step: 1
3108 01:24:33.865415
3109 01:24:33.867210 RX Delay -21 -> 252, step: 4
3110 01:24:33.874025 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3111 01:24:33.877302 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3112 01:24:33.881242 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
3113 01:24:33.884113 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3114 01:24:33.887607 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
3115 01:24:33.890456 iDelay=195, Bit 5, Center 112 (47 ~ 178) 132
3116 01:24:33.896909 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3117 01:24:33.900593 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3118 01:24:33.903691 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3119 01:24:33.907083 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3120 01:24:33.913599 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3121 01:24:33.917296 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3122 01:24:33.919987 iDelay=195, Bit 12, Center 114 (47 ~ 182) 136
3123 01:24:33.923952 iDelay=195, Bit 13, Center 114 (47 ~ 182) 136
3124 01:24:33.926674 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3125 01:24:33.933590 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3126 01:24:33.934025 ==
3127 01:24:33.937248 Dram Type= 6, Freq= 0, CH_0, rank 1
3128 01:24:33.939959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 01:24:33.940518 ==
3130 01:24:33.940986 DQS Delay:
3131 01:24:33.943312 DQS0 = 0, DQS1 = 0
3132 01:24:33.943724 DQM Delay:
3133 01:24:33.946531 DQM0 = 116, DQM1 = 107
3134 01:24:33.946940 DQ Delay:
3135 01:24:33.950159 DQ0 =114, DQ1 =118, DQ2 =112, DQ3 =114
3136 01:24:33.953571 DQ4 =118, DQ5 =112, DQ6 =124, DQ7 =122
3137 01:24:33.956447 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3138 01:24:33.960166 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =116
3139 01:24:33.960681
3140 01:24:33.961008
3141 01:24:33.970016 [DQSOSCAuto] RK1, (LSB)MR18= 0xae4, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
3142 01:24:33.973266 CH0 RK1: MR19=403, MR18=AE4
3143 01:24:33.976320 CH0_RK1: MR19=0x403, MR18=0xAE4, DQSOSC=406, MR23=63, INC=39, DEC=26
3144 01:24:33.979689 [RxdqsGatingPostProcess] freq 1200
3145 01:24:33.986796 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3146 01:24:33.989900 best DQS0 dly(2T, 0.5T) = (0, 11)
3147 01:24:33.993542 best DQS1 dly(2T, 0.5T) = (0, 12)
3148 01:24:33.996483 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3149 01:24:34.000052 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3150 01:24:34.003422 best DQS0 dly(2T, 0.5T) = (0, 11)
3151 01:24:34.006262 best DQS1 dly(2T, 0.5T) = (0, 12)
3152 01:24:34.009470 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3153 01:24:34.012880 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3154 01:24:34.016172 Pre-setting of DQS Precalculation
3155 01:24:34.020031 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3156 01:24:34.020575 ==
3157 01:24:34.023705 Dram Type= 6, Freq= 0, CH_1, rank 0
3158 01:24:34.026455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3159 01:24:34.027007 ==
3160 01:24:34.033131 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3161 01:24:34.039995 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3162 01:24:34.047315 [CA 0] Center 37 (7~68) winsize 62
3163 01:24:34.050656 [CA 1] Center 38 (8~68) winsize 61
3164 01:24:34.054096 [CA 2] Center 34 (4~64) winsize 61
3165 01:24:34.057166 [CA 3] Center 33 (3~64) winsize 62
3166 01:24:34.060487 [CA 4] Center 34 (5~64) winsize 60
3167 01:24:34.063888 [CA 5] Center 33 (3~64) winsize 62
3168 01:24:34.064441
3169 01:24:34.067458 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3170 01:24:34.068009
3171 01:24:34.070729 [CATrainingPosCal] consider 1 rank data
3172 01:24:34.073871 u2DelayCellTimex100 = 270/100 ps
3173 01:24:34.077380 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3174 01:24:34.083858 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3175 01:24:34.087547 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3176 01:24:34.090267 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3177 01:24:34.094004 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3178 01:24:34.097009 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3179 01:24:34.097615
3180 01:24:34.100026 CA PerBit enable=1, Macro0, CA PI delay=33
3181 01:24:34.100593
3182 01:24:34.103905 [CBTSetCACLKResult] CA Dly = 33
3183 01:24:34.106556 CS Dly: 6 (0~37)
3184 01:24:34.107081 ==
3185 01:24:34.109867 Dram Type= 6, Freq= 0, CH_1, rank 1
3186 01:24:34.113453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3187 01:24:34.113911 ==
3188 01:24:34.119839 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3189 01:24:34.122837 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3190 01:24:34.133603 [CA 0] Center 37 (7~68) winsize 62
3191 01:24:34.136319 [CA 1] Center 38 (8~68) winsize 61
3192 01:24:34.139407 [CA 2] Center 34 (4~65) winsize 62
3193 01:24:34.142573 [CA 3] Center 34 (4~64) winsize 61
3194 01:24:34.145927 [CA 4] Center 34 (3~65) winsize 63
3195 01:24:34.149430 [CA 5] Center 33 (3~64) winsize 62
3196 01:24:34.150064
3197 01:24:34.152647 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3198 01:24:34.153196
3199 01:24:34.156286 [CATrainingPosCal] consider 2 rank data
3200 01:24:34.159291 u2DelayCellTimex100 = 270/100 ps
3201 01:24:34.162889 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3202 01:24:34.169789 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3203 01:24:34.172879 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3204 01:24:34.176253 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3205 01:24:34.179357 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3206 01:24:34.182464 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3207 01:24:34.182921
3208 01:24:34.186112 CA PerBit enable=1, Macro0, CA PI delay=33
3209 01:24:34.186567
3210 01:24:34.188798 [CBTSetCACLKResult] CA Dly = 33
3211 01:24:34.192710 CS Dly: 7 (0~40)
3212 01:24:34.193261
3213 01:24:34.196131 ----->DramcWriteLeveling(PI) begin...
3214 01:24:34.196687 ==
3215 01:24:34.199376 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 01:24:34.202318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 01:24:34.202776 ==
3218 01:24:34.205486 Write leveling (Byte 0): 25 => 25
3219 01:24:34.208888 Write leveling (Byte 1): 27 => 27
3220 01:24:34.212175 DramcWriteLeveling(PI) end<-----
3221 01:24:34.212731
3222 01:24:34.213096 ==
3223 01:24:34.215669 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 01:24:34.218586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 01:24:34.219041 ==
3226 01:24:34.221710 [Gating] SW mode calibration
3227 01:24:34.228422 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3228 01:24:34.235334 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3229 01:24:34.238072 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3230 01:24:34.245302 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3231 01:24:34.248315 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3232 01:24:34.251597 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3233 01:24:34.258430 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3234 01:24:34.261714 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3235 01:24:34.264686 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
3236 01:24:34.268261 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (0 1) (1 0)
3237 01:24:34.274987 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3238 01:24:34.278137 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3239 01:24:34.281281 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3240 01:24:34.288051 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3241 01:24:34.290801 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3242 01:24:34.294537 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3243 01:24:34.301065 1 0 24 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
3244 01:24:34.304431 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3245 01:24:34.307990 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3246 01:24:34.314713 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3247 01:24:34.317761 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3248 01:24:34.321073 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3249 01:24:34.327734 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3250 01:24:34.330993 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3251 01:24:34.334176 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3252 01:24:34.340638 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3253 01:24:34.344277 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3254 01:24:34.347457 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3255 01:24:34.354251 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3256 01:24:34.357847 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3257 01:24:34.360881 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3258 01:24:34.367280 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3259 01:24:34.370996 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3260 01:24:34.373965 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3261 01:24:34.380533 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3262 01:24:34.384139 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3263 01:24:34.387222 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3264 01:24:34.393491 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3265 01:24:34.397075 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3266 01:24:34.400287 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3267 01:24:34.406728 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3268 01:24:34.409984 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3269 01:24:34.413426 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3270 01:24:34.417017 Total UI for P1: 0, mck2ui 16
3271 01:24:34.420681 best dqsien dly found for B0: ( 1, 3, 26)
3272 01:24:34.423621 Total UI for P1: 0, mck2ui 16
3273 01:24:34.426734 best dqsien dly found for B1: ( 1, 3, 28)
3274 01:24:34.430050 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3275 01:24:34.433658 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3276 01:24:34.434204
3277 01:24:34.440201 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3278 01:24:34.443439 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3279 01:24:34.444087 [Gating] SW calibration Done
3280 01:24:34.446306 ==
3281 01:24:34.450079 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 01:24:34.453874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 01:24:34.454424 ==
3284 01:24:34.454785 RX Vref Scan: 0
3285 01:24:34.455154
3286 01:24:34.456371 RX Vref 0 -> 0, step: 1
3287 01:24:34.456824
3288 01:24:34.459647 RX Delay -40 -> 252, step: 8
3289 01:24:34.463298 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3290 01:24:34.466784 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3291 01:24:34.473258 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3292 01:24:34.476459 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3293 01:24:34.479902 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3294 01:24:34.483198 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3295 01:24:34.486388 iDelay=208, Bit 6, Center 127 (56 ~ 199) 144
3296 01:24:34.489925 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3297 01:24:34.496229 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
3298 01:24:34.500038 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3299 01:24:34.503043 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3300 01:24:34.505970 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3301 01:24:34.509448 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3302 01:24:34.516085 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3303 01:24:34.519264 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3304 01:24:34.522476 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3305 01:24:34.522928 ==
3306 01:24:34.525903 Dram Type= 6, Freq= 0, CH_1, rank 0
3307 01:24:34.529568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3308 01:24:34.533101 ==
3309 01:24:34.533722 DQS Delay:
3310 01:24:34.534120 DQS0 = 0, DQS1 = 0
3311 01:24:34.536679 DQM Delay:
3312 01:24:34.537227 DQM0 = 118, DQM1 = 110
3313 01:24:34.539271 DQ Delay:
3314 01:24:34.542734 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3315 01:24:34.545965 DQ4 =111, DQ5 =131, DQ6 =127, DQ7 =115
3316 01:24:34.549303 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =99
3317 01:24:34.552812 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3318 01:24:34.553397
3319 01:24:34.553763
3320 01:24:34.554096 ==
3321 01:24:34.556095 Dram Type= 6, Freq= 0, CH_1, rank 0
3322 01:24:34.558818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3323 01:24:34.559276 ==
3324 01:24:34.562213
3325 01:24:34.562762
3326 01:24:34.563120 TX Vref Scan disable
3327 01:24:34.566032 == TX Byte 0 ==
3328 01:24:34.568945 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3329 01:24:34.572434 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3330 01:24:34.575556 == TX Byte 1 ==
3331 01:24:34.578797 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3332 01:24:34.582420 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3333 01:24:34.582876 ==
3334 01:24:34.585492 Dram Type= 6, Freq= 0, CH_1, rank 0
3335 01:24:34.591785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3336 01:24:34.592337 ==
3337 01:24:34.602765 TX Vref=22, minBit 8, minWin=25, winSum=420
3338 01:24:34.606809 TX Vref=24, minBit 9, minWin=25, winSum=424
3339 01:24:34.609456 TX Vref=26, minBit 10, minWin=25, winSum=428
3340 01:24:34.612741 TX Vref=28, minBit 8, minWin=26, winSum=434
3341 01:24:34.615688 TX Vref=30, minBit 9, minWin=26, winSum=433
3342 01:24:34.622993 TX Vref=32, minBit 9, minWin=25, winSum=426
3343 01:24:34.625969 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 28
3344 01:24:34.626580
3345 01:24:34.629038 Final TX Range 1 Vref 28
3346 01:24:34.629692
3347 01:24:34.630098 ==
3348 01:24:34.632579 Dram Type= 6, Freq= 0, CH_1, rank 0
3349 01:24:34.636296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3350 01:24:34.639163 ==
3351 01:24:34.639616
3352 01:24:34.639971
3353 01:24:34.640304 TX Vref Scan disable
3354 01:24:34.642629 == TX Byte 0 ==
3355 01:24:34.646036 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3356 01:24:34.652419 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3357 01:24:34.652982 == TX Byte 1 ==
3358 01:24:34.655608 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3359 01:24:34.661885 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3360 01:24:34.662333
3361 01:24:34.662683 [DATLAT]
3362 01:24:34.663016 Freq=1200, CH1 RK0
3363 01:24:34.665612
3364 01:24:34.666117 DATLAT Default: 0xd
3365 01:24:34.668698 0, 0xFFFF, sum = 0
3366 01:24:34.669153 1, 0xFFFF, sum = 0
3367 01:24:34.671849 2, 0xFFFF, sum = 0
3368 01:24:34.672300 3, 0xFFFF, sum = 0
3369 01:24:34.675406 4, 0xFFFF, sum = 0
3370 01:24:34.675907 5, 0xFFFF, sum = 0
3371 01:24:34.678742 6, 0xFFFF, sum = 0
3372 01:24:34.679155 7, 0xFFFF, sum = 0
3373 01:24:34.682092 8, 0xFFFF, sum = 0
3374 01:24:34.682502 9, 0xFFFF, sum = 0
3375 01:24:34.685242 10, 0xFFFF, sum = 0
3376 01:24:34.685777 11, 0xFFFF, sum = 0
3377 01:24:34.689031 12, 0x0, sum = 1
3378 01:24:34.689482 13, 0x0, sum = 2
3379 01:24:34.691814 14, 0x0, sum = 3
3380 01:24:34.692325 15, 0x0, sum = 4
3381 01:24:34.695214 best_step = 13
3382 01:24:34.695626
3383 01:24:34.695976 ==
3384 01:24:34.698379 Dram Type= 6, Freq= 0, CH_1, rank 0
3385 01:24:34.701311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3386 01:24:34.701944 ==
3387 01:24:34.705286 RX Vref Scan: 1
3388 01:24:34.705731
3389 01:24:34.706054 Set Vref Range= 32 -> 127
3390 01:24:34.706354
3391 01:24:34.707987 RX Vref 32 -> 127, step: 1
3392 01:24:34.708390
3393 01:24:34.711636 RX Delay -21 -> 252, step: 4
3394 01:24:34.712225
3395 01:24:34.714828 Set Vref, RX VrefLevel [Byte0]: 32
3396 01:24:34.717767 [Byte1]: 32
3397 01:24:34.718246
3398 01:24:34.721166 Set Vref, RX VrefLevel [Byte0]: 33
3399 01:24:34.724747 [Byte1]: 33
3400 01:24:34.729033
3401 01:24:34.729657 Set Vref, RX VrefLevel [Byte0]: 34
3402 01:24:34.732230 [Byte1]: 34
3403 01:24:34.737303
3404 01:24:34.737851 Set Vref, RX VrefLevel [Byte0]: 35
3405 01:24:34.740043 [Byte1]: 35
3406 01:24:34.744920
3407 01:24:34.745322 Set Vref, RX VrefLevel [Byte0]: 36
3408 01:24:34.747954 [Byte1]: 36
3409 01:24:34.753488
3410 01:24:34.753984 Set Vref, RX VrefLevel [Byte0]: 37
3411 01:24:34.756187 [Byte1]: 37
3412 01:24:34.761000
3413 01:24:34.761538 Set Vref, RX VrefLevel [Byte0]: 38
3414 01:24:34.763866 [Byte1]: 38
3415 01:24:34.768521
3416 01:24:34.769017 Set Vref, RX VrefLevel [Byte0]: 39
3417 01:24:34.772219 [Byte1]: 39
3418 01:24:34.776537
3419 01:24:34.776942 Set Vref, RX VrefLevel [Byte0]: 40
3420 01:24:34.779550 [Byte1]: 40
3421 01:24:34.784395
3422 01:24:34.784886 Set Vref, RX VrefLevel [Byte0]: 41
3423 01:24:34.787783 [Byte1]: 41
3424 01:24:34.792219
3425 01:24:34.792723 Set Vref, RX VrefLevel [Byte0]: 42
3426 01:24:34.795912 [Byte1]: 42
3427 01:24:34.800221
3428 01:24:34.800721 Set Vref, RX VrefLevel [Byte0]: 43
3429 01:24:34.803407 [Byte1]: 43
3430 01:24:34.807966
3431 01:24:34.808466 Set Vref, RX VrefLevel [Byte0]: 44
3432 01:24:34.811723 [Byte1]: 44
3433 01:24:34.816149
3434 01:24:34.816659 Set Vref, RX VrefLevel [Byte0]: 45
3435 01:24:34.819363 [Byte1]: 45
3436 01:24:34.823931
3437 01:24:34.824446 Set Vref, RX VrefLevel [Byte0]: 46
3438 01:24:34.827125 [Byte1]: 46
3439 01:24:34.832040
3440 01:24:34.832661 Set Vref, RX VrefLevel [Byte0]: 47
3441 01:24:34.834957 [Byte1]: 47
3442 01:24:34.840144
3443 01:24:34.840642 Set Vref, RX VrefLevel [Byte0]: 48
3444 01:24:34.845934 [Byte1]: 48
3445 01:24:34.846428
3446 01:24:34.849784 Set Vref, RX VrefLevel [Byte0]: 49
3447 01:24:34.852959 [Byte1]: 49
3448 01:24:34.853505
3449 01:24:34.856338 Set Vref, RX VrefLevel [Byte0]: 50
3450 01:24:34.859817 [Byte1]: 50
3451 01:24:34.864040
3452 01:24:34.864537 Set Vref, RX VrefLevel [Byte0]: 51
3453 01:24:34.866871 [Byte1]: 51
3454 01:24:34.871821
3455 01:24:34.872316 Set Vref, RX VrefLevel [Byte0]: 52
3456 01:24:34.874992 [Byte1]: 52
3457 01:24:34.880107
3458 01:24:34.880606 Set Vref, RX VrefLevel [Byte0]: 53
3459 01:24:34.882408 [Byte1]: 53
3460 01:24:34.887540
3461 01:24:34.888087 Set Vref, RX VrefLevel [Byte0]: 54
3462 01:24:34.890494 [Byte1]: 54
3463 01:24:34.895063
3464 01:24:34.895562 Set Vref, RX VrefLevel [Byte0]: 55
3465 01:24:34.899327 [Byte1]: 55
3466 01:24:34.903604
3467 01:24:34.904281 Set Vref, RX VrefLevel [Byte0]: 56
3468 01:24:34.906479 [Byte1]: 56
3469 01:24:34.910709
3470 01:24:34.911360 Set Vref, RX VrefLevel [Byte0]: 57
3471 01:24:34.914300 [Byte1]: 57
3472 01:24:34.918634
3473 01:24:34.919089 Set Vref, RX VrefLevel [Byte0]: 58
3474 01:24:34.921900 [Byte1]: 58
3475 01:24:34.926407
3476 01:24:34.926782 Set Vref, RX VrefLevel [Byte0]: 59
3477 01:24:34.929870 [Byte1]: 59
3478 01:24:34.934310
3479 01:24:34.934499 Set Vref, RX VrefLevel [Byte0]: 60
3480 01:24:34.937802 [Byte1]: 60
3481 01:24:34.942423
3482 01:24:34.942597 Set Vref, RX VrefLevel [Byte0]: 61
3483 01:24:34.945420 [Byte1]: 61
3484 01:24:34.949978
3485 01:24:34.950145 Set Vref, RX VrefLevel [Byte0]: 62
3486 01:24:34.953450 [Byte1]: 62
3487 01:24:34.957957
3488 01:24:34.958092 Set Vref, RX VrefLevel [Byte0]: 63
3489 01:24:34.961076 [Byte1]: 63
3490 01:24:34.965929
3491 01:24:34.966034 Set Vref, RX VrefLevel [Byte0]: 64
3492 01:24:34.969008 [Byte1]: 64
3493 01:24:34.973848
3494 01:24:34.973952 Set Vref, RX VrefLevel [Byte0]: 65
3495 01:24:34.977064 [Byte1]: 65
3496 01:24:34.981648
3497 01:24:34.981754 Set Vref, RX VrefLevel [Byte0]: 66
3498 01:24:34.984975 [Byte1]: 66
3499 01:24:34.989705
3500 01:24:34.989787 Final RX Vref Byte 0 = 51 to rank0
3501 01:24:34.993211 Final RX Vref Byte 1 = 53 to rank0
3502 01:24:34.996645 Final RX Vref Byte 0 = 51 to rank1
3503 01:24:35.000481 Final RX Vref Byte 1 = 53 to rank1==
3504 01:24:35.003492 Dram Type= 6, Freq= 0, CH_1, rank 0
3505 01:24:35.009880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3506 01:24:35.010304 ==
3507 01:24:35.010634 DQS Delay:
3508 01:24:35.013295 DQS0 = 0, DQS1 = 0
3509 01:24:35.014013 DQM Delay:
3510 01:24:35.014500 DQM0 = 116, DQM1 = 110
3511 01:24:35.016380 DQ Delay:
3512 01:24:35.020103 DQ0 =120, DQ1 =110, DQ2 =110, DQ3 =110
3513 01:24:35.023067 DQ4 =114, DQ5 =128, DQ6 =126, DQ7 =112
3514 01:24:35.026423 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =100
3515 01:24:35.029548 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3516 01:24:35.029913
3517 01:24:35.030197
3518 01:24:35.039385 [DQSOSCAuto] RK0, (LSB)MR18= 0xfdf1, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 411 ps
3519 01:24:35.039570 CH1 RK0: MR19=303, MR18=FDF1
3520 01:24:35.046209 CH1_RK0: MR19=0x303, MR18=0xFDF1, DQSOSC=411, MR23=63, INC=38, DEC=25
3521 01:24:35.046362
3522 01:24:35.049423 ----->DramcWriteLeveling(PI) begin...
3523 01:24:35.049553 ==
3524 01:24:35.052887 Dram Type= 6, Freq= 0, CH_1, rank 1
3525 01:24:35.059172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3526 01:24:35.059293 ==
3527 01:24:35.062476 Write leveling (Byte 0): 24 => 24
3528 01:24:35.065792 Write leveling (Byte 1): 27 => 27
3529 01:24:35.065905 DramcWriteLeveling(PI) end<-----
3530 01:24:35.065994
3531 01:24:35.069186 ==
3532 01:24:35.072773 Dram Type= 6, Freq= 0, CH_1, rank 1
3533 01:24:35.075782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3534 01:24:35.075898 ==
3535 01:24:35.079369 [Gating] SW mode calibration
3536 01:24:35.086255 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3537 01:24:35.089211 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3538 01:24:35.095972 0 15 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3539 01:24:35.099369 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3540 01:24:35.102908 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3541 01:24:35.109546 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3542 01:24:35.112357 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3543 01:24:35.115918 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3544 01:24:35.122448 0 15 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3545 01:24:35.125513 0 15 28 | B1->B0 | 2727 2c2c | 0 0 | (0 0) (1 0)
3546 01:24:35.128756 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3547 01:24:35.135506 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3548 01:24:35.138885 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3549 01:24:35.141824 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3550 01:24:35.148796 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3551 01:24:35.152001 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3552 01:24:35.155552 1 0 24 | B1->B0 | 3838 2626 | 1 0 | (0 0) (0 0)
3553 01:24:35.161610 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3554 01:24:35.164948 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3555 01:24:35.168217 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3556 01:24:35.174630 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3557 01:24:35.178728 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3558 01:24:35.181628 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3559 01:24:35.188304 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3560 01:24:35.191179 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3561 01:24:35.194547 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3562 01:24:35.201142 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 01:24:35.204482 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 01:24:35.207968 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 01:24:35.214705 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 01:24:35.217514 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3567 01:24:35.220942 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3568 01:24:35.228023 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3569 01:24:35.231215 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3570 01:24:35.234470 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3571 01:24:35.240771 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 01:24:35.244146 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3573 01:24:35.247950 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3574 01:24:35.254223 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3575 01:24:35.257233 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3576 01:24:35.260675 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3577 01:24:35.267003 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3578 01:24:35.270713 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3579 01:24:35.273706 Total UI for P1: 0, mck2ui 16
3580 01:24:35.276831 best dqsien dly found for B0: ( 1, 3, 26)
3581 01:24:35.280846 Total UI for P1: 0, mck2ui 16
3582 01:24:35.284143 best dqsien dly found for B1: ( 1, 3, 26)
3583 01:24:35.287850 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3584 01:24:35.291003 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3585 01:24:35.291579
3586 01:24:35.294055 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3587 01:24:35.300453 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3588 01:24:35.301030 [Gating] SW calibration Done
3589 01:24:35.301603 ==
3590 01:24:35.304004 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 01:24:35.310105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 01:24:35.310670 ==
3593 01:24:35.311157 RX Vref Scan: 0
3594 01:24:35.311608
3595 01:24:35.313710 RX Vref 0 -> 0, step: 1
3596 01:24:35.314205
3597 01:24:35.316623 RX Delay -40 -> 252, step: 8
3598 01:24:35.321444 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3599 01:24:35.323180 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3600 01:24:35.326912 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3601 01:24:35.333220 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3602 01:24:35.337160 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3603 01:24:35.339846 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3604 01:24:35.343139 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3605 01:24:35.346604 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3606 01:24:35.353111 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3607 01:24:35.356529 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3608 01:24:35.359829 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3609 01:24:35.363036 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3610 01:24:35.366277 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3611 01:24:35.372827 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3612 01:24:35.376252 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3613 01:24:35.379115 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3614 01:24:35.379694 ==
3615 01:24:35.382580 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 01:24:35.389384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 01:24:35.389975 ==
3618 01:24:35.390463 DQS Delay:
3619 01:24:35.390917 DQS0 = 0, DQS1 = 0
3620 01:24:35.392349 DQM Delay:
3621 01:24:35.392824 DQM0 = 116, DQM1 = 109
3622 01:24:35.395918 DQ Delay:
3623 01:24:35.399186 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3624 01:24:35.402425 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3625 01:24:35.405868 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3626 01:24:35.408804 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3627 01:24:35.409284
3628 01:24:35.409791
3629 01:24:35.410245 ==
3630 01:24:35.412016 Dram Type= 6, Freq= 0, CH_1, rank 1
3631 01:24:35.415200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3632 01:24:35.418556 ==
3633 01:24:35.419008
3634 01:24:35.419408
3635 01:24:35.419744 TX Vref Scan disable
3636 01:24:35.421821 == TX Byte 0 ==
3637 01:24:35.425163 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3638 01:24:35.428788 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3639 01:24:35.432021 == TX Byte 1 ==
3640 01:24:35.435150 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3641 01:24:35.438388 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3642 01:24:35.441875 ==
3643 01:24:35.444696 Dram Type= 6, Freq= 0, CH_1, rank 1
3644 01:24:35.448685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3645 01:24:35.449239 ==
3646 01:24:35.459556 TX Vref=22, minBit 8, minWin=25, winSum=422
3647 01:24:35.463148 TX Vref=24, minBit 4, minWin=26, winSum=428
3648 01:24:35.466261 TX Vref=26, minBit 3, minWin=26, winSum=430
3649 01:24:35.469133 TX Vref=28, minBit 8, minWin=26, winSum=432
3650 01:24:35.473058 TX Vref=30, minBit 7, minWin=26, winSum=435
3651 01:24:35.479783 TX Vref=32, minBit 8, minWin=26, winSum=433
3652 01:24:35.482667 [TxChooseVref] Worse bit 7, Min win 26, Win sum 435, Final Vref 30
3653 01:24:35.483219
3654 01:24:35.485881 Final TX Range 1 Vref 30
3655 01:24:35.486448
3656 01:24:35.486813 ==
3657 01:24:35.489376 Dram Type= 6, Freq= 0, CH_1, rank 1
3658 01:24:35.492193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3659 01:24:35.495613 ==
3660 01:24:35.496161
3661 01:24:35.496522
3662 01:24:35.496852 TX Vref Scan disable
3663 01:24:35.499200 == TX Byte 0 ==
3664 01:24:35.502117 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3665 01:24:35.509169 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3666 01:24:35.509768 == TX Byte 1 ==
3667 01:24:35.512060 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3668 01:24:35.518412 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3669 01:24:35.518936
3670 01:24:35.519302 [DATLAT]
3671 01:24:35.519645 Freq=1200, CH1 RK1
3672 01:24:35.521864
3673 01:24:35.522321 DATLAT Default: 0xd
3674 01:24:35.525411 0, 0xFFFF, sum = 0
3675 01:24:35.525881 1, 0xFFFF, sum = 0
3676 01:24:35.528458 2, 0xFFFF, sum = 0
3677 01:24:35.528923 3, 0xFFFF, sum = 0
3678 01:24:35.532034 4, 0xFFFF, sum = 0
3679 01:24:35.532633 5, 0xFFFF, sum = 0
3680 01:24:35.535493 6, 0xFFFF, sum = 0
3681 01:24:35.536065 7, 0xFFFF, sum = 0
3682 01:24:35.538190 8, 0xFFFF, sum = 0
3683 01:24:35.538657 9, 0xFFFF, sum = 0
3684 01:24:35.541406 10, 0xFFFF, sum = 0
3685 01:24:35.541885 11, 0xFFFF, sum = 0
3686 01:24:35.545015 12, 0x0, sum = 1
3687 01:24:35.545534 13, 0x0, sum = 2
3688 01:24:35.548408 14, 0x0, sum = 3
3689 01:24:35.548992 15, 0x0, sum = 4
3690 01:24:35.552303 best_step = 13
3691 01:24:35.552864
3692 01:24:35.553227 ==
3693 01:24:35.554975 Dram Type= 6, Freq= 0, CH_1, rank 1
3694 01:24:35.558012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3695 01:24:35.558622 ==
3696 01:24:35.561148 RX Vref Scan: 0
3697 01:24:35.561629
3698 01:24:35.561995 RX Vref 0 -> 0, step: 1
3699 01:24:35.562336
3700 01:24:35.565012 RX Delay -21 -> 252, step: 4
3701 01:24:35.571938 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3702 01:24:35.575091 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3703 01:24:35.578055 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3704 01:24:35.581290 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3705 01:24:35.587990 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3706 01:24:35.591071 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3707 01:24:35.594278 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3708 01:24:35.597559 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3709 01:24:35.601201 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3710 01:24:35.608056 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3711 01:24:35.611549 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3712 01:24:35.613929 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3713 01:24:35.617642 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3714 01:24:35.620917 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3715 01:24:35.627590 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3716 01:24:35.630708 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3717 01:24:35.631276 ==
3718 01:24:35.634115 Dram Type= 6, Freq= 0, CH_1, rank 1
3719 01:24:35.637587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3720 01:24:35.638148 ==
3721 01:24:35.641036 DQS Delay:
3722 01:24:35.641735 DQS0 = 0, DQS1 = 0
3723 01:24:35.642189 DQM Delay:
3724 01:24:35.643696 DQM0 = 117, DQM1 = 110
3725 01:24:35.644149 DQ Delay:
3726 01:24:35.647104 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3727 01:24:35.650457 DQ4 =114, DQ5 =128, DQ6 =130, DQ7 =116
3728 01:24:35.657255 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =100
3729 01:24:35.660100 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =118
3730 01:24:35.660549
3731 01:24:35.660898
3732 01:24:35.666897 [DQSOSCAuto] RK1, (LSB)MR18= 0xf2ed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3733 01:24:35.670101 CH1 RK1: MR19=303, MR18=F2ED
3734 01:24:35.676966 CH1_RK1: MR19=0x303, MR18=0xF2ED, DQSOSC=415, MR23=63, INC=38, DEC=25
3735 01:24:35.680545 [RxdqsGatingPostProcess] freq 1200
3736 01:24:35.686658 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3737 01:24:35.687411 best DQS0 dly(2T, 0.5T) = (0, 11)
3738 01:24:35.689912 best DQS1 dly(2T, 0.5T) = (0, 11)
3739 01:24:35.692821 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3740 01:24:35.696356 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3741 01:24:35.699805 best DQS0 dly(2T, 0.5T) = (0, 11)
3742 01:24:35.703069 best DQS1 dly(2T, 0.5T) = (0, 11)
3743 01:24:35.706228 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3744 01:24:35.709989 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3745 01:24:35.713280 Pre-setting of DQS Precalculation
3746 01:24:35.719425 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3747 01:24:35.726249 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3748 01:24:35.732804 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3749 01:24:35.733414
3750 01:24:35.733791
3751 01:24:35.735520 [Calibration Summary] 2400 Mbps
3752 01:24:35.735979 CH 0, Rank 0
3753 01:24:35.739073 SW Impedance : PASS
3754 01:24:35.742403 DUTY Scan : NO K
3755 01:24:35.742970 ZQ Calibration : PASS
3756 01:24:35.745855 Jitter Meter : NO K
3757 01:24:35.748868 CBT Training : PASS
3758 01:24:35.749358 Write leveling : PASS
3759 01:24:35.752135 RX DQS gating : PASS
3760 01:24:35.755999 RX DQ/DQS(RDDQC) : PASS
3761 01:24:35.756574 TX DQ/DQS : PASS
3762 01:24:35.759291 RX DATLAT : PASS
3763 01:24:35.762276 RX DQ/DQS(Engine): PASS
3764 01:24:35.762769 TX OE : NO K
3765 01:24:35.765747 All Pass.
3766 01:24:35.766305
3767 01:24:35.766671 CH 0, Rank 1
3768 01:24:35.769091 SW Impedance : PASS
3769 01:24:35.769703 DUTY Scan : NO K
3770 01:24:35.772313 ZQ Calibration : PASS
3771 01:24:35.775658 Jitter Meter : NO K
3772 01:24:35.776206 CBT Training : PASS
3773 01:24:35.778708 Write leveling : PASS
3774 01:24:35.781698 RX DQS gating : PASS
3775 01:24:35.782154 RX DQ/DQS(RDDQC) : PASS
3776 01:24:35.785386 TX DQ/DQS : PASS
3777 01:24:35.788706 RX DATLAT : PASS
3778 01:24:35.789253 RX DQ/DQS(Engine): PASS
3779 01:24:35.791764 TX OE : NO K
3780 01:24:35.792313 All Pass.
3781 01:24:35.792679
3782 01:24:35.795804 CH 1, Rank 0
3783 01:24:35.796362 SW Impedance : PASS
3784 01:24:35.798550 DUTY Scan : NO K
3785 01:24:35.801861 ZQ Calibration : PASS
3786 01:24:35.802413 Jitter Meter : NO K
3787 01:24:35.804894 CBT Training : PASS
3788 01:24:35.805403 Write leveling : PASS
3789 01:24:35.808117 RX DQS gating : PASS
3790 01:24:35.812054 RX DQ/DQS(RDDQC) : PASS
3791 01:24:35.812605 TX DQ/DQS : PASS
3792 01:24:35.814785 RX DATLAT : PASS
3793 01:24:35.818001 RX DQ/DQS(Engine): PASS
3794 01:24:35.818463 TX OE : NO K
3795 01:24:35.821509 All Pass.
3796 01:24:35.822115
3797 01:24:35.822526 CH 1, Rank 1
3798 01:24:35.825121 SW Impedance : PASS
3799 01:24:35.825623 DUTY Scan : NO K
3800 01:24:35.828683 ZQ Calibration : PASS
3801 01:24:35.831373 Jitter Meter : NO K
3802 01:24:35.831921 CBT Training : PASS
3803 01:24:35.834567 Write leveling : PASS
3804 01:24:35.837823 RX DQS gating : PASS
3805 01:24:35.838286 RX DQ/DQS(RDDQC) : PASS
3806 01:24:35.841154 TX DQ/DQS : PASS
3807 01:24:35.844133 RX DATLAT : PASS
3808 01:24:35.844592 RX DQ/DQS(Engine): PASS
3809 01:24:35.847403 TX OE : NO K
3810 01:24:35.847864 All Pass.
3811 01:24:35.848227
3812 01:24:35.850663 DramC Write-DBI off
3813 01:24:35.854248 PER_BANK_REFRESH: Hybrid Mode
3814 01:24:35.854814 TX_TRACKING: ON
3815 01:24:35.864213 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3816 01:24:35.867965 [FAST_K] Save calibration result to emmc
3817 01:24:35.871289 dramc_set_vcore_voltage set vcore to 650000
3818 01:24:35.874242 Read voltage for 600, 5
3819 01:24:35.874811 Vio18 = 0
3820 01:24:35.875178 Vcore = 650000
3821 01:24:35.877187 Vdram = 0
3822 01:24:35.877697 Vddq = 0
3823 01:24:35.878062 Vmddr = 0
3824 01:24:35.884312 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3825 01:24:35.887541 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3826 01:24:35.890376 MEM_TYPE=3, freq_sel=19
3827 01:24:35.894064 sv_algorithm_assistance_LP4_1600
3828 01:24:35.897301 ============ PULL DRAM RESETB DOWN ============
3829 01:24:35.903876 ========== PULL DRAM RESETB DOWN end =========
3830 01:24:35.907318 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3831 01:24:35.910107 ===================================
3832 01:24:35.913785 LPDDR4 DRAM CONFIGURATION
3833 01:24:35.917195 ===================================
3834 01:24:35.917973 EX_ROW_EN[0] = 0x0
3835 01:24:35.919806 EX_ROW_EN[1] = 0x0
3836 01:24:35.920263 LP4Y_EN = 0x0
3837 01:24:35.923355 WORK_FSP = 0x0
3838 01:24:35.923862 WL = 0x2
3839 01:24:35.926745 RL = 0x2
3840 01:24:35.927158 BL = 0x2
3841 01:24:35.929984 RPST = 0x0
3842 01:24:35.932908 RD_PRE = 0x0
3843 01:24:35.933393 WR_PRE = 0x1
3844 01:24:35.936369 WR_PST = 0x0
3845 01:24:35.936922 DBI_WR = 0x0
3846 01:24:35.939573 DBI_RD = 0x0
3847 01:24:35.940128 OTF = 0x1
3848 01:24:35.942886 ===================================
3849 01:24:35.946162 ===================================
3850 01:24:35.949991 ANA top config
3851 01:24:35.952994 ===================================
3852 01:24:35.953590 DLL_ASYNC_EN = 0
3853 01:24:35.956318 ALL_SLAVE_EN = 1
3854 01:24:35.959812 NEW_RANK_MODE = 1
3855 01:24:35.962742 DLL_IDLE_MODE = 1
3856 01:24:35.963308 LP45_APHY_COMB_EN = 1
3857 01:24:35.966853 TX_ODT_DIS = 1
3858 01:24:35.969442 NEW_8X_MODE = 1
3859 01:24:35.972775 ===================================
3860 01:24:35.975879 ===================================
3861 01:24:35.979261 data_rate = 1200
3862 01:24:35.982885 CKR = 1
3863 01:24:35.986135 DQ_P2S_RATIO = 8
3864 01:24:35.989356 ===================================
3865 01:24:35.989775 CA_P2S_RATIO = 8
3866 01:24:35.992882 DQ_CA_OPEN = 0
3867 01:24:35.996066 DQ_SEMI_OPEN = 0
3868 01:24:35.999411 CA_SEMI_OPEN = 0
3869 01:24:36.002238 CA_FULL_RATE = 0
3870 01:24:36.005898 DQ_CKDIV4_EN = 1
3871 01:24:36.009068 CA_CKDIV4_EN = 1
3872 01:24:36.009762 CA_PREDIV_EN = 0
3873 01:24:36.012204 PH8_DLY = 0
3874 01:24:36.015699 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3875 01:24:36.018702 DQ_AAMCK_DIV = 4
3876 01:24:36.022174 CA_AAMCK_DIV = 4
3877 01:24:36.025151 CA_ADMCK_DIV = 4
3878 01:24:36.025657 DQ_TRACK_CA_EN = 0
3879 01:24:36.028860 CA_PICK = 600
3880 01:24:36.032335 CA_MCKIO = 600
3881 01:24:36.035535 MCKIO_SEMI = 0
3882 01:24:36.038620 PLL_FREQ = 2288
3883 01:24:36.041698 DQ_UI_PI_RATIO = 32
3884 01:24:36.045220 CA_UI_PI_RATIO = 0
3885 01:24:36.048210 ===================================
3886 01:24:36.051675 ===================================
3887 01:24:36.052139 memory_type:LPDDR4
3888 01:24:36.055077 GP_NUM : 10
3889 01:24:36.058269 SRAM_EN : 1
3890 01:24:36.058727 MD32_EN : 0
3891 01:24:36.061711 ===================================
3892 01:24:36.064901 [ANA_INIT] >>>>>>>>>>>>>>
3893 01:24:36.068044 <<<<<< [CONFIGURE PHASE]: ANA_TX
3894 01:24:36.071732 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3895 01:24:36.075024 ===================================
3896 01:24:36.077683 data_rate = 1200,PCW = 0X5800
3897 01:24:36.081537 ===================================
3898 01:24:36.084781 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3899 01:24:36.088299 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3900 01:24:36.094694 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3901 01:24:36.098300 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3902 01:24:36.104537 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3903 01:24:36.107388 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3904 01:24:36.107851 [ANA_INIT] flow start
3905 01:24:36.111445 [ANA_INIT] PLL >>>>>>>>
3906 01:24:36.113915 [ANA_INIT] PLL <<<<<<<<
3907 01:24:36.114378 [ANA_INIT] MIDPI >>>>>>>>
3908 01:24:36.117516 [ANA_INIT] MIDPI <<<<<<<<
3909 01:24:36.120695 [ANA_INIT] DLL >>>>>>>>
3910 01:24:36.121389 [ANA_INIT] flow end
3911 01:24:36.127927 ============ LP4 DIFF to SE enter ============
3912 01:24:36.130741 ============ LP4 DIFF to SE exit ============
3913 01:24:36.131301 [ANA_INIT] <<<<<<<<<<<<<
3914 01:24:36.133925 [Flow] Enable top DCM control >>>>>
3915 01:24:36.137210 [Flow] Enable top DCM control <<<<<
3916 01:24:36.140364 Enable DLL master slave shuffle
3917 01:24:36.147112 ==============================================================
3918 01:24:36.150466 Gating Mode config
3919 01:24:36.153652 ==============================================================
3920 01:24:36.156919 Config description:
3921 01:24:36.167000 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3922 01:24:36.173097 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3923 01:24:36.176563 SELPH_MODE 0: By rank 1: By Phase
3924 01:24:36.183133 ==============================================================
3925 01:24:36.186269 GAT_TRACK_EN = 1
3926 01:24:36.189857 RX_GATING_MODE = 2
3927 01:24:36.193165 RX_GATING_TRACK_MODE = 2
3928 01:24:36.196392 SELPH_MODE = 1
3929 01:24:36.199516 PICG_EARLY_EN = 1
3930 01:24:36.200052 VALID_LAT_VALUE = 1
3931 01:24:36.206445 ==============================================================
3932 01:24:36.209919 Enter into Gating configuration >>>>
3933 01:24:36.213521 Exit from Gating configuration <<<<
3934 01:24:36.216440 Enter into DVFS_PRE_config >>>>>
3935 01:24:36.226615 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3936 01:24:36.229145 Exit from DVFS_PRE_config <<<<<
3937 01:24:36.232754 Enter into PICG configuration >>>>
3938 01:24:36.236022 Exit from PICG configuration <<<<
3939 01:24:36.239365 [RX_INPUT] configuration >>>>>
3940 01:24:36.242690 [RX_INPUT] configuration <<<<<
3941 01:24:36.249374 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3942 01:24:36.252525 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3943 01:24:36.258916 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3944 01:24:36.265425 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3945 01:24:36.272214 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3946 01:24:36.278560 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3947 01:24:36.282292 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3948 01:24:36.285204 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3949 01:24:36.288278 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3950 01:24:36.295167 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3951 01:24:36.298493 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3952 01:24:36.301594 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3953 01:24:36.304796 ===================================
3954 01:24:36.308481 LPDDR4 DRAM CONFIGURATION
3955 01:24:36.311476 ===================================
3956 01:24:36.315219 EX_ROW_EN[0] = 0x0
3957 01:24:36.315628 EX_ROW_EN[1] = 0x0
3958 01:24:36.318155 LP4Y_EN = 0x0
3959 01:24:36.318568 WORK_FSP = 0x0
3960 01:24:36.321165 WL = 0x2
3961 01:24:36.321797 RL = 0x2
3962 01:24:36.324500 BL = 0x2
3963 01:24:36.325042 RPST = 0x0
3964 01:24:36.327926 RD_PRE = 0x0
3965 01:24:36.328545 WR_PRE = 0x1
3966 01:24:36.331018 WR_PST = 0x0
3967 01:24:36.331430 DBI_WR = 0x0
3968 01:24:36.334361 DBI_RD = 0x0
3969 01:24:36.337695 OTF = 0x1
3970 01:24:36.341296 ===================================
3971 01:24:36.344062 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3972 01:24:36.347297 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3973 01:24:36.351158 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3974 01:24:36.354524 ===================================
3975 01:24:36.357712 LPDDR4 DRAM CONFIGURATION
3976 01:24:36.360810 ===================================
3977 01:24:36.363820 EX_ROW_EN[0] = 0x10
3978 01:24:36.364234 EX_ROW_EN[1] = 0x0
3979 01:24:36.367979 LP4Y_EN = 0x0
3980 01:24:36.368489 WORK_FSP = 0x0
3981 01:24:36.370820 WL = 0x2
3982 01:24:36.371330 RL = 0x2
3983 01:24:36.373925 BL = 0x2
3984 01:24:36.374335 RPST = 0x0
3985 01:24:36.377257 RD_PRE = 0x0
3986 01:24:36.380270 WR_PRE = 0x1
3987 01:24:36.380679 WR_PST = 0x0
3988 01:24:36.384227 DBI_WR = 0x0
3989 01:24:36.384751 DBI_RD = 0x0
3990 01:24:36.386792 OTF = 0x1
3991 01:24:36.390398 ===================================
3992 01:24:36.394340 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3993 01:24:36.399002 nWR fixed to 30
3994 01:24:36.402678 [ModeRegInit_LP4] CH0 RK0
3995 01:24:36.403219 [ModeRegInit_LP4] CH0 RK1
3996 01:24:36.405663 [ModeRegInit_LP4] CH1 RK0
3997 01:24:36.408927 [ModeRegInit_LP4] CH1 RK1
3998 01:24:36.409362 match AC timing 17
3999 01:24:36.415462 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4000 01:24:36.418812 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4001 01:24:36.421841 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4002 01:24:36.428299 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4003 01:24:36.431876 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4004 01:24:36.432386 ==
4005 01:24:36.434821 Dram Type= 6, Freq= 0, CH_0, rank 0
4006 01:24:36.438093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4007 01:24:36.441937 ==
4008 01:24:36.445027 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4009 01:24:36.451527 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4010 01:24:36.454945 [CA 0] Center 36 (6~66) winsize 61
4011 01:24:36.458199 [CA 1] Center 36 (6~66) winsize 61
4012 01:24:36.461257 [CA 2] Center 34 (4~65) winsize 62
4013 01:24:36.464847 [CA 3] Center 34 (4~65) winsize 62
4014 01:24:36.468030 [CA 4] Center 33 (3~64) winsize 62
4015 01:24:36.470975 [CA 5] Center 33 (3~64) winsize 62
4016 01:24:36.471514
4017 01:24:36.474710 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4018 01:24:36.475223
4019 01:24:36.478089 [CATrainingPosCal] consider 1 rank data
4020 01:24:36.480970 u2DelayCellTimex100 = 270/100 ps
4021 01:24:36.484332 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4022 01:24:36.487402 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4023 01:24:36.494311 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4024 01:24:36.497626 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4025 01:24:36.501082 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4026 01:24:36.504113 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4027 01:24:36.504632
4028 01:24:36.507139 CA PerBit enable=1, Macro0, CA PI delay=33
4029 01:24:36.507608
4030 01:24:36.510467 [CBTSetCACLKResult] CA Dly = 33
4031 01:24:36.510981 CS Dly: 4 (0~35)
4032 01:24:36.513868 ==
4033 01:24:36.517083 Dram Type= 6, Freq= 0, CH_0, rank 1
4034 01:24:36.520568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4035 01:24:36.521164 ==
4036 01:24:36.523571 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4037 01:24:36.530285 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4038 01:24:36.534126 [CA 0] Center 35 (5~66) winsize 62
4039 01:24:36.537952 [CA 1] Center 36 (6~66) winsize 61
4040 01:24:36.540828 [CA 2] Center 34 (4~65) winsize 62
4041 01:24:36.544067 [CA 3] Center 34 (4~64) winsize 61
4042 01:24:36.547857 [CA 4] Center 33 (3~64) winsize 62
4043 01:24:36.551789 [CA 5] Center 33 (2~64) winsize 63
4044 01:24:36.552349
4045 01:24:36.554357 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4046 01:24:36.554816
4047 01:24:36.557781 [CATrainingPosCal] consider 2 rank data
4048 01:24:36.561170 u2DelayCellTimex100 = 270/100 ps
4049 01:24:36.567553 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4050 01:24:36.570419 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4051 01:24:36.573452 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4052 01:24:36.576975 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4053 01:24:36.580150 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4054 01:24:36.583876 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4055 01:24:36.584561
4056 01:24:36.586889 CA PerBit enable=1, Macro0, CA PI delay=33
4057 01:24:36.587351
4058 01:24:36.590038 [CBTSetCACLKResult] CA Dly = 33
4059 01:24:36.594032 CS Dly: 5 (0~37)
4060 01:24:36.594579
4061 01:24:36.597015 ----->DramcWriteLeveling(PI) begin...
4062 01:24:36.597612 ==
4063 01:24:36.600738 Dram Type= 6, Freq= 0, CH_0, rank 0
4064 01:24:36.603595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4065 01:24:36.604144 ==
4066 01:24:36.606869 Write leveling (Byte 0): 32 => 32
4067 01:24:36.610098 Write leveling (Byte 1): 31 => 31
4068 01:24:36.613257 DramcWriteLeveling(PI) end<-----
4069 01:24:36.613858
4070 01:24:36.614227 ==
4071 01:24:36.616550 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 01:24:36.619591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 01:24:36.620055 ==
4074 01:24:36.622919 [Gating] SW mode calibration
4075 01:24:36.629481 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4076 01:24:36.636537 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4077 01:24:36.639468 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4078 01:24:36.646598 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4079 01:24:36.649494 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4080 01:24:36.652918 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
4081 01:24:36.658881 0 9 16 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
4082 01:24:36.662334 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4083 01:24:36.665501 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4084 01:24:36.672362 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4085 01:24:36.675747 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4086 01:24:36.678968 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4087 01:24:36.685758 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4088 01:24:36.688832 0 10 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
4089 01:24:36.691786 0 10 16 | B1->B0 | 3333 4545 | 0 0 | (1 1) (0 0)
4090 01:24:36.698424 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4091 01:24:36.702316 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4092 01:24:36.705319 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4093 01:24:36.712166 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4094 01:24:36.715241 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4095 01:24:36.718624 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4096 01:24:36.725172 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4097 01:24:36.728566 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4098 01:24:36.731534 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 01:24:36.738356 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 01:24:36.741608 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 01:24:36.744718 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 01:24:36.751188 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 01:24:36.754428 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4104 01:24:36.758006 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 01:24:36.764634 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 01:24:36.768050 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4107 01:24:36.771222 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 01:24:36.778283 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 01:24:36.781450 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 01:24:36.784573 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4111 01:24:36.791199 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4112 01:24:36.794041 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4113 01:24:36.797663 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4114 01:24:36.804166 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4115 01:24:36.804747 Total UI for P1: 0, mck2ui 16
4116 01:24:36.810837 best dqsien dly found for B0: ( 0, 13, 16)
4117 01:24:36.811403 Total UI for P1: 0, mck2ui 16
4118 01:24:36.817602 best dqsien dly found for B1: ( 0, 13, 16)
4119 01:24:36.820548 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4120 01:24:36.823602 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4121 01:24:36.824061
4122 01:24:36.826867 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4123 01:24:36.830829 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4124 01:24:36.834030 [Gating] SW calibration Done
4125 01:24:36.834590 ==
4126 01:24:36.837287 Dram Type= 6, Freq= 0, CH_0, rank 0
4127 01:24:36.840205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 01:24:36.840765 ==
4129 01:24:36.843242 RX Vref Scan: 0
4130 01:24:36.843698
4131 01:24:36.844059 RX Vref 0 -> 0, step: 1
4132 01:24:36.847152
4133 01:24:36.847788 RX Delay -230 -> 252, step: 16
4134 01:24:36.853481 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4135 01:24:36.856899 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4136 01:24:36.860038 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4137 01:24:36.863341 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4138 01:24:36.870240 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4139 01:24:36.873721 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4140 01:24:36.876686 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4141 01:24:36.879590 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4142 01:24:36.883268 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4143 01:24:36.890299 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4144 01:24:36.892805 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4145 01:24:36.896260 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4146 01:24:36.899511 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4147 01:24:36.906539 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4148 01:24:36.909460 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4149 01:24:36.913129 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4150 01:24:36.913739 ==
4151 01:24:36.916409 Dram Type= 6, Freq= 0, CH_0, rank 0
4152 01:24:36.919533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 01:24:36.922757 ==
4154 01:24:36.923273 DQS Delay:
4155 01:24:36.923885 DQS0 = 0, DQS1 = 0
4156 01:24:36.925878 DQM Delay:
4157 01:24:36.926344 DQM0 = 42, DQM1 = 30
4158 01:24:36.929383 DQ Delay:
4159 01:24:36.932860 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4160 01:24:36.933480 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4161 01:24:36.936600 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4162 01:24:36.943054 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4163 01:24:36.943681
4164 01:24:36.944059
4165 01:24:36.944398 ==
4166 01:24:36.945930 Dram Type= 6, Freq= 0, CH_0, rank 0
4167 01:24:36.949474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 01:24:36.950029 ==
4169 01:24:36.950463
4170 01:24:36.950811
4171 01:24:36.952563 TX Vref Scan disable
4172 01:24:36.953014 == TX Byte 0 ==
4173 01:24:36.958965 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4174 01:24:36.962465 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4175 01:24:36.963022 == TX Byte 1 ==
4176 01:24:36.969161 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4177 01:24:36.972102 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4178 01:24:36.972818 ==
4179 01:24:36.975539 Dram Type= 6, Freq= 0, CH_0, rank 0
4180 01:24:36.978879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4181 01:24:36.979335 ==
4182 01:24:36.982129
4183 01:24:36.982581
4184 01:24:36.982940 TX Vref Scan disable
4185 01:24:36.985535 == TX Byte 0 ==
4186 01:24:36.988626 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4187 01:24:36.995778 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4188 01:24:36.996431 == TX Byte 1 ==
4189 01:24:36.998524 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4190 01:24:37.005364 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4191 01:24:37.005930
4192 01:24:37.006344 [DATLAT]
4193 01:24:37.006692 Freq=600, CH0 RK0
4194 01:24:37.007015
4195 01:24:37.008703 DATLAT Default: 0x9
4196 01:24:37.011749 0, 0xFFFF, sum = 0
4197 01:24:37.012213 1, 0xFFFF, sum = 0
4198 01:24:37.016061 2, 0xFFFF, sum = 0
4199 01:24:37.016632 3, 0xFFFF, sum = 0
4200 01:24:37.018375 4, 0xFFFF, sum = 0
4201 01:24:37.018933 5, 0xFFFF, sum = 0
4202 01:24:37.021869 6, 0xFFFF, sum = 0
4203 01:24:37.022396 7, 0xFFFF, sum = 0
4204 01:24:37.025220 8, 0x0, sum = 1
4205 01:24:37.025730 9, 0x0, sum = 2
4206 01:24:37.028340 10, 0x0, sum = 3
4207 01:24:37.028801 11, 0x0, sum = 4
4208 01:24:37.029166 best_step = 9
4209 01:24:37.029562
4210 01:24:37.031758 ==
4211 01:24:37.035125 Dram Type= 6, Freq= 0, CH_0, rank 0
4212 01:24:37.038186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4213 01:24:37.038678 ==
4214 01:24:37.039044 RX Vref Scan: 1
4215 01:24:37.039384
4216 01:24:37.041722 RX Vref 0 -> 0, step: 1
4217 01:24:37.042177
4218 01:24:37.044900 RX Delay -195 -> 252, step: 8
4219 01:24:37.045378
4220 01:24:37.048672 Set Vref, RX VrefLevel [Byte0]: 65
4221 01:24:37.051851 [Byte1]: 49
4222 01:24:37.052409
4223 01:24:37.054914 Final RX Vref Byte 0 = 65 to rank0
4224 01:24:37.058420 Final RX Vref Byte 1 = 49 to rank0
4225 01:24:37.061115 Final RX Vref Byte 0 = 65 to rank1
4226 01:24:37.064639 Final RX Vref Byte 1 = 49 to rank1==
4227 01:24:37.068234 Dram Type= 6, Freq= 0, CH_0, rank 0
4228 01:24:37.074686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 01:24:37.075253 ==
4230 01:24:37.075623 DQS Delay:
4231 01:24:37.075958 DQS0 = 0, DQS1 = 0
4232 01:24:37.077447 DQM Delay:
4233 01:24:37.077900 DQM0 = 44, DQM1 = 32
4234 01:24:37.080910 DQ Delay:
4235 01:24:37.084297 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4236 01:24:37.087712 DQ4 =48, DQ5 =36, DQ6 =48, DQ7 =52
4237 01:24:37.090997 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =24
4238 01:24:37.094182 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4239 01:24:37.094637
4240 01:24:37.094997
4241 01:24:37.100752 [DQSOSCAuto] RK0, (LSB)MR18= 0x5e36, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
4242 01:24:37.103945 CH0 RK0: MR19=808, MR18=5E36
4243 01:24:37.110867 CH0_RK0: MR19=0x808, MR18=0x5E36, DQSOSC=392, MR23=63, INC=170, DEC=113
4244 01:24:37.111408
4245 01:24:37.114285 ----->DramcWriteLeveling(PI) begin...
4246 01:24:37.114901 ==
4247 01:24:37.117249 Dram Type= 6, Freq= 0, CH_0, rank 1
4248 01:24:37.120738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4249 01:24:37.121387 ==
4250 01:24:37.123813 Write leveling (Byte 0): 35 => 35
4251 01:24:37.127184 Write leveling (Byte 1): 31 => 31
4252 01:24:37.130330 DramcWriteLeveling(PI) end<-----
4253 01:24:37.130873
4254 01:24:37.131237 ==
4255 01:24:37.133284 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 01:24:37.137108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 01:24:37.140671 ==
4258 01:24:37.141221 [Gating] SW mode calibration
4259 01:24:37.150186 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4260 01:24:37.153502 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4261 01:24:37.156791 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4262 01:24:37.163209 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4263 01:24:37.166933 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4264 01:24:37.170200 0 9 12 | B1->B0 | 3333 3232 | 1 1 | (1 0) (1 0)
4265 01:24:37.176736 0 9 16 | B1->B0 | 3030 2929 | 0 0 | (1 1) (0 0)
4266 01:24:37.180105 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4267 01:24:37.183005 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4268 01:24:37.189765 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4269 01:24:37.192655 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4270 01:24:37.195955 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4271 01:24:37.202939 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4272 01:24:37.206046 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4273 01:24:37.212422 0 10 16 | B1->B0 | 3535 3b3b | 1 0 | (0 0) (0 0)
4274 01:24:37.215732 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4275 01:24:37.219328 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4276 01:24:37.225315 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4277 01:24:37.229524 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4278 01:24:37.232376 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4279 01:24:37.238680 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4280 01:24:37.242050 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4281 01:24:37.245134 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 01:24:37.249723 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 01:24:37.255388 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 01:24:37.258861 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 01:24:37.261932 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 01:24:37.268591 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 01:24:37.271878 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 01:24:37.275548 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 01:24:37.281808 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 01:24:37.284996 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 01:24:37.291445 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 01:24:37.294535 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 01:24:37.298283 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 01:24:37.304538 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 01:24:37.308425 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 01:24:37.311164 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4297 01:24:37.317712 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4298 01:24:37.318288 Total UI for P1: 0, mck2ui 16
4299 01:24:37.320945 best dqsien dly found for B0: ( 0, 13, 14)
4300 01:24:37.324065 Total UI for P1: 0, mck2ui 16
4301 01:24:37.327781 best dqsien dly found for B1: ( 0, 13, 12)
4302 01:24:37.334146 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4303 01:24:37.337308 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4304 01:24:37.337825
4305 01:24:37.340465 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4306 01:24:37.344095 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4307 01:24:37.347304 [Gating] SW calibration Done
4308 01:24:37.347779 ==
4309 01:24:37.350513 Dram Type= 6, Freq= 0, CH_0, rank 1
4310 01:24:37.354163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4311 01:24:37.354737 ==
4312 01:24:37.357084 RX Vref Scan: 0
4313 01:24:37.357678
4314 01:24:37.358157 RX Vref 0 -> 0, step: 1
4315 01:24:37.358611
4316 01:24:37.360131 RX Delay -230 -> 252, step: 16
4317 01:24:37.367101 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4318 01:24:37.370552 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4319 01:24:37.373699 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4320 01:24:37.377372 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4321 01:24:37.380170 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4322 01:24:37.387077 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4323 01:24:37.390272 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4324 01:24:37.393465 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4325 01:24:37.396353 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4326 01:24:37.403063 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4327 01:24:37.406592 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4328 01:24:37.409810 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4329 01:24:37.412984 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4330 01:24:37.419745 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4331 01:24:37.422685 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4332 01:24:37.425841 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4333 01:24:37.426305 ==
4334 01:24:37.429515 Dram Type= 6, Freq= 0, CH_0, rank 1
4335 01:24:37.436075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4336 01:24:37.436582 ==
4337 01:24:37.436918 DQS Delay:
4338 01:24:37.439647 DQS0 = 0, DQS1 = 0
4339 01:24:37.440179 DQM Delay:
4340 01:24:37.440744 DQM0 = 41, DQM1 = 36
4341 01:24:37.442353 DQ Delay:
4342 01:24:37.445879 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4343 01:24:37.448951 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4344 01:24:37.452077 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4345 01:24:37.455356 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4346 01:24:37.456035
4347 01:24:37.456442
4348 01:24:37.457063 ==
4349 01:24:37.458773 Dram Type= 6, Freq= 0, CH_0, rank 1
4350 01:24:37.461970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 01:24:37.462392 ==
4352 01:24:37.462741
4353 01:24:37.463163
4354 01:24:37.465626 TX Vref Scan disable
4355 01:24:37.468977 == TX Byte 0 ==
4356 01:24:37.472310 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4357 01:24:37.475810 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4358 01:24:37.478902 == TX Byte 1 ==
4359 01:24:37.481945 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4360 01:24:37.485535 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4361 01:24:37.486068 ==
4362 01:24:37.488677 Dram Type= 6, Freq= 0, CH_0, rank 1
4363 01:24:37.491992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 01:24:37.495237 ==
4365 01:24:37.495684
4366 01:24:37.496009
4367 01:24:37.496313 TX Vref Scan disable
4368 01:24:37.499063 == TX Byte 0 ==
4369 01:24:37.502477 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4370 01:24:37.509185 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4371 01:24:37.509540 == TX Byte 1 ==
4372 01:24:37.512545 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4373 01:24:37.518964 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4374 01:24:37.519270
4375 01:24:37.519454 [DATLAT]
4376 01:24:37.519622 Freq=600, CH0 RK1
4377 01:24:37.519783
4378 01:24:37.522020 DATLAT Default: 0x9
4379 01:24:37.525324 0, 0xFFFF, sum = 0
4380 01:24:37.525662 1, 0xFFFF, sum = 0
4381 01:24:37.528651 2, 0xFFFF, sum = 0
4382 01:24:37.529111 3, 0xFFFF, sum = 0
4383 01:24:37.532069 4, 0xFFFF, sum = 0
4384 01:24:37.532624 5, 0xFFFF, sum = 0
4385 01:24:37.536072 6, 0xFFFF, sum = 0
4386 01:24:37.536629 7, 0xFFFF, sum = 0
4387 01:24:37.539083 8, 0x0, sum = 1
4388 01:24:37.539547 9, 0x0, sum = 2
4389 01:24:37.541829 10, 0x0, sum = 3
4390 01:24:37.542293 11, 0x0, sum = 4
4391 01:24:37.542656 best_step = 9
4392 01:24:37.542989
4393 01:24:37.545029 ==
4394 01:24:37.548851 Dram Type= 6, Freq= 0, CH_0, rank 1
4395 01:24:37.552119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 01:24:37.552576 ==
4397 01:24:37.552936 RX Vref Scan: 0
4398 01:24:37.553272
4399 01:24:37.555402 RX Vref 0 -> 0, step: 1
4400 01:24:37.555856
4401 01:24:37.558851 RX Delay -179 -> 252, step: 8
4402 01:24:37.565144 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4403 01:24:37.568406 iDelay=205, Bit 1, Center 48 (-107 ~ 204) 312
4404 01:24:37.571954 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4405 01:24:37.575289 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4406 01:24:37.581380 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4407 01:24:37.584925 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4408 01:24:37.588011 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4409 01:24:37.591353 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4410 01:24:37.594975 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4411 01:24:37.601742 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4412 01:24:37.604747 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4413 01:24:37.608283 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4414 01:24:37.611323 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4415 01:24:37.617746 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4416 01:24:37.621641 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4417 01:24:37.624461 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4418 01:24:37.624918 ==
4419 01:24:37.628203 Dram Type= 6, Freq= 0, CH_0, rank 1
4420 01:24:37.631008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 01:24:37.634267 ==
4422 01:24:37.634726 DQS Delay:
4423 01:24:37.635086 DQS0 = 0, DQS1 = 0
4424 01:24:37.637870 DQM Delay:
4425 01:24:37.638415 DQM0 = 41, DQM1 = 37
4426 01:24:37.640814 DQ Delay:
4427 01:24:37.641268 DQ0 =36, DQ1 =48, DQ2 =36, DQ3 =36
4428 01:24:37.644451 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4429 01:24:37.647974 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4430 01:24:37.650905 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4431 01:24:37.651443
4432 01:24:37.654264
4433 01:24:37.660874 [DQSOSCAuto] RK1, (LSB)MR18= 0x5d12, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
4434 01:24:37.664337 CH0 RK1: MR19=808, MR18=5D12
4435 01:24:37.670512 CH0_RK1: MR19=0x808, MR18=0x5D12, DQSOSC=392, MR23=63, INC=170, DEC=113
4436 01:24:37.673824 [RxdqsGatingPostProcess] freq 600
4437 01:24:37.677529 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4438 01:24:37.680702 Pre-setting of DQS Precalculation
4439 01:24:37.687338 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4440 01:24:37.687880 ==
4441 01:24:37.690796 Dram Type= 6, Freq= 0, CH_1, rank 0
4442 01:24:37.693695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4443 01:24:37.694162 ==
4444 01:24:37.700322 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4445 01:24:37.704024 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4446 01:24:37.708090 [CA 0] Center 35 (5~66) winsize 62
4447 01:24:37.711735 [CA 1] Center 35 (5~66) winsize 62
4448 01:24:37.714221 [CA 2] Center 34 (4~65) winsize 62
4449 01:24:37.717869 [CA 3] Center 33 (3~64) winsize 62
4450 01:24:37.721383 [CA 4] Center 34 (4~64) winsize 61
4451 01:24:37.724251 [CA 5] Center 33 (3~64) winsize 62
4452 01:24:37.724710
4453 01:24:37.727376 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4454 01:24:37.727879
4455 01:24:37.734115 [CATrainingPosCal] consider 1 rank data
4456 01:24:37.734685 u2DelayCellTimex100 = 270/100 ps
4457 01:24:37.740800 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4458 01:24:37.744166 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4459 01:24:37.747067 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4460 01:24:37.750857 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4461 01:24:37.754105 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4462 01:24:37.756916 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4463 01:24:37.757415
4464 01:24:37.760438 CA PerBit enable=1, Macro0, CA PI delay=33
4465 01:24:37.760896
4466 01:24:37.764061 [CBTSetCACLKResult] CA Dly = 33
4467 01:24:37.767345 CS Dly: 6 (0~37)
4468 01:24:37.767893 ==
4469 01:24:37.770216 Dram Type= 6, Freq= 0, CH_1, rank 1
4470 01:24:37.773997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4471 01:24:37.774548 ==
4472 01:24:37.780334 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4473 01:24:37.786757 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4474 01:24:37.790055 [CA 0] Center 35 (5~66) winsize 62
4475 01:24:37.793462 [CA 1] Center 36 (6~66) winsize 61
4476 01:24:37.796615 [CA 2] Center 34 (4~65) winsize 62
4477 01:24:37.800268 [CA 3] Center 34 (3~65) winsize 63
4478 01:24:37.803030 [CA 4] Center 34 (4~65) winsize 62
4479 01:24:37.806739 [CA 5] Center 34 (3~65) winsize 63
4480 01:24:37.807316
4481 01:24:37.809803 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4482 01:24:37.810260
4483 01:24:37.813109 [CATrainingPosCal] consider 2 rank data
4484 01:24:37.816624 u2DelayCellTimex100 = 270/100 ps
4485 01:24:37.819802 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4486 01:24:37.823066 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4487 01:24:37.825945 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4488 01:24:37.829545 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4489 01:24:37.833301 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4490 01:24:37.836084 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4491 01:24:37.836634
4492 01:24:37.842582 CA PerBit enable=1, Macro0, CA PI delay=33
4493 01:24:37.843175
4494 01:24:37.846296 [CBTSetCACLKResult] CA Dly = 33
4495 01:24:37.846753 CS Dly: 6 (0~37)
4496 01:24:37.847114
4497 01:24:37.849057 ----->DramcWriteLeveling(PI) begin...
4498 01:24:37.849566 ==
4499 01:24:37.852530 Dram Type= 6, Freq= 0, CH_1, rank 0
4500 01:24:37.855849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4501 01:24:37.859477 ==
4502 01:24:37.860024 Write leveling (Byte 0): 29 => 29
4503 01:24:37.862181 Write leveling (Byte 1): 29 => 29
4504 01:24:37.865659 DramcWriteLeveling(PI) end<-----
4505 01:24:37.866218
4506 01:24:37.866582 ==
4507 01:24:37.869285 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 01:24:37.875700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 01:24:37.876242 ==
4510 01:24:37.879215 [Gating] SW mode calibration
4511 01:24:37.885940 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4512 01:24:37.889592 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4513 01:24:37.895263 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4514 01:24:37.898950 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4515 01:24:37.902548 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4516 01:24:37.908539 0 9 12 | B1->B0 | 3030 2e2e | 0 0 | (0 1) (1 1)
4517 01:24:37.911674 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4518 01:24:37.915240 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4519 01:24:37.921648 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4520 01:24:37.925396 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4521 01:24:37.928384 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4522 01:24:37.934721 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4523 01:24:37.938312 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4524 01:24:37.941372 0 10 12 | B1->B0 | 2c2c 3a3a | 0 0 | (0 0) (0 0)
4525 01:24:37.948684 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4526 01:24:37.951866 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4527 01:24:37.955532 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4528 01:24:37.961670 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4529 01:24:37.964719 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4530 01:24:37.968234 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4531 01:24:37.974543 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4532 01:24:37.977732 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4533 01:24:37.981253 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 01:24:37.984536 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 01:24:37.991350 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 01:24:37.994805 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 01:24:37.998257 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 01:24:38.004532 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 01:24:38.007650 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 01:24:38.014337 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 01:24:38.017453 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 01:24:38.020654 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 01:24:38.028040 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 01:24:38.030790 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 01:24:38.033990 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 01:24:38.040467 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 01:24:38.043826 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4548 01:24:38.047239 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4549 01:24:38.053807 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4550 01:24:38.054361 Total UI for P1: 0, mck2ui 16
4551 01:24:38.060679 best dqsien dly found for B1: ( 0, 13, 14)
4552 01:24:38.063440 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4553 01:24:38.067391 Total UI for P1: 0, mck2ui 16
4554 01:24:38.070262 best dqsien dly found for B0: ( 0, 13, 12)
4555 01:24:38.073301 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4556 01:24:38.076294 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4557 01:24:38.076746
4558 01:24:38.080453 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4559 01:24:38.083175 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4560 01:24:38.086560 [Gating] SW calibration Done
4561 01:24:38.087110 ==
4562 01:24:38.090016 Dram Type= 6, Freq= 0, CH_1, rank 0
4563 01:24:38.093152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 01:24:38.096674 ==
4565 01:24:38.097219 RX Vref Scan: 0
4566 01:24:38.097644
4567 01:24:38.099491 RX Vref 0 -> 0, step: 1
4568 01:24:38.099965
4569 01:24:38.102646 RX Delay -230 -> 252, step: 16
4570 01:24:38.106107 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4571 01:24:38.110001 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4572 01:24:38.112899 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4573 01:24:38.119489 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4574 01:24:38.123075 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4575 01:24:38.125854 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4576 01:24:38.129145 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4577 01:24:38.136148 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4578 01:24:38.139243 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4579 01:24:38.142622 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4580 01:24:38.145758 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4581 01:24:38.149204 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4582 01:24:38.156063 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4583 01:24:38.159175 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4584 01:24:38.162148 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4585 01:24:38.169404 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4586 01:24:38.169984 ==
4587 01:24:38.172281 Dram Type= 6, Freq= 0, CH_1, rank 0
4588 01:24:38.175721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 01:24:38.176306 ==
4590 01:24:38.176797 DQS Delay:
4591 01:24:38.178799 DQS0 = 0, DQS1 = 0
4592 01:24:38.179377 DQM Delay:
4593 01:24:38.182369 DQM0 = 46, DQM1 = 38
4594 01:24:38.182845 DQ Delay:
4595 01:24:38.185707 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4596 01:24:38.188806 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4597 01:24:38.192264 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4598 01:24:38.195285 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4599 01:24:38.195840
4600 01:24:38.196207
4601 01:24:38.196542 ==
4602 01:24:38.198392 Dram Type= 6, Freq= 0, CH_1, rank 0
4603 01:24:38.201457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 01:24:38.201922 ==
4605 01:24:38.205150
4606 01:24:38.205753
4607 01:24:38.206124 TX Vref Scan disable
4608 01:24:38.208335 == TX Byte 0 ==
4609 01:24:38.211541 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4610 01:24:38.214803 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4611 01:24:38.217981 == TX Byte 1 ==
4612 01:24:38.221502 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4613 01:24:38.224448 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4614 01:24:38.228117 ==
4615 01:24:38.231471 Dram Type= 6, Freq= 0, CH_1, rank 0
4616 01:24:38.234509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4617 01:24:38.235020 ==
4618 01:24:38.235396
4619 01:24:38.235735
4620 01:24:38.237918 TX Vref Scan disable
4621 01:24:38.238376 == TX Byte 0 ==
4622 01:24:38.244363 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4623 01:24:38.247765 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4624 01:24:38.248227 == TX Byte 1 ==
4625 01:24:38.254325 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4626 01:24:38.257681 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4627 01:24:38.258142
4628 01:24:38.258504 [DATLAT]
4629 01:24:38.260801 Freq=600, CH1 RK0
4630 01:24:38.261409
4631 01:24:38.261789 DATLAT Default: 0x9
4632 01:24:38.264284 0, 0xFFFF, sum = 0
4633 01:24:38.267554 1, 0xFFFF, sum = 0
4634 01:24:38.268109 2, 0xFFFF, sum = 0
4635 01:24:38.270748 3, 0xFFFF, sum = 0
4636 01:24:38.271304 4, 0xFFFF, sum = 0
4637 01:24:38.274191 5, 0xFFFF, sum = 0
4638 01:24:38.274659 6, 0xFFFF, sum = 0
4639 01:24:38.277271 7, 0xFFFF, sum = 0
4640 01:24:38.277770 8, 0x0, sum = 1
4641 01:24:38.281153 9, 0x0, sum = 2
4642 01:24:38.281762 10, 0x0, sum = 3
4643 01:24:38.282142 11, 0x0, sum = 4
4644 01:24:38.284024 best_step = 9
4645 01:24:38.284569
4646 01:24:38.284930 ==
4647 01:24:38.287772 Dram Type= 6, Freq= 0, CH_1, rank 0
4648 01:24:38.290812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4649 01:24:38.291277 ==
4650 01:24:38.294362 RX Vref Scan: 1
4651 01:24:38.294909
4652 01:24:38.295274 RX Vref 0 -> 0, step: 1
4653 01:24:38.297406
4654 01:24:38.297948 RX Delay -179 -> 252, step: 8
4655 01:24:38.298314
4656 01:24:38.300558 Set Vref, RX VrefLevel [Byte0]: 51
4657 01:24:38.303857 [Byte1]: 53
4658 01:24:38.308219
4659 01:24:38.308766 Final RX Vref Byte 0 = 51 to rank0
4660 01:24:38.311820 Final RX Vref Byte 1 = 53 to rank0
4661 01:24:38.314715 Final RX Vref Byte 0 = 51 to rank1
4662 01:24:38.318055 Final RX Vref Byte 1 = 53 to rank1==
4663 01:24:38.322062 Dram Type= 6, Freq= 0, CH_1, rank 0
4664 01:24:38.327754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 01:24:38.328298 ==
4666 01:24:38.328662 DQS Delay:
4667 01:24:38.331571 DQS0 = 0, DQS1 = 0
4668 01:24:38.332029 DQM Delay:
4669 01:24:38.332395 DQM0 = 47, DQM1 = 37
4670 01:24:38.334719 DQ Delay:
4671 01:24:38.337850 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4672 01:24:38.341508 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44
4673 01:24:38.344674 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4674 01:24:38.347532 DQ12 =48, DQ13 =40, DQ14 =48, DQ15 =48
4675 01:24:38.347994
4676 01:24:38.348357
4677 01:24:38.354257 [DQSOSCAuto] RK0, (LSB)MR18= 0x492e, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4678 01:24:38.357552 CH1 RK0: MR19=808, MR18=492E
4679 01:24:38.364905 CH1_RK0: MR19=0x808, MR18=0x492E, DQSOSC=396, MR23=63, INC=167, DEC=111
4680 01:24:38.365547
4681 01:24:38.367524 ----->DramcWriteLeveling(PI) begin...
4682 01:24:38.368106 ==
4683 01:24:38.371267 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 01:24:38.375957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 01:24:38.376675 ==
4686 01:24:38.377632 Write leveling (Byte 0): 29 => 29
4687 01:24:38.380764 Write leveling (Byte 1): 29 => 29
4688 01:24:38.384286 DramcWriteLeveling(PI) end<-----
4689 01:24:38.384765
4690 01:24:38.385249 ==
4691 01:24:38.387051 Dram Type= 6, Freq= 0, CH_1, rank 1
4692 01:24:38.390286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4693 01:24:38.393934 ==
4694 01:24:38.394476 [Gating] SW mode calibration
4695 01:24:38.403849 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4696 01:24:38.407524 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4697 01:24:38.410431 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4698 01:24:38.417530 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4699 01:24:38.420641 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4700 01:24:38.423807 0 9 12 | B1->B0 | 3232 3333 | 1 0 | (1 1) (0 0)
4701 01:24:38.430381 0 9 16 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4702 01:24:38.433527 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4703 01:24:38.437013 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4704 01:24:38.443381 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4705 01:24:38.447028 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4706 01:24:38.449975 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4707 01:24:38.456958 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4708 01:24:38.460004 0 10 12 | B1->B0 | 3030 2b2b | 0 0 | (0 0) (0 0)
4709 01:24:38.463636 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4710 01:24:38.469785 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4711 01:24:38.473422 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4712 01:24:38.476553 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4713 01:24:38.482821 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4714 01:24:38.486429 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4715 01:24:38.489782 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4716 01:24:38.496653 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4717 01:24:38.499177 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 01:24:38.502515 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 01:24:38.509106 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 01:24:38.512647 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 01:24:38.515871 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 01:24:38.522150 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4723 01:24:38.525729 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 01:24:38.528796 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 01:24:38.535450 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4726 01:24:38.538781 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 01:24:38.542000 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 01:24:38.548828 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 01:24:38.551793 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 01:24:38.555387 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4731 01:24:38.561521 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4732 01:24:38.565202 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4733 01:24:38.568332 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4734 01:24:38.571677 Total UI for P1: 0, mck2ui 16
4735 01:24:38.575083 best dqsien dly found for B0: ( 0, 13, 12)
4736 01:24:38.577989 Total UI for P1: 0, mck2ui 16
4737 01:24:38.581525 best dqsien dly found for B1: ( 0, 13, 14)
4738 01:24:38.584596 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4739 01:24:38.591231 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4740 01:24:38.591815
4741 01:24:38.594756 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4742 01:24:38.598009 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4743 01:24:38.601312 [Gating] SW calibration Done
4744 01:24:38.601785 ==
4745 01:24:38.604571 Dram Type= 6, Freq= 0, CH_1, rank 1
4746 01:24:38.607660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4747 01:24:38.608094 ==
4748 01:24:38.611007 RX Vref Scan: 0
4749 01:24:38.611435
4750 01:24:38.611869 RX Vref 0 -> 0, step: 1
4751 01:24:38.612281
4752 01:24:38.614301 RX Delay -230 -> 252, step: 16
4753 01:24:38.617511 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4754 01:24:38.624153 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4755 01:24:38.627522 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4756 01:24:38.630779 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4757 01:24:38.633887 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4758 01:24:38.640816 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4759 01:24:38.644309 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4760 01:24:38.647033 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4761 01:24:38.650362 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4762 01:24:38.657388 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4763 01:24:38.660880 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4764 01:24:38.664125 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4765 01:24:38.666844 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4766 01:24:38.673824 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4767 01:24:38.676985 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4768 01:24:38.680175 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4769 01:24:38.680690 ==
4770 01:24:38.683524 Dram Type= 6, Freq= 0, CH_1, rank 1
4771 01:24:38.687045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4772 01:24:38.689863 ==
4773 01:24:38.690337 DQS Delay:
4774 01:24:38.690814 DQS0 = 0, DQS1 = 0
4775 01:24:38.693113 DQM Delay:
4776 01:24:38.693645 DQM0 = 46, DQM1 = 40
4777 01:24:38.697262 DQ Delay:
4778 01:24:38.697883 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4779 01:24:38.700116 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4780 01:24:38.702992 DQ8 =17, DQ9 =33, DQ10 =41, DQ11 =33
4781 01:24:38.706493 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4782 01:24:38.710037
4783 01:24:38.710511
4784 01:24:38.710996 ==
4785 01:24:38.712929 Dram Type= 6, Freq= 0, CH_1, rank 1
4786 01:24:38.716653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4787 01:24:38.717234 ==
4788 01:24:38.717769
4789 01:24:38.718227
4790 01:24:38.719453 TX Vref Scan disable
4791 01:24:38.719931 == TX Byte 0 ==
4792 01:24:38.726095 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4793 01:24:38.729475 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4794 01:24:38.730053 == TX Byte 1 ==
4795 01:24:38.736018 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4796 01:24:38.739525 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4797 01:24:38.740099 ==
4798 01:24:38.742614 Dram Type= 6, Freq= 0, CH_1, rank 1
4799 01:24:38.746014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4800 01:24:38.746496 ==
4801 01:24:38.746985
4802 01:24:38.749258
4803 01:24:38.749793 TX Vref Scan disable
4804 01:24:38.753001 == TX Byte 0 ==
4805 01:24:38.756112 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4806 01:24:38.762967 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4807 01:24:38.763448 == TX Byte 1 ==
4808 01:24:38.766291 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4809 01:24:38.772827 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4810 01:24:38.773449
4811 01:24:38.773939 [DATLAT]
4812 01:24:38.774392 Freq=600, CH1 RK1
4813 01:24:38.774836
4814 01:24:38.775891 DATLAT Default: 0x9
4815 01:24:38.779276 0, 0xFFFF, sum = 0
4816 01:24:38.779863 1, 0xFFFF, sum = 0
4817 01:24:38.782557 2, 0xFFFF, sum = 0
4818 01:24:38.783054 3, 0xFFFF, sum = 0
4819 01:24:38.785788 4, 0xFFFF, sum = 0
4820 01:24:38.786373 5, 0xFFFF, sum = 0
4821 01:24:38.789507 6, 0xFFFF, sum = 0
4822 01:24:38.790096 7, 0xFFFF, sum = 0
4823 01:24:38.792213 8, 0x0, sum = 1
4824 01:24:38.792796 9, 0x0, sum = 2
4825 01:24:38.795958 10, 0x0, sum = 3
4826 01:24:38.796542 11, 0x0, sum = 4
4827 01:24:38.797038 best_step = 9
4828 01:24:38.797595
4829 01:24:38.798665 ==
4830 01:24:38.802056 Dram Type= 6, Freq= 0, CH_1, rank 1
4831 01:24:38.805809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4832 01:24:38.806389 ==
4833 01:24:38.806883 RX Vref Scan: 0
4834 01:24:38.807338
4835 01:24:38.808747 RX Vref 0 -> 0, step: 1
4836 01:24:38.809222
4837 01:24:38.812179 RX Delay -195 -> 252, step: 8
4838 01:24:38.818409 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4839 01:24:38.821921 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4840 01:24:38.825475 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4841 01:24:38.828615 iDelay=213, Bit 3, Center 44 (-99 ~ 188) 288
4842 01:24:38.831831 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4843 01:24:38.838314 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4844 01:24:38.841493 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4845 01:24:38.845172 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4846 01:24:38.848401 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4847 01:24:38.854897 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4848 01:24:38.858087 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4849 01:24:38.861286 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4850 01:24:38.864881 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4851 01:24:38.870815 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4852 01:24:38.874529 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4853 01:24:38.877902 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4854 01:24:38.878362 ==
4855 01:24:38.881233 Dram Type= 6, Freq= 0, CH_1, rank 1
4856 01:24:38.887531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4857 01:24:38.888089 ==
4858 01:24:38.888453 DQS Delay:
4859 01:24:38.888795 DQS0 = 0, DQS1 = 0
4860 01:24:38.890541 DQM Delay:
4861 01:24:38.890995 DQM0 = 45, DQM1 = 37
4862 01:24:38.894321 DQ Delay:
4863 01:24:38.897891 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44
4864 01:24:38.901272 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =40
4865 01:24:38.903971 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4866 01:24:38.907583 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4867 01:24:38.908135
4868 01:24:38.908500
4869 01:24:38.914181 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a1f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
4870 01:24:38.917687 CH1 RK1: MR19=808, MR18=2A1F
4871 01:24:38.923943 CH1_RK1: MR19=0x808, MR18=0x2A1F, DQSOSC=401, MR23=63, INC=163, DEC=108
4872 01:24:38.926880 [RxdqsGatingPostProcess] freq 600
4873 01:24:38.930662 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4874 01:24:38.933443 Pre-setting of DQS Precalculation
4875 01:24:38.940269 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4876 01:24:38.946674 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4877 01:24:38.953962 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4878 01:24:38.954510
4879 01:24:38.954875
4880 01:24:38.956688 [Calibration Summary] 1200 Mbps
4881 01:24:38.957239 CH 0, Rank 0
4882 01:24:38.960028 SW Impedance : PASS
4883 01:24:38.963607 DUTY Scan : NO K
4884 01:24:38.964154 ZQ Calibration : PASS
4885 01:24:38.966325 Jitter Meter : NO K
4886 01:24:38.970176 CBT Training : PASS
4887 01:24:38.970734 Write leveling : PASS
4888 01:24:38.973639 RX DQS gating : PASS
4889 01:24:38.976780 RX DQ/DQS(RDDQC) : PASS
4890 01:24:38.977560 TX DQ/DQS : PASS
4891 01:24:38.980088 RX DATLAT : PASS
4892 01:24:38.982934 RX DQ/DQS(Engine): PASS
4893 01:24:38.983389 TX OE : NO K
4894 01:24:38.986931 All Pass.
4895 01:24:38.987481
4896 01:24:38.987843 CH 0, Rank 1
4897 01:24:38.989788 SW Impedance : PASS
4898 01:24:38.990243 DUTY Scan : NO K
4899 01:24:38.992986 ZQ Calibration : PASS
4900 01:24:38.996245 Jitter Meter : NO K
4901 01:24:38.996791 CBT Training : PASS
4902 01:24:38.999823 Write leveling : PASS
4903 01:24:39.002674 RX DQS gating : PASS
4904 01:24:39.003131 RX DQ/DQS(RDDQC) : PASS
4905 01:24:39.006661 TX DQ/DQS : PASS
4906 01:24:39.009596 RX DATLAT : PASS
4907 01:24:39.010055 RX DQ/DQS(Engine): PASS
4908 01:24:39.012621 TX OE : NO K
4909 01:24:39.013079 All Pass.
4910 01:24:39.013494
4911 01:24:39.016070 CH 1, Rank 0
4912 01:24:39.016524 SW Impedance : PASS
4913 01:24:39.019605 DUTY Scan : NO K
4914 01:24:39.020151 ZQ Calibration : PASS
4915 01:24:39.022738 Jitter Meter : NO K
4916 01:24:39.026152 CBT Training : PASS
4917 01:24:39.026702 Write leveling : PASS
4918 01:24:39.029617 RX DQS gating : PASS
4919 01:24:39.033033 RX DQ/DQS(RDDQC) : PASS
4920 01:24:39.033639 TX DQ/DQS : PASS
4921 01:24:39.035674 RX DATLAT : PASS
4922 01:24:39.039312 RX DQ/DQS(Engine): PASS
4923 01:24:39.039861 TX OE : NO K
4924 01:24:39.042581 All Pass.
4925 01:24:39.043034
4926 01:24:39.043392 CH 1, Rank 1
4927 01:24:39.045846 SW Impedance : PASS
4928 01:24:39.046301 DUTY Scan : NO K
4929 01:24:39.049138 ZQ Calibration : PASS
4930 01:24:39.052485 Jitter Meter : NO K
4931 01:24:39.053034 CBT Training : PASS
4932 01:24:39.055816 Write leveling : PASS
4933 01:24:39.058842 RX DQS gating : PASS
4934 01:24:39.059302 RX DQ/DQS(RDDQC) : PASS
4935 01:24:39.062319 TX DQ/DQS : PASS
4936 01:24:39.065537 RX DATLAT : PASS
4937 01:24:39.065997 RX DQ/DQS(Engine): PASS
4938 01:24:39.068874 TX OE : NO K
4939 01:24:39.069483 All Pass.
4940 01:24:39.069857
4941 01:24:39.072115 DramC Write-DBI off
4942 01:24:39.075464 PER_BANK_REFRESH: Hybrid Mode
4943 01:24:39.076017 TX_TRACKING: ON
4944 01:24:39.085154 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4945 01:24:39.088628 [FAST_K] Save calibration result to emmc
4946 01:24:39.091453 dramc_set_vcore_voltage set vcore to 662500
4947 01:24:39.095194 Read voltage for 933, 3
4948 01:24:39.095739 Vio18 = 0
4949 01:24:39.096104 Vcore = 662500
4950 01:24:39.098266 Vdram = 0
4951 01:24:39.098721 Vddq = 0
4952 01:24:39.099078 Vmddr = 0
4953 01:24:39.105005 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4954 01:24:39.108305 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4955 01:24:39.111372 MEM_TYPE=3, freq_sel=17
4956 01:24:39.114972 sv_algorithm_assistance_LP4_1600
4957 01:24:39.117982 ============ PULL DRAM RESETB DOWN ============
4958 01:24:39.124778 ========== PULL DRAM RESETB DOWN end =========
4959 01:24:39.128127 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4960 01:24:39.131271 ===================================
4961 01:24:39.134335 LPDDR4 DRAM CONFIGURATION
4962 01:24:39.137413 ===================================
4963 01:24:39.137874 EX_ROW_EN[0] = 0x0
4964 01:24:39.140693 EX_ROW_EN[1] = 0x0
4965 01:24:39.141153 LP4Y_EN = 0x0
4966 01:24:39.144654 WORK_FSP = 0x0
4967 01:24:39.145212 WL = 0x3
4968 01:24:39.147829 RL = 0x3
4969 01:24:39.148394 BL = 0x2
4970 01:24:39.151070 RPST = 0x0
4971 01:24:39.154581 RD_PRE = 0x0
4972 01:24:39.155144 WR_PRE = 0x1
4973 01:24:39.157205 WR_PST = 0x0
4974 01:24:39.157708 DBI_WR = 0x0
4975 01:24:39.160470 DBI_RD = 0x0
4976 01:24:39.160928 OTF = 0x1
4977 01:24:39.164050 ===================================
4978 01:24:39.167834 ===================================
4979 01:24:39.170913 ANA top config
4980 01:24:39.173911 ===================================
4981 01:24:39.174477 DLL_ASYNC_EN = 0
4982 01:24:39.177745 ALL_SLAVE_EN = 1
4983 01:24:39.180669 NEW_RANK_MODE = 1
4984 01:24:39.183905 DLL_IDLE_MODE = 1
4985 01:24:39.184461 LP45_APHY_COMB_EN = 1
4986 01:24:39.187187 TX_ODT_DIS = 1
4987 01:24:39.190548 NEW_8X_MODE = 1
4988 01:24:39.193558 ===================================
4989 01:24:39.197226 ===================================
4990 01:24:39.200369 data_rate = 1866
4991 01:24:39.204006 CKR = 1
4992 01:24:39.206829 DQ_P2S_RATIO = 8
4993 01:24:39.210241 ===================================
4994 01:24:39.210804 CA_P2S_RATIO = 8
4995 01:24:39.213397 DQ_CA_OPEN = 0
4996 01:24:39.216661 DQ_SEMI_OPEN = 0
4997 01:24:39.220184 CA_SEMI_OPEN = 0
4998 01:24:39.223325 CA_FULL_RATE = 0
4999 01:24:39.226495 DQ_CKDIV4_EN = 1
5000 01:24:39.226951 CA_CKDIV4_EN = 1
5001 01:24:39.229827 CA_PREDIV_EN = 0
5002 01:24:39.233071 PH8_DLY = 0
5003 01:24:39.236468 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5004 01:24:39.239818 DQ_AAMCK_DIV = 4
5005 01:24:39.243352 CA_AAMCK_DIV = 4
5006 01:24:39.246636 CA_ADMCK_DIV = 4
5007 01:24:39.247180 DQ_TRACK_CA_EN = 0
5008 01:24:39.249606 CA_PICK = 933
5009 01:24:39.253174 CA_MCKIO = 933
5010 01:24:39.256599 MCKIO_SEMI = 0
5011 01:24:39.259572 PLL_FREQ = 3732
5012 01:24:39.262951 DQ_UI_PI_RATIO = 32
5013 01:24:39.265953 CA_UI_PI_RATIO = 0
5014 01:24:39.269919 ===================================
5015 01:24:39.273228 ===================================
5016 01:24:39.273828 memory_type:LPDDR4
5017 01:24:39.276431 GP_NUM : 10
5018 01:24:39.279760 SRAM_EN : 1
5019 01:24:39.280306 MD32_EN : 0
5020 01:24:39.282803 ===================================
5021 01:24:39.286106 [ANA_INIT] >>>>>>>>>>>>>>
5022 01:24:39.289753 <<<<<< [CONFIGURE PHASE]: ANA_TX
5023 01:24:39.293403 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5024 01:24:39.295889 ===================================
5025 01:24:39.300154 data_rate = 1866,PCW = 0X8f00
5026 01:24:39.302398 ===================================
5027 01:24:39.306450 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5028 01:24:39.309794 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5029 01:24:39.315670 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5030 01:24:39.319029 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5031 01:24:39.322209 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5032 01:24:39.325235 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5033 01:24:39.328779 [ANA_INIT] flow start
5034 01:24:39.331875 [ANA_INIT] PLL >>>>>>>>
5035 01:24:39.332334 [ANA_INIT] PLL <<<<<<<<
5036 01:24:39.335221 [ANA_INIT] MIDPI >>>>>>>>
5037 01:24:39.338856 [ANA_INIT] MIDPI <<<<<<<<
5038 01:24:39.341832 [ANA_INIT] DLL >>>>>>>>
5039 01:24:39.342295 [ANA_INIT] flow end
5040 01:24:39.344956 ============ LP4 DIFF to SE enter ============
5041 01:24:39.351985 ============ LP4 DIFF to SE exit ============
5042 01:24:39.352548 [ANA_INIT] <<<<<<<<<<<<<
5043 01:24:39.355425 [Flow] Enable top DCM control >>>>>
5044 01:24:39.358833 [Flow] Enable top DCM control <<<<<
5045 01:24:39.361930 Enable DLL master slave shuffle
5046 01:24:39.368305 ==============================================================
5047 01:24:39.368871 Gating Mode config
5048 01:24:39.374747 ==============================================================
5049 01:24:39.378657 Config description:
5050 01:24:39.388138 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5051 01:24:39.394883 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5052 01:24:39.397942 SELPH_MODE 0: By rank 1: By Phase
5053 01:24:39.404979 ==============================================================
5054 01:24:39.408664 GAT_TRACK_EN = 1
5055 01:24:39.411304 RX_GATING_MODE = 2
5056 01:24:39.414484 RX_GATING_TRACK_MODE = 2
5057 01:24:39.414945 SELPH_MODE = 1
5058 01:24:39.417934 PICG_EARLY_EN = 1
5059 01:24:39.420892 VALID_LAT_VALUE = 1
5060 01:24:39.427644 ==============================================================
5061 01:24:39.431322 Enter into Gating configuration >>>>
5062 01:24:39.434315 Exit from Gating configuration <<<<
5063 01:24:39.437629 Enter into DVFS_PRE_config >>>>>
5064 01:24:39.447820 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5065 01:24:39.451194 Exit from DVFS_PRE_config <<<<<
5066 01:24:39.454503 Enter into PICG configuration >>>>
5067 01:24:39.457356 Exit from PICG configuration <<<<
5068 01:24:39.460629 [RX_INPUT] configuration >>>>>
5069 01:24:39.464069 [RX_INPUT] configuration <<<<<
5070 01:24:39.467651 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5071 01:24:39.473985 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5072 01:24:39.480525 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5073 01:24:39.487435 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5074 01:24:39.493869 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5075 01:24:39.500021 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5076 01:24:39.503354 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5077 01:24:39.507050 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5078 01:24:39.509932 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5079 01:24:39.517063 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5080 01:24:39.519809 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5081 01:24:39.523439 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5082 01:24:39.526385 ===================================
5083 01:24:39.530066 LPDDR4 DRAM CONFIGURATION
5084 01:24:39.533416 ===================================
5085 01:24:39.533962 EX_ROW_EN[0] = 0x0
5086 01:24:39.536259 EX_ROW_EN[1] = 0x0
5087 01:24:39.539858 LP4Y_EN = 0x0
5088 01:24:39.540410 WORK_FSP = 0x0
5089 01:24:39.542921 WL = 0x3
5090 01:24:39.543376 RL = 0x3
5091 01:24:39.546064 BL = 0x2
5092 01:24:39.546518 RPST = 0x0
5093 01:24:39.550048 RD_PRE = 0x0
5094 01:24:39.550501 WR_PRE = 0x1
5095 01:24:39.552711 WR_PST = 0x0
5096 01:24:39.553163 DBI_WR = 0x0
5097 01:24:39.556100 DBI_RD = 0x0
5098 01:24:39.556645 OTF = 0x1
5099 01:24:39.559407 ===================================
5100 01:24:39.562704 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5101 01:24:39.568914 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5102 01:24:39.572429 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5103 01:24:39.575649 ===================================
5104 01:24:39.579199 LPDDR4 DRAM CONFIGURATION
5105 01:24:39.582502 ===================================
5106 01:24:39.583059 EX_ROW_EN[0] = 0x10
5107 01:24:39.585595 EX_ROW_EN[1] = 0x0
5108 01:24:39.588983 LP4Y_EN = 0x0
5109 01:24:39.589466 WORK_FSP = 0x0
5110 01:24:39.592024 WL = 0x3
5111 01:24:39.592470 RL = 0x3
5112 01:24:39.595570 BL = 0x2
5113 01:24:39.596120 RPST = 0x0
5114 01:24:39.599058 RD_PRE = 0x0
5115 01:24:39.599607 WR_PRE = 0x1
5116 01:24:39.602170 WR_PST = 0x0
5117 01:24:39.602722 DBI_WR = 0x0
5118 01:24:39.605980 DBI_RD = 0x0
5119 01:24:39.606530 OTF = 0x1
5120 01:24:39.608755 ===================================
5121 01:24:39.615140 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5122 01:24:39.620405 nWR fixed to 30
5123 01:24:39.622916 [ModeRegInit_LP4] CH0 RK0
5124 01:24:39.623368 [ModeRegInit_LP4] CH0 RK1
5125 01:24:39.626287 [ModeRegInit_LP4] CH1 RK0
5126 01:24:39.630086 [ModeRegInit_LP4] CH1 RK1
5127 01:24:39.630636 match AC timing 9
5128 01:24:39.636741 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5129 01:24:39.639536 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5130 01:24:39.642937 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5131 01:24:39.649394 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5132 01:24:39.652933 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5133 01:24:39.653525 ==
5134 01:24:39.656004 Dram Type= 6, Freq= 0, CH_0, rank 0
5135 01:24:39.659323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 01:24:39.659799 ==
5137 01:24:39.666056 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5138 01:24:39.672796 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5139 01:24:39.675747 [CA 0] Center 38 (7~69) winsize 63
5140 01:24:39.679052 [CA 1] Center 37 (7~68) winsize 62
5141 01:24:39.682080 [CA 2] Center 34 (4~65) winsize 62
5142 01:24:39.685604 [CA 3] Center 34 (4~65) winsize 62
5143 01:24:39.688758 [CA 4] Center 33 (3~64) winsize 62
5144 01:24:39.692252 [CA 5] Center 33 (3~64) winsize 62
5145 01:24:39.692663
5146 01:24:39.695800 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5147 01:24:39.696327
5148 01:24:39.699026 [CATrainingPosCal] consider 1 rank data
5149 01:24:39.702281 u2DelayCellTimex100 = 270/100 ps
5150 01:24:39.705353 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5151 01:24:39.708559 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5152 01:24:39.712266 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5153 01:24:39.718614 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5154 01:24:39.721873 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5155 01:24:39.725875 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5156 01:24:39.726384
5157 01:24:39.728320 CA PerBit enable=1, Macro0, CA PI delay=33
5158 01:24:39.728734
5159 01:24:39.731332 [CBTSetCACLKResult] CA Dly = 33
5160 01:24:39.731743 CS Dly: 7 (0~38)
5161 01:24:39.732071 ==
5162 01:24:39.734984 Dram Type= 6, Freq= 0, CH_0, rank 1
5163 01:24:39.741481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5164 01:24:39.742069 ==
5165 01:24:39.744686 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5166 01:24:39.751355 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5167 01:24:39.755016 [CA 0] Center 37 (7~68) winsize 62
5168 01:24:39.757888 [CA 1] Center 37 (7~68) winsize 62
5169 01:24:39.761303 [CA 2] Center 34 (4~65) winsize 62
5170 01:24:39.764442 [CA 3] Center 34 (4~65) winsize 62
5171 01:24:39.767896 [CA 4] Center 33 (3~64) winsize 62
5172 01:24:39.771487 [CA 5] Center 33 (3~63) winsize 61
5173 01:24:39.772030
5174 01:24:39.774543 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5175 01:24:39.775046
5176 01:24:39.777597 [CATrainingPosCal] consider 2 rank data
5177 01:24:39.781000 u2DelayCellTimex100 = 270/100 ps
5178 01:24:39.787809 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5179 01:24:39.790866 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5180 01:24:39.794274 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5181 01:24:39.797693 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5182 01:24:39.800935 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5183 01:24:39.804062 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5184 01:24:39.804540
5185 01:24:39.807289 CA PerBit enable=1, Macro0, CA PI delay=33
5186 01:24:39.807701
5187 01:24:39.810704 [CBTSetCACLKResult] CA Dly = 33
5188 01:24:39.814284 CS Dly: 7 (0~39)
5189 01:24:39.814699
5190 01:24:39.817708 ----->DramcWriteLeveling(PI) begin...
5191 01:24:39.818130 ==
5192 01:24:39.820358 Dram Type= 6, Freq= 0, CH_0, rank 0
5193 01:24:39.823835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5194 01:24:39.824245 ==
5195 01:24:39.826933 Write leveling (Byte 0): 32 => 32
5196 01:24:39.830372 Write leveling (Byte 1): 28 => 28
5197 01:24:39.833695 DramcWriteLeveling(PI) end<-----
5198 01:24:39.834199
5199 01:24:39.834528 ==
5200 01:24:39.837308 Dram Type= 6, Freq= 0, CH_0, rank 0
5201 01:24:39.840110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5202 01:24:39.840533 ==
5203 01:24:39.843801 [Gating] SW mode calibration
5204 01:24:39.850240 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5205 01:24:39.856969 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5206 01:24:39.860294 0 14 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
5207 01:24:39.867054 0 14 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
5208 01:24:39.869539 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5209 01:24:39.872966 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5210 01:24:39.879364 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5211 01:24:39.883085 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5212 01:24:39.886131 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5213 01:24:39.892983 0 14 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
5214 01:24:39.896687 0 15 0 | B1->B0 | 3131 2424 | 1 0 | (1 0) (1 0)
5215 01:24:39.899326 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5216 01:24:39.906485 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5217 01:24:39.909477 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5218 01:24:39.912531 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5219 01:24:39.919233 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5220 01:24:39.922335 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5221 01:24:39.926056 0 15 28 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
5222 01:24:39.932843 1 0 0 | B1->B0 | 2929 4545 | 0 0 | (0 0) (0 0)
5223 01:24:39.935306 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5224 01:24:39.938939 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5225 01:24:39.945268 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5226 01:24:39.948683 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5227 01:24:39.951604 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5228 01:24:39.958221 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5229 01:24:39.962027 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5230 01:24:39.965084 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5231 01:24:39.971534 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 01:24:39.974818 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 01:24:39.978223 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 01:24:39.985263 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 01:24:39.987918 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5236 01:24:39.991778 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5237 01:24:39.997978 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5238 01:24:40.001975 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5239 01:24:40.004333 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5240 01:24:40.011736 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 01:24:40.014594 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 01:24:40.018318 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5243 01:24:40.024067 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 01:24:40.027408 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5245 01:24:40.031018 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5246 01:24:40.037792 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5247 01:24:40.041035 Total UI for P1: 0, mck2ui 16
5248 01:24:40.043883 best dqsien dly found for B0: ( 1, 2, 28)
5249 01:24:40.047437 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5250 01:24:40.050366 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5251 01:24:40.053698 Total UI for P1: 0, mck2ui 16
5252 01:24:40.057219 best dqsien dly found for B1: ( 1, 3, 0)
5253 01:24:40.060502 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5254 01:24:40.064002 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5255 01:24:40.067264
5256 01:24:40.070204 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5257 01:24:40.073787 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5258 01:24:40.076916 [Gating] SW calibration Done
5259 01:24:40.077520 ==
5260 01:24:40.080214 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 01:24:40.083949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 01:24:40.084504 ==
5263 01:24:40.084867 RX Vref Scan: 0
5264 01:24:40.085201
5265 01:24:40.086993 RX Vref 0 -> 0, step: 1
5266 01:24:40.087447
5267 01:24:40.090326 RX Delay -80 -> 252, step: 8
5268 01:24:40.093664 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5269 01:24:40.096918 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5270 01:24:40.103772 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5271 01:24:40.106745 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5272 01:24:40.109701 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5273 01:24:40.113303 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5274 01:24:40.116445 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5275 01:24:40.119609 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5276 01:24:40.126337 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5277 01:24:40.129308 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5278 01:24:40.133039 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5279 01:24:40.136545 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5280 01:24:40.142584 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5281 01:24:40.145815 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5282 01:24:40.149316 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5283 01:24:40.152755 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5284 01:24:40.153316 ==
5285 01:24:40.156175 Dram Type= 6, Freq= 0, CH_0, rank 0
5286 01:24:40.159317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 01:24:40.162485 ==
5288 01:24:40.162943 DQS Delay:
5289 01:24:40.163305 DQS0 = 0, DQS1 = 0
5290 01:24:40.165555 DQM Delay:
5291 01:24:40.166011 DQM0 = 96, DQM1 = 84
5292 01:24:40.168675 DQ Delay:
5293 01:24:40.172102 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5294 01:24:40.175419 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =107
5295 01:24:40.178614 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =79
5296 01:24:40.182237 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =91
5297 01:24:40.182907
5298 01:24:40.183275
5299 01:24:40.183608 ==
5300 01:24:40.185167 Dram Type= 6, Freq= 0, CH_0, rank 0
5301 01:24:40.188918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5302 01:24:40.189530 ==
5303 01:24:40.189996
5304 01:24:40.190344
5305 01:24:40.192313 TX Vref Scan disable
5306 01:24:40.192858 == TX Byte 0 ==
5307 01:24:40.198609 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5308 01:24:40.202255 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5309 01:24:40.205715 == TX Byte 1 ==
5310 01:24:40.208717 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5311 01:24:40.211794 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5312 01:24:40.212341 ==
5313 01:24:40.214868 Dram Type= 6, Freq= 0, CH_0, rank 0
5314 01:24:40.218274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5315 01:24:40.221605 ==
5316 01:24:40.222155
5317 01:24:40.222513
5318 01:24:40.222846 TX Vref Scan disable
5319 01:24:40.225133 == TX Byte 0 ==
5320 01:24:40.228085 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5321 01:24:40.235366 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5322 01:24:40.235985 == TX Byte 1 ==
5323 01:24:40.238083 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5324 01:24:40.245120 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5325 01:24:40.245749
5326 01:24:40.246117 [DATLAT]
5327 01:24:40.246450 Freq=933, CH0 RK0
5328 01:24:40.246771
5329 01:24:40.248052 DATLAT Default: 0xd
5330 01:24:40.248431 0, 0xFFFF, sum = 0
5331 01:24:40.251762 1, 0xFFFF, sum = 0
5332 01:24:40.254803 2, 0xFFFF, sum = 0
5333 01:24:40.255262 3, 0xFFFF, sum = 0
5334 01:24:40.258024 4, 0xFFFF, sum = 0
5335 01:24:40.258478 5, 0xFFFF, sum = 0
5336 01:24:40.261389 6, 0xFFFF, sum = 0
5337 01:24:40.261853 7, 0xFFFF, sum = 0
5338 01:24:40.264869 8, 0xFFFF, sum = 0
5339 01:24:40.265358 9, 0xFFFF, sum = 0
5340 01:24:40.268073 10, 0x0, sum = 1
5341 01:24:40.268557 11, 0x0, sum = 2
5342 01:24:40.271396 12, 0x0, sum = 3
5343 01:24:40.271956 13, 0x0, sum = 4
5344 01:24:40.272323 best_step = 11
5345 01:24:40.274791
5346 01:24:40.275246 ==
5347 01:24:40.277578 Dram Type= 6, Freq= 0, CH_0, rank 0
5348 01:24:40.281024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5349 01:24:40.281518 ==
5350 01:24:40.281885 RX Vref Scan: 1
5351 01:24:40.282224
5352 01:24:40.284191 RX Vref 0 -> 0, step: 1
5353 01:24:40.284663
5354 01:24:40.287949 RX Delay -69 -> 252, step: 4
5355 01:24:40.288412
5356 01:24:40.290875 Set Vref, RX VrefLevel [Byte0]: 65
5357 01:24:40.294368 [Byte1]: 49
5358 01:24:40.297385
5359 01:24:40.297872 Final RX Vref Byte 0 = 65 to rank0
5360 01:24:40.300922 Final RX Vref Byte 1 = 49 to rank0
5361 01:24:40.304479 Final RX Vref Byte 0 = 65 to rank1
5362 01:24:40.307528 Final RX Vref Byte 1 = 49 to rank1==
5363 01:24:40.310506 Dram Type= 6, Freq= 0, CH_0, rank 0
5364 01:24:40.317506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5365 01:24:40.317935 ==
5366 01:24:40.318264 DQS Delay:
5367 01:24:40.320958 DQS0 = 0, DQS1 = 0
5368 01:24:40.321391 DQM Delay:
5369 01:24:40.321724 DQM0 = 97, DQM1 = 85
5370 01:24:40.323547 DQ Delay:
5371 01:24:40.327067 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5372 01:24:40.329925 DQ4 =96, DQ5 =90, DQ6 =106, DQ7 =106
5373 01:24:40.333865 DQ8 =76, DQ9 =74, DQ10 =86, DQ11 =82
5374 01:24:40.336822 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =92
5375 01:24:40.337113
5376 01:24:40.337365
5377 01:24:40.343965 [DQSOSCAuto] RK0, (LSB)MR18= 0x280f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 409 ps
5378 01:24:40.346478 CH0 RK0: MR19=505, MR18=280F
5379 01:24:40.353409 CH0_RK0: MR19=0x505, MR18=0x280F, DQSOSC=409, MR23=63, INC=64, DEC=43
5380 01:24:40.353870
5381 01:24:40.356506 ----->DramcWriteLeveling(PI) begin...
5382 01:24:40.356958 ==
5383 01:24:40.359959 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 01:24:40.363326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 01:24:40.363768 ==
5386 01:24:40.366427 Write leveling (Byte 0): 31 => 31
5387 01:24:40.369668 Write leveling (Byte 1): 28 => 28
5388 01:24:40.373213 DramcWriteLeveling(PI) end<-----
5389 01:24:40.373805
5390 01:24:40.374132 ==
5391 01:24:40.376692 Dram Type= 6, Freq= 0, CH_0, rank 1
5392 01:24:40.383021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5393 01:24:40.383548 ==
5394 01:24:40.383906 [Gating] SW mode calibration
5395 01:24:40.393610 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5396 01:24:40.396745 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5397 01:24:40.399908 0 14 0 | B1->B0 | 2424 2f2e | 0 1 | (0 0) (1 1)
5398 01:24:40.407021 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5399 01:24:40.409631 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5400 01:24:40.413396 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5401 01:24:40.419618 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5402 01:24:40.423021 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5403 01:24:40.426186 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5404 01:24:40.432861 0 14 28 | B1->B0 | 3333 2c2c | 1 1 | (1 1) (1 0)
5405 01:24:40.436196 0 15 0 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (0 0)
5406 01:24:40.442374 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5407 01:24:40.445909 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5408 01:24:40.448944 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5409 01:24:40.456080 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5410 01:24:40.458655 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5411 01:24:40.461873 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5412 01:24:40.469037 0 15 28 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5413 01:24:40.472269 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5414 01:24:40.475005 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5415 01:24:40.482139 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5416 01:24:40.484884 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5417 01:24:40.488309 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5418 01:24:40.495391 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5419 01:24:40.498716 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5420 01:24:40.501701 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5421 01:24:40.508149 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5422 01:24:40.511385 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 01:24:40.514796 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 01:24:40.521060 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 01:24:40.524711 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 01:24:40.527504 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 01:24:40.534384 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 01:24:40.537897 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 01:24:40.540958 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 01:24:40.547725 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 01:24:40.550565 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 01:24:40.554176 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 01:24:40.561007 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 01:24:40.563971 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 01:24:40.567259 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 01:24:40.574252 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5437 01:24:40.577909 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5438 01:24:40.580471 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5439 01:24:40.583574 Total UI for P1: 0, mck2ui 16
5440 01:24:40.586991 best dqsien dly found for B0: ( 1, 2, 30)
5441 01:24:40.590340 Total UI for P1: 0, mck2ui 16
5442 01:24:40.593379 best dqsien dly found for B1: ( 1, 2, 30)
5443 01:24:40.597289 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5444 01:24:40.600592 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5445 01:24:40.601138
5446 01:24:40.606738 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5447 01:24:40.610242 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5448 01:24:40.610796 [Gating] SW calibration Done
5449 01:24:40.613493 ==
5450 01:24:40.616415 Dram Type= 6, Freq= 0, CH_0, rank 1
5451 01:24:40.619976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5452 01:24:40.620483 ==
5453 01:24:40.620850 RX Vref Scan: 0
5454 01:24:40.621183
5455 01:24:40.623405 RX Vref 0 -> 0, step: 1
5456 01:24:40.623857
5457 01:24:40.626386 RX Delay -80 -> 252, step: 8
5458 01:24:40.629764 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5459 01:24:40.633383 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5460 01:24:40.639673 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5461 01:24:40.642772 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5462 01:24:40.646021 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5463 01:24:40.649881 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5464 01:24:40.652903 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5465 01:24:40.655695 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5466 01:24:40.662846 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5467 01:24:40.665830 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5468 01:24:40.668864 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5469 01:24:40.672197 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5470 01:24:40.675930 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5471 01:24:40.682270 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5472 01:24:40.685910 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5473 01:24:40.689171 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5474 01:24:40.689794 ==
5475 01:24:40.692266 Dram Type= 6, Freq= 0, CH_0, rank 1
5476 01:24:40.695051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5477 01:24:40.695530 ==
5478 01:24:40.699106 DQS Delay:
5479 01:24:40.699663 DQS0 = 0, DQS1 = 0
5480 01:24:40.701910 DQM Delay:
5481 01:24:40.702368 DQM0 = 97, DQM1 = 89
5482 01:24:40.702731 DQ Delay:
5483 01:24:40.705796 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =91
5484 01:24:40.708419 DQ4 =99, DQ5 =91, DQ6 =107, DQ7 =107
5485 01:24:40.712184 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5486 01:24:40.714669 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5487 01:24:40.718647
5488 01:24:40.719103
5489 01:24:40.719466 ==
5490 01:24:40.721722 Dram Type= 6, Freq= 0, CH_0, rank 1
5491 01:24:40.724958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 01:24:40.725452 ==
5493 01:24:40.725822
5494 01:24:40.726155
5495 01:24:40.728171 TX Vref Scan disable
5496 01:24:40.728629 == TX Byte 0 ==
5497 01:24:40.734925 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5498 01:24:40.738137 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5499 01:24:40.738699 == TX Byte 1 ==
5500 01:24:40.744526 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5501 01:24:40.747936 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5502 01:24:40.748460 ==
5503 01:24:40.751101 Dram Type= 6, Freq= 0, CH_0, rank 1
5504 01:24:40.754792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5505 01:24:40.755252 ==
5506 01:24:40.755613
5507 01:24:40.755948
5508 01:24:40.757935 TX Vref Scan disable
5509 01:24:40.761270 == TX Byte 0 ==
5510 01:24:40.764514 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5511 01:24:40.767693 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5512 01:24:40.771099 == TX Byte 1 ==
5513 01:24:40.774542 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5514 01:24:40.777477 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5515 01:24:40.781066
5516 01:24:40.781504 [DATLAT]
5517 01:24:40.781833 Freq=933, CH0 RK1
5518 01:24:40.782142
5519 01:24:40.784695 DATLAT Default: 0xb
5520 01:24:40.785102 0, 0xFFFF, sum = 0
5521 01:24:40.787261 1, 0xFFFF, sum = 0
5522 01:24:40.787678 2, 0xFFFF, sum = 0
5523 01:24:40.791183 3, 0xFFFF, sum = 0
5524 01:24:40.791755 4, 0xFFFF, sum = 0
5525 01:24:40.794179 5, 0xFFFF, sum = 0
5526 01:24:40.797411 6, 0xFFFF, sum = 0
5527 01:24:40.797950 7, 0xFFFF, sum = 0
5528 01:24:40.800495 8, 0xFFFF, sum = 0
5529 01:24:40.800913 9, 0xFFFF, sum = 0
5530 01:24:40.804324 10, 0x0, sum = 1
5531 01:24:40.804851 11, 0x0, sum = 2
5532 01:24:40.807865 12, 0x0, sum = 3
5533 01:24:40.808394 13, 0x0, sum = 4
5534 01:24:40.808736 best_step = 11
5535 01:24:40.809041
5536 01:24:40.810524 ==
5537 01:24:40.813529 Dram Type= 6, Freq= 0, CH_0, rank 1
5538 01:24:40.817178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5539 01:24:40.817633 ==
5540 01:24:40.817965 RX Vref Scan: 0
5541 01:24:40.818271
5542 01:24:40.820262 RX Vref 0 -> 0, step: 1
5543 01:24:40.820673
5544 01:24:40.823468 RX Delay -61 -> 252, step: 4
5545 01:24:40.830309 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5546 01:24:40.833234 iDelay=199, Bit 1, Center 96 (-1 ~ 194) 196
5547 01:24:40.836724 iDelay=199, Bit 2, Center 90 (-5 ~ 186) 192
5548 01:24:40.839770 iDelay=199, Bit 3, Center 90 (-5 ~ 186) 192
5549 01:24:40.843707 iDelay=199, Bit 4, Center 94 (-1 ~ 190) 192
5550 01:24:40.846629 iDelay=199, Bit 5, Center 86 (-9 ~ 182) 192
5551 01:24:40.852991 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5552 01:24:40.856469 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5553 01:24:40.859386 iDelay=199, Bit 8, Center 76 (-17 ~ 170) 188
5554 01:24:40.863092 iDelay=199, Bit 9, Center 74 (-17 ~ 166) 184
5555 01:24:40.865935 iDelay=199, Bit 10, Center 86 (-9 ~ 182) 192
5556 01:24:40.873026 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5557 01:24:40.876528 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5558 01:24:40.879744 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5559 01:24:40.882846 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5560 01:24:40.889438 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5561 01:24:40.889853 ==
5562 01:24:40.892826 Dram Type= 6, Freq= 0, CH_0, rank 1
5563 01:24:40.896130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5564 01:24:40.896544 ==
5565 01:24:40.896871 DQS Delay:
5566 01:24:40.898707 DQS0 = 0, DQS1 = 0
5567 01:24:40.899120 DQM Delay:
5568 01:24:40.902475 DQM0 = 94, DQM1 = 86
5569 01:24:40.902888 DQ Delay:
5570 01:24:40.905989 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =90
5571 01:24:40.908749 DQ4 =94, DQ5 =86, DQ6 =104, DQ7 =104
5572 01:24:40.912500 DQ8 =76, DQ9 =74, DQ10 =86, DQ11 =78
5573 01:24:40.915826 DQ12 =92, DQ13 =92, DQ14 =100, DQ15 =92
5574 01:24:40.916353
5575 01:24:40.916689
5576 01:24:40.925399 [DQSOSCAuto] RK1, (LSB)MR18= 0x26f7, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 409 ps
5577 01:24:40.925900 CH0 RK1: MR19=504, MR18=26F7
5578 01:24:40.931858 CH0_RK1: MR19=0x504, MR18=0x26F7, DQSOSC=409, MR23=63, INC=64, DEC=43
5579 01:24:40.935690 [RxdqsGatingPostProcess] freq 933
5580 01:24:40.941753 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5581 01:24:40.945240 best DQS0 dly(2T, 0.5T) = (0, 10)
5582 01:24:40.948781 best DQS1 dly(2T, 0.5T) = (0, 11)
5583 01:24:40.951838 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5584 01:24:40.954828 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5585 01:24:40.958659 best DQS0 dly(2T, 0.5T) = (0, 10)
5586 01:24:40.961291 best DQS1 dly(2T, 0.5T) = (0, 10)
5587 01:24:40.964827 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5588 01:24:40.968104 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5589 01:24:40.968624 Pre-setting of DQS Precalculation
5590 01:24:40.974942 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5591 01:24:40.975459 ==
5592 01:24:40.978156 Dram Type= 6, Freq= 0, CH_1, rank 0
5593 01:24:40.981622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5594 01:24:40.982153 ==
5595 01:24:40.988102 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5596 01:24:40.994494 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5597 01:24:40.997841 [CA 0] Center 36 (6~67) winsize 62
5598 01:24:41.000858 [CA 1] Center 37 (6~68) winsize 63
5599 01:24:41.004358 [CA 2] Center 34 (4~65) winsize 62
5600 01:24:41.007410 [CA 3] Center 33 (3~64) winsize 62
5601 01:24:41.011246 [CA 4] Center 34 (4~64) winsize 61
5602 01:24:41.014260 [CA 5] Center 33 (3~64) winsize 62
5603 01:24:41.014776
5604 01:24:41.018143 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5605 01:24:41.018661
5606 01:24:41.020740 [CATrainingPosCal] consider 1 rank data
5607 01:24:41.024597 u2DelayCellTimex100 = 270/100 ps
5608 01:24:41.027798 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5609 01:24:41.030713 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5610 01:24:41.034023 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5611 01:24:41.037812 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5612 01:24:41.044020 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5613 01:24:41.046975 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5614 01:24:41.047586
5615 01:24:41.050926 CA PerBit enable=1, Macro0, CA PI delay=33
5616 01:24:41.051439
5617 01:24:41.053657 [CBTSetCACLKResult] CA Dly = 33
5618 01:24:41.054072 CS Dly: 6 (0~37)
5619 01:24:41.054404 ==
5620 01:24:41.056870 Dram Type= 6, Freq= 0, CH_1, rank 1
5621 01:24:41.064300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5622 01:24:41.064865 ==
5623 01:24:41.067450 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5624 01:24:41.073544 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5625 01:24:41.076973 [CA 0] Center 36 (6~67) winsize 62
5626 01:24:41.080517 [CA 1] Center 36 (6~67) winsize 62
5627 01:24:41.083591 [CA 2] Center 34 (4~65) winsize 62
5628 01:24:41.086969 [CA 3] Center 33 (3~64) winsize 62
5629 01:24:41.089883 [CA 4] Center 34 (3~65) winsize 63
5630 01:24:41.093365 [CA 5] Center 33 (3~64) winsize 62
5631 01:24:41.093827
5632 01:24:41.096678 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5633 01:24:41.097139
5634 01:24:41.100333 [CATrainingPosCal] consider 2 rank data
5635 01:24:41.102842 u2DelayCellTimex100 = 270/100 ps
5636 01:24:41.106715 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5637 01:24:41.113297 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5638 01:24:41.116575 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5639 01:24:41.120058 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5640 01:24:41.123022 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5641 01:24:41.126600 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5642 01:24:41.127150
5643 01:24:41.129553 CA PerBit enable=1, Macro0, CA PI delay=33
5644 01:24:41.130080
5645 01:24:41.133569 [CBTSetCACLKResult] CA Dly = 33
5646 01:24:41.134125 CS Dly: 7 (0~39)
5647 01:24:41.135928
5648 01:24:41.139346 ----->DramcWriteLeveling(PI) begin...
5649 01:24:41.139811 ==
5650 01:24:41.142984 Dram Type= 6, Freq= 0, CH_1, rank 0
5651 01:24:41.146287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5652 01:24:41.146840 ==
5653 01:24:41.149261 Write leveling (Byte 0): 27 => 27
5654 01:24:41.152454 Write leveling (Byte 1): 30 => 30
5655 01:24:41.156024 DramcWriteLeveling(PI) end<-----
5656 01:24:41.156575
5657 01:24:41.156939 ==
5658 01:24:41.159207 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 01:24:41.162151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 01:24:41.162690 ==
5661 01:24:41.165494 [Gating] SW mode calibration
5662 01:24:41.172268 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5663 01:24:41.178637 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5664 01:24:41.182022 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5665 01:24:41.185415 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5666 01:24:41.192026 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5667 01:24:41.195454 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5668 01:24:41.198594 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5669 01:24:41.205282 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5670 01:24:41.208542 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
5671 01:24:41.212107 0 14 28 | B1->B0 | 2e2e 2b2b | 0 0 | (0 0) (1 1)
5672 01:24:41.218079 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5673 01:24:41.221871 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5674 01:24:41.225515 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5675 01:24:41.231623 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5676 01:24:41.234884 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5677 01:24:41.238233 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5678 01:24:41.244762 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5679 01:24:41.247998 0 15 28 | B1->B0 | 2929 3232 | 0 0 | (0 0) (0 0)
5680 01:24:41.250904 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5681 01:24:41.257600 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5682 01:24:41.260993 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5683 01:24:41.267794 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5684 01:24:41.271072 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5685 01:24:41.274161 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5686 01:24:41.281112 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5687 01:24:41.284314 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 01:24:41.287489 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 01:24:41.293829 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 01:24:41.297118 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 01:24:41.300734 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 01:24:41.303988 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 01:24:41.311600 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 01:24:41.313470 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 01:24:41.317093 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 01:24:41.323520 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 01:24:41.326569 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 01:24:41.330205 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 01:24:41.337109 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 01:24:41.340578 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5701 01:24:41.343116 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5702 01:24:41.350101 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5703 01:24:41.353523 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5704 01:24:41.356499 Total UI for P1: 0, mck2ui 16
5705 01:24:41.360381 best dqsien dly found for B0: ( 1, 2, 24)
5706 01:24:41.363413 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5707 01:24:41.366316 Total UI for P1: 0, mck2ui 16
5708 01:24:41.369916 best dqsien dly found for B1: ( 1, 2, 28)
5709 01:24:41.376530 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5710 01:24:41.380109 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5711 01:24:41.380658
5712 01:24:41.383391 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5713 01:24:41.386461 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5714 01:24:41.389631 [Gating] SW calibration Done
5715 01:24:41.390093 ==
5716 01:24:41.392927 Dram Type= 6, Freq= 0, CH_1, rank 0
5717 01:24:41.396167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5718 01:24:41.396631 ==
5719 01:24:41.399544 RX Vref Scan: 0
5720 01:24:41.400091
5721 01:24:41.400457 RX Vref 0 -> 0, step: 1
5722 01:24:41.400798
5723 01:24:41.402480 RX Delay -80 -> 252, step: 8
5724 01:24:41.405696 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5725 01:24:41.412851 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5726 01:24:41.416165 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5727 01:24:41.418765 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5728 01:24:41.422470 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5729 01:24:41.425566 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5730 01:24:41.428796 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5731 01:24:41.435128 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5732 01:24:41.439043 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5733 01:24:41.442000 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5734 01:24:41.445654 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5735 01:24:41.449145 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5736 01:24:41.455159 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5737 01:24:41.458386 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5738 01:24:41.462044 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5739 01:24:41.465318 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5740 01:24:41.465900 ==
5741 01:24:41.468342 Dram Type= 6, Freq= 0, CH_1, rank 0
5742 01:24:41.474452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 01:24:41.474914 ==
5744 01:24:41.475273 DQS Delay:
5745 01:24:41.475610 DQS0 = 0, DQS1 = 0
5746 01:24:41.477901 DQM Delay:
5747 01:24:41.478355 DQM0 = 100, DQM1 = 91
5748 01:24:41.481622 DQ Delay:
5749 01:24:41.484890 DQ0 =103, DQ1 =99, DQ2 =91, DQ3 =95
5750 01:24:41.488970 DQ4 =95, DQ5 =111, DQ6 =107, DQ7 =99
5751 01:24:41.491873 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5752 01:24:41.494890 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5753 01:24:41.495442
5754 01:24:41.495804
5755 01:24:41.496138 ==
5756 01:24:41.497978 Dram Type= 6, Freq= 0, CH_1, rank 0
5757 01:24:41.501579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5758 01:24:41.502130 ==
5759 01:24:41.502496
5760 01:24:41.502832
5761 01:24:41.504802 TX Vref Scan disable
5762 01:24:41.508181 == TX Byte 0 ==
5763 01:24:41.511214 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5764 01:24:41.514596 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5765 01:24:41.518171 == TX Byte 1 ==
5766 01:24:41.521486 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5767 01:24:41.523867 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5768 01:24:41.524326 ==
5769 01:24:41.527602 Dram Type= 6, Freq= 0, CH_1, rank 0
5770 01:24:41.530646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5771 01:24:41.534159 ==
5772 01:24:41.534614
5773 01:24:41.534968
5774 01:24:41.535299 TX Vref Scan disable
5775 01:24:41.538243 == TX Byte 0 ==
5776 01:24:41.541088 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5777 01:24:41.548002 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5778 01:24:41.548561 == TX Byte 1 ==
5779 01:24:41.551125 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5780 01:24:41.557984 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5781 01:24:41.558535
5782 01:24:41.558897 [DATLAT]
5783 01:24:41.559235 Freq=933, CH1 RK0
5784 01:24:41.559563
5785 01:24:41.560823 DATLAT Default: 0xd
5786 01:24:41.561282 0, 0xFFFF, sum = 0
5787 01:24:41.564386 1, 0xFFFF, sum = 0
5788 01:24:41.567199 2, 0xFFFF, sum = 0
5789 01:24:41.567703 3, 0xFFFF, sum = 0
5790 01:24:41.570434 4, 0xFFFF, sum = 0
5791 01:24:41.570879 5, 0xFFFF, sum = 0
5792 01:24:41.573863 6, 0xFFFF, sum = 0
5793 01:24:41.574287 7, 0xFFFF, sum = 0
5794 01:24:41.577483 8, 0xFFFF, sum = 0
5795 01:24:41.578000 9, 0xFFFF, sum = 0
5796 01:24:41.580717 10, 0x0, sum = 1
5797 01:24:41.581268 11, 0x0, sum = 2
5798 01:24:41.583538 12, 0x0, sum = 3
5799 01:24:41.584017 13, 0x0, sum = 4
5800 01:24:41.586966 best_step = 11
5801 01:24:41.587425
5802 01:24:41.587780 ==
5803 01:24:41.590456 Dram Type= 6, Freq= 0, CH_1, rank 0
5804 01:24:41.593493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5805 01:24:41.593913 ==
5806 01:24:41.594244 RX Vref Scan: 1
5807 01:24:41.597325
5808 01:24:41.597914 RX Vref 0 -> 0, step: 1
5809 01:24:41.598252
5810 01:24:41.600546 RX Delay -69 -> 252, step: 4
5811 01:24:41.601056
5812 01:24:41.603961 Set Vref, RX VrefLevel [Byte0]: 51
5813 01:24:41.607042 [Byte1]: 53
5814 01:24:41.610168
5815 01:24:41.610584 Final RX Vref Byte 0 = 51 to rank0
5816 01:24:41.613967 Final RX Vref Byte 1 = 53 to rank0
5817 01:24:41.617108 Final RX Vref Byte 0 = 51 to rank1
5818 01:24:41.620031 Final RX Vref Byte 1 = 53 to rank1==
5819 01:24:41.623743 Dram Type= 6, Freq= 0, CH_1, rank 0
5820 01:24:41.630225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5821 01:24:41.630710 ==
5822 01:24:41.631054 DQS Delay:
5823 01:24:41.633519 DQS0 = 0, DQS1 = 0
5824 01:24:41.633949 DQM Delay:
5825 01:24:41.634280 DQM0 = 100, DQM1 = 93
5826 01:24:41.636766 DQ Delay:
5827 01:24:41.640610 DQ0 =104, DQ1 =94, DQ2 =90, DQ3 =96
5828 01:24:41.643447 DQ4 =96, DQ5 =112, DQ6 =112, DQ7 =96
5829 01:24:41.647099 DQ8 =82, DQ9 =84, DQ10 =92, DQ11 =84
5830 01:24:41.649732 DQ12 =100, DQ13 =98, DQ14 =100, DQ15 =104
5831 01:24:41.650151
5832 01:24:41.650550
5833 01:24:41.656668 [DQSOSCAuto] RK0, (LSB)MR18= 0x1505, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 415 ps
5834 01:24:41.659827 CH1 RK0: MR19=505, MR18=1505
5835 01:24:41.666726 CH1_RK0: MR19=0x505, MR18=0x1505, DQSOSC=415, MR23=63, INC=62, DEC=41
5836 01:24:41.667355
5837 01:24:41.669650 ----->DramcWriteLeveling(PI) begin...
5838 01:24:41.670072 ==
5839 01:24:41.673388 Dram Type= 6, Freq= 0, CH_1, rank 1
5840 01:24:41.676290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5841 01:24:41.676709 ==
5842 01:24:41.679952 Write leveling (Byte 0): 24 => 24
5843 01:24:41.682843 Write leveling (Byte 1): 30 => 30
5844 01:24:41.686505 DramcWriteLeveling(PI) end<-----
5845 01:24:41.686921
5846 01:24:41.687251 ==
5847 01:24:41.689884 Dram Type= 6, Freq= 0, CH_1, rank 1
5848 01:24:41.693243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 01:24:41.696612 ==
5850 01:24:41.697120 [Gating] SW mode calibration
5851 01:24:41.706286 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5852 01:24:41.709432 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5853 01:24:41.712908 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5854 01:24:41.719402 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5855 01:24:41.722808 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5856 01:24:41.728821 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5857 01:24:41.732473 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5858 01:24:41.736445 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5859 01:24:41.742242 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
5860 01:24:41.745793 0 14 28 | B1->B0 | 2b2b 2f2f | 0 0 | (1 0) (1 0)
5861 01:24:41.749216 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5862 01:24:41.755820 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5863 01:24:41.759227 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5864 01:24:41.762272 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5865 01:24:41.768586 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5866 01:24:41.772504 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5867 01:24:41.775536 0 15 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5868 01:24:41.781474 0 15 28 | B1->B0 | 3b3b 3434 | 0 0 | (0 0) (0 0)
5869 01:24:41.785406 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5870 01:24:41.788600 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5871 01:24:41.795372 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5872 01:24:41.798271 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5873 01:24:41.801680 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5874 01:24:41.808210 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5875 01:24:41.811465 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5876 01:24:41.814839 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5877 01:24:41.821317 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5878 01:24:41.824866 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 01:24:41.828150 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 01:24:41.834512 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 01:24:41.837527 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 01:24:41.841357 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 01:24:41.847638 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 01:24:41.850945 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 01:24:41.853763 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 01:24:41.861182 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 01:24:41.864084 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 01:24:41.867642 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5889 01:24:41.874257 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5890 01:24:41.877150 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5891 01:24:41.880556 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5892 01:24:41.887595 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5893 01:24:41.888114 Total UI for P1: 0, mck2ui 16
5894 01:24:41.893710 best dqsien dly found for B1: ( 1, 2, 24)
5895 01:24:41.897157 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5896 01:24:41.900358 Total UI for P1: 0, mck2ui 16
5897 01:24:41.903701 best dqsien dly found for B0: ( 1, 2, 28)
5898 01:24:41.906998 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5899 01:24:41.910240 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5900 01:24:41.910658
5901 01:24:41.913767 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5902 01:24:41.916879 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5903 01:24:41.920067 [Gating] SW calibration Done
5904 01:24:41.920560 ==
5905 01:24:41.923288 Dram Type= 6, Freq= 0, CH_1, rank 1
5906 01:24:41.927139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5907 01:24:41.930254 ==
5908 01:24:41.930670 RX Vref Scan: 0
5909 01:24:41.931007
5910 01:24:41.933555 RX Vref 0 -> 0, step: 1
5911 01:24:41.933991
5912 01:24:41.936499 RX Delay -80 -> 252, step: 8
5913 01:24:41.940090 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5914 01:24:41.943932 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5915 01:24:41.946595 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5916 01:24:41.950140 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5917 01:24:41.953136 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5918 01:24:41.959583 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5919 01:24:41.962837 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5920 01:24:41.966080 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5921 01:24:41.969521 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5922 01:24:41.972668 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5923 01:24:41.979591 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5924 01:24:41.982826 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5925 01:24:41.985871 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5926 01:24:41.989211 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5927 01:24:41.992517 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5928 01:24:41.999845 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5929 01:24:42.000373 ==
5930 01:24:42.002194 Dram Type= 6, Freq= 0, CH_1, rank 1
5931 01:24:42.005646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5932 01:24:42.006068 ==
5933 01:24:42.006399 DQS Delay:
5934 01:24:42.008980 DQS0 = 0, DQS1 = 0
5935 01:24:42.009529 DQM Delay:
5936 01:24:42.011943 DQM0 = 100, DQM1 = 90
5937 01:24:42.012460 DQ Delay:
5938 01:24:42.015535 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =103
5939 01:24:42.018274 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5940 01:24:42.022026 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5941 01:24:42.025382 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5942 01:24:42.025812
5943 01:24:42.026146
5944 01:24:42.026452 ==
5945 01:24:42.028237 Dram Type= 6, Freq= 0, CH_1, rank 1
5946 01:24:42.035171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5947 01:24:42.035587 ==
5948 01:24:42.035915
5949 01:24:42.036220
5950 01:24:42.036510 TX Vref Scan disable
5951 01:24:42.038719 == TX Byte 0 ==
5952 01:24:42.041952 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5953 01:24:42.048645 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5954 01:24:42.049156 == TX Byte 1 ==
5955 01:24:42.051609 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5956 01:24:42.058614 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5957 01:24:42.059033 ==
5958 01:24:42.061971 Dram Type= 6, Freq= 0, CH_1, rank 1
5959 01:24:42.064849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5960 01:24:42.065268 ==
5961 01:24:42.065639
5962 01:24:42.065950
5963 01:24:42.068369 TX Vref Scan disable
5964 01:24:42.071658 == TX Byte 0 ==
5965 01:24:42.075112 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5966 01:24:42.078037 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5967 01:24:42.081152 == TX Byte 1 ==
5968 01:24:42.084485 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5969 01:24:42.087832 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5970 01:24:42.088328
5971 01:24:42.088666 [DATLAT]
5972 01:24:42.090954 Freq=933, CH1 RK1
5973 01:24:42.091370
5974 01:24:42.094461 DATLAT Default: 0xb
5975 01:24:42.094878 0, 0xFFFF, sum = 0
5976 01:24:42.097743 1, 0xFFFF, sum = 0
5977 01:24:42.098183 2, 0xFFFF, sum = 0
5978 01:24:42.101008 3, 0xFFFF, sum = 0
5979 01:24:42.101571 4, 0xFFFF, sum = 0
5980 01:24:42.104364 5, 0xFFFF, sum = 0
5981 01:24:42.104793 6, 0xFFFF, sum = 0
5982 01:24:42.107255 7, 0xFFFF, sum = 0
5983 01:24:42.107702 8, 0xFFFF, sum = 0
5984 01:24:42.111068 9, 0xFFFF, sum = 0
5985 01:24:42.111502 10, 0x0, sum = 1
5986 01:24:42.114301 11, 0x0, sum = 2
5987 01:24:42.114722 12, 0x0, sum = 3
5988 01:24:42.117802 13, 0x0, sum = 4
5989 01:24:42.118220 best_step = 11
5990 01:24:42.118547
5991 01:24:42.118853 ==
5992 01:24:42.120915 Dram Type= 6, Freq= 0, CH_1, rank 1
5993 01:24:42.127266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5994 01:24:42.127680 ==
5995 01:24:42.128008 RX Vref Scan: 0
5996 01:24:42.128317
5997 01:24:42.130138 RX Vref 0 -> 0, step: 1
5998 01:24:42.130682
5999 01:24:42.133466 RX Delay -61 -> 252, step: 4
6000 01:24:42.136997 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
6001 01:24:42.140655 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
6002 01:24:42.147200 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
6003 01:24:42.150375 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6004 01:24:42.153742 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
6005 01:24:42.156945 iDelay=207, Bit 5, Center 108 (19 ~ 198) 180
6006 01:24:42.159990 iDelay=207, Bit 6, Center 112 (19 ~ 206) 188
6007 01:24:42.166914 iDelay=207, Bit 7, Center 100 (11 ~ 190) 180
6008 01:24:42.170221 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
6009 01:24:42.173675 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
6010 01:24:42.176205 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
6011 01:24:42.179505 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6012 01:24:42.185926 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
6013 01:24:42.189717 iDelay=207, Bit 13, Center 100 (11 ~ 190) 180
6014 01:24:42.192977 iDelay=207, Bit 14, Center 100 (11 ~ 190) 180
6015 01:24:42.196258 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6016 01:24:42.196824 ==
6017 01:24:42.199066 Dram Type= 6, Freq= 0, CH_1, rank 1
6018 01:24:42.205686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6019 01:24:42.206248 ==
6020 01:24:42.206740 DQS Delay:
6021 01:24:42.209394 DQS0 = 0, DQS1 = 0
6022 01:24:42.209765 DQM Delay:
6023 01:24:42.212657 DQM0 = 101, DQM1 = 93
6024 01:24:42.213077 DQ Delay:
6025 01:24:42.216066 DQ0 =106, DQ1 =94, DQ2 =90, DQ3 =98
6026 01:24:42.219048 DQ4 =100, DQ5 =108, DQ6 =112, DQ7 =100
6027 01:24:42.222348 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =84
6028 01:24:42.225891 DQ12 =102, DQ13 =100, DQ14 =100, DQ15 =102
6029 01:24:42.226310
6030 01:24:42.226641
6031 01:24:42.235208 [DQSOSCAuto] RK1, (LSB)MR18= 0x4fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 420 ps
6032 01:24:42.235643 CH1 RK1: MR19=504, MR18=4FE
6033 01:24:42.242436 CH1_RK1: MR19=0x504, MR18=0x4FE, DQSOSC=420, MR23=63, INC=61, DEC=40
6034 01:24:42.245488 [RxdqsGatingPostProcess] freq 933
6035 01:24:42.252284 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6036 01:24:42.255122 best DQS0 dly(2T, 0.5T) = (0, 10)
6037 01:24:42.258597 best DQS1 dly(2T, 0.5T) = (0, 10)
6038 01:24:42.261558 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6039 01:24:42.265054 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6040 01:24:42.268789 best DQS0 dly(2T, 0.5T) = (0, 10)
6041 01:24:42.269296 best DQS1 dly(2T, 0.5T) = (0, 10)
6042 01:24:42.271608 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6043 01:24:42.275274 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6044 01:24:42.278533 Pre-setting of DQS Precalculation
6045 01:24:42.285196 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6046 01:24:42.291118 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6047 01:24:42.298115 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6048 01:24:42.298645
6049 01:24:42.298978
6050 01:24:42.301319 [Calibration Summary] 1866 Mbps
6051 01:24:42.304234 CH 0, Rank 0
6052 01:24:42.304650 SW Impedance : PASS
6053 01:24:42.308407 DUTY Scan : NO K
6054 01:24:42.310936 ZQ Calibration : PASS
6055 01:24:42.311358 Jitter Meter : NO K
6056 01:24:42.314533 CBT Training : PASS
6057 01:24:42.317767 Write leveling : PASS
6058 01:24:42.318189 RX DQS gating : PASS
6059 01:24:42.321176 RX DQ/DQS(RDDQC) : PASS
6060 01:24:42.321753 TX DQ/DQS : PASS
6061 01:24:42.324085 RX DATLAT : PASS
6062 01:24:42.327760 RX DQ/DQS(Engine): PASS
6063 01:24:42.328269 TX OE : NO K
6064 01:24:42.330959 All Pass.
6065 01:24:42.331375
6066 01:24:42.331721 CH 0, Rank 1
6067 01:24:42.333812 SW Impedance : PASS
6068 01:24:42.334231 DUTY Scan : NO K
6069 01:24:42.337306 ZQ Calibration : PASS
6070 01:24:42.340928 Jitter Meter : NO K
6071 01:24:42.341382 CBT Training : PASS
6072 01:24:42.344342 Write leveling : PASS
6073 01:24:42.347580 RX DQS gating : PASS
6074 01:24:42.348106 RX DQ/DQS(RDDQC) : PASS
6075 01:24:42.350670 TX DQ/DQS : PASS
6076 01:24:42.353770 RX DATLAT : PASS
6077 01:24:42.354415 RX DQ/DQS(Engine): PASS
6078 01:24:42.357161 TX OE : NO K
6079 01:24:42.357619 All Pass.
6080 01:24:42.357958
6081 01:24:42.360658 CH 1, Rank 0
6082 01:24:42.361164 SW Impedance : PASS
6083 01:24:42.363565 DUTY Scan : NO K
6084 01:24:42.366870 ZQ Calibration : PASS
6085 01:24:42.367380 Jitter Meter : NO K
6086 01:24:42.370190 CBT Training : PASS
6087 01:24:42.373764 Write leveling : PASS
6088 01:24:42.374275 RX DQS gating : PASS
6089 01:24:42.376758 RX DQ/DQS(RDDQC) : PASS
6090 01:24:42.380307 TX DQ/DQS : PASS
6091 01:24:42.380850 RX DATLAT : PASS
6092 01:24:42.383551 RX DQ/DQS(Engine): PASS
6093 01:24:42.387121 TX OE : NO K
6094 01:24:42.387644 All Pass.
6095 01:24:42.387982
6096 01:24:42.388292 CH 1, Rank 1
6097 01:24:42.390077 SW Impedance : PASS
6098 01:24:42.393807 DUTY Scan : NO K
6099 01:24:42.394314 ZQ Calibration : PASS
6100 01:24:42.396964 Jitter Meter : NO K
6101 01:24:42.400313 CBT Training : PASS
6102 01:24:42.400825 Write leveling : PASS
6103 01:24:42.403273 RX DQS gating : PASS
6104 01:24:42.406352 RX DQ/DQS(RDDQC) : PASS
6105 01:24:42.406817 TX DQ/DQS : PASS
6106 01:24:42.409816 RX DATLAT : PASS
6107 01:24:42.410391 RX DQ/DQS(Engine): PASS
6108 01:24:42.413097 TX OE : NO K
6109 01:24:42.413657 All Pass.
6110 01:24:42.413997
6111 01:24:42.416505 DramC Write-DBI off
6112 01:24:42.419325 PER_BANK_REFRESH: Hybrid Mode
6113 01:24:42.419758 TX_TRACKING: ON
6114 01:24:42.429377 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6115 01:24:42.432500 [FAST_K] Save calibration result to emmc
6116 01:24:42.436309 dramc_set_vcore_voltage set vcore to 650000
6117 01:24:42.439282 Read voltage for 400, 6
6118 01:24:42.439850 Vio18 = 0
6119 01:24:42.442900 Vcore = 650000
6120 01:24:42.443408 Vdram = 0
6121 01:24:42.443821 Vddq = 0
6122 01:24:42.444146 Vmddr = 0
6123 01:24:42.449319 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6124 01:24:42.455771 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6125 01:24:42.456273 MEM_TYPE=3, freq_sel=20
6126 01:24:42.458992 sv_algorithm_assistance_LP4_800
6127 01:24:42.461984 ============ PULL DRAM RESETB DOWN ============
6128 01:24:42.468766 ========== PULL DRAM RESETB DOWN end =========
6129 01:24:42.472122 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6130 01:24:42.475712 ===================================
6131 01:24:42.478492 LPDDR4 DRAM CONFIGURATION
6132 01:24:42.482248 ===================================
6133 01:24:42.482758 EX_ROW_EN[0] = 0x0
6134 01:24:42.485059 EX_ROW_EN[1] = 0x0
6135 01:24:42.488372 LP4Y_EN = 0x0
6136 01:24:42.488789 WORK_FSP = 0x0
6137 01:24:42.492544 WL = 0x2
6138 01:24:42.493055 RL = 0x2
6139 01:24:42.495248 BL = 0x2
6140 01:24:42.495662 RPST = 0x0
6141 01:24:42.498436 RD_PRE = 0x0
6142 01:24:42.498948 WR_PRE = 0x1
6143 01:24:42.502268 WR_PST = 0x0
6144 01:24:42.502775 DBI_WR = 0x0
6145 01:24:42.504889 DBI_RD = 0x0
6146 01:24:42.505303 OTF = 0x1
6147 01:24:42.508383 ===================================
6148 01:24:42.511887 ===================================
6149 01:24:42.515164 ANA top config
6150 01:24:42.518102 ===================================
6151 01:24:42.521802 DLL_ASYNC_EN = 0
6152 01:24:42.522222 ALL_SLAVE_EN = 1
6153 01:24:42.524636 NEW_RANK_MODE = 1
6154 01:24:42.528108 DLL_IDLE_MODE = 1
6155 01:24:42.531336 LP45_APHY_COMB_EN = 1
6156 01:24:42.531756 TX_ODT_DIS = 1
6157 01:24:42.534864 NEW_8X_MODE = 1
6158 01:24:42.538164 ===================================
6159 01:24:42.541181 ===================================
6160 01:24:42.544679 data_rate = 800
6161 01:24:42.547824 CKR = 1
6162 01:24:42.551276 DQ_P2S_RATIO = 4
6163 01:24:42.554500 ===================================
6164 01:24:42.557951 CA_P2S_RATIO = 4
6165 01:24:42.558386 DQ_CA_OPEN = 0
6166 01:24:42.561022 DQ_SEMI_OPEN = 1
6167 01:24:42.564419 CA_SEMI_OPEN = 1
6168 01:24:42.567689 CA_FULL_RATE = 0
6169 01:24:42.570819 DQ_CKDIV4_EN = 0
6170 01:24:42.574099 CA_CKDIV4_EN = 1
6171 01:24:42.574636 CA_PREDIV_EN = 0
6172 01:24:42.577794 PH8_DLY = 0
6173 01:24:42.580856 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6174 01:24:42.584670 DQ_AAMCK_DIV = 0
6175 01:24:42.587170 CA_AAMCK_DIV = 0
6176 01:24:42.590345 CA_ADMCK_DIV = 4
6177 01:24:42.593946 DQ_TRACK_CA_EN = 0
6178 01:24:42.594472 CA_PICK = 800
6179 01:24:42.596982 CA_MCKIO = 400
6180 01:24:42.600455 MCKIO_SEMI = 400
6181 01:24:42.604173 PLL_FREQ = 3016
6182 01:24:42.607230 DQ_UI_PI_RATIO = 32
6183 01:24:42.610603 CA_UI_PI_RATIO = 32
6184 01:24:42.613836 ===================================
6185 01:24:42.617316 ===================================
6186 01:24:42.620198 memory_type:LPDDR4
6187 01:24:42.620615 GP_NUM : 10
6188 01:24:42.623970 SRAM_EN : 1
6189 01:24:42.624487 MD32_EN : 0
6190 01:24:42.627111 ===================================
6191 01:24:42.629825 [ANA_INIT] >>>>>>>>>>>>>>
6192 01:24:42.633211 <<<<<< [CONFIGURE PHASE]: ANA_TX
6193 01:24:42.637155 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6194 01:24:42.640032 ===================================
6195 01:24:42.643305 data_rate = 800,PCW = 0X7400
6196 01:24:42.646856 ===================================
6197 01:24:42.649908 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6198 01:24:42.656119 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6199 01:24:42.666457 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6200 01:24:42.669660 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6201 01:24:42.676315 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6202 01:24:42.679141 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6203 01:24:42.679563 [ANA_INIT] flow start
6204 01:24:42.683010 [ANA_INIT] PLL >>>>>>>>
6205 01:24:42.685889 [ANA_INIT] PLL <<<<<<<<
6206 01:24:42.686310 [ANA_INIT] MIDPI >>>>>>>>
6207 01:24:42.689430 [ANA_INIT] MIDPI <<<<<<<<
6208 01:24:42.692576 [ANA_INIT] DLL >>>>>>>>
6209 01:24:42.693269 [ANA_INIT] flow end
6210 01:24:42.699368 ============ LP4 DIFF to SE enter ============
6211 01:24:42.702674 ============ LP4 DIFF to SE exit ============
6212 01:24:42.703238 [ANA_INIT] <<<<<<<<<<<<<
6213 01:24:42.706019 [Flow] Enable top DCM control >>>>>
6214 01:24:42.709183 [Flow] Enable top DCM control <<<<<
6215 01:24:42.712198 Enable DLL master slave shuffle
6216 01:24:42.719013 ==============================================================
6217 01:24:42.722208 Gating Mode config
6218 01:24:42.725456 ==============================================================
6219 01:24:42.728709 Config description:
6220 01:24:42.738741 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6221 01:24:42.745296 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6222 01:24:42.748238 SELPH_MODE 0: By rank 1: By Phase
6223 01:24:42.755252 ==============================================================
6224 01:24:42.759005 GAT_TRACK_EN = 0
6225 01:24:42.761565 RX_GATING_MODE = 2
6226 01:24:42.765128 RX_GATING_TRACK_MODE = 2
6227 01:24:42.768566 SELPH_MODE = 1
6228 01:24:42.771983 PICG_EARLY_EN = 1
6229 01:24:42.772493 VALID_LAT_VALUE = 1
6230 01:24:42.778703 ==============================================================
6231 01:24:42.781396 Enter into Gating configuration >>>>
6232 01:24:42.785372 Exit from Gating configuration <<<<
6233 01:24:42.788169 Enter into DVFS_PRE_config >>>>>
6234 01:24:42.798176 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6235 01:24:42.801392 Exit from DVFS_PRE_config <<<<<
6236 01:24:42.804658 Enter into PICG configuration >>>>
6237 01:24:42.807958 Exit from PICG configuration <<<<
6238 01:24:42.811284 [RX_INPUT] configuration >>>>>
6239 01:24:42.814373 [RX_INPUT] configuration <<<<<
6240 01:24:42.820900 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6241 01:24:42.824593 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6242 01:24:42.830925 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6243 01:24:42.837311 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6244 01:24:42.844698 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6245 01:24:42.851047 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6246 01:24:42.853918 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6247 01:24:42.857245 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6248 01:24:42.860642 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6249 01:24:42.867178 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6250 01:24:42.870365 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6251 01:24:42.873955 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6252 01:24:42.877410 ===================================
6253 01:24:42.880479 LPDDR4 DRAM CONFIGURATION
6254 01:24:42.883701 ===================================
6255 01:24:42.887212 EX_ROW_EN[0] = 0x0
6256 01:24:42.887741 EX_ROW_EN[1] = 0x0
6257 01:24:42.890058 LP4Y_EN = 0x0
6258 01:24:42.890476 WORK_FSP = 0x0
6259 01:24:42.893531 WL = 0x2
6260 01:24:42.894150 RL = 0x2
6261 01:24:42.896844 BL = 0x2
6262 01:24:42.897257 RPST = 0x0
6263 01:24:42.899772 RD_PRE = 0x0
6264 01:24:42.900245 WR_PRE = 0x1
6265 01:24:42.903725 WR_PST = 0x0
6266 01:24:42.904234 DBI_WR = 0x0
6267 01:24:42.906751 DBI_RD = 0x0
6268 01:24:42.907292 OTF = 0x1
6269 01:24:42.910264 ===================================
6270 01:24:42.916767 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6271 01:24:42.919652 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6272 01:24:42.923582 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6273 01:24:42.926404 ===================================
6274 01:24:42.929696 LPDDR4 DRAM CONFIGURATION
6275 01:24:42.932620 ===================================
6276 01:24:42.936333 EX_ROW_EN[0] = 0x10
6277 01:24:42.936847 EX_ROW_EN[1] = 0x0
6278 01:24:42.939701 LP4Y_EN = 0x0
6279 01:24:42.940210 WORK_FSP = 0x0
6280 01:24:42.943014 WL = 0x2
6281 01:24:42.943523 RL = 0x2
6282 01:24:42.946279 BL = 0x2
6283 01:24:42.946794 RPST = 0x0
6284 01:24:42.949559 RD_PRE = 0x0
6285 01:24:42.950105 WR_PRE = 0x1
6286 01:24:42.952312 WR_PST = 0x0
6287 01:24:42.952729 DBI_WR = 0x0
6288 01:24:42.955664 DBI_RD = 0x0
6289 01:24:42.959140 OTF = 0x1
6290 01:24:42.962321 ===================================
6291 01:24:42.966190 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6292 01:24:42.971320 nWR fixed to 30
6293 01:24:42.974247 [ModeRegInit_LP4] CH0 RK0
6294 01:24:42.974759 [ModeRegInit_LP4] CH0 RK1
6295 01:24:42.977894 [ModeRegInit_LP4] CH1 RK0
6296 01:24:42.980824 [ModeRegInit_LP4] CH1 RK1
6297 01:24:42.981358 match AC timing 19
6298 01:24:42.988004 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6299 01:24:42.990826 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6300 01:24:42.994340 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6301 01:24:43.000652 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6302 01:24:43.004011 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6303 01:24:43.004547 ==
6304 01:24:43.007099 Dram Type= 6, Freq= 0, CH_0, rank 0
6305 01:24:43.010718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 01:24:43.011354 ==
6307 01:24:43.017392 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6308 01:24:43.023464 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6309 01:24:43.027244 [CA 0] Center 36 (8~64) winsize 57
6310 01:24:43.030281 [CA 1] Center 36 (8~64) winsize 57
6311 01:24:43.033496 [CA 2] Center 36 (8~64) winsize 57
6312 01:24:43.036952 [CA 3] Center 36 (8~64) winsize 57
6313 01:24:43.040384 [CA 4] Center 36 (8~64) winsize 57
6314 01:24:43.043137 [CA 5] Center 36 (8~64) winsize 57
6315 01:24:43.043604
6316 01:24:43.046545 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6317 01:24:43.047103
6318 01:24:43.049888 [CATrainingPosCal] consider 1 rank data
6319 01:24:43.053072 u2DelayCellTimex100 = 270/100 ps
6320 01:24:43.056529 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 01:24:43.059916 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 01:24:43.062984 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 01:24:43.066378 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 01:24:43.069926 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 01:24:43.073239 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 01:24:43.073742
6327 01:24:43.076580 CA PerBit enable=1, Macro0, CA PI delay=36
6328 01:24:43.079646
6329 01:24:43.080198 [CBTSetCACLKResult] CA Dly = 36
6330 01:24:43.082845 CS Dly: 1 (0~32)
6331 01:24:43.083302 ==
6332 01:24:43.086237 Dram Type= 6, Freq= 0, CH_0, rank 1
6333 01:24:43.090028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 01:24:43.090580 ==
6335 01:24:43.096276 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6336 01:24:43.103104 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6337 01:24:43.106231 [CA 0] Center 36 (8~64) winsize 57
6338 01:24:43.109751 [CA 1] Center 36 (8~64) winsize 57
6339 01:24:43.113408 [CA 2] Center 36 (8~64) winsize 57
6340 01:24:43.113990 [CA 3] Center 36 (8~64) winsize 57
6341 01:24:43.116216 [CA 4] Center 36 (8~64) winsize 57
6342 01:24:43.119571 [CA 5] Center 36 (8~64) winsize 57
6343 01:24:43.120126
6344 01:24:43.126029 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6345 01:24:43.126585
6346 01:24:43.129283 [CATrainingPosCal] consider 2 rank data
6347 01:24:43.132499 u2DelayCellTimex100 = 270/100 ps
6348 01:24:43.136187 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6349 01:24:43.138968 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6350 01:24:43.142928 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6351 01:24:43.145860 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6352 01:24:43.149127 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6353 01:24:43.152720 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6354 01:24:43.153268
6355 01:24:43.155921 CA PerBit enable=1, Macro0, CA PI delay=36
6356 01:24:43.156378
6357 01:24:43.158919 [CBTSetCACLKResult] CA Dly = 36
6358 01:24:43.162069 CS Dly: 1 (0~32)
6359 01:24:43.162524
6360 01:24:43.165695 ----->DramcWriteLeveling(PI) begin...
6361 01:24:43.166156 ==
6362 01:24:43.168673 Dram Type= 6, Freq= 0, CH_0, rank 0
6363 01:24:43.172262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6364 01:24:43.172719 ==
6365 01:24:43.175604 Write leveling (Byte 0): 40 => 8
6366 01:24:43.178713 Write leveling (Byte 1): 32 => 0
6367 01:24:43.181631 DramcWriteLeveling(PI) end<-----
6368 01:24:43.182038
6369 01:24:43.182363 ==
6370 01:24:43.185053 Dram Type= 6, Freq= 0, CH_0, rank 0
6371 01:24:43.188555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6372 01:24:43.188966 ==
6373 01:24:43.192193 [Gating] SW mode calibration
6374 01:24:43.199016 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6375 01:24:43.205390 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6376 01:24:43.208376 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6377 01:24:43.214942 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6378 01:24:43.218651 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6379 01:24:43.221424 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6380 01:24:43.227852 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6381 01:24:43.231624 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6382 01:24:43.234819 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6383 01:24:43.241129 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6384 01:24:43.244529 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6385 01:24:43.247511 Total UI for P1: 0, mck2ui 16
6386 01:24:43.251211 best dqsien dly found for B0: ( 0, 14, 24)
6387 01:24:43.254045 Total UI for P1: 0, mck2ui 16
6388 01:24:43.257580 best dqsien dly found for B1: ( 0, 14, 24)
6389 01:24:43.261193 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6390 01:24:43.264373 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6391 01:24:43.264974
6392 01:24:43.267091 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6393 01:24:43.270667 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6394 01:24:43.274291 [Gating] SW calibration Done
6395 01:24:43.274750 ==
6396 01:24:43.277268 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 01:24:43.283946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 01:24:43.284466 ==
6399 01:24:43.284800 RX Vref Scan: 0
6400 01:24:43.285108
6401 01:24:43.287319 RX Vref 0 -> 0, step: 1
6402 01:24:43.287850
6403 01:24:43.290377 RX Delay -410 -> 252, step: 16
6404 01:24:43.293451 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6405 01:24:43.297051 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6406 01:24:43.303443 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6407 01:24:43.306878 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6408 01:24:43.310044 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6409 01:24:43.313389 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6410 01:24:43.320261 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6411 01:24:43.323120 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6412 01:24:43.326665 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6413 01:24:43.330643 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6414 01:24:43.336658 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6415 01:24:43.339733 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6416 01:24:43.343188 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6417 01:24:43.349728 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6418 01:24:43.352742 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6419 01:24:43.355910 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6420 01:24:43.356323 ==
6421 01:24:43.359179 Dram Type= 6, Freq= 0, CH_0, rank 0
6422 01:24:43.362936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 01:24:43.366292 ==
6424 01:24:43.366704 DQS Delay:
6425 01:24:43.367034 DQS0 = 43, DQS1 = 59
6426 01:24:43.369711 DQM Delay:
6427 01:24:43.370122 DQM0 = 10, DQM1 = 13
6428 01:24:43.372941 DQ Delay:
6429 01:24:43.373380 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6430 01:24:43.375929 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6431 01:24:43.379379 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6432 01:24:43.382446 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =16
6433 01:24:43.382857
6434 01:24:43.383185
6435 01:24:43.383491 ==
6436 01:24:43.385683 Dram Type= 6, Freq= 0, CH_0, rank 0
6437 01:24:43.392225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6438 01:24:43.392655 ==
6439 01:24:43.392985
6440 01:24:43.393293
6441 01:24:43.395619 TX Vref Scan disable
6442 01:24:43.396032 == TX Byte 0 ==
6443 01:24:43.399228 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6444 01:24:43.406215 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6445 01:24:43.406724 == TX Byte 1 ==
6446 01:24:43.409365 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6447 01:24:43.415984 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6448 01:24:43.416523 ==
6449 01:24:43.419212 Dram Type= 6, Freq= 0, CH_0, rank 0
6450 01:24:43.422187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6451 01:24:43.422605 ==
6452 01:24:43.422932
6453 01:24:43.423237
6454 01:24:43.425194 TX Vref Scan disable
6455 01:24:43.425637 == TX Byte 0 ==
6456 01:24:43.431615 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6457 01:24:43.435144 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6458 01:24:43.435559 == TX Byte 1 ==
6459 01:24:43.441814 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6460 01:24:43.445379 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6461 01:24:43.445898
6462 01:24:43.446229 [DATLAT]
6463 01:24:43.448373 Freq=400, CH0 RK0
6464 01:24:43.448786
6465 01:24:43.449191 DATLAT Default: 0xf
6466 01:24:43.451981 0, 0xFFFF, sum = 0
6467 01:24:43.452500 1, 0xFFFF, sum = 0
6468 01:24:43.454844 2, 0xFFFF, sum = 0
6469 01:24:43.455280 3, 0xFFFF, sum = 0
6470 01:24:43.457958 4, 0xFFFF, sum = 0
6471 01:24:43.458376 5, 0xFFFF, sum = 0
6472 01:24:43.461278 6, 0xFFFF, sum = 0
6473 01:24:43.461735 7, 0xFFFF, sum = 0
6474 01:24:43.464757 8, 0xFFFF, sum = 0
6475 01:24:43.465276 9, 0xFFFF, sum = 0
6476 01:24:43.468433 10, 0xFFFF, sum = 0
6477 01:24:43.471696 11, 0xFFFF, sum = 0
6478 01:24:43.472116 12, 0xFFFF, sum = 0
6479 01:24:43.474761 13, 0x0, sum = 1
6480 01:24:43.475194 14, 0x0, sum = 2
6481 01:24:43.475527 15, 0x0, sum = 3
6482 01:24:43.478064 16, 0x0, sum = 4
6483 01:24:43.478482 best_step = 14
6484 01:24:43.478808
6485 01:24:43.481408 ==
6486 01:24:43.484528 Dram Type= 6, Freq= 0, CH_0, rank 0
6487 01:24:43.487963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6488 01:24:43.488478 ==
6489 01:24:43.488817 RX Vref Scan: 1
6490 01:24:43.489127
6491 01:24:43.491917 RX Vref 0 -> 0, step: 1
6492 01:24:43.492426
6493 01:24:43.494642 RX Delay -359 -> 252, step: 8
6494 01:24:43.495148
6495 01:24:43.498167 Set Vref, RX VrefLevel [Byte0]: 65
6496 01:24:43.500928 [Byte1]: 49
6497 01:24:43.505294
6498 01:24:43.505847 Final RX Vref Byte 0 = 65 to rank0
6499 01:24:43.508432 Final RX Vref Byte 1 = 49 to rank0
6500 01:24:43.512086 Final RX Vref Byte 0 = 65 to rank1
6501 01:24:43.514961 Final RX Vref Byte 1 = 49 to rank1==
6502 01:24:43.518682 Dram Type= 6, Freq= 0, CH_0, rank 0
6503 01:24:43.524673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 01:24:43.525185 ==
6505 01:24:43.525574 DQS Delay:
6506 01:24:43.528162 DQS0 = 48, DQS1 = 60
6507 01:24:43.528675 DQM Delay:
6508 01:24:43.529010 DQM0 = 12, DQM1 = 11
6509 01:24:43.531504 DQ Delay:
6510 01:24:43.534213 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6511 01:24:43.537806 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =24
6512 01:24:43.538313 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6513 01:24:43.544425 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6514 01:24:43.544925
6515 01:24:43.545251
6516 01:24:43.551209 [DQSOSCAuto] RK0, (LSB)MR18= 0xb478, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 387 ps
6517 01:24:43.554336 CH0 RK0: MR19=C0C, MR18=B478
6518 01:24:43.560845 CH0_RK0: MR19=0xC0C, MR18=0xB478, DQSOSC=387, MR23=63, INC=394, DEC=262
6519 01:24:43.561372 ==
6520 01:24:43.564697 Dram Type= 6, Freq= 0, CH_0, rank 1
6521 01:24:43.567949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6522 01:24:43.568460 ==
6523 01:24:43.570685 [Gating] SW mode calibration
6524 01:24:43.577451 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6525 01:24:43.583952 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6526 01:24:43.587133 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6527 01:24:43.590501 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6528 01:24:43.597430 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6529 01:24:43.600964 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6530 01:24:43.603885 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6531 01:24:43.610481 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6532 01:24:43.613940 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6533 01:24:43.617100 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6534 01:24:43.623622 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6535 01:24:43.626729 Total UI for P1: 0, mck2ui 16
6536 01:24:43.629932 best dqsien dly found for B0: ( 0, 14, 24)
6537 01:24:43.633568 Total UI for P1: 0, mck2ui 16
6538 01:24:43.636609 best dqsien dly found for B1: ( 0, 14, 24)
6539 01:24:43.639844 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6540 01:24:43.643974 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6541 01:24:43.644526
6542 01:24:43.646675 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6543 01:24:43.649914 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6544 01:24:43.653392 [Gating] SW calibration Done
6545 01:24:43.653883 ==
6546 01:24:43.656676 Dram Type= 6, Freq= 0, CH_0, rank 1
6547 01:24:43.659647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6548 01:24:43.660109 ==
6549 01:24:43.663223 RX Vref Scan: 0
6550 01:24:43.663772
6551 01:24:43.666061 RX Vref 0 -> 0, step: 1
6552 01:24:43.666513
6553 01:24:43.667063 RX Delay -410 -> 252, step: 16
6554 01:24:43.672843 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6555 01:24:43.676768 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6556 01:24:43.679788 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6557 01:24:43.686271 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6558 01:24:43.690025 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6559 01:24:43.693006 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6560 01:24:43.696340 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6561 01:24:43.702547 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6562 01:24:43.705909 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6563 01:24:43.709559 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6564 01:24:43.712694 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6565 01:24:43.719619 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6566 01:24:43.722484 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6567 01:24:43.725827 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6568 01:24:43.729166 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6569 01:24:43.735473 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6570 01:24:43.735930 ==
6571 01:24:43.738678 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 01:24:43.742058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 01:24:43.742611 ==
6574 01:24:43.745574 DQS Delay:
6575 01:24:43.746123 DQS0 = 35, DQS1 = 59
6576 01:24:43.746486 DQM Delay:
6577 01:24:43.749244 DQM0 = 3, DQM1 = 17
6578 01:24:43.749844 DQ Delay:
6579 01:24:43.751978 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6580 01:24:43.755503 DQ4 =0, DQ5 =0, DQ6 =8, DQ7 =8
6581 01:24:43.758760 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6582 01:24:43.761937 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6583 01:24:43.762390
6584 01:24:43.762746
6585 01:24:43.763075 ==
6586 01:24:43.765092 Dram Type= 6, Freq= 0, CH_0, rank 1
6587 01:24:43.768364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6588 01:24:43.768820 ==
6589 01:24:43.769180
6590 01:24:43.771821
6591 01:24:43.772371 TX Vref Scan disable
6592 01:24:43.775486 == TX Byte 0 ==
6593 01:24:43.778494 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6594 01:24:43.781836 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6595 01:24:43.785295 == TX Byte 1 ==
6596 01:24:43.788608 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6597 01:24:43.791439 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6598 01:24:43.791893 ==
6599 01:24:43.794803 Dram Type= 6, Freq= 0, CH_0, rank 1
6600 01:24:43.798311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6601 01:24:43.801565 ==
6602 01:24:43.802022
6603 01:24:43.802461
6604 01:24:43.802795 TX Vref Scan disable
6605 01:24:43.804687 == TX Byte 0 ==
6606 01:24:43.808204 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6607 01:24:43.811537 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6608 01:24:43.815288 == TX Byte 1 ==
6609 01:24:43.818300 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6610 01:24:43.821320 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6611 01:24:43.821901
6612 01:24:43.822261 [DATLAT]
6613 01:24:43.824869 Freq=400, CH0 RK1
6614 01:24:43.825474
6615 01:24:43.827911 DATLAT Default: 0xe
6616 01:24:43.828461 0, 0xFFFF, sum = 0
6617 01:24:43.831351 1, 0xFFFF, sum = 0
6618 01:24:43.831809 2, 0xFFFF, sum = 0
6619 01:24:43.834141 3, 0xFFFF, sum = 0
6620 01:24:43.834672 4, 0xFFFF, sum = 0
6621 01:24:43.837789 5, 0xFFFF, sum = 0
6622 01:24:43.838345 6, 0xFFFF, sum = 0
6623 01:24:43.841359 7, 0xFFFF, sum = 0
6624 01:24:43.841826 8, 0xFFFF, sum = 0
6625 01:24:43.844692 9, 0xFFFF, sum = 0
6626 01:24:43.845246 10, 0xFFFF, sum = 0
6627 01:24:43.847236 11, 0xFFFF, sum = 0
6628 01:24:43.850667 12, 0xFFFF, sum = 0
6629 01:24:43.851126 13, 0x0, sum = 1
6630 01:24:43.851490 14, 0x0, sum = 2
6631 01:24:43.854262 15, 0x0, sum = 3
6632 01:24:43.854820 16, 0x0, sum = 4
6633 01:24:43.857362 best_step = 14
6634 01:24:43.857843
6635 01:24:43.858208 ==
6636 01:24:43.860944 Dram Type= 6, Freq= 0, CH_0, rank 1
6637 01:24:43.863930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6638 01:24:43.864392 ==
6639 01:24:43.867459 RX Vref Scan: 0
6640 01:24:43.868006
6641 01:24:43.868367 RX Vref 0 -> 0, step: 1
6642 01:24:43.870155
6643 01:24:43.870613 RX Delay -359 -> 252, step: 8
6644 01:24:43.878785 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6645 01:24:43.882924 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6646 01:24:43.885326 iDelay=217, Bit 2, Center -44 (-287 ~ 200) 488
6647 01:24:43.892268 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6648 01:24:43.895738 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6649 01:24:43.898626 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6650 01:24:43.901987 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6651 01:24:43.908631 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6652 01:24:43.911690 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6653 01:24:43.915548 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6654 01:24:43.918086 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6655 01:24:43.925057 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6656 01:24:43.928238 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6657 01:24:43.931637 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6658 01:24:43.938311 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6659 01:24:43.941704 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6660 01:24:43.942255 ==
6661 01:24:43.944363 Dram Type= 6, Freq= 0, CH_0, rank 1
6662 01:24:43.947799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6663 01:24:43.948370 ==
6664 01:24:43.951102 DQS Delay:
6665 01:24:43.951663 DQS0 = 44, DQS1 = 60
6666 01:24:43.952033 DQM Delay:
6667 01:24:43.955342 DQM0 = 6, DQM1 = 14
6668 01:24:43.955907 DQ Delay:
6669 01:24:43.957581 DQ0 =4, DQ1 =8, DQ2 =0, DQ3 =0
6670 01:24:43.960997 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6671 01:24:43.964549 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6672 01:24:43.968018 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6673 01:24:43.968568
6674 01:24:43.968935
6675 01:24:43.977409 [DQSOSCAuto] RK1, (LSB)MR18= 0xad3a, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 388 ps
6676 01:24:43.977963 CH0 RK1: MR19=C0C, MR18=AD3A
6677 01:24:43.984252 CH0_RK1: MR19=0xC0C, MR18=0xAD3A, DQSOSC=388, MR23=63, INC=392, DEC=261
6678 01:24:43.987236 [RxdqsGatingPostProcess] freq 400
6679 01:24:43.993755 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6680 01:24:43.997176 best DQS0 dly(2T, 0.5T) = (0, 10)
6681 01:24:44.001170 best DQS1 dly(2T, 0.5T) = (0, 10)
6682 01:24:44.003665 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6683 01:24:44.007348 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6684 01:24:44.010368 best DQS0 dly(2T, 0.5T) = (0, 10)
6685 01:24:44.013819 best DQS1 dly(2T, 0.5T) = (0, 10)
6686 01:24:44.017195 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6687 01:24:44.020129 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6688 01:24:44.020678 Pre-setting of DQS Precalculation
6689 01:24:44.026758 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6690 01:24:44.027219 ==
6691 01:24:44.030030 Dram Type= 6, Freq= 0, CH_1, rank 0
6692 01:24:44.033115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 01:24:44.033711 ==
6694 01:24:44.039956 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6695 01:24:44.046802 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6696 01:24:44.049736 [CA 0] Center 36 (8~64) winsize 57
6697 01:24:44.053107 [CA 1] Center 36 (8~64) winsize 57
6698 01:24:44.056435 [CA 2] Center 36 (8~64) winsize 57
6699 01:24:44.060193 [CA 3] Center 36 (8~64) winsize 57
6700 01:24:44.063099 [CA 4] Center 36 (8~64) winsize 57
6701 01:24:44.063567 [CA 5] Center 36 (8~64) winsize 57
6702 01:24:44.066321
6703 01:24:44.069858 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6704 01:24:44.070319
6705 01:24:44.072827 [CATrainingPosCal] consider 1 rank data
6706 01:24:44.076272 u2DelayCellTimex100 = 270/100 ps
6707 01:24:44.079451 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 01:24:44.083196 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 01:24:44.085821 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 01:24:44.089527 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 01:24:44.092413 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 01:24:44.095929 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 01:24:44.096478
6714 01:24:44.099344 CA PerBit enable=1, Macro0, CA PI delay=36
6715 01:24:44.102777
6716 01:24:44.103236 [CBTSetCACLKResult] CA Dly = 36
6717 01:24:44.106000 CS Dly: 1 (0~32)
6718 01:24:44.106548 ==
6719 01:24:44.109229 Dram Type= 6, Freq= 0, CH_1, rank 1
6720 01:24:44.112745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 01:24:44.113295 ==
6722 01:24:44.119014 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6723 01:24:44.125620 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6724 01:24:44.128839 [CA 0] Center 36 (8~64) winsize 57
6725 01:24:44.132166 [CA 1] Center 36 (8~64) winsize 57
6726 01:24:44.135373 [CA 2] Center 36 (8~64) winsize 57
6727 01:24:44.135857 [CA 3] Center 36 (8~64) winsize 57
6728 01:24:44.139199 [CA 4] Center 36 (8~64) winsize 57
6729 01:24:44.142054 [CA 5] Center 36 (8~64) winsize 57
6730 01:24:44.142603
6731 01:24:44.148663 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6732 01:24:44.149219
6733 01:24:44.152100 [CATrainingPosCal] consider 2 rank data
6734 01:24:44.155672 u2DelayCellTimex100 = 270/100 ps
6735 01:24:44.158275 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6736 01:24:44.161992 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6737 01:24:44.165018 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6738 01:24:44.168403 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6739 01:24:44.171607 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6740 01:24:44.175124 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6741 01:24:44.175673
6742 01:24:44.178163 CA PerBit enable=1, Macro0, CA PI delay=36
6743 01:24:44.178627
6744 01:24:44.181532 [CBTSetCACLKResult] CA Dly = 36
6745 01:24:44.184816 CS Dly: 1 (0~32)
6746 01:24:44.185408
6747 01:24:44.188718 ----->DramcWriteLeveling(PI) begin...
6748 01:24:44.189270 ==
6749 01:24:44.191004 Dram Type= 6, Freq= 0, CH_1, rank 0
6750 01:24:44.194426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6751 01:24:44.194891 ==
6752 01:24:44.197819 Write leveling (Byte 0): 40 => 8
6753 01:24:44.201258 Write leveling (Byte 1): 40 => 8
6754 01:24:44.204440 DramcWriteLeveling(PI) end<-----
6755 01:24:44.204987
6756 01:24:44.205381 ==
6757 01:24:44.208193 Dram Type= 6, Freq= 0, CH_1, rank 0
6758 01:24:44.210961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6759 01:24:44.211518 ==
6760 01:24:44.214495 [Gating] SW mode calibration
6761 01:24:44.221087 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6762 01:24:44.227755 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6763 01:24:44.230578 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6764 01:24:44.237133 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6765 01:24:44.240540 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6766 01:24:44.244427 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6767 01:24:44.250953 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6768 01:24:44.253921 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6769 01:24:44.257100 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6770 01:24:44.263895 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6771 01:24:44.267035 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6772 01:24:44.270780 Total UI for P1: 0, mck2ui 16
6773 01:24:44.274250 best dqsien dly found for B0: ( 0, 14, 24)
6774 01:24:44.276949 Total UI for P1: 0, mck2ui 16
6775 01:24:44.280408 best dqsien dly found for B1: ( 0, 14, 24)
6776 01:24:44.283632 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6777 01:24:44.287209 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6778 01:24:44.287761
6779 01:24:44.290360 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6780 01:24:44.293881 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6781 01:24:44.296924 [Gating] SW calibration Done
6782 01:24:44.297428 ==
6783 01:24:44.300070 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 01:24:44.307016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 01:24:44.307572 ==
6786 01:24:44.308126 RX Vref Scan: 0
6787 01:24:44.308550
6788 01:24:44.309681 RX Vref 0 -> 0, step: 1
6789 01:24:44.310142
6790 01:24:44.313297 RX Delay -410 -> 252, step: 16
6791 01:24:44.316606 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6792 01:24:44.319877 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6793 01:24:44.326333 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6794 01:24:44.329463 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6795 01:24:44.332715 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6796 01:24:44.335854 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6797 01:24:44.342863 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6798 01:24:44.345936 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6799 01:24:44.349244 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6800 01:24:44.352983 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6801 01:24:44.359096 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6802 01:24:44.362463 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6803 01:24:44.365861 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6804 01:24:44.372860 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6805 01:24:44.375497 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6806 01:24:44.379425 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6807 01:24:44.379986 ==
6808 01:24:44.382468 Dram Type= 6, Freq= 0, CH_1, rank 0
6809 01:24:44.385809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 01:24:44.388832 ==
6811 01:24:44.389471 DQS Delay:
6812 01:24:44.389850 DQS0 = 43, DQS1 = 51
6813 01:24:44.392039 DQM Delay:
6814 01:24:44.392443 DQM0 = 12, DQM1 = 14
6815 01:24:44.395387 DQ Delay:
6816 01:24:44.395845 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6817 01:24:44.398743 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6818 01:24:44.401831 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6819 01:24:44.405158 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6820 01:24:44.405771
6821 01:24:44.406144
6822 01:24:44.406569 ==
6823 01:24:44.408782 Dram Type= 6, Freq= 0, CH_1, rank 0
6824 01:24:44.415405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6825 01:24:44.415932 ==
6826 01:24:44.416608
6827 01:24:44.417079
6828 01:24:44.417463 TX Vref Scan disable
6829 01:24:44.418715 == TX Byte 0 ==
6830 01:24:44.421860 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6831 01:24:44.425265 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6832 01:24:44.428078 == TX Byte 1 ==
6833 01:24:44.432273 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6834 01:24:44.434864 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6835 01:24:44.438653 ==
6836 01:24:44.441854 Dram Type= 6, Freq= 0, CH_1, rank 0
6837 01:24:44.444743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6838 01:24:44.445174 ==
6839 01:24:44.445747
6840 01:24:44.446212
6841 01:24:44.447940 TX Vref Scan disable
6842 01:24:44.448348 == TX Byte 0 ==
6843 01:24:44.450945 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6844 01:24:44.458002 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6845 01:24:44.458463 == TX Byte 1 ==
6846 01:24:44.461202 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6847 01:24:44.467421 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6848 01:24:44.467832
6849 01:24:44.468155 [DATLAT]
6850 01:24:44.468456 Freq=400, CH1 RK0
6851 01:24:44.470861
6852 01:24:44.471433 DATLAT Default: 0xf
6853 01:24:44.473972 0, 0xFFFF, sum = 0
6854 01:24:44.474521 1, 0xFFFF, sum = 0
6855 01:24:44.477384 2, 0xFFFF, sum = 0
6856 01:24:44.478025 3, 0xFFFF, sum = 0
6857 01:24:44.480940 4, 0xFFFF, sum = 0
6858 01:24:44.481392 5, 0xFFFF, sum = 0
6859 01:24:44.484279 6, 0xFFFF, sum = 0
6860 01:24:44.484692 7, 0xFFFF, sum = 0
6861 01:24:44.487614 8, 0xFFFF, sum = 0
6862 01:24:44.488173 9, 0xFFFF, sum = 0
6863 01:24:44.490415 10, 0xFFFF, sum = 0
6864 01:24:44.490981 11, 0xFFFF, sum = 0
6865 01:24:44.494320 12, 0xFFFF, sum = 0
6866 01:24:44.494736 13, 0x0, sum = 1
6867 01:24:44.497226 14, 0x0, sum = 2
6868 01:24:44.497681 15, 0x0, sum = 3
6869 01:24:44.500381 16, 0x0, sum = 4
6870 01:24:44.500808 best_step = 14
6871 01:24:44.501132
6872 01:24:44.501615 ==
6873 01:24:44.503653 Dram Type= 6, Freq= 0, CH_1, rank 0
6874 01:24:44.510410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6875 01:24:44.510924 ==
6876 01:24:44.511259 RX Vref Scan: 1
6877 01:24:44.511566
6878 01:24:44.514107 RX Vref 0 -> 0, step: 1
6879 01:24:44.514922
6880 01:24:44.517006 RX Delay -343 -> 252, step: 8
6881 01:24:44.517446
6882 01:24:44.520406 Set Vref, RX VrefLevel [Byte0]: 51
6883 01:24:44.523358 [Byte1]: 53
6884 01:24:44.527161
6885 01:24:44.527570 Final RX Vref Byte 0 = 51 to rank0
6886 01:24:44.530158 Final RX Vref Byte 1 = 53 to rank0
6887 01:24:44.533241 Final RX Vref Byte 0 = 51 to rank1
6888 01:24:44.536620 Final RX Vref Byte 1 = 53 to rank1==
6889 01:24:44.539890 Dram Type= 6, Freq= 0, CH_1, rank 0
6890 01:24:44.546896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 01:24:44.547594 ==
6892 01:24:44.548216 DQS Delay:
6893 01:24:44.550046 DQS0 = 44, DQS1 = 56
6894 01:24:44.550459 DQM Delay:
6895 01:24:44.550784 DQM0 = 7, DQM1 = 12
6896 01:24:44.553455 DQ Delay:
6897 01:24:44.556750 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6898 01:24:44.559660 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =0
6899 01:24:44.560076 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6900 01:24:44.563044 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6901 01:24:44.566920
6902 01:24:44.567330
6903 01:24:44.573018 [DQSOSCAuto] RK0, (LSB)MR18= 0x946a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6904 01:24:44.576411 CH1 RK0: MR19=C0C, MR18=946A
6905 01:24:44.582904 CH1_RK0: MR19=0xC0C, MR18=0x946A, DQSOSC=391, MR23=63, INC=386, DEC=257
6906 01:24:44.583453 ==
6907 01:24:44.586132 Dram Type= 6, Freq= 0, CH_1, rank 1
6908 01:24:44.589575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6909 01:24:44.590039 ==
6910 01:24:44.592720 [Gating] SW mode calibration
6911 01:24:44.600091 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6912 01:24:44.605893 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6913 01:24:44.609493 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6914 01:24:44.612661 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6915 01:24:44.619394 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6916 01:24:44.622288 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6917 01:24:44.626025 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6918 01:24:44.632589 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6919 01:24:44.635680 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6920 01:24:44.639101 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6921 01:24:44.645654 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6922 01:24:44.648395 Total UI for P1: 0, mck2ui 16
6923 01:24:44.651803 best dqsien dly found for B0: ( 0, 14, 24)
6924 01:24:44.652473 Total UI for P1: 0, mck2ui 16
6925 01:24:44.658480 best dqsien dly found for B1: ( 0, 14, 24)
6926 01:24:44.661984 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6927 01:24:44.665230 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6928 01:24:44.665754
6929 01:24:44.668685 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6930 01:24:44.672196 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6931 01:24:44.675067 [Gating] SW calibration Done
6932 01:24:44.675522 ==
6933 01:24:44.678350 Dram Type= 6, Freq= 0, CH_1, rank 1
6934 01:24:44.681907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6935 01:24:44.682466 ==
6936 01:24:44.684895 RX Vref Scan: 0
6937 01:24:44.685487
6938 01:24:44.688695 RX Vref 0 -> 0, step: 1
6939 01:24:44.689242
6940 01:24:44.689673 RX Delay -410 -> 252, step: 16
6941 01:24:44.694934 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6942 01:24:44.698507 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6943 01:24:44.702078 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6944 01:24:44.708471 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6945 01:24:44.711540 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6946 01:24:44.715018 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6947 01:24:44.717997 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6948 01:24:44.724805 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6949 01:24:44.728451 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6950 01:24:44.730996 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6951 01:24:44.734364 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6952 01:24:44.741001 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6953 01:24:44.744526 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6954 01:24:44.747584 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6955 01:24:44.750969 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6956 01:24:44.757232 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6957 01:24:44.757817 ==
6958 01:24:44.760865 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 01:24:44.764130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 01:24:44.764612 ==
6961 01:24:44.764971 DQS Delay:
6962 01:24:44.767438 DQS0 = 51, DQS1 = 59
6963 01:24:44.767893 DQM Delay:
6964 01:24:44.770761 DQM0 = 19, DQM1 = 21
6965 01:24:44.771360 DQ Delay:
6966 01:24:44.773864 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6967 01:24:44.776959 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6968 01:24:44.780629 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =8
6969 01:24:44.784065 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6970 01:24:44.784615
6971 01:24:44.784977
6972 01:24:44.785315 ==
6973 01:24:44.787642 Dram Type= 6, Freq= 0, CH_1, rank 1
6974 01:24:44.794187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6975 01:24:44.794729 ==
6976 01:24:44.795091
6977 01:24:44.795428
6978 01:24:44.795811 TX Vref Scan disable
6979 01:24:44.796801 == TX Byte 0 ==
6980 01:24:44.800662 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6981 01:24:44.803470 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6982 01:24:44.806991 == TX Byte 1 ==
6983 01:24:44.810441 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6984 01:24:44.813537 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6985 01:24:44.813994 ==
6986 01:24:44.817219 Dram Type= 6, Freq= 0, CH_1, rank 1
6987 01:24:44.823649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6988 01:24:44.824201 ==
6989 01:24:44.824568
6990 01:24:44.824903
6991 01:24:44.825225 TX Vref Scan disable
6992 01:24:44.826477 == TX Byte 0 ==
6993 01:24:44.829901 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6994 01:24:44.833374 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6995 01:24:44.836534 == TX Byte 1 ==
6996 01:24:44.840042 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6997 01:24:44.843330 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6998 01:24:44.843792
6999 01:24:44.846399 [DATLAT]
7000 01:24:44.846948 Freq=400, CH1 RK1
7001 01:24:44.847314
7002 01:24:44.850267 DATLAT Default: 0xe
7003 01:24:44.850829 0, 0xFFFF, sum = 0
7004 01:24:44.853592 1, 0xFFFF, sum = 0
7005 01:24:44.854171 2, 0xFFFF, sum = 0
7006 01:24:44.856141 3, 0xFFFF, sum = 0
7007 01:24:44.856696 4, 0xFFFF, sum = 0
7008 01:24:44.859631 5, 0xFFFF, sum = 0
7009 01:24:44.860093 6, 0xFFFF, sum = 0
7010 01:24:44.863437 7, 0xFFFF, sum = 0
7011 01:24:44.866464 8, 0xFFFF, sum = 0
7012 01:24:44.867133 9, 0xFFFF, sum = 0
7013 01:24:44.869500 10, 0xFFFF, sum = 0
7014 01:24:44.869963 11, 0xFFFF, sum = 0
7015 01:24:44.873444 12, 0xFFFF, sum = 0
7016 01:24:44.873995 13, 0x0, sum = 1
7017 01:24:44.876044 14, 0x0, sum = 2
7018 01:24:44.876503 15, 0x0, sum = 3
7019 01:24:44.879528 16, 0x0, sum = 4
7020 01:24:44.880088 best_step = 14
7021 01:24:44.880451
7022 01:24:44.880791 ==
7023 01:24:44.882696 Dram Type= 6, Freq= 0, CH_1, rank 1
7024 01:24:44.885941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7025 01:24:44.889070 ==
7026 01:24:44.889829 RX Vref Scan: 0
7027 01:24:44.890353
7028 01:24:44.892339 RX Vref 0 -> 0, step: 1
7029 01:24:44.892914
7030 01:24:44.895296 RX Delay -359 -> 252, step: 8
7031 01:24:44.901945 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
7032 01:24:44.905047 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
7033 01:24:44.908796 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
7034 01:24:44.912200 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7035 01:24:44.918721 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7036 01:24:44.921714 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7037 01:24:44.925542 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7038 01:24:44.928553 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7039 01:24:44.934910 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7040 01:24:44.938023 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7041 01:24:44.941726 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7042 01:24:44.944772 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7043 01:24:44.951826 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7044 01:24:44.954819 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7045 01:24:44.957849 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7046 01:24:44.964827 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7047 01:24:44.965322 ==
7048 01:24:44.967986 Dram Type= 6, Freq= 0, CH_1, rank 1
7049 01:24:44.970986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7050 01:24:44.971467 ==
7051 01:24:44.971798 DQS Delay:
7052 01:24:44.974745 DQS0 = 44, DQS1 = 56
7053 01:24:44.975252 DQM Delay:
7054 01:24:44.977563 DQM0 = 8, DQM1 = 11
7055 01:24:44.977971 DQ Delay:
7056 01:24:44.981200 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =4
7057 01:24:44.984378 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
7058 01:24:44.987872 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7059 01:24:44.991054 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7060 01:24:44.991653
7061 01:24:44.992016
7062 01:24:44.997855 [DQSOSCAuto] RK1, (LSB)MR18= 0x6250, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7063 01:24:45.000712 CH1 RK1: MR19=C0C, MR18=6250
7064 01:24:45.007525 CH1_RK1: MR19=0xC0C, MR18=0x6250, DQSOSC=397, MR23=63, INC=374, DEC=249
7065 01:24:45.010680 [RxdqsGatingPostProcess] freq 400
7066 01:24:45.017200 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7067 01:24:45.020735 best DQS0 dly(2T, 0.5T) = (0, 10)
7068 01:24:45.024412 best DQS1 dly(2T, 0.5T) = (0, 10)
7069 01:24:45.024869 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7070 01:24:45.027364 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7071 01:24:45.031019 best DQS0 dly(2T, 0.5T) = (0, 10)
7072 01:24:45.033604 best DQS1 dly(2T, 0.5T) = (0, 10)
7073 01:24:45.037139 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7074 01:24:45.040758 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7075 01:24:45.043880 Pre-setting of DQS Precalculation
7076 01:24:45.050371 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7077 01:24:45.057227 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7078 01:24:45.063626 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7079 01:24:45.064193
7080 01:24:45.064556
7081 01:24:45.066629 [Calibration Summary] 800 Mbps
7082 01:24:45.067084 CH 0, Rank 0
7083 01:24:45.070031 SW Impedance : PASS
7084 01:24:45.073509 DUTY Scan : NO K
7085 01:24:45.074053 ZQ Calibration : PASS
7086 01:24:45.076555 Jitter Meter : NO K
7087 01:24:45.080073 CBT Training : PASS
7088 01:24:45.080622 Write leveling : PASS
7089 01:24:45.083009 RX DQS gating : PASS
7090 01:24:45.086609 RX DQ/DQS(RDDQC) : PASS
7091 01:24:45.087061 TX DQ/DQS : PASS
7092 01:24:45.089758 RX DATLAT : PASS
7093 01:24:45.092911 RX DQ/DQS(Engine): PASS
7094 01:24:45.093390 TX OE : NO K
7095 01:24:45.096846 All Pass.
7096 01:24:45.097444
7097 01:24:45.097812 CH 0, Rank 1
7098 01:24:45.099410 SW Impedance : PASS
7099 01:24:45.099861 DUTY Scan : NO K
7100 01:24:45.102943 ZQ Calibration : PASS
7101 01:24:45.106125 Jitter Meter : NO K
7102 01:24:45.106677 CBT Training : PASS
7103 01:24:45.109846 Write leveling : NO K
7104 01:24:45.112892 RX DQS gating : PASS
7105 01:24:45.113491 RX DQ/DQS(RDDQC) : PASS
7106 01:24:45.115901 TX DQ/DQS : PASS
7107 01:24:45.119276 RX DATLAT : PASS
7108 01:24:45.119732 RX DQ/DQS(Engine): PASS
7109 01:24:45.123286 TX OE : NO K
7110 01:24:45.123839 All Pass.
7111 01:24:45.124209
7112 01:24:45.126031 CH 1, Rank 0
7113 01:24:45.126485 SW Impedance : PASS
7114 01:24:45.129433 DUTY Scan : NO K
7115 01:24:45.129985 ZQ Calibration : PASS
7116 01:24:45.132522 Jitter Meter : NO K
7117 01:24:45.135810 CBT Training : PASS
7118 01:24:45.136269 Write leveling : PASS
7119 01:24:45.139720 RX DQS gating : PASS
7120 01:24:45.142363 RX DQ/DQS(RDDQC) : PASS
7121 01:24:45.142817 TX DQ/DQS : PASS
7122 01:24:45.145640 RX DATLAT : PASS
7123 01:24:45.149094 RX DQ/DQS(Engine): PASS
7124 01:24:45.149729 TX OE : NO K
7125 01:24:45.152432 All Pass.
7126 01:24:45.152981
7127 01:24:45.153398 CH 1, Rank 1
7128 01:24:45.155503 SW Impedance : PASS
7129 01:24:45.156050 DUTY Scan : NO K
7130 01:24:45.158948 ZQ Calibration : PASS
7131 01:24:45.161923 Jitter Meter : NO K
7132 01:24:45.162378 CBT Training : PASS
7133 01:24:45.165537 Write leveling : NO K
7134 01:24:45.168709 RX DQS gating : PASS
7135 01:24:45.169439 RX DQ/DQS(RDDQC) : PASS
7136 01:24:45.171882 TX DQ/DQS : PASS
7137 01:24:45.175096 RX DATLAT : PASS
7138 01:24:45.175551 RX DQ/DQS(Engine): PASS
7139 01:24:45.178657 TX OE : NO K
7140 01:24:45.179113 All Pass.
7141 01:24:45.179471
7142 01:24:45.181922 DramC Write-DBI off
7143 01:24:45.185311 PER_BANK_REFRESH: Hybrid Mode
7144 01:24:45.185918 TX_TRACKING: ON
7145 01:24:45.194886 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7146 01:24:45.198503 [FAST_K] Save calibration result to emmc
7147 01:24:45.201784 dramc_set_vcore_voltage set vcore to 725000
7148 01:24:45.205284 Read voltage for 1600, 0
7149 01:24:45.205875 Vio18 = 0
7150 01:24:45.206241 Vcore = 725000
7151 01:24:45.208664 Vdram = 0
7152 01:24:45.209210 Vddq = 0
7153 01:24:45.209676 Vmddr = 0
7154 01:24:45.214938 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7155 01:24:45.218937 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7156 01:24:45.221866 MEM_TYPE=3, freq_sel=13
7157 01:24:45.224814 sv_algorithm_assistance_LP4_3733
7158 01:24:45.228323 ============ PULL DRAM RESETB DOWN ============
7159 01:24:45.234307 ========== PULL DRAM RESETB DOWN end =========
7160 01:24:45.237834 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7161 01:24:45.241102 ===================================
7162 01:24:45.244224 LPDDR4 DRAM CONFIGURATION
7163 01:24:45.247944 ===================================
7164 01:24:45.248524 EX_ROW_EN[0] = 0x0
7165 01:24:45.251155 EX_ROW_EN[1] = 0x0
7166 01:24:45.251742 LP4Y_EN = 0x0
7167 01:24:45.254492 WORK_FSP = 0x1
7168 01:24:45.254965 WL = 0x5
7169 01:24:45.257615 RL = 0x5
7170 01:24:45.258092 BL = 0x2
7171 01:24:45.260729 RPST = 0x0
7172 01:24:45.261204 RD_PRE = 0x0
7173 01:24:45.264317 WR_PRE = 0x1
7174 01:24:45.267460 WR_PST = 0x1
7175 01:24:45.267937 DBI_WR = 0x0
7176 01:24:45.270965 DBI_RD = 0x0
7177 01:24:45.271542 OTF = 0x1
7178 01:24:45.274639 ===================================
7179 01:24:45.277209 ===================================
7180 01:24:45.281266 ANA top config
7181 01:24:45.281898 ===================================
7182 01:24:45.284472 DLL_ASYNC_EN = 0
7183 01:24:45.287508 ALL_SLAVE_EN = 0
7184 01:24:45.291124 NEW_RANK_MODE = 1
7185 01:24:45.294485 DLL_IDLE_MODE = 1
7186 01:24:45.295039 LP45_APHY_COMB_EN = 1
7187 01:24:45.297714 TX_ODT_DIS = 0
7188 01:24:45.301035 NEW_8X_MODE = 1
7189 01:24:45.304684 ===================================
7190 01:24:45.307539 ===================================
7191 01:24:45.311019 data_rate = 3200
7192 01:24:45.313912 CKR = 1
7193 01:24:45.317200 DQ_P2S_RATIO = 8
7194 01:24:45.320919 ===================================
7195 01:24:45.321540 CA_P2S_RATIO = 8
7196 01:24:45.323529 DQ_CA_OPEN = 0
7197 01:24:45.326631 DQ_SEMI_OPEN = 0
7198 01:24:45.330441 CA_SEMI_OPEN = 0
7199 01:24:45.334046 CA_FULL_RATE = 0
7200 01:24:45.336732 DQ_CKDIV4_EN = 0
7201 01:24:45.337240 CA_CKDIV4_EN = 0
7202 01:24:45.340411 CA_PREDIV_EN = 0
7203 01:24:45.343783 PH8_DLY = 12
7204 01:24:45.346706 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7205 01:24:45.350076 DQ_AAMCK_DIV = 4
7206 01:24:45.353249 CA_AAMCK_DIV = 4
7207 01:24:45.353839 CA_ADMCK_DIV = 4
7208 01:24:45.356530 DQ_TRACK_CA_EN = 0
7209 01:24:45.359674 CA_PICK = 1600
7210 01:24:45.362777 CA_MCKIO = 1600
7211 01:24:45.366584 MCKIO_SEMI = 0
7212 01:24:45.369735 PLL_FREQ = 3068
7213 01:24:45.373080 DQ_UI_PI_RATIO = 32
7214 01:24:45.376243 CA_UI_PI_RATIO = 0
7215 01:24:45.379714 ===================================
7216 01:24:45.382617 ===================================
7217 01:24:45.383072 memory_type:LPDDR4
7218 01:24:45.386302 GP_NUM : 10
7219 01:24:45.389934 SRAM_EN : 1
7220 01:24:45.390483 MD32_EN : 0
7221 01:24:45.392901 ===================================
7222 01:24:45.396390 [ANA_INIT] >>>>>>>>>>>>>>
7223 01:24:45.399148 <<<<<< [CONFIGURE PHASE]: ANA_TX
7224 01:24:45.402706 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7225 01:24:45.406078 ===================================
7226 01:24:45.409417 data_rate = 3200,PCW = 0X7600
7227 01:24:45.412762 ===================================
7228 01:24:45.416103 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7229 01:24:45.419334 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7230 01:24:45.425917 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7231 01:24:45.428648 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7232 01:24:45.435429 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7233 01:24:45.438419 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7234 01:24:45.438874 [ANA_INIT] flow start
7235 01:24:45.442110 [ANA_INIT] PLL >>>>>>>>
7236 01:24:45.445723 [ANA_INIT] PLL <<<<<<<<
7237 01:24:45.446272 [ANA_INIT] MIDPI >>>>>>>>
7238 01:24:45.448864 [ANA_INIT] MIDPI <<<<<<<<
7239 01:24:45.451877 [ANA_INIT] DLL >>>>>>>>
7240 01:24:45.452430 [ANA_INIT] DLL <<<<<<<<
7241 01:24:45.455533 [ANA_INIT] flow end
7242 01:24:45.458455 ============ LP4 DIFF to SE enter ============
7243 01:24:45.461933 ============ LP4 DIFF to SE exit ============
7244 01:24:45.465400 [ANA_INIT] <<<<<<<<<<<<<
7245 01:24:45.469019 [Flow] Enable top DCM control >>>>>
7246 01:24:45.471840 [Flow] Enable top DCM control <<<<<
7247 01:24:45.475464 Enable DLL master slave shuffle
7248 01:24:45.482080 ==============================================================
7249 01:24:45.482638 Gating Mode config
7250 01:24:45.488652 ==============================================================
7251 01:24:45.491870 Config description:
7252 01:24:45.498088 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7253 01:24:45.504527 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7254 01:24:45.511643 SELPH_MODE 0: By rank 1: By Phase
7255 01:24:45.517939 ==============================================================
7256 01:24:45.518500 GAT_TRACK_EN = 1
7257 01:24:45.521851 RX_GATING_MODE = 2
7258 01:24:45.525103 RX_GATING_TRACK_MODE = 2
7259 01:24:45.527880 SELPH_MODE = 1
7260 01:24:45.531210 PICG_EARLY_EN = 1
7261 01:24:45.534689 VALID_LAT_VALUE = 1
7262 01:24:45.541133 ==============================================================
7263 01:24:45.544467 Enter into Gating configuration >>>>
7264 01:24:45.548102 Exit from Gating configuration <<<<
7265 01:24:45.551440 Enter into DVFS_PRE_config >>>>>
7266 01:24:45.560863 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7267 01:24:45.564087 Exit from DVFS_PRE_config <<<<<
7268 01:24:45.567432 Enter into PICG configuration >>>>
7269 01:24:45.570674 Exit from PICG configuration <<<<
7270 01:24:45.573882 [RX_INPUT] configuration >>>>>
7271 01:24:45.577641 [RX_INPUT] configuration <<<<<
7272 01:24:45.580806 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7273 01:24:45.586957 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7274 01:24:45.593963 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7275 01:24:45.600121 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7276 01:24:45.603497 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7277 01:24:45.609836 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7278 01:24:45.613219 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7279 01:24:45.619751 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7280 01:24:45.623214 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7281 01:24:45.626350 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7282 01:24:45.629894 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7283 01:24:45.636265 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7284 01:24:45.639857 ===================================
7285 01:24:45.643008 LPDDR4 DRAM CONFIGURATION
7286 01:24:45.646126 ===================================
7287 01:24:45.646739 EX_ROW_EN[0] = 0x0
7288 01:24:45.649925 EX_ROW_EN[1] = 0x0
7289 01:24:45.650359 LP4Y_EN = 0x0
7290 01:24:45.652713 WORK_FSP = 0x1
7291 01:24:45.653124 WL = 0x5
7292 01:24:45.656391 RL = 0x5
7293 01:24:45.656906 BL = 0x2
7294 01:24:45.659582 RPST = 0x0
7295 01:24:45.660025 RD_PRE = 0x0
7296 01:24:45.662731 WR_PRE = 0x1
7297 01:24:45.666251 WR_PST = 0x1
7298 01:24:45.666662 DBI_WR = 0x0
7299 01:24:45.669285 DBI_RD = 0x0
7300 01:24:45.669757 OTF = 0x1
7301 01:24:45.672616 ===================================
7302 01:24:45.675881 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7303 01:24:45.682227 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7304 01:24:45.685883 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7305 01:24:45.688809 ===================================
7306 01:24:45.692283 LPDDR4 DRAM CONFIGURATION
7307 01:24:45.695561 ===================================
7308 01:24:45.695973 EX_ROW_EN[0] = 0x10
7309 01:24:45.698850 EX_ROW_EN[1] = 0x0
7310 01:24:45.699262 LP4Y_EN = 0x0
7311 01:24:45.702313 WORK_FSP = 0x1
7312 01:24:45.702724 WL = 0x5
7313 01:24:45.705813 RL = 0x5
7314 01:24:45.706225 BL = 0x2
7315 01:24:45.709482 RPST = 0x0
7316 01:24:45.709996 RD_PRE = 0x0
7317 01:24:45.712195 WR_PRE = 0x1
7318 01:24:45.715830 WR_PST = 0x1
7319 01:24:45.716240 DBI_WR = 0x0
7320 01:24:45.718584 DBI_RD = 0x0
7321 01:24:45.718998 OTF = 0x1
7322 01:24:45.722630 ===================================
7323 01:24:45.729120 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7324 01:24:45.729662 ==
7325 01:24:45.731851 Dram Type= 6, Freq= 0, CH_0, rank 0
7326 01:24:45.735120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7327 01:24:45.735538 ==
7328 01:24:45.738734 [Duty_Offset_Calibration]
7329 01:24:45.741777 B0:1 B1:-1 CA:0
7330 01:24:45.742290
7331 01:24:45.745050 [DutyScan_Calibration_Flow] k_type=0
7332 01:24:45.753726
7333 01:24:45.754279 ==CLK 0==
7334 01:24:45.757518 Final CLK duty delay cell = 0
7335 01:24:45.760200 [0] MAX Duty = 5124%(X100), DQS PI = 22
7336 01:24:45.763753 [0] MIN Duty = 4907%(X100), DQS PI = 4
7337 01:24:45.764315 [0] AVG Duty = 5015%(X100)
7338 01:24:45.766893
7339 01:24:45.770004 CH0 CLK Duty spec in!! Max-Min= 217%
7340 01:24:45.773781 [DutyScan_Calibration_Flow] ====Done====
7341 01:24:45.774239
7342 01:24:45.776581 [DutyScan_Calibration_Flow] k_type=1
7343 01:24:45.792878
7344 01:24:45.793494 ==DQS 0 ==
7345 01:24:45.796147 Final DQS duty delay cell = -4
7346 01:24:45.799540 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7347 01:24:45.802892 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7348 01:24:45.805634 [-4] AVG Duty = 4906%(X100)
7349 01:24:45.806160
7350 01:24:45.806526 ==DQS 1 ==
7351 01:24:45.809323 Final DQS duty delay cell = 0
7352 01:24:45.812714 [0] MAX Duty = 5156%(X100), DQS PI = 2
7353 01:24:45.816012 [0] MIN Duty = 5031%(X100), DQS PI = 18
7354 01:24:45.818948 [0] AVG Duty = 5093%(X100)
7355 01:24:45.819496
7356 01:24:45.822422 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7357 01:24:45.822877
7358 01:24:45.825413 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7359 01:24:45.828831 [DutyScan_Calibration_Flow] ====Done====
7360 01:24:45.829280
7361 01:24:45.832144 [DutyScan_Calibration_Flow] k_type=3
7362 01:24:45.850231
7363 01:24:45.850680 ==DQM 0 ==
7364 01:24:45.853288 Final DQM duty delay cell = 0
7365 01:24:45.856765 [0] MAX Duty = 5124%(X100), DQS PI = 22
7366 01:24:45.860153 [0] MIN Duty = 4875%(X100), DQS PI = 10
7367 01:24:45.863733 [0] AVG Duty = 4999%(X100)
7368 01:24:45.864057
7369 01:24:45.864311 ==DQM 1 ==
7370 01:24:45.866466 Final DQM duty delay cell = 0
7371 01:24:45.869805 [0] MAX Duty = 5000%(X100), DQS PI = 2
7372 01:24:45.873240 [0] MIN Duty = 4782%(X100), DQS PI = 22
7373 01:24:45.876415 [0] AVG Duty = 4891%(X100)
7374 01:24:45.876820
7375 01:24:45.879776 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7376 01:24:45.880218
7377 01:24:45.882953 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7378 01:24:45.886348 [DutyScan_Calibration_Flow] ====Done====
7379 01:24:45.886857
7380 01:24:45.889662 [DutyScan_Calibration_Flow] k_type=2
7381 01:24:45.906678
7382 01:24:45.907233 ==DQ 0 ==
7383 01:24:45.909819 Final DQ duty delay cell = -4
7384 01:24:45.913290 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7385 01:24:45.916660 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7386 01:24:45.919901 [-4] AVG Duty = 4953%(X100)
7387 01:24:45.920351
7388 01:24:45.920708 ==DQ 1 ==
7389 01:24:45.923073 Final DQ duty delay cell = 0
7390 01:24:45.926747 [0] MAX Duty = 5125%(X100), DQS PI = 48
7391 01:24:45.930060 [0] MIN Duty = 5000%(X100), DQS PI = 36
7392 01:24:45.933224 [0] AVG Duty = 5062%(X100)
7393 01:24:45.933804
7394 01:24:45.936419 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7395 01:24:45.936965
7396 01:24:45.939359 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7397 01:24:45.943240 [DutyScan_Calibration_Flow] ====Done====
7398 01:24:45.943790 ==
7399 01:24:45.946386 Dram Type= 6, Freq= 0, CH_1, rank 0
7400 01:24:45.949385 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7401 01:24:45.949955 ==
7402 01:24:45.953003 [Duty_Offset_Calibration]
7403 01:24:45.953609 B0:-1 B1:1 CA:1
7404 01:24:45.953977
7405 01:24:45.956095 [DutyScan_Calibration_Flow] k_type=0
7406 01:24:45.967351
7407 01:24:45.967902 ==CLK 0==
7408 01:24:45.970690 Final CLK duty delay cell = 0
7409 01:24:45.973706 [0] MAX Duty = 5187%(X100), DQS PI = 24
7410 01:24:45.977483 [0] MIN Duty = 5000%(X100), DQS PI = 0
7411 01:24:45.980577 [0] AVG Duty = 5093%(X100)
7412 01:24:45.981127
7413 01:24:45.984171 CH1 CLK Duty spec in!! Max-Min= 187%
7414 01:24:45.986729 [DutyScan_Calibration_Flow] ====Done====
7415 01:24:45.987184
7416 01:24:45.990208 [DutyScan_Calibration_Flow] k_type=1
7417 01:24:46.006975
7418 01:24:46.007637 ==DQS 0 ==
7419 01:24:46.009940 Final DQS duty delay cell = 0
7420 01:24:46.013492 [0] MAX Duty = 5093%(X100), DQS PI = 18
7421 01:24:46.016684 [0] MIN Duty = 4907%(X100), DQS PI = 10
7422 01:24:46.020421 [0] AVG Duty = 5000%(X100)
7423 01:24:46.020974
7424 01:24:46.021367 ==DQS 1 ==
7425 01:24:46.023665 Final DQS duty delay cell = 0
7426 01:24:46.026743 [0] MAX Duty = 5124%(X100), DQS PI = 26
7427 01:24:46.029641 [0] MIN Duty = 4969%(X100), DQS PI = 54
7428 01:24:46.033490 [0] AVG Duty = 5046%(X100)
7429 01:24:46.034040
7430 01:24:46.036934 CH1 DQS 0 Duty spec in!! Max-Min= 186%
7431 01:24:46.037532
7432 01:24:46.039502 CH1 DQS 1 Duty spec in!! Max-Min= 155%
7433 01:24:46.043063 [DutyScan_Calibration_Flow] ====Done====
7434 01:24:46.043618
7435 01:24:46.046417 [DutyScan_Calibration_Flow] k_type=3
7436 01:24:46.063002
7437 01:24:46.063554 ==DQM 0 ==
7438 01:24:46.066714 Final DQM duty delay cell = -4
7439 01:24:46.069726 [-4] MAX Duty = 5062%(X100), DQS PI = 38
7440 01:24:46.072758 [-4] MIN Duty = 4782%(X100), DQS PI = 8
7441 01:24:46.076268 [-4] AVG Duty = 4922%(X100)
7442 01:24:46.076815
7443 01:24:46.077169 ==DQM 1 ==
7444 01:24:46.079833 Final DQM duty delay cell = 0
7445 01:24:46.083057 [0] MAX Duty = 5125%(X100), DQS PI = 2
7446 01:24:46.086251 [0] MIN Duty = 4938%(X100), DQS PI = 34
7447 01:24:46.090026 [0] AVG Duty = 5031%(X100)
7448 01:24:46.090476
7449 01:24:46.093226 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7450 01:24:46.093807
7451 01:24:46.096955 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7452 01:24:46.100159 [DutyScan_Calibration_Flow] ====Done====
7453 01:24:46.100702
7454 01:24:46.102966 [DutyScan_Calibration_Flow] k_type=2
7455 01:24:46.120253
7456 01:24:46.120794 ==DQ 0 ==
7457 01:24:46.123445 Final DQ duty delay cell = 0
7458 01:24:46.126670 [0] MAX Duty = 5156%(X100), DQS PI = 28
7459 01:24:46.129847 [0] MIN Duty = 4906%(X100), DQS PI = 8
7460 01:24:46.130307 [0] AVG Duty = 5031%(X100)
7461 01:24:46.133592
7462 01:24:46.134142 ==DQ 1 ==
7463 01:24:46.136740 Final DQ duty delay cell = 0
7464 01:24:46.139989 [0] MAX Duty = 5156%(X100), DQS PI = 10
7465 01:24:46.143425 [0] MIN Duty = 4969%(X100), DQS PI = 56
7466 01:24:46.143984 [0] AVG Duty = 5062%(X100)
7467 01:24:46.146114
7468 01:24:46.150034 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7469 01:24:46.150588
7470 01:24:46.153284 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7471 01:24:46.156706 [DutyScan_Calibration_Flow] ====Done====
7472 01:24:46.160034 nWR fixed to 30
7473 01:24:46.162881 [ModeRegInit_LP4] CH0 RK0
7474 01:24:46.163354 [ModeRegInit_LP4] CH0 RK1
7475 01:24:46.166431 [ModeRegInit_LP4] CH1 RK0
7476 01:24:46.169709 [ModeRegInit_LP4] CH1 RK1
7477 01:24:46.170264 match AC timing 5
7478 01:24:46.176212 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7479 01:24:46.179415 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7480 01:24:46.182571 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7481 01:24:46.189402 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7482 01:24:46.193020 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7483 01:24:46.193624 [MiockJmeterHQA]
7484 01:24:46.193992
7485 01:24:46.196102 [DramcMiockJmeter] u1RxGatingPI = 0
7486 01:24:46.199691 0 : 4255, 4030
7487 01:24:46.200156 4 : 4253, 4027
7488 01:24:46.202880 8 : 4363, 4137
7489 01:24:46.203436 12 : 4365, 4140
7490 01:24:46.205932 16 : 4363, 4137
7491 01:24:46.206392 20 : 4368, 4139
7492 01:24:46.206755 24 : 4252, 4027
7493 01:24:46.209223 28 : 4252, 4027
7494 01:24:46.209706 32 : 4254, 4029
7495 01:24:46.212607 36 : 4252, 4027
7496 01:24:46.213169 40 : 4364, 4137
7497 01:24:46.216138 44 : 4252, 4027
7498 01:24:46.216706 48 : 4252, 4027
7499 01:24:46.219586 52 : 4253, 4026
7500 01:24:46.220146 56 : 4252, 4027
7501 01:24:46.220514 60 : 4251, 4027
7502 01:24:46.222746 64 : 4361, 4138
7503 01:24:46.223302 68 : 4361, 4138
7504 01:24:46.225668 72 : 4250, 4027
7505 01:24:46.226129 76 : 4250, 4026
7506 01:24:46.229068 80 : 4249, 4027
7507 01:24:46.229667 84 : 4250, 4027
7508 01:24:46.232137 88 : 4250, 4027
7509 01:24:46.232600 92 : 4361, 697
7510 01:24:46.232970 96 : 4250, 0
7511 01:24:46.235540 100 : 4363, 0
7512 01:24:46.236095 104 : 4363, 0
7513 01:24:46.238418 108 : 4249, 0
7514 01:24:46.238893 112 : 4250, 0
7515 01:24:46.239263 116 : 4250, 0
7516 01:24:46.242030 120 : 4249, 0
7517 01:24:46.242493 124 : 4250, 0
7518 01:24:46.242860 128 : 4250, 0
7519 01:24:46.245699 132 : 4249, 0
7520 01:24:46.246255 136 : 4250, 0
7521 01:24:46.249065 140 : 4361, 0
7522 01:24:46.249678 144 : 4361, 0
7523 01:24:46.250052 148 : 4361, 0
7524 01:24:46.251608 152 : 4250, 0
7525 01:24:46.252079 156 : 4250, 0
7526 01:24:46.255069 160 : 4249, 0
7527 01:24:46.255529 164 : 4250, 0
7528 01:24:46.255893 168 : 4250, 0
7529 01:24:46.258318 172 : 4249, 0
7530 01:24:46.258843 176 : 4250, 0
7531 01:24:46.261650 180 : 4250, 0
7532 01:24:46.262111 184 : 4250, 0
7533 01:24:46.262474 188 : 4250, 0
7534 01:24:46.265036 192 : 4361, 0
7535 01:24:46.265543 196 : 4250, 0
7536 01:24:46.268929 200 : 4360, 0
7537 01:24:46.269536 204 : 4250, 0
7538 01:24:46.269910 208 : 4250, 0
7539 01:24:46.271531 212 : 4250, 0
7540 01:24:46.271988 216 : 4250, 0
7541 01:24:46.274727 220 : 4250, 0
7542 01:24:46.275186 224 : 4250, 77
7543 01:24:46.275550 228 : 4250, 2639
7544 01:24:46.278001 232 : 4253, 4029
7545 01:24:46.278460 236 : 4250, 4027
7546 01:24:46.281909 240 : 4249, 4027
7547 01:24:46.282368 244 : 4361, 4138
7548 01:24:46.284541 248 : 4250, 4027
7549 01:24:46.284999 252 : 4250, 4027
7550 01:24:46.288151 256 : 4360, 4137
7551 01:24:46.288708 260 : 4250, 4027
7552 01:24:46.291553 264 : 4250, 4026
7553 01:24:46.292121 268 : 4360, 4138
7554 01:24:46.294999 272 : 4249, 4027
7555 01:24:46.295554 276 : 4250, 4027
7556 01:24:46.298437 280 : 4250, 4027
7557 01:24:46.298896 284 : 4250, 4027
7558 01:24:46.299265 288 : 4250, 4027
7559 01:24:46.301572 292 : 4250, 4027
7560 01:24:46.302126 296 : 4361, 4137
7561 01:24:46.304795 300 : 4250, 4027
7562 01:24:46.305382 304 : 4250, 4027
7563 01:24:46.307558 308 : 4360, 4137
7564 01:24:46.308017 312 : 4250, 4027
7565 01:24:46.311189 316 : 4250, 4026
7566 01:24:46.311747 320 : 4360, 4138
7567 01:24:46.314932 324 : 4250, 4027
7568 01:24:46.315493 328 : 4250, 4027
7569 01:24:46.317447 332 : 4250, 4027
7570 01:24:46.317906 336 : 4250, 3874
7571 01:24:46.321240 340 : 4250, 2419
7572 01:24:46.321838 344 : 4250, 46
7573 01:24:46.322203
7574 01:24:46.324916 MIOCK jitter meter ch=0
7575 01:24:46.325520
7576 01:24:46.327911 1T = (344-92) = 252 dly cells
7577 01:24:46.331006 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7578 01:24:46.331461 ==
7579 01:24:46.334246 Dram Type= 6, Freq= 0, CH_0, rank 0
7580 01:24:46.340365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7581 01:24:46.340822 ==
7582 01:24:46.343904 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7583 01:24:46.350502 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7584 01:24:46.353926 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7585 01:24:46.360391 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7586 01:24:46.368474 [CA 0] Center 43 (12~74) winsize 63
7587 01:24:46.371802 [CA 1] Center 42 (12~73) winsize 62
7588 01:24:46.375184 [CA 2] Center 38 (9~68) winsize 60
7589 01:24:46.378508 [CA 3] Center 38 (9~68) winsize 60
7590 01:24:46.381436 [CA 4] Center 36 (7~66) winsize 60
7591 01:24:46.385082 [CA 5] Center 35 (6~65) winsize 60
7592 01:24:46.385695
7593 01:24:46.388303 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7594 01:24:46.388846
7595 01:24:46.392178 [CATrainingPosCal] consider 1 rank data
7596 01:24:46.395228 u2DelayCellTimex100 = 258/100 ps
7597 01:24:46.401577 CA0 delay=43 (12~74),Diff = 8 PI (30 cell)
7598 01:24:46.404840 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7599 01:24:46.408060 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7600 01:24:46.411555 CA3 delay=38 (9~68),Diff = 3 PI (11 cell)
7601 01:24:46.414937 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7602 01:24:46.418291 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7603 01:24:46.418842
7604 01:24:46.421396 CA PerBit enable=1, Macro0, CA PI delay=35
7605 01:24:46.421959
7606 01:24:46.424713 [CBTSetCACLKResult] CA Dly = 35
7607 01:24:46.428048 CS Dly: 12 (0~43)
7608 01:24:46.431357 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7609 01:24:46.435221 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7610 01:24:46.435906 ==
7611 01:24:46.437672 Dram Type= 6, Freq= 0, CH_0, rank 1
7612 01:24:46.444463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7613 01:24:46.445039 ==
7614 01:24:46.447541 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7615 01:24:46.454353 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7616 01:24:46.457600 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7617 01:24:46.464387 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7618 01:24:46.472442 [CA 0] Center 42 (12~73) winsize 62
7619 01:24:46.475465 [CA 1] Center 43 (13~73) winsize 61
7620 01:24:46.478820 [CA 2] Center 37 (8~67) winsize 60
7621 01:24:46.481741 [CA 3] Center 37 (8~67) winsize 60
7622 01:24:46.485506 [CA 4] Center 35 (6~65) winsize 60
7623 01:24:46.488931 [CA 5] Center 35 (5~65) winsize 61
7624 01:24:46.489535
7625 01:24:46.491813 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7626 01:24:46.492369
7627 01:24:46.495087 [CATrainingPosCal] consider 2 rank data
7628 01:24:46.498521 u2DelayCellTimex100 = 258/100 ps
7629 01:24:46.502112 CA0 delay=42 (12~73),Diff = 7 PI (26 cell)
7630 01:24:46.508245 CA1 delay=43 (13~73),Diff = 8 PI (30 cell)
7631 01:24:46.511871 CA2 delay=38 (9~67),Diff = 3 PI (11 cell)
7632 01:24:46.514989 CA3 delay=38 (9~67),Diff = 3 PI (11 cell)
7633 01:24:46.518279 CA4 delay=36 (7~65),Diff = 1 PI (3 cell)
7634 01:24:46.521900 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7635 01:24:46.522457
7636 01:24:46.524796 CA PerBit enable=1, Macro0, CA PI delay=35
7637 01:24:46.525252
7638 01:24:46.528371 [CBTSetCACLKResult] CA Dly = 35
7639 01:24:46.531488 CS Dly: 12 (0~43)
7640 01:24:46.534431 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7641 01:24:46.537873 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7642 01:24:46.538326
7643 01:24:46.541140 ----->DramcWriteLeveling(PI) begin...
7644 01:24:46.544582 ==
7645 01:24:46.545143 Dram Type= 6, Freq= 0, CH_0, rank 0
7646 01:24:46.551025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7647 01:24:46.551485 ==
7648 01:24:46.554396 Write leveling (Byte 0): 33 => 33
7649 01:24:46.558018 Write leveling (Byte 1): 27 => 27
7650 01:24:46.561238 DramcWriteLeveling(PI) end<-----
7651 01:24:46.561724
7652 01:24:46.562181 ==
7653 01:24:46.564143 Dram Type= 6, Freq= 0, CH_0, rank 0
7654 01:24:46.567697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7655 01:24:46.568158 ==
7656 01:24:46.570568 [Gating] SW mode calibration
7657 01:24:46.577158 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7658 01:24:46.583959 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7659 01:24:46.587584 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7660 01:24:46.590643 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7661 01:24:46.597270 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7662 01:24:46.600788 1 4 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7663 01:24:46.604080 1 4 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7664 01:24:46.610533 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7665 01:24:46.614408 1 4 24 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
7666 01:24:46.616985 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7667 01:24:46.624142 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7668 01:24:46.626805 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7669 01:24:46.630676 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7670 01:24:46.637428 1 5 12 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
7671 01:24:46.639779 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7672 01:24:46.642993 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7673 01:24:46.650239 1 5 24 | B1->B0 | 2626 2323 | 1 0 | (1 0) (0 0)
7674 01:24:46.653584 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7675 01:24:46.656921 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7676 01:24:46.663299 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7677 01:24:46.666796 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7678 01:24:46.669856 1 6 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7679 01:24:46.676300 1 6 16 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7680 01:24:46.680864 1 6 20 | B1->B0 | 2828 4646 | 0 0 | (1 1) (0 0)
7681 01:24:46.682764 1 6 24 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
7682 01:24:46.689917 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7683 01:24:46.693078 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7684 01:24:46.696539 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7685 01:24:46.703085 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7686 01:24:46.706456 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7687 01:24:46.709433 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7688 01:24:46.716551 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7689 01:24:46.719759 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7690 01:24:46.722406 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 01:24:46.729136 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 01:24:46.732352 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7693 01:24:46.735664 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7694 01:24:46.742351 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7695 01:24:46.745428 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7696 01:24:46.748680 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 01:24:46.755612 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7698 01:24:46.758387 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7699 01:24:46.761854 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7700 01:24:46.768515 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7701 01:24:46.771634 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7702 01:24:46.775099 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7703 01:24:46.781498 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7704 01:24:46.781971 Total UI for P1: 0, mck2ui 16
7705 01:24:46.788218 best dqsien dly found for B0: ( 1, 9, 12)
7706 01:24:46.791620 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7707 01:24:46.794550 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7708 01:24:46.801315 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7709 01:24:46.801776 Total UI for P1: 0, mck2ui 16
7710 01:24:46.805117 best dqsien dly found for B1: ( 1, 9, 22)
7711 01:24:46.811409 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7712 01:24:46.814629 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7713 01:24:46.815042
7714 01:24:46.817710 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7715 01:24:46.821511 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7716 01:24:46.825067 [Gating] SW calibration Done
7717 01:24:46.825647 ==
7718 01:24:46.827659 Dram Type= 6, Freq= 0, CH_0, rank 0
7719 01:24:46.831263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7720 01:24:46.831782 ==
7721 01:24:46.834358 RX Vref Scan: 0
7722 01:24:46.834785
7723 01:24:46.835110 RX Vref 0 -> 0, step: 1
7724 01:24:46.835416
7725 01:24:46.837806 RX Delay 0 -> 252, step: 8
7726 01:24:46.841110 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7727 01:24:46.847285 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
7728 01:24:46.850531 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7729 01:24:46.854302 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7730 01:24:46.857196 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7731 01:24:46.860757 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7732 01:24:46.867153 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7733 01:24:46.870946 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7734 01:24:46.873836 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7735 01:24:46.876781 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7736 01:24:46.883798 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7737 01:24:46.887180 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7738 01:24:46.890085 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7739 01:24:46.893452 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7740 01:24:46.897094 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7741 01:24:46.903915 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7742 01:24:46.904469 ==
7743 01:24:46.907221 Dram Type= 6, Freq= 0, CH_0, rank 0
7744 01:24:46.909886 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7745 01:24:46.910354 ==
7746 01:24:46.910717 DQS Delay:
7747 01:24:46.913289 DQS0 = 0, DQS1 = 0
7748 01:24:46.913779 DQM Delay:
7749 01:24:46.916572 DQM0 = 134, DQM1 = 126
7750 01:24:46.917027 DQ Delay:
7751 01:24:46.920033 DQ0 =135, DQ1 =135, DQ2 =131, DQ3 =131
7752 01:24:46.923034 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =147
7753 01:24:46.926941 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7754 01:24:46.929953 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
7755 01:24:46.933206
7756 01:24:46.933684
7757 01:24:46.934040 ==
7758 01:24:46.936710 Dram Type= 6, Freq= 0, CH_0, rank 0
7759 01:24:46.939742 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7760 01:24:46.940217 ==
7761 01:24:46.940720
7762 01:24:46.941068
7763 01:24:46.943291 TX Vref Scan disable
7764 01:24:46.943844 == TX Byte 0 ==
7765 01:24:46.949778 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7766 01:24:46.953111 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7767 01:24:46.953719 == TX Byte 1 ==
7768 01:24:46.959172 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7769 01:24:46.962584 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7770 01:24:46.963085 ==
7771 01:24:46.965916 Dram Type= 6, Freq= 0, CH_0, rank 0
7772 01:24:46.970065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7773 01:24:46.970525 ==
7774 01:24:46.983766
7775 01:24:46.986661 TX Vref early break, caculate TX vref
7776 01:24:46.990003 TX Vref=16, minBit 6, minWin=21, winSum=369
7777 01:24:46.993491 TX Vref=18, minBit 4, minWin=22, winSum=382
7778 01:24:46.996629 TX Vref=20, minBit 14, minWin=23, winSum=392
7779 01:24:47.000198 TX Vref=22, minBit 6, minWin=23, winSum=401
7780 01:24:47.004061 TX Vref=24, minBit 4, minWin=24, winSum=407
7781 01:24:47.009952 TX Vref=26, minBit 4, minWin=25, winSum=416
7782 01:24:47.013285 TX Vref=28, minBit 0, minWin=25, winSum=420
7783 01:24:47.017053 TX Vref=30, minBit 4, minWin=24, winSum=408
7784 01:24:47.019974 TX Vref=32, minBit 4, minWin=23, winSum=402
7785 01:24:47.023159 TX Vref=34, minBit 4, minWin=22, winSum=390
7786 01:24:47.029680 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 28
7787 01:24:47.030254
7788 01:24:47.033384 Final TX Range 0 Vref 28
7789 01:24:47.033958
7790 01:24:47.034321 ==
7791 01:24:47.036397 Dram Type= 6, Freq= 0, CH_0, rank 0
7792 01:24:47.039692 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7793 01:24:47.040152 ==
7794 01:24:47.040560
7795 01:24:47.040958
7796 01:24:47.042480 TX Vref Scan disable
7797 01:24:47.049604 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7798 01:24:47.050060 == TX Byte 0 ==
7799 01:24:47.053091 u2DelayCellOfst[0]=11 cells (3 PI)
7800 01:24:47.055936 u2DelayCellOfst[1]=18 cells (5 PI)
7801 01:24:47.058866 u2DelayCellOfst[2]=11 cells (3 PI)
7802 01:24:47.062186 u2DelayCellOfst[3]=11 cells (3 PI)
7803 01:24:47.065996 u2DelayCellOfst[4]=11 cells (3 PI)
7804 01:24:47.068812 u2DelayCellOfst[5]=0 cells (0 PI)
7805 01:24:47.072582 u2DelayCellOfst[6]=18 cells (5 PI)
7806 01:24:47.075638 u2DelayCellOfst[7]=18 cells (5 PI)
7807 01:24:47.078891 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7808 01:24:47.082004 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7809 01:24:47.085473 == TX Byte 1 ==
7810 01:24:47.089046 u2DelayCellOfst[8]=0 cells (0 PI)
7811 01:24:47.092061 u2DelayCellOfst[9]=0 cells (0 PI)
7812 01:24:47.095919 u2DelayCellOfst[10]=3 cells (1 PI)
7813 01:24:47.098815 u2DelayCellOfst[11]=0 cells (0 PI)
7814 01:24:47.102744 u2DelayCellOfst[12]=11 cells (3 PI)
7815 01:24:47.103294 u2DelayCellOfst[13]=11 cells (3 PI)
7816 01:24:47.105197 u2DelayCellOfst[14]=15 cells (4 PI)
7817 01:24:47.108518 u2DelayCellOfst[15]=11 cells (3 PI)
7818 01:24:47.115237 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7819 01:24:47.118473 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7820 01:24:47.121746 DramC Write-DBI on
7821 01:24:47.122206 ==
7822 01:24:47.125174 Dram Type= 6, Freq= 0, CH_0, rank 0
7823 01:24:47.128324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7824 01:24:47.128875 ==
7825 01:24:47.129244
7826 01:24:47.129650
7827 01:24:47.131501 TX Vref Scan disable
7828 01:24:47.131960 == TX Byte 0 ==
7829 01:24:47.138316 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7830 01:24:47.138875 == TX Byte 1 ==
7831 01:24:47.144626 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7832 01:24:47.145178 DramC Write-DBI off
7833 01:24:47.145588
7834 01:24:47.145934 [DATLAT]
7835 01:24:47.148377 Freq=1600, CH0 RK0
7836 01:24:47.148942
7837 01:24:47.149315 DATLAT Default: 0xf
7838 01:24:47.151129 0, 0xFFFF, sum = 0
7839 01:24:47.154512 1, 0xFFFF, sum = 0
7840 01:24:47.154996 2, 0xFFFF, sum = 0
7841 01:24:47.157885 3, 0xFFFF, sum = 0
7842 01:24:47.158354 4, 0xFFFF, sum = 0
7843 01:24:47.161107 5, 0xFFFF, sum = 0
7844 01:24:47.161703 6, 0xFFFF, sum = 0
7845 01:24:47.165086 7, 0xFFFF, sum = 0
7846 01:24:47.165695 8, 0xFFFF, sum = 0
7847 01:24:47.168235 9, 0xFFFF, sum = 0
7848 01:24:47.168821 10, 0xFFFF, sum = 0
7849 01:24:47.171175 11, 0xFFFF, sum = 0
7850 01:24:47.171640 12, 0xFFFF, sum = 0
7851 01:24:47.173896 13, 0xFFFF, sum = 0
7852 01:24:47.174364 14, 0x0, sum = 1
7853 01:24:47.177873 15, 0x0, sum = 2
7854 01:24:47.178436 16, 0x0, sum = 3
7855 01:24:47.180639 17, 0x0, sum = 4
7856 01:24:47.181104 best_step = 15
7857 01:24:47.181534
7858 01:24:47.181886 ==
7859 01:24:47.184370 Dram Type= 6, Freq= 0, CH_0, rank 0
7860 01:24:47.190405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7861 01:24:47.190937 ==
7862 01:24:47.191311 RX Vref Scan: 1
7863 01:24:47.191655
7864 01:24:47.194089 Set Vref Range= 24 -> 127
7865 01:24:47.194549
7866 01:24:47.197402 RX Vref 24 -> 127, step: 1
7867 01:24:47.197954
7868 01:24:47.200157 RX Delay 19 -> 252, step: 4
7869 01:24:47.200630
7870 01:24:47.203699 Set Vref, RX VrefLevel [Byte0]: 24
7871 01:24:47.206714 [Byte1]: 24
7872 01:24:47.207266
7873 01:24:47.209887 Set Vref, RX VrefLevel [Byte0]: 25
7874 01:24:47.213395 [Byte1]: 25
7875 01:24:47.213945
7876 01:24:47.216979 Set Vref, RX VrefLevel [Byte0]: 26
7877 01:24:47.220040 [Byte1]: 26
7878 01:24:47.223632
7879 01:24:47.224184 Set Vref, RX VrefLevel [Byte0]: 27
7880 01:24:47.227009 [Byte1]: 27
7881 01:24:47.230948
7882 01:24:47.231507 Set Vref, RX VrefLevel [Byte0]: 28
7883 01:24:47.234337 [Byte1]: 28
7884 01:24:47.239001
7885 01:24:47.239547 Set Vref, RX VrefLevel [Byte0]: 29
7886 01:24:47.241654 [Byte1]: 29
7887 01:24:47.246307
7888 01:24:47.246855 Set Vref, RX VrefLevel [Byte0]: 30
7889 01:24:47.249556 [Byte1]: 30
7890 01:24:47.253998
7891 01:24:47.254551 Set Vref, RX VrefLevel [Byte0]: 31
7892 01:24:47.257585 [Byte1]: 31
7893 01:24:47.261554
7894 01:24:47.262104 Set Vref, RX VrefLevel [Byte0]: 32
7895 01:24:47.264232 [Byte1]: 32
7896 01:24:47.269171
7897 01:24:47.269760 Set Vref, RX VrefLevel [Byte0]: 33
7898 01:24:47.272301 [Byte1]: 33
7899 01:24:47.276969
7900 01:24:47.277560 Set Vref, RX VrefLevel [Byte0]: 34
7901 01:24:47.279708 [Byte1]: 34
7902 01:24:47.283919
7903 01:24:47.284367 Set Vref, RX VrefLevel [Byte0]: 35
7904 01:24:47.287542 [Byte1]: 35
7905 01:24:47.291683
7906 01:24:47.292237 Set Vref, RX VrefLevel [Byte0]: 36
7907 01:24:47.294917 [Byte1]: 36
7908 01:24:47.299064
7909 01:24:47.299517 Set Vref, RX VrefLevel [Byte0]: 37
7910 01:24:47.302421 [Byte1]: 37
7911 01:24:47.306968
7912 01:24:47.307522 Set Vref, RX VrefLevel [Byte0]: 38
7913 01:24:47.309747 [Byte1]: 38
7914 01:24:47.314090
7915 01:24:47.314559 Set Vref, RX VrefLevel [Byte0]: 39
7916 01:24:47.317708 [Byte1]: 39
7917 01:24:47.322073
7918 01:24:47.322621 Set Vref, RX VrefLevel [Byte0]: 40
7919 01:24:47.325201 [Byte1]: 40
7920 01:24:47.329549
7921 01:24:47.330138 Set Vref, RX VrefLevel [Byte0]: 41
7922 01:24:47.336145 [Byte1]: 41
7923 01:24:47.336699
7924 01:24:47.339298 Set Vref, RX VrefLevel [Byte0]: 42
7925 01:24:47.342294 [Byte1]: 42
7926 01:24:47.342750
7927 01:24:47.345867 Set Vref, RX VrefLevel [Byte0]: 43
7928 01:24:47.349016 [Byte1]: 43
7929 01:24:47.349507
7930 01:24:47.352361 Set Vref, RX VrefLevel [Byte0]: 44
7931 01:24:47.355686 [Byte1]: 44
7932 01:24:47.359874
7933 01:24:47.360434 Set Vref, RX VrefLevel [Byte0]: 45
7934 01:24:47.362951 [Byte1]: 45
7935 01:24:47.367501
7936 01:24:47.368054 Set Vref, RX VrefLevel [Byte0]: 46
7937 01:24:47.370498 [Byte1]: 46
7938 01:24:47.374985
7939 01:24:47.375540 Set Vref, RX VrefLevel [Byte0]: 47
7940 01:24:47.378418 [Byte1]: 47
7941 01:24:47.382480
7942 01:24:47.382937 Set Vref, RX VrefLevel [Byte0]: 48
7943 01:24:47.385372 [Byte1]: 48
7944 01:24:47.389924
7945 01:24:47.390479 Set Vref, RX VrefLevel [Byte0]: 49
7946 01:24:47.393306 [Byte1]: 49
7947 01:24:47.397666
7948 01:24:47.398216 Set Vref, RX VrefLevel [Byte0]: 50
7949 01:24:47.401147 [Byte1]: 50
7950 01:24:47.405202
7951 01:24:47.405863 Set Vref, RX VrefLevel [Byte0]: 51
7952 01:24:47.408347 [Byte1]: 51
7953 01:24:47.412904
7954 01:24:47.413604 Set Vref, RX VrefLevel [Byte0]: 52
7955 01:24:47.416137 [Byte1]: 52
7956 01:24:47.421041
7957 01:24:47.421636 Set Vref, RX VrefLevel [Byte0]: 53
7958 01:24:47.423818 [Byte1]: 53
7959 01:24:47.428121
7960 01:24:47.428666 Set Vref, RX VrefLevel [Byte0]: 54
7961 01:24:47.431123 [Byte1]: 54
7962 01:24:47.435622
7963 01:24:47.436170 Set Vref, RX VrefLevel [Byte0]: 55
7964 01:24:47.438907 [Byte1]: 55
7965 01:24:47.443039
7966 01:24:47.443492 Set Vref, RX VrefLevel [Byte0]: 56
7967 01:24:47.446023 [Byte1]: 56
7968 01:24:47.450758
7969 01:24:47.451210 Set Vref, RX VrefLevel [Byte0]: 57
7970 01:24:47.453807 [Byte1]: 57
7971 01:24:47.458133
7972 01:24:47.458542 Set Vref, RX VrefLevel [Byte0]: 58
7973 01:24:47.461667 [Byte1]: 58
7974 01:24:47.465754
7975 01:24:47.466164 Set Vref, RX VrefLevel [Byte0]: 59
7976 01:24:47.468775 [Byte1]: 59
7977 01:24:47.473529
7978 01:24:47.474074 Set Vref, RX VrefLevel [Byte0]: 60
7979 01:24:47.476232 [Byte1]: 60
7980 01:24:47.480722
7981 01:24:47.481201 Set Vref, RX VrefLevel [Byte0]: 61
7982 01:24:47.484631 [Byte1]: 61
7983 01:24:47.488307
7984 01:24:47.488818 Set Vref, RX VrefLevel [Byte0]: 62
7985 01:24:47.491999 [Byte1]: 62
7986 01:24:47.496201
7987 01:24:47.496712 Set Vref, RX VrefLevel [Byte0]: 63
7988 01:24:47.499427 [Byte1]: 63
7989 01:24:47.503471
7990 01:24:47.504135 Set Vref, RX VrefLevel [Byte0]: 64
7991 01:24:47.507314 [Byte1]: 64
7992 01:24:47.511238
7993 01:24:47.511795 Set Vref, RX VrefLevel [Byte0]: 65
7994 01:24:47.514177 [Byte1]: 65
7995 01:24:47.518707
7996 01:24:47.519283 Set Vref, RX VrefLevel [Byte0]: 66
7997 01:24:47.521829 [Byte1]: 66
7998 01:24:47.526264
7999 01:24:47.526814 Set Vref, RX VrefLevel [Byte0]: 67
8000 01:24:47.529516 [Byte1]: 67
8001 01:24:47.533957
8002 01:24:47.534454 Set Vref, RX VrefLevel [Byte0]: 68
8003 01:24:47.537213 [Byte1]: 68
8004 01:24:47.541542
8005 01:24:47.542018 Set Vref, RX VrefLevel [Byte0]: 69
8006 01:24:47.545001 [Byte1]: 69
8007 01:24:47.549181
8008 01:24:47.549836 Set Vref, RX VrefLevel [Byte0]: 70
8009 01:24:47.552607 [Byte1]: 70
8010 01:24:47.556939
8011 01:24:47.557539 Set Vref, RX VrefLevel [Byte0]: 71
8012 01:24:47.560091 [Byte1]: 71
8013 01:24:47.564268
8014 01:24:47.564824 Set Vref, RX VrefLevel [Byte0]: 72
8015 01:24:47.567884 [Byte1]: 72
8016 01:24:47.572323
8017 01:24:47.572874 Set Vref, RX VrefLevel [Byte0]: 73
8018 01:24:47.575295 [Byte1]: 73
8019 01:24:47.579196
8020 01:24:47.579655 Set Vref, RX VrefLevel [Byte0]: 74
8021 01:24:47.582315 [Byte1]: 74
8022 01:24:47.586543
8023 01:24:47.586998 Set Vref, RX VrefLevel [Byte0]: 75
8024 01:24:47.589906 [Byte1]: 75
8025 01:24:47.594761
8026 01:24:47.595277 Set Vref, RX VrefLevel [Byte0]: 76
8027 01:24:47.597679 [Byte1]: 76
8028 01:24:47.602197
8029 01:24:47.602703 Set Vref, RX VrefLevel [Byte0]: 77
8030 01:24:47.605153 [Byte1]: 77
8031 01:24:47.609812
8032 01:24:47.610377 Set Vref, RX VrefLevel [Byte0]: 78
8033 01:24:47.612641 [Byte1]: 78
8034 01:24:47.617141
8035 01:24:47.617702 Set Vref, RX VrefLevel [Byte0]: 79
8036 01:24:47.620265 [Byte1]: 79
8037 01:24:47.624972
8038 01:24:47.625543 Set Vref, RX VrefLevel [Byte0]: 80
8039 01:24:47.628144 [Byte1]: 80
8040 01:24:47.632468
8041 01:24:47.632920 Final RX Vref Byte 0 = 63 to rank0
8042 01:24:47.635609 Final RX Vref Byte 1 = 61 to rank0
8043 01:24:47.638952 Final RX Vref Byte 0 = 63 to rank1
8044 01:24:47.641912 Final RX Vref Byte 1 = 61 to rank1==
8045 01:24:47.645819 Dram Type= 6, Freq= 0, CH_0, rank 0
8046 01:24:47.652499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8047 01:24:47.653032 ==
8048 01:24:47.653623 DQS Delay:
8049 01:24:47.654010 DQS0 = 0, DQS1 = 0
8050 01:24:47.655245 DQM Delay:
8051 01:24:47.655658 DQM0 = 132, DQM1 = 124
8052 01:24:47.659022 DQ Delay:
8053 01:24:47.661739 DQ0 =130, DQ1 =132, DQ2 =130, DQ3 =132
8054 01:24:47.665324 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =142
8055 01:24:47.668824 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8056 01:24:47.671773 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =130
8057 01:24:47.672207
8058 01:24:47.672539
8059 01:24:47.672843
8060 01:24:47.675333 [DramC_TX_OE_Calibration] TA2
8061 01:24:47.679010 Original DQ_B0 (3 6) =30, OEN = 27
8062 01:24:47.681984 Original DQ_B1 (3 6) =30, OEN = 27
8063 01:24:47.685138 24, 0x0, End_B0=24 End_B1=24
8064 01:24:47.685691 25, 0x0, End_B0=25 End_B1=25
8065 01:24:47.688817 26, 0x0, End_B0=26 End_B1=26
8066 01:24:47.691855 27, 0x0, End_B0=27 End_B1=27
8067 01:24:47.694837 28, 0x0, End_B0=28 End_B1=28
8068 01:24:47.698386 29, 0x0, End_B0=29 End_B1=29
8069 01:24:47.698909 30, 0x0, End_B0=30 End_B1=30
8070 01:24:47.701136 31, 0x4545, End_B0=30 End_B1=30
8071 01:24:47.705119 Byte0 end_step=30 best_step=27
8072 01:24:47.708464 Byte1 end_step=30 best_step=27
8073 01:24:47.711425 Byte0 TX OE(2T, 0.5T) = (3, 3)
8074 01:24:47.714567 Byte1 TX OE(2T, 0.5T) = (3, 3)
8075 01:24:47.714998
8076 01:24:47.715461
8077 01:24:47.721706 [DQSOSCAuto] RK0, (LSB)MR18= 0x2113, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8078 01:24:47.724716 CH0 RK0: MR19=303, MR18=2113
8079 01:24:47.731197 CH0_RK0: MR19=0x303, MR18=0x2113, DQSOSC=393, MR23=63, INC=23, DEC=15
8080 01:24:47.731733
8081 01:24:47.734235 ----->DramcWriteLeveling(PI) begin...
8082 01:24:47.734683 ==
8083 01:24:47.737525 Dram Type= 6, Freq= 0, CH_0, rank 1
8084 01:24:47.741180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8085 01:24:47.741836 ==
8086 01:24:47.744274 Write leveling (Byte 0): 34 => 34
8087 01:24:47.748096 Write leveling (Byte 1): 26 => 26
8088 01:24:47.750568 DramcWriteLeveling(PI) end<-----
8089 01:24:47.751002
8090 01:24:47.751332 ==
8091 01:24:47.753995 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 01:24:47.760756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 01:24:47.761264 ==
8094 01:24:47.761640 [Gating] SW mode calibration
8095 01:24:47.770704 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8096 01:24:47.774292 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8097 01:24:47.777545 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8098 01:24:47.783850 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8099 01:24:47.787330 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8100 01:24:47.790346 1 4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8101 01:24:47.797221 1 4 16 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
8102 01:24:47.800895 1 4 20 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
8103 01:24:47.804157 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8104 01:24:47.810258 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8105 01:24:47.813407 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8106 01:24:47.816822 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8107 01:24:47.823584 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8108 01:24:47.826366 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8109 01:24:47.833084 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
8110 01:24:47.836084 1 5 20 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
8111 01:24:47.839620 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8112 01:24:47.846243 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8113 01:24:47.849415 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8114 01:24:47.852684 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8115 01:24:47.859060 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8116 01:24:47.862892 1 6 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8117 01:24:47.865957 1 6 16 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8118 01:24:47.872933 1 6 20 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
8119 01:24:47.876232 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8120 01:24:47.879286 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8121 01:24:47.885229 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8122 01:24:47.888987 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8123 01:24:47.892275 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8124 01:24:47.898612 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8125 01:24:47.902078 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8126 01:24:47.905099 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8127 01:24:47.911703 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8128 01:24:47.915003 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8129 01:24:47.918240 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8130 01:24:47.925495 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8131 01:24:47.928648 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 01:24:47.931450 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8133 01:24:47.938005 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8134 01:24:47.941894 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8135 01:24:47.944595 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8136 01:24:47.951115 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8137 01:24:47.954481 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8138 01:24:47.957968 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8139 01:24:47.964205 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8140 01:24:47.967649 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8141 01:24:47.970750 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8142 01:24:47.974243 Total UI for P1: 0, mck2ui 16
8143 01:24:47.977446 best dqsien dly found for B0: ( 1, 9, 12)
8144 01:24:47.984070 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8145 01:24:47.987707 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8146 01:24:47.990767 Total UI for P1: 0, mck2ui 16
8147 01:24:47.994035 best dqsien dly found for B1: ( 1, 9, 18)
8148 01:24:47.997651 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8149 01:24:48.000855 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8150 01:24:48.001427
8151 01:24:48.003799 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8152 01:24:48.006902 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8153 01:24:48.010650 [Gating] SW calibration Done
8154 01:24:48.011072 ==
8155 01:24:48.014165 Dram Type= 6, Freq= 0, CH_0, rank 1
8156 01:24:48.020213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8157 01:24:48.020760 ==
8158 01:24:48.021326 RX Vref Scan: 0
8159 01:24:48.021767
8160 01:24:48.023687 RX Vref 0 -> 0, step: 1
8161 01:24:48.024107
8162 01:24:48.027221 RX Delay 0 -> 252, step: 8
8163 01:24:48.030134 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8164 01:24:48.033302 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8165 01:24:48.036833 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8166 01:24:48.040365 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8167 01:24:48.047029 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8168 01:24:48.050138 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8169 01:24:48.053515 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8170 01:24:48.057039 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8171 01:24:48.060232 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8172 01:24:48.066851 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8173 01:24:48.069729 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8174 01:24:48.072998 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8175 01:24:48.076682 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8176 01:24:48.083125 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8177 01:24:48.086309 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8178 01:24:48.089811 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8179 01:24:48.090221 ==
8180 01:24:48.093042 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 01:24:48.096662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 01:24:48.097085 ==
8183 01:24:48.099570 DQS Delay:
8184 01:24:48.099976 DQS0 = 0, DQS1 = 0
8185 01:24:48.102746 DQM Delay:
8186 01:24:48.103189 DQM0 = 132, DQM1 = 128
8187 01:24:48.106146 DQ Delay:
8188 01:24:48.109556 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8189 01:24:48.112335 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8190 01:24:48.115819 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =119
8191 01:24:48.119251 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8192 01:24:48.119846
8193 01:24:48.120403
8194 01:24:48.120927 ==
8195 01:24:48.122683 Dram Type= 6, Freq= 0, CH_0, rank 1
8196 01:24:48.125780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8197 01:24:48.126192 ==
8198 01:24:48.129053
8199 01:24:48.129489
8200 01:24:48.129974 TX Vref Scan disable
8201 01:24:48.132414 == TX Byte 0 ==
8202 01:24:48.135467 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8203 01:24:48.139251 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8204 01:24:48.142250 == TX Byte 1 ==
8205 01:24:48.145890 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8206 01:24:48.149072 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8207 01:24:48.152276 ==
8208 01:24:48.152813 Dram Type= 6, Freq= 0, CH_0, rank 1
8209 01:24:48.158497 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8210 01:24:48.158991 ==
8211 01:24:48.171629
8212 01:24:48.174841 TX Vref early break, caculate TX vref
8213 01:24:48.177769 TX Vref=16, minBit 1, minWin=23, winSum=375
8214 01:24:48.180926 TX Vref=18, minBit 0, minWin=23, winSum=381
8215 01:24:48.184378 TX Vref=20, minBit 0, minWin=23, winSum=393
8216 01:24:48.188230 TX Vref=22, minBit 1, minWin=23, winSum=397
8217 01:24:48.191131 TX Vref=24, minBit 1, minWin=24, winSum=406
8218 01:24:48.198187 TX Vref=26, minBit 1, minWin=24, winSum=411
8219 01:24:48.200962 TX Vref=28, minBit 0, minWin=25, winSum=410
8220 01:24:48.204403 TX Vref=30, minBit 0, minWin=24, winSum=400
8221 01:24:48.207717 TX Vref=32, minBit 0, minWin=23, winSum=393
8222 01:24:48.211171 TX Vref=34, minBit 0, minWin=23, winSum=385
8223 01:24:48.217842 [TxChooseVref] Worse bit 0, Min win 25, Win sum 410, Final Vref 28
8224 01:24:48.218404
8225 01:24:48.221175 Final TX Range 0 Vref 28
8226 01:24:48.221800
8227 01:24:48.222169 ==
8228 01:24:48.224206 Dram Type= 6, Freq= 0, CH_0, rank 1
8229 01:24:48.227626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8230 01:24:48.228178 ==
8231 01:24:48.228540
8232 01:24:48.228869
8233 01:24:48.230632 TX Vref Scan disable
8234 01:24:48.237564 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8235 01:24:48.238120 == TX Byte 0 ==
8236 01:24:48.240817 u2DelayCellOfst[0]=15 cells (4 PI)
8237 01:24:48.243691 u2DelayCellOfst[1]=18 cells (5 PI)
8238 01:24:48.247305 u2DelayCellOfst[2]=15 cells (4 PI)
8239 01:24:48.250820 u2DelayCellOfst[3]=15 cells (4 PI)
8240 01:24:48.253551 u2DelayCellOfst[4]=11 cells (3 PI)
8241 01:24:48.257310 u2DelayCellOfst[5]=0 cells (0 PI)
8242 01:24:48.260639 u2DelayCellOfst[6]=18 cells (5 PI)
8243 01:24:48.263777 u2DelayCellOfst[7]=22 cells (6 PI)
8244 01:24:48.266887 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8245 01:24:48.270546 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8246 01:24:48.273570 == TX Byte 1 ==
8247 01:24:48.277791 u2DelayCellOfst[8]=0 cells (0 PI)
8248 01:24:48.280892 u2DelayCellOfst[9]=3 cells (1 PI)
8249 01:24:48.283363 u2DelayCellOfst[10]=7 cells (2 PI)
8250 01:24:48.283815 u2DelayCellOfst[11]=3 cells (1 PI)
8251 01:24:48.286866 u2DelayCellOfst[12]=11 cells (3 PI)
8252 01:24:48.289932 u2DelayCellOfst[13]=11 cells (3 PI)
8253 01:24:48.293553 u2DelayCellOfst[14]=18 cells (5 PI)
8254 01:24:48.296780 u2DelayCellOfst[15]=11 cells (3 PI)
8255 01:24:48.303756 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8256 01:24:48.306990 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8257 01:24:48.307542 DramC Write-DBI on
8258 01:24:48.310062 ==
8259 01:24:48.313639 Dram Type= 6, Freq= 0, CH_0, rank 1
8260 01:24:48.316917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8261 01:24:48.317550 ==
8262 01:24:48.317927
8263 01:24:48.318261
8264 01:24:48.320147 TX Vref Scan disable
8265 01:24:48.320701 == TX Byte 0 ==
8266 01:24:48.326602 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8267 01:24:48.327150 == TX Byte 1 ==
8268 01:24:48.329445 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8269 01:24:48.333435 DramC Write-DBI off
8270 01:24:48.333995
8271 01:24:48.334353 [DATLAT]
8272 01:24:48.336091 Freq=1600, CH0 RK1
8273 01:24:48.336540
8274 01:24:48.336895 DATLAT Default: 0xf
8275 01:24:48.339352 0, 0xFFFF, sum = 0
8276 01:24:48.339814 1, 0xFFFF, sum = 0
8277 01:24:48.342895 2, 0xFFFF, sum = 0
8278 01:24:48.343354 3, 0xFFFF, sum = 0
8279 01:24:48.346961 4, 0xFFFF, sum = 0
8280 01:24:48.349505 5, 0xFFFF, sum = 0
8281 01:24:48.350058 6, 0xFFFF, sum = 0
8282 01:24:48.353081 7, 0xFFFF, sum = 0
8283 01:24:48.353693 8, 0xFFFF, sum = 0
8284 01:24:48.356281 9, 0xFFFF, sum = 0
8285 01:24:48.356828 10, 0xFFFF, sum = 0
8286 01:24:48.359779 11, 0xFFFF, sum = 0
8287 01:24:48.360272 12, 0xFFFF, sum = 0
8288 01:24:48.362900 13, 0xFFFF, sum = 0
8289 01:24:48.363453 14, 0x0, sum = 1
8290 01:24:48.366132 15, 0x0, sum = 2
8291 01:24:48.366617 16, 0x0, sum = 3
8292 01:24:48.369269 17, 0x0, sum = 4
8293 01:24:48.369772 best_step = 15
8294 01:24:48.370128
8295 01:24:48.370539 ==
8296 01:24:48.372653 Dram Type= 6, Freq= 0, CH_0, rank 1
8297 01:24:48.376034 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8298 01:24:48.379423 ==
8299 01:24:48.379986 RX Vref Scan: 0
8300 01:24:48.380465
8301 01:24:48.382322 RX Vref 0 -> 0, step: 1
8302 01:24:48.382784
8303 01:24:48.385668 RX Delay 11 -> 252, step: 4
8304 01:24:48.389278 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8305 01:24:48.392740 iDelay=195, Bit 1, Center 134 (83 ~ 186) 104
8306 01:24:48.395689 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8307 01:24:48.402283 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8308 01:24:48.405472 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8309 01:24:48.408903 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8310 01:24:48.411827 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8311 01:24:48.415535 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8312 01:24:48.422010 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8313 01:24:48.425467 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8314 01:24:48.428882 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8315 01:24:48.431817 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8316 01:24:48.438755 iDelay=195, Bit 12, Center 128 (75 ~ 182) 108
8317 01:24:48.441967 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8318 01:24:48.445285 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8319 01:24:48.448705 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8320 01:24:48.449272 ==
8321 01:24:48.451556 Dram Type= 6, Freq= 0, CH_0, rank 1
8322 01:24:48.457939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8323 01:24:48.458689 ==
8324 01:24:48.459247 DQS Delay:
8325 01:24:48.459606 DQS0 = 0, DQS1 = 0
8326 01:24:48.461267 DQM Delay:
8327 01:24:48.461772 DQM0 = 130, DQM1 = 125
8328 01:24:48.464585 DQ Delay:
8329 01:24:48.467977 DQ0 =128, DQ1 =134, DQ2 =126, DQ3 =128
8330 01:24:48.471024 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8331 01:24:48.474618 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8332 01:24:48.477495 DQ12 =128, DQ13 =132, DQ14 =136, DQ15 =132
8333 01:24:48.477948
8334 01:24:48.478304
8335 01:24:48.478637
8336 01:24:48.480897 [DramC_TX_OE_Calibration] TA2
8337 01:24:48.484836 Original DQ_B0 (3 6) =30, OEN = 27
8338 01:24:48.487587 Original DQ_B1 (3 6) =30, OEN = 27
8339 01:24:48.490784 24, 0x0, End_B0=24 End_B1=24
8340 01:24:48.491316 25, 0x0, End_B0=25 End_B1=25
8341 01:24:48.494053 26, 0x0, End_B0=26 End_B1=26
8342 01:24:48.497195 27, 0x0, End_B0=27 End_B1=27
8343 01:24:48.500903 28, 0x0, End_B0=28 End_B1=28
8344 01:24:48.504007 29, 0x0, End_B0=29 End_B1=29
8345 01:24:48.504428 30, 0x0, End_B0=30 End_B1=30
8346 01:24:48.507446 31, 0x4141, End_B0=30 End_B1=30
8347 01:24:48.510945 Byte0 end_step=30 best_step=27
8348 01:24:48.513831 Byte1 end_step=30 best_step=27
8349 01:24:48.517474 Byte0 TX OE(2T, 0.5T) = (3, 3)
8350 01:24:48.520734 Byte1 TX OE(2T, 0.5T) = (3, 3)
8351 01:24:48.521244
8352 01:24:48.521660
8353 01:24:48.527397 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d01, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 395 ps
8354 01:24:48.530600 CH0 RK1: MR19=303, MR18=1D01
8355 01:24:48.537024 CH0_RK1: MR19=0x303, MR18=0x1D01, DQSOSC=395, MR23=63, INC=23, DEC=15
8356 01:24:48.540469 [RxdqsGatingPostProcess] freq 1600
8357 01:24:48.547101 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8358 01:24:48.547613 best DQS0 dly(2T, 0.5T) = (1, 1)
8359 01:24:48.549957 best DQS1 dly(2T, 0.5T) = (1, 1)
8360 01:24:48.553490 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8361 01:24:48.556437 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8362 01:24:48.559719 best DQS0 dly(2T, 0.5T) = (1, 1)
8363 01:24:48.563474 best DQS1 dly(2T, 0.5T) = (1, 1)
8364 01:24:48.566328 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8365 01:24:48.570032 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8366 01:24:48.573061 Pre-setting of DQS Precalculation
8367 01:24:48.576389 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8368 01:24:48.579716 ==
8369 01:24:48.583478 Dram Type= 6, Freq= 0, CH_1, rank 0
8370 01:24:48.586257 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8371 01:24:48.586862 ==
8372 01:24:48.589018 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8373 01:24:48.596167 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8374 01:24:48.599461 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8375 01:24:48.605706 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8376 01:24:48.614566 [CA 0] Center 42 (13~72) winsize 60
8377 01:24:48.617505 [CA 1] Center 42 (13~72) winsize 60
8378 01:24:48.621173 [CA 2] Center 37 (9~66) winsize 58
8379 01:24:48.624327 [CA 3] Center 37 (8~66) winsize 59
8380 01:24:48.627248 [CA 4] Center 38 (8~68) winsize 61
8381 01:24:48.630709 [CA 5] Center 37 (8~67) winsize 60
8382 01:24:48.631209
8383 01:24:48.633678 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8384 01:24:48.634126
8385 01:24:48.640783 [CATrainingPosCal] consider 1 rank data
8386 01:24:48.641322 u2DelayCellTimex100 = 258/100 ps
8387 01:24:48.647145 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8388 01:24:48.650685 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8389 01:24:48.653911 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8390 01:24:48.656885 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8391 01:24:48.660168 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8392 01:24:48.663383 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8393 01:24:48.663920
8394 01:24:48.666973 CA PerBit enable=1, Macro0, CA PI delay=37
8395 01:24:48.667438
8396 01:24:48.670424 [CBTSetCACLKResult] CA Dly = 37
8397 01:24:48.673233 CS Dly: 9 (0~40)
8398 01:24:48.676810 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8399 01:24:48.680414 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8400 01:24:48.680977 ==
8401 01:24:48.683403 Dram Type= 6, Freq= 0, CH_1, rank 1
8402 01:24:48.689733 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8403 01:24:48.690182 ==
8404 01:24:48.693807 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8405 01:24:48.700249 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8406 01:24:48.703010 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8407 01:24:48.709478 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8408 01:24:48.717372 [CA 0] Center 42 (13~72) winsize 60
8409 01:24:48.720731 [CA 1] Center 42 (13~72) winsize 60
8410 01:24:48.723929 [CA 2] Center 37 (8~67) winsize 60
8411 01:24:48.727008 [CA 3] Center 37 (8~66) winsize 59
8412 01:24:48.730814 [CA 4] Center 37 (8~67) winsize 60
8413 01:24:48.733906 [CA 5] Center 37 (8~67) winsize 60
8414 01:24:48.734449
8415 01:24:48.737150 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8416 01:24:48.737743
8417 01:24:48.740676 [CATrainingPosCal] consider 2 rank data
8418 01:24:48.743804 u2DelayCellTimex100 = 258/100 ps
8419 01:24:48.750296 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8420 01:24:48.753405 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8421 01:24:48.757186 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8422 01:24:48.760329 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8423 01:24:48.763620 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8424 01:24:48.766689 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8425 01:24:48.767251
8426 01:24:48.770384 CA PerBit enable=1, Macro0, CA PI delay=37
8427 01:24:48.770925
8428 01:24:48.773523 [CBTSetCACLKResult] CA Dly = 37
8429 01:24:48.776634 CS Dly: 10 (0~43)
8430 01:24:48.780003 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8431 01:24:48.783612 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8432 01:24:48.784159
8433 01:24:48.786615 ----->DramcWriteLeveling(PI) begin...
8434 01:24:48.787108 ==
8435 01:24:48.789783 Dram Type= 6, Freq= 0, CH_1, rank 0
8436 01:24:48.796468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8437 01:24:48.797019 ==
8438 01:24:48.799905 Write leveling (Byte 0): 23 => 23
8439 01:24:48.803477 Write leveling (Byte 1): 27 => 27
8440 01:24:48.804026 DramcWriteLeveling(PI) end<-----
8441 01:24:48.806025
8442 01:24:48.806468 ==
8443 01:24:48.809706 Dram Type= 6, Freq= 0, CH_1, rank 0
8444 01:24:48.812949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8445 01:24:48.813443 ==
8446 01:24:48.816164 [Gating] SW mode calibration
8447 01:24:48.822494 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8448 01:24:48.829491 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8449 01:24:48.832678 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8450 01:24:48.835856 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8451 01:24:48.842357 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8452 01:24:48.845641 1 4 12 | B1->B0 | 2525 2d2d | 0 0 | (0 0) (0 0)
8453 01:24:48.848674 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8454 01:24:48.855368 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8455 01:24:48.858321 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8456 01:24:48.861653 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8457 01:24:48.868526 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8458 01:24:48.872015 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8459 01:24:48.875041 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8460 01:24:48.881223 1 5 12 | B1->B0 | 3333 2626 | 1 0 | (0 1) (1 0)
8461 01:24:48.885468 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8462 01:24:48.888263 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8463 01:24:48.895369 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8464 01:24:48.898231 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8465 01:24:48.901049 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8466 01:24:48.908120 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8467 01:24:48.911506 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8468 01:24:48.914396 1 6 12 | B1->B0 | 3837 4545 | 1 0 | (0 0) (0 0)
8469 01:24:48.921132 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8470 01:24:48.924904 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8471 01:24:48.927858 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8472 01:24:48.934535 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8473 01:24:48.937500 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8474 01:24:48.941051 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8475 01:24:48.947196 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8476 01:24:48.951047 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8477 01:24:48.954012 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8478 01:24:48.960707 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8479 01:24:48.963862 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8480 01:24:48.966855 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8481 01:24:48.973746 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8482 01:24:48.977130 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8483 01:24:48.980146 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8484 01:24:48.986801 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8485 01:24:48.989910 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8486 01:24:48.993360 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8487 01:24:49.000082 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8488 01:24:49.002974 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8489 01:24:49.006862 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8490 01:24:49.013073 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8491 01:24:49.016289 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8492 01:24:49.019900 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8493 01:24:49.026390 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8494 01:24:49.029673 Total UI for P1: 0, mck2ui 16
8495 01:24:49.033235 best dqsien dly found for B0: ( 1, 9, 10)
8496 01:24:49.033829 Total UI for P1: 0, mck2ui 16
8497 01:24:49.040272 best dqsien dly found for B1: ( 1, 9, 12)
8498 01:24:49.043252 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8499 01:24:49.046029 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8500 01:24:49.046480
8501 01:24:49.049866 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8502 01:24:49.053010 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8503 01:24:49.056042 [Gating] SW calibration Done
8504 01:24:49.056591 ==
8505 01:24:49.059088 Dram Type= 6, Freq= 0, CH_1, rank 0
8506 01:24:49.062726 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8507 01:24:49.063178 ==
8508 01:24:49.066038 RX Vref Scan: 0
8509 01:24:49.066488
8510 01:24:49.069404 RX Vref 0 -> 0, step: 1
8511 01:24:49.069852
8512 01:24:49.070211 RX Delay 0 -> 252, step: 8
8513 01:24:49.075747 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8514 01:24:49.079401 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8515 01:24:49.082644 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8516 01:24:49.085750 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8517 01:24:49.089014 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8518 01:24:49.095800 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8519 01:24:49.099488 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8520 01:24:49.102657 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8521 01:24:49.105908 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8522 01:24:49.109236 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8523 01:24:49.115509 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8524 01:24:49.118583 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8525 01:24:49.121950 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8526 01:24:49.125303 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8527 01:24:49.132278 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8528 01:24:49.135177 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8529 01:24:49.135739 ==
8530 01:24:49.138531 Dram Type= 6, Freq= 0, CH_1, rank 0
8531 01:24:49.141939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8532 01:24:49.142506 ==
8533 01:24:49.144868 DQS Delay:
8534 01:24:49.145495 DQS0 = 0, DQS1 = 0
8535 01:24:49.145969 DQM Delay:
8536 01:24:49.148689 DQM0 = 138, DQM1 = 131
8537 01:24:49.149302 DQ Delay:
8538 01:24:49.151909 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =139
8539 01:24:49.155315 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8540 01:24:49.158366 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8541 01:24:49.165216 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =143
8542 01:24:49.165821
8543 01:24:49.166294
8544 01:24:49.166733 ==
8545 01:24:49.168032 Dram Type= 6, Freq= 0, CH_1, rank 0
8546 01:24:49.171515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8547 01:24:49.172116 ==
8548 01:24:49.172596
8549 01:24:49.173041
8550 01:24:49.174741 TX Vref Scan disable
8551 01:24:49.175204 == TX Byte 0 ==
8552 01:24:49.181730 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8553 01:24:49.185046 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8554 01:24:49.185562 == TX Byte 1 ==
8555 01:24:49.191058 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8556 01:24:49.194288 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8557 01:24:49.194753 ==
8558 01:24:49.197826 Dram Type= 6, Freq= 0, CH_1, rank 0
8559 01:24:49.201048 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8560 01:24:49.201549 ==
8561 01:24:49.216217
8562 01:24:49.219358 TX Vref early break, caculate TX vref
8563 01:24:49.223021 TX Vref=16, minBit 5, minWin=21, winSum=370
8564 01:24:49.226443 TX Vref=18, minBit 0, minWin=22, winSum=384
8565 01:24:49.229374 TX Vref=20, minBit 5, minWin=22, winSum=391
8566 01:24:49.233028 TX Vref=22, minBit 5, minWin=23, winSum=399
8567 01:24:49.236141 TX Vref=24, minBit 0, minWin=24, winSum=409
8568 01:24:49.242829 TX Vref=26, minBit 0, minWin=24, winSum=413
8569 01:24:49.245969 TX Vref=28, minBit 5, minWin=24, winSum=414
8570 01:24:49.249044 TX Vref=30, minBit 0, minWin=24, winSum=411
8571 01:24:49.252716 TX Vref=32, minBit 1, minWin=24, winSum=402
8572 01:24:49.255691 TX Vref=34, minBit 0, minWin=23, winSum=394
8573 01:24:49.262261 TX Vref=36, minBit 1, minWin=22, winSum=380
8574 01:24:49.265985 [TxChooseVref] Worse bit 5, Min win 24, Win sum 414, Final Vref 28
8575 01:24:49.266453
8576 01:24:49.268979 Final TX Range 0 Vref 28
8577 01:24:49.269589
8578 01:24:49.270068 ==
8579 01:24:49.272014 Dram Type= 6, Freq= 0, CH_1, rank 0
8580 01:24:49.275480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8581 01:24:49.278822 ==
8582 01:24:49.279449
8583 01:24:49.279932
8584 01:24:49.280426 TX Vref Scan disable
8585 01:24:49.285639 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8586 01:24:49.286067 == TX Byte 0 ==
8587 01:24:49.288869 u2DelayCellOfst[0]=22 cells (6 PI)
8588 01:24:49.292276 u2DelayCellOfst[1]=15 cells (4 PI)
8589 01:24:49.295452 u2DelayCellOfst[2]=0 cells (0 PI)
8590 01:24:49.298472 u2DelayCellOfst[3]=7 cells (2 PI)
8591 01:24:49.302141 u2DelayCellOfst[4]=11 cells (3 PI)
8592 01:24:49.305150 u2DelayCellOfst[5]=22 cells (6 PI)
8593 01:24:49.308683 u2DelayCellOfst[6]=22 cells (6 PI)
8594 01:24:49.311568 u2DelayCellOfst[7]=7 cells (2 PI)
8595 01:24:49.315076 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8596 01:24:49.318050 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8597 01:24:49.321746 == TX Byte 1 ==
8598 01:24:49.324884 u2DelayCellOfst[8]=0 cells (0 PI)
8599 01:24:49.328418 u2DelayCellOfst[9]=3 cells (1 PI)
8600 01:24:49.331492 u2DelayCellOfst[10]=11 cells (3 PI)
8601 01:24:49.334788 u2DelayCellOfst[11]=3 cells (1 PI)
8602 01:24:49.338319 u2DelayCellOfst[12]=15 cells (4 PI)
8603 01:24:49.342057 u2DelayCellOfst[13]=18 cells (5 PI)
8604 01:24:49.344508 u2DelayCellOfst[14]=18 cells (5 PI)
8605 01:24:49.348145 u2DelayCellOfst[15]=18 cells (5 PI)
8606 01:24:49.351279 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8607 01:24:49.354848 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8608 01:24:49.358173 DramC Write-DBI on
8609 01:24:49.358634 ==
8610 01:24:49.361571 Dram Type= 6, Freq= 0, CH_1, rank 0
8611 01:24:49.364759 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8612 01:24:49.365319 ==
8613 01:24:49.365747
8614 01:24:49.366087
8615 01:24:49.368179 TX Vref Scan disable
8616 01:24:49.368631 == TX Byte 0 ==
8617 01:24:49.374549 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8618 01:24:49.375008 == TX Byte 1 ==
8619 01:24:49.378253 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8620 01:24:49.381210 DramC Write-DBI off
8621 01:24:49.381704
8622 01:24:49.382069 [DATLAT]
8623 01:24:49.384538 Freq=1600, CH1 RK0
8624 01:24:49.384994
8625 01:24:49.385396 DATLAT Default: 0xf
8626 01:24:49.388113 0, 0xFFFF, sum = 0
8627 01:24:49.390836 1, 0xFFFF, sum = 0
8628 01:24:49.391556 2, 0xFFFF, sum = 0
8629 01:24:49.393971 3, 0xFFFF, sum = 0
8630 01:24:49.394431 4, 0xFFFF, sum = 0
8631 01:24:49.397789 5, 0xFFFF, sum = 0
8632 01:24:49.398351 6, 0xFFFF, sum = 0
8633 01:24:49.400757 7, 0xFFFF, sum = 0
8634 01:24:49.401321 8, 0xFFFF, sum = 0
8635 01:24:49.404742 9, 0xFFFF, sum = 0
8636 01:24:49.405303 10, 0xFFFF, sum = 0
8637 01:24:49.407163 11, 0xFFFF, sum = 0
8638 01:24:49.407622 12, 0xFFFF, sum = 0
8639 01:24:49.410959 13, 0xFFFF, sum = 0
8640 01:24:49.411524 14, 0x0, sum = 1
8641 01:24:49.414466 15, 0x0, sum = 2
8642 01:24:49.415037 16, 0x0, sum = 3
8643 01:24:49.417399 17, 0x0, sum = 4
8644 01:24:49.417953 best_step = 15
8645 01:24:49.418318
8646 01:24:49.418654 ==
8647 01:24:49.420510 Dram Type= 6, Freq= 0, CH_1, rank 0
8648 01:24:49.427434 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8649 01:24:49.427992 ==
8650 01:24:49.428354 RX Vref Scan: 1
8651 01:24:49.428689
8652 01:24:49.430186 Set Vref Range= 24 -> 127
8653 01:24:49.430638
8654 01:24:49.433419 RX Vref 24 -> 127, step: 1
8655 01:24:49.433889
8656 01:24:49.437223 RX Delay 19 -> 252, step: 4
8657 01:24:49.437856
8658 01:24:49.440371 Set Vref, RX VrefLevel [Byte0]: 24
8659 01:24:49.443744 [Byte1]: 24
8660 01:24:49.444301
8661 01:24:49.447090 Set Vref, RX VrefLevel [Byte0]: 25
8662 01:24:49.450164 [Byte1]: 25
8663 01:24:49.450617
8664 01:24:49.453875 Set Vref, RX VrefLevel [Byte0]: 26
8665 01:24:49.457257 [Byte1]: 26
8666 01:24:49.457853
8667 01:24:49.459756 Set Vref, RX VrefLevel [Byte0]: 27
8668 01:24:49.463307 [Byte1]: 27
8669 01:24:49.467512
8670 01:24:49.468109 Set Vref, RX VrefLevel [Byte0]: 28
8671 01:24:49.470857 [Byte1]: 28
8672 01:24:49.475103
8673 01:24:49.478159 Set Vref, RX VrefLevel [Byte0]: 29
8674 01:24:49.478707 [Byte1]: 29
8675 01:24:49.482402
8676 01:24:49.482948 Set Vref, RX VrefLevel [Byte0]: 30
8677 01:24:49.486156 [Byte1]: 30
8678 01:24:49.489963
8679 01:24:49.490416 Set Vref, RX VrefLevel [Byte0]: 31
8680 01:24:49.493263 [Byte1]: 31
8681 01:24:49.497841
8682 01:24:49.498382 Set Vref, RX VrefLevel [Byte0]: 32
8683 01:24:49.500880 [Byte1]: 32
8684 01:24:49.505478
8685 01:24:49.506028 Set Vref, RX VrefLevel [Byte0]: 33
8686 01:24:49.508684 [Byte1]: 33
8687 01:24:49.512749
8688 01:24:49.513294 Set Vref, RX VrefLevel [Byte0]: 34
8689 01:24:49.515872 [Byte1]: 34
8690 01:24:49.520887
8691 01:24:49.521464 Set Vref, RX VrefLevel [Byte0]: 35
8692 01:24:49.523931 [Byte1]: 35
8693 01:24:49.528347
8694 01:24:49.528889 Set Vref, RX VrefLevel [Byte0]: 36
8695 01:24:49.531533 [Byte1]: 36
8696 01:24:49.535823
8697 01:24:49.536364 Set Vref, RX VrefLevel [Byte0]: 37
8698 01:24:49.539086 [Byte1]: 37
8699 01:24:49.543032
8700 01:24:49.543577 Set Vref, RX VrefLevel [Byte0]: 38
8701 01:24:49.546525 [Byte1]: 38
8702 01:24:49.550810
8703 01:24:49.551259 Set Vref, RX VrefLevel [Byte0]: 39
8704 01:24:49.553702 [Byte1]: 39
8705 01:24:49.558070
8706 01:24:49.558517 Set Vref, RX VrefLevel [Byte0]: 40
8707 01:24:49.561579 [Byte1]: 40
8708 01:24:49.565850
8709 01:24:49.566298 Set Vref, RX VrefLevel [Byte0]: 41
8710 01:24:49.569224 [Byte1]: 41
8711 01:24:49.573775
8712 01:24:49.574325 Set Vref, RX VrefLevel [Byte0]: 42
8713 01:24:49.576713 [Byte1]: 42
8714 01:24:49.581587
8715 01:24:49.582081 Set Vref, RX VrefLevel [Byte0]: 43
8716 01:24:49.584573 [Byte1]: 43
8717 01:24:49.588874
8718 01:24:49.589461 Set Vref, RX VrefLevel [Byte0]: 44
8719 01:24:49.591822 [Byte1]: 44
8720 01:24:49.596436
8721 01:24:49.596985 Set Vref, RX VrefLevel [Byte0]: 45
8722 01:24:49.599883 [Byte1]: 45
8723 01:24:49.603913
8724 01:24:49.604464 Set Vref, RX VrefLevel [Byte0]: 46
8725 01:24:49.607653 [Byte1]: 46
8726 01:24:49.611726
8727 01:24:49.612281 Set Vref, RX VrefLevel [Byte0]: 47
8728 01:24:49.614618 [Byte1]: 47
8729 01:24:49.618978
8730 01:24:49.619549 Set Vref, RX VrefLevel [Byte0]: 48
8731 01:24:49.621871 [Byte1]: 48
8732 01:24:49.626499
8733 01:24:49.626960 Set Vref, RX VrefLevel [Byte0]: 49
8734 01:24:49.629801 [Byte1]: 49
8735 01:24:49.634016
8736 01:24:49.634504 Set Vref, RX VrefLevel [Byte0]: 50
8737 01:24:49.637771 [Byte1]: 50
8738 01:24:49.641937
8739 01:24:49.642481 Set Vref, RX VrefLevel [Byte0]: 51
8740 01:24:49.644626 [Byte1]: 51
8741 01:24:49.649513
8742 01:24:49.650068 Set Vref, RX VrefLevel [Byte0]: 52
8743 01:24:49.652409 [Byte1]: 52
8744 01:24:49.656841
8745 01:24:49.657437 Set Vref, RX VrefLevel [Byte0]: 53
8746 01:24:49.660457 [Byte1]: 53
8747 01:24:49.664430
8748 01:24:49.664884 Set Vref, RX VrefLevel [Byte0]: 54
8749 01:24:49.667774 [Byte1]: 54
8750 01:24:49.672317
8751 01:24:49.672859 Set Vref, RX VrefLevel [Byte0]: 55
8752 01:24:49.675120 [Byte1]: 55
8753 01:24:49.679459
8754 01:24:49.680007 Set Vref, RX VrefLevel [Byte0]: 56
8755 01:24:49.682980 [Byte1]: 56
8756 01:24:49.687284
8757 01:24:49.687832 Set Vref, RX VrefLevel [Byte0]: 57
8758 01:24:49.690271 [Byte1]: 57
8759 01:24:49.694886
8760 01:24:49.695449 Set Vref, RX VrefLevel [Byte0]: 58
8761 01:24:49.697919 [Byte1]: 58
8762 01:24:49.702196
8763 01:24:49.702640 Set Vref, RX VrefLevel [Byte0]: 59
8764 01:24:49.708877 [Byte1]: 59
8765 01:24:49.709470
8766 01:24:49.712112 Set Vref, RX VrefLevel [Byte0]: 60
8767 01:24:49.715444 [Byte1]: 60
8768 01:24:49.715991
8769 01:24:49.719437 Set Vref, RX VrefLevel [Byte0]: 61
8770 01:24:49.722072 [Byte1]: 61
8771 01:24:49.722524
8772 01:24:49.725526 Set Vref, RX VrefLevel [Byte0]: 62
8773 01:24:49.728874 [Byte1]: 62
8774 01:24:49.732644
8775 01:24:49.733196 Set Vref, RX VrefLevel [Byte0]: 63
8776 01:24:49.735826 [Byte1]: 63
8777 01:24:49.740248
8778 01:24:49.740800 Set Vref, RX VrefLevel [Byte0]: 64
8779 01:24:49.743493 [Byte1]: 64
8780 01:24:49.748563
8781 01:24:49.749148 Set Vref, RX VrefLevel [Byte0]: 65
8782 01:24:49.750960 [Byte1]: 65
8783 01:24:49.755370
8784 01:24:49.755914 Set Vref, RX VrefLevel [Byte0]: 66
8785 01:24:49.758589 [Byte1]: 66
8786 01:24:49.762789
8787 01:24:49.763348 Set Vref, RX VrefLevel [Byte0]: 67
8788 01:24:49.766336 [Byte1]: 67
8789 01:24:49.770204
8790 01:24:49.770700 Set Vref, RX VrefLevel [Byte0]: 68
8791 01:24:49.773593 [Byte1]: 68
8792 01:24:49.777899
8793 01:24:49.778347 Set Vref, RX VrefLevel [Byte0]: 69
8794 01:24:49.781140 [Byte1]: 69
8795 01:24:49.785881
8796 01:24:49.786430 Set Vref, RX VrefLevel [Byte0]: 70
8797 01:24:49.788631 [Byte1]: 70
8798 01:24:49.793400
8799 01:24:49.794078 Set Vref, RX VrefLevel [Byte0]: 71
8800 01:24:49.796530 [Byte1]: 71
8801 01:24:49.800969
8802 01:24:49.801673 Set Vref, RX VrefLevel [Byte0]: 72
8803 01:24:49.803844 [Byte1]: 72
8804 01:24:49.808171
8805 01:24:49.808725 Set Vref, RX VrefLevel [Byte0]: 73
8806 01:24:49.811677 [Byte1]: 73
8807 01:24:49.815985
8808 01:24:49.816526 Set Vref, RX VrefLevel [Byte0]: 74
8809 01:24:49.819101 [Byte1]: 74
8810 01:24:49.823591
8811 01:24:49.824130 Set Vref, RX VrefLevel [Byte0]: 75
8812 01:24:49.826943 [Byte1]: 75
8813 01:24:49.830969
8814 01:24:49.831510 Set Vref, RX VrefLevel [Byte0]: 76
8815 01:24:49.834677 [Byte1]: 76
8816 01:24:49.838688
8817 01:24:49.839229 Set Vref, RX VrefLevel [Byte0]: 77
8818 01:24:49.841934 [Byte1]: 77
8819 01:24:49.846154
8820 01:24:49.846757 Final RX Vref Byte 0 = 53 to rank0
8821 01:24:49.849473 Final RX Vref Byte 1 = 63 to rank0
8822 01:24:49.852442 Final RX Vref Byte 0 = 53 to rank1
8823 01:24:49.855898 Final RX Vref Byte 1 = 63 to rank1==
8824 01:24:49.859298 Dram Type= 6, Freq= 0, CH_1, rank 0
8825 01:24:49.865799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8826 01:24:49.866367 ==
8827 01:24:49.866729 DQS Delay:
8828 01:24:49.868791 DQS0 = 0, DQS1 = 0
8829 01:24:49.869239 DQM Delay:
8830 01:24:49.869697 DQM0 = 135, DQM1 = 129
8831 01:24:49.872213 DQ Delay:
8832 01:24:49.875426 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8833 01:24:49.878798 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =130
8834 01:24:49.882570 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
8835 01:24:49.885999 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =138
8836 01:24:49.886448
8837 01:24:49.886809
8838 01:24:49.887141
8839 01:24:49.888508 [DramC_TX_OE_Calibration] TA2
8840 01:24:49.891980 Original DQ_B0 (3 6) =30, OEN = 27
8841 01:24:49.895620 Original DQ_B1 (3 6) =30, OEN = 27
8842 01:24:49.898595 24, 0x0, End_B0=24 End_B1=24
8843 01:24:49.902116 25, 0x0, End_B0=25 End_B1=25
8844 01:24:49.902575 26, 0x0, End_B0=26 End_B1=26
8845 01:24:49.905422 27, 0x0, End_B0=27 End_B1=27
8846 01:24:49.908814 28, 0x0, End_B0=28 End_B1=28
8847 01:24:49.911948 29, 0x0, End_B0=29 End_B1=29
8848 01:24:49.915085 30, 0x0, End_B0=30 End_B1=30
8849 01:24:49.915546 31, 0x4141, End_B0=30 End_B1=30
8850 01:24:49.918769 Byte0 end_step=30 best_step=27
8851 01:24:49.921924 Byte1 end_step=30 best_step=27
8852 01:24:49.925276 Byte0 TX OE(2T, 0.5T) = (3, 3)
8853 01:24:49.928631 Byte1 TX OE(2T, 0.5T) = (3, 3)
8854 01:24:49.929176
8855 01:24:49.929592
8856 01:24:49.935139 [DQSOSCAuto] RK0, (LSB)MR18= 0x170d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8857 01:24:49.938404 CH1 RK0: MR19=303, MR18=170D
8858 01:24:49.945140 CH1_RK0: MR19=0x303, MR18=0x170D, DQSOSC=398, MR23=63, INC=23, DEC=15
8859 01:24:49.945747
8860 01:24:49.948292 ----->DramcWriteLeveling(PI) begin...
8861 01:24:49.948846 ==
8862 01:24:49.951483 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 01:24:49.954726 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 01:24:49.955182 ==
8865 01:24:49.958228 Write leveling (Byte 0): 24 => 24
8866 01:24:49.961453 Write leveling (Byte 1): 26 => 26
8867 01:24:49.964865 DramcWriteLeveling(PI) end<-----
8868 01:24:49.965449
8869 01:24:49.965811 ==
8870 01:24:49.968109 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 01:24:49.974144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 01:24:49.974599 ==
8873 01:24:49.974958 [Gating] SW mode calibration
8874 01:24:49.984440 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8875 01:24:49.987484 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8876 01:24:49.993730 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8877 01:24:49.997085 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8878 01:24:50.001074 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8879 01:24:50.007144 1 4 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
8880 01:24:50.010684 1 4 16 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
8881 01:24:50.013947 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8882 01:24:50.020591 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8883 01:24:50.023877 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8884 01:24:50.026777 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8885 01:24:50.033959 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8886 01:24:50.036978 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8887 01:24:50.040001 1 5 12 | B1->B0 | 2727 3434 | 0 1 | (1 0) (1 0)
8888 01:24:50.046845 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8889 01:24:50.050496 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8890 01:24:50.053400 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8891 01:24:50.060487 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8892 01:24:50.063231 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8893 01:24:50.066639 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8894 01:24:50.073121 1 6 8 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
8895 01:24:50.076505 1 6 12 | B1->B0 | 4646 2424 | 0 0 | (0 0) (0 0)
8896 01:24:50.079903 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8897 01:24:50.086592 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8898 01:24:50.089725 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8899 01:24:50.093118 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8900 01:24:50.099639 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8901 01:24:50.102510 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8902 01:24:50.106034 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8903 01:24:50.112642 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8904 01:24:50.115911 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8905 01:24:50.119513 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8906 01:24:50.125762 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8907 01:24:50.129473 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8908 01:24:50.132428 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8909 01:24:50.139143 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8910 01:24:50.143016 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8911 01:24:50.145592 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8912 01:24:50.152607 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8913 01:24:50.156264 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8914 01:24:50.158915 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8915 01:24:50.162398 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8916 01:24:50.168898 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8917 01:24:50.172194 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8918 01:24:50.179241 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8919 01:24:50.182649 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8920 01:24:50.185199 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8921 01:24:50.188676 Total UI for P1: 0, mck2ui 16
8922 01:24:50.191723 best dqsien dly found for B0: ( 1, 9, 14)
8923 01:24:50.195163 Total UI for P1: 0, mck2ui 16
8924 01:24:50.198582 best dqsien dly found for B1: ( 1, 9, 10)
8925 01:24:50.202002 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8926 01:24:50.205075 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8927 01:24:50.205674
8928 01:24:50.211731 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8929 01:24:50.215164 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8930 01:24:50.215620 [Gating] SW calibration Done
8931 01:24:50.218188 ==
8932 01:24:50.221879 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 01:24:50.225023 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 01:24:50.225661 ==
8935 01:24:50.226037 RX Vref Scan: 0
8936 01:24:50.226373
8937 01:24:50.227982 RX Vref 0 -> 0, step: 1
8938 01:24:50.228522
8939 01:24:50.231161 RX Delay 0 -> 252, step: 8
8940 01:24:50.235240 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8941 01:24:50.238175 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8942 01:24:50.241528 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8943 01:24:50.247617 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8944 01:24:50.251234 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8945 01:24:50.254598 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8946 01:24:50.257716 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8947 01:24:50.261194 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8948 01:24:50.268157 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8949 01:24:50.271083 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8950 01:24:50.274024 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8951 01:24:50.277911 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8952 01:24:50.284326 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8953 01:24:50.287477 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8954 01:24:50.291353 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8955 01:24:50.294096 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8956 01:24:50.294549 ==
8957 01:24:50.297047 Dram Type= 6, Freq= 0, CH_1, rank 1
8958 01:24:50.304226 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8959 01:24:50.304776 ==
8960 01:24:50.305135 DQS Delay:
8961 01:24:50.305506 DQS0 = 0, DQS1 = 0
8962 01:24:50.307147 DQM Delay:
8963 01:24:50.307597 DQM0 = 136, DQM1 = 130
8964 01:24:50.310462 DQ Delay:
8965 01:24:50.313808 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8966 01:24:50.317133 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8967 01:24:50.320407 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8968 01:24:50.323920 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8969 01:24:50.324461
8970 01:24:50.324815
8971 01:24:50.325143 ==
8972 01:24:50.327106 Dram Type= 6, Freq= 0, CH_1, rank 1
8973 01:24:50.333585 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8974 01:24:50.334131 ==
8975 01:24:50.334490
8976 01:24:50.334824
8977 01:24:50.335142 TX Vref Scan disable
8978 01:24:50.336541 == TX Byte 0 ==
8979 01:24:50.339888 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8980 01:24:50.346838 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8981 01:24:50.347299 == TX Byte 1 ==
8982 01:24:50.349695 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8983 01:24:50.356836 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8984 01:24:50.357443 ==
8985 01:24:50.359564 Dram Type= 6, Freq= 0, CH_1, rank 1
8986 01:24:50.363032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8987 01:24:50.363487 ==
8988 01:24:50.376067
8989 01:24:50.379284 TX Vref early break, caculate TX vref
8990 01:24:50.382560 TX Vref=16, minBit 0, minWin=23, winSum=384
8991 01:24:50.385489 TX Vref=18, minBit 0, minWin=23, winSum=393
8992 01:24:50.388967 TX Vref=20, minBit 1, minWin=24, winSum=401
8993 01:24:50.392183 TX Vref=22, minBit 0, minWin=25, winSum=410
8994 01:24:50.395671 TX Vref=24, minBit 1, minWin=24, winSum=420
8995 01:24:50.401926 TX Vref=26, minBit 0, minWin=25, winSum=423
8996 01:24:50.405249 TX Vref=28, minBit 0, minWin=25, winSum=424
8997 01:24:50.408668 TX Vref=30, minBit 0, minWin=24, winSum=416
8998 01:24:50.412003 TX Vref=32, minBit 0, minWin=24, winSum=411
8999 01:24:50.415359 TX Vref=34, minBit 5, minWin=23, winSum=399
9000 01:24:50.421443 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 28
9001 01:24:50.421857
9002 01:24:50.425119 Final TX Range 0 Vref 28
9003 01:24:50.425597
9004 01:24:50.425927 ==
9005 01:24:50.428531 Dram Type= 6, Freq= 0, CH_1, rank 1
9006 01:24:50.432087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9007 01:24:50.432599 ==
9008 01:24:50.432929
9009 01:24:50.433235
9010 01:24:50.434876 TX Vref Scan disable
9011 01:24:50.441619 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
9012 01:24:50.442032 == TX Byte 0 ==
9013 01:24:50.444976 u2DelayCellOfst[0]=18 cells (5 PI)
9014 01:24:50.447850 u2DelayCellOfst[1]=15 cells (4 PI)
9015 01:24:50.451248 u2DelayCellOfst[2]=0 cells (0 PI)
9016 01:24:50.454573 u2DelayCellOfst[3]=7 cells (2 PI)
9017 01:24:50.457847 u2DelayCellOfst[4]=7 cells (2 PI)
9018 01:24:50.460926 u2DelayCellOfst[5]=22 cells (6 PI)
9019 01:24:50.464189 u2DelayCellOfst[6]=22 cells (6 PI)
9020 01:24:50.467569 u2DelayCellOfst[7]=7 cells (2 PI)
9021 01:24:50.471137 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9022 01:24:50.474057 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9023 01:24:50.477670 == TX Byte 1 ==
9024 01:24:50.481051 u2DelayCellOfst[8]=0 cells (0 PI)
9025 01:24:50.483782 u2DelayCellOfst[9]=3 cells (1 PI)
9026 01:24:50.487419 u2DelayCellOfst[10]=7 cells (2 PI)
9027 01:24:50.487973 u2DelayCellOfst[11]=3 cells (1 PI)
9028 01:24:50.490744 u2DelayCellOfst[12]=15 cells (4 PI)
9029 01:24:50.493792 u2DelayCellOfst[13]=15 cells (4 PI)
9030 01:24:50.497064 u2DelayCellOfst[14]=18 cells (5 PI)
9031 01:24:50.500514 u2DelayCellOfst[15]=15 cells (4 PI)
9032 01:24:50.507254 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9033 01:24:50.510360 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9034 01:24:50.510776 DramC Write-DBI on
9035 01:24:50.513912 ==
9036 01:24:50.514325 Dram Type= 6, Freq= 0, CH_1, rank 1
9037 01:24:50.520726 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9038 01:24:50.521231 ==
9039 01:24:50.521669
9040 01:24:50.521985
9041 01:24:50.523456 TX Vref Scan disable
9042 01:24:50.523866 == TX Byte 0 ==
9043 01:24:50.530040 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9044 01:24:50.530453 == TX Byte 1 ==
9045 01:24:50.533583 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9046 01:24:50.536996 DramC Write-DBI off
9047 01:24:50.537433
9048 01:24:50.537764 [DATLAT]
9049 01:24:50.539954 Freq=1600, CH1 RK1
9050 01:24:50.540367
9051 01:24:50.540693 DATLAT Default: 0xf
9052 01:24:50.542985 0, 0xFFFF, sum = 0
9053 01:24:50.543417 1, 0xFFFF, sum = 0
9054 01:24:50.546407 2, 0xFFFF, sum = 0
9055 01:24:50.546825 3, 0xFFFF, sum = 0
9056 01:24:50.549896 4, 0xFFFF, sum = 0
9057 01:24:50.550315 5, 0xFFFF, sum = 0
9058 01:24:50.553295 6, 0xFFFF, sum = 0
9059 01:24:50.556838 7, 0xFFFF, sum = 0
9060 01:24:50.557383 8, 0xFFFF, sum = 0
9061 01:24:50.559937 9, 0xFFFF, sum = 0
9062 01:24:50.560354 10, 0xFFFF, sum = 0
9063 01:24:50.563249 11, 0xFFFF, sum = 0
9064 01:24:50.563667 12, 0xFFFF, sum = 0
9065 01:24:50.566532 13, 0xFFFF, sum = 0
9066 01:24:50.566949 14, 0x0, sum = 1
9067 01:24:50.569521 15, 0x0, sum = 2
9068 01:24:50.569940 16, 0x0, sum = 3
9069 01:24:50.572855 17, 0x0, sum = 4
9070 01:24:50.573272 best_step = 15
9071 01:24:50.573659
9072 01:24:50.573973 ==
9073 01:24:50.576468 Dram Type= 6, Freq= 0, CH_1, rank 1
9074 01:24:50.579450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9075 01:24:50.582982 ==
9076 01:24:50.583494 RX Vref Scan: 0
9077 01:24:50.583832
9078 01:24:50.585833 RX Vref 0 -> 0, step: 1
9079 01:24:50.586250
9080 01:24:50.589068 RX Delay 11 -> 252, step: 4
9081 01:24:50.592863 iDelay=199, Bit 0, Center 138 (87 ~ 190) 104
9082 01:24:50.596045 iDelay=199, Bit 1, Center 128 (75 ~ 182) 108
9083 01:24:50.599572 iDelay=199, Bit 2, Center 122 (67 ~ 178) 112
9084 01:24:50.605711 iDelay=199, Bit 3, Center 130 (79 ~ 182) 104
9085 01:24:50.608954 iDelay=199, Bit 4, Center 134 (79 ~ 190) 112
9086 01:24:50.612570 iDelay=199, Bit 5, Center 144 (95 ~ 194) 100
9087 01:24:50.615509 iDelay=199, Bit 6, Center 144 (91 ~ 198) 108
9088 01:24:50.618686 iDelay=199, Bit 7, Center 130 (79 ~ 182) 104
9089 01:24:50.625410 iDelay=199, Bit 8, Center 112 (55 ~ 170) 116
9090 01:24:50.628633 iDelay=199, Bit 9, Center 116 (63 ~ 170) 108
9091 01:24:50.632179 iDelay=199, Bit 10, Center 126 (71 ~ 182) 112
9092 01:24:50.635377 iDelay=199, Bit 11, Center 118 (63 ~ 174) 112
9093 01:24:50.641747 iDelay=199, Bit 12, Center 136 (83 ~ 190) 108
9094 01:24:50.645056 iDelay=199, Bit 13, Center 132 (79 ~ 186) 108
9095 01:24:50.648586 iDelay=199, Bit 14, Center 134 (79 ~ 190) 112
9096 01:24:50.651797 iDelay=199, Bit 15, Center 138 (83 ~ 194) 112
9097 01:24:50.652346 ==
9098 01:24:50.654791 Dram Type= 6, Freq= 0, CH_1, rank 1
9099 01:24:50.661905 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9100 01:24:50.662457 ==
9101 01:24:50.662820 DQS Delay:
9102 01:24:50.664985 DQS0 = 0, DQS1 = 0
9103 01:24:50.665590 DQM Delay:
9104 01:24:50.668108 DQM0 = 133, DQM1 = 126
9105 01:24:50.668667 DQ Delay:
9106 01:24:50.671658 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9107 01:24:50.674780 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =130
9108 01:24:50.677785 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =118
9109 01:24:50.681260 DQ12 =136, DQ13 =132, DQ14 =134, DQ15 =138
9110 01:24:50.681872
9111 01:24:50.682240
9112 01:24:50.682579
9113 01:24:50.684590 [DramC_TX_OE_Calibration] TA2
9114 01:24:50.687660 Original DQ_B0 (3 6) =30, OEN = 27
9115 01:24:50.690816 Original DQ_B1 (3 6) =30, OEN = 27
9116 01:24:50.694364 24, 0x0, End_B0=24 End_B1=24
9117 01:24:50.697492 25, 0x0, End_B0=25 End_B1=25
9118 01:24:50.698074 26, 0x0, End_B0=26 End_B1=26
9119 01:24:50.700979 27, 0x0, End_B0=27 End_B1=27
9120 01:24:50.704352 28, 0x0, End_B0=28 End_B1=28
9121 01:24:50.707391 29, 0x0, End_B0=29 End_B1=29
9122 01:24:50.711033 30, 0x0, End_B0=30 End_B1=30
9123 01:24:50.711510 31, 0x4141, End_B0=30 End_B1=30
9124 01:24:50.713908 Byte0 end_step=30 best_step=27
9125 01:24:50.717161 Byte1 end_step=30 best_step=27
9126 01:24:50.720960 Byte0 TX OE(2T, 0.5T) = (3, 3)
9127 01:24:50.724156 Byte1 TX OE(2T, 0.5T) = (3, 3)
9128 01:24:50.724708
9129 01:24:50.725074
9130 01:24:50.731230 [DQSOSCAuto] RK1, (LSB)MR18= 0xb06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
9131 01:24:50.733771 CH1 RK1: MR19=303, MR18=B06
9132 01:24:50.740505 CH1_RK1: MR19=0x303, MR18=0xB06, DQSOSC=404, MR23=63, INC=22, DEC=15
9133 01:24:50.743722 [RxdqsGatingPostProcess] freq 1600
9134 01:24:50.750149 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9135 01:24:50.750618 best DQS0 dly(2T, 0.5T) = (1, 1)
9136 01:24:50.754011 best DQS1 dly(2T, 0.5T) = (1, 1)
9137 01:24:50.756935 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9138 01:24:50.760341 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9139 01:24:50.763224 best DQS0 dly(2T, 0.5T) = (1, 1)
9140 01:24:50.766747 best DQS1 dly(2T, 0.5T) = (1, 1)
9141 01:24:50.770078 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9142 01:24:50.773514 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9143 01:24:50.776972 Pre-setting of DQS Precalculation
9144 01:24:50.779930 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9145 01:24:50.790165 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9146 01:24:50.797001 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9147 01:24:50.797604
9148 01:24:50.798092
9149 01:24:50.799481 [Calibration Summary] 3200 Mbps
9150 01:24:50.799952 CH 0, Rank 0
9151 01:24:50.803589 SW Impedance : PASS
9152 01:24:50.804135 DUTY Scan : NO K
9153 01:24:50.806650 ZQ Calibration : PASS
9154 01:24:50.809781 Jitter Meter : NO K
9155 01:24:50.810239 CBT Training : PASS
9156 01:24:50.813186 Write leveling : PASS
9157 01:24:50.816473 RX DQS gating : PASS
9158 01:24:50.816929 RX DQ/DQS(RDDQC) : PASS
9159 01:24:50.819834 TX DQ/DQS : PASS
9160 01:24:50.823192 RX DATLAT : PASS
9161 01:24:50.823741 RX DQ/DQS(Engine): PASS
9162 01:24:50.826250 TX OE : PASS
9163 01:24:50.826819 All Pass.
9164 01:24:50.827183
9165 01:24:50.829250 CH 0, Rank 1
9166 01:24:50.829737 SW Impedance : PASS
9167 01:24:50.833026 DUTY Scan : NO K
9168 01:24:50.836392 ZQ Calibration : PASS
9169 01:24:50.836938 Jitter Meter : NO K
9170 01:24:50.839605 CBT Training : PASS
9171 01:24:50.842857 Write leveling : PASS
9172 01:24:50.843408 RX DQS gating : PASS
9173 01:24:50.845871 RX DQ/DQS(RDDQC) : PASS
9174 01:24:50.849261 TX DQ/DQS : PASS
9175 01:24:50.849745 RX DATLAT : PASS
9176 01:24:50.852437 RX DQ/DQS(Engine): PASS
9177 01:24:50.855832 TX OE : PASS
9178 01:24:50.856387 All Pass.
9179 01:24:50.856756
9180 01:24:50.857093 CH 1, Rank 0
9181 01:24:50.859097 SW Impedance : PASS
9182 01:24:50.862575 DUTY Scan : NO K
9183 01:24:50.863034 ZQ Calibration : PASS
9184 01:24:50.865612 Jitter Meter : NO K
9185 01:24:50.866071 CBT Training : PASS
9186 01:24:50.868917 Write leveling : PASS
9187 01:24:50.872955 RX DQS gating : PASS
9188 01:24:50.873554 RX DQ/DQS(RDDQC) : PASS
9189 01:24:50.876055 TX DQ/DQS : PASS
9190 01:24:50.878693 RX DATLAT : PASS
9191 01:24:50.879153 RX DQ/DQS(Engine): PASS
9192 01:24:50.882539 TX OE : PASS
9193 01:24:50.883091 All Pass.
9194 01:24:50.883454
9195 01:24:50.886169 CH 1, Rank 1
9196 01:24:50.886716 SW Impedance : PASS
9197 01:24:50.889175 DUTY Scan : NO K
9198 01:24:50.892217 ZQ Calibration : PASS
9199 01:24:50.892765 Jitter Meter : NO K
9200 01:24:50.895662 CBT Training : PASS
9201 01:24:50.898646 Write leveling : PASS
9202 01:24:50.899231 RX DQS gating : PASS
9203 01:24:50.901859 RX DQ/DQS(RDDQC) : PASS
9204 01:24:50.905374 TX DQ/DQS : PASS
9205 01:24:50.905930 RX DATLAT : PASS
9206 01:24:50.908689 RX DQ/DQS(Engine): PASS
9207 01:24:50.911604 TX OE : PASS
9208 01:24:50.912065 All Pass.
9209 01:24:50.912431
9210 01:24:50.915484 DramC Write-DBI on
9211 01:24:50.916051 PER_BANK_REFRESH: Hybrid Mode
9212 01:24:50.918701 TX_TRACKING: ON
9213 01:24:50.928183 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9214 01:24:50.934703 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9215 01:24:50.941112 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9216 01:24:50.944887 [FAST_K] Save calibration result to emmc
9217 01:24:50.948120 sync common calibartion params.
9218 01:24:50.951541 sync cbt_mode0:1, 1:1
9219 01:24:50.952089 dram_init: ddr_geometry: 2
9220 01:24:50.954612 dram_init: ddr_geometry: 2
9221 01:24:50.958056 dram_init: ddr_geometry: 2
9222 01:24:50.961130 0:dram_rank_size:100000000
9223 01:24:50.961802 1:dram_rank_size:100000000
9224 01:24:50.967967 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9225 01:24:50.970842 DFS_SHUFFLE_HW_MODE: ON
9226 01:24:50.974231 dramc_set_vcore_voltage set vcore to 725000
9227 01:24:50.977266 Read voltage for 1600, 0
9228 01:24:50.977833 Vio18 = 0
9229 01:24:50.978224 Vcore = 725000
9230 01:24:50.980907 Vdram = 0
9231 01:24:50.981401 Vddq = 0
9232 01:24:50.981788 Vmddr = 0
9233 01:24:50.984567 switch to 3200 Mbps bootup
9234 01:24:50.985113 [DramcRunTimeConfig]
9235 01:24:50.987287 PHYPLL
9236 01:24:50.987737 DPM_CONTROL_AFTERK: ON
9237 01:24:50.990636 PER_BANK_REFRESH: ON
9238 01:24:50.994272 REFRESH_OVERHEAD_REDUCTION: ON
9239 01:24:50.994822 CMD_PICG_NEW_MODE: OFF
9240 01:24:50.997413 XRTWTW_NEW_MODE: ON
9241 01:24:50.997864 XRTRTR_NEW_MODE: ON
9242 01:24:51.000430 TX_TRACKING: ON
9243 01:24:51.000987 RDSEL_TRACKING: OFF
9244 01:24:51.004106 DQS Precalculation for DVFS: ON
9245 01:24:51.007512 RX_TRACKING: OFF
9246 01:24:51.008138 HW_GATING DBG: ON
9247 01:24:51.010528 ZQCS_ENABLE_LP4: ON
9248 01:24:51.010983 RX_PICG_NEW_MODE: ON
9249 01:24:51.013722 TX_PICG_NEW_MODE: ON
9250 01:24:51.017154 ENABLE_RX_DCM_DPHY: ON
9251 01:24:51.017753 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9252 01:24:51.020617 DUMMY_READ_FOR_TRACKING: OFF
9253 01:24:51.023425 !!! SPM_CONTROL_AFTERK: OFF
9254 01:24:51.027350 !!! SPM could not control APHY
9255 01:24:51.029917 IMPEDANCE_TRACKING: ON
9256 01:24:51.030376 TEMP_SENSOR: ON
9257 01:24:51.033438 HW_SAVE_FOR_SR: OFF
9258 01:24:51.033897 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9259 01:24:51.040706 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9260 01:24:51.041404 Read ODT Tracking: ON
9261 01:24:51.043339 Refresh Rate DeBounce: ON
9262 01:24:51.043888 DFS_NO_QUEUE_FLUSH: ON
9263 01:24:51.046385 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9264 01:24:51.050091 ENABLE_DFS_RUNTIME_MRW: OFF
9265 01:24:51.053378 DDR_RESERVE_NEW_MODE: ON
9266 01:24:51.056669 MR_CBT_SWITCH_FREQ: ON
9267 01:24:51.057130 =========================
9268 01:24:51.076569 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9269 01:24:51.079685 dram_init: ddr_geometry: 2
9270 01:24:51.097739 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9271 01:24:51.100967 dram_init: dram init end (result: 0)
9272 01:24:51.107741 DRAM-K: Full calibration passed in 24651 msecs
9273 01:24:51.110781 MRC: failed to locate region type 0.
9274 01:24:51.111330 DRAM rank0 size:0x100000000,
9275 01:24:51.114476 DRAM rank1 size=0x100000000
9276 01:24:51.123798 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9277 01:24:51.130965 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9278 01:24:51.140415 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9279 01:24:51.147168 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9280 01:24:51.147722 DRAM rank0 size:0x100000000,
9281 01:24:51.150333 DRAM rank1 size=0x100000000
9282 01:24:51.150790 CBMEM:
9283 01:24:51.153914 IMD: root @ 0xfffff000 254 entries.
9284 01:24:51.157319 IMD: root @ 0xffffec00 62 entries.
9285 01:24:51.163619 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9286 01:24:51.166401 WARNING: RO_VPD is uninitialized or empty.
9287 01:24:51.170145 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9288 01:24:51.177882 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9289 01:24:51.190422 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9290 01:24:51.201872 BS: romstage times (exec / console): total (unknown) / 24149 ms
9291 01:24:51.202418
9292 01:24:51.202778
9293 01:24:51.211997 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9294 01:24:51.215061 ARM64: Exception handlers installed.
9295 01:24:51.218298 ARM64: Testing exception
9296 01:24:51.221442 ARM64: Done test exception
9297 01:24:51.221894 Enumerating buses...
9298 01:24:51.224938 Show all devs... Before device enumeration.
9299 01:24:51.229012 Root Device: enabled 1
9300 01:24:51.232131 CPU_CLUSTER: 0: enabled 1
9301 01:24:51.232676 CPU: 00: enabled 1
9302 01:24:51.235389 Compare with tree...
9303 01:24:51.235934 Root Device: enabled 1
9304 01:24:51.237944 CPU_CLUSTER: 0: enabled 1
9305 01:24:51.241557 CPU: 00: enabled 1
9306 01:24:51.242251 Root Device scanning...
9307 01:24:51.244686 scan_static_bus for Root Device
9308 01:24:51.248184 CPU_CLUSTER: 0 enabled
9309 01:24:51.251799 scan_static_bus for Root Device done
9310 01:24:51.254751 scan_bus: bus Root Device finished in 8 msecs
9311 01:24:51.255298 done
9312 01:24:51.261450 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9313 01:24:51.264775 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9314 01:24:51.271167 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9315 01:24:51.274349 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9316 01:24:51.277905 Allocating resources...
9317 01:24:51.281178 Reading resources...
9318 01:24:51.284687 Root Device read_resources bus 0 link: 0
9319 01:24:51.287662 DRAM rank0 size:0x100000000,
9320 01:24:51.288202 DRAM rank1 size=0x100000000
9321 01:24:51.294655 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9322 01:24:51.295235 CPU: 00 missing read_resources
9323 01:24:51.301071 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9324 01:24:51.304729 Root Device read_resources bus 0 link: 0 done
9325 01:24:51.307153 Done reading resources.
9326 01:24:51.311138 Show resources in subtree (Root Device)...After reading.
9327 01:24:51.313844 Root Device child on link 0 CPU_CLUSTER: 0
9328 01:24:51.317132 CPU_CLUSTER: 0 child on link 0 CPU: 00
9329 01:24:51.327099 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9330 01:24:51.327680 CPU: 00
9331 01:24:51.330388 Root Device assign_resources, bus 0 link: 0
9332 01:24:51.334062 CPU_CLUSTER: 0 missing set_resources
9333 01:24:51.340672 Root Device assign_resources, bus 0 link: 0 done
9334 01:24:51.341231 Done setting resources.
9335 01:24:51.346941 Show resources in subtree (Root Device)...After assigning values.
9336 01:24:51.349981 Root Device child on link 0 CPU_CLUSTER: 0
9337 01:24:51.353700 CPU_CLUSTER: 0 child on link 0 CPU: 00
9338 01:24:51.363339 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9339 01:24:51.363879 CPU: 00
9340 01:24:51.366723 Done allocating resources.
9341 01:24:51.373300 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9342 01:24:51.373875 Enabling resources...
9343 01:24:51.376860 done.
9344 01:24:51.379627 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9345 01:24:51.383521 Initializing devices...
9346 01:24:51.384074 Root Device init
9347 01:24:51.387004 init hardware done!
9348 01:24:51.387548 0x00000018: ctrlr->caps
9349 01:24:51.389947 52.000 MHz: ctrlr->f_max
9350 01:24:51.393272 0.400 MHz: ctrlr->f_min
9351 01:24:51.393979 0x40ff8080: ctrlr->voltages
9352 01:24:51.396616 sclk: 390625
9353 01:24:51.397195 Bus Width = 1
9354 01:24:51.399683 sclk: 390625
9355 01:24:51.400132 Bus Width = 1
9356 01:24:51.402970 Early init status = 3
9357 01:24:51.406204 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9358 01:24:51.409761 in-header: 03 fc 00 00 01 00 00 00
9359 01:24:51.412834 in-data: 00
9360 01:24:51.415971 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9361 01:24:51.420273 in-header: 03 fd 00 00 00 00 00 00
9362 01:24:51.423648 in-data:
9363 01:24:51.427174 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9364 01:24:51.430622 in-header: 03 fc 00 00 01 00 00 00
9365 01:24:51.433978 in-data: 00
9366 01:24:51.437180 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9367 01:24:51.441792 in-header: 03 fd 00 00 00 00 00 00
9368 01:24:51.445296 in-data:
9369 01:24:51.448356 [SSUSB] Setting up USB HOST controller...
9370 01:24:51.452043 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9371 01:24:51.455580 [SSUSB] phy power-on done.
9372 01:24:51.458438 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9373 01:24:51.465081 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9374 01:24:51.468164 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9375 01:24:51.474702 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9376 01:24:51.481612 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9377 01:24:51.488442 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9378 01:24:51.495076 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9379 01:24:51.501414 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9380 01:24:51.504483 SPM: binary array size = 0x9dc
9381 01:24:51.508130 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9382 01:24:51.514383 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9383 01:24:51.521061 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9384 01:24:51.527752 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9385 01:24:51.531072 configure_display: Starting display init
9386 01:24:51.565125 anx7625_power_on_init: Init interface.
9387 01:24:51.568758 anx7625_disable_pd_protocol: Disabled PD feature.
9388 01:24:51.571766 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9389 01:24:51.599760 anx7625_start_dp_work: Secure OCM version=00
9390 01:24:51.603091 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9391 01:24:51.617410 sp_tx_get_edid_block: EDID Block = 1
9392 01:24:51.720631 Extracted contents:
9393 01:24:51.724003 header: 00 ff ff ff ff ff ff 00
9394 01:24:51.726447 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9395 01:24:51.730270 version: 01 04
9396 01:24:51.733660 basic params: 95 1f 11 78 0a
9397 01:24:51.737051 chroma info: 76 90 94 55 54 90 27 21 50 54
9398 01:24:51.739723 established: 00 00 00
9399 01:24:51.746922 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9400 01:24:51.753281 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9401 01:24:51.756618 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9402 01:24:51.763075 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9403 01:24:51.769647 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9404 01:24:51.773130 extensions: 00
9405 01:24:51.773729 checksum: fb
9406 01:24:51.774100
9407 01:24:51.779959 Manufacturer: IVO Model 57d Serial Number 0
9408 01:24:51.780535 Made week 0 of 2020
9409 01:24:51.782433 EDID version: 1.4
9410 01:24:51.782883 Digital display
9411 01:24:51.786180 6 bits per primary color channel
9412 01:24:51.789414 DisplayPort interface
9413 01:24:51.789975 Maximum image size: 31 cm x 17 cm
9414 01:24:51.792935 Gamma: 220%
9415 01:24:51.793420 Check DPMS levels
9416 01:24:51.799607 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9417 01:24:51.802675 First detailed timing is preferred timing
9418 01:24:51.805820 Established timings supported:
9419 01:24:51.806341 Standard timings supported:
9420 01:24:51.809259 Detailed timings
9421 01:24:51.813110 Hex of detail: 383680a07038204018303c0035ae10000019
9422 01:24:51.818752 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9423 01:24:51.822289 0780 0798 07c8 0820 hborder 0
9424 01:24:51.825468 0438 043b 0447 0458 vborder 0
9425 01:24:51.828824 -hsync -vsync
9426 01:24:51.829425 Did detailed timing
9427 01:24:51.835564 Hex of detail: 000000000000000000000000000000000000
9428 01:24:51.838423 Manufacturer-specified data, tag 0
9429 01:24:51.841943 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9430 01:24:51.845308 ASCII string: InfoVision
9431 01:24:51.848499 Hex of detail: 000000fe00523134304e574635205248200a
9432 01:24:51.851503 ASCII string: R140NWF5 RH
9433 01:24:51.851965 Checksum
9434 01:24:51.855240 Checksum: 0xfb (valid)
9435 01:24:51.858650 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9436 01:24:51.861945 DSI data_rate: 832800000 bps
9437 01:24:51.868256 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9438 01:24:51.871715 anx7625_parse_edid: pixelclock(138800).
9439 01:24:51.874940 hactive(1920), hsync(48), hfp(24), hbp(88)
9440 01:24:51.878101 vactive(1080), vsync(12), vfp(3), vbp(17)
9441 01:24:51.881494 anx7625_dsi_config: config dsi.
9442 01:24:51.888080 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9443 01:24:51.902552 anx7625_dsi_config: success to config DSI
9444 01:24:51.905493 anx7625_dp_start: MIPI phy setup OK.
9445 01:24:51.908830 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9446 01:24:51.912029 mtk_ddp_mode_set invalid vrefresh 60
9447 01:24:51.915620 main_disp_path_setup
9448 01:24:51.916171 ovl_layer_smi_id_en
9449 01:24:51.918886 ovl_layer_smi_id_en
9450 01:24:51.919341 ccorr_config
9451 01:24:51.919700 aal_config
9452 01:24:51.922125 gamma_config
9453 01:24:51.922576 postmask_config
9454 01:24:51.925582 dither_config
9455 01:24:51.928839 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9456 01:24:51.934826 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9457 01:24:51.938124 Root Device init finished in 551 msecs
9458 01:24:51.941602 CPU_CLUSTER: 0 init
9459 01:24:51.948817 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9460 01:24:51.955043 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9461 01:24:51.955599 APU_MBOX 0x190000b0 = 0x10001
9462 01:24:51.958212 APU_MBOX 0x190001b0 = 0x10001
9463 01:24:51.961597 APU_MBOX 0x190005b0 = 0x10001
9464 01:24:51.964836 APU_MBOX 0x190006b0 = 0x10001
9465 01:24:51.971876 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9466 01:24:51.981455 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9467 01:24:51.993594 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9468 01:24:52.000599 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9469 01:24:52.012579 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9470 01:24:52.021364 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9471 01:24:52.024662 CPU_CLUSTER: 0 init finished in 81 msecs
9472 01:24:52.028186 Devices initialized
9473 01:24:52.031266 Show all devs... After init.
9474 01:24:52.031828 Root Device: enabled 1
9475 01:24:52.033915 CPU_CLUSTER: 0: enabled 1
9476 01:24:52.037735 CPU: 00: enabled 1
9477 01:24:52.041027 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9478 01:24:52.043642 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9479 01:24:52.047389 ELOG: NV offset 0x57f000 size 0x1000
9480 01:24:52.054175 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9481 01:24:52.060722 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9482 01:24:52.064298 ELOG: Event(17) added with size 13 at 2024-04-23 01:24:51 UTC
9483 01:24:52.070924 out: cmd=0x121: 03 db 21 01 00 00 00 00
9484 01:24:52.073849 in-header: 03 84 00 00 2c 00 00 00
9485 01:24:52.083721 in-data: db 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9486 01:24:52.090530 ELOG: Event(A1) added with size 10 at 2024-04-23 01:24:52 UTC
9487 01:24:52.096835 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9488 01:24:52.103990 ELOG: Event(A0) added with size 9 at 2024-04-23 01:24:52 UTC
9489 01:24:52.107230 elog_add_boot_reason: Logged dev mode boot
9490 01:24:52.114242 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9491 01:24:52.114790 Finalize devices...
9492 01:24:52.116818 Devices finalized
9493 01:24:52.119871 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9494 01:24:52.123420 Writing coreboot table at 0xffe64000
9495 01:24:52.127070 0. 000000000010a000-0000000000113fff: RAMSTAGE
9496 01:24:52.133682 1. 0000000040000000-00000000400fffff: RAM
9497 01:24:52.136665 2. 0000000040100000-000000004032afff: RAMSTAGE
9498 01:24:52.139921 3. 000000004032b000-00000000545fffff: RAM
9499 01:24:52.143192 4. 0000000054600000-000000005465ffff: BL31
9500 01:24:52.146544 5. 0000000054660000-00000000ffe63fff: RAM
9501 01:24:52.153124 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9502 01:24:52.156571 7. 0000000100000000-000000023fffffff: RAM
9503 01:24:52.159929 Passing 5 GPIOs to payload:
9504 01:24:52.162811 NAME | PORT | POLARITY | VALUE
9505 01:24:52.169434 EC in RW | 0x000000aa | low | undefined
9506 01:24:52.172771 EC interrupt | 0x00000005 | low | undefined
9507 01:24:52.179047 TPM interrupt | 0x000000ab | high | undefined
9508 01:24:52.182597 SD card detect | 0x00000011 | high | undefined
9509 01:24:52.185550 speaker enable | 0x00000093 | high | undefined
9510 01:24:52.189365 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9511 01:24:52.192360 in-header: 03 f9 00 00 02 00 00 00
9512 01:24:52.195768 in-data: 02 00
9513 01:24:52.199123 ADC[4]: Raw value=903031 ID=7
9514 01:24:52.202958 ADC[3]: Raw value=213652 ID=1
9515 01:24:52.203536 RAM Code: 0x71
9516 01:24:52.205460 ADC[6]: Raw value=75036 ID=0
9517 01:24:52.208884 ADC[5]: Raw value=212912 ID=1
9518 01:24:52.209375 SKU Code: 0x1
9519 01:24:52.216106 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ec0b
9520 01:24:52.216658 coreboot table: 964 bytes.
9521 01:24:52.218849 IMD ROOT 0. 0xfffff000 0x00001000
9522 01:24:52.221934 IMD SMALL 1. 0xffffe000 0x00001000
9523 01:24:52.225859 RO MCACHE 2. 0xffffc000 0x00001104
9524 01:24:52.228848 CONSOLE 3. 0xfff7c000 0x00080000
9525 01:24:52.232249 FMAP 4. 0xfff7b000 0x00000452
9526 01:24:52.235416 TIME STAMP 5. 0xfff7a000 0x00000910
9527 01:24:52.238584 VBOOT WORK 6. 0xfff66000 0x00014000
9528 01:24:52.241706 RAMOOPS 7. 0xffe66000 0x00100000
9529 01:24:52.245261 COREBOOT 8. 0xffe64000 0x00002000
9530 01:24:52.248666 IMD small region:
9531 01:24:52.251861 IMD ROOT 0. 0xffffec00 0x00000400
9532 01:24:52.255373 VPD 1. 0xffffeb80 0x0000006c
9533 01:24:52.258421 MMC STATUS 2. 0xffffeb60 0x00000004
9534 01:24:52.265435 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9535 01:24:52.265940 Probing TPM: done!
9536 01:24:52.272890 Connected to device vid:did:rid of 1ae0:0028:00
9537 01:24:52.279028 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9538 01:24:52.281873 Initialized TPM device CR50 revision 0
9539 01:24:52.285267 Checking cr50 for pending updates
9540 01:24:52.290758 Reading cr50 TPM mode
9541 01:24:52.299536 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9542 01:24:52.306009 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9543 01:24:52.345823 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9544 01:24:52.349693 Checking segment from ROM address 0x40100000
9545 01:24:52.352555 Checking segment from ROM address 0x4010001c
9546 01:24:52.359209 Loading segment from ROM address 0x40100000
9547 01:24:52.359864 code (compression=0)
9548 01:24:52.369305 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9549 01:24:52.375627 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9550 01:24:52.376185 it's not compressed!
9551 01:24:52.382408 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9552 01:24:52.389007 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9553 01:24:52.406224 Loading segment from ROM address 0x4010001c
9554 01:24:52.406791 Entry Point 0x80000000
9555 01:24:52.409692 Loaded segments
9556 01:24:52.412799 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9557 01:24:52.419286 Jumping to boot code at 0x80000000(0xffe64000)
9558 01:24:52.425900 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9559 01:24:52.432682 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9560 01:24:52.441146 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9561 01:24:52.444276 Checking segment from ROM address 0x40100000
9562 01:24:52.447446 Checking segment from ROM address 0x4010001c
9563 01:24:52.454117 Loading segment from ROM address 0x40100000
9564 01:24:52.454569 code (compression=1)
9565 01:24:52.460590 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9566 01:24:52.470385 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9567 01:24:52.470879 using LZMA
9568 01:24:52.479570 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9569 01:24:52.485971 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9570 01:24:52.489590 Loading segment from ROM address 0x4010001c
9571 01:24:52.490140 Entry Point 0x54601000
9572 01:24:52.492669 Loaded segments
9573 01:24:52.495446 NOTICE: MT8192 bl31_setup
9574 01:24:52.502795 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9575 01:24:52.506492 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9576 01:24:52.509095 WARNING: region 0:
9577 01:24:52.512874 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9578 01:24:52.513481 WARNING: region 1:
9579 01:24:52.519030 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9580 01:24:52.522681 WARNING: region 2:
9581 01:24:52.525727 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9582 01:24:52.529176 WARNING: region 3:
9583 01:24:52.535740 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9584 01:24:52.536306 WARNING: region 4:
9585 01:24:52.542059 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9586 01:24:52.542610 WARNING: region 5:
9587 01:24:52.546201 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9588 01:24:52.549025 WARNING: region 6:
9589 01:24:52.552442 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9590 01:24:52.555545 WARNING: region 7:
9591 01:24:52.558888 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9592 01:24:52.565512 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9593 01:24:52.569286 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9594 01:24:52.572238 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9595 01:24:52.578791 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9596 01:24:52.582065 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9597 01:24:52.588867 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9598 01:24:52.592142 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9599 01:24:52.596132 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9600 01:24:52.602044 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9601 01:24:52.605452 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9602 01:24:52.608910 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9603 01:24:52.615396 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9604 01:24:52.618977 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9605 01:24:52.625400 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9606 01:24:52.628845 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9607 01:24:52.632077 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9608 01:24:52.638217 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9609 01:24:52.641887 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9610 01:24:52.648163 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9611 01:24:52.651906 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9612 01:24:52.655692 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9613 01:24:52.661771 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9614 01:24:52.664741 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9615 01:24:52.668577 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9616 01:24:52.675218 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9617 01:24:52.678371 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9618 01:24:52.684842 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9619 01:24:52.688328 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9620 01:24:52.694826 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9621 01:24:52.697916 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9622 01:24:52.701656 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9623 01:24:52.707846 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9624 01:24:52.711249 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9625 01:24:52.715000 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9626 01:24:52.717964 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9627 01:24:52.724786 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9628 01:24:52.728072 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9629 01:24:52.731493 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9630 01:24:52.734780 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9631 01:24:52.741208 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9632 01:24:52.744371 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9633 01:24:52.747768 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9634 01:24:52.751543 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9635 01:24:52.757985 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9636 01:24:52.761114 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9637 01:24:52.764163 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9638 01:24:52.770983 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9639 01:24:52.774343 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9640 01:24:52.778054 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9641 01:24:52.783969 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9642 01:24:52.787712 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9643 01:24:52.793926 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9644 01:24:52.797663 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9645 01:24:52.800929 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9646 01:24:52.807435 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9647 01:24:52.810799 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9648 01:24:52.817642 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9649 01:24:52.820424 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9650 01:24:52.827455 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9651 01:24:52.830599 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9652 01:24:52.837491 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9653 01:24:52.840893 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9654 01:24:52.843932 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9655 01:24:52.850577 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9656 01:24:52.853430 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9657 01:24:52.860458 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9658 01:24:52.864070 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9659 01:24:52.870697 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9660 01:24:52.874000 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9661 01:24:52.880252 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9662 01:24:52.883410 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9663 01:24:52.887108 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9664 01:24:52.893487 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9665 01:24:52.897140 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9666 01:24:52.903357 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9667 01:24:52.906681 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9668 01:24:52.913277 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9669 01:24:52.916734 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9670 01:24:52.923391 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9671 01:24:52.926676 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9672 01:24:52.929806 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9673 01:24:52.936857 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9674 01:24:52.940035 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9675 01:24:52.946589 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9676 01:24:52.949982 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9677 01:24:52.956094 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9678 01:24:52.959992 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9679 01:24:52.966101 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9680 01:24:52.969187 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9681 01:24:52.972737 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9682 01:24:52.979870 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9683 01:24:52.982950 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9684 01:24:52.989516 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9685 01:24:52.992824 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9686 01:24:52.999630 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9687 01:24:53.002871 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9688 01:24:53.005997 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9689 01:24:53.012761 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9690 01:24:53.016084 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9691 01:24:53.018962 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9692 01:24:53.022140 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9693 01:24:53.029100 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9694 01:24:53.032439 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9695 01:24:53.038911 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9696 01:24:53.042008 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9697 01:24:53.045191 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9698 01:24:53.052068 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9699 01:24:53.055857 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9700 01:24:53.062270 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9701 01:24:53.065544 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9702 01:24:53.068349 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9703 01:24:53.075379 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9704 01:24:53.078410 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9705 01:24:53.085359 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9706 01:24:53.088952 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9707 01:24:53.091589 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9708 01:24:53.098187 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9709 01:24:53.102083 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9710 01:24:53.105104 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9711 01:24:53.111777 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9712 01:24:53.115551 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9713 01:24:53.118189 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9714 01:24:53.121883 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9715 01:24:53.128748 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9716 01:24:53.131861 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9717 01:24:53.135002 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9718 01:24:53.141719 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9719 01:24:53.144586 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9720 01:24:53.151336 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9721 01:24:53.155193 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9722 01:24:53.158157 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9723 01:24:53.164590 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9724 01:24:53.167840 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9725 01:24:53.174493 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9726 01:24:53.177672 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9727 01:24:53.181039 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9728 01:24:53.187842 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9729 01:24:53.190919 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9730 01:24:53.197630 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9731 01:24:53.201016 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9732 01:24:53.204002 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9733 01:24:53.211107 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9734 01:24:53.213781 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9735 01:24:53.220488 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9736 01:24:53.223983 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9737 01:24:53.227087 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9738 01:24:53.234146 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9739 01:24:53.236993 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9740 01:24:53.243948 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9741 01:24:53.246731 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9742 01:24:53.250175 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9743 01:24:53.257067 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9744 01:24:53.260137 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9745 01:24:53.267044 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9746 01:24:53.269943 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9747 01:24:53.273381 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9748 01:24:53.280022 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9749 01:24:53.283106 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9750 01:24:53.289824 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9751 01:24:53.292954 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9752 01:24:53.296332 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9753 01:24:53.302929 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9754 01:24:53.305910 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9755 01:24:53.312805 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9756 01:24:53.316514 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9757 01:24:53.319374 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9758 01:24:53.326048 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9759 01:24:53.329436 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9760 01:24:53.335597 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9761 01:24:53.339157 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9762 01:24:53.346033 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9763 01:24:53.349387 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9764 01:24:53.352591 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9765 01:24:53.359061 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9766 01:24:53.362202 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9767 01:24:53.368704 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9768 01:24:53.372099 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9769 01:24:53.375244 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9770 01:24:53.381953 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9771 01:24:53.385069 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9772 01:24:53.388582 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9773 01:24:53.395105 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9774 01:24:53.398381 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9775 01:24:53.404942 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9776 01:24:53.408714 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9777 01:24:53.414751 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9778 01:24:53.418167 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9779 01:24:53.421500 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9780 01:24:53.428449 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9781 01:24:53.431474 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9782 01:24:53.437858 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9783 01:24:53.441498 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9784 01:24:53.447801 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9785 01:24:53.451267 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9786 01:24:53.454404 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9787 01:24:53.461389 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9788 01:24:53.464334 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9789 01:24:53.471395 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9790 01:24:53.474021 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9791 01:24:53.480907 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9792 01:24:53.484107 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9793 01:24:53.487474 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9794 01:24:53.494124 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9795 01:24:53.497464 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9796 01:24:53.503819 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9797 01:24:53.507316 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9798 01:24:53.510688 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9799 01:24:53.516510 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9800 01:24:53.520281 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9801 01:24:53.526987 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9802 01:24:53.530279 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9803 01:24:53.536528 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9804 01:24:53.539973 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9805 01:24:53.546695 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9806 01:24:53.549953 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9807 01:24:53.553382 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9808 01:24:53.559306 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9809 01:24:53.563370 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9810 01:24:53.569448 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9811 01:24:53.572808 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9812 01:24:53.579620 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9813 01:24:53.582751 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9814 01:24:53.585967 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9815 01:24:53.592575 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9816 01:24:53.595770 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9817 01:24:53.602473 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9818 01:24:53.605650 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9819 01:24:53.612453 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9820 01:24:53.615198 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9821 01:24:53.618626 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9822 01:24:53.621886 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9823 01:24:53.628917 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9824 01:24:53.631803 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9825 01:24:53.635048 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9826 01:24:53.639098 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9827 01:24:53.645037 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9828 01:24:53.648488 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9829 01:24:53.654822 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9830 01:24:53.658240 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9831 01:24:53.661926 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9832 01:24:53.667972 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9833 01:24:53.671482 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9834 01:24:53.677812 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9835 01:24:53.680907 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9836 01:24:53.684513 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9837 01:24:53.691056 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9838 01:24:53.694564 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9839 01:24:53.701446 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9840 01:24:53.704301 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9841 01:24:53.707341 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9842 01:24:53.714246 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9843 01:24:53.717190 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9844 01:24:53.720987 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9845 01:24:53.726832 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9846 01:24:53.730029 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9847 01:24:53.737320 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9848 01:24:53.740504 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9849 01:24:53.743493 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9850 01:24:53.750028 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9851 01:24:53.753386 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9852 01:24:53.757070 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9853 01:24:53.763051 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9854 01:24:53.766673 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9855 01:24:53.770182 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9856 01:24:53.776948 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9857 01:24:53.780226 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9858 01:24:53.786147 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9859 01:24:53.789734 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9860 01:24:53.793041 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9861 01:24:53.799373 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9862 01:24:53.802757 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9863 01:24:53.806012 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9864 01:24:53.809489 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9865 01:24:53.812914 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9866 01:24:53.819124 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9867 01:24:53.822248 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9868 01:24:53.825517 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9869 01:24:53.832436 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9870 01:24:53.835376 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9871 01:24:53.838818 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9872 01:24:53.845677 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9873 01:24:53.848442 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9874 01:24:53.851796 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9875 01:24:53.858427 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9876 01:24:53.861490 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9877 01:24:53.868474 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9878 01:24:53.871744 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9879 01:24:53.875193 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9880 01:24:53.881464 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9881 01:24:53.885552 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9882 01:24:53.891508 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9883 01:24:53.894615 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9884 01:24:53.897905 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9885 01:24:53.904672 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9886 01:24:53.907790 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9887 01:24:53.914445 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9888 01:24:53.917918 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9889 01:24:53.921247 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9890 01:24:53.927317 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9891 01:24:53.930923 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9892 01:24:53.937761 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9893 01:24:53.940637 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9894 01:24:53.947566 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9895 01:24:53.950664 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9896 01:24:53.957377 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9897 01:24:53.960262 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9898 01:24:53.964052 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9899 01:24:53.970599 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9900 01:24:53.974075 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9901 01:24:53.980435 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9902 01:24:53.983741 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9903 01:24:53.986771 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9904 01:24:53.993798 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9905 01:24:53.996667 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9906 01:24:54.003537 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9907 01:24:54.006519 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9908 01:24:54.013390 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9909 01:24:54.016302 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9910 01:24:54.020049 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9911 01:24:54.026161 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9912 01:24:54.029728 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9913 01:24:54.036586 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9914 01:24:54.039732 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9915 01:24:54.042679 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9916 01:24:54.049614 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9917 01:24:54.052646 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9918 01:24:54.059483 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9919 01:24:54.062667 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9920 01:24:54.069072 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9921 01:24:54.072461 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9922 01:24:54.075899 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9923 01:24:54.082274 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9924 01:24:54.085302 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9925 01:24:54.092780 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9926 01:24:54.095374 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9927 01:24:54.102101 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9928 01:24:54.105472 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9929 01:24:54.108289 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9930 01:24:54.115173 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9931 01:24:54.118649 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9932 01:24:54.124848 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9933 01:24:54.128297 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9934 01:24:54.134838 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9935 01:24:54.138587 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9936 01:24:54.141721 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9937 01:24:54.148070 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9938 01:24:54.151472 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9939 01:24:54.157834 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9940 01:24:54.160848 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9941 01:24:54.164262 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9942 01:24:54.171089 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9943 01:24:54.174291 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9944 01:24:54.180888 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9945 01:24:54.184207 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9946 01:24:54.190623 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9947 01:24:54.194244 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9948 01:24:54.197024 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9949 01:24:54.204166 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9950 01:24:54.206818 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9951 01:24:54.214150 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9952 01:24:54.216703 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9953 01:24:54.223407 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9954 01:24:54.226796 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9955 01:24:54.233640 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9956 01:24:54.236562 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9957 01:24:54.243318 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9958 01:24:54.246298 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9959 01:24:54.252981 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9960 01:24:54.256334 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9961 01:24:54.259960 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9962 01:24:54.266275 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9963 01:24:54.269711 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9964 01:24:54.276129 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9965 01:24:54.279961 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9966 01:24:54.285720 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9967 01:24:54.289625 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9968 01:24:54.295931 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9969 01:24:54.299325 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9970 01:24:54.302759 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9971 01:24:54.309115 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9972 01:24:54.312731 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9973 01:24:54.318717 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9974 01:24:54.321942 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9975 01:24:54.328623 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9976 01:24:54.331902 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9977 01:24:54.335516 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9978 01:24:54.342128 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9979 01:24:54.345261 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9980 01:24:54.352021 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9981 01:24:54.355011 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9982 01:24:54.361855 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9983 01:24:54.365138 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9984 01:24:54.371211 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9985 01:24:54.374642 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9986 01:24:54.381316 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9987 01:24:54.384964 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9988 01:24:54.387736 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9989 01:24:54.394586 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9990 01:24:54.397577 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9991 01:24:54.404498 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9992 01:24:54.408233 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9993 01:24:54.414599 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9994 01:24:54.417864 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9995 01:24:54.420316 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9996 01:24:54.427326 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9997 01:24:54.430644 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9998 01:24:54.437566 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9999 01:24:54.441033 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
10000 01:24:54.447203 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
10001 01:24:54.450278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
10002 01:24:54.456807 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
10003 01:24:54.460037 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
10004 01:24:54.467296 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
10005 01:24:54.470290 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
10006 01:24:54.476583 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
10007 01:24:54.479907 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
10008 01:24:54.486663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10009 01:24:54.490049 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10010 01:24:54.496807 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10011 01:24:54.499819 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10012 01:24:54.506316 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10013 01:24:54.509733 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10014 01:24:54.516315 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10015 01:24:54.519504 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10016 01:24:54.526390 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10017 01:24:54.529304 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10018 01:24:54.536318 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10019 01:24:54.539563 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10020 01:24:54.546087 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10021 01:24:54.549131 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10022 01:24:54.555743 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10023 01:24:54.559082 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10024 01:24:54.565786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10025 01:24:54.569181 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10026 01:24:54.575409 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10027 01:24:54.575942 INFO: [APUAPC] vio 0
10028 01:24:54.582586 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10029 01:24:54.585895 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10030 01:24:54.588997 INFO: [APUAPC] D0_APC_0: 0x400510
10031 01:24:54.593093 INFO: [APUAPC] D0_APC_1: 0x0
10032 01:24:54.596146 INFO: [APUAPC] D0_APC_2: 0x1540
10033 01:24:54.598926 INFO: [APUAPC] D0_APC_3: 0x0
10034 01:24:54.602538 INFO: [APUAPC] D1_APC_0: 0xffffffff
10035 01:24:54.605627 INFO: [APUAPC] D1_APC_1: 0xffffffff
10036 01:24:54.608965 INFO: [APUAPC] D1_APC_2: 0x3fffff
10037 01:24:54.612260 INFO: [APUAPC] D1_APC_3: 0x0
10038 01:24:54.615437 INFO: [APUAPC] D2_APC_0: 0xffffffff
10039 01:24:54.618733 INFO: [APUAPC] D2_APC_1: 0xffffffff
10040 01:24:54.621807 INFO: [APUAPC] D2_APC_2: 0x3fffff
10041 01:24:54.625288 INFO: [APUAPC] D2_APC_3: 0x0
10042 01:24:54.628736 INFO: [APUAPC] D3_APC_0: 0xffffffff
10043 01:24:54.631674 INFO: [APUAPC] D3_APC_1: 0xffffffff
10044 01:24:54.635016 INFO: [APUAPC] D3_APC_2: 0x3fffff
10045 01:24:54.638183 INFO: [APUAPC] D3_APC_3: 0x0
10046 01:24:54.641825 INFO: [APUAPC] D4_APC_0: 0xffffffff
10047 01:24:54.645199 INFO: [APUAPC] D4_APC_1: 0xffffffff
10048 01:24:54.647995 INFO: [APUAPC] D4_APC_2: 0x3fffff
10049 01:24:54.651304 INFO: [APUAPC] D4_APC_3: 0x0
10050 01:24:54.654670 INFO: [APUAPC] D5_APC_0: 0xffffffff
10051 01:24:54.657871 INFO: [APUAPC] D5_APC_1: 0xffffffff
10052 01:24:54.661369 INFO: [APUAPC] D5_APC_2: 0x3fffff
10053 01:24:54.664483 INFO: [APUAPC] D5_APC_3: 0x0
10054 01:24:54.667876 INFO: [APUAPC] D6_APC_0: 0xffffffff
10055 01:24:54.670852 INFO: [APUAPC] D6_APC_1: 0xffffffff
10056 01:24:54.674281 INFO: [APUAPC] D6_APC_2: 0x3fffff
10057 01:24:54.677486 INFO: [APUAPC] D6_APC_3: 0x0
10058 01:24:54.680990 INFO: [APUAPC] D7_APC_0: 0xffffffff
10059 01:24:54.684021 INFO: [APUAPC] D7_APC_1: 0xffffffff
10060 01:24:54.687472 INFO: [APUAPC] D7_APC_2: 0x3fffff
10061 01:24:54.690822 INFO: [APUAPC] D7_APC_3: 0x0
10062 01:24:54.694508 INFO: [APUAPC] D8_APC_0: 0xffffffff
10063 01:24:54.697453 INFO: [APUAPC] D8_APC_1: 0xffffffff
10064 01:24:54.700951 INFO: [APUAPC] D8_APC_2: 0x3fffff
10065 01:24:54.704196 INFO: [APUAPC] D8_APC_3: 0x0
10066 01:24:54.707148 INFO: [APUAPC] D9_APC_0: 0xffffffff
10067 01:24:54.710737 INFO: [APUAPC] D9_APC_1: 0xffffffff
10068 01:24:54.713525 INFO: [APUAPC] D9_APC_2: 0x3fffff
10069 01:24:54.717087 INFO: [APUAPC] D9_APC_3: 0x0
10070 01:24:54.720575 INFO: [APUAPC] D10_APC_0: 0xffffffff
10071 01:24:54.723567 INFO: [APUAPC] D10_APC_1: 0xffffffff
10072 01:24:54.727064 INFO: [APUAPC] D10_APC_2: 0x3fffff
10073 01:24:54.730049 INFO: [APUAPC] D10_APC_3: 0x0
10074 01:24:54.734197 INFO: [APUAPC] D11_APC_0: 0xffffffff
10075 01:24:54.737174 INFO: [APUAPC] D11_APC_1: 0xffffffff
10076 01:24:54.740445 INFO: [APUAPC] D11_APC_2: 0x3fffff
10077 01:24:54.743584 INFO: [APUAPC] D11_APC_3: 0x0
10078 01:24:54.746691 INFO: [APUAPC] D12_APC_0: 0xffffffff
10079 01:24:54.750044 INFO: [APUAPC] D12_APC_1: 0xffffffff
10080 01:24:54.753702 INFO: [APUAPC] D12_APC_2: 0x3fffff
10081 01:24:54.756659 INFO: [APUAPC] D12_APC_3: 0x0
10082 01:24:54.759860 INFO: [APUAPC] D13_APC_0: 0xffffffff
10083 01:24:54.763669 INFO: [APUAPC] D13_APC_1: 0xffffffff
10084 01:24:54.766596 INFO: [APUAPC] D13_APC_2: 0x3fffff
10085 01:24:54.769705 INFO: [APUAPC] D13_APC_3: 0x0
10086 01:24:54.772767 INFO: [APUAPC] D14_APC_0: 0xffffffff
10087 01:24:54.776266 INFO: [APUAPC] D14_APC_1: 0xffffffff
10088 01:24:54.779402 INFO: [APUAPC] D14_APC_2: 0x3fffff
10089 01:24:54.783618 INFO: [APUAPC] D14_APC_3: 0x0
10090 01:24:54.786101 INFO: [APUAPC] D15_APC_0: 0xffffffff
10091 01:24:54.789657 INFO: [APUAPC] D15_APC_1: 0xffffffff
10092 01:24:54.792957 INFO: [APUAPC] D15_APC_2: 0x3fffff
10093 01:24:54.796026 INFO: [APUAPC] D15_APC_3: 0x0
10094 01:24:54.799212 INFO: [APUAPC] APC_CON: 0x4
10095 01:24:54.802098 INFO: [NOCDAPC] D0_APC_0: 0x0
10096 01:24:54.806067 INFO: [NOCDAPC] D0_APC_1: 0x0
10097 01:24:54.806630 INFO: [NOCDAPC] D1_APC_0: 0x0
10098 01:24:54.809486 INFO: [NOCDAPC] D1_APC_1: 0xfff
10099 01:24:54.812040 INFO: [NOCDAPC] D2_APC_0: 0x0
10100 01:24:54.815726 INFO: [NOCDAPC] D2_APC_1: 0xfff
10101 01:24:54.818707 INFO: [NOCDAPC] D3_APC_0: 0x0
10102 01:24:54.822170 INFO: [NOCDAPC] D3_APC_1: 0xfff
10103 01:24:54.825382 INFO: [NOCDAPC] D4_APC_0: 0x0
10104 01:24:54.828992 INFO: [NOCDAPC] D4_APC_1: 0xfff
10105 01:24:54.832138 INFO: [NOCDAPC] D5_APC_0: 0x0
10106 01:24:54.835642 INFO: [NOCDAPC] D5_APC_1: 0xfff
10107 01:24:54.838759 INFO: [NOCDAPC] D6_APC_0: 0x0
10108 01:24:54.841862 INFO: [NOCDAPC] D6_APC_1: 0xfff
10109 01:24:54.842325 INFO: [NOCDAPC] D7_APC_0: 0x0
10110 01:24:54.845059 INFO: [NOCDAPC] D7_APC_1: 0xfff
10111 01:24:54.848717 INFO: [NOCDAPC] D8_APC_0: 0x0
10112 01:24:54.851521 INFO: [NOCDAPC] D8_APC_1: 0xfff
10113 01:24:54.855288 INFO: [NOCDAPC] D9_APC_0: 0x0
10114 01:24:54.858370 INFO: [NOCDAPC] D9_APC_1: 0xfff
10115 01:24:54.861721 INFO: [NOCDAPC] D10_APC_0: 0x0
10116 01:24:54.865137 INFO: [NOCDAPC] D10_APC_1: 0xfff
10117 01:24:54.868897 INFO: [NOCDAPC] D11_APC_0: 0x0
10118 01:24:54.871324 INFO: [NOCDAPC] D11_APC_1: 0xfff
10119 01:24:54.875030 INFO: [NOCDAPC] D12_APC_0: 0x0
10120 01:24:54.878238 INFO: [NOCDAPC] D12_APC_1: 0xfff
10121 01:24:54.881910 INFO: [NOCDAPC] D13_APC_0: 0x0
10122 01:24:54.884754 INFO: [NOCDAPC] D13_APC_1: 0xfff
10123 01:24:54.888100 INFO: [NOCDAPC] D14_APC_0: 0x0
10124 01:24:54.888563 INFO: [NOCDAPC] D14_APC_1: 0xfff
10125 01:24:54.891297 INFO: [NOCDAPC] D15_APC_0: 0x0
10126 01:24:54.894441 INFO: [NOCDAPC] D15_APC_1: 0xfff
10127 01:24:54.897470 INFO: [NOCDAPC] APC_CON: 0x4
10128 01:24:54.900971 INFO: [APUAPC] set_apusys_apc done
10129 01:24:54.904588 INFO: [DEVAPC] devapc_init done
10130 01:24:54.911131 INFO: GICv3 without legacy support detected.
10131 01:24:54.914232 INFO: ARM GICv3 driver initialized in EL3
10132 01:24:54.917147 INFO: Maximum SPI INTID supported: 639
10133 01:24:54.921088 INFO: BL31: Initializing runtime services
10134 01:24:54.927834 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10135 01:24:54.930712 INFO: SPM: enable CPC mode
10136 01:24:54.933637 INFO: mcdi ready for mcusys-off-idle and system suspend
10137 01:24:54.940519 INFO: BL31: Preparing for EL3 exit to normal world
10138 01:24:54.943613 INFO: Entry point address = 0x80000000
10139 01:24:54.944244 INFO: SPSR = 0x8
10140 01:24:54.950499
10141 01:24:54.950959
10142 01:24:54.951323
10143 01:24:54.953782 Starting depthcharge on Spherion...
10144 01:24:54.954241
10145 01:24:54.954605 Wipe memory regions:
10146 01:24:54.954943
10147 01:24:54.957696 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10148 01:24:54.958227 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10149 01:24:54.958668 Setting prompt string to ['asurada:']
10150 01:24:54.959124 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10151 01:24:54.959831 [0x00000040000000, 0x00000054600000)
10152 01:24:55.079578
10153 01:24:55.080134 [0x00000054660000, 0x00000080000000)
10154 01:24:55.340813
10155 01:24:55.341415 [0x000000821a7280, 0x000000ffe64000)
10156 01:24:56.085505
10157 01:24:56.086063 [0x00000100000000, 0x00000240000000)
10158 01:24:57.975833
10159 01:24:57.978745 Initializing XHCI USB controller at 0x11200000.
10160 01:24:59.016721
10161 01:24:59.020096 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10162 01:24:59.020671
10163 01:24:59.021094
10164 01:24:59.021564
10165 01:24:59.022420 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10167 01:24:59.123847 asurada: tftpboot 192.168.201.1 13468798/tftp-deploy-usmeg6ua/kernel/image.itb 13468798/tftp-deploy-usmeg6ua/kernel/cmdline
10168 01:24:59.124523 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10169 01:24:59.125001 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10170 01:24:59.129593 tftpboot 192.168.201.1 13468798/tftp-deploy-usmeg6ua/kernel/image.itp-deploy-usmeg6ua/kernel/cmdline
10171 01:24:59.130159
10172 01:24:59.130530 Waiting for link
10173 01:24:59.289678
10174 01:24:59.290237 R8152: Initializing
10175 01:24:59.290616
10176 01:24:59.292995 Version 6 (ocp_data = 5c30)
10177 01:24:59.293624
10178 01:24:59.296087 R8152: Done initializing
10179 01:24:59.296568
10180 01:24:59.297018 Adding net device
10181 01:25:01.195850
10182 01:25:01.196405 done.
10183 01:25:01.196779
10184 01:25:01.197125 MAC: 00:e0:4c:68:02:81
10185 01:25:01.197510
10186 01:25:01.198783 Sending DHCP discover... done.
10187 01:25:01.199242
10188 01:25:04.787198 Waiting for reply... done.
10189 01:25:04.787729
10190 01:25:04.788095 Sending DHCP request... done.
10191 01:25:04.789858
10192 01:25:04.794918 Waiting for reply... done.
10193 01:25:04.795436
10194 01:25:04.795769 My ip is 192.168.201.14
10195 01:25:04.796074
10196 01:25:04.798000 The DHCP server ip is 192.168.201.1
10197 01:25:04.798459
10198 01:25:04.804848 TFTP server IP predefined by user: 192.168.201.1
10199 01:25:04.805592
10200 01:25:04.811337 Bootfile predefined by user: 13468798/tftp-deploy-usmeg6ua/kernel/image.itb
10201 01:25:04.811895
10202 01:25:04.814648 Sending tftp read request... done.
10203 01:25:04.815150
10204 01:25:04.821282 Waiting for the transfer...
10205 01:25:04.821741
10206 01:25:05.485723 00000000 ################################################################
10207 01:25:05.486244
10208 01:25:06.153891 00080000 ################################################################
10209 01:25:06.154387
10210 01:25:06.827353 00100000 ################################################################
10211 01:25:06.827857
10212 01:25:07.508880 00180000 ################################################################
10213 01:25:07.509440
10214 01:25:08.174033 00200000 ################################################################
10215 01:25:08.174546
10216 01:25:08.851831 00280000 ################################################################
10217 01:25:08.852374
10218 01:25:09.533416 00300000 ################################################################
10219 01:25:09.533963
10220 01:25:10.208156 00380000 ################################################################
10221 01:25:10.208661
10222 01:25:10.882460 00400000 ################################################################
10223 01:25:10.882986
10224 01:25:11.541528 00480000 ################################################################
10225 01:25:11.542041
10226 01:25:12.220484 00500000 ################################################################
10227 01:25:12.220998
10228 01:25:12.883144 00580000 ################################################################
10229 01:25:12.883655
10230 01:25:13.565511 00600000 ################################################################
10231 01:25:13.566027
10232 01:25:14.242023 00680000 ################################################################
10233 01:25:14.242538
10234 01:25:14.919875 00700000 ################################################################
10235 01:25:14.920377
10236 01:25:15.600066 00780000 ################################################################
10237 01:25:15.600598
10238 01:25:16.279663 00800000 ################################################################
10239 01:25:16.280171
10240 01:25:16.965855 00880000 ################################################################
10241 01:25:16.966352
10242 01:25:17.657298 00900000 ################################################################
10243 01:25:17.657839
10244 01:25:18.337391 00980000 ################################################################
10245 01:25:18.337886
10246 01:25:19.019520 00a00000 ################################################################
10247 01:25:19.020028
10248 01:25:19.699311 00a80000 ################################################################
10249 01:25:19.699823
10250 01:25:20.392018 00b00000 ################################################################
10251 01:25:20.392512
10252 01:25:21.036161 00b80000 ################################################################
10253 01:25:21.036652
10254 01:25:21.718388 00c00000 ################################################################
10255 01:25:21.718952
10256 01:25:22.377930 00c80000 ################################################################
10257 01:25:22.378106
10258 01:25:23.057925 00d00000 ################################################################
10259 01:25:23.058437
10260 01:25:23.731570 00d80000 ################################################################
10261 01:25:23.732095
10262 01:25:24.408511 00e00000 ################################################################
10263 01:25:24.409021
10264 01:25:25.081646 00e80000 ################################################################
10265 01:25:25.082183
10266 01:25:25.754081 00f00000 ################################################################
10267 01:25:25.754650
10268 01:25:26.427460 00f80000 ################################################################
10269 01:25:26.427968
10270 01:25:27.093323 01000000 ################################################################
10271 01:25:27.093964
10272 01:25:27.771056 01080000 ################################################################
10273 01:25:27.771569
10274 01:25:28.440882 01100000 ################################################################
10275 01:25:28.441469
10276 01:25:29.099015 01180000 ################################################################
10277 01:25:29.099575
10278 01:25:29.779125 01200000 ################################################################
10279 01:25:29.779715
10280 01:25:30.460745 01280000 ################################################################
10281 01:25:30.461574
10282 01:25:31.074392 01300000 ################################################################
10283 01:25:31.074540
10284 01:25:31.628793 01380000 ################################################################
10285 01:25:31.628940
10286 01:25:32.180823 01400000 ################################################################
10287 01:25:32.180968
10288 01:25:32.717724 01480000 ################################################################
10289 01:25:32.717872
10290 01:25:33.296098 01500000 ################################################################
10291 01:25:33.296228
10292 01:25:33.897775 01580000 ################################################################
10293 01:25:33.898281
10294 01:25:34.583062 01600000 ################################################################
10295 01:25:34.583556
10296 01:25:35.260876 01680000 ################################################################
10297 01:25:35.261418
10298 01:25:35.945832 01700000 ################################################################
10299 01:25:35.946339
10300 01:25:36.595887 01780000 ################################################################
10301 01:25:36.596391
10302 01:25:37.251396 01800000 ################################################################
10303 01:25:37.251928
10304 01:25:37.932949 01880000 ################################################################
10305 01:25:37.933600
10306 01:25:38.577589 01900000 ################################################################
10307 01:25:38.577783
10308 01:25:39.252262 01980000 ################################################################
10309 01:25:39.252774
10310 01:25:39.926414 01a00000 ################################################################
10311 01:25:39.926925
10312 01:25:40.604504 01a80000 ################################################################
10313 01:25:40.605164
10314 01:25:41.190837 01b00000 ################################################################
10315 01:25:41.190974
10316 01:25:41.797995 01b80000 ################################################################
10317 01:25:41.798161
10318 01:25:42.346512 01c00000 ################################################################
10319 01:25:42.346668
10320 01:25:42.901222 01c80000 ################################################################
10321 01:25:42.901373
10322 01:25:43.445890 01d00000 ################################################################
10323 01:25:43.446030
10324 01:25:44.000454 01d80000 ################################################################
10325 01:25:44.000626
10326 01:25:44.302349 01e00000 ################################### done.
10327 01:25:44.302512
10328 01:25:44.305715 The bootfile was 31739074 bytes long.
10329 01:25:44.305851
10330 01:25:44.309193 Sending tftp read request... done.
10331 01:25:44.309297
10332 01:25:44.309422 Waiting for the transfer...
10333 01:25:44.309510
10334 01:25:44.312346 00000000 # done.
10335 01:25:44.312450
10336 01:25:44.318764 Command line loaded dynamically from TFTP file: 13468798/tftp-deploy-usmeg6ua/kernel/cmdline
10337 01:25:44.318880
10338 01:25:44.341675 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13468798/extract-nfsrootfs-v8wz2pm6,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10339 01:25:44.341824
10340 01:25:44.341890 Loading FIT.
10341 01:25:44.341950
10342 01:25:44.345199 Image ramdisk-1 has 18779757 bytes.
10343 01:25:44.345308
10344 01:25:44.348435 Image fdt-1 has 47230 bytes.
10345 01:25:44.348544
10346 01:25:44.351424 Image kernel-1 has 12910050 bytes.
10347 01:25:44.351526
10348 01:25:44.361744 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10349 01:25:44.361860
10350 01:25:44.378309 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10351 01:25:44.378432
10352 01:25:44.384863 Choosing best match conf-1 for compat google,spherion-rev2.
10353 01:25:44.384967
10354 01:25:44.392197 Connected to device vid:did:rid of 1ae0:0028:00
10355 01:25:44.399500
10356 01:25:44.402425 tpm_get_response: command 0x17b, return code 0x0
10357 01:25:44.402528
10358 01:25:44.405513 ec_init: CrosEC protocol v3 supported (256, 248)
10359 01:25:44.410284
10360 01:25:44.413200 tpm_cleanup: add release locality here.
10361 01:25:44.413303
10362 01:25:44.416793 Shutting down all USB controllers.
10363 01:25:44.416911
10364 01:25:44.417011 Removing current net device
10365 01:25:44.417100
10366 01:25:44.423282 Exiting depthcharge with code 4 at timestamp: 78943295
10367 01:25:44.423387
10368 01:25:44.426611 LZMA decompressing kernel-1 to 0x821a6718
10369 01:25:44.426713
10370 01:25:44.430143 LZMA decompressing kernel-1 to 0x40000000
10371 01:25:46.023960
10372 01:25:46.024109 jumping to kernel
10373 01:25:46.024584 end: 2.2.4 bootloader-commands (duration 00:00:51) [common]
10374 01:25:46.024686 start: 2.2.5 auto-login-action (timeout 00:03:34) [common]
10375 01:25:46.024762 Setting prompt string to ['Linux version [0-9]']
10376 01:25:46.024828 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10377 01:25:46.024897 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10378 01:25:46.106191
10379 01:25:46.109450 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10380 01:25:46.112502 start: 2.2.5.1 login-action (timeout 00:03:34) [common]
10381 01:25:46.112599 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10382 01:25:46.112670 Setting prompt string to []
10383 01:25:46.112746 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10384 01:25:46.112817 Using line separator: #'\n'#
10385 01:25:46.112875 No login prompt set.
10386 01:25:46.112934 Parsing kernel messages
10387 01:25:46.112989 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10388 01:25:46.113092 [login-action] Waiting for messages, (timeout 00:03:34)
10389 01:25:46.113155 Waiting using forced prompt support (timeout 00:01:47)
10390 01:25:46.132377 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j174389-arm64-gcc-10-defconfig-arm64-chromebook-96m9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024
10391 01:25:46.135495 [ 0.000000] random: crng init done
10392 01:25:46.142051 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10393 01:25:46.145534 [ 0.000000] efi: UEFI not found.
10394 01:25:46.151991 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10395 01:25:46.161942 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10396 01:25:46.172106 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10397 01:25:46.178501 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10398 01:25:46.184771 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10399 01:25:46.191352 [ 0.000000] printk: bootconsole [mtk8250] enabled
10400 01:25:46.197876 [ 0.000000] NUMA: No NUMA configuration found
10401 01:25:46.204873 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10402 01:25:46.211293 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10403 01:25:46.211380 [ 0.000000] Zone ranges:
10404 01:25:46.217781 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10405 01:25:46.221190 [ 0.000000] DMA32 empty
10406 01:25:46.227463 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10407 01:25:46.230990 [ 0.000000] Movable zone start for each node
10408 01:25:46.234090 [ 0.000000] Early memory node ranges
10409 01:25:46.240723 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10410 01:25:46.247416 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10411 01:25:46.254055 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10412 01:25:46.260473 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10413 01:25:46.266947 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10414 01:25:46.273516 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10415 01:25:46.330853 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10416 01:25:46.337185 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10417 01:25:46.343829 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10418 01:25:46.347347 [ 0.000000] psci: probing for conduit method from DT.
10419 01:25:46.353360 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10420 01:25:46.356746 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10421 01:25:46.363481 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10422 01:25:46.366942 [ 0.000000] psci: SMC Calling Convention v1.2
10423 01:25:46.373324 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10424 01:25:46.376442 [ 0.000000] Detected VIPT I-cache on CPU0
10425 01:25:46.383311 [ 0.000000] CPU features: detected: GIC system register CPU interface
10426 01:25:46.390061 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10427 01:25:46.396154 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10428 01:25:46.402779 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10429 01:25:46.412701 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10430 01:25:46.419159 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10431 01:25:46.422493 [ 0.000000] alternatives: applying boot alternatives
10432 01:25:46.429827 [ 0.000000] Fallback order for Node 0: 0
10433 01:25:46.436047 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10434 01:25:46.439626 [ 0.000000] Policy zone: Normal
10435 01:25:46.462446 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13468798/extract-nfsrootfs-v8wz2pm6,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10436 01:25:46.472335 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10437 01:25:46.482794 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10438 01:25:46.492397 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10439 01:25:46.498910 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10440 01:25:46.502395 <6>[ 0.000000] software IO TLB: area num 8.
10441 01:25:46.559152 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10442 01:25:46.708456 <6>[ 0.000000] Memory: 7946168K/8385536K available (18048K kernel code, 4118K rwdata, 22292K rodata, 8448K init, 616K bss, 406600K reserved, 32768K cma-reserved)
10443 01:25:46.714916 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10444 01:25:46.721522 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10445 01:25:46.724842 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10446 01:25:46.731137 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10447 01:25:46.737610 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10448 01:25:46.744689 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10449 01:25:46.751160 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10450 01:25:46.757676 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10451 01:25:46.764095 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10452 01:25:46.770470 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10453 01:25:46.774178 <6>[ 0.000000] GICv3: 608 SPIs implemented
10454 01:25:46.777163 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10455 01:25:46.783759 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10456 01:25:46.786723 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10457 01:25:46.793694 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10458 01:25:46.806652 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10459 01:25:46.819870 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10460 01:25:46.826560 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10461 01:25:46.834878 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10462 01:25:46.848169 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10463 01:25:46.854801 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10464 01:25:46.861086 <6>[ 0.009184] Console: colour dummy device 80x25
10465 01:25:46.871421 <6>[ 0.013913] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10466 01:25:46.877919 <6>[ 0.024420] pid_max: default: 32768 minimum: 301
10467 01:25:46.881307 <6>[ 0.029292] LSM: Security Framework initializing
10468 01:25:46.887759 <6>[ 0.034261] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10469 01:25:46.897464 <6>[ 0.042123] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10470 01:25:46.907795 <6>[ 0.051583] cblist_init_generic: Setting adjustable number of callback queues.
10471 01:25:46.914270 <6>[ 0.059072] cblist_init_generic: Setting shift to 3 and lim to 1.
10472 01:25:46.920986 <6>[ 0.065411] cblist_init_generic: Setting adjustable number of callback queues.
10473 01:25:46.927515 <6>[ 0.072838] cblist_init_generic: Setting shift to 3 and lim to 1.
10474 01:25:46.930775 <6>[ 0.079239] rcu: Hierarchical SRCU implementation.
10475 01:25:46.937200 <6>[ 0.084255] rcu: Max phase no-delay instances is 1000.
10476 01:25:46.943978 <6>[ 0.091288] EFI services will not be available.
10477 01:25:46.947088 <6>[ 0.096270] smp: Bringing up secondary CPUs ...
10478 01:25:46.955709 <6>[ 0.101319] Detected VIPT I-cache on CPU1
10479 01:25:46.962474 <6>[ 0.101387] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10480 01:25:46.968978 <6>[ 0.101418] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10481 01:25:46.972084 <6>[ 0.101747] Detected VIPT I-cache on CPU2
10482 01:25:46.982204 <6>[ 0.101794] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10483 01:25:46.988855 <6>[ 0.101810] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10484 01:25:46.991886 <6>[ 0.102067] Detected VIPT I-cache on CPU3
10485 01:25:46.998769 <6>[ 0.102114] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10486 01:25:47.005153 <6>[ 0.102127] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10487 01:25:47.011677 <6>[ 0.102430] CPU features: detected: Spectre-v4
10488 01:25:47.015284 <6>[ 0.102436] CPU features: detected: Spectre-BHB
10489 01:25:47.018382 <6>[ 0.102441] Detected PIPT I-cache on CPU4
10490 01:25:47.024875 <6>[ 0.102498] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10491 01:25:47.034908 <6>[ 0.102515] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10492 01:25:47.037916 <6>[ 0.102808] Detected PIPT I-cache on CPU5
10493 01:25:47.044766 <6>[ 0.102871] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10494 01:25:47.051010 <6>[ 0.102887] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10495 01:25:47.054679 <6>[ 0.103168] Detected PIPT I-cache on CPU6
10496 01:25:47.064156 <6>[ 0.103231] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10497 01:25:47.070778 <6>[ 0.103248] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10498 01:25:47.074029 <6>[ 0.103543] Detected PIPT I-cache on CPU7
10499 01:25:47.080766 <6>[ 0.103608] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10500 01:25:47.086911 <6>[ 0.103624] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10501 01:25:47.094090 <6>[ 0.103671] smp: Brought up 1 node, 8 CPUs
10502 01:25:47.097069 <6>[ 0.244991] SMP: Total of 8 processors activated.
10503 01:25:47.103871 <6>[ 0.249912] CPU features: detected: 32-bit EL0 Support
10504 01:25:47.110389 <6>[ 0.255308] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10505 01:25:47.117007 <6>[ 0.264108] CPU features: detected: Common not Private translations
10506 01:25:47.123368 <6>[ 0.270625] CPU features: detected: CRC32 instructions
10507 01:25:47.130159 <6>[ 0.276010] CPU features: detected: RCpc load-acquire (LDAPR)
10508 01:25:47.136729 <6>[ 0.281970] CPU features: detected: LSE atomic instructions
10509 01:25:47.139527 <6>[ 0.287752] CPU features: detected: Privileged Access Never
10510 01:25:47.146392 <6>[ 0.293532] CPU features: detected: RAS Extension Support
10511 01:25:47.153011 <6>[ 0.299176] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10512 01:25:47.159413 <6>[ 0.306397] CPU: All CPU(s) started at EL2
10513 01:25:47.162559 <6>[ 0.310713] alternatives: applying system-wide alternatives
10514 01:25:47.173413 <6>[ 0.321532] devtmpfs: initialized
10515 01:25:47.189177 <6>[ 0.330452] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10516 01:25:47.195856 <6>[ 0.340414] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10517 01:25:47.202321 <6>[ 0.348640] pinctrl core: initialized pinctrl subsystem
10518 01:25:47.205314 <6>[ 0.355284] DMI not present or invalid.
10519 01:25:47.211961 <6>[ 0.359696] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10520 01:25:47.222076 <6>[ 0.366594] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10521 01:25:47.228506 <6>[ 0.374184] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10522 01:25:47.238554 <6>[ 0.382421] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10523 01:25:47.244762 <6>[ 0.390664] audit: initializing netlink subsys (disabled)
10524 01:25:47.251649 <5>[ 0.396359] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10525 01:25:47.258243 <6>[ 0.397025] thermal_sys: Registered thermal governor 'step_wise'
10526 01:25:47.264465 <6>[ 0.404328] thermal_sys: Registered thermal governor 'power_allocator'
10527 01:25:47.268100 <6>[ 0.410580] cpuidle: using governor menu
10528 01:25:47.274375 <6>[ 0.421538] NET: Registered PF_QIPCRTR protocol family
10529 01:25:47.281092 <6>[ 0.427035] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10530 01:25:47.287756 <6>[ 0.434136] ASID allocator initialised with 32768 entries
10531 01:25:47.290809 <6>[ 0.440702] Serial: AMBA PL011 UART driver
10532 01:25:47.301372 <4>[ 0.449451] Trying to register duplicate clock ID: 134
10533 01:25:47.355819 <6>[ 0.507011] KASLR enabled
10534 01:25:47.370011 <6>[ 0.514703] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10535 01:25:47.376501 <6>[ 0.521715] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10536 01:25:47.383318 <6>[ 0.528202] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10537 01:25:47.390032 <6>[ 0.535211] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10538 01:25:47.396446 <6>[ 0.541697] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10539 01:25:47.402523 <6>[ 0.548701] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10540 01:25:47.409252 <6>[ 0.555187] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10541 01:25:47.415934 <6>[ 0.562190] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10542 01:25:47.422614 <6>[ 0.569709] ACPI: Interpreter disabled.
10543 01:25:47.428771 <6>[ 0.576130] iommu: Default domain type: Translated
10544 01:25:47.435685 <6>[ 0.581243] iommu: DMA domain TLB invalidation policy: strict mode
10545 01:25:47.439142 <5>[ 0.587903] SCSI subsystem initialized
10546 01:25:47.445750 <6>[ 0.592072] usbcore: registered new interface driver usbfs
10547 01:25:47.448973 <6>[ 0.597801] usbcore: registered new interface driver hub
10548 01:25:47.455253 <6>[ 0.603352] usbcore: registered new device driver usb
10549 01:25:47.462077 <6>[ 0.609449] pps_core: LinuxPPS API ver. 1 registered
10550 01:25:47.471759 <6>[ 0.614642] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10551 01:25:47.475362 <6>[ 0.623985] PTP clock support registered
10552 01:25:47.478308 <6>[ 0.628226] EDAC MC: Ver: 3.0.0
10553 01:25:47.486001 <6>[ 0.633385] FPGA manager framework
10554 01:25:47.492178 <6>[ 0.637066] Advanced Linux Sound Architecture Driver Initialized.
10555 01:25:47.495217 <6>[ 0.643840] vgaarb: loaded
10556 01:25:47.501910 <6>[ 0.647011] clocksource: Switched to clocksource arch_sys_counter
10557 01:25:47.504759 <5>[ 0.653456] VFS: Disk quotas dquot_6.6.0
10558 01:25:47.511483 <6>[ 0.657644] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10559 01:25:47.515044 <6>[ 0.664814] pnp: PnP ACPI: disabled
10560 01:25:47.523678 <6>[ 0.671494] NET: Registered PF_INET protocol family
10561 01:25:47.533263 <6>[ 0.677092] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10562 01:25:47.544825 <6>[ 0.689416] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10563 01:25:47.554841 <6>[ 0.698230] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10564 01:25:47.561207 <6>[ 0.706200] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10565 01:25:47.570858 <6>[ 0.714853] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10566 01:25:47.577890 <6>[ 0.724612] TCP: Hash tables configured (established 65536 bind 65536)
10567 01:25:47.584553 <6>[ 0.731478] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10568 01:25:47.594497 <6>[ 0.738674] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10569 01:25:47.600918 <6>[ 0.746374] NET: Registered PF_UNIX/PF_LOCAL protocol family
10570 01:25:47.607383 <6>[ 0.752523] RPC: Registered named UNIX socket transport module.
10571 01:25:47.610893 <6>[ 0.758676] RPC: Registered udp transport module.
10572 01:25:47.617310 <6>[ 0.763609] RPC: Registered tcp transport module.
10573 01:25:47.624049 <6>[ 0.768543] RPC: Registered tcp NFSv4.1 backchannel transport module.
10574 01:25:47.626821 <6>[ 0.775204] PCI: CLS 0 bytes, default 64
10575 01:25:47.630459 <6>[ 0.779531] Unpacking initramfs...
10576 01:25:47.654744 <6>[ 0.799133] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10577 01:25:47.664463 <6>[ 0.807774] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10578 01:25:47.667986 <6>[ 0.816619] kvm [1]: IPA Size Limit: 40 bits
10579 01:25:47.674189 <6>[ 0.821146] kvm [1]: GICv3: no GICV resource entry
10580 01:25:47.677494 <6>[ 0.826169] kvm [1]: disabling GICv2 emulation
10581 01:25:47.684193 <6>[ 0.830857] kvm [1]: GIC system register CPU interface enabled
10582 01:25:47.687701 <6>[ 0.837021] kvm [1]: vgic interrupt IRQ18
10583 01:25:47.694162 <6>[ 0.841370] kvm [1]: VHE mode initialized successfully
10584 01:25:47.700821 <5>[ 0.847865] Initialise system trusted keyrings
10585 01:25:47.707178 <6>[ 0.852691] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10586 01:25:47.715136 <6>[ 0.862675] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10587 01:25:47.721169 <5>[ 0.869067] NFS: Registering the id_resolver key type
10588 01:25:47.724641 <5>[ 0.874370] Key type id_resolver registered
10589 01:25:47.731197 <5>[ 0.878786] Key type id_legacy registered
10590 01:25:47.737642 <6>[ 0.883068] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10591 01:25:47.744218 <6>[ 0.889988] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10592 01:25:47.751186 <6>[ 0.897703] 9p: Installing v9fs 9p2000 file system support
10593 01:25:47.787926 <5>[ 0.936092] Key type asymmetric registered
10594 01:25:47.791240 <5>[ 0.940423] Asymmetric key parser 'x509' registered
10595 01:25:47.801217 <6>[ 0.945567] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10596 01:25:47.804458 <6>[ 0.953182] io scheduler mq-deadline registered
10597 01:25:47.807755 <6>[ 0.957958] io scheduler kyber registered
10598 01:25:47.826900 <6>[ 0.974898] EINJ: ACPI disabled.
10599 01:25:47.859254 <4>[ 1.000535] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10600 01:25:47.868676 <4>[ 1.011180] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10601 01:25:47.883971 <6>[ 1.032066] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10602 01:25:47.892384 <6>[ 1.040143] printk: console [ttyS0] disabled
10603 01:25:47.919811 <6>[ 1.064770] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10604 01:25:47.926554 <6>[ 1.074244] printk: console [ttyS0] enabled
10605 01:25:47.929972 <6>[ 1.074244] printk: console [ttyS0] enabled
10606 01:25:47.936820 <6>[ 1.083137] printk: bootconsole [mtk8250] disabled
10607 01:25:47.939903 <6>[ 1.083137] printk: bootconsole [mtk8250] disabled
10608 01:25:47.946421 <6>[ 1.094302] SuperH (H)SCI(F) driver initialized
10609 01:25:47.950018 <6>[ 1.099599] msm_serial: driver initialized
10610 01:25:47.963898 <6>[ 1.108527] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10611 01:25:47.973868 <6>[ 1.117073] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10612 01:25:47.980346 <6>[ 1.125616] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10613 01:25:47.990453 <6>[ 1.134242] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10614 01:25:47.999978 <6>[ 1.142948] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10615 01:25:48.007208 <6>[ 1.151669] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10616 01:25:48.016523 <6>[ 1.160210] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10617 01:25:48.023134 <6>[ 1.169007] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10618 01:25:48.033084 <6>[ 1.177551] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10619 01:25:48.045157 <6>[ 1.193187] loop: module loaded
10620 01:25:48.051651 <6>[ 1.199129] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10621 01:25:48.074570 <4>[ 1.222480] mtk-pmic-keys: Failed to locate of_node [id: -1]
10622 01:25:48.081295 <6>[ 1.229331] megasas: 07.719.03.00-rc1
10623 01:25:48.091091 <6>[ 1.238895] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10624 01:25:48.098947 <6>[ 1.246413] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10625 01:25:48.114842 <6>[ 1.262921] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10626 01:25:48.175565 <6>[ 1.316739] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10627 01:25:48.426069 <6>[ 1.574095] Freeing initrd memory: 18336K
10628 01:25:48.437277 <6>[ 1.585593] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10629 01:25:48.448479 <6>[ 1.596708] tun: Universal TUN/TAP device driver, 1.6
10630 01:25:48.451999 <6>[ 1.602777] thunder_xcv, ver 1.0
10631 01:25:48.455394 <6>[ 1.606284] thunder_bgx, ver 1.0
10632 01:25:48.458425 <6>[ 1.609783] nicpf, ver 1.0
10633 01:25:48.469352 <6>[ 1.613799] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10634 01:25:48.472423 <6>[ 1.621275] hns3: Copyright (c) 2017 Huawei Corporation.
10635 01:25:48.475764 <6>[ 1.626865] hclge is initializing
10636 01:25:48.482209 <6>[ 1.630446] e1000: Intel(R) PRO/1000 Network Driver
10637 01:25:48.489069 <6>[ 1.635575] e1000: Copyright (c) 1999-2006 Intel Corporation.
10638 01:25:48.492177 <6>[ 1.641590] e1000e: Intel(R) PRO/1000 Network Driver
10639 01:25:48.498883 <6>[ 1.646806] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10640 01:25:48.505577 <6>[ 1.652990] igb: Intel(R) Gigabit Ethernet Network Driver
10641 01:25:48.512253 <6>[ 1.658640] igb: Copyright (c) 2007-2014 Intel Corporation.
10642 01:25:48.518840 <6>[ 1.664477] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10643 01:25:48.525451 <6>[ 1.670995] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10644 01:25:48.529064 <6>[ 1.677460] sky2: driver version 1.30
10645 01:25:48.535074 <6>[ 1.682444] VFIO - User Level meta-driver version: 0.3
10646 01:25:48.542964 <6>[ 1.690663] usbcore: registered new interface driver usb-storage
10647 01:25:48.549484 <6>[ 1.697109] usbcore: registered new device driver onboard-usb-hub
10648 01:25:48.558192 <6>[ 1.706289] mt6397-rtc mt6359-rtc: registered as rtc0
10649 01:25:48.568391 <6>[ 1.711752] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-23T01:25:48 UTC (1713835548)
10650 01:25:48.571989 <6>[ 1.721312] i2c_dev: i2c /dev entries driver
10651 01:25:48.588250 <6>[ 1.733129] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10652 01:25:48.595132 <4>[ 1.741855] cpu cpu0: supply cpu not found, using dummy regulator
10653 01:25:48.601669 <4>[ 1.748286] cpu cpu1: supply cpu not found, using dummy regulator
10654 01:25:48.608398 <4>[ 1.754694] cpu cpu2: supply cpu not found, using dummy regulator
10655 01:25:48.614440 <4>[ 1.761112] cpu cpu3: supply cpu not found, using dummy regulator
10656 01:25:48.621254 <4>[ 1.767510] cpu cpu4: supply cpu not found, using dummy regulator
10657 01:25:48.627819 <4>[ 1.773909] cpu cpu5: supply cpu not found, using dummy regulator
10658 01:25:48.634561 <4>[ 1.780307] cpu cpu6: supply cpu not found, using dummy regulator
10659 01:25:48.641297 <4>[ 1.786704] cpu cpu7: supply cpu not found, using dummy regulator
10660 01:25:48.660737 <6>[ 1.808357] cpu cpu0: EM: created perf domain
10661 01:25:48.663419 <6>[ 1.813304] cpu cpu4: EM: created perf domain
10662 01:25:48.671231 <6>[ 1.818941] sdhci: Secure Digital Host Controller Interface driver
10663 01:25:48.677552 <6>[ 1.825373] sdhci: Copyright(c) Pierre Ossman
10664 01:25:48.684210 <6>[ 1.830331] Synopsys Designware Multimedia Card Interface Driver
10665 01:25:48.690726 <6>[ 1.836972] sdhci-pltfm: SDHCI platform and OF driver helper
10666 01:25:48.693857 <6>[ 1.837018] mmc0: CQHCI version 5.10
10667 01:25:48.700526 <6>[ 1.847222] ledtrig-cpu: registered to indicate activity on CPUs
10668 01:25:48.707121 <6>[ 1.854352] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10669 01:25:48.713799 <6>[ 1.861414] usbcore: registered new interface driver usbhid
10670 01:25:48.717388 <6>[ 1.867239] usbhid: USB HID core driver
10671 01:25:48.724445 <6>[ 1.871404] spi_master spi0: will run message pump with realtime priority
10672 01:25:48.766304 <6>[ 1.907999] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10673 01:25:48.784992 <6>[ 1.922918] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10674 01:25:48.792143 <6>[ 1.937934] cros-ec-spi spi0.0: Chrome EC device registered
10675 01:25:48.795296 <6>[ 1.944047] mmc0: Command Queue Engine enabled
10676 01:25:48.801944 <6>[ 1.948808] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10677 01:25:48.808440 <6>[ 1.956492] mmcblk0: mmc0:0001 DA4128 116 GiB
10678 01:25:48.818838 <6>[ 1.966659] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10679 01:25:48.825999 <6>[ 1.973867] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10680 01:25:48.835687 <6>[ 1.978810] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10681 01:25:48.839494 <6>[ 1.979831] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10682 01:25:48.845983 <6>[ 1.989751] NET: Registered PF_PACKET protocol family
10683 01:25:48.852137 <6>[ 1.994325] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10684 01:25:48.855845 <6>[ 1.999036] 9pnet: Installing 9P2000 support
10685 01:25:48.862353 <5>[ 2.010014] Key type dns_resolver registered
10686 01:25:48.865586 <6>[ 2.014991] registered taskstats version 1
10687 01:25:48.872177 <5>[ 2.019383] Loading compiled-in X.509 certificates
10688 01:25:48.901539 <4>[ 2.042954] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10689 01:25:48.911785 <4>[ 2.053793] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10690 01:25:48.918259 <3>[ 2.064371] debugfs: File 'uA_load' in directory '/' already present!
10691 01:25:48.924405 <3>[ 2.071157] debugfs: File 'min_uV' in directory '/' already present!
10692 01:25:48.931113 <3>[ 2.077785] debugfs: File 'max_uV' in directory '/' already present!
10693 01:25:48.937770 <3>[ 2.084412] debugfs: File 'constraint_flags' in directory '/' already present!
10694 01:25:48.949625 <3>[ 2.094438] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10695 01:25:48.959248 <6>[ 2.106964] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10696 01:25:48.965835 <6>[ 2.113793] xhci-mtk 11200000.usb: xHCI Host Controller
10697 01:25:48.972610 <6>[ 2.119298] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10698 01:25:48.982370 <6>[ 2.127147] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10699 01:25:48.989121 <6>[ 2.136569] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10700 01:25:48.995755 <6>[ 2.142656] xhci-mtk 11200000.usb: xHCI Host Controller
10701 01:25:49.002365 <6>[ 2.148133] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10702 01:25:49.009286 <6>[ 2.155780] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10703 01:25:49.015794 <6>[ 2.163442] hub 1-0:1.0: USB hub found
10704 01:25:49.019061 <6>[ 2.167454] hub 1-0:1.0: 1 port detected
10705 01:25:49.025719 <6>[ 2.171721] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10706 01:25:49.032213 <6>[ 2.180261] hub 2-0:1.0: USB hub found
10707 01:25:49.035744 <6>[ 2.184267] hub 2-0:1.0: 1 port detected
10708 01:25:49.044066 <6>[ 2.192167] mtk-msdc 11f70000.mmc: Got CD GPIO
10709 01:25:49.056085 <6>[ 2.201143] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10710 01:25:49.063435 <6>[ 2.209175] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10711 01:25:49.072888 <4>[ 2.217100] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10712 01:25:49.082744 <6>[ 2.226623] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10713 01:25:49.089434 <6>[ 2.234700] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10714 01:25:49.099075 <6>[ 2.242785] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10715 01:25:49.105660 <6>[ 2.250717] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10716 01:25:49.112551 <6>[ 2.258591] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10717 01:25:49.122195 <6>[ 2.266412] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10718 01:25:49.132116 <6>[ 2.277063] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10719 01:25:49.142279 <6>[ 2.285421] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10720 01:25:49.148711 <6>[ 2.293791] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10721 01:25:49.158745 <6>[ 2.302131] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10722 01:25:49.165363 <6>[ 2.310480] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10723 01:25:49.175615 <6>[ 2.318819] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10724 01:25:49.181832 <6>[ 2.327168] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10725 01:25:49.191476 <6>[ 2.335507] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10726 01:25:49.198365 <6>[ 2.343857] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10727 01:25:49.208317 <6>[ 2.352194] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10728 01:25:49.214646 <6>[ 2.360541] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10729 01:25:49.224426 <6>[ 2.368879] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10730 01:25:49.231357 <6>[ 2.377216] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10731 01:25:49.241289 <6>[ 2.385554] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10732 01:25:49.247804 <6>[ 2.393892] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10733 01:25:49.254419 <6>[ 2.402678] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10734 01:25:49.261663 <6>[ 2.409890] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10735 01:25:49.268663 <6>[ 2.416666] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10736 01:25:49.278939 <6>[ 2.423447] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10737 01:25:49.285406 <6>[ 2.430371] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10738 01:25:49.292072 <6>[ 2.437211] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10739 01:25:49.301656 <6>[ 2.446342] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10740 01:25:49.311393 <6>[ 2.455461] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10741 01:25:49.321547 <6>[ 2.464755] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10742 01:25:49.331643 <6>[ 2.474245] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10743 01:25:49.338177 <6>[ 2.483722] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10744 01:25:49.348256 <6>[ 2.492843] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10745 01:25:49.358157 <6>[ 2.502311] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10746 01:25:49.367768 <6>[ 2.511430] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10747 01:25:49.377621 <6>[ 2.520724] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10748 01:25:49.387751 <6>[ 2.530884] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10749 01:25:49.397677 <6>[ 2.542398] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10750 01:25:49.404265 <6>[ 2.552052] Trying to probe devices needed for running init ...
10751 01:25:49.426861 <6>[ 2.571498] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10752 01:25:49.454871 <6>[ 2.602821] hub 2-1:1.0: USB hub found
10753 01:25:49.457843 <6>[ 2.607302] hub 2-1:1.0: 3 ports detected
10754 01:25:49.466500 <6>[ 2.614485] hub 2-1:1.0: USB hub found
10755 01:25:49.469569 <6>[ 2.618874] hub 2-1:1.0: 3 ports detected
10756 01:25:49.578396 <6>[ 2.723222] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10757 01:25:49.733156 <6>[ 2.881273] hub 1-1:1.0: USB hub found
10758 01:25:49.736210 <6>[ 2.885760] hub 1-1:1.0: 4 ports detected
10759 01:25:49.746066 <6>[ 2.894045] hub 1-1:1.0: USB hub found
10760 01:25:49.749068 <6>[ 2.898400] hub 1-1:1.0: 4 ports detected
10761 01:25:49.810162 <6>[ 2.955346] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10762 01:25:50.070583 <6>[ 3.215330] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10763 01:25:50.202950 <6>[ 3.351153] hub 1-1.4:1.0: USB hub found
10764 01:25:50.205965 <6>[ 3.355815] hub 1-1.4:1.0: 2 ports detected
10765 01:25:50.216045 <6>[ 3.364153] hub 1-1.4:1.0: USB hub found
10766 01:25:50.219245 <6>[ 3.368760] hub 1-1.4:1.0: 2 ports detected
10767 01:25:50.518462 <6>[ 3.663305] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10768 01:25:50.710206 <6>[ 3.855304] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10769 01:26:01.679381 <6>[ 14.832334] ALSA device list:
10770 01:26:01.686343 <6>[ 14.835625] No soundcards found.
10771 01:26:01.694269 <6>[ 14.843588] Freeing unused kernel memory: 8448K
10772 01:26:01.697397 <6>[ 14.849150] Run /init as init process
10773 01:26:01.709932 Loading, please wait...
10774 01:26:01.740336 Starting systemd-udevd version 252.22-1~deb12u1
10775 01:26:01.740468
10776 01:26:01.970034 <6>[ 15.116146] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10777 01:26:01.983986 <6>[ 15.130305] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10778 01:26:01.987148 <6>[ 15.130558] remoteproc remoteproc0: scp is available
10779 01:26:01.997552 <6>[ 15.141584] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10780 01:26:02.003753 <6>[ 15.144892] remoteproc remoteproc0: powering up scp
10781 01:26:02.010693 <6>[ 15.152522] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10782 01:26:02.020791 <6>[ 15.157209] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10783 01:26:02.023697 <6>[ 15.157243] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10784 01:26:02.038334 <3>[ 15.184693] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10785 01:26:02.048349 <3>[ 15.193417] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10786 01:26:02.055152 <6>[ 15.193882] usbcore: registered new device driver r8152-cfgselector
10787 01:26:02.061371 <4>[ 15.194419] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10788 01:26:02.068061 <4>[ 15.195372] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10789 01:26:02.071347 <6>[ 15.200975] mc: Linux media interface: v0.10
10790 01:26:02.081278 <3>[ 15.201552] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10791 01:26:02.087882 <6>[ 15.227842] videodev: Linux video capture interface: v2.00
10792 01:26:02.094565 <3>[ 15.238998] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10793 01:26:02.101157 <6>[ 15.240411] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10794 01:26:02.111302 <3>[ 15.257417] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10795 01:26:02.118128 <3>[ 15.265541] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10796 01:26:02.127986 <4>[ 15.267431] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10797 01:26:02.134544 <4>[ 15.267431] Fallback method does not support PEC.
10798 01:26:02.140779 <3>[ 15.273745] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10799 01:26:02.147691 <6>[ 15.284391] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10800 01:26:02.154607 <6>[ 15.284403] pci_bus 0000:00: root bus resource [bus 00-ff]
10801 01:26:02.161219 <6>[ 15.284414] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10802 01:26:02.171156 <6>[ 15.284421] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10803 01:26:02.178011 <6>[ 15.284453] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10804 01:26:02.184502 <6>[ 15.284474] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10805 01:26:02.188288 <6>[ 15.284553] pci 0000:00:00.0: supports D1 D2
10806 01:26:02.194403 <6>[ 15.284557] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10807 01:26:02.204555 <6>[ 15.286115] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10808 01:26:02.210771 <6>[ 15.286245] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10809 01:26:02.217670 <6>[ 15.286277] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10810 01:26:02.224864 <6>[ 15.286299] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10811 01:26:02.231095 <6>[ 15.286317] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10812 01:26:02.238064 <6>[ 15.286436] pci 0000:01:00.0: supports D1 D2
10813 01:26:02.244670 <6>[ 15.286440] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10814 01:26:02.251022 <6>[ 15.299079] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10815 01:26:02.257838 <3>[ 15.302286] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10816 01:26:02.267765 <3>[ 15.302328] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10817 01:26:02.274276 <6>[ 15.308122] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10818 01:26:02.284137 <6>[ 15.308190] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10819 01:26:02.290431 <6>[ 15.308196] remoteproc remoteproc0: remote processor scp is now up
10820 01:26:02.297284 <6>[ 15.311159] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10821 01:26:02.304087 <6>[ 15.311165] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10822 01:26:02.313312 <6>[ 15.311173] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10823 01:26:02.319995 <6>[ 15.311185] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10824 01:26:02.329924 <6>[ 15.311198] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10825 01:26:02.333142 <6>[ 15.311210] pci 0000:00:00.0: PCI bridge to [bus 01]
10826 01:26:02.342900 <6>[ 15.311215] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10827 01:26:02.350023 <6>[ 15.311336] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10828 01:26:02.356749 <6>[ 15.311838] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10829 01:26:02.359859 <6>[ 15.312419] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10830 01:26:02.369848 <3>[ 15.315202] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10831 01:26:02.376068 <3>[ 15.326726] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10832 01:26:02.385975 <6>[ 15.327304] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10833 01:26:02.395781 <6>[ 15.327947] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10834 01:26:02.405925 <6>[ 15.328268] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10835 01:26:02.416003 <6>[ 15.328554] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10836 01:26:02.422446 <3>[ 15.331328] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10837 01:26:02.432206 <3>[ 15.331337] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10838 01:26:02.438747 <3>[ 15.331462] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10839 01:26:02.445296 <6>[ 15.342560] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10840 01:26:02.455531 <3>[ 15.343381] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10841 01:26:02.461985 <5>[ 15.351388] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10842 01:26:02.471934 <6>[ 15.353364] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10843 01:26:02.481803 <4>[ 15.354782] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10844 01:26:02.488106 <4>[ 15.354791] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10845 01:26:02.494843 <3>[ 15.358505] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10846 01:26:02.504977 <3>[ 15.358515] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10847 01:26:02.511197 <3>[ 15.358520] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10848 01:26:02.521137 <3>[ 15.358544] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10849 01:26:02.524260 <6>[ 15.359265] Bluetooth: Core ver 2.22
10850 01:26:02.530903 <6>[ 15.373546] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10851 01:26:02.537412 <6>[ 15.380030] NET: Registered PF_BLUETOOTH protocol family
10852 01:26:02.547343 <3>[ 15.380518] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10853 01:26:02.553888 <5>[ 15.385006] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10854 01:26:02.560690 <5>[ 15.385291] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10855 01:26:02.570344 <4>[ 15.385344] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10856 01:26:02.573982 <6>[ 15.385349] cfg80211: failed to load regulatory.db
10857 01:26:02.586660 <6>[ 15.389952] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10858 01:26:02.593590 <6>[ 15.390184] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10859 01:26:02.600495 <6>[ 15.391837] Bluetooth: HCI device and connection manager initialized
10860 01:26:02.606751 <6>[ 15.391856] Bluetooth: HCI socket layer initialized
10861 01:26:02.609696 <6>[ 15.398990] usbcore: registered new interface driver uvcvideo
10862 01:26:02.616538 <6>[ 15.405594] Bluetooth: L2CAP socket layer initialized
10863 01:26:02.623477 <6>[ 15.405608] Bluetooth: SCO socket layer initialized
10864 01:26:02.626513 <6>[ 15.415133] r8152 2-1.3:1.0 eth0: v1.12.13
10865 01:26:02.633219 <6>[ 15.471350] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10866 01:26:02.639602 <6>[ 15.476083] usbcore: registered new interface driver r8152
10867 01:26:02.645980 <6>[ 15.476389] usbcore: registered new interface driver btusb
10868 01:26:02.656305 <4>[ 15.477704] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10869 01:26:02.662988 <3>[ 15.477718] Bluetooth: hci0: Failed to load firmware file (-2)
10870 01:26:02.665815 <3>[ 15.477722] Bluetooth: hci0: Failed to set up firmware (-2)
10871 01:26:02.679197 <4>[ 15.477726] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10872 01:26:02.685465 <6>[ 15.483972] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10873 01:26:02.689069 <6>[ 15.503712] usbcore: registered new interface driver cdc_ether
10874 01:26:02.695744 <6>[ 15.527124] mt7921e 0000:01:00.0: ASIC revision: 79610010
10875 01:26:02.701884 <6>[ 15.540855] usbcore: registered new interface driver r8153_ecm
10876 01:26:02.708623 <6>[ 15.645901] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10877 01:26:02.711817 <6>[ 15.645901]
10878 01:26:02.718720 <6>[ 15.660894] r8152 2-1.3:1.0 enx00e04c680281: renamed from eth0
10879 01:26:02.777227 <6>[ 15.923674] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10880 01:26:02.780534 Begin: Loading essential drivers ... done.
10881 01:26:02.787189 Begin: Running /scripts/init-premount ... done.
10882 01:26:02.794326 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10883 01:26:02.800473 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10884 01:26:02.807315 Device /sys/class/net/enx00e04c680281 found
10885 01:26:02.807397 done.
10886 01:26:02.813468 Begin: Waiting up to 180 secs for any network device to become available ... done.
10887 01:26:02.885139 IP-Config: enx00e04c680281 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10888 01:26:03.641322 <6>[ 16.791262] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10889 01:26:03.832604 <6>[ 16.982395] r8152 2-1.3:1.0 enx00e04c680281: carrier on
10890 01:26:04.061939 IP-Config: no response after 2 secs - giving up
10891 01:26:04.101378 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:47 mtu 1500 DHCP
10892 01:26:04.808962 IP-Config: enx00e04c680281 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10893 01:26:04.811952 IP-Config: enx00e04c680281 complete (dhcp from 192.168.201.1):
10894 01:26:04.818652 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10895 01:26:04.828684 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10896 01:26:04.835387 host : mt8192-asurada-spherion-r0-cbg-9
10897 01:26:04.842072 domain : lava-rack
10898 01:26:04.845166 rootserver: 192.168.201.1 rootpath:
10899 01:26:04.845242 filename :
10900 01:26:04.956873 done.
10901 01:26:04.964197 Begin: Running /scripts/nfs-bottom ... done.
10902 01:26:04.977008 Begin: Running /scripts/init-bottom ... done.
10903 01:26:06.353790 <6>[ 19.504088] NET: Registered PF_INET6 protocol family
10904 01:26:06.361788 <6>[ 19.511748] Segment Routing with IPv6
10905 01:26:06.364682 <6>[ 19.515726] In-situ OAM (IOAM) with IPv6
10906 01:26:06.567494 <30>[ 19.688188] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10907 01:26:06.571147 <30>[ 19.721292] systemd[1]: Detected architecture arm64.
10908 01:26:06.579865
10909 01:26:06.583033 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10910 01:26:06.583112
10911 01:26:06.583175
10912 01:26:06.610830 <30>[ 19.760979] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10913 01:26:07.754119 <30>[ 20.900852] systemd[1]: Queued start job for default target graphical.target.
10914 01:26:07.793615 <30>[ 20.940432] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10915 01:26:07.800316 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10916 01:26:07.800418
10917 01:26:07.822248 <30>[ 20.969163] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10918 01:26:07.831899 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10919 01:26:07.831992
10920 01:26:07.849812 <30>[ 20.997068] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10921 01:26:07.859765 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10922 01:26:07.859883
10923 01:26:07.878877 <30>[ 21.025488] systemd[1]: Created slice user.slice - User and Session Slice.
10924 01:26:07.885212 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10925 01:26:07.885306
10926 01:26:07.908382 <30>[ 21.052180] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10927 01:26:07.918112 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10928 01:26:07.918200
10929 01:26:07.936123 <30>[ 21.079550] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10930 01:26:07.942334 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10931 01:26:07.942422
10932 01:26:07.971165 <30>[ 21.107966] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10933 01:26:07.980996 <30>[ 21.127869] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10934 01:26:07.987672 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10935 01:26:07.987758
10936 01:26:08.004920 <30>[ 21.151698] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10937 01:26:08.014824 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10938 01:26:08.014932
10939 01:26:08.032868 <30>[ 21.179821] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10940 01:26:08.042609 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10941 01:26:08.042695
10942 01:26:08.057547 <30>[ 21.207753] systemd[1]: Reached target paths.target - Path Units.
10943 01:26:08.064344 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10944 01:26:08.067773
10945 01:26:08.084223 <30>[ 21.231341] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10946 01:26:08.090894 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10947 01:26:08.090976
10948 01:26:08.105299 <30>[ 21.255305] systemd[1]: Reached target slices.target - Slice Units.
10949 01:26:08.115072 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10950 01:26:08.115171
10951 01:26:08.129881 <30>[ 21.279785] systemd[1]: Reached target swap.target - Swaps.
10952 01:26:08.136409 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10953 01:26:08.136491
10954 01:26:08.156805 <30>[ 21.303743] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10955 01:26:08.166846 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10956 01:26:08.166930
10957 01:26:08.184913 <30>[ 21.331781] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10958 01:26:08.194663 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10959 01:26:08.194755
10960 01:26:08.215900 <30>[ 21.362769] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10961 01:26:08.225667 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10962 01:26:08.225760
10963 01:26:08.241579 <30>[ 21.388729] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10964 01:26:08.251236 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10965 01:26:08.251324
10966 01:26:08.269028 <30>[ 21.415942] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10967 01:26:08.275984 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10968 01:26:08.276070
10969 01:26:08.293643 <30>[ 21.440929] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10970 01:26:08.303822 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10971 01:26:08.303911
10972 01:26:08.323380 <30>[ 21.470342] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10973 01:26:08.333431 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10974 01:26:08.333519
10975 01:26:08.348717 <30>[ 21.495792] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10976 01:26:08.358555 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10977 01:26:08.358676
10978 01:26:08.408988 <30>[ 21.555769] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10979 01:26:08.415061 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10980 01:26:08.415171
10981 01:26:08.428020 <30>[ 21.574802] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10982 01:26:08.434361 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10983 01:26:08.434447
10984 01:26:08.456000 <30>[ 21.602648] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10985 01:26:08.462082 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10986 01:26:08.462164
10987 01:26:08.487372 <30>[ 21.627806] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10988 01:26:08.502430 <30>[ 21.649417] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10989 01:26:08.512487 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10990 01:26:08.512574
10991 01:26:08.534011 <30>[ 21.681179] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10992 01:26:08.540430 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10993 01:26:08.540516
10994 01:26:08.566310 <30>[ 21.713154] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10995 01:26:08.572439 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10996 01:26:08.572533
10997 01:26:08.597831 <30>[ 21.744865] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10998 01:26:08.611219 Starting [0;1;39mmodprobe@drm.service<6>[ 21.756015] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10999 01:26:08.614178 [0m - Load Kernel Module drm...
11000 01:26:08.614261
11001 01:26:08.664931 <30>[ 21.812148] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
11002 01:26:08.674795 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
11003 01:26:08.674886
11004 01:26:08.698136 <30>[ 21.845199] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
11005 01:26:08.704943 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
11006 01:26:08.705028
11007 01:26:08.729738 <30>[ 21.877130] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
11008 01:26:08.736712 Starting [0;1;39mmodpr<6>[ 21.887243] fuse: init (API version 7.37)
11009 01:26:08.742823 obe@loop.ser…e[0m - Load Kernel Module loop...
11010 01:26:08.742909
11011 01:26:08.789382 <30>[ 21.936257] systemd[1]: Starting systemd-journald.service - Journal Service...
11012 01:26:08.795802 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
11013 01:26:08.795892
11014 01:26:08.829532 <30>[ 21.976630] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
11015 01:26:08.836310 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
11016 01:26:08.836402
11017 01:26:08.864464 <30>[ 22.008296] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
11018 01:26:08.871298 Starting [0;1;39msystemd-network-g… units from Kernel command line...
11019 01:26:08.871430
11020 01:26:08.933535 <30>[ 22.080257] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
11021 01:26:08.950023 Starting [0;1;39msystemd-remount-f…nt Root and Kerne<3>[ 22.094986] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11022 01:26:08.950160 l File Systems...
11023 01:26:08.950231
11024 01:26:08.972337 <30>[ 22.118816] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
11025 01:26:08.985134 Starting [0;1;39msyste<3>[ 22.129398] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11026 01:26:08.988695 md-udev-trig…[0m - Coldplug All udev Devices...
11027 01:26:08.988778
11028 01:26:09.012719 <30>[ 22.159538] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
11029 01:26:09.026662 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - H<3>[ 22.171879] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11030 01:26:09.029501 uge Pages File System.
11031 01:26:09.029623
11032 01:26:09.048909 <30>[ 22.195878] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
11033 01:26:09.058825 [[0;32m OK [<3>[ 22.204807] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11034 01:26:09.065656 0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
11035 01:26:09.065744
11036 01:26:09.084534 <30>[ 22.231453] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
11037 01:26:09.091255 <3>[ 22.235528] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11038 01:26:09.100846 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
11039 01:26:09.100955
11040 01:26:09.122253 <3>[ 22.269665] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11041 01:26:09.132143 <30>[ 22.279423] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
11042 01:26:09.142241 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
11043 01:26:09.142323
11044 01:26:09.160812 <3>[ 22.308013] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11045 01:26:09.172223 <30>[ 22.319342] systemd[1]: modprobe@configfs.service: Deactivated successfully.
11046 01:26:09.178847 <30>[ 22.327362] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
11047 01:26:09.192989 [[0;32m OK [0m] Finished [0;1;39mmodprobe@c<3>[ 22.339894] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11048 01:26:09.199180 onfigfs…[0m - Load Kernel Module configfs.
11049 01:26:09.199266
11050 01:26:09.217022 <30>[ 22.364199] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
11051 01:26:09.224436 <30>[ 22.372363] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
11052 01:26:09.234075 [[0;32m OK [<3>[ 22.381011] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11053 01:26:09.240461 0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
11054 01:26:09.243819
11055 01:26:09.265587 <30>[ 22.412638] systemd[1]: modprobe@drm.service: Deactivated successfully.
11056 01:26:09.272354 <3>[ 22.413337] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11057 01:26:09.282291 <30>[ 22.420441] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
11058 01:26:09.288602 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
11059 01:26:09.288718
11060 01:26:09.309204 <30>[ 22.456413] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
11061 01:26:09.319959 <30>[ 22.464851] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
11062 01:26:09.326064 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11063 01:26:09.326148
11064 01:26:09.345547 <30>[ 22.492614] systemd[1]: Started systemd-journald.service - Journal Service.
11065 01:26:09.351599 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11066 01:26:09.351682
11067 01:26:09.386957 <4>[ 22.527649] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11068 01:26:09.397254 <3>[ 22.543319] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11069 01:26:09.403213 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11070 01:26:09.403295
11071 01:26:09.422780 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11072 01:26:09.422864
11073 01:26:09.442146 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11074 01:26:09.442232
11075 01:26:09.462027 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11076 01:26:09.462113
11077 01:26:09.481892 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11078 01:26:09.481985
11079 01:26:09.501581 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11080 01:26:09.501666
11081 01:26:09.522982 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11082 01:26:09.523064
11083 01:26:09.569211 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11084 01:26:09.569360
11085 01:26:09.591331 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11086 01:26:09.591430
11087 01:26:09.613555 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11088 01:26:09.613646
11089 01:26:09.638369 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11090 01:26:09.638462
11091 01:26:09.672540 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables..<46>[ 22.819976] systemd-journald[298]: Received client request to flush runtime journal.
11092 01:26:09.672639 .
11093 01:26:09.672704
11094 01:26:09.725277 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11095 01:26:09.725422
11096 01:26:09.995979 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11097 01:26:09.996173
11098 01:26:10.012891 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11099 01:26:10.013018
11100 01:26:10.033662 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11101 01:26:10.033802
11102 01:26:10.624976 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11103 01:26:10.625132
11104 01:26:11.086778 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11105 01:26:11.086907
11106 01:26:11.108632 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11107 01:26:11.108754
11108 01:26:11.157406 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11109 01:26:11.157506
11110 01:26:11.256430 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11111 01:26:11.256559
11112 01:26:11.277068 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11113 01:26:11.277191
11114 01:26:11.296106 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11115 01:26:11.296211
11116 01:26:11.341298 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11117 01:26:11.341420
11118 01:26:11.366722 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11119 01:26:11.366813
11120 01:26:11.629537 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11121 01:26:11.629709
11122 01:26:11.690894 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11123 01:26:11.691024
11124 01:26:11.717265 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11125 01:26:11.717411
11126 01:26:12.057254 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11127 01:26:12.057456
11128 01:26:12.093311 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11129 01:26:12.093435
11130 01:26:12.165644 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11131 01:26:12.165763
11132 01:26:12.208574 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11133 01:26:12.208688
11134 01:26:12.236309 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11135 01:26:12.236396
11136 01:26:12.273212 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11137 01:26:12.273356
11138 01:26:12.292583 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11139 01:26:12.292707
11140 01:26:12.308772 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11141 01:26:12.308864
11142 01:26:12.336200 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11143 01:26:12.336293
11144 01:26:12.356409 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11145 01:26:12.356532
11146 01:26:12.425856 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11147 01:26:12.425981
11148 01:26:12.449375 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11149 01:26:12.449463
11150 01:26:12.475226 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11151 01:26:12.475316
11152 01:26:12.497099 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11153 01:26:12.497213
11154 01:26:12.521530 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11155 01:26:12.521614
11156 01:26:12.544576 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11157 01:26:12.544671
11158 01:26:12.575994 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11159 01:26:12.576082
11160 01:26:12.595129 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11161 01:26:12.595241
11162 01:26:12.611954 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11163 01:26:12.612040
11164 01:26:12.631657 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11165 01:26:12.631742
11166 01:26:12.651814 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11167 01:26:12.651898
11168 01:26:12.668297 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11169 01:26:12.668381
11170 01:26:12.684040 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11171 01:26:12.684126
11172 01:26:12.702431 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11173 01:26:12.702517
11174 01:26:12.719997 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11175 01:26:12.720080
11176 01:26:12.736094 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11177 01:26:12.736180
11178 01:26:12.773315 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11179 01:26:12.773474
11180 01:26:12.808776 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11181 01:26:12.808885
11182 01:26:12.913706 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11183 01:26:12.913873
11184 01:26:12.940342 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11185 01:26:12.940432
11186 01:26:13.097035 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11187 01:26:13.097168
11188 01:26:13.131661 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11189 01:26:13.131784
11190 01:26:13.156249 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11191 01:26:13.156339
11192 01:26:13.176777 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11193 01:26:13.176910
11194 01:26:13.192462 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11195 01:26:13.192592
11196 01:26:13.234767 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11197 01:26:13.234886
11198 01:26:13.272963 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11199 01:26:13.273063
11200 01:26:13.292600 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11201 01:26:13.292688
11202 01:26:13.310885 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11203 01:26:13.311000
11204 01:26:13.372138 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11205 01:26:13.372234
11206 01:26:13.397178 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11207 01:26:13.397322
11208 01:26:13.446587 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11209 01:26:13.446718
11210 01:26:13.481762 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11211 01:26:13.481891
11212 01:26:13.567157
11213 01:26:13.567289
11214 01:26:13.570375 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11215 01:26:13.570451
11216 01:26:13.573458 debian-bookworm-arm64 login: root (automatic login)
11217 01:26:13.573545
11218 01:26:13.573609
11219 01:26:13.896083 Linux debian-bookworm-arm64 6.1.86-cip19 #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024 aarch64
11220 01:26:13.896240
11221 01:26:13.902747 The programs included with the Debian GNU/Linux system are free software;
11222 01:26:13.909037 the exact distribution terms for each program are described in the
11223 01:26:13.912538 individual files in /usr/share/doc/*/copyright.
11224 01:26:13.912684
11225 01:26:13.919011 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11226 01:26:13.922467 permitted by applicable law.
11227 01:26:14.979809 Matched prompt #10: / #
11229 01:26:14.980164 Setting prompt string to ['/ #']
11230 01:26:14.980301 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11232 01:26:14.980593 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11233 01:26:14.980688 start: 2.2.6 expect-shell-connection (timeout 00:03:05) [common]
11234 01:26:14.980760 Setting prompt string to ['/ #']
11235 01:26:14.980824 Forcing a shell prompt, looking for ['/ #']
11237 01:26:15.031048 / #
11238 01:26:15.031184 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11239 01:26:15.031262 Waiting using forced prompt support (timeout 00:02:30)
11240 01:26:15.035900
11241 01:26:15.036207 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11242 01:26:15.036306 start: 2.2.7 export-device-env (timeout 00:03:05) [common]
11244 01:26:15.136781 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13468798/extract-nfsrootfs-v8wz2pm6'
11245 01:26:15.141746 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13468798/extract-nfsrootfs-v8wz2pm6'
11247 01:26:15.242267 / # export NFS_SERVER_IP='192.168.201.1'
11248 01:26:15.247544 export NFS_SERVER_IP='192.168.201.1'
11249 01:26:15.247915 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11250 01:26:15.248044 end: 2.2 depthcharge-retry (duration 00:01:55) [common]
11251 01:26:15.248174 end: 2 depthcharge-action (duration 00:01:55) [common]
11252 01:26:15.248295 start: 3 lava-test-retry (timeout 00:07:27) [common]
11253 01:26:15.248411 start: 3.1 lava-test-shell (timeout 00:07:27) [common]
11254 01:26:15.248518 Using namespace: common
11256 01:26:15.348875 / # #
11257 01:26:15.349015 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11258 01:26:15.354010 #
11259 01:26:15.354302 Using /lava-13468798
11261 01:26:15.454697 / # export SHELL=/bin/bash
11262 01:26:15.459540 export SHELL=/bin/bash
11264 01:26:15.560016 / # . /lava-13468798/environment
11265 01:26:15.564783 . /lava-13468798/environment
11267 01:26:15.671329 / # /lava-13468798/bin/lava-test-runner /lava-13468798/0
11268 01:26:15.671499 Test shell timeout: 10s (minimum of the action and connection timeout)
11269 01:26:15.676915 /lava-13468798/bin/lava-test-runner /lava-13468798/0
11270 01:26:15.932732 + export TESTRUN_ID=0_timesync-off
11271 01:26:15.936099 + TESTRUN_ID=0_timesync-off
11272 01:26:15.939217 + cd /lava-13468798/0/tests/0_timesync-off
11273 01:26:15.942845 ++ cat uuid
11274 01:26:15.946522 + UUID=13468798_1.6.2.3.1
11275 01:26:15.946599 + set +x
11276 01:26:15.953252 <LAVA_SIGNAL_STARTRUN 0_timesync-off 13468798_1.6.2.3.1>
11277 01:26:15.953546 Received signal: <STARTRUN> 0_timesync-off 13468798_1.6.2.3.1
11278 01:26:15.953622 Starting test lava.0_timesync-off (13468798_1.6.2.3.1)
11279 01:26:15.953709 Skipping test definition patterns.
11280 01:26:15.956267 + systemctl stop systemd-timesyncd
11281 01:26:16.021940 + set +x
11282 01:26:16.025599 <LAVA_SIGNAL_ENDRUN 0_timesync-off 13468798_1.6.2.3.1>
11283 01:26:16.025869 Received signal: <ENDRUN> 0_timesync-off 13468798_1.6.2.3.1
11284 01:26:16.025956 Ending use of test pattern.
11285 01:26:16.026036 Ending test lava.0_timesync-off (13468798_1.6.2.3.1), duration 0.07
11287 01:26:16.100213 + export TESTRUN_ID=1_kselftest-arm64
11288 01:26:16.100330 + TESTRUN_ID=1_kselftest-arm64
11289 01:26:16.106876 + cd /lava-13468798/0/tests/1_kselftest-arm64
11290 01:26:16.106966 ++ cat uuid
11291 01:26:16.110480 + UUID=13468798_1.6.2.3.5
11292 01:26:16.110566 + set +x
11293 01:26:16.116546 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 13468798_1.6.2.3.5>
11294 01:26:16.116803 Received signal: <STARTRUN> 1_kselftest-arm64 13468798_1.6.2.3.5
11295 01:26:16.116874 Starting test lava.1_kselftest-arm64 (13468798_1.6.2.3.5)
11296 01:26:16.116957 Skipping test definition patterns.
11297 01:26:16.120248 + cd ./automated/linux/kselftest/
11298 01:26:16.146151 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11299 01:26:16.191897 INFO: install_deps skipped
11300 01:26:16.700877 --2024-04-23 01:26:16-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11301 01:26:16.712609 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11302 01:26:16.839530 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11303 01:26:16.965929 HTTP request sent, awaiting response... 200 OK
11304 01:26:16.969689 Length: 1651524 (1.6M) [application/octet-stream]
11305 01:26:16.972667 Saving to: 'kselftest_armhf.tar.gz'
11306 01:26:16.972740
11307 01:26:16.972802
11308 01:26:17.222473 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11309 01:26:17.475433 kselftest_armhf.tar 2%[ ] 47.81K 187KB/s
11310 01:26:17.776843 kselftest_armhf.tar 13%[=> ] 217.50K 426KB/s
11311 01:26:17.908888 kselftest_armhf.tar 50%[=========> ] 818.47K 1006KB/s
11312 01:26:17.915701 kselftest_armhf.tar 100%[===================>] 1.57M 1.66MB/s in 0.9s
11313 01:26:17.915791
11314 01:26:18.060723 2024-04-23 01:26:17 (1.66 MB/s) - 'kselftest_armhf.tar.gz' saved [1651524/1651524]
11315 01:26:18.060870
11316 01:26:22.640627 skiplist:
11317 01:26:22.643843 ========================================
11318 01:26:22.647374 ========================================
11319 01:26:22.699950 arm64:tags_test
11320 01:26:22.703038 arm64:run_tags_test.sh
11321 01:26:22.703186 arm64:fake_sigreturn_bad_magic
11322 01:26:22.706619 arm64:fake_sigreturn_bad_size
11323 01:26:22.709711 arm64:fake_sigreturn_bad_size_for_magic0
11324 01:26:22.712817 arm64:fake_sigreturn_duplicated_fpsimd
11325 01:26:22.716584 arm64:fake_sigreturn_misaligned_sp
11326 01:26:22.719527 arm64:fake_sigreturn_missing_fpsimd
11327 01:26:22.722993 arm64:fake_sigreturn_sme_change_vl
11328 01:26:22.725933 arm64:fake_sigreturn_sve_change_vl
11329 01:26:22.729737 arm64:mangle_pstate_invalid_compat_toggle
11330 01:26:22.732738 arm64:mangle_pstate_invalid_daif_bits
11331 01:26:22.735895 arm64:mangle_pstate_invalid_mode_el1h
11332 01:26:22.739520 arm64:mangle_pstate_invalid_mode_el1t
11333 01:26:22.742592 arm64:mangle_pstate_invalid_mode_el2h
11334 01:26:22.746206 arm64:mangle_pstate_invalid_mode_el2t
11335 01:26:22.749231 arm64:mangle_pstate_invalid_mode_el3h
11336 01:26:22.755833 arm64:mangle_pstate_invalid_mode_el3t
11337 01:26:22.755917 arm64:sme_trap_no_sm
11338 01:26:22.758989 arm64:sme_trap_non_streaming
11339 01:26:22.759085 arm64:sme_trap_za
11340 01:26:22.762466 arm64:sme_vl
11341 01:26:22.762538 arm64:ssve_regs
11342 01:26:22.765813 arm64:sve_regs
11343 01:26:22.765888 arm64:sve_vl
11344 01:26:22.765948 arm64:za_no_regs
11345 01:26:22.768994 arm64:za_regs
11346 01:26:22.769060 arm64:pac
11347 01:26:22.772117 arm64:fp-stress
11348 01:26:22.772202 arm64:sve-ptrace
11349 01:26:22.775447 arm64:sve-probe-vls
11350 01:26:22.775525 arm64:vec-syscfg
11351 01:26:22.775595 arm64:za-fork
11352 01:26:22.778673 arm64:za-ptrace
11353 01:26:22.782365 arm64:check_buffer_fill
11354 01:26:22.782445 arm64:check_child_memory
11355 01:26:22.785320 arm64:check_gcr_el1_cswitch
11356 01:26:22.788795 arm64:check_ksm_options
11357 01:26:22.788868 arm64:check_mmap_options
11358 01:26:22.792330 arm64:check_prctl
11359 01:26:22.795361 arm64:check_tags_inclusion
11360 01:26:22.795434 arm64:check_user_mem
11361 01:26:22.798536 arm64:btitest
11362 01:26:22.798608 arm64:nobtitest
11363 01:26:22.798668 arm64:hwcap
11364 01:26:22.802120 arm64:ptrace
11365 01:26:22.802194 arm64:syscall-abi
11366 01:26:22.805142 arm64:tpidr2
11367 01:26:22.808961 ============== Tests to run ===============
11368 01:26:22.809041 arm64:tags_test
11369 01:26:22.812075 arm64:run_tags_test.sh
11370 01:26:22.815319 arm64:fake_sigreturn_bad_magic
11371 01:26:22.818421 arm64:fake_sigreturn_bad_size
11372 01:26:22.822083 arm64:fake_sigreturn_bad_size_for_magic0
11373 01:26:22.825151 arm64:fake_sigreturn_duplicated_fpsimd
11374 01:26:22.828589 arm64:fake_sigreturn_misaligned_sp
11375 01:26:22.831688 arm64:fake_sigreturn_missing_fpsimd
11376 01:26:22.835164 arm64:fake_sigreturn_sme_change_vl
11377 01:26:22.838362 arm64:fake_sigreturn_sve_change_vl
11378 01:26:22.841523 arm64:mangle_pstate_invalid_compat_toggle
11379 01:26:22.845239 arm64:mangle_pstate_invalid_daif_bits
11380 01:26:22.848455 arm64:mangle_pstate_invalid_mode_el1h
11381 01:26:22.851628 arm64:mangle_pstate_invalid_mode_el1t
11382 01:26:22.854563 arm64:mangle_pstate_invalid_mode_el2h
11383 01:26:22.858092 arm64:mangle_pstate_invalid_mode_el2t
11384 01:26:22.861642 arm64:mangle_pstate_invalid_mode_el3h
11385 01:26:22.864434 arm64:mangle_pstate_invalid_mode_el3t
11386 01:26:22.864507 arm64:sme_trap_no_sm
11387 01:26:22.867946 arm64:sme_trap_non_streaming
11388 01:26:22.871623 arm64:sme_trap_za
11389 01:26:22.871710 arm64:sme_vl
11390 01:26:22.874442 arm64:ssve_regs
11391 01:26:22.874523 arm64:sve_regs
11392 01:26:22.874587 arm64:sve_vl
11393 01:26:22.877832 arm64:za_no_regs
11394 01:26:22.877913 arm64:za_regs
11395 01:26:22.877976 arm64:pac
11396 01:26:22.881048 arm64:fp-stress
11397 01:26:22.881154 arm64:sve-ptrace
11398 01:26:22.884242 arm64:sve-probe-vls
11399 01:26:22.884322 arm64:vec-syscfg
11400 01:26:22.887732 arm64:za-fork
11401 01:26:22.887813 arm64:za-ptrace
11402 01:26:22.891041 arm64:check_buffer_fill
11403 01:26:22.894506 arm64:check_child_memory
11404 01:26:22.894587 arm64:check_gcr_el1_cswitch
11405 01:26:22.897485 arm64:check_ksm_options
11406 01:26:22.900973 arm64:check_mmap_options
11407 01:26:22.901053 arm64:check_prctl
11408 01:26:22.904207 arm64:check_tags_inclusion
11409 01:26:22.907751 arm64:check_user_mem
11410 01:26:22.907832 arm64:btitest
11411 01:26:22.907896 arm64:nobtitest
11412 01:26:22.910902 arm64:hwcap
11413 01:26:22.910983 arm64:ptrace
11414 01:26:22.914005 arm64:syscall-abi
11415 01:26:22.914085 arm64:tpidr2
11416 01:26:22.917677 ===========End Tests to run ===============
11417 01:26:22.920816 shardfile-arm64 pass
11418 01:26:23.154511 <12>[ 36.306731] kselftest: Running tests in arm64
11419 01:26:23.165343 TAP version 13
11420 01:26:23.181676 1..48
11421 01:26:23.200026 # selftests: arm64: tags_test
11422 01:26:23.659013 ok 1 selftests: arm64: tags_test
11423 01:26:23.675912 # selftests: arm64: run_tags_test.sh
11424 01:26:23.736147 # --------------------
11425 01:26:23.739340 # running tags test
11426 01:26:23.739430 # --------------------
11427 01:26:23.742238 # [PASS]
11428 01:26:23.746059 ok 2 selftests: arm64: run_tags_test.sh
11429 01:26:23.758990 # selftests: arm64: fake_sigreturn_bad_magic
11430 01:26:23.814232 # Registered handlers for all signals.
11431 01:26:23.814353 # Detected MINSTKSIGSZ:4720
11432 01:26:23.817955 # Testcase initialized.
11433 01:26:23.821193 # uc context validated.
11434 01:26:23.824206 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11435 01:26:23.828203 # Handled SIG_COPYCTX
11436 01:26:23.828305 # Available space:3568
11437 01:26:23.834431 # Using badly built context - ERR: BAD MAGIC !
11438 01:26:23.841104 # SIG_OK -- SP:0xFFFFEF430050 si_addr@:0xffffef430050 si_code:2 token@:0xffffef42edf0 offset:-4704
11439 01:26:23.843993 # ==>> completed. PASS(1)
11440 01:26:23.850903 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11441 01:26:23.857076 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEF42EDF0
11442 01:26:23.863977 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11443 01:26:23.867136 # selftests: arm64: fake_sigreturn_bad_size
11444 01:26:23.915147 # Registered handlers for all signals.
11445 01:26:23.915258 # Detected MINSTKSIGSZ:4720
11446 01:26:23.918418 # Testcase initialized.
11447 01:26:23.921865 # uc context validated.
11448 01:26:23.924789 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11449 01:26:23.928516 # Handled SIG_COPYCTX
11450 01:26:23.928617 # Available space:3568
11451 01:26:23.931614 # uc context validated.
11452 01:26:23.938394 # Using badly built context - ERR: Bad size for esr_context
11453 01:26:23.944395 # SIG_OK -- SP:0xFFFFD4038DB0 si_addr@:0xffffd4038db0 si_code:2 token@:0xffffd4037b50 offset:-4704
11454 01:26:23.947884 # ==>> completed. PASS(1)
11455 01:26:23.954599 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11456 01:26:23.961112 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD4037B50
11457 01:26:23.964791 ok 4 selftests: arm64: fake_sigreturn_bad_size
11458 01:26:23.971039 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11459 01:26:23.992111 # Registered handlers for all signals.
11460 01:26:23.992221 # Detected MINSTKSIGSZ:4720
11461 01:26:23.995710 # Testcase initialized.
11462 01:26:23.998782 # uc context validated.
11463 01:26:24.002311 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11464 01:26:24.005121 # Handled SIG_COPYCTX
11465 01:26:24.005225 # Available space:3568
11466 01:26:24.012006 # Using badly built context - ERR: Bad size for terminator
11467 01:26:24.021895 # SIG_OK -- SP:0xFFFFEA0FE980 si_addr@:0xffffea0fe980 si_code:2 token@:0xffffea0fd720 offset:-4704
11468 01:26:24.021986 # ==>> completed. PASS(1)
11469 01:26:24.031594 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11470 01:26:24.038159 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEA0FD720
11471 01:26:24.041342 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11472 01:26:24.048157 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11473 01:26:24.076585 # Registered handlers for all signals.
11474 01:26:24.076678 # Detected MINSTKSIGSZ:4720
11475 01:26:24.079633 # Testcase initialized.
11476 01:26:24.082790 # uc context validated.
11477 01:26:24.086522 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11478 01:26:24.089387 # Handled SIG_COPYCTX
11479 01:26:24.089469 # Available space:3568
11480 01:26:24.096281 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11481 01:26:24.106188 # SIG_OK -- SP:0xFFFFF1525B40 si_addr@:0xfffff1525b40 si_code:2 token@:0xfffff15248e0 offset:-4704
11482 01:26:24.106277 # ==>> completed. PASS(1)
11483 01:26:24.115964 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11484 01:26:24.122839 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF15248E0
11485 01:26:24.125900 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11486 01:26:24.129053 # selftests: arm64: fake_sigreturn_misaligned_sp
11487 01:26:24.161161 # Registered handlers for all signals.
11488 01:26:24.161287 # Detected MINSTKSIGSZ:4720
11489 01:26:24.164662 # Testcase initialized.
11490 01:26:24.167716 # uc context validated.
11491 01:26:24.171198 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11492 01:26:24.174058 # Handled SIG_COPYCTX
11493 01:26:24.180863 # SIG_OK -- SP:0xFFFFDBA57443 si_addr@:0xffffdba57443 si_code:2 token@:0xffffdba57443 offset:0
11494 01:26:24.183859 # ==>> completed. PASS(1)
11495 01:26:24.190790 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11496 01:26:24.196974 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDBA57443
11497 01:26:24.206317 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11498 01:26:24.206967 # selftests: arm64: fake_sigreturn_missing_fpsimd
11499 01:26:24.259437 # Registered handlers for all signals.
11500 01:26:24.259542 # Detected MINSTKSIGSZ:4720
11501 01:26:24.262539 # Testcase initialized.
11502 01:26:24.266101 # uc context validated.
11503 01:26:24.269101 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11504 01:26:24.272614 # Handled SIG_COPYCTX
11505 01:26:24.275870 # Mangling template header. Spare space:4096
11506 01:26:24.278950 # Using badly built context - ERR: Missing FPSIMD
11507 01:26:24.289247 # SIG_OK -- SP:0xFFFFF8DCEE40 si_addr@:0xfffff8dcee40 si_code:2 token@:0xfffff8dcdbe0 offset:-4704
11508 01:26:24.292427 # ==>> completed. PASS(1)
11509 01:26:24.298823 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11510 01:26:24.305597 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF8DCDBE0
11511 01:26:24.308785 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11512 01:26:24.315131 # selftests: arm64: fake_sigreturn_sme_change_vl
11513 01:26:24.335401 # Registered handlers for all signals.
11514 01:26:24.335510 # Detected MINSTKSIGSZ:4720
11515 01:26:24.338439 # ==>> completed. SKIP.
11516 01:26:24.344925 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11517 01:26:24.348471 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11518 01:26:24.356639 # selftests: arm64: fake_sigreturn_sve_change_vl
11519 01:26:24.423497 # Registered handlers for all signals.
11520 01:26:24.423607 # Detected MINSTKSIGSZ:4720
11521 01:26:24.426832 # ==>> completed. SKIP.
11522 01:26:24.433216 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11523 01:26:24.436720 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11524 01:26:24.443013 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11525 01:26:24.512083 # Registered handlers for all signals.
11526 01:26:24.512237 # Detected MINSTKSIGSZ:4720
11527 01:26:24.514923 # Testcase initialized.
11528 01:26:24.518873 # uc context validated.
11529 01:26:24.518946 # Handled SIG_TRIG
11530 01:26:24.528385 # SIG_OK -- SP:0xFFFFC34502F0 si_addr@:0xffffc34502f0 si_code:2 token@:(nil) offset:-281473957823216
11531 01:26:24.531792 # ==>> completed. PASS(1)
11532 01:26:24.538097 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11533 01:26:24.544861 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11534 01:26:24.547862 # selftests: arm64: mangle_pstate_invalid_daif_bits
11535 01:26:24.605964 # Registered handlers for all signals.
11536 01:26:24.606113 # Detected MINSTKSIGSZ:4720
11537 01:26:24.608681 # Testcase initialized.
11538 01:26:24.612435 # uc context validated.
11539 01:26:24.612539 # Handled SIG_TRIG
11540 01:26:24.622101 # SIG_OK -- SP:0xFFFFEFE84A40 si_addr@:0xffffefe84a40 si_code:2 token@:(nil) offset:-281474706721344
11541 01:26:24.625686 # ==>> completed. PASS(1)
11542 01:26:24.632290 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11543 01:26:24.635392 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11544 01:26:24.641808 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11545 01:26:24.680461 # Registered handlers for all signals.
11546 01:26:24.680557 # Detected MINSTKSIGSZ:4720
11547 01:26:24.683392 # Testcase initialized.
11548 01:26:24.687130 # uc context validated.
11549 01:26:24.687238 # Handled SIG_TRIG
11550 01:26:24.696704 # SIG_OK -- SP:0xFFFFFEA16EC0 si_addr@:0xfffffea16ec0 si_code:2 token@:(nil) offset:-281474953735872
11551 01:26:24.700059 # ==>> completed. PASS(1)
11552 01:26:24.706829 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11553 01:26:24.710004 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11554 01:26:24.716243 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11555 01:26:24.748351 # Registered handlers for all signals.
11556 01:26:24.748450 # Detected MINSTKSIGSZ:4720
11557 01:26:24.751832 # Testcase initialized.
11558 01:26:24.754681 # uc context validated.
11559 01:26:24.754770 # Handled SIG_TRIG
11560 01:26:24.764515 # SIG_OK -- SP:0xFFFFCE0171F0 si_addr@:0xffffce0171f0 si_code:2 token@:(nil) offset:-281474137944560
11561 01:26:24.768282 # ==>> completed. PASS(1)
11562 01:26:24.774908 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11563 01:26:24.778230 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11564 01:26:24.784559 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11565 01:26:24.852296 # Registered handlers for all signals.
11566 01:26:24.852420 # Detected MINSTKSIGSZ:4720
11567 01:26:24.855668 # Testcase initialized.
11568 01:26:24.859107 # uc context validated.
11569 01:26:24.859188 # Handled SIG_TRIG
11570 01:26:24.868883 # SIG_OK -- SP:0xFFFFDA188AC0 si_addr@:0xffffda188ac0 si_code:2 token@:(nil) offset:-281474340784832
11571 01:26:24.872350 # ==>> completed. PASS(1)
11572 01:26:24.878994 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11573 01:26:24.882355 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11574 01:26:24.888544 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11575 01:26:24.945299 # Registered handlers for all signals.
11576 01:26:24.945450 # Detected MINSTKSIGSZ:4720
11577 01:26:24.948521 # Testcase initialized.
11578 01:26:24.952020 # uc context validated.
11579 01:26:24.952101 # Handled SIG_TRIG
11580 01:26:24.961566 # SIG_OK -- SP:0xFFFFC910DEB0 si_addr@:0xffffc910deb0 si_code:2 token@:(nil) offset:-281474055069360
11581 01:26:24.964975 # ==>> completed. PASS(1)
11582 01:26:24.971684 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11583 01:26:24.974854 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11584 01:26:24.981233 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11585 01:26:25.050841 # Registered handlers for all signals.
11586 01:26:25.050966 # Detected MINSTKSIGSZ:4720
11587 01:26:25.053855 # Testcase initialized.
11588 01:26:25.057543 # uc context validated.
11589 01:26:25.057639 # Handled SIG_TRIG
11590 01:26:25.067029 # SIG_OK -- SP:0xFFFFCAD074A0 si_addr@:0xffffcad074a0 si_code:2 token@:(nil) offset:-281474084402336
11591 01:26:25.070568 # ==>> completed. PASS(1)
11592 01:26:25.077006 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11593 01:26:25.080472 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11594 01:26:25.087213 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11595 01:26:25.125320 # Registered handlers for all signals.
11596 01:26:25.125476 # Detected MINSTKSIGSZ:4720
11597 01:26:25.128430 # Testcase initialized.
11598 01:26:25.131704 # uc context validated.
11599 01:26:25.131806 # Handled SIG_TRIG
11600 01:26:25.141545 # SIG_OK -- SP:0xFFFFF3B4ACD0 si_addr@:0xfffff3b4acd0 si_code:2 token@:(nil) offset:-281474770447568
11601 01:26:25.144539 # ==>> completed. PASS(1)
11602 01:26:25.151024 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11603 01:26:25.154899 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11604 01:26:25.157766 # selftests: arm64: sme_trap_no_sm
11605 01:26:25.199837 # Registered handlers for all signals.
11606 01:26:25.199933 # Detected MINSTKSIGSZ:4720
11607 01:26:25.203175 # ==>> completed. SKIP.
11608 01:26:25.213467 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11609 01:26:25.216512 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11610 01:26:25.219526 # selftests: arm64: sme_trap_non_streaming
11611 01:26:25.278551 # Registered handlers for all signals.
11612 01:26:25.278690 # Detected MINSTKSIGSZ:4720
11613 01:26:25.281565 # ==>> completed. SKIP.
11614 01:26:25.291310 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11615 01:26:25.298210 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11616 01:26:25.301335 # selftests: arm64: sme_trap_za
11617 01:26:25.391753 # Registered handlers for all signals.
11618 01:26:25.391863 # Detected MINSTKSIGSZ:4720
11619 01:26:25.394498 # Testcase initialized.
11620 01:26:25.404782 # SIG_OK -- SP:0xFFFFE4F664D0 si_addr@:0xaaaad9a22510 si_code:1 token@:(nil) offset:-187650772444432
11621 01:26:25.404868 # ==>> completed. PASS(1)
11622 01:26:25.414637 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11623 01:26:25.418072 ok 21 selftests: arm64: sme_trap_za
11624 01:26:25.418153 # selftests: arm64: sme_vl
11625 01:26:25.479180 # Registered handlers for all signals.
11626 01:26:25.479274 # Detected MINSTKSIGSZ:4720
11627 01:26:25.482357 # ==>> completed. SKIP.
11628 01:26:25.488916 # # SME VL :: Check that we get the right SME VL reported
11629 01:26:25.491823 ok 22 selftests: arm64: sme_vl # SKIP
11630 01:26:25.496361 # selftests: arm64: ssve_regs
11631 01:26:25.564061 # Registered handlers for all signals.
11632 01:26:25.564163 # Detected MINSTKSIGSZ:4720
11633 01:26:25.567011 # ==>> completed. SKIP.
11634 01:26:25.573611 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11635 01:26:25.580246 ok 23 selftests: arm64: ssve_regs # SKIP
11636 01:26:25.580327 # selftests: arm64: sve_regs
11637 01:26:25.643716 # Registered handlers for all signals.
11638 01:26:25.643852 # Detected MINSTKSIGSZ:4720
11639 01:26:25.647360 # ==>> completed. SKIP.
11640 01:26:25.653894 # # SVE registers :: Check that we get the right SVE registers reported
11641 01:26:25.656943 ok 24 selftests: arm64: sve_regs # SKIP
11642 01:26:25.661159 # selftests: arm64: sve_vl
11643 01:26:25.716103 # Registered handlers for all signals.
11644 01:26:25.716205 # Detected MINSTKSIGSZ:4720
11645 01:26:25.719448 # ==>> completed. SKIP.
11646 01:26:25.725737 # # SVE VL :: Check that we get the right SVE VL reported
11647 01:26:25.729119 ok 25 selftests: arm64: sve_vl # SKIP
11648 01:26:25.732675 # selftests: arm64: za_no_regs
11649 01:26:25.800241 # Registered handlers for all signals.
11650 01:26:25.800368 # Detected MINSTKSIGSZ:4720
11651 01:26:25.803944 # ==>> completed. SKIP.
11652 01:26:25.810445 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11653 01:26:25.813287 ok 26 selftests: arm64: za_no_regs # SKIP
11654 01:26:25.817115 # selftests: arm64: za_regs
11655 01:26:25.880486 # Registered handlers for all signals.
11656 01:26:25.880605 # Detected MINSTKSIGSZ:4720
11657 01:26:25.884055 # ==>> completed. SKIP.
11658 01:26:25.890166 # # ZA register :: Check that we get the right ZA registers reported
11659 01:26:25.893702 ok 27 selftests: arm64: za_regs # SKIP
11660 01:26:25.898023 # selftests: arm64: pac
11661 01:26:25.980676 # TAP version 13
11662 01:26:25.980828 # 1..7
11663 01:26:25.984460 # # Starting 7 tests from 1 test cases.
11664 01:26:25.987554 # # RUN global.corrupt_pac ...
11665 01:26:25.991250 # # SKIP PAUTH not enabled
11666 01:26:25.994116 # # OK global.corrupt_pac
11667 01:26:25.997244 # ok 1 # SKIP PAUTH not enabled
11668 01:26:26.003875 # # RUN global.pac_instructions_not_nop ...
11669 01:26:26.007518 # # SKIP PAUTH not enabled
11670 01:26:26.010879 # # OK global.pac_instructions_not_nop
11671 01:26:26.013979 # ok 2 # SKIP PAUTH not enabled
11672 01:26:26.020498 # # RUN global.pac_instructions_not_nop_generic ...
11673 01:26:26.024098 # # SKIP Generic PAUTH not enabled
11674 01:26:26.027154 # # OK global.pac_instructions_not_nop_generic
11675 01:26:26.033686 # ok 3 # SKIP Generic PAUTH not enabled
11676 01:26:26.036952 # # RUN global.single_thread_different_keys ...
11677 01:26:26.040392 # # SKIP PAUTH not enabled
11678 01:26:26.047019 # # OK global.single_thread_different_keys
11679 01:26:26.047102 # ok 4 # SKIP PAUTH not enabled
11680 01:26:26.053583 # # RUN global.exec_changed_keys ...
11681 01:26:26.056721 # # SKIP PAUTH not enabled
11682 01:26:26.059951 # # OK global.exec_changed_keys
11683 01:26:26.063718 # ok 5 # SKIP PAUTH not enabled
11684 01:26:26.067051 # # RUN global.context_switch_keep_keys ...
11685 01:26:26.069964 # # SKIP PAUTH not enabled
11686 01:26:26.076697 # # OK global.context_switch_keep_keys
11687 01:26:26.079606 # ok 6 # SKIP PAUTH not enabled
11688 01:26:26.083243 # # RUN global.context_switch_keep_keys_generic ...
11689 01:26:26.086218 # # SKIP Generic PAUTH not enabled
11690 01:26:26.092997 # # OK global.context_switch_keep_keys_generic
11691 01:26:26.096612 # ok 7 # SKIP Generic PAUTH not enabled
11692 01:26:26.099695 # # PASSED: 7 / 7 tests passed.
11693 01:26:26.103168 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11694 01:26:26.106276 ok 28 selftests: arm64: pac
11695 01:26:26.109258 # selftests: arm64: fp-stress
11696 01:26:32.952569 <6>[ 46.109019] vpu: disabling
11697 01:26:32.956150 <6>[ 46.112069] vproc2: disabling
11698 01:26:32.959285 <6>[ 46.115701] vproc1: disabling
11699 01:26:32.963364 <6>[ 46.119597] vaud18: disabling
11700 01:26:32.970446 <6>[ 46.123139] vsram_others: disabling
11701 01:26:32.973479 <6>[ 46.127127] va09: disabling
11702 01:26:32.976440 <6>[ 46.130323] vsram_md: disabling
11703 01:26:32.980070 <6>[ 46.133920] Vgpu: disabling
11704 01:26:36.063723 # TAP version 13
11705 01:26:36.063866 # 1..16
11706 01:26:36.066729 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11707 01:26:36.070444 # # Will run for 10s
11708 01:26:36.070540 # # Started FPSIMD-0-0
11709 01:26:36.073576 # # Started FPSIMD-0-1
11710 01:26:36.076705 # # Started FPSIMD-1-0
11711 01:26:36.076801 # # Started FPSIMD-1-1
11712 01:26:36.080048 # # Started FPSIMD-2-0
11713 01:26:36.080168 # # Started FPSIMD-2-1
11714 01:26:36.083272 # # Started FPSIMD-3-0
11715 01:26:36.086936 # # Started FPSIMD-3-1
11716 01:26:36.087077 # # Started FPSIMD-4-0
11717 01:26:36.089834 # # Started FPSIMD-4-1
11718 01:26:36.093293 # # Started FPSIMD-5-0
11719 01:26:36.093422 # # Started FPSIMD-5-1
11720 01:26:36.096411 # # Started FPSIMD-6-0
11721 01:26:36.099996 # # Started FPSIMD-6-1
11722 01:26:36.100077 # # Started FPSIMD-7-0
11723 01:26:36.103002 # # Started FPSIMD-7-1
11724 01:26:36.106833 # # FPSIMD-0-0: Vector length: 128 bits
11725 01:26:36.109787 # # FPSIMD-0-0: PID: 1162
11726 01:26:36.112931 # # FPSIMD-0-1: Vector length: 128 bits
11727 01:26:36.113012 # # FPSIMD-0-1: PID: 1163
11728 01:26:36.116470 # # FPSIMD-1-0: Vector length: 128 bits
11729 01:26:36.119642 # # FPSIMD-1-0: PID: 1164
11730 01:26:36.123249 # # FPSIMD-3-0: Vector length: 128 bits
11731 01:26:36.126278 # # FPSIMD-3-0: PID: 1168
11732 01:26:36.129462 # # FPSIMD-2-1: Vector length: 128 bits
11733 01:26:36.132972 # # FPSIMD-2-1: PID: 1167
11734 01:26:36.136362 # # FPSIMD-3-1: Vector length: 128 bits
11735 01:26:36.139849 # # FPSIMD-3-1: PID: 1169
11736 01:26:36.142891 # # FPSIMD-1-1: Vector length: 128 bits
11737 01:26:36.142973 # # FPSIMD-1-1: PID: 1165
11738 01:26:36.146381 # # FPSIMD-4-0: Vector length: 128 bits
11739 01:26:36.149369 # # FPSIMD-4-0: PID: 1170
11740 01:26:36.152571 # # FPSIMD-6-0: Vector length: 128 bits
11741 01:26:36.156214 # # FPSIMD-6-0: PID: 1174
11742 01:26:36.159200 # # FPSIMD-7-0: Vector length: 128 bits
11743 01:26:36.162976 # # FPSIMD-7-0: PID: 1176
11744 01:26:36.165761 # # FPSIMD-4-1: Vector length: 128 bits
11745 01:26:36.165838 # # FPSIMD-4-1: PID: 1171
11746 01:26:36.172649 # # FPSIMD-5-0: Vector length: 128 bits
11747 01:26:36.172762 # # FPSIMD-5-0: PID: 1172
11748 01:26:36.175559 # # FPSIMD-6-1: Vector length: 128 bits
11749 01:26:36.179506 # # FPSIMD-6-1: PID: 1175
11750 01:26:36.182254 # # FPSIMD-5-1: Vector length: 128 bits
11751 01:26:36.186041 # # FPSIMD-5-1: PID: 1173
11752 01:26:36.188815 # # FPSIMD-2-0: Vector length: 128 bits
11753 01:26:36.192402 # # FPSIMD-2-0: PID: 1166
11754 01:26:36.195604 # # FPSIMD-7-1: Vector length: 128 bits
11755 01:26:36.195693 # # FPSIMD-7-1: PID: 1177
11756 01:26:36.199040 # # Finishing up...
11757 01:26:36.205264 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=989641, signals=10
11758 01:26:36.211837 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1467153, signals=10
11759 01:26:36.218368 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1014628, signals=10
11760 01:26:36.228602 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1429169, signals=10
11761 01:26:36.235359 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1339644, signals=10
11762 01:26:36.241964 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=834167, signals=10
11763 01:26:36.248084 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=1906450, signals=10
11764 01:26:36.251794 # ok 1 FPSIMD-0-0
11765 01:26:36.251880 # ok 2 FPSIMD-0-1
11766 01:26:36.254873 # ok 3 FPSIMD-1-0
11767 01:26:36.254954 # ok 4 FPSIMD-1-1
11768 01:26:36.257905 # ok 5 FPSIMD-2-0
11769 01:26:36.257986 # ok 6 FPSIMD-2-1
11770 01:26:36.261523 # ok 7 FPSIMD-3-0
11771 01:26:36.261625 # ok 8 FPSIMD-3-1
11772 01:26:36.264590 # ok 9 FPSIMD-4-0
11773 01:26:36.264695 # ok 10 FPSIMD-4-1
11774 01:26:36.268226 # ok 11 FPSIMD-5-0
11775 01:26:36.268307 # ok 12 FPSIMD-5-1
11776 01:26:36.271388 # ok 13 FPSIMD-6-0
11777 01:26:36.271491 # ok 14 FPSIMD-6-1
11778 01:26:36.274631 # ok 15 FPSIMD-7-0
11779 01:26:36.274712 # ok 16 FPSIMD-7-1
11780 01:26:36.284642 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=1041425, signals=9
11781 01:26:36.291033 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1148086, signals=10
11782 01:26:36.297676 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=1315043, signals=10
11783 01:26:36.304413 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=913372, signals=10
11784 01:26:36.310969 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1307482, signals=10
11785 01:26:36.318016 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=1207447, signals=9
11786 01:26:36.327725 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=956506, signals=10
11787 01:26:36.334437 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1294542, signals=10
11788 01:26:36.340586 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1126560, signals=10
11789 01:26:36.344141 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11790 01:26:36.347087 ok 29 selftests: arm64: fp-stress
11791 01:26:36.350508 # selftests: arm64: sve-ptrace
11792 01:26:36.353849 # TAP version 13
11793 01:26:36.353930 # 1..4104
11794 01:26:36.357580 # ok 2 # SKIP SVE not available
11795 01:26:36.360542 # # Planned tests != run tests (4104 != 1)
11796 01:26:36.367359 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11797 01:26:36.370439 ok 30 selftests: arm64: sve-ptrace # SKIP
11798 01:26:36.374135 # selftests: arm64: sve-probe-vls
11799 01:26:36.374216 # TAP version 13
11800 01:26:36.374281 # 1..2
11801 01:26:36.377236 # ok 2 # SKIP SVE not available
11802 01:26:36.380429 # # Planned tests != run tests (2 != 1)
11803 01:26:36.386759 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11804 01:26:36.390415 ok 31 selftests: arm64: sve-probe-vls # SKIP
11805 01:26:36.393589 # selftests: arm64: vec-syscfg
11806 01:26:36.393671 # TAP version 13
11807 01:26:36.397035 # 1..20
11808 01:26:36.397116 # ok 1 # SKIP SVE not supported
11809 01:26:36.400250 # ok 2 # SKIP SVE not supported
11810 01:26:36.403739 # ok 3 # SKIP SVE not supported
11811 01:26:36.406405 # ok 4 # SKIP SVE not supported
11812 01:26:36.410103 # ok 5 # SKIP SVE not supported
11813 01:26:36.413196 # ok 6 # SKIP SVE not supported
11814 01:26:36.416490 # ok 7 # SKIP SVE not supported
11815 01:26:36.416568 # ok 8 # SKIP SVE not supported
11816 01:26:36.419941 # ok 9 # SKIP SVE not supported
11817 01:26:36.423437 # ok 10 # SKIP SVE not supported
11818 01:26:36.426601 # ok 11 # SKIP SME not supported
11819 01:26:36.430071 # ok 12 # SKIP SME not supported
11820 01:26:36.433107 # ok 13 # SKIP SME not supported
11821 01:26:36.436305 # ok 14 # SKIP SME not supported
11822 01:26:36.439888 # ok 15 # SKIP SME not supported
11823 01:26:36.442960 # ok 16 # SKIP SME not supported
11824 01:26:36.443067 # ok 17 # SKIP SME not supported
11825 01:26:36.446025 # ok 18 # SKIP SME not supported
11826 01:26:36.449677 # ok 19 # SKIP SME not supported
11827 01:26:36.452605 # ok 20 # SKIP SME not supported
11828 01:26:36.459153 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11829 01:26:36.462919 ok 32 selftests: arm64: vec-syscfg
11830 01:26:36.463002 # selftests: arm64: za-fork
11831 01:26:36.465967 # TAP version 13
11832 01:26:36.466047 # 1..1
11833 01:26:36.469543 # # PID: 1254
11834 01:26:36.469622 # # SME support not present
11835 01:26:36.472540 # ok 0 skipped
11836 01:26:36.476175 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11837 01:26:36.479209 ok 33 selftests: arm64: za-fork
11838 01:26:36.482648 # selftests: arm64: za-ptrace
11839 01:26:36.482732 # TAP version 13
11840 01:26:36.485512 # 1..1
11841 01:26:36.485586 # ok 2 # SKIP SME not available
11842 01:26:36.492206 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11843 01:26:36.495716 ok 34 selftests: arm64: za-ptrace # SKIP
11844 01:26:36.498780 # selftests: arm64: check_buffer_fill
11845 01:26:36.567511 # # SKIP: MTE features unavailable
11846 01:26:36.575521 ok 35 selftests: arm64: check_buffer_fill # SKIP
11847 01:26:36.594830 # selftests: arm64: check_child_memory
11848 01:26:36.679411 # # SKIP: MTE features unavailable
11849 01:26:36.687116 ok 36 selftests: arm64: check_child_memory # SKIP
11850 01:26:36.704324 # selftests: arm64: check_gcr_el1_cswitch
11851 01:26:36.753702 # # SKIP: MTE features unavailable
11852 01:26:36.761632 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11853 01:26:36.778620 # selftests: arm64: check_ksm_options
11854 01:26:36.831448 # # SKIP: MTE features unavailable
11855 01:26:36.838008 ok 38 selftests: arm64: check_ksm_options # SKIP
11856 01:26:36.855484 # selftests: arm64: check_mmap_options
11857 01:26:36.932112 # # SKIP: MTE features unavailable
11858 01:26:36.940059 ok 39 selftests: arm64: check_mmap_options # SKIP
11859 01:26:36.951942 # selftests: arm64: check_prctl
11860 01:26:37.024977 # TAP version 13
11861 01:26:37.025089 # 1..5
11862 01:26:37.028726 # ok 1 check_basic_read
11863 01:26:37.028807 # ok 2 NONE
11864 01:26:37.031648 # ok 3 # SKIP SYNC
11865 01:26:37.031729 # ok 4 # SKIP ASYNC
11866 01:26:37.035130 # ok 5 # SKIP SYNC+ASYNC
11867 01:26:37.038578 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11868 01:26:37.041607 ok 40 selftests: arm64: check_prctl
11869 01:26:37.050706 # selftests: arm64: check_tags_inclusion
11870 01:26:37.104327 # # SKIP: MTE features unavailable
11871 01:26:37.112177 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11872 01:26:37.125653 # selftests: arm64: check_user_mem
11873 01:26:37.198373 # # SKIP: MTE features unavailable
11874 01:26:37.206963 ok 42 selftests: arm64: check_user_mem # SKIP
11875 01:26:37.221833 # selftests: arm64: btitest
11876 01:26:37.288303 # TAP version 13
11877 01:26:37.288422 # 1..18
11878 01:26:37.291796 # # HWCAP_PACA not present
11879 01:26:37.294810 # # HWCAP2_BTI not present
11880 01:26:37.294890 # # Test binary built for BTI
11881 01:26:37.301597 # ok 1 nohint_func/call_using_br_x0 # SKIP
11882 01:26:37.305152 # ok 1 nohint_func/call_using_br_x16 # SKIP
11883 01:26:37.308113 # ok 1 nohint_func/call_using_blr # SKIP
11884 01:26:37.311496 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11885 01:26:37.314365 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11886 01:26:37.321128 # ok 1 bti_none_func/call_using_blr # SKIP
11887 01:26:37.324376 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11888 01:26:37.328147 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11889 01:26:37.331237 # ok 1 bti_c_func/call_using_blr # SKIP
11890 01:26:37.334114 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11891 01:26:37.337715 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11892 01:26:37.340794 # ok 1 bti_j_func/call_using_blr # SKIP
11893 01:26:37.344318 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11894 01:26:37.350919 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11895 01:26:37.354145 # ok 1 bti_jc_func/call_using_blr # SKIP
11896 01:26:37.357229 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11897 01:26:37.360688 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11898 01:26:37.363945 # ok 1 paciasp_func/call_using_blr # SKIP
11899 01:26:37.370310 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11900 01:26:37.373905 # # WARNING - EXPECTED TEST COUNT WRONG
11901 01:26:37.377083 ok 43 selftests: arm64: btitest
11902 01:26:37.380395 # selftests: arm64: nobtitest
11903 01:26:37.380475 # TAP version 13
11904 01:26:37.380538 # 1..18
11905 01:26:37.383918 # # HWCAP_PACA not present
11906 01:26:37.386797 # # HWCAP2_BTI not present
11907 01:26:37.390241 # # Test binary not built for BTI
11908 01:26:37.393598 # ok 1 nohint_func/call_using_br_x0 # SKIP
11909 01:26:37.396619 # ok 1 nohint_func/call_using_br_x16 # SKIP
11910 01:26:37.400136 # ok 1 nohint_func/call_using_blr # SKIP
11911 01:26:37.403208 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11912 01:26:37.409796 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11913 01:26:37.413282 # ok 1 bti_none_func/call_using_blr # SKIP
11914 01:26:37.417034 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11915 01:26:37.420000 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11916 01:26:37.423135 # ok 1 bti_c_func/call_using_blr # SKIP
11917 01:26:37.426773 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11918 01:26:37.429904 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11919 01:26:37.436672 # ok 1 bti_j_func/call_using_blr # SKIP
11920 01:26:37.439671 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11921 01:26:37.442641 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11922 01:26:37.446447 # ok 1 bti_jc_func/call_using_blr # SKIP
11923 01:26:37.449308 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11924 01:26:37.453085 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11925 01:26:37.459569 # ok 1 paciasp_func/call_using_blr # SKIP
11926 01:26:37.462801 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11927 01:26:37.466277 # # WARNING - EXPECTED TEST COUNT WRONG
11928 01:26:37.469093 ok 44 selftests: arm64: nobtitest
11929 01:26:37.472502 # selftests: arm64: hwcap
11930 01:26:37.472582 # TAP version 13
11931 01:26:37.476090 # 1..28
11932 01:26:37.476174 # ok 1 cpuinfo_match_RNG
11933 01:26:37.479075 # # SIGILL reported for RNG
11934 01:26:37.482457 # ok 2 # SKIP sigill_RNG
11935 01:26:37.482537 # ok 3 cpuinfo_match_SME
11936 01:26:37.486140 # ok 4 sigill_SME
11937 01:26:37.489077 # ok 5 cpuinfo_match_SVE
11938 01:26:37.489145 # ok 6 sigill_SVE
11939 01:26:37.492614 # ok 7 cpuinfo_match_SVE 2
11940 01:26:37.495454 # # SIGILL reported for SVE 2
11941 01:26:37.495521 # ok 8 # SKIP sigill_SVE 2
11942 01:26:37.498886 # ok 9 cpuinfo_match_SVE AES
11943 01:26:37.502369 # # SIGILL reported for SVE AES
11944 01:26:37.505429 # ok 10 # SKIP sigill_SVE AES
11945 01:26:37.509155 # ok 11 cpuinfo_match_SVE2 PMULL
11946 01:26:37.512189 # # SIGILL reported for SVE2 PMULL
11947 01:26:37.515204 # ok 12 # SKIP sigill_SVE2 PMULL
11948 01:26:37.515285 # ok 13 cpuinfo_match_SVE2 BITPERM
11949 01:26:37.518533 # # SIGILL reported for SVE2 BITPERM
11950 01:26:37.521889 # ok 14 # SKIP sigill_SVE2 BITPERM
11951 01:26:37.525528 # ok 15 cpuinfo_match_SVE2 SHA3
11952 01:26:37.528411 # # SIGILL reported for SVE2 SHA3
11953 01:26:37.532218 # ok 16 # SKIP sigill_SVE2 SHA3
11954 01:26:37.534881 # ok 17 cpuinfo_match_SVE2 SM4
11955 01:26:37.538697 # # SIGILL reported for SVE2 SM4
11956 01:26:37.541745 # ok 18 # SKIP sigill_SVE2 SM4
11957 01:26:37.544915 # ok 19 cpuinfo_match_SVE2 I8MM
11958 01:26:37.544995 # # SIGILL reported for SVE2 I8MM
11959 01:26:37.548424 # ok 20 # SKIP sigill_SVE2 I8MM
11960 01:26:37.551365 # ok 21 cpuinfo_match_SVE2 F32MM
11961 01:26:37.555031 # # SIGILL reported for SVE2 F32MM
11962 01:26:37.558173 # ok 22 # SKIP sigill_SVE2 F32MM
11963 01:26:37.561654 # ok 23 cpuinfo_match_SVE2 F64MM
11964 01:26:37.564757 # # SIGILL reported for SVE2 F64MM
11965 01:26:37.568110 # ok 24 # SKIP sigill_SVE2 F64MM
11966 01:26:37.571350 # ok 25 cpuinfo_match_SVE2 BF16
11967 01:26:37.574924 # # SIGILL reported for SVE2 BF16
11968 01:26:37.574997 # ok 26 # SKIP sigill_SVE2 BF16
11969 01:26:37.577994 # ok 27 cpuinfo_match_SVE2 EBF16
11970 01:26:37.580889 # ok 28 # SKIP sigill_SVE2 EBF16
11971 01:26:37.587960 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11972 01:26:37.591136 ok 45 selftests: arm64: hwcap
11973 01:26:37.591217 # selftests: arm64: ptrace
11974 01:26:37.594255 # TAP version 13
11975 01:26:37.594336 # 1..7
11976 01:26:37.597384 # # Parent is 1496, child is 1497
11977 01:26:37.600673 # ok 1 read_tpidr_one
11978 01:26:37.600754 # ok 2 write_tpidr_one
11979 01:26:37.604356 # ok 3 verify_tpidr_one
11980 01:26:37.607101 # ok 4 count_tpidrs
11981 01:26:37.607219 # ok 5 tpidr2_write
11982 01:26:37.610427 # ok 6 tpidr2_read
11983 01:26:37.610506 # ok 7 write_tpidr_only
11984 01:26:37.617110 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11985 01:26:37.620613 ok 46 selftests: arm64: ptrace
11986 01:26:37.623533 # selftests: arm64: syscall-abi
11987 01:26:37.623613 # TAP version 13
11988 01:26:37.623686 # 1..2
11989 01:26:37.627078 # ok 1 getpid() FPSIMD
11990 01:26:37.630428 # ok 2 sched_yield() FPSIMD
11991 01:26:37.633324 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11992 01:26:37.637213 ok 47 selftests: arm64: syscall-abi
11993 01:26:37.640364 # selftests: arm64: tpidr2
11994 01:26:37.688229 # TAP version 13
11995 01:26:37.688311 # 1..5
11996 01:26:37.690975 # # PID: 1533
11997 01:26:37.691054 # # SME support not present
11998 01:26:37.693975 # ok 0 skipped, TPIDR2 not supported
11999 01:26:37.697455 # ok 1 skipped, TPIDR2 not supported
12000 01:26:37.700742 # ok 2 skipped, TPIDR2 not supported
12001 01:26:37.704135 # ok 3 skipped, TPIDR2 not supported
12002 01:26:37.707264 # ok 4 skipped, TPIDR2 not supported
12003 01:26:37.714258 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
12004 01:26:37.717286 ok 48 selftests: arm64: tpidr2
12005 01:26:39.239991 arm64_tags_test pass
12006 01:26:39.243016 arm64_run_tags_test_sh pass
12007 01:26:39.246528 arm64_fake_sigreturn_bad_magic pass
12008 01:26:39.249531 arm64_fake_sigreturn_bad_size pass
12009 01:26:39.253187 arm64_fake_sigreturn_bad_size_for_magic0 pass
12010 01:26:39.256188 arm64_fake_sigreturn_duplicated_fpsimd pass
12011 01:26:39.259890 arm64_fake_sigreturn_misaligned_sp pass
12012 01:26:39.262842 arm64_fake_sigreturn_missing_fpsimd pass
12013 01:26:39.265982 arm64_fake_sigreturn_sme_change_vl skip
12014 01:26:39.272793 arm64_fake_sigreturn_sve_change_vl skip
12015 01:26:39.276297 arm64_mangle_pstate_invalid_compat_toggle pass
12016 01:26:39.279576 arm64_mangle_pstate_invalid_daif_bits pass
12017 01:26:39.282724 arm64_mangle_pstate_invalid_mode_el1h pass
12018 01:26:39.285947 arm64_mangle_pstate_invalid_mode_el1t pass
12019 01:26:39.289695 arm64_mangle_pstate_invalid_mode_el2h pass
12020 01:26:39.295885 arm64_mangle_pstate_invalid_mode_el2t pass
12021 01:26:39.299048 arm64_mangle_pstate_invalid_mode_el3h pass
12022 01:26:39.302732 arm64_mangle_pstate_invalid_mode_el3t pass
12023 01:26:39.305695 arm64_sme_trap_no_sm skip
12024 01:26:39.309448 arm64_sme_trap_non_streaming skip
12025 01:26:39.309527 arm64_sme_trap_za pass
12026 01:26:39.312276 arm64_sme_vl skip
12027 01:26:39.312354 arm64_ssve_regs skip
12028 01:26:39.315742 arm64_sve_regs skip
12029 01:26:39.315845 arm64_sve_vl skip
12030 01:26:39.319157 arm64_za_no_regs skip
12031 01:26:39.319238 arm64_za_regs skip
12032 01:26:39.322162 arm64_pac_PAUTH_not_enabled skip
12033 01:26:39.325907 arm64_pac_PAUTH_not_enabled_dup2 skip
12034 01:26:39.328858 arm64_pac_Generic_PAUTH_not_enabled skip
12035 01:26:39.331858 arm64_pac_PAUTH_not_enabled_dup3 skip
12036 01:26:39.338577 arm64_pac_PAUTH_not_enabled_dup4 skip
12037 01:26:39.342276 arm64_pac_PAUTH_not_enabled_dup5 skip
12038 01:26:39.345109 arm64_pac_Generic_PAUTH_not_enabled_dup2 skip
12039 01:26:39.345189 arm64_pac pass
12040 01:26:39.348590 arm64_fp-stress_FPSIMD-0-0 pass
12041 01:26:39.352131 arm64_fp-stress_FPSIMD-0-1 pass
12042 01:26:39.355251 arm64_fp-stress_FPSIMD-1-0 pass
12043 01:26:39.358814 arm64_fp-stress_FPSIMD-1-1 pass
12044 01:26:39.361767 arm64_fp-stress_FPSIMD-2-0 pass
12045 01:26:39.361853 arm64_fp-stress_FPSIMD-2-1 pass
12046 01:26:39.364965 arm64_fp-stress_FPSIMD-3-0 pass
12047 01:26:39.368546 arm64_fp-stress_FPSIMD-3-1 pass
12048 01:26:39.371455 arm64_fp-stress_FPSIMD-4-0 pass
12049 01:26:39.374842 arm64_fp-stress_FPSIMD-4-1 pass
12050 01:26:39.378461 arm64_fp-stress_FPSIMD-5-0 pass
12051 01:26:39.381656 arm64_fp-stress_FPSIMD-5-1 pass
12052 01:26:39.381735 arm64_fp-stress_FPSIMD-6-0 pass
12053 01:26:39.384634 arm64_fp-stress_FPSIMD-6-1 pass
12054 01:26:39.388320 arm64_fp-stress_FPSIMD-7-0 pass
12055 01:26:39.391487 arm64_fp-stress_FPSIMD-7-1 pass
12056 01:26:39.394535 arm64_fp-stress pass
12057 01:26:39.397862 arm64_sve-ptrace_SVE_not_available skip
12058 01:26:39.397942 arm64_sve-ptrace skip
12059 01:26:39.404452 arm64_sve-probe-vls_SVE_not_available skip
12060 01:26:39.404533 arm64_sve-probe-vls skip
12061 01:26:39.408059 arm64_vec-syscfg_SVE_not_supported skip
12062 01:26:39.411041 arm64_vec-syscfg_SVE_not_supported_dup2 skip
12063 01:26:39.417651 arm64_vec-syscfg_SVE_not_supported_dup3 skip
12064 01:26:39.421523 arm64_vec-syscfg_SVE_not_supported_dup4 skip
12065 01:26:39.424227 arm64_vec-syscfg_SVE_not_supported_dup5 skip
12066 01:26:39.427976 arm64_vec-syscfg_SVE_not_supported_dup6 skip
12067 01:26:39.434467 arm64_vec-syscfg_SVE_not_supported_dup7 skip
12068 01:26:39.437590 arm64_vec-syscfg_SVE_not_supported_dup8 skip
12069 01:26:39.440546 arm64_vec-syscfg_SVE_not_supported_dup9 skip
12070 01:26:39.443974 arm64_vec-syscfg_SVE_not_supported_dup10 skip
12071 01:26:39.447528 arm64_vec-syscfg_SME_not_supported skip
12072 01:26:39.451016 arm64_vec-syscfg_SME_not_supported_dup2 skip
12073 01:26:39.457167 arm64_vec-syscfg_SME_not_supported_dup3 skip
12074 01:26:39.460809 arm64_vec-syscfg_SME_not_supported_dup4 skip
12075 01:26:39.463822 arm64_vec-syscfg_SME_not_supported_dup5 skip
12076 01:26:39.467311 arm64_vec-syscfg_SME_not_supported_dup6 skip
12077 01:26:39.474169 arm64_vec-syscfg_SME_not_supported_dup7 skip
12078 01:26:39.477072 arm64_vec-syscfg_SME_not_supported_dup8 skip
12079 01:26:39.480883 arm64_vec-syscfg_SME_not_supported_dup9 skip
12080 01:26:39.483687 arm64_vec-syscfg_SME_not_supported_dup10 skip
12081 01:26:39.487189 arm64_vec-syscfg pass
12082 01:26:39.490557 arm64_za-fork_skipped pass
12083 01:26:39.490636 arm64_za-fork pass
12084 01:26:39.493936 arm64_za-ptrace_SME_not_available skip
12085 01:26:39.496848 arm64_za-ptrace skip
12086 01:26:39.496926 arm64_check_buffer_fill skip
12087 01:26:39.500144 arm64_check_child_memory skip
12088 01:26:39.503508 arm64_check_gcr_el1_cswitch skip
12089 01:26:39.506755 arm64_check_ksm_options skip
12090 01:26:39.509985 arm64_check_mmap_options skip
12091 01:26:39.513694 arm64_check_prctl_check_basic_read pass
12092 01:26:39.516670 arm64_check_prctl_NONE pass
12093 01:26:39.516749 arm64_check_prctl_SYNC skip
12094 01:26:39.520646 arm64_check_prctl_ASYNC skip
12095 01:26:39.523360 arm64_check_prctl_SYNC_ASYNC skip
12096 01:26:39.526518 arm64_check_prctl pass
12097 01:26:39.529734 arm64_check_tags_inclusion skip
12098 01:26:39.529814 arm64_check_user_mem skip
12099 01:26:39.536843 arm64_btitest_nohint_func_call_using_br_x0 skip
12100 01:26:39.539674 arm64_btitest_nohint_func_call_using_br_x16 skip
12101 01:26:39.543081 arm64_btitest_nohint_func_call_using_blr skip
12102 01:26:39.550055 arm64_btitest_bti_none_func_call_using_br_x0 skip
12103 01:26:39.553022 arm64_btitest_bti_none_func_call_using_br_x16 skip
12104 01:26:39.555992 arm64_btitest_bti_none_func_call_using_blr skip
12105 01:26:39.559966 arm64_btitest_bti_c_func_call_using_br_x0 skip
12106 01:26:39.565981 arm64_btitest_bti_c_func_call_using_br_x16 skip
12107 01:26:39.569512 arm64_btitest_bti_c_func_call_using_blr skip
12108 01:26:39.572711 arm64_btitest_bti_j_func_call_using_br_x0 skip
12109 01:26:39.576148 arm64_btitest_bti_j_func_call_using_br_x16 skip
12110 01:26:39.582716 arm64_btitest_bti_j_func_call_using_blr skip
12111 01:26:39.586372 arm64_btitest_bti_jc_func_call_using_br_x0 skip
12112 01:26:39.589203 arm64_btitest_bti_jc_func_call_using_br_x16 skip
12113 01:26:39.595739 arm64_btitest_bti_jc_func_call_using_blr skip
12114 01:26:39.599162 arm64_btitest_paciasp_func_call_using_br_x0 skip
12115 01:26:39.602691 arm64_btitest_paciasp_func_call_using_br_x16 skip
12116 01:26:39.605872 arm64_btitest_paciasp_func_call_using_blr skip
12117 01:26:39.609142 arm64_btitest pass
12118 01:26:39.612388 arm64_nobtitest_nohint_func_call_using_br_x0 skip
12119 01:26:39.618707 arm64_nobtitest_nohint_func_call_using_br_x16 skip
12120 01:26:39.622355 arm64_nobtitest_nohint_func_call_using_blr skip
12121 01:26:39.625277 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
12122 01:26:39.631957 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
12123 01:26:39.635622 arm64_nobtitest_bti_none_func_call_using_blr skip
12124 01:26:39.638898 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
12125 01:26:39.645057 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
12126 01:26:39.648645 arm64_nobtitest_bti_c_func_call_using_blr skip
12127 01:26:39.651767 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
12128 01:26:39.658467 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
12129 01:26:39.661903 arm64_nobtitest_bti_j_func_call_using_blr skip
12130 01:26:39.665194 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
12131 01:26:39.671627 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
12132 01:26:39.674747 arm64_nobtitest_bti_jc_func_call_using_blr skip
12133 01:26:39.678400 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
12134 01:26:39.684482 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
12135 01:26:39.688048 arm64_nobtitest_paciasp_func_call_using_blr skip
12136 01:26:39.691499 arm64_nobtitest pass
12137 01:26:39.694477 arm64_hwcap_cpuinfo_match_RNG pass
12138 01:26:39.694545 arm64_hwcap_sigill_RNG skip
12139 01:26:39.698132 arm64_hwcap_cpuinfo_match_SME pass
12140 01:26:39.701208 arm64_hwcap_sigill_SME pass
12141 01:26:39.704788 arm64_hwcap_cpuinfo_match_SVE pass
12142 01:26:39.707725 arm64_hwcap_sigill_SVE pass
12143 01:26:39.711159 arm64_hwcap_cpuinfo_match_SVE_2 pass
12144 01:26:39.714686 arm64_hwcap_sigill_SVE_2 skip
12145 01:26:39.717656 arm64_hwcap_cpuinfo_match_SVE_AES pass
12146 01:26:39.721027 arm64_hwcap_sigill_SVE_AES skip
12147 01:26:39.724117 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
12148 01:26:39.727702 arm64_hwcap_sigill_SVE2_PMULL skip
12149 01:26:39.730892 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
12150 01:26:39.734529 arm64_hwcap_sigill_SVE2_BITPERM skip
12151 01:26:39.737573 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
12152 01:26:39.740731 arm64_hwcap_sigill_SVE2_SHA3 skip
12153 01:26:39.744471 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
12154 01:26:39.747356 arm64_hwcap_sigill_SVE2_SM4 skip
12155 01:26:39.750484 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
12156 01:26:39.754023 arm64_hwcap_sigill_SVE2_I8MM skip
12157 01:26:39.757120 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
12158 01:26:39.760870 arm64_hwcap_sigill_SVE2_F32MM skip
12159 01:26:39.763739 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
12160 01:26:39.767503 arm64_hwcap_sigill_SVE2_F64MM skip
12161 01:26:39.770706 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
12162 01:26:39.773475 arm64_hwcap_sigill_SVE2_BF16 skip
12163 01:26:39.777010 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
12164 01:26:39.780269 arm64_hwcap_sigill_SVE2_EBF16 skip
12165 01:26:39.783601 arm64_hwcap pass
12166 01:26:39.783680 arm64_ptrace_read_tpidr_one pass
12167 01:26:39.786899 arm64_ptrace_write_tpidr_one pass
12168 01:26:39.790387 arm64_ptrace_verify_tpidr_one pass
12169 01:26:39.794023 arm64_ptrace_count_tpidrs pass
12170 01:26:39.796549 arm64_ptrace_tpidr2_write pass
12171 01:26:39.800222 arm64_ptrace_tpidr2_read pass
12172 01:26:39.803722 arm64_ptrace_write_tpidr_only pass
12173 01:26:39.803802 arm64_ptrace pass
12174 01:26:39.806793 arm64_syscall-abi_getpid_FPSIMD pass
12175 01:26:39.810374 arm64_syscall-abi_sched_yield_FPSIMD pass
12176 01:26:39.813268 arm64_syscall-abi pass
12177 01:26:39.816751 arm64_tpidr2_skipped_TPIDR2_not_supported pass
12178 01:26:39.823474 arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 pass
12179 01:26:39.826660 arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 pass
12180 01:26:39.833127 arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 pass
12181 01:26:39.836274 arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 pass
12182 01:26:39.836352 arm64_tpidr2 pass
12183 01:26:39.843098 + ../../utils/send-to-lava.sh ./output/result.txt
12184 01:26:39.846641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
12185 01:26:39.846913 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
12187 01:26:39.853380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
12188 01:26:39.853625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
12190 01:26:39.859849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
12191 01:26:39.860101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
12193 01:26:39.865988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
12194 01:26:39.866236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
12196 01:26:39.883105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
12197 01:26:39.883354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
12199 01:26:39.941420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
12200 01:26:39.941697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
12202 01:26:39.996456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
12203 01:26:39.996715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
12205 01:26:40.052947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
12206 01:26:40.053257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
12208 01:26:40.109655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
12209 01:26:40.109951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
12211 01:26:40.164090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
12212 01:26:40.164364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
12214 01:26:40.218050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
12215 01:26:40.218339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12217 01:26:40.276524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12218 01:26:40.276799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12220 01:26:40.334546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12221 01:26:40.334811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12223 01:26:40.391804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12224 01:26:40.392071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12226 01:26:40.448067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12227 01:26:40.448346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12229 01:26:40.503505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12230 01:26:40.503784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12232 01:26:40.561533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12233 01:26:40.561838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12235 01:26:40.624864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12236 01:26:40.625717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12238 01:26:40.689050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12239 01:26:40.689890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12241 01:26:40.751461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12242 01:26:40.752180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12244 01:26:40.815301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12246 01:26:40.818748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12247 01:26:40.880371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12248 01:26:40.881101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12250 01:26:40.943529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12251 01:26:40.944246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12253 01:26:41.007060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12254 01:26:41.007771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12256 01:26:41.069565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12257 01:26:41.070429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12259 01:26:41.138700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12260 01:26:41.139408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12262 01:26:41.201926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12263 01:26:41.202784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12265 01:26:41.263393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12266 01:26:41.264143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12268 01:26:41.331161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12270 01:26:41.334373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12271 01:26:41.399932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip>
12272 01:26:41.400655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip
12274 01:26:41.453118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12275 01:26:41.453431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12277 01:26:41.504870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip>
12278 01:26:41.505149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip
12280 01:26:41.561210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip>
12281 01:26:41.561493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip
12283 01:26:41.611936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip>
12284 01:26:41.612213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip
12286 01:26:41.668801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip>
12287 01:26:41.669108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip
12289 01:26:41.717731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12290 01:26:41.718034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12292 01:26:41.772136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12293 01:26:41.772415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12295 01:26:41.828084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12296 01:26:41.828359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12298 01:26:41.883056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12299 01:26:41.883330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12301 01:26:41.940096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12302 01:26:41.940376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12304 01:26:41.995141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12305 01:26:41.995418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12307 01:26:42.044453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12308 01:26:42.044754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12310 01:26:42.095237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12311 01:26:42.095558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12313 01:26:42.148233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12314 01:26:42.148559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12316 01:26:42.201233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12317 01:26:42.201568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12319 01:26:42.251521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12320 01:26:42.251818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12322 01:26:42.304708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12324 01:26:42.307741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12325 01:26:42.360731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12327 01:26:42.364026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12328 01:26:42.416232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12329 01:26:42.416501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12331 01:26:42.470234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12332 01:26:42.470528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12334 01:26:42.526237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12335 01:26:42.526508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12337 01:26:42.576230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12338 01:26:42.576507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12340 01:26:42.632358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12341 01:26:42.632639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12343 01:26:42.688630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
12344 01:26:42.688905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
12346 01:26:42.744994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12347 01:26:42.745272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12349 01:26:42.807854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
12350 01:26:42.808127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
12352 01:26:42.860673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12353 01:26:42.860944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12355 01:26:42.916028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12356 01:26:42.916291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12358 01:26:42.974791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip>
12359 01:26:42.975070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip
12361 01:26:43.034924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip>
12362 01:26:43.035199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip
12364 01:26:43.091369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip>
12365 01:26:43.091640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip
12367 01:26:43.143036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip>
12368 01:26:43.143321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip
12370 01:26:43.196511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip>
12371 01:26:43.196795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip
12373 01:26:43.251473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip>
12374 01:26:43.251807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip
12376 01:26:43.303563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip>
12377 01:26:43.303874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip
12379 01:26:43.362255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip>
12380 01:26:43.362531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip
12382 01:26:43.420007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip>
12383 01:26:43.420276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip
12385 01:26:43.475064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12386 01:26:43.475365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12388 01:26:43.535129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip>
12389 01:26:43.535402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip
12391 01:26:43.586911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip>
12392 01:26:43.587168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip
12394 01:26:43.640248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip>
12395 01:26:43.640522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip
12397 01:26:43.697215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip>
12398 01:26:43.697486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip
12400 01:26:43.756798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip>
12401 01:26:43.757099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip
12403 01:26:43.819082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip>
12404 01:26:43.819387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip
12406 01:26:43.882645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip>
12407 01:26:43.882923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip
12409 01:26:43.944489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip>
12410 01:26:43.944787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip
12412 01:26:43.994439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip>
12413 01:26:43.994722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip
12415 01:26:44.047200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12416 01:26:44.047504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12418 01:26:44.109513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12419 01:26:44.109773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12421 01:26:44.170293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12422 01:26:44.170591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12424 01:26:44.227827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
12425 01:26:44.228087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
12427 01:26:44.285634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12428 01:26:44.285944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12430 01:26:44.338849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12431 01:26:44.339148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12433 01:26:44.397631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12434 01:26:44.397918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12436 01:26:44.451351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12438 01:26:44.454417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12439 01:26:44.507840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12440 01:26:44.508114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12442 01:26:44.563711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12443 01:26:44.564006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12445 01:26:44.622867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12446 01:26:44.623137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12448 01:26:44.672987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12449 01:26:44.673258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12451 01:26:44.724978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
12452 01:26:44.725272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
12454 01:26:44.779277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
12455 01:26:44.779548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
12457 01:26:44.839088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12459 01:26:44.841944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12460 01:26:44.897451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12461 01:26:44.897743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12463 01:26:44.958501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12465 01:26:44.961431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12466 01:26:45.016612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12467 01:26:45.016875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12469 01:26:45.078549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12470 01:26:45.078836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12472 01:26:45.137323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12473 01:26:45.137615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12475 01:26:45.194392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12476 01:26:45.194664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12478 01:26:45.252688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12479 01:26:45.252954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12481 01:26:45.313476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12482 01:26:45.313744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12484 01:26:45.368334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12485 01:26:45.368627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12487 01:26:45.423983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12488 01:26:45.424267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12490 01:26:45.482065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12491 01:26:45.482343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12493 01:26:45.540927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12494 01:26:45.541228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12496 01:26:45.596334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12497 01:26:45.596644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12499 01:26:45.651162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12500 01:26:45.651434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12502 01:26:45.705474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12503 01:26:45.705732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12505 01:26:45.763331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12506 01:26:45.763600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12508 01:26:45.823654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12509 01:26:45.823917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12511 01:26:45.886358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12512 01:26:45.886629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12514 01:26:45.945950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12515 01:26:45.946214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12517 01:26:45.999106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12518 01:26:45.999373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12520 01:26:46.057685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12521 01:26:46.057963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12523 01:26:46.112906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12524 01:26:46.113164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12526 01:26:46.170679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12527 01:26:46.170944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12529 01:26:46.231667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12530 01:26:46.232377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12532 01:26:46.296331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12533 01:26:46.297011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12535 01:26:46.359697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12536 01:26:46.360383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12538 01:26:46.425816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12539 01:26:46.426532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12541 01:26:46.491575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12542 01:26:46.492286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12544 01:26:46.559035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12545 01:26:46.559735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12547 01:26:46.622554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12548 01:26:46.623274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12550 01:26:46.683165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12551 01:26:46.683876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12553 01:26:46.750745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12554 01:26:46.751445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12556 01:26:46.815962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12557 01:26:46.816703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12559 01:26:46.885192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12560 01:26:46.885921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12562 01:26:46.954558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12563 01:26:46.955266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12565 01:26:47.017632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12566 01:26:47.018368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12568 01:26:47.078008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12569 01:26:47.078719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12571 01:26:47.146260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12572 01:26:47.146960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12574 01:26:47.214120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12575 01:26:47.214916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12577 01:26:47.276554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12578 01:26:47.276831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12580 01:26:47.329275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12581 01:26:47.329588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12583 01:26:47.389258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12584 01:26:47.389592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12586 01:26:47.445070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12587 01:26:47.445343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12589 01:26:47.509602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12590 01:26:47.509868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12592 01:26:47.561766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12593 01:26:47.562029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12595 01:26:47.621161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12596 01:26:47.621425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12598 01:26:47.675254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12599 01:26:47.675516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12601 01:26:47.732803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12602 01:26:47.733074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12604 01:26:47.788023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12605 01:26:47.788297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12607 01:26:47.847557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12608 01:26:47.847830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12610 01:26:47.901310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12611 01:26:47.901619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12613 01:26:47.958290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12614 01:26:47.958565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12616 01:26:48.009092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12617 01:26:48.009367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12619 01:26:48.059362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12620 01:26:48.059638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12622 01:26:48.116342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12623 01:26:48.116608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12625 01:26:48.175560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12626 01:26:48.175848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12628 01:26:48.222749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12630 01:26:48.226546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12631 01:26:48.279327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12632 01:26:48.279601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12634 01:26:48.331235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12636 01:26:48.334046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12637 01:26:48.395352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12638 01:26:48.395625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12640 01:26:48.449215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12642 01:26:48.452580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12643 01:26:48.509755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12644 01:26:48.510017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12646 01:26:48.563894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12647 01:26:48.564163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12649 01:26:48.624406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12650 01:26:48.624697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12652 01:26:48.686393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12653 01:26:48.686708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12655 01:26:48.749212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12656 01:26:48.749575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12658 01:26:48.797358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12660 01:26:48.800260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12661 01:26:48.861864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12662 01:26:48.862613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12664 01:26:48.929037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12665 01:26:48.929795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12667 01:26:48.994437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12668 01:26:48.995135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12670 01:26:49.055547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12672 01:26:49.058725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12673 01:26:49.121899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12675 01:26:49.124790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12676 01:26:49.195124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12677 01:26:49.195815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12679 01:26:49.252062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12680 01:26:49.252754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12682 01:26:49.315496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12683 01:26:49.316224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12685 01:26:49.382019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12686 01:26:49.382709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12688 01:26:49.446702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12689 01:26:49.447496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12691 01:26:49.512559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12692 01:26:49.513267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12694 01:26:49.580755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12695 01:26:49.581451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12697 01:26:49.650626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12698 01:26:49.651381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12700 01:26:49.716716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12701 01:26:49.716984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12703 01:26:49.774067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12704 01:26:49.774339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12706 01:26:49.829008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass>
12707 01:26:49.829273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass
12709 01:26:49.887908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass>
12710 01:26:49.888175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass
12712 01:26:49.943889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass>
12713 01:26:49.944169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass
12715 01:26:49.998134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass>
12716 01:26:49.998454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass
12718 01:26:50.052989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12719 01:26:50.053114 + set +x
12720 01:26:50.053384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12722 01:26:50.059542 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 13468798_1.6.2.3.5>
12723 01:26:50.059801 Received signal: <ENDRUN> 1_kselftest-arm64 13468798_1.6.2.3.5
12724 01:26:50.059903 Ending use of test pattern.
12725 01:26:50.059980 Ending test lava.1_kselftest-arm64 (13468798_1.6.2.3.5), duration 33.94
12727 01:26:50.062824 <LAVA_TEST_RUNNER EXIT>
12728 01:26:50.063077 ok: lava_test_shell seems to have completed
12729 01:26:50.064162 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_Generic_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled_dup3: skip
arm64_pac_PAUTH_not_enabled_dup4: skip
arm64_pac_PAUTH_not_enabled_dup5: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup3: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup4: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup5: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SME_not_supported_dup10: skip
arm64_vec-syscfg_SME_not_supported_dup2: skip
arm64_vec-syscfg_SME_not_supported_dup3: skip
arm64_vec-syscfg_SME_not_supported_dup4: skip
arm64_vec-syscfg_SME_not_supported_dup5: skip
arm64_vec-syscfg_SME_not_supported_dup6: skip
arm64_vec-syscfg_SME_not_supported_dup7: skip
arm64_vec-syscfg_SME_not_supported_dup8: skip
arm64_vec-syscfg_SME_not_supported_dup9: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_vec-syscfg_SVE_not_supported_dup10: skip
arm64_vec-syscfg_SVE_not_supported_dup2: skip
arm64_vec-syscfg_SVE_not_supported_dup3: skip
arm64_vec-syscfg_SVE_not_supported_dup4: skip
arm64_vec-syscfg_SVE_not_supported_dup5: skip
arm64_vec-syscfg_SVE_not_supported_dup6: skip
arm64_vec-syscfg_SVE_not_supported_dup7: skip
arm64_vec-syscfg_SVE_not_supported_dup8: skip
arm64_vec-syscfg_SVE_not_supported_dup9: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12730 01:26:50.064319 end: 3.1 lava-test-shell (duration 00:00:35) [common]
12731 01:26:50.064409 end: 3 lava-test-retry (duration 00:00:35) [common]
12732 01:26:50.064499 start: 4 finalize (timeout 00:06:52) [common]
12733 01:26:50.064588 start: 4.1 power-off (timeout 00:00:30) [common]
12734 01:26:50.064740 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
12735 01:26:50.140786 >> Command sent successfully.
12736 01:26:50.143097 Returned 0 in 0 seconds
12737 01:26:50.243523 end: 4.1 power-off (duration 00:00:00) [common]
12739 01:26:50.243869 start: 4.2 read-feedback (timeout 00:06:52) [common]
12740 01:26:50.244135 Listened to connection for namespace 'common' for up to 1s
12741 01:26:51.245053 Finalising connection for namespace 'common'
12742 01:26:51.245250 Disconnecting from shell: Finalise
12743 01:26:51.245398 / #
12744 01:26:51.345710 end: 4.2 read-feedback (duration 00:00:01) [common]
12745 01:26:51.345904 end: 4 finalize (duration 00:00:01) [common]
12746 01:26:51.346055 Cleaning after the job
12747 01:26:51.346170 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468798/tftp-deploy-usmeg6ua/ramdisk
12748 01:26:51.348354 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468798/tftp-deploy-usmeg6ua/kernel
12749 01:26:51.358988 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468798/tftp-deploy-usmeg6ua/dtb
12750 01:26:51.359203 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468798/tftp-deploy-usmeg6ua/nfsrootfs
12751 01:26:51.421492 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468798/tftp-deploy-usmeg6ua/modules
12752 01:26:51.427382 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13468798
12753 01:26:51.984539 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13468798
12754 01:26:51.984707 Job finished correctly