Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 25
- Errors: 0
- Kernel Errors: 34
- Boot result: PASS
1 01:21:38.018021 lava-dispatcher, installed at version: 2024.01
2 01:21:38.018253 start: 0 validate
3 01:21:38.018385 Start time: 2024-04-23 01:21:38.018378+00:00 (UTC)
4 01:21:38.018524 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:21:38.018662 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:21:38.274058 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:21:38.274226 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:21:38.527452 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:21:38.527615 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:21:38.781533 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:21:38.781707 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:21:39.037420 Using caching service: 'http://localhost/cache/?uri=%s'
13 01:21:39.037707 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 01:21:39.305906 validate duration: 1.29
16 01:21:39.306284 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:21:39.306440 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:21:39.306577 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:21:39.306752 Not decompressing ramdisk as can be used compressed.
20 01:21:39.306879 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/initrd.cpio.gz
21 01:21:39.306994 saving as /var/lib/lava/dispatcher/tmp/13468790/tftp-deploy-0zi91qtm/ramdisk/initrd.cpio.gz
22 01:21:39.307096 total size: 5628151 (5 MB)
23 01:21:39.311936 progress 0 % (0 MB)
24 01:21:39.314603 progress 5 % (0 MB)
25 01:21:39.317179 progress 10 % (0 MB)
26 01:21:39.319484 progress 15 % (0 MB)
27 01:21:39.322103 progress 20 % (1 MB)
28 01:21:39.324355 progress 25 % (1 MB)
29 01:21:39.326944 progress 30 % (1 MB)
30 01:21:39.329434 progress 35 % (1 MB)
31 01:21:39.331763 progress 40 % (2 MB)
32 01:21:39.334314 progress 45 % (2 MB)
33 01:21:39.336593 progress 50 % (2 MB)
34 01:21:39.339125 progress 55 % (2 MB)
35 01:21:39.341671 progress 60 % (3 MB)
36 01:21:39.343935 progress 65 % (3 MB)
37 01:21:39.346488 progress 70 % (3 MB)
38 01:21:39.348739 progress 75 % (4 MB)
39 01:21:39.350670 progress 80 % (4 MB)
40 01:21:39.352098 progress 85 % (4 MB)
41 01:21:39.353678 progress 90 % (4 MB)
42 01:21:39.355308 progress 95 % (5 MB)
43 01:21:39.356707 progress 100 % (5 MB)
44 01:21:39.356917 5 MB downloaded in 0.05 s (107.73 MB/s)
45 01:21:39.357078 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:21:39.357355 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:21:39.357492 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:21:39.357635 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:21:39.357790 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 01:21:39.357865 saving as /var/lib/lava/dispatcher/tmp/13468790/tftp-deploy-0zi91qtm/kernel/Image
52 01:21:39.357928 total size: 54352384 (51 MB)
53 01:21:39.357990 No compression specified
54 01:21:39.359224 progress 0 % (0 MB)
55 01:21:39.373168 progress 5 % (2 MB)
56 01:21:39.387480 progress 10 % (5 MB)
57 01:21:39.401657 progress 15 % (7 MB)
58 01:21:39.415894 progress 20 % (10 MB)
59 01:21:39.429996 progress 25 % (12 MB)
60 01:21:39.443967 progress 30 % (15 MB)
61 01:21:39.458124 progress 35 % (18 MB)
62 01:21:39.472232 progress 40 % (20 MB)
63 01:21:39.486308 progress 45 % (23 MB)
64 01:21:39.500316 progress 50 % (25 MB)
65 01:21:39.514395 progress 55 % (28 MB)
66 01:21:39.528505 progress 60 % (31 MB)
67 01:21:39.542499 progress 65 % (33 MB)
68 01:21:39.556501 progress 70 % (36 MB)
69 01:21:39.570619 progress 75 % (38 MB)
70 01:21:39.584551 progress 80 % (41 MB)
71 01:21:39.598673 progress 85 % (44 MB)
72 01:21:39.612664 progress 90 % (46 MB)
73 01:21:39.626650 progress 95 % (49 MB)
74 01:21:39.640358 progress 100 % (51 MB)
75 01:21:39.640646 51 MB downloaded in 0.28 s (183.35 MB/s)
76 01:21:39.640812 end: 1.2.1 http-download (duration 00:00:00) [common]
78 01:21:39.641055 end: 1.2 download-retry (duration 00:00:00) [common]
79 01:21:39.641143 start: 1.3 download-retry (timeout 00:10:00) [common]
80 01:21:39.641240 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 01:21:39.641381 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 01:21:39.641452 saving as /var/lib/lava/dispatcher/tmp/13468790/tftp-deploy-0zi91qtm/dtb/mt8192-asurada-spherion-r0.dtb
83 01:21:39.641541 total size: 47230 (0 MB)
84 01:21:39.641621 No compression specified
85 01:21:39.642776 progress 69 % (0 MB)
86 01:21:39.643048 progress 100 % (0 MB)
87 01:21:39.643205 0 MB downloaded in 0.00 s (26.84 MB/s)
88 01:21:39.643337 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:21:39.643560 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:21:39.643646 start: 1.4 download-retry (timeout 00:10:00) [common]
92 01:21:39.643729 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 01:21:39.643853 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/full.rootfs.tar.xz
94 01:21:39.643921 saving as /var/lib/lava/dispatcher/tmp/13468790/tftp-deploy-0zi91qtm/nfsrootfs/full.rootfs.tar
95 01:21:39.643983 total size: 69067788 (65 MB)
96 01:21:39.644045 Using unxz to decompress xz
97 01:21:39.651355 progress 0 % (0 MB)
98 01:21:39.850569 progress 5 % (3 MB)
99 01:21:40.057179 progress 10 % (6 MB)
100 01:21:40.265359 progress 15 % (9 MB)
101 01:21:40.428937 progress 20 % (13 MB)
102 01:21:40.606175 progress 25 % (16 MB)
103 01:21:40.805958 progress 30 % (19 MB)
104 01:21:40.923955 progress 35 % (23 MB)
105 01:21:41.021995 progress 40 % (26 MB)
106 01:21:41.231912 progress 45 % (29 MB)
107 01:21:41.459722 progress 50 % (32 MB)
108 01:21:41.681245 progress 55 % (36 MB)
109 01:21:41.910969 progress 60 % (39 MB)
110 01:21:42.108164 progress 65 % (42 MB)
111 01:21:42.314070 progress 70 % (46 MB)
112 01:21:42.508879 progress 75 % (49 MB)
113 01:21:42.724372 progress 80 % (52 MB)
114 01:21:42.905200 progress 85 % (56 MB)
115 01:21:43.104523 progress 90 % (59 MB)
116 01:21:43.314234 progress 95 % (62 MB)
117 01:21:43.525868 progress 100 % (65 MB)
118 01:21:43.532055 65 MB downloaded in 3.89 s (16.94 MB/s)
119 01:21:43.532308 end: 1.4.1 http-download (duration 00:00:04) [common]
121 01:21:43.532620 end: 1.4 download-retry (duration 00:00:04) [common]
122 01:21:43.532739 start: 1.5 download-retry (timeout 00:09:56) [common]
123 01:21:43.532897 start: 1.5.1 http-download (timeout 00:09:56) [common]
124 01:21:43.533050 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 01:21:43.533124 saving as /var/lib/lava/dispatcher/tmp/13468790/tftp-deploy-0zi91qtm/modules/modules.tar
126 01:21:43.533187 total size: 8638160 (8 MB)
127 01:21:43.533253 Using unxz to decompress xz
128 01:21:43.537625 progress 0 % (0 MB)
129 01:21:43.556459 progress 5 % (0 MB)
130 01:21:43.580901 progress 10 % (0 MB)
131 01:21:43.604915 progress 15 % (1 MB)
132 01:21:43.628298 progress 20 % (1 MB)
133 01:21:43.652895 progress 25 % (2 MB)
134 01:21:43.678440 progress 30 % (2 MB)
135 01:21:43.702359 progress 35 % (2 MB)
136 01:21:43.727527 progress 40 % (3 MB)
137 01:21:43.751513 progress 45 % (3 MB)
138 01:21:43.776743 progress 50 % (4 MB)
139 01:21:43.801910 progress 55 % (4 MB)
140 01:21:43.831183 progress 60 % (4 MB)
141 01:21:43.857214 progress 65 % (5 MB)
142 01:21:43.883487 progress 70 % (5 MB)
143 01:21:43.908884 progress 75 % (6 MB)
144 01:21:43.935210 progress 80 % (6 MB)
145 01:21:43.964462 progress 85 % (7 MB)
146 01:21:43.992186 progress 90 % (7 MB)
147 01:21:44.022825 progress 95 % (7 MB)
148 01:21:44.050620 progress 100 % (8 MB)
149 01:21:44.056690 8 MB downloaded in 0.52 s (15.74 MB/s)
150 01:21:44.056951 end: 1.5.1 http-download (duration 00:00:01) [common]
152 01:21:44.057242 end: 1.5 download-retry (duration 00:00:01) [common]
153 01:21:44.057337 start: 1.6 prepare-tftp-overlay (timeout 00:09:55) [common]
154 01:21:44.057436 start: 1.6.1 extract-nfsrootfs (timeout 00:09:55) [common]
155 01:21:45.671960 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13468790/extract-nfsrootfs-pagiv9fy
156 01:21:45.672160 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 01:21:45.672261 start: 1.6.2 lava-overlay (timeout 00:09:54) [common]
158 01:21:45.672438 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm
159 01:21:45.672571 makedir: /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/bin
160 01:21:45.672675 makedir: /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/tests
161 01:21:45.672776 makedir: /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/results
162 01:21:45.672883 Creating /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/bin/lava-add-keys
163 01:21:45.673024 Creating /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/bin/lava-add-sources
164 01:21:45.673152 Creating /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/bin/lava-background-process-start
165 01:21:45.673282 Creating /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/bin/lava-background-process-stop
166 01:21:45.673415 Creating /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/bin/lava-common-functions
167 01:21:45.673587 Creating /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/bin/lava-echo-ipv4
168 01:21:45.673716 Creating /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/bin/lava-install-packages
169 01:21:45.673841 Creating /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/bin/lava-installed-packages
170 01:21:45.673973 Creating /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/bin/lava-os-build
171 01:21:45.674102 Creating /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/bin/lava-probe-channel
172 01:21:45.674228 Creating /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/bin/lava-probe-ip
173 01:21:45.674354 Creating /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/bin/lava-target-ip
174 01:21:45.674478 Creating /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/bin/lava-target-mac
175 01:21:45.674608 Creating /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/bin/lava-target-storage
176 01:21:45.674734 Creating /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/bin/lava-test-case
177 01:21:45.674859 Creating /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/bin/lava-test-event
178 01:21:45.674982 Creating /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/bin/lava-test-feedback
179 01:21:45.675112 Creating /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/bin/lava-test-raise
180 01:21:45.675235 Creating /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/bin/lava-test-reference
181 01:21:45.675359 Creating /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/bin/lava-test-runner
182 01:21:45.675484 Creating /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/bin/lava-test-set
183 01:21:45.675614 Creating /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/bin/lava-test-shell
184 01:21:45.675739 Updating /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/bin/lava-install-packages (oe)
185 01:21:45.675890 Updating /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/bin/lava-installed-packages (oe)
186 01:21:45.676010 Creating /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/environment
187 01:21:45.676112 LAVA metadata
188 01:21:45.676184 - LAVA_JOB_ID=13468790
189 01:21:45.676249 - LAVA_DISPATCHER_IP=192.168.201.1
190 01:21:45.676348 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:54) [common]
191 01:21:45.676415 skipped lava-vland-overlay
192 01:21:45.676490 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 01:21:45.676568 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:54) [common]
194 01:21:45.676638 skipped lava-multinode-overlay
195 01:21:45.676712 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 01:21:45.676790 start: 1.6.2.3 test-definition (timeout 00:09:54) [common]
197 01:21:45.676864 Loading test definitions
198 01:21:45.676952 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:54) [common]
199 01:21:45.677024 Using /lava-13468790 at stage 0
200 01:21:45.677337 uuid=13468790_1.6.2.3.1 testdef=None
201 01:21:45.677428 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 01:21:45.677614 start: 1.6.2.3.2 test-overlay (timeout 00:09:54) [common]
203 01:21:45.678111 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 01:21:45.678332 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:54) [common]
206 01:21:45.678953 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 01:21:45.679218 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:54) [common]
209 01:21:45.679835 runner path: /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/0/tests/0_lc-compliance test_uuid 13468790_1.6.2.3.1
210 01:21:45.679991 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 01:21:45.680196 Creating lava-test-runner.conf files
213 01:21:45.680266 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13468790/lava-overlay-79ti4dbm/lava-13468790/0 for stage 0
214 01:21:45.680356 - 0_lc-compliance
215 01:21:45.680452 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 01:21:45.680537 start: 1.6.2.4 compress-overlay (timeout 00:09:54) [common]
217 01:21:45.686557 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 01:21:45.686663 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:54) [common]
219 01:21:45.686757 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 01:21:45.686842 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 01:21:45.686927 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:54) [common]
222 01:21:45.853135 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 01:21:45.853546 start: 1.6.4 extract-modules (timeout 00:09:53) [common]
224 01:21:45.853679 extracting modules file /var/lib/lava/dispatcher/tmp/13468790/tftp-deploy-0zi91qtm/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13468790/extract-nfsrootfs-pagiv9fy
225 01:21:46.075150 extracting modules file /var/lib/lava/dispatcher/tmp/13468790/tftp-deploy-0zi91qtm/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13468790/extract-overlay-ramdisk-ym0r_n74/ramdisk
226 01:21:46.300753 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 01:21:46.300920 start: 1.6.5 apply-overlay-tftp (timeout 00:09:53) [common]
228 01:21:46.301013 [common] Applying overlay to NFS
229 01:21:46.301083 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13468790/compress-overlay-v5al_5d1/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13468790/extract-nfsrootfs-pagiv9fy
230 01:21:46.307691 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 01:21:46.307802 start: 1.6.6 configure-preseed-file (timeout 00:09:53) [common]
232 01:21:46.307894 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 01:21:46.307987 start: 1.6.7 compress-ramdisk (timeout 00:09:53) [common]
234 01:21:46.308069 Building ramdisk /var/lib/lava/dispatcher/tmp/13468790/extract-overlay-ramdisk-ym0r_n74/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13468790/extract-overlay-ramdisk-ym0r_n74/ramdisk
235 01:21:46.641261 >> 130624 blocks
236 01:21:48.688311 rename /var/lib/lava/dispatcher/tmp/13468790/extract-overlay-ramdisk-ym0r_n74/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13468790/tftp-deploy-0zi91qtm/ramdisk/ramdisk.cpio.gz
237 01:21:48.688785 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 01:21:48.688938 start: 1.6.8 prepare-kernel (timeout 00:09:51) [common]
239 01:21:48.689060 start: 1.6.8.1 prepare-fit (timeout 00:09:51) [common]
240 01:21:48.689169 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13468790/tftp-deploy-0zi91qtm/kernel/Image'
241 01:22:02.316700 Returned 0 in 13 seconds
242 01:22:02.417346 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13468790/tftp-deploy-0zi91qtm/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13468790/tftp-deploy-0zi91qtm/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13468790/tftp-deploy-0zi91qtm/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13468790/tftp-deploy-0zi91qtm/kernel/image.itb
243 01:22:02.782093 output: FIT description: Kernel Image image with one or more FDT blobs
244 01:22:02.782461 output: Created: Tue Apr 23 02:22:02 2024
245 01:22:02.782542 output: Image 0 (kernel-1)
246 01:22:02.782626 output: Description:
247 01:22:02.782690 output: Created: Tue Apr 23 02:22:02 2024
248 01:22:02.782758 output: Type: Kernel Image
249 01:22:02.782849 output: Compression: lzma compressed
250 01:22:02.782944 output: Data Size: 12910050 Bytes = 12607.47 KiB = 12.31 MiB
251 01:22:02.783044 output: Architecture: AArch64
252 01:22:02.783140 output: OS: Linux
253 01:22:02.783233 output: Load Address: 0x00000000
254 01:22:02.783346 output: Entry Point: 0x00000000
255 01:22:02.783446 output: Hash algo: crc32
256 01:22:02.783554 output: Hash value: 1126c3f9
257 01:22:02.783653 output: Image 1 (fdt-1)
258 01:22:02.783740 output: Description: mt8192-asurada-spherion-r0
259 01:22:02.783836 output: Created: Tue Apr 23 02:22:02 2024
260 01:22:02.783922 output: Type: Flat Device Tree
261 01:22:02.784018 output: Compression: uncompressed
262 01:22:02.784106 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
263 01:22:02.784191 output: Architecture: AArch64
264 01:22:02.784287 output: Hash algo: crc32
265 01:22:02.784373 output: Hash value: 4bf0d1ac
266 01:22:02.784459 output: Image 2 (ramdisk-1)
267 01:22:02.784554 output: Description: unavailable
268 01:22:02.784639 output: Created: Tue Apr 23 02:22:02 2024
269 01:22:02.784742 output: Type: RAMDisk Image
270 01:22:02.784831 output: Compression: Unknown Compression
271 01:22:02.784916 output: Data Size: 18779963 Bytes = 18339.81 KiB = 17.91 MiB
272 01:22:02.785012 output: Architecture: AArch64
273 01:22:02.785097 output: OS: Linux
274 01:22:02.785182 output: Load Address: unavailable
275 01:22:02.785277 output: Entry Point: unavailable
276 01:22:02.785362 output: Hash algo: crc32
277 01:22:02.785455 output: Hash value: 236215db
278 01:22:02.785553 output: Default Configuration: 'conf-1'
279 01:22:02.785638 output: Configuration 0 (conf-1)
280 01:22:02.785733 output: Description: mt8192-asurada-spherion-r0
281 01:22:02.785819 output: Kernel: kernel-1
282 01:22:02.785904 output: Init Ramdisk: ramdisk-1
283 01:22:02.785999 output: FDT: fdt-1
284 01:22:02.786084 output: Loadables: kernel-1
285 01:22:02.786177 output:
286 01:22:02.786435 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
287 01:22:02.786580 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
288 01:22:02.786731 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
289 01:22:02.786859 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:37) [common]
290 01:22:02.786984 No LXC device requested
291 01:22:02.787113 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 01:22:02.787245 start: 1.8 deploy-device-env (timeout 00:09:37) [common]
293 01:22:02.787365 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 01:22:02.787477 Checking files for TFTP limit of 4294967296 bytes.
295 01:22:02.788145 end: 1 tftp-deploy (duration 00:00:23) [common]
296 01:22:02.788286 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 01:22:02.788425 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 01:22:02.788611 substitutions:
299 01:22:02.788687 - {DTB}: 13468790/tftp-deploy-0zi91qtm/dtb/mt8192-asurada-spherion-r0.dtb
300 01:22:02.788754 - {INITRD}: 13468790/tftp-deploy-0zi91qtm/ramdisk/ramdisk.cpio.gz
301 01:22:02.788816 - {KERNEL}: 13468790/tftp-deploy-0zi91qtm/kernel/Image
302 01:22:02.788895 - {LAVA_MAC}: None
303 01:22:02.788958 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13468790/extract-nfsrootfs-pagiv9fy
304 01:22:02.789028 - {NFS_SERVER_IP}: 192.168.201.1
305 01:22:02.789103 - {PRESEED_CONFIG}: None
306 01:22:02.789164 - {PRESEED_LOCAL}: None
307 01:22:02.789225 - {RAMDISK}: 13468790/tftp-deploy-0zi91qtm/ramdisk/ramdisk.cpio.gz
308 01:22:02.789282 - {ROOT_PART}: None
309 01:22:02.789368 - {ROOT}: None
310 01:22:02.789471 - {SERVER_IP}: 192.168.201.1
311 01:22:02.789579 - {TEE}: None
312 01:22:02.789669 Parsed boot commands:
313 01:22:02.789757 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 01:22:02.789993 Parsed boot commands: tftpboot 192.168.201.1 13468790/tftp-deploy-0zi91qtm/kernel/image.itb 13468790/tftp-deploy-0zi91qtm/kernel/cmdline
315 01:22:02.790134 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 01:22:02.790255 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 01:22:02.790394 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 01:22:02.790519 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 01:22:02.790626 Not connected, no need to disconnect.
320 01:22:02.790723 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 01:22:02.790813 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 01:22:02.790919 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
323 01:22:02.794927 Setting prompt string to ['lava-test: # ']
324 01:22:02.795332 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 01:22:02.795488 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 01:22:02.795628 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 01:22:02.795764 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 01:22:02.796085 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
329 01:22:07.927536 >> Command sent successfully.
330 01:22:07.930334 Returned 0 in 5 seconds
331 01:22:08.030742 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 01:22:08.031121 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 01:22:08.031254 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 01:22:08.031417 Setting prompt string to 'Starting depthcharge on Spherion...'
336 01:22:08.031551 Changing prompt to 'Starting depthcharge on Spherion...'
337 01:22:08.031628 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 01:22:08.031898 [Enter `^Ec?' for help]
339 01:22:08.202214
340 01:22:08.202367
341 01:22:08.202445 F0: 102B 0000
342 01:22:08.202512
343 01:22:08.202611 F3: 1001 0000 [0200]
344 01:22:08.205160
345 01:22:08.205243 F3: 1001 0000
346 01:22:08.205309
347 01:22:08.205370 F7: 102D 0000
348 01:22:08.205429
349 01:22:08.208703 F1: 0000 0000
350 01:22:08.208786
351 01:22:08.208852 V0: 0000 0000 [0001]
352 01:22:08.208916
353 01:22:08.211966 00: 0007 8000
354 01:22:08.212056
355 01:22:08.212122 01: 0000 0000
356 01:22:08.212186
357 01:22:08.214965 BP: 0C00 0209 [0000]
358 01:22:08.215048
359 01:22:08.215114 G0: 1182 0000
360 01:22:08.215176
361 01:22:08.219088 EC: 0000 0021 [4000]
362 01:22:08.219171
363 01:22:08.219236 S7: 0000 0000 [0000]
364 01:22:08.219298
365 01:22:08.222699 CC: 0000 0000 [0001]
366 01:22:08.222782
367 01:22:08.222848 T0: 0000 0040 [010F]
368 01:22:08.222910
369 01:22:08.222969 Jump to BL
370 01:22:08.225882
371 01:22:08.249305
372 01:22:08.249391
373 01:22:08.249457
374 01:22:08.256499 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 01:22:08.260054 ARM64: Exception handlers installed.
376 01:22:08.263367 ARM64: Testing exception
377 01:22:08.266455 ARM64: Done test exception
378 01:22:08.273427 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 01:22:08.283775 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 01:22:08.290084 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 01:22:08.300186 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 01:22:08.306935 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 01:22:08.313475 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 01:22:08.326225 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 01:22:08.332429 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 01:22:08.352207 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 01:22:08.355247 WDT: Last reset was cold boot
388 01:22:08.358387 SPI1(PAD0) initialized at 2873684 Hz
389 01:22:08.362142 SPI5(PAD0) initialized at 992727 Hz
390 01:22:08.365224 VBOOT: Loading verstage.
391 01:22:08.371710 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 01:22:08.375224 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 01:22:08.378573 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 01:22:08.381645 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 01:22:08.389651 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 01:22:08.395727 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 01:22:08.406823 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
398 01:22:08.406912
399 01:22:08.406979
400 01:22:08.417197 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 01:22:08.420258 ARM64: Exception handlers installed.
402 01:22:08.423821 ARM64: Testing exception
403 01:22:08.423909 ARM64: Done test exception
404 01:22:08.430452 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 01:22:08.433388 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 01:22:08.447572 Probing TPM: . done!
407 01:22:08.447659 TPM ready after 0 ms
408 01:22:08.454463 Connected to device vid:did:rid of 1ae0:0028:00
409 01:22:08.502480 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
410 01:22:08.502597 Initialized TPM device CR50 revision 0
411 01:22:08.514514 tlcl_send_startup: Startup return code is 0
412 01:22:08.514615 TPM: setup succeeded
413 01:22:08.526177 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 01:22:08.535056 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 01:22:08.546570 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 01:22:08.556635 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 01:22:08.560104 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 01:22:08.563759 in-header: 03 07 00 00 08 00 00 00
419 01:22:08.567472 in-data: aa e4 47 04 13 02 00 00
420 01:22:08.571364 Chrome EC: UHEPI supported
421 01:22:08.574335 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 01:22:08.579230 in-header: 03 9d 00 00 08 00 00 00
423 01:22:08.583056 in-data: 10 20 20 08 00 00 00 00
424 01:22:08.583140 Phase 1
425 01:22:08.590471 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 01:22:08.593966 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 01:22:08.601354 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 01:22:08.601441 Recovery requested (1009000e)
429 01:22:08.610274 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 01:22:08.615861 tlcl_extend: response is 0
431 01:22:08.624063 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 01:22:08.629312 tlcl_extend: response is 0
433 01:22:08.635734 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 01:22:08.657221 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
435 01:22:08.664111 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 01:22:08.664204
437 01:22:08.664272
438 01:22:08.675052 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 01:22:08.675142 ARM64: Exception handlers installed.
440 01:22:08.679375 ARM64: Testing exception
441 01:22:08.682537 ARM64: Done test exception
442 01:22:08.702451 pmic_efuse_setting: Set efuses in 11 msecs
443 01:22:08.706186 pmwrap_interface_init: Select PMIF_VLD_RDY
444 01:22:08.709898 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 01:22:08.717094 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 01:22:08.720628 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 01:22:08.724245 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 01:22:08.731449 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 01:22:08.735564 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 01:22:08.739075 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 01:22:08.745715 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 01:22:08.749185 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 01:22:08.752439 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 01:22:08.759133 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 01:22:08.762599 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 01:22:08.769382 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 01:22:08.772711 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 01:22:08.779464 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 01:22:08.785968 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 01:22:08.792196 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 01:22:08.795943 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 01:22:08.802484 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 01:22:08.810109 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 01:22:08.813626 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 01:22:08.817366 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 01:22:08.824335 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 01:22:08.831305 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 01:22:08.835118 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 01:22:08.841501 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 01:22:08.845324 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 01:22:08.852921 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 01:22:08.856065 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 01:22:08.859348 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 01:22:08.866895 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 01:22:08.870354 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 01:22:08.877461 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 01:22:08.881391 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 01:22:08.885494 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 01:22:08.892102 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 01:22:08.895746 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 01:22:08.902462 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 01:22:08.905434 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 01:22:08.909246 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 01:22:08.915590 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 01:22:08.919209 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 01:22:08.922368 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 01:22:08.925480 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 01:22:08.932333 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 01:22:08.935319 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 01:22:08.939058 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 01:22:08.945777 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 01:22:08.948867 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 01:22:08.951927 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 01:22:08.955697 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 01:22:08.965555 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 01:22:08.972208 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 01:22:08.978688 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 01:22:08.985095 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 01:22:08.995574 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 01:22:08.998874 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 01:22:09.001789 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 01:22:09.008600 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 01:22:09.015315 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x15
504 01:22:09.021826 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 01:22:09.025520 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
506 01:22:09.028502 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 01:22:09.039509 [RTC]rtc_get_frequency_meter,154: input=15, output=793
508 01:22:09.042735 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
509 01:22:09.049342 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
510 01:22:09.052481 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
511 01:22:09.055576 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
512 01:22:09.059287 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
513 01:22:09.062503 ADC[4]: Raw value=896300 ID=7
514 01:22:09.065573 ADC[3]: Raw value=213440 ID=1
515 01:22:09.065679 RAM Code: 0x71
516 01:22:09.072493 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
517 01:22:09.075381 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
518 01:22:09.085403 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
519 01:22:09.093276 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
520 01:22:09.096368 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
521 01:22:09.099447 in-header: 03 07 00 00 08 00 00 00
522 01:22:09.103018 in-data: aa e4 47 04 13 02 00 00
523 01:22:09.106151 Chrome EC: UHEPI supported
524 01:22:09.109629 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
525 01:22:09.113927 in-header: 03 d5 00 00 08 00 00 00
526 01:22:09.117251 in-data: 98 20 60 08 00 00 00 00
527 01:22:09.121389 MRC: failed to locate region type 0.
528 01:22:09.128521 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
529 01:22:09.132136 DRAM-K: Running full calibration
530 01:22:09.135714 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
531 01:22:09.139912 header.status = 0x0
532 01:22:09.143023 header.version = 0x6 (expected: 0x6)
533 01:22:09.146655 header.size = 0xd00 (expected: 0xd00)
534 01:22:09.146739 header.flags = 0x0
535 01:22:09.153394 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
536 01:22:09.172226 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
537 01:22:09.179487 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
538 01:22:09.179572 dram_init: ddr_geometry: 2
539 01:22:09.183069 [EMI] MDL number = 2
540 01:22:09.186537 [EMI] Get MDL freq = 0
541 01:22:09.186623 dram_init: ddr_type: 0
542 01:22:09.190825 is_discrete_lpddr4: 1
543 01:22:09.194249 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
544 01:22:09.194362
545 01:22:09.194462
546 01:22:09.194525 [Bian_co] ETT version 0.0.0.1
547 01:22:09.201949 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
548 01:22:09.202033
549 01:22:09.205515 dramc_set_vcore_voltage set vcore to 650000
550 01:22:09.205612 Read voltage for 800, 4
551 01:22:09.205678 Vio18 = 0
552 01:22:09.209080 Vcore = 650000
553 01:22:09.209204 Vdram = 0
554 01:22:09.209299 Vddq = 0
555 01:22:09.212587 Vmddr = 0
556 01:22:09.212701 dram_init: config_dvfs: 1
557 01:22:09.220790 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
558 01:22:09.224306 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
559 01:22:09.228500 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
560 01:22:09.232341 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
561 01:22:09.235681 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
562 01:22:09.238837 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
563 01:22:09.242352 MEM_TYPE=3, freq_sel=18
564 01:22:09.245741 sv_algorithm_assistance_LP4_1600
565 01:22:09.248973 ============ PULL DRAM RESETB DOWN ============
566 01:22:09.252367 ========== PULL DRAM RESETB DOWN end =========
567 01:22:09.255491 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
568 01:22:09.258826 ===================================
569 01:22:09.262474 LPDDR4 DRAM CONFIGURATION
570 01:22:09.265582 ===================================
571 01:22:09.269214 EX_ROW_EN[0] = 0x0
572 01:22:09.269299 EX_ROW_EN[1] = 0x0
573 01:22:09.272426 LP4Y_EN = 0x0
574 01:22:09.272519 WORK_FSP = 0x0
575 01:22:09.275426 WL = 0x2
576 01:22:09.275511 RL = 0x2
577 01:22:09.279054 BL = 0x2
578 01:22:09.279150 RPST = 0x0
579 01:22:09.282384 RD_PRE = 0x0
580 01:22:09.285331 WR_PRE = 0x1
581 01:22:09.285415 WR_PST = 0x0
582 01:22:09.288957 DBI_WR = 0x0
583 01:22:09.289042 DBI_RD = 0x0
584 01:22:09.292209 OTF = 0x1
585 01:22:09.295217 ===================================
586 01:22:09.299096 ===================================
587 01:22:09.299181 ANA top config
588 01:22:09.301934 ===================================
589 01:22:09.305489 DLL_ASYNC_EN = 0
590 01:22:09.305587 ALL_SLAVE_EN = 1
591 01:22:09.308901 NEW_RANK_MODE = 1
592 01:22:09.312366 DLL_IDLE_MODE = 1
593 01:22:09.315374 LP45_APHY_COMB_EN = 1
594 01:22:09.319097 TX_ODT_DIS = 1
595 01:22:09.319182 NEW_8X_MODE = 1
596 01:22:09.322128 ===================================
597 01:22:09.325301 ===================================
598 01:22:09.328888 data_rate = 1600
599 01:22:09.331915 CKR = 1
600 01:22:09.335733 DQ_P2S_RATIO = 8
601 01:22:09.338638 ===================================
602 01:22:09.342400 CA_P2S_RATIO = 8
603 01:22:09.345352 DQ_CA_OPEN = 0
604 01:22:09.345437 DQ_SEMI_OPEN = 0
605 01:22:09.348447 CA_SEMI_OPEN = 0
606 01:22:09.351977 CA_FULL_RATE = 0
607 01:22:09.355616 DQ_CKDIV4_EN = 1
608 01:22:09.358439 CA_CKDIV4_EN = 1
609 01:22:09.361752 CA_PREDIV_EN = 0
610 01:22:09.361841 PH8_DLY = 0
611 01:22:09.365318 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
612 01:22:09.368575 DQ_AAMCK_DIV = 4
613 01:22:09.371651 CA_AAMCK_DIV = 4
614 01:22:09.375470 CA_ADMCK_DIV = 4
615 01:22:09.378670 DQ_TRACK_CA_EN = 0
616 01:22:09.378749 CA_PICK = 800
617 01:22:09.381723 CA_MCKIO = 800
618 01:22:09.385318 MCKIO_SEMI = 0
619 01:22:09.388405 PLL_FREQ = 3068
620 01:22:09.392144 DQ_UI_PI_RATIO = 32
621 01:22:09.395098 CA_UI_PI_RATIO = 0
622 01:22:09.398627 ===================================
623 01:22:09.401827 ===================================
624 01:22:09.401912 memory_type:LPDDR4
625 01:22:09.404858 GP_NUM : 10
626 01:22:09.408413 SRAM_EN : 1
627 01:22:09.408508 MD32_EN : 0
628 01:22:09.411416 ===================================
629 01:22:09.415015 [ANA_INIT] >>>>>>>>>>>>>>
630 01:22:09.418565 <<<<<< [CONFIGURE PHASE]: ANA_TX
631 01:22:09.421427 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
632 01:22:09.424831 ===================================
633 01:22:09.428522 data_rate = 1600,PCW = 0X7600
634 01:22:09.431643 ===================================
635 01:22:09.435281 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
636 01:22:09.438375 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
637 01:22:09.445124 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
638 01:22:09.448785 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
639 01:22:09.452495 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
640 01:22:09.456259 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
641 01:22:09.459837 [ANA_INIT] flow start
642 01:22:09.459917 [ANA_INIT] PLL >>>>>>>>
643 01:22:09.464147 [ANA_INIT] PLL <<<<<<<<
644 01:22:09.464224 [ANA_INIT] MIDPI >>>>>>>>
645 01:22:09.467585 [ANA_INIT] MIDPI <<<<<<<<
646 01:22:09.471592 [ANA_INIT] DLL >>>>>>>>
647 01:22:09.471698 [ANA_INIT] flow end
648 01:22:09.475279 ============ LP4 DIFF to SE enter ============
649 01:22:09.478574 ============ LP4 DIFF to SE exit ============
650 01:22:09.482528 [ANA_INIT] <<<<<<<<<<<<<
651 01:22:09.486078 [Flow] Enable top DCM control >>>>>
652 01:22:09.490018 [Flow] Enable top DCM control <<<<<
653 01:22:09.493094 Enable DLL master slave shuffle
654 01:22:09.497391 ==============================================================
655 01:22:09.500589 Gating Mode config
656 01:22:09.504124 ==============================================================
657 01:22:09.507662 Config description:
658 01:22:09.515429 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
659 01:22:09.522149 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
660 01:22:09.526492 SELPH_MODE 0: By rank 1: By Phase
661 01:22:09.533934 ==============================================================
662 01:22:09.537380 GAT_TRACK_EN = 1
663 01:22:09.541067 RX_GATING_MODE = 2
664 01:22:09.541169 RX_GATING_TRACK_MODE = 2
665 01:22:09.544795 SELPH_MODE = 1
666 01:22:09.548591 PICG_EARLY_EN = 1
667 01:22:09.552321 VALID_LAT_VALUE = 1
668 01:22:09.555953 ==============================================================
669 01:22:09.559976 Enter into Gating configuration >>>>
670 01:22:09.563579 Exit from Gating configuration <<<<
671 01:22:09.567763 Enter into DVFS_PRE_config >>>>>
672 01:22:09.578767 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
673 01:22:09.582523 Exit from DVFS_PRE_config <<<<<
674 01:22:09.585404 Enter into PICG configuration >>>>
675 01:22:09.585520 Exit from PICG configuration <<<<
676 01:22:09.588586 [RX_INPUT] configuration >>>>>
677 01:22:09.592250 [RX_INPUT] configuration <<<<<
678 01:22:09.598773 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
679 01:22:09.602255 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
680 01:22:09.608720 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
681 01:22:09.615340 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
682 01:22:09.622450 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
683 01:22:09.629343 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
684 01:22:09.632486 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
685 01:22:09.635483 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
686 01:22:09.638951 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
687 01:22:09.645697 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
688 01:22:09.648982 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
689 01:22:09.652084 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
690 01:22:09.655719 ===================================
691 01:22:09.658734 LPDDR4 DRAM CONFIGURATION
692 01:22:09.662314 ===================================
693 01:22:09.665502 EX_ROW_EN[0] = 0x0
694 01:22:09.665599 EX_ROW_EN[1] = 0x0
695 01:22:09.668656 LP4Y_EN = 0x0
696 01:22:09.668730 WORK_FSP = 0x0
697 01:22:09.672323 WL = 0x2
698 01:22:09.672434 RL = 0x2
699 01:22:09.675400 BL = 0x2
700 01:22:09.675485 RPST = 0x0
701 01:22:09.679074 RD_PRE = 0x0
702 01:22:09.679153 WR_PRE = 0x1
703 01:22:09.682286 WR_PST = 0x0
704 01:22:09.682370 DBI_WR = 0x0
705 01:22:09.685115 DBI_RD = 0x0
706 01:22:09.685227 OTF = 0x1
707 01:22:09.688653 ===================================
708 01:22:09.695380 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
709 01:22:09.698437 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
710 01:22:09.702079 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
711 01:22:09.705109 ===================================
712 01:22:09.708675 LPDDR4 DRAM CONFIGURATION
713 01:22:09.711590 ===================================
714 01:22:09.711705 EX_ROW_EN[0] = 0x10
715 01:22:09.715604 EX_ROW_EN[1] = 0x0
716 01:22:09.718680 LP4Y_EN = 0x0
717 01:22:09.718766 WORK_FSP = 0x0
718 01:22:09.722009 WL = 0x2
719 01:22:09.722094 RL = 0x2
720 01:22:09.725022 BL = 0x2
721 01:22:09.725107 RPST = 0x0
722 01:22:09.728252 RD_PRE = 0x0
723 01:22:09.728337 WR_PRE = 0x1
724 01:22:09.731965 WR_PST = 0x0
725 01:22:09.732050 DBI_WR = 0x0
726 01:22:09.734960 DBI_RD = 0x0
727 01:22:09.735044 OTF = 0x1
728 01:22:09.738242 ===================================
729 01:22:09.744855 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
730 01:22:09.749252 nWR fixed to 40
731 01:22:09.752801 [ModeRegInit_LP4] CH0 RK0
732 01:22:09.752886 [ModeRegInit_LP4] CH0 RK1
733 01:22:09.756099 [ModeRegInit_LP4] CH1 RK0
734 01:22:09.759227 [ModeRegInit_LP4] CH1 RK1
735 01:22:09.759312 match AC timing 13
736 01:22:09.766451 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
737 01:22:09.769357 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
738 01:22:09.772645 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
739 01:22:09.779193 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
740 01:22:09.782754 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
741 01:22:09.782838 [EMI DOE] emi_dcm 0
742 01:22:09.789679 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
743 01:22:09.789762 ==
744 01:22:09.792615 Dram Type= 6, Freq= 0, CH_0, rank 0
745 01:22:09.795700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
746 01:22:09.795784 ==
747 01:22:09.802495 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
748 01:22:09.809282 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
749 01:22:09.817217 [CA 0] Center 38 (7~69) winsize 63
750 01:22:09.820167 [CA 1] Center 38 (7~69) winsize 63
751 01:22:09.823660 [CA 2] Center 35 (5~66) winsize 62
752 01:22:09.826930 [CA 3] Center 35 (5~66) winsize 62
753 01:22:09.830476 [CA 4] Center 34 (4~65) winsize 62
754 01:22:09.834109 [CA 5] Center 34 (4~65) winsize 62
755 01:22:09.834197
756 01:22:09.836905 [CmdBusTrainingLP45] Vref(ca) range 1: 34
757 01:22:09.837010
758 01:22:09.840694 [CATrainingPosCal] consider 1 rank data
759 01:22:09.843872 u2DelayCellTimex100 = 270/100 ps
760 01:22:09.846932 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
761 01:22:09.850502 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
762 01:22:09.853701 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
763 01:22:09.860530 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
764 01:22:09.864126 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
765 01:22:09.867563 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
766 01:22:09.867649
767 01:22:09.870794 CA PerBit enable=1, Macro0, CA PI delay=34
768 01:22:09.870869
769 01:22:09.873846 [CBTSetCACLKResult] CA Dly = 34
770 01:22:09.873957 CS Dly: 6 (0~37)
771 01:22:09.874059 ==
772 01:22:09.877432 Dram Type= 6, Freq= 0, CH_0, rank 1
773 01:22:09.884191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 01:22:09.884277 ==
775 01:22:09.887167 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
776 01:22:09.893841 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
777 01:22:09.903489 [CA 0] Center 38 (7~69) winsize 63
778 01:22:09.906657 [CA 1] Center 37 (7~68) winsize 62
779 01:22:09.909749 [CA 2] Center 35 (5~66) winsize 62
780 01:22:09.913478 [CA 3] Center 35 (5~66) winsize 62
781 01:22:09.916556 [CA 4] Center 34 (4~65) winsize 62
782 01:22:09.919707 [CA 5] Center 34 (4~65) winsize 62
783 01:22:09.919809
784 01:22:09.922929 [CmdBusTrainingLP45] Vref(ca) range 1: 30
785 01:22:09.923008
786 01:22:09.926740 [CATrainingPosCal] consider 2 rank data
787 01:22:09.929788 u2DelayCellTimex100 = 270/100 ps
788 01:22:09.933303 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
789 01:22:09.936687 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
790 01:22:09.943619 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
791 01:22:09.946445 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
792 01:22:09.949771 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
793 01:22:09.953196 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
794 01:22:09.953305
795 01:22:09.956451 CA PerBit enable=1, Macro0, CA PI delay=34
796 01:22:09.956535
797 01:22:09.959629 [CBTSetCACLKResult] CA Dly = 34
798 01:22:09.959714 CS Dly: 6 (0~37)
799 01:22:09.959799
800 01:22:09.963158 ----->DramcWriteLeveling(PI) begin...
801 01:22:09.966253 ==
802 01:22:09.970053 Dram Type= 6, Freq= 0, CH_0, rank 0
803 01:22:09.973064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 01:22:09.973188 ==
805 01:22:09.976557 Write leveling (Byte 0): 31 => 31
806 01:22:09.979589 Write leveling (Byte 1): 29 => 29
807 01:22:09.982911 DramcWriteLeveling(PI) end<-----
808 01:22:09.983007
809 01:22:09.983072 ==
810 01:22:09.986431 Dram Type= 6, Freq= 0, CH_0, rank 0
811 01:22:09.989707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
812 01:22:09.989818 ==
813 01:22:09.993019 [Gating] SW mode calibration
814 01:22:10.000021 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
815 01:22:10.002905 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
816 01:22:10.009860 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
817 01:22:10.012864 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
818 01:22:10.016041 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
819 01:22:10.022993 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
820 01:22:10.026106 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 01:22:10.029692 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 01:22:10.036484 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 01:22:10.039689 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 01:22:10.043022 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 01:22:10.049664 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 01:22:10.052714 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 01:22:10.056566 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 01:22:10.062985 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 01:22:10.066149 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 01:22:10.069495 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 01:22:10.076290 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 01:22:10.079884 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 01:22:10.083664 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 01:22:10.086900 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
835 01:22:10.091110 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
836 01:22:10.098321 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 01:22:10.101306 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 01:22:10.104665 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 01:22:10.111725 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 01:22:10.115076 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 01:22:10.118610 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 01:22:10.121779 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 01:22:10.128554 0 9 12 | B1->B0 | 2727 3333 | 1 1 | (0 0) (1 1)
844 01:22:10.132173 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
845 01:22:10.135278 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
846 01:22:10.142213 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
847 01:22:10.145115 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
848 01:22:10.148719 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
849 01:22:10.155301 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
850 01:22:10.158326 0 10 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
851 01:22:10.161980 0 10 12 | B1->B0 | 2e2e 2424 | 0 0 | (1 1) (1 1)
852 01:22:10.168505 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 01:22:10.171607 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 01:22:10.175437 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 01:22:10.181917 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 01:22:10.185414 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 01:22:10.188669 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 01:22:10.195286 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 01:22:10.198251 0 11 12 | B1->B0 | 3434 4141 | 0 0 | (0 0) (0 0)
860 01:22:10.201864 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
861 01:22:10.204874 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
862 01:22:10.212155 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 01:22:10.214886 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 01:22:10.218313 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 01:22:10.224936 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 01:22:10.228187 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 01:22:10.231843 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
868 01:22:10.238542 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
869 01:22:10.241744 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
870 01:22:10.244979 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 01:22:10.251650 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 01:22:10.255171 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 01:22:10.258278 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 01:22:10.264844 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 01:22:10.268364 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 01:22:10.271372 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 01:22:10.278032 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 01:22:10.281673 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 01:22:10.284832 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 01:22:10.291457 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 01:22:10.294972 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 01:22:10.298468 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 01:22:10.305000 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
884 01:22:10.308271 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
885 01:22:10.311746 Total UI for P1: 0, mck2ui 16
886 01:22:10.314870 best dqsien dly found for B0: ( 0, 14, 12)
887 01:22:10.318516 Total UI for P1: 0, mck2ui 16
888 01:22:10.321464 best dqsien dly found for B1: ( 0, 14, 12)
889 01:22:10.324514 best DQS0 dly(MCK, UI, PI) = (0, 14, 12)
890 01:22:10.328047 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
891 01:22:10.328155
892 01:22:10.331467 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 12)
893 01:22:10.334781 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
894 01:22:10.338094 [Gating] SW calibration Done
895 01:22:10.338178 ==
896 01:22:10.341781 Dram Type= 6, Freq= 0, CH_0, rank 0
897 01:22:10.344667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
898 01:22:10.344750 ==
899 01:22:10.348319 RX Vref Scan: 0
900 01:22:10.348405
901 01:22:10.351418 RX Vref 0 -> 0, step: 1
902 01:22:10.351507
903 01:22:10.351591 RX Delay -130 -> 252, step: 16
904 01:22:10.358207 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
905 01:22:10.361798 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
906 01:22:10.364876 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
907 01:22:10.368688 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
908 01:22:10.371736 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
909 01:22:10.378555 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
910 01:22:10.381607 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
911 01:22:10.385336 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
912 01:22:10.388464 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
913 01:22:10.391542 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
914 01:22:10.398241 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
915 01:22:10.401330 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
916 01:22:10.405070 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
917 01:22:10.408099 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
918 01:22:10.411495 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
919 01:22:10.418225 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
920 01:22:10.418317 ==
921 01:22:10.421747 Dram Type= 6, Freq= 0, CH_0, rank 0
922 01:22:10.424888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
923 01:22:10.424974 ==
924 01:22:10.425039 DQS Delay:
925 01:22:10.427752 DQS0 = 0, DQS1 = 0
926 01:22:10.427856 DQM Delay:
927 01:22:10.431119 DQM0 = 80, DQM1 = 69
928 01:22:10.431225 DQ Delay:
929 01:22:10.434599 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
930 01:22:10.438154 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
931 01:22:10.441235 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
932 01:22:10.444637 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
933 01:22:10.444719
934 01:22:10.444807
935 01:22:10.444909 ==
936 01:22:10.448022 Dram Type= 6, Freq= 0, CH_0, rank 0
937 01:22:10.451634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
938 01:22:10.451713 ==
939 01:22:10.454961
940 01:22:10.455040
941 01:22:10.455125 TX Vref Scan disable
942 01:22:10.457837 == TX Byte 0 ==
943 01:22:10.461680 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
944 01:22:10.464734 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
945 01:22:10.468407 == TX Byte 1 ==
946 01:22:10.471195 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
947 01:22:10.475060 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
948 01:22:10.475146 ==
949 01:22:10.477872 Dram Type= 6, Freq= 0, CH_0, rank 0
950 01:22:10.484547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
951 01:22:10.484634 ==
952 01:22:10.496464 TX Vref=22, minBit 0, minWin=27, winSum=434
953 01:22:10.500299 TX Vref=24, minBit 0, minWin=27, winSum=439
954 01:22:10.504121 TX Vref=26, minBit 14, minWin=26, winSum=442
955 01:22:10.507732 TX Vref=28, minBit 4, minWin=27, winSum=443
956 01:22:10.510975 TX Vref=30, minBit 10, minWin=27, winSum=443
957 01:22:10.514026 TX Vref=32, minBit 9, minWin=27, winSum=441
958 01:22:10.520752 [TxChooseVref] Worse bit 4, Min win 27, Win sum 443, Final Vref 28
959 01:22:10.520863
960 01:22:10.524274 Final TX Range 1 Vref 28
961 01:22:10.524356
962 01:22:10.524440 ==
963 01:22:10.527213 Dram Type= 6, Freq= 0, CH_0, rank 0
964 01:22:10.530655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
965 01:22:10.530737 ==
966 01:22:10.530826
967 01:22:10.530905
968 01:22:10.533953 TX Vref Scan disable
969 01:22:10.537315 == TX Byte 0 ==
970 01:22:10.540552 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
971 01:22:10.543845 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
972 01:22:10.547751 == TX Byte 1 ==
973 01:22:10.550864 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
974 01:22:10.553895 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
975 01:22:10.554005
976 01:22:10.557604 [DATLAT]
977 01:22:10.557693 Freq=800, CH0 RK0
978 01:22:10.557808
979 01:22:10.560480 DATLAT Default: 0xa
980 01:22:10.560562 0, 0xFFFF, sum = 0
981 01:22:10.564162 1, 0xFFFF, sum = 0
982 01:22:10.564250 2, 0xFFFF, sum = 0
983 01:22:10.567785 3, 0xFFFF, sum = 0
984 01:22:10.567873 4, 0xFFFF, sum = 0
985 01:22:10.570786 5, 0xFFFF, sum = 0
986 01:22:10.570889 6, 0xFFFF, sum = 0
987 01:22:10.574469 7, 0xFFFF, sum = 0
988 01:22:10.574549 8, 0xFFFF, sum = 0
989 01:22:10.577394 9, 0x0, sum = 1
990 01:22:10.577502 10, 0x0, sum = 2
991 01:22:10.580729 11, 0x0, sum = 3
992 01:22:10.580813 12, 0x0, sum = 4
993 01:22:10.584020 best_step = 10
994 01:22:10.584159
995 01:22:10.584259 ==
996 01:22:10.587700 Dram Type= 6, Freq= 0, CH_0, rank 0
997 01:22:10.590681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
998 01:22:10.590765 ==
999 01:22:10.590849 RX Vref Scan: 1
1000 01:22:10.594332
1001 01:22:10.594412 Set Vref Range= 32 -> 127
1002 01:22:10.594498
1003 01:22:10.597594 RX Vref 32 -> 127, step: 1
1004 01:22:10.597699
1005 01:22:10.600599 RX Delay -111 -> 252, step: 8
1006 01:22:10.600691
1007 01:22:10.604429 Set Vref, RX VrefLevel [Byte0]: 32
1008 01:22:10.607400 [Byte1]: 32
1009 01:22:10.607505
1010 01:22:10.611160 Set Vref, RX VrefLevel [Byte0]: 33
1011 01:22:10.614053 [Byte1]: 33
1012 01:22:10.617148
1013 01:22:10.617233 Set Vref, RX VrefLevel [Byte0]: 34
1014 01:22:10.620717 [Byte1]: 34
1015 01:22:10.625131
1016 01:22:10.625215 Set Vref, RX VrefLevel [Byte0]: 35
1017 01:22:10.628203 [Byte1]: 35
1018 01:22:10.632652
1019 01:22:10.632732 Set Vref, RX VrefLevel [Byte0]: 36
1020 01:22:10.635790 [Byte1]: 36
1021 01:22:10.640204
1022 01:22:10.640322 Set Vref, RX VrefLevel [Byte0]: 37
1023 01:22:10.643670 [Byte1]: 37
1024 01:22:10.648309
1025 01:22:10.648429 Set Vref, RX VrefLevel [Byte0]: 38
1026 01:22:10.651244 [Byte1]: 38
1027 01:22:10.655513
1028 01:22:10.655636 Set Vref, RX VrefLevel [Byte0]: 39
1029 01:22:10.659031 [Byte1]: 39
1030 01:22:10.662937
1031 01:22:10.663033 Set Vref, RX VrefLevel [Byte0]: 40
1032 01:22:10.666707 [Byte1]: 40
1033 01:22:10.671145
1034 01:22:10.671238 Set Vref, RX VrefLevel [Byte0]: 41
1035 01:22:10.674130 [Byte1]: 41
1036 01:22:10.678293
1037 01:22:10.678387 Set Vref, RX VrefLevel [Byte0]: 42
1038 01:22:10.681939 [Byte1]: 42
1039 01:22:10.686091
1040 01:22:10.686170 Set Vref, RX VrefLevel [Byte0]: 43
1041 01:22:10.689484 [Byte1]: 43
1042 01:22:10.693742
1043 01:22:10.693828 Set Vref, RX VrefLevel [Byte0]: 44
1044 01:22:10.697397 [Byte1]: 44
1045 01:22:10.701842
1046 01:22:10.701926 Set Vref, RX VrefLevel [Byte0]: 45
1047 01:22:10.704892 [Byte1]: 45
1048 01:22:10.709212
1049 01:22:10.709296 Set Vref, RX VrefLevel [Byte0]: 46
1050 01:22:10.712237 [Byte1]: 46
1051 01:22:10.716521
1052 01:22:10.716639 Set Vref, RX VrefLevel [Byte0]: 47
1053 01:22:10.720308 [Byte1]: 47
1054 01:22:10.724539
1055 01:22:10.724619 Set Vref, RX VrefLevel [Byte0]: 48
1056 01:22:10.727643 [Byte1]: 48
1057 01:22:10.732143
1058 01:22:10.732231 Set Vref, RX VrefLevel [Byte0]: 49
1059 01:22:10.735205 [Byte1]: 49
1060 01:22:10.739872
1061 01:22:10.739959 Set Vref, RX VrefLevel [Byte0]: 50
1062 01:22:10.742958 [Byte1]: 50
1063 01:22:10.747490
1064 01:22:10.747579 Set Vref, RX VrefLevel [Byte0]: 51
1065 01:22:10.750628 [Byte1]: 51
1066 01:22:10.754959
1067 01:22:10.755045 Set Vref, RX VrefLevel [Byte0]: 52
1068 01:22:10.758517 [Byte1]: 52
1069 01:22:10.763167
1070 01:22:10.763276 Set Vref, RX VrefLevel [Byte0]: 53
1071 01:22:10.766219 [Byte1]: 53
1072 01:22:10.770502
1073 01:22:10.770586 Set Vref, RX VrefLevel [Byte0]: 54
1074 01:22:10.774082 [Byte1]: 54
1075 01:22:10.777781
1076 01:22:10.777863 Set Vref, RX VrefLevel [Byte0]: 55
1077 01:22:10.781306 [Byte1]: 55
1078 01:22:10.785879
1079 01:22:10.785963 Set Vref, RX VrefLevel [Byte0]: 56
1080 01:22:10.789017 [Byte1]: 56
1081 01:22:10.793472
1082 01:22:10.793605 Set Vref, RX VrefLevel [Byte0]: 57
1083 01:22:10.796744 [Byte1]: 57
1084 01:22:10.800614
1085 01:22:10.800693 Set Vref, RX VrefLevel [Byte0]: 58
1086 01:22:10.804425 [Byte1]: 58
1087 01:22:10.808522
1088 01:22:10.808620 Set Vref, RX VrefLevel [Byte0]: 59
1089 01:22:10.811829 [Byte1]: 59
1090 01:22:10.816073
1091 01:22:10.816184 Set Vref, RX VrefLevel [Byte0]: 60
1092 01:22:10.819213 [Byte1]: 60
1093 01:22:10.823656
1094 01:22:10.823741 Set Vref, RX VrefLevel [Byte0]: 61
1095 01:22:10.827384 [Byte1]: 61
1096 01:22:10.831688
1097 01:22:10.831798 Set Vref, RX VrefLevel [Byte0]: 62
1098 01:22:10.834885 [Byte1]: 62
1099 01:22:10.839267
1100 01:22:10.839352 Set Vref, RX VrefLevel [Byte0]: 63
1101 01:22:10.842260 [Byte1]: 63
1102 01:22:10.846758
1103 01:22:10.846844 Set Vref, RX VrefLevel [Byte0]: 64
1104 01:22:10.853484 [Byte1]: 64
1105 01:22:10.853602
1106 01:22:10.856712 Set Vref, RX VrefLevel [Byte0]: 65
1107 01:22:10.859687 [Byte1]: 65
1108 01:22:10.859768
1109 01:22:10.863126 Set Vref, RX VrefLevel [Byte0]: 66
1110 01:22:10.866642 [Byte1]: 66
1111 01:22:10.866725
1112 01:22:10.869992 Set Vref, RX VrefLevel [Byte0]: 67
1113 01:22:10.873330 [Byte1]: 67
1114 01:22:10.877168
1115 01:22:10.877251 Set Vref, RX VrefLevel [Byte0]: 68
1116 01:22:10.880453 [Byte1]: 68
1117 01:22:10.884970
1118 01:22:10.885084 Set Vref, RX VrefLevel [Byte0]: 69
1119 01:22:10.888331 [Byte1]: 69
1120 01:22:10.892598
1121 01:22:10.892682 Set Vref, RX VrefLevel [Byte0]: 70
1122 01:22:10.896063 [Byte1]: 70
1123 01:22:10.899908
1124 01:22:10.899991 Set Vref, RX VrefLevel [Byte0]: 71
1125 01:22:10.903402 [Byte1]: 71
1126 01:22:10.908081
1127 01:22:10.908179 Set Vref, RX VrefLevel [Byte0]: 72
1128 01:22:10.911284 [Byte1]: 72
1129 01:22:10.915770
1130 01:22:10.915856 Set Vref, RX VrefLevel [Byte0]: 73
1131 01:22:10.918910 [Byte1]: 73
1132 01:22:10.923030
1133 01:22:10.923110 Set Vref, RX VrefLevel [Byte0]: 74
1134 01:22:10.926833 [Byte1]: 74
1135 01:22:10.930449
1136 01:22:10.930525 Set Vref, RX VrefLevel [Byte0]: 75
1137 01:22:10.934042 [Byte1]: 75
1138 01:22:10.938519
1139 01:22:10.938600 Set Vref, RX VrefLevel [Byte0]: 76
1140 01:22:10.941636 [Byte1]: 76
1141 01:22:10.945842
1142 01:22:10.945922 Set Vref, RX VrefLevel [Byte0]: 77
1143 01:22:10.949657 [Byte1]: 77
1144 01:22:10.953921
1145 01:22:10.953996 Set Vref, RX VrefLevel [Byte0]: 78
1146 01:22:10.957181 [Byte1]: 78
1147 01:22:10.961524
1148 01:22:10.961618 Set Vref, RX VrefLevel [Byte0]: 79
1149 01:22:10.964602 [Byte1]: 79
1150 01:22:10.969081
1151 01:22:10.969162 Set Vref, RX VrefLevel [Byte0]: 80
1152 01:22:10.972107 [Byte1]: 80
1153 01:22:10.976803
1154 01:22:10.976894 Final RX Vref Byte 0 = 57 to rank0
1155 01:22:10.979848 Final RX Vref Byte 1 = 58 to rank0
1156 01:22:10.983428 Final RX Vref Byte 0 = 57 to rank1
1157 01:22:10.986500 Final RX Vref Byte 1 = 58 to rank1==
1158 01:22:10.989722 Dram Type= 6, Freq= 0, CH_0, rank 0
1159 01:22:10.996640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1160 01:22:10.996778 ==
1161 01:22:10.996848 DQS Delay:
1162 01:22:10.996910 DQS0 = 0, DQS1 = 0
1163 01:22:11.000142 DQM Delay:
1164 01:22:11.000214 DQM0 = 82, DQM1 = 68
1165 01:22:11.003067 DQ Delay:
1166 01:22:11.006550 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1167 01:22:11.009702 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1168 01:22:11.009786 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1169 01:22:11.016663 DQ12 =72, DQ13 =76, DQ14 =80, DQ15 =76
1170 01:22:11.016767
1171 01:22:11.016834
1172 01:22:11.022815 [DQSOSCAuto] RK0, (LSB)MR18= 0x2726, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1173 01:22:11.026613 CH0 RK0: MR19=606, MR18=2726
1174 01:22:11.033164 CH0_RK0: MR19=0x606, MR18=0x2726, DQSOSC=400, MR23=63, INC=92, DEC=61
1175 01:22:11.033254
1176 01:22:11.036363 ----->DramcWriteLeveling(PI) begin...
1177 01:22:11.036451 ==
1178 01:22:11.040065 Dram Type= 6, Freq= 0, CH_0, rank 1
1179 01:22:11.043147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1180 01:22:11.043227 ==
1181 01:22:11.046824 Write leveling (Byte 0): 34 => 34
1182 01:22:11.049958 Write leveling (Byte 1): 31 => 31
1183 01:22:11.053427 DramcWriteLeveling(PI) end<-----
1184 01:22:11.053561
1185 01:22:11.053636 ==
1186 01:22:11.056521 Dram Type= 6, Freq= 0, CH_0, rank 1
1187 01:22:11.059569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1188 01:22:11.059643 ==
1189 01:22:11.063288 [Gating] SW mode calibration
1190 01:22:11.070161 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1191 01:22:11.076825 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1192 01:22:11.079830 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1193 01:22:11.082887 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1194 01:22:11.089831 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1195 01:22:11.092840 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1196 01:22:11.096680 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 01:22:11.103161 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 01:22:11.106657 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 01:22:11.109920 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 01:22:11.116381 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 01:22:11.119902 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 01:22:11.123205 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 01:22:11.167293 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 01:22:11.167777 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 01:22:11.167963 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 01:22:11.168115 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 01:22:11.168267 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 01:22:11.168419 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 01:22:11.168563 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1210 01:22:11.168762 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1211 01:22:11.168913 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 01:22:11.169055 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 01:22:11.199144 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 01:22:11.199596 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 01:22:11.199769 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 01:22:11.199908 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 01:22:11.200037 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 01:22:11.200193 0 9 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
1219 01:22:11.202776 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1220 01:22:11.206523 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 01:22:11.206679 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 01:22:11.213029 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1223 01:22:11.216254 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1224 01:22:11.219208 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1225 01:22:11.225891 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
1226 01:22:11.229356 0 10 8 | B1->B0 | 2f2f 2c2c | 1 1 | (1 0) (1 0)
1227 01:22:11.232527 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1228 01:22:11.239552 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 01:22:11.242726 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 01:22:11.246152 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 01:22:11.252559 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 01:22:11.256228 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 01:22:11.259466 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 01:22:11.266225 0 11 8 | B1->B0 | 2e2e 3e3e | 1 0 | (0 0) (0 0)
1235 01:22:11.269160 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (1 1) (0 0)
1236 01:22:11.272893 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 01:22:11.279222 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 01:22:11.282404 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1239 01:22:11.286126 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1240 01:22:11.289122 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1241 01:22:11.295750 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1242 01:22:11.299473 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1243 01:22:11.302691 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 01:22:11.309633 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 01:22:11.312617 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 01:22:11.315724 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 01:22:11.323762 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 01:22:11.327489 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 01:22:11.331238 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 01:22:11.334969 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 01:22:11.338548 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 01:22:11.345225 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 01:22:11.349173 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 01:22:11.352543 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 01:22:11.356089 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 01:22:11.362410 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 01:22:11.365815 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1258 01:22:11.368850 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1259 01:22:11.372213 Total UI for P1: 0, mck2ui 16
1260 01:22:11.375608 best dqsien dly found for B0: ( 0, 14, 4)
1261 01:22:11.382184 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1262 01:22:11.385657 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 01:22:11.389294 Total UI for P1: 0, mck2ui 16
1264 01:22:11.392294 best dqsien dly found for B1: ( 0, 14, 10)
1265 01:22:11.395810 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1266 01:22:11.399192 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1267 01:22:11.399271
1268 01:22:11.402088 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1269 01:22:11.405767 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1270 01:22:11.408863 [Gating] SW calibration Done
1271 01:22:11.408944 ==
1272 01:22:11.412771 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 01:22:11.415760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 01:22:11.415863 ==
1275 01:22:11.418849 RX Vref Scan: 0
1276 01:22:11.418935
1277 01:22:11.422558 RX Vref 0 -> 0, step: 1
1278 01:22:11.422642
1279 01:22:11.422736 RX Delay -130 -> 252, step: 16
1280 01:22:11.429194 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1281 01:22:11.432174 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1282 01:22:11.435775 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1283 01:22:11.438962 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1284 01:22:11.442605 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1285 01:22:11.448803 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
1286 01:22:11.452545 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1287 01:22:11.456117 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1288 01:22:11.459441 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1289 01:22:11.462639 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1290 01:22:11.468862 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1291 01:22:11.472226 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1292 01:22:11.475697 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1293 01:22:11.479302 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1294 01:22:11.482294 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1295 01:22:11.488953 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1296 01:22:11.489036 ==
1297 01:22:11.492345 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 01:22:11.496087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 01:22:11.496170 ==
1300 01:22:11.496255 DQS Delay:
1301 01:22:11.499313 DQS0 = 0, DQS1 = 0
1302 01:22:11.499397 DQM Delay:
1303 01:22:11.502414 DQM0 = 76, DQM1 = 69
1304 01:22:11.502498 DQ Delay:
1305 01:22:11.506143 DQ0 =77, DQ1 =85, DQ2 =69, DQ3 =69
1306 01:22:11.509025 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =85
1307 01:22:11.512763 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1308 01:22:11.515879 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1309 01:22:11.515994
1310 01:22:11.516079
1311 01:22:11.516158 ==
1312 01:22:11.519552 Dram Type= 6, Freq= 0, CH_0, rank 1
1313 01:22:11.522617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1314 01:22:11.522702 ==
1315 01:22:11.522787
1316 01:22:11.522883
1317 01:22:11.526344 TX Vref Scan disable
1318 01:22:11.529385 == TX Byte 0 ==
1319 01:22:11.532360 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1320 01:22:11.536123 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1321 01:22:11.539209 == TX Byte 1 ==
1322 01:22:11.542255 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1323 01:22:11.545850 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1324 01:22:11.545935 ==
1325 01:22:11.548868 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 01:22:11.555915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 01:22:11.556002 ==
1328 01:22:11.567892 TX Vref=22, minBit 9, minWin=26, winSum=431
1329 01:22:11.570994 TX Vref=24, minBit 11, minWin=26, winSum=435
1330 01:22:11.574444 TX Vref=26, minBit 7, minWin=27, winSum=440
1331 01:22:11.577373 TX Vref=28, minBit 8, minWin=27, winSum=441
1332 01:22:11.580889 TX Vref=30, minBit 11, minWin=26, winSum=439
1333 01:22:11.587592 TX Vref=32, minBit 1, minWin=27, winSum=440
1334 01:22:11.591139 [TxChooseVref] Worse bit 8, Min win 27, Win sum 441, Final Vref 28
1335 01:22:11.591222
1336 01:22:11.594194 Final TX Range 1 Vref 28
1337 01:22:11.594275
1338 01:22:11.594339 ==
1339 01:22:11.597401 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 01:22:11.600843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 01:22:11.604475 ==
1342 01:22:11.604556
1343 01:22:11.604619
1344 01:22:11.604679 TX Vref Scan disable
1345 01:22:11.607751 == TX Byte 0 ==
1346 01:22:11.610945 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1347 01:22:11.614529 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1348 01:22:11.617974 == TX Byte 1 ==
1349 01:22:11.621040 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1350 01:22:11.624315 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1351 01:22:11.627854
1352 01:22:11.627935 [DATLAT]
1353 01:22:11.627999 Freq=800, CH0 RK1
1354 01:22:11.628059
1355 01:22:11.630987 DATLAT Default: 0xa
1356 01:22:11.631068 0, 0xFFFF, sum = 0
1357 01:22:11.634573 1, 0xFFFF, sum = 0
1358 01:22:11.634655 2, 0xFFFF, sum = 0
1359 01:22:11.637655 3, 0xFFFF, sum = 0
1360 01:22:11.637737 4, 0xFFFF, sum = 0
1361 01:22:11.641347 5, 0xFFFF, sum = 0
1362 01:22:11.644363 6, 0xFFFF, sum = 0
1363 01:22:11.644445 7, 0xFFFF, sum = 0
1364 01:22:11.647628 8, 0xFFFF, sum = 0
1365 01:22:11.647710 9, 0x0, sum = 1
1366 01:22:11.647775 10, 0x0, sum = 2
1367 01:22:11.651197 11, 0x0, sum = 3
1368 01:22:11.651279 12, 0x0, sum = 4
1369 01:22:11.654262 best_step = 10
1370 01:22:11.654343
1371 01:22:11.654405 ==
1372 01:22:11.657868 Dram Type= 6, Freq= 0, CH_0, rank 1
1373 01:22:11.661102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1374 01:22:11.661184 ==
1375 01:22:11.664012 RX Vref Scan: 0
1376 01:22:11.664092
1377 01:22:11.664155 RX Vref 0 -> 0, step: 1
1378 01:22:11.667730
1379 01:22:11.667891 RX Delay -111 -> 252, step: 8
1380 01:22:11.674739 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1381 01:22:11.677611 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1382 01:22:11.680991 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1383 01:22:11.684392 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1384 01:22:11.687993 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1385 01:22:11.694256 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1386 01:22:11.697497 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1387 01:22:11.701258 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1388 01:22:11.704318 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1389 01:22:11.707892 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1390 01:22:11.714351 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1391 01:22:11.717848 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1392 01:22:11.721319 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1393 01:22:11.724205 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1394 01:22:11.730909 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1395 01:22:11.734090 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1396 01:22:11.734174 ==
1397 01:22:11.737442 Dram Type= 6, Freq= 0, CH_0, rank 1
1398 01:22:11.741265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1399 01:22:11.741387 ==
1400 01:22:11.741486 DQS Delay:
1401 01:22:11.744466 DQS0 = 0, DQS1 = 0
1402 01:22:11.744551 DQM Delay:
1403 01:22:11.747651 DQM0 = 79, DQM1 = 70
1404 01:22:11.747734 DQ Delay:
1405 01:22:11.751217 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1406 01:22:11.754122 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =92
1407 01:22:11.757925 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1408 01:22:11.760806 DQ12 =76, DQ13 =72, DQ14 =80, DQ15 =80
1409 01:22:11.760891
1410 01:22:11.760975
1411 01:22:11.770753 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a24, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1412 01:22:11.770841 CH0 RK1: MR19=606, MR18=4A24
1413 01:22:11.777334 CH0_RK1: MR19=0x606, MR18=0x4A24, DQSOSC=391, MR23=63, INC=96, DEC=64
1414 01:22:11.780794 [RxdqsGatingPostProcess] freq 800
1415 01:22:11.787119 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1416 01:22:11.790656 Pre-setting of DQS Precalculation
1417 01:22:11.794207 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1418 01:22:11.794362 ==
1419 01:22:11.797409 Dram Type= 6, Freq= 0, CH_1, rank 0
1420 01:22:11.800596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1421 01:22:11.804142 ==
1422 01:22:11.807110 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1423 01:22:11.813893 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1424 01:22:11.823069 [CA 0] Center 36 (6~66) winsize 61
1425 01:22:11.826123 [CA 1] Center 37 (7~67) winsize 61
1426 01:22:11.829865 [CA 2] Center 35 (5~65) winsize 61
1427 01:22:11.832944 [CA 3] Center 34 (4~64) winsize 61
1428 01:22:11.836111 [CA 4] Center 34 (4~64) winsize 61
1429 01:22:11.839600 [CA 5] Center 34 (4~64) winsize 61
1430 01:22:11.839688
1431 01:22:11.843125 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1432 01:22:11.843210
1433 01:22:11.846167 [CATrainingPosCal] consider 1 rank data
1434 01:22:11.849940 u2DelayCellTimex100 = 270/100 ps
1435 01:22:11.852864 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1436 01:22:11.856380 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1437 01:22:11.862876 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1438 01:22:11.866071 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1439 01:22:11.869819 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1440 01:22:11.872879 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1441 01:22:11.872965
1442 01:22:11.876387 CA PerBit enable=1, Macro0, CA PI delay=34
1443 01:22:11.876472
1444 01:22:11.879530 [CBTSetCACLKResult] CA Dly = 34
1445 01:22:11.879615 CS Dly: 5 (0~36)
1446 01:22:11.879700 ==
1447 01:22:11.883070 Dram Type= 6, Freq= 0, CH_1, rank 1
1448 01:22:11.889567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 01:22:11.889679 ==
1450 01:22:11.892975 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1451 01:22:11.899425 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1452 01:22:11.909242 [CA 0] Center 37 (7~67) winsize 61
1453 01:22:11.912140 [CA 1] Center 36 (6~67) winsize 62
1454 01:22:11.915639 [CA 2] Center 34 (4~65) winsize 62
1455 01:22:11.918672 [CA 3] Center 34 (4~64) winsize 61
1456 01:22:11.922519 [CA 4] Center 34 (4~65) winsize 62
1457 01:22:11.925643 [CA 5] Center 33 (3~64) winsize 62
1458 01:22:11.925727
1459 01:22:11.929198 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1460 01:22:11.929281
1461 01:22:11.932127 [CATrainingPosCal] consider 2 rank data
1462 01:22:11.935996 u2DelayCellTimex100 = 270/100 ps
1463 01:22:11.939032 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1464 01:22:11.942216 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1465 01:22:11.948947 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1466 01:22:11.951968 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1467 01:22:11.955508 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1468 01:22:11.958618 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1469 01:22:11.958689
1470 01:22:11.962398 CA PerBit enable=1, Macro0, CA PI delay=34
1471 01:22:11.962470
1472 01:22:11.965662 [CBTSetCACLKResult] CA Dly = 34
1473 01:22:11.965741 CS Dly: 6 (0~38)
1474 01:22:11.965826
1475 01:22:11.968934 ----->DramcWriteLeveling(PI) begin...
1476 01:22:11.972189 ==
1477 01:22:11.975423 Dram Type= 6, Freq= 0, CH_1, rank 0
1478 01:22:11.979154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1479 01:22:11.979238 ==
1480 01:22:11.982859 Write leveling (Byte 0): 30 => 30
1481 01:22:11.986668 Write leveling (Byte 1): 30 => 30
1482 01:22:11.986782 DramcWriteLeveling(PI) end<-----
1483 01:22:11.986868
1484 01:22:11.986947 ==
1485 01:22:11.989854 Dram Type= 6, Freq= 0, CH_1, rank 0
1486 01:22:11.993746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1487 01:22:11.997280 ==
1488 01:22:11.997354 [Gating] SW mode calibration
1489 01:22:12.004663 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1490 01:22:12.011859 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1491 01:22:12.015730 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1492 01:22:12.018718 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1493 01:22:12.022325 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1494 01:22:12.029093 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 01:22:12.032246 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 01:22:12.035818 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 01:22:12.042555 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 01:22:12.045622 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 01:22:12.048642 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 01:22:12.055471 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 01:22:12.059319 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 01:22:12.062439 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 01:22:12.069167 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 01:22:12.072048 0 7 20 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1505 01:22:12.075660 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 01:22:12.082065 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 01:22:12.085327 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 01:22:12.088992 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1509 01:22:12.092110 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1510 01:22:12.098800 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 01:22:12.102272 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 01:22:12.105758 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 01:22:12.112137 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 01:22:12.115701 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 01:22:12.118861 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 01:22:12.125647 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 01:22:12.129346 0 9 8 | B1->B0 | 2828 2929 | 0 0 | (0 0) (0 0)
1518 01:22:12.132312 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 01:22:12.139160 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1520 01:22:12.142123 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1521 01:22:12.145740 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1522 01:22:12.151931 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1523 01:22:12.155735 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1524 01:22:12.158794 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (0 1)
1525 01:22:12.165527 0 10 8 | B1->B0 | 2c2c 2828 | 1 1 | (1 1) (1 0)
1526 01:22:12.168557 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 01:22:12.172116 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 01:22:12.178882 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 01:22:12.182130 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 01:22:12.185146 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 01:22:12.188908 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 01:22:12.195502 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 01:22:12.199026 0 11 8 | B1->B0 | 3333 3939 | 1 0 | (0 0) (0 0)
1534 01:22:12.202176 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 01:22:12.209108 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 01:22:12.212138 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 01:22:12.215448 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1538 01:22:12.222194 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1539 01:22:12.225377 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1540 01:22:12.228730 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1541 01:22:12.235466 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1542 01:22:12.239001 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 01:22:12.242113 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 01:22:12.248678 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 01:22:12.252420 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 01:22:12.255584 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 01:22:12.262344 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 01:22:12.265687 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 01:22:12.268825 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 01:22:12.275508 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 01:22:12.279129 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 01:22:12.282186 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 01:22:12.289033 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 01:22:12.292049 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 01:22:12.295708 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 01:22:12.298757 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 01:22:12.305377 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1558 01:22:12.308920 Total UI for P1: 0, mck2ui 16
1559 01:22:12.312055 best dqsien dly found for B1: ( 0, 14, 6)
1560 01:22:12.315701 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 01:22:12.319138 Total UI for P1: 0, mck2ui 16
1562 01:22:12.322007 best dqsien dly found for B0: ( 0, 14, 8)
1563 01:22:12.325310 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1564 01:22:12.328842 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1565 01:22:12.328929
1566 01:22:12.331848 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1567 01:22:12.335490 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1568 01:22:12.338951 [Gating] SW calibration Done
1569 01:22:12.339053 ==
1570 01:22:12.342425 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 01:22:12.345391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 01:22:12.348664 ==
1573 01:22:12.348744 RX Vref Scan: 0
1574 01:22:12.348809
1575 01:22:12.352351 RX Vref 0 -> 0, step: 1
1576 01:22:12.352427
1577 01:22:12.355444 RX Delay -130 -> 252, step: 16
1578 01:22:12.359202 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1579 01:22:12.362543 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1580 01:22:12.365734 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1581 01:22:12.368822 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1582 01:22:12.375688 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1583 01:22:12.378736 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1584 01:22:12.382391 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1585 01:22:12.385324 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1586 01:22:12.388692 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1587 01:22:12.392514 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1588 01:22:12.398565 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1589 01:22:12.402330 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1590 01:22:12.405411 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1591 01:22:12.409051 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1592 01:22:12.415636 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1593 01:22:12.418811 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1594 01:22:12.418899 ==
1595 01:22:12.422021 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 01:22:12.425519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 01:22:12.425605 ==
1598 01:22:12.425676 DQS Delay:
1599 01:22:12.428754 DQS0 = 0, DQS1 = 0
1600 01:22:12.428832 DQM Delay:
1601 01:22:12.432265 DQM0 = 80, DQM1 = 70
1602 01:22:12.432374 DQ Delay:
1603 01:22:12.435953 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =77
1604 01:22:12.438932 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1605 01:22:12.441999 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1606 01:22:12.445689 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1607 01:22:12.445784
1608 01:22:12.445851
1609 01:22:12.445913 ==
1610 01:22:12.448531 Dram Type= 6, Freq= 0, CH_1, rank 0
1611 01:22:12.452211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1612 01:22:12.455100 ==
1613 01:22:12.455186
1614 01:22:12.455252
1615 01:22:12.455314 TX Vref Scan disable
1616 01:22:12.458375 == TX Byte 0 ==
1617 01:22:12.462276 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1618 01:22:12.465289 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1619 01:22:12.468447 == TX Byte 1 ==
1620 01:22:12.472166 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1621 01:22:12.475468 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1622 01:22:12.478624 ==
1623 01:22:12.481995 Dram Type= 6, Freq= 0, CH_1, rank 0
1624 01:22:12.485370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1625 01:22:12.485454 ==
1626 01:22:12.497639 TX Vref=22, minBit 0, minWin=27, winSum=441
1627 01:22:12.500697 TX Vref=24, minBit 1, minWin=27, winSum=443
1628 01:22:12.504591 TX Vref=26, minBit 4, minWin=27, winSum=446
1629 01:22:12.507609 TX Vref=28, minBit 2, minWin=27, winSum=448
1630 01:22:12.510706 TX Vref=30, minBit 0, minWin=28, winSum=451
1631 01:22:12.514260 TX Vref=32, minBit 0, minWin=28, winSum=453
1632 01:22:12.521012 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 32
1633 01:22:12.521102
1634 01:22:12.524050 Final TX Range 1 Vref 32
1635 01:22:12.524126
1636 01:22:12.524188 ==
1637 01:22:12.527709 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 01:22:12.530786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 01:22:12.530869 ==
1640 01:22:12.530935
1641 01:22:12.530995
1642 01:22:12.534027 TX Vref Scan disable
1643 01:22:12.537519 == TX Byte 0 ==
1644 01:22:12.541069 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1645 01:22:12.544034 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1646 01:22:12.547759 == TX Byte 1 ==
1647 01:22:12.550749 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1648 01:22:12.554393 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1649 01:22:12.554483
1650 01:22:12.558123 [DATLAT]
1651 01:22:12.558227 Freq=800, CH1 RK0
1652 01:22:12.558345
1653 01:22:12.561814 DATLAT Default: 0xa
1654 01:22:12.561901 0, 0xFFFF, sum = 0
1655 01:22:12.564775 1, 0xFFFF, sum = 0
1656 01:22:12.564862 2, 0xFFFF, sum = 0
1657 01:22:12.568512 3, 0xFFFF, sum = 0
1658 01:22:12.568604 4, 0xFFFF, sum = 0
1659 01:22:12.571801 5, 0xFFFF, sum = 0
1660 01:22:12.571888 6, 0xFFFF, sum = 0
1661 01:22:12.574873 7, 0xFFFF, sum = 0
1662 01:22:12.574960 8, 0xFFFF, sum = 0
1663 01:22:12.578213 9, 0x0, sum = 1
1664 01:22:12.578300 10, 0x0, sum = 2
1665 01:22:12.581840 11, 0x0, sum = 3
1666 01:22:12.581930 12, 0x0, sum = 4
1667 01:22:12.584577 best_step = 10
1668 01:22:12.584651
1669 01:22:12.584721 ==
1670 01:22:12.588203 Dram Type= 6, Freq= 0, CH_1, rank 0
1671 01:22:12.591320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1672 01:22:12.591397 ==
1673 01:22:12.591475 RX Vref Scan: 1
1674 01:22:12.594759
1675 01:22:12.594837 Set Vref Range= 32 -> 127
1676 01:22:12.594914
1677 01:22:12.598069 RX Vref 32 -> 127, step: 1
1678 01:22:12.598152
1679 01:22:12.601453 RX Delay -111 -> 252, step: 8
1680 01:22:12.601549
1681 01:22:12.604971 Set Vref, RX VrefLevel [Byte0]: 32
1682 01:22:12.607951 [Byte1]: 32
1683 01:22:12.608037
1684 01:22:12.611809 Set Vref, RX VrefLevel [Byte0]: 33
1685 01:22:12.614821 [Byte1]: 33
1686 01:22:12.614907
1687 01:22:12.617818 Set Vref, RX VrefLevel [Byte0]: 34
1688 01:22:12.621676 [Byte1]: 34
1689 01:22:12.625307
1690 01:22:12.625418 Set Vref, RX VrefLevel [Byte0]: 35
1691 01:22:12.629132 [Byte1]: 35
1692 01:22:12.633518
1693 01:22:12.633604 Set Vref, RX VrefLevel [Byte0]: 36
1694 01:22:12.636644 [Byte1]: 36
1695 01:22:12.641039
1696 01:22:12.641124 Set Vref, RX VrefLevel [Byte0]: 37
1697 01:22:12.644119 [Byte1]: 37
1698 01:22:12.648432
1699 01:22:12.648520 Set Vref, RX VrefLevel [Byte0]: 38
1700 01:22:12.651783 [Byte1]: 38
1701 01:22:12.656480
1702 01:22:12.656573 Set Vref, RX VrefLevel [Byte0]: 39
1703 01:22:12.659558 [Byte1]: 39
1704 01:22:12.663918
1705 01:22:12.664007 Set Vref, RX VrefLevel [Byte0]: 40
1706 01:22:12.666887 [Byte1]: 40
1707 01:22:12.671628
1708 01:22:12.671713 Set Vref, RX VrefLevel [Byte0]: 41
1709 01:22:12.674713 [Byte1]: 41
1710 01:22:12.679122
1711 01:22:12.679206 Set Vref, RX VrefLevel [Byte0]: 42
1712 01:22:12.682723 [Byte1]: 42
1713 01:22:12.686957
1714 01:22:12.687041 Set Vref, RX VrefLevel [Byte0]: 43
1715 01:22:12.690204 [Byte1]: 43
1716 01:22:12.694547
1717 01:22:12.694679 Set Vref, RX VrefLevel [Byte0]: 44
1718 01:22:12.698055 [Byte1]: 44
1719 01:22:12.702021
1720 01:22:12.702104 Set Vref, RX VrefLevel [Byte0]: 45
1721 01:22:12.705386 [Byte1]: 45
1722 01:22:12.709527
1723 01:22:12.709624 Set Vref, RX VrefLevel [Byte0]: 46
1724 01:22:12.713057 [Byte1]: 46
1725 01:22:12.717258
1726 01:22:12.717342 Set Vref, RX VrefLevel [Byte0]: 47
1727 01:22:12.720834 [Byte1]: 47
1728 01:22:12.724765
1729 01:22:12.724856 Set Vref, RX VrefLevel [Byte0]: 48
1730 01:22:12.728186 [Byte1]: 48
1731 01:22:12.732566
1732 01:22:12.732718 Set Vref, RX VrefLevel [Byte0]: 49
1733 01:22:12.736177 [Byte1]: 49
1734 01:22:12.740136
1735 01:22:12.740248 Set Vref, RX VrefLevel [Byte0]: 50
1736 01:22:12.743870 [Byte1]: 50
1737 01:22:12.748108
1738 01:22:12.748224 Set Vref, RX VrefLevel [Byte0]: 51
1739 01:22:12.751138 [Byte1]: 51
1740 01:22:12.755270
1741 01:22:12.755375 Set Vref, RX VrefLevel [Byte0]: 52
1742 01:22:12.759213 [Byte1]: 52
1743 01:22:12.762881
1744 01:22:12.762963 Set Vref, RX VrefLevel [Byte0]: 53
1745 01:22:12.766515 [Byte1]: 53
1746 01:22:12.770723
1747 01:22:12.770808 Set Vref, RX VrefLevel [Byte0]: 54
1748 01:22:12.774322 [Byte1]: 54
1749 01:22:12.778727
1750 01:22:12.778812 Set Vref, RX VrefLevel [Byte0]: 55
1751 01:22:12.781720 [Byte1]: 55
1752 01:22:12.785863
1753 01:22:12.785949 Set Vref, RX VrefLevel [Byte0]: 56
1754 01:22:12.789457 [Byte1]: 56
1755 01:22:12.793821
1756 01:22:12.793907 Set Vref, RX VrefLevel [Byte0]: 57
1757 01:22:12.796993 [Byte1]: 57
1758 01:22:12.801764
1759 01:22:12.801854 Set Vref, RX VrefLevel [Byte0]: 58
1760 01:22:12.804856 [Byte1]: 58
1761 01:22:12.809208
1762 01:22:12.809300 Set Vref, RX VrefLevel [Byte0]: 59
1763 01:22:12.812424 [Byte1]: 59
1764 01:22:12.816949
1765 01:22:12.817040 Set Vref, RX VrefLevel [Byte0]: 60
1766 01:22:12.819814 [Byte1]: 60
1767 01:22:12.824539
1768 01:22:12.824631 Set Vref, RX VrefLevel [Byte0]: 61
1769 01:22:12.827720 [Byte1]: 61
1770 01:22:12.831921
1771 01:22:12.832005 Set Vref, RX VrefLevel [Byte0]: 62
1772 01:22:12.835444 [Byte1]: 62
1773 01:22:12.839941
1774 01:22:12.840025 Set Vref, RX VrefLevel [Byte0]: 63
1775 01:22:12.842917 [Byte1]: 63
1776 01:22:12.847205
1777 01:22:12.847290 Set Vref, RX VrefLevel [Byte0]: 64
1778 01:22:12.850437 [Byte1]: 64
1779 01:22:12.855301
1780 01:22:12.855385 Set Vref, RX VrefLevel [Byte0]: 65
1781 01:22:12.858316 [Byte1]: 65
1782 01:22:12.862672
1783 01:22:12.862781 Set Vref, RX VrefLevel [Byte0]: 66
1784 01:22:12.866167 [Byte1]: 66
1785 01:22:12.870192
1786 01:22:12.870277 Set Vref, RX VrefLevel [Byte0]: 67
1787 01:22:12.873558 [Byte1]: 67
1788 01:22:12.878172
1789 01:22:12.878258 Set Vref, RX VrefLevel [Byte0]: 68
1790 01:22:12.881316 [Byte1]: 68
1791 01:22:12.885705
1792 01:22:12.885791 Set Vref, RX VrefLevel [Byte0]: 69
1793 01:22:12.888785 [Byte1]: 69
1794 01:22:12.893005
1795 01:22:12.893091 Set Vref, RX VrefLevel [Byte0]: 70
1796 01:22:12.896562 [Byte1]: 70
1797 01:22:12.900828
1798 01:22:12.900913 Set Vref, RX VrefLevel [Byte0]: 71
1799 01:22:12.904517 [Byte1]: 71
1800 01:22:12.908279
1801 01:22:12.908366 Set Vref, RX VrefLevel [Byte0]: 72
1802 01:22:12.911930 [Byte1]: 72
1803 01:22:12.916465
1804 01:22:12.916556 Set Vref, RX VrefLevel [Byte0]: 73
1805 01:22:12.919570 [Byte1]: 73
1806 01:22:12.923883
1807 01:22:12.923974 Final RX Vref Byte 0 = 60 to rank0
1808 01:22:12.927074 Final RX Vref Byte 1 = 56 to rank0
1809 01:22:12.930724 Final RX Vref Byte 0 = 60 to rank1
1810 01:22:12.933973 Final RX Vref Byte 1 = 56 to rank1==
1811 01:22:12.937007 Dram Type= 6, Freq= 0, CH_1, rank 0
1812 01:22:12.943713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1813 01:22:12.943799 ==
1814 01:22:12.943866 DQS Delay:
1815 01:22:12.943929 DQS0 = 0, DQS1 = 0
1816 01:22:12.947120 DQM Delay:
1817 01:22:12.947204 DQM0 = 81, DQM1 = 72
1818 01:22:12.950518 DQ Delay:
1819 01:22:12.953755 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1820 01:22:12.957004 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1821 01:22:12.957094 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1822 01:22:12.963588 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =80
1823 01:22:12.963673
1824 01:22:12.963740
1825 01:22:12.970293 [DQSOSCAuto] RK0, (LSB)MR18= 0x141e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
1826 01:22:12.973271 CH1 RK0: MR19=606, MR18=141E
1827 01:22:12.980146 CH1_RK0: MR19=0x606, MR18=0x141E, DQSOSC=402, MR23=63, INC=91, DEC=60
1828 01:22:12.980255
1829 01:22:12.983890 ----->DramcWriteLeveling(PI) begin...
1830 01:22:12.983974 ==
1831 01:22:12.986692 Dram Type= 6, Freq= 0, CH_1, rank 1
1832 01:22:12.990319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1833 01:22:12.990403 ==
1834 01:22:12.993768 Write leveling (Byte 0): 30 => 30
1835 01:22:12.997233 Write leveling (Byte 1): 30 => 30
1836 01:22:13.000350 DramcWriteLeveling(PI) end<-----
1837 01:22:13.000433
1838 01:22:13.000497 ==
1839 01:22:13.003610 Dram Type= 6, Freq= 0, CH_1, rank 1
1840 01:22:13.007390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1841 01:22:13.007498 ==
1842 01:22:13.010241 [Gating] SW mode calibration
1843 01:22:13.016881 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1844 01:22:13.023700 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1845 01:22:13.026907 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1846 01:22:13.030472 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1847 01:22:13.037277 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1848 01:22:13.040267 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 01:22:13.043386 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 01:22:13.050136 0 6 20 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1851 01:22:13.053244 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 01:22:13.056408 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 01:22:13.063428 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 01:22:13.066627 0 7 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1855 01:22:13.069945 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 01:22:13.076810 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 01:22:13.080075 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 01:22:13.083566 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 01:22:13.090283 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 01:22:13.093255 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 01:22:13.096621 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1862 01:22:13.103416 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1863 01:22:13.106907 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1864 01:22:13.110249 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 01:22:13.113496 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 01:22:13.120372 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 01:22:13.123645 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 01:22:13.126911 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 01:22:13.133595 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 01:22:13.136665 0 9 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1871 01:22:13.140362 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1872 01:22:13.146519 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1873 01:22:13.150122 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1874 01:22:13.153303 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1875 01:22:13.160330 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1876 01:22:13.163318 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1877 01:22:13.166568 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1878 01:22:13.173196 0 10 4 | B1->B0 | 3131 2e2e | 1 1 | (1 1) (1 0)
1879 01:22:13.176579 0 10 8 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
1880 01:22:13.179821 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 01:22:13.186441 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 01:22:13.190047 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 01:22:13.193231 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 01:22:13.200024 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 01:22:13.203396 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1886 01:22:13.206375 0 11 4 | B1->B0 | 2929 3434 | 0 0 | (0 0) (0 0)
1887 01:22:13.213195 0 11 8 | B1->B0 | 3c3c 4645 | 1 1 | (0 0) (0 0)
1888 01:22:13.216769 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 01:22:13.219630 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 01:22:13.223121 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 01:22:13.229844 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 01:22:13.233308 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 01:22:13.236368 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1894 01:22:13.243305 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1895 01:22:13.246565 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1896 01:22:13.249499 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 01:22:13.256212 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 01:22:13.259829 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 01:22:13.263007 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 01:22:13.269407 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 01:22:13.273155 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 01:22:13.276186 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 01:22:13.282792 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 01:22:13.286317 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 01:22:13.289979 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 01:22:13.296185 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 01:22:13.300028 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 01:22:13.303123 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 01:22:13.309589 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 01:22:13.313260 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1911 01:22:13.316499 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 01:22:13.319596 Total UI for P1: 0, mck2ui 16
1913 01:22:13.322902 best dqsien dly found for B0: ( 0, 14, 4)
1914 01:22:13.326340 Total UI for P1: 0, mck2ui 16
1915 01:22:13.329594 best dqsien dly found for B1: ( 0, 14, 4)
1916 01:22:13.333044 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1917 01:22:13.336076 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1918 01:22:13.336191
1919 01:22:13.339582 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1920 01:22:13.346023 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1921 01:22:13.346106 [Gating] SW calibration Done
1922 01:22:13.346172 ==
1923 01:22:13.349776 Dram Type= 6, Freq= 0, CH_1, rank 1
1924 01:22:13.356328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1925 01:22:13.356433 ==
1926 01:22:13.356535 RX Vref Scan: 0
1927 01:22:13.356625
1928 01:22:13.359356 RX Vref 0 -> 0, step: 1
1929 01:22:13.359454
1930 01:22:13.362517 RX Delay -130 -> 252, step: 16
1931 01:22:13.366287 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1932 01:22:13.369372 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1933 01:22:13.372514 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1934 01:22:13.379285 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1935 01:22:13.382804 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1936 01:22:13.385828 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1937 01:22:13.389504 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1938 01:22:13.393022 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1939 01:22:13.399770 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1940 01:22:13.402663 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1941 01:22:13.406355 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1942 01:22:13.409557 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1943 01:22:13.412603 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1944 01:22:13.419568 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1945 01:22:13.423035 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1946 01:22:13.426035 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1947 01:22:13.426115 ==
1948 01:22:13.429584 Dram Type= 6, Freq= 0, CH_1, rank 1
1949 01:22:13.433056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1950 01:22:13.433134 ==
1951 01:22:13.435766 DQS Delay:
1952 01:22:13.435883 DQS0 = 0, DQS1 = 0
1953 01:22:13.439715 DQM Delay:
1954 01:22:13.439825 DQM0 = 76, DQM1 = 71
1955 01:22:13.439920 DQ Delay:
1956 01:22:13.442767 DQ0 =77, DQ1 =69, DQ2 =61, DQ3 =77
1957 01:22:13.446224 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1958 01:22:13.449662 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1959 01:22:13.452927 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1960 01:22:13.453037
1961 01:22:13.453106
1962 01:22:13.453169 ==
1963 01:22:13.456094 Dram Type= 6, Freq= 0, CH_1, rank 1
1964 01:22:13.462565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1965 01:22:13.462653 ==
1966 01:22:13.462722
1967 01:22:13.462785
1968 01:22:13.462854 TX Vref Scan disable
1969 01:22:13.466696 == TX Byte 0 ==
1970 01:22:13.469750 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1971 01:22:13.473570 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1972 01:22:13.476444 == TX Byte 1 ==
1973 01:22:13.480201 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1974 01:22:13.483300 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1975 01:22:13.486837 ==
1976 01:22:13.490024 Dram Type= 6, Freq= 0, CH_1, rank 1
1977 01:22:13.493155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1978 01:22:13.493256 ==
1979 01:22:13.505237 TX Vref=22, minBit 1, minWin=27, winSum=446
1980 01:22:13.508840 TX Vref=24, minBit 1, minWin=27, winSum=451
1981 01:22:13.512041 TX Vref=26, minBit 1, minWin=27, winSum=450
1982 01:22:13.515224 TX Vref=28, minBit 1, minWin=27, winSum=454
1983 01:22:13.518812 TX Vref=30, minBit 1, minWin=27, winSum=458
1984 01:22:13.521979 TX Vref=32, minBit 1, minWin=27, winSum=454
1985 01:22:13.528504 [TxChooseVref] Worse bit 1, Min win 27, Win sum 458, Final Vref 30
1986 01:22:13.528602
1987 01:22:13.532049 Final TX Range 1 Vref 30
1988 01:22:13.532137
1989 01:22:13.532203 ==
1990 01:22:13.535060 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 01:22:13.538765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 01:22:13.538871 ==
1993 01:22:13.538945
1994 01:22:13.542025
1995 01:22:13.542108 TX Vref Scan disable
1996 01:22:13.545292 == TX Byte 0 ==
1997 01:22:13.548867 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1998 01:22:13.555477 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1999 01:22:13.555576 == TX Byte 1 ==
2000 01:22:13.559010 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2001 01:22:13.565160 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2002 01:22:13.565247
2003 01:22:13.565314 [DATLAT]
2004 01:22:13.565383 Freq=800, CH1 RK1
2005 01:22:13.565470
2006 01:22:13.568302 DATLAT Default: 0xa
2007 01:22:13.568381 0, 0xFFFF, sum = 0
2008 01:22:13.571733 1, 0xFFFF, sum = 0
2009 01:22:13.571809 2, 0xFFFF, sum = 0
2010 01:22:13.575248 3, 0xFFFF, sum = 0
2011 01:22:13.575332 4, 0xFFFF, sum = 0
2012 01:22:13.578390 5, 0xFFFF, sum = 0
2013 01:22:13.581719 6, 0xFFFF, sum = 0
2014 01:22:13.581841 7, 0xFFFF, sum = 0
2015 01:22:13.585260 8, 0xFFFF, sum = 0
2016 01:22:13.585369 9, 0x0, sum = 1
2017 01:22:13.585465 10, 0x0, sum = 2
2018 01:22:13.588261 11, 0x0, sum = 3
2019 01:22:13.588334 12, 0x0, sum = 4
2020 01:22:13.591859 best_step = 10
2021 01:22:13.591942
2022 01:22:13.592008 ==
2023 01:22:13.594940 Dram Type= 6, Freq= 0, CH_1, rank 1
2024 01:22:13.598685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2025 01:22:13.598771 ==
2026 01:22:13.601703 RX Vref Scan: 0
2027 01:22:13.601786
2028 01:22:13.601851 RX Vref 0 -> 0, step: 1
2029 01:22:13.601913
2030 01:22:13.605147 RX Delay -111 -> 252, step: 8
2031 01:22:13.611991 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2032 01:22:13.615105 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2033 01:22:13.618868 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2034 01:22:13.621957 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2035 01:22:13.625032 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2036 01:22:13.632228 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2037 01:22:13.635084 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2038 01:22:13.638470 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2039 01:22:13.641929 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2040 01:22:13.645023 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2041 01:22:13.651703 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2042 01:22:13.655404 iDelay=209, Bit 11, Center 72 (-47 ~ 192) 240
2043 01:22:13.658444 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2044 01:22:13.661975 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2045 01:22:13.668955 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2046 01:22:13.672020 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2047 01:22:13.672104 ==
2048 01:22:13.674984 Dram Type= 6, Freq= 0, CH_1, rank 1
2049 01:22:13.678712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2050 01:22:13.678797 ==
2051 01:22:13.678863 DQS Delay:
2052 01:22:13.681724 DQS0 = 0, DQS1 = 0
2053 01:22:13.681806 DQM Delay:
2054 01:22:13.685401 DQM0 = 78, DQM1 = 74
2055 01:22:13.685520 DQ Delay:
2056 01:22:13.688266 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =72
2057 01:22:13.691696 DQ4 =76, DQ5 =88, DQ6 =92, DQ7 =76
2058 01:22:13.695477 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =72
2059 01:22:13.698716 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2060 01:22:13.698800
2061 01:22:13.698866
2062 01:22:13.708343 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c34, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
2063 01:22:13.708430 CH1 RK1: MR19=606, MR18=1C34
2064 01:22:13.714962 CH1_RK1: MR19=0x606, MR18=0x1C34, DQSOSC=396, MR23=63, INC=94, DEC=62
2065 01:22:13.718473 [RxdqsGatingPostProcess] freq 800
2066 01:22:13.725323 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2067 01:22:13.728622 Pre-setting of DQS Precalculation
2068 01:22:13.731727 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2069 01:22:13.738598 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2070 01:22:13.745127 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2071 01:22:13.748012
2072 01:22:13.748097
2073 01:22:13.748161 [Calibration Summary] 1600 Mbps
2074 01:22:13.751753 CH 0, Rank 0
2075 01:22:13.751829 SW Impedance : PASS
2076 01:22:13.755005 DUTY Scan : NO K
2077 01:22:13.758062 ZQ Calibration : PASS
2078 01:22:13.758138 Jitter Meter : NO K
2079 01:22:13.761799 CBT Training : PASS
2080 01:22:13.764769 Write leveling : PASS
2081 01:22:13.764842 RX DQS gating : PASS
2082 01:22:13.768415 RX DQ/DQS(RDDQC) : PASS
2083 01:22:13.771577 TX DQ/DQS : PASS
2084 01:22:13.771654 RX DATLAT : PASS
2085 01:22:13.775234 RX DQ/DQS(Engine): PASS
2086 01:22:13.778311 TX OE : NO K
2087 01:22:13.778391 All Pass.
2088 01:22:13.778455
2089 01:22:13.778549 CH 0, Rank 1
2090 01:22:13.781379 SW Impedance : PASS
2091 01:22:13.785070 DUTY Scan : NO K
2092 01:22:13.785152 ZQ Calibration : PASS
2093 01:22:13.788227 Jitter Meter : NO K
2094 01:22:13.791448 CBT Training : PASS
2095 01:22:13.791525 Write leveling : PASS
2096 01:22:13.795208 RX DQS gating : PASS
2097 01:22:13.795285 RX DQ/DQS(RDDQC) : PASS
2098 01:22:13.798326 TX DQ/DQS : PASS
2099 01:22:13.801267 RX DATLAT : PASS
2100 01:22:13.801341 RX DQ/DQS(Engine): PASS
2101 01:22:13.804735 TX OE : NO K
2102 01:22:13.804810 All Pass.
2103 01:22:13.804873
2104 01:22:13.807866 CH 1, Rank 0
2105 01:22:13.807951 SW Impedance : PASS
2106 01:22:13.811461 DUTY Scan : NO K
2107 01:22:13.814512 ZQ Calibration : PASS
2108 01:22:13.814588 Jitter Meter : NO K
2109 01:22:13.817803 CBT Training : PASS
2110 01:22:13.821241 Write leveling : PASS
2111 01:22:13.821331 RX DQS gating : PASS
2112 01:22:13.824537 RX DQ/DQS(RDDQC) : PASS
2113 01:22:13.827885 TX DQ/DQS : PASS
2114 01:22:13.827969 RX DATLAT : PASS
2115 01:22:13.831622 RX DQ/DQS(Engine): PASS
2116 01:22:13.834620 TX OE : NO K
2117 01:22:13.834731 All Pass.
2118 01:22:13.834826
2119 01:22:13.834918 CH 1, Rank 1
2120 01:22:13.838139 SW Impedance : PASS
2121 01:22:13.841238 DUTY Scan : NO K
2122 01:22:13.841322 ZQ Calibration : PASS
2123 01:22:13.845056 Jitter Meter : NO K
2124 01:22:13.845139 CBT Training : PASS
2125 01:22:13.847979 Write leveling : PASS
2126 01:22:13.851293 RX DQS gating : PASS
2127 01:22:13.851377 RX DQ/DQS(RDDQC) : PASS
2128 01:22:13.854859 TX DQ/DQS : PASS
2129 01:22:13.857901 RX DATLAT : PASS
2130 01:22:13.857985 RX DQ/DQS(Engine): PASS
2131 01:22:13.861632 TX OE : NO K
2132 01:22:13.861716 All Pass.
2133 01:22:13.861783
2134 01:22:13.864866 DramC Write-DBI off
2135 01:22:13.867974 PER_BANK_REFRESH: Hybrid Mode
2136 01:22:13.868058 TX_TRACKING: ON
2137 01:22:13.871577 [GetDramInforAfterCalByMRR] Vendor 6.
2138 01:22:13.874634 [GetDramInforAfterCalByMRR] Revision 606.
2139 01:22:13.878377 [GetDramInforAfterCalByMRR] Revision 2 0.
2140 01:22:13.881522 MR0 0x3b3b
2141 01:22:13.881632 MR8 0x5151
2142 01:22:13.884466 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2143 01:22:13.884548
2144 01:22:13.884612 MR0 0x3b3b
2145 01:22:13.888083 MR8 0x5151
2146 01:22:13.891343 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2147 01:22:13.891425
2148 01:22:13.901191 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2149 01:22:13.904847 [FAST_K] Save calibration result to emmc
2150 01:22:13.908106 [FAST_K] Save calibration result to emmc
2151 01:22:13.908211 dram_init: config_dvfs: 1
2152 01:22:13.914727 dramc_set_vcore_voltage set vcore to 662500
2153 01:22:13.914807 Read voltage for 1200, 2
2154 01:22:13.917830 Vio18 = 0
2155 01:22:13.917904 Vcore = 662500
2156 01:22:13.917973 Vdram = 0
2157 01:22:13.921616 Vddq = 0
2158 01:22:13.921727 Vmddr = 0
2159 01:22:13.924500 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2160 01:22:13.931283 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2161 01:22:13.934964 MEM_TYPE=3, freq_sel=15
2162 01:22:13.935056 sv_algorithm_assistance_LP4_1600
2163 01:22:13.941536 ============ PULL DRAM RESETB DOWN ============
2164 01:22:13.944448 ========== PULL DRAM RESETB DOWN end =========
2165 01:22:13.948347 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2166 01:22:13.951342 ===================================
2167 01:22:13.954776 LPDDR4 DRAM CONFIGURATION
2168 01:22:13.957876 ===================================
2169 01:22:13.961248 EX_ROW_EN[0] = 0x0
2170 01:22:13.961337 EX_ROW_EN[1] = 0x0
2171 01:22:13.964598 LP4Y_EN = 0x0
2172 01:22:13.964677 WORK_FSP = 0x0
2173 01:22:13.968041 WL = 0x4
2174 01:22:13.968155 RL = 0x4
2175 01:22:13.971226 BL = 0x2
2176 01:22:13.971336 RPST = 0x0
2177 01:22:13.974846 RD_PRE = 0x0
2178 01:22:13.974928 WR_PRE = 0x1
2179 01:22:13.977845 WR_PST = 0x0
2180 01:22:13.977918 DBI_WR = 0x0
2181 01:22:13.981190 DBI_RD = 0x0
2182 01:22:13.981261 OTF = 0x1
2183 01:22:13.984376 ===================================
2184 01:22:13.988056 ===================================
2185 01:22:13.991213 ANA top config
2186 01:22:13.994892 ===================================
2187 01:22:13.998056 DLL_ASYNC_EN = 0
2188 01:22:13.998150 ALL_SLAVE_EN = 0
2189 01:22:14.001166 NEW_RANK_MODE = 1
2190 01:22:14.004287 DLL_IDLE_MODE = 1
2191 01:22:14.008098 LP45_APHY_COMB_EN = 1
2192 01:22:14.008179 TX_ODT_DIS = 1
2193 01:22:14.011167 NEW_8X_MODE = 1
2194 01:22:14.014714 ===================================
2195 01:22:14.017707 ===================================
2196 01:22:14.021376 data_rate = 2400
2197 01:22:14.024646 CKR = 1
2198 01:22:14.028071 DQ_P2S_RATIO = 8
2199 01:22:14.030996 ===================================
2200 01:22:14.034580 CA_P2S_RATIO = 8
2201 01:22:14.034663 DQ_CA_OPEN = 0
2202 01:22:14.037616 DQ_SEMI_OPEN = 0
2203 01:22:14.041378 CA_SEMI_OPEN = 0
2204 01:22:14.044585 CA_FULL_RATE = 0
2205 01:22:14.047576 DQ_CKDIV4_EN = 0
2206 01:22:14.051287 CA_CKDIV4_EN = 0
2207 01:22:14.051386 CA_PREDIV_EN = 0
2208 01:22:14.054424 PH8_DLY = 17
2209 01:22:14.057701 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2210 01:22:14.061234 DQ_AAMCK_DIV = 4
2211 01:22:14.064770 CA_AAMCK_DIV = 4
2212 01:22:14.067867 CA_ADMCK_DIV = 4
2213 01:22:14.067949 DQ_TRACK_CA_EN = 0
2214 01:22:14.071296 CA_PICK = 1200
2215 01:22:14.074550 CA_MCKIO = 1200
2216 01:22:14.077679 MCKIO_SEMI = 0
2217 01:22:14.081009 PLL_FREQ = 2366
2218 01:22:14.084203 DQ_UI_PI_RATIO = 32
2219 01:22:14.087563 CA_UI_PI_RATIO = 0
2220 01:22:14.091061 ===================================
2221 01:22:14.094755 ===================================
2222 01:22:14.094840 memory_type:LPDDR4
2223 01:22:14.097991 GP_NUM : 10
2224 01:22:14.101182 SRAM_EN : 1
2225 01:22:14.101295 MD32_EN : 0
2226 01:22:14.104211 ===================================
2227 01:22:14.107842 [ANA_INIT] >>>>>>>>>>>>>>
2228 01:22:14.110938 <<<<<< [CONFIGURE PHASE]: ANA_TX
2229 01:22:14.114617 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2230 01:22:14.117486 ===================================
2231 01:22:14.121090 data_rate = 2400,PCW = 0X5b00
2232 01:22:14.124386 ===================================
2233 01:22:14.127354 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2234 01:22:14.131173 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2235 01:22:14.137356 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2236 01:22:14.140997 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2237 01:22:14.144122 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2238 01:22:14.148028 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2239 01:22:14.151073 [ANA_INIT] flow start
2240 01:22:14.154240 [ANA_INIT] PLL >>>>>>>>
2241 01:22:14.154324 [ANA_INIT] PLL <<<<<<<<
2242 01:22:14.157305 [ANA_INIT] MIDPI >>>>>>>>
2243 01:22:14.161072 [ANA_INIT] MIDPI <<<<<<<<
2244 01:22:14.161184 [ANA_INIT] DLL >>>>>>>>
2245 01:22:14.163980 [ANA_INIT] DLL <<<<<<<<
2246 01:22:14.167292 [ANA_INIT] flow end
2247 01:22:14.170908 ============ LP4 DIFF to SE enter ============
2248 01:22:14.174632 ============ LP4 DIFF to SE exit ============
2249 01:22:14.177878 [ANA_INIT] <<<<<<<<<<<<<
2250 01:22:14.180932 [Flow] Enable top DCM control >>>>>
2251 01:22:14.184182 [Flow] Enable top DCM control <<<<<
2252 01:22:14.187604 Enable DLL master slave shuffle
2253 01:22:14.191247 ==============================================================
2254 01:22:14.194412 Gating Mode config
2255 01:22:14.201054 ==============================================================
2256 01:22:14.201152 Config description:
2257 01:22:14.211261 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2258 01:22:14.217441 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2259 01:22:14.221087 SELPH_MODE 0: By rank 1: By Phase
2260 01:22:14.228170 ==============================================================
2261 01:22:14.231287 GAT_TRACK_EN = 1
2262 01:22:14.234441 RX_GATING_MODE = 2
2263 01:22:14.238208 RX_GATING_TRACK_MODE = 2
2264 01:22:14.241118 SELPH_MODE = 1
2265 01:22:14.244381 PICG_EARLY_EN = 1
2266 01:22:14.244463 VALID_LAT_VALUE = 1
2267 01:22:14.251421 ==============================================================
2268 01:22:14.254840 Enter into Gating configuration >>>>
2269 01:22:14.257899 Exit from Gating configuration <<<<
2270 01:22:14.261132 Enter into DVFS_PRE_config >>>>>
2271 01:22:14.271361 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2272 01:22:14.274439 Exit from DVFS_PRE_config <<<<<
2273 01:22:14.278094 Enter into PICG configuration >>>>
2274 01:22:14.281231 Exit from PICG configuration <<<<
2275 01:22:14.284331 [RX_INPUT] configuration >>>>>
2276 01:22:14.287474 [RX_INPUT] configuration <<<<<
2277 01:22:14.294391 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2278 01:22:14.297688 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2279 01:22:14.304340 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2280 01:22:14.310948 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2281 01:22:14.317370 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2282 01:22:14.324189 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2283 01:22:14.327298 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2284 01:22:14.330996 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2285 01:22:14.334023 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2286 01:22:14.340820 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2287 01:22:14.344271 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2288 01:22:14.347302 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2289 01:22:14.351105 ===================================
2290 01:22:14.354156 LPDDR4 DRAM CONFIGURATION
2291 01:22:14.357075 ===================================
2292 01:22:14.357160 EX_ROW_EN[0] = 0x0
2293 01:22:14.360569 EX_ROW_EN[1] = 0x0
2294 01:22:14.360654 LP4Y_EN = 0x0
2295 01:22:14.364194 WORK_FSP = 0x0
2296 01:22:14.367234 WL = 0x4
2297 01:22:14.367318 RL = 0x4
2298 01:22:14.370425 BL = 0x2
2299 01:22:14.370522 RPST = 0x0
2300 01:22:14.373929 RD_PRE = 0x0
2301 01:22:14.374012 WR_PRE = 0x1
2302 01:22:14.377645 WR_PST = 0x0
2303 01:22:14.377728 DBI_WR = 0x0
2304 01:22:14.380573 DBI_RD = 0x0
2305 01:22:14.380703 OTF = 0x1
2306 01:22:14.384184 ===================================
2307 01:22:14.387329 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2308 01:22:14.394173 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2309 01:22:14.397318 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2310 01:22:14.400425 ===================================
2311 01:22:14.404217 LPDDR4 DRAM CONFIGURATION
2312 01:22:14.407403 ===================================
2313 01:22:14.407486 EX_ROW_EN[0] = 0x10
2314 01:22:14.410461 EX_ROW_EN[1] = 0x0
2315 01:22:14.410553 LP4Y_EN = 0x0
2316 01:22:14.414102 WORK_FSP = 0x0
2317 01:22:14.414185 WL = 0x4
2318 01:22:14.417331 RL = 0x4
2319 01:22:14.417407 BL = 0x2
2320 01:22:14.420742 RPST = 0x0
2321 01:22:14.420855 RD_PRE = 0x0
2322 01:22:14.424169 WR_PRE = 0x1
2323 01:22:14.424274 WR_PST = 0x0
2324 01:22:14.427290 DBI_WR = 0x0
2325 01:22:14.430791 DBI_RD = 0x0
2326 01:22:14.430885 OTF = 0x1
2327 01:22:14.433853 ===================================
2328 01:22:14.440470 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2329 01:22:14.440576 ==
2330 01:22:14.444043 Dram Type= 6, Freq= 0, CH_0, rank 0
2331 01:22:14.447008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2332 01:22:14.447119 ==
2333 01:22:14.450536 [Duty_Offset_Calibration]
2334 01:22:14.450626 B0:2 B1:0 CA:3
2335 01:22:14.450731
2336 01:22:14.454027 [DutyScan_Calibration_Flow] k_type=0
2337 01:22:14.465071
2338 01:22:14.465156 ==CLK 0==
2339 01:22:14.467989 Final CLK duty delay cell = 0
2340 01:22:14.471757 [0] MAX Duty = 5062%(X100), DQS PI = 20
2341 01:22:14.474639 [0] MIN Duty = 4906%(X100), DQS PI = 54
2342 01:22:14.474746 [0] AVG Duty = 4984%(X100)
2343 01:22:14.478064
2344 01:22:14.481600 CH0 CLK Duty spec in!! Max-Min= 156%
2345 01:22:14.484448 [DutyScan_Calibration_Flow] ====Done====
2346 01:22:14.484553
2347 01:22:14.488092 [DutyScan_Calibration_Flow] k_type=1
2348 01:22:14.503600
2349 01:22:14.503687 ==DQS 0 ==
2350 01:22:14.506664 Final DQS duty delay cell = 0
2351 01:22:14.509858 [0] MAX Duty = 5062%(X100), DQS PI = 12
2352 01:22:14.513586 [0] MIN Duty = 4907%(X100), DQS PI = 44
2353 01:22:14.516521 [0] AVG Duty = 4984%(X100)
2354 01:22:14.516632
2355 01:22:14.516702 ==DQS 1 ==
2356 01:22:14.519610 Final DQS duty delay cell = -4
2357 01:22:14.523276 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2358 01:22:14.526303 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2359 01:22:14.529767 [-4] AVG Duty = 4937%(X100)
2360 01:22:14.529884
2361 01:22:14.533447 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2362 01:22:14.533555
2363 01:22:14.536516 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2364 01:22:14.540120 [DutyScan_Calibration_Flow] ====Done====
2365 01:22:14.540231
2366 01:22:14.543266 [DutyScan_Calibration_Flow] k_type=3
2367 01:22:14.561022
2368 01:22:14.561110 ==DQM 0 ==
2369 01:22:14.564557 Final DQM duty delay cell = 0
2370 01:22:14.567625 [0] MAX Duty = 5124%(X100), DQS PI = 28
2371 01:22:14.571257 [0] MIN Duty = 4876%(X100), DQS PI = 48
2372 01:22:14.571342 [0] AVG Duty = 5000%(X100)
2373 01:22:14.574221
2374 01:22:14.574303 ==DQM 1 ==
2375 01:22:14.577619 Final DQM duty delay cell = 4
2376 01:22:14.581306 [4] MAX Duty = 5124%(X100), DQS PI = 50
2377 01:22:14.584117 [4] MIN Duty = 5000%(X100), DQS PI = 12
2378 01:22:14.587798 [4] AVG Duty = 5062%(X100)
2379 01:22:14.587901
2380 01:22:14.590747 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2381 01:22:14.590826
2382 01:22:14.594161 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2383 01:22:14.597746 [DutyScan_Calibration_Flow] ====Done====
2384 01:22:14.597834
2385 01:22:14.601130 [DutyScan_Calibration_Flow] k_type=2
2386 01:22:14.615938
2387 01:22:14.616046 ==DQ 0 ==
2388 01:22:14.619237 Final DQ duty delay cell = -4
2389 01:22:14.622464 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2390 01:22:14.626021 [-4] MIN Duty = 4907%(X100), DQS PI = 42
2391 01:22:14.629158 [-4] AVG Duty = 4969%(X100)
2392 01:22:14.629265
2393 01:22:14.629363 ==DQ 1 ==
2394 01:22:14.632097 Final DQ duty delay cell = -4
2395 01:22:14.635735 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2396 01:22:14.639138 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2397 01:22:14.642419 [-4] AVG Duty = 4938%(X100)
2398 01:22:14.642498
2399 01:22:14.645909 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2400 01:22:14.645987
2401 01:22:14.649056 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2402 01:22:14.652054 [DutyScan_Calibration_Flow] ====Done====
2403 01:22:14.652174 ==
2404 01:22:14.655715 Dram Type= 6, Freq= 0, CH_1, rank 0
2405 01:22:14.658828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2406 01:22:14.658911 ==
2407 01:22:14.662085 [Duty_Offset_Calibration]
2408 01:22:14.662185 B0:1 B1:-2 CA:0
2409 01:22:14.665790
2410 01:22:14.665868 [DutyScan_Calibration_Flow] k_type=0
2411 01:22:14.676587
2412 01:22:14.676673 ==CLK 0==
2413 01:22:14.679765 Final CLK duty delay cell = 0
2414 01:22:14.683387 [0] MAX Duty = 5062%(X100), DQS PI = 30
2415 01:22:14.686657 [0] MIN Duty = 4875%(X100), DQS PI = 58
2416 01:22:14.686776 [0] AVG Duty = 4968%(X100)
2417 01:22:14.689628
2418 01:22:14.693278 CH1 CLK Duty spec in!! Max-Min= 187%
2419 01:22:14.696400 [DutyScan_Calibration_Flow] ====Done====
2420 01:22:14.696512
2421 01:22:14.700000 [DutyScan_Calibration_Flow] k_type=1
2422 01:22:14.715203
2423 01:22:14.715327 ==DQS 0 ==
2424 01:22:14.718347 Final DQS duty delay cell = -4
2425 01:22:14.721709 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2426 01:22:14.724821 [-4] MIN Duty = 4876%(X100), DQS PI = 50
2427 01:22:14.728534 [-4] AVG Duty = 4938%(X100)
2428 01:22:14.728638
2429 01:22:14.728721 ==DQS 1 ==
2430 01:22:14.731605 Final DQS duty delay cell = 0
2431 01:22:14.735240 [0] MAX Duty = 5062%(X100), DQS PI = 0
2432 01:22:14.738299 [0] MIN Duty = 4875%(X100), DQS PI = 26
2433 01:22:14.741903 [0] AVG Duty = 4968%(X100)
2434 01:22:14.741991
2435 01:22:14.745162 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2436 01:22:14.745266
2437 01:22:14.748115 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2438 01:22:14.751823 [DutyScan_Calibration_Flow] ====Done====
2439 01:22:14.751914
2440 01:22:14.755067 [DutyScan_Calibration_Flow] k_type=3
2441 01:22:14.771558
2442 01:22:14.771680 ==DQM 0 ==
2443 01:22:14.774999 Final DQM duty delay cell = 0
2444 01:22:14.778561 [0] MAX Duty = 5000%(X100), DQS PI = 22
2445 01:22:14.781579 [0] MIN Duty = 4844%(X100), DQS PI = 54
2446 01:22:14.785416 [0] AVG Duty = 4922%(X100)
2447 01:22:14.785532
2448 01:22:14.785601 ==DQM 1 ==
2449 01:22:14.788410 Final DQM duty delay cell = 0
2450 01:22:14.791589 [0] MAX Duty = 5031%(X100), DQS PI = 36
2451 01:22:14.795259 [0] MIN Duty = 4907%(X100), DQS PI = 2
2452 01:22:14.798235 [0] AVG Duty = 4969%(X100)
2453 01:22:14.798322
2454 01:22:14.801702 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2455 01:22:14.801785
2456 01:22:14.805485 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2457 01:22:14.808602 [DutyScan_Calibration_Flow] ====Done====
2458 01:22:14.808677
2459 01:22:14.811541 [DutyScan_Calibration_Flow] k_type=2
2460 01:22:14.828138
2461 01:22:14.828238 ==DQ 0 ==
2462 01:22:14.831867 Final DQ duty delay cell = 0
2463 01:22:14.835323 [0] MAX Duty = 5062%(X100), DQS PI = 12
2464 01:22:14.838558 [0] MIN Duty = 4938%(X100), DQS PI = 54
2465 01:22:14.838676 [0] AVG Duty = 5000%(X100)
2466 01:22:14.838774
2467 01:22:14.841543 ==DQ 1 ==
2468 01:22:14.841656 Final DQ duty delay cell = 0
2469 01:22:14.848131 [0] MAX Duty = 5093%(X100), DQS PI = 20
2470 01:22:14.851557 [0] MIN Duty = 4969%(X100), DQS PI = 26
2471 01:22:14.851675 [0] AVG Duty = 5031%(X100)
2472 01:22:14.851771
2473 01:22:14.855050 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2474 01:22:14.855169
2475 01:22:14.858637 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2476 01:22:14.864995 [DutyScan_Calibration_Flow] ====Done====
2477 01:22:14.868504 nWR fixed to 30
2478 01:22:14.868621 [ModeRegInit_LP4] CH0 RK0
2479 01:22:14.871623 [ModeRegInit_LP4] CH0 RK1
2480 01:22:14.875239 [ModeRegInit_LP4] CH1 RK0
2481 01:22:14.875349 [ModeRegInit_LP4] CH1 RK1
2482 01:22:14.878332 match AC timing 7
2483 01:22:14.881802 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2484 01:22:14.884813 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2485 01:22:14.891623 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2486 01:22:14.894781 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2487 01:22:14.901668 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2488 01:22:14.901777 ==
2489 01:22:14.905197 Dram Type= 6, Freq= 0, CH_0, rank 0
2490 01:22:14.908170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2491 01:22:14.908285 ==
2492 01:22:14.915104 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2493 01:22:14.918048 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2494 01:22:14.928503 [CA 0] Center 40 (10~71) winsize 62
2495 01:22:14.931615 [CA 1] Center 39 (9~70) winsize 62
2496 01:22:14.935137 [CA 2] Center 36 (6~66) winsize 61
2497 01:22:14.938587 [CA 3] Center 35 (5~66) winsize 62
2498 01:22:14.941622 [CA 4] Center 34 (4~65) winsize 62
2499 01:22:14.945123 [CA 5] Center 33 (3~63) winsize 61
2500 01:22:14.945206
2501 01:22:14.948112 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2502 01:22:14.948195
2503 01:22:14.951931 [CATrainingPosCal] consider 1 rank data
2504 01:22:14.955323 u2DelayCellTimex100 = 270/100 ps
2505 01:22:14.958165 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2506 01:22:14.965127 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2507 01:22:14.968079 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2508 01:22:14.971685 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2509 01:22:14.974837 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2510 01:22:14.978432 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2511 01:22:14.978516
2512 01:22:14.981579 CA PerBit enable=1, Macro0, CA PI delay=33
2513 01:22:14.981663
2514 01:22:14.985237 [CBTSetCACLKResult] CA Dly = 33
2515 01:22:14.985321 CS Dly: 7 (0~38)
2516 01:22:14.988123 ==
2517 01:22:14.991718 Dram Type= 6, Freq= 0, CH_0, rank 1
2518 01:22:14.994917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2519 01:22:14.995002 ==
2520 01:22:14.998546 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2521 01:22:15.005184 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2522 01:22:15.014457 [CA 0] Center 40 (10~71) winsize 62
2523 01:22:15.017578 [CA 1] Center 40 (10~70) winsize 61
2524 01:22:15.021258 [CA 2] Center 35 (5~66) winsize 62
2525 01:22:15.024147 [CA 3] Center 35 (5~66) winsize 62
2526 01:22:15.027704 [CA 4] Center 34 (4~65) winsize 62
2527 01:22:15.031408 [CA 5] Center 33 (3~63) winsize 61
2528 01:22:15.031519
2529 01:22:15.034392 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2530 01:22:15.034500
2531 01:22:15.037471 [CATrainingPosCal] consider 2 rank data
2532 01:22:15.041221 u2DelayCellTimex100 = 270/100 ps
2533 01:22:15.044605 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2534 01:22:15.051071 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2535 01:22:15.054219 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2536 01:22:15.057819 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2537 01:22:15.061145 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2538 01:22:15.064515 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2539 01:22:15.064617
2540 01:22:15.067728 CA PerBit enable=1, Macro0, CA PI delay=33
2541 01:22:15.067809
2542 01:22:15.070867 [CBTSetCACLKResult] CA Dly = 33
2543 01:22:15.074362 CS Dly: 8 (0~40)
2544 01:22:15.074477
2545 01:22:15.077589 ----->DramcWriteLeveling(PI) begin...
2546 01:22:15.077708 ==
2547 01:22:15.080952 Dram Type= 6, Freq= 0, CH_0, rank 0
2548 01:22:15.084094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2549 01:22:15.084201 ==
2550 01:22:15.087710 Write leveling (Byte 0): 32 => 32
2551 01:22:15.090680 Write leveling (Byte 1): 30 => 30
2552 01:22:15.094119 DramcWriteLeveling(PI) end<-----
2553 01:22:15.094201
2554 01:22:15.094267 ==
2555 01:22:15.097745 Dram Type= 6, Freq= 0, CH_0, rank 0
2556 01:22:15.100855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2557 01:22:15.100958 ==
2558 01:22:15.104612 [Gating] SW mode calibration
2559 01:22:15.110743 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2560 01:22:15.117489 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2561 01:22:15.120636 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2562 01:22:15.124281 0 15 4 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
2563 01:22:15.130997 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2564 01:22:15.133797 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2565 01:22:15.137544 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2566 01:22:15.143768 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2567 01:22:15.147382 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2568 01:22:15.150427 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2569 01:22:15.157308 1 0 0 | B1->B0 | 3333 2e2e | 0 0 | (0 1) (0 0)
2570 01:22:15.160411 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2571 01:22:15.164123 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2572 01:22:15.170660 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2573 01:22:15.174143 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2574 01:22:15.177281 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2575 01:22:15.180784 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2576 01:22:15.187531 1 0 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2577 01:22:15.190749 1 1 0 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2578 01:22:15.194070 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2579 01:22:15.200735 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 01:22:15.204415 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 01:22:15.207304 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 01:22:15.214135 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2583 01:22:15.217343 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2584 01:22:15.220418 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2585 01:22:15.227337 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2586 01:22:15.230458 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 01:22:15.234180 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 01:22:15.240654 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 01:22:15.244260 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 01:22:15.247291 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 01:22:15.254283 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 01:22:15.257643 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 01:22:15.260704 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 01:22:15.263941 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 01:22:15.270718 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 01:22:15.274345 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 01:22:15.277497 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 01:22:15.284085 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 01:22:15.287155 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 01:22:15.290599 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2601 01:22:15.297116 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2602 01:22:15.300878 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 01:22:15.304266 Total UI for P1: 0, mck2ui 16
2604 01:22:15.307506 best dqsien dly found for B0: ( 1, 3, 30)
2605 01:22:15.310552 Total UI for P1: 0, mck2ui 16
2606 01:22:15.313897 best dqsien dly found for B1: ( 1, 4, 0)
2607 01:22:15.317622 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2608 01:22:15.320911 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2609 01:22:15.321020
2610 01:22:15.324091 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2611 01:22:15.327621 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2612 01:22:15.330716 [Gating] SW calibration Done
2613 01:22:15.330814 ==
2614 01:22:15.333858 Dram Type= 6, Freq= 0, CH_0, rank 0
2615 01:22:15.337426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2616 01:22:15.337546 ==
2617 01:22:15.340639 RX Vref Scan: 0
2618 01:22:15.340721
2619 01:22:15.344141 RX Vref 0 -> 0, step: 1
2620 01:22:15.344246
2621 01:22:15.344340 RX Delay -40 -> 252, step: 8
2622 01:22:15.350855 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2623 01:22:15.353844 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2624 01:22:15.357733 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2625 01:22:15.360668 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2626 01:22:15.364275 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2627 01:22:15.370936 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2628 01:22:15.373741 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2629 01:22:15.377447 iDelay=200, Bit 7, Center 119 (40 ~ 199) 160
2630 01:22:15.380519 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2631 01:22:15.383981 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2632 01:22:15.390826 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2633 01:22:15.393964 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2634 01:22:15.397166 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2635 01:22:15.400964 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2636 01:22:15.403750 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2637 01:22:15.410490 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2638 01:22:15.410604 ==
2639 01:22:15.414023 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 01:22:15.417434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 01:22:15.417548 ==
2642 01:22:15.417617 DQS Delay:
2643 01:22:15.420810 DQS0 = 0, DQS1 = 0
2644 01:22:15.420917 DQM Delay:
2645 01:22:15.424262 DQM0 = 111, DQM1 = 102
2646 01:22:15.424378 DQ Delay:
2647 01:22:15.427466 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2648 01:22:15.430727 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =119
2649 01:22:15.434036 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2650 01:22:15.437173 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2651 01:22:15.437258
2652 01:22:15.437324
2653 01:22:15.437385 ==
2654 01:22:15.440912 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 01:22:15.447597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 01:22:15.447682 ==
2657 01:22:15.447748
2658 01:22:15.447809
2659 01:22:15.447868 TX Vref Scan disable
2660 01:22:15.451202 == TX Byte 0 ==
2661 01:22:15.454150 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2662 01:22:15.457350 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2663 01:22:15.460837 == TX Byte 1 ==
2664 01:22:15.464555 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2665 01:22:15.470755 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2666 01:22:15.470861 ==
2667 01:22:15.473938 Dram Type= 6, Freq= 0, CH_0, rank 0
2668 01:22:15.477345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2669 01:22:15.477428 ==
2670 01:22:15.488746 TX Vref=22, minBit 4, minWin=25, winSum=415
2671 01:22:15.492026 TX Vref=24, minBit 11, minWin=25, winSum=422
2672 01:22:15.495198 TX Vref=26, minBit 7, minWin=26, winSum=433
2673 01:22:15.498946 TX Vref=28, minBit 12, minWin=26, winSum=437
2674 01:22:15.502030 TX Vref=30, minBit 8, minWin=26, winSum=429
2675 01:22:15.508916 TX Vref=32, minBit 8, minWin=26, winSum=431
2676 01:22:15.512131 [TxChooseVref] Worse bit 12, Min win 26, Win sum 437, Final Vref 28
2677 01:22:15.512219
2678 01:22:15.515749 Final TX Range 1 Vref 28
2679 01:22:15.515868
2680 01:22:15.515969 ==
2681 01:22:15.518760 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 01:22:15.521920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 01:22:15.525550 ==
2684 01:22:15.525664
2685 01:22:15.525759
2686 01:22:15.525825 TX Vref Scan disable
2687 01:22:15.528635 == TX Byte 0 ==
2688 01:22:15.531998 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2689 01:22:15.535257 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2690 01:22:15.539083 == TX Byte 1 ==
2691 01:22:15.542163 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2692 01:22:15.545250 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2693 01:22:15.548473
2694 01:22:15.548569 [DATLAT]
2695 01:22:15.548637 Freq=1200, CH0 RK0
2696 01:22:15.548704
2697 01:22:15.552339 DATLAT Default: 0xd
2698 01:22:15.552443 0, 0xFFFF, sum = 0
2699 01:22:15.555320 1, 0xFFFF, sum = 0
2700 01:22:15.555402 2, 0xFFFF, sum = 0
2701 01:22:15.558809 3, 0xFFFF, sum = 0
2702 01:22:15.558921 4, 0xFFFF, sum = 0
2703 01:22:15.561823 5, 0xFFFF, sum = 0
2704 01:22:15.565387 6, 0xFFFF, sum = 0
2705 01:22:15.565495 7, 0xFFFF, sum = 0
2706 01:22:15.568600 8, 0xFFFF, sum = 0
2707 01:22:15.568679 9, 0xFFFF, sum = 0
2708 01:22:15.572298 10, 0xFFFF, sum = 0
2709 01:22:15.572374 11, 0xFFFF, sum = 0
2710 01:22:15.575529 12, 0x0, sum = 1
2711 01:22:15.575613 13, 0x0, sum = 2
2712 01:22:15.578542 14, 0x0, sum = 3
2713 01:22:15.578625 15, 0x0, sum = 4
2714 01:22:15.578692 best_step = 13
2715 01:22:15.578754
2716 01:22:15.582108 ==
2717 01:22:15.585720 Dram Type= 6, Freq= 0, CH_0, rank 0
2718 01:22:15.588681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2719 01:22:15.588765 ==
2720 01:22:15.588831 RX Vref Scan: 1
2721 01:22:15.588892
2722 01:22:15.592129 Set Vref Range= 32 -> 127
2723 01:22:15.592213
2724 01:22:15.595268 RX Vref 32 -> 127, step: 1
2725 01:22:15.595351
2726 01:22:15.598687 RX Delay -37 -> 252, step: 4
2727 01:22:15.598771
2728 01:22:15.602110 Set Vref, RX VrefLevel [Byte0]: 32
2729 01:22:15.605783 [Byte1]: 32
2730 01:22:15.605867
2731 01:22:15.609049 Set Vref, RX VrefLevel [Byte0]: 33
2732 01:22:15.612023 [Byte1]: 33
2733 01:22:15.615597
2734 01:22:15.615680 Set Vref, RX VrefLevel [Byte0]: 34
2735 01:22:15.618456 [Byte1]: 34
2736 01:22:15.623381
2737 01:22:15.623492 Set Vref, RX VrefLevel [Byte0]: 35
2738 01:22:15.626454 [Byte1]: 35
2739 01:22:15.631425
2740 01:22:15.631509 Set Vref, RX VrefLevel [Byte0]: 36
2741 01:22:15.635016 [Byte1]: 36
2742 01:22:15.639297
2743 01:22:15.639380 Set Vref, RX VrefLevel [Byte0]: 37
2744 01:22:15.643050 [Byte1]: 37
2745 01:22:15.647250
2746 01:22:15.647335 Set Vref, RX VrefLevel [Byte0]: 38
2747 01:22:15.650674 [Byte1]: 38
2748 01:22:15.655625
2749 01:22:15.655708 Set Vref, RX VrefLevel [Byte0]: 39
2750 01:22:15.659154 [Byte1]: 39
2751 01:22:15.663095
2752 01:22:15.663204 Set Vref, RX VrefLevel [Byte0]: 40
2753 01:22:15.666883 [Byte1]: 40
2754 01:22:15.671593
2755 01:22:15.671677 Set Vref, RX VrefLevel [Byte0]: 41
2756 01:22:15.674545 [Byte1]: 41
2757 01:22:15.679378
2758 01:22:15.679462 Set Vref, RX VrefLevel [Byte0]: 42
2759 01:22:15.682920 [Byte1]: 42
2760 01:22:15.687253
2761 01:22:15.687336 Set Vref, RX VrefLevel [Byte0]: 43
2762 01:22:15.690892 [Byte1]: 43
2763 01:22:15.695546
2764 01:22:15.695662 Set Vref, RX VrefLevel [Byte0]: 44
2765 01:22:15.698871 [Byte1]: 44
2766 01:22:15.703264
2767 01:22:15.703373 Set Vref, RX VrefLevel [Byte0]: 45
2768 01:22:15.706748 [Byte1]: 45
2769 01:22:15.711302
2770 01:22:15.711426 Set Vref, RX VrefLevel [Byte0]: 46
2771 01:22:15.715041 [Byte1]: 46
2772 01:22:15.719369
2773 01:22:15.719479 Set Vref, RX VrefLevel [Byte0]: 47
2774 01:22:15.722838 [Byte1]: 47
2775 01:22:15.727178
2776 01:22:15.727263 Set Vref, RX VrefLevel [Byte0]: 48
2777 01:22:15.730967 [Byte1]: 48
2778 01:22:15.735322
2779 01:22:15.735435 Set Vref, RX VrefLevel [Byte0]: 49
2780 01:22:15.738402 [Byte1]: 49
2781 01:22:15.743261
2782 01:22:15.743346 Set Vref, RX VrefLevel [Byte0]: 50
2783 01:22:15.746406 [Byte1]: 50
2784 01:22:15.751302
2785 01:22:15.751409 Set Vref, RX VrefLevel [Byte0]: 51
2786 01:22:15.754784 [Byte1]: 51
2787 01:22:15.759411
2788 01:22:15.759524 Set Vref, RX VrefLevel [Byte0]: 52
2789 01:22:15.762604 [Byte1]: 52
2790 01:22:15.767494
2791 01:22:15.767604 Set Vref, RX VrefLevel [Byte0]: 53
2792 01:22:15.770602 [Byte1]: 53
2793 01:22:15.775542
2794 01:22:15.775654 Set Vref, RX VrefLevel [Byte0]: 54
2795 01:22:15.778449 [Byte1]: 54
2796 01:22:15.783184
2797 01:22:15.783297 Set Vref, RX VrefLevel [Byte0]: 55
2798 01:22:15.786442 [Byte1]: 55
2799 01:22:15.791299
2800 01:22:15.791413 Set Vref, RX VrefLevel [Byte0]: 56
2801 01:22:15.794444 [Byte1]: 56
2802 01:22:15.799088
2803 01:22:15.799200 Set Vref, RX VrefLevel [Byte0]: 57
2804 01:22:15.802519 [Byte1]: 57
2805 01:22:15.807579
2806 01:22:15.807695 Set Vref, RX VrefLevel [Byte0]: 58
2807 01:22:15.810716 [Byte1]: 58
2808 01:22:15.815370
2809 01:22:15.815482 Set Vref, RX VrefLevel [Byte0]: 59
2810 01:22:15.818900 [Byte1]: 59
2811 01:22:15.823128
2812 01:22:15.823244 Set Vref, RX VrefLevel [Byte0]: 60
2813 01:22:15.826586 [Byte1]: 60
2814 01:22:15.831587
2815 01:22:15.831698 Set Vref, RX VrefLevel [Byte0]: 61
2816 01:22:15.834593 [Byte1]: 61
2817 01:22:15.839627
2818 01:22:15.839732 Set Vref, RX VrefLevel [Byte0]: 62
2819 01:22:15.842580 [Byte1]: 62
2820 01:22:15.847629
2821 01:22:15.847737 Set Vref, RX VrefLevel [Byte0]: 63
2822 01:22:15.850837 [Byte1]: 63
2823 01:22:15.855141
2824 01:22:15.855248 Set Vref, RX VrefLevel [Byte0]: 64
2825 01:22:15.858926 [Byte1]: 64
2826 01:22:15.863354
2827 01:22:15.863457 Set Vref, RX VrefLevel [Byte0]: 65
2828 01:22:15.866419 [Byte1]: 65
2829 01:22:15.871293
2830 01:22:15.871402 Set Vref, RX VrefLevel [Byte0]: 66
2831 01:22:15.874969 [Byte1]: 66
2832 01:22:15.879208
2833 01:22:15.879317 Set Vref, RX VrefLevel [Byte0]: 67
2834 01:22:15.883012 [Byte1]: 67
2835 01:22:15.887336
2836 01:22:15.887420 Set Vref, RX VrefLevel [Byte0]: 68
2837 01:22:15.890889 [Byte1]: 68
2838 01:22:15.895554
2839 01:22:15.895639 Set Vref, RX VrefLevel [Byte0]: 69
2840 01:22:15.898944 [Byte1]: 69
2841 01:22:15.903617
2842 01:22:15.903725 Set Vref, RX VrefLevel [Byte0]: 70
2843 01:22:15.906992 [Byte1]: 70
2844 01:22:15.911308
2845 01:22:15.911427 Set Vref, RX VrefLevel [Byte0]: 71
2846 01:22:15.914868 [Byte1]: 71
2847 01:22:15.919230
2848 01:22:15.919339 Set Vref, RX VrefLevel [Byte0]: 72
2849 01:22:15.922586 [Byte1]: 72
2850 01:22:15.927595
2851 01:22:15.927712 Set Vref, RX VrefLevel [Byte0]: 73
2852 01:22:15.930511 [Byte1]: 73
2853 01:22:15.935270
2854 01:22:15.935383 Set Vref, RX VrefLevel [Byte0]: 74
2855 01:22:15.938854 [Byte1]: 74
2856 01:22:15.943292
2857 01:22:15.943397 Final RX Vref Byte 0 = 62 to rank0
2858 01:22:15.947086 Final RX Vref Byte 1 = 47 to rank0
2859 01:22:15.950125 Final RX Vref Byte 0 = 62 to rank1
2860 01:22:15.953234 Final RX Vref Byte 1 = 47 to rank1==
2861 01:22:15.956828 Dram Type= 6, Freq= 0, CH_0, rank 0
2862 01:22:15.963125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2863 01:22:15.963235 ==
2864 01:22:15.963331 DQS Delay:
2865 01:22:15.963424 DQS0 = 0, DQS1 = 0
2866 01:22:15.966666 DQM Delay:
2867 01:22:15.966773 DQM0 = 112, DQM1 = 98
2868 01:22:15.970099 DQ Delay:
2869 01:22:15.973187 DQ0 =112, DQ1 =112, DQ2 =114, DQ3 =108
2870 01:22:15.976845 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2871 01:22:15.979823 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =90
2872 01:22:15.982996 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =106
2873 01:22:15.983106
2874 01:22:15.983204
2875 01:22:15.989781 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbfb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2876 01:22:15.993600 CH0 RK0: MR19=303, MR18=FBFB
2877 01:22:16.000226 CH0_RK0: MR19=0x303, MR18=0xFBFB, DQSOSC=412, MR23=63, INC=38, DEC=25
2878 01:22:16.000338
2879 01:22:16.003172 ----->DramcWriteLeveling(PI) begin...
2880 01:22:16.003275 ==
2881 01:22:16.006489 Dram Type= 6, Freq= 0, CH_0, rank 1
2882 01:22:16.009639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2883 01:22:16.013295 ==
2884 01:22:16.013404 Write leveling (Byte 0): 32 => 32
2885 01:22:16.016369 Write leveling (Byte 1): 30 => 30
2886 01:22:16.019962 DramcWriteLeveling(PI) end<-----
2887 01:22:16.020071
2888 01:22:16.020169 ==
2889 01:22:16.023253 Dram Type= 6, Freq= 0, CH_0, rank 1
2890 01:22:16.029692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 01:22:16.029808 ==
2892 01:22:16.029904 [Gating] SW mode calibration
2893 01:22:16.039835 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2894 01:22:16.043292 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2895 01:22:16.046261 0 15 0 | B1->B0 | 2929 3434 | 1 1 | (0 0) (1 1)
2896 01:22:16.053315 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 01:22:16.056510 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 01:22:16.059636 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 01:22:16.066332 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 01:22:16.069522 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2901 01:22:16.073174 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2902 01:22:16.079778 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 1)
2903 01:22:16.082775 1 0 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2904 01:22:16.086376 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 01:22:16.093182 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 01:22:16.096251 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 01:22:16.099392 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 01:22:16.106192 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 01:22:16.109191 1 0 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2910 01:22:16.112530 1 0 28 | B1->B0 | 2424 4343 | 0 0 | (0 0) (0 0)
2911 01:22:16.119215 1 1 0 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
2912 01:22:16.122831 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 01:22:16.125976 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 01:22:16.132761 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 01:22:16.136369 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 01:22:16.139224 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 01:22:16.146346 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2918 01:22:16.149489 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2919 01:22:16.152498 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2920 01:22:16.159293 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 01:22:16.162510 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 01:22:16.165865 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 01:22:16.172408 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 01:22:16.176126 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 01:22:16.179053 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 01:22:16.182525 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 01:22:16.189177 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 01:22:16.192711 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 01:22:16.195849 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 01:22:16.202781 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 01:22:16.205658 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 01:22:16.209327 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 01:22:16.216203 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 01:22:16.219285 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2935 01:22:16.222250 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2936 01:22:16.225779 Total UI for P1: 0, mck2ui 16
2937 01:22:16.229556 best dqsien dly found for B0: ( 1, 3, 28)
2938 01:22:16.235787 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 01:22:16.235872 Total UI for P1: 0, mck2ui 16
2940 01:22:16.242571 best dqsien dly found for B1: ( 1, 4, 0)
2941 01:22:16.246022 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2942 01:22:16.249024 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2943 01:22:16.249103
2944 01:22:16.252810 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2945 01:22:16.255750 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2946 01:22:16.259543 [Gating] SW calibration Done
2947 01:22:16.259637 ==
2948 01:22:16.262641 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 01:22:16.265567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 01:22:16.265678 ==
2951 01:22:16.269098 RX Vref Scan: 0
2952 01:22:16.269175
2953 01:22:16.269249 RX Vref 0 -> 0, step: 1
2954 01:22:16.269341
2955 01:22:16.272333 RX Delay -40 -> 252, step: 8
2956 01:22:16.275655 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2957 01:22:16.279379 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2958 01:22:16.286263 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2959 01:22:16.289422 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2960 01:22:16.292563 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2961 01:22:16.295821 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2962 01:22:16.299104 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2963 01:22:16.306287 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2964 01:22:16.309281 iDelay=200, Bit 8, Center 87 (16 ~ 159) 144
2965 01:22:16.312361 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2966 01:22:16.316076 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2967 01:22:16.319162 iDelay=200, Bit 11, Center 91 (16 ~ 167) 152
2968 01:22:16.325886 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2969 01:22:16.329550 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2970 01:22:16.332829 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2971 01:22:16.335983 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2972 01:22:16.336086 ==
2973 01:22:16.339096 Dram Type= 6, Freq= 0, CH_0, rank 1
2974 01:22:16.342743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2975 01:22:16.345988 ==
2976 01:22:16.346095 DQS Delay:
2977 01:22:16.346193 DQS0 = 0, DQS1 = 0
2978 01:22:16.349064 DQM Delay:
2979 01:22:16.349171 DQM0 = 111, DQM1 = 100
2980 01:22:16.352426 DQ Delay:
2981 01:22:16.356252 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
2982 01:22:16.359315 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2983 01:22:16.362824 DQ8 =87, DQ9 =83, DQ10 =103, DQ11 =91
2984 01:22:16.365741 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =111
2985 01:22:16.365850
2986 01:22:16.365943
2987 01:22:16.366036 ==
2988 01:22:16.369626 Dram Type= 6, Freq= 0, CH_0, rank 1
2989 01:22:16.372636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2990 01:22:16.372720 ==
2991 01:22:16.372788
2992 01:22:16.372849
2993 01:22:16.375733 TX Vref Scan disable
2994 01:22:16.379030 == TX Byte 0 ==
2995 01:22:16.382544 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2996 01:22:16.385593 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2997 01:22:16.389228 == TX Byte 1 ==
2998 01:22:16.392406 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2999 01:22:16.395403 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3000 01:22:16.395481 ==
3001 01:22:16.399022 Dram Type= 6, Freq= 0, CH_0, rank 1
3002 01:22:16.405417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3003 01:22:16.405541 ==
3004 01:22:16.415870 TX Vref=22, minBit 5, minWin=26, winSum=426
3005 01:22:16.419255 TX Vref=24, minBit 0, minWin=26, winSum=430
3006 01:22:16.423013 TX Vref=26, minBit 10, minWin=26, winSum=435
3007 01:22:16.426404 TX Vref=28, minBit 8, minWin=26, winSum=437
3008 01:22:16.429476 TX Vref=30, minBit 1, minWin=27, winSum=443
3009 01:22:16.436229 TX Vref=32, minBit 10, minWin=26, winSum=438
3010 01:22:16.439590 [TxChooseVref] Worse bit 1, Min win 27, Win sum 443, Final Vref 30
3011 01:22:16.439704
3012 01:22:16.442626 Final TX Range 1 Vref 30
3013 01:22:16.442734
3014 01:22:16.442839 ==
3015 01:22:16.446355 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 01:22:16.449330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 01:22:16.452537 ==
3018 01:22:16.452643
3019 01:22:16.452743
3020 01:22:16.452836 TX Vref Scan disable
3021 01:22:16.456203 == TX Byte 0 ==
3022 01:22:16.459245 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3023 01:22:16.465862 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3024 01:22:16.465976 == TX Byte 1 ==
3025 01:22:16.469105 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3026 01:22:16.475691 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3027 01:22:16.475800
3028 01:22:16.475900 [DATLAT]
3029 01:22:16.475992 Freq=1200, CH0 RK1
3030 01:22:16.476084
3031 01:22:16.479520 DATLAT Default: 0xd
3032 01:22:16.479592 0, 0xFFFF, sum = 0
3033 01:22:16.482591 1, 0xFFFF, sum = 0
3034 01:22:16.485851 2, 0xFFFF, sum = 0
3035 01:22:16.485937 3, 0xFFFF, sum = 0
3036 01:22:16.489478 4, 0xFFFF, sum = 0
3037 01:22:16.489600 5, 0xFFFF, sum = 0
3038 01:22:16.492378 6, 0xFFFF, sum = 0
3039 01:22:16.492496 7, 0xFFFF, sum = 0
3040 01:22:16.496108 8, 0xFFFF, sum = 0
3041 01:22:16.496222 9, 0xFFFF, sum = 0
3042 01:22:16.499174 10, 0xFFFF, sum = 0
3043 01:22:16.499259 11, 0xFFFF, sum = 0
3044 01:22:16.502861 12, 0x0, sum = 1
3045 01:22:16.502946 13, 0x0, sum = 2
3046 01:22:16.506026 14, 0x0, sum = 3
3047 01:22:16.506113 15, 0x0, sum = 4
3048 01:22:16.508937 best_step = 13
3049 01:22:16.509052
3050 01:22:16.509146 ==
3051 01:22:16.512686 Dram Type= 6, Freq= 0, CH_0, rank 1
3052 01:22:16.515692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3053 01:22:16.515777 ==
3054 01:22:16.515844 RX Vref Scan: 0
3055 01:22:16.515908
3056 01:22:16.519428 RX Vref 0 -> 0, step: 1
3057 01:22:16.519512
3058 01:22:16.522555 RX Delay -37 -> 252, step: 4
3059 01:22:16.525876 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3060 01:22:16.532715 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3061 01:22:16.535989 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3062 01:22:16.539301 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3063 01:22:16.542412 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3064 01:22:16.545850 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3065 01:22:16.552653 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3066 01:22:16.556185 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3067 01:22:16.559127 iDelay=195, Bit 8, Center 88 (19 ~ 158) 140
3068 01:22:16.562310 iDelay=195, Bit 9, Center 80 (11 ~ 150) 140
3069 01:22:16.565809 iDelay=195, Bit 10, Center 100 (31 ~ 170) 140
3070 01:22:16.572621 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3071 01:22:16.575707 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3072 01:22:16.579434 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3073 01:22:16.582678 iDelay=195, Bit 14, Center 112 (47 ~ 178) 132
3074 01:22:16.586249 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3075 01:22:16.586334 ==
3076 01:22:16.589411 Dram Type= 6, Freq= 0, CH_0, rank 1
3077 01:22:16.595877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3078 01:22:16.595964 ==
3079 01:22:16.596032 DQS Delay:
3080 01:22:16.599017 DQS0 = 0, DQS1 = 0
3081 01:22:16.599103 DQM Delay:
3082 01:22:16.602769 DQM0 = 110, DQM1 = 99
3083 01:22:16.602879 DQ Delay:
3084 01:22:16.605794 DQ0 =108, DQ1 =112, DQ2 =106, DQ3 =108
3085 01:22:16.609033 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3086 01:22:16.612727 DQ8 =88, DQ9 =80, DQ10 =100, DQ11 =90
3087 01:22:16.615858 DQ12 =108, DQ13 =106, DQ14 =112, DQ15 =108
3088 01:22:16.615936
3089 01:22:16.616005
3090 01:22:16.625800 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3091 01:22:16.625911 CH0 RK1: MR19=403, MR18=10F8
3092 01:22:16.632676 CH0_RK1: MR19=0x403, MR18=0x10F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3093 01:22:16.636069 [RxdqsGatingPostProcess] freq 1200
3094 01:22:16.642562 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3095 01:22:16.646159 best DQS0 dly(2T, 0.5T) = (0, 11)
3096 01:22:16.649041 best DQS1 dly(2T, 0.5T) = (0, 12)
3097 01:22:16.652123 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3098 01:22:16.656008 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3099 01:22:16.656119 best DQS0 dly(2T, 0.5T) = (0, 11)
3100 01:22:16.658913 best DQS1 dly(2T, 0.5T) = (0, 12)
3101 01:22:16.662721 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3102 01:22:16.665890 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3103 01:22:16.669096 Pre-setting of DQS Precalculation
3104 01:22:16.676012 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3105 01:22:16.676123 ==
3106 01:22:16.678831 Dram Type= 6, Freq= 0, CH_1, rank 0
3107 01:22:16.682583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 01:22:16.682692 ==
3109 01:22:16.688780 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3110 01:22:16.692523 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3111 01:22:16.702074 [CA 0] Center 37 (7~67) winsize 61
3112 01:22:16.705868 [CA 1] Center 37 (7~68) winsize 62
3113 01:22:16.709164 [CA 2] Center 34 (4~64) winsize 61
3114 01:22:16.712146 [CA 3] Center 33 (3~64) winsize 62
3115 01:22:16.715315 [CA 4] Center 34 (4~64) winsize 61
3116 01:22:16.718949 [CA 5] Center 33 (3~63) winsize 61
3117 01:22:16.719054
3118 01:22:16.721997 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3119 01:22:16.722109
3120 01:22:16.725161 [CATrainingPosCal] consider 1 rank data
3121 01:22:16.728989 u2DelayCellTimex100 = 270/100 ps
3122 01:22:16.732108 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3123 01:22:16.735581 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3124 01:22:16.742115 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3125 01:22:16.745820 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3126 01:22:16.748761 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3127 01:22:16.751803 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3128 01:22:16.751910
3129 01:22:16.755507 CA PerBit enable=1, Macro0, CA PI delay=33
3130 01:22:16.755615
3131 01:22:16.758378 [CBTSetCACLKResult] CA Dly = 33
3132 01:22:16.758489 CS Dly: 5 (0~36)
3133 01:22:16.762276 ==
3134 01:22:16.762382 Dram Type= 6, Freq= 0, CH_1, rank 1
3135 01:22:16.768558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 01:22:16.768647 ==
3137 01:22:16.772059 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3138 01:22:16.778634 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3139 01:22:16.788002 [CA 0] Center 37 (7~67) winsize 61
3140 01:22:16.791058 [CA 1] Center 37 (7~68) winsize 62
3141 01:22:16.794505 [CA 2] Center 34 (4~65) winsize 62
3142 01:22:16.797449 [CA 3] Center 33 (3~64) winsize 62
3143 01:22:16.801168 [CA 4] Center 34 (4~65) winsize 62
3144 01:22:16.804753 [CA 5] Center 33 (3~63) winsize 61
3145 01:22:16.804833
3146 01:22:16.807877 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3147 01:22:16.807954
3148 01:22:16.811010 [CATrainingPosCal] consider 2 rank data
3149 01:22:16.814720 u2DelayCellTimex100 = 270/100 ps
3150 01:22:16.817726 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3151 01:22:16.821402 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3152 01:22:16.828252 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3153 01:22:16.831349 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3154 01:22:16.834582 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3155 01:22:16.837556 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3156 01:22:16.837641
3157 01:22:16.840740 CA PerBit enable=1, Macro0, CA PI delay=33
3158 01:22:16.840825
3159 01:22:16.844533 [CBTSetCACLKResult] CA Dly = 33
3160 01:22:16.844644 CS Dly: 7 (0~40)
3161 01:22:16.844739
3162 01:22:16.847474 ----->DramcWriteLeveling(PI) begin...
3163 01:22:16.851069 ==
3164 01:22:16.854652 Dram Type= 6, Freq= 0, CH_1, rank 0
3165 01:22:16.857733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3166 01:22:16.857851 ==
3167 01:22:16.860918 Write leveling (Byte 0): 25 => 25
3168 01:22:16.864565 Write leveling (Byte 1): 30 => 30
3169 01:22:16.867567 DramcWriteLeveling(PI) end<-----
3170 01:22:16.867654
3171 01:22:16.867742 ==
3172 01:22:16.870845 Dram Type= 6, Freq= 0, CH_1, rank 0
3173 01:22:16.874441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3174 01:22:16.874551 ==
3175 01:22:16.877357 [Gating] SW mode calibration
3176 01:22:16.884066 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3177 01:22:16.890840 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3178 01:22:16.894410 0 15 0 | B1->B0 | 3333 2d2d | 1 1 | (1 1) (0 0)
3179 01:22:16.897351 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 01:22:16.900755 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 01:22:16.907849 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 01:22:16.910557 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 01:22:16.913875 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3184 01:22:16.920654 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3185 01:22:16.924345 0 15 28 | B1->B0 | 2c2c 2f2f | 0 1 | (0 0) (1 0)
3186 01:22:16.927345 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 01:22:16.934314 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 01:22:16.937404 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 01:22:16.940442 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 01:22:16.947087 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 01:22:16.950489 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 01:22:16.953994 1 0 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3193 01:22:16.960724 1 0 28 | B1->B0 | 3d3d 3f3f | 0 0 | (0 0) (1 1)
3194 01:22:16.963790 1 1 0 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
3195 01:22:16.967545 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 01:22:16.974258 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 01:22:16.977114 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 01:22:16.980448 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 01:22:16.987108 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 01:22:16.990496 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 01:22:16.993969 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 01:22:17.000853 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 01:22:17.004081 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 01:22:17.007349 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 01:22:17.013983 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 01:22:17.017351 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 01:22:17.020588 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 01:22:17.023915 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 01:22:17.030863 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 01:22:17.034083 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 01:22:17.037256 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 01:22:17.043634 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 01:22:17.047251 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 01:22:17.050825 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 01:22:17.057183 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 01:22:17.060842 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 01:22:17.064170 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3218 01:22:17.070753 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 01:22:17.070868 Total UI for P1: 0, mck2ui 16
3220 01:22:17.077135 best dqsien dly found for B0: ( 1, 3, 28)
3221 01:22:17.077251 Total UI for P1: 0, mck2ui 16
3222 01:22:17.083873 best dqsien dly found for B1: ( 1, 3, 28)
3223 01:22:17.087353 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3224 01:22:17.090291 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3225 01:22:17.090379
3226 01:22:17.093867 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3227 01:22:17.097359 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3228 01:22:17.100634 [Gating] SW calibration Done
3229 01:22:17.100749 ==
3230 01:22:17.103717 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 01:22:17.107324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 01:22:17.107426 ==
3233 01:22:17.110512 RX Vref Scan: 0
3234 01:22:17.110599
3235 01:22:17.110689 RX Vref 0 -> 0, step: 1
3236 01:22:17.110773
3237 01:22:17.114163 RX Delay -40 -> 252, step: 8
3238 01:22:17.117163 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3239 01:22:17.124007 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3240 01:22:17.127039 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3241 01:22:17.130658 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3242 01:22:17.133632 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3243 01:22:17.136883 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3244 01:22:17.140650 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3245 01:22:17.147258 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3246 01:22:17.150316 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3247 01:22:17.154088 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3248 01:22:17.157037 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3249 01:22:17.160631 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3250 01:22:17.167236 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3251 01:22:17.170409 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3252 01:22:17.174005 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3253 01:22:17.177191 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3254 01:22:17.177281 ==
3255 01:22:17.180396 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 01:22:17.187242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 01:22:17.187350 ==
3258 01:22:17.187454 DQS Delay:
3259 01:22:17.190186 DQS0 = 0, DQS1 = 0
3260 01:22:17.190265 DQM Delay:
3261 01:22:17.190366 DQM0 = 114, DQM1 = 106
3262 01:22:17.193965 DQ Delay:
3263 01:22:17.197154 DQ0 =115, DQ1 =111, DQ2 =99, DQ3 =115
3264 01:22:17.200415 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3265 01:22:17.203945 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103
3266 01:22:17.206874 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3267 01:22:17.206978
3268 01:22:17.207062
3269 01:22:17.207163 ==
3270 01:22:17.210217 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 01:22:17.214067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 01:22:17.217044 ==
3273 01:22:17.217160
3274 01:22:17.217266
3275 01:22:17.217369 TX Vref Scan disable
3276 01:22:17.220212 == TX Byte 0 ==
3277 01:22:17.223972 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3278 01:22:17.227180 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3279 01:22:17.230417 == TX Byte 1 ==
3280 01:22:17.233452 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3281 01:22:17.236695 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3282 01:22:17.240429 ==
3283 01:22:17.240544 Dram Type= 6, Freq= 0, CH_1, rank 0
3284 01:22:17.246551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3285 01:22:17.246667 ==
3286 01:22:17.257775 TX Vref=22, minBit 3, minWin=25, winSum=414
3287 01:22:17.261471 TX Vref=24, minBit 3, minWin=25, winSum=417
3288 01:22:17.264545 TX Vref=26, minBit 3, minWin=25, winSum=424
3289 01:22:17.268092 TX Vref=28, minBit 1, minWin=26, winSum=426
3290 01:22:17.271054 TX Vref=30, minBit 9, minWin=25, winSum=430
3291 01:22:17.274759 TX Vref=32, minBit 0, minWin=26, winSum=424
3292 01:22:17.281501 [TxChooseVref] Worse bit 1, Min win 26, Win sum 426, Final Vref 28
3293 01:22:17.281599
3294 01:22:17.284690 Final TX Range 1 Vref 28
3295 01:22:17.284792
3296 01:22:17.284874 ==
3297 01:22:17.287824 Dram Type= 6, Freq= 0, CH_1, rank 0
3298 01:22:17.291011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3299 01:22:17.291124 ==
3300 01:22:17.291230
3301 01:22:17.294570
3302 01:22:17.294683 TX Vref Scan disable
3303 01:22:17.297656 == TX Byte 0 ==
3304 01:22:17.301357 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3305 01:22:17.304702 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3306 01:22:17.307692 == TX Byte 1 ==
3307 01:22:17.311554 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3308 01:22:17.314472 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3309 01:22:17.314585
3310 01:22:17.317788 [DATLAT]
3311 01:22:17.317877 Freq=1200, CH1 RK0
3312 01:22:17.317965
3313 01:22:17.321267 DATLAT Default: 0xd
3314 01:22:17.321380 0, 0xFFFF, sum = 0
3315 01:22:17.324137 1, 0xFFFF, sum = 0
3316 01:22:17.324252 2, 0xFFFF, sum = 0
3317 01:22:17.327978 3, 0xFFFF, sum = 0
3318 01:22:17.328068 4, 0xFFFF, sum = 0
3319 01:22:17.331021 5, 0xFFFF, sum = 0
3320 01:22:17.331137 6, 0xFFFF, sum = 0
3321 01:22:17.334157 7, 0xFFFF, sum = 0
3322 01:22:17.337999 8, 0xFFFF, sum = 0
3323 01:22:17.338114 9, 0xFFFF, sum = 0
3324 01:22:17.341243 10, 0xFFFF, sum = 0
3325 01:22:17.341333 11, 0xFFFF, sum = 0
3326 01:22:17.344691 12, 0x0, sum = 1
3327 01:22:17.344780 13, 0x0, sum = 2
3328 01:22:17.347579 14, 0x0, sum = 3
3329 01:22:17.347669 15, 0x0, sum = 4
3330 01:22:17.347773 best_step = 13
3331 01:22:17.347874
3332 01:22:17.351247 ==
3333 01:22:17.351355 Dram Type= 6, Freq= 0, CH_1, rank 0
3334 01:22:17.357978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3335 01:22:17.358069 ==
3336 01:22:17.358137 RX Vref Scan: 1
3337 01:22:17.358203
3338 01:22:17.361371 Set Vref Range= 32 -> 127
3339 01:22:17.361481
3340 01:22:17.364853 RX Vref 32 -> 127, step: 1
3341 01:22:17.364936
3342 01:22:17.368154 RX Delay -21 -> 252, step: 4
3343 01:22:17.368236
3344 01:22:17.371601 Set Vref, RX VrefLevel [Byte0]: 32
3345 01:22:17.374498 [Byte1]: 32
3346 01:22:17.374610
3347 01:22:17.377784 Set Vref, RX VrefLevel [Byte0]: 33
3348 01:22:17.381432 [Byte1]: 33
3349 01:22:17.381523
3350 01:22:17.384423 Set Vref, RX VrefLevel [Byte0]: 34
3351 01:22:17.387526 [Byte1]: 34
3352 01:22:17.391974
3353 01:22:17.392083 Set Vref, RX VrefLevel [Byte0]: 35
3354 01:22:17.395263 [Byte1]: 35
3355 01:22:17.400042
3356 01:22:17.400125 Set Vref, RX VrefLevel [Byte0]: 36
3357 01:22:17.403520 [Byte1]: 36
3358 01:22:17.407972
3359 01:22:17.408054 Set Vref, RX VrefLevel [Byte0]: 37
3360 01:22:17.410985 [Byte1]: 37
3361 01:22:17.415967
3362 01:22:17.416049 Set Vref, RX VrefLevel [Byte0]: 38
3363 01:22:17.419213 [Byte1]: 38
3364 01:22:17.423830
3365 01:22:17.423950 Set Vref, RX VrefLevel [Byte0]: 39
3366 01:22:17.427200 [Byte1]: 39
3367 01:22:17.431607
3368 01:22:17.431692 Set Vref, RX VrefLevel [Byte0]: 40
3369 01:22:17.434702 [Byte1]: 40
3370 01:22:17.439789
3371 01:22:17.439876 Set Vref, RX VrefLevel [Byte0]: 41
3372 01:22:17.442836 [Byte1]: 41
3373 01:22:17.447223
3374 01:22:17.447318 Set Vref, RX VrefLevel [Byte0]: 42
3375 01:22:17.450890 [Byte1]: 42
3376 01:22:17.455610
3377 01:22:17.455695 Set Vref, RX VrefLevel [Byte0]: 43
3378 01:22:17.458679 [Byte1]: 43
3379 01:22:17.463494
3380 01:22:17.463577 Set Vref, RX VrefLevel [Byte0]: 44
3381 01:22:17.466599 [Byte1]: 44
3382 01:22:17.471503
3383 01:22:17.471593 Set Vref, RX VrefLevel [Byte0]: 45
3384 01:22:17.474475 [Byte1]: 45
3385 01:22:17.479117
3386 01:22:17.479206 Set Vref, RX VrefLevel [Byte0]: 46
3387 01:22:17.482543 [Byte1]: 46
3388 01:22:17.487067
3389 01:22:17.487153 Set Vref, RX VrefLevel [Byte0]: 47
3390 01:22:17.490514 [Byte1]: 47
3391 01:22:17.494768
3392 01:22:17.494854 Set Vref, RX VrefLevel [Byte0]: 48
3393 01:22:17.497970 [Byte1]: 48
3394 01:22:17.502696
3395 01:22:17.502773 Set Vref, RX VrefLevel [Byte0]: 49
3396 01:22:17.506369 [Byte1]: 49
3397 01:22:17.511153
3398 01:22:17.511237 Set Vref, RX VrefLevel [Byte0]: 50
3399 01:22:17.513866 [Byte1]: 50
3400 01:22:17.519032
3401 01:22:17.519127 Set Vref, RX VrefLevel [Byte0]: 51
3402 01:22:17.522208 [Byte1]: 51
3403 01:22:17.527093
3404 01:22:17.527187 Set Vref, RX VrefLevel [Byte0]: 52
3405 01:22:17.530121 [Byte1]: 52
3406 01:22:17.534445
3407 01:22:17.534520 Set Vref, RX VrefLevel [Byte0]: 53
3408 01:22:17.537753 [Byte1]: 53
3409 01:22:17.542773
3410 01:22:17.542855 Set Vref, RX VrefLevel [Byte0]: 54
3411 01:22:17.545861 [Byte1]: 54
3412 01:22:17.550358
3413 01:22:17.550445 Set Vref, RX VrefLevel [Byte0]: 55
3414 01:22:17.553975 [Byte1]: 55
3415 01:22:17.558310
3416 01:22:17.558402 Set Vref, RX VrefLevel [Byte0]: 56
3417 01:22:17.561585 [Byte1]: 56
3418 01:22:17.566428
3419 01:22:17.566519 Set Vref, RX VrefLevel [Byte0]: 57
3420 01:22:17.569643 [Byte1]: 57
3421 01:22:17.574562
3422 01:22:17.574655 Set Vref, RX VrefLevel [Byte0]: 58
3423 01:22:17.577484 [Byte1]: 58
3424 01:22:17.582440
3425 01:22:17.582552 Set Vref, RX VrefLevel [Byte0]: 59
3426 01:22:17.585216 [Byte1]: 59
3427 01:22:17.590379
3428 01:22:17.590537 Set Vref, RX VrefLevel [Byte0]: 60
3429 01:22:17.593532 [Byte1]: 60
3430 01:22:17.598040
3431 01:22:17.598157 Set Vref, RX VrefLevel [Byte0]: 61
3432 01:22:17.601268 [Byte1]: 61
3433 01:22:17.606005
3434 01:22:17.606094 Set Vref, RX VrefLevel [Byte0]: 62
3435 01:22:17.609114 [Byte1]: 62
3436 01:22:17.613961
3437 01:22:17.614048 Set Vref, RX VrefLevel [Byte0]: 63
3438 01:22:17.617165 [Byte1]: 63
3439 01:22:17.622027
3440 01:22:17.622112 Set Vref, RX VrefLevel [Byte0]: 64
3441 01:22:17.625236 [Byte1]: 64
3442 01:22:17.629581
3443 01:22:17.629697 Set Vref, RX VrefLevel [Byte0]: 65
3444 01:22:17.636415 [Byte1]: 65
3445 01:22:17.636523
3446 01:22:17.639484 Set Vref, RX VrefLevel [Byte0]: 66
3447 01:22:17.642695 [Byte1]: 66
3448 01:22:17.642792
3449 01:22:17.646214 Set Vref, RX VrefLevel [Byte0]: 67
3450 01:22:17.649018 [Byte1]: 67
3451 01:22:17.653126
3452 01:22:17.653227 Final RX Vref Byte 0 = 54 to rank0
3453 01:22:17.656847 Final RX Vref Byte 1 = 48 to rank0
3454 01:22:17.659820 Final RX Vref Byte 0 = 54 to rank1
3455 01:22:17.663266 Final RX Vref Byte 1 = 48 to rank1==
3456 01:22:17.666849 Dram Type= 6, Freq= 0, CH_1, rank 0
3457 01:22:17.673479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3458 01:22:17.673602 ==
3459 01:22:17.673673 DQS Delay:
3460 01:22:17.673735 DQS0 = 0, DQS1 = 0
3461 01:22:17.676622 DQM Delay:
3462 01:22:17.676700 DQM0 = 114, DQM1 = 105
3463 01:22:17.680377 DQ Delay:
3464 01:22:17.683507 DQ0 =118, DQ1 =110, DQ2 =104, DQ3 =112
3465 01:22:17.686597 DQ4 =112, DQ5 =122, DQ6 =126, DQ7 =112
3466 01:22:17.690156 DQ8 =92, DQ9 =98, DQ10 =104, DQ11 =100
3467 01:22:17.693592 DQ12 =112, DQ13 =110, DQ14 =114, DQ15 =110
3468 01:22:17.693673
3469 01:22:17.693747
3470 01:22:17.700363 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f7, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
3471 01:22:17.703369 CH1 RK0: MR19=303, MR18=F0F7
3472 01:22:17.710075 CH1_RK0: MR19=0x303, MR18=0xF0F7, DQSOSC=413, MR23=63, INC=38, DEC=25
3473 01:22:17.710189
3474 01:22:17.713728 ----->DramcWriteLeveling(PI) begin...
3475 01:22:17.713852 ==
3476 01:22:17.716711 Dram Type= 6, Freq= 0, CH_1, rank 1
3477 01:22:17.719826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3478 01:22:17.723408 ==
3479 01:22:17.723500 Write leveling (Byte 0): 24 => 24
3480 01:22:17.726607 Write leveling (Byte 1): 26 => 26
3481 01:22:17.730342 DramcWriteLeveling(PI) end<-----
3482 01:22:17.730434
3483 01:22:17.730504 ==
3484 01:22:17.733181 Dram Type= 6, Freq= 0, CH_1, rank 1
3485 01:22:17.740007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3486 01:22:17.740106 ==
3487 01:22:17.740177 [Gating] SW mode calibration
3488 01:22:17.750084 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3489 01:22:17.753648 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3490 01:22:17.756545 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3491 01:22:17.763115 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3492 01:22:17.766820 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3493 01:22:17.769821 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 01:22:17.776653 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 01:22:17.779824 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3496 01:22:17.782992 0 15 24 | B1->B0 | 3131 2525 | 1 1 | (1 1) (1 0)
3497 01:22:17.789797 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3498 01:22:17.793381 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3499 01:22:17.796874 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3500 01:22:17.803059 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 01:22:17.806389 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 01:22:17.809726 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 01:22:17.816605 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3504 01:22:17.819880 1 0 24 | B1->B0 | 2c2c 4545 | 0 0 | (0 0) (0 0)
3505 01:22:17.822890 1 0 28 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
3506 01:22:17.829577 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 01:22:17.832680 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 01:22:17.835945 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 01:22:17.842733 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 01:22:17.846153 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 01:22:17.849433 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 01:22:17.856218 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3513 01:22:17.859333 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3514 01:22:17.863002 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 01:22:17.868994 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 01:22:17.872628 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 01:22:17.876199 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 01:22:17.882554 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 01:22:17.885893 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 01:22:17.888994 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 01:22:17.895843 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 01:22:17.898883 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 01:22:17.902668 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 01:22:17.909347 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 01:22:17.912377 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 01:22:17.915772 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 01:22:17.922186 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 01:22:17.925529 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3529 01:22:17.928995 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3530 01:22:17.932249 Total UI for P1: 0, mck2ui 16
3531 01:22:17.935912 best dqsien dly found for B0: ( 1, 3, 24)
3532 01:22:17.939016 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 01:22:17.942115 Total UI for P1: 0, mck2ui 16
3534 01:22:17.945905 best dqsien dly found for B1: ( 1, 3, 26)
3535 01:22:17.948805 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3536 01:22:17.955334 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3537 01:22:17.955434
3538 01:22:17.958626 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3539 01:22:17.961986 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3540 01:22:17.965799 [Gating] SW calibration Done
3541 01:22:17.965887 ==
3542 01:22:17.969043 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 01:22:17.972067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 01:22:17.972189 ==
3545 01:22:17.975267 RX Vref Scan: 0
3546 01:22:17.975359
3547 01:22:17.975427 RX Vref 0 -> 0, step: 1
3548 01:22:17.975489
3549 01:22:17.978856 RX Delay -40 -> 252, step: 8
3550 01:22:17.981992 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3551 01:22:17.988563 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3552 01:22:17.991850 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3553 01:22:17.995024 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3554 01:22:17.998594 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3555 01:22:18.001787 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3556 01:22:18.005334 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3557 01:22:18.011547 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3558 01:22:18.014776 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3559 01:22:18.018486 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3560 01:22:18.021650 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3561 01:22:18.024681 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3562 01:22:18.031452 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3563 01:22:18.034867 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3564 01:22:18.038074 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3565 01:22:18.041309 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3566 01:22:18.041427 ==
3567 01:22:18.044650 Dram Type= 6, Freq= 0, CH_1, rank 1
3568 01:22:18.051662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3569 01:22:18.051805 ==
3570 01:22:18.051906 DQS Delay:
3571 01:22:18.054681 DQS0 = 0, DQS1 = 0
3572 01:22:18.054801 DQM Delay:
3573 01:22:18.057806 DQM0 = 110, DQM1 = 106
3574 01:22:18.057892 DQ Delay:
3575 01:22:18.061418 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3576 01:22:18.064416 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3577 01:22:18.067734 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
3578 01:22:18.071220 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3579 01:22:18.071342
3580 01:22:18.071441
3581 01:22:18.071535 ==
3582 01:22:18.074184 Dram Type= 6, Freq= 0, CH_1, rank 1
3583 01:22:18.081037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3584 01:22:18.081205 ==
3585 01:22:18.081306
3586 01:22:18.081407
3587 01:22:18.081498 TX Vref Scan disable
3588 01:22:18.084209 == TX Byte 0 ==
3589 01:22:18.088005 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3590 01:22:18.090794 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3591 01:22:18.094122 == TX Byte 1 ==
3592 01:22:18.097514 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3593 01:22:18.101010 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3594 01:22:18.104286 ==
3595 01:22:18.107225 Dram Type= 6, Freq= 0, CH_1, rank 1
3596 01:22:18.111029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3597 01:22:18.111188 ==
3598 01:22:18.122079 TX Vref=22, minBit 9, minWin=25, winSum=415
3599 01:22:18.125171 TX Vref=24, minBit 0, minWin=25, winSum=423
3600 01:22:18.128896 TX Vref=26, minBit 8, minWin=26, winSum=432
3601 01:22:18.131834 TX Vref=28, minBit 8, minWin=26, winSum=432
3602 01:22:18.134989 TX Vref=30, minBit 4, minWin=26, winSum=434
3603 01:22:18.142129 TX Vref=32, minBit 0, minWin=26, winSum=429
3604 01:22:18.145132 [TxChooseVref] Worse bit 4, Min win 26, Win sum 434, Final Vref 30
3605 01:22:18.145284
3606 01:22:18.148381 Final TX Range 1 Vref 30
3607 01:22:18.148482
3608 01:22:18.148553 ==
3609 01:22:18.151714 Dram Type= 6, Freq= 0, CH_1, rank 1
3610 01:22:18.154718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3611 01:22:18.158496 ==
3612 01:22:18.158601
3613 01:22:18.158671
3614 01:22:18.158733 TX Vref Scan disable
3615 01:22:18.161875 == TX Byte 0 ==
3616 01:22:18.164930 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3617 01:22:18.171586 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3618 01:22:18.171724 == TX Byte 1 ==
3619 01:22:18.175138 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3620 01:22:18.181335 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3621 01:22:18.181496
3622 01:22:18.181610 [DATLAT]
3623 01:22:18.181710 Freq=1200, CH1 RK1
3624 01:22:18.181801
3625 01:22:18.185084 DATLAT Default: 0xd
3626 01:22:18.188315 0, 0xFFFF, sum = 0
3627 01:22:18.188426 1, 0xFFFF, sum = 0
3628 01:22:18.191442 2, 0xFFFF, sum = 0
3629 01:22:18.191540 3, 0xFFFF, sum = 0
3630 01:22:18.194621 4, 0xFFFF, sum = 0
3631 01:22:18.194711 5, 0xFFFF, sum = 0
3632 01:22:18.198190 6, 0xFFFF, sum = 0
3633 01:22:18.198281 7, 0xFFFF, sum = 0
3634 01:22:18.201232 8, 0xFFFF, sum = 0
3635 01:22:18.201330 9, 0xFFFF, sum = 0
3636 01:22:18.204592 10, 0xFFFF, sum = 0
3637 01:22:18.204701 11, 0xFFFF, sum = 0
3638 01:22:18.207901 12, 0x0, sum = 1
3639 01:22:18.208013 13, 0x0, sum = 2
3640 01:22:18.211290 14, 0x0, sum = 3
3641 01:22:18.211401 15, 0x0, sum = 4
3642 01:22:18.214372 best_step = 13
3643 01:22:18.214463
3644 01:22:18.214531 ==
3645 01:22:18.218220 Dram Type= 6, Freq= 0, CH_1, rank 1
3646 01:22:18.221421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3647 01:22:18.221548 ==
3648 01:22:18.221653 RX Vref Scan: 0
3649 01:22:18.224402
3650 01:22:18.224508 RX Vref 0 -> 0, step: 1
3651 01:22:18.224601
3652 01:22:18.227566 RX Delay -21 -> 252, step: 4
3653 01:22:18.234237 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3654 01:22:18.238115 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3655 01:22:18.240828 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3656 01:22:18.244479 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3657 01:22:18.247487 iDelay=195, Bit 4, Center 106 (35 ~ 178) 144
3658 01:22:18.254156 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3659 01:22:18.257747 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3660 01:22:18.261204 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3661 01:22:18.264279 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3662 01:22:18.267609 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3663 01:22:18.274054 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3664 01:22:18.277327 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3665 01:22:18.280872 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3666 01:22:18.284069 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3667 01:22:18.287220 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3668 01:22:18.293896 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3669 01:22:18.294025 ==
3670 01:22:18.297415 Dram Type= 6, Freq= 0, CH_1, rank 1
3671 01:22:18.301009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3672 01:22:18.301135 ==
3673 01:22:18.301233 DQS Delay:
3674 01:22:18.304123 DQS0 = 0, DQS1 = 0
3675 01:22:18.304228 DQM Delay:
3676 01:22:18.307155 DQM0 = 111, DQM1 = 109
3677 01:22:18.307276 DQ Delay:
3678 01:22:18.310785 DQ0 =114, DQ1 =110, DQ2 =100, DQ3 =108
3679 01:22:18.314318 DQ4 =106, DQ5 =122, DQ6 =122, DQ7 =108
3680 01:22:18.317139 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =102
3681 01:22:18.320363 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3682 01:22:18.320515
3683 01:22:18.324107
3684 01:22:18.330347 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa0a, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3685 01:22:18.334039 CH1 RK1: MR19=304, MR18=FA0A
3686 01:22:18.340393 CH1_RK1: MR19=0x304, MR18=0xFA0A, DQSOSC=406, MR23=63, INC=39, DEC=26
3687 01:22:18.343435 [RxdqsGatingPostProcess] freq 1200
3688 01:22:18.347085 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3689 01:22:18.350667 best DQS0 dly(2T, 0.5T) = (0, 11)
3690 01:22:18.353687 best DQS1 dly(2T, 0.5T) = (0, 11)
3691 01:22:18.356787 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3692 01:22:18.360299 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3693 01:22:18.363567 best DQS0 dly(2T, 0.5T) = (0, 11)
3694 01:22:18.366568 best DQS1 dly(2T, 0.5T) = (0, 11)
3695 01:22:18.370230 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3696 01:22:18.373311 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3697 01:22:18.376504 Pre-setting of DQS Precalculation
3698 01:22:18.380160 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3699 01:22:18.386735 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3700 01:22:18.396552 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3701 01:22:18.396713
3702 01:22:18.396802
3703 01:22:18.399953 [Calibration Summary] 2400 Mbps
3704 01:22:18.400076 CH 0, Rank 0
3705 01:22:18.402991 SW Impedance : PASS
3706 01:22:18.403110 DUTY Scan : NO K
3707 01:22:18.406700 ZQ Calibration : PASS
3708 01:22:18.409884 Jitter Meter : NO K
3709 01:22:18.410001 CBT Training : PASS
3710 01:22:18.413165 Write leveling : PASS
3711 01:22:18.416145 RX DQS gating : PASS
3712 01:22:18.416296 RX DQ/DQS(RDDQC) : PASS
3713 01:22:18.419708 TX DQ/DQS : PASS
3714 01:22:18.419845 RX DATLAT : PASS
3715 01:22:18.423272 RX DQ/DQS(Engine): PASS
3716 01:22:18.426618 TX OE : NO K
3717 01:22:18.426777 All Pass.
3718 01:22:18.426880
3719 01:22:18.426971 CH 0, Rank 1
3720 01:22:18.429492 SW Impedance : PASS
3721 01:22:18.433034 DUTY Scan : NO K
3722 01:22:18.433158 ZQ Calibration : PASS
3723 01:22:18.436122 Jitter Meter : NO K
3724 01:22:18.439749 CBT Training : PASS
3725 01:22:18.439886 Write leveling : PASS
3726 01:22:18.442966 RX DQS gating : PASS
3727 01:22:18.446028 RX DQ/DQS(RDDQC) : PASS
3728 01:22:18.446125 TX DQ/DQS : PASS
3729 01:22:18.449747 RX DATLAT : PASS
3730 01:22:18.452762 RX DQ/DQS(Engine): PASS
3731 01:22:18.452865 TX OE : NO K
3732 01:22:18.456198 All Pass.
3733 01:22:18.456341
3734 01:22:18.456438 CH 1, Rank 0
3735 01:22:18.459283 SW Impedance : PASS
3736 01:22:18.459459 DUTY Scan : NO K
3737 01:22:18.463182 ZQ Calibration : PASS
3738 01:22:18.466027 Jitter Meter : NO K
3739 01:22:18.466145 CBT Training : PASS
3740 01:22:18.469171 Write leveling : PASS
3741 01:22:18.472477 RX DQS gating : PASS
3742 01:22:18.472668 RX DQ/DQS(RDDQC) : PASS
3743 01:22:18.476005 TX DQ/DQS : PASS
3744 01:22:18.479047 RX DATLAT : PASS
3745 01:22:18.479241 RX DQ/DQS(Engine): PASS
3746 01:22:18.482608 TX OE : NO K
3747 01:22:18.482804 All Pass.
3748 01:22:18.482945
3749 01:22:18.485723 CH 1, Rank 1
3750 01:22:18.485900 SW Impedance : PASS
3751 01:22:18.489020 DUTY Scan : NO K
3752 01:22:18.489164 ZQ Calibration : PASS
3753 01:22:18.492504 Jitter Meter : NO K
3754 01:22:18.496202 CBT Training : PASS
3755 01:22:18.496365 Write leveling : PASS
3756 01:22:18.499201 RX DQS gating : PASS
3757 01:22:18.502343 RX DQ/DQS(RDDQC) : PASS
3758 01:22:18.502475 TX DQ/DQS : PASS
3759 01:22:18.506039 RX DATLAT : PASS
3760 01:22:18.508964 RX DQ/DQS(Engine): PASS
3761 01:22:18.509082 TX OE : NO K
3762 01:22:18.512556 All Pass.
3763 01:22:18.512689
3764 01:22:18.512780 DramC Write-DBI off
3765 01:22:18.515517 PER_BANK_REFRESH: Hybrid Mode
3766 01:22:18.515641 TX_TRACKING: ON
3767 01:22:18.525730 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3768 01:22:18.529066 [FAST_K] Save calibration result to emmc
3769 01:22:18.532044 dramc_set_vcore_voltage set vcore to 650000
3770 01:22:18.535521 Read voltage for 600, 5
3771 01:22:18.535658 Vio18 = 0
3772 01:22:18.538839 Vcore = 650000
3773 01:22:18.538956 Vdram = 0
3774 01:22:18.539051 Vddq = 0
3775 01:22:18.541828 Vmddr = 0
3776 01:22:18.545480 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3777 01:22:18.552274 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3778 01:22:18.552419 MEM_TYPE=3, freq_sel=19
3779 01:22:18.555383 sv_algorithm_assistance_LP4_1600
3780 01:22:18.561782 ============ PULL DRAM RESETB DOWN ============
3781 01:22:18.565538 ========== PULL DRAM RESETB DOWN end =========
3782 01:22:18.568679 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3783 01:22:18.571711 ===================================
3784 01:22:18.575249 LPDDR4 DRAM CONFIGURATION
3785 01:22:18.578712 ===================================
3786 01:22:18.581622 EX_ROW_EN[0] = 0x0
3787 01:22:18.581717 EX_ROW_EN[1] = 0x0
3788 01:22:18.585258 LP4Y_EN = 0x0
3789 01:22:18.585348 WORK_FSP = 0x0
3790 01:22:18.588782 WL = 0x2
3791 01:22:18.588873 RL = 0x2
3792 01:22:18.592107 BL = 0x2
3793 01:22:18.592196 RPST = 0x0
3794 01:22:18.594956 RD_PRE = 0x0
3795 01:22:18.595042 WR_PRE = 0x1
3796 01:22:18.598633 WR_PST = 0x0
3797 01:22:18.598722 DBI_WR = 0x0
3798 01:22:18.601809 DBI_RD = 0x0
3799 01:22:18.601904 OTF = 0x1
3800 01:22:18.605451 ===================================
3801 01:22:18.608584 ===================================
3802 01:22:18.611705 ANA top config
3803 01:22:18.614680 ===================================
3804 01:22:18.618258 DLL_ASYNC_EN = 0
3805 01:22:18.618359 ALL_SLAVE_EN = 1
3806 01:22:18.621388 NEW_RANK_MODE = 1
3807 01:22:18.625087 DLL_IDLE_MODE = 1
3808 01:22:18.628037 LP45_APHY_COMB_EN = 1
3809 01:22:18.628170 TX_ODT_DIS = 1
3810 01:22:18.631590 NEW_8X_MODE = 1
3811 01:22:18.634975 ===================================
3812 01:22:18.638262 ===================================
3813 01:22:18.641458 data_rate = 1200
3814 01:22:18.644861 CKR = 1
3815 01:22:18.648182 DQ_P2S_RATIO = 8
3816 01:22:18.651352 ===================================
3817 01:22:18.655034 CA_P2S_RATIO = 8
3818 01:22:18.655139 DQ_CA_OPEN = 0
3819 01:22:18.658078 DQ_SEMI_OPEN = 0
3820 01:22:18.661307 CA_SEMI_OPEN = 0
3821 01:22:18.665041 CA_FULL_RATE = 0
3822 01:22:18.667939 DQ_CKDIV4_EN = 1
3823 01:22:18.671678 CA_CKDIV4_EN = 1
3824 01:22:18.671781 CA_PREDIV_EN = 0
3825 01:22:18.674924 PH8_DLY = 0
3826 01:22:18.677791 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3827 01:22:18.681535 DQ_AAMCK_DIV = 4
3828 01:22:18.684393 CA_AAMCK_DIV = 4
3829 01:22:18.687898 CA_ADMCK_DIV = 4
3830 01:22:18.687992 DQ_TRACK_CA_EN = 0
3831 01:22:18.691395 CA_PICK = 600
3832 01:22:18.694244 CA_MCKIO = 600
3833 01:22:18.697847 MCKIO_SEMI = 0
3834 01:22:18.701031 PLL_FREQ = 2288
3835 01:22:18.704690 DQ_UI_PI_RATIO = 32
3836 01:22:18.707929 CA_UI_PI_RATIO = 0
3837 01:22:18.710959 ===================================
3838 01:22:18.714107 ===================================
3839 01:22:18.714228 memory_type:LPDDR4
3840 01:22:18.717668 GP_NUM : 10
3841 01:22:18.721245 SRAM_EN : 1
3842 01:22:18.721349 MD32_EN : 0
3843 01:22:18.724014 ===================================
3844 01:22:18.727268 [ANA_INIT] >>>>>>>>>>>>>>
3845 01:22:18.731023 <<<<<< [CONFIGURE PHASE]: ANA_TX
3846 01:22:18.733980 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3847 01:22:18.737693 ===================================
3848 01:22:18.740774 data_rate = 1200,PCW = 0X5800
3849 01:22:18.743803 ===================================
3850 01:22:18.747365 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3851 01:22:18.750699 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3852 01:22:18.757067 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3853 01:22:18.760367 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3854 01:22:18.764027 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3855 01:22:18.767244 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3856 01:22:18.770212 [ANA_INIT] flow start
3857 01:22:18.773681 [ANA_INIT] PLL >>>>>>>>
3858 01:22:18.773782 [ANA_INIT] PLL <<<<<<<<
3859 01:22:18.777415 [ANA_INIT] MIDPI >>>>>>>>
3860 01:22:18.780357 [ANA_INIT] MIDPI <<<<<<<<
3861 01:22:18.783494 [ANA_INIT] DLL >>>>>>>>
3862 01:22:18.783590 [ANA_INIT] flow end
3863 01:22:18.787152 ============ LP4 DIFF to SE enter ============
3864 01:22:18.793372 ============ LP4 DIFF to SE exit ============
3865 01:22:18.793487 [ANA_INIT] <<<<<<<<<<<<<
3866 01:22:18.797037 [Flow] Enable top DCM control >>>>>
3867 01:22:18.799966 [Flow] Enable top DCM control <<<<<
3868 01:22:18.803500 Enable DLL master slave shuffle
3869 01:22:18.810188 ==============================================================
3870 01:22:18.810308 Gating Mode config
3871 01:22:18.816870 ==============================================================
3872 01:22:18.820001 Config description:
3873 01:22:18.829826 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3874 01:22:18.837012 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3875 01:22:18.839952 SELPH_MODE 0: By rank 1: By Phase
3876 01:22:18.846297 ==============================================================
3877 01:22:18.850020 GAT_TRACK_EN = 1
3878 01:22:18.853065 RX_GATING_MODE = 2
3879 01:22:18.853166 RX_GATING_TRACK_MODE = 2
3880 01:22:18.856516 SELPH_MODE = 1
3881 01:22:18.860003 PICG_EARLY_EN = 1
3882 01:22:18.863077 VALID_LAT_VALUE = 1
3883 01:22:18.869608 ==============================================================
3884 01:22:18.872963 Enter into Gating configuration >>>>
3885 01:22:18.876027 Exit from Gating configuration <<<<
3886 01:22:18.879569 Enter into DVFS_PRE_config >>>>>
3887 01:22:18.889522 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3888 01:22:18.892570 Exit from DVFS_PRE_config <<<<<
3889 01:22:18.896179 Enter into PICG configuration >>>>
3890 01:22:18.899154 Exit from PICG configuration <<<<
3891 01:22:18.902719 [RX_INPUT] configuration >>>>>
3892 01:22:18.905733 [RX_INPUT] configuration <<<<<
3893 01:22:18.909138 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3894 01:22:18.915562 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3895 01:22:18.922370 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3896 01:22:18.929260 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3897 01:22:18.935407 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3898 01:22:18.938942 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3899 01:22:18.945562 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3900 01:22:18.949288 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3901 01:22:18.952346 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3902 01:22:18.955486 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3903 01:22:18.962133 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3904 01:22:18.965174 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3905 01:22:18.968593 ===================================
3906 01:22:18.972125 LPDDR4 DRAM CONFIGURATION
3907 01:22:18.975370 ===================================
3908 01:22:18.975464 EX_ROW_EN[0] = 0x0
3909 01:22:18.978399 EX_ROW_EN[1] = 0x0
3910 01:22:18.978484 LP4Y_EN = 0x0
3911 01:22:18.981822 WORK_FSP = 0x0
3912 01:22:18.981914 WL = 0x2
3913 01:22:18.985060 RL = 0x2
3914 01:22:18.985148 BL = 0x2
3915 01:22:18.988307 RPST = 0x0
3916 01:22:18.991868 RD_PRE = 0x0
3917 01:22:18.991965 WR_PRE = 0x1
3918 01:22:18.994949 WR_PST = 0x0
3919 01:22:18.995043 DBI_WR = 0x0
3920 01:22:18.998321 DBI_RD = 0x0
3921 01:22:18.998409 OTF = 0x1
3922 01:22:19.001886 ===================================
3923 01:22:19.004941 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3924 01:22:19.011776 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3925 01:22:19.015257 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3926 01:22:19.018217 ===================================
3927 01:22:19.021547 LPDDR4 DRAM CONFIGURATION
3928 01:22:19.025113 ===================================
3929 01:22:19.025243 EX_ROW_EN[0] = 0x10
3930 01:22:19.028157 EX_ROW_EN[1] = 0x0
3931 01:22:19.028254 LP4Y_EN = 0x0
3932 01:22:19.031792 WORK_FSP = 0x0
3933 01:22:19.031913 WL = 0x2
3934 01:22:19.034958 RL = 0x2
3935 01:22:19.035049 BL = 0x2
3936 01:22:19.038060 RPST = 0x0
3937 01:22:19.038156 RD_PRE = 0x0
3938 01:22:19.041970 WR_PRE = 0x1
3939 01:22:19.042067 WR_PST = 0x0
3940 01:22:19.044956 DBI_WR = 0x0
3941 01:22:19.047895 DBI_RD = 0x0
3942 01:22:19.048006 OTF = 0x1
3943 01:22:19.051642 ===================================
3944 01:22:19.057720 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3945 01:22:19.061571 nWR fixed to 30
3946 01:22:19.065248 [ModeRegInit_LP4] CH0 RK0
3947 01:22:19.065365 [ModeRegInit_LP4] CH0 RK1
3948 01:22:19.068284 [ModeRegInit_LP4] CH1 RK0
3949 01:22:19.071984 [ModeRegInit_LP4] CH1 RK1
3950 01:22:19.072076 match AC timing 17
3951 01:22:19.078289 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3952 01:22:19.081337 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3953 01:22:19.084987 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3954 01:22:19.091071 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3955 01:22:19.094599 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3956 01:22:19.094696 ==
3957 01:22:19.098017 Dram Type= 6, Freq= 0, CH_0, rank 0
3958 01:22:19.101304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3959 01:22:19.101402 ==
3960 01:22:19.107653 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3961 01:22:19.114419 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3962 01:22:19.117889 [CA 0] Center 37 (7~67) winsize 61
3963 01:22:19.121364 [CA 1] Center 37 (7~67) winsize 61
3964 01:22:19.124227 [CA 2] Center 35 (5~65) winsize 61
3965 01:22:19.127664 [CA 3] Center 35 (5~65) winsize 61
3966 01:22:19.131055 [CA 4] Center 34 (4~65) winsize 62
3967 01:22:19.134125 [CA 5] Center 33 (3~64) winsize 62
3968 01:22:19.134272
3969 01:22:19.137367 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3970 01:22:19.137494
3971 01:22:19.141031 [CATrainingPosCal] consider 1 rank data
3972 01:22:19.144043 u2DelayCellTimex100 = 270/100 ps
3973 01:22:19.147165 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3974 01:22:19.150967 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
3975 01:22:19.153813 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3976 01:22:19.160590 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
3977 01:22:19.163775 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3978 01:22:19.167425 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3979 01:22:19.167547
3980 01:22:19.170625 CA PerBit enable=1, Macro0, CA PI delay=33
3981 01:22:19.170745
3982 01:22:19.173651 [CBTSetCACLKResult] CA Dly = 33
3983 01:22:19.173762 CS Dly: 5 (0~36)
3984 01:22:19.173834 ==
3985 01:22:19.177310 Dram Type= 6, Freq= 0, CH_0, rank 1
3986 01:22:19.184078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3987 01:22:19.184233 ==
3988 01:22:19.186894 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3989 01:22:19.193563 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3990 01:22:19.197389 [CA 0] Center 37 (7~67) winsize 61
3991 01:22:19.200591 [CA 1] Center 37 (7~67) winsize 61
3992 01:22:19.204315 [CA 2] Center 35 (5~65) winsize 61
3993 01:22:19.207139 [CA 3] Center 35 (5~65) winsize 61
3994 01:22:19.210756 [CA 4] Center 34 (4~65) winsize 62
3995 01:22:19.213641 [CA 5] Center 33 (3~64) winsize 62
3996 01:22:19.213732
3997 01:22:19.216894 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3998 01:22:19.217004
3999 01:22:19.220599 [CATrainingPosCal] consider 2 rank data
4000 01:22:19.223519 u2DelayCellTimex100 = 270/100 ps
4001 01:22:19.227018 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
4002 01:22:19.233737 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
4003 01:22:19.237305 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4004 01:22:19.240082 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
4005 01:22:19.243728 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4006 01:22:19.246811 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4007 01:22:19.246942
4008 01:22:19.250624 CA PerBit enable=1, Macro0, CA PI delay=33
4009 01:22:19.250752
4010 01:22:19.253667 [CBTSetCACLKResult] CA Dly = 33
4011 01:22:19.253784 CS Dly: 6 (0~38)
4012 01:22:19.256771
4013 01:22:19.260428 ----->DramcWriteLeveling(PI) begin...
4014 01:22:19.260524 ==
4015 01:22:19.263508 Dram Type= 6, Freq= 0, CH_0, rank 0
4016 01:22:19.267274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4017 01:22:19.267380 ==
4018 01:22:19.270448 Write leveling (Byte 0): 32 => 32
4019 01:22:19.273413 Write leveling (Byte 1): 30 => 30
4020 01:22:19.277165 DramcWriteLeveling(PI) end<-----
4021 01:22:19.277257
4022 01:22:19.277322 ==
4023 01:22:19.280056 Dram Type= 6, Freq= 0, CH_0, rank 0
4024 01:22:19.283771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4025 01:22:19.283858 ==
4026 01:22:19.286812 [Gating] SW mode calibration
4027 01:22:19.293470 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4028 01:22:19.300181 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4029 01:22:19.303833 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4030 01:22:19.307009 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4031 01:22:19.313703 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4032 01:22:19.316762 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
4033 01:22:19.319825 0 9 16 | B1->B0 | 3030 2e2e | 1 0 | (0 0) (1 1)
4034 01:22:19.326466 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 01:22:19.329721 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 01:22:19.333436 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 01:22:19.340249 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 01:22:19.343615 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 01:22:19.346432 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 01:22:19.350162 0 10 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4041 01:22:19.356430 0 10 16 | B1->B0 | 3333 3939 | 1 0 | (0 0) (0 0)
4042 01:22:19.359557 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 01:22:19.363321 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 01:22:19.369821 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 01:22:19.372871 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 01:22:19.376491 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 01:22:19.382651 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 01:22:19.386373 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 01:22:19.389342 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 01:22:19.396281 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 01:22:19.399168 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 01:22:19.402557 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 01:22:19.409195 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 01:22:19.412979 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 01:22:19.415981 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 01:22:19.422777 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 01:22:19.425872 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 01:22:19.428982 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 01:22:19.435757 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 01:22:19.439201 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 01:22:19.442599 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 01:22:19.449180 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 01:22:19.452212 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 01:22:19.455825 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4065 01:22:19.462543 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4066 01:22:19.465810 Total UI for P1: 0, mck2ui 16
4067 01:22:19.469119 best dqsien dly found for B0: ( 0, 13, 12)
4068 01:22:19.472010 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 01:22:19.475378 Total UI for P1: 0, mck2ui 16
4070 01:22:19.478737 best dqsien dly found for B1: ( 0, 13, 16)
4071 01:22:19.482001 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4072 01:22:19.485569 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4073 01:22:19.485698
4074 01:22:19.488554 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4075 01:22:19.495494 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4076 01:22:19.495638 [Gating] SW calibration Done
4077 01:22:19.495741 ==
4078 01:22:19.498493 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 01:22:19.505174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 01:22:19.505311 ==
4081 01:22:19.505411 RX Vref Scan: 0
4082 01:22:19.505507
4083 01:22:19.508627 RX Vref 0 -> 0, step: 1
4084 01:22:19.508714
4085 01:22:19.511557 RX Delay -230 -> 252, step: 16
4086 01:22:19.515177 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4087 01:22:19.518160 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4088 01:22:19.524974 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4089 01:22:19.528556 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4090 01:22:19.531503 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4091 01:22:19.535257 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4092 01:22:19.538348 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4093 01:22:19.545027 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4094 01:22:19.548025 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4095 01:22:19.550999 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4096 01:22:19.554520 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4097 01:22:19.561382 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4098 01:22:19.564309 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4099 01:22:19.567904 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4100 01:22:19.570999 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4101 01:22:19.577425 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4102 01:22:19.577560 ==
4103 01:22:19.581028 Dram Type= 6, Freq= 0, CH_0, rank 0
4104 01:22:19.584465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4105 01:22:19.584620 ==
4106 01:22:19.584703 DQS Delay:
4107 01:22:19.587739 DQS0 = 0, DQS1 = 0
4108 01:22:19.587825 DQM Delay:
4109 01:22:19.590950 DQM0 = 38, DQM1 = 29
4110 01:22:19.591037 DQ Delay:
4111 01:22:19.594234 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4112 01:22:19.597847 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4113 01:22:19.601051 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4114 01:22:19.604349 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4115 01:22:19.604467
4116 01:22:19.604570
4117 01:22:19.604660 ==
4118 01:22:19.607417 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 01:22:19.610694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 01:22:19.610785 ==
4121 01:22:19.614422
4122 01:22:19.614510
4123 01:22:19.614578 TX Vref Scan disable
4124 01:22:19.617525 == TX Byte 0 ==
4125 01:22:19.620589 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4126 01:22:19.624041 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4127 01:22:19.627608 == TX Byte 1 ==
4128 01:22:19.630731 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4129 01:22:19.633840 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4130 01:22:19.637440 ==
4131 01:22:19.640660 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 01:22:19.643757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 01:22:19.643850 ==
4134 01:22:19.643918
4135 01:22:19.643980
4136 01:22:19.647143 TX Vref Scan disable
4137 01:22:19.650182 == TX Byte 0 ==
4138 01:22:19.653671 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4139 01:22:19.657192 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4140 01:22:19.660376 == TX Byte 1 ==
4141 01:22:19.663239 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4142 01:22:19.666487 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4143 01:22:19.666578
4144 01:22:19.666646 [DATLAT]
4145 01:22:19.670404 Freq=600, CH0 RK0
4146 01:22:19.670498
4147 01:22:19.670566 DATLAT Default: 0x9
4148 01:22:19.673406 0, 0xFFFF, sum = 0
4149 01:22:19.676525 1, 0xFFFF, sum = 0
4150 01:22:19.676616 2, 0xFFFF, sum = 0
4151 01:22:19.680082 3, 0xFFFF, sum = 0
4152 01:22:19.680174 4, 0xFFFF, sum = 0
4153 01:22:19.683562 5, 0xFFFF, sum = 0
4154 01:22:19.683655 6, 0xFFFF, sum = 0
4155 01:22:19.686464 7, 0xFFFF, sum = 0
4156 01:22:19.686556 8, 0x0, sum = 1
4157 01:22:19.690235 9, 0x0, sum = 2
4158 01:22:19.690326 10, 0x0, sum = 3
4159 01:22:19.693308 11, 0x0, sum = 4
4160 01:22:19.693418 best_step = 9
4161 01:22:19.693529
4162 01:22:19.693623 ==
4163 01:22:19.696355 Dram Type= 6, Freq= 0, CH_0, rank 0
4164 01:22:19.700105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 01:22:19.700217 ==
4166 01:22:19.703395 RX Vref Scan: 1
4167 01:22:19.703507
4168 01:22:19.706568 RX Vref 0 -> 0, step: 1
4169 01:22:19.706676
4170 01:22:19.706779 RX Delay -195 -> 252, step: 8
4171 01:22:19.706885
4172 01:22:19.709612 Set Vref, RX VrefLevel [Byte0]: 62
4173 01:22:19.712697 [Byte1]: 47
4174 01:22:19.717647
4175 01:22:19.717769 Final RX Vref Byte 0 = 62 to rank0
4176 01:22:19.720664 Final RX Vref Byte 1 = 47 to rank0
4177 01:22:19.724261 Final RX Vref Byte 0 = 62 to rank1
4178 01:22:19.727776 Final RX Vref Byte 1 = 47 to rank1==
4179 01:22:19.730690 Dram Type= 6, Freq= 0, CH_0, rank 0
4180 01:22:19.737654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4181 01:22:19.737790 ==
4182 01:22:19.737866 DQS Delay:
4183 01:22:19.737930 DQS0 = 0, DQS1 = 0
4184 01:22:19.740885 DQM Delay:
4185 01:22:19.740975 DQM0 = 35, DQM1 = 29
4186 01:22:19.744109 DQ Delay:
4187 01:22:19.747848 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =32
4188 01:22:19.750894 DQ4 =36, DQ5 =24, DQ6 =44, DQ7 =44
4189 01:22:19.753948 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =24
4190 01:22:19.757632 DQ12 =32, DQ13 =32, DQ14 =40, DQ15 =36
4191 01:22:19.757730
4192 01:22:19.757800
4193 01:22:19.764196 [DQSOSCAuto] RK0, (LSB)MR18= 0x3838, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
4194 01:22:19.767353 CH0 RK0: MR19=808, MR18=3838
4195 01:22:19.773797 CH0_RK0: MR19=0x808, MR18=0x3838, DQSOSC=399, MR23=63, INC=164, DEC=109
4196 01:22:19.773910
4197 01:22:19.777269 ----->DramcWriteLeveling(PI) begin...
4198 01:22:19.777402 ==
4199 01:22:19.780363 Dram Type= 6, Freq= 0, CH_0, rank 1
4200 01:22:19.783495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4201 01:22:19.783587 ==
4202 01:22:19.787022 Write leveling (Byte 0): 33 => 33
4203 01:22:19.790616 Write leveling (Byte 1): 30 => 30
4204 01:22:19.793474 DramcWriteLeveling(PI) end<-----
4205 01:22:19.793634
4206 01:22:19.793727 ==
4207 01:22:19.797020 Dram Type= 6, Freq= 0, CH_0, rank 1
4208 01:22:19.800274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4209 01:22:19.800363 ==
4210 01:22:19.803301 [Gating] SW mode calibration
4211 01:22:19.809980 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4212 01:22:19.816705 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4213 01:22:19.820399 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4214 01:22:19.826465 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4215 01:22:19.830339 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4216 01:22:19.833462 0 9 12 | B1->B0 | 3434 3131 | 0 0 | (0 1) (0 1)
4217 01:22:19.839988 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
4218 01:22:19.843268 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 01:22:19.846478 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 01:22:19.853299 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 01:22:19.856408 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 01:22:19.860275 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 01:22:19.866853 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 01:22:19.869867 0 10 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
4225 01:22:19.873430 0 10 16 | B1->B0 | 3939 4343 | 0 0 | (1 1) (0 0)
4226 01:22:19.879554 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 01:22:19.883090 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 01:22:19.886426 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 01:22:19.892773 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 01:22:19.896217 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 01:22:19.899794 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 01:22:19.905974 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4233 01:22:19.909791 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4234 01:22:19.912923 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 01:22:19.919575 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 01:22:19.922639 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 01:22:19.926050 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 01:22:19.932426 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 01:22:19.936324 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 01:22:19.939565 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 01:22:19.945762 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 01:22:19.949537 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 01:22:19.952501 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 01:22:19.955841 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 01:22:19.962241 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 01:22:19.966108 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 01:22:19.969233 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 01:22:19.975938 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4249 01:22:19.978962 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4250 01:22:19.982086 Total UI for P1: 0, mck2ui 16
4251 01:22:19.985711 best dqsien dly found for B0: ( 0, 13, 12)
4252 01:22:19.988778 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 01:22:19.992211 Total UI for P1: 0, mck2ui 16
4254 01:22:19.995699 best dqsien dly found for B1: ( 0, 13, 18)
4255 01:22:19.998551 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4256 01:22:20.005700 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4257 01:22:20.005833
4258 01:22:20.008716 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4259 01:22:20.011838 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4260 01:22:20.015741 [Gating] SW calibration Done
4261 01:22:20.015838 ==
4262 01:22:20.018934 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 01:22:20.021933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 01:22:20.022025 ==
4265 01:22:20.025398 RX Vref Scan: 0
4266 01:22:20.025539
4267 01:22:20.025654 RX Vref 0 -> 0, step: 1
4268 01:22:20.025749
4269 01:22:20.028565 RX Delay -230 -> 252, step: 16
4270 01:22:20.031690 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4271 01:22:20.038413 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4272 01:22:20.041905 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4273 01:22:20.045351 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4274 01:22:20.048680 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4275 01:22:20.051982 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4276 01:22:20.058557 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4277 01:22:20.061784 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4278 01:22:20.065387 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4279 01:22:20.068368 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4280 01:22:20.075509 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4281 01:22:20.078448 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4282 01:22:20.082191 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4283 01:22:20.085065 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4284 01:22:20.091680 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4285 01:22:20.094857 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4286 01:22:20.094944 ==
4287 01:22:20.098356 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 01:22:20.102006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 01:22:20.102087 ==
4290 01:22:20.104909 DQS Delay:
4291 01:22:20.105000 DQS0 = 0, DQS1 = 0
4292 01:22:20.105066 DQM Delay:
4293 01:22:20.107884 DQM0 = 35, DQM1 = 30
4294 01:22:20.107987 DQ Delay:
4295 01:22:20.111481 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4296 01:22:20.114525 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4297 01:22:20.118151 DQ8 =17, DQ9 =9, DQ10 =33, DQ11 =25
4298 01:22:20.121179 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =41
4299 01:22:20.121286
4300 01:22:20.121366
4301 01:22:20.121427 ==
4302 01:22:20.124924 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 01:22:20.130948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 01:22:20.131091 ==
4305 01:22:20.131249
4306 01:22:20.131341
4307 01:22:20.131489 TX Vref Scan disable
4308 01:22:20.135209 == TX Byte 0 ==
4309 01:22:20.138350 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4310 01:22:20.141385 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4311 01:22:20.144996 == TX Byte 1 ==
4312 01:22:20.148046 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4313 01:22:20.154875 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4314 01:22:20.155008 ==
4315 01:22:20.158534 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 01:22:20.161386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 01:22:20.161500 ==
4318 01:22:20.161599
4319 01:22:20.161701
4320 01:22:20.164462 TX Vref Scan disable
4321 01:22:20.168026 == TX Byte 0 ==
4322 01:22:20.171690 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4323 01:22:20.174723 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4324 01:22:20.178299 == TX Byte 1 ==
4325 01:22:20.181049 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4326 01:22:20.184819 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4327 01:22:20.184907
4328 01:22:20.184973 [DATLAT]
4329 01:22:20.188108 Freq=600, CH0 RK1
4330 01:22:20.188198
4331 01:22:20.191443 DATLAT Default: 0x9
4332 01:22:20.191540 0, 0xFFFF, sum = 0
4333 01:22:20.194404 1, 0xFFFF, sum = 0
4334 01:22:20.194486 2, 0xFFFF, sum = 0
4335 01:22:20.198091 3, 0xFFFF, sum = 0
4336 01:22:20.198176 4, 0xFFFF, sum = 0
4337 01:22:20.201022 5, 0xFFFF, sum = 0
4338 01:22:20.201107 6, 0xFFFF, sum = 0
4339 01:22:20.204686 7, 0xFFFF, sum = 0
4340 01:22:20.204775 8, 0x0, sum = 1
4341 01:22:20.207765 9, 0x0, sum = 2
4342 01:22:20.207850 10, 0x0, sum = 3
4343 01:22:20.207920 11, 0x0, sum = 4
4344 01:22:20.211382 best_step = 9
4345 01:22:20.211489
4346 01:22:20.211593 ==
4347 01:22:20.214357 Dram Type= 6, Freq= 0, CH_0, rank 1
4348 01:22:20.217996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4349 01:22:20.218087 ==
4350 01:22:20.220794 RX Vref Scan: 0
4351 01:22:20.220876
4352 01:22:20.220942 RX Vref 0 -> 0, step: 1
4353 01:22:20.224543
4354 01:22:20.224631 RX Delay -195 -> 252, step: 8
4355 01:22:20.232037 iDelay=205, Bit 0, Center 28 (-131 ~ 188) 320
4356 01:22:20.235155 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4357 01:22:20.238397 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4358 01:22:20.242073 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4359 01:22:20.248841 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4360 01:22:20.252025 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4361 01:22:20.255010 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4362 01:22:20.258764 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4363 01:22:20.261813 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4364 01:22:20.268489 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4365 01:22:20.272005 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4366 01:22:20.275222 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4367 01:22:20.278527 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4368 01:22:20.285166 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4369 01:22:20.288288 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4370 01:22:20.291902 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4371 01:22:20.292027 ==
4372 01:22:20.295075 Dram Type= 6, Freq= 0, CH_0, rank 1
4373 01:22:20.298704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 01:22:20.301475 ==
4375 01:22:20.301605 DQS Delay:
4376 01:22:20.301673 DQS0 = 0, DQS1 = 0
4377 01:22:20.304862 DQM Delay:
4378 01:22:20.304937 DQM0 = 33, DQM1 = 28
4379 01:22:20.308150 DQ Delay:
4380 01:22:20.311341 DQ0 =28, DQ1 =36, DQ2 =32, DQ3 =32
4381 01:22:20.311447 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4382 01:22:20.314729 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4383 01:22:20.321478 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4384 01:22:20.321630
4385 01:22:20.321736
4386 01:22:20.328030 [DQSOSCAuto] RK1, (LSB)MR18= 0x6937, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4387 01:22:20.331701 CH0 RK1: MR19=808, MR18=6937
4388 01:22:20.338290 CH0_RK1: MR19=0x808, MR18=0x6937, DQSOSC=390, MR23=63, INC=172, DEC=114
4389 01:22:20.341532 [RxdqsGatingPostProcess] freq 600
4390 01:22:20.344607 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4391 01:22:20.347769 Pre-setting of DQS Precalculation
4392 01:22:20.354333 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4393 01:22:20.354446 ==
4394 01:22:20.358068 Dram Type= 6, Freq= 0, CH_1, rank 0
4395 01:22:20.361073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 01:22:20.361165 ==
4397 01:22:20.367766 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4398 01:22:20.371078 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4399 01:22:20.375449 [CA 0] Center 35 (5~66) winsize 62
4400 01:22:20.379189 [CA 1] Center 36 (6~66) winsize 61
4401 01:22:20.382777 [CA 2] Center 34 (4~65) winsize 62
4402 01:22:20.385420 [CA 3] Center 34 (4~65) winsize 62
4403 01:22:20.388705 [CA 4] Center 34 (4~65) winsize 62
4404 01:22:20.392224 [CA 5] Center 33 (3~64) winsize 62
4405 01:22:20.392329
4406 01:22:20.395379 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4407 01:22:20.395477
4408 01:22:20.398759 [CATrainingPosCal] consider 1 rank data
4409 01:22:20.402353 u2DelayCellTimex100 = 270/100 ps
4410 01:22:20.405227 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4411 01:22:20.412076 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4412 01:22:20.415562 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4413 01:22:20.418794 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4414 01:22:20.422018 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4415 01:22:20.425370 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4416 01:22:20.425478
4417 01:22:20.428735 CA PerBit enable=1, Macro0, CA PI delay=33
4418 01:22:20.428824
4419 01:22:20.431748 [CBTSetCACLKResult] CA Dly = 33
4420 01:22:20.435562 CS Dly: 4 (0~35)
4421 01:22:20.435688 ==
4422 01:22:20.438835 Dram Type= 6, Freq= 0, CH_1, rank 1
4423 01:22:20.442034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4424 01:22:20.442169 ==
4425 01:22:20.445161 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4426 01:22:20.451757 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4427 01:22:20.455977 [CA 0] Center 36 (6~66) winsize 61
4428 01:22:20.459189 [CA 1] Center 36 (6~67) winsize 62
4429 01:22:20.462201 [CA 2] Center 34 (4~65) winsize 62
4430 01:22:20.465851 [CA 3] Center 34 (4~65) winsize 62
4431 01:22:20.468921 [CA 4] Center 34 (4~65) winsize 62
4432 01:22:20.472189 [CA 5] Center 33 (3~64) winsize 62
4433 01:22:20.472295
4434 01:22:20.475810 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4435 01:22:20.475910
4436 01:22:20.479008 [CATrainingPosCal] consider 2 rank data
4437 01:22:20.482083 u2DelayCellTimex100 = 270/100 ps
4438 01:22:20.485695 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4439 01:22:20.491827 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4440 01:22:20.495634 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4441 01:22:20.498567 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4442 01:22:20.501760 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4443 01:22:20.505467 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4444 01:22:20.505591
4445 01:22:20.508740 CA PerBit enable=1, Macro0, CA PI delay=33
4446 01:22:20.508843
4447 01:22:20.511841 [CBTSetCACLKResult] CA Dly = 33
4448 01:22:20.515642 CS Dly: 4 (0~36)
4449 01:22:20.515758
4450 01:22:20.518560 ----->DramcWriteLeveling(PI) begin...
4451 01:22:20.518656 ==
4452 01:22:20.521482 Dram Type= 6, Freq= 0, CH_1, rank 0
4453 01:22:20.525036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4454 01:22:20.525133 ==
4455 01:22:20.528003 Write leveling (Byte 0): 28 => 28
4456 01:22:20.531659 Write leveling (Byte 1): 32 => 32
4457 01:22:20.534931 DramcWriteLeveling(PI) end<-----
4458 01:22:20.535075
4459 01:22:20.535181 ==
4460 01:22:20.538150 Dram Type= 6, Freq= 0, CH_1, rank 0
4461 01:22:20.541374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4462 01:22:20.541496 ==
4463 01:22:20.544798 [Gating] SW mode calibration
4464 01:22:20.551397 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4465 01:22:20.558307 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4466 01:22:20.561457 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4467 01:22:20.564493 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4468 01:22:20.571252 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4469 01:22:20.574314 0 9 12 | B1->B0 | 3131 3333 | 0 0 | (1 0) (0 0)
4470 01:22:20.577985 0 9 16 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4471 01:22:20.584316 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 01:22:20.587829 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 01:22:20.591579 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 01:22:20.597644 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 01:22:20.601342 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 01:22:20.604435 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 01:22:20.611219 0 10 12 | B1->B0 | 3030 3130 | 0 1 | (1 1) (0 0)
4478 01:22:20.614263 0 10 16 | B1->B0 | 3f3f 4141 | 0 1 | (0 0) (0 0)
4479 01:22:20.617854 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 01:22:20.624452 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 01:22:20.627643 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 01:22:20.630955 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 01:22:20.637900 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 01:22:20.640782 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 01:22:20.644370 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4486 01:22:20.651051 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 01:22:20.654023 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 01:22:20.657399 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 01:22:20.664045 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 01:22:20.667357 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 01:22:20.670525 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 01:22:20.674179 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 01:22:20.680703 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 01:22:20.683829 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 01:22:20.687538 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 01:22:20.693685 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 01:22:20.697246 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 01:22:20.700465 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 01:22:20.707095 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 01:22:20.710489 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 01:22:20.714049 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4502 01:22:20.720350 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4503 01:22:20.723478 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 01:22:20.726644 Total UI for P1: 0, mck2ui 16
4505 01:22:20.730154 best dqsien dly found for B0: ( 0, 13, 14)
4506 01:22:20.733538 Total UI for P1: 0, mck2ui 16
4507 01:22:20.736803 best dqsien dly found for B1: ( 0, 13, 14)
4508 01:22:20.740082 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4509 01:22:20.743385 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4510 01:22:20.743532
4511 01:22:20.746854 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4512 01:22:20.753604 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4513 01:22:20.753771 [Gating] SW calibration Done
4514 01:22:20.753887 ==
4515 01:22:20.756726 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 01:22:20.763577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 01:22:20.763749 ==
4518 01:22:20.763879 RX Vref Scan: 0
4519 01:22:20.764000
4520 01:22:20.766683 RX Vref 0 -> 0, step: 1
4521 01:22:20.766798
4522 01:22:20.769712 RX Delay -230 -> 252, step: 16
4523 01:22:20.773420 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4524 01:22:20.776425 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4525 01:22:20.783198 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4526 01:22:20.786431 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4527 01:22:20.790031 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4528 01:22:20.793316 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4529 01:22:20.796034 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4530 01:22:20.802834 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4531 01:22:20.806201 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4532 01:22:20.809615 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4533 01:22:20.812528 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4534 01:22:20.819176 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4535 01:22:20.823000 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4536 01:22:20.826064 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4537 01:22:20.829180 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4538 01:22:20.835966 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4539 01:22:20.836095 ==
4540 01:22:20.839351 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 01:22:20.842509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 01:22:20.842603 ==
4543 01:22:20.842672 DQS Delay:
4544 01:22:20.846185 DQS0 = 0, DQS1 = 0
4545 01:22:20.846275 DQM Delay:
4546 01:22:20.849067 DQM0 = 37, DQM1 = 28
4547 01:22:20.849154 DQ Delay:
4548 01:22:20.852385 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4549 01:22:20.855724 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4550 01:22:20.859324 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4551 01:22:20.862255 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4552 01:22:20.862376
4553 01:22:20.862474
4554 01:22:20.862542 ==
4555 01:22:20.865857 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 01:22:20.869139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 01:22:20.869227 ==
4558 01:22:20.872644
4559 01:22:20.872733
4560 01:22:20.872800 TX Vref Scan disable
4561 01:22:20.875705 == TX Byte 0 ==
4562 01:22:20.879388 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4563 01:22:20.882487 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4564 01:22:20.885418 == TX Byte 1 ==
4565 01:22:20.889142 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4566 01:22:20.892504 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4567 01:22:20.895635 ==
4568 01:22:20.895730 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 01:22:20.902057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 01:22:20.902164 ==
4571 01:22:20.902234
4572 01:22:20.902294
4573 01:22:20.905561 TX Vref Scan disable
4574 01:22:20.905659 == TX Byte 0 ==
4575 01:22:20.912313 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4576 01:22:20.915163 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4577 01:22:20.915258 == TX Byte 1 ==
4578 01:22:20.922241 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4579 01:22:20.925534 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4580 01:22:20.925636
4581 01:22:20.925706 [DATLAT]
4582 01:22:20.928687 Freq=600, CH1 RK0
4583 01:22:20.928773
4584 01:22:20.928839 DATLAT Default: 0x9
4585 01:22:20.932451 0, 0xFFFF, sum = 0
4586 01:22:20.932540 1, 0xFFFF, sum = 0
4587 01:22:20.935532 2, 0xFFFF, sum = 0
4588 01:22:20.935626 3, 0xFFFF, sum = 0
4589 01:22:20.938492 4, 0xFFFF, sum = 0
4590 01:22:20.942058 5, 0xFFFF, sum = 0
4591 01:22:20.942189 6, 0xFFFF, sum = 0
4592 01:22:20.945137 7, 0xFFFF, sum = 0
4593 01:22:20.945298 8, 0x0, sum = 1
4594 01:22:20.945428 9, 0x0, sum = 2
4595 01:22:20.948865 10, 0x0, sum = 3
4596 01:22:20.949013 11, 0x0, sum = 4
4597 01:22:20.951910 best_step = 9
4598 01:22:20.952088
4599 01:22:20.952201 ==
4600 01:22:20.955647 Dram Type= 6, Freq= 0, CH_1, rank 0
4601 01:22:20.958504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4602 01:22:20.958694 ==
4603 01:22:20.961941 RX Vref Scan: 1
4604 01:22:20.962096
4605 01:22:20.962194 RX Vref 0 -> 0, step: 1
4606 01:22:20.962285
4607 01:22:20.964914 RX Delay -195 -> 252, step: 8
4608 01:22:20.965071
4609 01:22:20.968354 Set Vref, RX VrefLevel [Byte0]: 54
4610 01:22:20.971861 [Byte1]: 48
4611 01:22:20.975821
4612 01:22:20.975939 Final RX Vref Byte 0 = 54 to rank0
4613 01:22:20.979232 Final RX Vref Byte 1 = 48 to rank0
4614 01:22:20.982765 Final RX Vref Byte 0 = 54 to rank1
4615 01:22:20.985875 Final RX Vref Byte 1 = 48 to rank1==
4616 01:22:20.989072 Dram Type= 6, Freq= 0, CH_1, rank 0
4617 01:22:20.995769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 01:22:20.995881 ==
4619 01:22:20.995950 DQS Delay:
4620 01:22:20.996012 DQS0 = 0, DQS1 = 0
4621 01:22:20.999367 DQM Delay:
4622 01:22:20.999454 DQM0 = 38, DQM1 = 28
4623 01:22:21.002425 DQ Delay:
4624 01:22:21.005962 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4625 01:22:21.009101 DQ4 =36, DQ5 =44, DQ6 =52, DQ7 =36
4626 01:22:21.012698 DQ8 =16, DQ9 =16, DQ10 =28, DQ11 =20
4627 01:22:21.015585 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4628 01:22:21.015676
4629 01:22:21.015743
4630 01:22:21.022120 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b28, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
4631 01:22:21.025513 CH1 RK0: MR19=808, MR18=1B28
4632 01:22:21.032260 CH1_RK0: MR19=0x808, MR18=0x1B28, DQSOSC=402, MR23=63, INC=162, DEC=108
4633 01:22:21.032380
4634 01:22:21.035663 ----->DramcWriteLeveling(PI) begin...
4635 01:22:21.035762 ==
4636 01:22:21.038612 Dram Type= 6, Freq= 0, CH_1, rank 1
4637 01:22:21.042395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 01:22:21.042501 ==
4639 01:22:21.045419 Write leveling (Byte 0): 29 => 29
4640 01:22:21.049029 Write leveling (Byte 1): 29 => 29
4641 01:22:21.052088 DramcWriteLeveling(PI) end<-----
4642 01:22:21.052178
4643 01:22:21.052245 ==
4644 01:22:21.055137 Dram Type= 6, Freq= 0, CH_1, rank 1
4645 01:22:21.058846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4646 01:22:21.058936 ==
4647 01:22:21.061850 [Gating] SW mode calibration
4648 01:22:21.068526 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4649 01:22:21.075086 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4650 01:22:21.078561 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4651 01:22:21.085369 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4652 01:22:21.088288 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4653 01:22:21.091841 0 9 12 | B1->B0 | 3232 2d2d | 1 1 | (1 0) (1 0)
4654 01:22:21.098448 0 9 16 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
4655 01:22:21.101360 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 01:22:21.105086 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 01:22:21.111613 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 01:22:21.114696 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 01:22:21.118301 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 01:22:21.124763 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 01:22:21.128039 0 10 12 | B1->B0 | 3030 3c3c | 0 0 | (0 0) (0 0)
4662 01:22:21.131526 0 10 16 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
4663 01:22:21.137901 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 01:22:21.141290 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 01:22:21.144752 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 01:22:21.151155 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 01:22:21.154228 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 01:22:21.157870 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 01:22:21.164543 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 01:22:21.167591 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4671 01:22:21.170784 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 01:22:21.177483 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 01:22:21.181056 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 01:22:21.183928 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 01:22:21.190673 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 01:22:21.194002 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 01:22:21.197143 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 01:22:21.203801 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 01:22:21.207493 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 01:22:21.210571 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 01:22:21.217342 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 01:22:21.220369 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 01:22:21.223805 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 01:22:21.230376 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 01:22:21.233462 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4686 01:22:21.237179 Total UI for P1: 0, mck2ui 16
4687 01:22:21.240228 best dqsien dly found for B0: ( 0, 13, 10)
4688 01:22:21.243845 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4689 01:22:21.250066 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 01:22:21.250168 Total UI for P1: 0, mck2ui 16
4691 01:22:21.253480 best dqsien dly found for B1: ( 0, 13, 14)
4692 01:22:21.260267 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4693 01:22:21.263821 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4694 01:22:21.263919
4695 01:22:21.266874 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4696 01:22:21.269886 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4697 01:22:21.273516 [Gating] SW calibration Done
4698 01:22:21.273655 ==
4699 01:22:21.276635 Dram Type= 6, Freq= 0, CH_1, rank 1
4700 01:22:21.279791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4701 01:22:21.279880 ==
4702 01:22:21.283536 RX Vref Scan: 0
4703 01:22:21.283623
4704 01:22:21.283711 RX Vref 0 -> 0, step: 1
4705 01:22:21.283797
4706 01:22:21.286515 RX Delay -230 -> 252, step: 16
4707 01:22:21.293161 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4708 01:22:21.296173 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4709 01:22:21.299685 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4710 01:22:21.303113 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4711 01:22:21.306265 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4712 01:22:21.313044 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4713 01:22:21.316281 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4714 01:22:21.319638 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4715 01:22:21.322756 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4716 01:22:21.329361 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4717 01:22:21.333100 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4718 01:22:21.336242 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4719 01:22:21.339238 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4720 01:22:21.345843 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4721 01:22:21.349627 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4722 01:22:21.352556 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4723 01:22:21.352677 ==
4724 01:22:21.355981 Dram Type= 6, Freq= 0, CH_1, rank 1
4725 01:22:21.359544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4726 01:22:21.359641 ==
4727 01:22:21.362339 DQS Delay:
4728 01:22:21.362424 DQS0 = 0, DQS1 = 0
4729 01:22:21.365704 DQM Delay:
4730 01:22:21.365790 DQM0 = 35, DQM1 = 29
4731 01:22:21.365856 DQ Delay:
4732 01:22:21.369159 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4733 01:22:21.372155 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4734 01:22:21.375769 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4735 01:22:21.378998 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4736 01:22:21.379091
4737 01:22:21.382622
4738 01:22:21.382708 ==
4739 01:22:21.385668 Dram Type= 6, Freq= 0, CH_1, rank 1
4740 01:22:21.388717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4741 01:22:21.388824 ==
4742 01:22:21.388909
4743 01:22:21.388971
4744 01:22:21.391931 TX Vref Scan disable
4745 01:22:21.392017 == TX Byte 0 ==
4746 01:22:21.399058 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4747 01:22:21.401911 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4748 01:22:21.402006 == TX Byte 1 ==
4749 01:22:21.408804 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4750 01:22:21.412363 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4751 01:22:21.412464 ==
4752 01:22:21.415252 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 01:22:21.418428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 01:22:21.418520 ==
4755 01:22:21.418587
4756 01:22:21.418648
4757 01:22:21.421922 TX Vref Scan disable
4758 01:22:21.425288 == TX Byte 0 ==
4759 01:22:21.428836 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4760 01:22:21.432052 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4761 01:22:21.435185 == TX Byte 1 ==
4762 01:22:21.438685 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4763 01:22:21.441807 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4764 01:22:21.441906
4765 01:22:21.445346 [DATLAT]
4766 01:22:21.445436 Freq=600, CH1 RK1
4767 01:22:21.445503
4768 01:22:21.448432 DATLAT Default: 0x9
4769 01:22:21.448528 0, 0xFFFF, sum = 0
4770 01:22:21.452074 1, 0xFFFF, sum = 0
4771 01:22:21.452164 2, 0xFFFF, sum = 0
4772 01:22:21.455111 3, 0xFFFF, sum = 0
4773 01:22:21.455225 4, 0xFFFF, sum = 0
4774 01:22:21.458314 5, 0xFFFF, sum = 0
4775 01:22:21.458402 6, 0xFFFF, sum = 0
4776 01:22:21.461808 7, 0xFFFF, sum = 0
4777 01:22:21.461896 8, 0x0, sum = 1
4778 01:22:21.465210 9, 0x0, sum = 2
4779 01:22:21.465295 10, 0x0, sum = 3
4780 01:22:21.468199 11, 0x0, sum = 4
4781 01:22:21.468293 best_step = 9
4782 01:22:21.468440
4783 01:22:21.468520 ==
4784 01:22:21.471585 Dram Type= 6, Freq= 0, CH_1, rank 1
4785 01:22:21.478681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4786 01:22:21.478796 ==
4787 01:22:21.478865 RX Vref Scan: 0
4788 01:22:21.478927
4789 01:22:21.481851 RX Vref 0 -> 0, step: 1
4790 01:22:21.481941
4791 01:22:21.485393 RX Delay -195 -> 252, step: 8
4792 01:22:21.488384 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4793 01:22:21.495027 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4794 01:22:21.498667 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4795 01:22:21.501474 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4796 01:22:21.505240 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4797 01:22:21.508325 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4798 01:22:21.514914 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4799 01:22:21.518536 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4800 01:22:21.521674 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4801 01:22:21.524886 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4802 01:22:21.531957 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4803 01:22:21.535174 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4804 01:22:21.538275 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4805 01:22:21.541892 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4806 01:22:21.548182 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4807 01:22:21.551534 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4808 01:22:21.551635 ==
4809 01:22:21.555059 Dram Type= 6, Freq= 0, CH_1, rank 1
4810 01:22:21.558320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4811 01:22:21.558418 ==
4812 01:22:21.558486 DQS Delay:
4813 01:22:21.561412 DQS0 = 0, DQS1 = 0
4814 01:22:21.561499 DQM Delay:
4815 01:22:21.565162 DQM0 = 35, DQM1 = 31
4816 01:22:21.565263 DQ Delay:
4817 01:22:21.568144 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4818 01:22:21.571452 DQ4 =32, DQ5 =48, DQ6 =44, DQ7 =32
4819 01:22:21.574713 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4820 01:22:21.578047 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4821 01:22:21.578143
4822 01:22:21.578211
4823 01:22:21.587939 [DQSOSCAuto] RK1, (LSB)MR18= 0x3252, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
4824 01:22:21.588104 CH1 RK1: MR19=808, MR18=3252
4825 01:22:21.594746 CH1_RK1: MR19=0x808, MR18=0x3252, DQSOSC=394, MR23=63, INC=168, DEC=112
4826 01:22:21.597744 [RxdqsGatingPostProcess] freq 600
4827 01:22:21.604510 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4828 01:22:21.607487 Pre-setting of DQS Precalculation
4829 01:22:21.611015 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4830 01:22:21.617690 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4831 01:22:21.627429 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4832 01:22:21.627592
4833 01:22:21.627679
4834 01:22:21.631221 [Calibration Summary] 1200 Mbps
4835 01:22:21.631324 CH 0, Rank 0
4836 01:22:21.634248 SW Impedance : PASS
4837 01:22:21.634350 DUTY Scan : NO K
4838 01:22:21.637248 ZQ Calibration : PASS
4839 01:22:21.640929 Jitter Meter : NO K
4840 01:22:21.641025 CBT Training : PASS
4841 01:22:21.643943 Write leveling : PASS
4842 01:22:21.644030 RX DQS gating : PASS
4843 01:22:21.647611 RX DQ/DQS(RDDQC) : PASS
4844 01:22:21.651061 TX DQ/DQS : PASS
4845 01:22:21.651169 RX DATLAT : PASS
4846 01:22:21.654580 RX DQ/DQS(Engine): PASS
4847 01:22:21.657724 TX OE : NO K
4848 01:22:21.657833 All Pass.
4849 01:22:21.657930
4850 01:22:21.658005 CH 0, Rank 1
4851 01:22:21.661168 SW Impedance : PASS
4852 01:22:21.664484 DUTY Scan : NO K
4853 01:22:21.664591 ZQ Calibration : PASS
4854 01:22:21.667441 Jitter Meter : NO K
4855 01:22:21.670576 CBT Training : PASS
4856 01:22:21.670669 Write leveling : PASS
4857 01:22:21.674141 RX DQS gating : PASS
4858 01:22:21.677611 RX DQ/DQS(RDDQC) : PASS
4859 01:22:21.677709 TX DQ/DQS : PASS
4860 01:22:21.680997 RX DATLAT : PASS
4861 01:22:21.684328 RX DQ/DQS(Engine): PASS
4862 01:22:21.684424 TX OE : NO K
4863 01:22:21.684496 All Pass.
4864 01:22:21.687446
4865 01:22:21.687534 CH 1, Rank 0
4866 01:22:21.690744 SW Impedance : PASS
4867 01:22:21.690836 DUTY Scan : NO K
4868 01:22:21.694164 ZQ Calibration : PASS
4869 01:22:21.694253 Jitter Meter : NO K
4870 01:22:21.697285 CBT Training : PASS
4871 01:22:21.700978 Write leveling : PASS
4872 01:22:21.701074 RX DQS gating : PASS
4873 01:22:21.704127 RX DQ/DQS(RDDQC) : PASS
4874 01:22:21.707103 TX DQ/DQS : PASS
4875 01:22:21.707193 RX DATLAT : PASS
4876 01:22:21.710819 RX DQ/DQS(Engine): PASS
4877 01:22:21.713847 TX OE : NO K
4878 01:22:21.713939 All Pass.
4879 01:22:21.714008
4880 01:22:21.714071 CH 1, Rank 1
4881 01:22:21.717232 SW Impedance : PASS
4882 01:22:21.720790 DUTY Scan : NO K
4883 01:22:21.720885 ZQ Calibration : PASS
4884 01:22:21.723727 Jitter Meter : NO K
4885 01:22:21.727534 CBT Training : PASS
4886 01:22:21.727628 Write leveling : PASS
4887 01:22:21.730513 RX DQS gating : PASS
4888 01:22:21.733615 RX DQ/DQS(RDDQC) : PASS
4889 01:22:21.733707 TX DQ/DQS : PASS
4890 01:22:21.737330 RX DATLAT : PASS
4891 01:22:21.740448 RX DQ/DQS(Engine): PASS
4892 01:22:21.740544 TX OE : NO K
4893 01:22:21.743410 All Pass.
4894 01:22:21.743498
4895 01:22:21.743567 DramC Write-DBI off
4896 01:22:21.746962 PER_BANK_REFRESH: Hybrid Mode
4897 01:22:21.747053 TX_TRACKING: ON
4898 01:22:21.756586 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4899 01:22:21.760195 [FAST_K] Save calibration result to emmc
4900 01:22:21.763244 dramc_set_vcore_voltage set vcore to 662500
4901 01:22:21.767018 Read voltage for 933, 3
4902 01:22:21.767114 Vio18 = 0
4903 01:22:21.769931 Vcore = 662500
4904 01:22:21.770018 Vdram = 0
4905 01:22:21.770085 Vddq = 0
4906 01:22:21.770147 Vmddr = 0
4907 01:22:21.776479 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4908 01:22:21.783007 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4909 01:22:21.783143 MEM_TYPE=3, freq_sel=17
4910 01:22:21.787355 sv_algorithm_assistance_LP4_1600
4911 01:22:21.789811 ============ PULL DRAM RESETB DOWN ============
4912 01:22:21.796839 ========== PULL DRAM RESETB DOWN end =========
4913 01:22:21.799499 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4914 01:22:21.803166 ===================================
4915 01:22:21.806198 LPDDR4 DRAM CONFIGURATION
4916 01:22:21.809821 ===================================
4917 01:22:21.809920 EX_ROW_EN[0] = 0x0
4918 01:22:21.812790 EX_ROW_EN[1] = 0x0
4919 01:22:21.816321 LP4Y_EN = 0x0
4920 01:22:21.816413 WORK_FSP = 0x0
4921 01:22:21.819786 WL = 0x3
4922 01:22:21.819872 RL = 0x3
4923 01:22:21.822750 BL = 0x2
4924 01:22:21.822836 RPST = 0x0
4925 01:22:21.826239 RD_PRE = 0x0
4926 01:22:21.826326 WR_PRE = 0x1
4927 01:22:21.829695 WR_PST = 0x0
4928 01:22:21.829782 DBI_WR = 0x0
4929 01:22:21.832760 DBI_RD = 0x0
4930 01:22:21.832871 OTF = 0x1
4931 01:22:21.836500 ===================================
4932 01:22:21.839503 ===================================
4933 01:22:21.842670 ANA top config
4934 01:22:21.846292 ===================================
4935 01:22:21.846386 DLL_ASYNC_EN = 0
4936 01:22:21.849297 ALL_SLAVE_EN = 1
4937 01:22:21.852754 NEW_RANK_MODE = 1
4938 01:22:21.855988 DLL_IDLE_MODE = 1
4939 01:22:21.859515 LP45_APHY_COMB_EN = 1
4940 01:22:21.859607 TX_ODT_DIS = 1
4941 01:22:21.862505 NEW_8X_MODE = 1
4942 01:22:21.866128 ===================================
4943 01:22:21.869195 ===================================
4944 01:22:21.872331 data_rate = 1866
4945 01:22:21.875869 CKR = 1
4946 01:22:21.879028 DQ_P2S_RATIO = 8
4947 01:22:21.882594 ===================================
4948 01:22:21.882686 CA_P2S_RATIO = 8
4949 01:22:21.885785 DQ_CA_OPEN = 0
4950 01:22:21.889313 DQ_SEMI_OPEN = 0
4951 01:22:21.892360 CA_SEMI_OPEN = 0
4952 01:22:21.895829 CA_FULL_RATE = 0
4953 01:22:21.899265 DQ_CKDIV4_EN = 1
4954 01:22:21.899358 CA_CKDIV4_EN = 1
4955 01:22:21.902473 CA_PREDIV_EN = 0
4956 01:22:21.905441 PH8_DLY = 0
4957 01:22:21.909164 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4958 01:22:21.912109 DQ_AAMCK_DIV = 4
4959 01:22:21.915526 CA_AAMCK_DIV = 4
4960 01:22:21.918670 CA_ADMCK_DIV = 4
4961 01:22:21.918762 DQ_TRACK_CA_EN = 0
4962 01:22:21.922302 CA_PICK = 933
4963 01:22:21.925750 CA_MCKIO = 933
4964 01:22:21.928887 MCKIO_SEMI = 0
4965 01:22:21.932271 PLL_FREQ = 3732
4966 01:22:21.935163 DQ_UI_PI_RATIO = 32
4967 01:22:21.938673 CA_UI_PI_RATIO = 0
4968 01:22:21.941787 ===================================
4969 01:22:21.945446 ===================================
4970 01:22:21.945583 memory_type:LPDDR4
4971 01:22:21.948522 GP_NUM : 10
4972 01:22:21.948606 SRAM_EN : 1
4973 01:22:21.952177 MD32_EN : 0
4974 01:22:21.955543 ===================================
4975 01:22:21.958680 [ANA_INIT] >>>>>>>>>>>>>>
4976 01:22:21.961797 <<<<<< [CONFIGURE PHASE]: ANA_TX
4977 01:22:21.965363 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4978 01:22:21.968338 ===================================
4979 01:22:21.971992 data_rate = 1866,PCW = 0X8f00
4980 01:22:21.975149 ===================================
4981 01:22:21.978611 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4982 01:22:21.981695 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4983 01:22:21.988520 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4984 01:22:21.992180 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4985 01:22:21.995002 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4986 01:22:21.998518 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4987 01:22:22.002297 [ANA_INIT] flow start
4988 01:22:22.005192 [ANA_INIT] PLL >>>>>>>>
4989 01:22:22.005307 [ANA_INIT] PLL <<<<<<<<
4990 01:22:22.008677 [ANA_INIT] MIDPI >>>>>>>>
4991 01:22:22.011566 [ANA_INIT] MIDPI <<<<<<<<
4992 01:22:22.011673 [ANA_INIT] DLL >>>>>>>>
4993 01:22:22.014794 [ANA_INIT] flow end
4994 01:22:22.018269 ============ LP4 DIFF to SE enter ============
4995 01:22:22.024921 ============ LP4 DIFF to SE exit ============
4996 01:22:22.025062 [ANA_INIT] <<<<<<<<<<<<<
4997 01:22:22.028276 [Flow] Enable top DCM control >>>>>
4998 01:22:22.031375 [Flow] Enable top DCM control <<<<<
4999 01:22:22.034682 Enable DLL master slave shuffle
5000 01:22:22.041547 ==============================================================
5001 01:22:22.041684 Gating Mode config
5002 01:22:22.048405 ==============================================================
5003 01:22:22.051355 Config description:
5004 01:22:22.058059 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5005 01:22:22.064674 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5006 01:22:22.071343 SELPH_MODE 0: By rank 1: By Phase
5007 01:22:22.078374 ==============================================================
5008 01:22:22.078505 GAT_TRACK_EN = 1
5009 01:22:22.081384 RX_GATING_MODE = 2
5010 01:22:22.084305 RX_GATING_TRACK_MODE = 2
5011 01:22:22.087546 SELPH_MODE = 1
5012 01:22:22.090834 PICG_EARLY_EN = 1
5013 01:22:22.094033 VALID_LAT_VALUE = 1
5014 01:22:22.100808 ==============================================================
5015 01:22:22.104547 Enter into Gating configuration >>>>
5016 01:22:22.107449 Exit from Gating configuration <<<<
5017 01:22:22.110713 Enter into DVFS_PRE_config >>>>>
5018 01:22:22.120530 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5019 01:22:22.124124 Exit from DVFS_PRE_config <<<<<
5020 01:22:22.127253 Enter into PICG configuration >>>>
5021 01:22:22.130420 Exit from PICG configuration <<<<
5022 01:22:22.134175 [RX_INPUT] configuration >>>>>
5023 01:22:22.137076 [RX_INPUT] configuration <<<<<
5024 01:22:22.140463 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5025 01:22:22.147250 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5026 01:22:22.153958 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5027 01:22:22.160360 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5028 01:22:22.163741 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5029 01:22:22.170158 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5030 01:22:22.173670 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5031 01:22:22.180279 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5032 01:22:22.184059 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5033 01:22:22.187050 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5034 01:22:22.190000 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5035 01:22:22.196815 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5036 01:22:22.200381 ===================================
5037 01:22:22.200482 LPDDR4 DRAM CONFIGURATION
5038 01:22:22.203658 ===================================
5039 01:22:22.207088 EX_ROW_EN[0] = 0x0
5040 01:22:22.210049 EX_ROW_EN[1] = 0x0
5041 01:22:22.210142 LP4Y_EN = 0x0
5042 01:22:22.213602 WORK_FSP = 0x0
5043 01:22:22.213697 WL = 0x3
5044 01:22:22.216512 RL = 0x3
5045 01:22:22.216603 BL = 0x2
5046 01:22:22.220288 RPST = 0x0
5047 01:22:22.220376 RD_PRE = 0x0
5048 01:22:22.223332 WR_PRE = 0x1
5049 01:22:22.223420 WR_PST = 0x0
5050 01:22:22.226436 DBI_WR = 0x0
5051 01:22:22.226525 DBI_RD = 0x0
5052 01:22:22.230152 OTF = 0x1
5053 01:22:22.233101 ===================================
5054 01:22:22.236562 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5055 01:22:22.239970 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5056 01:22:22.246220 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5057 01:22:22.249756 ===================================
5058 01:22:22.249862 LPDDR4 DRAM CONFIGURATION
5059 01:22:22.252992 ===================================
5060 01:22:22.256396 EX_ROW_EN[0] = 0x10
5061 01:22:22.259901 EX_ROW_EN[1] = 0x0
5062 01:22:22.259996 LP4Y_EN = 0x0
5063 01:22:22.262797 WORK_FSP = 0x0
5064 01:22:22.262889 WL = 0x3
5065 01:22:22.266413 RL = 0x3
5066 01:22:22.266513 BL = 0x2
5067 01:22:22.269880 RPST = 0x0
5068 01:22:22.269962 RD_PRE = 0x0
5069 01:22:22.273088 WR_PRE = 0x1
5070 01:22:22.273166 WR_PST = 0x0
5071 01:22:22.276404 DBI_WR = 0x0
5072 01:22:22.276540 DBI_RD = 0x0
5073 01:22:22.279649 OTF = 0x1
5074 01:22:22.282744 ===================================
5075 01:22:22.289441 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5076 01:22:22.292958 nWR fixed to 30
5077 01:22:22.296046 [ModeRegInit_LP4] CH0 RK0
5078 01:22:22.296131 [ModeRegInit_LP4] CH0 RK1
5079 01:22:22.299710 [ModeRegInit_LP4] CH1 RK0
5080 01:22:22.302765 [ModeRegInit_LP4] CH1 RK1
5081 01:22:22.302862 match AC timing 9
5082 01:22:22.309531 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5083 01:22:22.313089 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5084 01:22:22.315887 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5085 01:22:22.322508 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5086 01:22:22.326092 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5087 01:22:22.326195 ==
5088 01:22:22.329361 Dram Type= 6, Freq= 0, CH_0, rank 0
5089 01:22:22.333031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5090 01:22:22.333123 ==
5091 01:22:22.339696 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5092 01:22:22.345834 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5093 01:22:22.349406 [CA 0] Center 38 (8~69) winsize 62
5094 01:22:22.352407 [CA 1] Center 38 (7~69) winsize 63
5095 01:22:22.355671 [CA 2] Center 35 (5~66) winsize 62
5096 01:22:22.359444 [CA 3] Center 35 (4~66) winsize 63
5097 01:22:22.362979 [CA 4] Center 34 (4~65) winsize 62
5098 01:22:22.365869 [CA 5] Center 34 (4~64) winsize 61
5099 01:22:22.365963
5100 01:22:22.369392 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5101 01:22:22.369480
5102 01:22:22.372725 [CATrainingPosCal] consider 1 rank data
5103 01:22:22.375770 u2DelayCellTimex100 = 270/100 ps
5104 01:22:22.379021 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5105 01:22:22.382298 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5106 01:22:22.385878 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5107 01:22:22.389195 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5108 01:22:22.392336 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5109 01:22:22.395435 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5110 01:22:22.395557
5111 01:22:22.402325 CA PerBit enable=1, Macro0, CA PI delay=34
5112 01:22:22.402440
5113 01:22:22.402513 [CBTSetCACLKResult] CA Dly = 34
5114 01:22:22.405473 CS Dly: 7 (0~38)
5115 01:22:22.405572 ==
5116 01:22:22.409211 Dram Type= 6, Freq= 0, CH_0, rank 1
5117 01:22:22.412443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5118 01:22:22.412538 ==
5119 01:22:22.418937 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5120 01:22:22.425398 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5121 01:22:22.428533 [CA 0] Center 38 (8~69) winsize 62
5122 01:22:22.432344 [CA 1] Center 38 (8~69) winsize 62
5123 01:22:22.435571 [CA 2] Center 35 (5~66) winsize 62
5124 01:22:22.438672 [CA 3] Center 35 (5~66) winsize 62
5125 01:22:22.441700 [CA 4] Center 34 (4~65) winsize 62
5126 01:22:22.445530 [CA 5] Center 33 (3~64) winsize 62
5127 01:22:22.445627
5128 01:22:22.448547 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5129 01:22:22.448686
5130 01:22:22.452243 [CATrainingPosCal] consider 2 rank data
5131 01:22:22.455333 u2DelayCellTimex100 = 270/100 ps
5132 01:22:22.458467 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5133 01:22:22.462081 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5134 01:22:22.465237 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5135 01:22:22.468718 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5136 01:22:22.472009 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5137 01:22:22.478450 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5138 01:22:22.478596
5139 01:22:22.481854 CA PerBit enable=1, Macro0, CA PI delay=34
5140 01:22:22.481977
5141 01:22:22.485109 [CBTSetCACLKResult] CA Dly = 34
5142 01:22:22.485203 CS Dly: 7 (0~39)
5143 01:22:22.485275
5144 01:22:22.487991 ----->DramcWriteLeveling(PI) begin...
5145 01:22:22.488083 ==
5146 01:22:22.491592 Dram Type= 6, Freq= 0, CH_0, rank 0
5147 01:22:22.498359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5148 01:22:22.498474 ==
5149 01:22:22.501737 Write leveling (Byte 0): 31 => 31
5150 01:22:22.501835 Write leveling (Byte 1): 31 => 31
5151 01:22:22.504853 DramcWriteLeveling(PI) end<-----
5152 01:22:22.504955
5153 01:22:22.505027 ==
5154 01:22:22.508429 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 01:22:22.514711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 01:22:22.514823 ==
5157 01:22:22.517888 [Gating] SW mode calibration
5158 01:22:22.524761 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5159 01:22:22.527857 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5160 01:22:22.534531 0 14 0 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
5161 01:22:22.537706 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5162 01:22:22.541497 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 01:22:22.547859 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 01:22:22.551085 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 01:22:22.554883 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 01:22:22.561266 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 01:22:22.564316 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
5168 01:22:22.567999 0 15 0 | B1->B0 | 3434 2929 | 0 1 | (0 0) (1 0)
5169 01:22:22.574647 0 15 4 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
5170 01:22:22.578039 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 01:22:22.581024 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 01:22:22.587502 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 01:22:22.591003 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 01:22:22.594368 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 01:22:22.600694 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5176 01:22:22.604335 1 0 0 | B1->B0 | 2828 3a3a | 0 1 | (0 0) (0 0)
5177 01:22:22.607410 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5178 01:22:22.613825 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 01:22:22.617437 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 01:22:22.621105 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 01:22:22.623969 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 01:22:22.630939 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 01:22:22.634020 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 01:22:22.637399 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5185 01:22:22.644214 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 01:22:22.647177 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 01:22:22.650247 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 01:22:22.657069 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 01:22:22.660278 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 01:22:22.664003 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 01:22:22.670116 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 01:22:22.673742 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 01:22:22.676869 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 01:22:22.683703 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 01:22:22.686753 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 01:22:22.690128 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 01:22:22.696687 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 01:22:22.699932 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 01:22:22.703442 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5200 01:22:22.709881 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5201 01:22:22.713055 Total UI for P1: 0, mck2ui 16
5202 01:22:22.716246 best dqsien dly found for B0: ( 1, 2, 28)
5203 01:22:22.719682 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5204 01:22:22.722990 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 01:22:22.726400 Total UI for P1: 0, mck2ui 16
5206 01:22:22.729881 best dqsien dly found for B1: ( 1, 3, 4)
5207 01:22:22.733063 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5208 01:22:22.736059 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5209 01:22:22.739722
5210 01:22:22.743220 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5211 01:22:22.746279 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5212 01:22:22.749440 [Gating] SW calibration Done
5213 01:22:22.749560 ==
5214 01:22:22.753038 Dram Type= 6, Freq= 0, CH_0, rank 0
5215 01:22:22.756148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5216 01:22:22.756244 ==
5217 01:22:22.756340 RX Vref Scan: 0
5218 01:22:22.756409
5219 01:22:22.759370 RX Vref 0 -> 0, step: 1
5220 01:22:22.759472
5221 01:22:22.763282 RX Delay -80 -> 252, step: 8
5222 01:22:22.766322 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5223 01:22:22.769284 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5224 01:22:22.776147 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5225 01:22:22.779201 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5226 01:22:22.782806 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5227 01:22:22.785797 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5228 01:22:22.789417 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5229 01:22:22.792605 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5230 01:22:22.798894 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5231 01:22:22.802377 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5232 01:22:22.805799 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5233 01:22:22.809004 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5234 01:22:22.812380 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5235 01:22:22.818663 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5236 01:22:22.822060 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5237 01:22:22.825395 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5238 01:22:22.825487 ==
5239 01:22:22.828566 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 01:22:22.831867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 01:22:22.835307 ==
5242 01:22:22.835428 DQS Delay:
5243 01:22:22.835524 DQS0 = 0, DQS1 = 0
5244 01:22:22.838889 DQM Delay:
5245 01:22:22.839012 DQM0 = 94, DQM1 = 82
5246 01:22:22.842462 DQ Delay:
5247 01:22:22.842578 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5248 01:22:22.845025 DQ4 =95, DQ5 =79, DQ6 =99, DQ7 =111
5249 01:22:22.848838 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =75
5250 01:22:22.852147 DQ12 =83, DQ13 =87, DQ14 =91, DQ15 =91
5251 01:22:22.854934
5252 01:22:22.855023
5253 01:22:22.855090 ==
5254 01:22:22.858441 Dram Type= 6, Freq= 0, CH_0, rank 0
5255 01:22:22.861484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5256 01:22:22.861604 ==
5257 01:22:22.861682
5258 01:22:22.861745
5259 01:22:22.865259 TX Vref Scan disable
5260 01:22:22.865375 == TX Byte 0 ==
5261 01:22:22.871582 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5262 01:22:22.875167 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5263 01:22:22.875272 == TX Byte 1 ==
5264 01:22:22.881567 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5265 01:22:22.884799 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5266 01:22:22.884896 ==
5267 01:22:22.888423 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 01:22:22.891411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 01:22:22.891524 ==
5270 01:22:22.891636
5271 01:22:22.891706
5272 01:22:22.894481 TX Vref Scan disable
5273 01:22:22.898295 == TX Byte 0 ==
5274 01:22:22.901239 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5275 01:22:22.905059 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5276 01:22:22.908181 == TX Byte 1 ==
5277 01:22:22.911307 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5278 01:22:22.914908 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5279 01:22:22.915011
5280 01:22:22.917859 [DATLAT]
5281 01:22:22.917951 Freq=933, CH0 RK0
5282 01:22:22.918018
5283 01:22:22.921073 DATLAT Default: 0xd
5284 01:22:22.921161 0, 0xFFFF, sum = 0
5285 01:22:22.924684 1, 0xFFFF, sum = 0
5286 01:22:22.924776 2, 0xFFFF, sum = 0
5287 01:22:22.928089 3, 0xFFFF, sum = 0
5288 01:22:22.928185 4, 0xFFFF, sum = 0
5289 01:22:22.931001 5, 0xFFFF, sum = 0
5290 01:22:22.931093 6, 0xFFFF, sum = 0
5291 01:22:22.934530 7, 0xFFFF, sum = 0
5292 01:22:22.937951 8, 0xFFFF, sum = 0
5293 01:22:22.938056 9, 0xFFFF, sum = 0
5294 01:22:22.941056 10, 0x0, sum = 1
5295 01:22:22.941153 11, 0x0, sum = 2
5296 01:22:22.941223 12, 0x0, sum = 3
5297 01:22:22.944205 13, 0x0, sum = 4
5298 01:22:22.944325 best_step = 11
5299 01:22:22.944426
5300 01:22:22.944491 ==
5301 01:22:22.947967 Dram Type= 6, Freq= 0, CH_0, rank 0
5302 01:22:22.954475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5303 01:22:22.954587 ==
5304 01:22:22.954668 RX Vref Scan: 1
5305 01:22:22.954742
5306 01:22:22.957988 RX Vref 0 -> 0, step: 1
5307 01:22:22.958078
5308 01:22:22.961043 RX Delay -69 -> 252, step: 4
5309 01:22:22.961162
5310 01:22:22.964108 Set Vref, RX VrefLevel [Byte0]: 62
5311 01:22:22.967531 [Byte1]: 47
5312 01:22:22.967630
5313 01:22:22.970620 Final RX Vref Byte 0 = 62 to rank0
5314 01:22:22.974247 Final RX Vref Byte 1 = 47 to rank0
5315 01:22:22.977473 Final RX Vref Byte 0 = 62 to rank1
5316 01:22:22.980682 Final RX Vref Byte 1 = 47 to rank1==
5317 01:22:22.984468 Dram Type= 6, Freq= 0, CH_0, rank 0
5318 01:22:22.987509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5319 01:22:22.987609 ==
5320 01:22:22.990721 DQS Delay:
5321 01:22:22.990813 DQS0 = 0, DQS1 = 0
5322 01:22:22.993851 DQM Delay:
5323 01:22:22.993951 DQM0 = 95, DQM1 = 82
5324 01:22:22.994040 DQ Delay:
5325 01:22:22.997071 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =92
5326 01:22:23.001047 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5327 01:22:23.004232 DQ8 =74, DQ9 =68, DQ10 =82, DQ11 =78
5328 01:22:23.007402 DQ12 =86, DQ13 =88, DQ14 =96, DQ15 =90
5329 01:22:23.011022
5330 01:22:23.011146
5331 01:22:23.016985 [DQSOSCAuto] RK0, (LSB)MR18= 0x1111, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5332 01:22:23.020605 CH0 RK0: MR19=505, MR18=1111
5333 01:22:23.027220 CH0_RK0: MR19=0x505, MR18=0x1111, DQSOSC=416, MR23=63, INC=62, DEC=41
5334 01:22:23.027337
5335 01:22:23.030709 ----->DramcWriteLeveling(PI) begin...
5336 01:22:23.030802 ==
5337 01:22:23.033826 Dram Type= 6, Freq= 0, CH_0, rank 1
5338 01:22:23.037207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5339 01:22:23.037297 ==
5340 01:22:23.040615 Write leveling (Byte 0): 33 => 33
5341 01:22:23.043273 Write leveling (Byte 1): 27 => 27
5342 01:22:23.046649 DramcWriteLeveling(PI) end<-----
5343 01:22:23.046775
5344 01:22:23.046849 ==
5345 01:22:23.050178 Dram Type= 6, Freq= 0, CH_0, rank 1
5346 01:22:23.053305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5347 01:22:23.053427 ==
5348 01:22:23.056926 [Gating] SW mode calibration
5349 01:22:23.063231 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5350 01:22:23.069810 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5351 01:22:23.073232 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5352 01:22:23.080097 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 01:22:23.083137 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 01:22:23.086858 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 01:22:23.089831 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 01:22:23.096709 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 01:22:23.099795 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5358 01:22:23.102998 0 14 28 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
5359 01:22:23.109967 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5360 01:22:23.113625 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 01:22:23.116812 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 01:22:23.123079 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 01:22:23.126854 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 01:22:23.129854 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 01:22:23.136619 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 01:22:23.139794 0 15 28 | B1->B0 | 2727 3131 | 0 0 | (0 0) (0 0)
5367 01:22:23.142867 1 0 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
5368 01:22:23.149830 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 01:22:23.153126 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 01:22:23.156377 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 01:22:23.162841 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 01:22:23.166249 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 01:22:23.169153 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 01:22:23.175875 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5375 01:22:23.179364 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5376 01:22:23.182290 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 01:22:23.189268 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 01:22:23.192489 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 01:22:23.196209 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 01:22:23.202323 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 01:22:23.205590 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 01:22:23.209256 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 01:22:23.215606 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 01:22:23.218775 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 01:22:23.221963 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 01:22:23.228767 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 01:22:23.232128 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 01:22:23.235101 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 01:22:23.241838 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 01:22:23.245504 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5391 01:22:23.248617 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5392 01:22:23.251631 Total UI for P1: 0, mck2ui 16
5393 01:22:23.255199 best dqsien dly found for B0: ( 1, 2, 28)
5394 01:22:23.261998 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 01:22:23.262153 Total UI for P1: 0, mck2ui 16
5396 01:22:23.268572 best dqsien dly found for B1: ( 1, 2, 30)
5397 01:22:23.271614 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5398 01:22:23.275223 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5399 01:22:23.275361
5400 01:22:23.278201 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5401 01:22:23.281699 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5402 01:22:23.285078 [Gating] SW calibration Done
5403 01:22:23.285206 ==
5404 01:22:23.288388 Dram Type= 6, Freq= 0, CH_0, rank 1
5405 01:22:23.291214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5406 01:22:23.291320 ==
5407 01:22:23.294672 RX Vref Scan: 0
5408 01:22:23.294774
5409 01:22:23.294863 RX Vref 0 -> 0, step: 1
5410 01:22:23.294945
5411 01:22:23.298484 RX Delay -80 -> 252, step: 8
5412 01:22:23.304451 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5413 01:22:23.308171 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5414 01:22:23.311396 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5415 01:22:23.314539 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5416 01:22:23.318234 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5417 01:22:23.321275 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5418 01:22:23.327521 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5419 01:22:23.331159 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5420 01:22:23.334250 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5421 01:22:23.338013 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5422 01:22:23.341126 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5423 01:22:23.347653 iDelay=208, Bit 11, Center 71 (-24 ~ 167) 192
5424 01:22:23.350664 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5425 01:22:23.354653 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5426 01:22:23.357928 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5427 01:22:23.360744 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5428 01:22:23.360840 ==
5429 01:22:23.364464 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 01:22:23.370583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 01:22:23.370700 ==
5432 01:22:23.370778 DQS Delay:
5433 01:22:23.374015 DQS0 = 0, DQS1 = 0
5434 01:22:23.374109 DQM Delay:
5435 01:22:23.377397 DQM0 = 91, DQM1 = 81
5436 01:22:23.377522 DQ Delay:
5437 01:22:23.380684 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5438 01:22:23.384084 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5439 01:22:23.387614 DQ8 =71, DQ9 =63, DQ10 =87, DQ11 =71
5440 01:22:23.390725 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =87
5441 01:22:23.390822
5442 01:22:23.390890
5443 01:22:23.390953 ==
5444 01:22:23.394142 Dram Type= 6, Freq= 0, CH_0, rank 1
5445 01:22:23.396964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5446 01:22:23.397049 ==
5447 01:22:23.397122
5448 01:22:23.397184
5449 01:22:23.400454 TX Vref Scan disable
5450 01:22:23.403601 == TX Byte 0 ==
5451 01:22:23.407152 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5452 01:22:23.410651 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5453 01:22:23.413466 == TX Byte 1 ==
5454 01:22:23.416794 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5455 01:22:23.420376 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5456 01:22:23.420514 ==
5457 01:22:23.424111 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 01:22:23.430049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 01:22:23.430169 ==
5460 01:22:23.430244
5461 01:22:23.430306
5462 01:22:23.430379 TX Vref Scan disable
5463 01:22:23.434611 == TX Byte 0 ==
5464 01:22:23.437621 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5465 01:22:23.443967 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5466 01:22:23.444086 == TX Byte 1 ==
5467 01:22:23.447693 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5468 01:22:23.454422 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5469 01:22:23.454566
5470 01:22:23.454668 [DATLAT]
5471 01:22:23.454770 Freq=933, CH0 RK1
5472 01:22:23.454862
5473 01:22:23.457533 DATLAT Default: 0xb
5474 01:22:23.457611 0, 0xFFFF, sum = 0
5475 01:22:23.460545 1, 0xFFFF, sum = 0
5476 01:22:23.460658 2, 0xFFFF, sum = 0
5477 01:22:23.464325 3, 0xFFFF, sum = 0
5478 01:22:23.467392 4, 0xFFFF, sum = 0
5479 01:22:23.467520 5, 0xFFFF, sum = 0
5480 01:22:23.470672 6, 0xFFFF, sum = 0
5481 01:22:23.470793 7, 0xFFFF, sum = 0
5482 01:22:23.474223 8, 0xFFFF, sum = 0
5483 01:22:23.474309 9, 0xFFFF, sum = 0
5484 01:22:23.477392 10, 0x0, sum = 1
5485 01:22:23.477521 11, 0x0, sum = 2
5486 01:22:23.480907 12, 0x0, sum = 3
5487 01:22:23.481023 13, 0x0, sum = 4
5488 01:22:23.481122 best_step = 11
5489 01:22:23.481213
5490 01:22:23.483859 ==
5491 01:22:23.483936 Dram Type= 6, Freq= 0, CH_0, rank 1
5492 01:22:23.490947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5493 01:22:23.491052 ==
5494 01:22:23.491132 RX Vref Scan: 0
5495 01:22:23.491197
5496 01:22:23.494270 RX Vref 0 -> 0, step: 1
5497 01:22:23.494354
5498 01:22:23.497476 RX Delay -77 -> 252, step: 4
5499 01:22:23.500337 iDelay=199, Bit 0, Center 88 (-5 ~ 182) 188
5500 01:22:23.506936 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5501 01:22:23.510356 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5502 01:22:23.513963 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5503 01:22:23.517184 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5504 01:22:23.520737 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5505 01:22:23.527074 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5506 01:22:23.530466 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5507 01:22:23.533590 iDelay=199, Bit 8, Center 74 (-13 ~ 162) 176
5508 01:22:23.537220 iDelay=199, Bit 9, Center 66 (-21 ~ 154) 176
5509 01:22:23.540477 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5510 01:22:23.546727 iDelay=199, Bit 11, Center 74 (-13 ~ 162) 176
5511 01:22:23.550407 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5512 01:22:23.553450 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5513 01:22:23.556997 iDelay=199, Bit 14, Center 96 (11 ~ 182) 172
5514 01:22:23.560250 iDelay=199, Bit 15, Center 90 (-1 ~ 182) 184
5515 01:22:23.560387 ==
5516 01:22:23.563759 Dram Type= 6, Freq= 0, CH_0, rank 1
5517 01:22:23.569976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5518 01:22:23.570080 ==
5519 01:22:23.570153 DQS Delay:
5520 01:22:23.573225 DQS0 = 0, DQS1 = 0
5521 01:22:23.573342 DQM Delay:
5522 01:22:23.573438 DQM0 = 92, DQM1 = 83
5523 01:22:23.576395 DQ Delay:
5524 01:22:23.580115 DQ0 =88, DQ1 =94, DQ2 =88, DQ3 =88
5525 01:22:23.583383 DQ4 =92, DQ5 =82, DQ6 =104, DQ7 =104
5526 01:22:23.586384 DQ8 =74, DQ9 =66, DQ10 =86, DQ11 =74
5527 01:22:23.590095 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =90
5528 01:22:23.590218
5529 01:22:23.590328
5530 01:22:23.596823 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 408 ps
5531 01:22:23.599784 CH0 RK1: MR19=505, MR18=2C0E
5532 01:22:23.606252 CH0_RK1: MR19=0x505, MR18=0x2C0E, DQSOSC=408, MR23=63, INC=65, DEC=43
5533 01:22:23.609995 [RxdqsGatingPostProcess] freq 933
5534 01:22:23.616321 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5535 01:22:23.616443 best DQS0 dly(2T, 0.5T) = (0, 10)
5536 01:22:23.619548 best DQS1 dly(2T, 0.5T) = (0, 11)
5537 01:22:23.622790 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5538 01:22:23.626195 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5539 01:22:23.629768 best DQS0 dly(2T, 0.5T) = (0, 10)
5540 01:22:23.632703 best DQS1 dly(2T, 0.5T) = (0, 10)
5541 01:22:23.636403 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5542 01:22:23.639728 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5543 01:22:23.643009 Pre-setting of DQS Precalculation
5544 01:22:23.649291 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5545 01:22:23.649435 ==
5546 01:22:23.653053 Dram Type= 6, Freq= 0, CH_1, rank 0
5547 01:22:23.656073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5548 01:22:23.656160 ==
5549 01:22:23.662604 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5550 01:22:23.665558 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5551 01:22:23.669962 [CA 0] Center 37 (7~67) winsize 61
5552 01:22:23.673181 [CA 1] Center 37 (7~68) winsize 62
5553 01:22:23.676870 [CA 2] Center 34 (5~64) winsize 60
5554 01:22:23.679751 [CA 3] Center 34 (4~64) winsize 61
5555 01:22:23.682757 [CA 4] Center 34 (4~64) winsize 61
5556 01:22:23.686408 [CA 5] Center 33 (4~63) winsize 60
5557 01:22:23.686529
5558 01:22:23.689413 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5559 01:22:23.689506
5560 01:22:23.692910 [CATrainingPosCal] consider 1 rank data
5561 01:22:23.696462 u2DelayCellTimex100 = 270/100 ps
5562 01:22:23.699513 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5563 01:22:23.706261 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5564 01:22:23.709989 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5565 01:22:23.712815 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5566 01:22:23.716291 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5567 01:22:23.719720 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5568 01:22:23.719882
5569 01:22:23.723108 CA PerBit enable=1, Macro0, CA PI delay=33
5570 01:22:23.723226
5571 01:22:23.726120 [CBTSetCACLKResult] CA Dly = 33
5572 01:22:23.726258 CS Dly: 5 (0~36)
5573 01:22:23.729833 ==
5574 01:22:23.729949 Dram Type= 6, Freq= 0, CH_1, rank 1
5575 01:22:23.736419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5576 01:22:23.736595 ==
5577 01:22:23.739691 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5578 01:22:23.746270 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5579 01:22:23.749700 [CA 0] Center 37 (7~67) winsize 61
5580 01:22:23.753139 [CA 1] Center 37 (7~68) winsize 62
5581 01:22:23.756441 [CA 2] Center 35 (5~65) winsize 61
5582 01:22:23.759810 [CA 3] Center 34 (4~65) winsize 62
5583 01:22:23.762777 [CA 4] Center 34 (4~65) winsize 62
5584 01:22:23.766274 [CA 5] Center 34 (4~65) winsize 62
5585 01:22:23.766401
5586 01:22:23.769736 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5587 01:22:23.769847
5588 01:22:23.772804 [CATrainingPosCal] consider 2 rank data
5589 01:22:23.776307 u2DelayCellTimex100 = 270/100 ps
5590 01:22:23.779308 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5591 01:22:23.786121 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5592 01:22:23.789139 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5593 01:22:23.792811 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5594 01:22:23.795887 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5595 01:22:23.798954 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5596 01:22:23.799147
5597 01:22:23.802522 CA PerBit enable=1, Macro0, CA PI delay=33
5598 01:22:23.802647
5599 01:22:23.805730 [CBTSetCACLKResult] CA Dly = 33
5600 01:22:23.808646 CS Dly: 6 (0~39)
5601 01:22:23.808739
5602 01:22:23.812250 ----->DramcWriteLeveling(PI) begin...
5603 01:22:23.812346 ==
5604 01:22:23.815380 Dram Type= 6, Freq= 0, CH_1, rank 0
5605 01:22:23.819152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5606 01:22:23.819275 ==
5607 01:22:23.822201 Write leveling (Byte 0): 25 => 25
5608 01:22:23.825524 Write leveling (Byte 1): 26 => 26
5609 01:22:23.828911 DramcWriteLeveling(PI) end<-----
5610 01:22:23.829040
5611 01:22:23.829139 ==
5612 01:22:23.831852 Dram Type= 6, Freq= 0, CH_1, rank 0
5613 01:22:23.835373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5614 01:22:23.835464 ==
5615 01:22:23.838957 [Gating] SW mode calibration
5616 01:22:23.845108 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5617 01:22:23.851637 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5618 01:22:23.855078 0 14 0 | B1->B0 | 3232 3333 | 0 0 | (0 0) (0 0)
5619 01:22:23.858190 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 01:22:23.865193 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 01:22:23.868507 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 01:22:23.871600 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5623 01:22:23.878065 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 01:22:23.881808 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 01:22:23.884830 0 14 28 | B1->B0 | 3131 2f2f | 1 0 | (1 0) (0 1)
5626 01:22:23.891713 0 15 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (1 0)
5627 01:22:23.894732 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 01:22:23.898323 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 01:22:23.905047 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 01:22:23.908057 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5631 01:22:23.911107 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 01:22:23.917885 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 01:22:23.921018 0 15 28 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
5634 01:22:23.924758 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 01:22:23.930985 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 01:22:23.934573 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 01:22:23.938082 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 01:22:23.944289 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 01:22:23.947244 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 01:22:23.950790 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 01:22:23.957281 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5642 01:22:23.961133 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5643 01:22:23.964053 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 01:22:23.970924 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 01:22:23.973947 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 01:22:23.977569 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 01:22:23.984162 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 01:22:23.987513 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 01:22:23.990558 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 01:22:23.997055 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 01:22:24.000721 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 01:22:24.003667 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 01:22:24.010371 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 01:22:24.013856 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 01:22:24.016902 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 01:22:24.023481 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 01:22:24.026506 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5658 01:22:24.030272 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 01:22:24.033407 Total UI for P1: 0, mck2ui 16
5660 01:22:24.036570 best dqsien dly found for B0: ( 1, 2, 28)
5661 01:22:24.040034 Total UI for P1: 0, mck2ui 16
5662 01:22:24.043353 best dqsien dly found for B1: ( 1, 2, 28)
5663 01:22:24.046815 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5664 01:22:24.049727 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5665 01:22:24.052971
5666 01:22:24.056556 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5667 01:22:24.059792 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5668 01:22:24.063313 [Gating] SW calibration Done
5669 01:22:24.063404 ==
5670 01:22:24.066333 Dram Type= 6, Freq= 0, CH_1, rank 0
5671 01:22:24.069651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5672 01:22:24.069747 ==
5673 01:22:24.069837 RX Vref Scan: 0
5674 01:22:24.072993
5675 01:22:24.073087 RX Vref 0 -> 0, step: 1
5676 01:22:24.073176
5677 01:22:24.076249 RX Delay -80 -> 252, step: 8
5678 01:22:24.079818 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5679 01:22:24.082798 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5680 01:22:24.089630 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5681 01:22:24.092847 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5682 01:22:24.096358 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5683 01:22:24.099326 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5684 01:22:24.102473 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5685 01:22:24.106259 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5686 01:22:24.112622 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5687 01:22:24.115956 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5688 01:22:24.119031 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5689 01:22:24.122772 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5690 01:22:24.125920 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5691 01:22:24.132695 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5692 01:22:24.135785 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5693 01:22:24.139597 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5694 01:22:24.139800 ==
5695 01:22:24.142820 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 01:22:24.145895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 01:22:24.145991 ==
5698 01:22:24.149302 DQS Delay:
5699 01:22:24.149391 DQS0 = 0, DQS1 = 0
5700 01:22:24.152605 DQM Delay:
5701 01:22:24.152684 DQM0 = 95, DQM1 = 87
5702 01:22:24.152751 DQ Delay:
5703 01:22:24.155817 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5704 01:22:24.159034 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5705 01:22:24.162348 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5706 01:22:24.165404 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =91
5707 01:22:24.165526
5708 01:22:24.169191
5709 01:22:24.169297 ==
5710 01:22:24.172397 Dram Type= 6, Freq= 0, CH_1, rank 0
5711 01:22:24.175802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5712 01:22:24.175928 ==
5713 01:22:24.176028
5714 01:22:24.176124
5715 01:22:24.178712 TX Vref Scan disable
5716 01:22:24.178799 == TX Byte 0 ==
5717 01:22:24.185524 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5718 01:22:24.189258 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5719 01:22:24.189363 == TX Byte 1 ==
5720 01:22:24.195669 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5721 01:22:24.199053 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5722 01:22:24.199180 ==
5723 01:22:24.201914 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 01:22:24.205692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 01:22:24.205792 ==
5726 01:22:24.205863
5727 01:22:24.205925
5728 01:22:24.208796 TX Vref Scan disable
5729 01:22:24.212291 == TX Byte 0 ==
5730 01:22:24.215367 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5731 01:22:24.219035 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5732 01:22:24.222342 == TX Byte 1 ==
5733 01:22:24.225390 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5734 01:22:24.228738 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5735 01:22:24.228829
5736 01:22:24.232088 [DATLAT]
5737 01:22:24.232168 Freq=933, CH1 RK0
5738 01:22:24.232232
5739 01:22:24.235123 DATLAT Default: 0xd
5740 01:22:24.235209 0, 0xFFFF, sum = 0
5741 01:22:24.238280 1, 0xFFFF, sum = 0
5742 01:22:24.238364 2, 0xFFFF, sum = 0
5743 01:22:24.241945 3, 0xFFFF, sum = 0
5744 01:22:24.242037 4, 0xFFFF, sum = 0
5745 01:22:24.244927 5, 0xFFFF, sum = 0
5746 01:22:24.245035 6, 0xFFFF, sum = 0
5747 01:22:24.248829 7, 0xFFFF, sum = 0
5748 01:22:24.248939 8, 0xFFFF, sum = 0
5749 01:22:24.251823 9, 0xFFFF, sum = 0
5750 01:22:24.251903 10, 0x0, sum = 1
5751 01:22:24.255106 11, 0x0, sum = 2
5752 01:22:24.255187 12, 0x0, sum = 3
5753 01:22:24.258237 13, 0x0, sum = 4
5754 01:22:24.258316 best_step = 11
5755 01:22:24.258403
5756 01:22:24.258465 ==
5757 01:22:24.261737 Dram Type= 6, Freq= 0, CH_1, rank 0
5758 01:22:24.268455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5759 01:22:24.268585 ==
5760 01:22:24.268686 RX Vref Scan: 1
5761 01:22:24.268777
5762 01:22:24.271659 RX Vref 0 -> 0, step: 1
5763 01:22:24.271738
5764 01:22:24.274708 RX Delay -61 -> 252, step: 4
5765 01:22:24.274841
5766 01:22:24.278251 Set Vref, RX VrefLevel [Byte0]: 54
5767 01:22:24.281246 [Byte1]: 48
5768 01:22:24.281360
5769 01:22:24.284763 Final RX Vref Byte 0 = 54 to rank0
5770 01:22:24.288178 Final RX Vref Byte 1 = 48 to rank0
5771 01:22:24.291655 Final RX Vref Byte 0 = 54 to rank1
5772 01:22:24.295059 Final RX Vref Byte 1 = 48 to rank1==
5773 01:22:24.298271 Dram Type= 6, Freq= 0, CH_1, rank 0
5774 01:22:24.300975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5775 01:22:24.301078 ==
5776 01:22:24.304694 DQS Delay:
5777 01:22:24.304776 DQS0 = 0, DQS1 = 0
5778 01:22:24.307856 DQM Delay:
5779 01:22:24.307934 DQM0 = 95, DQM1 = 88
5780 01:22:24.307998 DQ Delay:
5781 01:22:24.311079 DQ0 =100, DQ1 =90, DQ2 =84, DQ3 =92
5782 01:22:24.314614 DQ4 =92, DQ5 =106, DQ6 =108, DQ7 =92
5783 01:22:24.317867 DQ8 =74, DQ9 =82, DQ10 =88, DQ11 =82
5784 01:22:24.321328 DQ12 =98, DQ13 =92, DQ14 =96, DQ15 =94
5785 01:22:24.321418
5786 01:22:24.324133
5787 01:22:24.330763 [DQSOSCAuto] RK0, (LSB)MR18= 0xff08, (MSB)MR19= 0x405, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5788 01:22:24.334259 CH1 RK0: MR19=405, MR18=FF08
5789 01:22:24.340672 CH1_RK0: MR19=0x405, MR18=0xFF08, DQSOSC=419, MR23=63, INC=61, DEC=41
5790 01:22:24.340851
5791 01:22:24.344244 ----->DramcWriteLeveling(PI) begin...
5792 01:22:24.344374 ==
5793 01:22:24.347260 Dram Type= 6, Freq= 0, CH_1, rank 1
5794 01:22:24.350555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5795 01:22:24.350640 ==
5796 01:22:24.354216 Write leveling (Byte 0): 28 => 28
5797 01:22:24.357273 Write leveling (Byte 1): 29 => 29
5798 01:22:24.360938 DramcWriteLeveling(PI) end<-----
5799 01:22:24.361031
5800 01:22:24.361101 ==
5801 01:22:24.364083 Dram Type= 6, Freq= 0, CH_1, rank 1
5802 01:22:24.367791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5803 01:22:24.367878 ==
5804 01:22:24.371019 [Gating] SW mode calibration
5805 01:22:24.377216 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5806 01:22:24.384041 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5807 01:22:24.387102 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 01:22:24.390821 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 01:22:24.397288 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5810 01:22:24.400447 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5811 01:22:24.404100 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5812 01:22:24.410388 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 01:22:24.413431 0 14 24 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (1 1)
5814 01:22:24.416604 0 14 28 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
5815 01:22:24.423730 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5816 01:22:24.426950 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 01:22:24.430056 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5818 01:22:24.436922 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5819 01:22:24.439821 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5820 01:22:24.443633 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 01:22:24.449978 0 15 24 | B1->B0 | 2727 3636 | 0 0 | (0 0) (0 0)
5822 01:22:24.453043 0 15 28 | B1->B0 | 3a3a 4343 | 0 0 | (0 0) (1 1)
5823 01:22:24.456790 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5824 01:22:24.463272 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 01:22:24.466228 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 01:22:24.470236 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 01:22:24.476231 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 01:22:24.479977 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 01:22:24.482943 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 01:22:24.489613 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5831 01:22:24.493057 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 01:22:24.496120 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 01:22:24.503146 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 01:22:24.506099 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 01:22:24.509686 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 01:22:24.515914 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 01:22:24.519838 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 01:22:24.522665 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 01:22:24.529589 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 01:22:24.532613 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 01:22:24.535689 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 01:22:24.542307 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 01:22:24.545722 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 01:22:24.549146 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 01:22:24.555966 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5846 01:22:24.559038 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5847 01:22:24.562211 Total UI for P1: 0, mck2ui 16
5848 01:22:24.565968 best dqsien dly found for B0: ( 1, 2, 24)
5849 01:22:24.569077 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5850 01:22:24.572244 Total UI for P1: 0, mck2ui 16
5851 01:22:24.575354 best dqsien dly found for B1: ( 1, 2, 28)
5852 01:22:24.579123 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5853 01:22:24.582244 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5854 01:22:24.582343
5855 01:22:24.588480 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5856 01:22:24.592329 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5857 01:22:24.592483 [Gating] SW calibration Done
5858 01:22:24.595216 ==
5859 01:22:24.598579 Dram Type= 6, Freq= 0, CH_1, rank 1
5860 01:22:24.601956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5861 01:22:24.602058 ==
5862 01:22:24.602141 RX Vref Scan: 0
5863 01:22:24.602221
5864 01:22:24.605122 RX Vref 0 -> 0, step: 1
5865 01:22:24.605245
5866 01:22:24.608702 RX Delay -80 -> 252, step: 8
5867 01:22:24.611702 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5868 01:22:24.615330 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5869 01:22:24.618493 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5870 01:22:24.625248 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5871 01:22:24.628814 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5872 01:22:24.631904 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5873 01:22:24.635006 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5874 01:22:24.638571 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5875 01:22:24.644823 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5876 01:22:24.648523 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5877 01:22:24.651320 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5878 01:22:24.655036 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5879 01:22:24.658619 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5880 01:22:24.665131 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5881 01:22:24.668196 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5882 01:22:24.671354 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5883 01:22:24.671457 ==
5884 01:22:24.675072 Dram Type= 6, Freq= 0, CH_1, rank 1
5885 01:22:24.678184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5886 01:22:24.678282 ==
5887 01:22:24.681265 DQS Delay:
5888 01:22:24.681389 DQS0 = 0, DQS1 = 0
5889 01:22:24.681506 DQM Delay:
5890 01:22:24.684425 DQM0 = 94, DQM1 = 88
5891 01:22:24.684553 DQ Delay:
5892 01:22:24.688235 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5893 01:22:24.691104 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5894 01:22:24.694747 DQ8 =75, DQ9 =79, DQ10 =95, DQ11 =79
5895 01:22:24.698043 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5896 01:22:24.698174
5897 01:22:24.698283
5898 01:22:24.698384 ==
5899 01:22:24.701002 Dram Type= 6, Freq= 0, CH_1, rank 1
5900 01:22:24.708048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5901 01:22:24.708200 ==
5902 01:22:24.708309
5903 01:22:24.708407
5904 01:22:24.708499 TX Vref Scan disable
5905 01:22:24.711356 == TX Byte 0 ==
5906 01:22:24.714656 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5907 01:22:24.721345 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5908 01:22:24.721474 == TX Byte 1 ==
5909 01:22:24.725020 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5910 01:22:24.731245 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5911 01:22:24.731388 ==
5912 01:22:24.734721 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 01:22:24.737752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 01:22:24.737880 ==
5915 01:22:24.737984
5916 01:22:24.738086
5917 01:22:24.741130 TX Vref Scan disable
5918 01:22:24.741257 == TX Byte 0 ==
5919 01:22:24.747944 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5920 01:22:24.751112 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5921 01:22:24.751250 == TX Byte 1 ==
5922 01:22:24.757875 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5923 01:22:24.760926 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5924 01:22:24.761052
5925 01:22:24.761154 [DATLAT]
5926 01:22:24.764536 Freq=933, CH1 RK1
5927 01:22:24.764651
5928 01:22:24.764768 DATLAT Default: 0xb
5929 01:22:24.767891 0, 0xFFFF, sum = 0
5930 01:22:24.770814 1, 0xFFFF, sum = 0
5931 01:22:24.770906 2, 0xFFFF, sum = 0
5932 01:22:24.774433 3, 0xFFFF, sum = 0
5933 01:22:24.774569 4, 0xFFFF, sum = 0
5934 01:22:24.777593 5, 0xFFFF, sum = 0
5935 01:22:24.777711 6, 0xFFFF, sum = 0
5936 01:22:24.781378 7, 0xFFFF, sum = 0
5937 01:22:24.781515 8, 0xFFFF, sum = 0
5938 01:22:24.784394 9, 0xFFFF, sum = 0
5939 01:22:24.784516 10, 0x0, sum = 1
5940 01:22:24.787470 11, 0x0, sum = 2
5941 01:22:24.787599 12, 0x0, sum = 3
5942 01:22:24.791019 13, 0x0, sum = 4
5943 01:22:24.791138 best_step = 11
5944 01:22:24.791255
5945 01:22:24.791354 ==
5946 01:22:24.794244 Dram Type= 6, Freq= 0, CH_1, rank 1
5947 01:22:24.797263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5948 01:22:24.797383 ==
5949 01:22:24.801034 RX Vref Scan: 0
5950 01:22:24.801143
5951 01:22:24.804317 RX Vref 0 -> 0, step: 1
5952 01:22:24.804447
5953 01:22:24.804542 RX Delay -69 -> 252, step: 4
5954 01:22:24.811673 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5955 01:22:24.815422 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5956 01:22:24.818518 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5957 01:22:24.821491 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5958 01:22:24.824871 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5959 01:22:24.831518 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5960 01:22:24.835219 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5961 01:22:24.838525 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5962 01:22:24.841607 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5963 01:22:24.845015 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5964 01:22:24.851580 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5965 01:22:24.854871 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5966 01:22:24.857844 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5967 01:22:24.861450 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5968 01:22:24.864699 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5969 01:22:24.867775 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5970 01:22:24.871254 ==
5971 01:22:24.874753 Dram Type= 6, Freq= 0, CH_1, rank 1
5972 01:22:24.878071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5973 01:22:24.878179 ==
5974 01:22:24.878248 DQS Delay:
5975 01:22:24.880982 DQS0 = 0, DQS1 = 0
5976 01:22:24.881101 DQM Delay:
5977 01:22:24.884136 DQM0 = 92, DQM1 = 90
5978 01:22:24.884231 DQ Delay:
5979 01:22:24.887875 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
5980 01:22:24.891011 DQ4 =90, DQ5 =102, DQ6 =104, DQ7 =88
5981 01:22:24.894108 DQ8 =76, DQ9 =82, DQ10 =92, DQ11 =84
5982 01:22:24.897712 DQ12 =98, DQ13 =98, DQ14 =96, DQ15 =96
5983 01:22:24.897812
5984 01:22:24.897881
5985 01:22:24.904410 [DQSOSCAuto] RK1, (LSB)MR18= 0xc20, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5986 01:22:24.907487 CH1 RK1: MR19=505, MR18=C20
5987 01:22:24.914069 CH1_RK1: MR19=0x505, MR18=0xC20, DQSOSC=411, MR23=63, INC=64, DEC=42
5988 01:22:24.917369 [RxdqsGatingPostProcess] freq 933
5989 01:22:24.924183 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5990 01:22:24.927307 best DQS0 dly(2T, 0.5T) = (0, 10)
5991 01:22:24.927425 best DQS1 dly(2T, 0.5T) = (0, 10)
5992 01:22:24.930521 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5993 01:22:24.933658 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5994 01:22:24.937272 best DQS0 dly(2T, 0.5T) = (0, 10)
5995 01:22:24.940681 best DQS1 dly(2T, 0.5T) = (0, 10)
5996 01:22:24.944069 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5997 01:22:24.947174 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5998 01:22:24.950560 Pre-setting of DQS Precalculation
5999 01:22:24.957066 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6000 01:22:24.963610 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6001 01:22:24.970179 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6002 01:22:24.970308
6003 01:22:24.970412
6004 01:22:24.973410 [Calibration Summary] 1866 Mbps
6005 01:22:24.973530 CH 0, Rank 0
6006 01:22:24.977189 SW Impedance : PASS
6007 01:22:24.980105 DUTY Scan : NO K
6008 01:22:24.980183 ZQ Calibration : PASS
6009 01:22:24.983551 Jitter Meter : NO K
6010 01:22:24.986952 CBT Training : PASS
6011 01:22:24.987067 Write leveling : PASS
6012 01:22:24.990381 RX DQS gating : PASS
6013 01:22:24.993070 RX DQ/DQS(RDDQC) : PASS
6014 01:22:24.993185 TX DQ/DQS : PASS
6015 01:22:24.996327 RX DATLAT : PASS
6016 01:22:25.000125 RX DQ/DQS(Engine): PASS
6017 01:22:25.000206 TX OE : NO K
6018 01:22:25.000287 All Pass.
6019 01:22:25.000354
6020 01:22:25.003093 CH 0, Rank 1
6021 01:22:25.006782 SW Impedance : PASS
6022 01:22:25.006863 DUTY Scan : NO K
6023 01:22:25.010062 ZQ Calibration : PASS
6024 01:22:25.010152 Jitter Meter : NO K
6025 01:22:25.013191 CBT Training : PASS
6026 01:22:25.016238 Write leveling : PASS
6027 01:22:25.016322 RX DQS gating : PASS
6028 01:22:25.019957 RX DQ/DQS(RDDQC) : PASS
6029 01:22:25.023177 TX DQ/DQS : PASS
6030 01:22:25.023268 RX DATLAT : PASS
6031 01:22:25.026365 RX DQ/DQS(Engine): PASS
6032 01:22:25.029873 TX OE : NO K
6033 01:22:25.029990 All Pass.
6034 01:22:25.030090
6035 01:22:25.030194 CH 1, Rank 0
6036 01:22:25.033136 SW Impedance : PASS
6037 01:22:25.036191 DUTY Scan : NO K
6038 01:22:25.036279 ZQ Calibration : PASS
6039 01:22:25.039843 Jitter Meter : NO K
6040 01:22:25.042913 CBT Training : PASS
6041 01:22:25.043002 Write leveling : PASS
6042 01:22:25.046586 RX DQS gating : PASS
6043 01:22:25.049615 RX DQ/DQS(RDDQC) : PASS
6044 01:22:25.049701 TX DQ/DQS : PASS
6045 01:22:25.052970 RX DATLAT : PASS
6046 01:22:25.056162 RX DQ/DQS(Engine): PASS
6047 01:22:25.056268 TX OE : NO K
6048 01:22:25.056373 All Pass.
6049 01:22:25.059234
6050 01:22:25.059344 CH 1, Rank 1
6051 01:22:25.062794 SW Impedance : PASS
6052 01:22:25.062876 DUTY Scan : NO K
6053 01:22:25.065679 ZQ Calibration : PASS
6054 01:22:25.069131 Jitter Meter : NO K
6055 01:22:25.069237 CBT Training : PASS
6056 01:22:25.072322 Write leveling : PASS
6057 01:22:25.072401 RX DQS gating : PASS
6058 01:22:25.075915 RX DQ/DQS(RDDQC) : PASS
6059 01:22:25.079426 TX DQ/DQS : PASS
6060 01:22:25.079539 RX DATLAT : PASS
6061 01:22:25.082468 RX DQ/DQS(Engine): PASS
6062 01:22:25.085674 TX OE : NO K
6063 01:22:25.085763 All Pass.
6064 01:22:25.085829
6065 01:22:25.088766 DramC Write-DBI off
6066 01:22:25.088843 PER_BANK_REFRESH: Hybrid Mode
6067 01:22:25.092461 TX_TRACKING: ON
6068 01:22:25.102192 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6069 01:22:25.105409 [FAST_K] Save calibration result to emmc
6070 01:22:25.108688 dramc_set_vcore_voltage set vcore to 650000
6071 01:22:25.112296 Read voltage for 400, 6
6072 01:22:25.112381 Vio18 = 0
6073 01:22:25.112454 Vcore = 650000
6074 01:22:25.112533 Vdram = 0
6075 01:22:25.115276 Vddq = 0
6076 01:22:25.115355 Vmddr = 0
6077 01:22:25.122076 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6078 01:22:25.125281 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6079 01:22:25.129007 MEM_TYPE=3, freq_sel=20
6080 01:22:25.132130 sv_algorithm_assistance_LP4_800
6081 01:22:25.135709 ============ PULL DRAM RESETB DOWN ============
6082 01:22:25.138718 ========== PULL DRAM RESETB DOWN end =========
6083 01:22:25.145394 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6084 01:22:25.148453 ===================================
6085 01:22:25.148572 LPDDR4 DRAM CONFIGURATION
6086 01:22:25.152143 ===================================
6087 01:22:25.155216 EX_ROW_EN[0] = 0x0
6088 01:22:25.158259 EX_ROW_EN[1] = 0x0
6089 01:22:25.158377 LP4Y_EN = 0x0
6090 01:22:25.161593 WORK_FSP = 0x0
6091 01:22:25.161726 WL = 0x2
6092 01:22:25.165333 RL = 0x2
6093 01:22:25.165448 BL = 0x2
6094 01:22:25.168465 RPST = 0x0
6095 01:22:25.168577 RD_PRE = 0x0
6096 01:22:25.171971 WR_PRE = 0x1
6097 01:22:25.172094 WR_PST = 0x0
6098 01:22:25.175003 DBI_WR = 0x0
6099 01:22:25.175114 DBI_RD = 0x0
6100 01:22:25.178459 OTF = 0x1
6101 01:22:25.181359 ===================================
6102 01:22:25.184883 ===================================
6103 01:22:25.185000 ANA top config
6104 01:22:25.187941 ===================================
6105 01:22:25.191818 DLL_ASYNC_EN = 0
6106 01:22:25.195026 ALL_SLAVE_EN = 1
6107 01:22:25.197999 NEW_RANK_MODE = 1
6108 01:22:25.198086 DLL_IDLE_MODE = 1
6109 01:22:25.201656 LP45_APHY_COMB_EN = 1
6110 01:22:25.204688 TX_ODT_DIS = 1
6111 01:22:25.208093 NEW_8X_MODE = 1
6112 01:22:25.211532 ===================================
6113 01:22:25.214605 ===================================
6114 01:22:25.218012 data_rate = 800
6115 01:22:25.218128 CKR = 1
6116 01:22:25.221256 DQ_P2S_RATIO = 4
6117 01:22:25.224432 ===================================
6118 01:22:25.227517 CA_P2S_RATIO = 4
6119 01:22:25.231260 DQ_CA_OPEN = 0
6120 01:22:25.234335 DQ_SEMI_OPEN = 1
6121 01:22:25.237458 CA_SEMI_OPEN = 1
6122 01:22:25.237566 CA_FULL_RATE = 0
6123 01:22:25.241289 DQ_CKDIV4_EN = 0
6124 01:22:25.244280 CA_CKDIV4_EN = 1
6125 01:22:25.247500 CA_PREDIV_EN = 0
6126 01:22:25.250551 PH8_DLY = 0
6127 01:22:25.254029 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6128 01:22:25.254114 DQ_AAMCK_DIV = 0
6129 01:22:25.257169 CA_AAMCK_DIV = 0
6130 01:22:25.260831 CA_ADMCK_DIV = 4
6131 01:22:25.263960 DQ_TRACK_CA_EN = 0
6132 01:22:25.267508 CA_PICK = 800
6133 01:22:25.270921 CA_MCKIO = 400
6134 01:22:25.273704 MCKIO_SEMI = 400
6135 01:22:25.277218 PLL_FREQ = 3016
6136 01:22:25.277304 DQ_UI_PI_RATIO = 32
6137 01:22:25.280609 CA_UI_PI_RATIO = 32
6138 01:22:25.283624 ===================================
6139 01:22:25.287281 ===================================
6140 01:22:25.290285 memory_type:LPDDR4
6141 01:22:25.293744 GP_NUM : 10
6142 01:22:25.293859 SRAM_EN : 1
6143 01:22:25.297011 MD32_EN : 0
6144 01:22:25.300107 ===================================
6145 01:22:25.303911 [ANA_INIT] >>>>>>>>>>>>>>
6146 01:22:25.303997 <<<<<< [CONFIGURE PHASE]: ANA_TX
6147 01:22:25.306992 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6148 01:22:25.310584 ===================================
6149 01:22:25.313629 data_rate = 800,PCW = 0X7400
6150 01:22:25.317253 ===================================
6151 01:22:25.320081 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6152 01:22:25.326946 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6153 01:22:25.337139 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6154 01:22:25.343795 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6155 01:22:25.347012 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6156 01:22:25.350134 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6157 01:22:25.350224 [ANA_INIT] flow start
6158 01:22:25.353924 [ANA_INIT] PLL >>>>>>>>
6159 01:22:25.356940 [ANA_INIT] PLL <<<<<<<<
6160 01:22:25.357046 [ANA_INIT] MIDPI >>>>>>>>
6161 01:22:25.360048 [ANA_INIT] MIDPI <<<<<<<<
6162 01:22:25.363417 [ANA_INIT] DLL >>>>>>>>
6163 01:22:25.363497 [ANA_INIT] flow end
6164 01:22:25.370177 ============ LP4 DIFF to SE enter ============
6165 01:22:25.373207 ============ LP4 DIFF to SE exit ============
6166 01:22:25.376814 [ANA_INIT] <<<<<<<<<<<<<
6167 01:22:25.380106 [Flow] Enable top DCM control >>>>>
6168 01:22:25.383498 [Flow] Enable top DCM control <<<<<
6169 01:22:25.386447 Enable DLL master slave shuffle
6170 01:22:25.389885 ==============================================================
6171 01:22:25.393295 Gating Mode config
6172 01:22:25.397048 ==============================================================
6173 01:22:25.400011 Config description:
6174 01:22:25.409816 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6175 01:22:25.416660 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6176 01:22:25.419733 SELPH_MODE 0: By rank 1: By Phase
6177 01:22:25.426512 ==============================================================
6178 01:22:25.430132 GAT_TRACK_EN = 0
6179 01:22:25.432976 RX_GATING_MODE = 2
6180 01:22:25.436370 RX_GATING_TRACK_MODE = 2
6181 01:22:25.439522 SELPH_MODE = 1
6182 01:22:25.442993 PICG_EARLY_EN = 1
6183 01:22:25.443114 VALID_LAT_VALUE = 1
6184 01:22:25.449821 ==============================================================
6185 01:22:25.452846 Enter into Gating configuration >>>>
6186 01:22:25.456371 Exit from Gating configuration <<<<
6187 01:22:25.459461 Enter into DVFS_PRE_config >>>>>
6188 01:22:25.469689 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6189 01:22:25.472846 Exit from DVFS_PRE_config <<<<<
6190 01:22:25.476038 Enter into PICG configuration >>>>
6191 01:22:25.479701 Exit from PICG configuration <<<<
6192 01:22:25.482762 [RX_INPUT] configuration >>>>>
6193 01:22:25.486316 [RX_INPUT] configuration <<<<<
6194 01:22:25.492504 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6195 01:22:25.495829 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6196 01:22:25.502518 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6197 01:22:25.509438 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6198 01:22:25.516145 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6199 01:22:25.522991 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6200 01:22:25.526143 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6201 01:22:25.529218 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6202 01:22:25.532292 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6203 01:22:25.539341 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6204 01:22:25.542709 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6205 01:22:25.545648 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6206 01:22:25.549285 ===================================
6207 01:22:25.552403 LPDDR4 DRAM CONFIGURATION
6208 01:22:25.555434 ===================================
6209 01:22:25.555517 EX_ROW_EN[0] = 0x0
6210 01:22:25.558713 EX_ROW_EN[1] = 0x0
6211 01:22:25.562458 LP4Y_EN = 0x0
6212 01:22:25.562541 WORK_FSP = 0x0
6213 01:22:25.565568 WL = 0x2
6214 01:22:25.565656 RL = 0x2
6215 01:22:25.568719 BL = 0x2
6216 01:22:25.568828 RPST = 0x0
6217 01:22:25.572383 RD_PRE = 0x0
6218 01:22:25.572512 WR_PRE = 0x1
6219 01:22:25.575459 WR_PST = 0x0
6220 01:22:25.575547 DBI_WR = 0x0
6221 01:22:25.578706 DBI_RD = 0x0
6222 01:22:25.578790 OTF = 0x1
6223 01:22:25.582350 ===================================
6224 01:22:25.585426 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6225 01:22:25.592092 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6226 01:22:25.595586 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6227 01:22:25.598687 ===================================
6228 01:22:25.601970 LPDDR4 DRAM CONFIGURATION
6229 01:22:25.605373 ===================================
6230 01:22:25.605515 EX_ROW_EN[0] = 0x10
6231 01:22:25.608809 EX_ROW_EN[1] = 0x0
6232 01:22:25.608935 LP4Y_EN = 0x0
6233 01:22:25.612242 WORK_FSP = 0x0
6234 01:22:25.612369 WL = 0x2
6235 01:22:25.615302 RL = 0x2
6236 01:22:25.618586 BL = 0x2
6237 01:22:25.618681 RPST = 0x0
6238 01:22:25.622028 RD_PRE = 0x0
6239 01:22:25.622154 WR_PRE = 0x1
6240 01:22:25.625368 WR_PST = 0x0
6241 01:22:25.625495 DBI_WR = 0x0
6242 01:22:25.628505 DBI_RD = 0x0
6243 01:22:25.628616 OTF = 0x1
6244 01:22:25.632189 ===================================
6245 01:22:25.638341 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6246 01:22:25.642555 nWR fixed to 30
6247 01:22:25.646077 [ModeRegInit_LP4] CH0 RK0
6248 01:22:25.646172 [ModeRegInit_LP4] CH0 RK1
6249 01:22:25.649356 [ModeRegInit_LP4] CH1 RK0
6250 01:22:25.652490 [ModeRegInit_LP4] CH1 RK1
6251 01:22:25.652602 match AC timing 19
6252 01:22:25.658821 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6253 01:22:25.662229 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6254 01:22:25.665990 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6255 01:22:25.672173 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6256 01:22:25.675481 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6257 01:22:25.675576 ==
6258 01:22:25.679102 Dram Type= 6, Freq= 0, CH_0, rank 0
6259 01:22:25.682272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6260 01:22:25.682404 ==
6261 01:22:25.689131 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6262 01:22:25.695297 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6263 01:22:25.698772 [CA 0] Center 36 (8~64) winsize 57
6264 01:22:25.702360 [CA 1] Center 36 (8~64) winsize 57
6265 01:22:25.705419 [CA 2] Center 36 (8~64) winsize 57
6266 01:22:25.708579 [CA 3] Center 36 (8~64) winsize 57
6267 01:22:25.708703 [CA 4] Center 36 (8~64) winsize 57
6268 01:22:25.712177 [CA 5] Center 36 (8~64) winsize 57
6269 01:22:25.712296
6270 01:22:25.718772 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6271 01:22:25.718904
6272 01:22:25.721739 [CATrainingPosCal] consider 1 rank data
6273 01:22:25.725016 u2DelayCellTimex100 = 270/100 ps
6274 01:22:25.728381 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 01:22:25.731825 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 01:22:25.735268 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 01:22:25.738537 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 01:22:25.742067 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 01:22:25.744771 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 01:22:25.744873
6281 01:22:25.748540 CA PerBit enable=1, Macro0, CA PI delay=36
6282 01:22:25.748631
6283 01:22:25.751556 [CBTSetCACLKResult] CA Dly = 36
6284 01:22:25.755247 CS Dly: 1 (0~32)
6285 01:22:25.755340 ==
6286 01:22:25.758240 Dram Type= 6, Freq= 0, CH_0, rank 1
6287 01:22:25.761697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 01:22:25.761816 ==
6289 01:22:25.767908 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6290 01:22:25.775004 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6291 01:22:25.778111 [CA 0] Center 36 (8~64) winsize 57
6292 01:22:25.781278 [CA 1] Center 36 (8~64) winsize 57
6293 01:22:25.784330 [CA 2] Center 36 (8~64) winsize 57
6294 01:22:25.784422 [CA 3] Center 36 (8~64) winsize 57
6295 01:22:25.788028 [CA 4] Center 36 (8~64) winsize 57
6296 01:22:25.791082 [CA 5] Center 36 (8~64) winsize 57
6297 01:22:25.791173
6298 01:22:25.794816 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6299 01:22:25.797981
6300 01:22:25.801055 [CATrainingPosCal] consider 2 rank data
6301 01:22:25.801144 u2DelayCellTimex100 = 270/100 ps
6302 01:22:25.807522 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 01:22:25.811292 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 01:22:25.814419 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 01:22:25.817520 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 01:22:25.821167 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 01:22:25.824219 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 01:22:25.824347
6309 01:22:25.827281 CA PerBit enable=1, Macro0, CA PI delay=36
6310 01:22:25.827380
6311 01:22:25.830836 [CBTSetCACLKResult] CA Dly = 36
6312 01:22:25.833964 CS Dly: 1 (0~32)
6313 01:22:25.834071
6314 01:22:25.837240 ----->DramcWriteLeveling(PI) begin...
6315 01:22:25.837332 ==
6316 01:22:25.840840 Dram Type= 6, Freq= 0, CH_0, rank 0
6317 01:22:25.843723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6318 01:22:25.843836 ==
6319 01:22:25.847360 Write leveling (Byte 0): 40 => 8
6320 01:22:25.850710 Write leveling (Byte 1): 40 => 8
6321 01:22:25.853772 DramcWriteLeveling(PI) end<-----
6322 01:22:25.853892
6323 01:22:25.853996 ==
6324 01:22:25.857422 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 01:22:25.860492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 01:22:25.860625 ==
6327 01:22:25.863621 [Gating] SW mode calibration
6328 01:22:25.870433 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6329 01:22:25.876971 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6330 01:22:25.880359 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6331 01:22:25.883569 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6332 01:22:25.890299 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6333 01:22:25.893398 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6334 01:22:25.897174 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6335 01:22:25.903412 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6336 01:22:25.907016 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6337 01:22:25.909985 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6338 01:22:25.916522 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6339 01:22:25.920132 Total UI for P1: 0, mck2ui 16
6340 01:22:25.923186 best dqsien dly found for B0: ( 0, 14, 24)
6341 01:22:25.926325 Total UI for P1: 0, mck2ui 16
6342 01:22:25.930185 best dqsien dly found for B1: ( 0, 14, 24)
6343 01:22:25.933110 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6344 01:22:25.936760 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6345 01:22:25.936868
6346 01:22:25.939645 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6347 01:22:25.942803 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6348 01:22:25.946466 [Gating] SW calibration Done
6349 01:22:25.946559 ==
6350 01:22:25.949524 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 01:22:25.952653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 01:22:25.952736 ==
6353 01:22:25.956278 RX Vref Scan: 0
6354 01:22:25.956396
6355 01:22:25.959220 RX Vref 0 -> 0, step: 1
6356 01:22:25.959323
6357 01:22:25.962530 RX Delay -410 -> 252, step: 16
6358 01:22:25.966125 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6359 01:22:25.968989 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6360 01:22:25.972745 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6361 01:22:25.979390 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6362 01:22:25.982400 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6363 01:22:25.985841 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6364 01:22:25.989265 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6365 01:22:25.996028 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6366 01:22:25.999024 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6367 01:22:26.002284 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6368 01:22:26.005974 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6369 01:22:26.012356 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6370 01:22:26.015354 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6371 01:22:26.019084 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6372 01:22:26.025651 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6373 01:22:26.028764 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6374 01:22:26.028855 ==
6375 01:22:26.031935 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 01:22:26.035500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 01:22:26.035592 ==
6378 01:22:26.038488 DQS Delay:
6379 01:22:26.038600 DQS0 = 59, DQS1 = 59
6380 01:22:26.038696 DQM Delay:
6381 01:22:26.042045 DQM0 = 18, DQM1 = 10
6382 01:22:26.042147 DQ Delay:
6383 01:22:26.045108 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6384 01:22:26.048704 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6385 01:22:26.051728 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6386 01:22:26.054818 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6387 01:22:26.054948
6388 01:22:26.055049
6389 01:22:26.055149 ==
6390 01:22:26.058334 Dram Type= 6, Freq= 0, CH_0, rank 0
6391 01:22:26.065378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6392 01:22:26.065476 ==
6393 01:22:26.065572
6394 01:22:26.065637
6395 01:22:26.065697 TX Vref Scan disable
6396 01:22:26.068355 == TX Byte 0 ==
6397 01:22:26.071747 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6398 01:22:26.074864 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6399 01:22:26.078435 == TX Byte 1 ==
6400 01:22:26.081212 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6401 01:22:26.084640 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6402 01:22:26.084760 ==
6403 01:22:26.087882 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 01:22:26.094850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 01:22:26.094957 ==
6406 01:22:26.095061
6407 01:22:26.095160
6408 01:22:26.095258 TX Vref Scan disable
6409 01:22:26.097832 == TX Byte 0 ==
6410 01:22:26.101363 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6411 01:22:26.104661 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6412 01:22:26.107646 == TX Byte 1 ==
6413 01:22:26.110988 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6414 01:22:26.114782 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6415 01:22:26.114868
6416 01:22:26.117777 [DATLAT]
6417 01:22:26.117855 Freq=400, CH0 RK0
6418 01:22:26.117923
6419 01:22:26.121369 DATLAT Default: 0xf
6420 01:22:26.121472 0, 0xFFFF, sum = 0
6421 01:22:26.124606 1, 0xFFFF, sum = 0
6422 01:22:26.124724 2, 0xFFFF, sum = 0
6423 01:22:26.127524 3, 0xFFFF, sum = 0
6424 01:22:26.127605 4, 0xFFFF, sum = 0
6425 01:22:26.130928 5, 0xFFFF, sum = 0
6426 01:22:26.131039 6, 0xFFFF, sum = 0
6427 01:22:26.134616 7, 0xFFFF, sum = 0
6428 01:22:26.134727 8, 0xFFFF, sum = 0
6429 01:22:26.137782 9, 0xFFFF, sum = 0
6430 01:22:26.140691 10, 0xFFFF, sum = 0
6431 01:22:26.140804 11, 0xFFFF, sum = 0
6432 01:22:26.143903 12, 0xFFFF, sum = 0
6433 01:22:26.143996 13, 0x0, sum = 1
6434 01:22:26.147241 14, 0x0, sum = 2
6435 01:22:26.147357 15, 0x0, sum = 3
6436 01:22:26.150821 16, 0x0, sum = 4
6437 01:22:26.150939 best_step = 14
6438 01:22:26.151010
6439 01:22:26.151073 ==
6440 01:22:26.154414 Dram Type= 6, Freq= 0, CH_0, rank 0
6441 01:22:26.157244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 01:22:26.157359 ==
6443 01:22:26.160429 RX Vref Scan: 1
6444 01:22:26.160542
6445 01:22:26.164243 RX Vref 0 -> 0, step: 1
6446 01:22:26.164331
6447 01:22:26.164399 RX Delay -359 -> 252, step: 8
6448 01:22:26.167442
6449 01:22:26.167528 Set Vref, RX VrefLevel [Byte0]: 62
6450 01:22:26.170512 [Byte1]: 47
6451 01:22:26.176219
6452 01:22:26.176338 Final RX Vref Byte 0 = 62 to rank0
6453 01:22:26.179775 Final RX Vref Byte 1 = 47 to rank0
6454 01:22:26.182622 Final RX Vref Byte 0 = 62 to rank1
6455 01:22:26.185968 Final RX Vref Byte 1 = 47 to rank1==
6456 01:22:26.189248 Dram Type= 6, Freq= 0, CH_0, rank 0
6457 01:22:26.196076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6458 01:22:26.196174 ==
6459 01:22:26.196242 DQS Delay:
6460 01:22:26.199859 DQS0 = 60, DQS1 = 68
6461 01:22:26.199948 DQM Delay:
6462 01:22:26.200017 DQM0 = 14, DQM1 = 14
6463 01:22:26.202890 DQ Delay:
6464 01:22:26.205986 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6465 01:22:26.209421 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6466 01:22:26.209544 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6467 01:22:26.212908 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6468 01:22:26.216430
6469 01:22:26.216514
6470 01:22:26.222804 [DQSOSCAuto] RK0, (LSB)MR18= 0x7f7e, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6471 01:22:26.225701 CH0 RK0: MR19=C0C, MR18=7F7E
6472 01:22:26.232727 CH0_RK0: MR19=0xC0C, MR18=0x7F7E, DQSOSC=393, MR23=63, INC=382, DEC=254
6473 01:22:26.232858 ==
6474 01:22:26.235595 Dram Type= 6, Freq= 0, CH_0, rank 1
6475 01:22:26.239369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 01:22:26.239461 ==
6477 01:22:26.242451 [Gating] SW mode calibration
6478 01:22:26.249229 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6479 01:22:26.255622 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6480 01:22:26.259118 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6481 01:22:26.262599 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6482 01:22:26.269278 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6483 01:22:26.272280 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6484 01:22:26.275552 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6485 01:22:26.282134 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6486 01:22:26.286034 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6487 01:22:26.289165 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6488 01:22:26.295609 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6489 01:22:26.295707 Total UI for P1: 0, mck2ui 16
6490 01:22:26.302583 best dqsien dly found for B0: ( 0, 14, 24)
6491 01:22:26.302681 Total UI for P1: 0, mck2ui 16
6492 01:22:26.305473 best dqsien dly found for B1: ( 0, 14, 24)
6493 01:22:26.312376 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6494 01:22:26.315444 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6495 01:22:26.315529
6496 01:22:26.318575 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6497 01:22:26.321946 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6498 01:22:26.325279 [Gating] SW calibration Done
6499 01:22:26.325391 ==
6500 01:22:26.329135 Dram Type= 6, Freq= 0, CH_0, rank 1
6501 01:22:26.332132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 01:22:26.332249 ==
6503 01:22:26.335609 RX Vref Scan: 0
6504 01:22:26.335726
6505 01:22:26.335836 RX Vref 0 -> 0, step: 1
6506 01:22:26.335943
6507 01:22:26.339050 RX Delay -410 -> 252, step: 16
6508 01:22:26.345106 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6509 01:22:26.349007 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6510 01:22:26.351941 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6511 01:22:26.355126 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6512 01:22:26.358831 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6513 01:22:26.365294 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6514 01:22:26.368740 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6515 01:22:26.371690 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6516 01:22:26.378488 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6517 01:22:26.381673 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6518 01:22:26.384662 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6519 01:22:26.387939 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6520 01:22:26.394812 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6521 01:22:26.397989 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6522 01:22:26.401470 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6523 01:22:26.404764 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6524 01:22:26.408270 ==
6525 01:22:26.411673 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 01:22:26.414874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 01:22:26.415013 ==
6528 01:22:26.415127 DQS Delay:
6529 01:22:26.418058 DQS0 = 59, DQS1 = 59
6530 01:22:26.418167 DQM Delay:
6531 01:22:26.421093 DQM0 = 16, DQM1 = 10
6532 01:22:26.421199 DQ Delay:
6533 01:22:26.424656 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6534 01:22:26.427660 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6535 01:22:26.431281 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6536 01:22:26.434670 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6537 01:22:26.434783
6538 01:22:26.434897
6539 01:22:26.435001 ==
6540 01:22:26.437620 Dram Type= 6, Freq= 0, CH_0, rank 1
6541 01:22:26.441002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6542 01:22:26.441126 ==
6543 01:22:26.441243
6544 01:22:26.441340
6545 01:22:26.444278 TX Vref Scan disable
6546 01:22:26.444407 == TX Byte 0 ==
6547 01:22:26.451253 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6548 01:22:26.454399 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6549 01:22:26.454490 == TX Byte 1 ==
6550 01:22:26.461088 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6551 01:22:26.464537 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6552 01:22:26.464656 ==
6553 01:22:26.467625 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 01:22:26.470787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 01:22:26.470878 ==
6556 01:22:26.470947
6557 01:22:26.471009
6558 01:22:26.474011 TX Vref Scan disable
6559 01:22:26.477465 == TX Byte 0 ==
6560 01:22:26.480798 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6561 01:22:26.484152 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6562 01:22:26.484243 == TX Byte 1 ==
6563 01:22:26.490907 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6564 01:22:26.494203 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6565 01:22:26.494288
6566 01:22:26.494353 [DATLAT]
6567 01:22:26.497329 Freq=400, CH0 RK1
6568 01:22:26.497403
6569 01:22:26.497464 DATLAT Default: 0xe
6570 01:22:26.500588 0, 0xFFFF, sum = 0
6571 01:22:26.500704 1, 0xFFFF, sum = 0
6572 01:22:26.503750 2, 0xFFFF, sum = 0
6573 01:22:26.507487 3, 0xFFFF, sum = 0
6574 01:22:26.507573 4, 0xFFFF, sum = 0
6575 01:22:26.510511 5, 0xFFFF, sum = 0
6576 01:22:26.510591 6, 0xFFFF, sum = 0
6577 01:22:26.514020 7, 0xFFFF, sum = 0
6578 01:22:26.514109 8, 0xFFFF, sum = 0
6579 01:22:26.517113 9, 0xFFFF, sum = 0
6580 01:22:26.517203 10, 0xFFFF, sum = 0
6581 01:22:26.520490 11, 0xFFFF, sum = 0
6582 01:22:26.520582 12, 0xFFFF, sum = 0
6583 01:22:26.523444 13, 0x0, sum = 1
6584 01:22:26.523533 14, 0x0, sum = 2
6585 01:22:26.527036 15, 0x0, sum = 3
6586 01:22:26.527124 16, 0x0, sum = 4
6587 01:22:26.530215 best_step = 14
6588 01:22:26.530330
6589 01:22:26.530425 ==
6590 01:22:26.533407 Dram Type= 6, Freq= 0, CH_0, rank 1
6591 01:22:26.536575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6592 01:22:26.536675 ==
6593 01:22:26.540138 RX Vref Scan: 0
6594 01:22:26.540226
6595 01:22:26.540294 RX Vref 0 -> 0, step: 1
6596 01:22:26.540358
6597 01:22:26.543434 RX Delay -359 -> 252, step: 8
6598 01:22:26.551392 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6599 01:22:26.554518 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6600 01:22:26.557908 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6601 01:22:26.561195 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6602 01:22:26.567725 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6603 01:22:26.570794 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6604 01:22:26.574032 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6605 01:22:26.577312 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6606 01:22:26.584232 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6607 01:22:26.587605 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6608 01:22:26.590860 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6609 01:22:26.597602 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6610 01:22:26.600740 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6611 01:22:26.603735 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6612 01:22:26.607517 iDelay=217, Bit 14, Center -48 (-295 ~ 200) 496
6613 01:22:26.613852 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6614 01:22:26.613973 ==
6615 01:22:26.616992 Dram Type= 6, Freq= 0, CH_0, rank 1
6616 01:22:26.620558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6617 01:22:26.620653 ==
6618 01:22:26.620723 DQS Delay:
6619 01:22:26.624099 DQS0 = 60, DQS1 = 72
6620 01:22:26.624212 DQM Delay:
6621 01:22:26.627338 DQM0 = 11, DQM1 = 16
6622 01:22:26.627425 DQ Delay:
6623 01:22:26.630617 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6624 01:22:26.633686 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6625 01:22:26.637204 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6626 01:22:26.640390 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6627 01:22:26.640493
6628 01:22:26.640569
6629 01:22:26.647316 [DQSOSCAuto] RK1, (LSB)MR18= 0xc379, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6630 01:22:26.650330 CH0 RK1: MR19=C0C, MR18=C379
6631 01:22:26.656672 CH0_RK1: MR19=0xC0C, MR18=0xC379, DQSOSC=385, MR23=63, INC=398, DEC=265
6632 01:22:26.660435 [RxdqsGatingPostProcess] freq 400
6633 01:22:26.666596 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6634 01:22:26.670278 best DQS0 dly(2T, 0.5T) = (0, 10)
6635 01:22:26.673487 best DQS1 dly(2T, 0.5T) = (0, 10)
6636 01:22:26.676855 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6637 01:22:26.680358 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6638 01:22:26.680457 best DQS0 dly(2T, 0.5T) = (0, 10)
6639 01:22:26.683496 best DQS1 dly(2T, 0.5T) = (0, 10)
6640 01:22:26.686557 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6641 01:22:26.689706 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6642 01:22:26.693403 Pre-setting of DQS Precalculation
6643 01:22:26.699854 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6644 01:22:26.699976 ==
6645 01:22:26.703520 Dram Type= 6, Freq= 0, CH_1, rank 0
6646 01:22:26.706650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6647 01:22:26.706738 ==
6648 01:22:26.712963 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6649 01:22:26.719735 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6650 01:22:26.722971 [CA 0] Center 36 (8~64) winsize 57
6651 01:22:26.723087 [CA 1] Center 36 (8~64) winsize 57
6652 01:22:26.726727 [CA 2] Center 36 (8~64) winsize 57
6653 01:22:26.729679 [CA 3] Center 36 (8~64) winsize 57
6654 01:22:26.732675 [CA 4] Center 36 (8~64) winsize 57
6655 01:22:26.736110 [CA 5] Center 36 (8~64) winsize 57
6656 01:22:26.736230
6657 01:22:26.739458 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6658 01:22:26.739556
6659 01:22:26.742936 [CATrainingPosCal] consider 1 rank data
6660 01:22:26.746036 u2DelayCellTimex100 = 270/100 ps
6661 01:22:26.749745 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 01:22:26.756006 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 01:22:26.759615 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 01:22:26.762438 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 01:22:26.766277 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 01:22:26.769322 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 01:22:26.769431
6668 01:22:26.772717 CA PerBit enable=1, Macro0, CA PI delay=36
6669 01:22:26.772844
6670 01:22:26.775560 [CBTSetCACLKResult] CA Dly = 36
6671 01:22:26.779100 CS Dly: 1 (0~32)
6672 01:22:26.779217 ==
6673 01:22:26.782328 Dram Type= 6, Freq= 0, CH_1, rank 1
6674 01:22:26.785900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 01:22:26.786020 ==
6676 01:22:26.792457 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6677 01:22:26.796104 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6678 01:22:26.799279 [CA 0] Center 36 (8~64) winsize 57
6679 01:22:26.802368 [CA 1] Center 36 (8~64) winsize 57
6680 01:22:26.805956 [CA 2] Center 36 (8~64) winsize 57
6681 01:22:26.808824 [CA 3] Center 36 (8~64) winsize 57
6682 01:22:26.812560 [CA 4] Center 36 (8~64) winsize 57
6683 01:22:26.815787 [CA 5] Center 36 (8~64) winsize 57
6684 01:22:26.815910
6685 01:22:26.818990 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6686 01:22:26.819103
6687 01:22:26.822238 [CATrainingPosCal] consider 2 rank data
6688 01:22:26.825306 u2DelayCellTimex100 = 270/100 ps
6689 01:22:26.829219 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 01:22:26.832143 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 01:22:26.835276 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 01:22:26.842117 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 01:22:26.845601 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 01:22:26.848388 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 01:22:26.848504
6696 01:22:26.851827 CA PerBit enable=1, Macro0, CA PI delay=36
6697 01:22:26.851941
6698 01:22:26.855534 [CBTSetCACLKResult] CA Dly = 36
6699 01:22:26.855650 CS Dly: 1 (0~32)
6700 01:22:26.855758
6701 01:22:26.858655 ----->DramcWriteLeveling(PI) begin...
6702 01:22:26.858763 ==
6703 01:22:26.862139 Dram Type= 6, Freq= 0, CH_1, rank 0
6704 01:22:26.868539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6705 01:22:26.868664 ==
6706 01:22:26.871792 Write leveling (Byte 0): 40 => 8
6707 01:22:26.875455 Write leveling (Byte 1): 40 => 8
6708 01:22:26.875564 DramcWriteLeveling(PI) end<-----
6709 01:22:26.875676
6710 01:22:26.878473 ==
6711 01:22:26.882222 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 01:22:26.885191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 01:22:26.885305 ==
6714 01:22:26.888595 [Gating] SW mode calibration
6715 01:22:26.895449 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6716 01:22:26.898835 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6717 01:22:26.905146 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6718 01:22:26.908439 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6719 01:22:26.912074 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6720 01:22:26.918357 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6721 01:22:26.921529 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6722 01:22:26.925346 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6723 01:22:26.931430 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6724 01:22:26.935340 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6725 01:22:26.938339 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6726 01:22:26.941289 Total UI for P1: 0, mck2ui 16
6727 01:22:26.945151 best dqsien dly found for B0: ( 0, 14, 24)
6728 01:22:26.948380 Total UI for P1: 0, mck2ui 16
6729 01:22:26.951486 best dqsien dly found for B1: ( 0, 14, 24)
6730 01:22:26.954581 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6731 01:22:26.957877 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6732 01:22:26.957959
6733 01:22:26.964529 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6734 01:22:26.968215 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6735 01:22:26.971461 [Gating] SW calibration Done
6736 01:22:26.971548 ==
6737 01:22:26.974303 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 01:22:26.978103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 01:22:26.978191 ==
6740 01:22:26.978258 RX Vref Scan: 0
6741 01:22:26.978321
6742 01:22:26.981145 RX Vref 0 -> 0, step: 1
6743 01:22:26.981227
6744 01:22:26.984756 RX Delay -410 -> 252, step: 16
6745 01:22:26.987938 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6746 01:22:26.994220 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6747 01:22:26.997970 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6748 01:22:27.001041 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6749 01:22:27.004697 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6750 01:22:27.011153 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6751 01:22:27.014574 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6752 01:22:27.017871 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6753 01:22:27.021142 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6754 01:22:27.027718 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6755 01:22:27.030940 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6756 01:22:27.034423 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6757 01:22:27.037502 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6758 01:22:27.044073 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6759 01:22:27.047797 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6760 01:22:27.051144 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6761 01:22:27.051230 ==
6762 01:22:27.054214 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 01:22:27.057802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 01:22:27.060900 ==
6765 01:22:27.060982 DQS Delay:
6766 01:22:27.061050 DQS0 = 51, DQS1 = 67
6767 01:22:27.063764 DQM Delay:
6768 01:22:27.063841 DQM0 = 13, DQM1 = 20
6769 01:22:27.067155 DQ Delay:
6770 01:22:27.071003 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6771 01:22:27.071098 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6772 01:22:27.074548 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6773 01:22:27.077364 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =32
6774 01:22:27.077475
6775 01:22:27.077565
6776 01:22:27.080551 ==
6777 01:22:27.084222 Dram Type= 6, Freq= 0, CH_1, rank 0
6778 01:22:27.087049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6779 01:22:27.087136 ==
6780 01:22:27.087203
6781 01:22:27.087266
6782 01:22:27.090671 TX Vref Scan disable
6783 01:22:27.090755 == TX Byte 0 ==
6784 01:22:27.093814 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6785 01:22:27.100708 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6786 01:22:27.100801 == TX Byte 1 ==
6787 01:22:27.104014 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6788 01:22:27.110205 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6789 01:22:27.110291 ==
6790 01:22:27.113805 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 01:22:27.116695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 01:22:27.116782 ==
6793 01:22:27.116851
6794 01:22:27.116913
6795 01:22:27.120347 TX Vref Scan disable
6796 01:22:27.120434 == TX Byte 0 ==
6797 01:22:27.126639 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6798 01:22:27.129586 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6799 01:22:27.129676 == TX Byte 1 ==
6800 01:22:27.136404 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6801 01:22:27.140021 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6802 01:22:27.140142
6803 01:22:27.140242 [DATLAT]
6804 01:22:27.143013 Freq=400, CH1 RK0
6805 01:22:27.143103
6806 01:22:27.143171 DATLAT Default: 0xf
6807 01:22:27.146256 0, 0xFFFF, sum = 0
6808 01:22:27.146348 1, 0xFFFF, sum = 0
6809 01:22:27.149953 2, 0xFFFF, sum = 0
6810 01:22:27.150042 3, 0xFFFF, sum = 0
6811 01:22:27.153084 4, 0xFFFF, sum = 0
6812 01:22:27.153197 5, 0xFFFF, sum = 0
6813 01:22:27.156224 6, 0xFFFF, sum = 0
6814 01:22:27.156312 7, 0xFFFF, sum = 0
6815 01:22:27.159569 8, 0xFFFF, sum = 0
6816 01:22:27.159658 9, 0xFFFF, sum = 0
6817 01:22:27.163326 10, 0xFFFF, sum = 0
6818 01:22:27.166331 11, 0xFFFF, sum = 0
6819 01:22:27.166419 12, 0xFFFF, sum = 0
6820 01:22:27.169476 13, 0x0, sum = 1
6821 01:22:27.169575 14, 0x0, sum = 2
6822 01:22:27.169644 15, 0x0, sum = 3
6823 01:22:27.173102 16, 0x0, sum = 4
6824 01:22:27.173189 best_step = 14
6825 01:22:27.173257
6826 01:22:27.176039 ==
6827 01:22:27.179355 Dram Type= 6, Freq= 0, CH_1, rank 0
6828 01:22:27.182635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 01:22:27.182748 ==
6830 01:22:27.182856 RX Vref Scan: 1
6831 01:22:27.182925
6832 01:22:27.185745 RX Vref 0 -> 0, step: 1
6833 01:22:27.185849
6834 01:22:27.189583 RX Delay -375 -> 252, step: 8
6835 01:22:27.189711
6836 01:22:27.192590 Set Vref, RX VrefLevel [Byte0]: 54
6837 01:22:27.195714 [Byte1]: 48
6838 01:22:27.199463
6839 01:22:27.199554 Final RX Vref Byte 0 = 54 to rank0
6840 01:22:27.203089 Final RX Vref Byte 1 = 48 to rank0
6841 01:22:27.206269 Final RX Vref Byte 0 = 54 to rank1
6842 01:22:27.209391 Final RX Vref Byte 1 = 48 to rank1==
6843 01:22:27.213111 Dram Type= 6, Freq= 0, CH_1, rank 0
6844 01:22:27.219706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6845 01:22:27.219825 ==
6846 01:22:27.219923 DQS Delay:
6847 01:22:27.220016 DQS0 = 52, DQS1 = 68
6848 01:22:27.222719 DQM Delay:
6849 01:22:27.222830 DQM0 = 9, DQM1 = 14
6850 01:22:27.226348 DQ Delay:
6851 01:22:27.226463 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6852 01:22:27.229558 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
6853 01:22:27.232736 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6854 01:22:27.235992 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6855 01:22:27.236094
6856 01:22:27.236162
6857 01:22:27.246194 [DQSOSCAuto] RK0, (LSB)MR18= 0x5366, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
6858 01:22:27.249730 CH1 RK0: MR19=C0C, MR18=5366
6859 01:22:27.255895 CH1_RK0: MR19=0xC0C, MR18=0x5366, DQSOSC=396, MR23=63, INC=376, DEC=251
6860 01:22:27.256041 ==
6861 01:22:27.259311 Dram Type= 6, Freq= 0, CH_1, rank 1
6862 01:22:27.262380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 01:22:27.262468 ==
6864 01:22:27.266236 [Gating] SW mode calibration
6865 01:22:27.272619 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6866 01:22:27.279317 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6867 01:22:27.282443 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6868 01:22:27.286009 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6869 01:22:27.288971 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6870 01:22:27.296118 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6871 01:22:27.299320 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6872 01:22:27.302110 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6873 01:22:27.309057 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6874 01:22:27.312560 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6875 01:22:27.315685 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6876 01:22:27.318873 Total UI for P1: 0, mck2ui 16
6877 01:22:27.321940 best dqsien dly found for B0: ( 0, 14, 24)
6878 01:22:27.325563 Total UI for P1: 0, mck2ui 16
6879 01:22:27.329138 best dqsien dly found for B1: ( 0, 14, 24)
6880 01:22:27.332273 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6881 01:22:27.339026 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6882 01:22:27.339122
6883 01:22:27.342365 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6884 01:22:27.345318 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6885 01:22:27.349060 [Gating] SW calibration Done
6886 01:22:27.349156 ==
6887 01:22:27.351922 Dram Type= 6, Freq= 0, CH_1, rank 1
6888 01:22:27.355542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 01:22:27.355633 ==
6890 01:22:27.358590 RX Vref Scan: 0
6891 01:22:27.358675
6892 01:22:27.358743 RX Vref 0 -> 0, step: 1
6893 01:22:27.358807
6894 01:22:27.361882 RX Delay -410 -> 252, step: 16
6895 01:22:27.365055 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6896 01:22:27.371818 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6897 01:22:27.375740 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6898 01:22:27.378590 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6899 01:22:27.381865 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6900 01:22:27.388269 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6901 01:22:27.392002 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6902 01:22:27.395085 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6903 01:22:27.398382 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6904 01:22:27.404915 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6905 01:22:27.408557 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6906 01:22:27.412003 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6907 01:22:27.414911 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6908 01:22:27.421536 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6909 01:22:27.424864 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6910 01:22:27.428378 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6911 01:22:27.428462 ==
6912 01:22:27.431930 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 01:22:27.438387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 01:22:27.438486 ==
6915 01:22:27.438557 DQS Delay:
6916 01:22:27.441944 DQS0 = 59, DQS1 = 59
6917 01:22:27.442028 DQM Delay:
6918 01:22:27.442097 DQM0 = 19, DQM1 = 12
6919 01:22:27.445146 DQ Delay:
6920 01:22:27.448112 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6921 01:22:27.451417 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6922 01:22:27.451501 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6923 01:22:27.458114 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6924 01:22:27.458201
6925 01:22:27.458273
6926 01:22:27.458356 ==
6927 01:22:27.461258 Dram Type= 6, Freq= 0, CH_1, rank 1
6928 01:22:27.464825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6929 01:22:27.464932 ==
6930 01:22:27.465026
6931 01:22:27.465090
6932 01:22:27.468115 TX Vref Scan disable
6933 01:22:27.468192 == TX Byte 0 ==
6934 01:22:27.471734 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6935 01:22:27.477966 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6936 01:22:27.478079 == TX Byte 1 ==
6937 01:22:27.481058 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6938 01:22:27.487651 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6939 01:22:27.487746 ==
6940 01:22:27.491070 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 01:22:27.494315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 01:22:27.494404 ==
6943 01:22:27.494482
6944 01:22:27.494547
6945 01:22:27.497744 TX Vref Scan disable
6946 01:22:27.497852 == TX Byte 0 ==
6947 01:22:27.504423 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6948 01:22:27.507816 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6949 01:22:27.507937 == TX Byte 1 ==
6950 01:22:27.514609 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6951 01:22:27.517783 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6952 01:22:27.517895
6953 01:22:27.517989 [DATLAT]
6954 01:22:27.520741 Freq=400, CH1 RK1
6955 01:22:27.520828
6956 01:22:27.520896 DATLAT Default: 0xe
6957 01:22:27.524518 0, 0xFFFF, sum = 0
6958 01:22:27.524597 1, 0xFFFF, sum = 0
6959 01:22:27.527556 2, 0xFFFF, sum = 0
6960 01:22:27.527647 3, 0xFFFF, sum = 0
6961 01:22:27.531102 4, 0xFFFF, sum = 0
6962 01:22:27.531197 5, 0xFFFF, sum = 0
6963 01:22:27.534119 6, 0xFFFF, sum = 0
6964 01:22:27.534234 7, 0xFFFF, sum = 0
6965 01:22:27.537580 8, 0xFFFF, sum = 0
6966 01:22:27.537668 9, 0xFFFF, sum = 0
6967 01:22:27.541200 10, 0xFFFF, sum = 0
6968 01:22:27.541319 11, 0xFFFF, sum = 0
6969 01:22:27.544124 12, 0xFFFF, sum = 0
6970 01:22:27.544245 13, 0x0, sum = 1
6971 01:22:27.547326 14, 0x0, sum = 2
6972 01:22:27.547418 15, 0x0, sum = 3
6973 01:22:27.551086 16, 0x0, sum = 4
6974 01:22:27.551202 best_step = 14
6975 01:22:27.551301
6976 01:22:27.551398 ==
6977 01:22:27.554091 Dram Type= 6, Freq= 0, CH_1, rank 1
6978 01:22:27.560966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6979 01:22:27.561057 ==
6980 01:22:27.561125 RX Vref Scan: 0
6981 01:22:27.561189
6982 01:22:27.563892 RX Vref 0 -> 0, step: 1
6983 01:22:27.563978
6984 01:22:27.567076 RX Delay -359 -> 252, step: 8
6985 01:22:27.574041 iDelay=217, Bit 0, Center -40 (-287 ~ 208) 496
6986 01:22:27.577755 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6987 01:22:27.580972 iDelay=217, Bit 2, Center -56 (-303 ~ 192) 496
6988 01:22:27.584032 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6989 01:22:27.590637 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
6990 01:22:27.593736 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6991 01:22:27.597460 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6992 01:22:27.600415 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6993 01:22:27.607013 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6994 01:22:27.610389 iDelay=217, Bit 9, Center -60 (-319 ~ 200) 520
6995 01:22:27.613663 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6996 01:22:27.620374 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6997 01:22:27.624110 iDelay=217, Bit 12, Center -44 (-295 ~ 208) 504
6998 01:22:27.627167 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6999 01:22:27.630383 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7000 01:22:27.637173 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7001 01:22:27.637276 ==
7002 01:22:27.640341 Dram Type= 6, Freq= 0, CH_1, rank 1
7003 01:22:27.644077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7004 01:22:27.644168 ==
7005 01:22:27.644237 DQS Delay:
7006 01:22:27.647084 DQS0 = 56, DQS1 = 64
7007 01:22:27.647177 DQM Delay:
7008 01:22:27.650275 DQM0 = 10, DQM1 = 11
7009 01:22:27.650374 DQ Delay:
7010 01:22:27.653803 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
7011 01:22:27.657303 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =4
7012 01:22:27.660402 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
7013 01:22:27.663432 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
7014 01:22:27.663525
7015 01:22:27.663592
7016 01:22:27.670428 [DQSOSCAuto] RK1, (LSB)MR18= 0x73a3, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
7017 01:22:27.673499 CH1 RK1: MR19=C0C, MR18=73A3
7018 01:22:27.680299 CH1_RK1: MR19=0xC0C, MR18=0x73A3, DQSOSC=389, MR23=63, INC=390, DEC=260
7019 01:22:27.683314 [RxdqsGatingPostProcess] freq 400
7020 01:22:27.689975 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7021 01:22:27.693391 best DQS0 dly(2T, 0.5T) = (0, 10)
7022 01:22:27.693521 best DQS1 dly(2T, 0.5T) = (0, 10)
7023 01:22:27.696607 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7024 01:22:27.699849 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7025 01:22:27.703566 best DQS0 dly(2T, 0.5T) = (0, 10)
7026 01:22:27.706484 best DQS1 dly(2T, 0.5T) = (0, 10)
7027 01:22:27.710077 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7028 01:22:27.713475 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7029 01:22:27.716584 Pre-setting of DQS Precalculation
7030 01:22:27.723211 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7031 01:22:27.729787 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7032 01:22:27.736450 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7033 01:22:27.736558
7034 01:22:27.736626
7035 01:22:27.739670 [Calibration Summary] 800 Mbps
7036 01:22:27.739784 CH 0, Rank 0
7037 01:22:27.743199 SW Impedance : PASS
7038 01:22:27.746499 DUTY Scan : NO K
7039 01:22:27.746584 ZQ Calibration : PASS
7040 01:22:27.749577 Jitter Meter : NO K
7041 01:22:27.753242 CBT Training : PASS
7042 01:22:27.753365 Write leveling : PASS
7043 01:22:27.756248 RX DQS gating : PASS
7044 01:22:27.756354 RX DQ/DQS(RDDQC) : PASS
7045 01:22:27.759817 TX DQ/DQS : PASS
7046 01:22:27.762680 RX DATLAT : PASS
7047 01:22:27.762793 RX DQ/DQS(Engine): PASS
7048 01:22:27.766331 TX OE : NO K
7049 01:22:27.766444 All Pass.
7050 01:22:27.766543
7051 01:22:27.769734 CH 0, Rank 1
7052 01:22:27.769841 SW Impedance : PASS
7053 01:22:27.773184 DUTY Scan : NO K
7054 01:22:27.776375 ZQ Calibration : PASS
7055 01:22:27.776493 Jitter Meter : NO K
7056 01:22:27.779750 CBT Training : PASS
7057 01:22:27.782857 Write leveling : NO K
7058 01:22:27.782945 RX DQS gating : PASS
7059 01:22:27.786018 RX DQ/DQS(RDDQC) : PASS
7060 01:22:27.789190 TX DQ/DQS : PASS
7061 01:22:27.789278 RX DATLAT : PASS
7062 01:22:27.792714 RX DQ/DQS(Engine): PASS
7063 01:22:27.795735 TX OE : NO K
7064 01:22:27.795825 All Pass.
7065 01:22:27.795893
7066 01:22:27.795955 CH 1, Rank 0
7067 01:22:27.799575 SW Impedance : PASS
7068 01:22:27.802748 DUTY Scan : NO K
7069 01:22:27.802829 ZQ Calibration : PASS
7070 01:22:27.805819 Jitter Meter : NO K
7071 01:22:27.809566 CBT Training : PASS
7072 01:22:27.809658 Write leveling : PASS
7073 01:22:27.812777 RX DQS gating : PASS
7074 01:22:27.815952 RX DQ/DQS(RDDQC) : PASS
7075 01:22:27.816067 TX DQ/DQS : PASS
7076 01:22:27.819445 RX DATLAT : PASS
7077 01:22:27.819557 RX DQ/DQS(Engine): PASS
7078 01:22:27.823026 TX OE : NO K
7079 01:22:27.823112 All Pass.
7080 01:22:27.823179
7081 01:22:27.826146 CH 1, Rank 1
7082 01:22:27.826257 SW Impedance : PASS
7083 01:22:27.829100 DUTY Scan : NO K
7084 01:22:27.832685 ZQ Calibration : PASS
7085 01:22:27.832801 Jitter Meter : NO K
7086 01:22:27.836055 CBT Training : PASS
7087 01:22:27.839041 Write leveling : NO K
7088 01:22:27.839127 RX DQS gating : PASS
7089 01:22:27.842673 RX DQ/DQS(RDDQC) : PASS
7090 01:22:27.845646 TX DQ/DQS : PASS
7091 01:22:27.845762 RX DATLAT : PASS
7092 01:22:27.849376 RX DQ/DQS(Engine): PASS
7093 01:22:27.852415 TX OE : NO K
7094 01:22:27.852503 All Pass.
7095 01:22:27.852571
7096 01:22:27.852633 DramC Write-DBI off
7097 01:22:27.855635 PER_BANK_REFRESH: Hybrid Mode
7098 01:22:27.858785 TX_TRACKING: ON
7099 01:22:27.865337 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7100 01:22:27.872421 [FAST_K] Save calibration result to emmc
7101 01:22:27.875421 dramc_set_vcore_voltage set vcore to 725000
7102 01:22:27.875549 Read voltage for 1600, 0
7103 01:22:27.878593 Vio18 = 0
7104 01:22:27.878706 Vcore = 725000
7105 01:22:27.878804 Vdram = 0
7106 01:22:27.881955 Vddq = 0
7107 01:22:27.882034 Vmddr = 0
7108 01:22:27.885689 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7109 01:22:27.892134 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7110 01:22:27.895662 MEM_TYPE=3, freq_sel=13
7111 01:22:27.898604 sv_algorithm_assistance_LP4_3733
7112 01:22:27.902313 ============ PULL DRAM RESETB DOWN ============
7113 01:22:27.905522 ========== PULL DRAM RESETB DOWN end =========
7114 01:22:27.912350 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7115 01:22:27.915611 ===================================
7116 01:22:27.915702 LPDDR4 DRAM CONFIGURATION
7117 01:22:27.918725 ===================================
7118 01:22:27.921787 EX_ROW_EN[0] = 0x0
7119 01:22:27.921872 EX_ROW_EN[1] = 0x0
7120 01:22:27.925391 LP4Y_EN = 0x0
7121 01:22:27.925478 WORK_FSP = 0x1
7122 01:22:27.928757 WL = 0x5
7123 01:22:27.928842 RL = 0x5
7124 01:22:27.932027 BL = 0x2
7125 01:22:27.935111 RPST = 0x0
7126 01:22:27.935198 RD_PRE = 0x0
7127 01:22:27.938191 WR_PRE = 0x1
7128 01:22:27.938278 WR_PST = 0x1
7129 01:22:27.941976 DBI_WR = 0x0
7130 01:22:27.942062 DBI_RD = 0x0
7131 01:22:27.945071 OTF = 0x1
7132 01:22:27.948519 ===================================
7133 01:22:27.951470 ===================================
7134 01:22:27.951562 ANA top config
7135 01:22:27.954702 ===================================
7136 01:22:27.958059 DLL_ASYNC_EN = 0
7137 01:22:27.961555 ALL_SLAVE_EN = 0
7138 01:22:27.961644 NEW_RANK_MODE = 1
7139 01:22:27.964824 DLL_IDLE_MODE = 1
7140 01:22:27.968054 LP45_APHY_COMB_EN = 1
7141 01:22:27.971743 TX_ODT_DIS = 0
7142 01:22:27.974802 NEW_8X_MODE = 1
7143 01:22:27.977740 ===================================
7144 01:22:27.981444 ===================================
7145 01:22:27.981578 data_rate = 3200
7146 01:22:27.984482 CKR = 1
7147 01:22:27.988134 DQ_P2S_RATIO = 8
7148 01:22:27.991394 ===================================
7149 01:22:27.994414 CA_P2S_RATIO = 8
7150 01:22:27.997868 DQ_CA_OPEN = 0
7151 01:22:28.001070 DQ_SEMI_OPEN = 0
7152 01:22:28.001156 CA_SEMI_OPEN = 0
7153 01:22:28.004713 CA_FULL_RATE = 0
7154 01:22:28.007919 DQ_CKDIV4_EN = 0
7155 01:22:28.010958 CA_CKDIV4_EN = 0
7156 01:22:28.014214 CA_PREDIV_EN = 0
7157 01:22:28.018006 PH8_DLY = 12
7158 01:22:28.018106 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7159 01:22:28.021267 DQ_AAMCK_DIV = 4
7160 01:22:28.024444 CA_AAMCK_DIV = 4
7161 01:22:28.027397 CA_ADMCK_DIV = 4
7162 01:22:28.031251 DQ_TRACK_CA_EN = 0
7163 01:22:28.034279 CA_PICK = 1600
7164 01:22:28.037568 CA_MCKIO = 1600
7165 01:22:28.037659 MCKIO_SEMI = 0
7166 01:22:28.041305 PLL_FREQ = 3068
7167 01:22:28.044404 DQ_UI_PI_RATIO = 32
7168 01:22:28.047431 CA_UI_PI_RATIO = 0
7169 01:22:28.051330 ===================================
7170 01:22:28.054359 ===================================
7171 01:22:28.057640 memory_type:LPDDR4
7172 01:22:28.057728 GP_NUM : 10
7173 01:22:28.060763 SRAM_EN : 1
7174 01:22:28.064384 MD32_EN : 0
7175 01:22:28.067775 ===================================
7176 01:22:28.067866 [ANA_INIT] >>>>>>>>>>>>>>
7177 01:22:28.071114 <<<<<< [CONFIGURE PHASE]: ANA_TX
7178 01:22:28.074305 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7179 01:22:28.077587 ===================================
7180 01:22:28.080990 data_rate = 3200,PCW = 0X7600
7181 01:22:28.084236 ===================================
7182 01:22:28.087445 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7183 01:22:28.094183 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7184 01:22:28.097336 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7185 01:22:28.104173 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7186 01:22:28.107181 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7187 01:22:28.110529 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7188 01:22:28.110620 [ANA_INIT] flow start
7189 01:22:28.113702 [ANA_INIT] PLL >>>>>>>>
7190 01:22:28.117275 [ANA_INIT] PLL <<<<<<<<
7191 01:22:28.120603 [ANA_INIT] MIDPI >>>>>>>>
7192 01:22:28.120694 [ANA_INIT] MIDPI <<<<<<<<
7193 01:22:28.123888 [ANA_INIT] DLL >>>>>>>>
7194 01:22:28.127005 [ANA_INIT] DLL <<<<<<<<
7195 01:22:28.127117 [ANA_INIT] flow end
7196 01:22:28.130798 ============ LP4 DIFF to SE enter ============
7197 01:22:28.136963 ============ LP4 DIFF to SE exit ============
7198 01:22:28.137065 [ANA_INIT] <<<<<<<<<<<<<
7199 01:22:28.140491 [Flow] Enable top DCM control >>>>>
7200 01:22:28.143970 [Flow] Enable top DCM control <<<<<
7201 01:22:28.147211 Enable DLL master slave shuffle
7202 01:22:28.154120 ==============================================================
7203 01:22:28.154218 Gating Mode config
7204 01:22:28.160402 ==============================================================
7205 01:22:28.163353 Config description:
7206 01:22:28.173414 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7207 01:22:28.180179 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7208 01:22:28.183602 SELPH_MODE 0: By rank 1: By Phase
7209 01:22:28.190082 ==============================================================
7210 01:22:28.193457 GAT_TRACK_EN = 1
7211 01:22:28.196709 RX_GATING_MODE = 2
7212 01:22:28.196796 RX_GATING_TRACK_MODE = 2
7213 01:22:28.199966 SELPH_MODE = 1
7214 01:22:28.203424 PICG_EARLY_EN = 1
7215 01:22:28.206658 VALID_LAT_VALUE = 1
7216 01:22:28.213497 ==============================================================
7217 01:22:28.216907 Enter into Gating configuration >>>>
7218 01:22:28.220015 Exit from Gating configuration <<<<
7219 01:22:28.223751 Enter into DVFS_PRE_config >>>>>
7220 01:22:28.233329 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7221 01:22:28.236426 Exit from DVFS_PRE_config <<<<<
7222 01:22:28.240232 Enter into PICG configuration >>>>
7223 01:22:28.243200 Exit from PICG configuration <<<<
7224 01:22:28.246179 [RX_INPUT] configuration >>>>>
7225 01:22:28.250018 [RX_INPUT] configuration <<<<<
7226 01:22:28.253454 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7227 01:22:28.259621 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7228 01:22:28.266259 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7229 01:22:28.272675 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7230 01:22:28.276309 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7231 01:22:28.283121 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7232 01:22:28.286213 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7233 01:22:28.292742 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7234 01:22:28.296479 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7235 01:22:28.299482 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7236 01:22:28.302459 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7237 01:22:28.308971 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7238 01:22:28.312404 ===================================
7239 01:22:28.316131 LPDDR4 DRAM CONFIGURATION
7240 01:22:28.319248 ===================================
7241 01:22:28.319375 EX_ROW_EN[0] = 0x0
7242 01:22:28.322279 EX_ROW_EN[1] = 0x0
7243 01:22:28.322359 LP4Y_EN = 0x0
7244 01:22:28.325990 WORK_FSP = 0x1
7245 01:22:28.326092 WL = 0x5
7246 01:22:28.329150 RL = 0x5
7247 01:22:28.329238 BL = 0x2
7248 01:22:28.332274 RPST = 0x0
7249 01:22:28.332388 RD_PRE = 0x0
7250 01:22:28.335910 WR_PRE = 0x1
7251 01:22:28.336022 WR_PST = 0x1
7252 01:22:28.338847 DBI_WR = 0x0
7253 01:22:28.338940 DBI_RD = 0x0
7254 01:22:28.342297 OTF = 0x1
7255 01:22:28.345730 ===================================
7256 01:22:28.348811 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7257 01:22:28.352052 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7258 01:22:28.358994 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7259 01:22:28.362209 ===================================
7260 01:22:28.365648 LPDDR4 DRAM CONFIGURATION
7261 01:22:28.368819 ===================================
7262 01:22:28.368908 EX_ROW_EN[0] = 0x10
7263 01:22:28.372154 EX_ROW_EN[1] = 0x0
7264 01:22:28.372272 LP4Y_EN = 0x0
7265 01:22:28.375240 WORK_FSP = 0x1
7266 01:22:28.375324 WL = 0x5
7267 01:22:28.378444 RL = 0x5
7268 01:22:28.378524 BL = 0x2
7269 01:22:28.382006 RPST = 0x0
7270 01:22:28.382095 RD_PRE = 0x0
7271 01:22:28.385188 WR_PRE = 0x1
7272 01:22:28.385279 WR_PST = 0x1
7273 01:22:28.388728 DBI_WR = 0x0
7274 01:22:28.388844 DBI_RD = 0x0
7275 01:22:28.391873 OTF = 0x1
7276 01:22:28.395455 ===================================
7277 01:22:28.402177 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7278 01:22:28.402312 ==
7279 01:22:28.405235 Dram Type= 6, Freq= 0, CH_0, rank 0
7280 01:22:28.408210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7281 01:22:28.408332 ==
7282 01:22:28.411764 [Duty_Offset_Calibration]
7283 01:22:28.411883 B0:2 B1:0 CA:3
7284 01:22:28.411982
7285 01:22:28.415009 [DutyScan_Calibration_Flow] k_type=0
7286 01:22:28.426259
7287 01:22:28.426387 ==CLK 0==
7288 01:22:28.429851 Final CLK duty delay cell = 0
7289 01:22:28.432814 [0] MAX Duty = 5031%(X100), DQS PI = 12
7290 01:22:28.435996 [0] MIN Duty = 4907%(X100), DQS PI = 6
7291 01:22:28.436123 [0] AVG Duty = 4969%(X100)
7292 01:22:28.439729
7293 01:22:28.442592 CH0 CLK Duty spec in!! Max-Min= 124%
7294 01:22:28.446291 [DutyScan_Calibration_Flow] ====Done====
7295 01:22:28.446432
7296 01:22:28.449423 [DutyScan_Calibration_Flow] k_type=1
7297 01:22:28.466458
7298 01:22:28.466590 ==DQS 0 ==
7299 01:22:28.469349 Final DQS duty delay cell = 0
7300 01:22:28.472693 [0] MAX Duty = 5094%(X100), DQS PI = 28
7301 01:22:28.476000 [0] MIN Duty = 4875%(X100), DQS PI = 48
7302 01:22:28.479112 [0] AVG Duty = 4984%(X100)
7303 01:22:28.479211
7304 01:22:28.479279 ==DQS 1 ==
7305 01:22:28.482960 Final DQS duty delay cell = 0
7306 01:22:28.485953 [0] MAX Duty = 5156%(X100), DQS PI = 30
7307 01:22:28.489018 [0] MIN Duty = 5031%(X100), DQS PI = 12
7308 01:22:28.492706 [0] AVG Duty = 5093%(X100)
7309 01:22:28.492799
7310 01:22:28.495860 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7311 01:22:28.495946
7312 01:22:28.498963 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7313 01:22:28.502317 [DutyScan_Calibration_Flow] ====Done====
7314 01:22:28.502410
7315 01:22:28.505794 [DutyScan_Calibration_Flow] k_type=3
7316 01:22:28.524212
7317 01:22:28.524376 ==DQM 0 ==
7318 01:22:28.527650 Final DQM duty delay cell = 0
7319 01:22:28.530633 [0] MAX Duty = 5156%(X100), DQS PI = 14
7320 01:22:28.534087 [0] MIN Duty = 4875%(X100), DQS PI = 0
7321 01:22:28.537439 [0] AVG Duty = 5015%(X100)
7322 01:22:28.537584
7323 01:22:28.537683 ==DQM 1 ==
7324 01:22:28.540855 Final DQM duty delay cell = 4
7325 01:22:28.543915 [4] MAX Duty = 5156%(X100), DQS PI = 52
7326 01:22:28.547044 [4] MIN Duty = 5000%(X100), DQS PI = 40
7327 01:22:28.550517 [4] AVG Duty = 5078%(X100)
7328 01:22:28.550629
7329 01:22:28.553659 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7330 01:22:28.553761
7331 01:22:28.557162 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7332 01:22:28.560640 [DutyScan_Calibration_Flow] ====Done====
7333 01:22:28.560756
7334 01:22:28.563672 [DutyScan_Calibration_Flow] k_type=2
7335 01:22:28.580252
7336 01:22:28.580399 ==DQ 0 ==
7337 01:22:28.583704 Final DQ duty delay cell = -4
7338 01:22:28.586965 [-4] MAX Duty = 5000%(X100), DQS PI = 16
7339 01:22:28.590488 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7340 01:22:28.593365 [-4] AVG Duty = 4938%(X100)
7341 01:22:28.593469
7342 01:22:28.593582 ==DQ 1 ==
7343 01:22:28.597093 Final DQ duty delay cell = 0
7344 01:22:28.600230 [0] MAX Duty = 5156%(X100), DQS PI = 60
7345 01:22:28.603965 [0] MIN Duty = 5000%(X100), DQS PI = 14
7346 01:22:28.606812 [0] AVG Duty = 5078%(X100)
7347 01:22:28.606894
7348 01:22:28.610341 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7349 01:22:28.610423
7350 01:22:28.613324 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7351 01:22:28.616963 [DutyScan_Calibration_Flow] ====Done====
7352 01:22:28.617073 ==
7353 01:22:28.620065 Dram Type= 6, Freq= 0, CH_1, rank 0
7354 01:22:28.623098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7355 01:22:28.623212 ==
7356 01:22:28.626769 [Duty_Offset_Calibration]
7357 01:22:28.626860 B0:1 B1:-2 CA:1
7358 01:22:28.626927
7359 01:22:28.630025 [DutyScan_Calibration_Flow] k_type=0
7360 01:22:28.641104
7361 01:22:28.641204 ==CLK 0==
7362 01:22:28.644538 Final CLK duty delay cell = 0
7363 01:22:28.647799 [0] MAX Duty = 5094%(X100), DQS PI = 22
7364 01:22:28.651049 [0] MIN Duty = 4813%(X100), DQS PI = 60
7365 01:22:28.654474 [0] AVG Duty = 4953%(X100)
7366 01:22:28.654596
7367 01:22:28.657433 CH1 CLK Duty spec in!! Max-Min= 281%
7368 01:22:28.660758 [DutyScan_Calibration_Flow] ====Done====
7369 01:22:28.660870
7370 01:22:28.663872 [DutyScan_Calibration_Flow] k_type=1
7371 01:22:28.681040
7372 01:22:28.681160 ==DQS 0 ==
7373 01:22:28.684267 Final DQS duty delay cell = 0
7374 01:22:28.687699 [0] MAX Duty = 5187%(X100), DQS PI = 24
7375 01:22:28.690553 [0] MIN Duty = 5062%(X100), DQS PI = 0
7376 01:22:28.694395 [0] AVG Duty = 5124%(X100)
7377 01:22:28.694515
7378 01:22:28.694611 ==DQS 1 ==
7379 01:22:28.697188 Final DQS duty delay cell = 0
7380 01:22:28.700447 [0] MAX Duty = 5093%(X100), DQS PI = 60
7381 01:22:28.704073 [0] MIN Duty = 4844%(X100), DQS PI = 24
7382 01:22:28.707207 [0] AVG Duty = 4968%(X100)
7383 01:22:28.707313
7384 01:22:28.710409 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7385 01:22:28.710491
7386 01:22:28.713981 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7387 01:22:28.717003 [DutyScan_Calibration_Flow] ====Done====
7388 01:22:28.717114
7389 01:22:28.720385 [DutyScan_Calibration_Flow] k_type=3
7390 01:22:28.737657
7391 01:22:28.737800 ==DQM 0 ==
7392 01:22:28.741527 Final DQM duty delay cell = 0
7393 01:22:28.744693 [0] MAX Duty = 5031%(X100), DQS PI = 24
7394 01:22:28.747585 [0] MIN Duty = 4813%(X100), DQS PI = 54
7395 01:22:28.751339 [0] AVG Duty = 4922%(X100)
7396 01:22:28.751455
7397 01:22:28.751530 ==DQM 1 ==
7398 01:22:28.754279 Final DQM duty delay cell = 0
7399 01:22:28.757687 [0] MAX Duty = 5062%(X100), DQS PI = 34
7400 01:22:28.761145 [0] MIN Duty = 4875%(X100), DQS PI = 26
7401 01:22:28.764433 [0] AVG Duty = 4968%(X100)
7402 01:22:28.764518
7403 01:22:28.767557 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7404 01:22:28.767671
7405 01:22:28.770674 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7406 01:22:28.774202 [DutyScan_Calibration_Flow] ====Done====
7407 01:22:28.774321
7408 01:22:28.777733 [DutyScan_Calibration_Flow] k_type=2
7409 01:22:28.794675
7410 01:22:28.794816 ==DQ 0 ==
7411 01:22:28.797995 Final DQ duty delay cell = 0
7412 01:22:28.801429 [0] MAX Duty = 5124%(X100), DQS PI = 22
7413 01:22:28.804366 [0] MIN Duty = 4907%(X100), DQS PI = 60
7414 01:22:28.804453 [0] AVG Duty = 5015%(X100)
7415 01:22:28.807700
7416 01:22:28.807783 ==DQ 1 ==
7417 01:22:28.810967 Final DQ duty delay cell = 0
7418 01:22:28.814178 [0] MAX Duty = 5125%(X100), DQS PI = 34
7419 01:22:28.817703 [0] MIN Duty = 4938%(X100), DQS PI = 24
7420 01:22:28.821277 [0] AVG Duty = 5031%(X100)
7421 01:22:28.821394
7422 01:22:28.824180 CH1 DQ 0 Duty spec in!! Max-Min= 217%
7423 01:22:28.824269
7424 01:22:28.827811 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7425 01:22:28.830917 [DutyScan_Calibration_Flow] ====Done====
7426 01:22:28.834109 nWR fixed to 30
7427 01:22:28.837831 [ModeRegInit_LP4] CH0 RK0
7428 01:22:28.837916 [ModeRegInit_LP4] CH0 RK1
7429 01:22:28.840987 [ModeRegInit_LP4] CH1 RK0
7430 01:22:28.844132 [ModeRegInit_LP4] CH1 RK1
7431 01:22:28.844239 match AC timing 5
7432 01:22:28.851199 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7433 01:22:28.854296 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7434 01:22:28.857387 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7435 01:22:28.864013 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7436 01:22:28.867156 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7437 01:22:28.867268 [MiockJmeterHQA]
7438 01:22:28.867375
7439 01:22:28.870773 [DramcMiockJmeter] u1RxGatingPI = 0
7440 01:22:28.873796 0 : 4366, 4139
7441 01:22:28.873879 4 : 4252, 4027
7442 01:22:28.877350 8 : 4252, 4027
7443 01:22:28.877434 12 : 4252, 4027
7444 01:22:28.880913 16 : 4253, 4027
7445 01:22:28.880991 20 : 4254, 4029
7446 01:22:28.881075 24 : 4363, 4138
7447 01:22:28.883614 28 : 4363, 4137
7448 01:22:28.883691 32 : 4252, 4027
7449 01:22:28.887049 36 : 4252, 4027
7450 01:22:28.887126 40 : 4253, 4026
7451 01:22:28.890526 44 : 4363, 4138
7452 01:22:28.890628 48 : 4252, 4027
7453 01:22:28.893611 52 : 4360, 4138
7454 01:22:28.893700 56 : 4253, 4027
7455 01:22:28.893775 60 : 4250, 4027
7456 01:22:28.897148 64 : 4250, 4027
7457 01:22:28.897248 68 : 4252, 4029
7458 01:22:28.900020 72 : 4360, 4138
7459 01:22:28.900100 76 : 4250, 4027
7460 01:22:28.903486 80 : 4361, 4137
7461 01:22:28.903567 84 : 4250, 4027
7462 01:22:28.906826 88 : 4250, 4027
7463 01:22:28.906904 92 : 4250, 4027
7464 01:22:28.906971 96 : 4360, 4138
7465 01:22:28.910113 100 : 4250, 4027
7466 01:22:28.910201 104 : 4250, 3334
7467 01:22:28.913793 108 : 4250, 0
7468 01:22:28.913882 112 : 4250, 0
7469 01:22:28.916995 116 : 4250, 0
7470 01:22:28.917081 120 : 4250, 0
7471 01:22:28.917150 124 : 4250, 0
7472 01:22:28.920206 128 : 4252, 0
7473 01:22:28.920303 132 : 4360, 0
7474 01:22:28.920414 136 : 4250, 0
7475 01:22:28.923171 140 : 4250, 0
7476 01:22:28.923258 144 : 4250, 0
7477 01:22:28.926824 148 : 4361, 0
7478 01:22:28.926941 152 : 4360, 0
7479 01:22:28.927046 156 : 4250, 0
7480 01:22:28.929837 160 : 4250, 0
7481 01:22:28.929951 164 : 4250, 0
7482 01:22:28.933244 168 : 4360, 0
7483 01:22:28.933330 172 : 4250, 0
7484 01:22:28.933438 176 : 4250, 0
7485 01:22:28.936847 180 : 4252, 0
7486 01:22:28.936928 184 : 4360, 0
7487 01:22:28.939901 188 : 4250, 0
7488 01:22:28.939981 192 : 4250, 0
7489 01:22:28.940047 196 : 4250, 0
7490 01:22:28.943190 200 : 4250, 0
7491 01:22:28.943269 204 : 4363, 0
7492 01:22:28.946798 208 : 4250, 0
7493 01:22:28.946878 212 : 4361, 0
7494 01:22:28.946943 216 : 4361, 0
7495 01:22:28.949969 220 : 4249, 0
7496 01:22:28.950081 224 : 4250, 0
7497 01:22:28.950187 228 : 4250, 0
7498 01:22:28.953064 232 : 4250, 0
7499 01:22:28.953170 236 : 4360, 1534
7500 01:22:28.956718 240 : 4250, 4027
7501 01:22:28.956824 244 : 4361, 4137
7502 01:22:28.960003 248 : 4250, 4027
7503 01:22:28.960115 252 : 4250, 4027
7504 01:22:28.963068 256 : 4250, 4027
7505 01:22:28.963180 260 : 4253, 4029
7506 01:22:28.966489 264 : 4250, 4026
7507 01:22:28.966596 268 : 4250, 4027
7508 01:22:28.969541 272 : 4250, 4027
7509 01:22:28.969621 276 : 4252, 4029
7510 01:22:28.969687 280 : 4250, 4026
7511 01:22:28.972703 284 : 4361, 4137
7512 01:22:28.972778 288 : 4363, 4138
7513 01:22:28.976501 292 : 4250, 4027
7514 01:22:28.976580 296 : 4363, 4140
7515 01:22:28.979332 300 : 4250, 4026
7516 01:22:28.979411 304 : 4250, 4027
7517 01:22:28.982926 308 : 4252, 4030
7518 01:22:28.983008 312 : 4252, 4029
7519 01:22:28.986348 316 : 4250, 4026
7520 01:22:28.986428 320 : 4253, 4029
7521 01:22:28.989348 324 : 4250, 4027
7522 01:22:28.989426 328 : 4252, 4029
7523 01:22:28.993070 332 : 4250, 4026
7524 01:22:28.993156 336 : 4361, 4137
7525 01:22:28.995774 340 : 4360, 4138
7526 01:22:28.995869 344 : 4250, 4027
7527 01:22:28.995954 348 : 4363, 4140
7528 01:22:28.999368 352 : 4360, 4081
7529 01:22:28.999474 356 : 4250, 2333
7530 01:22:29.002926 360 : 4250, 1
7531 01:22:29.003040
7532 01:22:29.006144 MIOCK jitter meter ch=0
7533 01:22:29.006227
7534 01:22:29.006321 1T = (360-108) = 252 dly cells
7535 01:22:29.012732 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7536 01:22:29.012828 ==
7537 01:22:29.015908 Dram Type= 6, Freq= 0, CH_0, rank 0
7538 01:22:29.019196 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 01:22:29.022569 ==
7540 01:22:29.025495 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7541 01:22:29.029011 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7542 01:22:29.035867 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7543 01:22:29.042233 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7544 01:22:29.049765 [CA 0] Center 44 (14~75) winsize 62
7545 01:22:29.052897 [CA 1] Center 43 (13~74) winsize 62
7546 01:22:29.056085 [CA 2] Center 40 (11~69) winsize 59
7547 01:22:29.059774 [CA 3] Center 39 (10~68) winsize 59
7548 01:22:29.062937 [CA 4] Center 37 (8~67) winsize 60
7549 01:22:29.066047 [CA 5] Center 37 (7~67) winsize 61
7550 01:22:29.066133
7551 01:22:29.069498 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7552 01:22:29.069595
7553 01:22:29.076104 [CATrainingPosCal] consider 1 rank data
7554 01:22:29.076225 u2DelayCellTimex100 = 258/100 ps
7555 01:22:29.083084 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7556 01:22:29.086131 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7557 01:22:29.089713 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7558 01:22:29.092585 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7559 01:22:29.096290 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7560 01:22:29.099173 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7561 01:22:29.099263
7562 01:22:29.102819 CA PerBit enable=1, Macro0, CA PI delay=37
7563 01:22:29.102905
7564 01:22:29.105767 [CBTSetCACLKResult] CA Dly = 37
7565 01:22:29.109606 CS Dly: 11 (0~42)
7566 01:22:29.112750 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7567 01:22:29.116257 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7568 01:22:29.116345 ==
7569 01:22:29.119280 Dram Type= 6, Freq= 0, CH_0, rank 1
7570 01:22:29.125619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7571 01:22:29.125708 ==
7572 01:22:29.129335 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7573 01:22:29.135898 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7574 01:22:29.139159 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7575 01:22:29.145923 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7576 01:22:29.153566 [CA 0] Center 44 (14~75) winsize 62
7577 01:22:29.156758 [CA 1] Center 44 (13~75) winsize 63
7578 01:22:29.160017 [CA 2] Center 39 (10~69) winsize 60
7579 01:22:29.163899 [CA 3] Center 39 (10~69) winsize 60
7580 01:22:29.166952 [CA 4] Center 37 (8~67) winsize 60
7581 01:22:29.170076 [CA 5] Center 37 (7~67) winsize 61
7582 01:22:29.170163
7583 01:22:29.173613 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7584 01:22:29.173697
7585 01:22:29.180297 [CATrainingPosCal] consider 2 rank data
7586 01:22:29.180387 u2DelayCellTimex100 = 258/100 ps
7587 01:22:29.186982 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7588 01:22:29.190136 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7589 01:22:29.193227 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7590 01:22:29.196265 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7591 01:22:29.199705 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7592 01:22:29.203312 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7593 01:22:29.203434
7594 01:22:29.206316 CA PerBit enable=1, Macro0, CA PI delay=37
7595 01:22:29.206402
7596 01:22:29.209974 [CBTSetCACLKResult] CA Dly = 37
7597 01:22:29.213077 CS Dly: 11 (0~43)
7598 01:22:29.216012 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7599 01:22:29.219662 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7600 01:22:29.219778
7601 01:22:29.222709 ----->DramcWriteLeveling(PI) begin...
7602 01:22:29.226287 ==
7603 01:22:29.226397 Dram Type= 6, Freq= 0, CH_0, rank 0
7604 01:22:29.233143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7605 01:22:29.233226 ==
7606 01:22:29.236199 Write leveling (Byte 0): 35 => 35
7607 01:22:29.239502 Write leveling (Byte 1): 26 => 26
7608 01:22:29.242955 DramcWriteLeveling(PI) end<-----
7609 01:22:29.243036
7610 01:22:29.243101 ==
7611 01:22:29.245736 Dram Type= 6, Freq= 0, CH_0, rank 0
7612 01:22:29.249553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7613 01:22:29.249666 ==
7614 01:22:29.252871 [Gating] SW mode calibration
7615 01:22:29.259478 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7616 01:22:29.266287 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7617 01:22:29.269357 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 01:22:29.272567 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 01:22:29.279146 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 01:22:29.282309 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 01:22:29.285427 1 4 16 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7622 01:22:29.292304 1 4 20 | B1->B0 | 2323 3333 | 0 1 | (1 0) (1 1)
7623 01:22:29.295426 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7624 01:22:29.298749 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7625 01:22:29.305183 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7626 01:22:29.308550 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7627 01:22:29.312111 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7628 01:22:29.318321 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7629 01:22:29.322142 1 5 16 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 1)
7630 01:22:29.325284 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7631 01:22:29.331946 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
7632 01:22:29.335047 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 01:22:29.338286 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7634 01:22:29.344808 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7635 01:22:29.348680 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7636 01:22:29.351780 1 6 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7637 01:22:29.358280 1 6 16 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
7638 01:22:29.361405 1 6 20 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7639 01:22:29.364979 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7640 01:22:29.368293 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 01:22:29.374983 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 01:22:29.377858 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7643 01:22:29.384509 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7644 01:22:29.388150 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7645 01:22:29.391318 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7646 01:22:29.397963 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7647 01:22:29.401157 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7648 01:22:29.404238 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 01:22:29.410892 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 01:22:29.414582 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 01:22:29.417345 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 01:22:29.421290 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 01:22:29.427477 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 01:22:29.430660 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 01:22:29.434307 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 01:22:29.440958 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 01:22:29.443982 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 01:22:29.447100 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 01:22:29.453700 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 01:22:29.457446 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7661 01:22:29.460824 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7662 01:22:29.467409 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7663 01:22:29.470564 Total UI for P1: 0, mck2ui 16
7664 01:22:29.473740 best dqsien dly found for B0: ( 1, 9, 14)
7665 01:22:29.476949 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7666 01:22:29.480620 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7667 01:22:29.483446 Total UI for P1: 0, mck2ui 16
7668 01:22:29.486955 best dqsien dly found for B1: ( 1, 9, 22)
7669 01:22:29.490082 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7670 01:22:29.496950 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7671 01:22:29.497091
7672 01:22:29.499848 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7673 01:22:29.503079 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7674 01:22:29.506808 [Gating] SW calibration Done
7675 01:22:29.506898 ==
7676 01:22:29.509937 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 01:22:29.513069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7678 01:22:29.513182 ==
7679 01:22:29.516313 RX Vref Scan: 0
7680 01:22:29.516401
7681 01:22:29.516470 RX Vref 0 -> 0, step: 1
7682 01:22:29.516553
7683 01:22:29.520043 RX Delay 0 -> 252, step: 8
7684 01:22:29.523062 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7685 01:22:29.529425 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7686 01:22:29.532854 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7687 01:22:29.536505 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7688 01:22:29.539641 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7689 01:22:29.542771 iDelay=192, Bit 5, Center 115 (64 ~ 167) 104
7690 01:22:29.549483 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7691 01:22:29.553025 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7692 01:22:29.556130 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7693 01:22:29.559189 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7694 01:22:29.562930 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7695 01:22:29.569384 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7696 01:22:29.572495 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7697 01:22:29.576147 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7698 01:22:29.579493 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7699 01:22:29.582500 iDelay=192, Bit 15, Center 127 (72 ~ 183) 112
7700 01:22:29.585677 ==
7701 01:22:29.589359 Dram Type= 6, Freq= 0, CH_0, rank 0
7702 01:22:29.592464 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7703 01:22:29.592548 ==
7704 01:22:29.592616 DQS Delay:
7705 01:22:29.595951 DQS0 = 0, DQS1 = 0
7706 01:22:29.596061 DQM Delay:
7707 01:22:29.599088 DQM0 = 128, DQM1 = 123
7708 01:22:29.599169 DQ Delay:
7709 01:22:29.602664 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7710 01:22:29.605973 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
7711 01:22:29.609378 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7712 01:22:29.612669 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =127
7713 01:22:29.612772
7714 01:22:29.612841
7715 01:22:29.612903 ==
7716 01:22:29.615764 Dram Type= 6, Freq= 0, CH_0, rank 0
7717 01:22:29.622322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7718 01:22:29.622410 ==
7719 01:22:29.622478
7720 01:22:29.622540
7721 01:22:29.622610 TX Vref Scan disable
7722 01:22:29.625965 == TX Byte 0 ==
7723 01:22:29.629742 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7724 01:22:29.636035 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7725 01:22:29.636124 == TX Byte 1 ==
7726 01:22:29.639368 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7727 01:22:29.645976 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7728 01:22:29.646067 ==
7729 01:22:29.649525 Dram Type= 6, Freq= 0, CH_0, rank 0
7730 01:22:29.652544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7731 01:22:29.652637 ==
7732 01:22:29.666205
7733 01:22:29.669210 TX Vref early break, caculate TX vref
7734 01:22:29.673001 TX Vref=16, minBit 8, minWin=20, winSum=359
7735 01:22:29.675960 TX Vref=18, minBit 8, minWin=22, winSum=371
7736 01:22:29.679427 TX Vref=20, minBit 8, minWin=21, winSum=376
7737 01:22:29.682774 TX Vref=22, minBit 8, minWin=23, winSum=386
7738 01:22:29.685718 TX Vref=24, minBit 4, minWin=24, winSum=398
7739 01:22:29.692560 TX Vref=26, minBit 4, minWin=24, winSum=406
7740 01:22:29.696172 TX Vref=28, minBit 8, minWin=24, winSum=407
7741 01:22:29.699125 TX Vref=30, minBit 8, minWin=23, winSum=395
7742 01:22:29.702647 TX Vref=32, minBit 8, minWin=23, winSum=389
7743 01:22:29.705581 TX Vref=34, minBit 8, minWin=22, winSum=376
7744 01:22:29.712201 [TxChooseVref] Worse bit 8, Min win 24, Win sum 407, Final Vref 28
7745 01:22:29.712322
7746 01:22:29.715441 Final TX Range 0 Vref 28
7747 01:22:29.715528
7748 01:22:29.715597 ==
7749 01:22:29.719276 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 01:22:29.722245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 01:22:29.722340 ==
7752 01:22:29.722409
7753 01:22:29.722471
7754 01:22:29.725683 TX Vref Scan disable
7755 01:22:29.731998 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7756 01:22:29.732118 == TX Byte 0 ==
7757 01:22:29.735552 u2DelayCellOfst[0]=11 cells (3 PI)
7758 01:22:29.738623 u2DelayCellOfst[1]=18 cells (5 PI)
7759 01:22:29.742416 u2DelayCellOfst[2]=11 cells (3 PI)
7760 01:22:29.745867 u2DelayCellOfst[3]=11 cells (3 PI)
7761 01:22:29.748710 u2DelayCellOfst[4]=7 cells (2 PI)
7762 01:22:29.752285 u2DelayCellOfst[5]=0 cells (0 PI)
7763 01:22:29.755769 u2DelayCellOfst[6]=18 cells (5 PI)
7764 01:22:29.758937 u2DelayCellOfst[7]=18 cells (5 PI)
7765 01:22:29.761795 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7766 01:22:29.765368 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7767 01:22:29.769033 == TX Byte 1 ==
7768 01:22:29.772052 u2DelayCellOfst[8]=0 cells (0 PI)
7769 01:22:29.772139 u2DelayCellOfst[9]=0 cells (0 PI)
7770 01:22:29.775193 u2DelayCellOfst[10]=7 cells (2 PI)
7771 01:22:29.778337 u2DelayCellOfst[11]=3 cells (1 PI)
7772 01:22:29.782077 u2DelayCellOfst[12]=15 cells (4 PI)
7773 01:22:29.785140 u2DelayCellOfst[13]=11 cells (3 PI)
7774 01:22:29.788369 u2DelayCellOfst[14]=15 cells (4 PI)
7775 01:22:29.791510 u2DelayCellOfst[15]=11 cells (3 PI)
7776 01:22:29.798525 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7777 01:22:29.801733 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7778 01:22:29.801821 DramC Write-DBI on
7779 01:22:29.801889 ==
7780 01:22:29.805187 Dram Type= 6, Freq= 0, CH_0, rank 0
7781 01:22:29.811720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7782 01:22:29.811811 ==
7783 01:22:29.811878
7784 01:22:29.811940
7785 01:22:29.812000 TX Vref Scan disable
7786 01:22:29.815762 == TX Byte 0 ==
7787 01:22:29.819280 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7788 01:22:29.822329 == TX Byte 1 ==
7789 01:22:29.825444 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7790 01:22:29.828746 DramC Write-DBI off
7791 01:22:29.828848
7792 01:22:29.828917 [DATLAT]
7793 01:22:29.828980 Freq=1600, CH0 RK0
7794 01:22:29.829042
7795 01:22:29.832427 DATLAT Default: 0xf
7796 01:22:29.832513 0, 0xFFFF, sum = 0
7797 01:22:29.835395 1, 0xFFFF, sum = 0
7798 01:22:29.838884 2, 0xFFFF, sum = 0
7799 01:22:29.838969 3, 0xFFFF, sum = 0
7800 01:22:29.842179 4, 0xFFFF, sum = 0
7801 01:22:29.842266 5, 0xFFFF, sum = 0
7802 01:22:29.845764 6, 0xFFFF, sum = 0
7803 01:22:29.845851 7, 0xFFFF, sum = 0
7804 01:22:29.848724 8, 0xFFFF, sum = 0
7805 01:22:29.848811 9, 0xFFFF, sum = 0
7806 01:22:29.852060 10, 0xFFFF, sum = 0
7807 01:22:29.852182 11, 0xFFFF, sum = 0
7808 01:22:29.855599 12, 0xFFFF, sum = 0
7809 01:22:29.855686 13, 0xFFFF, sum = 0
7810 01:22:29.858931 14, 0x0, sum = 1
7811 01:22:29.859018 15, 0x0, sum = 2
7812 01:22:29.861968 16, 0x0, sum = 3
7813 01:22:29.862055 17, 0x0, sum = 4
7814 01:22:29.865522 best_step = 15
7815 01:22:29.865607
7816 01:22:29.865674 ==
7817 01:22:29.868381 Dram Type= 6, Freq= 0, CH_0, rank 0
7818 01:22:29.871948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7819 01:22:29.872034 ==
7820 01:22:29.875160 RX Vref Scan: 1
7821 01:22:29.875272
7822 01:22:29.875384 Set Vref Range= 24 -> 127
7823 01:22:29.875478
7824 01:22:29.878697 RX Vref 24 -> 127, step: 1
7825 01:22:29.878792
7826 01:22:29.881776 RX Delay 11 -> 252, step: 4
7827 01:22:29.881850
7828 01:22:29.885379 Set Vref, RX VrefLevel [Byte0]: 24
7829 01:22:29.888448 [Byte1]: 24
7830 01:22:29.888543
7831 01:22:29.891861 Set Vref, RX VrefLevel [Byte0]: 25
7832 01:22:29.894951 [Byte1]: 25
7833 01:22:29.898712
7834 01:22:29.898792 Set Vref, RX VrefLevel [Byte0]: 26
7835 01:22:29.901743 [Byte1]: 26
7836 01:22:29.906022
7837 01:22:29.906126 Set Vref, RX VrefLevel [Byte0]: 27
7838 01:22:29.909560 [Byte1]: 27
7839 01:22:29.913461
7840 01:22:29.913578 Set Vref, RX VrefLevel [Byte0]: 28
7841 01:22:29.917029 [Byte1]: 28
7842 01:22:29.921235
7843 01:22:29.921340 Set Vref, RX VrefLevel [Byte0]: 29
7844 01:22:29.924851 [Byte1]: 29
7845 01:22:29.929118
7846 01:22:29.929225 Set Vref, RX VrefLevel [Byte0]: 30
7847 01:22:29.932072 [Byte1]: 30
7848 01:22:29.936341
7849 01:22:29.936446 Set Vref, RX VrefLevel [Byte0]: 31
7850 01:22:29.940050 [Byte1]: 31
7851 01:22:29.944391
7852 01:22:29.944495 Set Vref, RX VrefLevel [Byte0]: 32
7853 01:22:29.947408 [Byte1]: 32
7854 01:22:29.951779
7855 01:22:29.951899 Set Vref, RX VrefLevel [Byte0]: 33
7856 01:22:29.955099 [Byte1]: 33
7857 01:22:29.959680
7858 01:22:29.959786 Set Vref, RX VrefLevel [Byte0]: 34
7859 01:22:29.962735 [Byte1]: 34
7860 01:22:29.967033
7861 01:22:29.967114 Set Vref, RX VrefLevel [Byte0]: 35
7862 01:22:29.970611 [Byte1]: 35
7863 01:22:29.974606
7864 01:22:29.974684 Set Vref, RX VrefLevel [Byte0]: 36
7865 01:22:29.978137 [Byte1]: 36
7866 01:22:29.981942
7867 01:22:29.982018 Set Vref, RX VrefLevel [Byte0]: 37
7868 01:22:29.985389 [Byte1]: 37
7869 01:22:29.989614
7870 01:22:29.989694 Set Vref, RX VrefLevel [Byte0]: 38
7871 01:22:29.993295 [Byte1]: 38
7872 01:22:29.997822
7873 01:22:29.997907 Set Vref, RX VrefLevel [Byte0]: 39
7874 01:22:30.000853 [Byte1]: 39
7875 01:22:30.005390
7876 01:22:30.005494 Set Vref, RX VrefLevel [Byte0]: 40
7877 01:22:30.008379 [Byte1]: 40
7878 01:22:30.012700
7879 01:22:30.012775 Set Vref, RX VrefLevel [Byte0]: 41
7880 01:22:30.016181 [Byte1]: 41
7881 01:22:30.020127
7882 01:22:30.020211 Set Vref, RX VrefLevel [Byte0]: 42
7883 01:22:30.023656 [Byte1]: 42
7884 01:22:30.027823
7885 01:22:30.027899 Set Vref, RX VrefLevel [Byte0]: 43
7886 01:22:30.031459 [Byte1]: 43
7887 01:22:30.035621
7888 01:22:30.035723 Set Vref, RX VrefLevel [Byte0]: 44
7889 01:22:30.038584 [Byte1]: 44
7890 01:22:30.042871
7891 01:22:30.042972 Set Vref, RX VrefLevel [Byte0]: 45
7892 01:22:30.046632 [Byte1]: 45
7893 01:22:30.050990
7894 01:22:30.051106 Set Vref, RX VrefLevel [Byte0]: 46
7895 01:22:30.054200 [Byte1]: 46
7896 01:22:30.058586
7897 01:22:30.058692 Set Vref, RX VrefLevel [Byte0]: 47
7898 01:22:30.061623 [Byte1]: 47
7899 01:22:30.066195
7900 01:22:30.066297 Set Vref, RX VrefLevel [Byte0]: 48
7901 01:22:30.069617 [Byte1]: 48
7902 01:22:30.073318
7903 01:22:30.073432 Set Vref, RX VrefLevel [Byte0]: 49
7904 01:22:30.076874 [Byte1]: 49
7905 01:22:30.081374
7906 01:22:30.081473 Set Vref, RX VrefLevel [Byte0]: 50
7907 01:22:30.084420 [Byte1]: 50
7908 01:22:30.088562
7909 01:22:30.088635 Set Vref, RX VrefLevel [Byte0]: 51
7910 01:22:30.092318 [Byte1]: 51
7911 01:22:30.096321
7912 01:22:30.096408 Set Vref, RX VrefLevel [Byte0]: 52
7913 01:22:30.099610 [Byte1]: 52
7914 01:22:30.103840
7915 01:22:30.103956 Set Vref, RX VrefLevel [Byte0]: 53
7916 01:22:30.107348 [Byte1]: 53
7917 01:22:30.111375
7918 01:22:30.111485 Set Vref, RX VrefLevel [Byte0]: 54
7919 01:22:30.115113 [Byte1]: 54
7920 01:22:30.118923
7921 01:22:30.119033 Set Vref, RX VrefLevel [Byte0]: 55
7922 01:22:30.122435 [Byte1]: 55
7923 01:22:30.126940
7924 01:22:30.127026 Set Vref, RX VrefLevel [Byte0]: 56
7925 01:22:30.129844 [Byte1]: 56
7926 01:22:30.134425
7927 01:22:30.134510 Set Vref, RX VrefLevel [Byte0]: 57
7928 01:22:30.138007 [Byte1]: 57
7929 01:22:30.141806
7930 01:22:30.141892 Set Vref, RX VrefLevel [Byte0]: 58
7931 01:22:30.145620 [Byte1]: 58
7932 01:22:30.149778
7933 01:22:30.149861 Set Vref, RX VrefLevel [Byte0]: 59
7934 01:22:30.153002 [Byte1]: 59
7935 01:22:30.157309
7936 01:22:30.157422 Set Vref, RX VrefLevel [Byte0]: 60
7937 01:22:30.160455 [Byte1]: 60
7938 01:22:30.165406
7939 01:22:30.165490 Set Vref, RX VrefLevel [Byte0]: 61
7940 01:22:30.168300 [Byte1]: 61
7941 01:22:30.172741
7942 01:22:30.172826 Set Vref, RX VrefLevel [Byte0]: 62
7943 01:22:30.175642 [Byte1]: 62
7944 01:22:30.180011
7945 01:22:30.180095 Set Vref, RX VrefLevel [Byte0]: 63
7946 01:22:30.183525 [Byte1]: 63
7947 01:22:30.187925
7948 01:22:30.188009 Set Vref, RX VrefLevel [Byte0]: 64
7949 01:22:30.191025 [Byte1]: 64
7950 01:22:30.195623
7951 01:22:30.195712 Set Vref, RX VrefLevel [Byte0]: 65
7952 01:22:30.198779 [Byte1]: 65
7953 01:22:30.203291
7954 01:22:30.203378 Set Vref, RX VrefLevel [Byte0]: 66
7955 01:22:30.206088 [Byte1]: 66
7956 01:22:30.210638
7957 01:22:30.210740 Set Vref, RX VrefLevel [Byte0]: 67
7958 01:22:30.213832 [Byte1]: 67
7959 01:22:30.218513
7960 01:22:30.218621 Set Vref, RX VrefLevel [Byte0]: 68
7961 01:22:30.221625 [Byte1]: 68
7962 01:22:30.225734
7963 01:22:30.225818 Set Vref, RX VrefLevel [Byte0]: 69
7964 01:22:30.229177 [Byte1]: 69
7965 01:22:30.233421
7966 01:22:30.233568 Set Vref, RX VrefLevel [Byte0]: 70
7967 01:22:30.236801 [Byte1]: 70
7968 01:22:30.240929
7969 01:22:30.241009 Set Vref, RX VrefLevel [Byte0]: 71
7970 01:22:30.244363 [Byte1]: 71
7971 01:22:30.248633
7972 01:22:30.248737 Set Vref, RX VrefLevel [Byte0]: 72
7973 01:22:30.251702 [Byte1]: 72
7974 01:22:30.256602
7975 01:22:30.256688 Set Vref, RX VrefLevel [Byte0]: 73
7976 01:22:30.259720 [Byte1]: 73
7977 01:22:30.264149
7978 01:22:30.264258 Set Vref, RX VrefLevel [Byte0]: 74
7979 01:22:30.267127 [Byte1]: 74
7980 01:22:30.271476
7981 01:22:30.271579 Set Vref, RX VrefLevel [Byte0]: 75
7982 01:22:30.274602 [Byte1]: 75
7983 01:22:30.278826
7984 01:22:30.278901 Set Vref, RX VrefLevel [Byte0]: 76
7985 01:22:30.282625 [Byte1]: 76
7986 01:22:30.286795
7987 01:22:30.286878 Set Vref, RX VrefLevel [Byte0]: 77
7988 01:22:30.289649 [Byte1]: 77
7989 01:22:30.294374
7990 01:22:30.294458 Set Vref, RX VrefLevel [Byte0]: 78
7991 01:22:30.297627 [Byte1]: 78
7992 01:22:30.301712
7993 01:22:30.301796 Set Vref, RX VrefLevel [Byte0]: 79
7994 01:22:30.305376 [Byte1]: 79
7995 01:22:30.309363
7996 01:22:30.309465 Final RX Vref Byte 0 = 64 to rank0
7997 01:22:30.312715 Final RX Vref Byte 1 = 61 to rank0
7998 01:22:30.316109 Final RX Vref Byte 0 = 64 to rank1
7999 01:22:30.319546 Final RX Vref Byte 1 = 61 to rank1==
8000 01:22:30.322810 Dram Type= 6, Freq= 0, CH_0, rank 0
8001 01:22:30.329434 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8002 01:22:30.329575 ==
8003 01:22:30.329665 DQS Delay:
8004 01:22:30.329779 DQS0 = 0, DQS1 = 0
8005 01:22:30.332873 DQM Delay:
8006 01:22:30.332959 DQM0 = 126, DQM1 = 119
8007 01:22:30.336210 DQ Delay:
8008 01:22:30.339377 DQ0 =126, DQ1 =126, DQ2 =126, DQ3 =122
8009 01:22:30.342598 DQ4 =126, DQ5 =114, DQ6 =132, DQ7 =138
8010 01:22:30.345967 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8011 01:22:30.349057 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
8012 01:22:30.349141
8013 01:22:30.349206
8014 01:22:30.349267
8015 01:22:30.352350 [DramC_TX_OE_Calibration] TA2
8016 01:22:30.356052 Original DQ_B0 (3 6) =30, OEN = 27
8017 01:22:30.359128 Original DQ_B1 (3 6) =30, OEN = 27
8018 01:22:30.362734 24, 0x0, End_B0=24 End_B1=24
8019 01:22:30.362820 25, 0x0, End_B0=25 End_B1=25
8020 01:22:30.365840 26, 0x0, End_B0=26 End_B1=26
8021 01:22:30.368988 27, 0x0, End_B0=27 End_B1=27
8022 01:22:30.372561 28, 0x0, End_B0=28 End_B1=28
8023 01:22:30.375575 29, 0x0, End_B0=29 End_B1=29
8024 01:22:30.375712 30, 0x0, End_B0=30 End_B1=30
8025 01:22:30.379442 31, 0x4141, End_B0=30 End_B1=30
8026 01:22:30.382399 Byte0 end_step=30 best_step=27
8027 01:22:30.385429 Byte1 end_step=30 best_step=27
8028 01:22:30.389337 Byte0 TX OE(2T, 0.5T) = (3, 3)
8029 01:22:30.392379 Byte1 TX OE(2T, 0.5T) = (3, 3)
8030 01:22:30.392459
8031 01:22:30.392542
8032 01:22:30.399155 [DQSOSCAuto] RK0, (LSB)MR18= 0x1111, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
8033 01:22:30.402305 CH0 RK0: MR19=303, MR18=1111
8034 01:22:30.409061 CH0_RK0: MR19=0x303, MR18=0x1111, DQSOSC=401, MR23=63, INC=22, DEC=15
8035 01:22:30.409181
8036 01:22:30.412270 ----->DramcWriteLeveling(PI) begin...
8037 01:22:30.412351 ==
8038 01:22:30.415565 Dram Type= 6, Freq= 0, CH_0, rank 1
8039 01:22:30.418709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8040 01:22:30.418814 ==
8041 01:22:30.422234 Write leveling (Byte 0): 34 => 34
8042 01:22:30.425028 Write leveling (Byte 1): 26 => 26
8043 01:22:30.428855 DramcWriteLeveling(PI) end<-----
8044 01:22:30.428956
8045 01:22:30.429050 ==
8046 01:22:30.431657 Dram Type= 6, Freq= 0, CH_0, rank 1
8047 01:22:30.435174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8048 01:22:30.435251 ==
8049 01:22:30.438344 [Gating] SW mode calibration
8050 01:22:30.445277 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8051 01:22:30.452036 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8052 01:22:30.454795 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8053 01:22:30.461950 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8054 01:22:30.464999 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 01:22:30.468430 1 4 12 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
8056 01:22:30.475111 1 4 16 | B1->B0 | 2827 3434 | 1 1 | (1 1) (1 1)
8057 01:22:30.478153 1 4 20 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
8058 01:22:30.481195 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8059 01:22:30.488115 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8060 01:22:30.491117 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8061 01:22:30.494825 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8062 01:22:30.501036 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8063 01:22:30.504716 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
8064 01:22:30.507747 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8065 01:22:30.514262 1 5 20 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
8066 01:22:30.517786 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 01:22:30.521135 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 01:22:30.527362 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8069 01:22:30.530656 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 01:22:30.534442 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8071 01:22:30.540791 1 6 12 | B1->B0 | 2323 3e3e | 0 1 | (0 0) (0 0)
8072 01:22:30.544269 1 6 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
8073 01:22:30.547314 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 01:22:30.554045 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 01:22:30.557399 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 01:22:30.560705 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 01:22:30.567046 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 01:22:30.570405 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 01:22:30.573622 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8080 01:22:30.580495 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8081 01:22:30.584212 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8082 01:22:30.587282 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 01:22:30.593908 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 01:22:30.596997 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 01:22:30.600093 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 01:22:30.606860 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 01:22:30.610058 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 01:22:30.613763 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 01:22:30.620369 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 01:22:30.623283 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 01:22:30.626763 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 01:22:30.633423 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 01:22:30.637110 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 01:22:30.639990 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8095 01:22:30.646754 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8096 01:22:30.646874 Total UI for P1: 0, mck2ui 16
8097 01:22:30.649965 best dqsien dly found for B0: ( 1, 9, 8)
8098 01:22:30.656774 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8099 01:22:30.659780 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8100 01:22:30.663411 Total UI for P1: 0, mck2ui 16
8101 01:22:30.666934 best dqsien dly found for B1: ( 1, 9, 14)
8102 01:22:30.669819 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8103 01:22:30.673471 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8104 01:22:30.673599
8105 01:22:30.676478 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8106 01:22:30.679984 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8107 01:22:30.683251 [Gating] SW calibration Done
8108 01:22:30.683357 ==
8109 01:22:30.686511 Dram Type= 6, Freq= 0, CH_0, rank 1
8110 01:22:30.693205 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8111 01:22:30.693294 ==
8112 01:22:30.693359 RX Vref Scan: 0
8113 01:22:30.693427
8114 01:22:30.696318 RX Vref 0 -> 0, step: 1
8115 01:22:30.696396
8116 01:22:30.700007 RX Delay 0 -> 252, step: 8
8117 01:22:30.703023 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8118 01:22:30.706674 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8119 01:22:30.709715 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8120 01:22:30.712843 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8121 01:22:30.719586 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8122 01:22:30.722444 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8123 01:22:30.726249 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8124 01:22:30.729217 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8125 01:22:30.735654 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8126 01:22:30.739205 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8127 01:22:30.742757 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8128 01:22:30.745811 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8129 01:22:30.749264 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8130 01:22:30.755743 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8131 01:22:30.759012 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8132 01:22:30.762448 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8133 01:22:30.762563 ==
8134 01:22:30.765839 Dram Type= 6, Freq= 0, CH_0, rank 1
8135 01:22:30.769302 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8136 01:22:30.772073 ==
8137 01:22:30.772182 DQS Delay:
8138 01:22:30.772276 DQS0 = 0, DQS1 = 0
8139 01:22:30.775526 DQM Delay:
8140 01:22:30.775636 DQM0 = 127, DQM1 = 122
8141 01:22:30.778518 DQ Delay:
8142 01:22:30.782247 DQ0 =127, DQ1 =127, DQ2 =123, DQ3 =123
8143 01:22:30.785276 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8144 01:22:30.788727 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8145 01:22:30.792250 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8146 01:22:30.792356
8147 01:22:30.792448
8148 01:22:30.792538 ==
8149 01:22:30.795265 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 01:22:30.798549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 01:22:30.798628 ==
8152 01:22:30.798695
8153 01:22:30.801748
8154 01:22:30.801884 TX Vref Scan disable
8155 01:22:30.805117 == TX Byte 0 ==
8156 01:22:30.808275 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8157 01:22:30.811836 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8158 01:22:30.814935 == TX Byte 1 ==
8159 01:22:30.818732 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8160 01:22:30.821770 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8161 01:22:30.824784 ==
8162 01:22:30.824859 Dram Type= 6, Freq= 0, CH_0, rank 1
8163 01:22:30.831495 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8164 01:22:30.831580 ==
8165 01:22:30.845356
8166 01:22:30.848996 TX Vref early break, caculate TX vref
8167 01:22:30.852122 TX Vref=16, minBit 9, minWin=21, winSum=365
8168 01:22:30.855068 TX Vref=18, minBit 0, minWin=22, winSum=370
8169 01:22:30.858455 TX Vref=20, minBit 8, minWin=22, winSum=382
8170 01:22:30.862306 TX Vref=22, minBit 0, minWin=24, winSum=392
8171 01:22:30.865248 TX Vref=24, minBit 0, minWin=24, winSum=399
8172 01:22:30.872101 TX Vref=26, minBit 7, minWin=24, winSum=405
8173 01:22:30.875086 TX Vref=28, minBit 8, minWin=24, winSum=409
8174 01:22:30.878552 TX Vref=30, minBit 8, minWin=24, winSum=405
8175 01:22:30.881877 TX Vref=32, minBit 8, minWin=22, winSum=395
8176 01:22:30.885293 TX Vref=34, minBit 8, minWin=23, winSum=390
8177 01:22:30.888255 TX Vref=36, minBit 8, minWin=22, winSum=382
8178 01:22:30.895239 [TxChooseVref] Worse bit 8, Min win 24, Win sum 409, Final Vref 28
8179 01:22:30.895357
8180 01:22:30.898406 Final TX Range 0 Vref 28
8181 01:22:30.898486
8182 01:22:30.898558 ==
8183 01:22:30.901382 Dram Type= 6, Freq= 0, CH_0, rank 1
8184 01:22:30.904979 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8185 01:22:30.905092 ==
8186 01:22:30.905182
8187 01:22:30.908490
8188 01:22:30.908569 TX Vref Scan disable
8189 01:22:30.914828 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8190 01:22:30.914922 == TX Byte 0 ==
8191 01:22:30.918467 u2DelayCellOfst[0]=11 cells (3 PI)
8192 01:22:30.921417 u2DelayCellOfst[1]=18 cells (5 PI)
8193 01:22:30.925110 u2DelayCellOfst[2]=7 cells (2 PI)
8194 01:22:30.928179 u2DelayCellOfst[3]=11 cells (3 PI)
8195 01:22:30.931197 u2DelayCellOfst[4]=7 cells (2 PI)
8196 01:22:30.934966 u2DelayCellOfst[5]=0 cells (0 PI)
8197 01:22:30.938164 u2DelayCellOfst[6]=18 cells (5 PI)
8198 01:22:30.941184 u2DelayCellOfst[7]=18 cells (5 PI)
8199 01:22:30.944649 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8200 01:22:30.948090 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8201 01:22:30.951313 == TX Byte 1 ==
8202 01:22:30.954671 u2DelayCellOfst[8]=0 cells (0 PI)
8203 01:22:30.957837 u2DelayCellOfst[9]=0 cells (0 PI)
8204 01:22:30.961275 u2DelayCellOfst[10]=7 cells (2 PI)
8205 01:22:30.964510 u2DelayCellOfst[11]=7 cells (2 PI)
8206 01:22:30.964594 u2DelayCellOfst[12]=15 cells (4 PI)
8207 01:22:30.967604 u2DelayCellOfst[13]=11 cells (3 PI)
8208 01:22:30.971214 u2DelayCellOfst[14]=15 cells (4 PI)
8209 01:22:30.974755 u2DelayCellOfst[15]=11 cells (3 PI)
8210 01:22:30.981415 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8211 01:22:30.984423 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8212 01:22:30.984512 DramC Write-DBI on
8213 01:22:30.987729 ==
8214 01:22:30.991109 Dram Type= 6, Freq= 0, CH_0, rank 1
8215 01:22:30.994262 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8216 01:22:30.994413 ==
8217 01:22:30.994561
8218 01:22:30.994683
8219 01:22:30.997881 TX Vref Scan disable
8220 01:22:30.997964 == TX Byte 0 ==
8221 01:22:31.004359 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8222 01:22:31.004445 == TX Byte 1 ==
8223 01:22:31.007398 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8224 01:22:31.010956 DramC Write-DBI off
8225 01:22:31.011060
8226 01:22:31.011152 [DATLAT]
8227 01:22:31.014307 Freq=1600, CH0 RK1
8228 01:22:31.014406
8229 01:22:31.014474 DATLAT Default: 0xf
8230 01:22:31.017190 0, 0xFFFF, sum = 0
8231 01:22:31.017291 1, 0xFFFF, sum = 0
8232 01:22:31.020594 2, 0xFFFF, sum = 0
8233 01:22:31.020698 3, 0xFFFF, sum = 0
8234 01:22:31.024378 4, 0xFFFF, sum = 0
8235 01:22:31.024477 5, 0xFFFF, sum = 0
8236 01:22:31.027223 6, 0xFFFF, sum = 0
8237 01:22:31.030363 7, 0xFFFF, sum = 0
8238 01:22:31.030460 8, 0xFFFF, sum = 0
8239 01:22:31.034042 9, 0xFFFF, sum = 0
8240 01:22:31.034118 10, 0xFFFF, sum = 0
8241 01:22:31.037156 11, 0xFFFF, sum = 0
8242 01:22:31.037254 12, 0xFFFF, sum = 0
8243 01:22:31.040202 13, 0xCFFF, sum = 0
8244 01:22:31.040270 14, 0x0, sum = 1
8245 01:22:31.043822 15, 0x0, sum = 2
8246 01:22:31.043890 16, 0x0, sum = 3
8247 01:22:31.046963 17, 0x0, sum = 4
8248 01:22:31.047031 best_step = 15
8249 01:22:31.047092
8250 01:22:31.047149 ==
8251 01:22:31.050486 Dram Type= 6, Freq= 0, CH_0, rank 1
8252 01:22:31.053473 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8253 01:22:31.056918 ==
8254 01:22:31.057026 RX Vref Scan: 0
8255 01:22:31.057117
8256 01:22:31.060057 RX Vref 0 -> 0, step: 1
8257 01:22:31.060153
8258 01:22:31.060241 RX Delay 3 -> 252, step: 4
8259 01:22:31.067676 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8260 01:22:31.070869 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8261 01:22:31.073933 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8262 01:22:31.077490 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8263 01:22:31.081050 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8264 01:22:31.087688 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8265 01:22:31.090874 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8266 01:22:31.093943 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8267 01:22:31.097518 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8268 01:22:31.100519 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8269 01:22:31.107154 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8270 01:22:31.110529 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8271 01:22:31.113953 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8272 01:22:31.117254 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8273 01:22:31.123758 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8274 01:22:31.127190 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8275 01:22:31.127270 ==
8276 01:22:31.130557 Dram Type= 6, Freq= 0, CH_0, rank 1
8277 01:22:31.133629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8278 01:22:31.133714 ==
8279 01:22:31.137466 DQS Delay:
8280 01:22:31.137577 DQS0 = 0, DQS1 = 0
8281 01:22:31.137643 DQM Delay:
8282 01:22:31.140663 DQM0 = 124, DQM1 = 118
8283 01:22:31.140735 DQ Delay:
8284 01:22:31.143793 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8285 01:22:31.147017 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8286 01:22:31.150235 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
8287 01:22:31.156969 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8288 01:22:31.157061
8289 01:22:31.157128
8290 01:22:31.157188
8291 01:22:31.160703 [DramC_TX_OE_Calibration] TA2
8292 01:22:31.160796 Original DQ_B0 (3 6) =30, OEN = 27
8293 01:22:31.163604 Original DQ_B1 (3 6) =30, OEN = 27
8294 01:22:31.166988 24, 0x0, End_B0=24 End_B1=24
8295 01:22:31.170436 25, 0x0, End_B0=25 End_B1=25
8296 01:22:31.173858 26, 0x0, End_B0=26 End_B1=26
8297 01:22:31.176950 27, 0x0, End_B0=27 End_B1=27
8298 01:22:31.177029 28, 0x0, End_B0=28 End_B1=28
8299 01:22:31.180063 29, 0x0, End_B0=29 End_B1=29
8300 01:22:31.183466 30, 0x0, End_B0=30 End_B1=30
8301 01:22:31.187265 31, 0x5151, End_B0=30 End_B1=30
8302 01:22:31.190107 Byte0 end_step=30 best_step=27
8303 01:22:31.190186 Byte1 end_step=30 best_step=27
8304 01:22:31.193298 Byte0 TX OE(2T, 0.5T) = (3, 3)
8305 01:22:31.196854 Byte1 TX OE(2T, 0.5T) = (3, 3)
8306 01:22:31.196939
8307 01:22:31.197032
8308 01:22:31.206656 [DQSOSCAuto] RK1, (LSB)MR18= 0x2310, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8309 01:22:31.206757 CH0 RK1: MR19=303, MR18=2310
8310 01:22:31.213384 CH0_RK1: MR19=0x303, MR18=0x2310, DQSOSC=392, MR23=63, INC=24, DEC=16
8311 01:22:31.216863 [RxdqsGatingPostProcess] freq 1600
8312 01:22:31.223296 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8313 01:22:31.226109 best DQS0 dly(2T, 0.5T) = (1, 1)
8314 01:22:31.229452 best DQS1 dly(2T, 0.5T) = (1, 1)
8315 01:22:31.232851 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8316 01:22:31.236182 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8317 01:22:31.239488 best DQS0 dly(2T, 0.5T) = (1, 1)
8318 01:22:31.239571 best DQS1 dly(2T, 0.5T) = (1, 1)
8319 01:22:31.243367 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8320 01:22:31.246397 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8321 01:22:31.249981 Pre-setting of DQS Precalculation
8322 01:22:31.256063 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8323 01:22:31.256180 ==
8324 01:22:31.259744 Dram Type= 6, Freq= 0, CH_1, rank 0
8325 01:22:31.262908 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8326 01:22:31.263010 ==
8327 01:22:31.269663 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8328 01:22:31.273234 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8329 01:22:31.276191 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8330 01:22:31.282939 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8331 01:22:31.291988 [CA 0] Center 41 (12~70) winsize 59
8332 01:22:31.295181 [CA 1] Center 42 (12~72) winsize 61
8333 01:22:31.298484 [CA 2] Center 37 (8~66) winsize 59
8334 01:22:31.302047 [CA 3] Center 37 (8~66) winsize 59
8335 01:22:31.305064 [CA 4] Center 37 (8~67) winsize 60
8336 01:22:31.308134 [CA 5] Center 36 (6~66) winsize 61
8337 01:22:31.308234
8338 01:22:31.311808 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8339 01:22:31.311887
8340 01:22:31.314713 [CATrainingPosCal] consider 1 rank data
8341 01:22:31.318193 u2DelayCellTimex100 = 258/100 ps
8342 01:22:31.325021 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8343 01:22:31.328155 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8344 01:22:31.331543 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8345 01:22:31.334429 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8346 01:22:31.337770 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8347 01:22:31.341011 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8348 01:22:31.341113
8349 01:22:31.344604 CA PerBit enable=1, Macro0, CA PI delay=36
8350 01:22:31.344681
8351 01:22:31.347697 [CBTSetCACLKResult] CA Dly = 36
8352 01:22:31.351442 CS Dly: 10 (0~41)
8353 01:22:31.354630 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8354 01:22:31.357859 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8355 01:22:31.357940 ==
8356 01:22:31.361057 Dram Type= 6, Freq= 0, CH_1, rank 1
8357 01:22:31.368044 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8358 01:22:31.368191 ==
8359 01:22:31.370892 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8360 01:22:31.374529 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8361 01:22:31.381083 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8362 01:22:31.387927 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8363 01:22:31.395153 [CA 0] Center 41 (12~71) winsize 60
8364 01:22:31.398195 [CA 1] Center 42 (12~72) winsize 61
8365 01:22:31.402181 [CA 2] Center 37 (8~67) winsize 60
8366 01:22:31.404888 [CA 3] Center 36 (7~66) winsize 60
8367 01:22:31.408406 [CA 4] Center 37 (8~67) winsize 60
8368 01:22:31.411716 [CA 5] Center 36 (6~66) winsize 61
8369 01:22:31.411827
8370 01:22:31.414934 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8371 01:22:31.415015
8372 01:22:31.418048 [CATrainingPosCal] consider 2 rank data
8373 01:22:31.421731 u2DelayCellTimex100 = 258/100 ps
8374 01:22:31.428421 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8375 01:22:31.431577 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8376 01:22:31.435242 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8377 01:22:31.438244 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8378 01:22:31.441332 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8379 01:22:31.444786 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8380 01:22:31.444881
8381 01:22:31.448344 CA PerBit enable=1, Macro0, CA PI delay=36
8382 01:22:31.448448
8383 01:22:31.451251 [CBTSetCACLKResult] CA Dly = 36
8384 01:22:31.454636 CS Dly: 11 (0~43)
8385 01:22:31.458021 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8386 01:22:31.461306 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8387 01:22:31.461422
8388 01:22:31.464411 ----->DramcWriteLeveling(PI) begin...
8389 01:22:31.464515 ==
8390 01:22:31.467745 Dram Type= 6, Freq= 0, CH_1, rank 0
8391 01:22:31.474518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8392 01:22:31.474610 ==
8393 01:22:31.477588 Write leveling (Byte 0): 25 => 25
8394 01:22:31.477693 Write leveling (Byte 1): 29 => 29
8395 01:22:31.481305 DramcWriteLeveling(PI) end<-----
8396 01:22:31.481415
8397 01:22:31.484233 ==
8398 01:22:31.484327 Dram Type= 6, Freq= 0, CH_1, rank 0
8399 01:22:31.490969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8400 01:22:31.491088 ==
8401 01:22:31.494366 [Gating] SW mode calibration
8402 01:22:31.501149 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8403 01:22:31.504500 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8404 01:22:31.510981 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 01:22:31.514551 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 01:22:31.517891 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 01:22:31.523994 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 01:22:31.527498 1 4 16 | B1->B0 | 3232 3433 | 0 1 | (1 1) (1 1)
8409 01:22:31.531030 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8410 01:22:31.537092 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8411 01:22:31.540649 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8412 01:22:31.543670 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8413 01:22:31.550235 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8414 01:22:31.553943 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8415 01:22:31.557068 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8416 01:22:31.563655 1 5 16 | B1->B0 | 2f2f 2b2b | 1 1 | (1 1) (1 0)
8417 01:22:31.567218 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 01:22:31.570601 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8419 01:22:31.577187 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 01:22:31.580103 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 01:22:31.583816 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 01:22:31.590114 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8423 01:22:31.593966 1 6 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8424 01:22:31.596947 1 6 16 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
8425 01:22:31.603982 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8426 01:22:31.607261 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 01:22:31.610230 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8428 01:22:31.616687 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 01:22:31.620258 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 01:22:31.623679 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8431 01:22:31.629803 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8432 01:22:31.633401 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8433 01:22:31.636931 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 01:22:31.643149 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 01:22:31.646990 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 01:22:31.649835 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 01:22:31.653392 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 01:22:31.660092 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 01:22:31.663251 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 01:22:31.666268 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 01:22:31.673344 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 01:22:31.676380 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 01:22:31.680034 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 01:22:31.686090 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 01:22:31.689963 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 01:22:31.692832 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 01:22:31.699338 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8448 01:22:31.702801 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8449 01:22:31.706297 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8450 01:22:31.709282 Total UI for P1: 0, mck2ui 16
8451 01:22:31.712868 best dqsien dly found for B0: ( 1, 9, 14)
8452 01:22:31.719747 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8453 01:22:31.719859 Total UI for P1: 0, mck2ui 16
8454 01:22:31.725979 best dqsien dly found for B1: ( 1, 9, 18)
8455 01:22:31.729471 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8456 01:22:31.732410 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8457 01:22:31.732514
8458 01:22:31.736265 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8459 01:22:31.739297 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8460 01:22:31.742770 [Gating] SW calibration Done
8461 01:22:31.742863 ==
8462 01:22:31.745877 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 01:22:31.749386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 01:22:31.749493 ==
8465 01:22:31.752413 RX Vref Scan: 0
8466 01:22:31.752517
8467 01:22:31.755867 RX Vref 0 -> 0, step: 1
8468 01:22:31.755977
8469 01:22:31.756077 RX Delay 0 -> 252, step: 8
8470 01:22:31.762395 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8471 01:22:31.765473 iDelay=208, Bit 1, Center 127 (64 ~ 191) 128
8472 01:22:31.769011 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8473 01:22:31.772136 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8474 01:22:31.775951 iDelay=208, Bit 4, Center 127 (72 ~ 183) 112
8475 01:22:31.782523 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8476 01:22:31.785503 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8477 01:22:31.789110 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8478 01:22:31.792080 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8479 01:22:31.795669 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8480 01:22:31.801916 iDelay=208, Bit 10, Center 123 (72 ~ 175) 104
8481 01:22:31.805256 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8482 01:22:31.809138 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8483 01:22:31.812479 iDelay=208, Bit 13, Center 131 (72 ~ 191) 120
8484 01:22:31.815533 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8485 01:22:31.822426 iDelay=208, Bit 15, Center 131 (72 ~ 191) 120
8486 01:22:31.822516 ==
8487 01:22:31.825259 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 01:22:31.828562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 01:22:31.828674 ==
8490 01:22:31.828784 DQS Delay:
8491 01:22:31.832195 DQS0 = 0, DQS1 = 0
8492 01:22:31.832285 DQM Delay:
8493 01:22:31.835389 DQM0 = 132, DQM1 = 125
8494 01:22:31.835474 DQ Delay:
8495 01:22:31.838835 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8496 01:22:31.841814 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =131
8497 01:22:31.845001 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8498 01:22:31.848356 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =131
8499 01:22:31.851792
8500 01:22:31.851871
8501 01:22:31.851935 ==
8502 01:22:31.854986 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 01:22:31.858564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8504 01:22:31.858668 ==
8505 01:22:31.858734
8506 01:22:31.858795
8507 01:22:31.861641 TX Vref Scan disable
8508 01:22:31.861740 == TX Byte 0 ==
8509 01:22:31.868407 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8510 01:22:31.871526 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8511 01:22:31.871641 == TX Byte 1 ==
8512 01:22:31.878180 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8513 01:22:31.881236 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8514 01:22:31.881316 ==
8515 01:22:31.884719 Dram Type= 6, Freq= 0, CH_1, rank 0
8516 01:22:31.888284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8517 01:22:31.888370 ==
8518 01:22:31.902733
8519 01:22:31.906378 TX Vref early break, caculate TX vref
8520 01:22:31.909395 TX Vref=16, minBit 11, minWin=20, winSum=366
8521 01:22:31.912942 TX Vref=18, minBit 11, minWin=21, winSum=370
8522 01:22:31.916265 TX Vref=20, minBit 11, minWin=22, winSum=382
8523 01:22:31.919120 TX Vref=22, minBit 11, minWin=22, winSum=394
8524 01:22:31.925610 TX Vref=24, minBit 13, minWin=23, winSum=401
8525 01:22:31.929328 TX Vref=26, minBit 12, minWin=24, winSum=412
8526 01:22:31.932483 TX Vref=28, minBit 11, minWin=24, winSum=415
8527 01:22:31.935562 TX Vref=30, minBit 0, minWin=25, winSum=413
8528 01:22:31.939242 TX Vref=32, minBit 9, minWin=24, winSum=406
8529 01:22:31.945384 TX Vref=34, minBit 9, minWin=23, winSum=396
8530 01:22:31.948834 TX Vref=36, minBit 6, minWin=23, winSum=385
8531 01:22:31.952272 [TxChooseVref] Worse bit 0, Min win 25, Win sum 413, Final Vref 30
8532 01:22:31.952393
8533 01:22:31.955742 Final TX Range 0 Vref 30
8534 01:22:31.955860
8535 01:22:31.955956 ==
8536 01:22:31.959244 Dram Type= 6, Freq= 0, CH_1, rank 0
8537 01:22:31.966009 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8538 01:22:31.966094 ==
8539 01:22:31.966161
8540 01:22:31.966223
8541 01:22:31.966282 TX Vref Scan disable
8542 01:22:31.972679 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8543 01:22:31.972765 == TX Byte 0 ==
8544 01:22:31.976374 u2DelayCellOfst[0]=18 cells (5 PI)
8545 01:22:31.979483 u2DelayCellOfst[1]=15 cells (4 PI)
8546 01:22:31.982611 u2DelayCellOfst[2]=0 cells (0 PI)
8547 01:22:31.985757 u2DelayCellOfst[3]=7 cells (2 PI)
8548 01:22:31.989129 u2DelayCellOfst[4]=11 cells (3 PI)
8549 01:22:31.992579 u2DelayCellOfst[5]=22 cells (6 PI)
8550 01:22:31.996000 u2DelayCellOfst[6]=22 cells (6 PI)
8551 01:22:31.999045 u2DelayCellOfst[7]=7 cells (2 PI)
8552 01:22:32.002634 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8553 01:22:32.005818 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8554 01:22:32.009206 == TX Byte 1 ==
8555 01:22:32.012174 u2DelayCellOfst[8]=0 cells (0 PI)
8556 01:22:32.016013 u2DelayCellOfst[9]=3 cells (1 PI)
8557 01:22:32.018889 u2DelayCellOfst[10]=15 cells (4 PI)
8558 01:22:32.022474 u2DelayCellOfst[11]=7 cells (2 PI)
8559 01:22:32.025452 u2DelayCellOfst[12]=15 cells (4 PI)
8560 01:22:32.025542 u2DelayCellOfst[13]=18 cells (5 PI)
8561 01:22:32.029234 u2DelayCellOfst[14]=18 cells (5 PI)
8562 01:22:32.032229 u2DelayCellOfst[15]=18 cells (5 PI)
8563 01:22:32.039006 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8564 01:22:32.042256 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8565 01:22:32.042343 DramC Write-DBI on
8566 01:22:32.045524 ==
8567 01:22:32.048888 Dram Type= 6, Freq= 0, CH_1, rank 0
8568 01:22:32.052104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8569 01:22:32.052193 ==
8570 01:22:32.052262
8571 01:22:32.052340
8572 01:22:32.055588 TX Vref Scan disable
8573 01:22:32.055720 == TX Byte 0 ==
8574 01:22:32.061776 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8575 01:22:32.061869 == TX Byte 1 ==
8576 01:22:32.065183 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8577 01:22:32.068770 DramC Write-DBI off
8578 01:22:32.068874
8579 01:22:32.068981 [DATLAT]
8580 01:22:32.071661 Freq=1600, CH1 RK0
8581 01:22:32.071773
8582 01:22:32.071867 DATLAT Default: 0xf
8583 01:22:32.075357 0, 0xFFFF, sum = 0
8584 01:22:32.075469 1, 0xFFFF, sum = 0
8585 01:22:32.078458 2, 0xFFFF, sum = 0
8586 01:22:32.078545 3, 0xFFFF, sum = 0
8587 01:22:32.081485 4, 0xFFFF, sum = 0
8588 01:22:32.081597 5, 0xFFFF, sum = 0
8589 01:22:32.085039 6, 0xFFFF, sum = 0
8590 01:22:32.088107 7, 0xFFFF, sum = 0
8591 01:22:32.088215 8, 0xFFFF, sum = 0
8592 01:22:32.091723 9, 0xFFFF, sum = 0
8593 01:22:32.091836 10, 0xFFFF, sum = 0
8594 01:22:32.095189 11, 0xFFFF, sum = 0
8595 01:22:32.095271 12, 0xFFFF, sum = 0
8596 01:22:32.098165 13, 0x8FFF, sum = 0
8597 01:22:32.098245 14, 0x0, sum = 1
8598 01:22:32.101432 15, 0x0, sum = 2
8599 01:22:32.101521 16, 0x0, sum = 3
8600 01:22:32.104976 17, 0x0, sum = 4
8601 01:22:32.105058 best_step = 15
8602 01:22:32.105123
8603 01:22:32.105213 ==
8604 01:22:32.108038 Dram Type= 6, Freq= 0, CH_1, rank 0
8605 01:22:32.111610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8606 01:22:32.115120 ==
8607 01:22:32.115204 RX Vref Scan: 1
8608 01:22:32.115271
8609 01:22:32.118254 Set Vref Range= 24 -> 127
8610 01:22:32.118330
8611 01:22:32.121318 RX Vref 24 -> 127, step: 1
8612 01:22:32.121402
8613 01:22:32.121468 RX Delay 11 -> 252, step: 4
8614 01:22:32.121542
8615 01:22:32.124726 Set Vref, RX VrefLevel [Byte0]: 24
8616 01:22:32.128214 [Byte1]: 24
8617 01:22:32.132051
8618 01:22:32.132139 Set Vref, RX VrefLevel [Byte0]: 25
8619 01:22:32.135179 [Byte1]: 25
8620 01:22:32.139311
8621 01:22:32.139394 Set Vref, RX VrefLevel [Byte0]: 26
8622 01:22:32.142961 [Byte1]: 26
8623 01:22:32.147084
8624 01:22:32.147167 Set Vref, RX VrefLevel [Byte0]: 27
8625 01:22:32.150384 [Byte1]: 27
8626 01:22:32.154986
8627 01:22:32.155069 Set Vref, RX VrefLevel [Byte0]: 28
8628 01:22:32.157656 [Byte1]: 28
8629 01:22:32.162082
8630 01:22:32.162245 Set Vref, RX VrefLevel [Byte0]: 29
8631 01:22:32.165406 [Byte1]: 29
8632 01:22:32.169795
8633 01:22:32.169971 Set Vref, RX VrefLevel [Byte0]: 30
8634 01:22:32.173401 [Byte1]: 30
8635 01:22:32.177399
8636 01:22:32.177605 Set Vref, RX VrefLevel [Byte0]: 31
8637 01:22:32.180800 [Byte1]: 31
8638 01:22:32.185110
8639 01:22:32.185275 Set Vref, RX VrefLevel [Byte0]: 32
8640 01:22:32.188823 [Byte1]: 32
8641 01:22:32.192485
8642 01:22:32.192606 Set Vref, RX VrefLevel [Byte0]: 33
8643 01:22:32.196127 [Byte1]: 33
8644 01:22:32.200397
8645 01:22:32.200522 Set Vref, RX VrefLevel [Byte0]: 34
8646 01:22:32.203874 [Byte1]: 34
8647 01:22:32.207826
8648 01:22:32.207951 Set Vref, RX VrefLevel [Byte0]: 35
8649 01:22:32.211451 [Byte1]: 35
8650 01:22:32.215345
8651 01:22:32.215473 Set Vref, RX VrefLevel [Byte0]: 36
8652 01:22:32.219026 [Byte1]: 36
8653 01:22:32.223065
8654 01:22:32.223194 Set Vref, RX VrefLevel [Byte0]: 37
8655 01:22:32.226699 [Byte1]: 37
8656 01:22:32.230831
8657 01:22:32.230962 Set Vref, RX VrefLevel [Byte0]: 38
8658 01:22:32.234404 [Byte1]: 38
8659 01:22:32.238695
8660 01:22:32.238790 Set Vref, RX VrefLevel [Byte0]: 39
8661 01:22:32.241748 [Byte1]: 39
8662 01:22:32.246018
8663 01:22:32.246113 Set Vref, RX VrefLevel [Byte0]: 40
8664 01:22:32.249576 [Byte1]: 40
8665 01:22:32.253707
8666 01:22:32.253795 Set Vref, RX VrefLevel [Byte0]: 41
8667 01:22:32.256760 [Byte1]: 41
8668 01:22:32.261335
8669 01:22:32.261451 Set Vref, RX VrefLevel [Byte0]: 42
8670 01:22:32.264767 [Byte1]: 42
8671 01:22:32.268848
8672 01:22:32.268931 Set Vref, RX VrefLevel [Byte0]: 43
8673 01:22:32.272050 [Byte1]: 43
8674 01:22:32.276774
8675 01:22:32.276915 Set Vref, RX VrefLevel [Byte0]: 44
8676 01:22:32.280174 [Byte1]: 44
8677 01:22:32.283866
8678 01:22:32.283980 Set Vref, RX VrefLevel [Byte0]: 45
8679 01:22:32.287518 [Byte1]: 45
8680 01:22:32.291525
8681 01:22:32.291652 Set Vref, RX VrefLevel [Byte0]: 46
8682 01:22:32.295088 [Byte1]: 46
8683 01:22:32.299191
8684 01:22:32.299314 Set Vref, RX VrefLevel [Byte0]: 47
8685 01:22:32.302312 [Byte1]: 47
8686 01:22:32.306589
8687 01:22:32.306720 Set Vref, RX VrefLevel [Byte0]: 48
8688 01:22:32.310197 [Byte1]: 48
8689 01:22:32.314312
8690 01:22:32.314439 Set Vref, RX VrefLevel [Byte0]: 49
8691 01:22:32.317816 [Byte1]: 49
8692 01:22:32.322066
8693 01:22:32.322171 Set Vref, RX VrefLevel [Byte0]: 50
8694 01:22:32.325390 [Byte1]: 50
8695 01:22:32.329626
8696 01:22:32.329712 Set Vref, RX VrefLevel [Byte0]: 51
8697 01:22:32.333208 [Byte1]: 51
8698 01:22:32.337313
8699 01:22:32.337396 Set Vref, RX VrefLevel [Byte0]: 52
8700 01:22:32.340432 [Byte1]: 52
8701 01:22:32.344817
8702 01:22:32.344901 Set Vref, RX VrefLevel [Byte0]: 53
8703 01:22:32.348417 [Byte1]: 53
8704 01:22:32.352614
8705 01:22:32.352698 Set Vref, RX VrefLevel [Byte0]: 54
8706 01:22:32.356112 [Byte1]: 54
8707 01:22:32.360384
8708 01:22:32.360496 Set Vref, RX VrefLevel [Byte0]: 55
8709 01:22:32.363435 [Byte1]: 55
8710 01:22:32.367996
8711 01:22:32.368108 Set Vref, RX VrefLevel [Byte0]: 56
8712 01:22:32.370884 [Byte1]: 56
8713 01:22:32.375184
8714 01:22:32.375296 Set Vref, RX VrefLevel [Byte0]: 57
8715 01:22:32.378716 [Byte1]: 57
8716 01:22:32.383135
8717 01:22:32.383251 Set Vref, RX VrefLevel [Byte0]: 58
8718 01:22:32.386063 [Byte1]: 58
8719 01:22:32.390367
8720 01:22:32.390445 Set Vref, RX VrefLevel [Byte0]: 59
8721 01:22:32.393682 [Byte1]: 59
8722 01:22:32.398317
8723 01:22:32.398406 Set Vref, RX VrefLevel [Byte0]: 60
8724 01:22:32.401528 [Byte1]: 60
8725 01:22:32.405965
8726 01:22:32.406047 Set Vref, RX VrefLevel [Byte0]: 61
8727 01:22:32.409301 [Byte1]: 61
8728 01:22:32.413206
8729 01:22:32.413316 Set Vref, RX VrefLevel [Byte0]: 62
8730 01:22:32.416927 [Byte1]: 62
8731 01:22:32.421232
8732 01:22:32.421347 Set Vref, RX VrefLevel [Byte0]: 63
8733 01:22:32.424119 [Byte1]: 63
8734 01:22:32.428627
8735 01:22:32.428735 Set Vref, RX VrefLevel [Byte0]: 64
8736 01:22:32.432018 [Byte1]: 64
8737 01:22:32.436385
8738 01:22:32.436498 Set Vref, RX VrefLevel [Byte0]: 65
8739 01:22:32.439708 [Byte1]: 65
8740 01:22:32.443776
8741 01:22:32.443866 Set Vref, RX VrefLevel [Byte0]: 66
8742 01:22:32.446887 [Byte1]: 66
8743 01:22:32.451397
8744 01:22:32.451504 Set Vref, RX VrefLevel [Byte0]: 67
8745 01:22:32.454909 [Byte1]: 67
8746 01:22:32.459174
8747 01:22:32.459288 Set Vref, RX VrefLevel [Byte0]: 68
8748 01:22:32.462139 [Byte1]: 68
8749 01:22:32.466492
8750 01:22:32.466604 Set Vref, RX VrefLevel [Byte0]: 69
8751 01:22:32.470020 [Byte1]: 69
8752 01:22:32.474120
8753 01:22:32.474207 Set Vref, RX VrefLevel [Byte0]: 70
8754 01:22:32.477597 [Byte1]: 70
8755 01:22:32.481879
8756 01:22:32.481956 Set Vref, RX VrefLevel [Byte0]: 71
8757 01:22:32.484953 [Byte1]: 71
8758 01:22:32.489968
8759 01:22:32.490055 Final RX Vref Byte 0 = 56 to rank0
8760 01:22:32.493037 Final RX Vref Byte 1 = 52 to rank0
8761 01:22:32.495990 Final RX Vref Byte 0 = 56 to rank1
8762 01:22:32.499510 Final RX Vref Byte 1 = 52 to rank1==
8763 01:22:32.503025 Dram Type= 6, Freq= 0, CH_1, rank 0
8764 01:22:32.509525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8765 01:22:32.509625 ==
8766 01:22:32.509693 DQS Delay:
8767 01:22:32.512647 DQS0 = 0, DQS1 = 0
8768 01:22:32.512734 DQM Delay:
8769 01:22:32.512800 DQM0 = 131, DQM1 = 122
8770 01:22:32.516099 DQ Delay:
8771 01:22:32.519472 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =128
8772 01:22:32.522821 DQ4 =128, DQ5 =140, DQ6 =142, DQ7 =126
8773 01:22:32.526099 DQ8 =106, DQ9 =112, DQ10 =122, DQ11 =114
8774 01:22:32.529054 DQ12 =132, DQ13 =130, DQ14 =132, DQ15 =132
8775 01:22:32.529166
8776 01:22:32.529261
8777 01:22:32.529360
8778 01:22:32.532629 [DramC_TX_OE_Calibration] TA2
8779 01:22:32.535659 Original DQ_B0 (3 6) =30, OEN = 27
8780 01:22:32.539389 Original DQ_B1 (3 6) =30, OEN = 27
8781 01:22:32.542243 24, 0x0, End_B0=24 End_B1=24
8782 01:22:32.542350 25, 0x0, End_B0=25 End_B1=25
8783 01:22:32.545478 26, 0x0, End_B0=26 End_B1=26
8784 01:22:32.548889 27, 0x0, End_B0=27 End_B1=27
8785 01:22:32.552227 28, 0x0, End_B0=28 End_B1=28
8786 01:22:32.555840 29, 0x0, End_B0=29 End_B1=29
8787 01:22:32.555924 30, 0x0, End_B0=30 End_B1=30
8788 01:22:32.559032 31, 0x4141, End_B0=30 End_B1=30
8789 01:22:32.562517 Byte0 end_step=30 best_step=27
8790 01:22:32.565722 Byte1 end_step=30 best_step=27
8791 01:22:32.568868 Byte0 TX OE(2T, 0.5T) = (3, 3)
8792 01:22:32.571753 Byte1 TX OE(2T, 0.5T) = (3, 3)
8793 01:22:32.571839
8794 01:22:32.571906
8795 01:22:32.578807 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
8796 01:22:32.582001 CH1 RK0: MR19=303, MR18=A0F
8797 01:22:32.588626 CH1_RK0: MR19=0x303, MR18=0xA0F, DQSOSC=402, MR23=63, INC=22, DEC=15
8798 01:22:32.588745
8799 01:22:32.591817 ----->DramcWriteLeveling(PI) begin...
8800 01:22:32.591930 ==
8801 01:22:32.594968 Dram Type= 6, Freq= 0, CH_1, rank 1
8802 01:22:32.598528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8803 01:22:32.598616 ==
8804 01:22:32.601662 Write leveling (Byte 0): 23 => 23
8805 01:22:32.605108 Write leveling (Byte 1): 26 => 26
8806 01:22:32.608302 DramcWriteLeveling(PI) end<-----
8807 01:22:32.608379
8808 01:22:32.608453 ==
8809 01:22:32.611758 Dram Type= 6, Freq= 0, CH_1, rank 1
8810 01:22:32.615375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8811 01:22:32.615477 ==
8812 01:22:32.618536 [Gating] SW mode calibration
8813 01:22:32.625096 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8814 01:22:32.631539 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8815 01:22:32.634938 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8816 01:22:32.641376 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 01:22:32.644965 1 4 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8818 01:22:32.647976 1 4 12 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8819 01:22:32.655101 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8820 01:22:32.658101 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8821 01:22:32.661310 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8822 01:22:32.668384 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8823 01:22:32.671342 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8824 01:22:32.674989 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8825 01:22:32.681274 1 5 8 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (1 0)
8826 01:22:32.684694 1 5 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (1 0)
8827 01:22:32.688120 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8828 01:22:32.694669 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 01:22:32.697646 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 01:22:32.701288 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8831 01:22:32.707992 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8832 01:22:32.710787 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 01:22:32.714632 1 6 8 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8834 01:22:32.720704 1 6 12 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
8835 01:22:32.724208 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 01:22:32.727752 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8837 01:22:32.734027 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8838 01:22:32.737063 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8839 01:22:32.740632 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8840 01:22:32.747583 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8841 01:22:32.750321 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8842 01:22:32.753735 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8843 01:22:32.757462 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8844 01:22:32.763736 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 01:22:32.767410 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 01:22:32.770169 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 01:22:32.776965 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 01:22:32.780529 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 01:22:32.783700 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 01:22:32.790545 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 01:22:32.793588 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 01:22:32.797087 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 01:22:32.803606 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 01:22:32.806780 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 01:22:32.810317 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 01:22:32.816977 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8857 01:22:32.820022 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8858 01:22:32.823533 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8859 01:22:32.830200 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8860 01:22:32.833073 Total UI for P1: 0, mck2ui 16
8861 01:22:32.836782 best dqsien dly found for B0: ( 1, 9, 8)
8862 01:22:32.836869 Total UI for P1: 0, mck2ui 16
8863 01:22:32.843134 best dqsien dly found for B1: ( 1, 9, 12)
8864 01:22:32.846725 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8865 01:22:32.850202 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8866 01:22:32.850287
8867 01:22:32.853210 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8868 01:22:32.856699 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8869 01:22:32.859536 [Gating] SW calibration Done
8870 01:22:32.859624 ==
8871 01:22:32.863203 Dram Type= 6, Freq= 0, CH_1, rank 1
8872 01:22:32.866584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8873 01:22:32.866671 ==
8874 01:22:32.869694 RX Vref Scan: 0
8875 01:22:32.869778
8876 01:22:32.869845 RX Vref 0 -> 0, step: 1
8877 01:22:32.873220
8878 01:22:32.873336 RX Delay 0 -> 252, step: 8
8879 01:22:32.879914 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8880 01:22:32.882813 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8881 01:22:32.886370 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8882 01:22:32.889377 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8883 01:22:32.893193 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8884 01:22:32.896333 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8885 01:22:32.902912 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8886 01:22:32.906292 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8887 01:22:32.909706 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8888 01:22:32.912606 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8889 01:22:32.916169 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8890 01:22:32.922654 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8891 01:22:32.926236 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8892 01:22:32.929318 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8893 01:22:32.933051 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8894 01:22:32.939082 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8895 01:22:32.939238 ==
8896 01:22:32.942760 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 01:22:32.946514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 01:22:32.946599 ==
8899 01:22:32.946667 DQS Delay:
8900 01:22:32.949475 DQS0 = 0, DQS1 = 0
8901 01:22:32.949595 DQM Delay:
8902 01:22:32.952538 DQM0 = 130, DQM1 = 127
8903 01:22:32.952643 DQ Delay:
8904 01:22:32.956096 DQ0 =135, DQ1 =127, DQ2 =115, DQ3 =131
8905 01:22:32.958898 DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =127
8906 01:22:32.962529 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8907 01:22:32.965578 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8908 01:22:32.965663
8909 01:22:32.969234
8910 01:22:32.969318 ==
8911 01:22:32.972230 Dram Type= 6, Freq= 0, CH_1, rank 1
8912 01:22:32.975507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8913 01:22:32.975593 ==
8914 01:22:32.975660
8915 01:22:32.975723
8916 01:22:32.978683 TX Vref Scan disable
8917 01:22:32.978769 == TX Byte 0 ==
8918 01:22:32.985794 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8919 01:22:32.988653 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8920 01:22:32.988739 == TX Byte 1 ==
8921 01:22:32.995293 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8922 01:22:32.999018 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8923 01:22:32.999101 ==
8924 01:22:33.002192 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 01:22:33.005327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 01:22:33.005408 ==
8927 01:22:33.019867
8928 01:22:33.023278 TX Vref early break, caculate TX vref
8929 01:22:33.026695 TX Vref=16, minBit 0, minWin=22, winSum=380
8930 01:22:33.029613 TX Vref=18, minBit 0, minWin=22, winSum=389
8931 01:22:33.033378 TX Vref=20, minBit 0, minWin=24, winSum=404
8932 01:22:33.036345 TX Vref=22, minBit 0, minWin=25, winSum=409
8933 01:22:33.039659 TX Vref=24, minBit 0, minWin=24, winSum=417
8934 01:22:33.046423 TX Vref=26, minBit 0, minWin=26, winSum=426
8935 01:22:33.049521 TX Vref=28, minBit 0, minWin=25, winSum=424
8936 01:22:33.052599 TX Vref=30, minBit 1, minWin=25, winSum=420
8937 01:22:33.056227 TX Vref=32, minBit 5, minWin=24, winSum=413
8938 01:22:33.059279 TX Vref=34, minBit 5, minWin=24, winSum=409
8939 01:22:33.065955 TX Vref=36, minBit 1, minWin=23, winSum=395
8940 01:22:33.069167 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 26
8941 01:22:33.069284
8942 01:22:33.072822 Final TX Range 0 Vref 26
8943 01:22:33.072908
8944 01:22:33.072975 ==
8945 01:22:33.075832 Dram Type= 6, Freq= 0, CH_1, rank 1
8946 01:22:33.079388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8947 01:22:33.082505 ==
8948 01:22:33.082590
8949 01:22:33.082657
8950 01:22:33.082719 TX Vref Scan disable
8951 01:22:33.088942 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8952 01:22:33.089028 == TX Byte 0 ==
8953 01:22:33.092378 u2DelayCellOfst[0]=15 cells (4 PI)
8954 01:22:33.095770 u2DelayCellOfst[1]=11 cells (3 PI)
8955 01:22:33.099177 u2DelayCellOfst[2]=0 cells (0 PI)
8956 01:22:33.102586 u2DelayCellOfst[3]=3 cells (1 PI)
8957 01:22:33.105414 u2DelayCellOfst[4]=7 cells (2 PI)
8958 01:22:33.109204 u2DelayCellOfst[5]=22 cells (6 PI)
8959 01:22:33.112191 u2DelayCellOfst[6]=18 cells (5 PI)
8960 01:22:33.115327 u2DelayCellOfst[7]=3 cells (1 PI)
8961 01:22:33.119037 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8962 01:22:33.121965 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8963 01:22:33.125384 == TX Byte 1 ==
8964 01:22:33.128810 u2DelayCellOfst[8]=0 cells (0 PI)
8965 01:22:33.132152 u2DelayCellOfst[9]=3 cells (1 PI)
8966 01:22:33.135406 u2DelayCellOfst[10]=11 cells (3 PI)
8967 01:22:33.138426 u2DelayCellOfst[11]=3 cells (1 PI)
8968 01:22:33.142118 u2DelayCellOfst[12]=15 cells (4 PI)
8969 01:22:33.142218 u2DelayCellOfst[13]=15 cells (4 PI)
8970 01:22:33.145763 u2DelayCellOfst[14]=18 cells (5 PI)
8971 01:22:33.148720 u2DelayCellOfst[15]=18 cells (5 PI)
8972 01:22:33.155500 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8973 01:22:33.158606 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8974 01:22:33.158693 DramC Write-DBI on
8975 01:22:33.162238 ==
8976 01:22:33.162322 Dram Type= 6, Freq= 0, CH_1, rank 1
8977 01:22:33.168980 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8978 01:22:33.169071 ==
8979 01:22:33.169138
8980 01:22:33.169199
8981 01:22:33.172060 TX Vref Scan disable
8982 01:22:33.172149 == TX Byte 0 ==
8983 01:22:33.178545 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8984 01:22:33.178631 == TX Byte 1 ==
8985 01:22:33.182244 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8986 01:22:33.185466 DramC Write-DBI off
8987 01:22:33.185590
8988 01:22:33.185689 [DATLAT]
8989 01:22:33.188798 Freq=1600, CH1 RK1
8990 01:22:33.188881
8991 01:22:33.188999 DATLAT Default: 0xf
8992 01:22:33.191811 0, 0xFFFF, sum = 0
8993 01:22:33.191896 1, 0xFFFF, sum = 0
8994 01:22:33.195267 2, 0xFFFF, sum = 0
8995 01:22:33.195351 3, 0xFFFF, sum = 0
8996 01:22:33.198291 4, 0xFFFF, sum = 0
8997 01:22:33.198376 5, 0xFFFF, sum = 0
8998 01:22:33.201701 6, 0xFFFF, sum = 0
8999 01:22:33.201785 7, 0xFFFF, sum = 0
9000 01:22:33.205117 8, 0xFFFF, sum = 0
9001 01:22:33.208447 9, 0xFFFF, sum = 0
9002 01:22:33.208558 10, 0xFFFF, sum = 0
9003 01:22:33.211988 11, 0xFFFF, sum = 0
9004 01:22:33.212072 12, 0xFFFF, sum = 0
9005 01:22:33.214965 13, 0x8FFF, sum = 0
9006 01:22:33.215048 14, 0x0, sum = 1
9007 01:22:33.218070 15, 0x0, sum = 2
9008 01:22:33.218153 16, 0x0, sum = 3
9009 01:22:33.221746 17, 0x0, sum = 4
9010 01:22:33.221829 best_step = 15
9011 01:22:33.221895
9012 01:22:33.221955 ==
9013 01:22:33.224720 Dram Type= 6, Freq= 0, CH_1, rank 1
9014 01:22:33.228352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9015 01:22:33.228435 ==
9016 01:22:33.231212 RX Vref Scan: 0
9017 01:22:33.231332
9018 01:22:33.234828 RX Vref 0 -> 0, step: 1
9019 01:22:33.234910
9020 01:22:33.234975 RX Delay 3 -> 252, step: 4
9021 01:22:33.241629 iDelay=195, Bit 0, Center 130 (75 ~ 186) 112
9022 01:22:33.245085 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
9023 01:22:33.248887 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
9024 01:22:33.251894 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
9025 01:22:33.258134 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
9026 01:22:33.261755 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
9027 01:22:33.265376 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
9028 01:22:33.268443 iDelay=195, Bit 7, Center 122 (67 ~ 178) 112
9029 01:22:33.271630 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
9030 01:22:33.274768 iDelay=195, Bit 9, Center 114 (59 ~ 170) 112
9031 01:22:33.281630 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9032 01:22:33.285067 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
9033 01:22:33.288391 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9034 01:22:33.291237 iDelay=195, Bit 13, Center 132 (75 ~ 190) 116
9035 01:22:33.298294 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9036 01:22:33.301238 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9037 01:22:33.301321 ==
9038 01:22:33.304853 Dram Type= 6, Freq= 0, CH_1, rank 1
9039 01:22:33.307727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9040 01:22:33.307813 ==
9041 01:22:33.311292 DQS Delay:
9042 01:22:33.311401 DQS0 = 0, DQS1 = 0
9043 01:22:33.311475 DQM Delay:
9044 01:22:33.314644 DQM0 = 127, DQM1 = 124
9045 01:22:33.314733 DQ Delay:
9046 01:22:33.317895 DQ0 =130, DQ1 =124, DQ2 =114, DQ3 =126
9047 01:22:33.321013 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =122
9048 01:22:33.328131 DQ8 =108, DQ9 =114, DQ10 =128, DQ11 =118
9049 01:22:33.331193 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =134
9050 01:22:33.331277
9051 01:22:33.331343
9052 01:22:33.331404
9053 01:22:33.334563 [DramC_TX_OE_Calibration] TA2
9054 01:22:33.337619 Original DQ_B0 (3 6) =30, OEN = 27
9055 01:22:33.341063 Original DQ_B1 (3 6) =30, OEN = 27
9056 01:22:33.341146 24, 0x0, End_B0=24 End_B1=24
9057 01:22:33.344155 25, 0x0, End_B0=25 End_B1=25
9058 01:22:33.347675 26, 0x0, End_B0=26 End_B1=26
9059 01:22:33.350599 27, 0x0, End_B0=27 End_B1=27
9060 01:22:33.350716 28, 0x0, End_B0=28 End_B1=28
9061 01:22:33.354166 29, 0x0, End_B0=29 End_B1=29
9062 01:22:33.357418 30, 0x0, End_B0=30 End_B1=30
9063 01:22:33.360519 31, 0x4141, End_B0=30 End_B1=30
9064 01:22:33.364185 Byte0 end_step=30 best_step=27
9065 01:22:33.367328 Byte1 end_step=30 best_step=27
9066 01:22:33.367418 Byte0 TX OE(2T, 0.5T) = (3, 3)
9067 01:22:33.370505 Byte1 TX OE(2T, 0.5T) = (3, 3)
9068 01:22:33.370590
9069 01:22:33.370655
9070 01:22:33.380527 [DQSOSCAuto] RK1, (LSB)MR18= 0xd1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
9071 01:22:33.383733 CH1 RK1: MR19=303, MR18=D1A
9072 01:22:33.387506 CH1_RK1: MR19=0x303, MR18=0xD1A, DQSOSC=396, MR23=63, INC=23, DEC=15
9073 01:22:33.390511 [RxdqsGatingPostProcess] freq 1600
9074 01:22:33.397339 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9075 01:22:33.400277 best DQS0 dly(2T, 0.5T) = (1, 1)
9076 01:22:33.403857 best DQS1 dly(2T, 0.5T) = (1, 1)
9077 01:22:33.407242 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9078 01:22:33.410103 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9079 01:22:33.413515 best DQS0 dly(2T, 0.5T) = (1, 1)
9080 01:22:33.413607 best DQS1 dly(2T, 0.5T) = (1, 1)
9081 01:22:33.417153 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9082 01:22:33.420300 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9083 01:22:33.423429 Pre-setting of DQS Precalculation
9084 01:22:33.430112 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9085 01:22:33.437049 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9086 01:22:33.443465 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9087 01:22:33.443545
9088 01:22:33.443609
9089 01:22:33.446979 [Calibration Summary] 3200 Mbps
9090 01:22:33.450159 CH 0, Rank 0
9091 01:22:33.450235 SW Impedance : PASS
9092 01:22:33.453122 DUTY Scan : NO K
9093 01:22:33.453194 ZQ Calibration : PASS
9094 01:22:33.456633 Jitter Meter : NO K
9095 01:22:33.460153 CBT Training : PASS
9096 01:22:33.460233 Write leveling : PASS
9097 01:22:33.463037 RX DQS gating : PASS
9098 01:22:33.466399 RX DQ/DQS(RDDQC) : PASS
9099 01:22:33.466487 TX DQ/DQS : PASS
9100 01:22:33.470144 RX DATLAT : PASS
9101 01:22:33.473267 RX DQ/DQS(Engine): PASS
9102 01:22:33.473348 TX OE : PASS
9103 01:22:33.476448 All Pass.
9104 01:22:33.476520
9105 01:22:33.476582 CH 0, Rank 1
9106 01:22:33.479651 SW Impedance : PASS
9107 01:22:33.479722 DUTY Scan : NO K
9108 01:22:33.483300 ZQ Calibration : PASS
9109 01:22:33.486544 Jitter Meter : NO K
9110 01:22:33.486640 CBT Training : PASS
9111 01:22:33.489634 Write leveling : PASS
9112 01:22:33.493359 RX DQS gating : PASS
9113 01:22:33.493439 RX DQ/DQS(RDDQC) : PASS
9114 01:22:33.496428 TX DQ/DQS : PASS
9115 01:22:33.499548 RX DATLAT : PASS
9116 01:22:33.499622 RX DQ/DQS(Engine): PASS
9117 01:22:33.503242 TX OE : PASS
9118 01:22:33.503318 All Pass.
9119 01:22:33.503380
9120 01:22:33.506210 CH 1, Rank 0
9121 01:22:33.506281 SW Impedance : PASS
9122 01:22:33.509429 DUTY Scan : NO K
9123 01:22:33.513080 ZQ Calibration : PASS
9124 01:22:33.513164 Jitter Meter : NO K
9125 01:22:33.516169 CBT Training : PASS
9126 01:22:33.519588 Write leveling : PASS
9127 01:22:33.519665 RX DQS gating : PASS
9128 01:22:33.522873 RX DQ/DQS(RDDQC) : PASS
9129 01:22:33.522950 TX DQ/DQS : PASS
9130 01:22:33.525805 RX DATLAT : PASS
9131 01:22:33.529052 RX DQ/DQS(Engine): PASS
9132 01:22:33.529126 TX OE : PASS
9133 01:22:33.532675 All Pass.
9134 01:22:33.532748
9135 01:22:33.532824 CH 1, Rank 1
9136 01:22:33.536042 SW Impedance : PASS
9137 01:22:33.536148 DUTY Scan : NO K
9138 01:22:33.538940 ZQ Calibration : PASS
9139 01:22:33.542530 Jitter Meter : NO K
9140 01:22:33.542604 CBT Training : PASS
9141 01:22:33.545706 Write leveling : PASS
9142 01:22:33.549076 RX DQS gating : PASS
9143 01:22:33.549181 RX DQ/DQS(RDDQC) : PASS
9144 01:22:33.552664 TX DQ/DQS : PASS
9145 01:22:33.555601 RX DATLAT : PASS
9146 01:22:33.555683 RX DQ/DQS(Engine): PASS
9147 01:22:33.559193 TX OE : PASS
9148 01:22:33.559272 All Pass.
9149 01:22:33.559335
9150 01:22:33.562090 DramC Write-DBI on
9151 01:22:33.565811 PER_BANK_REFRESH: Hybrid Mode
9152 01:22:33.565894 TX_TRACKING: ON
9153 01:22:33.575396 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9154 01:22:33.582104 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9155 01:22:33.588956 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9156 01:22:33.592072 [FAST_K] Save calibration result to emmc
9157 01:22:33.595157 sync common calibartion params.
9158 01:22:33.598977 sync cbt_mode0:1, 1:1
9159 01:22:33.601974 dram_init: ddr_geometry: 2
9160 01:22:33.602056 dram_init: ddr_geometry: 2
9161 01:22:33.605089 dram_init: ddr_geometry: 2
9162 01:22:33.608753 0:dram_rank_size:100000000
9163 01:22:33.611549 1:dram_rank_size:100000000
9164 01:22:33.615349 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9165 01:22:33.618462 DFS_SHUFFLE_HW_MODE: ON
9166 01:22:33.621648 dramc_set_vcore_voltage set vcore to 725000
9167 01:22:33.625325 Read voltage for 1600, 0
9168 01:22:33.625410 Vio18 = 0
9169 01:22:33.625475 Vcore = 725000
9170 01:22:33.628280 Vdram = 0
9171 01:22:33.628354 Vddq = 0
9172 01:22:33.628416 Vmddr = 0
9173 01:22:33.631820 switch to 3200 Mbps bootup
9174 01:22:33.635184 [DramcRunTimeConfig]
9175 01:22:33.635265 PHYPLL
9176 01:22:33.635329 DPM_CONTROL_AFTERK: ON
9177 01:22:33.638205 PER_BANK_REFRESH: ON
9178 01:22:33.641761 REFRESH_OVERHEAD_REDUCTION: ON
9179 01:22:33.641838 CMD_PICG_NEW_MODE: OFF
9180 01:22:33.644879 XRTWTW_NEW_MODE: ON
9181 01:22:33.648338 XRTRTR_NEW_MODE: ON
9182 01:22:33.648413 TX_TRACKING: ON
9183 01:22:33.651874 RDSEL_TRACKING: OFF
9184 01:22:33.651958 DQS Precalculation for DVFS: ON
9185 01:22:33.655039 RX_TRACKING: OFF
9186 01:22:33.655130 HW_GATING DBG: ON
9187 01:22:33.658389 ZQCS_ENABLE_LP4: ON
9188 01:22:33.661541 RX_PICG_NEW_MODE: ON
9189 01:22:33.661635 TX_PICG_NEW_MODE: ON
9190 01:22:33.664787 ENABLE_RX_DCM_DPHY: ON
9191 01:22:33.668131 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9192 01:22:33.668208 DUMMY_READ_FOR_TRACKING: OFF
9193 01:22:33.671179 !!! SPM_CONTROL_AFTERK: OFF
9194 01:22:33.674813 !!! SPM could not control APHY
9195 01:22:33.677936 IMPEDANCE_TRACKING: ON
9196 01:22:33.678042 TEMP_SENSOR: ON
9197 01:22:33.680908 HW_SAVE_FOR_SR: OFF
9198 01:22:33.684492 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9199 01:22:33.687543 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9200 01:22:33.687623 Read ODT Tracking: ON
9201 01:22:33.691229 Refresh Rate DeBounce: ON
9202 01:22:33.694195 DFS_NO_QUEUE_FLUSH: ON
9203 01:22:33.697899 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9204 01:22:33.697974 ENABLE_DFS_RUNTIME_MRW: OFF
9205 01:22:33.701027 DDR_RESERVE_NEW_MODE: ON
9206 01:22:33.704017 MR_CBT_SWITCH_FREQ: ON
9207 01:22:33.704132 =========================
9208 01:22:33.724307 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9209 01:22:33.727335 dram_init: ddr_geometry: 2
9210 01:22:33.745969 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9211 01:22:33.749051 dram_init: dram init end (result: 0)
9212 01:22:33.755763 DRAM-K: Full calibration passed in 24613 msecs
9213 01:22:33.758992 MRC: failed to locate region type 0.
9214 01:22:33.759078 DRAM rank0 size:0x100000000,
9215 01:22:33.762072 DRAM rank1 size=0x100000000
9216 01:22:33.772250 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9217 01:22:33.778987 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9218 01:22:33.785318 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9219 01:22:33.795537 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9220 01:22:33.795623 DRAM rank0 size:0x100000000,
9221 01:22:33.798549 DRAM rank1 size=0x100000000
9222 01:22:33.798631 CBMEM:
9223 01:22:33.801667 IMD: root @ 0xfffff000 254 entries.
9224 01:22:33.805402 IMD: root @ 0xffffec00 62 entries.
9225 01:22:33.808425 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9226 01:22:33.815258 WARNING: RO_VPD is uninitialized or empty.
9227 01:22:33.818291 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9228 01:22:33.825690 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9229 01:22:33.838469 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9230 01:22:33.850347 BS: romstage times (exec / console): total (unknown) / 24070 ms
9231 01:22:33.850431
9232 01:22:33.850497
9233 01:22:33.859823 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9234 01:22:33.863552 ARM64: Exception handlers installed.
9235 01:22:33.866675 ARM64: Testing exception
9236 01:22:33.869882 ARM64: Done test exception
9237 01:22:33.869954 Enumerating buses...
9238 01:22:33.873421 Show all devs... Before device enumeration.
9239 01:22:33.876427 Root Device: enabled 1
9240 01:22:33.879575 CPU_CLUSTER: 0: enabled 1
9241 01:22:33.879655 CPU: 00: enabled 1
9242 01:22:33.883120 Compare with tree...
9243 01:22:33.883199 Root Device: enabled 1
9244 01:22:33.886678 CPU_CLUSTER: 0: enabled 1
9245 01:22:33.889506 CPU: 00: enabled 1
9246 01:22:33.889620 Root Device scanning...
9247 01:22:33.893018 scan_static_bus for Root Device
9248 01:22:33.896447 CPU_CLUSTER: 0 enabled
9249 01:22:33.899964 scan_static_bus for Root Device done
9250 01:22:33.902979 scan_bus: bus Root Device finished in 8 msecs
9251 01:22:33.903056 done
9252 01:22:33.909570 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9253 01:22:33.912965 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9254 01:22:33.919658 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9255 01:22:33.922760 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9256 01:22:33.926336 Allocating resources...
9257 01:22:33.929346 Reading resources...
9258 01:22:33.933187 Root Device read_resources bus 0 link: 0
9259 01:22:33.933269 DRAM rank0 size:0x100000000,
9260 01:22:33.936159 DRAM rank1 size=0x100000000
9261 01:22:33.939087 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9262 01:22:33.943018 CPU: 00 missing read_resources
9263 01:22:33.948987 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9264 01:22:33.952649 Root Device read_resources bus 0 link: 0 done
9265 01:22:33.952758 Done reading resources.
9266 01:22:33.959585 Show resources in subtree (Root Device)...After reading.
9267 01:22:33.962591 Root Device child on link 0 CPU_CLUSTER: 0
9268 01:22:33.965775 CPU_CLUSTER: 0 child on link 0 CPU: 00
9269 01:22:33.975781 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9270 01:22:33.975863 CPU: 00
9271 01:22:33.978795 Root Device assign_resources, bus 0 link: 0
9272 01:22:33.982427 CPU_CLUSTER: 0 missing set_resources
9273 01:22:33.989030 Root Device assign_resources, bus 0 link: 0 done
9274 01:22:33.989112 Done setting resources.
9275 01:22:33.995739 Show resources in subtree (Root Device)...After assigning values.
9276 01:22:33.998664 Root Device child on link 0 CPU_CLUSTER: 0
9277 01:22:34.002169 CPU_CLUSTER: 0 child on link 0 CPU: 00
9278 01:22:34.012725 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9279 01:22:34.012808 CPU: 00
9280 01:22:34.015639 Done allocating resources.
9281 01:22:34.021968 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9282 01:22:34.022046 Enabling resources...
9283 01:22:34.022108 done.
9284 01:22:34.028681 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9285 01:22:34.031539 Initializing devices...
9286 01:22:34.031620 Root Device init
9287 01:22:34.035111 init hardware done!
9288 01:22:34.035191 0x00000018: ctrlr->caps
9289 01:22:34.038190 52.000 MHz: ctrlr->f_max
9290 01:22:34.041816 0.400 MHz: ctrlr->f_min
9291 01:22:34.041900 0x40ff8080: ctrlr->voltages
9292 01:22:34.045119 sclk: 390625
9293 01:22:34.045203 Bus Width = 1
9294 01:22:34.045269 sclk: 390625
9295 01:22:34.048650 Bus Width = 1
9296 01:22:34.048725 Early init status = 3
9297 01:22:34.054720 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9298 01:22:34.058519 in-header: 03 fc 00 00 01 00 00 00
9299 01:22:34.061487 in-data: 00
9300 01:22:34.064996 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9301 01:22:34.068964 in-header: 03 fd 00 00 00 00 00 00
9302 01:22:34.072098 in-data:
9303 01:22:34.075084 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9304 01:22:34.078822 in-header: 03 fc 00 00 01 00 00 00
9305 01:22:34.082326 in-data: 00
9306 01:22:34.085353 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9307 01:22:34.090356 in-header: 03 fd 00 00 00 00 00 00
9308 01:22:34.093540 in-data:
9309 01:22:34.096501 [SSUSB] Setting up USB HOST controller...
9310 01:22:34.100179 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9311 01:22:34.103156 [SSUSB] phy power-on done.
9312 01:22:34.106612 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9313 01:22:34.113301 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9314 01:22:34.116973 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9315 01:22:34.123171 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9316 01:22:34.130163 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9317 01:22:34.136567 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9318 01:22:34.143269 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9319 01:22:34.149801 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9320 01:22:34.152947 SPM: binary array size = 0x9dc
9321 01:22:34.156529 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9322 01:22:34.162703 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9323 01:22:34.169513 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9324 01:22:34.176232 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9325 01:22:34.179731 configure_display: Starting display init
9326 01:22:34.213645 anx7625_power_on_init: Init interface.
9327 01:22:34.216982 anx7625_disable_pd_protocol: Disabled PD feature.
9328 01:22:34.219999 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9329 01:22:34.247871 anx7625_start_dp_work: Secure OCM version=00
9330 01:22:34.250796 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9331 01:22:34.265605 sp_tx_get_edid_block: EDID Block = 1
9332 01:22:34.368317 Extracted contents:
9333 01:22:34.372097 header: 00 ff ff ff ff ff ff 00
9334 01:22:34.375212 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9335 01:22:34.378210 version: 01 04
9336 01:22:34.381335 basic params: 95 1f 11 78 0a
9337 01:22:34.385096 chroma info: 76 90 94 55 54 90 27 21 50 54
9338 01:22:34.387998 established: 00 00 00
9339 01:22:34.394873 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9340 01:22:34.401283 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9341 01:22:34.404473 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9342 01:22:34.411388 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9343 01:22:34.417623 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9344 01:22:34.421316 extensions: 00
9345 01:22:34.421421 checksum: fb
9346 01:22:34.421519
9347 01:22:34.427783 Manufacturer: IVO Model 57d Serial Number 0
9348 01:22:34.427859 Made week 0 of 2020
9349 01:22:34.430702 EDID version: 1.4
9350 01:22:34.430777 Digital display
9351 01:22:34.434469 6 bits per primary color channel
9352 01:22:34.434544 DisplayPort interface
9353 01:22:34.437427 Maximum image size: 31 cm x 17 cm
9354 01:22:34.441204 Gamma: 220%
9355 01:22:34.441312 Check DPMS levels
9356 01:22:34.447459 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9357 01:22:34.451122 First detailed timing is preferred timing
9358 01:22:34.451197 Established timings supported:
9359 01:22:34.454082 Standard timings supported:
9360 01:22:34.457185 Detailed timings
9361 01:22:34.460860 Hex of detail: 383680a07038204018303c0035ae10000019
9362 01:22:34.467425 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9363 01:22:34.470476 0780 0798 07c8 0820 hborder 0
9364 01:22:34.473959 0438 043b 0447 0458 vborder 0
9365 01:22:34.477373 -hsync -vsync
9366 01:22:34.477451 Did detailed timing
9367 01:22:34.484091 Hex of detail: 000000000000000000000000000000000000
9368 01:22:34.487055 Manufacturer-specified data, tag 0
9369 01:22:34.490940 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9370 01:22:34.493869 ASCII string: InfoVision
9371 01:22:34.497051 Hex of detail: 000000fe00523134304e574635205248200a
9372 01:22:34.500533 ASCII string: R140NWF5 RH
9373 01:22:34.500616 Checksum
9374 01:22:34.503449 Checksum: 0xfb (valid)
9375 01:22:34.507072 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9376 01:22:34.510328 DSI data_rate: 832800000 bps
9377 01:22:34.517242 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9378 01:22:34.520292 anx7625_parse_edid: pixelclock(138800).
9379 01:22:34.523457 hactive(1920), hsync(48), hfp(24), hbp(88)
9380 01:22:34.526916 vactive(1080), vsync(12), vfp(3), vbp(17)
9381 01:22:34.530106 anx7625_dsi_config: config dsi.
9382 01:22:34.536941 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9383 01:22:34.550398 anx7625_dsi_config: success to config DSI
9384 01:22:34.553939 anx7625_dp_start: MIPI phy setup OK.
9385 01:22:34.556936 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9386 01:22:34.560640 mtk_ddp_mode_set invalid vrefresh 60
9387 01:22:34.563789 main_disp_path_setup
9388 01:22:34.563882 ovl_layer_smi_id_en
9389 01:22:34.567280 ovl_layer_smi_id_en
9390 01:22:34.567355 ccorr_config
9391 01:22:34.567417 aal_config
9392 01:22:34.570434 gamma_config
9393 01:22:34.570509 postmask_config
9394 01:22:34.573774 dither_config
9395 01:22:34.577273 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9396 01:22:34.583335 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9397 01:22:34.586724 Root Device init finished in 551 msecs
9398 01:22:34.590182 CPU_CLUSTER: 0 init
9399 01:22:34.596487 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9400 01:22:34.600059 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9401 01:22:34.603601 APU_MBOX 0x190000b0 = 0x10001
9402 01:22:34.606499 APU_MBOX 0x190001b0 = 0x10001
9403 01:22:34.610007 APU_MBOX 0x190005b0 = 0x10001
9404 01:22:34.613193 APU_MBOX 0x190006b0 = 0x10001
9405 01:22:34.620028 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9406 01:22:34.629413 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9407 01:22:34.641828 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9408 01:22:34.648773 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9409 01:22:34.660284 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9410 01:22:34.669535 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9411 01:22:34.672473 CPU_CLUSTER: 0 init finished in 81 msecs
9412 01:22:34.675667 Devices initialized
9413 01:22:34.679390 Show all devs... After init.
9414 01:22:34.679472 Root Device: enabled 1
9415 01:22:34.682457 CPU_CLUSTER: 0: enabled 1
9416 01:22:34.685503 CPU: 00: enabled 1
9417 01:22:34.689335 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9418 01:22:34.692245 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9419 01:22:34.695590 ELOG: NV offset 0x57f000 size 0x1000
9420 01:22:34.702608 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9421 01:22:34.709327 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9422 01:22:34.712287 ELOG: Event(17) added with size 13 at 2024-04-23 01:22:34 UTC
9423 01:22:34.715710 out: cmd=0x121: 03 db 21 01 00 00 00 00
9424 01:22:34.719863 in-header: 03 34 00 00 2c 00 00 00
9425 01:22:34.733034 in-data: 2a 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9426 01:22:34.739202 ELOG: Event(A1) added with size 10 at 2024-04-23 01:22:34 UTC
9427 01:22:34.745807 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9428 01:22:34.753092 ELOG: Event(A0) added with size 9 at 2024-04-23 01:22:34 UTC
9429 01:22:34.756069 elog_add_boot_reason: Logged dev mode boot
9430 01:22:34.759391 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9431 01:22:34.762462 Finalize devices...
9432 01:22:34.762572 Devices finalized
9433 01:22:34.769264 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9434 01:22:34.772331 Writing coreboot table at 0xffe64000
9435 01:22:34.775797 0. 000000000010a000-0000000000113fff: RAMSTAGE
9436 01:22:34.778925 1. 0000000040000000-00000000400fffff: RAM
9437 01:22:34.785725 2. 0000000040100000-000000004032afff: RAMSTAGE
9438 01:22:34.788819 3. 000000004032b000-00000000545fffff: RAM
9439 01:22:34.792559 4. 0000000054600000-000000005465ffff: BL31
9440 01:22:34.795760 5. 0000000054660000-00000000ffe63fff: RAM
9441 01:22:34.802440 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9442 01:22:34.805769 7. 0000000100000000-000000023fffffff: RAM
9443 01:22:34.805850 Passing 5 GPIOs to payload:
9444 01:22:34.812389 NAME | PORT | POLARITY | VALUE
9445 01:22:34.815417 EC in RW | 0x000000aa | low | undefined
9446 01:22:34.822071 EC interrupt | 0x00000005 | low | undefined
9447 01:22:34.825681 TPM interrupt | 0x000000ab | high | undefined
9448 01:22:34.829081 SD card detect | 0x00000011 | high | undefined
9449 01:22:34.835659 speaker enable | 0x00000093 | high | undefined
9450 01:22:34.838857 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9451 01:22:34.842338 in-header: 03 f9 00 00 02 00 00 00
9452 01:22:34.842414 in-data: 02 00
9453 01:22:34.845417 ADC[4]: Raw value=893711 ID=7
9454 01:22:34.848621 ADC[3]: Raw value=212700 ID=1
9455 01:22:34.848703 RAM Code: 0x71
9456 01:22:34.852295 ADC[6]: Raw value=74722 ID=0
9457 01:22:34.855947 ADC[5]: Raw value=212330 ID=1
9458 01:22:34.856057 SKU Code: 0x1
9459 01:22:34.862479 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 9a05
9460 01:22:34.865436 coreboot table: 964 bytes.
9461 01:22:34.868831 IMD ROOT 0. 0xfffff000 0x00001000
9462 01:22:34.871919 IMD SMALL 1. 0xffffe000 0x00001000
9463 01:22:34.875431 RO MCACHE 2. 0xffffc000 0x00001104
9464 01:22:34.878465 CONSOLE 3. 0xfff7c000 0x00080000
9465 01:22:34.882013 FMAP 4. 0xfff7b000 0x00000452
9466 01:22:34.885235 TIME STAMP 5. 0xfff7a000 0x00000910
9467 01:22:34.888374 VBOOT WORK 6. 0xfff66000 0x00014000
9468 01:22:34.892132 RAMOOPS 7. 0xffe66000 0x00100000
9469 01:22:34.895045 COREBOOT 8. 0xffe64000 0x00002000
9470 01:22:34.895127 IMD small region:
9471 01:22:34.898370 IMD ROOT 0. 0xffffec00 0x00000400
9472 01:22:34.902037 VPD 1. 0xffffeb80 0x0000006c
9473 01:22:34.905154 MMC STATUS 2. 0xffffeb60 0x00000004
9474 01:22:34.911606 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9475 01:22:34.915657 Probing TPM: done!
9476 01:22:34.918622 Connected to device vid:did:rid of 1ae0:0028:00
9477 01:22:34.928572 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9478 01:22:34.932236 Initialized TPM device CR50 revision 0
9479 01:22:34.935706 Checking cr50 for pending updates
9480 01:22:34.939201 Reading cr50 TPM mode
9481 01:22:34.947351 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9482 01:22:34.953835 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9483 01:22:34.993999 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9484 01:22:34.997639 Checking segment from ROM address 0x40100000
9485 01:22:35.000692 Checking segment from ROM address 0x4010001c
9486 01:22:35.007414 Loading segment from ROM address 0x40100000
9487 01:22:35.007497 code (compression=0)
9488 01:22:35.017749 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9489 01:22:35.024206 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9490 01:22:35.024327 it's not compressed!
9491 01:22:35.030550 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9492 01:22:35.034288 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9493 01:22:35.054733 Loading segment from ROM address 0x4010001c
9494 01:22:35.054819 Entry Point 0x80000000
9495 01:22:35.057822 Loaded segments
9496 01:22:35.060949 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9497 01:22:35.067924 Jumping to boot code at 0x80000000(0xffe64000)
9498 01:22:35.074310 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9499 01:22:35.080996 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9500 01:22:35.089044 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9501 01:22:35.092241 Checking segment from ROM address 0x40100000
9502 01:22:35.095971 Checking segment from ROM address 0x4010001c
9503 01:22:35.102660 Loading segment from ROM address 0x40100000
9504 01:22:35.102743 code (compression=1)
9505 01:22:35.109417 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9506 01:22:35.118915 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9507 01:22:35.118995 using LZMA
9508 01:22:35.127294 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9509 01:22:35.134436 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9510 01:22:35.137477 Loading segment from ROM address 0x4010001c
9511 01:22:35.137595 Entry Point 0x54601000
9512 01:22:35.140587 Loaded segments
9513 01:22:35.144280 NOTICE: MT8192 bl31_setup
9514 01:22:35.150892 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9515 01:22:35.154417 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9516 01:22:35.157536 WARNING: region 0:
9517 01:22:35.161291 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9518 01:22:35.161383 WARNING: region 1:
9519 01:22:35.167637 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9520 01:22:35.171295 WARNING: region 2:
9521 01:22:35.174427 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9522 01:22:35.178189 WARNING: region 3:
9523 01:22:35.180996 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9524 01:22:35.184368 WARNING: region 4:
9525 01:22:35.187579 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9526 01:22:35.191099 WARNING: region 5:
9527 01:22:35.194520 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9528 01:22:35.198083 WARNING: region 6:
9529 01:22:35.201350 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9530 01:22:35.201459 WARNING: region 7:
9531 01:22:35.207728 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9532 01:22:35.214654 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9533 01:22:35.217850 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9534 01:22:35.220818 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9535 01:22:35.227519 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9536 01:22:35.231180 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9537 01:22:35.234359 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9538 01:22:35.241342 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9539 01:22:35.244552 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9540 01:22:35.251148 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9541 01:22:35.254211 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9542 01:22:35.257361 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9543 01:22:35.264026 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9544 01:22:35.267740 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9545 01:22:35.270827 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9546 01:22:35.277859 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9547 01:22:35.280918 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9548 01:22:35.287413 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9549 01:22:35.291030 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9550 01:22:35.293917 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9551 01:22:35.301102 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9552 01:22:35.304069 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9553 01:22:35.307927 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9554 01:22:35.313917 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9555 01:22:35.317430 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9556 01:22:35.324319 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9557 01:22:35.327838 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9558 01:22:35.330868 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9559 01:22:35.337503 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9560 01:22:35.340653 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9561 01:22:35.347372 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9562 01:22:35.350836 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9563 01:22:35.353987 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9564 01:22:35.361074 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9565 01:22:35.364180 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9566 01:22:35.367732 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9567 01:22:35.370985 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9568 01:22:35.377950 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9569 01:22:35.381084 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9570 01:22:35.384198 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9571 01:22:35.387914 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9572 01:22:35.390941 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9573 01:22:35.397707 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9574 01:22:35.401201 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9575 01:22:35.404249 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9576 01:22:35.411069 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9577 01:22:35.414687 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9578 01:22:35.417749 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9579 01:22:35.420913 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9580 01:22:35.427668 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9581 01:22:35.430935 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9582 01:22:35.437639 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9583 01:22:35.441174 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9584 01:22:35.444548 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9585 01:22:35.450965 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9586 01:22:35.454077 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9587 01:22:35.460663 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9588 01:22:35.464164 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9589 01:22:35.470856 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9590 01:22:35.474440 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9591 01:22:35.477689 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9592 01:22:35.484079 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9593 01:22:35.487703 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9594 01:22:35.494554 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9595 01:22:35.497433 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9596 01:22:35.504171 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9597 01:22:35.507329 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9598 01:22:35.514006 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9599 01:22:35.517639 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9600 01:22:35.520804 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9601 01:22:35.527734 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9602 01:22:35.530783 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9603 01:22:35.537540 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9604 01:22:35.540481 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9605 01:22:35.547383 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9606 01:22:35.550884 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9607 01:22:35.553889 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9608 01:22:35.560988 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9609 01:22:35.563958 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9610 01:22:35.570817 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9611 01:22:35.574232 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9612 01:22:35.580989 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9613 01:22:35.583896 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9614 01:22:35.587169 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9615 01:22:35.593917 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9616 01:22:35.597107 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9617 01:22:35.603828 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9618 01:22:35.607407 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9619 01:22:35.613585 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9620 01:22:35.617285 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9621 01:22:35.620853 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9622 01:22:35.627310 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9623 01:22:35.630463 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9624 01:22:35.637203 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9625 01:22:35.640257 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9626 01:22:35.647339 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9627 01:22:35.650487 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9628 01:22:35.654216 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9629 01:22:35.660429 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9630 01:22:35.664106 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9631 01:22:35.667173 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9632 01:22:35.670682 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9633 01:22:35.676978 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9634 01:22:35.680351 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9635 01:22:35.687126 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9636 01:22:35.690569 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9637 01:22:35.693980 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9638 01:22:35.700565 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9639 01:22:35.704209 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9640 01:22:35.710805 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9641 01:22:35.713958 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9642 01:22:35.717118 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9643 01:22:35.723889 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9644 01:22:35.727371 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9645 01:22:35.733790 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9646 01:22:35.737040 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9647 01:22:35.740871 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9648 01:22:35.743827 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9649 01:22:35.750592 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9650 01:22:35.754105 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9651 01:22:35.757195 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9652 01:22:35.764145 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9653 01:22:35.767119 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9654 01:22:35.770091 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9655 01:22:35.773888 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9656 01:22:35.780516 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9657 01:22:35.783634 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9658 01:22:35.790487 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9659 01:22:35.793466 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9660 01:22:35.797166 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9661 01:22:35.803939 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9662 01:22:35.806937 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9663 01:22:35.813590 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9664 01:22:35.817205 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9665 01:22:35.820270 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9666 01:22:35.827031 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9667 01:22:35.830067 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9668 01:22:35.836670 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9669 01:22:35.840082 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9670 01:22:35.843184 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9671 01:22:35.850106 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9672 01:22:35.853686 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9673 01:22:35.860443 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9674 01:22:35.863563 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9675 01:22:35.866747 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9676 01:22:35.873447 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9677 01:22:35.876514 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9678 01:22:35.880242 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9679 01:22:35.886982 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9680 01:22:35.890152 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9681 01:22:35.897029 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9682 01:22:35.900157 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9683 01:22:35.903162 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9684 01:22:35.910205 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9685 01:22:35.913403 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9686 01:22:35.917186 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9687 01:22:35.923300 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9688 01:22:35.926812 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9689 01:22:35.933478 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9690 01:22:35.936651 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9691 01:22:35.940018 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9692 01:22:35.947142 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9693 01:22:35.950118 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9694 01:22:35.956971 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9695 01:22:35.959952 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9696 01:22:35.963562 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9697 01:22:35.969956 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9698 01:22:35.973162 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9699 01:22:35.979877 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9700 01:22:35.982956 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9701 01:22:35.986692 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9702 01:22:35.993424 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9703 01:22:35.996572 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9704 01:22:35.999805 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9705 01:22:36.006645 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9706 01:22:36.009700 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9707 01:22:36.016534 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9708 01:22:36.019656 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9709 01:22:36.025951 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9710 01:22:36.029231 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9711 01:22:36.032818 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9712 01:22:36.039104 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9713 01:22:36.042717 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9714 01:22:36.049005 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9715 01:22:36.052666 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9716 01:22:36.056063 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9717 01:22:36.062203 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9718 01:22:36.065900 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9719 01:22:36.072449 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9720 01:22:36.075416 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9721 01:22:36.078662 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9722 01:22:36.085286 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9723 01:22:36.088957 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9724 01:22:36.095724 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9725 01:22:36.098928 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9726 01:22:36.102118 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9727 01:22:36.108977 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9728 01:22:36.112144 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9729 01:22:36.118906 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9730 01:22:36.122019 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9731 01:22:36.128820 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9732 01:22:36.131828 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9733 01:22:36.135570 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9734 01:22:36.141971 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9735 01:22:36.145264 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9736 01:22:36.151806 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9737 01:22:36.155074 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9738 01:22:36.161820 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9739 01:22:36.164959 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9740 01:22:36.168018 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9741 01:22:36.175051 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9742 01:22:36.178294 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9743 01:22:36.184965 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9744 01:22:36.188270 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9745 01:22:36.194513 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9746 01:22:36.197800 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9747 01:22:36.201441 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9748 01:22:36.208188 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9749 01:22:36.211434 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9750 01:22:36.217726 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9751 01:22:36.221375 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9752 01:22:36.227600 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9753 01:22:36.231420 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9754 01:22:36.234393 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9755 01:22:36.240809 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9756 01:22:36.244569 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9757 01:22:36.251182 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9758 01:22:36.254226 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9759 01:22:36.257648 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9760 01:22:36.264144 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9761 01:22:36.267623 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9762 01:22:36.270860 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9763 01:22:36.273887 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9764 01:22:36.280830 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9765 01:22:36.283897 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9766 01:22:36.287549 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9767 01:22:36.294314 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9768 01:22:36.297487 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9769 01:22:36.304129 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9770 01:22:36.307627 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9771 01:22:36.310625 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9772 01:22:36.317034 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9773 01:22:36.320265 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9774 01:22:36.324036 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9775 01:22:36.330295 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9776 01:22:36.333928 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9777 01:22:36.337030 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9778 01:22:36.343778 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9779 01:22:36.346878 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9780 01:22:36.350605 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9781 01:22:36.356689 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9782 01:22:36.360402 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9783 01:22:36.366536 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9784 01:22:36.370292 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9785 01:22:36.373353 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9786 01:22:36.380183 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9787 01:22:36.383423 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9788 01:22:36.386878 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9789 01:22:36.393434 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9790 01:22:36.398433 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9791 01:22:36.403270 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9792 01:22:36.406542 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9793 01:22:36.409410 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9794 01:22:36.416327 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9795 01:22:36.419322 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9796 01:22:36.422775 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9797 01:22:36.429494 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9798 01:22:36.433027 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9799 01:22:36.439534 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9800 01:22:36.442647 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9801 01:22:36.445722 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9802 01:22:36.448941 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9803 01:22:36.455775 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9804 01:22:36.459371 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9805 01:22:36.462445 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9806 01:22:36.465633 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9807 01:22:36.472350 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9808 01:22:36.475503 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9809 01:22:36.479168 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9810 01:22:36.482250 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9811 01:22:36.489048 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9812 01:22:36.491877 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9813 01:22:36.495224 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9814 01:22:36.502209 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9815 01:22:36.505389 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9816 01:22:36.512043 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9817 01:22:36.515367 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9818 01:22:36.518338 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9819 01:22:36.525055 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9820 01:22:36.528336 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9821 01:22:36.535201 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9822 01:22:36.538663 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9823 01:22:36.541414 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9824 01:22:36.548347 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9825 01:22:36.551282 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9826 01:22:36.557887 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9827 01:22:36.561597 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9828 01:22:36.567745 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9829 01:22:36.571471 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9830 01:22:36.574540 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9831 01:22:36.581352 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9832 01:22:36.584595 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9833 01:22:36.591211 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9834 01:22:36.594326 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9835 01:22:36.598000 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9836 01:22:36.604394 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9837 01:22:36.607854 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9838 01:22:36.614463 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9839 01:22:36.617631 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9840 01:22:36.620774 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9841 01:22:36.627747 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9842 01:22:36.630591 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9843 01:22:36.637451 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9844 01:22:36.640392 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9845 01:22:36.647059 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9846 01:22:36.650568 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9847 01:22:36.653645 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9848 01:22:36.660352 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9849 01:22:36.663597 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9850 01:22:36.670646 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9851 01:22:36.673708 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9852 01:22:36.680037 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9853 01:22:36.684003 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9854 01:22:36.687027 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9855 01:22:36.693413 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9856 01:22:36.696554 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9857 01:22:36.703472 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9858 01:22:36.706537 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9859 01:22:36.710203 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9860 01:22:36.716578 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9861 01:22:36.720031 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9862 01:22:36.726687 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9863 01:22:36.730032 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9864 01:22:36.736107 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9865 01:22:36.739941 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9866 01:22:36.742810 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9867 01:22:36.749445 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9868 01:22:36.752983 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9869 01:22:36.759193 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9870 01:22:36.763089 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9871 01:22:36.766241 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9872 01:22:36.772824 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9873 01:22:36.776078 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9874 01:22:36.782637 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9875 01:22:36.786055 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9876 01:22:36.792795 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9877 01:22:36.795958 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9878 01:22:36.798976 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9879 01:22:36.805907 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9880 01:22:36.809059 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9881 01:22:36.815798 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9882 01:22:36.819018 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9883 01:22:36.822013 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9884 01:22:36.828794 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9885 01:22:36.831746 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9886 01:22:36.838969 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9887 01:22:36.841807 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9888 01:22:36.848543 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9889 01:22:36.852161 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9890 01:22:36.858259 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9891 01:22:36.861749 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9892 01:22:36.864781 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9893 01:22:36.871839 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9894 01:22:36.874885 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9895 01:22:36.881457 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9896 01:22:36.885012 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9897 01:22:36.891657 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9898 01:22:36.894997 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9899 01:22:36.901285 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9900 01:22:36.904519 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9901 01:22:36.908192 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9902 01:22:36.914386 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9903 01:22:36.918184 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9904 01:22:36.924429 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9905 01:22:36.927886 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9906 01:22:36.934539 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9907 01:22:36.937448 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9908 01:22:36.944248 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9909 01:22:36.947910 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9910 01:22:36.951009 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9911 01:22:36.957903 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9912 01:22:36.960779 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9913 01:22:36.967121 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9914 01:22:36.970577 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9915 01:22:36.977084 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9916 01:22:36.980289 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9917 01:22:36.983985 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9918 01:22:36.990660 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9919 01:22:36.993762 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9920 01:22:37.000560 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9921 01:22:37.003646 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9922 01:22:37.010371 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9923 01:22:37.013670 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9924 01:22:37.020023 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9925 01:22:37.023258 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9926 01:22:37.026987 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9927 01:22:37.033499 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9928 01:22:37.036636 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9929 01:22:37.043447 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9930 01:22:37.046413 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9931 01:22:37.053299 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9932 01:22:37.056408 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9933 01:22:37.059890 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9934 01:22:37.066442 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9935 01:22:37.070114 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9936 01:22:37.076778 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9937 01:22:37.079636 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9938 01:22:37.086762 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9939 01:22:37.089764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9940 01:22:37.096359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9941 01:22:37.099530 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9942 01:22:37.106365 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9943 01:22:37.109495 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9944 01:22:37.115767 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9945 01:22:37.119524 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9946 01:22:37.125973 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9947 01:22:37.128935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9948 01:22:37.136011 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9949 01:22:37.138861 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9950 01:22:37.145541 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9951 01:22:37.149213 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9952 01:22:37.155388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9953 01:22:37.158475 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9954 01:22:37.165159 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9955 01:22:37.168325 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9956 01:22:37.175017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9957 01:22:37.178123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9958 01:22:37.184905 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9959 01:22:37.188336 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9960 01:22:37.194523 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9961 01:22:37.198087 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9962 01:22:37.204395 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9963 01:22:37.208199 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9964 01:22:37.214329 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9965 01:22:37.218231 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9966 01:22:37.221097 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9967 01:22:37.224784 INFO: [APUAPC] vio 0
9968 01:22:37.230938 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9969 01:22:37.234509 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9970 01:22:37.238231 INFO: [APUAPC] D0_APC_0: 0x400510
9971 01:22:37.241221 INFO: [APUAPC] D0_APC_1: 0x0
9972 01:22:37.244284 INFO: [APUAPC] D0_APC_2: 0x1540
9973 01:22:37.247867 INFO: [APUAPC] D0_APC_3: 0x0
9974 01:22:37.250600 INFO: [APUAPC] D1_APC_0: 0xffffffff
9975 01:22:37.254072 INFO: [APUAPC] D1_APC_1: 0xffffffff
9976 01:22:37.257247 INFO: [APUAPC] D1_APC_2: 0x3fffff
9977 01:22:37.260627 INFO: [APUAPC] D1_APC_3: 0x0
9978 01:22:37.263929 INFO: [APUAPC] D2_APC_0: 0xffffffff
9979 01:22:37.267261 INFO: [APUAPC] D2_APC_1: 0xffffffff
9980 01:22:37.270507 INFO: [APUAPC] D2_APC_2: 0x3fffff
9981 01:22:37.274393 INFO: [APUAPC] D2_APC_3: 0x0
9982 01:22:37.277490 INFO: [APUAPC] D3_APC_0: 0xffffffff
9983 01:22:37.280543 INFO: [APUAPC] D3_APC_1: 0xffffffff
9984 01:22:37.284059 INFO: [APUAPC] D3_APC_2: 0x3fffff
9985 01:22:37.287386 INFO: [APUAPC] D3_APC_3: 0x0
9986 01:22:37.290648 INFO: [APUAPC] D4_APC_0: 0xffffffff
9987 01:22:37.293888 INFO: [APUAPC] D4_APC_1: 0xffffffff
9988 01:22:37.297042 INFO: [APUAPC] D4_APC_2: 0x3fffff
9989 01:22:37.297135 INFO: [APUAPC] D4_APC_3: 0x0
9990 01:22:37.303922 INFO: [APUAPC] D5_APC_0: 0xffffffff
9991 01:22:37.307164 INFO: [APUAPC] D5_APC_1: 0xffffffff
9992 01:22:37.310274 INFO: [APUAPC] D5_APC_2: 0x3fffff
9993 01:22:37.310360 INFO: [APUAPC] D5_APC_3: 0x0
9994 01:22:37.313983 INFO: [APUAPC] D6_APC_0: 0xffffffff
9995 01:22:37.317050 INFO: [APUAPC] D6_APC_1: 0xffffffff
9996 01:22:37.320215 INFO: [APUAPC] D6_APC_2: 0x3fffff
9997 01:22:37.323998 INFO: [APUAPC] D6_APC_3: 0x0
9998 01:22:37.327100 INFO: [APUAPC] D7_APC_0: 0xffffffff
9999 01:22:37.330142 INFO: [APUAPC] D7_APC_1: 0xffffffff
10000 01:22:37.333332 INFO: [APUAPC] D7_APC_2: 0x3fffff
10001 01:22:37.337072 INFO: [APUAPC] D7_APC_3: 0x0
10002 01:22:37.340127 INFO: [APUAPC] D8_APC_0: 0xffffffff
10003 01:22:37.343779 INFO: [APUAPC] D8_APC_1: 0xffffffff
10004 01:22:37.346879 INFO: [APUAPC] D8_APC_2: 0x3fffff
10005 01:22:37.349824 INFO: [APUAPC] D8_APC_3: 0x0
10006 01:22:37.353056 INFO: [APUAPC] D9_APC_0: 0xffffffff
10007 01:22:37.356254 INFO: [APUAPC] D9_APC_1: 0xffffffff
10008 01:22:37.359981 INFO: [APUAPC] D9_APC_2: 0x3fffff
10009 01:22:37.362856 INFO: [APUAPC] D9_APC_3: 0x0
10010 01:22:37.366440 INFO: [APUAPC] D10_APC_0: 0xffffffff
10011 01:22:37.370055 INFO: [APUAPC] D10_APC_1: 0xffffffff
10012 01:22:37.372848 INFO: [APUAPC] D10_APC_2: 0x3fffff
10013 01:22:37.376287 INFO: [APUAPC] D10_APC_3: 0x0
10014 01:22:37.379526 INFO: [APUAPC] D11_APC_0: 0xffffffff
10015 01:22:37.383030 INFO: [APUAPC] D11_APC_1: 0xffffffff
10016 01:22:37.386592 INFO: [APUAPC] D11_APC_2: 0x3fffff
10017 01:22:37.389731 INFO: [APUAPC] D11_APC_3: 0x0
10018 01:22:37.392766 INFO: [APUAPC] D12_APC_0: 0xffffffff
10019 01:22:37.396318 INFO: [APUAPC] D12_APC_1: 0xffffffff
10020 01:22:37.399674 INFO: [APUAPC] D12_APC_2: 0x3fffff
10021 01:22:37.402858 INFO: [APUAPC] D12_APC_3: 0x0
10022 01:22:37.405799 INFO: [APUAPC] D13_APC_0: 0xffffffff
10023 01:22:37.409235 INFO: [APUAPC] D13_APC_1: 0xffffffff
10024 01:22:37.412753 INFO: [APUAPC] D13_APC_2: 0x3fffff
10025 01:22:37.416112 INFO: [APUAPC] D13_APC_3: 0x0
10026 01:22:37.419411 INFO: [APUAPC] D14_APC_0: 0xffffffff
10027 01:22:37.425649 INFO: [APUAPC] D14_APC_1: 0xffffffff
10028 01:22:37.429418 INFO: [APUAPC] D14_APC_2: 0x3fffff
10029 01:22:37.429500 INFO: [APUAPC] D14_APC_3: 0x0
10030 01:22:37.432579 INFO: [APUAPC] D15_APC_0: 0xffffffff
10031 01:22:37.439532 INFO: [APUAPC] D15_APC_1: 0xffffffff
10032 01:22:37.442487 INFO: [APUAPC] D15_APC_2: 0x3fffff
10033 01:22:37.442586 INFO: [APUAPC] D15_APC_3: 0x0
10034 01:22:37.445936 INFO: [APUAPC] APC_CON: 0x4
10035 01:22:37.448875 INFO: [NOCDAPC] D0_APC_0: 0x0
10036 01:22:37.452074 INFO: [NOCDAPC] D0_APC_1: 0x0
10037 01:22:37.455810 INFO: [NOCDAPC] D1_APC_0: 0x0
10038 01:22:37.458780 INFO: [NOCDAPC] D1_APC_1: 0xfff
10039 01:22:37.461917 INFO: [NOCDAPC] D2_APC_0: 0x0
10040 01:22:37.465403 INFO: [NOCDAPC] D2_APC_1: 0xfff
10041 01:22:37.469174 INFO: [NOCDAPC] D3_APC_0: 0x0
10042 01:22:37.472284 INFO: [NOCDAPC] D3_APC_1: 0xfff
10043 01:22:37.472372 INFO: [NOCDAPC] D4_APC_0: 0x0
10044 01:22:37.475428 INFO: [NOCDAPC] D4_APC_1: 0xfff
10045 01:22:37.479177 INFO: [NOCDAPC] D5_APC_0: 0x0
10046 01:22:37.481994 INFO: [NOCDAPC] D5_APC_1: 0xfff
10047 01:22:37.485420 INFO: [NOCDAPC] D6_APC_0: 0x0
10048 01:22:37.488260 INFO: [NOCDAPC] D6_APC_1: 0xfff
10049 01:22:37.491661 INFO: [NOCDAPC] D7_APC_0: 0x0
10050 01:22:37.495066 INFO: [NOCDAPC] D7_APC_1: 0xfff
10051 01:22:37.498713 INFO: [NOCDAPC] D8_APC_0: 0x0
10052 01:22:37.501848 INFO: [NOCDAPC] D8_APC_1: 0xfff
10053 01:22:37.504848 INFO: [NOCDAPC] D9_APC_0: 0x0
10054 01:22:37.508474 INFO: [NOCDAPC] D9_APC_1: 0xfff
10055 01:22:37.508554 INFO: [NOCDAPC] D10_APC_0: 0x0
10056 01:22:37.511490 INFO: [NOCDAPC] D10_APC_1: 0xfff
10057 01:22:37.514979 INFO: [NOCDAPC] D11_APC_0: 0x0
10058 01:22:37.518051 INFO: [NOCDAPC] D11_APC_1: 0xfff
10059 01:22:37.521045 INFO: [NOCDAPC] D12_APC_0: 0x0
10060 01:22:37.524499 INFO: [NOCDAPC] D12_APC_1: 0xfff
10061 01:22:37.527725 INFO: [NOCDAPC] D13_APC_0: 0x0
10062 01:22:37.531106 INFO: [NOCDAPC] D13_APC_1: 0xfff
10063 01:22:37.534714 INFO: [NOCDAPC] D14_APC_0: 0x0
10064 01:22:37.537881 INFO: [NOCDAPC] D14_APC_1: 0xfff
10065 01:22:37.541216 INFO: [NOCDAPC] D15_APC_0: 0x0
10066 01:22:37.544310 INFO: [NOCDAPC] D15_APC_1: 0xfff
10067 01:22:37.548129 INFO: [NOCDAPC] APC_CON: 0x4
10068 01:22:37.551223 INFO: [APUAPC] set_apusys_apc done
10069 01:22:37.554239 INFO: [DEVAPC] devapc_init done
10070 01:22:37.557927 INFO: GICv3 without legacy support detected.
10071 01:22:37.560969 INFO: ARM GICv3 driver initialized in EL3
10072 01:22:37.564572 INFO: Maximum SPI INTID supported: 639
10073 01:22:37.567783 INFO: BL31: Initializing runtime services
10074 01:22:37.574551 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10075 01:22:37.577724 INFO: SPM: enable CPC mode
10076 01:22:37.583892 INFO: mcdi ready for mcusys-off-idle and system suspend
10077 01:22:37.587759 INFO: BL31: Preparing for EL3 exit to normal world
10078 01:22:37.590661 INFO: Entry point address = 0x80000000
10079 01:22:37.594139 INFO: SPSR = 0x8
10080 01:22:37.598913
10081 01:22:37.599002
10082 01:22:37.599068
10083 01:22:37.602192 Starting depthcharge on Spherion...
10084 01:22:37.602284
10085 01:22:37.602348 Wipe memory regions:
10086 01:22:37.602408
10087 01:22:37.603092 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10088 01:22:37.603199 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10089 01:22:37.603284 Setting prompt string to ['asurada:']
10090 01:22:37.603368 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10091 01:22:37.605231 [0x00000040000000, 0x00000054600000)
10092 01:22:37.727824
10093 01:22:37.727957 [0x00000054660000, 0x00000080000000)
10094 01:22:37.988469
10095 01:22:37.988604 [0x000000821a7280, 0x000000ffe64000)
10096 01:22:38.733761
10097 01:22:38.734278 [0x00000100000000, 0x00000240000000)
10098 01:22:40.623387
10099 01:22:40.626563 Initializing XHCI USB controller at 0x11200000.
10100 01:22:41.664351
10101 01:22:41.667645 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10102 01:22:41.667735
10103 01:22:41.667800
10104 01:22:41.667860
10105 01:22:41.668144 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10107 01:22:41.768504 asurada: tftpboot 192.168.201.1 13468790/tftp-deploy-0zi91qtm/kernel/image.itb 13468790/tftp-deploy-0zi91qtm/kernel/cmdline
10108 01:22:41.768631 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10109 01:22:41.768716 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10110 01:22:41.773400 tftpboot 192.168.201.1 13468790/tftp-deploy-0zi91qtm/kernel/image.itp-deploy-0zi91qtm/kernel/cmdline
10111 01:22:41.773516
10112 01:22:41.773616 Waiting for link
10113 01:22:41.933737
10114 01:22:41.933868 R8152: Initializing
10115 01:22:41.933937
10116 01:22:41.936904 Version 6 (ocp_data = 5c30)
10117 01:22:41.937010
10118 01:22:41.939969 R8152: Done initializing
10119 01:22:41.940058
10120 01:22:41.940123 Adding net device
10121 01:22:44.032580
10122 01:22:44.032743 done.
10123 01:22:44.032839
10124 01:22:44.032935 MAC: 00:24:32:30:78:ff
10125 01:22:44.033025
10126 01:22:44.035694 Sending DHCP discover... done.
10127 01:22:44.035794
10128 01:22:44.038909 Waiting for reply... done.
10129 01:22:44.039009
10130 01:22:44.042078 Sending DHCP request... done.
10131 01:22:44.042153
10132 01:22:44.047093 Waiting for reply... done.
10133 01:22:44.047194
10134 01:22:44.047288 My ip is 192.168.201.21
10135 01:22:44.047377
10136 01:22:44.050017 The DHCP server ip is 192.168.201.1
10137 01:22:44.050117
10138 01:22:44.056685 TFTP server IP predefined by user: 192.168.201.1
10139 01:22:44.056788
10140 01:22:44.063875 Bootfile predefined by user: 13468790/tftp-deploy-0zi91qtm/kernel/image.itb
10141 01:22:44.063977
10142 01:22:44.064071 Sending tftp read request... done.
10143 01:22:44.067152
10144 01:22:44.070860 Waiting for the transfer...
10145 01:22:44.070961
10146 01:22:44.604581 00000000 ################################################################
10147 01:22:44.604720
10148 01:22:45.133836 00080000 ################################################################
10149 01:22:45.133969
10150 01:22:45.672517 00100000 ################################################################
10151 01:22:45.672653
10152 01:22:46.212826 00180000 ################################################################
10153 01:22:46.212986
10154 01:22:46.756950 00200000 ################################################################
10155 01:22:46.757117
10156 01:22:47.291962 00280000 ################################################################
10157 01:22:47.292101
10158 01:22:47.824729 00300000 ################################################################
10159 01:22:47.824910
10160 01:22:48.357584 00380000 ################################################################
10161 01:22:48.357740
10162 01:22:48.904206 00400000 ################################################################
10163 01:22:48.904372
10164 01:22:49.454047 00480000 ################################################################
10165 01:22:49.454182
10166 01:22:50.003307 00500000 ################################################################
10167 01:22:50.003465
10168 01:22:50.549249 00580000 ################################################################
10169 01:22:50.549384
10170 01:22:51.092472 00600000 ################################################################
10171 01:22:51.092619
10172 01:22:51.628245 00680000 ################################################################
10173 01:22:51.628409
10174 01:22:52.184779 00700000 ################################################################
10175 01:22:52.184927
10176 01:22:52.737931 00780000 ################################################################
10177 01:22:52.738077
10178 01:22:53.282288 00800000 ################################################################
10179 01:22:53.282440
10180 01:22:53.817285 00880000 ################################################################
10181 01:22:53.817452
10182 01:22:54.369234 00900000 ################################################################
10183 01:22:54.369379
10184 01:22:54.919336 00980000 ################################################################
10185 01:22:54.919511
10186 01:22:55.482342 00a00000 ################################################################
10187 01:22:55.482506
10188 01:22:56.021739 00a80000 ################################################################
10189 01:22:56.021882
10190 01:22:56.570988 00b00000 ################################################################
10191 01:22:56.571145
10192 01:22:57.141475 00b80000 ################################################################
10193 01:22:57.141617
10194 01:22:57.692424 00c00000 ################################################################
10195 01:22:57.692561
10196 01:22:58.236508 00c80000 ################################################################
10197 01:22:58.236644
10198 01:22:58.781381 00d00000 ################################################################
10199 01:22:58.781521
10200 01:22:59.329152 00d80000 ################################################################
10201 01:22:59.329316
10202 01:22:59.901343 00e00000 ################################################################
10203 01:22:59.901532
10204 01:23:00.456882 00e80000 ################################################################
10205 01:23:00.457046
10206 01:23:01.020889 00f00000 ################################################################
10207 01:23:01.021042
10208 01:23:01.580006 00f80000 ################################################################
10209 01:23:01.580150
10210 01:23:02.126193 01000000 ################################################################
10211 01:23:02.126338
10212 01:23:02.676658 01080000 ################################################################
10213 01:23:02.676803
10214 01:23:03.233738 01100000 ################################################################
10215 01:23:03.233885
10216 01:23:03.780461 01180000 ################################################################
10217 01:23:03.780596
10218 01:23:04.322046 01200000 ################################################################
10219 01:23:04.322210
10220 01:23:04.875613 01280000 ################################################################
10221 01:23:04.875761
10222 01:23:05.412808 01300000 ################################################################
10223 01:23:05.412954
10224 01:23:05.952997 01380000 ################################################################
10225 01:23:05.953137
10226 01:23:06.493110 01400000 ################################################################
10227 01:23:06.493275
10228 01:23:07.022261 01480000 ################################################################
10229 01:23:07.022413
10230 01:23:07.543853 01500000 ################################################################
10231 01:23:07.544006
10232 01:23:08.070781 01580000 ################################################################
10233 01:23:08.070925
10234 01:23:08.606212 01600000 ################################################################
10235 01:23:08.606366
10236 01:23:09.133908 01680000 ################################################################
10237 01:23:09.134090
10238 01:23:09.661773 01700000 ################################################################
10239 01:23:09.661912
10240 01:23:10.196311 01780000 ################################################################
10241 01:23:10.196473
10242 01:23:10.755257 01800000 ################################################################
10243 01:23:10.755426
10244 01:23:11.317699 01880000 ################################################################
10245 01:23:11.317851
10246 01:23:11.868384 01900000 ################################################################
10247 01:23:11.868534
10248 01:23:12.418384 01980000 ################################################################
10249 01:23:12.418532
10250 01:23:12.977446 01a00000 ################################################################
10251 01:23:12.977615
10252 01:23:13.520939 01a80000 ################################################################
10253 01:23:13.521100
10254 01:23:14.053366 01b00000 ################################################################
10255 01:23:14.053515
10256 01:23:14.600268 01b80000 ################################################################
10257 01:23:14.600444
10258 01:23:15.167891 01c00000 ################################################################
10259 01:23:15.168026
10260 01:23:15.745154 01c80000 ################################################################
10261 01:23:15.745302
10262 01:23:16.304156 01d00000 ################################################################
10263 01:23:16.304307
10264 01:23:16.836861 01d80000 ################################################################
10265 01:23:16.837004
10266 01:23:17.115995 01e00000 ################################### done.
10267 01:23:17.116143
10268 01:23:17.119539 The bootfile was 31739278 bytes long.
10269 01:23:17.119617
10270 01:23:17.122511 Sending tftp read request... done.
10271 01:23:17.122584
10272 01:23:17.122650 Waiting for the transfer...
10273 01:23:17.122718
10274 01:23:17.125983 00000000 # done.
10275 01:23:17.126057
10276 01:23:17.132528 Command line loaded dynamically from TFTP file: 13468790/tftp-deploy-0zi91qtm/kernel/cmdline
10277 01:23:17.132640
10278 01:23:17.155908 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13468790/extract-nfsrootfs-pagiv9fy,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10279 01:23:17.156026
10280 01:23:17.156106 Loading FIT.
10281 01:23:17.156169
10282 01:23:17.159103 Image ramdisk-1 has 18779963 bytes.
10283 01:23:17.159204
10284 01:23:17.162347 Image fdt-1 has 47230 bytes.
10285 01:23:17.162422
10286 01:23:17.165493 Image kernel-1 has 12910050 bytes.
10287 01:23:17.165605
10288 01:23:17.175567 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10289 01:23:17.175651
10290 01:23:17.192062 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10291 01:23:17.192150
10292 01:23:17.198870 Choosing best match conf-1 for compat google,spherion-rev2.
10293 01:23:17.198953
10294 01:23:17.206390 Connected to device vid:did:rid of 1ae0:0028:00
10295 01:23:17.213290
10296 01:23:17.216479 tpm_get_response: command 0x17b, return code 0x0
10297 01:23:17.216562
10298 01:23:17.223336 ec_init: CrosEC protocol v3 supported (256, 248)
10299 01:23:17.223419
10300 01:23:17.226500 tpm_cleanup: add release locality here.
10301 01:23:17.226583
10302 01:23:17.229563 Shutting down all USB controllers.
10303 01:23:17.229646
10304 01:23:17.233414 Removing current net device
10305 01:23:17.233498
10306 01:23:17.239682 Exiting depthcharge with code 4 at timestamp: 68986335
10307 01:23:17.239765
10308 01:23:17.243063 LZMA decompressing kernel-1 to 0x821a6718
10309 01:23:17.243170
10310 01:23:17.246275 LZMA decompressing kernel-1 to 0x40000000
10311 01:23:18.839423
10312 01:23:18.839587 jumping to kernel
10313 01:23:18.840442 end: 2.2.4 bootloader-commands (duration 00:00:41) [common]
10314 01:23:18.840568 start: 2.2.5 auto-login-action (timeout 00:03:44) [common]
10315 01:23:18.840645 Setting prompt string to ['Linux version [0-9]']
10316 01:23:18.840713 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10317 01:23:18.840784 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10318 01:23:18.921544
10319 01:23:18.924469 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10320 01:23:18.928174 start: 2.2.5.1 login-action (timeout 00:03:44) [common]
10321 01:23:18.928291 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10322 01:23:18.928406 Setting prompt string to []
10323 01:23:18.928518 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10324 01:23:18.928621 Using line separator: #'\n'#
10325 01:23:18.928718 No login prompt set.
10326 01:23:18.928810 Parsing kernel messages
10327 01:23:18.928896 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10328 01:23:18.929083 [login-action] Waiting for messages, (timeout 00:03:44)
10329 01:23:18.929185 Waiting using forced prompt support (timeout 00:01:52)
10330 01:23:18.948002 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j174389-arm64-gcc-10-defconfig-arm64-chromebook-96m9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024
10331 01:23:18.951056 [ 0.000000] random: crng init done
10332 01:23:18.957377 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10333 01:23:18.960873 [ 0.000000] efi: UEFI not found.
10334 01:23:18.967157 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10335 01:23:18.977430 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10336 01:23:18.983830 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10337 01:23:18.994037 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10338 01:23:19.000284 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10339 01:23:19.007180 [ 0.000000] printk: bootconsole [mtk8250] enabled
10340 01:23:19.013560 [ 0.000000] NUMA: No NUMA configuration found
10341 01:23:19.019848 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10342 01:23:19.023536 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10343 01:23:19.026647 [ 0.000000] Zone ranges:
10344 01:23:19.033460 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10345 01:23:19.036562 [ 0.000000] DMA32 empty
10346 01:23:19.043423 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10347 01:23:19.046360 [ 0.000000] Movable zone start for each node
10348 01:23:19.049954 [ 0.000000] Early memory node ranges
10349 01:23:19.056481 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10350 01:23:19.062811 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10351 01:23:19.069494 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10352 01:23:19.076363 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10353 01:23:19.082963 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10354 01:23:19.089898 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10355 01:23:19.145809 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10356 01:23:19.152356 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10357 01:23:19.159013 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10358 01:23:19.162464 [ 0.000000] psci: probing for conduit method from DT.
10359 01:23:19.168985 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10360 01:23:19.172214 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10361 01:23:19.178848 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10362 01:23:19.182312 [ 0.000000] psci: SMC Calling Convention v1.2
10363 01:23:19.189010 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10364 01:23:19.192087 [ 0.000000] Detected VIPT I-cache on CPU0
10365 01:23:19.198392 [ 0.000000] CPU features: detected: GIC system register CPU interface
10366 01:23:19.205306 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10367 01:23:19.211726 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10368 01:23:19.218519 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10369 01:23:19.228133 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10370 01:23:19.234773 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10371 01:23:19.238204 [ 0.000000] alternatives: applying boot alternatives
10372 01:23:19.245039 [ 0.000000] Fallback order for Node 0: 0
10373 01:23:19.251707 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10374 01:23:19.254671 [ 0.000000] Policy zone: Normal
10375 01:23:19.278032 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13468790/extract-nfsrootfs-pagiv9fy,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10376 01:23:19.287799 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10377 01:23:19.298424 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10378 01:23:19.308330 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10379 01:23:19.315205 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10380 01:23:19.318461 <6>[ 0.000000] software IO TLB: area num 8.
10381 01:23:19.374806 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10382 01:23:19.524265 <6>[ 0.000000] Memory: 7946168K/8385536K available (18048K kernel code, 4118K rwdata, 22292K rodata, 8448K init, 616K bss, 406600K reserved, 32768K cma-reserved)
10383 01:23:19.531148 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10384 01:23:19.538032 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10385 01:23:19.541105 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10386 01:23:19.547905 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10387 01:23:19.554049 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10388 01:23:19.557495 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10389 01:23:19.567579 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10390 01:23:19.573718 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10391 01:23:19.580529 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10392 01:23:19.586740 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10393 01:23:19.590456 <6>[ 0.000000] GICv3: 608 SPIs implemented
10394 01:23:19.593532 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10395 01:23:19.600328 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10396 01:23:19.603464 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10397 01:23:19.610073 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10398 01:23:19.623634 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10399 01:23:19.636636 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10400 01:23:19.643048 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10401 01:23:19.650697 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10402 01:23:19.664263 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10403 01:23:19.670485 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10404 01:23:19.677150 <6>[ 0.009183] Console: colour dummy device 80x25
10405 01:23:19.687279 <6>[ 0.013941] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10406 01:23:19.691110 <6>[ 0.024383] pid_max: default: 32768 minimum: 301
10407 01:23:19.697274 <6>[ 0.029255] LSM: Security Framework initializing
10408 01:23:19.704038 <6>[ 0.034192] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10409 01:23:19.713915 <6>[ 0.042008] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10410 01:23:19.720580 <6>[ 0.051421] cblist_init_generic: Setting adjustable number of callback queues.
10411 01:23:19.727160 <6>[ 0.058863] cblist_init_generic: Setting shift to 3 and lim to 1.
10412 01:23:19.737308 <6>[ 0.065203] cblist_init_generic: Setting adjustable number of callback queues.
10413 01:23:19.743432 <6>[ 0.072675] cblist_init_generic: Setting shift to 3 and lim to 1.
10414 01:23:19.747282 <6>[ 0.079074] rcu: Hierarchical SRCU implementation.
10415 01:23:19.753484 <6>[ 0.084090] rcu: Max phase no-delay instances is 1000.
10416 01:23:19.760254 <6>[ 0.091154] EFI services will not be available.
10417 01:23:19.763227 <6>[ 0.096110] smp: Bringing up secondary CPUs ...
10418 01:23:19.772040 <6>[ 0.101158] Detected VIPT I-cache on CPU1
10419 01:23:19.778271 <6>[ 0.101227] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10420 01:23:19.784986 <6>[ 0.101258] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10421 01:23:19.788191 <6>[ 0.101588] Detected VIPT I-cache on CPU2
10422 01:23:19.794533 <6>[ 0.101634] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10423 01:23:19.804529 <6>[ 0.101650] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10424 01:23:19.807815 <6>[ 0.101911] Detected VIPT I-cache on CPU3
10425 01:23:19.814510 <6>[ 0.101956] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10426 01:23:19.821401 <6>[ 0.101969] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10427 01:23:19.824318 <6>[ 0.102271] CPU features: detected: Spectre-v4
10428 01:23:19.831002 <6>[ 0.102277] CPU features: detected: Spectre-BHB
10429 01:23:19.834454 <6>[ 0.102282] Detected PIPT I-cache on CPU4
10430 01:23:19.840786 <6>[ 0.102340] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10431 01:23:19.847561 <6>[ 0.102357] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10432 01:23:19.854393 <6>[ 0.102654] Detected PIPT I-cache on CPU5
10433 01:23:19.860757 <6>[ 0.102716] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10434 01:23:19.867675 <6>[ 0.102733] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10435 01:23:19.870468 <6>[ 0.103011] Detected PIPT I-cache on CPU6
10436 01:23:19.877156 <6>[ 0.103076] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10437 01:23:19.883966 <6>[ 0.103092] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10438 01:23:19.890802 <6>[ 0.103386] Detected PIPT I-cache on CPU7
10439 01:23:19.896901 <6>[ 0.103451] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10440 01:23:19.903873 <6>[ 0.103467] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10441 01:23:19.907188 <6>[ 0.103514] smp: Brought up 1 node, 8 CPUs
10442 01:23:19.914284 <6>[ 0.244822] SMP: Total of 8 processors activated.
10443 01:23:19.917214 <6>[ 0.249743] CPU features: detected: 32-bit EL0 Support
10444 01:23:19.926711 <6>[ 0.255107] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10445 01:23:19.933408 <6>[ 0.263907] CPU features: detected: Common not Private translations
10446 01:23:19.940403 <6>[ 0.270384] CPU features: detected: CRC32 instructions
10447 01:23:19.943401 <6>[ 0.275768] CPU features: detected: RCpc load-acquire (LDAPR)
10448 01:23:19.949992 <6>[ 0.281728] CPU features: detected: LSE atomic instructions
10449 01:23:19.956480 <6>[ 0.287545] CPU features: detected: Privileged Access Never
10450 01:23:19.963262 <6>[ 0.293361] CPU features: detected: RAS Extension Support
10451 01:23:19.970173 <6>[ 0.298970] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10452 01:23:19.973280 <6>[ 0.306236] CPU: All CPU(s) started at EL2
10453 01:23:19.979928 <6>[ 0.310579] alternatives: applying system-wide alternatives
10454 01:23:19.989196 <6>[ 0.321390] devtmpfs: initialized
10455 01:23:20.004854 <6>[ 0.330308] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10456 01:23:20.011785 <6>[ 0.340268] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10457 01:23:20.017936 <6>[ 0.348508] pinctrl core: initialized pinctrl subsystem
10458 01:23:20.021456 <6>[ 0.355153] DMI not present or invalid.
10459 01:23:20.027991 <6>[ 0.359508] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10460 01:23:20.037869 <6>[ 0.366399] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10461 01:23:20.044640 <6>[ 0.373987] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10462 01:23:20.054744 <6>[ 0.382223] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10463 01:23:20.057746 <6>[ 0.390464] audit: initializing netlink subsys (disabled)
10464 01:23:20.067583 <5>[ 0.396156] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10465 01:23:20.074320 <6>[ 0.396856] thermal_sys: Registered thermal governor 'step_wise'
10466 01:23:20.081238 <6>[ 0.404122] thermal_sys: Registered thermal governor 'power_allocator'
10467 01:23:20.084295 <6>[ 0.410378] cpuidle: using governor menu
10468 01:23:20.091054 <6>[ 0.421339] NET: Registered PF_QIPCRTR protocol family
10469 01:23:20.097329 <6>[ 0.426812] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10470 01:23:20.104355 <6>[ 0.433913] ASID allocator initialised with 32768 entries
10471 01:23:20.107476 <6>[ 0.440482] Serial: AMBA PL011 UART driver
10472 01:23:20.117323 <4>[ 0.449234] Trying to register duplicate clock ID: 134
10473 01:23:20.171612 <6>[ 0.506805] KASLR enabled
10474 01:23:20.185970 <6>[ 0.514500] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10475 01:23:20.192505 <6>[ 0.521513] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10476 01:23:20.198759 <6>[ 0.528000] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10477 01:23:20.205573 <6>[ 0.535005] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10478 01:23:20.211822 <6>[ 0.541493] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10479 01:23:20.218604 <6>[ 0.548496] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10480 01:23:20.225042 <6>[ 0.554982] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10481 01:23:20.232005 <6>[ 0.561987] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10482 01:23:20.235183 <6>[ 0.569497] ACPI: Interpreter disabled.
10483 01:23:20.243956 <6>[ 0.575926] iommu: Default domain type: Translated
10484 01:23:20.250723 <6>[ 0.581040] iommu: DMA domain TLB invalidation policy: strict mode
10485 01:23:20.253912 <5>[ 0.587697] SCSI subsystem initialized
10486 01:23:20.260338 <6>[ 0.591863] usbcore: registered new interface driver usbfs
10487 01:23:20.266939 <6>[ 0.597593] usbcore: registered new interface driver hub
10488 01:23:20.270558 <6>[ 0.603144] usbcore: registered new device driver usb
10489 01:23:20.277098 <6>[ 0.609244] pps_core: LinuxPPS API ver. 1 registered
10490 01:23:20.287535 <6>[ 0.614437] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10491 01:23:20.290846 <6>[ 0.623781] PTP clock support registered
10492 01:23:20.294205 <6>[ 0.628021] EDAC MC: Ver: 3.0.0
10493 01:23:20.301115 <6>[ 0.633171] FPGA manager framework
10494 01:23:20.307803 <6>[ 0.636852] Advanced Linux Sound Architecture Driver Initialized.
10495 01:23:20.310883 <6>[ 0.643635] vgaarb: loaded
10496 01:23:20.317726 <6>[ 0.646812] clocksource: Switched to clocksource arch_sys_counter
10497 01:23:20.321390 <5>[ 0.653256] VFS: Disk quotas dquot_6.6.0
10498 01:23:20.328186 <6>[ 0.657442] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10499 01:23:20.331328 <6>[ 0.664632] pnp: PnP ACPI: disabled
10500 01:23:20.339582 <6>[ 0.671354] NET: Registered PF_INET protocol family
10501 01:23:20.349139 <6>[ 0.676956] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10502 01:23:20.360590 <6>[ 0.689289] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10503 01:23:20.370293 <6>[ 0.698102] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10504 01:23:20.377085 <6>[ 0.706072] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10505 01:23:20.386864 <6>[ 0.714770] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10506 01:23:20.393838 <6>[ 0.724519] TCP: Hash tables configured (established 65536 bind 65536)
10507 01:23:20.400273 <6>[ 0.731378] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10508 01:23:20.410008 <6>[ 0.738574] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10509 01:23:20.416452 <6>[ 0.746278] NET: Registered PF_UNIX/PF_LOCAL protocol family
10510 01:23:20.423361 <6>[ 0.752447] RPC: Registered named UNIX socket transport module.
10511 01:23:20.426408 <6>[ 0.758600] RPC: Registered udp transport module.
10512 01:23:20.433081 <6>[ 0.763531] RPC: Registered tcp transport module.
10513 01:23:20.440026 <6>[ 0.768464] RPC: Registered tcp NFSv4.1 backchannel transport module.
10514 01:23:20.443185 <6>[ 0.775132] PCI: CLS 0 bytes, default 64
10515 01:23:20.446316 <6>[ 0.779528] Unpacking initramfs...
10516 01:23:20.470579 <6>[ 0.798916] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10517 01:23:20.480256 <6>[ 0.807567] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10518 01:23:20.484043 <6>[ 0.816410] kvm [1]: IPA Size Limit: 40 bits
10519 01:23:20.490303 <6>[ 0.820941] kvm [1]: GICv3: no GICV resource entry
10520 01:23:20.493414 <6>[ 0.825961] kvm [1]: disabling GICv2 emulation
10521 01:23:20.500168 <6>[ 0.830647] kvm [1]: GIC system register CPU interface enabled
10522 01:23:20.503159 <6>[ 0.836806] kvm [1]: vgic interrupt IRQ18
10523 01:23:20.509933 <6>[ 0.841157] kvm [1]: VHE mode initialized successfully
10524 01:23:20.516367 <5>[ 0.847587] Initialise system trusted keyrings
10525 01:23:20.522970 <6>[ 0.852411] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10526 01:23:20.530466 <6>[ 0.862398] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10527 01:23:20.537030 <5>[ 0.868802] NFS: Registering the id_resolver key type
10528 01:23:20.540157 <5>[ 0.874106] Key type id_resolver registered
10529 01:23:20.547081 <5>[ 0.878520] Key type id_legacy registered
10530 01:23:20.553886 <6>[ 0.882812] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10531 01:23:20.560283 <6>[ 0.889734] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10532 01:23:20.566527 <6>[ 0.897487] 9p: Installing v9fs 9p2000 file system support
10533 01:23:20.603240 <5>[ 0.935167] Key type asymmetric registered
10534 01:23:20.606903 <5>[ 0.939499] Asymmetric key parser 'x509' registered
10535 01:23:20.616716 <6>[ 0.944640] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10536 01:23:20.620108 <6>[ 0.952255] io scheduler mq-deadline registered
10537 01:23:20.622942 <6>[ 0.957033] io scheduler kyber registered
10538 01:23:20.642301 <6>[ 0.973945] EINJ: ACPI disabled.
10539 01:23:20.674949 <4>[ 0.999477] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10540 01:23:20.683970 <4>[ 1.010121] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10541 01:23:20.698755 <6>[ 1.030687] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10542 01:23:20.706515 <6>[ 1.038674] printk: console [ttyS0] disabled
10543 01:23:20.734439 <6>[ 1.063304] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10544 01:23:20.741307 <6>[ 1.072787] printk: console [ttyS0] enabled
10545 01:23:20.744336 <6>[ 1.072787] printk: console [ttyS0] enabled
10546 01:23:20.751293 <6>[ 1.081679] printk: bootconsole [mtk8250] disabled
10547 01:23:20.754467 <6>[ 1.081679] printk: bootconsole [mtk8250] disabled
10548 01:23:20.761117 <6>[ 1.092682] SuperH (H)SCI(F) driver initialized
10549 01:23:20.764667 <6>[ 1.097949] msm_serial: driver initialized
10550 01:23:20.778466 <6>[ 1.106843] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10551 01:23:20.788252 <6>[ 1.115386] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10552 01:23:20.794841 <6>[ 1.123927] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10553 01:23:20.804825 <6>[ 1.132553] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10554 01:23:20.814527 <6>[ 1.141259] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10555 01:23:20.821318 <6>[ 1.149978] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10556 01:23:20.831250 <6>[ 1.158521] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10557 01:23:20.837899 <6>[ 1.167311] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10558 01:23:20.847775 <6>[ 1.175853] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10559 01:23:20.859580 <6>[ 1.191459] loop: module loaded
10560 01:23:20.865876 <6>[ 1.197339] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10561 01:23:20.888780 <4>[ 1.220768] mtk-pmic-keys: Failed to locate of_node [id: -1]
10562 01:23:20.895425 <6>[ 1.227589] megasas: 07.719.03.00-rc1
10563 01:23:20.905253 <6>[ 1.237252] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10564 01:23:20.914510 <6>[ 1.246202] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10565 01:23:20.931043 <6>[ 1.262905] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10566 01:23:20.987722 <6>[ 1.312917] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10567 01:23:21.240374 <6>[ 1.572541] Freeing initrd memory: 18336K
10568 01:23:21.251946 <6>[ 1.584009] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10569 01:23:21.262962 <6>[ 1.594947] tun: Universal TUN/TAP device driver, 1.6
10570 01:23:21.266084 <6>[ 1.600996] thunder_xcv, ver 1.0
10571 01:23:21.269524 <6>[ 1.604502] thunder_bgx, ver 1.0
10572 01:23:21.272888 <6>[ 1.608001] nicpf, ver 1.0
10573 01:23:21.283514 <6>[ 1.612009] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10574 01:23:21.286752 <6>[ 1.619485] hns3: Copyright (c) 2017 Huawei Corporation.
10575 01:23:21.290199 <6>[ 1.625075] hclge is initializing
10576 01:23:21.297049 <6>[ 1.628656] e1000: Intel(R) PRO/1000 Network Driver
10577 01:23:21.303274 <6>[ 1.633786] e1000: Copyright (c) 1999-2006 Intel Corporation.
10578 01:23:21.306895 <6>[ 1.639798] e1000e: Intel(R) PRO/1000 Network Driver
10579 01:23:21.313044 <6>[ 1.645013] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10580 01:23:21.319915 <6>[ 1.651198] igb: Intel(R) Gigabit Ethernet Network Driver
10581 01:23:21.326761 <6>[ 1.656848] igb: Copyright (c) 2007-2014 Intel Corporation.
10582 01:23:21.332909 <6>[ 1.662683] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10583 01:23:21.339662 <6>[ 1.669201] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10584 01:23:21.343327 <6>[ 1.675662] sky2: driver version 1.30
10585 01:23:21.349973 <6>[ 1.680641] VFIO - User Level meta-driver version: 0.3
10586 01:23:21.356674 <6>[ 1.688871] usbcore: registered new interface driver usb-storage
10587 01:23:21.363402 <6>[ 1.695315] usbcore: registered new device driver onboard-usb-hub
10588 01:23:21.372562 <6>[ 1.704463] mt6397-rtc mt6359-rtc: registered as rtc0
10589 01:23:21.382104 <6>[ 1.709925] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-23T01:23:21 UTC (1713835401)
10590 01:23:21.385874 <6>[ 1.719487] i2c_dev: i2c /dev entries driver
10591 01:23:21.402419 <6>[ 1.731233] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10592 01:23:21.409007 <4>[ 1.739964] cpu cpu0: supply cpu not found, using dummy regulator
10593 01:23:21.415984 <4>[ 1.746384] cpu cpu1: supply cpu not found, using dummy regulator
10594 01:23:21.422667 <4>[ 1.752789] cpu cpu2: supply cpu not found, using dummy regulator
10595 01:23:21.428916 <4>[ 1.759193] cpu cpu3: supply cpu not found, using dummy regulator
10596 01:23:21.435581 <4>[ 1.765588] cpu cpu4: supply cpu not found, using dummy regulator
10597 01:23:21.442466 <4>[ 1.772000] cpu cpu5: supply cpu not found, using dummy regulator
10598 01:23:21.449148 <4>[ 1.778396] cpu cpu6: supply cpu not found, using dummy regulator
10599 01:23:21.455738 <4>[ 1.784796] cpu cpu7: supply cpu not found, using dummy regulator
10600 01:23:21.473455 <6>[ 1.805435] cpu cpu0: EM: created perf domain
10601 01:23:21.476416 <6>[ 1.810380] cpu cpu4: EM: created perf domain
10602 01:23:21.484283 <6>[ 1.815933] sdhci: Secure Digital Host Controller Interface driver
10603 01:23:21.490398 <6>[ 1.822368] sdhci: Copyright(c) Pierre Ossman
10604 01:23:21.497029 <6>[ 1.827330] Synopsys Designware Multimedia Card Interface Driver
10605 01:23:21.503925 <6>[ 1.833963] sdhci-pltfm: SDHCI platform and OF driver helper
10606 01:23:21.506956 <6>[ 1.833991] mmc0: CQHCI version 5.10
10607 01:23:21.513463 <6>[ 1.844206] ledtrig-cpu: registered to indicate activity on CPUs
10608 01:23:21.520701 <6>[ 1.851142] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10609 01:23:21.527065 <6>[ 1.858200] usbcore: registered new interface driver usbhid
10610 01:23:21.530272 <6>[ 1.864024] usbhid: USB HID core driver
10611 01:23:21.537311 <6>[ 1.868226] spi_master spi0: will run message pump with realtime priority
10612 01:23:21.581243 <6>[ 1.906792] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10613 01:23:21.599693 <6>[ 1.921948] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10614 01:23:21.603438 <6>[ 1.935491] mmc0: Command Queue Engine enabled
10615 01:23:21.610238 <6>[ 1.940227] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10616 01:23:21.617164 <6>[ 1.947691] mmcblk0: mmc0:0001 DA4128 116 GiB
10617 01:23:21.620069 <6>[ 1.952655] cros-ec-spi spi0.0: Chrome EC device registered
10618 01:23:21.627461 <6>[ 1.956213] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10619 01:23:21.633462 <6>[ 1.965486] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10620 01:23:21.640435 <6>[ 1.971519] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10621 01:23:21.646909 <6>[ 1.977819] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10622 01:23:21.663803 <6>[ 1.992911] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10623 01:23:21.671817 <6>[ 2.003543] NET: Registered PF_PACKET protocol family
10624 01:23:21.674955 <6>[ 2.008939] 9pnet: Installing 9P2000 support
10625 01:23:21.681723 <5>[ 2.013501] Key type dns_resolver registered
10626 01:23:21.684587 <6>[ 2.018470] registered taskstats version 1
10627 01:23:21.691264 <5>[ 2.022867] Loading compiled-in X.509 certificates
10628 01:23:21.722038 <4>[ 2.047328] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10629 01:23:21.732291 <4>[ 2.058156] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10630 01:23:21.738455 <3>[ 2.068704] debugfs: File 'uA_load' in directory '/' already present!
10631 01:23:21.745409 <3>[ 2.075406] debugfs: File 'min_uV' in directory '/' already present!
10632 01:23:21.751985 <3>[ 2.082013] debugfs: File 'max_uV' in directory '/' already present!
10633 01:23:21.758176 <3>[ 2.088620] debugfs: File 'constraint_flags' in directory '/' already present!
10634 01:23:21.769263 <3>[ 2.098430] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10635 01:23:21.778882 <6>[ 2.110784] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10636 01:23:21.785454 <6>[ 2.117511] xhci-mtk 11200000.usb: xHCI Host Controller
10637 01:23:21.792129 <6>[ 2.123024] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10638 01:23:21.802190 <6>[ 2.130867] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10639 01:23:21.808855 <6>[ 2.140286] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10640 01:23:21.815732 <6>[ 2.146354] xhci-mtk 11200000.usb: xHCI Host Controller
10641 01:23:21.822399 <6>[ 2.151829] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10642 01:23:21.829229 <6>[ 2.159477] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10643 01:23:21.835400 <6>[ 2.167267] hub 1-0:1.0: USB hub found
10644 01:23:21.838445 <6>[ 2.171290] hub 1-0:1.0: 1 port detected
10645 01:23:21.845311 <6>[ 2.175560] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10646 01:23:21.851989 <6>[ 2.184250] hub 2-0:1.0: USB hub found
10647 01:23:21.855547 <6>[ 2.188268] hub 2-0:1.0: 1 port detected
10648 01:23:21.863763 <6>[ 2.196087] mtk-msdc 11f70000.mmc: Got CD GPIO
10649 01:23:21.875304 <6>[ 2.204018] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10650 01:23:21.882196 <6>[ 2.212043] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10651 01:23:21.891878 <4>[ 2.219969] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10652 01:23:21.901792 <6>[ 2.229496] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10653 01:23:21.908425 <6>[ 2.237576] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10654 01:23:21.915124 <6>[ 2.245591] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10655 01:23:21.925067 <6>[ 2.253504] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10656 01:23:21.931900 <6>[ 2.261323] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10657 01:23:21.941783 <6>[ 2.269139] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10658 01:23:21.951440 <6>[ 2.279589] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10659 01:23:21.958112 <6>[ 2.287960] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10660 01:23:21.968488 <6>[ 2.296298] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10661 01:23:21.974610 <6>[ 2.304637] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10662 01:23:21.985214 <6>[ 2.312974] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10663 01:23:21.991400 <6>[ 2.321312] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10664 01:23:22.001590 <6>[ 2.329650] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10665 01:23:22.007806 <6>[ 2.337988] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10666 01:23:22.018022 <6>[ 2.346326] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10667 01:23:22.024235 <6>[ 2.354664] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10668 01:23:22.034125 <6>[ 2.363001] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10669 01:23:22.040778 <6>[ 2.371338] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10670 01:23:22.050657 <6>[ 2.379676] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10671 01:23:22.061126 <6>[ 2.388016] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10672 01:23:22.067939 <6>[ 2.396354] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10673 01:23:22.073928 <6>[ 2.405119] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10674 01:23:22.080941 <6>[ 2.412314] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10675 01:23:22.087165 <6>[ 2.419080] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10676 01:23:22.093795 <6>[ 2.425855] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10677 01:23:22.104068 <6>[ 2.432784] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10678 01:23:22.110857 <6>[ 2.439628] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10679 01:23:22.120702 <6>[ 2.448758] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10680 01:23:22.130432 <6>[ 2.457877] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10681 01:23:22.140808 <6>[ 2.467170] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10682 01:23:22.150481 <6>[ 2.476639] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10683 01:23:22.157207 <6>[ 2.486105] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10684 01:23:22.166997 <6>[ 2.495225] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10685 01:23:22.176999 <6>[ 2.504702] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10686 01:23:22.187022 <6>[ 2.513821] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10687 01:23:22.196919 <6>[ 2.523116] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10688 01:23:22.206599 <6>[ 2.533276] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10689 01:23:22.216252 <6>[ 2.545251] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10690 01:23:22.223077 <6>[ 2.554799] Trying to probe devices needed for running init ...
10691 01:23:22.246608 <6>[ 2.575392] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10692 01:23:22.274689 <6>[ 2.606684] hub 2-1:1.0: USB hub found
10693 01:23:22.277973 <6>[ 2.611139] hub 2-1:1.0: 3 ports detected
10694 01:23:22.286183 <6>[ 2.618127] hub 2-1:1.0: USB hub found
10695 01:23:22.288983 <6>[ 2.622429] hub 2-1:1.0: 3 ports detected
10696 01:23:22.398134 <6>[ 2.727109] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10697 01:23:22.552602 <6>[ 2.885064] hub 1-1:1.0: USB hub found
10698 01:23:22.556167 <6>[ 2.889552] hub 1-1:1.0: 4 ports detected
10699 01:23:22.565988 <6>[ 2.897916] hub 1-1:1.0: USB hub found
10700 01:23:22.569037 <6>[ 2.902211] hub 1-1:1.0: 4 ports detected
10701 01:23:22.638134 <6>[ 2.967315] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10702 01:23:22.889980 <6>[ 3.219145] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10703 01:23:23.023081 <6>[ 3.355073] hub 1-1.4:1.0: USB hub found
10704 01:23:23.026163 <6>[ 3.359747] hub 1-1.4:1.0: 2 ports detected
10705 01:23:23.035588 <6>[ 3.367817] hub 1-1.4:1.0: USB hub found
10706 01:23:23.038982 <6>[ 3.372351] hub 1-1.4:1.0: 2 ports detected
10707 01:23:23.334139 <6>[ 3.663114] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10708 01:23:23.526048 <6>[ 3.855109] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10709 01:23:34.495460 <6>[ 14.832125] ALSA device list:
10710 01:23:34.502044 <6>[ 14.835410] No soundcards found.
10711 01:23:34.510154 <6>[ 14.843385] Freeing unused kernel memory: 8448K
10712 01:23:34.513118 <6>[ 14.848919] Run /init as init process
10713 01:23:34.524411 Loading, please wait...
10714 01:23:34.556398 Starting systemd-udevd version 252.22-1~deb12u1
10715 01:23:34.556489
10716 01:23:34.851139 <6>[ 15.181315] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10717 01:23:34.861236 <6>[ 15.191623] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10718 01:23:34.871215 <6>[ 15.200536] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10719 01:23:34.874909 <6>[ 15.204859] remoteproc remoteproc0: scp is available
10720 01:23:34.884548 <6>[ 15.210862] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10721 01:23:34.891499 <6>[ 15.216278] remoteproc remoteproc0: powering up scp
10722 01:23:34.897813 <3>[ 15.219158] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 01:23:34.904348 <3>[ 15.219196] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 01:23:34.914811 <3>[ 15.219206] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10725 01:23:34.921141 <3>[ 15.219407] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 01:23:34.931048 <3>[ 15.219420] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 01:23:34.937841 <3>[ 15.219428] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10728 01:23:34.948181 <3>[ 15.219437] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 01:23:34.954218 <3>[ 15.219445] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10730 01:23:34.964723 <3>[ 15.219486] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10731 01:23:34.971286 <3>[ 15.219525] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10732 01:23:34.980899 <3>[ 15.219533] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10733 01:23:34.987727 <3>[ 15.219540] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 01:23:34.997321 <3>[ 15.219582] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 01:23:35.003823 <3>[ 15.219590] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 01:23:35.010707 <3>[ 15.219597] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10737 01:23:35.020373 <3>[ 15.219604] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 01:23:35.026866 <3>[ 15.219611] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 01:23:35.037099 <3>[ 15.219641] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 01:23:35.040207 <6>[ 15.223699] mc: Linux media interface: v0.10
10741 01:23:35.050064 <6>[ 15.228350] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10742 01:23:35.053810 <6>[ 15.228384] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10743 01:23:35.059831 <6>[ 15.235784] usbcore: registered new device driver r8152-cfgselector
10744 01:23:35.070241 <4>[ 15.238217] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10745 01:23:35.076926 <6>[ 15.257541] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10746 01:23:35.083269 <4>[ 15.261429] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10747 01:23:35.089991 <6>[ 15.272772] videodev: Linux video capture interface: v2.00
10748 01:23:35.100083 <4>[ 15.281435] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10749 01:23:35.103229 <4>[ 15.281435] Fallback method does not support PEC.
10750 01:23:35.109384 <6>[ 15.352318] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10751 01:23:35.119517 <6>[ 15.360166] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10752 01:23:35.126215 <6>[ 15.360167] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10753 01:23:35.136465 <6>[ 15.366299] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10754 01:23:35.146462 <6>[ 15.366914] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10755 01:23:35.149860 <6>[ 15.367304] pci_bus 0000:00: root bus resource [bus 00-ff]
10756 01:23:35.157002 <6>[ 15.375361] remoteproc remoteproc0: remote processor scp is now up
10757 01:23:35.163685 <6>[ 15.380097] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10758 01:23:35.173598 <6>[ 15.393150] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10759 01:23:35.183305 <6>[ 15.393723] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10760 01:23:35.193454 <6>[ 15.423686] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10761 01:23:35.196549 <6>[ 15.423796] Bluetooth: Core ver 2.22
10762 01:23:35.199697 <6>[ 15.423857] NET: Registered PF_BLUETOOTH protocol family
10763 01:23:35.206630 <6>[ 15.423860] Bluetooth: HCI device and connection manager initialized
10764 01:23:35.212801 <6>[ 15.423876] Bluetooth: HCI socket layer initialized
10765 01:23:35.219575 <6>[ 15.423884] Bluetooth: L2CAP socket layer initialized
10766 01:23:35.223244 <6>[ 15.423898] Bluetooth: SCO socket layer initialized
10767 01:23:35.229387 <6>[ 15.428441] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10768 01:23:35.239909 <6>[ 15.443886] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10769 01:23:35.246023 <6>[ 15.449004] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10770 01:23:35.252800 <6>[ 15.459450] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10771 01:23:35.259202 <6>[ 15.464585] pci 0000:00:00.0: supports D1 D2
10772 01:23:35.266054 <6>[ 15.465267] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10773 01:23:35.272816 <6>[ 15.465723] usbcore: registered new interface driver btusb
10774 01:23:35.282598 <4>[ 15.466365] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10775 01:23:35.289421 <3>[ 15.466375] Bluetooth: hci0: Failed to load firmware file (-2)
10776 01:23:35.292435 <3>[ 15.466378] Bluetooth: hci0: Failed to set up firmware (-2)
10777 01:23:35.302117 <4>[ 15.466382] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10778 01:23:35.315672 <6>[ 15.467181] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10779 01:23:35.321791 <6>[ 15.467372] usbcore: registered new interface driver uvcvideo
10780 01:23:35.331958 <3>[ 15.471582] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10781 01:23:35.338658 <4>[ 15.478865] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10782 01:23:35.345363 <6>[ 15.483611] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10783 01:23:35.354977 <6>[ 15.484856] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10784 01:23:35.361727 <6>[ 15.485001] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10785 01:23:35.368546 <4>[ 15.489364] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10786 01:23:35.378150 <3>[ 15.494548] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10787 01:23:35.384797 <6>[ 15.495883] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10788 01:23:35.388025 <6>[ 15.547100] r8152 2-1.3:1.0 eth0: v1.12.13
10789 01:23:35.398043 <6>[ 15.551476] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10790 01:23:35.401501 <6>[ 15.556799] usbcore: registered new interface driver r8152
10791 01:23:35.411371 <6>[ 15.561897] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10792 01:23:35.414278 <6>[ 15.584176] usbcore: registered new interface driver cdc_ether
10793 01:23:35.424462 <6>[ 15.592220] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10794 01:23:35.428001 <6>[ 15.603934] usbcore: registered new interface driver r8153_ecm
10795 01:23:35.434023 <6>[ 15.609607] pci 0000:01:00.0: supports D1 D2
10796 01:23:35.440954 <6>[ 15.652391] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10797 01:23:35.447198 <6>[ 15.654742] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10798 01:23:35.464585 <6>[ 15.794969] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10799 01:23:35.471575 <6>[ 15.801871] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10800 01:23:35.477873 <6>[ 15.809951] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10801 01:23:35.488076 <6>[ 15.817948] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10802 01:23:35.494881 <6>[ 15.825949] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10803 01:23:35.504907 <6>[ 15.833950] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10804 01:23:35.507713 <6>[ 15.841951] pci 0000:00:00.0: PCI bridge to [bus 01]
10805 01:23:35.517789 <6>[ 15.847167] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10806 01:23:35.524475 <6>[ 15.855305] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10807 01:23:35.531225 <6>[ 15.862152] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10808 01:23:35.537233 <6>[ 15.869020] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10809 01:23:35.555818 <5>[ 15.886019] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10810 01:23:35.577950 <5>[ 15.908242] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10811 01:23:35.584186 <5>[ 15.915432] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10812 01:23:35.594664 <4>[ 15.923847] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10813 01:23:35.597787 <6>[ 15.932738] cfg80211: failed to load regulatory.db
10814 01:23:35.643142 <6>[ 15.973166] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10815 01:23:35.649247 <6>[ 15.980721] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10816 01:23:35.673227 <6>[ 16.007060] mt7921e 0000:01:00.0: ASIC revision: 79610010
10817 01:23:35.777213 <6>[ 16.107229] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10818 01:23:35.780269 <6>[ 16.107229]
10819 01:23:35.798252 Begin: Loading essential drivers ... done.
10820 01:23:35.801759 Begin: Running /scripts/init-premount ... done.
10821 01:23:35.807985 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10822 01:23:35.818380 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10823 01:23:35.821439 Device /sys/class/net/enx0024323078ff found
10824 01:23:35.821541 done.
10825 01:23:35.828204 Begin: Waiting up to 180 secs for any network device to become available ... done.
10826 01:23:35.900786 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10827 01:23:36.045068 <6>[ 16.375698] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10828 01:23:36.796986 <6>[ 17.130143] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10829 01:23:36.901352 <6>[ 17.234992] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10830 01:23:46.885637 IP-Config: no response after 2 secs - giving up
10831 01:23:46.924712 IP-Config: wlp1s0 hardware address d8:f3:bc:78:28:07 mtu 1500 DHCP
10832 01:23:47.627457 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10833 01:23:47.634978 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10834 01:23:47.641261 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10835 01:23:47.647985 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10836 01:23:47.654639 host : mt8192-asurada-spherion-r0-cbg-8
10837 01:23:47.661308 domain : lava-rack
10838 01:23:47.664601 rootserver: 192.168.201.1 rootpath:
10839 01:23:47.667963 filename :
10840 01:23:47.824446 done.
10841 01:23:47.832887 Begin: Running /scripts/nfs-bottom ... done.
10842 01:23:47.842806 Begin: Running /scripts/init-bottom ... done.
10843 01:23:49.219090 <6>[ 29.554464] NET: Registered PF_INET6 protocol family
10844 01:23:49.226453 <6>[ 29.561676] Segment Routing with IPv6
10845 01:23:49.229952 <6>[ 29.565671] In-situ OAM (IOAM) with IPv6
10846 01:23:49.436595 <30>[ 29.745084] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10847 01:23:49.443181 <30>[ 29.778219] systemd[1]: Detected architecture arm64.
10848 01:23:49.454420
10849 01:23:49.457671 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10850 01:23:49.458092
10851 01:23:49.458421
10852 01:23:49.486481 <30>[ 29.821053] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10853 01:23:50.635552 <30>[ 30.967362] systemd[1]: Queued start job for default target graphical.target.
10854 01:23:50.668470 <30>[ 30.999909] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10855 01:23:50.674901 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10856 01:23:50.675439
10857 01:23:50.697026 <30>[ 31.028668] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10858 01:23:50.707189 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10859 01:23:50.707781
10860 01:23:50.725420 <30>[ 31.056716] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10861 01:23:50.735137 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10862 01:23:50.735761
10863 01:23:50.752611 <30>[ 31.084273] systemd[1]: Created slice user.slice - User and Session Slice.
10864 01:23:50.759330 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10865 01:23:50.759911
10866 01:23:50.779310 <30>[ 31.107327] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10867 01:23:50.785618 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10868 01:23:50.789137
10869 01:23:50.806829 <30>[ 31.135260] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10870 01:23:50.813119 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10871 01:23:50.813665
10872 01:23:50.841947 <30>[ 31.163705] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10873 01:23:50.852181 <30>[ 31.183605] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10874 01:23:50.858416 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10875 01:23:50.858912
10876 01:23:50.876017 <30>[ 31.207465] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10877 01:23:50.882731 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10878 01:23:50.885777
10879 01:23:50.903781 <30>[ 31.235541] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10880 01:23:50.914174 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10881 01:23:50.914642
10882 01:23:50.928739 <30>[ 31.263570] systemd[1]: Reached target paths.target - Path Units.
10883 01:23:50.935373 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10884 01:23:50.938802
10885 01:23:50.955841 <30>[ 31.287521] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10886 01:23:50.962370 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10887 01:23:50.962836
10888 01:23:50.976435 <30>[ 31.311234] systemd[1]: Reached target slices.target - Slice Units.
10889 01:23:50.986106 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10890 01:23:50.986650
10891 01:23:51.000309 <30>[ 31.335553] systemd[1]: Reached target swap.target - Swaps.
10892 01:23:51.007501 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10893 01:23:51.007964
10894 01:23:51.027895 <30>[ 31.359557] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10895 01:23:51.038095 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10896 01:23:51.038569
10897 01:23:51.055631 <30>[ 31.387502] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10898 01:23:51.065564 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10899 01:23:51.066190
10900 01:23:51.087222 <30>[ 31.418726] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10901 01:23:51.096984 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10902 01:23:51.097505
10903 01:23:51.113202 <30>[ 31.444542] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10904 01:23:51.122541 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10905 01:23:51.123039
10906 01:23:51.140385 <30>[ 31.471645] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10907 01:23:51.146448 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10908 01:23:51.146981
10909 01:23:51.165010 <30>[ 31.496732] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10910 01:23:51.174649 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10911 01:23:51.175373
10912 01:23:51.194599 <30>[ 31.526436] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10913 01:23:51.204601 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10914 01:23:51.205190
10915 01:23:51.219878 <30>[ 31.551506] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10916 01:23:51.229972 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10917 01:23:51.230502
10918 01:23:51.287819 <30>[ 31.619241] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10919 01:23:51.294118 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10920 01:23:51.294770
10921 01:23:51.315799 <30>[ 31.647512] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10922 01:23:51.322492 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10923 01:23:51.323002
10924 01:23:51.348686 <30>[ 31.680133] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10925 01:23:51.354725 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10926 01:23:51.355315
10927 01:23:51.382075 <30>[ 31.707415] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10928 01:23:51.416370 <30>[ 31.747905] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10929 01:23:51.426404 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10930 01:23:51.426887
10931 01:23:51.449193 <30>[ 31.781023] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10932 01:23:51.455969 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10933 01:23:51.456484
10934 01:23:51.481241 <30>[ 31.812708] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10935 01:23:51.487897 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10936 01:23:51.488406
10937 01:23:51.513799 <30>[ 31.845154] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10938 01:23:51.520300 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10939 01:23:51.520839
10940 01:23:51.530784 <6>[ 31.862595] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10941 01:23:51.544973 <30>[ 31.876245] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10942 01:23:51.554349 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10943 01:23:51.554846
10944 01:23:51.604384 <30>[ 31.935915] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10945 01:23:51.610669 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10946 01:23:51.611306
10947 01:23:51.634943 <30>[ 31.966474] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10948 01:23:51.641561 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10949 01:23:51.642089
10950 01:23:51.650334 <6>[ 31.985386] fuse: init (API version 7.37)
10951 01:23:51.666039 <30>[ 31.997881] systemd[1]: Starting systemd-journald.service - Journal Service...
10952 01:23:51.673008 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10953 01:23:51.673454
10954 01:23:51.739984 <30>[ 32.071979] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10955 01:23:51.746522 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10956 01:23:51.746997
10957 01:23:51.776119 <30>[ 32.104775] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10958 01:23:51.782659 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10959 01:23:51.783098
10960 01:23:51.820042 <3>[ 32.151756] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10961 01:23:51.840290 <30>[ 32.171635] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10962 01:23:51.850474 Startin<3>[ 32.182350] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10963 01:23:51.857102 g [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10964 01:23:51.857595
10965 01:23:51.878991 <30>[ 32.210746] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10966 01:23:51.885465 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10967 01:23:51.885962
10968 01:23:51.899194 <3>[ 32.230755] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 01:23:51.914118 <30>[ 32.245833] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10970 01:23:51.921210 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10971 01:23:51.921698
10972 01:23:51.931266 <3>[ 32.260502] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10973 01:23:51.944636 <30>[ 32.275840] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10974 01:23:51.960865 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue <3>[ 32.290235] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10975 01:23:51.961344 File System.
10976 01:23:51.961802
10977 01:23:51.979911 <30>[ 32.311532] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10978 01:23:51.990416 [[0;32m OK [<3>[ 32.320753] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10979 01:23:51.996053 0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10980 01:23:51.996141
10981 01:23:52.015945 <30>[ 32.347584] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10982 01:23:52.025864 <3>[ 32.349997] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10983 01:23:52.032346 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10984 01:23:52.032463
10985 01:23:52.049381 <30>[ 32.383888] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10986 01:23:52.059140 <3>[ 32.390110] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10987 01:23:52.069381 <30>[ 32.391850] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10988 01:23:52.076330 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10989 01:23:52.076793
10990 01:23:52.088718 <3>[ 32.420521] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10991 01:23:52.099339 <30>[ 32.431175] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10992 01:23:52.105966 <30>[ 32.439368] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10993 01:23:52.119554 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 32.450479] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10994 01:23:52.125877 m_mod.s…e[0m - Load Kernel Module dm_mod.
10995 01:23:52.126346
10996 01:23:52.141142 <30>[ 32.475923] systemd[1]: modprobe@drm.service: Deactivated successfully.
10997 01:23:52.151919 <30>[ 32.483635] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10998 01:23:52.158975 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10999 01:23:52.159428
11000 01:23:52.175858 <30>[ 32.507834] systemd[1]: Started systemd-journald.service - Journal Service.
11001 01:23:52.182653 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11002 01:23:52.183121
11003 01:23:52.205012 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11004 01:23:52.205446
11005 01:23:52.226216 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11006 01:23:52.226657
11007 01:23:52.247027 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11008 01:23:52.247568
11009 01:23:52.265040 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11010 01:23:52.265633
11011 01:23:52.289687 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11012 01:23:52.290127
11013 01:23:52.306952 <4>[ 32.632244] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11014 01:23:52.316827 <3>[ 32.647910] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11015 01:23:52.323259 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11016 01:23:52.323693
11017 01:23:52.346289 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11018 01:23:52.346842
11019 01:23:52.370190 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11020 01:23:52.370651
11021 01:23:52.432222 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11022 01:23:52.432782
11023 01:23:52.458403 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11024 01:23:52.458878
11025 01:23:52.485048 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11026 01:23:52.485616
11027 01:23:52.508861 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11028 01:23:52.508947
11029 01:23:52.558166 <46>[ 32.890021] systemd-journald[314]: Received client request to flush runtime journal.
11030 01:23:52.568153 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11031 01:23:52.568311
11032 01:23:52.594160 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11033 01:23:52.594247
11034 01:23:52.886989 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11035 01:23:52.887133
11036 01:23:52.903800 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11037 01:23:52.903886
11038 01:23:52.924630 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11039 01:23:52.924720
11040 01:23:53.607346 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11041 01:23:53.607490
11042 01:23:53.991023 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11043 01:23:53.991194
11044 01:23:54.024163 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11045 01:23:54.024641
11046 01:23:54.063536 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11047 01:23:54.064199
11048 01:23:54.213227 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11049 01:23:54.213753
11050 01:23:54.231866 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11051 01:23:54.232307
11052 01:23:54.247280 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11053 01:23:54.247842
11054 01:23:54.291550 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11055 01:23:54.292117
11056 01:23:54.312611 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11057 01:23:54.313089
11058 01:23:54.551372 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11059 01:23:54.551521
11060 01:23:54.629753 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11061 01:23:54.630227
11062 01:23:54.675377 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11063 01:23:54.675899
11064 01:23:54.942528 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11065 01:23:54.942676
11066 01:23:54.989279 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11067 01:23:54.989478
11068 01:23:55.027308 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11069 01:23:55.027432
11070 01:23:55.057446 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11071 01:23:55.057570
11072 01:23:55.179727 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11073 01:23:55.180221
11074 01:23:55.198519 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11075 01:23:55.198968
11076 01:23:55.216724 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11077 01:23:55.217153
11078 01:23:55.267278 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11079 01:23:55.267724
11080 01:23:55.280417 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11081 01:23:55.280841
11082 01:23:55.304057 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11083 01:23:55.304487
11084 01:23:55.361116 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11085 01:23:55.361773
11086 01:23:55.381888 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11087 01:23:55.382374
11088 01:23:55.420453 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11089 01:23:55.421016
11090 01:23:55.440111 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11091 01:23:55.440591
11092 01:23:55.460365 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11093 01:23:55.460933
11094 01:23:55.483446 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11095 01:23:55.484178
11096 01:23:55.498798 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11097 01:23:55.499582
11098 01:23:55.528578 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11099 01:23:55.529049
11100 01:23:55.550666 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11101 01:23:55.551175
11102 01:23:55.567570 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11103 01:23:55.568023
11104 01:23:55.587787 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11105 01:23:55.588221
11106 01:23:55.606978 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11107 01:23:55.607407
11108 01:23:55.623411 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11109 01:23:55.623848
11110 01:23:55.641495 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11111 01:23:55.642036
11112 01:23:55.659303 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11113 01:23:55.659789
11114 01:23:55.676448 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11115 01:23:55.676886
11116 01:23:55.725317 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11117 01:23:55.725908
11118 01:23:55.765630 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11119 01:23:55.766127
11120 01:23:55.911699 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11121 01:23:55.911829
11122 01:23:55.949446 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11123 01:23:55.949599
11124 01:23:56.091442 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11125 01:23:56.091646
11126 01:23:56.165208 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11127 01:23:56.165391
11128 01:23:56.186239 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11129 01:23:56.186543
11130 01:23:56.208751 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11131 01:23:56.209217
11132 01:23:56.226383 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11133 01:23:56.226826
11134 01:23:56.262116 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11135 01:23:56.262669
11136 01:23:56.287442 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11137 01:23:56.287957
11138 01:23:56.319413 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11139 01:23:56.320026
11140 01:23:56.339762 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11141 01:23:56.340413
11142 01:23:56.403468 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11143 01:23:56.403610
11144 01:23:56.428219 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11145 01:23:56.428326
11146 01:23:56.487019 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11147 01:23:56.487192
11148 01:23:56.611868 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11149 01:23:56.612551
11150 01:23:56.695096
11151 01:23:56.695741
11152 01:23:56.698319 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11153 01:23:56.698749
11154 01:23:56.701239 debian-bookworm-arm64 login: root (automatic login)
11155 01:23:56.701778
11156 01:23:56.702132
11157 01:23:57.008796 Linux debian-bookworm-arm64 6.1.86-cip19 #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024 aarch64
11158 01:23:57.009453
11159 01:23:57.015431 The programs included with the Debian GNU/Linux system are free software;
11160 01:23:57.021629 the exact distribution terms for each program are described in the
11161 01:23:57.024915 individual files in /usr/share/doc/*/copyright.
11162 01:23:57.025008
11163 01:23:57.031612 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11164 01:23:57.034561 permitted by applicable law.
11165 01:23:57.135113 Matched prompt #10: / #
11167 01:23:57.135365 Setting prompt string to ['/ #']
11168 01:23:57.135457 end: 2.2.5.1 login-action (duration 00:00:38) [common]
11170 01:23:57.135650 end: 2.2.5 auto-login-action (duration 00:00:38) [common]
11171 01:23:57.135743 start: 2.2.6 expect-shell-connection (timeout 00:03:06) [common]
11172 01:23:57.135842 Setting prompt string to ['/ #']
11173 01:23:57.135929 Forcing a shell prompt, looking for ['/ #']
11175 01:23:57.186243 / #
11176 01:23:57.186534 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11177 01:23:57.186750 Waiting using forced prompt support (timeout 00:02:30)
11178 01:23:57.191633
11179 01:23:57.192289 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11180 01:23:57.192752 start: 2.2.7 export-device-env (timeout 00:03:06) [common]
11182 01:23:57.293952 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13468790/extract-nfsrootfs-pagiv9fy'
11183 01:23:57.299942 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13468790/extract-nfsrootfs-pagiv9fy'
11185 01:23:57.401315 / # export NFS_SERVER_IP='192.168.201.1'
11186 01:23:57.407761 export NFS_SERVER_IP='192.168.201.1'
11187 01:23:57.408724 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11188 01:23:57.409245 end: 2.2 depthcharge-retry (duration 00:01:55) [common]
11189 01:23:57.409733 end: 2 depthcharge-action (duration 00:01:55) [common]
11190 01:23:57.410196 start: 3 lava-test-retry (timeout 00:30:00) [common]
11191 01:23:57.410632 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11192 01:23:57.411006 Using namespace: common
11194 01:23:57.512044 / # #
11195 01:23:57.512702 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11196 01:23:57.518852 #
11197 01:23:57.519648 Using /lava-13468790
11199 01:23:57.620856 / # export SHELL=/bin/sh
11200 01:23:57.627510 export SHELL=/bin/sh
11202 01:23:57.729103 / # . /lava-13468790/environment
11203 01:23:57.735899 . /lava-13468790/environment
11205 01:23:57.843677 / # /lava-13468790/bin/lava-test-runner /lava-13468790/0
11206 01:23:57.844293 Test shell timeout: 10s (minimum of the action and connection timeout)
11207 01:23:57.849597 /lava-13468790/bin/lava-test-runner /lava-13468790/0
11208 01:23:58.114110 + export TESTRUN_ID=0_lc-compliance
11209 01:23:58.120874 + cd /lava-13468790/0/tests/0_lc-compliance
11210 01:23:58.120954 + cat uuid
11211 01:23:58.132025 + UUID=13468790_1.6.2.3.1
11212 01:23:58.132102 + set +x
11213 01:23:58.138353 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 13468790_1.6.2.3.1>
11214 01:23:58.138605 Received signal: <STARTRUN> 0_lc-compliance 13468790_1.6.2.3.1
11215 01:23:58.138680 Starting test lava.0_lc-compliance (13468790_1.6.2.3.1)
11216 01:23:58.138765 Skipping test definition patterns.
11217 01:23:58.141778 + /usr/bin/lc-compliance-parser.sh
11218 01:23:59.828061 [0:00:39.988124922] [419] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:284 [0mlibcamera v0.0.0+1-01935edb
11219 01:23:59.831628 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11220 01:23:59.851101 [0:00:40.011226266] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11221 01:23:59.915276 [0:00:40.074509504] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11222 01:23:59.941087 [==========] Running 120 tests from 1 test suite.
11223 01:23:59.969663 [0:00:40.128490951] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11224 01:24:00.023281 [0:00:40.181562809] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11225 01:24:00.037531 [----------] Global test environment set-up.
11226 01:24:00.115486 [----------] 120 tests from CaptureTests/SingleStream
11227 01:24:00.199069 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11228 01:24:00.268072 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11229 01:24:00.268482 Received signal: <TESTSET> START CaptureTests/SingleStream
11230 01:24:00.268619 Starting test_set CaptureTests/SingleStream
11231 01:24:00.271760 Camera needs 4 requests, can't test only 1
11232 01:24:00.355879 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11233 01:24:00.432111
11234 01:24:00.451064 [0:00:40.605644805] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11235 01:24:00.517753 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (64 ms)
11236 01:24:00.616621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11237 01:24:00.616943 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11239 01:24:00.632220 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11240 01:24:00.690671 Camera needs 4 requests, can't test only 2
11241 01:24:00.778374 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11242 01:24:00.863840
11243 01:24:00.952682 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (52 ms)
11244 01:24:01.047848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11245 01:24:01.048174 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11247 01:24:01.064979 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11248 01:24:01.121489 Camera needs 4 requests, can't test only 3
11249 01:24:01.144955 [0:00:41.292995112] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11250 01:24:01.210199 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11251 01:24:01.296419
11252 01:24:01.389168 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (54 ms)
11253 01:24:01.494061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11254 01:24:01.494382 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11256 01:24:01.513343 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11257 01:24:01.572278 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (424 ms)
11258 01:24:01.664679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11259 01:24:01.665006 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11261 01:24:01.684273 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11262 01:24:01.743089 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (686 ms)
11263 01:24:01.835591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11264 01:24:01.835917 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11266 01:24:01.851086 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11267 01:24:02.392199 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (1246 ms)
11268 01:24:02.402158 [0:00:42.539944269] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11269 01:24:02.493385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11270 01:24:02.493743 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11272 01:24:02.511640 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11273 01:24:04.209436 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1805 ms)
11274 01:24:04.219689 [0:00:44.345449781] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11275 01:24:04.308267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11276 01:24:04.308583 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11278 01:24:04.323582 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11279 01:24:05.917478 <6>[ 46.257537] vpu: disabling
11280 01:24:05.920300 <6>[ 46.260611] vproc2: disabling
11281 01:24:05.924178 <6>[ 46.263889] vproc1: disabling
11282 01:24:05.927070 <6>[ 46.267155] vaud18: disabling
11283 01:24:05.933776 <6>[ 46.270566] vsram_others: disabling
11284 01:24:05.937249 <6>[ 46.274515] va09: disabling
11285 01:24:05.940268 <6>[ 46.277673] vsram_md: disabling
11286 01:24:05.943719 <6>[ 46.281206] Vgpu: disabling
11287 01:24:06.937380 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (2714 ms)
11288 01:24:06.946905 [0:00:47.059867059] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11289 01:24:07.043166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11290 01:24:07.043472 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11292 01:24:07.061112 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11293 01:24:11.134695 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (4184 ms)
11294 01:24:11.145066 [0:00:51.244870853] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11295 01:24:11.237647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11296 01:24:11.237973 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11298 01:24:11.254952 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11299 01:24:17.713097 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (6568 ms)
11300 01:24:17.723301 [0:00:57.813157515] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11301 01:24:17.777402 [0:00:57.867745895] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11302 01:24:17.833617 [0:00:57.923754005] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11303 01:24:17.840328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11304 01:24:17.841027 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11306 01:24:17.861975 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11307 01:24:17.889403 [0:00:57.979524661] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11308 01:24:17.924980 Camera needs 4 requests, can't test only 1
11309 01:24:18.007405 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11310 01:24:18.093915
11311 01:24:18.191093 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (55 ms)
11312 01:24:18.312034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11313 01:24:18.312828 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11315 01:24:18.332818 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11316 01:24:18.397381 Camera needs 4 requests, can't test only 2
11317 01:24:18.497132 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11318 01:24:18.585968 [0:00:58.675141504] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11319 01:24:18.597888
11320 01:24:18.702198 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (56 ms)
11321 01:24:18.816363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11322 01:24:18.817116 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11324 01:24:18.837471 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11325 01:24:18.902208 Camera needs 4 requests, can't test only 3
11326 01:24:19.004835 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11327 01:24:19.104206
11328 01:24:19.198725 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (54 ms)
11329 01:24:19.301882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11330 01:24:19.302267 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11332 01:24:19.320470 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11333 01:24:19.380183 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (695 ms)
11334 01:24:19.469788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11335 01:24:19.470112 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11337 01:24:19.493432 [0:00:59.582574115] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11338 01:24:19.496666 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11339 01:24:19.553409 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (907 ms)
11340 01:24:19.657374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11341 01:24:19.657721 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11343 01:24:19.675788 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11344 01:24:20.740062 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1255 ms)
11345 01:24:20.753648 [0:01:00.838098231] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11346 01:24:20.847720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11347 01:24:20.848044 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11349 01:24:20.865463 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11350 01:24:22.558096 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (1817 ms)
11351 01:24:22.571216 [0:01:02.655579293] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11352 01:24:22.667556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11353 01:24:22.667883 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11355 01:24:22.688469 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11356 01:24:25.287582 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (2728 ms)
11357 01:24:25.300365 [0:01:05.383573715] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11358 01:24:25.389537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11359 01:24:25.389857 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11361 01:24:25.410729 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11362 01:24:29.483254 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (4194 ms)
11363 01:24:29.496763 [0:01:09.579214350] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11364 01:24:29.592477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11365 01:24:29.592785 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11367 01:24:29.609944 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11368 01:24:36.060874 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (6576 ms)
11369 01:24:36.073735 [0:01:16.155642910] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11370 01:24:36.126742 [0:01:16.211874486] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11371 01:24:36.161192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11372 01:24:36.161562 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11374 01:24:36.179895 [0:01:16.265290841] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11375 01:24:36.183280 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11376 01:24:36.235463 [0:01:16.320251356] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11377 01:24:36.238341 Camera needs 4 requests, can't test only 1
11378 01:24:36.307179 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11379 01:24:36.384800
11380 01:24:36.467563 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (56 ms)
11381 01:24:36.561098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11382 01:24:36.561442 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11384 01:24:36.577990 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11385 01:24:36.633452 Camera needs 4 requests, can't test only 2
11386 01:24:36.715952 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11387 01:24:36.789265
11388 01:24:36.874732 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (54 ms)
11389 01:24:36.931575 [0:01:17.016734260] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11390 01:24:36.968470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11391 01:24:36.968824 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11393 01:24:36.986010 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11394 01:24:37.039625 Camera needs 4 requests, can't test only 3
11395 01:24:37.122646 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11396 01:24:37.198952
11397 01:24:37.283157 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (54 ms)
11398 01:24:37.378730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11399 01:24:37.379082 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11401 01:24:37.397240 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11402 01:24:37.453885 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (695 ms)
11403 01:24:37.546525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11404 01:24:37.546883 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11406 01:24:37.564336 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11407 01:24:37.828889 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (906 ms)
11408 01:24:37.842399 [0:01:17.923272431] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11409 01:24:37.928342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11410 01:24:37.928652 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11412 01:24:37.945077 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11413 01:24:39.084546 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (1255 ms)
11414 01:24:39.097842 [0:01:19.178983947] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11415 01:24:39.187144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11416 01:24:39.187462 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11418 01:24:39.206309 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11419 01:24:40.900293 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (1815 ms)
11420 01:24:40.913448 [0:01:20.994711125] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11421 01:24:41.003331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11422 01:24:41.003645 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11424 01:24:41.019929 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11425 01:24:43.627905 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (2727 ms)
11426 01:24:43.641301 [0:01:23.722313404] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11427 01:24:43.751236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11428 01:24:43.752107 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11430 01:24:43.771284 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11431 01:24:47.824580 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (4196 ms)
11432 01:24:47.838243 [0:01:27.918597819] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11433 01:24:47.940347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11434 01:24:47.941091 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11436 01:24:47.962815 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11437 01:24:54.400623 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (6576 ms)
11438 01:24:54.413710 [0:01:34.494601978] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11439 01:24:54.462960 [0:01:34.547901721] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11440 01:24:54.503452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11441 01:24:54.503741 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11443 01:24:54.517941 [0:01:34.602993236] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11444 01:24:54.521296 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11445 01:24:54.573349 [0:01:34.657857231] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11446 01:24:54.576655 Camera needs 4 requests, can't test only 1
11447 01:24:54.661782 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11448 01:24:54.745006
11449 01:24:54.835585 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (54 ms)
11450 01:24:54.941721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11451 01:24:54.942028 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11453 01:24:54.959707 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11454 01:24:55.017642 Camera needs 4 requests, can't test only 2
11455 01:24:55.108310 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11456 01:24:55.205421
11457 01:24:55.266830 [0:01:35.351328168] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11458 01:24:55.299593 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (54 ms)
11459 01:24:55.398724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11460 01:24:55.399027 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11462 01:24:55.417474 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11463 01:24:55.475188 Camera needs 4 requests, can't test only 3
11464 01:24:55.562667 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11465 01:24:55.644098
11466 01:24:55.736887 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (55 ms)
11467 01:24:55.838000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11468 01:24:55.838304 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11470 01:24:55.857978 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11471 01:24:55.917485 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (693 ms)
11472 01:24:56.017681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11473 01:24:56.017982 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11475 01:24:56.037868 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11476 01:24:56.162668 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (904 ms)
11477 01:24:56.175700 [0:01:36.255732017] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11478 01:24:56.267248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11479 01:24:56.267571 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11481 01:24:56.285384 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11482 01:24:57.417419 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (1254 ms)
11483 01:24:57.430281 [0:01:37.510020429] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11484 01:24:57.520973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11485 01:24:57.521278 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11487 01:24:57.539829 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11488 01:24:59.231587 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (1814 ms)
11489 01:24:59.244428 [0:01:39.324693696] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11490 01:24:59.328852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11491 01:24:59.329162 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11493 01:24:59.345925 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11494 01:25:01.956850 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (2725 ms)
11495 01:25:01.969390 [0:01:42.050276365] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11496 01:25:02.058437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11497 01:25:02.058792 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11499 01:25:02.075469 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11500 01:25:06.151590 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (4195 ms)
11501 01:25:06.164533 [0:01:46.245361100] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11502 01:25:06.245979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11503 01:25:06.246311 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11505 01:25:06.262469 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11506 01:25:12.726465 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (6575 ms)
11507 01:25:12.739723 [0:01:52.820578439] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11508 01:25:12.788878 [0:01:52.874681604] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11509 01:25:12.824090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11510 01:25:12.824418 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11512 01:25:12.843529 [0:01:52.929092447] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11513 01:25:12.846554 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11514 01:25:12.899377 [0:01:52.985481037] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11515 01:25:12.903008 Camera needs 4 requests, can't test only 1
11516 01:25:12.980400 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11517 01:25:13.060850
11518 01:25:13.148202 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (53 ms)
11519 01:25:13.247784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11520 01:25:13.248116 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11522 01:25:13.263267 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11523 01:25:13.315674 Camera needs 4 requests, can't test only 2
11524 01:25:13.392646 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11525 01:25:13.472553
11526 01:25:13.559999 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (53 ms)
11527 01:25:13.657601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11528 01:25:13.657933 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11530 01:25:13.675590 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11531 01:25:13.730445 Camera needs 4 requests, can't test only 3
11532 01:25:13.812849 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11533 01:25:13.893214
11534 01:25:13.978648 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (56 ms)
11535 01:25:14.077532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11536 01:25:14.077875 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11538 01:25:14.095125 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11539 01:25:14.969946 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (2078 ms)
11540 01:25:14.983733 [0:01:55.064225486] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11541 01:25:15.072821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11542 01:25:15.073124 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11544 01:25:15.090659 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11545 01:25:17.681263 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (2711 ms)
11546 01:25:17.694463 [0:01:57.776052582] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11547 01:25:17.772240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11548 01:25:17.772548 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11550 01:25:17.789248 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11551 01:25:21.439532 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (3758 ms)
11552 01:25:21.453003 [0:02:01.534583194] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11553 01:25:21.543532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11554 01:25:21.543847 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11556 01:25:21.561278 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11557 01:25:26.877090 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (5437 ms)
11558 01:25:26.890056 [0:02:06.972328511] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11559 01:25:26.977593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11560 01:25:26.977922 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11562 01:25:26.994492 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11563 01:25:35.047296 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (8170 ms)
11564 01:25:35.060671 [0:02:15.142970390] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11565 01:25:35.156482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11566 01:25:35.156920 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11568 01:25:35.174439 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11569 01:25:47.625350 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (12576 ms)
11570 01:25:47.638680 [0:02:27.719482851] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11571 01:25:47.728423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11572 01:25:47.728753 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11574 01:25:47.745483 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11575 01:26:07.343118 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (19717 ms)
11576 01:26:07.356063 [0:02:47.437139956] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11577 01:26:07.405708 [0:02:47.491282467] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11578 01:26:07.438728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11579 01:26:07.439025 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11581 01:26:07.460099 [0:02:47.545764172] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11582 01:26:07.466537 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11583 01:26:07.515288 [0:02:47.601050327] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11584 01:26:07.518676 Camera needs 4 requests, can't test only 1
11585 01:26:07.598983 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11586 01:26:07.678946
11587 01:26:07.775681 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (53 ms)
11588 01:26:07.857736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11589 01:26:07.858095 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11591 01:26:07.874133 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11592 01:26:07.929845 Camera needs 4 requests, can't test only 2
11593 01:26:08.010764 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11594 01:26:08.079959
11595 01:26:08.168963 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (54 ms)
11596 01:26:08.262040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11597 01:26:08.262379 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11599 01:26:08.275998 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11600 01:26:08.332801 Camera needs 4 requests, can't test only 3
11601 01:26:08.415192 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11602 01:26:08.493570
11603 01:26:08.586174 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (54 ms)
11604 01:26:08.684984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11605 01:26:08.685293 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11607 01:26:08.699361 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11608 01:26:09.589246 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (2079 ms)
11609 01:26:09.599553 [0:02:49.680158194] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11610 01:26:09.686793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11611 01:26:09.687106 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11613 01:26:09.700448 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11614 01:26:12.297837 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (2707 ms)
11615 01:26:12.307473 [0:02:52.387986252] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11616 01:26:12.404521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11617 01:26:12.404856 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11619 01:26:12.420418 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11620 01:26:16.054955 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (3757 ms)
11621 01:26:16.065065 [0:02:56.145543447] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11622 01:26:16.175358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11623 01:26:16.176119 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11625 01:26:16.193343 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11626 01:26:21.492293 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (5437 ms)
11627 01:26:21.502488 [0:03:01.583065353] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11628 01:26:21.606423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11629 01:26:21.606718 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11631 01:26:21.620264 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11632 01:26:29.661256 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (8169 ms)
11633 01:26:29.671023 [0:03:09.752212404] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11634 01:26:29.780177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11635 01:26:29.780939 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11637 01:26:29.795548 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11638 01:26:42.239043 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (12578 ms)
11639 01:26:42.249278 [0:03:22.330933922] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11640 01:26:42.344929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11641 01:26:42.345226 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11643 01:26:42.358808 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11644 01:27:01.958212 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (19719 ms)
11645 01:27:01.967874 [0:03:42.050627184] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11646 01:27:02.016882 [0:03:42.104206358] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11647 01:27:02.058726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11648 01:27:02.059043 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11650 01:27:02.068655 [0:03:42.158000380] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11651 01:27:02.075254 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11652 01:27:02.123500 [0:03:42.211211054] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11653 01:27:02.131388 Camera needs 4 requests, can't test only 1
11654 01:27:02.218337 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11655 01:27:02.299187
11656 01:27:02.392999 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (53 ms)
11657 01:27:02.494673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11658 01:27:02.494990 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11660 01:27:02.510726 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11661 01:27:02.570518 Camera needs 4 requests, can't test only 2
11662 01:27:02.656313 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11663 01:27:02.748918
11664 01:27:02.855204 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (53 ms)
11665 01:27:02.968977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11666 01:27:02.969332 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11668 01:27:02.985944 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11669 01:27:03.051840 Camera needs 4 requests, can't test only 3
11670 01:27:03.148298 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11671 01:27:03.239683
11672 01:27:03.343637 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (53 ms)
11673 01:27:03.461533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11674 01:27:03.461864 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11676 01:27:03.478261 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11677 01:27:04.196507 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (2077 ms)
11678 01:27:04.206148 [0:03:44.289065831] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11679 01:27:04.298433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11680 01:27:04.298819 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11682 01:27:04.312858 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11683 01:27:06.903212 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (2706 ms)
11684 01:27:06.913427 [0:03:46.996086825] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11685 01:27:06.999542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11686 01:27:06.999858 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11688 01:27:07.014469 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11689 01:27:10.660964 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (3757 ms)
11690 01:27:10.670527 [0:03:50.754111796] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11691 01:27:10.760225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11692 01:27:10.760586 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11694 01:27:10.774989 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11695 01:27:16.098323 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (5437 ms)
11696 01:27:16.108244 [0:03:56.192236632] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11697 01:27:16.201201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11698 01:27:16.201500 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11700 01:27:16.216082 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11701 01:27:24.268939 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (8170 ms)
11702 01:27:24.278875 [0:04:04.363785979] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11703 01:27:24.373387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11704 01:27:24.374374 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11706 01:27:24.389193 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11707 01:27:36.848513 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (12580 ms)
11708 01:27:36.858032 [0:04:16.943860218] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11709 01:27:36.956447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11710 01:27:36.956754 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11712 01:27:36.972143 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11713 01:27:56.568349 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (19718 ms)
11714 01:27:56.578236 [0:04:36.663099629] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11715 01:27:56.627870 [0:04:36.716623308] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11716 01:27:56.672712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11717 01:27:56.672991 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11719 01:27:56.682709 [0:04:36.773126037] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11720 01:27:56.689266 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11721 01:27:56.738938 [0:04:36.827313453] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11722 01:27:56.742169 Camera needs 4 requests, can't test only 1
11723 01:27:56.823172 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11724 01:27:56.906090
11725 01:27:56.999378 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (54 ms)
11726 01:27:57.099539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11727 01:27:57.099841 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11729 01:27:57.113393 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11730 01:27:57.171323 Camera needs 4 requests, can't test only 2
11731 01:27:57.257497 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11732 01:27:57.340339
11733 01:27:57.428376 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (56 ms)
11734 01:27:57.523541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11735 01:27:57.523847 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11737 01:27:57.535416 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11738 01:27:57.588079 Camera needs 4 requests, can't test only 3
11739 01:27:57.669903 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11740 01:27:57.750314
11741 01:27:57.838932 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (53 ms)
11742 01:27:57.931044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11743 01:27:57.931451 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11745 01:27:57.948505 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11746 01:27:58.814981 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (2081 ms)
11747 01:27:58.824511 [0:04:38.908999121] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11748 01:27:58.932643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11749 01:27:58.933462 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11751 01:27:58.954155 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11752 01:28:01.522808 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (2707 ms)
11753 01:28:01.532497 [0:04:41.617667958] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11754 01:28:01.620370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11755 01:28:01.620704 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11757 01:28:01.635061 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11758 01:28:05.282341 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (3759 ms)
11759 01:28:05.292526 [0:04:45.376641206] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11760 01:28:05.380386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11761 01:28:05.380756 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11763 01:28:05.395272 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11764 01:28:10.721337 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (5438 ms)
11765 01:28:10.730712 [0:04:50.815181412] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11766 01:28:10.829368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11767 01:28:10.829672 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11769 01:28:10.846682 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11770 01:28:18.893599 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (8171 ms)
11771 01:28:18.903044 [0:04:58.986617737] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11772 01:28:19.009782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11773 01:28:19.010528 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11775 01:28:19.029356 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11776 01:28:31.471836 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (12578 ms)
11777 01:28:31.481840 [0:05:11.565809944] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11778 01:28:31.564568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11779 01:28:31.565012 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11781 01:28:31.577870 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11782 01:28:51.191840 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (19719 ms)
11783 01:28:51.201761 [0:05:31.285111743] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11784 01:28:51.301086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11785 01:28:51.301388 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11787 01:28:51.317482 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11788 01:28:51.604003 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (415 ms)
11789 01:28:51.616897 [0:05:31.700740615] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11790 01:28:51.710190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11791 01:28:51.710518 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11793 01:28:51.728284 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11794 01:28:52.091621 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (487 ms)
11795 01:28:52.104659 [0:05:32.188185090] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11796 01:28:52.192023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11797 01:28:52.192319 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11799 01:28:52.209445 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11800 01:28:52.646548 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (555 ms)
11801 01:28:52.659930 [0:05:32.743504987] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11802 01:28:52.750840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11803 01:28:52.751144 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11805 01:28:52.770357 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11806 01:28:53.342542 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (695 ms)
11807 01:28:53.355139 [0:05:33.439177707] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11808 01:28:53.444816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11809 01:28:53.445114 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11811 01:28:53.462849 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11812 01:28:54.248638 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (906 ms)
11813 01:28:54.261981 [0:05:34.345383849] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11814 01:28:54.355376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11815 01:28:54.355668 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11817 01:28:54.375292 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11818 01:28:55.504798 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (1256 ms)
11819 01:28:55.518053 [0:05:35.601749812] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11820 01:28:55.609759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11821 01:28:55.610062 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11823 01:28:55.627253 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11824 01:28:57.320716 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (1815 ms)
11825 01:28:57.333655 [0:05:37.417218521] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11826 01:28:57.426508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11827 01:28:57.426814 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11829 01:28:57.445748 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11830 01:29:00.046026 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (2725 ms)
11831 01:29:00.059221 [0:05:40.142982081] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11832 01:29:00.152869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11833 01:29:00.153216 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11835 01:29:00.170895 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11836 01:29:04.241805 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (4196 ms)
11837 01:29:04.255016 [0:05:44.339180897] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11838 01:29:04.341123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11839 01:29:04.341480 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11841 01:29:04.359095 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11842 01:29:10.818978 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (6576 ms)
11843 01:29:10.831913 [0:05:50.916108640] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11844 01:29:10.923957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11845 01:29:10.924280 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11847 01:29:10.942793 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11848 01:29:11.237494 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (415 ms)
11849 01:29:11.247496 [0:05:51.331232803] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11850 01:29:11.336432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11851 01:29:11.336867 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11853 01:29:11.352738 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11854 01:29:11.724018 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (486 ms)
11855 01:29:11.734105 [0:05:51.817455364] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11856 01:29:11.821279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11857 01:29:11.821570 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11859 01:29:11.835235 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11860 01:29:12.279618 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (555 ms)
11861 01:29:12.289131 [0:05:52.373443806] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11862 01:29:12.384546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11863 01:29:12.384843 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11865 01:29:12.400585 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11866 01:29:12.975580 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (696 ms)
11867 01:29:12.985961 [0:05:53.069267222] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11868 01:29:13.077501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11869 01:29:13.077891 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11871 01:29:13.091542 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11872 01:29:13.883175 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (907 ms)
11873 01:29:13.892761 [0:05:53.976520179] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11874 01:29:13.977405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11875 01:29:13.977797 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11877 01:29:13.991907 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11878 01:29:15.138103 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (1255 ms)
11879 01:29:15.148219 [0:05:55.232187520] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11880 01:29:15.232026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11881 01:29:15.232372 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11883 01:29:15.245660 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11884 01:29:16.954131 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (1815 ms)
11885 01:29:16.963933 [0:05:57.048166233] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11886 01:29:17.055565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11887 01:29:17.055865 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11889 01:29:17.069584 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11890 01:29:19.681975 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (2728 ms)
11891 01:29:19.692099 [0:05:59.776251096] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11892 01:29:19.784959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11893 01:29:19.785256 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11895 01:29:19.797980 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11896 01:29:23.878131 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (4195 ms)
11897 01:29:23.887835 [0:06:03.971903944] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11898 01:29:23.971862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11899 01:29:23.972156 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11901 01:29:23.984803 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11902 01:29:30.454517 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (6576 ms)
11903 01:29:30.464323 [0:06:10.548625577] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11904 01:29:30.578060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11905 01:29:30.578857 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11907 01:29:30.596762 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11908 01:29:30.870878 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (416 ms)
11909 01:29:30.880731 [0:06:10.964736474] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11910 01:29:30.987802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11911 01:29:30.988628 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11913 01:29:31.005746 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11914 01:29:31.357389 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (485 ms)
11915 01:29:31.366513 [0:06:11.450662995] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11916 01:29:31.473034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11917 01:29:31.473846 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11919 01:29:31.489882 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11920 01:29:31.913259 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (556 ms)
11921 01:29:31.923032 [0:06:12.006975346] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11922 01:29:32.019706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11923 01:29:32.020028 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11925 01:29:32.035160 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11926 01:29:32.608776 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (695 ms)
11927 01:29:32.618732 [0:06:12.703030329] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11928 01:29:32.713143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11929 01:29:32.713483 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11931 01:29:32.727600 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11932 01:29:33.516605 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (907 ms)
11933 01:29:33.526948 [0:06:13.610927794] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11934 01:29:33.624286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11935 01:29:33.624781 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11937 01:29:33.639808 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11938 01:29:34.772794 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (1255 ms)
11939 01:29:34.782363 [0:06:14.866925980] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11940 01:29:34.876696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11941 01:29:34.877009 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11943 01:29:34.890017 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11944 01:29:36.588007 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (1815 ms)
11945 01:29:36.597727 [0:06:16.681483239] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11946 01:29:36.686886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11947 01:29:36.687184 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11949 01:29:36.701584 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11950 01:29:39.312679 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (2724 ms)
11951 01:29:39.322457 [0:06:19.407124478] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11952 01:29:39.403316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11953 01:29:39.403625 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11955 01:29:39.415123 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11956 01:29:43.509171 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (4196 ms)
11957 01:29:43.518937 [0:06:23.603893882] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11958 01:29:43.606981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11959 01:29:43.607328 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11961 01:29:43.621036 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11962 01:29:50.085503 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (6576 ms)
11963 01:29:50.095789 [0:06:30.180511894] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11964 01:29:50.189286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11965 01:29:50.189550 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11967 01:29:50.203133 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11968 01:29:50.500980 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (415 ms)
11969 01:29:50.510729 [0:06:30.595965504] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11970 01:29:50.604308 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11972 01:29:50.606921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11973 01:29:50.622601 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11974 01:29:50.987019 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (485 ms)
11975 01:29:50.996616 [0:06:31.081711756] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11976 01:29:51.089144 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11978 01:29:51.092048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11979 01:29:51.108565 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11980 01:29:51.542916 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (555 ms)
11981 01:29:51.552441 [0:06:31.637539798] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11982 01:29:51.649358 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11984 01:29:51.652731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11985 01:29:51.669194 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11986 01:29:52.238181 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (695 ms)
11987 01:29:52.248184 [0:06:32.333467489] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11988 01:29:52.332994 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11990 01:29:52.335557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11991 01:29:52.349660 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11992 01:29:53.145025 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (906 ms)
11993 01:29:53.154610 [0:06:33.240128747] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11994 01:29:53.239993 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11996 01:29:53.243361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11997 01:29:53.258469 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11998 01:29:54.400933 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (1256 ms)
11999 01:29:54.410980 [0:06:34.496192759] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
12000 01:29:54.494496 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
12002 01:29:54.497354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
12003 01:29:54.511099 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
12004 01:29:56.217565 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (1816 ms)
12005 01:29:56.227297 [0:06:36.312631364] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
12006 01:29:56.318948 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
12008 01:29:56.322245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
12009 01:29:56.336867 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
12010 01:29:58.944365 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (2726 ms)
12011 01:29:58.953979 [0:06:39.038908534] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
12012 01:29:59.041148 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
12014 01:29:59.044319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
12015 01:29:59.057034 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
12016 01:30:03.139294 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (4195 ms)
12017 01:30:03.149354 [0:06:43.234654776] [419] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
12018 01:30:03.238811 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
12020 01:30:03.241636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
12021 01:30:03.256179 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
12022 01:30:09.715897 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (6576 ms)
12023 01:30:09.803991 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
12025 01:30:09.806919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
12026 01:30:09.820679 [----------] 120 tests from CaptureTests/SingleStream (369800 ms total)
12027 01:30:09.897181
12028 01:30:09.979385 [----------] Global test environment tear-down
12029 01:30:10.057011 [==========] 120 tests from 1 test suite ran. (369801 ms total)
12030 01:30:10.134176 <LAVA_SIGNAL_TESTSET STOP>
12031 01:30:10.134462 Received signal: <TESTSET> STOP
12032 01:30:10.134542 Closing test_set CaptureTests/SingleStream
12033 01:30:10.137612 + set +x
12034 01:30:10.141190 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 13468790_1.6.2.3.1>
12035 01:30:10.141441 Received signal: <ENDRUN> 0_lc-compliance 13468790_1.6.2.3.1
12036 01:30:10.141529 Ending use of test pattern.
12037 01:30:10.141631 Ending test lava.0_lc-compliance (13468790_1.6.2.3.1), duration 372.00
12039 01:30:10.144122 <LAVA_TEST_RUNNER EXIT>
12040 01:30:10.144371 ok: lava_test_shell seems to have completed
12041 01:30:10.146183 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
12042 01:30:10.146357 end: 3.1 lava-test-shell (duration 00:06:13) [common]
12043 01:30:10.146443 end: 3 lava-test-retry (duration 00:06:13) [common]
12044 01:30:10.146529 start: 4 finalize (timeout 00:10:00) [common]
12045 01:30:10.146616 start: 4.1 power-off (timeout 00:00:30) [common]
12046 01:30:10.146766 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
12047 01:30:10.221859 >> Command sent successfully.
12048 01:30:10.224135 Returned 0 in 0 seconds
12049 01:30:10.324523 end: 4.1 power-off (duration 00:00:00) [common]
12051 01:30:10.324832 start: 4.2 read-feedback (timeout 00:10:00) [common]
12052 01:30:10.325100 Listened to connection for namespace 'common' for up to 1s
12053 01:30:11.325603 Finalising connection for namespace 'common'
12054 01:30:11.325771 Disconnecting from shell: Finalise
12055 01:30:11.325855 / #
12056 01:30:11.426180 end: 4.2 read-feedback (duration 00:00:01) [common]
12057 01:30:11.426377 end: 4 finalize (duration 00:00:01) [common]
12058 01:30:11.426523 Cleaning after the job
12059 01:30:11.426653 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468790/tftp-deploy-0zi91qtm/ramdisk
12060 01:30:11.429053 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468790/tftp-deploy-0zi91qtm/kernel
12061 01:30:11.439785 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468790/tftp-deploy-0zi91qtm/dtb
12062 01:30:11.439965 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468790/tftp-deploy-0zi91qtm/nfsrootfs
12063 01:30:11.481692 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468790/tftp-deploy-0zi91qtm/modules
12064 01:30:11.487468 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13468790
12065 01:30:11.761486 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13468790
12066 01:30:11.761705 Job finished correctly