Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 22
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 14:42:23.578516 lava-dispatcher, installed at version: 2024.03
2 14:42:23.578727 start: 0 validate
3 14:42:23.578858 Start time: 2024-06-04 14:42:23.578850+00:00 (UTC)
4 14:42:23.578975 Using caching service: 'http://localhost/cache/?uri=%s'
5 14:42:23.579108 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 14:42:23.840846 Using caching service: 'http://localhost/cache/?uri=%s'
7 14:42:23.841713 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 14:43:46.921379 Using caching service: 'http://localhost/cache/?uri=%s'
9 14:43:46.921541 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 14:43:47.179119 Using caching service: 'http://localhost/cache/?uri=%s'
11 14:43:47.179630 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 14:43:47.715713 validate duration: 84.14
14 14:43:47.717117 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 14:43:47.717930 start: 1.1 download-retry (timeout 00:10:00) [common]
16 14:43:47.718556 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 14:43:47.719209 Not decompressing ramdisk as can be used compressed.
18 14:43:47.719700 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 14:43:47.720081 saving as /var/lib/lava/dispatcher/tmp/14167015/tftp-deploy-r735clyv/ramdisk/rootfs.cpio.gz
20 14:43:47.720423 total size: 8181887 (7 MB)
21 14:43:47.983998 progress 0 % (0 MB)
22 14:43:47.986652 progress 5 % (0 MB)
23 14:43:47.988758 progress 10 % (0 MB)
24 14:43:47.991045 progress 15 % (1 MB)
25 14:43:47.993132 progress 20 % (1 MB)
26 14:43:47.995421 progress 25 % (1 MB)
27 14:43:47.997544 progress 30 % (2 MB)
28 14:43:47.999820 progress 35 % (2 MB)
29 14:43:48.001933 progress 40 % (3 MB)
30 14:43:48.004177 progress 45 % (3 MB)
31 14:43:48.006323 progress 50 % (3 MB)
32 14:43:48.008501 progress 55 % (4 MB)
33 14:43:48.010540 progress 60 % (4 MB)
34 14:43:48.012720 progress 65 % (5 MB)
35 14:43:48.014719 progress 70 % (5 MB)
36 14:43:48.016885 progress 75 % (5 MB)
37 14:43:48.018946 progress 80 % (6 MB)
38 14:43:48.021100 progress 85 % (6 MB)
39 14:43:48.023183 progress 90 % (7 MB)
40 14:43:48.025488 progress 95 % (7 MB)
41 14:43:48.027635 progress 100 % (7 MB)
42 14:43:48.027859 7 MB downloaded in 0.31 s (25.38 MB/s)
43 14:43:48.028085 end: 1.1.1 http-download (duration 00:00:00) [common]
45 14:43:48.028451 end: 1.1 download-retry (duration 00:00:00) [common]
46 14:43:48.028568 start: 1.2 download-retry (timeout 00:10:00) [common]
47 14:43:48.028680 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 14:43:48.028856 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 14:43:48.028954 saving as /var/lib/lava/dispatcher/tmp/14167015/tftp-deploy-r735clyv/kernel/Image
50 14:43:48.029042 total size: 54682112 (52 MB)
51 14:43:48.029134 No compression specified
52 14:43:48.030781 progress 0 % (0 MB)
53 14:43:48.044983 progress 5 % (2 MB)
54 14:43:48.058912 progress 10 % (5 MB)
55 14:43:48.073136 progress 15 % (7 MB)
56 14:43:48.087084 progress 20 % (10 MB)
57 14:43:48.101180 progress 25 % (13 MB)
58 14:43:48.115519 progress 30 % (15 MB)
59 14:43:48.130103 progress 35 % (18 MB)
60 14:43:48.144282 progress 40 % (20 MB)
61 14:43:48.159145 progress 45 % (23 MB)
62 14:43:48.173837 progress 50 % (26 MB)
63 14:43:48.188083 progress 55 % (28 MB)
64 14:43:48.202587 progress 60 % (31 MB)
65 14:43:48.216879 progress 65 % (33 MB)
66 14:43:48.231511 progress 70 % (36 MB)
67 14:43:48.246133 progress 75 % (39 MB)
68 14:43:48.260628 progress 80 % (41 MB)
69 14:43:48.275531 progress 85 % (44 MB)
70 14:43:48.290466 progress 90 % (46 MB)
71 14:43:48.304817 progress 95 % (49 MB)
72 14:43:48.319389 progress 100 % (52 MB)
73 14:43:48.319650 52 MB downloaded in 0.29 s (179.45 MB/s)
74 14:43:48.319808 end: 1.2.1 http-download (duration 00:00:00) [common]
76 14:43:48.320033 end: 1.2 download-retry (duration 00:00:00) [common]
77 14:43:48.320118 start: 1.3 download-retry (timeout 00:09:59) [common]
78 14:43:48.320264 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 14:43:48.320400 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 14:43:48.320469 saving as /var/lib/lava/dispatcher/tmp/14167015/tftp-deploy-r735clyv/dtb/mt8192-asurada-spherion-r0.dtb
81 14:43:48.320540 total size: 47258 (0 MB)
82 14:43:48.320632 No compression specified
83 14:43:48.321890 progress 69 % (0 MB)
84 14:43:48.322165 progress 100 % (0 MB)
85 14:43:48.322323 0 MB downloaded in 0.00 s (25.30 MB/s)
86 14:43:48.322445 end: 1.3.1 http-download (duration 00:00:00) [common]
88 14:43:48.322673 end: 1.3 download-retry (duration 00:00:00) [common]
89 14:43:48.322785 start: 1.4 download-retry (timeout 00:09:59) [common]
90 14:43:48.322877 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 14:43:48.322989 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 14:43:48.323056 saving as /var/lib/lava/dispatcher/tmp/14167015/tftp-deploy-r735clyv/modules/modules.tar
93 14:43:48.323114 total size: 8608920 (8 MB)
94 14:43:48.323174 Using unxz to decompress xz
95 14:43:48.328037 progress 0 % (0 MB)
96 14:43:48.347630 progress 5 % (0 MB)
97 14:43:48.376646 progress 10 % (0 MB)
98 14:43:48.407369 progress 15 % (1 MB)
99 14:43:48.432271 progress 20 % (1 MB)
100 14:43:48.457740 progress 25 % (2 MB)
101 14:43:48.483105 progress 30 % (2 MB)
102 14:43:48.507867 progress 35 % (2 MB)
103 14:43:48.535681 progress 40 % (3 MB)
104 14:43:48.559967 progress 45 % (3 MB)
105 14:43:48.585609 progress 50 % (4 MB)
106 14:43:48.613266 progress 55 % (4 MB)
107 14:43:48.639287 progress 60 % (4 MB)
108 14:43:48.665188 progress 65 % (5 MB)
109 14:43:48.691972 progress 70 % (5 MB)
110 14:43:48.719906 progress 75 % (6 MB)
111 14:43:48.747713 progress 80 % (6 MB)
112 14:43:48.774087 progress 85 % (7 MB)
113 14:43:48.801481 progress 90 % (7 MB)
114 14:43:48.828705 progress 95 % (7 MB)
115 14:43:48.855402 progress 100 % (8 MB)
116 14:43:48.861179 8 MB downloaded in 0.54 s (15.26 MB/s)
117 14:43:48.861513 end: 1.4.1 http-download (duration 00:00:01) [common]
119 14:43:48.861784 end: 1.4 download-retry (duration 00:00:01) [common]
120 14:43:48.861879 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 14:43:48.861970 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 14:43:48.862057 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 14:43:48.862143 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 14:43:48.862378 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw
125 14:43:48.862510 makedir: /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/bin
126 14:43:48.862614 makedir: /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/tests
127 14:43:48.862740 makedir: /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/results
128 14:43:48.862854 Creating /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/bin/lava-add-keys
129 14:43:48.863002 Creating /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/bin/lava-add-sources
130 14:43:48.863133 Creating /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/bin/lava-background-process-start
131 14:43:48.863263 Creating /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/bin/lava-background-process-stop
132 14:43:48.863420 Creating /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/bin/lava-common-functions
133 14:43:48.863590 Creating /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/bin/lava-echo-ipv4
134 14:43:48.863762 Creating /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/bin/lava-install-packages
135 14:43:48.863905 Creating /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/bin/lava-installed-packages
136 14:43:48.864107 Creating /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/bin/lava-os-build
137 14:43:48.864264 Creating /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/bin/lava-probe-channel
138 14:43:48.864389 Creating /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/bin/lava-probe-ip
139 14:43:48.864515 Creating /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/bin/lava-target-ip
140 14:43:48.864639 Creating /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/bin/lava-target-mac
141 14:43:48.864763 Creating /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/bin/lava-target-storage
142 14:43:48.864893 Creating /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/bin/lava-test-case
143 14:43:48.865018 Creating /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/bin/lava-test-event
144 14:43:48.865141 Creating /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/bin/lava-test-feedback
145 14:43:48.865287 Creating /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/bin/lava-test-raise
146 14:43:48.865429 Creating /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/bin/lava-test-reference
147 14:43:48.865553 Creating /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/bin/lava-test-runner
148 14:43:48.865676 Creating /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/bin/lava-test-set
149 14:43:48.865802 Creating /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/bin/lava-test-shell
150 14:43:48.865928 Updating /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/bin/lava-install-packages (oe)
151 14:43:48.866080 Updating /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/bin/lava-installed-packages (oe)
152 14:43:48.866199 Creating /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/environment
153 14:43:48.866301 LAVA metadata
154 14:43:48.866375 - LAVA_JOB_ID=14167015
155 14:43:48.866442 - LAVA_DISPATCHER_IP=192.168.201.1
156 14:43:48.866549 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 14:43:48.866618 skipped lava-vland-overlay
158 14:43:48.866692 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 14:43:48.866771 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 14:43:48.866834 skipped lava-multinode-overlay
161 14:43:48.866906 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 14:43:48.866988 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 14:43:48.867065 Loading test definitions
164 14:43:48.867156 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 14:43:48.867231 Using /lava-14167015 at stage 0
166 14:43:48.867548 uuid=14167015_1.5.2.3.1 testdef=None
167 14:43:48.867637 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 14:43:48.867725 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 14:43:48.868955 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 14:43:48.869191 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 14:43:48.869913 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 14:43:48.870145 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 14:43:48.870763 runner path: /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/0/tests/0_dmesg test_uuid 14167015_1.5.2.3.1
176 14:43:48.870921 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 14:43:48.871126 Creating lava-test-runner.conf files
179 14:43:48.871189 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14167015/lava-overlay-ale3k_dw/lava-14167015/0 for stage 0
180 14:43:48.871278 - 0_dmesg
181 14:43:48.871374 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 14:43:48.871458 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 14:43:48.878185 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 14:43:48.878311 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 14:43:48.878402 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 14:43:48.878516 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 14:43:48.878603 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 14:43:49.124354 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 14:43:49.124843 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
190 14:43:49.124992 extracting modules file /var/lib/lava/dispatcher/tmp/14167015/tftp-deploy-r735clyv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14167015/extract-overlay-ramdisk-_wdjrdbq/ramdisk
191 14:43:49.349565 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 14:43:49.349737 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 14:43:49.349837 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14167015/compress-overlay-1faf5fyu/overlay-1.5.2.4.tar.gz to ramdisk
194 14:43:49.349909 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14167015/compress-overlay-1faf5fyu/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14167015/extract-overlay-ramdisk-_wdjrdbq/ramdisk
195 14:43:49.356794 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 14:43:49.356935 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 14:43:49.357030 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 14:43:49.357123 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 14:43:49.357205 Building ramdisk /var/lib/lava/dispatcher/tmp/14167015/extract-overlay-ramdisk-_wdjrdbq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14167015/extract-overlay-ramdisk-_wdjrdbq/ramdisk
200 14:43:49.740382 >> 145117 blocks
201 14:43:52.060782 rename /var/lib/lava/dispatcher/tmp/14167015/extract-overlay-ramdisk-_wdjrdbq/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14167015/tftp-deploy-r735clyv/ramdisk/ramdisk.cpio.gz
202 14:43:52.061230 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
203 14:43:52.061402 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
204 14:43:52.061501 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
205 14:43:52.061610 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14167015/tftp-deploy-r735clyv/kernel/Image']
206 14:44:05.828367 Returned 0 in 13 seconds
207 14:44:05.928995 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14167015/tftp-deploy-r735clyv/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14167015/tftp-deploy-r735clyv/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14167015/tftp-deploy-r735clyv/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14167015/tftp-deploy-r735clyv/kernel/image.itb
208 14:44:06.330244 output: FIT description: Kernel Image image with one or more FDT blobs
209 14:44:06.330611 output: Created: Tue Jun 4 15:44:06 2024
210 14:44:06.330685 output: Image 0 (kernel-1)
211 14:44:06.330750 output: Description:
212 14:44:06.330810 output: Created: Tue Jun 4 15:44:06 2024
213 14:44:06.330871 output: Type: Kernel Image
214 14:44:06.330933 output: Compression: lzma compressed
215 14:44:06.330997 output: Data Size: 13060619 Bytes = 12754.51 KiB = 12.46 MiB
216 14:44:06.331059 output: Architecture: AArch64
217 14:44:06.331118 output: OS: Linux
218 14:44:06.331181 output: Load Address: 0x00000000
219 14:44:06.331243 output: Entry Point: 0x00000000
220 14:44:06.331298 output: Hash algo: crc32
221 14:44:06.331356 output: Hash value: 88dcd836
222 14:44:06.331412 output: Image 1 (fdt-1)
223 14:44:06.331466 output: Description: mt8192-asurada-spherion-r0
224 14:44:06.331519 output: Created: Tue Jun 4 15:44:06 2024
225 14:44:06.331574 output: Type: Flat Device Tree
226 14:44:06.331627 output: Compression: uncompressed
227 14:44:06.331707 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 14:44:06.331765 output: Architecture: AArch64
229 14:44:06.331818 output: Hash algo: crc32
230 14:44:06.331871 output: Hash value: 0f8e4d2e
231 14:44:06.331924 output: Image 2 (ramdisk-1)
232 14:44:06.331976 output: Description: unavailable
233 14:44:06.332028 output: Created: Tue Jun 4 15:44:06 2024
234 14:44:06.332082 output: Type: RAMDisk Image
235 14:44:06.332135 output: Compression: Unknown Compression
236 14:44:06.332188 output: Data Size: 21345597 Bytes = 20845.31 KiB = 20.36 MiB
237 14:44:06.332241 output: Architecture: AArch64
238 14:44:06.332295 output: OS: Linux
239 14:44:06.332347 output: Load Address: unavailable
240 14:44:06.332400 output: Entry Point: unavailable
241 14:44:06.332452 output: Hash algo: crc32
242 14:44:06.332504 output: Hash value: d619ffc5
243 14:44:06.332556 output: Default Configuration: 'conf-1'
244 14:44:06.332608 output: Configuration 0 (conf-1)
245 14:44:06.332661 output: Description: mt8192-asurada-spherion-r0
246 14:44:06.332714 output: Kernel: kernel-1
247 14:44:06.332766 output: Init Ramdisk: ramdisk-1
248 14:44:06.332819 output: FDT: fdt-1
249 14:44:06.332871 output: Loadables: kernel-1
250 14:44:06.332940 output:
251 14:44:06.333157 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 14:44:06.333254 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 14:44:06.333401 end: 1.5 prepare-tftp-overlay (duration 00:00:17) [common]
254 14:44:06.333494 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
255 14:44:06.333574 No LXC device requested
256 14:44:06.333655 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 14:44:06.333743 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
258 14:44:06.333822 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 14:44:06.333897 Checking files for TFTP limit of 4294967296 bytes.
260 14:44:06.334400 end: 1 tftp-deploy (duration 00:00:19) [common]
261 14:44:06.334505 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 14:44:06.334598 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 14:44:06.334718 substitutions:
264 14:44:06.334784 - {DTB}: 14167015/tftp-deploy-r735clyv/dtb/mt8192-asurada-spherion-r0.dtb
265 14:44:06.334849 - {INITRD}: 14167015/tftp-deploy-r735clyv/ramdisk/ramdisk.cpio.gz
266 14:44:06.334924 - {KERNEL}: 14167015/tftp-deploy-r735clyv/kernel/Image
267 14:44:06.335006 - {LAVA_MAC}: None
268 14:44:06.335063 - {PRESEED_CONFIG}: None
269 14:44:06.335119 - {PRESEED_LOCAL}: None
270 14:44:06.335174 - {RAMDISK}: 14167015/tftp-deploy-r735clyv/ramdisk/ramdisk.cpio.gz
271 14:44:06.335229 - {ROOT_PART}: None
272 14:44:06.335283 - {ROOT}: None
273 14:44:06.335337 - {SERVER_IP}: 192.168.201.1
274 14:44:06.335390 - {TEE}: None
275 14:44:06.335444 Parsed boot commands:
276 14:44:06.335499 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 14:44:06.335674 Parsed boot commands: tftpboot 192.168.201.1 14167015/tftp-deploy-r735clyv/kernel/image.itb 14167015/tftp-deploy-r735clyv/kernel/cmdline
278 14:44:06.335762 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 14:44:06.335850 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 14:44:06.335940 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 14:44:06.336026 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 14:44:06.336094 Not connected, no need to disconnect.
283 14:44:06.336170 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 14:44:06.336297 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 14:44:06.336382 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
286 14:44:06.340129 Setting prompt string to ['lava-test: # ']
287 14:44:06.340489 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 14:44:06.340598 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 14:44:06.340721 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 14:44:06.340842 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 14:44:06.341134 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-2']
292 14:44:20.109544 Returned 0 in 13 seconds
293 14:44:20.210173 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 14:44:20.210710 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 14:44:20.210814 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 14:44:20.210910 Setting prompt string to 'Starting depthcharge on Spherion...'
298 14:44:20.211011 Changing prompt to 'Starting depthcharge on Spherion...'
299 14:44:20.211106 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 14:44:20.211684 [Enter `^Ec?' for help]
301 14:44:20.211769
302 14:44:20.211837
303 14:44:20.211899 F0: 102B 0000
304 14:44:20.211966
305 14:44:20.212028 F3: 1001 0000 [0200]
306 14:44:20.212087
307 14:44:20.212146 F3: 1001 0000
308 14:44:20.212204
309 14:44:20.212258 F7: 102D 0000
310 14:44:20.212313
311 14:44:20.212367 F1: 0000 0000
312 14:44:20.212421
313 14:44:20.212482 V0: 0000 0000 [0001]
314 14:44:20.212537
315 14:44:20.212592 00: 0007 8000
316 14:44:20.212650
317 14:44:20.212705 01: 0000 0000
318 14:44:20.212760
319 14:44:20.212814 BP: 0C00 0209 [0000]
320 14:44:20.212867
321 14:44:20.212934 G0: 1182 0000
322 14:44:20.212990
323 14:44:20.213043 EC: 0000 0021 [4000]
324 14:44:20.213096
325 14:44:20.213149 S7: 0000 0000 [0000]
326 14:44:20.213203
327 14:44:20.213265 CC: 0000 0000 [0001]
328 14:44:20.213382
329 14:44:20.213436 T0: 0000 0040 [010F]
330 14:44:20.213490
331 14:44:20.213544 Jump to BL
332 14:44:20.213598
333 14:44:20.213651
334 14:44:20.213705
335 14:44:20.213765 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 14:44:20.213824 ARM64: Exception handlers installed.
337 14:44:20.213879 ARM64: Testing exception
338 14:44:20.213933 ARM64: Done test exception
339 14:44:20.213986 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 14:44:20.214041 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 14:44:20.214096 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 14:44:20.214151 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 14:44:20.214217 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 14:44:20.214303 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 14:44:20.214358 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 14:44:20.214413 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 14:44:20.214498 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 14:44:20.214553 WDT: Last reset was cold boot
349 14:44:20.214608 SPI1(PAD0) initialized at 2873684 Hz
350 14:44:20.214667 SPI5(PAD0) initialized at 992727 Hz
351 14:44:20.214723 VBOOT: Loading verstage.
352 14:44:20.214777 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 14:44:20.214832 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 14:44:20.214886 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 14:44:20.214940 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 14:44:20.214994 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 14:44:20.215049 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 14:44:20.215103 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
359 14:44:20.215166
360 14:44:20.215222
361 14:44:20.215275 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 14:44:20.215331 ARM64: Exception handlers installed.
363 14:44:20.215384 ARM64: Testing exception
364 14:44:20.215438 ARM64: Done test exception
365 14:44:20.215492 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 14:44:20.215546 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 14:44:20.215599 Probing TPM: . done!
368 14:44:20.215661 TPM ready after 0 ms
369 14:44:20.215715 Connected to device vid:did:rid of 1ae0:0028:00
370 14:44:20.215769 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
371 14:44:20.215824 Initialized TPM device CR50 revision 0
372 14:44:20.215878 tlcl_send_startup: Startup return code is 0
373 14:44:20.215932 TPM: setup succeeded
374 14:44:20.215986 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 14:44:20.216040 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 14:44:20.216108 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 14:44:20.216164 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 14:44:20.216218 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 14:44:20.216272 in-header: 03 07 00 00 08 00 00 00
380 14:44:20.216326 in-data: aa e4 47 04 13 02 00 00
381 14:44:20.216379 Chrome EC: UHEPI supported
382 14:44:20.216432 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 14:44:20.216486 in-header: 03 a9 00 00 08 00 00 00
384 14:44:20.216577 in-data: 84 60 60 08 00 00 00 00
385 14:44:20.216632 Phase 1
386 14:44:20.216685 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 14:44:20.216739 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 14:44:20.216794 VB2:vb2_check_recovery() Recovery was requested manually
389 14:44:20.216848 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 14:44:20.216902 Recovery requested (1009000e)
391 14:44:20.216971 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 14:44:20.217054 tlcl_extend: response is 0
393 14:44:20.217110 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 14:44:20.217164 tlcl_extend: response is 0
395 14:44:20.217219 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 14:44:20.217297 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
397 14:44:20.217367 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 14:44:20.217421
399 14:44:20.217474
400 14:44:20.217528 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 14:44:20.217616 ARM64: Exception handlers installed.
402 14:44:20.217746 ARM64: Testing exception
403 14:44:20.217830 ARM64: Done test exception
404 14:44:20.217913 pmic_efuse_setting: Set efuses in 11 msecs
405 14:44:20.217997 pmwrap_interface_init: Select PMIF_VLD_RDY
406 14:44:20.218084 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 14:44:20.218142 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 14:44:20.218399 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 14:44:20.218463 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 14:44:20.218519 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 14:44:20.218597 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 14:44:20.218686 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 14:44:20.218771 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 14:44:20.218854 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 14:44:20.218939 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 14:44:20.219022 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 14:44:20.219079 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 14:44:20.219133 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 14:44:20.219187 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 14:44:20.219242 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 14:44:20.219296 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 14:44:20.219350 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 14:44:20.219403 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 14:44:20.219456 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 14:44:20.219509 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 14:44:20.219563 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 14:44:20.219617 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 14:44:20.219670 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 14:44:20.219728 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 14:44:20.219815 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 14:44:20.219899 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 14:44:20.220002 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 14:44:20.220104 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 14:44:20.220157 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 14:44:20.220210 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 14:44:20.220264 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 14:44:20.220318 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 14:44:20.220372 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 14:44:20.220424 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 14:44:20.220478 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 14:44:20.220592 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 14:44:20.220677 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 14:44:20.220761 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 14:44:20.220849 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 14:44:20.220934 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 14:44:20.221017 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 14:44:20.221113 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 14:44:20.221198 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 14:44:20.221304 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 14:44:20.221375 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 14:44:20.221429 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 14:44:20.221481 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 14:44:20.221535 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 14:44:20.221588 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 14:44:20.221641 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 14:44:20.221694 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 14:44:20.221748 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 14:44:20.221803 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 14:44:20.221870 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 14:44:20.221956 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 14:44:20.222041 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 14:44:20.222153 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 14:44:20.222237 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 14:44:20.222321 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 14:44:20.222405 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x2f
466 14:44:20.222489 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 14:44:20.222586 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
468 14:44:20.222641 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 14:44:20.222695 [RTC]rtc_get_frequency_meter,154: input=15, output=853
470 14:44:20.222749 [RTC]rtc_get_frequency_meter,154: input=7, output=725
471 14:44:20.222803 [RTC]rtc_get_frequency_meter,154: input=11, output=789
472 14:44:20.222857 [RTC]rtc_get_frequency_meter,154: input=13, output=821
473 14:44:20.222917 [RTC]rtc_get_frequency_meter,154: input=12, output=805
474 14:44:20.222972 [RTC]rtc_get_frequency_meter,154: input=11, output=789
475 14:44:20.223025 [RTC]rtc_get_frequency_meter,154: input=12, output=805
476 14:44:20.223079 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
477 14:44:20.223132 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
478 14:44:20.223388 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 14:44:20.223452 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 14:44:20.223508 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 14:44:20.223563 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 14:44:20.223617 ADC[4]: Raw value=904433 ID=7
483 14:44:20.223671 ADC[3]: Raw value=213546 ID=1
484 14:44:20.223725 RAM Code: 0x71
485 14:44:20.223779 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 14:44:20.223834 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 14:44:20.223889 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 14:44:20.223943 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 14:44:20.224009 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 14:44:20.224065 in-header: 03 07 00 00 08 00 00 00
491 14:44:20.224118 in-data: aa e4 47 04 13 02 00 00
492 14:44:20.224171 Chrome EC: UHEPI supported
493 14:44:20.224225 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 14:44:20.224279 in-header: 03 a9 00 00 08 00 00 00
495 14:44:20.224332 in-data: 84 60 60 08 00 00 00 00
496 14:44:20.224385 MRC: failed to locate region type 0.
497 14:44:20.224469 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 14:44:20.224577 DRAM-K: Running full calibration
499 14:44:20.224636 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 14:44:20.224691 header.status = 0x0
501 14:44:20.224745 header.version = 0x6 (expected: 0x6)
502 14:44:20.224821 header.size = 0xd00 (expected: 0xd00)
503 14:44:20.224919 header.flags = 0x0
504 14:44:20.225004 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 14:44:20.225093 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
506 14:44:20.225179 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 14:44:20.225286 dram_init: ddr_geometry: 2
508 14:44:20.225357 [EMI] MDL number = 2
509 14:44:20.225410 [EMI] Get MDL freq = 0
510 14:44:20.225464 dram_init: ddr_type: 0
511 14:44:20.225517 is_discrete_lpddr4: 1
512 14:44:20.225570 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 14:44:20.225624
514 14:44:20.225678
515 14:44:20.225731 [Bian_co] ETT version 0.0.0.1
516 14:44:20.225786 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 14:44:20.225839
518 14:44:20.225893 dramc_set_vcore_voltage set vcore to 650000
519 14:44:20.225947 Read voltage for 800, 4
520 14:44:20.226000 Vio18 = 0
521 14:44:20.226054 Vcore = 650000
522 14:44:20.226107 Vdram = 0
523 14:44:20.226160 Vddq = 0
524 14:44:20.226213 Vmddr = 0
525 14:44:20.226265 dram_init: config_dvfs: 1
526 14:44:20.226319 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 14:44:20.226373 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 14:44:20.226426 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
529 14:44:20.226479 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
530 14:44:20.226533 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
531 14:44:20.226586 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
532 14:44:20.226640 MEM_TYPE=3, freq_sel=18
533 14:44:20.226693 sv_algorithm_assistance_LP4_1600
534 14:44:20.226746 ============ PULL DRAM RESETB DOWN ============
535 14:44:20.226800 ========== PULL DRAM RESETB DOWN end =========
536 14:44:20.226854 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 14:44:20.226907 ===================================
538 14:44:20.226961 LPDDR4 DRAM CONFIGURATION
539 14:44:20.227014 ===================================
540 14:44:20.227068 EX_ROW_EN[0] = 0x0
541 14:44:20.227185 EX_ROW_EN[1] = 0x0
542 14:44:20.227253 LP4Y_EN = 0x0
543 14:44:20.227330 WORK_FSP = 0x0
544 14:44:20.227399 WL = 0x2
545 14:44:20.227507 RL = 0x2
546 14:44:20.227595 BL = 0x2
547 14:44:20.227648 RPST = 0x0
548 14:44:20.227701 RD_PRE = 0x0
549 14:44:20.227754 WR_PRE = 0x1
550 14:44:20.227806 WR_PST = 0x0
551 14:44:20.227859 DBI_WR = 0x0
552 14:44:20.227911 DBI_RD = 0x0
553 14:44:20.227964 OTF = 0x1
554 14:44:20.228018 ===================================
555 14:44:20.228072 ===================================
556 14:44:20.228125 ANA top config
557 14:44:20.228178 ===================================
558 14:44:20.228232 DLL_ASYNC_EN = 0
559 14:44:20.228285 ALL_SLAVE_EN = 1
560 14:44:20.228337 NEW_RANK_MODE = 1
561 14:44:20.228391 DLL_IDLE_MODE = 1
562 14:44:20.228444 LP45_APHY_COMB_EN = 1
563 14:44:20.228496 TX_ODT_DIS = 1
564 14:44:20.228549 NEW_8X_MODE = 1
565 14:44:20.228603 ===================================
566 14:44:20.228656 ===================================
567 14:44:20.228709 data_rate = 1600
568 14:44:20.228761 CKR = 1
569 14:44:20.228815 DQ_P2S_RATIO = 8
570 14:44:20.228868 ===================================
571 14:44:20.228921 CA_P2S_RATIO = 8
572 14:44:20.228974 DQ_CA_OPEN = 0
573 14:44:20.229027 DQ_SEMI_OPEN = 0
574 14:44:20.229080 CA_SEMI_OPEN = 0
575 14:44:20.229134 CA_FULL_RATE = 0
576 14:44:20.229203 DQ_CKDIV4_EN = 1
577 14:44:20.229310 CA_CKDIV4_EN = 1
578 14:44:20.229374 CA_PREDIV_EN = 0
579 14:44:20.229445 PH8_DLY = 0
580 14:44:20.229498 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 14:44:20.229552 DQ_AAMCK_DIV = 4
582 14:44:20.229605 CA_AAMCK_DIV = 4
583 14:44:20.229658 CA_ADMCK_DIV = 4
584 14:44:20.229712 DQ_TRACK_CA_EN = 0
585 14:44:20.229765 CA_PICK = 800
586 14:44:20.229817 CA_MCKIO = 800
587 14:44:20.229870 MCKIO_SEMI = 0
588 14:44:20.229924 PLL_FREQ = 3068
589 14:44:20.229976 DQ_UI_PI_RATIO = 32
590 14:44:20.230030 CA_UI_PI_RATIO = 0
591 14:44:20.230083 ===================================
592 14:44:20.230136 ===================================
593 14:44:20.230189 memory_type:LPDDR4
594 14:44:20.230250 GP_NUM : 10
595 14:44:20.230305 SRAM_EN : 1
596 14:44:20.230367 MD32_EN : 0
597 14:44:20.230649 ===================================
598 14:44:20.230745 [ANA_INIT] >>>>>>>>>>>>>>
599 14:44:20.230847 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 14:44:20.230948 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 14:44:20.231007 ===================================
602 14:44:20.231102 data_rate = 1600,PCW = 0X7600
603 14:44:20.231189 ===================================
604 14:44:20.231275 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 14:44:20.231342 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 14:44:20.231400 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 14:44:20.231456 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 14:44:20.231521 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 14:44:20.231579 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 14:44:20.231635 [ANA_INIT] flow start
611 14:44:20.231690 [ANA_INIT] PLL >>>>>>>>
612 14:44:20.231743 [ANA_INIT] PLL <<<<<<<<
613 14:44:20.231797 [ANA_INIT] MIDPI >>>>>>>>
614 14:44:20.231852 [ANA_INIT] MIDPI <<<<<<<<
615 14:44:20.231906 [ANA_INIT] DLL >>>>>>>>
616 14:44:20.231960 [ANA_INIT] flow end
617 14:44:20.232014 ============ LP4 DIFF to SE enter ============
618 14:44:20.232069 ============ LP4 DIFF to SE exit ============
619 14:44:20.232127 [ANA_INIT] <<<<<<<<<<<<<
620 14:44:20.232215 [Flow] Enable top DCM control >>>>>
621 14:44:20.232301 [Flow] Enable top DCM control <<<<<
622 14:44:20.232381 Enable DLL master slave shuffle
623 14:44:20.232439 ==============================================================
624 14:44:20.232495 Gating Mode config
625 14:44:20.232550 ==============================================================
626 14:44:20.232605 Config description:
627 14:44:20.232660 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 14:44:20.232724 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 14:44:20.232781 SELPH_MODE 0: By rank 1: By Phase
630 14:44:20.232837 ==============================================================
631 14:44:20.232892 GAT_TRACK_EN = 1
632 14:44:20.232947 RX_GATING_MODE = 2
633 14:44:20.233001 RX_GATING_TRACK_MODE = 2
634 14:44:20.233058 SELPH_MODE = 1
635 14:44:20.233146 PICG_EARLY_EN = 1
636 14:44:20.233230 VALID_LAT_VALUE = 1
637 14:44:20.233335 ==============================================================
638 14:44:20.233424 Enter into Gating configuration >>>>
639 14:44:20.233482 Exit from Gating configuration <<<<
640 14:44:20.233537 Enter into DVFS_PRE_config >>>>>
641 14:44:20.233593 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 14:44:20.233652 Exit from DVFS_PRE_config <<<<<
643 14:44:20.233706 Enter into PICG configuration >>>>
644 14:44:20.233761 Exit from PICG configuration <<<<
645 14:44:20.233816 [RX_INPUT] configuration >>>>>
646 14:44:20.233876 [RX_INPUT] configuration <<<<<
647 14:44:20.233931 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 14:44:20.233987 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 14:44:20.234076 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 14:44:20.234173 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 14:44:20.234260 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 14:44:20.234352 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 14:44:20.234439 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 14:44:20.234510 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 14:44:20.234567 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 14:44:20.234622 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 14:44:20.234677 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 14:44:20.234732 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 14:44:20.234787 ===================================
660 14:44:20.234850 LPDDR4 DRAM CONFIGURATION
661 14:44:20.234908 ===================================
662 14:44:20.234963 EX_ROW_EN[0] = 0x0
663 14:44:20.235030 EX_ROW_EN[1] = 0x0
664 14:44:20.235099 LP4Y_EN = 0x0
665 14:44:20.235154 WORK_FSP = 0x0
666 14:44:20.235209 WL = 0x2
667 14:44:20.235264 RL = 0x2
668 14:44:20.235322 BL = 0x2
669 14:44:20.235423 RPST = 0x0
670 14:44:20.235506 RD_PRE = 0x0
671 14:44:20.235570 WR_PRE = 0x1
672 14:44:20.235625 WR_PST = 0x0
673 14:44:20.235679 DBI_WR = 0x0
674 14:44:20.235732 DBI_RD = 0x0
675 14:44:20.235823 OTF = 0x1
676 14:44:20.235878 ===================================
677 14:44:20.235932 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 14:44:20.235985 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 14:44:20.236039 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 14:44:20.236093 ===================================
681 14:44:20.236146 LPDDR4 DRAM CONFIGURATION
682 14:44:20.236199 ===================================
683 14:44:20.236252 EX_ROW_EN[0] = 0x10
684 14:44:20.236357 EX_ROW_EN[1] = 0x0
685 14:44:20.236440 LP4Y_EN = 0x0
686 14:44:20.236523 WORK_FSP = 0x0
687 14:44:20.236605 WL = 0x2
688 14:44:20.236662 RL = 0x2
689 14:44:20.236715 BL = 0x2
690 14:44:20.236768 RPST = 0x0
691 14:44:20.236821 RD_PRE = 0x0
692 14:44:20.236874 WR_PRE = 0x1
693 14:44:20.236926 WR_PST = 0x0
694 14:44:20.236980 DBI_WR = 0x0
695 14:44:20.237033 DBI_RD = 0x0
696 14:44:20.237086 OTF = 0x1
697 14:44:20.237139 ===================================
698 14:44:20.237193 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 14:44:20.237250 nWR fixed to 40
700 14:44:20.237349 [ModeRegInit_LP4] CH0 RK0
701 14:44:20.237402 [ModeRegInit_LP4] CH0 RK1
702 14:44:20.237455 [ModeRegInit_LP4] CH1 RK0
703 14:44:20.237508 [ModeRegInit_LP4] CH1 RK1
704 14:44:20.237560 match AC timing 13
705 14:44:20.237612 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 14:44:20.237911 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 14:44:20.237978 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 14:44:20.238034 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 14:44:20.238090 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 14:44:20.238144 [EMI DOE] emi_dcm 0
711 14:44:20.238198 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 14:44:20.238252 ==
713 14:44:20.238331 Dram Type= 6, Freq= 0, CH_0, rank 0
714 14:44:20.238400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 14:44:20.238454 ==
716 14:44:20.238508 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 14:44:20.238562 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 14:44:20.238617 [CA 0] Center 37 (7~68) winsize 62
719 14:44:20.238670 [CA 1] Center 37 (7~68) winsize 62
720 14:44:20.238733 [CA 2] Center 34 (4~65) winsize 62
721 14:44:20.238787 [CA 3] Center 35 (4~66) winsize 63
722 14:44:20.238841 [CA 4] Center 33 (3~64) winsize 62
723 14:44:20.238894 [CA 5] Center 33 (3~64) winsize 62
724 14:44:20.238971
725 14:44:20.239041 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 14:44:20.239095
727 14:44:20.239148 [CATrainingPosCal] consider 1 rank data
728 14:44:20.239202 u2DelayCellTimex100 = 270/100 ps
729 14:44:20.239255 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 14:44:20.239309 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
731 14:44:20.239379 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
732 14:44:20.239433 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
733 14:44:20.239491 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
734 14:44:20.239593 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 14:44:20.239676
736 14:44:20.239762 CA PerBit enable=1, Macro0, CA PI delay=33
737 14:44:20.239849
738 14:44:20.239903 [CBTSetCACLKResult] CA Dly = 33
739 14:44:20.239957 CS Dly: 6 (0~37)
740 14:44:20.240010 ==
741 14:44:20.240064 Dram Type= 6, Freq= 0, CH_0, rank 1
742 14:44:20.240118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 14:44:20.240188 ==
744 14:44:20.240256 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 14:44:20.240310 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 14:44:20.240364 [CA 0] Center 38 (7~69) winsize 63
747 14:44:20.240417 [CA 1] Center 37 (7~68) winsize 62
748 14:44:20.240470 [CA 2] Center 35 (5~66) winsize 62
749 14:44:20.240523 [CA 3] Center 34 (4~65) winsize 62
750 14:44:20.240576 [CA 4] Center 34 (3~65) winsize 63
751 14:44:20.240629 [CA 5] Center 33 (3~64) winsize 62
752 14:44:20.240681
753 14:44:20.240734 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 14:44:20.240788
755 14:44:20.240863 [CATrainingPosCal] consider 2 rank data
756 14:44:20.240927 u2DelayCellTimex100 = 270/100 ps
757 14:44:20.240982 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 14:44:20.241036 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 14:44:20.241090 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
760 14:44:20.241144 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 14:44:20.241199 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
762 14:44:20.241252 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 14:44:20.241349
764 14:44:20.241403 CA PerBit enable=1, Macro0, CA PI delay=33
765 14:44:20.241457
766 14:44:20.241511 [CBTSetCACLKResult] CA Dly = 33
767 14:44:20.241564 CS Dly: 6 (0~38)
768 14:44:20.241618
769 14:44:20.241670 ----->DramcWriteLeveling(PI) begin...
770 14:44:20.241729 ==
771 14:44:20.241783 Dram Type= 6, Freq= 0, CH_0, rank 0
772 14:44:20.241836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 14:44:20.241897 ==
774 14:44:20.241953 Write leveling (Byte 0): 32 => 32
775 14:44:20.242008 Write leveling (Byte 1): 27 => 27
776 14:44:20.242061 DramcWriteLeveling(PI) end<-----
777 14:44:20.242114
778 14:44:20.242168 ==
779 14:44:20.242237 Dram Type= 6, Freq= 0, CH_0, rank 0
780 14:44:20.242304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 14:44:20.242358 ==
782 14:44:20.242412 [Gating] SW mode calibration
783 14:44:20.242466 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 14:44:20.242520 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 14:44:20.242573 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 14:44:20.242626 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
787 14:44:20.242679 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
788 14:44:20.242733 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 14:44:20.242786 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 14:44:20.242839 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 14:44:20.242892 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 14:44:20.243002 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 14:44:20.243069 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 14:44:20.243123 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 14:44:20.243176 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 14:44:20.243246 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 14:44:20.243313 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 14:44:20.243366 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 14:44:20.243419 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 14:44:20.243472 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 14:44:20.243525 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 14:44:20.243578 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 14:44:20.243631 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
804 14:44:20.243684 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 14:44:20.243737 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 14:44:20.243790 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 14:44:20.243844 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 14:44:20.243896 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 14:44:20.243950 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 14:44:20.244019 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 14:44:20.244082 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
812 14:44:20.244166 0 9 12 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
813 14:44:20.244219 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 14:44:20.244481 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 14:44:20.244580 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 14:44:20.244636 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 14:44:20.244690 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 14:44:20.244744 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
819 14:44:20.244799 0 10 8 | B1->B0 | 3030 2424 | 0 0 | (0 0) (0 0)
820 14:44:20.244854 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
821 14:44:20.244908 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 14:44:20.244961 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 14:44:20.245015 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 14:44:20.245068 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 14:44:20.245122 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 14:44:20.245175 0 11 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
827 14:44:20.245245 0 11 8 | B1->B0 | 2b2b 4545 | 0 0 | (0 0) (0 0)
828 14:44:20.245329 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
829 14:44:20.245383 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 14:44:20.245437 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 14:44:20.245490 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 14:44:20.245544 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 14:44:20.245597 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 14:44:20.245650 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
835 14:44:20.245704 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
836 14:44:20.245757 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 14:44:20.245810 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 14:44:20.245907 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 14:44:20.245961 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 14:44:20.246014 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 14:44:20.246068 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 14:44:20.246121 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 14:44:20.246175 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 14:44:20.246229 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 14:44:20.246282 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 14:44:20.246335 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 14:44:20.246389 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 14:44:20.246442 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 14:44:20.246495 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 14:44:20.246579 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 14:44:20.246632 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 14:44:20.246685 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 14:44:20.246737 Total UI for P1: 0, mck2ui 16
854 14:44:20.246792 best dqsien dly found for B0: ( 0, 14, 8)
855 14:44:20.246846 Total UI for P1: 0, mck2ui 16
856 14:44:20.246899 best dqsien dly found for B1: ( 0, 14, 10)
857 14:44:20.246953 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
858 14:44:20.247007 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
859 14:44:20.247060
860 14:44:20.247114 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
861 14:44:20.247168 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
862 14:44:20.247222 [Gating] SW calibration Done
863 14:44:20.247275 ==
864 14:44:20.247330 Dram Type= 6, Freq= 0, CH_0, rank 0
865 14:44:20.247384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 14:44:20.247438 ==
867 14:44:20.247492 RX Vref Scan: 0
868 14:44:20.247545
869 14:44:20.247637 RX Vref 0 -> 0, step: 1
870 14:44:20.247695
871 14:44:20.247749 RX Delay -130 -> 252, step: 16
872 14:44:20.247803 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
873 14:44:20.247875 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
874 14:44:20.247942 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
875 14:44:20.247996 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
876 14:44:20.248049 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
877 14:44:20.248103 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
878 14:44:20.248156 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
879 14:44:20.248210 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
880 14:44:20.248263 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
881 14:44:20.248317 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
882 14:44:20.248401 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
883 14:44:20.248454 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
884 14:44:20.248507 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
885 14:44:20.248578 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
886 14:44:20.248694 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
887 14:44:20.248794 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
888 14:44:20.248895 ==
889 14:44:20.249007 Dram Type= 6, Freq= 0, CH_0, rank 0
890 14:44:20.249118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 14:44:20.249204 ==
892 14:44:20.249306 DQS Delay:
893 14:44:20.249377 DQS0 = 0, DQS1 = 0
894 14:44:20.249432 DQM Delay:
895 14:44:20.249486 DQM0 = 87, DQM1 = 76
896 14:44:20.249540 DQ Delay:
897 14:44:20.249594 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
898 14:44:20.249649 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
899 14:44:20.249703 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
900 14:44:20.249757 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
901 14:44:20.249810
902 14:44:20.249863
903 14:44:20.249916 ==
904 14:44:20.249969 Dram Type= 6, Freq= 0, CH_0, rank 0
905 14:44:20.250024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 14:44:20.250077 ==
907 14:44:20.250131
908 14:44:20.250184
909 14:44:20.250237 TX Vref Scan disable
910 14:44:20.250291 == TX Byte 0 ==
911 14:44:20.250345 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
912 14:44:20.250399 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
913 14:44:20.250452 == TX Byte 1 ==
914 14:44:20.250536 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
915 14:44:20.250589 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
916 14:44:20.250672 ==
917 14:44:20.250725 Dram Type= 6, Freq= 0, CH_0, rank 0
918 14:44:20.250790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 14:44:20.250858 ==
920 14:44:20.250914 TX Vref=22, minBit 0, minWin=27, winSum=438
921 14:44:20.250969 TX Vref=24, minBit 1, minWin=27, winSum=443
922 14:44:20.251260 TX Vref=26, minBit 1, minWin=27, winSum=445
923 14:44:20.251329 TX Vref=28, minBit 5, minWin=27, winSum=451
924 14:44:20.251385 TX Vref=30, minBit 1, minWin=27, winSum=450
925 14:44:20.251439 TX Vref=32, minBit 1, minWin=27, winSum=447
926 14:44:20.251494 [TxChooseVref] Worse bit 5, Min win 27, Win sum 451, Final Vref 28
927 14:44:20.251549
928 14:44:20.251650 Final TX Range 1 Vref 28
929 14:44:20.251706
930 14:44:20.251760 ==
931 14:44:20.251814 Dram Type= 6, Freq= 0, CH_0, rank 0
932 14:44:20.251869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 14:44:20.251924 ==
934 14:44:20.251978
935 14:44:20.252031
936 14:44:20.252085 TX Vref Scan disable
937 14:44:20.252139 == TX Byte 0 ==
938 14:44:20.252193 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
939 14:44:20.252248 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
940 14:44:20.252302 == TX Byte 1 ==
941 14:44:20.252395 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
942 14:44:20.252450 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
943 14:44:20.252508
944 14:44:20.252562 [DATLAT]
945 14:44:20.252615 Freq=800, CH0 RK0
946 14:44:20.252685
947 14:44:20.252752 DATLAT Default: 0xa
948 14:44:20.252806 0, 0xFFFF, sum = 0
949 14:44:20.252860 1, 0xFFFF, sum = 0
950 14:44:20.252915 2, 0xFFFF, sum = 0
951 14:44:20.252970 3, 0xFFFF, sum = 0
952 14:44:20.253024 4, 0xFFFF, sum = 0
953 14:44:20.253077 5, 0xFFFF, sum = 0
954 14:44:20.253134 6, 0xFFFF, sum = 0
955 14:44:20.253242 7, 0xFFFF, sum = 0
956 14:44:20.253369 8, 0xFFFF, sum = 0
957 14:44:20.253431 9, 0x0, sum = 1
958 14:44:20.253487 10, 0x0, sum = 2
959 14:44:20.253558 11, 0x0, sum = 3
960 14:44:20.253615 12, 0x0, sum = 4
961 14:44:20.253670 best_step = 10
962 14:44:20.253725
963 14:44:20.253780 ==
964 14:44:20.253865 Dram Type= 6, Freq= 0, CH_0, rank 0
965 14:44:20.253936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 14:44:20.253991 ==
967 14:44:20.254075 RX Vref Scan: 1
968 14:44:20.254129
969 14:44:20.254183 Set Vref Range= 32 -> 127
970 14:44:20.254236
971 14:44:20.254289 RX Vref 32 -> 127, step: 1
972 14:44:20.254342
973 14:44:20.254395 RX Delay -95 -> 252, step: 8
974 14:44:20.254472
975 14:44:20.254541 Set Vref, RX VrefLevel [Byte0]: 32
976 14:44:20.254594 [Byte1]: 32
977 14:44:20.254648
978 14:44:20.254701 Set Vref, RX VrefLevel [Byte0]: 33
979 14:44:20.254753 [Byte1]: 33
980 14:44:20.254807
981 14:44:20.254860 Set Vref, RX VrefLevel [Byte0]: 34
982 14:44:20.254913 [Byte1]: 34
983 14:44:20.254966
984 14:44:20.255019 Set Vref, RX VrefLevel [Byte0]: 35
985 14:44:20.255072 [Byte1]: 35
986 14:44:20.255127
987 14:44:20.255220 Set Vref, RX VrefLevel [Byte0]: 36
988 14:44:20.255274 [Byte1]: 36
989 14:44:20.255327
990 14:44:20.255380 Set Vref, RX VrefLevel [Byte0]: 37
991 14:44:20.255433 [Byte1]: 37
992 14:44:20.255486
993 14:44:20.255539 Set Vref, RX VrefLevel [Byte0]: 38
994 14:44:20.255592 [Byte1]: 38
995 14:44:20.255644
996 14:44:20.255697 Set Vref, RX VrefLevel [Byte0]: 39
997 14:44:20.255750 [Byte1]: 39
998 14:44:20.255802
999 14:44:20.255855 Set Vref, RX VrefLevel [Byte0]: 40
1000 14:44:20.255908 [Byte1]: 40
1001 14:44:20.255961
1002 14:44:20.256014 Set Vref, RX VrefLevel [Byte0]: 41
1003 14:44:20.256067 [Byte1]: 41
1004 14:44:20.256120
1005 14:44:20.256172 Set Vref, RX VrefLevel [Byte0]: 42
1006 14:44:20.256226 [Byte1]: 42
1007 14:44:20.256279
1008 14:44:20.256332 Set Vref, RX VrefLevel [Byte0]: 43
1009 14:44:20.256385 [Byte1]: 43
1010 14:44:20.256438
1011 14:44:20.256491 Set Vref, RX VrefLevel [Byte0]: 44
1012 14:44:20.256543 [Byte1]: 44
1013 14:44:20.256596
1014 14:44:20.256648 Set Vref, RX VrefLevel [Byte0]: 45
1015 14:44:20.256702 [Byte1]: 45
1016 14:44:20.256754
1017 14:44:20.256807 Set Vref, RX VrefLevel [Byte0]: 46
1018 14:44:20.256862 [Byte1]: 46
1019 14:44:20.256933
1020 14:44:20.257035 Set Vref, RX VrefLevel [Byte0]: 47
1021 14:44:20.257119 [Byte1]: 47
1022 14:44:20.257202
1023 14:44:20.257327 Set Vref, RX VrefLevel [Byte0]: 48
1024 14:44:20.257389 [Byte1]: 48
1025 14:44:20.257447
1026 14:44:20.257531 Set Vref, RX VrefLevel [Byte0]: 49
1027 14:44:20.257584 [Byte1]: 49
1028 14:44:20.257670
1029 14:44:20.257722 Set Vref, RX VrefLevel [Byte0]: 50
1030 14:44:20.257775 [Byte1]: 50
1031 14:44:20.257827
1032 14:44:20.257878 Set Vref, RX VrefLevel [Byte0]: 51
1033 14:44:20.257930 [Byte1]: 51
1034 14:44:20.257983
1035 14:44:20.258035 Set Vref, RX VrefLevel [Byte0]: 52
1036 14:44:20.258086 [Byte1]: 52
1037 14:44:20.258139
1038 14:44:20.258191 Set Vref, RX VrefLevel [Byte0]: 53
1039 14:44:20.258244 [Byte1]: 53
1040 14:44:20.258296
1041 14:44:20.258347 Set Vref, RX VrefLevel [Byte0]: 54
1042 14:44:20.258400 [Byte1]: 54
1043 14:44:20.258452
1044 14:44:20.258505 Set Vref, RX VrefLevel [Byte0]: 55
1045 14:44:20.258557 [Byte1]: 55
1046 14:44:20.258610
1047 14:44:20.258662 Set Vref, RX VrefLevel [Byte0]: 56
1048 14:44:20.258715 [Byte1]: 56
1049 14:44:20.258783
1050 14:44:20.258836 Set Vref, RX VrefLevel [Byte0]: 57
1051 14:44:20.258919 [Byte1]: 57
1052 14:44:20.258972
1053 14:44:20.259026 Set Vref, RX VrefLevel [Byte0]: 58
1054 14:44:20.259080 [Byte1]: 58
1055 14:44:20.259147
1056 14:44:20.259199 Set Vref, RX VrefLevel [Byte0]: 59
1057 14:44:20.259252 [Byte1]: 59
1058 14:44:20.259304
1059 14:44:20.259356 Set Vref, RX VrefLevel [Byte0]: 60
1060 14:44:20.259409 [Byte1]: 60
1061 14:44:20.259460
1062 14:44:20.259512 Set Vref, RX VrefLevel [Byte0]: 61
1063 14:44:20.259565 [Byte1]: 61
1064 14:44:20.259617
1065 14:44:20.259669 Set Vref, RX VrefLevel [Byte0]: 62
1066 14:44:20.259721 [Byte1]: 62
1067 14:44:20.259773
1068 14:44:20.259825 Set Vref, RX VrefLevel [Byte0]: 63
1069 14:44:20.259877 [Byte1]: 63
1070 14:44:20.259930
1071 14:44:20.259981 Set Vref, RX VrefLevel [Byte0]: 64
1072 14:44:20.260034 [Byte1]: 64
1073 14:44:20.260086
1074 14:44:20.260138 Set Vref, RX VrefLevel [Byte0]: 65
1075 14:44:20.260190 [Byte1]: 65
1076 14:44:20.260242
1077 14:44:20.260295 Set Vref, RX VrefLevel [Byte0]: 66
1078 14:44:20.260347 [Byte1]: 66
1079 14:44:20.260416
1080 14:44:20.260542 Set Vref, RX VrefLevel [Byte0]: 67
1081 14:44:20.260598 [Byte1]: 67
1082 14:44:20.260651
1083 14:44:20.260720 Set Vref, RX VrefLevel [Byte0]: 68
1084 14:44:20.260787 [Byte1]: 68
1085 14:44:20.260870
1086 14:44:20.260923 Set Vref, RX VrefLevel [Byte0]: 69
1087 14:44:20.260975 [Byte1]: 69
1088 14:44:20.261027
1089 14:44:20.261079 Set Vref, RX VrefLevel [Byte0]: 70
1090 14:44:20.261358 [Byte1]: 70
1091 14:44:20.261422
1092 14:44:20.261477 Set Vref, RX VrefLevel [Byte0]: 71
1093 14:44:20.261531 [Byte1]: 71
1094 14:44:20.261584
1095 14:44:20.261637 Set Vref, RX VrefLevel [Byte0]: 72
1096 14:44:20.261690 [Byte1]: 72
1097 14:44:20.261742
1098 14:44:20.261794 Set Vref, RX VrefLevel [Byte0]: 73
1099 14:44:20.261847 [Byte1]: 73
1100 14:44:20.261899
1101 14:44:20.261951 Set Vref, RX VrefLevel [Byte0]: 74
1102 14:44:20.262004 [Byte1]: 74
1103 14:44:20.262056
1104 14:44:20.262108 Final RX Vref Byte 0 = 59 to rank0
1105 14:44:20.262161 Final RX Vref Byte 1 = 61 to rank0
1106 14:44:20.262214 Final RX Vref Byte 0 = 59 to rank1
1107 14:44:20.262267 Final RX Vref Byte 1 = 61 to rank1==
1108 14:44:20.262320 Dram Type= 6, Freq= 0, CH_0, rank 0
1109 14:44:20.262372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1110 14:44:20.262425 ==
1111 14:44:20.262477 DQS Delay:
1112 14:44:20.262530 DQS0 = 0, DQS1 = 0
1113 14:44:20.262582 DQM Delay:
1114 14:44:20.262634 DQM0 = 88, DQM1 = 76
1115 14:44:20.262686 DQ Delay:
1116 14:44:20.262739 DQ0 =88, DQ1 =88, DQ2 =88, DQ3 =84
1117 14:44:20.262790 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1118 14:44:20.262843 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =72
1119 14:44:20.262895 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1120 14:44:20.262948
1121 14:44:20.262999
1122 14:44:20.263051 [DQSOSCAuto] RK0, (LSB)MR18= 0x342d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
1123 14:44:20.263106 CH0 RK0: MR19=606, MR18=342D
1124 14:44:20.263158 CH0_RK0: MR19=0x606, MR18=0x342D, DQSOSC=396, MR23=63, INC=94, DEC=62
1125 14:44:20.263227
1126 14:44:20.263294 ----->DramcWriteLeveling(PI) begin...
1127 14:44:20.263347 ==
1128 14:44:20.263400 Dram Type= 6, Freq= 0, CH_0, rank 1
1129 14:44:20.263452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1130 14:44:20.263505 ==
1131 14:44:20.263557 Write leveling (Byte 0): 31 => 31
1132 14:44:20.263610 Write leveling (Byte 1): 27 => 27
1133 14:44:20.263663 DramcWriteLeveling(PI) end<-----
1134 14:44:20.263715
1135 14:44:20.263766 ==
1136 14:44:20.263819 Dram Type= 6, Freq= 0, CH_0, rank 1
1137 14:44:20.263912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1138 14:44:20.263985 ==
1139 14:44:20.264038 [Gating] SW mode calibration
1140 14:44:20.264121 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1141 14:44:20.264188 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1142 14:44:20.264272 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1143 14:44:20.264339 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1144 14:44:20.264392 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1145 14:44:20.264444 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 14:44:20.264497 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 14:44:20.264548 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 14:44:20.264600 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 14:44:20.264653 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 14:44:20.264705 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 14:44:20.264757 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 14:44:20.264809 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 14:44:20.264861 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 14:44:20.264913 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 14:44:20.264965 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 14:44:20.265017 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 14:44:20.265069 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 14:44:20.265120 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1159 14:44:20.265172 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1160 14:44:20.265225 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1161 14:44:20.265306 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 14:44:20.265396 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 14:44:20.265451 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 14:44:20.265520 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 14:44:20.265587 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 14:44:20.265640 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 14:44:20.265693 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1168 14:44:20.265745 0 9 8 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
1169 14:44:20.265798 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1170 14:44:20.265850 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1171 14:44:20.265902 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1172 14:44:20.265954 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 14:44:20.266007 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 14:44:20.266059 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 14:44:20.266111 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
1176 14:44:20.266164 0 10 8 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (0 0)
1177 14:44:20.266216 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 14:44:20.266269 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 14:44:20.266322 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 14:44:20.266374 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 14:44:20.266427 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 14:44:20.266480 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 14:44:20.266532 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
1184 14:44:20.266585 0 11 8 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
1185 14:44:20.266637 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 14:44:20.266690 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 14:44:20.266743 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 14:44:20.266795 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 14:44:20.266848 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 14:44:20.266900 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 14:44:20.266971 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1192 14:44:20.267305 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1193 14:44:20.267419 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 14:44:20.267489 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 14:44:20.267542 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 14:44:20.267596 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 14:44:20.267648 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 14:44:20.267701 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 14:44:20.267771 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 14:44:20.267838 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 14:44:20.267890 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 14:44:20.267943 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 14:44:20.267995 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 14:44:20.268048 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 14:44:20.268100 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 14:44:20.268152 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 14:44:20.268204 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1208 14:44:20.268257 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1209 14:44:20.268310 Total UI for P1: 0, mck2ui 16
1210 14:44:20.268363 best dqsien dly found for B0: ( 0, 14, 4)
1211 14:44:20.268416 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 14:44:20.268469 Total UI for P1: 0, mck2ui 16
1213 14:44:20.268521 best dqsien dly found for B1: ( 0, 14, 8)
1214 14:44:20.268574 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1215 14:44:20.268626 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1216 14:44:20.268679
1217 14:44:20.268731 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1218 14:44:20.268783 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1219 14:44:20.268836 [Gating] SW calibration Done
1220 14:44:20.268888 ==
1221 14:44:20.268940 Dram Type= 6, Freq= 0, CH_0, rank 1
1222 14:44:20.268993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1223 14:44:20.269046 ==
1224 14:44:20.269098 RX Vref Scan: 0
1225 14:44:20.269151
1226 14:44:20.269203 RX Vref 0 -> 0, step: 1
1227 14:44:20.269255
1228 14:44:20.269366 RX Delay -130 -> 252, step: 16
1229 14:44:20.269420 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1230 14:44:20.269487 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1231 14:44:20.269557 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1232 14:44:20.269611 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1233 14:44:20.269665 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1234 14:44:20.269733 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1235 14:44:20.269785 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1236 14:44:20.269838 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1237 14:44:20.269890 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1238 14:44:20.269942 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1239 14:44:20.269994 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1240 14:44:20.270046 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1241 14:44:20.270116 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1242 14:44:20.270181 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1243 14:44:20.270234 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1244 14:44:20.270287 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1245 14:44:20.270338 ==
1246 14:44:20.270391 Dram Type= 6, Freq= 0, CH_0, rank 1
1247 14:44:20.270443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1248 14:44:20.270497 ==
1249 14:44:20.270551 DQS Delay:
1250 14:44:20.270629 DQS0 = 0, DQS1 = 0
1251 14:44:20.270683 DQM Delay:
1252 14:44:20.270736 DQM0 = 85, DQM1 = 77
1253 14:44:20.270789 DQ Delay:
1254 14:44:20.270842 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1255 14:44:20.270895 DQ4 =93, DQ5 =69, DQ6 =93, DQ7 =93
1256 14:44:20.270947 DQ8 =69, DQ9 =61, DQ10 =85, DQ11 =69
1257 14:44:20.271000 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1258 14:44:20.271053
1259 14:44:20.271105
1260 14:44:20.271157 ==
1261 14:44:20.271209 Dram Type= 6, Freq= 0, CH_0, rank 1
1262 14:44:20.271262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1263 14:44:20.271315 ==
1264 14:44:20.271368
1265 14:44:20.271484
1266 14:44:20.271566 TX Vref Scan disable
1267 14:44:20.271644 == TX Byte 0 ==
1268 14:44:20.271699 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1269 14:44:20.271753 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1270 14:44:20.271806 == TX Byte 1 ==
1271 14:44:20.271858 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1272 14:44:20.271911 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1273 14:44:20.271964 ==
1274 14:44:20.272016 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 14:44:20.272068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 14:44:20.272121 ==
1277 14:44:20.272173 TX Vref=22, minBit 1, minWin=27, winSum=443
1278 14:44:20.272226 TX Vref=24, minBit 0, minWin=27, winSum=445
1279 14:44:20.272280 TX Vref=26, minBit 2, minWin=27, winSum=448
1280 14:44:20.272332 TX Vref=28, minBit 1, minWin=27, winSum=449
1281 14:44:20.272385 TX Vref=30, minBit 2, minWin=27, winSum=450
1282 14:44:20.272454 TX Vref=32, minBit 1, minWin=27, winSum=449
1283 14:44:20.272521 [TxChooseVref] Worse bit 2, Min win 27, Win sum 450, Final Vref 30
1284 14:44:20.272574
1285 14:44:20.272626 Final TX Range 1 Vref 30
1286 14:44:20.272679
1287 14:44:20.272730 ==
1288 14:44:20.272783 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 14:44:20.272835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 14:44:20.272888 ==
1291 14:44:20.272940
1292 14:44:20.272992
1293 14:44:20.273043 TX Vref Scan disable
1294 14:44:20.273096 == TX Byte 0 ==
1295 14:44:20.273148 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1296 14:44:20.273200 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1297 14:44:20.273280 == TX Byte 1 ==
1298 14:44:20.273349 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1299 14:44:20.273445 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1300 14:44:20.273530
1301 14:44:20.273581 [DATLAT]
1302 14:44:20.273633 Freq=800, CH0 RK1
1303 14:44:20.273701
1304 14:44:20.273775 DATLAT Default: 0xa
1305 14:44:20.273848 0, 0xFFFF, sum = 0
1306 14:44:20.273904 1, 0xFFFF, sum = 0
1307 14:44:20.273957 2, 0xFFFF, sum = 0
1308 14:44:20.274009 3, 0xFFFF, sum = 0
1309 14:44:20.274062 4, 0xFFFF, sum = 0
1310 14:44:20.274115 5, 0xFFFF, sum = 0
1311 14:44:20.274168 6, 0xFFFF, sum = 0
1312 14:44:20.274236 7, 0xFFFF, sum = 0
1313 14:44:20.274302 8, 0xFFFF, sum = 0
1314 14:44:20.274354 9, 0x0, sum = 1
1315 14:44:20.274425 10, 0x0, sum = 2
1316 14:44:20.274479 11, 0x0, sum = 3
1317 14:44:20.274563 12, 0x0, sum = 4
1318 14:44:20.274617 best_step = 10
1319 14:44:20.274670
1320 14:44:20.274723 ==
1321 14:44:20.274789 Dram Type= 6, Freq= 0, CH_0, rank 1
1322 14:44:20.274841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1323 14:44:20.274894 ==
1324 14:44:20.274946 RX Vref Scan: 0
1325 14:44:20.274997
1326 14:44:20.275049 RX Vref 0 -> 0, step: 1
1327 14:44:20.275101
1328 14:44:20.275365 RX Delay -95 -> 252, step: 8
1329 14:44:20.275431 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1330 14:44:20.275485 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1331 14:44:20.275538 iDelay=209, Bit 2, Center 84 (-23 ~ 192) 216
1332 14:44:20.275590 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1333 14:44:20.275642 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1334 14:44:20.275694 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1335 14:44:20.275746 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1336 14:44:20.275798 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1337 14:44:20.275851 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1338 14:44:20.275903 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1339 14:44:20.275956 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1340 14:44:20.276008 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1341 14:44:20.276060 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1342 14:44:20.276112 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1343 14:44:20.276164 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1344 14:44:20.276216 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1345 14:44:20.276267 ==
1346 14:44:20.276318 Dram Type= 6, Freq= 0, CH_0, rank 1
1347 14:44:20.276370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1348 14:44:20.276422 ==
1349 14:44:20.276474 DQS Delay:
1350 14:44:20.276525 DQS0 = 0, DQS1 = 0
1351 14:44:20.276577 DQM Delay:
1352 14:44:20.276649 DQM0 = 87, DQM1 = 76
1353 14:44:20.276702 DQ Delay:
1354 14:44:20.276755 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =80
1355 14:44:20.276807 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1356 14:44:20.276859 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
1357 14:44:20.276910 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1358 14:44:20.276962
1359 14:44:20.277017
1360 14:44:20.277106 [DQSOSCAuto] RK1, (LSB)MR18= 0x312c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1361 14:44:20.277190 CH0 RK1: MR19=606, MR18=312C
1362 14:44:20.277296 CH0_RK1: MR19=0x606, MR18=0x312C, DQSOSC=397, MR23=63, INC=93, DEC=62
1363 14:44:20.277367 [RxdqsGatingPostProcess] freq 800
1364 14:44:20.277481 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1365 14:44:20.277558 Pre-setting of DQS Precalculation
1366 14:44:20.277611 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1367 14:44:20.277664 ==
1368 14:44:20.277716 Dram Type= 6, Freq= 0, CH_1, rank 0
1369 14:44:20.277768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 14:44:20.277820 ==
1371 14:44:20.277872 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1372 14:44:20.277925 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1373 14:44:20.277977 [CA 0] Center 37 (6~68) winsize 63
1374 14:44:20.278055 [CA 1] Center 37 (6~68) winsize 63
1375 14:44:20.278127 [CA 2] Center 35 (5~65) winsize 61
1376 14:44:20.278179 [CA 3] Center 34 (4~65) winsize 62
1377 14:44:20.278231 [CA 4] Center 34 (4~65) winsize 62
1378 14:44:20.278283 [CA 5] Center 33 (3~64) winsize 62
1379 14:44:20.278334
1380 14:44:20.278386 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1381 14:44:20.278438
1382 14:44:20.278489 [CATrainingPosCal] consider 1 rank data
1383 14:44:20.278541 u2DelayCellTimex100 = 270/100 ps
1384 14:44:20.278593 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1385 14:44:20.278644 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1386 14:44:20.278696 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1387 14:44:20.278747 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1388 14:44:20.278799 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1389 14:44:20.278851 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1390 14:44:20.278902
1391 14:44:20.278954 CA PerBit enable=1, Macro0, CA PI delay=33
1392 14:44:20.279006
1393 14:44:20.279058 [CBTSetCACLKResult] CA Dly = 33
1394 14:44:20.279109 CS Dly: 4 (0~35)
1395 14:44:20.279160 ==
1396 14:44:20.279212 Dram Type= 6, Freq= 0, CH_1, rank 1
1397 14:44:20.279263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1398 14:44:20.279316 ==
1399 14:44:20.279368 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1400 14:44:20.279420 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1401 14:44:20.279472 [CA 0] Center 37 (6~68) winsize 63
1402 14:44:20.279524 [CA 1] Center 36 (6~67) winsize 62
1403 14:44:20.279576 [CA 2] Center 34 (4~65) winsize 62
1404 14:44:20.279627 [CA 3] Center 33 (3~64) winsize 62
1405 14:44:20.279679 [CA 4] Center 34 (3~65) winsize 63
1406 14:44:20.279731 [CA 5] Center 34 (3~65) winsize 63
1407 14:44:20.279783
1408 14:44:20.279835 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1409 14:44:20.279887
1410 14:44:20.279938 [CATrainingPosCal] consider 2 rank data
1411 14:44:20.280006 u2DelayCellTimex100 = 270/100 ps
1412 14:44:20.280060 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1413 14:44:20.280117 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1414 14:44:20.280248 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1415 14:44:20.280303 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1416 14:44:20.280357 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1417 14:44:20.280409 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1418 14:44:20.280462
1419 14:44:20.280514 CA PerBit enable=1, Macro0, CA PI delay=33
1420 14:44:20.280566
1421 14:44:20.280617 [CBTSetCACLKResult] CA Dly = 33
1422 14:44:20.280669 CS Dly: 5 (0~38)
1423 14:44:20.280721
1424 14:44:20.280773 ----->DramcWriteLeveling(PI) begin...
1425 14:44:20.280825 ==
1426 14:44:20.280877 Dram Type= 6, Freq= 0, CH_1, rank 0
1427 14:44:20.280929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1428 14:44:20.280981 ==
1429 14:44:20.281033 Write leveling (Byte 0): 27 => 27
1430 14:44:20.281085 Write leveling (Byte 1): 27 => 27
1431 14:44:20.281137 DramcWriteLeveling(PI) end<-----
1432 14:44:20.281188
1433 14:44:20.281239 ==
1434 14:44:20.281335 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 14:44:20.281422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 14:44:20.281547 ==
1437 14:44:20.281636 [Gating] SW mode calibration
1438 14:44:20.281704 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1439 14:44:20.281759 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1440 14:44:20.281812 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1441 14:44:20.281865 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1442 14:44:20.281917 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1443 14:44:20.281969 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 14:44:20.282021 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 14:44:20.282291 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 14:44:20.282370 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 14:44:20.282438 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 14:44:20.282491 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 14:44:20.282544 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 14:44:20.282597 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 14:44:20.282649 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 14:44:20.282702 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 14:44:20.282755 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 14:44:20.282807 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 14:44:20.282859 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 14:44:20.282911 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1457 14:44:20.282963 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1458 14:44:20.283015 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 14:44:20.283067 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 14:44:20.283119 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 14:44:20.283173 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 14:44:20.283226 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 14:44:20.283277 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 14:44:20.283329 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 14:44:20.283380 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1466 14:44:20.283432 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1467 14:44:20.283483 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1468 14:44:20.283559 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 14:44:20.283615 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 14:44:20.283668 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 14:44:20.283720 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 14:44:20.283772 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 14:44:20.283824 0 10 4 | B1->B0 | 3131 2f2f | 1 1 | (1 1) (1 1)
1474 14:44:20.283876 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1475 14:44:20.283928 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 14:44:20.283981 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 14:44:20.284033 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 14:44:20.284085 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 14:44:20.284137 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 14:44:20.284189 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 14:44:20.284241 0 11 4 | B1->B0 | 2828 2e2e | 0 0 | (0 0) (0 0)
1482 14:44:20.284293 0 11 8 | B1->B0 | 4040 4242 | 0 0 | (0 0) (0 0)
1483 14:44:20.284345 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1484 14:44:20.284399 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 14:44:20.284452 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 14:44:20.284504 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 14:44:20.284556 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 14:44:20.284607 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 14:44:20.284659 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1490 14:44:20.284711 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1491 14:44:20.284763 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 14:44:20.284815 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 14:44:20.284867 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 14:44:20.284949 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 14:44:20.285001 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 14:44:20.285052 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 14:44:20.285104 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 14:44:20.285171 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 14:44:20.285224 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 14:44:20.285291 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 14:44:20.285375 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 14:44:20.285441 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 14:44:20.285493 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 14:44:20.285545 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 14:44:20.285597 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1506 14:44:20.285648 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 14:44:20.285700 Total UI for P1: 0, mck2ui 16
1508 14:44:20.285753 best dqsien dly found for B0: ( 0, 14, 4)
1509 14:44:20.285805 Total UI for P1: 0, mck2ui 16
1510 14:44:20.285857 best dqsien dly found for B1: ( 0, 14, 6)
1511 14:44:20.285909 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1512 14:44:20.285961 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1513 14:44:20.286012
1514 14:44:20.286064 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1515 14:44:20.286115 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1516 14:44:20.286167 [Gating] SW calibration Done
1517 14:44:20.286219 ==
1518 14:44:20.286271 Dram Type= 6, Freq= 0, CH_1, rank 0
1519 14:44:20.286323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1520 14:44:20.286376 ==
1521 14:44:20.286428 RX Vref Scan: 0
1522 14:44:20.286480
1523 14:44:20.286531 RX Vref 0 -> 0, step: 1
1524 14:44:20.286582
1525 14:44:20.286633 RX Delay -130 -> 252, step: 16
1526 14:44:20.286685 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1527 14:44:20.286737 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1528 14:44:20.286788 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1529 14:44:20.286839 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1530 14:44:20.286891 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1531 14:44:20.286942 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1532 14:44:20.286994 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1533 14:44:20.287045 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1534 14:44:20.287097 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1535 14:44:20.287356 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1536 14:44:20.287473 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1537 14:44:20.287575 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1538 14:44:20.287666 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1539 14:44:20.287724 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1540 14:44:20.287778 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1541 14:44:20.287835 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1542 14:44:20.287889 ==
1543 14:44:20.287943 Dram Type= 6, Freq= 0, CH_1, rank 0
1544 14:44:20.288011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1545 14:44:20.288064 ==
1546 14:44:20.288117 DQS Delay:
1547 14:44:20.288169 DQS0 = 0, DQS1 = 0
1548 14:44:20.288221 DQM Delay:
1549 14:44:20.288277 DQM0 = 86, DQM1 = 79
1550 14:44:20.288360 DQ Delay:
1551 14:44:20.288412 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1552 14:44:20.288464 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =85
1553 14:44:20.288516 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1554 14:44:20.288569 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1555 14:44:20.288620
1556 14:44:20.288672
1557 14:44:20.288757 ==
1558 14:44:20.288808 Dram Type= 6, Freq= 0, CH_1, rank 0
1559 14:44:20.288860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1560 14:44:20.288913 ==
1561 14:44:20.288965
1562 14:44:20.289015
1563 14:44:20.289066 TX Vref Scan disable
1564 14:44:20.289118 == TX Byte 0 ==
1565 14:44:20.289171 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1566 14:44:20.289223 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1567 14:44:20.289319 == TX Byte 1 ==
1568 14:44:20.289372 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1569 14:44:20.289425 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1570 14:44:20.289477 ==
1571 14:44:20.289528 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 14:44:20.289580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 14:44:20.289633 ==
1574 14:44:20.289685 TX Vref=22, minBit 1, minWin=27, winSum=443
1575 14:44:20.289738 TX Vref=24, minBit 4, minWin=27, winSum=450
1576 14:44:20.289790 TX Vref=26, minBit 5, minWin=27, winSum=453
1577 14:44:20.289842 TX Vref=28, minBit 1, minWin=27, winSum=454
1578 14:44:20.289894 TX Vref=30, minBit 1, minWin=27, winSum=455
1579 14:44:20.289947 TX Vref=32, minBit 1, minWin=27, winSum=449
1580 14:44:20.289998 [TxChooseVref] Worse bit 1, Min win 27, Win sum 455, Final Vref 30
1581 14:44:20.290067
1582 14:44:20.290149 Final TX Range 1 Vref 30
1583 14:44:20.290232
1584 14:44:20.290314 ==
1585 14:44:20.290380 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 14:44:20.290433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 14:44:20.290485 ==
1588 14:44:20.290537
1589 14:44:20.290618
1590 14:44:20.290670 TX Vref Scan disable
1591 14:44:20.290721 == TX Byte 0 ==
1592 14:44:20.290773 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1593 14:44:20.290842 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1594 14:44:20.290909 == TX Byte 1 ==
1595 14:44:20.290961 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1596 14:44:20.291013 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1597 14:44:20.291065
1598 14:44:20.291116 [DATLAT]
1599 14:44:20.291168 Freq=800, CH1 RK0
1600 14:44:20.291219
1601 14:44:20.291272 DATLAT Default: 0xa
1602 14:44:20.291323 0, 0xFFFF, sum = 0
1603 14:44:20.291377 1, 0xFFFF, sum = 0
1604 14:44:20.291430 2, 0xFFFF, sum = 0
1605 14:44:20.291482 3, 0xFFFF, sum = 0
1606 14:44:20.291534 4, 0xFFFF, sum = 0
1607 14:44:20.291586 5, 0xFFFF, sum = 0
1608 14:44:20.291639 6, 0xFFFF, sum = 0
1609 14:44:20.291691 7, 0xFFFF, sum = 0
1610 14:44:20.291744 8, 0xFFFF, sum = 0
1611 14:44:20.291813 9, 0x0, sum = 1
1612 14:44:20.291879 10, 0x0, sum = 2
1613 14:44:20.291931 11, 0x0, sum = 3
1614 14:44:20.291983 12, 0x0, sum = 4
1615 14:44:20.292035 best_step = 10
1616 14:44:20.292087
1617 14:44:20.292137 ==
1618 14:44:20.292189 Dram Type= 6, Freq= 0, CH_1, rank 0
1619 14:44:20.292241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1620 14:44:20.292293 ==
1621 14:44:20.292345 RX Vref Scan: 1
1622 14:44:20.292396
1623 14:44:20.292447 Set Vref Range= 32 -> 127
1624 14:44:20.292499
1625 14:44:20.292550 RX Vref 32 -> 127, step: 1
1626 14:44:20.292602
1627 14:44:20.292653 RX Delay -95 -> 252, step: 8
1628 14:44:20.292705
1629 14:44:20.292756 Set Vref, RX VrefLevel [Byte0]: 32
1630 14:44:20.292808 [Byte1]: 32
1631 14:44:20.292859
1632 14:44:20.292910 Set Vref, RX VrefLevel [Byte0]: 33
1633 14:44:20.292961 [Byte1]: 33
1634 14:44:20.293013
1635 14:44:20.293063 Set Vref, RX VrefLevel [Byte0]: 34
1636 14:44:20.293115 [Byte1]: 34
1637 14:44:20.293167
1638 14:44:20.293218 Set Vref, RX VrefLevel [Byte0]: 35
1639 14:44:20.293290 [Byte1]: 35
1640 14:44:20.293355
1641 14:44:20.293407 Set Vref, RX VrefLevel [Byte0]: 36
1642 14:44:20.293458 [Byte1]: 36
1643 14:44:20.293510
1644 14:44:20.293561 Set Vref, RX VrefLevel [Byte0]: 37
1645 14:44:20.293612 [Byte1]: 37
1646 14:44:20.293665
1647 14:44:20.293717 Set Vref, RX VrefLevel [Byte0]: 38
1648 14:44:20.293768 [Byte1]: 38
1649 14:44:20.293819
1650 14:44:20.293871 Set Vref, RX VrefLevel [Byte0]: 39
1651 14:44:20.293922 [Byte1]: 39
1652 14:44:20.293973
1653 14:44:20.294024 Set Vref, RX VrefLevel [Byte0]: 40
1654 14:44:20.294076 [Byte1]: 40
1655 14:44:20.294127
1656 14:44:20.294179 Set Vref, RX VrefLevel [Byte0]: 41
1657 14:44:20.294230 [Byte1]: 41
1658 14:44:20.294281
1659 14:44:20.294373 Set Vref, RX VrefLevel [Byte0]: 42
1660 14:44:20.294426 [Byte1]: 42
1661 14:44:20.294478
1662 14:44:20.294529 Set Vref, RX VrefLevel [Byte0]: 43
1663 14:44:20.294581 [Byte1]: 43
1664 14:44:20.294633
1665 14:44:20.294684 Set Vref, RX VrefLevel [Byte0]: 44
1666 14:44:20.294735 [Byte1]: 44
1667 14:44:20.294786
1668 14:44:20.294838 Set Vref, RX VrefLevel [Byte0]: 45
1669 14:44:20.294889 [Byte1]: 45
1670 14:44:20.294940
1671 14:44:20.294991 Set Vref, RX VrefLevel [Byte0]: 46
1672 14:44:20.295063 [Byte1]: 46
1673 14:44:20.295129
1674 14:44:20.295180 Set Vref, RX VrefLevel [Byte0]: 47
1675 14:44:20.295231 [Byte1]: 47
1676 14:44:20.295283
1677 14:44:20.295334 Set Vref, RX VrefLevel [Byte0]: 48
1678 14:44:20.295386 [Byte1]: 48
1679 14:44:20.295438
1680 14:44:20.295489 Set Vref, RX VrefLevel [Byte0]: 49
1681 14:44:20.295540 [Byte1]: 49
1682 14:44:20.295592
1683 14:44:20.295675 Set Vref, RX VrefLevel [Byte0]: 50
1684 14:44:20.295726 [Byte1]: 50
1685 14:44:20.295777
1686 14:44:20.295863 Set Vref, RX VrefLevel [Byte0]: 51
1687 14:44:20.295915 [Byte1]: 51
1688 14:44:20.295968
1689 14:44:20.296019 Set Vref, RX VrefLevel [Byte0]: 52
1690 14:44:20.296071 [Byte1]: 52
1691 14:44:20.296122
1692 14:44:20.296173 Set Vref, RX VrefLevel [Byte0]: 53
1693 14:44:20.296266 [Byte1]: 53
1694 14:44:20.296333
1695 14:44:20.296384 Set Vref, RX VrefLevel [Byte0]: 54
1696 14:44:20.296436 [Byte1]: 54
1697 14:44:20.296487
1698 14:44:20.296750 Set Vref, RX VrefLevel [Byte0]: 55
1699 14:44:20.296815 [Byte1]: 55
1700 14:44:20.296898
1701 14:44:20.296965 Set Vref, RX VrefLevel [Byte0]: 56
1702 14:44:20.297027 [Byte1]: 56
1703 14:44:20.297080
1704 14:44:20.297133 Set Vref, RX VrefLevel [Byte0]: 57
1705 14:44:20.297186 [Byte1]: 57
1706 14:44:20.297239
1707 14:44:20.297306 Set Vref, RX VrefLevel [Byte0]: 58
1708 14:44:20.297403 [Byte1]: 58
1709 14:44:20.297455
1710 14:44:20.297523 Set Vref, RX VrefLevel [Byte0]: 59
1711 14:44:20.297583 [Byte1]: 59
1712 14:44:20.297651
1713 14:44:20.297731 Set Vref, RX VrefLevel [Byte0]: 60
1714 14:44:20.297783 [Byte1]: 60
1715 14:44:20.297834
1716 14:44:20.297901 Set Vref, RX VrefLevel [Byte0]: 61
1717 14:44:20.297968 [Byte1]: 61
1718 14:44:20.298019
1719 14:44:20.298071 Set Vref, RX VrefLevel [Byte0]: 62
1720 14:44:20.298122 [Byte1]: 62
1721 14:44:20.298177
1722 14:44:20.298237 Set Vref, RX VrefLevel [Byte0]: 63
1723 14:44:20.298313 [Byte1]: 63
1724 14:44:20.298410
1725 14:44:20.298461 Set Vref, RX VrefLevel [Byte0]: 64
1726 14:44:20.298513 [Byte1]: 64
1727 14:44:20.298564
1728 14:44:20.298615 Set Vref, RX VrefLevel [Byte0]: 65
1729 14:44:20.298667 [Byte1]: 65
1730 14:44:20.298719
1731 14:44:20.298776 Set Vref, RX VrefLevel [Byte0]: 66
1732 14:44:20.298830 [Byte1]: 66
1733 14:44:20.298882
1734 14:44:20.298932 Set Vref, RX VrefLevel [Byte0]: 67
1735 14:44:20.298984 [Byte1]: 67
1736 14:44:20.299035
1737 14:44:20.299086 Set Vref, RX VrefLevel [Byte0]: 68
1738 14:44:20.299137 [Byte1]: 68
1739 14:44:20.299189
1740 14:44:20.299270 Set Vref, RX VrefLevel [Byte0]: 69
1741 14:44:20.299357 [Byte1]: 69
1742 14:44:20.299410
1743 14:44:20.299461 Set Vref, RX VrefLevel [Byte0]: 70
1744 14:44:20.299513 [Byte1]: 70
1745 14:44:20.299564
1746 14:44:20.299615 Set Vref, RX VrefLevel [Byte0]: 71
1747 14:44:20.299667 [Byte1]: 71
1748 14:44:20.299718
1749 14:44:20.299769 Set Vref, RX VrefLevel [Byte0]: 72
1750 14:44:20.299821 [Byte1]: 72
1751 14:44:20.299873
1752 14:44:20.299924 Set Vref, RX VrefLevel [Byte0]: 73
1753 14:44:20.299976 [Byte1]: 73
1754 14:44:20.300027
1755 14:44:20.300078 Set Vref, RX VrefLevel [Byte0]: 74
1756 14:44:20.300130 [Byte1]: 74
1757 14:44:20.300181
1758 14:44:20.300232 Set Vref, RX VrefLevel [Byte0]: 75
1759 14:44:20.300284 [Byte1]: 75
1760 14:44:20.300335
1761 14:44:20.300386 Final RX Vref Byte 0 = 60 to rank0
1762 14:44:20.300439 Final RX Vref Byte 1 = 64 to rank0
1763 14:44:20.300490 Final RX Vref Byte 0 = 60 to rank1
1764 14:44:20.300543 Final RX Vref Byte 1 = 64 to rank1==
1765 14:44:20.300594 Dram Type= 6, Freq= 0, CH_1, rank 0
1766 14:44:20.300646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1767 14:44:20.300698 ==
1768 14:44:20.300750 DQS Delay:
1769 14:44:20.300802 DQS0 = 0, DQS1 = 0
1770 14:44:20.300855 DQM Delay:
1771 14:44:20.300906 DQM0 = 86, DQM1 = 80
1772 14:44:20.300958 DQ Delay:
1773 14:44:20.301009 DQ0 =88, DQ1 =80, DQ2 =76, DQ3 =84
1774 14:44:20.301061 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1775 14:44:20.301113 DQ8 =64, DQ9 =72, DQ10 =80, DQ11 =72
1776 14:44:20.301165 DQ12 =92, DQ13 =88, DQ14 =84, DQ15 =88
1777 14:44:20.301216
1778 14:44:20.301291
1779 14:44:20.301360 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a2e, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1780 14:44:20.301413 CH1 RK0: MR19=606, MR18=1A2E
1781 14:44:20.301466 CH1_RK0: MR19=0x606, MR18=0x1A2E, DQSOSC=398, MR23=63, INC=93, DEC=62
1782 14:44:20.301518
1783 14:44:20.301570 ----->DramcWriteLeveling(PI) begin...
1784 14:44:20.301623 ==
1785 14:44:20.301674 Dram Type= 6, Freq= 0, CH_1, rank 1
1786 14:44:20.301726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1787 14:44:20.301778 ==
1788 14:44:20.301830 Write leveling (Byte 0): 26 => 26
1789 14:44:20.301882 Write leveling (Byte 1): 30 => 30
1790 14:44:20.301940 DramcWriteLeveling(PI) end<-----
1791 14:44:20.301994
1792 14:44:20.302045 ==
1793 14:44:20.302097 Dram Type= 6, Freq= 0, CH_1, rank 1
1794 14:44:20.302149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1795 14:44:20.302201 ==
1796 14:44:20.302254 [Gating] SW mode calibration
1797 14:44:20.302306 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1798 14:44:20.302358 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1799 14:44:20.302422 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1800 14:44:20.302477 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1801 14:44:20.302529 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 14:44:20.302581 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 14:44:20.302634 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 14:44:20.302686 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 14:44:20.302738 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 14:44:20.302789 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 14:44:20.302841 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 14:44:20.302892 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 14:44:20.302944 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 14:44:20.303003 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 14:44:20.303057 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 14:44:20.303109 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 14:44:20.303161 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 14:44:20.303212 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 14:44:20.303264 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1816 14:44:20.303316 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1817 14:44:20.303368 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1818 14:44:20.303419 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 14:44:20.303471 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 14:44:20.303523 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 14:44:20.303584 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 14:44:20.303637 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 14:44:20.303690 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 14:44:20.303742 0 9 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1825 14:44:20.304001 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1826 14:44:20.304062 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 14:44:20.304116 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 14:44:20.304191 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 14:44:20.304259 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 14:44:20.304311 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 14:44:20.304364 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1832 14:44:20.304416 0 10 4 | B1->B0 | 3131 3030 | 0 0 | (0 0) (0 1)
1833 14:44:20.304468 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1834 14:44:20.304520 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 14:44:20.304572 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 14:44:20.304624 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 14:44:20.304685 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 14:44:20.304738 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 14:44:20.304790 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1840 14:44:20.304842 0 11 4 | B1->B0 | 2626 4040 | 0 0 | (0 0) (1 1)
1841 14:44:20.304894 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1842 14:44:20.304947 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 14:44:20.305000 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 14:44:20.305052 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 14:44:20.305105 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 14:44:20.305157 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 14:44:20.305209 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 14:44:20.305310 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1849 14:44:20.305366 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1850 14:44:20.305419 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 14:44:20.305471 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 14:44:20.305523 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 14:44:20.305575 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 14:44:20.305627 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 14:44:20.305679 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 14:44:20.305731 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 14:44:20.305783 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 14:44:20.305835 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 14:44:20.305896 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 14:44:20.305951 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 14:44:20.306044 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 14:44:20.306097 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 14:44:20.306148 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1864 14:44:20.306201 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1865 14:44:20.306253 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 14:44:20.306305 Total UI for P1: 0, mck2ui 16
1867 14:44:20.306357 best dqsien dly found for B0: ( 0, 14, 2)
1868 14:44:20.306409 Total UI for P1: 0, mck2ui 16
1869 14:44:20.306471 best dqsien dly found for B1: ( 0, 14, 4)
1870 14:44:20.306524 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1871 14:44:20.306576 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1872 14:44:20.306628
1873 14:44:20.306680 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1874 14:44:20.306732 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1875 14:44:20.306784 [Gating] SW calibration Done
1876 14:44:20.306835 ==
1877 14:44:20.306887 Dram Type= 6, Freq= 0, CH_1, rank 1
1878 14:44:20.306941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1879 14:44:20.307003 ==
1880 14:44:20.307056 RX Vref Scan: 0
1881 14:44:20.307107
1882 14:44:20.307159 RX Vref 0 -> 0, step: 1
1883 14:44:20.307211
1884 14:44:20.307262 RX Delay -130 -> 252, step: 16
1885 14:44:20.307314 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1886 14:44:20.307366 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1887 14:44:20.307417 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1888 14:44:20.307469 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1889 14:44:20.307571 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1890 14:44:20.307623 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1891 14:44:20.307675 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1892 14:44:20.307726 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1893 14:44:20.307778 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1894 14:44:20.307830 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1895 14:44:20.307881 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1896 14:44:20.307934 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1897 14:44:20.307985 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1898 14:44:20.308063 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1899 14:44:20.308134 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1900 14:44:20.308186 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1901 14:44:20.308238 ==
1902 14:44:20.308289 Dram Type= 6, Freq= 0, CH_1, rank 1
1903 14:44:20.308342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1904 14:44:20.308394 ==
1905 14:44:20.308445 DQS Delay:
1906 14:44:20.308497 DQS0 = 0, DQS1 = 0
1907 14:44:20.308548 DQM Delay:
1908 14:44:20.308621 DQM0 = 79, DQM1 = 80
1909 14:44:20.308680 DQ Delay:
1910 14:44:20.308745 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =69
1911 14:44:20.308812 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1912 14:44:20.308866 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1913 14:44:20.308931 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1914 14:44:20.308983
1915 14:44:20.309034
1916 14:44:20.309086 ==
1917 14:44:20.309138 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 14:44:20.444676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1919 14:44:20.444815 ==
1920 14:44:20.444882
1921 14:44:20.444942
1922 14:44:20.445000 TX Vref Scan disable
1923 14:44:20.445058 == TX Byte 0 ==
1924 14:44:20.445114 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1925 14:44:20.445199 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1926 14:44:20.445294 == TX Byte 1 ==
1927 14:44:20.445352 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1928 14:44:20.445407 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1929 14:44:20.445462 ==
1930 14:44:20.445517 Dram Type= 6, Freq= 0, CH_1, rank 1
1931 14:44:20.445780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1932 14:44:20.445845 ==
1933 14:44:20.445902 TX Vref=22, minBit 2, minWin=27, winSum=446
1934 14:44:20.445958 TX Vref=24, minBit 1, minWin=27, winSum=451
1935 14:44:20.446013 TX Vref=26, minBit 0, minWin=28, winSum=453
1936 14:44:20.446066 TX Vref=28, minBit 1, minWin=27, winSum=451
1937 14:44:20.446120 TX Vref=30, minBit 0, minWin=28, winSum=455
1938 14:44:20.446174 TX Vref=32, minBit 1, minWin=27, winSum=452
1939 14:44:20.446227 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30
1940 14:44:20.446282
1941 14:44:20.446335 Final TX Range 1 Vref 30
1942 14:44:20.446389
1943 14:44:20.446441 ==
1944 14:44:20.446494 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 14:44:20.446547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 14:44:20.446600 ==
1947 14:44:20.446653
1948 14:44:20.446705
1949 14:44:20.446757 TX Vref Scan disable
1950 14:44:20.446811 == TX Byte 0 ==
1951 14:44:20.446863 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1952 14:44:20.446917 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1953 14:44:20.446969 == TX Byte 1 ==
1954 14:44:20.447021 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1955 14:44:20.447074 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1956 14:44:20.447127
1957 14:44:20.447179 [DATLAT]
1958 14:44:20.447231 Freq=800, CH1 RK1
1959 14:44:20.447285
1960 14:44:20.447337 DATLAT Default: 0xa
1961 14:44:20.447390 0, 0xFFFF, sum = 0
1962 14:44:20.447444 1, 0xFFFF, sum = 0
1963 14:44:20.447498 2, 0xFFFF, sum = 0
1964 14:44:20.447552 3, 0xFFFF, sum = 0
1965 14:44:20.447605 4, 0xFFFF, sum = 0
1966 14:44:20.447658 5, 0xFFFF, sum = 0
1967 14:44:20.447712 6, 0xFFFF, sum = 0
1968 14:44:20.447766 7, 0xFFFF, sum = 0
1969 14:44:20.447819 8, 0xFFFF, sum = 0
1970 14:44:20.447872 9, 0x0, sum = 1
1971 14:44:20.447926 10, 0x0, sum = 2
1972 14:44:20.447980 11, 0x0, sum = 3
1973 14:44:20.448034 12, 0x0, sum = 4
1974 14:44:20.448087 best_step = 10
1975 14:44:20.448139
1976 14:44:20.448191 ==
1977 14:44:20.448257 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 14:44:20.448309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 14:44:20.448361 ==
1980 14:44:20.448426 RX Vref Scan: 0
1981 14:44:20.448492
1982 14:44:20.448543 RX Vref 0 -> 0, step: 1
1983 14:44:20.448593
1984 14:44:20.448644 RX Delay -95 -> 252, step: 8
1985 14:44:20.448696 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1986 14:44:20.448748 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1987 14:44:20.448799 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1988 14:44:20.448864 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1989 14:44:20.448951 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1990 14:44:20.449059 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1991 14:44:20.449154 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1992 14:44:20.449240 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1993 14:44:20.449343 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1994 14:44:20.449423 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1995 14:44:20.449480 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1996 14:44:20.449548 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1997 14:44:20.449601 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1998 14:44:20.449653 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1999 14:44:20.449705 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2000 14:44:20.449757 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2001 14:44:20.449808 ==
2002 14:44:20.449860 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 14:44:20.449913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 14:44:20.449965 ==
2005 14:44:20.450017 DQS Delay:
2006 14:44:20.450083 DQS0 = 0, DQS1 = 0
2007 14:44:20.450149 DQM Delay:
2008 14:44:20.450201 DQM0 = 86, DQM1 = 81
2009 14:44:20.450252 DQ Delay:
2010 14:44:20.450304 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
2011 14:44:20.450355 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2012 14:44:20.450407 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =76
2013 14:44:20.450473 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2014 14:44:20.450539
2015 14:44:20.450590
2016 14:44:20.450642 [DQSOSCAuto] RK1, (LSB)MR18= 0x2540, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
2017 14:44:20.450695 CH1 RK1: MR19=606, MR18=2540
2018 14:44:20.450747 CH1_RK1: MR19=0x606, MR18=0x2540, DQSOSC=393, MR23=63, INC=95, DEC=63
2019 14:44:20.450799 [RxdqsGatingPostProcess] freq 800
2020 14:44:20.450851 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2021 14:44:20.450903 Pre-setting of DQS Precalculation
2022 14:44:20.450955 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2023 14:44:20.451035 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2024 14:44:20.451088 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2025 14:44:20.451141
2026 14:44:20.451192
2027 14:44:20.451244 [Calibration Summary] 1600 Mbps
2028 14:44:20.451296 CH 0, Rank 0
2029 14:44:20.451348 SW Impedance : PASS
2030 14:44:20.451416 DUTY Scan : NO K
2031 14:44:20.451482 ZQ Calibration : PASS
2032 14:44:20.451534 Jitter Meter : NO K
2033 14:44:20.451594 CBT Training : PASS
2034 14:44:20.451671 Write leveling : PASS
2035 14:44:20.451725 RX DQS gating : PASS
2036 14:44:20.451778 RX DQ/DQS(RDDQC) : PASS
2037 14:44:20.451830 TX DQ/DQS : PASS
2038 14:44:20.451883 RX DATLAT : PASS
2039 14:44:20.451935 RX DQ/DQS(Engine): PASS
2040 14:44:20.452015 TX OE : NO K
2041 14:44:20.452067 All Pass.
2042 14:44:20.452119
2043 14:44:20.452171 CH 0, Rank 1
2044 14:44:20.452223 SW Impedance : PASS
2045 14:44:20.452302 DUTY Scan : NO K
2046 14:44:20.452354 ZQ Calibration : PASS
2047 14:44:20.452406 Jitter Meter : NO K
2048 14:44:20.452458 CBT Training : PASS
2049 14:44:20.452511 Write leveling : PASS
2050 14:44:20.452563 RX DQS gating : PASS
2051 14:44:20.452616 RX DQ/DQS(RDDQC) : PASS
2052 14:44:20.452668 TX DQ/DQS : PASS
2053 14:44:20.452721 RX DATLAT : PASS
2054 14:44:20.452773 RX DQ/DQS(Engine): PASS
2055 14:44:20.452826 TX OE : NO K
2056 14:44:20.452878 All Pass.
2057 14:44:20.452930
2058 14:44:20.452982 CH 1, Rank 0
2059 14:44:20.453035 SW Impedance : PASS
2060 14:44:20.453087 DUTY Scan : NO K
2061 14:44:20.453139 ZQ Calibration : PASS
2062 14:44:20.453191 Jitter Meter : NO K
2063 14:44:20.453243 CBT Training : PASS
2064 14:44:20.453334 Write leveling : PASS
2065 14:44:20.453387 RX DQS gating : PASS
2066 14:44:20.453439 RX DQ/DQS(RDDQC) : PASS
2067 14:44:20.453491 TX DQ/DQS : PASS
2068 14:44:20.453544 RX DATLAT : PASS
2069 14:44:20.453596 RX DQ/DQS(Engine): PASS
2070 14:44:20.453649 TX OE : NO K
2071 14:44:20.453718 All Pass.
2072 14:44:20.453783
2073 14:44:20.453835 CH 1, Rank 1
2074 14:44:20.453887 SW Impedance : PASS
2075 14:44:20.453940 DUTY Scan : NO K
2076 14:44:20.453993 ZQ Calibration : PASS
2077 14:44:20.454045 Jitter Meter : NO K
2078 14:44:20.454097 CBT Training : PASS
2079 14:44:20.454149 Write leveling : PASS
2080 14:44:20.454232 RX DQS gating : PASS
2081 14:44:20.454286 RX DQ/DQS(RDDQC) : PASS
2082 14:44:20.454549 TX DQ/DQS : PASS
2083 14:44:20.454611 RX DATLAT : PASS
2084 14:44:20.454665 RX DQ/DQS(Engine): PASS
2085 14:44:20.454718 TX OE : NO K
2086 14:44:20.454772 All Pass.
2087 14:44:20.454824
2088 14:44:20.454877 DramC Write-DBI off
2089 14:44:20.454929 PER_BANK_REFRESH: Hybrid Mode
2090 14:44:20.455033 TX_TRACKING: ON
2091 14:44:20.455090 [GetDramInforAfterCalByMRR] Vendor 6.
2092 14:44:20.455144 [GetDramInforAfterCalByMRR] Revision 606.
2093 14:44:20.455196 [GetDramInforAfterCalByMRR] Revision 2 0.
2094 14:44:20.455249 MR0 0x3b3b
2095 14:44:20.455301 MR8 0x5151
2096 14:44:20.455353 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2097 14:44:20.455406
2098 14:44:20.455457 MR0 0x3b3b
2099 14:44:20.455509 MR8 0x5151
2100 14:44:20.455561 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2101 14:44:20.455614
2102 14:44:20.455666 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2103 14:44:20.455719 [FAST_K] Save calibration result to emmc
2104 14:44:20.455771 [FAST_K] Save calibration result to emmc
2105 14:44:20.455823 dram_init: config_dvfs: 1
2106 14:44:20.455892 dramc_set_vcore_voltage set vcore to 662500
2107 14:44:20.455958 Read voltage for 1200, 2
2108 14:44:20.456010 Vio18 = 0
2109 14:44:20.456062 Vcore = 662500
2110 14:44:20.456114 Vdram = 0
2111 14:44:20.456166 Vddq = 0
2112 14:44:20.456218 Vmddr = 0
2113 14:44:20.456270 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2114 14:44:20.456323 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2115 14:44:20.456374 MEM_TYPE=3, freq_sel=15
2116 14:44:20.456426 sv_algorithm_assistance_LP4_1600
2117 14:44:20.456478 ============ PULL DRAM RESETB DOWN ============
2118 14:44:20.456531 ========== PULL DRAM RESETB DOWN end =========
2119 14:44:20.456584 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2120 14:44:20.456636 ===================================
2121 14:44:20.456689 LPDDR4 DRAM CONFIGURATION
2122 14:44:20.456741 ===================================
2123 14:44:20.456793 EX_ROW_EN[0] = 0x0
2124 14:44:20.456846 EX_ROW_EN[1] = 0x0
2125 14:44:20.456897 LP4Y_EN = 0x0
2126 14:44:20.456949 WORK_FSP = 0x0
2127 14:44:20.457001 WL = 0x4
2128 14:44:20.457053 RL = 0x4
2129 14:44:20.457104 BL = 0x2
2130 14:44:20.457156 RPST = 0x0
2131 14:44:20.457208 RD_PRE = 0x0
2132 14:44:20.457285 WR_PRE = 0x1
2133 14:44:20.457354 WR_PST = 0x0
2134 14:44:20.457406 DBI_WR = 0x0
2135 14:44:20.457458 DBI_RD = 0x0
2136 14:44:20.457509 OTF = 0x1
2137 14:44:20.457561 ===================================
2138 14:44:20.457614 ===================================
2139 14:44:20.457667 ANA top config
2140 14:44:20.457720 ===================================
2141 14:44:20.457771 DLL_ASYNC_EN = 0
2142 14:44:20.457823 ALL_SLAVE_EN = 0
2143 14:44:20.457875 NEW_RANK_MODE = 1
2144 14:44:20.457929 DLL_IDLE_MODE = 1
2145 14:44:20.457980 LP45_APHY_COMB_EN = 1
2146 14:44:20.458032 TX_ODT_DIS = 1
2147 14:44:20.458084 NEW_8X_MODE = 1
2148 14:44:20.458137 ===================================
2149 14:44:20.458189 ===================================
2150 14:44:20.458245 data_rate = 2400
2151 14:44:20.458323 CKR = 1
2152 14:44:20.458408 DQ_P2S_RATIO = 8
2153 14:44:20.458460 ===================================
2154 14:44:20.458512 CA_P2S_RATIO = 8
2155 14:44:20.458587 DQ_CA_OPEN = 0
2156 14:44:20.458641 DQ_SEMI_OPEN = 0
2157 14:44:20.458694 CA_SEMI_OPEN = 0
2158 14:44:20.458746 CA_FULL_RATE = 0
2159 14:44:20.458799 DQ_CKDIV4_EN = 0
2160 14:44:20.458851 CA_CKDIV4_EN = 0
2161 14:44:20.458903 CA_PREDIV_EN = 0
2162 14:44:20.458956 PH8_DLY = 17
2163 14:44:20.459009 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2164 14:44:20.459062 DQ_AAMCK_DIV = 4
2165 14:44:20.459114 CA_AAMCK_DIV = 4
2166 14:44:20.459166 CA_ADMCK_DIV = 4
2167 14:44:20.459218 DQ_TRACK_CA_EN = 0
2168 14:44:20.459270 CA_PICK = 1200
2169 14:44:20.459322 CA_MCKIO = 1200
2170 14:44:20.459375 MCKIO_SEMI = 0
2171 14:44:20.459427 PLL_FREQ = 2366
2172 14:44:20.459496 DQ_UI_PI_RATIO = 32
2173 14:44:20.459573 CA_UI_PI_RATIO = 0
2174 14:44:20.459626 ===================================
2175 14:44:20.459679 ===================================
2176 14:44:20.459732 memory_type:LPDDR4
2177 14:44:20.459784 GP_NUM : 10
2178 14:44:20.459836 SRAM_EN : 1
2179 14:44:20.459888 MD32_EN : 0
2180 14:44:20.459941 ===================================
2181 14:44:20.459993 [ANA_INIT] >>>>>>>>>>>>>>
2182 14:44:20.460045 <<<<<< [CONFIGURE PHASE]: ANA_TX
2183 14:44:20.460098 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2184 14:44:20.460151 ===================================
2185 14:44:20.460203 data_rate = 2400,PCW = 0X5b00
2186 14:44:20.460255 ===================================
2187 14:44:20.460307 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2188 14:44:20.460360 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2189 14:44:20.460413 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2190 14:44:20.460466 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2191 14:44:20.460547 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2192 14:44:20.460599 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2193 14:44:20.460652 [ANA_INIT] flow start
2194 14:44:20.460704 [ANA_INIT] PLL >>>>>>>>
2195 14:44:20.460755 [ANA_INIT] PLL <<<<<<<<
2196 14:44:20.460807 [ANA_INIT] MIDPI >>>>>>>>
2197 14:44:20.460859 [ANA_INIT] MIDPI <<<<<<<<
2198 14:44:20.460911 [ANA_INIT] DLL >>>>>>>>
2199 14:44:20.460963 [ANA_INIT] DLL <<<<<<<<
2200 14:44:20.461015 [ANA_INIT] flow end
2201 14:44:20.461067 ============ LP4 DIFF to SE enter ============
2202 14:44:20.461125 ============ LP4 DIFF to SE exit ============
2203 14:44:20.461217 [ANA_INIT] <<<<<<<<<<<<<
2204 14:44:20.461324 [Flow] Enable top DCM control >>>>>
2205 14:44:20.461379 [Flow] Enable top DCM control <<<<<
2206 14:44:20.461432 Enable DLL master slave shuffle
2207 14:44:20.461485 ==============================================================
2208 14:44:20.461552 Gating Mode config
2209 14:44:20.461623 ==============================================================
2210 14:44:20.461724 Config description:
2211 14:44:20.461991 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2212 14:44:20.462055 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2213 14:44:20.462111 SELPH_MODE 0: By rank 1: By Phase
2214 14:44:20.462166 ==============================================================
2215 14:44:20.462235 GAT_TRACK_EN = 1
2216 14:44:20.462304 RX_GATING_MODE = 2
2217 14:44:20.462356 RX_GATING_TRACK_MODE = 2
2218 14:44:20.462409 SELPH_MODE = 1
2219 14:44:20.462462 PICG_EARLY_EN = 1
2220 14:44:20.462514 VALID_LAT_VALUE = 1
2221 14:44:20.462566 ==============================================================
2222 14:44:20.462620 Enter into Gating configuration >>>>
2223 14:44:20.462690 Exit from Gating configuration <<<<
2224 14:44:20.462756 Enter into DVFS_PRE_config >>>>>
2225 14:44:20.462808 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2226 14:44:20.462862 Exit from DVFS_PRE_config <<<<<
2227 14:44:20.462914 Enter into PICG configuration >>>>
2228 14:44:20.462967 Exit from PICG configuration <<<<
2229 14:44:20.463018 [RX_INPUT] configuration >>>>>
2230 14:44:20.463070 [RX_INPUT] configuration <<<<<
2231 14:44:20.463123 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2232 14:44:20.463175 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2233 14:44:20.463228 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2234 14:44:20.463281 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2235 14:44:20.463362 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2236 14:44:20.463415 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2237 14:44:20.463467 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2238 14:44:20.463519 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2239 14:44:20.463572 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2240 14:44:20.463624 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2241 14:44:20.463676 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2242 14:44:20.463728 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2243 14:44:20.463781 ===================================
2244 14:44:20.463833 LPDDR4 DRAM CONFIGURATION
2245 14:44:20.463885 ===================================
2246 14:44:20.463938 EX_ROW_EN[0] = 0x0
2247 14:44:20.463990 EX_ROW_EN[1] = 0x0
2248 14:44:20.464042 LP4Y_EN = 0x0
2249 14:44:20.464093 WORK_FSP = 0x0
2250 14:44:20.464145 WL = 0x4
2251 14:44:20.464196 RL = 0x4
2252 14:44:20.464248 BL = 0x2
2253 14:44:20.464300 RPST = 0x0
2254 14:44:20.464352 RD_PRE = 0x0
2255 14:44:20.464434 WR_PRE = 0x1
2256 14:44:20.464514 WR_PST = 0x0
2257 14:44:20.464568 DBI_WR = 0x0
2258 14:44:20.464620 DBI_RD = 0x0
2259 14:44:20.464673 OTF = 0x1
2260 14:44:20.464726 ===================================
2261 14:44:20.464779 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2262 14:44:20.464831 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2263 14:44:20.464884 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2264 14:44:20.464967 ===================================
2265 14:44:20.465048 LPDDR4 DRAM CONFIGURATION
2266 14:44:20.465101 ===================================
2267 14:44:20.465167 EX_ROW_EN[0] = 0x10
2268 14:44:20.465220 EX_ROW_EN[1] = 0x0
2269 14:44:20.465298 LP4Y_EN = 0x0
2270 14:44:20.465352 WORK_FSP = 0x0
2271 14:44:20.465404 WL = 0x4
2272 14:44:20.465455 RL = 0x4
2273 14:44:20.465566 BL = 0x2
2274 14:44:20.465622 RPST = 0x0
2275 14:44:20.465675 RD_PRE = 0x0
2276 14:44:20.465727 WR_PRE = 0x1
2277 14:44:20.465779 WR_PST = 0x0
2278 14:44:20.465831 DBI_WR = 0x0
2279 14:44:20.465883 DBI_RD = 0x0
2280 14:44:20.465935 OTF = 0x1
2281 14:44:20.465987 ===================================
2282 14:44:20.466040 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2283 14:44:20.466093 ==
2284 14:44:20.466145 Dram Type= 6, Freq= 0, CH_0, rank 0
2285 14:44:20.466197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2286 14:44:20.466251 ==
2287 14:44:20.466303 [Duty_Offset_Calibration]
2288 14:44:20.466355 B0:2 B1:0 CA:4
2289 14:44:20.466407
2290 14:44:20.466459 [DutyScan_Calibration_Flow] k_type=0
2291 14:44:20.466511
2292 14:44:20.466563 ==CLK 0==
2293 14:44:20.466616 Final CLK duty delay cell = 0
2294 14:44:20.466668 [0] MAX Duty = 5156%(X100), DQS PI = 14
2295 14:44:20.466720 [0] MIN Duty = 4969%(X100), DQS PI = 8
2296 14:44:20.466772 [0] AVG Duty = 5062%(X100)
2297 14:44:20.466839
2298 14:44:20.466904 CH0 CLK Duty spec in!! Max-Min= 187%
2299 14:44:20.466956 [DutyScan_Calibration_Flow] ====Done====
2300 14:44:20.467008
2301 14:44:20.467059 [DutyScan_Calibration_Flow] k_type=1
2302 14:44:20.467110
2303 14:44:20.467161 ==DQS 0 ==
2304 14:44:20.467212 Final DQS duty delay cell = -4
2305 14:44:20.467264 [-4] MAX Duty = 4969%(X100), DQS PI = 14
2306 14:44:20.467316 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2307 14:44:20.467367 [-4] AVG Duty = 4922%(X100)
2308 14:44:20.467419
2309 14:44:20.467470 ==DQS 1 ==
2310 14:44:20.467522 Final DQS duty delay cell = 0
2311 14:44:20.467574 [0] MAX Duty = 5093%(X100), DQS PI = 50
2312 14:44:20.467650 [0] MIN Duty = 4969%(X100), DQS PI = 14
2313 14:44:20.467740 [0] AVG Duty = 5031%(X100)
2314 14:44:20.467794
2315 14:44:20.467846 CH0 DQS 0 Duty spec in!! Max-Min= 93%
2316 14:44:20.467898
2317 14:44:20.467950 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2318 14:44:20.468002 [DutyScan_Calibration_Flow] ====Done====
2319 14:44:20.468054
2320 14:44:20.468105 [DutyScan_Calibration_Flow] k_type=3
2321 14:44:20.468157
2322 14:44:20.468208 ==DQM 0 ==
2323 14:44:20.468259 Final DQM duty delay cell = 0
2324 14:44:20.468333 [0] MAX Duty = 5094%(X100), DQS PI = 20
2325 14:44:20.468387 [0] MIN Duty = 4844%(X100), DQS PI = 50
2326 14:44:20.468439 [0] AVG Duty = 4969%(X100)
2327 14:44:20.468491
2328 14:44:20.468542 ==DQM 1 ==
2329 14:44:20.468594 Final DQM duty delay cell = 0
2330 14:44:20.468646 [0] MAX Duty = 4969%(X100), DQS PI = 0
2331 14:44:20.468698 [0] MIN Duty = 4875%(X100), DQS PI = 20
2332 14:44:20.468750 [0] AVG Duty = 4922%(X100)
2333 14:44:20.468801
2334 14:44:20.468853 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2335 14:44:20.468905
2336 14:44:20.468975 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2337 14:44:20.469041 [DutyScan_Calibration_Flow] ====Done====
2338 14:44:20.469092
2339 14:44:20.469346 [DutyScan_Calibration_Flow] k_type=2
2340 14:44:20.469408
2341 14:44:20.469461 ==DQ 0 ==
2342 14:44:20.469514 Final DQ duty delay cell = 0
2343 14:44:20.469567 [0] MAX Duty = 5125%(X100), DQS PI = 16
2344 14:44:20.469619 [0] MIN Duty = 4938%(X100), DQS PI = 58
2345 14:44:20.469671 [0] AVG Duty = 5031%(X100)
2346 14:44:20.469723
2347 14:44:20.469775 ==DQ 1 ==
2348 14:44:20.469826 Final DQ duty delay cell = 0
2349 14:44:20.469879 [0] MAX Duty = 5156%(X100), DQS PI = 6
2350 14:44:20.469931 [0] MIN Duty = 4938%(X100), DQS PI = 14
2351 14:44:20.469984 [0] AVG Duty = 5047%(X100)
2352 14:44:20.470035
2353 14:44:20.470087 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2354 14:44:20.470140
2355 14:44:20.470191 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2356 14:44:20.470244 [DutyScan_Calibration_Flow] ====Done====
2357 14:44:20.470295 ==
2358 14:44:20.470348 Dram Type= 6, Freq= 0, CH_1, rank 0
2359 14:44:20.470429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2360 14:44:20.470482 ==
2361 14:44:20.470534 [Duty_Offset_Calibration]
2362 14:44:20.470585 B0:0 B1:-1 CA:3
2363 14:44:20.470638
2364 14:44:20.470689 [DutyScan_Calibration_Flow] k_type=0
2365 14:44:20.470741
2366 14:44:20.470792 ==CLK 0==
2367 14:44:20.470843 Final CLK duty delay cell = -4
2368 14:44:20.470895 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2369 14:44:20.470947 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2370 14:44:20.470999 [-4] AVG Duty = 4938%(X100)
2371 14:44:20.471050
2372 14:44:20.471103 CH1 CLK Duty spec in!! Max-Min= 124%
2373 14:44:20.471184 [DutyScan_Calibration_Flow] ====Done====
2374 14:44:20.471235
2375 14:44:20.471286 [DutyScan_Calibration_Flow] k_type=1
2376 14:44:20.471350
2377 14:44:20.471411 ==DQS 0 ==
2378 14:44:20.471463 Final DQS duty delay cell = 0
2379 14:44:20.471517 [0] MAX Duty = 5156%(X100), DQS PI = 18
2380 14:44:20.471569 [0] MIN Duty = 4907%(X100), DQS PI = 38
2381 14:44:20.471621 [0] AVG Duty = 5031%(X100)
2382 14:44:20.471672
2383 14:44:20.471723 ==DQS 1 ==
2384 14:44:20.471774 Final DQS duty delay cell = -4
2385 14:44:20.471826 [-4] MAX Duty = 5000%(X100), DQS PI = 32
2386 14:44:20.471885 [-4] MIN Duty = 4875%(X100), DQS PI = 2
2387 14:44:20.471951 [-4] AVG Duty = 4937%(X100)
2388 14:44:20.472004
2389 14:44:20.472056 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2390 14:44:20.472108
2391 14:44:20.472159 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2392 14:44:20.472211 [DutyScan_Calibration_Flow] ====Done====
2393 14:44:20.472262
2394 14:44:20.472314 [DutyScan_Calibration_Flow] k_type=3
2395 14:44:20.472365
2396 14:44:20.472416 ==DQM 0 ==
2397 14:44:20.472467 Final DQM duty delay cell = 0
2398 14:44:20.472519 [0] MAX Duty = 5031%(X100), DQS PI = 28
2399 14:44:20.472571 [0] MIN Duty = 4782%(X100), DQS PI = 38
2400 14:44:20.472623 [0] AVG Duty = 4906%(X100)
2401 14:44:20.472674
2402 14:44:20.472726 ==DQM 1 ==
2403 14:44:20.472777 Final DQM duty delay cell = 4
2404 14:44:20.472829 [4] MAX Duty = 5187%(X100), DQS PI = 32
2405 14:44:20.472880 [4] MIN Duty = 5062%(X100), DQS PI = 18
2406 14:44:20.472932 [4] AVG Duty = 5124%(X100)
2407 14:44:20.472983
2408 14:44:20.473035 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2409 14:44:20.473086
2410 14:44:20.473137 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2411 14:44:20.473188 [DutyScan_Calibration_Flow] ====Done====
2412 14:44:20.473240
2413 14:44:20.473338 [DutyScan_Calibration_Flow] k_type=2
2414 14:44:20.473391
2415 14:44:20.473442 ==DQ 0 ==
2416 14:44:20.473494 Final DQ duty delay cell = -4
2417 14:44:20.473546 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2418 14:44:20.473598 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2419 14:44:20.473649 [-4] AVG Duty = 4937%(X100)
2420 14:44:20.473700
2421 14:44:20.473753 ==DQ 1 ==
2422 14:44:20.473805 Final DQ duty delay cell = 0
2423 14:44:20.473857 [0] MAX Duty = 5031%(X100), DQS PI = 34
2424 14:44:20.473909 [0] MIN Duty = 4844%(X100), DQS PI = 62
2425 14:44:20.473961 [0] AVG Duty = 4937%(X100)
2426 14:44:20.474012
2427 14:44:20.474063 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2428 14:44:20.474115
2429 14:44:20.474167 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2430 14:44:20.474219 [DutyScan_Calibration_Flow] ====Done====
2431 14:44:20.474270 nWR fixed to 30
2432 14:44:20.474322 [ModeRegInit_LP4] CH0 RK0
2433 14:44:20.474374 [ModeRegInit_LP4] CH0 RK1
2434 14:44:20.474425 [ModeRegInit_LP4] CH1 RK0
2435 14:44:20.474476 [ModeRegInit_LP4] CH1 RK1
2436 14:44:20.474527 match AC timing 7
2437 14:44:20.474578 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2438 14:44:20.474631 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2439 14:44:20.474683 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2440 14:44:20.474734 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2441 14:44:20.474786 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2442 14:44:20.474837 ==
2443 14:44:20.474889 Dram Type= 6, Freq= 0, CH_0, rank 0
2444 14:44:20.474941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2445 14:44:20.474992 ==
2446 14:44:20.475044 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2447 14:44:20.475096 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2448 14:44:20.475158 [CA 0] Center 39 (9~70) winsize 62
2449 14:44:20.475241 [CA 1] Center 39 (9~69) winsize 61
2450 14:44:20.475308 [CA 2] Center 35 (5~66) winsize 62
2451 14:44:20.475360 [CA 3] Center 35 (5~66) winsize 62
2452 14:44:20.475412 [CA 4] Center 34 (3~65) winsize 63
2453 14:44:20.475463 [CA 5] Center 33 (3~63) winsize 61
2454 14:44:20.475514
2455 14:44:20.475565 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2456 14:44:20.475617
2457 14:44:20.475668 [CATrainingPosCal] consider 1 rank data
2458 14:44:20.475720 u2DelayCellTimex100 = 270/100 ps
2459 14:44:20.475787 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2460 14:44:20.475854 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2461 14:44:20.475907 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2462 14:44:20.475960 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2463 14:44:20.476012 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2464 14:44:20.476079 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2465 14:44:20.476145
2466 14:44:20.476195 CA PerBit enable=1, Macro0, CA PI delay=33
2467 14:44:20.476247
2468 14:44:20.476298 [CBTSetCACLKResult] CA Dly = 33
2469 14:44:20.476350 CS Dly: 7 (0~38)
2470 14:44:20.476401 ==
2471 14:44:20.476453 Dram Type= 6, Freq= 0, CH_0, rank 1
2472 14:44:20.476505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2473 14:44:20.476557 ==
2474 14:44:20.476609 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2475 14:44:20.476660 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2476 14:44:20.476712 [CA 0] Center 39 (9~70) winsize 62
2477 14:44:20.476763 [CA 1] Center 39 (9~70) winsize 62
2478 14:44:20.476815 [CA 2] Center 35 (5~66) winsize 62
2479 14:44:20.476867 [CA 3] Center 35 (5~66) winsize 62
2480 14:44:20.476939 [CA 4] Center 34 (3~65) winsize 63
2481 14:44:20.476993 [CA 5] Center 33 (3~63) winsize 61
2482 14:44:20.477044
2483 14:44:20.477344 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2484 14:44:20.477406
2485 14:44:20.477459 [CATrainingPosCal] consider 2 rank data
2486 14:44:20.477512 u2DelayCellTimex100 = 270/100 ps
2487 14:44:20.477564 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2488 14:44:20.477617 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2489 14:44:20.477670 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2490 14:44:20.477738 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2491 14:44:20.477803 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2492 14:44:20.477855 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2493 14:44:20.477907
2494 14:44:20.477958 CA PerBit enable=1, Macro0, CA PI delay=33
2495 14:44:20.478010
2496 14:44:20.478062 [CBTSetCACLKResult] CA Dly = 33
2497 14:44:20.478114 CS Dly: 8 (0~41)
2498 14:44:20.478165
2499 14:44:20.478234 ----->DramcWriteLeveling(PI) begin...
2500 14:44:20.478301 ==
2501 14:44:20.478354 Dram Type= 6, Freq= 0, CH_0, rank 0
2502 14:44:20.478427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2503 14:44:20.478484 ==
2504 14:44:20.478537 Write leveling (Byte 0): 31 => 31
2505 14:44:20.478590 Write leveling (Byte 1): 27 => 27
2506 14:44:20.478642 DramcWriteLeveling(PI) end<-----
2507 14:44:20.478694
2508 14:44:20.478745 ==
2509 14:44:20.478798 Dram Type= 6, Freq= 0, CH_0, rank 0
2510 14:44:20.478850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2511 14:44:20.478902 ==
2512 14:44:20.478953 [Gating] SW mode calibration
2513 14:44:20.479005 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2514 14:44:20.479058 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2515 14:44:20.479110 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2516 14:44:20.479163 0 15 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
2517 14:44:20.479215 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 14:44:20.479267 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 14:44:20.479319 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 14:44:20.479371 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 14:44:20.479422 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2522 14:44:20.479474 0 15 28 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 0)
2523 14:44:20.479526 1 0 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
2524 14:44:20.479578 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 14:44:20.479629 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 14:44:20.479681 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 14:44:20.479732 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 14:44:20.479784 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 14:44:20.479836 1 0 24 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
2530 14:44:20.479888 1 0 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
2531 14:44:20.479939 1 1 0 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
2532 14:44:20.479990 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 14:44:20.480042 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 14:44:20.480094 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 14:44:20.480146 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 14:44:20.480198 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 14:44:20.480250 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 14:44:20.480302 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2539 14:44:20.480355 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2540 14:44:20.480407 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 14:44:20.480458 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 14:44:20.480510 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 14:44:20.480562 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 14:44:20.480613 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 14:44:20.480665 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 14:44:20.480716 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 14:44:20.480768 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 14:44:20.480819 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 14:44:20.480871 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 14:44:20.480923 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 14:44:20.481004 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 14:44:20.481056 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 14:44:20.481108 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2554 14:44:20.481201 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2555 14:44:20.481316 Total UI for P1: 0, mck2ui 16
2556 14:44:20.481372 best dqsien dly found for B0: ( 1, 3, 24)
2557 14:44:20.481425 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2558 14:44:20.481477 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 14:44:20.481530 Total UI for P1: 0, mck2ui 16
2560 14:44:20.481582 best dqsien dly found for B1: ( 1, 4, 0)
2561 14:44:20.481633 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2562 14:44:20.481685 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2563 14:44:20.481736
2564 14:44:20.481787 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2565 14:44:20.481839 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2566 14:44:20.481891 [Gating] SW calibration Done
2567 14:44:20.481942 ==
2568 14:44:20.481994 Dram Type= 6, Freq= 0, CH_0, rank 0
2569 14:44:20.482047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2570 14:44:20.482099 ==
2571 14:44:20.482150 RX Vref Scan: 0
2572 14:44:20.482202
2573 14:44:20.482254 RX Vref 0 -> 0, step: 1
2574 14:44:20.482306
2575 14:44:20.482358 RX Delay -40 -> 252, step: 8
2576 14:44:20.482409 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2577 14:44:20.482460 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2578 14:44:20.482512 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2579 14:44:20.482564 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2580 14:44:20.482615 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2581 14:44:20.482666 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2582 14:44:20.482717 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2583 14:44:20.482769 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
2584 14:44:20.482821 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2585 14:44:20.482872 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
2586 14:44:20.483130 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2587 14:44:20.483223 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2588 14:44:20.483277 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2589 14:44:20.483329 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2590 14:44:20.483381 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2591 14:44:20.483432 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2592 14:44:20.483483 ==
2593 14:44:20.483535 Dram Type= 6, Freq= 0, CH_0, rank 0
2594 14:44:20.483587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2595 14:44:20.483638 ==
2596 14:44:20.483690 DQS Delay:
2597 14:44:20.483742 DQS0 = 0, DQS1 = 0
2598 14:44:20.483794 DQM Delay:
2599 14:44:20.483846 DQM0 = 119, DQM1 = 106
2600 14:44:20.483897 DQ Delay:
2601 14:44:20.483949 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2602 14:44:20.484001 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2603 14:44:20.484052 DQ8 =95, DQ9 =91, DQ10 =107, DQ11 =103
2604 14:44:20.484104 DQ12 =119, DQ13 =111, DQ14 =115, DQ15 =111
2605 14:44:20.484155
2606 14:44:20.484207
2607 14:44:20.484258 ==
2608 14:44:20.484310 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 14:44:20.484361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 14:44:20.484435 ==
2611 14:44:20.484490
2612 14:44:20.484542
2613 14:44:20.484595 TX Vref Scan disable
2614 14:44:20.484646 == TX Byte 0 ==
2615 14:44:20.484698 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2616 14:44:20.484750 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2617 14:44:20.484826 == TX Byte 1 ==
2618 14:44:20.484893 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2619 14:44:20.484945 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2620 14:44:20.484996 ==
2621 14:44:20.485047 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 14:44:20.485098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 14:44:20.485150 ==
2624 14:44:20.485215 TX Vref=22, minBit 5, minWin=24, winSum=410
2625 14:44:20.485302 TX Vref=24, minBit 13, minWin=25, winSum=419
2626 14:44:20.485359 TX Vref=26, minBit 1, minWin=26, winSum=426
2627 14:44:20.485412 TX Vref=28, minBit 1, minWin=26, winSum=428
2628 14:44:20.485464 TX Vref=30, minBit 5, minWin=26, winSum=430
2629 14:44:20.485516 TX Vref=32, minBit 5, minWin=26, winSum=428
2630 14:44:20.485568 [TxChooseVref] Worse bit 5, Min win 26, Win sum 430, Final Vref 30
2631 14:44:20.485621
2632 14:44:20.485673 Final TX Range 1 Vref 30
2633 14:44:20.485725
2634 14:44:20.485775 ==
2635 14:44:20.485826 Dram Type= 6, Freq= 0, CH_0, rank 0
2636 14:44:20.485878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2637 14:44:20.485946 ==
2638 14:44:20.486011
2639 14:44:20.486062
2640 14:44:20.486113 TX Vref Scan disable
2641 14:44:20.486165 == TX Byte 0 ==
2642 14:44:20.486217 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2643 14:44:20.486268 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2644 14:44:20.486320 == TX Byte 1 ==
2645 14:44:20.486371 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2646 14:44:20.486423 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2647 14:44:20.486474
2648 14:44:20.486525 [DATLAT]
2649 14:44:20.486576 Freq=1200, CH0 RK0
2650 14:44:20.486628
2651 14:44:20.486679 DATLAT Default: 0xd
2652 14:44:20.486731 0, 0xFFFF, sum = 0
2653 14:44:20.486784 1, 0xFFFF, sum = 0
2654 14:44:20.486838 2, 0xFFFF, sum = 0
2655 14:44:20.486891 3, 0xFFFF, sum = 0
2656 14:44:20.486943 4, 0xFFFF, sum = 0
2657 14:44:20.486996 5, 0xFFFF, sum = 0
2658 14:44:20.487048 6, 0xFFFF, sum = 0
2659 14:44:20.487101 7, 0xFFFF, sum = 0
2660 14:44:20.487153 8, 0xFFFF, sum = 0
2661 14:44:20.487205 9, 0xFFFF, sum = 0
2662 14:44:20.487258 10, 0xFFFF, sum = 0
2663 14:44:20.487310 11, 0xFFFF, sum = 0
2664 14:44:20.487362 12, 0x0, sum = 1
2665 14:44:20.487415 13, 0x0, sum = 2
2666 14:44:20.487467 14, 0x0, sum = 3
2667 14:44:20.487519 15, 0x0, sum = 4
2668 14:44:20.487571 best_step = 13
2669 14:44:20.487623
2670 14:44:20.487674 ==
2671 14:44:20.487726 Dram Type= 6, Freq= 0, CH_0, rank 0
2672 14:44:20.487778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2673 14:44:20.487858 ==
2674 14:44:20.487913 RX Vref Scan: 1
2675 14:44:20.487965
2676 14:44:20.488017 Set Vref Range= 32 -> 127
2677 14:44:20.488069
2678 14:44:20.488120 RX Vref 32 -> 127, step: 1
2679 14:44:20.488172
2680 14:44:20.488224 RX Delay -29 -> 252, step: 4
2681 14:44:20.488275
2682 14:44:20.488327 Set Vref, RX VrefLevel [Byte0]: 32
2683 14:44:20.488378 [Byte1]: 32
2684 14:44:20.488430
2685 14:44:20.488481 Set Vref, RX VrefLevel [Byte0]: 33
2686 14:44:20.488533 [Byte1]: 33
2687 14:44:20.488585
2688 14:44:20.488636 Set Vref, RX VrefLevel [Byte0]: 34
2689 14:44:20.488688 [Byte1]: 34
2690 14:44:20.488740
2691 14:44:20.488791 Set Vref, RX VrefLevel [Byte0]: 35
2692 14:44:20.488844 [Byte1]: 35
2693 14:44:20.488895
2694 14:44:20.488946 Set Vref, RX VrefLevel [Byte0]: 36
2695 14:44:20.488999 [Byte1]: 36
2696 14:44:20.489050
2697 14:44:20.489102 Set Vref, RX VrefLevel [Byte0]: 37
2698 14:44:20.489153 [Byte1]: 37
2699 14:44:20.489206
2700 14:44:20.489269 Set Vref, RX VrefLevel [Byte0]: 38
2701 14:44:20.489355 [Byte1]: 38
2702 14:44:20.489408
2703 14:44:20.489459 Set Vref, RX VrefLevel [Byte0]: 39
2704 14:44:20.489511 [Byte1]: 39
2705 14:44:20.489563
2706 14:44:20.489614 Set Vref, RX VrefLevel [Byte0]: 40
2707 14:44:20.489665 [Byte1]: 40
2708 14:44:20.489717
2709 14:44:20.489769 Set Vref, RX VrefLevel [Byte0]: 41
2710 14:44:20.489821 [Byte1]: 41
2711 14:44:20.489873
2712 14:44:20.489925 Set Vref, RX VrefLevel [Byte0]: 42
2713 14:44:20.489977 [Byte1]: 42
2714 14:44:20.490028
2715 14:44:20.490079 Set Vref, RX VrefLevel [Byte0]: 43
2716 14:44:20.490131 [Byte1]: 43
2717 14:44:20.490182
2718 14:44:20.490234 Set Vref, RX VrefLevel [Byte0]: 44
2719 14:44:20.490286 [Byte1]: 44
2720 14:44:20.490337
2721 14:44:20.490388 Set Vref, RX VrefLevel [Byte0]: 45
2722 14:44:20.490440 [Byte1]: 45
2723 14:44:20.490491
2724 14:44:20.490542 Set Vref, RX VrefLevel [Byte0]: 46
2725 14:44:20.490594 [Byte1]: 46
2726 14:44:20.490646
2727 14:44:20.490697 Set Vref, RX VrefLevel [Byte0]: 47
2728 14:44:20.490748 [Byte1]: 47
2729 14:44:20.490800
2730 14:44:20.490851 Set Vref, RX VrefLevel [Byte0]: 48
2731 14:44:20.490902 [Byte1]: 48
2732 14:44:20.490954
2733 14:44:20.491005 Set Vref, RX VrefLevel [Byte0]: 49
2734 14:44:20.491056 [Byte1]: 49
2735 14:44:20.491108
2736 14:44:20.491159 Set Vref, RX VrefLevel [Byte0]: 50
2737 14:44:20.491211 [Byte1]: 50
2738 14:44:20.491285
2739 14:44:20.491340 Set Vref, RX VrefLevel [Byte0]: 51
2740 14:44:20.491393 [Byte1]: 51
2741 14:44:20.491446
2742 14:44:20.491498 Set Vref, RX VrefLevel [Byte0]: 52
2743 14:44:20.491550 [Byte1]: 52
2744 14:44:20.491603
2745 14:44:20.491654 Set Vref, RX VrefLevel [Byte0]: 53
2746 14:44:20.491706 [Byte1]: 53
2747 14:44:20.491757
2748 14:44:20.491809 Set Vref, RX VrefLevel [Byte0]: 54
2749 14:44:20.491861 [Byte1]: 54
2750 14:44:20.491913
2751 14:44:20.492177 Set Vref, RX VrefLevel [Byte0]: 55
2752 14:44:20.492238 [Byte1]: 55
2753 14:44:20.492292
2754 14:44:20.492345 Set Vref, RX VrefLevel [Byte0]: 56
2755 14:44:20.492427 [Byte1]: 56
2756 14:44:20.492479
2757 14:44:20.492531 Set Vref, RX VrefLevel [Byte0]: 57
2758 14:44:20.492583 [Byte1]: 57
2759 14:44:20.492635
2760 14:44:20.492686 Set Vref, RX VrefLevel [Byte0]: 58
2761 14:44:20.492738 [Byte1]: 58
2762 14:44:20.492790
2763 14:44:20.492841 Set Vref, RX VrefLevel [Byte0]: 59
2764 14:44:20.492892 [Byte1]: 59
2765 14:44:20.492944
2766 14:44:20.492995 Set Vref, RX VrefLevel [Byte0]: 60
2767 14:44:20.493046 [Byte1]: 60
2768 14:44:20.493097
2769 14:44:20.493148 Set Vref, RX VrefLevel [Byte0]: 61
2770 14:44:20.493200 [Byte1]: 61
2771 14:44:20.493251
2772 14:44:20.493347 Set Vref, RX VrefLevel [Byte0]: 62
2773 14:44:20.493399 [Byte1]: 62
2774 14:44:20.493450
2775 14:44:20.493501 Set Vref, RX VrefLevel [Byte0]: 63
2776 14:44:20.493553 [Byte1]: 63
2777 14:44:20.493604
2778 14:44:20.493656 Set Vref, RX VrefLevel [Byte0]: 64
2779 14:44:20.493708 [Byte1]: 64
2780 14:44:20.493759
2781 14:44:20.493810 Set Vref, RX VrefLevel [Byte0]: 65
2782 14:44:20.493862 [Byte1]: 65
2783 14:44:20.493914
2784 14:44:20.493966 Set Vref, RX VrefLevel [Byte0]: 66
2785 14:44:20.494017 [Byte1]: 66
2786 14:44:20.494069
2787 14:44:20.494120 Set Vref, RX VrefLevel [Byte0]: 67
2788 14:44:20.494171 [Byte1]: 67
2789 14:44:20.494222
2790 14:44:20.494273 Set Vref, RX VrefLevel [Byte0]: 68
2791 14:44:20.494325 [Byte1]: 68
2792 14:44:20.494377
2793 14:44:20.494429 Final RX Vref Byte 0 = 55 to rank0
2794 14:44:20.494481 Final RX Vref Byte 1 = 52 to rank0
2795 14:44:20.494534 Final RX Vref Byte 0 = 55 to rank1
2796 14:44:20.494587 Final RX Vref Byte 1 = 52 to rank1==
2797 14:44:20.494664 Dram Type= 6, Freq= 0, CH_0, rank 0
2798 14:44:20.494718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2799 14:44:20.494772 ==
2800 14:44:20.494824 DQS Delay:
2801 14:44:20.494876 DQS0 = 0, DQS1 = 0
2802 14:44:20.494928 DQM Delay:
2803 14:44:20.494979 DQM0 = 119, DQM1 = 105
2804 14:44:20.495032 DQ Delay:
2805 14:44:20.495084 DQ0 =120, DQ1 =118, DQ2 =116, DQ3 =116
2806 14:44:20.495136 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =122
2807 14:44:20.495187 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2808 14:44:20.495238 DQ12 =116, DQ13 =110, DQ14 =116, DQ15 =114
2809 14:44:20.495290
2810 14:44:20.495342
2811 14:44:20.495393 [DQSOSCAuto] RK0, (LSB)MR18= 0x2fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
2812 14:44:20.495446 CH0 RK0: MR19=403, MR18=2FE
2813 14:44:20.495498 CH0_RK0: MR19=0x403, MR18=0x2FE, DQSOSC=409, MR23=63, INC=39, DEC=26
2814 14:44:20.495551
2815 14:44:20.495602 ----->DramcWriteLeveling(PI) begin...
2816 14:44:20.495655 ==
2817 14:44:20.495708 Dram Type= 6, Freq= 0, CH_0, rank 1
2818 14:44:20.495760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2819 14:44:20.495813 ==
2820 14:44:20.495864 Write leveling (Byte 0): 32 => 32
2821 14:44:20.495916 Write leveling (Byte 1): 25 => 25
2822 14:44:20.495968 DramcWriteLeveling(PI) end<-----
2823 14:44:20.496019
2824 14:44:20.496072 ==
2825 14:44:20.496123 Dram Type= 6, Freq= 0, CH_0, rank 1
2826 14:44:20.496175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2827 14:44:20.496228 ==
2828 14:44:20.496280 [Gating] SW mode calibration
2829 14:44:20.496332 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2830 14:44:20.496384 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2831 14:44:20.496437 0 15 0 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
2832 14:44:20.496489 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2833 14:44:20.496541 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2834 14:44:20.496592 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2835 14:44:20.496644 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 14:44:20.496726 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2837 14:44:20.496778 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2838 14:44:20.496828 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2839 14:44:20.496880 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
2840 14:44:20.496932 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2841 14:44:20.496984 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 14:44:20.497035 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 14:44:20.497087 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 14:44:20.497139 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 14:44:20.497190 1 0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2846 14:44:20.497241 1 0 28 | B1->B0 | 2d2c 4646 | 1 0 | (0 0) (0 0)
2847 14:44:20.497338 1 1 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2848 14:44:20.497391 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2849 14:44:20.497443 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 14:44:20.497495 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 14:44:20.497546 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 14:44:20.497624 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 14:44:20.497678 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2854 14:44:20.497730 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2855 14:44:20.497782 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2856 14:44:20.497834 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 14:44:20.497885 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 14:44:20.497937 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 14:44:20.497990 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 14:44:20.498043 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 14:44:20.498095 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 14:44:20.498146 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 14:44:20.498198 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 14:44:20.498250 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 14:44:20.498301 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 14:44:20.498353 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 14:44:20.498613 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 14:44:20.498673 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 14:44:20.498727 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2870 14:44:20.498779 Total UI for P1: 0, mck2ui 16
2871 14:44:20.498832 best dqsien dly found for B0: ( 1, 3, 22)
2872 14:44:20.498884 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2873 14:44:20.498936 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2874 14:44:20.498988 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 14:44:20.499039 Total UI for P1: 0, mck2ui 16
2876 14:44:20.499092 best dqsien dly found for B1: ( 1, 3, 30)
2877 14:44:20.499144 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
2878 14:44:20.499196 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2879 14:44:20.499248
2880 14:44:20.499299 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
2881 14:44:20.499351 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2882 14:44:20.499403 [Gating] SW calibration Done
2883 14:44:20.499455 ==
2884 14:44:20.499507 Dram Type= 6, Freq= 0, CH_0, rank 1
2885 14:44:20.499559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2886 14:44:20.499611 ==
2887 14:44:20.499663 RX Vref Scan: 0
2888 14:44:20.499714
2889 14:44:20.499766 RX Vref 0 -> 0, step: 1
2890 14:44:20.499818
2891 14:44:20.499869 RX Delay -40 -> 252, step: 8
2892 14:44:20.499921 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2893 14:44:20.499973 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2894 14:44:20.500025 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2895 14:44:20.500077 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2896 14:44:20.500130 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2897 14:44:20.500182 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2898 14:44:20.500234 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2899 14:44:20.500286 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2900 14:44:20.500337 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2901 14:44:20.500389 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2902 14:44:20.500441 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2903 14:44:20.500494 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2904 14:44:20.500546 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2905 14:44:20.500597 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2906 14:44:20.500649 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2907 14:44:20.500701 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2908 14:44:20.500753 ==
2909 14:44:20.500805 Dram Type= 6, Freq= 0, CH_0, rank 1
2910 14:44:20.500857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 14:44:20.500909 ==
2912 14:44:20.500960 DQS Delay:
2913 14:44:20.501011 DQS0 = 0, DQS1 = 0
2914 14:44:20.501063 DQM Delay:
2915 14:44:20.501115 DQM0 = 119, DQM1 = 107
2916 14:44:20.501167 DQ Delay:
2917 14:44:20.501278 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2918 14:44:20.501352 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2919 14:44:20.501404 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2920 14:44:20.501457 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2921 14:44:20.501508
2922 14:44:20.501560
2923 14:44:20.501611 ==
2924 14:44:20.501663 Dram Type= 6, Freq= 0, CH_0, rank 1
2925 14:44:20.501714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2926 14:44:20.501766 ==
2927 14:44:20.501818
2928 14:44:20.501869
2929 14:44:20.501920 TX Vref Scan disable
2930 14:44:20.501972 == TX Byte 0 ==
2931 14:44:20.502053 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2932 14:44:20.502106 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2933 14:44:20.502158 == TX Byte 1 ==
2934 14:44:20.502209 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2935 14:44:20.502260 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2936 14:44:20.630761 ==
2937 14:44:20.630924 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 14:44:20.631017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 14:44:20.631105 ==
2940 14:44:20.631191 TX Vref=22, minBit 15, minWin=25, winSum=420
2941 14:44:20.631277 TX Vref=24, minBit 13, minWin=25, winSum=423
2942 14:44:20.631361 TX Vref=26, minBit 1, minWin=26, winSum=424
2943 14:44:20.631445 TX Vref=28, minBit 2, minWin=26, winSum=431
2944 14:44:20.631528 TX Vref=30, minBit 10, minWin=26, winSum=433
2945 14:44:20.631611 TX Vref=32, minBit 4, minWin=26, winSum=430
2946 14:44:20.631694 [TxChooseVref] Worse bit 10, Min win 26, Win sum 433, Final Vref 30
2947 14:44:20.631776
2948 14:44:20.631857 Final TX Range 1 Vref 30
2949 14:44:20.631939
2950 14:44:20.632020 ==
2951 14:44:20.632101 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 14:44:20.632183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 14:44:20.632265 ==
2954 14:44:20.632346
2955 14:44:20.632426
2956 14:44:20.632511 TX Vref Scan disable
2957 14:44:20.632593 == TX Byte 0 ==
2958 14:44:20.632701 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2959 14:44:20.632783 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2960 14:44:20.632864 == TX Byte 1 ==
2961 14:44:20.632945 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2962 14:44:20.633026 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2963 14:44:20.633107
2964 14:44:20.633187 [DATLAT]
2965 14:44:20.633291 Freq=1200, CH0 RK1
2966 14:44:20.633389
2967 14:44:20.633470 DATLAT Default: 0xd
2968 14:44:20.633553 0, 0xFFFF, sum = 0
2969 14:44:20.633610 1, 0xFFFF, sum = 0
2970 14:44:20.633682 2, 0xFFFF, sum = 0
2971 14:44:20.633750 3, 0xFFFF, sum = 0
2972 14:44:20.633803 4, 0xFFFF, sum = 0
2973 14:44:20.633856 5, 0xFFFF, sum = 0
2974 14:44:20.633909 6, 0xFFFF, sum = 0
2975 14:44:20.633961 7, 0xFFFF, sum = 0
2976 14:44:20.634017 8, 0xFFFF, sum = 0
2977 14:44:20.634069 9, 0xFFFF, sum = 0
2978 14:44:20.634121 10, 0xFFFF, sum = 0
2979 14:44:20.634174 11, 0xFFFF, sum = 0
2980 14:44:20.634227 12, 0x0, sum = 1
2981 14:44:20.634279 13, 0x0, sum = 2
2982 14:44:20.634331 14, 0x0, sum = 3
2983 14:44:20.634399 15, 0x0, sum = 4
2984 14:44:20.634466 best_step = 13
2985 14:44:20.634518
2986 14:44:20.634569 ==
2987 14:44:20.634631 Dram Type= 6, Freq= 0, CH_0, rank 1
2988 14:44:20.634684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2989 14:44:20.634737 ==
2990 14:44:20.634789 RX Vref Scan: 0
2991 14:44:20.634841
2992 14:44:20.634892 RX Vref 0 -> 0, step: 1
2993 14:44:20.634944
2994 14:44:20.635012 RX Delay -21 -> 252, step: 4
2995 14:44:20.635079 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
2996 14:44:20.635131 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
2997 14:44:20.635196 iDelay=195, Bit 2, Center 114 (51 ~ 178) 128
2998 14:44:20.635249 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
2999 14:44:20.635301 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3000 14:44:20.635353 iDelay=195, Bit 5, Center 110 (47 ~ 174) 128
3001 14:44:20.635404 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3002 14:44:20.635456 iDelay=195, Bit 7, Center 124 (59 ~ 190) 132
3003 14:44:20.635572 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3004 14:44:20.635656 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3005 14:44:20.635941 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3006 14:44:20.636041 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3007 14:44:20.636147 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3008 14:44:20.636232 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3009 14:44:20.636285 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3010 14:44:20.636337 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3011 14:44:20.636388 ==
3012 14:44:20.636441 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 14:44:20.636523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 14:44:20.636621 ==
3015 14:44:20.636702 DQS Delay:
3016 14:44:20.636765 DQS0 = 0, DQS1 = 0
3017 14:44:20.636818 DQM Delay:
3018 14:44:20.636870 DQM0 = 117, DQM1 = 107
3019 14:44:20.636922 DQ Delay:
3020 14:44:20.636974 DQ0 =114, DQ1 =118, DQ2 =114, DQ3 =114
3021 14:44:20.637034 DQ4 =120, DQ5 =110, DQ6 =128, DQ7 =124
3022 14:44:20.637089 DQ8 =94, DQ9 =94, DQ10 =110, DQ11 =98
3023 14:44:20.637141 DQ12 =112, DQ13 =112, DQ14 =120, DQ15 =116
3024 14:44:20.637193
3025 14:44:20.637245
3026 14:44:20.637368 [DQSOSCAuto] RK1, (LSB)MR18= 0x1fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
3027 14:44:20.637422 CH0 RK1: MR19=403, MR18=1FE
3028 14:44:20.637475 CH0_RK1: MR19=0x403, MR18=0x1FE, DQSOSC=409, MR23=63, INC=39, DEC=26
3029 14:44:20.637564 [RxdqsGatingPostProcess] freq 1200
3030 14:44:20.637646 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3031 14:44:20.637728 best DQS0 dly(2T, 0.5T) = (0, 11)
3032 14:44:20.637806 best DQS1 dly(2T, 0.5T) = (0, 12)
3033 14:44:20.637861 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3034 14:44:20.637914 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3035 14:44:20.637967 best DQS0 dly(2T, 0.5T) = (0, 11)
3036 14:44:20.638019 best DQS1 dly(2T, 0.5T) = (0, 11)
3037 14:44:20.638122 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3038 14:44:20.638177 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3039 14:44:20.638230 Pre-setting of DQS Precalculation
3040 14:44:20.638282 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3041 14:44:20.638335 ==
3042 14:44:20.638388 Dram Type= 6, Freq= 0, CH_1, rank 0
3043 14:44:20.638441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 14:44:20.638494 ==
3045 14:44:20.638546 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3046 14:44:20.638599 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3047 14:44:20.638661 [CA 0] Center 38 (8~68) winsize 61
3048 14:44:20.638744 [CA 1] Center 37 (7~68) winsize 62
3049 14:44:20.638826 [CA 2] Center 35 (6~65) winsize 60
3050 14:44:20.638887 [CA 3] Center 34 (4~64) winsize 61
3051 14:44:20.638939 [CA 4] Center 34 (4~65) winsize 62
3052 14:44:20.638991 [CA 5] Center 33 (3~64) winsize 62
3053 14:44:20.639044
3054 14:44:20.639096 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3055 14:44:20.639226
3056 14:44:20.639323 [CATrainingPosCal] consider 1 rank data
3057 14:44:20.639443 u2DelayCellTimex100 = 270/100 ps
3058 14:44:20.639569 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3059 14:44:20.639665 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3060 14:44:20.639747 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3061 14:44:20.639828 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3062 14:44:20.639913 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3063 14:44:20.639996 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3064 14:44:20.640076
3065 14:44:20.640157 CA PerBit enable=1, Macro0, CA PI delay=33
3066 14:44:20.640237
3067 14:44:20.640318 [CBTSetCACLKResult] CA Dly = 33
3068 14:44:20.640398 CS Dly: 4 (0~35)
3069 14:44:20.640479 ==
3070 14:44:20.640560 Dram Type= 6, Freq= 0, CH_1, rank 1
3071 14:44:20.640642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3072 14:44:20.640723 ==
3073 14:44:20.640805 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3074 14:44:20.640887 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3075 14:44:20.640990 [CA 0] Center 37 (7~68) winsize 62
3076 14:44:20.641061 [CA 1] Center 38 (8~68) winsize 61
3077 14:44:20.641113 [CA 2] Center 35 (5~65) winsize 61
3078 14:44:20.641166 [CA 3] Center 33 (3~64) winsize 62
3079 14:44:20.641219 [CA 4] Center 34 (4~64) winsize 61
3080 14:44:20.641296 [CA 5] Center 33 (3~63) winsize 61
3081 14:44:20.641363
3082 14:44:20.641415 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3083 14:44:20.641467
3084 14:44:20.641519 [CATrainingPosCal] consider 2 rank data
3085 14:44:20.641571 u2DelayCellTimex100 = 270/100 ps
3086 14:44:20.641624 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3087 14:44:20.641676 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3088 14:44:20.641729 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3089 14:44:20.641782 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3090 14:44:20.641834 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3091 14:44:20.641886 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3092 14:44:20.641939
3093 14:44:20.641991 CA PerBit enable=1, Macro0, CA PI delay=33
3094 14:44:20.642044
3095 14:44:20.642096 [CBTSetCACLKResult] CA Dly = 33
3096 14:44:20.642148 CS Dly: 6 (0~39)
3097 14:44:20.642200
3098 14:44:20.642252 ----->DramcWriteLeveling(PI) begin...
3099 14:44:20.642305 ==
3100 14:44:20.642358 Dram Type= 6, Freq= 0, CH_1, rank 0
3101 14:44:20.642410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3102 14:44:20.642463 ==
3103 14:44:20.642515 Write leveling (Byte 0): 26 => 26
3104 14:44:20.642568 Write leveling (Byte 1): 26 => 26
3105 14:44:20.642620 DramcWriteLeveling(PI) end<-----
3106 14:44:20.642672
3107 14:44:20.642740 ==
3108 14:44:20.642805 Dram Type= 6, Freq= 0, CH_1, rank 0
3109 14:44:20.642857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3110 14:44:20.642910 ==
3111 14:44:20.642962 [Gating] SW mode calibration
3112 14:44:20.643014 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3113 14:44:20.643082 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3114 14:44:20.643137 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3115 14:44:20.643190 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3116 14:44:20.643243 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 14:44:20.643296 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 14:44:20.643349 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 14:44:20.643401 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 14:44:20.643453 0 15 24 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 0)
3121 14:44:20.643505 0 15 28 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
3122 14:44:20.643557 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3123 14:44:20.643831 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3124 14:44:20.643891 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 14:44:20.643945 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 14:44:20.643999 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 14:44:20.644086 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 14:44:20.644150 1 0 24 | B1->B0 | 2424 2e2e | 0 1 | (0 0) (0 0)
3129 14:44:20.644269 1 0 28 | B1->B0 | 4343 4545 | 1 0 | (0 0) (0 0)
3130 14:44:20.644353 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3131 14:44:20.644405 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 14:44:20.644458 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 14:44:20.644510 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 14:44:20.644563 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 14:44:20.644616 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 14:44:20.644668 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3137 14:44:20.644720 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3138 14:44:20.644772 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 14:44:20.644824 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 14:44:20.644876 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 14:44:20.644928 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 14:44:20.644981 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 14:44:20.645033 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 14:44:20.645085 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 14:44:20.645137 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 14:44:20.645211 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 14:44:20.645326 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 14:44:20.645381 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 14:44:20.645435 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 14:44:20.645487 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 14:44:20.645540 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 14:44:20.645592 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3153 14:44:20.645645 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 14:44:20.645697 Total UI for P1: 0, mck2ui 16
3155 14:44:20.645751 best dqsien dly found for B0: ( 1, 3, 24)
3156 14:44:20.645804 Total UI for P1: 0, mck2ui 16
3157 14:44:20.645877 best dqsien dly found for B1: ( 1, 3, 24)
3158 14:44:20.645976 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3159 14:44:20.646053 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3160 14:44:20.646139
3161 14:44:20.646206 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3162 14:44:20.646270 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3163 14:44:20.646323 [Gating] SW calibration Done
3164 14:44:20.646376 ==
3165 14:44:20.646429 Dram Type= 6, Freq= 0, CH_1, rank 0
3166 14:44:20.646482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3167 14:44:20.646535 ==
3168 14:44:20.646587 RX Vref Scan: 0
3169 14:44:20.646639
3170 14:44:20.646709 RX Vref 0 -> 0, step: 1
3171 14:44:20.646775
3172 14:44:20.646828 RX Delay -40 -> 252, step: 8
3173 14:44:20.646880 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3174 14:44:20.646932 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3175 14:44:20.646984 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3176 14:44:20.647037 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3177 14:44:20.647105 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3178 14:44:20.647171 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3179 14:44:20.647224 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3180 14:44:20.647277 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3181 14:44:20.647336 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3182 14:44:20.647389 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3183 14:44:20.647441 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3184 14:44:20.647494 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3185 14:44:20.647546 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3186 14:44:20.647637 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3187 14:44:20.647690 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3188 14:44:20.647742 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3189 14:44:20.647795 ==
3190 14:44:20.647847 Dram Type= 6, Freq= 0, CH_1, rank 0
3191 14:44:20.647899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 14:44:20.647952 ==
3193 14:44:20.648004 DQS Delay:
3194 14:44:20.648107 DQS0 = 0, DQS1 = 0
3195 14:44:20.648189 DQM Delay:
3196 14:44:20.648270 DQM0 = 116, DQM1 = 113
3197 14:44:20.648354 DQ Delay:
3198 14:44:20.648410 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3199 14:44:20.648464 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3200 14:44:20.648516 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3201 14:44:20.648569 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3202 14:44:20.648621
3203 14:44:20.648717
3204 14:44:20.648771 ==
3205 14:44:20.648823 Dram Type= 6, Freq= 0, CH_1, rank 0
3206 14:44:20.648876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3207 14:44:20.648928 ==
3208 14:44:20.648997
3209 14:44:20.649063
3210 14:44:20.649115 TX Vref Scan disable
3211 14:44:20.649167 == TX Byte 0 ==
3212 14:44:20.649220 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3213 14:44:20.649301 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3214 14:44:20.649385 == TX Byte 1 ==
3215 14:44:20.649474 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3216 14:44:20.649570 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3217 14:44:20.649659 ==
3218 14:44:20.649754 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 14:44:20.649812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 14:44:20.649866 ==
3221 14:44:20.649919 TX Vref=22, minBit 9, minWin=23, winSum=410
3222 14:44:20.649973 TX Vref=24, minBit 9, minWin=24, winSum=410
3223 14:44:20.650026 TX Vref=26, minBit 3, minWin=25, winSum=415
3224 14:44:20.650079 TX Vref=28, minBit 9, minWin=24, winSum=422
3225 14:44:20.650132 TX Vref=30, minBit 9, minWin=24, winSum=424
3226 14:44:20.650185 TX Vref=32, minBit 9, minWin=25, winSum=420
3227 14:44:20.650238 [TxChooseVref] Worse bit 9, Min win 25, Win sum 420, Final Vref 32
3228 14:44:20.650290
3229 14:44:20.650342 Final TX Range 1 Vref 32
3230 14:44:20.650395
3231 14:44:20.650447 ==
3232 14:44:20.650508 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 14:44:20.650561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 14:44:20.650623 ==
3235 14:44:20.650676
3236 14:44:20.650729
3237 14:44:20.650987 TX Vref Scan disable
3238 14:44:20.651048 == TX Byte 0 ==
3239 14:44:20.651104 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3240 14:44:20.651158 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3241 14:44:20.651211 == TX Byte 1 ==
3242 14:44:20.651263 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3243 14:44:20.651316 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3244 14:44:20.651400
3245 14:44:20.651480 [DATLAT]
3246 14:44:20.651554 Freq=1200, CH1 RK0
3247 14:44:20.651609
3248 14:44:20.651662 DATLAT Default: 0xd
3249 14:44:20.651714 0, 0xFFFF, sum = 0
3250 14:44:20.651768 1, 0xFFFF, sum = 0
3251 14:44:20.651831 2, 0xFFFF, sum = 0
3252 14:44:20.651886 3, 0xFFFF, sum = 0
3253 14:44:20.651939 4, 0xFFFF, sum = 0
3254 14:44:20.651992 5, 0xFFFF, sum = 0
3255 14:44:20.652076 6, 0xFFFF, sum = 0
3256 14:44:20.652129 7, 0xFFFF, sum = 0
3257 14:44:20.652211 8, 0xFFFF, sum = 0
3258 14:44:20.652264 9, 0xFFFF, sum = 0
3259 14:44:20.652352 10, 0xFFFF, sum = 0
3260 14:44:20.652451 11, 0xFFFF, sum = 0
3261 14:44:20.652534 12, 0x0, sum = 1
3262 14:44:20.652611 13, 0x0, sum = 2
3263 14:44:20.652667 14, 0x0, sum = 3
3264 14:44:20.652720 15, 0x0, sum = 4
3265 14:44:20.652772 best_step = 13
3266 14:44:20.652825
3267 14:44:20.652877 ==
3268 14:44:20.652930 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 14:44:20.652983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 14:44:20.653036 ==
3271 14:44:20.653088 RX Vref Scan: 1
3272 14:44:20.653141
3273 14:44:20.653192 Set Vref Range= 32 -> 127
3274 14:44:20.653244
3275 14:44:20.653339 RX Vref 32 -> 127, step: 1
3276 14:44:20.653393
3277 14:44:20.653445 RX Delay -13 -> 252, step: 4
3278 14:44:20.653497
3279 14:44:20.653549 Set Vref, RX VrefLevel [Byte0]: 32
3280 14:44:20.653602 [Byte1]: 32
3281 14:44:20.653654
3282 14:44:20.653705 Set Vref, RX VrefLevel [Byte0]: 33
3283 14:44:20.653757 [Byte1]: 33
3284 14:44:20.653810
3285 14:44:20.653862 Set Vref, RX VrefLevel [Byte0]: 34
3286 14:44:20.653914 [Byte1]: 34
3287 14:44:20.653966
3288 14:44:20.654038 Set Vref, RX VrefLevel [Byte0]: 35
3289 14:44:20.654098 [Byte1]: 35
3290 14:44:20.654152
3291 14:44:20.654218 Set Vref, RX VrefLevel [Byte0]: 36
3292 14:44:20.654271 [Byte1]: 36
3293 14:44:20.654323
3294 14:44:20.654375 Set Vref, RX VrefLevel [Byte0]: 37
3295 14:44:20.654427 [Byte1]: 37
3296 14:44:20.654479
3297 14:44:20.654531 Set Vref, RX VrefLevel [Byte0]: 38
3298 14:44:20.654583 [Byte1]: 38
3299 14:44:20.654655
3300 14:44:20.654772 Set Vref, RX VrefLevel [Byte0]: 39
3301 14:44:20.654838 [Byte1]: 39
3302 14:44:20.654890
3303 14:44:20.654941 Set Vref, RX VrefLevel [Byte0]: 40
3304 14:44:20.654993 [Byte1]: 40
3305 14:44:20.655045
3306 14:44:20.655096 Set Vref, RX VrefLevel [Byte0]: 41
3307 14:44:20.655148 [Byte1]: 41
3308 14:44:20.655207
3309 14:44:20.655259 Set Vref, RX VrefLevel [Byte0]: 42
3310 14:44:20.655311 [Byte1]: 42
3311 14:44:20.655362
3312 14:44:20.655414 Set Vref, RX VrefLevel [Byte0]: 43
3313 14:44:20.655465 [Byte1]: 43
3314 14:44:20.655516
3315 14:44:20.655596 Set Vref, RX VrefLevel [Byte0]: 44
3316 14:44:20.655648 [Byte1]: 44
3317 14:44:20.655734
3318 14:44:20.655787 Set Vref, RX VrefLevel [Byte0]: 45
3319 14:44:20.655839 [Byte1]: 45
3320 14:44:20.655891
3321 14:44:20.655942 Set Vref, RX VrefLevel [Byte0]: 46
3322 14:44:20.656017 [Byte1]: 46
3323 14:44:20.656084
3324 14:44:20.656135 Set Vref, RX VrefLevel [Byte0]: 47
3325 14:44:20.656187 [Byte1]: 47
3326 14:44:20.656238
3327 14:44:20.656290 Set Vref, RX VrefLevel [Byte0]: 48
3328 14:44:20.656355 [Byte1]: 48
3329 14:44:20.656409
3330 14:44:20.656461 Set Vref, RX VrefLevel [Byte0]: 49
3331 14:44:20.656512 [Byte1]: 49
3332 14:44:20.656564
3333 14:44:20.656616 Set Vref, RX VrefLevel [Byte0]: 50
3334 14:44:20.656668 [Byte1]: 50
3335 14:44:20.656719
3336 14:44:20.656776 Set Vref, RX VrefLevel [Byte0]: 51
3337 14:44:20.656875 [Byte1]: 51
3338 14:44:20.656928
3339 14:44:20.656980 Set Vref, RX VrefLevel [Byte0]: 52
3340 14:44:20.657032 [Byte1]: 52
3341 14:44:20.657084
3342 14:44:20.657135 Set Vref, RX VrefLevel [Byte0]: 53
3343 14:44:20.657187 [Byte1]: 53
3344 14:44:20.657238
3345 14:44:20.657314 Set Vref, RX VrefLevel [Byte0]: 54
3346 14:44:20.657380 [Byte1]: 54
3347 14:44:20.657432
3348 14:44:20.657483 Set Vref, RX VrefLevel [Byte0]: 55
3349 14:44:20.657535 [Byte1]: 55
3350 14:44:20.657587
3351 14:44:20.657639 Set Vref, RX VrefLevel [Byte0]: 56
3352 14:44:20.657690 [Byte1]: 56
3353 14:44:20.657742
3354 14:44:20.657793 Set Vref, RX VrefLevel [Byte0]: 57
3355 14:44:20.657845 [Byte1]: 57
3356 14:44:20.657897
3357 14:44:20.657948 Set Vref, RX VrefLevel [Byte0]: 58
3358 14:44:20.657999 [Byte1]: 58
3359 14:44:20.658068
3360 14:44:20.658166 Set Vref, RX VrefLevel [Byte0]: 59
3361 14:44:20.658249 [Byte1]: 59
3362 14:44:20.658300
3363 14:44:20.658352 Set Vref, RX VrefLevel [Byte0]: 60
3364 14:44:20.658403 [Byte1]: 60
3365 14:44:20.658454
3366 14:44:20.658505 Set Vref, RX VrefLevel [Byte0]: 61
3367 14:44:20.658557 [Byte1]: 61
3368 14:44:20.658609
3369 14:44:20.658660 Set Vref, RX VrefLevel [Byte0]: 62
3370 14:44:20.658711 [Byte1]: 62
3371 14:44:20.658763
3372 14:44:20.658814 Set Vref, RX VrefLevel [Byte0]: 63
3373 14:44:20.658882 [Byte1]: 63
3374 14:44:20.658965
3375 14:44:20.659029 Set Vref, RX VrefLevel [Byte0]: 64
3376 14:44:20.659112 [Byte1]: 64
3377 14:44:20.659163
3378 14:44:20.659214 Final RX Vref Byte 0 = 51 to rank0
3379 14:44:20.659307 Final RX Vref Byte 1 = 52 to rank0
3380 14:44:20.659361 Final RX Vref Byte 0 = 51 to rank1
3381 14:44:20.659413 Final RX Vref Byte 1 = 52 to rank1==
3382 14:44:20.659466 Dram Type= 6, Freq= 0, CH_1, rank 0
3383 14:44:20.659517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3384 14:44:20.659570 ==
3385 14:44:20.659621 DQS Delay:
3386 14:44:20.659673 DQS0 = 0, DQS1 = 0
3387 14:44:20.659725 DQM Delay:
3388 14:44:20.659776 DQM0 = 114, DQM1 = 112
3389 14:44:20.659828 DQ Delay:
3390 14:44:20.659880 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3391 14:44:20.659931 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3392 14:44:20.660007 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3393 14:44:20.660072 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =120
3394 14:44:20.660186
3395 14:44:20.660265
3396 14:44:20.660317 [DQSOSCAuto] RK0, (LSB)MR18= 0xf905, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 412 ps
3397 14:44:20.660370 CH1 RK0: MR19=304, MR18=F905
3398 14:44:20.660422 CH1_RK0: MR19=0x304, MR18=0xF905, DQSOSC=408, MR23=63, INC=39, DEC=26
3399 14:44:20.660475
3400 14:44:20.660526 ----->DramcWriteLeveling(PI) begin...
3401 14:44:20.660579 ==
3402 14:44:20.660835 Dram Type= 6, Freq= 0, CH_1, rank 1
3403 14:44:20.660896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3404 14:44:20.660949 ==
3405 14:44:20.661002 Write leveling (Byte 0): 26 => 26
3406 14:44:20.661055 Write leveling (Byte 1): 28 => 28
3407 14:44:20.661107 DramcWriteLeveling(PI) end<-----
3408 14:44:20.661158
3409 14:44:20.661211 ==
3410 14:44:20.661286 Dram Type= 6, Freq= 0, CH_1, rank 1
3411 14:44:20.661354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3412 14:44:20.661407 ==
3413 14:44:20.661459 [Gating] SW mode calibration
3414 14:44:20.661511 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3415 14:44:20.661587 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3416 14:44:20.661655 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3417 14:44:20.661707 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3418 14:44:20.661759 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3419 14:44:20.661812 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3420 14:44:20.661865 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3421 14:44:20.661917 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3422 14:44:20.661968 0 15 24 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
3423 14:44:20.662036 0 15 28 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
3424 14:44:20.662089 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3425 14:44:20.662155 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3426 14:44:20.662224 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3427 14:44:20.662289 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3428 14:44:20.662341 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3429 14:44:20.662393 1 0 20 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
3430 14:44:20.662460 1 0 24 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
3431 14:44:20.662542 1 0 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3432 14:44:20.662607 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3433 14:44:20.662659 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3434 14:44:20.662710 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3435 14:44:20.662761 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3436 14:44:20.662813 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3437 14:44:20.662864 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3438 14:44:20.662916 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3439 14:44:20.662967 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3440 14:44:20.663019 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3441 14:44:20.663071 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3442 14:44:20.663122 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3443 14:44:20.663174 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3444 14:44:20.663226 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3445 14:44:20.663277 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3446 14:44:20.663329 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3447 14:44:20.663381 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3448 14:44:20.663433 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3449 14:44:20.663484 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3450 14:44:20.663535 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 14:44:20.663587 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 14:44:20.663640 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 14:44:20.663692 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 14:44:20.663747 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3455 14:44:20.663804 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3456 14:44:20.663856 Total UI for P1: 0, mck2ui 16
3457 14:44:20.663909 best dqsien dly found for B0: ( 1, 3, 24)
3458 14:44:20.663961 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 14:44:20.664013 Total UI for P1: 0, mck2ui 16
3460 14:44:20.664065 best dqsien dly found for B1: ( 1, 3, 26)
3461 14:44:20.664116 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3462 14:44:20.664168 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3463 14:44:20.664220
3464 14:44:20.664274 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3465 14:44:20.664371 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3466 14:44:20.664424 [Gating] SW calibration Done
3467 14:44:20.664476 ==
3468 14:44:20.664527 Dram Type= 6, Freq= 0, CH_1, rank 1
3469 14:44:20.664580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3470 14:44:20.664632 ==
3471 14:44:20.664683 RX Vref Scan: 0
3472 14:44:20.664735
3473 14:44:20.664795 RX Vref 0 -> 0, step: 1
3474 14:44:20.664848
3475 14:44:20.664899 RX Delay -40 -> 252, step: 8
3476 14:44:20.664951 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3477 14:44:20.665003 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3478 14:44:20.665054 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3479 14:44:20.665106 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3480 14:44:20.665158 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3481 14:44:20.665209 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3482 14:44:20.665296 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3483 14:44:20.665352 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3484 14:44:20.665418 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3485 14:44:20.665470 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3486 14:44:20.665522 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3487 14:44:20.665574 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3488 14:44:20.665626 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3489 14:44:20.665678 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3490 14:44:20.665730 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3491 14:44:20.665782 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3492 14:44:20.665842 ==
3493 14:44:20.665895 Dram Type= 6, Freq= 0, CH_1, rank 1
3494 14:44:20.665947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3495 14:44:20.665999 ==
3496 14:44:20.666052 DQS Delay:
3497 14:44:20.666103 DQS0 = 0, DQS1 = 0
3498 14:44:20.666154 DQM Delay:
3499 14:44:20.666206 DQM0 = 114, DQM1 = 111
3500 14:44:20.666257 DQ Delay:
3501 14:44:20.666309 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3502 14:44:20.666361 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =111
3503 14:44:20.666413 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3504 14:44:20.666670 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3505 14:44:20.666734
3506 14:44:20.666787
3507 14:44:20.666839 ==
3508 14:44:20.666891 Dram Type= 6, Freq= 0, CH_1, rank 1
3509 14:44:20.666946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3510 14:44:20.667003 ==
3511 14:44:20.667055
3512 14:44:20.667107
3513 14:44:20.667158 TX Vref Scan disable
3514 14:44:20.667211 == TX Byte 0 ==
3515 14:44:20.667266 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3516 14:44:20.667353 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3517 14:44:20.667446 == TX Byte 1 ==
3518 14:44:20.667500 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3519 14:44:20.667553 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3520 14:44:20.667605 ==
3521 14:44:20.667657 Dram Type= 6, Freq= 0, CH_1, rank 1
3522 14:44:20.667710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3523 14:44:20.667762 ==
3524 14:44:20.667814 TX Vref=22, minBit 9, minWin=24, winSum=419
3525 14:44:20.667866 TX Vref=24, minBit 9, minWin=25, winSum=426
3526 14:44:20.667926 TX Vref=26, minBit 1, minWin=26, winSum=428
3527 14:44:20.667978 TX Vref=28, minBit 9, minWin=25, winSum=429
3528 14:44:20.668029 TX Vref=30, minBit 9, minWin=25, winSum=430
3529 14:44:20.668081 TX Vref=32, minBit 1, minWin=26, winSum=429
3530 14:44:20.668133 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 32
3531 14:44:20.668186
3532 14:44:20.668238 Final TX Range 1 Vref 32
3533 14:44:20.668290
3534 14:44:20.668341 ==
3535 14:44:20.668402 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 14:44:20.668455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 14:44:20.668507 ==
3538 14:44:20.668559
3539 14:44:20.668611
3540 14:44:20.668662 TX Vref Scan disable
3541 14:44:20.668714 == TX Byte 0 ==
3542 14:44:20.668766 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3543 14:44:20.668818 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3544 14:44:20.668879 == TX Byte 1 ==
3545 14:44:20.668931 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3546 14:44:20.668983 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3547 14:44:20.669035
3548 14:44:20.669086 [DATLAT]
3549 14:44:20.669152 Freq=1200, CH1 RK1
3550 14:44:20.669206
3551 14:44:20.669271 DATLAT Default: 0xd
3552 14:44:20.669345 0, 0xFFFF, sum = 0
3553 14:44:20.669400 1, 0xFFFF, sum = 0
3554 14:44:20.669454 2, 0xFFFF, sum = 0
3555 14:44:20.669506 3, 0xFFFF, sum = 0
3556 14:44:20.669560 4, 0xFFFF, sum = 0
3557 14:44:20.669612 5, 0xFFFF, sum = 0
3558 14:44:20.669665 6, 0xFFFF, sum = 0
3559 14:44:20.669734 7, 0xFFFF, sum = 0
3560 14:44:20.669799 8, 0xFFFF, sum = 0
3561 14:44:20.669890 9, 0xFFFF, sum = 0
3562 14:44:20.669958 10, 0xFFFF, sum = 0
3563 14:44:20.670011 11, 0xFFFF, sum = 0
3564 14:44:20.670064 12, 0x0, sum = 1
3565 14:44:20.670116 13, 0x0, sum = 2
3566 14:44:20.670169 14, 0x0, sum = 3
3567 14:44:20.670222 15, 0x0, sum = 4
3568 14:44:20.670274 best_step = 13
3569 14:44:20.670326
3570 14:44:20.670380 ==
3571 14:44:20.670434 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 14:44:20.670487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 14:44:20.670538 ==
3574 14:44:20.670590 RX Vref Scan: 0
3575 14:44:20.670642
3576 14:44:20.670694 RX Vref 0 -> 0, step: 1
3577 14:44:20.670745
3578 14:44:20.670796 RX Delay -13 -> 252, step: 4
3579 14:44:20.670890 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3580 14:44:20.670944 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3581 14:44:20.671043 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3582 14:44:20.671109 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3583 14:44:20.671161 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3584 14:44:20.671213 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3585 14:44:20.671265 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3586 14:44:20.671315 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3587 14:44:20.671367 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3588 14:44:20.671418 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3589 14:44:20.671470 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3590 14:44:20.671521 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3591 14:44:20.671572 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3592 14:44:20.671624 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3593 14:44:20.671706 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3594 14:44:20.671758 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3595 14:44:20.671809 ==
3596 14:44:20.671914 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 14:44:20.671983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 14:44:20.672035 ==
3599 14:44:20.672087 DQS Delay:
3600 14:44:20.672141 DQS0 = 0, DQS1 = 0
3601 14:44:20.672193 DQM Delay:
3602 14:44:20.672245 DQM0 = 114, DQM1 = 112
3603 14:44:20.672296 DQ Delay:
3604 14:44:20.672347 DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =112
3605 14:44:20.672399 DQ4 =112, DQ5 =124, DQ6 =122, DQ7 =112
3606 14:44:20.672450 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3607 14:44:20.672502 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =122
3608 14:44:20.672554
3609 14:44:20.672605
3610 14:44:20.672656 [DQSOSCAuto] RK1, (LSB)MR18= 0xf90b, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3611 14:44:20.672709 CH1 RK1: MR19=304, MR18=F90B
3612 14:44:20.672761 CH1_RK1: MR19=0x304, MR18=0xF90B, DQSOSC=405, MR23=63, INC=39, DEC=26
3613 14:44:20.672844 [RxdqsGatingPostProcess] freq 1200
3614 14:44:20.672897 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3615 14:44:20.672949 best DQS0 dly(2T, 0.5T) = (0, 11)
3616 14:44:20.673034 best DQS1 dly(2T, 0.5T) = (0, 11)
3617 14:44:20.673116 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3618 14:44:20.673197 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3619 14:44:20.673300 best DQS0 dly(2T, 0.5T) = (0, 11)
3620 14:44:20.673369 best DQS1 dly(2T, 0.5T) = (0, 11)
3621 14:44:20.673421 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3622 14:44:20.673473 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3623 14:44:20.673525 Pre-setting of DQS Precalculation
3624 14:44:20.673576 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3625 14:44:20.673628 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3626 14:44:20.673681 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3627 14:44:20.673733
3628 14:44:20.673784
3629 14:44:20.673835 [Calibration Summary] 2400 Mbps
3630 14:44:20.673887 CH 0, Rank 0
3631 14:44:20.673939 SW Impedance : PASS
3632 14:44:20.673991 DUTY Scan : NO K
3633 14:44:20.674052 ZQ Calibration : PASS
3634 14:44:20.674105 Jitter Meter : NO K
3635 14:44:20.674157 CBT Training : PASS
3636 14:44:20.674209 Write leveling : PASS
3637 14:44:20.674260 RX DQS gating : PASS
3638 14:44:20.674311 RX DQ/DQS(RDDQC) : PASS
3639 14:44:20.674363 TX DQ/DQS : PASS
3640 14:44:20.674415 RX DATLAT : PASS
3641 14:44:20.674467 RX DQ/DQS(Engine): PASS
3642 14:44:20.674518 TX OE : NO K
3643 14:44:20.674571 All Pass.
3644 14:44:20.674622
3645 14:44:20.674673 CH 0, Rank 1
3646 14:44:20.674724 SW Impedance : PASS
3647 14:44:20.674994 DUTY Scan : NO K
3648 14:44:20.675055 ZQ Calibration : PASS
3649 14:44:20.675117 Jitter Meter : NO K
3650 14:44:20.675171 CBT Training : PASS
3651 14:44:20.675222 Write leveling : PASS
3652 14:44:20.675275 RX DQS gating : PASS
3653 14:44:20.675357 RX DQ/DQS(RDDQC) : PASS
3654 14:44:20.675409 TX DQ/DQS : PASS
3655 14:44:20.675462 RX DATLAT : PASS
3656 14:44:20.675513 RX DQ/DQS(Engine): PASS
3657 14:44:20.675565 TX OE : NO K
3658 14:44:20.675640 All Pass.
3659 14:44:20.675708
3660 14:44:20.675760 CH 1, Rank 0
3661 14:44:20.675811 SW Impedance : PASS
3662 14:44:20.675862 DUTY Scan : NO K
3663 14:44:20.675913 ZQ Calibration : PASS
3664 14:44:20.675964 Jitter Meter : NO K
3665 14:44:20.676015 CBT Training : PASS
3666 14:44:20.676067 Write leveling : PASS
3667 14:44:20.676117 RX DQS gating : PASS
3668 14:44:20.676179 RX DQ/DQS(RDDQC) : PASS
3669 14:44:20.676232 TX DQ/DQS : PASS
3670 14:44:20.676285 RX DATLAT : PASS
3671 14:44:20.676336 RX DQ/DQS(Engine): PASS
3672 14:44:20.676388 TX OE : NO K
3673 14:44:20.676440 All Pass.
3674 14:44:20.676492
3675 14:44:20.676543 CH 1, Rank 1
3676 14:44:20.676594 SW Impedance : PASS
3677 14:44:20.676646 DUTY Scan : NO K
3678 14:44:20.676698 ZQ Calibration : PASS
3679 14:44:20.676750 Jitter Meter : NO K
3680 14:44:20.676800 CBT Training : PASS
3681 14:44:20.676851 Write leveling : PASS
3682 14:44:20.676903 RX DQS gating : PASS
3683 14:44:20.676954 RX DQ/DQS(RDDQC) : PASS
3684 14:44:20.677006 TX DQ/DQS : PASS
3685 14:44:20.677058 RX DATLAT : PASS
3686 14:44:20.677109 RX DQ/DQS(Engine): PASS
3687 14:44:20.677164 TX OE : NO K
3688 14:44:20.677264 All Pass.
3689 14:44:20.677335
3690 14:44:20.677387 DramC Write-DBI off
3691 14:44:20.677439 PER_BANK_REFRESH: Hybrid Mode
3692 14:44:20.677491 TX_TRACKING: ON
3693 14:44:20.677544 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3694 14:44:20.677597 [FAST_K] Save calibration result to emmc
3695 14:44:20.677649 dramc_set_vcore_voltage set vcore to 650000
3696 14:44:20.677701 Read voltage for 600, 5
3697 14:44:20.677753 Vio18 = 0
3698 14:44:20.677805 Vcore = 650000
3699 14:44:20.677857 Vdram = 0
3700 14:44:20.677907 Vddq = 0
3701 14:44:20.677958 Vmddr = 0
3702 14:44:20.678009 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3703 14:44:20.678062 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3704 14:44:20.678114 MEM_TYPE=3, freq_sel=19
3705 14:44:20.678165 sv_algorithm_assistance_LP4_1600
3706 14:44:20.678218 ============ PULL DRAM RESETB DOWN ============
3707 14:44:20.678270 ========== PULL DRAM RESETB DOWN end =========
3708 14:44:20.678322 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3709 14:44:20.678374 ===================================
3710 14:44:20.678426 LPDDR4 DRAM CONFIGURATION
3711 14:44:20.678476 ===================================
3712 14:44:20.678528 EX_ROW_EN[0] = 0x0
3713 14:44:20.678580 EX_ROW_EN[1] = 0x0
3714 14:44:20.678632 LP4Y_EN = 0x0
3715 14:44:20.678683 WORK_FSP = 0x0
3716 14:44:20.678735 WL = 0x2
3717 14:44:20.678786 RL = 0x2
3718 14:44:20.678837 BL = 0x2
3719 14:44:20.678888 RPST = 0x0
3720 14:44:20.678940 RD_PRE = 0x0
3721 14:44:20.678991 WR_PRE = 0x1
3722 14:44:20.679042 WR_PST = 0x0
3723 14:44:20.679093 DBI_WR = 0x0
3724 14:44:20.679145 DBI_RD = 0x0
3725 14:44:20.679196 OTF = 0x1
3726 14:44:20.679248 ===================================
3727 14:44:20.679305 ===================================
3728 14:44:20.679360 ANA top config
3729 14:44:20.679411 ===================================
3730 14:44:20.679463 DLL_ASYNC_EN = 0
3731 14:44:20.679515 ALL_SLAVE_EN = 1
3732 14:44:20.679567 NEW_RANK_MODE = 1
3733 14:44:20.679619 DLL_IDLE_MODE = 1
3734 14:44:20.679671 LP45_APHY_COMB_EN = 1
3735 14:44:20.679722 TX_ODT_DIS = 1
3736 14:44:20.679774 NEW_8X_MODE = 1
3737 14:44:20.679826 ===================================
3738 14:44:20.679879 ===================================
3739 14:44:20.679941 data_rate = 1200
3740 14:44:20.679993 CKR = 1
3741 14:44:20.680045 DQ_P2S_RATIO = 8
3742 14:44:20.680096 ===================================
3743 14:44:20.680148 CA_P2S_RATIO = 8
3744 14:44:20.680200 DQ_CA_OPEN = 0
3745 14:44:20.680251 DQ_SEMI_OPEN = 0
3746 14:44:20.680303 CA_SEMI_OPEN = 0
3747 14:44:20.680354 CA_FULL_RATE = 0
3748 14:44:20.680412 DQ_CKDIV4_EN = 1
3749 14:44:20.680465 CA_CKDIV4_EN = 1
3750 14:44:20.680517 CA_PREDIV_EN = 0
3751 14:44:20.680569 PH8_DLY = 0
3752 14:44:20.680620 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3753 14:44:20.680672 DQ_AAMCK_DIV = 4
3754 14:44:20.680723 CA_AAMCK_DIV = 4
3755 14:44:20.680775 CA_ADMCK_DIV = 4
3756 14:44:20.680827 DQ_TRACK_CA_EN = 0
3757 14:44:20.680878 CA_PICK = 600
3758 14:44:20.681001 CA_MCKIO = 600
3759 14:44:20.681053 MCKIO_SEMI = 0
3760 14:44:20.681105 PLL_FREQ = 2288
3761 14:44:20.681157 DQ_UI_PI_RATIO = 32
3762 14:44:20.681208 CA_UI_PI_RATIO = 0
3763 14:44:20.681265 ===================================
3764 14:44:20.681358 ===================================
3765 14:44:20.681412 memory_type:LPDDR4
3766 14:44:20.681464 GP_NUM : 10
3767 14:44:20.681515 SRAM_EN : 1
3768 14:44:20.681566 MD32_EN : 0
3769 14:44:20.681618 ===================================
3770 14:44:20.681670 [ANA_INIT] >>>>>>>>>>>>>>
3771 14:44:20.681721 <<<<<< [CONFIGURE PHASE]: ANA_TX
3772 14:44:20.681773 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3773 14:44:20.681826 ===================================
3774 14:44:20.681886 data_rate = 1200,PCW = 0X5800
3775 14:44:20.681938 ===================================
3776 14:44:20.681990 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3777 14:44:20.682044 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3778 14:44:20.682096 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3779 14:44:20.682149 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3780 14:44:20.682201 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3781 14:44:20.682253 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3782 14:44:20.682305 [ANA_INIT] flow start
3783 14:44:20.682365 [ANA_INIT] PLL >>>>>>>>
3784 14:44:20.682418 [ANA_INIT] PLL <<<<<<<<
3785 14:44:20.682469 [ANA_INIT] MIDPI >>>>>>>>
3786 14:44:20.682521 [ANA_INIT] MIDPI <<<<<<<<
3787 14:44:20.682573 [ANA_INIT] DLL >>>>>>>>
3788 14:44:20.682825 [ANA_INIT] flow end
3789 14:44:20.682894 ============ LP4 DIFF to SE enter ============
3790 14:44:20.682949 ============ LP4 DIFF to SE exit ============
3791 14:44:20.683002 [ANA_INIT] <<<<<<<<<<<<<
3792 14:44:20.683053 [Flow] Enable top DCM control >>>>>
3793 14:44:20.685304 [Flow] Enable top DCM control <<<<<
3794 14:44:20.688475 Enable DLL master slave shuffle
3795 14:44:20.695330 ==============================================================
3796 14:44:20.695447 Gating Mode config
3797 14:44:20.702008 ==============================================================
3798 14:44:20.702103 Config description:
3799 14:44:20.711672 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3800 14:44:20.718429 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3801 14:44:20.724917 SELPH_MODE 0: By rank 1: By Phase
3802 14:44:20.731409 ==============================================================
3803 14:44:20.731511 GAT_TRACK_EN = 1
3804 14:44:20.734798 RX_GATING_MODE = 2
3805 14:44:20.738461 RX_GATING_TRACK_MODE = 2
3806 14:44:20.741522 SELPH_MODE = 1
3807 14:44:20.745127 PICG_EARLY_EN = 1
3808 14:44:20.748351 VALID_LAT_VALUE = 1
3809 14:44:20.755186 ==============================================================
3810 14:44:20.758075 Enter into Gating configuration >>>>
3811 14:44:20.760832 Exit from Gating configuration <<<<
3812 14:44:20.764404 Enter into DVFS_PRE_config >>>>>
3813 14:44:20.773864 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3814 14:44:20.777248 Exit from DVFS_PRE_config <<<<<
3815 14:44:20.780742 Enter into PICG configuration >>>>
3816 14:44:20.784025 Exit from PICG configuration <<<<
3817 14:44:20.787504 [RX_INPUT] configuration >>>>>
3818 14:44:20.790424 [RX_INPUT] configuration <<<<<
3819 14:44:20.793934 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3820 14:44:20.800344 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3821 14:44:20.807076 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3822 14:44:20.814104 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3823 14:44:20.817570 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3824 14:44:20.823770 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3825 14:44:20.829935 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3826 14:44:20.833278 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3827 14:44:20.836679 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3828 14:44:20.840195 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3829 14:44:20.846412 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3830 14:44:20.849555 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3831 14:44:20.853021 ===================================
3832 14:44:20.856417 LPDDR4 DRAM CONFIGURATION
3833 14:44:20.859387 ===================================
3834 14:44:20.859484 EX_ROW_EN[0] = 0x0
3835 14:44:20.863228 EX_ROW_EN[1] = 0x0
3836 14:44:20.863321 LP4Y_EN = 0x0
3837 14:44:20.866662 WORK_FSP = 0x0
3838 14:44:20.866757 WL = 0x2
3839 14:44:20.870156 RL = 0x2
3840 14:44:20.870245 BL = 0x2
3841 14:44:20.872817 RPST = 0x0
3842 14:44:20.876140 RD_PRE = 0x0
3843 14:44:20.876236 WR_PRE = 0x1
3844 14:44:20.879454 WR_PST = 0x0
3845 14:44:20.879542 DBI_WR = 0x0
3846 14:44:20.882532 DBI_RD = 0x0
3847 14:44:20.882684 OTF = 0x1
3848 14:44:20.886073 ===================================
3849 14:44:20.889277 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3850 14:44:20.896341 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3851 14:44:20.899161 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3852 14:44:20.902148 ===================================
3853 14:44:20.906127 LPDDR4 DRAM CONFIGURATION
3854 14:44:20.909526 ===================================
3855 14:44:20.909621 EX_ROW_EN[0] = 0x10
3856 14:44:20.912396 EX_ROW_EN[1] = 0x0
3857 14:44:20.912482 LP4Y_EN = 0x0
3858 14:44:20.915699 WORK_FSP = 0x0
3859 14:44:20.915787 WL = 0x2
3860 14:44:20.919020 RL = 0x2
3861 14:44:20.919108 BL = 0x2
3862 14:44:20.922371 RPST = 0x0
3863 14:44:20.925442 RD_PRE = 0x0
3864 14:44:20.925531 WR_PRE = 0x1
3865 14:44:20.929130 WR_PST = 0x0
3866 14:44:20.929249 DBI_WR = 0x0
3867 14:44:20.932924 DBI_RD = 0x0
3868 14:44:20.933010 OTF = 0x1
3869 14:44:20.935632 ===================================
3870 14:44:20.942321 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3871 14:44:20.946211 nWR fixed to 30
3872 14:44:20.949581 [ModeRegInit_LP4] CH0 RK0
3873 14:44:20.949697 [ModeRegInit_LP4] CH0 RK1
3874 14:44:20.952500 [ModeRegInit_LP4] CH1 RK0
3875 14:44:20.956101 [ModeRegInit_LP4] CH1 RK1
3876 14:44:20.956192 match AC timing 17
3877 14:44:20.962400 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3878 14:44:20.966149 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3879 14:44:20.969956 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3880 14:44:20.975741 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3881 14:44:20.979342 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3882 14:44:20.979438 ==
3883 14:44:20.982737 Dram Type= 6, Freq= 0, CH_0, rank 0
3884 14:44:20.986214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3885 14:44:20.986302 ==
3886 14:44:20.992549 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3887 14:44:20.999000 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3888 14:44:21.002598 [CA 0] Center 36 (6~67) winsize 62
3889 14:44:21.005862 [CA 1] Center 36 (6~66) winsize 61
3890 14:44:21.008721 [CA 2] Center 34 (4~65) winsize 62
3891 14:44:21.012197 [CA 3] Center 34 (4~65) winsize 62
3892 14:44:21.015702 [CA 4] Center 33 (3~64) winsize 62
3893 14:44:21.018896 [CA 5] Center 33 (3~64) winsize 62
3894 14:44:21.018989
3895 14:44:21.022032 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3896 14:44:21.022117
3897 14:44:21.025621 [CATrainingPosCal] consider 1 rank data
3898 14:44:21.028915 u2DelayCellTimex100 = 270/100 ps
3899 14:44:21.032048 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3900 14:44:21.035160 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3901 14:44:21.038705 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3902 14:44:21.041720 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3903 14:44:21.048899 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3904 14:44:21.052332 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3905 14:44:21.052434
3906 14:44:21.055199 CA PerBit enable=1, Macro0, CA PI delay=33
3907 14:44:21.055282
3908 14:44:21.058418 [CBTSetCACLKResult] CA Dly = 33
3909 14:44:21.058504 CS Dly: 5 (0~36)
3910 14:44:21.058569 ==
3911 14:44:21.061567 Dram Type= 6, Freq= 0, CH_0, rank 1
3912 14:44:21.068162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3913 14:44:21.068258 ==
3914 14:44:21.072025 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3915 14:44:21.077983 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3916 14:44:21.081219 [CA 0] Center 36 (6~67) winsize 62
3917 14:44:21.084927 [CA 1] Center 36 (6~67) winsize 62
3918 14:44:21.087998 [CA 2] Center 34 (4~65) winsize 62
3919 14:44:21.091351 [CA 3] Center 34 (4~65) winsize 62
3920 14:44:21.094699 [CA 4] Center 34 (3~65) winsize 63
3921 14:44:21.098270 [CA 5] Center 34 (3~65) winsize 63
3922 14:44:21.098363
3923 14:44:21.100928 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3924 14:44:21.101012
3925 14:44:21.104762 [CATrainingPosCal] consider 2 rank data
3926 14:44:21.108267 u2DelayCellTimex100 = 270/100 ps
3927 14:44:21.111462 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3928 14:44:21.117735 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3929 14:44:21.121497 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3930 14:44:21.124282 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3931 14:44:21.127400 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3932 14:44:21.130616 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3933 14:44:21.130709
3934 14:44:21.134383 CA PerBit enable=1, Macro0, CA PI delay=33
3935 14:44:21.134469
3936 14:44:21.137164 [CBTSetCACLKResult] CA Dly = 33
3937 14:44:21.141001 CS Dly: 5 (0~36)
3938 14:44:21.141119
3939 14:44:21.144200 ----->DramcWriteLeveling(PI) begin...
3940 14:44:21.144286 ==
3941 14:44:21.147206 Dram Type= 6, Freq= 0, CH_0, rank 0
3942 14:44:21.150250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3943 14:44:21.150374 ==
3944 14:44:21.154108 Write leveling (Byte 0): 32 => 32
3945 14:44:21.156763 Write leveling (Byte 1): 31 => 31
3946 14:44:21.160399 DramcWriteLeveling(PI) end<-----
3947 14:44:21.160496
3948 14:44:21.160562 ==
3949 14:44:21.163973 Dram Type= 6, Freq= 0, CH_0, rank 0
3950 14:44:21.166851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3951 14:44:21.166938 ==
3952 14:44:21.170596 [Gating] SW mode calibration
3953 14:44:21.176853 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3954 14:44:21.183740 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3955 14:44:21.187242 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3956 14:44:21.190334 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3957 14:44:21.196497 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3958 14:44:21.199997 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
3959 14:44:21.203100 0 9 16 | B1->B0 | 2929 2424 | 1 0 | (1 0) (0 0)
3960 14:44:21.209696 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3961 14:44:21.212975 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3962 14:44:21.216402 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3963 14:44:21.223340 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3964 14:44:21.226307 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3965 14:44:21.229716 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3966 14:44:21.236295 0 10 12 | B1->B0 | 2626 3232 | 0 0 | (0 0) (0 0)
3967 14:44:21.239534 0 10 16 | B1->B0 | 3737 4242 | 1 1 | (0 0) (0 0)
3968 14:44:21.242904 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3969 14:44:21.249272 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3970 14:44:21.252675 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3971 14:44:21.256374 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3972 14:44:21.263008 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3973 14:44:21.265939 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3974 14:44:21.268945 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3975 14:44:21.275924 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3976 14:44:21.278942 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3977 14:44:21.282664 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3978 14:44:21.288580 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3979 14:44:21.292864 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3980 14:44:21.295752 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3981 14:44:21.301909 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3982 14:44:21.305248 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3983 14:44:21.308780 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 14:44:21.315508 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 14:44:21.318637 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 14:44:21.322345 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 14:44:21.328332 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 14:44:21.331735 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 14:44:21.335499 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3990 14:44:21.341418 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3991 14:44:21.345497 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 14:44:21.348256 Total UI for P1: 0, mck2ui 16
3993 14:44:21.351416 best dqsien dly found for B0: ( 0, 13, 10)
3994 14:44:21.355207 Total UI for P1: 0, mck2ui 16
3995 14:44:21.358445 best dqsien dly found for B1: ( 0, 13, 14)
3996 14:44:21.363051 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
3997 14:44:21.364634 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
3998 14:44:21.364730
3999 14:44:21.368091 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4000 14:44:21.374538 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4001 14:44:21.374649 [Gating] SW calibration Done
4002 14:44:21.374715 ==
4003 14:44:21.377956 Dram Type= 6, Freq= 0, CH_0, rank 0
4004 14:44:21.384322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4005 14:44:21.384430 ==
4006 14:44:21.384498 RX Vref Scan: 0
4007 14:44:21.384558
4008 14:44:21.387878 RX Vref 0 -> 0, step: 1
4009 14:44:21.387963
4010 14:44:21.391384 RX Delay -230 -> 252, step: 16
4011 14:44:21.394247 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4012 14:44:21.397737 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4013 14:44:21.404338 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4014 14:44:21.407610 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4015 14:44:21.414494 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4016 14:44:21.414599 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4017 14:44:21.420451 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4018 14:44:21.424475 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4019 14:44:21.427312 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4020 14:44:21.431166 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4021 14:44:21.434174 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4022 14:44:21.440827 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4023 14:44:21.443590 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4024 14:44:21.447003 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4025 14:44:21.453739 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4026 14:44:21.457095 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4027 14:44:21.457188 ==
4028 14:44:21.460146 Dram Type= 6, Freq= 0, CH_0, rank 0
4029 14:44:21.463805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4030 14:44:21.463897 ==
4031 14:44:21.463961 DQS Delay:
4032 14:44:21.466775 DQS0 = 0, DQS1 = 0
4033 14:44:21.466860 DQM Delay:
4034 14:44:21.470829 DQM0 = 45, DQM1 = 35
4035 14:44:21.470915 DQ Delay:
4036 14:44:21.474243 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4037 14:44:21.476930 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =57
4038 14:44:21.480051 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =33
4039 14:44:21.483411 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4040 14:44:21.483500
4041 14:44:21.483564
4042 14:44:21.483625 ==
4043 14:44:21.486333 Dram Type= 6, Freq= 0, CH_0, rank 0
4044 14:44:21.492909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4045 14:44:21.493041 ==
4046 14:44:21.493108
4047 14:44:21.493167
4048 14:44:21.493223 TX Vref Scan disable
4049 14:44:21.497185 == TX Byte 0 ==
4050 14:44:21.500059 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4051 14:44:21.506884 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4052 14:44:21.507028 == TX Byte 1 ==
4053 14:44:21.509975 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4054 14:44:21.516268 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4055 14:44:21.516409 ==
4056 14:44:21.519898 Dram Type= 6, Freq= 0, CH_0, rank 0
4057 14:44:21.522712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4058 14:44:21.522827 ==
4059 14:44:21.522895
4060 14:44:21.522955
4061 14:44:21.526256 TX Vref Scan disable
4062 14:44:21.529813 == TX Byte 0 ==
4063 14:44:21.532953 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4064 14:44:21.536171 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4065 14:44:21.539630 == TX Byte 1 ==
4066 14:44:21.543503 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4067 14:44:21.546026 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4068 14:44:21.546135
4069 14:44:21.546201 [DATLAT]
4070 14:44:21.549313 Freq=600, CH0 RK0
4071 14:44:21.549419
4072 14:44:21.552632 DATLAT Default: 0x9
4073 14:44:21.552773 0, 0xFFFF, sum = 0
4074 14:44:21.556080 1, 0xFFFF, sum = 0
4075 14:44:21.556182 2, 0xFFFF, sum = 0
4076 14:44:21.559283 3, 0xFFFF, sum = 0
4077 14:44:21.559387 4, 0xFFFF, sum = 0
4078 14:44:21.562777 5, 0xFFFF, sum = 0
4079 14:44:21.562894 6, 0xFFFF, sum = 0
4080 14:44:21.565874 7, 0xFFFF, sum = 0
4081 14:44:21.565975 8, 0x0, sum = 1
4082 14:44:21.568921 9, 0x0, sum = 2
4083 14:44:21.569021 10, 0x0, sum = 3
4084 14:44:21.572370 11, 0x0, sum = 4
4085 14:44:21.572470 best_step = 9
4086 14:44:21.572542
4087 14:44:21.572607 ==
4088 14:44:21.575704 Dram Type= 6, Freq= 0, CH_0, rank 0
4089 14:44:21.578862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4090 14:44:21.582377 ==
4091 14:44:21.582496 RX Vref Scan: 1
4092 14:44:21.582564
4093 14:44:21.585238 RX Vref 0 -> 0, step: 1
4094 14:44:21.585356
4095 14:44:21.589176 RX Delay -195 -> 252, step: 8
4096 14:44:21.589294
4097 14:44:21.592347 Set Vref, RX VrefLevel [Byte0]: 55
4098 14:44:21.595379 [Byte1]: 52
4099 14:44:21.595471
4100 14:44:21.598348 Final RX Vref Byte 0 = 55 to rank0
4101 14:44:21.602085 Final RX Vref Byte 1 = 52 to rank0
4102 14:44:21.605492 Final RX Vref Byte 0 = 55 to rank1
4103 14:44:21.608252 Final RX Vref Byte 1 = 52 to rank1==
4104 14:44:21.612190 Dram Type= 6, Freq= 0, CH_0, rank 0
4105 14:44:21.615101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4106 14:44:21.615189 ==
4107 14:44:21.618286 DQS Delay:
4108 14:44:21.618370 DQS0 = 0, DQS1 = 0
4109 14:44:21.618435 DQM Delay:
4110 14:44:21.621779 DQM0 = 44, DQM1 = 36
4111 14:44:21.621863 DQ Delay:
4112 14:44:21.625099 DQ0 =48, DQ1 =44, DQ2 =40, DQ3 =40
4113 14:44:21.628222 DQ4 =48, DQ5 =36, DQ6 =52, DQ7 =48
4114 14:44:21.631757 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4115 14:44:21.634908 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4116 14:44:21.634997
4117 14:44:21.635060
4118 14:44:21.644635 [DQSOSCAuto] RK0, (LSB)MR18= 0x5149, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
4119 14:44:21.648164 CH0 RK0: MR19=808, MR18=5149
4120 14:44:21.651200 CH0_RK0: MR19=0x808, MR18=0x5149, DQSOSC=394, MR23=63, INC=168, DEC=112
4121 14:44:21.654842
4122 14:44:21.658253 ----->DramcWriteLeveling(PI) begin...
4123 14:44:21.658353 ==
4124 14:44:21.661193 Dram Type= 6, Freq= 0, CH_0, rank 1
4125 14:44:21.664353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 14:44:21.664444 ==
4127 14:44:21.667867 Write leveling (Byte 0): 32 => 32
4128 14:44:21.671100 Write leveling (Byte 1): 29 => 29
4129 14:44:21.674468 DramcWriteLeveling(PI) end<-----
4130 14:44:21.674586
4131 14:44:21.674674 ==
4132 14:44:21.677626 Dram Type= 6, Freq= 0, CH_0, rank 1
4133 14:44:21.680626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 14:44:21.680716 ==
4135 14:44:21.684093 [Gating] SW mode calibration
4136 14:44:21.690757 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4137 14:44:21.697815 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4138 14:44:21.700510 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4139 14:44:21.703660 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4140 14:44:21.710752 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4141 14:44:21.713894 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4142 14:44:21.717001 0 9 16 | B1->B0 | 2e2e 2525 | 1 1 | (1 0) (0 0)
4143 14:44:21.724029 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4144 14:44:21.727123 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4145 14:44:21.730249 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4146 14:44:21.736628 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4147 14:44:21.739783 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4148 14:44:21.743242 0 10 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
4149 14:44:21.749798 0 10 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
4150 14:44:21.753272 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
4151 14:44:21.756693 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4152 14:44:21.763019 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4153 14:44:21.766522 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4154 14:44:21.769683 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4155 14:44:21.776228 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4156 14:44:21.779776 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4157 14:44:21.783347 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4158 14:44:21.789517 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4159 14:44:21.792917 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4160 14:44:21.796087 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4161 14:44:21.802830 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4162 14:44:21.806150 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4163 14:44:21.809162 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4164 14:44:21.815984 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4165 14:44:21.819129 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4166 14:44:21.822360 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4167 14:44:21.828976 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4168 14:44:21.832245 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 14:44:21.835835 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 14:44:21.842455 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 14:44:21.845130 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 14:44:21.849264 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 14:44:21.855248 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4174 14:44:21.858601 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 14:44:21.861585 Total UI for P1: 0, mck2ui 16
4176 14:44:21.865205 best dqsien dly found for B0: ( 0, 13, 12)
4177 14:44:21.868323 Total UI for P1: 0, mck2ui 16
4178 14:44:21.871749 best dqsien dly found for B1: ( 0, 13, 14)
4179 14:44:21.875460 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4180 14:44:21.878295 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4181 14:44:21.878385
4182 14:44:21.881817 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4183 14:44:21.888002 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4184 14:44:21.888105 [Gating] SW calibration Done
4185 14:44:21.888173 ==
4186 14:44:21.891587 Dram Type= 6, Freq= 0, CH_0, rank 1
4187 14:44:21.898029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4188 14:44:21.898151 ==
4189 14:44:21.898221 RX Vref Scan: 0
4190 14:44:21.898281
4191 14:44:21.901140 RX Vref 0 -> 0, step: 1
4192 14:44:21.901281
4193 14:44:21.904579 RX Delay -230 -> 252, step: 16
4194 14:44:21.908372 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4195 14:44:21.911234 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4196 14:44:21.917773 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4197 14:44:21.921299 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4198 14:44:21.924378 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4199 14:44:21.927705 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4200 14:44:21.931189 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4201 14:44:21.937438 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4202 14:44:21.940940 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4203 14:44:21.944468 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4204 14:44:21.948409 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4205 14:44:21.954366 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4206 14:44:21.957252 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4207 14:44:21.960843 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4208 14:44:21.963926 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4209 14:44:21.970504 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4210 14:44:21.970627 ==
4211 14:44:21.974264 Dram Type= 6, Freq= 0, CH_0, rank 1
4212 14:44:21.977628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4213 14:44:21.977733 ==
4214 14:44:21.977800 DQS Delay:
4215 14:44:21.980436 DQS0 = 0, DQS1 = 0
4216 14:44:21.980522 DQM Delay:
4217 14:44:21.983646 DQM0 = 45, DQM1 = 36
4218 14:44:21.983739 DQ Delay:
4219 14:44:21.987780 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4220 14:44:21.990099 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =57
4221 14:44:21.993686 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4222 14:44:21.996928 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4223 14:44:21.997047
4224 14:44:21.997142
4225 14:44:21.997228 ==
4226 14:44:22.000146 Dram Type= 6, Freq= 0, CH_0, rank 1
4227 14:44:22.003387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 14:44:22.006754 ==
4229 14:44:22.006846
4230 14:44:22.006910
4231 14:44:22.006968 TX Vref Scan disable
4232 14:44:22.010179 == TX Byte 0 ==
4233 14:44:22.014062 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4234 14:44:22.019924 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4235 14:44:22.020084 == TX Byte 1 ==
4236 14:44:22.023382 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4237 14:44:22.030119 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4238 14:44:22.030272 ==
4239 14:44:22.033430 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 14:44:22.036301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 14:44:22.036389 ==
4242 14:44:22.036454
4243 14:44:22.036513
4244 14:44:22.039702 TX Vref Scan disable
4245 14:44:22.043674 == TX Byte 0 ==
4246 14:44:22.045985 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4247 14:44:22.049933 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4248 14:44:22.053241 == TX Byte 1 ==
4249 14:44:22.056287 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4250 14:44:22.059353 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4251 14:44:22.059448
4252 14:44:22.059514 [DATLAT]
4253 14:44:22.062743 Freq=600, CH0 RK1
4254 14:44:22.062832
4255 14:44:22.066375 DATLAT Default: 0x9
4256 14:44:22.066465 0, 0xFFFF, sum = 0
4257 14:44:22.070012 1, 0xFFFF, sum = 0
4258 14:44:22.070192 2, 0xFFFF, sum = 0
4259 14:44:22.072517 3, 0xFFFF, sum = 0
4260 14:44:22.072626 4, 0xFFFF, sum = 0
4261 14:44:22.075888 5, 0xFFFF, sum = 0
4262 14:44:22.076174 6, 0xFFFF, sum = 0
4263 14:44:22.079298 7, 0xFFFF, sum = 0
4264 14:44:22.079406 8, 0x0, sum = 1
4265 14:44:22.082684 9, 0x0, sum = 2
4266 14:44:22.082774 10, 0x0, sum = 3
4267 14:44:22.085839 11, 0x0, sum = 4
4268 14:44:22.085926 best_step = 9
4269 14:44:22.085991
4270 14:44:22.086057 ==
4271 14:44:22.089132 Dram Type= 6, Freq= 0, CH_0, rank 1
4272 14:44:22.092258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4273 14:44:22.096201 ==
4274 14:44:22.096349 RX Vref Scan: 0
4275 14:44:22.096451
4276 14:44:22.099442 RX Vref 0 -> 0, step: 1
4277 14:44:22.099528
4278 14:44:22.102023 RX Delay -179 -> 252, step: 8
4279 14:44:22.106148 iDelay=197, Bit 0, Center 44 (-99 ~ 188) 288
4280 14:44:22.109219 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4281 14:44:22.115160 iDelay=197, Bit 2, Center 40 (-107 ~ 188) 296
4282 14:44:22.118929 iDelay=197, Bit 3, Center 40 (-107 ~ 188) 296
4283 14:44:22.121680 iDelay=197, Bit 4, Center 48 (-99 ~ 196) 296
4284 14:44:22.125204 iDelay=197, Bit 5, Center 32 (-115 ~ 180) 296
4285 14:44:22.128723 iDelay=197, Bit 6, Center 52 (-91 ~ 196) 288
4286 14:44:22.135247 iDelay=197, Bit 7, Center 48 (-99 ~ 196) 296
4287 14:44:22.138346 iDelay=197, Bit 8, Center 28 (-123 ~ 180) 304
4288 14:44:22.141987 iDelay=197, Bit 9, Center 24 (-131 ~ 180) 312
4289 14:44:22.145196 iDelay=197, Bit 10, Center 36 (-115 ~ 188) 304
4290 14:44:22.151598 iDelay=197, Bit 11, Center 28 (-123 ~ 180) 304
4291 14:44:22.155216 iDelay=197, Bit 12, Center 44 (-107 ~ 196) 304
4292 14:44:22.158731 iDelay=197, Bit 13, Center 44 (-107 ~ 196) 304
4293 14:44:22.161306 iDelay=197, Bit 14, Center 48 (-99 ~ 196) 296
4294 14:44:22.168305 iDelay=197, Bit 15, Center 44 (-107 ~ 196) 304
4295 14:44:22.168431 ==
4296 14:44:22.171270 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 14:44:22.175078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 14:44:22.175179 ==
4299 14:44:22.175258 DQS Delay:
4300 14:44:22.177880 DQS0 = 0, DQS1 = 0
4301 14:44:22.177986 DQM Delay:
4302 14:44:22.181865 DQM0 = 43, DQM1 = 37
4303 14:44:22.181958 DQ Delay:
4304 14:44:22.184932 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4305 14:44:22.187944 DQ4 =48, DQ5 =32, DQ6 =52, DQ7 =48
4306 14:44:22.191092 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =28
4307 14:44:22.194844 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4308 14:44:22.194988
4309 14:44:22.195088
4310 14:44:22.204652 [DQSOSCAuto] RK1, (LSB)MR18= 0x4743, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4311 14:44:22.204812 CH0 RK1: MR19=808, MR18=4743
4312 14:44:22.210800 CH0_RK1: MR19=0x808, MR18=0x4743, DQSOSC=396, MR23=63, INC=167, DEC=111
4313 14:44:22.214097 [RxdqsGatingPostProcess] freq 600
4314 14:44:22.221288 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4315 14:44:22.224123 Pre-setting of DQS Precalculation
4316 14:44:22.227197 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4317 14:44:22.227289 ==
4318 14:44:22.231176 Dram Type= 6, Freq= 0, CH_1, rank 0
4319 14:44:22.237302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 14:44:22.237426 ==
4321 14:44:22.240749 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4322 14:44:22.247036 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4323 14:44:22.250413 [CA 0] Center 35 (5~66) winsize 62
4324 14:44:22.253769 [CA 1] Center 35 (5~66) winsize 62
4325 14:44:22.257037 [CA 2] Center 34 (4~65) winsize 62
4326 14:44:22.260075 [CA 3] Center 34 (3~65) winsize 63
4327 14:44:22.263403 [CA 4] Center 34 (4~65) winsize 62
4328 14:44:22.266773 [CA 5] Center 34 (3~65) winsize 63
4329 14:44:22.266872
4330 14:44:22.270017 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4331 14:44:22.270103
4332 14:44:22.273291 [CATrainingPosCal] consider 1 rank data
4333 14:44:22.276660 u2DelayCellTimex100 = 270/100 ps
4334 14:44:22.279726 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4335 14:44:22.286388 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4336 14:44:22.289832 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4337 14:44:22.293517 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4338 14:44:22.296716 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4339 14:44:22.300026 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4340 14:44:22.300117
4341 14:44:22.303091 CA PerBit enable=1, Macro0, CA PI delay=34
4342 14:44:22.303179
4343 14:44:22.306296 [CBTSetCACLKResult] CA Dly = 34
4344 14:44:22.310045 CS Dly: 3 (0~34)
4345 14:44:22.310144 ==
4346 14:44:22.313218 Dram Type= 6, Freq= 0, CH_1, rank 1
4347 14:44:22.316650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 14:44:22.316800 ==
4349 14:44:22.323307 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4350 14:44:22.326505 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4351 14:44:22.330594 [CA 0] Center 36 (6~66) winsize 61
4352 14:44:22.334104 [CA 1] Center 35 (5~66) winsize 62
4353 14:44:22.336653 [CA 2] Center 34 (4~65) winsize 62
4354 14:44:22.340258 [CA 3] Center 34 (3~65) winsize 63
4355 14:44:22.343713 [CA 4] Center 34 (4~65) winsize 62
4356 14:44:22.346381 [CA 5] Center 34 (3~65) winsize 63
4357 14:44:22.346509
4358 14:44:22.350433 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4359 14:44:22.350550
4360 14:44:22.353388 [CATrainingPosCal] consider 2 rank data
4361 14:44:22.356908 u2DelayCellTimex100 = 270/100 ps
4362 14:44:22.359894 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4363 14:44:22.366269 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4364 14:44:22.370146 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4365 14:44:22.373025 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4366 14:44:22.376523 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4367 14:44:22.379417 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4368 14:44:22.379536
4369 14:44:22.382730 CA PerBit enable=1, Macro0, CA PI delay=34
4370 14:44:22.382893
4371 14:44:22.386414 [CBTSetCACLKResult] CA Dly = 34
4372 14:44:22.389542 CS Dly: 4 (0~36)
4373 14:44:22.389660
4374 14:44:22.392940 ----->DramcWriteLeveling(PI) begin...
4375 14:44:22.393050 ==
4376 14:44:22.396367 Dram Type= 6, Freq= 0, CH_1, rank 0
4377 14:44:22.399799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4378 14:44:22.399910 ==
4379 14:44:22.402543 Write leveling (Byte 0): 28 => 28
4380 14:44:22.406043 Write leveling (Byte 1): 29 => 29
4381 14:44:22.409140 DramcWriteLeveling(PI) end<-----
4382 14:44:22.409266
4383 14:44:22.409375 ==
4384 14:44:22.412616 Dram Type= 6, Freq= 0, CH_1, rank 0
4385 14:44:22.416320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4386 14:44:22.416454 ==
4387 14:44:22.419138 [Gating] SW mode calibration
4388 14:44:22.426083 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4389 14:44:22.432584 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4390 14:44:22.435243 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4391 14:44:22.438802 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4392 14:44:22.445575 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4393 14:44:22.448616 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (1 1) (1 0)
4394 14:44:22.451775 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4395 14:44:22.458399 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4396 14:44:22.461804 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4397 14:44:22.468748 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4398 14:44:22.472185 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4399 14:44:22.474938 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4400 14:44:22.481378 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4401 14:44:22.484974 0 10 12 | B1->B0 | 3434 3737 | 0 0 | (0 0) (0 0)
4402 14:44:22.487916 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4403 14:44:22.491502 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4404 14:44:22.497984 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4405 14:44:22.501299 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4406 14:44:22.504385 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4407 14:44:22.511402 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4408 14:44:22.514461 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4409 14:44:22.517853 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4410 14:44:22.524168 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4411 14:44:22.528356 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4412 14:44:22.531098 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4413 14:44:22.537580 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4414 14:44:22.540787 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4415 14:44:22.544041 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4416 14:44:22.551320 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4417 14:44:22.554438 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 14:44:22.558380 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 14:44:22.564362 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 14:44:22.567337 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 14:44:22.570985 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 14:44:22.577697 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 14:44:22.580921 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 14:44:22.584003 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 14:44:22.590395 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4426 14:44:22.593849 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 14:44:22.597358 Total UI for P1: 0, mck2ui 16
4428 14:44:22.600413 best dqsien dly found for B0: ( 0, 13, 12)
4429 14:44:22.603480 Total UI for P1: 0, mck2ui 16
4430 14:44:22.606908 best dqsien dly found for B1: ( 0, 13, 14)
4431 14:44:22.610303 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4432 14:44:22.613465 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4433 14:44:22.613598
4434 14:44:22.616583 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4435 14:44:22.624047 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4436 14:44:22.624163 [Gating] SW calibration Done
4437 14:44:22.624230 ==
4438 14:44:22.626620 Dram Type= 6, Freq= 0, CH_1, rank 0
4439 14:44:22.633101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4440 14:44:22.633236 ==
4441 14:44:22.633318 RX Vref Scan: 0
4442 14:44:22.633381
4443 14:44:22.636355 RX Vref 0 -> 0, step: 1
4444 14:44:22.636442
4445 14:44:22.640131 RX Delay -230 -> 252, step: 16
4446 14:44:22.643118 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4447 14:44:22.646988 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4448 14:44:22.653002 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4449 14:44:22.656364 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4450 14:44:22.659883 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4451 14:44:22.663064 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4452 14:44:22.669466 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4453 14:44:22.673184 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4454 14:44:22.675872 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4455 14:44:22.679469 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4456 14:44:22.682321 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4457 14:44:22.689863 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4458 14:44:22.692621 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4459 14:44:22.695950 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4460 14:44:22.702271 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4461 14:44:22.705447 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4462 14:44:22.705547 ==
4463 14:44:22.708848 Dram Type= 6, Freq= 0, CH_1, rank 0
4464 14:44:22.712167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4465 14:44:22.712261 ==
4466 14:44:22.712327 DQS Delay:
4467 14:44:22.715771 DQS0 = 0, DQS1 = 0
4468 14:44:22.715858 DQM Delay:
4469 14:44:22.718983 DQM0 = 44, DQM1 = 41
4470 14:44:22.719069 DQ Delay:
4471 14:44:22.722612 DQ0 =57, DQ1 =33, DQ2 =25, DQ3 =41
4472 14:44:22.725491 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4473 14:44:22.729014 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4474 14:44:22.732000 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =49
4475 14:44:22.732087
4476 14:44:22.732151
4477 14:44:22.732210 ==
4478 14:44:22.735080 Dram Type= 6, Freq= 0, CH_1, rank 0
4479 14:44:22.742022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4480 14:44:22.742136 ==
4481 14:44:22.742203
4482 14:44:22.742261
4483 14:44:22.742318 TX Vref Scan disable
4484 14:44:22.745464 == TX Byte 0 ==
4485 14:44:22.748458 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4486 14:44:22.752274 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4487 14:44:22.755650 == TX Byte 1 ==
4488 14:44:22.758699 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4489 14:44:22.764777 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4490 14:44:22.764879 ==
4491 14:44:22.768033 Dram Type= 6, Freq= 0, CH_1, rank 0
4492 14:44:22.771693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4493 14:44:22.771779 ==
4494 14:44:22.771844
4495 14:44:22.771903
4496 14:44:22.774826 TX Vref Scan disable
4497 14:44:22.778405 == TX Byte 0 ==
4498 14:44:22.781207 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4499 14:44:22.784707 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4500 14:44:22.787804 == TX Byte 1 ==
4501 14:44:22.791309 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4502 14:44:22.794578 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4503 14:44:22.794664
4504 14:44:22.797962 [DATLAT]
4505 14:44:22.798046 Freq=600, CH1 RK0
4506 14:44:22.798110
4507 14:44:22.800966 DATLAT Default: 0x9
4508 14:44:22.801052 0, 0xFFFF, sum = 0
4509 14:44:22.804774 1, 0xFFFF, sum = 0
4510 14:44:22.804871 2, 0xFFFF, sum = 0
4511 14:44:22.807376 3, 0xFFFF, sum = 0
4512 14:44:22.807462 4, 0xFFFF, sum = 0
4513 14:44:22.810804 5, 0xFFFF, sum = 0
4514 14:44:22.810894 6, 0xFFFF, sum = 0
4515 14:44:22.814137 7, 0xFFFF, sum = 0
4516 14:44:22.814225 8, 0x0, sum = 1
4517 14:44:22.817215 9, 0x0, sum = 2
4518 14:44:22.817318 10, 0x0, sum = 3
4519 14:44:22.820880 11, 0x0, sum = 4
4520 14:44:22.820971 best_step = 9
4521 14:44:22.821035
4522 14:44:22.821094 ==
4523 14:44:22.823706 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 14:44:22.827203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 14:44:22.830616 ==
4526 14:44:22.830720 RX Vref Scan: 1
4527 14:44:22.830784
4528 14:44:22.834249 RX Vref 0 -> 0, step: 1
4529 14:44:22.834338
4530 14:44:22.837543 RX Delay -179 -> 252, step: 8
4531 14:44:22.837630
4532 14:44:22.840842 Set Vref, RX VrefLevel [Byte0]: 51
4533 14:44:22.843788 [Byte1]: 52
4534 14:44:22.843880
4535 14:44:22.846859 Final RX Vref Byte 0 = 51 to rank0
4536 14:44:22.850333 Final RX Vref Byte 1 = 52 to rank0
4537 14:44:22.853777 Final RX Vref Byte 0 = 51 to rank1
4538 14:44:22.857056 Final RX Vref Byte 1 = 52 to rank1==
4539 14:44:22.860312 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 14:44:22.863431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 14:44:22.863530 ==
4542 14:44:22.867179 DQS Delay:
4543 14:44:22.867273 DQS0 = 0, DQS1 = 0
4544 14:44:22.867360 DQM Delay:
4545 14:44:22.870319 DQM0 = 42, DQM1 = 34
4546 14:44:22.870404 DQ Delay:
4547 14:44:22.874026 DQ0 =48, DQ1 =40, DQ2 =28, DQ3 =40
4548 14:44:22.877042 DQ4 =36, DQ5 =52, DQ6 =56, DQ7 =36
4549 14:44:22.880121 DQ8 =16, DQ9 =24, DQ10 =36, DQ11 =28
4550 14:44:22.883571 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4551 14:44:22.883666
4552 14:44:22.883742
4553 14:44:22.893472 [DQSOSCAuto] RK0, (LSB)MR18= 0x3650, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 399 ps
4554 14:44:22.897064 CH1 RK0: MR19=808, MR18=3650
4555 14:44:22.900130 CH1_RK0: MR19=0x808, MR18=0x3650, DQSOSC=394, MR23=63, INC=168, DEC=112
4556 14:44:22.902824
4557 14:44:22.906271 ----->DramcWriteLeveling(PI) begin...
4558 14:44:22.906367 ==
4559 14:44:22.909495 Dram Type= 6, Freq= 0, CH_1, rank 1
4560 14:44:22.913191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 14:44:22.913321 ==
4562 14:44:22.916316 Write leveling (Byte 0): 27 => 27
4563 14:44:22.920441 Write leveling (Byte 1): 28 => 28
4564 14:44:22.922646 DramcWriteLeveling(PI) end<-----
4565 14:44:22.922734
4566 14:44:22.922798 ==
4567 14:44:22.925945 Dram Type= 6, Freq= 0, CH_1, rank 1
4568 14:44:22.929741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 14:44:22.929831 ==
4570 14:44:22.932639 [Gating] SW mode calibration
4571 14:44:22.939456 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4572 14:44:22.945948 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4573 14:44:22.949009 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4574 14:44:22.952339 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4575 14:44:22.959492 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4576 14:44:22.962079 0 9 12 | B1->B0 | 3030 2929 | 0 0 | (0 1) (0 0)
4577 14:44:22.965425 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4578 14:44:22.972164 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4579 14:44:22.975510 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4580 14:44:22.978744 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4581 14:44:22.985196 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4582 14:44:22.988621 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4583 14:44:22.991710 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
4584 14:44:22.998676 0 10 12 | B1->B0 | 3232 3c3c | 0 0 | (0 0) (0 0)
4585 14:44:23.001973 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4586 14:44:23.004945 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4587 14:44:23.011705 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4588 14:44:23.014890 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4589 14:44:23.018296 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4590 14:44:23.025221 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4591 14:44:23.028484 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4592 14:44:23.031233 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4593 14:44:23.037684 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4594 14:44:23.041405 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4595 14:44:23.044704 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4596 14:44:23.051301 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4597 14:44:23.054424 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4598 14:44:23.057518 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4599 14:44:23.064549 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4600 14:44:23.068116 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4601 14:44:23.071300 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4602 14:44:23.077682 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4603 14:44:23.080891 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 14:44:23.084022 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 14:44:23.090650 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 14:44:23.094065 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 14:44:23.097396 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4608 14:44:23.104170 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 14:44:23.107287 Total UI for P1: 0, mck2ui 16
4610 14:44:23.111083 best dqsien dly found for B0: ( 0, 13, 8)
4611 14:44:23.113964 Total UI for P1: 0, mck2ui 16
4612 14:44:23.117487 best dqsien dly found for B1: ( 0, 13, 10)
4613 14:44:23.120614 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4614 14:44:23.123469 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4615 14:44:23.123556
4616 14:44:23.126650 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4617 14:44:23.130210 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4618 14:44:23.133570 [Gating] SW calibration Done
4619 14:44:23.133658 ==
4620 14:44:23.137067 Dram Type= 6, Freq= 0, CH_1, rank 1
4621 14:44:23.140165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 14:44:23.140252 ==
4623 14:44:23.143321 RX Vref Scan: 0
4624 14:44:23.143405
4625 14:44:23.146486 RX Vref 0 -> 0, step: 1
4626 14:44:23.146571
4627 14:44:23.146635 RX Delay -230 -> 252, step: 16
4628 14:44:23.152969 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4629 14:44:23.156320 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4630 14:44:23.159632 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4631 14:44:23.163259 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4632 14:44:23.169450 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4633 14:44:23.172872 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4634 14:44:23.176424 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4635 14:44:23.179678 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4636 14:44:23.186303 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4637 14:44:23.189175 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4638 14:44:23.192591 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4639 14:44:23.196081 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4640 14:44:23.202324 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4641 14:44:23.205891 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4642 14:44:23.209100 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4643 14:44:23.212396 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4644 14:44:23.212481 ==
4645 14:44:23.215724 Dram Type= 6, Freq= 0, CH_1, rank 1
4646 14:44:23.222157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 14:44:23.222262 ==
4648 14:44:23.222330 DQS Delay:
4649 14:44:23.225831 DQS0 = 0, DQS1 = 0
4650 14:44:23.225915 DQM Delay:
4651 14:44:23.228839 DQM0 = 41, DQM1 = 38
4652 14:44:23.228922 DQ Delay:
4653 14:44:23.232264 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4654 14:44:23.235629 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4655 14:44:23.238979 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4656 14:44:23.241668 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4657 14:44:23.241755
4658 14:44:23.241819
4659 14:44:23.241878 ==
4660 14:44:23.245201 Dram Type= 6, Freq= 0, CH_1, rank 1
4661 14:44:23.249118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4662 14:44:23.249236 ==
4663 14:44:23.249369
4664 14:44:23.249456
4665 14:44:23.251608 TX Vref Scan disable
4666 14:44:23.254724 == TX Byte 0 ==
4667 14:44:23.258311 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4668 14:44:23.262002 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4669 14:44:23.264925 == TX Byte 1 ==
4670 14:44:23.268028 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4671 14:44:23.271750 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4672 14:44:23.271847 ==
4673 14:44:23.275004 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 14:44:23.281445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 14:44:23.281551 ==
4676 14:44:23.281616
4677 14:44:23.281675
4678 14:44:23.281731 TX Vref Scan disable
4679 14:44:23.285751 == TX Byte 0 ==
4680 14:44:23.289034 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4681 14:44:23.296041 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4682 14:44:23.296156 == TX Byte 1 ==
4683 14:44:23.299332 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4684 14:44:23.305921 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4685 14:44:23.306044
4686 14:44:23.306124 [DATLAT]
4687 14:44:23.306214 Freq=600, CH1 RK1
4688 14:44:23.306276
4689 14:44:23.308948 DATLAT Default: 0x9
4690 14:44:23.312255 0, 0xFFFF, sum = 0
4691 14:44:23.312347 1, 0xFFFF, sum = 0
4692 14:44:23.315573 2, 0xFFFF, sum = 0
4693 14:44:23.315662 3, 0xFFFF, sum = 0
4694 14:44:23.318833 4, 0xFFFF, sum = 0
4695 14:44:23.318921 5, 0xFFFF, sum = 0
4696 14:44:23.321846 6, 0xFFFF, sum = 0
4697 14:44:23.321962 7, 0xFFFF, sum = 0
4698 14:44:23.325544 8, 0x0, sum = 1
4699 14:44:23.325633 9, 0x0, sum = 2
4700 14:44:23.328679 10, 0x0, sum = 3
4701 14:44:23.328766 11, 0x0, sum = 4
4702 14:44:23.328833 best_step = 9
4703 14:44:23.328892
4704 14:44:23.332055 ==
4705 14:44:23.332139 Dram Type= 6, Freq= 0, CH_1, rank 1
4706 14:44:23.338671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4707 14:44:23.338777 ==
4708 14:44:23.338844 RX Vref Scan: 0
4709 14:44:23.338905
4710 14:44:23.341893 RX Vref 0 -> 0, step: 1
4711 14:44:23.341978
4712 14:44:23.345156 RX Delay -179 -> 252, step: 8
4713 14:44:23.351705 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4714 14:44:23.355430 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4715 14:44:23.358528 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4716 14:44:23.361406 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4717 14:44:23.364706 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4718 14:44:23.371189 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4719 14:44:23.374566 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4720 14:44:23.377852 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4721 14:44:23.381254 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4722 14:44:23.387929 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4723 14:44:23.391546 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4724 14:44:23.394479 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4725 14:44:23.397734 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4726 14:44:23.404920 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4727 14:44:23.407613 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4728 14:44:23.410906 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4729 14:44:23.411000 ==
4730 14:44:23.414987 Dram Type= 6, Freq= 0, CH_1, rank 1
4731 14:44:23.417657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4732 14:44:23.420563 ==
4733 14:44:23.420650 DQS Delay:
4734 14:44:23.420714 DQS0 = 0, DQS1 = 0
4735 14:44:23.424512 DQM Delay:
4736 14:44:23.424596 DQM0 = 37, DQM1 = 36
4737 14:44:23.427681 DQ Delay:
4738 14:44:23.430874 DQ0 =40, DQ1 =36, DQ2 =24, DQ3 =36
4739 14:44:23.430960 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4740 14:44:23.434648 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4741 14:44:23.437470 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4742 14:44:23.440888
4743 14:44:23.440978
4744 14:44:23.447404 [DQSOSCAuto] RK1, (LSB)MR18= 0x3559, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4745 14:44:23.450731 CH1 RK1: MR19=808, MR18=3559
4746 14:44:23.457439 CH1_RK1: MR19=0x808, MR18=0x3559, DQSOSC=393, MR23=63, INC=169, DEC=113
4747 14:44:23.460513 [RxdqsGatingPostProcess] freq 600
4748 14:44:23.463917 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4749 14:44:23.467315 Pre-setting of DQS Precalculation
4750 14:44:23.473439 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4751 14:44:23.480265 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4752 14:44:23.486498 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4753 14:44:23.486619
4754 14:44:23.486686
4755 14:44:23.489895 [Calibration Summary] 1200 Mbps
4756 14:44:23.489982 CH 0, Rank 0
4757 14:44:23.493199 SW Impedance : PASS
4758 14:44:23.496622 DUTY Scan : NO K
4759 14:44:23.496710 ZQ Calibration : PASS
4760 14:44:23.499962 Jitter Meter : NO K
4761 14:44:23.503083 CBT Training : PASS
4762 14:44:23.503174 Write leveling : PASS
4763 14:44:23.506556 RX DQS gating : PASS
4764 14:44:23.509941 RX DQ/DQS(RDDQC) : PASS
4765 14:44:23.510033 TX DQ/DQS : PASS
4766 14:44:23.513228 RX DATLAT : PASS
4767 14:44:23.516962 RX DQ/DQS(Engine): PASS
4768 14:44:23.517050 TX OE : NO K
4769 14:44:23.519876 All Pass.
4770 14:44:23.519963
4771 14:44:23.520028 CH 0, Rank 1
4772 14:44:23.523397 SW Impedance : PASS
4773 14:44:23.523489 DUTY Scan : NO K
4774 14:44:23.526560 ZQ Calibration : PASS
4775 14:44:23.530114 Jitter Meter : NO K
4776 14:44:23.530205 CBT Training : PASS
4777 14:44:23.533126 Write leveling : PASS
4778 14:44:23.533212 RX DQS gating : PASS
4779 14:44:23.537174 RX DQ/DQS(RDDQC) : PASS
4780 14:44:23.539561 TX DQ/DQS : PASS
4781 14:44:23.539654 RX DATLAT : PASS
4782 14:44:23.542963 RX DQ/DQS(Engine): PASS
4783 14:44:23.546770 TX OE : NO K
4784 14:44:23.546867 All Pass.
4785 14:44:23.546932
4786 14:44:23.546991 CH 1, Rank 0
4787 14:44:23.549596 SW Impedance : PASS
4788 14:44:23.553034 DUTY Scan : NO K
4789 14:44:23.553148 ZQ Calibration : PASS
4790 14:44:23.556408 Jitter Meter : NO K
4791 14:44:23.559247 CBT Training : PASS
4792 14:44:23.559337 Write leveling : PASS
4793 14:44:23.562858 RX DQS gating : PASS
4794 14:44:23.566166 RX DQ/DQS(RDDQC) : PASS
4795 14:44:23.566249 TX DQ/DQS : PASS
4796 14:44:23.569898 RX DATLAT : PASS
4797 14:44:23.572647 RX DQ/DQS(Engine): PASS
4798 14:44:23.572733 TX OE : NO K
4799 14:44:23.576786 All Pass.
4800 14:44:23.576873
4801 14:44:23.576936 CH 1, Rank 1
4802 14:44:23.579124 SW Impedance : PASS
4803 14:44:23.579205 DUTY Scan : NO K
4804 14:44:23.582283 ZQ Calibration : PASS
4805 14:44:23.585955 Jitter Meter : NO K
4806 14:44:23.586042 CBT Training : PASS
4807 14:44:23.588955 Write leveling : PASS
4808 14:44:23.592066 RX DQS gating : PASS
4809 14:44:23.592153 RX DQ/DQS(RDDQC) : PASS
4810 14:44:23.595487 TX DQ/DQS : PASS
4811 14:44:23.598895 RX DATLAT : PASS
4812 14:44:23.598989 RX DQ/DQS(Engine): PASS
4813 14:44:23.602296 TX OE : NO K
4814 14:44:23.602390 All Pass.
4815 14:44:23.602457
4816 14:44:23.605837 DramC Write-DBI off
4817 14:44:23.608977 PER_BANK_REFRESH: Hybrid Mode
4818 14:44:23.609073 TX_TRACKING: ON
4819 14:44:23.618857 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4820 14:44:23.621997 [FAST_K] Save calibration result to emmc
4821 14:44:23.625319 dramc_set_vcore_voltage set vcore to 662500
4822 14:44:23.629002 Read voltage for 933, 3
4823 14:44:23.629098 Vio18 = 0
4824 14:44:23.629163 Vcore = 662500
4825 14:44:23.632038 Vdram = 0
4826 14:44:23.632123 Vddq = 0
4827 14:44:23.632187 Vmddr = 0
4828 14:44:23.638502 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4829 14:44:23.642148 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4830 14:44:23.645039 MEM_TYPE=3, freq_sel=17
4831 14:44:23.648793 sv_algorithm_assistance_LP4_1600
4832 14:44:23.652170 ============ PULL DRAM RESETB DOWN ============
4833 14:44:23.654862 ========== PULL DRAM RESETB DOWN end =========
4834 14:44:23.661212 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4835 14:44:23.664792 ===================================
4836 14:44:23.668093 LPDDR4 DRAM CONFIGURATION
4837 14:44:23.671577 ===================================
4838 14:44:23.671668 EX_ROW_EN[0] = 0x0
4839 14:44:23.674660 EX_ROW_EN[1] = 0x0
4840 14:44:23.674743 LP4Y_EN = 0x0
4841 14:44:23.678583 WORK_FSP = 0x0
4842 14:44:23.678667 WL = 0x3
4843 14:44:23.681527 RL = 0x3
4844 14:44:23.681611 BL = 0x2
4845 14:44:23.684699 RPST = 0x0
4846 14:44:23.684781 RD_PRE = 0x0
4847 14:44:23.688241 WR_PRE = 0x1
4848 14:44:23.688324 WR_PST = 0x0
4849 14:44:23.691437 DBI_WR = 0x0
4850 14:44:23.691532 DBI_RD = 0x0
4851 14:44:23.695054 OTF = 0x1
4852 14:44:23.697877 ===================================
4853 14:44:23.701296 ===================================
4854 14:44:23.701402 ANA top config
4855 14:44:23.704671 ===================================
4856 14:44:23.707958 DLL_ASYNC_EN = 0
4857 14:44:23.711676 ALL_SLAVE_EN = 1
4858 14:44:23.714438 NEW_RANK_MODE = 1
4859 14:44:23.714532 DLL_IDLE_MODE = 1
4860 14:44:23.717785 LP45_APHY_COMB_EN = 1
4861 14:44:23.721142 TX_ODT_DIS = 1
4862 14:44:23.724321 NEW_8X_MODE = 1
4863 14:44:23.727749 ===================================
4864 14:44:23.731436 ===================================
4865 14:44:23.733972 data_rate = 1866
4866 14:44:23.737564 CKR = 1
4867 14:44:23.737659 DQ_P2S_RATIO = 8
4868 14:44:23.740882 ===================================
4869 14:44:23.744905 CA_P2S_RATIO = 8
4870 14:44:23.747141 DQ_CA_OPEN = 0
4871 14:44:23.750347 DQ_SEMI_OPEN = 0
4872 14:44:23.753763 CA_SEMI_OPEN = 0
4873 14:44:23.757118 CA_FULL_RATE = 0
4874 14:44:23.757222 DQ_CKDIV4_EN = 1
4875 14:44:23.760217 CA_CKDIV4_EN = 1
4876 14:44:23.763584 CA_PREDIV_EN = 0
4877 14:44:23.766810 PH8_DLY = 0
4878 14:44:23.770270 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4879 14:44:23.773636 DQ_AAMCK_DIV = 4
4880 14:44:23.776640 CA_AAMCK_DIV = 4
4881 14:44:23.776750 CA_ADMCK_DIV = 4
4882 14:44:23.780172 DQ_TRACK_CA_EN = 0
4883 14:44:23.783354 CA_PICK = 933
4884 14:44:23.786629 CA_MCKIO = 933
4885 14:44:23.790051 MCKIO_SEMI = 0
4886 14:44:23.793212 PLL_FREQ = 3732
4887 14:44:23.796335 DQ_UI_PI_RATIO = 32
4888 14:44:23.796426 CA_UI_PI_RATIO = 0
4889 14:44:23.799648 ===================================
4890 14:44:23.803182 ===================================
4891 14:44:23.806988 memory_type:LPDDR4
4892 14:44:23.809663 GP_NUM : 10
4893 14:44:23.809755 SRAM_EN : 1
4894 14:44:23.813748 MD32_EN : 0
4895 14:44:23.816457 ===================================
4896 14:44:23.819357 [ANA_INIT] >>>>>>>>>>>>>>
4897 14:44:23.823210 <<<<<< [CONFIGURE PHASE]: ANA_TX
4898 14:44:23.826339 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4899 14:44:23.829356 ===================================
4900 14:44:23.829446 data_rate = 1866,PCW = 0X8f00
4901 14:44:23.832536 ===================================
4902 14:44:23.839028 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4903 14:44:23.842349 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4904 14:44:23.850195 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4905 14:44:23.852574 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4906 14:44:23.855922 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4907 14:44:23.859392 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4908 14:44:23.862386 [ANA_INIT] flow start
4909 14:44:23.865718 [ANA_INIT] PLL >>>>>>>>
4910 14:44:23.865812 [ANA_INIT] PLL <<<<<<<<
4911 14:44:23.869211 [ANA_INIT] MIDPI >>>>>>>>
4912 14:44:23.872057 [ANA_INIT] MIDPI <<<<<<<<
4913 14:44:23.875421 [ANA_INIT] DLL >>>>>>>>
4914 14:44:23.875518 [ANA_INIT] flow end
4915 14:44:23.879136 ============ LP4 DIFF to SE enter ============
4916 14:44:23.884951 ============ LP4 DIFF to SE exit ============
4917 14:44:23.885067 [ANA_INIT] <<<<<<<<<<<<<
4918 14:44:23.888408 [Flow] Enable top DCM control >>>>>
4919 14:44:23.891915 [Flow] Enable top DCM control <<<<<
4920 14:44:23.895439 Enable DLL master slave shuffle
4921 14:44:23.901839 ==============================================================
4922 14:44:23.901955 Gating Mode config
4923 14:44:23.908353 ==============================================================
4924 14:44:23.911843 Config description:
4925 14:44:23.921061 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4926 14:44:23.928037 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4927 14:44:23.931473 SELPH_MODE 0: By rank 1: By Phase
4928 14:44:23.937585 ==============================================================
4929 14:44:23.940985 GAT_TRACK_EN = 1
4930 14:44:23.944179 RX_GATING_MODE = 2
4931 14:44:23.947905 RX_GATING_TRACK_MODE = 2
4932 14:44:23.950674 SELPH_MODE = 1
4933 14:44:23.950765 PICG_EARLY_EN = 1
4934 14:44:23.954397 VALID_LAT_VALUE = 1
4935 14:44:23.961119 ==============================================================
4936 14:44:23.963798 Enter into Gating configuration >>>>
4937 14:44:23.966890 Exit from Gating configuration <<<<
4938 14:44:23.970469 Enter into DVFS_PRE_config >>>>>
4939 14:44:23.980585 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4940 14:44:23.984420 Exit from DVFS_PRE_config <<<<<
4941 14:44:23.986931 Enter into PICG configuration >>>>
4942 14:44:23.990723 Exit from PICG configuration <<<<
4943 14:44:23.993401 [RX_INPUT] configuration >>>>>
4944 14:44:23.996553 [RX_INPUT] configuration <<<<<
4945 14:44:24.003676 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4946 14:44:24.006405 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4947 14:44:24.013442 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4948 14:44:24.019810 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4949 14:44:24.026571 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4950 14:44:24.032965 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4951 14:44:24.036395 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4952 14:44:24.039394 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4953 14:44:24.042960 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4954 14:44:24.049390 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4955 14:44:24.052864 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4956 14:44:24.056027 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4957 14:44:24.059182 ===================================
4958 14:44:24.062676 LPDDR4 DRAM CONFIGURATION
4959 14:44:24.066319 ===================================
4960 14:44:24.069428 EX_ROW_EN[0] = 0x0
4961 14:44:24.069521 EX_ROW_EN[1] = 0x0
4962 14:44:24.072745 LP4Y_EN = 0x0
4963 14:44:24.072855 WORK_FSP = 0x0
4964 14:44:24.075777 WL = 0x3
4965 14:44:24.075861 RL = 0x3
4966 14:44:24.079748 BL = 0x2
4967 14:44:24.079841 RPST = 0x0
4968 14:44:24.082625 RD_PRE = 0x0
4969 14:44:24.082709 WR_PRE = 0x1
4970 14:44:24.086379 WR_PST = 0x0
4971 14:44:24.086468 DBI_WR = 0x0
4972 14:44:24.089451 DBI_RD = 0x0
4973 14:44:24.089549 OTF = 0x1
4974 14:44:24.092795 ===================================
4975 14:44:24.098817 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4976 14:44:24.102385 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4977 14:44:24.105287 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4978 14:44:24.108808 ===================================
4979 14:44:24.112267 LPDDR4 DRAM CONFIGURATION
4980 14:44:24.116002 ===================================
4981 14:44:24.118873 EX_ROW_EN[0] = 0x10
4982 14:44:24.118965 EX_ROW_EN[1] = 0x0
4983 14:44:24.121936 LP4Y_EN = 0x0
4984 14:44:24.122024 WORK_FSP = 0x0
4985 14:44:24.124937 WL = 0x3
4986 14:44:24.125021 RL = 0x3
4987 14:44:24.128383 BL = 0x2
4988 14:44:24.128469 RPST = 0x0
4989 14:44:24.132004 RD_PRE = 0x0
4990 14:44:24.132088 WR_PRE = 0x1
4991 14:44:24.135050 WR_PST = 0x0
4992 14:44:24.135132 DBI_WR = 0x0
4993 14:44:24.138640 DBI_RD = 0x0
4994 14:44:24.138723 OTF = 0x1
4995 14:44:24.142244 ===================================
4996 14:44:24.148185 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4997 14:44:24.153109 nWR fixed to 30
4998 14:44:24.156267 [ModeRegInit_LP4] CH0 RK0
4999 14:44:24.156366 [ModeRegInit_LP4] CH0 RK1
5000 14:44:24.159990 [ModeRegInit_LP4] CH1 RK0
5001 14:44:24.163456 [ModeRegInit_LP4] CH1 RK1
5002 14:44:24.163547 match AC timing 9
5003 14:44:24.169821 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5004 14:44:24.173147 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5005 14:44:24.176718 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5006 14:44:24.183919 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5007 14:44:24.186790 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5008 14:44:24.186883 ==
5009 14:44:24.189178 Dram Type= 6, Freq= 0, CH_0, rank 0
5010 14:44:24.192886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5011 14:44:24.193000 ==
5012 14:44:24.199252 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5013 14:44:24.205978 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5014 14:44:24.209389 [CA 0] Center 38 (7~69) winsize 63
5015 14:44:24.212359 [CA 1] Center 37 (7~68) winsize 62
5016 14:44:24.215650 [CA 2] Center 34 (4~65) winsize 62
5017 14:44:24.219580 [CA 3] Center 34 (4~65) winsize 62
5018 14:44:24.222341 [CA 4] Center 33 (2~64) winsize 63
5019 14:44:24.225686 [CA 5] Center 32 (2~63) winsize 62
5020 14:44:24.225808
5021 14:44:24.228785 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5022 14:44:24.228870
5023 14:44:24.232276 [CATrainingPosCal] consider 1 rank data
5024 14:44:24.235910 u2DelayCellTimex100 = 270/100 ps
5025 14:44:24.238732 CA0 delay=38 (7~69),Diff = 6 PI (37 cell)
5026 14:44:24.241931 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5027 14:44:24.245662 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5028 14:44:24.252218 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5029 14:44:24.255155 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5030 14:44:24.258588 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5031 14:44:24.258701
5032 14:44:24.262304 CA PerBit enable=1, Macro0, CA PI delay=32
5033 14:44:24.262391
5034 14:44:24.265382 [CBTSetCACLKResult] CA Dly = 32
5035 14:44:24.265469 CS Dly: 6 (0~37)
5036 14:44:24.265535 ==
5037 14:44:24.268494 Dram Type= 6, Freq= 0, CH_0, rank 1
5038 14:44:24.275426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5039 14:44:24.275532 ==
5040 14:44:24.278368 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5041 14:44:24.285486 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5042 14:44:24.288397 [CA 0] Center 38 (8~69) winsize 62
5043 14:44:24.292155 [CA 1] Center 38 (7~69) winsize 63
5044 14:44:24.294968 [CA 2] Center 34 (4~65) winsize 62
5045 14:44:24.298368 [CA 3] Center 34 (4~65) winsize 62
5046 14:44:24.301910 [CA 4] Center 33 (3~64) winsize 62
5047 14:44:24.304868 [CA 5] Center 33 (3~63) winsize 61
5048 14:44:24.304956
5049 14:44:24.308395 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5050 14:44:24.308482
5051 14:44:24.311517 [CATrainingPosCal] consider 2 rank data
5052 14:44:24.314746 u2DelayCellTimex100 = 270/100 ps
5053 14:44:24.318308 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5054 14:44:24.324831 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5055 14:44:24.328110 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5056 14:44:24.331480 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5057 14:44:24.334468 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5058 14:44:24.337926 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5059 14:44:24.338016
5060 14:44:24.341376 CA PerBit enable=1, Macro0, CA PI delay=33
5061 14:44:24.341468
5062 14:44:24.344390 [CBTSetCACLKResult] CA Dly = 33
5063 14:44:24.348138 CS Dly: 7 (0~39)
5064 14:44:24.348228
5065 14:44:24.351106 ----->DramcWriteLeveling(PI) begin...
5066 14:44:24.351192 ==
5067 14:44:24.354279 Dram Type= 6, Freq= 0, CH_0, rank 0
5068 14:44:24.358232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5069 14:44:24.358324 ==
5070 14:44:24.360789 Write leveling (Byte 0): 29 => 29
5071 14:44:24.364541 Write leveling (Byte 1): 28 => 28
5072 14:44:24.367848 DramcWriteLeveling(PI) end<-----
5073 14:44:24.367934
5074 14:44:24.367999 ==
5075 14:44:24.370594 Dram Type= 6, Freq= 0, CH_0, rank 0
5076 14:44:24.374124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5077 14:44:24.374208 ==
5078 14:44:24.377469 [Gating] SW mode calibration
5079 14:44:24.384051 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5080 14:44:24.390496 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5081 14:44:24.393866 0 14 0 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
5082 14:44:24.400232 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5083 14:44:24.404196 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5084 14:44:24.407411 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5085 14:44:24.413704 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5086 14:44:24.416648 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5087 14:44:24.419992 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5088 14:44:24.426423 0 14 28 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
5089 14:44:24.429858 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5090 14:44:24.432912 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5091 14:44:24.439742 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5092 14:44:24.443380 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5093 14:44:24.446554 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5094 14:44:24.453891 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5095 14:44:24.456504 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5096 14:44:24.459900 0 15 28 | B1->B0 | 2727 3b3b | 0 0 | (0 0) (0 0)
5097 14:44:24.466175 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5098 14:44:24.469490 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5099 14:44:24.473023 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5100 14:44:24.479413 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5101 14:44:24.482678 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5102 14:44:24.485947 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5103 14:44:24.492993 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5104 14:44:24.495748 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5105 14:44:24.499363 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5106 14:44:24.505392 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5107 14:44:24.509552 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5108 14:44:24.512356 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5109 14:44:24.518880 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5110 14:44:24.522069 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5111 14:44:24.525251 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5112 14:44:24.532116 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5113 14:44:24.535334 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5114 14:44:24.539009 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 14:44:24.545129 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 14:44:24.548504 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 14:44:24.551747 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 14:44:24.558309 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 14:44:24.561620 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5120 14:44:24.565120 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5121 14:44:24.568264 Total UI for P1: 0, mck2ui 16
5122 14:44:24.571734 best dqsien dly found for B0: ( 1, 2, 24)
5123 14:44:24.575058 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5124 14:44:24.581462 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 14:44:24.584857 Total UI for P1: 0, mck2ui 16
5126 14:44:24.588078 best dqsien dly found for B1: ( 1, 2, 30)
5127 14:44:24.591230 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5128 14:44:24.594815 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5129 14:44:24.594926
5130 14:44:24.597933 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5131 14:44:24.601671 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5132 14:44:24.604300 [Gating] SW calibration Done
5133 14:44:24.604411 ==
5134 14:44:24.607617 Dram Type= 6, Freq= 0, CH_0, rank 0
5135 14:44:24.611047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 14:44:24.614730 ==
5137 14:44:24.614842 RX Vref Scan: 0
5138 14:44:24.614935
5139 14:44:24.617459 RX Vref 0 -> 0, step: 1
5140 14:44:24.617566
5141 14:44:24.620851 RX Delay -80 -> 252, step: 8
5142 14:44:24.624228 iDelay=200, Bit 0, Center 107 (16 ~ 199) 184
5143 14:44:24.627686 iDelay=200, Bit 1, Center 107 (16 ~ 199) 184
5144 14:44:24.631516 iDelay=200, Bit 2, Center 99 (8 ~ 191) 184
5145 14:44:24.634149 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5146 14:44:24.640630 iDelay=200, Bit 4, Center 107 (16 ~ 199) 184
5147 14:44:24.644020 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5148 14:44:24.646955 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5149 14:44:24.650626 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5150 14:44:24.653859 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5151 14:44:24.656954 iDelay=200, Bit 9, Center 71 (-24 ~ 167) 192
5152 14:44:24.664136 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5153 14:44:24.667293 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5154 14:44:24.670884 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5155 14:44:24.673892 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5156 14:44:24.676729 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5157 14:44:24.683326 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5158 14:44:24.683429 ==
5159 14:44:24.686509 Dram Type= 6, Freq= 0, CH_0, rank 0
5160 14:44:24.689961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5161 14:44:24.690047 ==
5162 14:44:24.690111 DQS Delay:
5163 14:44:24.693289 DQS0 = 0, DQS1 = 0
5164 14:44:24.693388 DQM Delay:
5165 14:44:24.696382 DQM0 = 103, DQM1 = 87
5166 14:44:24.696465 DQ Delay:
5167 14:44:24.699862 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5168 14:44:24.702967 DQ4 =107, DQ5 =91, DQ6 =107, DQ7 =107
5169 14:44:24.706388 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =79
5170 14:44:24.709776 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5171 14:44:24.709864
5172 14:44:24.709928
5173 14:44:24.709985 ==
5174 14:44:24.713132 Dram Type= 6, Freq= 0, CH_0, rank 0
5175 14:44:24.720083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5176 14:44:24.720182 ==
5177 14:44:24.720269
5178 14:44:24.720349
5179 14:44:24.720426 TX Vref Scan disable
5180 14:44:24.723145 == TX Byte 0 ==
5181 14:44:24.726550 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5182 14:44:24.733479 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5183 14:44:24.733577 == TX Byte 1 ==
5184 14:44:24.736176 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5185 14:44:24.742726 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5186 14:44:24.742819 ==
5187 14:44:24.746433 Dram Type= 6, Freq= 0, CH_0, rank 0
5188 14:44:24.749587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5189 14:44:24.749675 ==
5190 14:44:24.749740
5191 14:44:24.749800
5192 14:44:24.752757 TX Vref Scan disable
5193 14:44:24.752842 == TX Byte 0 ==
5194 14:44:24.759384 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5195 14:44:24.762822 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5196 14:44:24.762915 == TX Byte 1 ==
5197 14:44:24.769549 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5198 14:44:24.773082 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5199 14:44:24.773196
5200 14:44:24.773325 [DATLAT]
5201 14:44:24.775946 Freq=933, CH0 RK0
5202 14:44:24.776030
5203 14:44:24.776095 DATLAT Default: 0xd
5204 14:44:24.779440 0, 0xFFFF, sum = 0
5205 14:44:24.779527 1, 0xFFFF, sum = 0
5206 14:44:24.782769 2, 0xFFFF, sum = 0
5207 14:44:24.786043 3, 0xFFFF, sum = 0
5208 14:44:24.786132 4, 0xFFFF, sum = 0
5209 14:44:24.789175 5, 0xFFFF, sum = 0
5210 14:44:24.789323 6, 0xFFFF, sum = 0
5211 14:44:24.792561 7, 0xFFFF, sum = 0
5212 14:44:24.792647 8, 0xFFFF, sum = 0
5213 14:44:24.795627 9, 0xFFFF, sum = 0
5214 14:44:24.795711 10, 0x0, sum = 1
5215 14:44:24.798884 11, 0x0, sum = 2
5216 14:44:24.798971 12, 0x0, sum = 3
5217 14:44:24.802370 13, 0x0, sum = 4
5218 14:44:24.802456 best_step = 11
5219 14:44:24.802521
5220 14:44:24.802581 ==
5221 14:44:24.805398 Dram Type= 6, Freq= 0, CH_0, rank 0
5222 14:44:24.808939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5223 14:44:24.809025 ==
5224 14:44:24.812799 RX Vref Scan: 1
5225 14:44:24.812884
5226 14:44:24.815519 RX Vref 0 -> 0, step: 1
5227 14:44:24.815603
5228 14:44:24.815668 RX Delay -69 -> 252, step: 4
5229 14:44:24.818810
5230 14:44:24.818894 Set Vref, RX VrefLevel [Byte0]: 55
5231 14:44:24.822277 [Byte1]: 52
5232 14:44:24.827303
5233 14:44:24.827391 Final RX Vref Byte 0 = 55 to rank0
5234 14:44:24.830246 Final RX Vref Byte 1 = 52 to rank0
5235 14:44:24.833483 Final RX Vref Byte 0 = 55 to rank1
5236 14:44:24.837007 Final RX Vref Byte 1 = 52 to rank1==
5237 14:44:24.840145 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 14:44:24.846763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 14:44:24.846863 ==
5240 14:44:24.846929 DQS Delay:
5241 14:44:24.850020 DQS0 = 0, DQS1 = 0
5242 14:44:24.850106 DQM Delay:
5243 14:44:24.850171 DQM0 = 102, DQM1 = 89
5244 14:44:24.854018 DQ Delay:
5245 14:44:24.856718 DQ0 =104, DQ1 =102, DQ2 =98, DQ3 =100
5246 14:44:24.860232 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =106
5247 14:44:24.863792 DQ8 =82, DQ9 =76, DQ10 =90, DQ11 =86
5248 14:44:24.867033 DQ12 =98, DQ13 =92, DQ14 =96, DQ15 =96
5249 14:44:24.867125
5250 14:44:24.867211
5251 14:44:24.873252 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d17, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 412 ps
5252 14:44:24.876836 CH0 RK0: MR19=505, MR18=1D17
5253 14:44:24.883549 CH0_RK0: MR19=0x505, MR18=0x1D17, DQSOSC=412, MR23=63, INC=63, DEC=42
5254 14:44:24.883655
5255 14:44:24.886814 ----->DramcWriteLeveling(PI) begin...
5256 14:44:24.886904 ==
5257 14:44:24.889998 Dram Type= 6, Freq= 0, CH_0, rank 1
5258 14:44:24.892759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 14:44:24.896317 ==
5260 14:44:24.896405 Write leveling (Byte 0): 29 => 29
5261 14:44:24.899545 Write leveling (Byte 1): 25 => 25
5262 14:44:24.902647 DramcWriteLeveling(PI) end<-----
5263 14:44:24.902737
5264 14:44:24.902821 ==
5265 14:44:24.906358 Dram Type= 6, Freq= 0, CH_0, rank 1
5266 14:44:24.913555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 14:44:24.913660 ==
5268 14:44:24.916175 [Gating] SW mode calibration
5269 14:44:24.922608 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5270 14:44:24.926137 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5271 14:44:24.932913 0 14 0 | B1->B0 | 2929 3434 | 0 0 | (1 1) (0 0)
5272 14:44:24.936441 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5273 14:44:24.939032 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5274 14:44:24.946222 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5275 14:44:24.948988 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5276 14:44:24.952453 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5277 14:44:24.958974 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
5278 14:44:24.962237 0 14 28 | B1->B0 | 3333 2c2c | 0 0 | (1 0) (0 0)
5279 14:44:24.965700 0 15 0 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (0 0)
5280 14:44:24.972234 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5281 14:44:24.975299 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5282 14:44:24.978773 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5283 14:44:24.985326 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5284 14:44:24.988589 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5285 14:44:24.992874 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5286 14:44:24.998695 0 15 28 | B1->B0 | 2525 3d3d | 0 1 | (1 1) (0 0)
5287 14:44:25.001780 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5288 14:44:25.004955 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5289 14:44:25.011654 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5290 14:44:25.014853 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5291 14:44:25.018176 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5292 14:44:25.025041 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5293 14:44:25.028119 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5294 14:44:25.031271 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5295 14:44:25.038095 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5296 14:44:25.041241 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5297 14:44:25.044756 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5298 14:44:25.051058 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5299 14:44:25.055125 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5300 14:44:25.057486 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5301 14:44:25.064781 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5302 14:44:25.067591 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5303 14:44:25.070815 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5304 14:44:25.077304 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5305 14:44:25.080677 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5306 14:44:25.084161 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 14:44:25.090327 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 14:44:25.094053 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 14:44:25.097739 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5310 14:44:25.103432 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5311 14:44:25.107126 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 14:44:25.110640 Total UI for P1: 0, mck2ui 16
5313 14:44:25.113795 best dqsien dly found for B0: ( 1, 2, 26)
5314 14:44:25.116975 Total UI for P1: 0, mck2ui 16
5315 14:44:25.120272 best dqsien dly found for B1: ( 1, 2, 30)
5316 14:44:25.123749 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5317 14:44:25.126605 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5318 14:44:25.126695
5319 14:44:25.130021 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5320 14:44:25.133513 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5321 14:44:25.137415 [Gating] SW calibration Done
5322 14:44:25.137509 ==
5323 14:44:25.140148 Dram Type= 6, Freq= 0, CH_0, rank 1
5324 14:44:25.146290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5325 14:44:25.146399 ==
5326 14:44:25.146465 RX Vref Scan: 0
5327 14:44:25.146526
5328 14:44:25.149704 RX Vref 0 -> 0, step: 1
5329 14:44:25.149819
5330 14:44:25.152925 RX Delay -80 -> 252, step: 8
5331 14:44:25.156024 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5332 14:44:25.160027 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5333 14:44:25.163231 iDelay=200, Bit 2, Center 99 (8 ~ 191) 184
5334 14:44:25.166723 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5335 14:44:25.172904 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5336 14:44:25.176188 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5337 14:44:25.179478 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5338 14:44:25.182511 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5339 14:44:25.185901 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5340 14:44:25.189208 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5341 14:44:25.196240 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5342 14:44:25.199360 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5343 14:44:25.202486 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5344 14:44:25.205693 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5345 14:44:25.209460 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5346 14:44:25.215683 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5347 14:44:25.215780 ==
5348 14:44:25.218907 Dram Type= 6, Freq= 0, CH_0, rank 1
5349 14:44:25.222387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5350 14:44:25.222476 ==
5351 14:44:25.222541 DQS Delay:
5352 14:44:25.225843 DQS0 = 0, DQS1 = 0
5353 14:44:25.225932 DQM Delay:
5354 14:44:25.229208 DQM0 = 100, DQM1 = 89
5355 14:44:25.229345 DQ Delay:
5356 14:44:25.232286 DQ0 =99, DQ1 =103, DQ2 =99, DQ3 =99
5357 14:44:25.235924 DQ4 =99, DQ5 =91, DQ6 =107, DQ7 =107
5358 14:44:25.238978 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5359 14:44:25.242979 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5360 14:44:25.243067
5361 14:44:25.243130
5362 14:44:25.243189 ==
5363 14:44:25.246043 Dram Type= 6, Freq= 0, CH_0, rank 1
5364 14:44:25.249086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5365 14:44:25.249198 ==
5366 14:44:25.252720
5367 14:44:25.252805
5368 14:44:25.252869 TX Vref Scan disable
5369 14:44:25.255260 == TX Byte 0 ==
5370 14:44:25.259091 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5371 14:44:25.261859 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5372 14:44:25.265068 == TX Byte 1 ==
5373 14:44:25.268885 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5374 14:44:25.271989 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5375 14:44:25.272075 ==
5376 14:44:25.275030 Dram Type= 6, Freq= 0, CH_0, rank 1
5377 14:44:25.281677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5378 14:44:25.281779 ==
5379 14:44:25.281845
5380 14:44:25.281904
5381 14:44:25.284774 TX Vref Scan disable
5382 14:44:25.284859 == TX Byte 0 ==
5383 14:44:25.291416 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5384 14:44:25.295899 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5385 14:44:25.295990 == TX Byte 1 ==
5386 14:44:25.301884 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5387 14:44:25.305401 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5388 14:44:25.305497
5389 14:44:25.305563 [DATLAT]
5390 14:44:25.307898 Freq=933, CH0 RK1
5391 14:44:25.307983
5392 14:44:25.308047 DATLAT Default: 0xb
5393 14:44:25.311459 0, 0xFFFF, sum = 0
5394 14:44:25.311548 1, 0xFFFF, sum = 0
5395 14:44:25.314685 2, 0xFFFF, sum = 0
5396 14:44:25.314772 3, 0xFFFF, sum = 0
5397 14:44:25.318209 4, 0xFFFF, sum = 0
5398 14:44:25.318324 5, 0xFFFF, sum = 0
5399 14:44:25.321132 6, 0xFFFF, sum = 0
5400 14:44:25.324692 7, 0xFFFF, sum = 0
5401 14:44:25.324781 8, 0xFFFF, sum = 0
5402 14:44:25.327562 9, 0xFFFF, sum = 0
5403 14:44:25.327647 10, 0x0, sum = 1
5404 14:44:25.331370 11, 0x0, sum = 2
5405 14:44:25.331457 12, 0x0, sum = 3
5406 14:44:25.334449 13, 0x0, sum = 4
5407 14:44:25.334541 best_step = 11
5408 14:44:25.334607
5409 14:44:25.334669 ==
5410 14:44:25.337849 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 14:44:25.341173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 14:44:25.341330 ==
5413 14:44:25.344213 RX Vref Scan: 0
5414 14:44:25.344297
5415 14:44:25.347604 RX Vref 0 -> 0, step: 1
5416 14:44:25.347692
5417 14:44:25.347756 RX Delay -61 -> 252, step: 4
5418 14:44:25.355159 iDelay=195, Bit 0, Center 98 (15 ~ 182) 168
5419 14:44:25.358462 iDelay=195, Bit 1, Center 102 (15 ~ 190) 176
5420 14:44:25.361941 iDelay=195, Bit 2, Center 96 (11 ~ 182) 172
5421 14:44:25.365202 iDelay=195, Bit 3, Center 98 (11 ~ 186) 176
5422 14:44:25.368391 iDelay=195, Bit 4, Center 102 (15 ~ 190) 176
5423 14:44:25.375287 iDelay=195, Bit 5, Center 90 (3 ~ 178) 176
5424 14:44:25.378325 iDelay=195, Bit 6, Center 112 (31 ~ 194) 164
5425 14:44:25.381822 iDelay=195, Bit 7, Center 108 (23 ~ 194) 172
5426 14:44:25.384761 iDelay=195, Bit 8, Center 82 (-5 ~ 170) 176
5427 14:44:25.388074 iDelay=195, Bit 9, Center 78 (-9 ~ 166) 176
5428 14:44:25.394619 iDelay=195, Bit 10, Center 92 (7 ~ 178) 172
5429 14:44:25.397799 iDelay=195, Bit 11, Center 84 (-1 ~ 170) 172
5430 14:44:25.401246 iDelay=195, Bit 12, Center 96 (11 ~ 182) 172
5431 14:44:25.404902 iDelay=195, Bit 13, Center 96 (11 ~ 182) 172
5432 14:44:25.407816 iDelay=195, Bit 14, Center 102 (15 ~ 190) 176
5433 14:44:25.414358 iDelay=195, Bit 15, Center 96 (11 ~ 182) 172
5434 14:44:25.414471 ==
5435 14:44:25.417602 Dram Type= 6, Freq= 0, CH_0, rank 1
5436 14:44:25.420884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5437 14:44:25.420973 ==
5438 14:44:25.421039 DQS Delay:
5439 14:44:25.424388 DQS0 = 0, DQS1 = 0
5440 14:44:25.424474 DQM Delay:
5441 14:44:25.427698 DQM0 = 100, DQM1 = 90
5442 14:44:25.427780 DQ Delay:
5443 14:44:25.430893 DQ0 =98, DQ1 =102, DQ2 =96, DQ3 =98
5444 14:44:25.434345 DQ4 =102, DQ5 =90, DQ6 =112, DQ7 =108
5445 14:44:25.437955 DQ8 =82, DQ9 =78, DQ10 =92, DQ11 =84
5446 14:44:25.441090 DQ12 =96, DQ13 =96, DQ14 =102, DQ15 =96
5447 14:44:25.441181
5448 14:44:25.441245
5449 14:44:25.450560 [DQSOSCAuto] RK1, (LSB)MR18= 0x1410, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5450 14:44:25.450678 CH0 RK1: MR19=505, MR18=1410
5451 14:44:25.457237 CH0_RK1: MR19=0x505, MR18=0x1410, DQSOSC=415, MR23=63, INC=62, DEC=41
5452 14:44:25.460545 [RxdqsGatingPostProcess] freq 933
5453 14:44:25.466984 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5454 14:44:25.470362 best DQS0 dly(2T, 0.5T) = (0, 10)
5455 14:44:25.474132 best DQS1 dly(2T, 0.5T) = (0, 10)
5456 14:44:25.477191 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5457 14:44:25.480437 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5458 14:44:25.483896 best DQS0 dly(2T, 0.5T) = (0, 10)
5459 14:44:25.486965 best DQS1 dly(2T, 0.5T) = (0, 10)
5460 14:44:25.490175 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5461 14:44:25.493939 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5462 14:44:25.496814 Pre-setting of DQS Precalculation
5463 14:44:25.500119 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5464 14:44:25.500215 ==
5465 14:44:25.503191 Dram Type= 6, Freq= 0, CH_1, rank 0
5466 14:44:25.506840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5467 14:44:25.506927 ==
5468 14:44:25.513131 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5469 14:44:25.520293 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5470 14:44:25.523199 [CA 0] Center 36 (6~67) winsize 62
5471 14:44:25.526782 [CA 1] Center 36 (6~67) winsize 62
5472 14:44:25.529702 [CA 2] Center 34 (4~65) winsize 62
5473 14:44:25.533236 [CA 3] Center 33 (3~64) winsize 62
5474 14:44:25.536368 [CA 4] Center 34 (4~65) winsize 62
5475 14:44:25.539647 [CA 5] Center 33 (3~64) winsize 62
5476 14:44:25.539731
5477 14:44:25.542997 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5478 14:44:25.543080
5479 14:44:25.546325 [CATrainingPosCal] consider 1 rank data
5480 14:44:25.549597 u2DelayCellTimex100 = 270/100 ps
5481 14:44:25.552908 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5482 14:44:25.556064 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5483 14:44:25.559342 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5484 14:44:25.562712 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5485 14:44:25.569433 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5486 14:44:25.572502 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5487 14:44:25.572588
5488 14:44:25.576156 CA PerBit enable=1, Macro0, CA PI delay=33
5489 14:44:25.576240
5490 14:44:25.579138 [CBTSetCACLKResult] CA Dly = 33
5491 14:44:25.579222 CS Dly: 5 (0~36)
5492 14:44:25.579287 ==
5493 14:44:25.582249 Dram Type= 6, Freq= 0, CH_1, rank 1
5494 14:44:25.589109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5495 14:44:25.589206 ==
5496 14:44:25.592411 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5497 14:44:25.599082 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5498 14:44:25.602709 [CA 0] Center 36 (6~66) winsize 61
5499 14:44:25.605772 [CA 1] Center 36 (6~67) winsize 62
5500 14:44:25.609544 [CA 2] Center 34 (4~65) winsize 62
5501 14:44:25.612229 [CA 3] Center 33 (3~64) winsize 62
5502 14:44:25.615534 [CA 4] Center 33 (3~64) winsize 62
5503 14:44:25.618970 [CA 5] Center 33 (3~64) winsize 62
5504 14:44:25.619061
5505 14:44:25.623167 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5506 14:44:25.623257
5507 14:44:25.625442 [CATrainingPosCal] consider 2 rank data
5508 14:44:25.628506 u2DelayCellTimex100 = 270/100 ps
5509 14:44:25.631904 CA0 delay=36 (6~66),Diff = 3 PI (18 cell)
5510 14:44:25.638387 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5511 14:44:25.641676 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5512 14:44:25.644981 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5513 14:44:25.648172 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5514 14:44:25.651528 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5515 14:44:25.651617
5516 14:44:25.655279 CA PerBit enable=1, Macro0, CA PI delay=33
5517 14:44:25.655365
5518 14:44:25.658225 [CBTSetCACLKResult] CA Dly = 33
5519 14:44:25.658314 CS Dly: 5 (0~37)
5520 14:44:25.661586
5521 14:44:25.664960 ----->DramcWriteLeveling(PI) begin...
5522 14:44:25.665073 ==
5523 14:44:25.668237 Dram Type= 6, Freq= 0, CH_1, rank 0
5524 14:44:25.671332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5525 14:44:25.671459 ==
5526 14:44:25.674716 Write leveling (Byte 0): 26 => 26
5527 14:44:25.678233 Write leveling (Byte 1): 27 => 27
5528 14:44:25.681727 DramcWriteLeveling(PI) end<-----
5529 14:44:25.681815
5530 14:44:25.681879 ==
5531 14:44:25.684666 Dram Type= 6, Freq= 0, CH_1, rank 0
5532 14:44:25.687788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 14:44:25.687876 ==
5534 14:44:25.691902 [Gating] SW mode calibration
5535 14:44:25.697612 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5536 14:44:25.704500 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5537 14:44:25.707589 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5538 14:44:25.710831 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5539 14:44:25.717416 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5540 14:44:25.720749 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5541 14:44:25.724287 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5542 14:44:25.730840 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5543 14:44:25.734181 0 14 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5544 14:44:25.737530 0 14 28 | B1->B0 | 2d2d 2525 | 0 0 | (1 0) (1 0)
5545 14:44:25.743530 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5546 14:44:25.747487 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5547 14:44:25.750632 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5548 14:44:25.757625 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5549 14:44:25.760881 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5550 14:44:25.763585 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5551 14:44:25.770170 0 15 24 | B1->B0 | 2525 2d2d | 0 0 | (0 0) (0 0)
5552 14:44:25.773371 0 15 28 | B1->B0 | 3535 3c3c | 0 0 | (1 1) (0 0)
5553 14:44:25.776982 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5554 14:44:25.783437 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5555 14:44:25.786540 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5556 14:44:25.790382 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5557 14:44:25.796826 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5558 14:44:25.799577 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5559 14:44:25.803519 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5560 14:44:25.809735 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5561 14:44:25.812893 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5562 14:44:25.816039 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5563 14:44:25.822647 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 14:44:25.826123 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 14:44:25.829527 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 14:44:25.836086 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 14:44:25.839338 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 14:44:25.842611 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 14:44:25.848996 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 14:44:25.852581 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 14:44:25.856354 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 14:44:25.862875 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 14:44:25.865840 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 14:44:25.869408 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 14:44:25.875577 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 14:44:25.879406 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5577 14:44:25.882352 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 14:44:25.885504 Total UI for P1: 0, mck2ui 16
5579 14:44:25.888900 best dqsien dly found for B0: ( 1, 2, 28)
5580 14:44:25.891988 Total UI for P1: 0, mck2ui 16
5581 14:44:25.895300 best dqsien dly found for B1: ( 1, 2, 28)
5582 14:44:25.899020 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5583 14:44:25.905165 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5584 14:44:25.905320
5585 14:44:25.908464 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5586 14:44:25.912038 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5587 14:44:25.915323 [Gating] SW calibration Done
5588 14:44:25.915414 ==
5589 14:44:25.918913 Dram Type= 6, Freq= 0, CH_1, rank 0
5590 14:44:25.921806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5591 14:44:25.921901 ==
5592 14:44:25.925144 RX Vref Scan: 0
5593 14:44:25.925254
5594 14:44:25.925370 RX Vref 0 -> 0, step: 1
5595 14:44:25.925431
5596 14:44:25.928271 RX Delay -80 -> 252, step: 8
5597 14:44:25.931601 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5598 14:44:25.938235 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5599 14:44:25.941002 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5600 14:44:25.944873 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5601 14:44:25.948437 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5602 14:44:25.951338 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5603 14:44:25.954684 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5604 14:44:25.961247 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5605 14:44:25.964844 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5606 14:44:25.968423 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5607 14:44:25.971511 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5608 14:44:25.974514 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5609 14:44:25.977602 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5610 14:44:25.984464 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5611 14:44:25.987462 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5612 14:44:25.991125 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5613 14:44:25.991210 ==
5614 14:44:25.994385 Dram Type= 6, Freq= 0, CH_1, rank 0
5615 14:44:25.998549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5616 14:44:25.998637 ==
5617 14:44:26.001088 DQS Delay:
5618 14:44:26.001170 DQS0 = 0, DQS1 = 0
5619 14:44:26.003930 DQM Delay:
5620 14:44:26.004013 DQM0 = 99, DQM1 = 96
5621 14:44:26.004078 DQ Delay:
5622 14:44:26.007441 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5623 14:44:26.010928 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5624 14:44:26.013985 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5625 14:44:26.020417 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5626 14:44:26.020504
5627 14:44:26.020568
5628 14:44:26.020627 ==
5629 14:44:26.023900 Dram Type= 6, Freq= 0, CH_1, rank 0
5630 14:44:26.026912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5631 14:44:26.026996 ==
5632 14:44:26.027060
5633 14:44:26.027120
5634 14:44:26.030277 TX Vref Scan disable
5635 14:44:26.030360 == TX Byte 0 ==
5636 14:44:26.037210 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5637 14:44:26.040113 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5638 14:44:26.040202 == TX Byte 1 ==
5639 14:44:26.047133 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5640 14:44:26.050320 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5641 14:44:26.050466 ==
5642 14:44:26.053947 Dram Type= 6, Freq= 0, CH_1, rank 0
5643 14:44:26.056822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5644 14:44:26.056938 ==
5645 14:44:26.060056
5646 14:44:26.060218
5647 14:44:26.060285 TX Vref Scan disable
5648 14:44:26.063399 == TX Byte 0 ==
5649 14:44:26.066668 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5650 14:44:26.073532 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5651 14:44:26.073684 == TX Byte 1 ==
5652 14:44:26.076849 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5653 14:44:26.082912 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5654 14:44:26.083058
5655 14:44:26.083127 [DATLAT]
5656 14:44:26.083187 Freq=933, CH1 RK0
5657 14:44:26.083246
5658 14:44:26.086749 DATLAT Default: 0xd
5659 14:44:26.089492 0, 0xFFFF, sum = 0
5660 14:44:26.089601 1, 0xFFFF, sum = 0
5661 14:44:26.092676 2, 0xFFFF, sum = 0
5662 14:44:26.092781 3, 0xFFFF, sum = 0
5663 14:44:26.096360 4, 0xFFFF, sum = 0
5664 14:44:26.096449 5, 0xFFFF, sum = 0
5665 14:44:26.099261 6, 0xFFFF, sum = 0
5666 14:44:26.099345 7, 0xFFFF, sum = 0
5667 14:44:26.102614 8, 0xFFFF, sum = 0
5668 14:44:26.102700 9, 0xFFFF, sum = 0
5669 14:44:26.105789 10, 0x0, sum = 1
5670 14:44:26.105873 11, 0x0, sum = 2
5671 14:44:26.109181 12, 0x0, sum = 3
5672 14:44:26.109290 13, 0x0, sum = 4
5673 14:44:26.113061 best_step = 11
5674 14:44:26.113145
5675 14:44:26.113209 ==
5676 14:44:26.115937 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 14:44:26.119250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 14:44:26.119337 ==
5679 14:44:26.119402 RX Vref Scan: 1
5680 14:44:26.122571
5681 14:44:26.122655 RX Vref 0 -> 0, step: 1
5682 14:44:26.122720
5683 14:44:26.126326 RX Delay -53 -> 252, step: 4
5684 14:44:26.126408
5685 14:44:26.128778 Set Vref, RX VrefLevel [Byte0]: 51
5686 14:44:26.132345 [Byte1]: 52
5687 14:44:26.136109
5688 14:44:26.136193 Final RX Vref Byte 0 = 51 to rank0
5689 14:44:26.139781 Final RX Vref Byte 1 = 52 to rank0
5690 14:44:26.142512 Final RX Vref Byte 0 = 51 to rank1
5691 14:44:26.145423 Final RX Vref Byte 1 = 52 to rank1==
5692 14:44:26.148839 Dram Type= 6, Freq= 0, CH_1, rank 0
5693 14:44:26.155649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5694 14:44:26.155743 ==
5695 14:44:26.155808 DQS Delay:
5696 14:44:26.158913 DQS0 = 0, DQS1 = 0
5697 14:44:26.158998 DQM Delay:
5698 14:44:26.159062 DQM0 = 99, DQM1 = 94
5699 14:44:26.162002 DQ Delay:
5700 14:44:26.165208 DQ0 =106, DQ1 =94, DQ2 =86, DQ3 =100
5701 14:44:26.168907 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5702 14:44:26.172014 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =88
5703 14:44:26.175620 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =104
5704 14:44:26.175707
5705 14:44:26.175771
5706 14:44:26.181818 [DQSOSCAuto] RK0, (LSB)MR18= 0xc1b, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 418 ps
5707 14:44:26.185150 CH1 RK0: MR19=505, MR18=C1B
5708 14:44:26.191902 CH1_RK0: MR19=0x505, MR18=0xC1B, DQSOSC=413, MR23=63, INC=63, DEC=42
5709 14:44:26.191998
5710 14:44:26.195584 ----->DramcWriteLeveling(PI) begin...
5711 14:44:26.195712 ==
5712 14:44:26.198615 Dram Type= 6, Freq= 0, CH_1, rank 1
5713 14:44:26.202092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 14:44:26.202178 ==
5715 14:44:26.205268 Write leveling (Byte 0): 28 => 28
5716 14:44:26.208585 Write leveling (Byte 1): 27 => 27
5717 14:44:26.211954 DramcWriteLeveling(PI) end<-----
5718 14:44:26.212040
5719 14:44:26.212103 ==
5720 14:44:26.215075 Dram Type= 6, Freq= 0, CH_1, rank 1
5721 14:44:26.221687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 14:44:26.221776 ==
5723 14:44:26.221842 [Gating] SW mode calibration
5724 14:44:26.231318 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5725 14:44:26.234735 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5726 14:44:26.238229 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5727 14:44:26.244673 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5728 14:44:26.248256 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5729 14:44:26.251432 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5730 14:44:26.257543 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5731 14:44:26.261010 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5732 14:44:26.264486 0 14 24 | B1->B0 | 3030 2c2c | 0 0 | (0 1) (1 1)
5733 14:44:26.271013 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (1 0)
5734 14:44:26.274506 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5735 14:44:26.277492 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5736 14:44:26.284054 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5737 14:44:26.287327 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5738 14:44:26.290784 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5739 14:44:26.297188 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5740 14:44:26.300888 0 15 24 | B1->B0 | 2a2a 3636 | 0 0 | (1 1) (0 0)
5741 14:44:26.307223 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
5742 14:44:26.310764 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5743 14:44:26.313879 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5744 14:44:26.320181 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5745 14:44:26.323852 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5746 14:44:26.326841 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5747 14:44:26.333567 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5748 14:44:26.336724 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5749 14:44:26.340957 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5750 14:44:26.346624 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5751 14:44:26.349833 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5752 14:44:26.353532 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5753 14:44:26.359602 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5754 14:44:26.363127 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5755 14:44:26.366219 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5756 14:44:26.373306 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5757 14:44:26.376331 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5758 14:44:26.379326 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5759 14:44:26.386690 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5760 14:44:26.389414 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5761 14:44:26.392400 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 14:44:26.399154 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 14:44:26.403219 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 14:44:26.405827 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5765 14:44:26.412894 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5766 14:44:26.412999 Total UI for P1: 0, mck2ui 16
5767 14:44:26.419656 best dqsien dly found for B0: ( 1, 2, 24)
5768 14:44:26.421984 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 14:44:26.425192 Total UI for P1: 0, mck2ui 16
5770 14:44:26.429267 best dqsien dly found for B1: ( 1, 2, 28)
5771 14:44:26.432270 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5772 14:44:26.435270 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5773 14:44:26.435412
5774 14:44:26.438344 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5775 14:44:26.442130 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5776 14:44:26.445143 [Gating] SW calibration Done
5777 14:44:26.445311 ==
5778 14:44:26.448385 Dram Type= 6, Freq= 0, CH_1, rank 1
5779 14:44:26.455074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 14:44:26.455255 ==
5781 14:44:26.455355 RX Vref Scan: 0
5782 14:44:26.455445
5783 14:44:26.458063 RX Vref 0 -> 0, step: 1
5784 14:44:26.458175
5785 14:44:26.461283 RX Delay -80 -> 252, step: 8
5786 14:44:26.464584 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5787 14:44:26.467875 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5788 14:44:26.471509 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5789 14:44:26.474452 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5790 14:44:26.481112 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5791 14:44:26.484795 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5792 14:44:26.488002 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5793 14:44:26.491632 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5794 14:44:26.494562 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5795 14:44:26.497319 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5796 14:44:26.504040 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5797 14:44:26.507698 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5798 14:44:26.510566 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5799 14:44:26.513928 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5800 14:44:26.517523 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5801 14:44:26.524033 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5802 14:44:26.524166 ==
5803 14:44:26.527564 Dram Type= 6, Freq= 0, CH_1, rank 1
5804 14:44:26.530826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5805 14:44:26.530932 ==
5806 14:44:26.531000 DQS Delay:
5807 14:44:26.533994 DQS0 = 0, DQS1 = 0
5808 14:44:26.534096 DQM Delay:
5809 14:44:26.537484 DQM0 = 97, DQM1 = 94
5810 14:44:26.537579 DQ Delay:
5811 14:44:26.540634 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =95
5812 14:44:26.543501 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5813 14:44:26.546999 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5814 14:44:26.550681 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5815 14:44:26.550789
5816 14:44:26.550854
5817 14:44:26.550913 ==
5818 14:44:26.553760 Dram Type= 6, Freq= 0, CH_1, rank 1
5819 14:44:26.559976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5820 14:44:26.560095 ==
5821 14:44:26.560164
5822 14:44:26.560224
5823 14:44:26.560303 TX Vref Scan disable
5824 14:44:26.564112 == TX Byte 0 ==
5825 14:44:26.567176 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5826 14:44:26.573315 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5827 14:44:26.573423 == TX Byte 1 ==
5828 14:44:26.576766 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5829 14:44:26.583682 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5830 14:44:26.583813 ==
5831 14:44:26.586688 Dram Type= 6, Freq= 0, CH_1, rank 1
5832 14:44:26.590146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5833 14:44:26.590248 ==
5834 14:44:26.590313
5835 14:44:26.590372
5836 14:44:26.593742 TX Vref Scan disable
5837 14:44:26.593837 == TX Byte 0 ==
5838 14:44:26.599914 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5839 14:44:26.603104 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5840 14:44:26.603224 == TX Byte 1 ==
5841 14:44:26.609994 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5842 14:44:26.613041 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5843 14:44:26.613153
5844 14:44:26.613220 [DATLAT]
5845 14:44:26.616556 Freq=933, CH1 RK1
5846 14:44:26.616652
5847 14:44:26.616717 DATLAT Default: 0xb
5848 14:44:26.619528 0, 0xFFFF, sum = 0
5849 14:44:26.619625 1, 0xFFFF, sum = 0
5850 14:44:26.623401 2, 0xFFFF, sum = 0
5851 14:44:26.626166 3, 0xFFFF, sum = 0
5852 14:44:26.626265 4, 0xFFFF, sum = 0
5853 14:44:26.629892 5, 0xFFFF, sum = 0
5854 14:44:26.629981 6, 0xFFFF, sum = 0
5855 14:44:26.633097 7, 0xFFFF, sum = 0
5856 14:44:26.633182 8, 0xFFFF, sum = 0
5857 14:44:26.636013 9, 0xFFFF, sum = 0
5858 14:44:26.636099 10, 0x0, sum = 1
5859 14:44:26.639377 11, 0x0, sum = 2
5860 14:44:26.639467 12, 0x0, sum = 3
5861 14:44:26.643001 13, 0x0, sum = 4
5862 14:44:26.643091 best_step = 11
5863 14:44:26.643163
5864 14:44:26.643222 ==
5865 14:44:26.645935 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 14:44:26.649368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 14:44:26.649453 ==
5868 14:44:26.652397 RX Vref Scan: 0
5869 14:44:26.652478
5870 14:44:26.655875 RX Vref 0 -> 0, step: 1
5871 14:44:26.655958
5872 14:44:26.656021 RX Delay -53 -> 252, step: 4
5873 14:44:26.663728 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5874 14:44:26.667081 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5875 14:44:26.670729 iDelay=199, Bit 2, Center 88 (-1 ~ 178) 180
5876 14:44:26.673478 iDelay=199, Bit 3, Center 96 (3 ~ 190) 188
5877 14:44:26.677050 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5878 14:44:26.683553 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5879 14:44:26.686812 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5880 14:44:26.690247 iDelay=199, Bit 7, Center 94 (3 ~ 186) 184
5881 14:44:26.693329 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5882 14:44:26.696801 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5883 14:44:26.700033 iDelay=199, Bit 10, Center 94 (3 ~ 186) 184
5884 14:44:26.706404 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5885 14:44:26.710234 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5886 14:44:26.712879 iDelay=199, Bit 13, Center 102 (11 ~ 194) 184
5887 14:44:26.716522 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5888 14:44:26.723049 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5889 14:44:26.723134 ==
5890 14:44:26.726096 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 14:44:26.729144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 14:44:26.729276 ==
5893 14:44:26.729429 DQS Delay:
5894 14:44:26.733147 DQS0 = 0, DQS1 = 0
5895 14:44:26.733233 DQM Delay:
5896 14:44:26.735759 DQM0 = 97, DQM1 = 93
5897 14:44:26.735843 DQ Delay:
5898 14:44:26.739727 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =96
5899 14:44:26.742347 DQ4 =96, DQ5 =106, DQ6 =106, DQ7 =94
5900 14:44:26.745700 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =86
5901 14:44:26.748979 DQ12 =100, DQ13 =102, DQ14 =98, DQ15 =102
5902 14:44:26.749126
5903 14:44:26.749192
5904 14:44:26.758819 [DQSOSCAuto] RK1, (LSB)MR18= 0xd24, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
5905 14:44:26.758973 CH1 RK1: MR19=505, MR18=D24
5906 14:44:26.765449 CH1_RK1: MR19=0x505, MR18=0xD24, DQSOSC=410, MR23=63, INC=64, DEC=42
5907 14:44:26.768750 [RxdqsGatingPostProcess] freq 933
5908 14:44:26.775565 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5909 14:44:26.779082 best DQS0 dly(2T, 0.5T) = (0, 10)
5910 14:44:26.782268 best DQS1 dly(2T, 0.5T) = (0, 10)
5911 14:44:26.785839 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5912 14:44:26.788676 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5913 14:44:26.791921 best DQS0 dly(2T, 0.5T) = (0, 10)
5914 14:44:26.795667 best DQS1 dly(2T, 0.5T) = (0, 10)
5915 14:44:26.798902 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5916 14:44:26.801866 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5917 14:44:26.801949 Pre-setting of DQS Precalculation
5918 14:44:26.808534 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5919 14:44:26.814807 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5920 14:44:26.821916 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5921 14:44:26.822004
5922 14:44:26.822068
5923 14:44:26.825518 [Calibration Summary] 1866 Mbps
5924 14:44:26.828207 CH 0, Rank 0
5925 14:44:26.828288 SW Impedance : PASS
5926 14:44:26.831848 DUTY Scan : NO K
5927 14:44:26.834791 ZQ Calibration : PASS
5928 14:44:26.834988 Jitter Meter : NO K
5929 14:44:26.838221 CBT Training : PASS
5930 14:44:26.841480 Write leveling : PASS
5931 14:44:26.841624 RX DQS gating : PASS
5932 14:44:26.844490 RX DQ/DQS(RDDQC) : PASS
5933 14:44:26.848050 TX DQ/DQS : PASS
5934 14:44:26.848201 RX DATLAT : PASS
5935 14:44:26.851165 RX DQ/DQS(Engine): PASS
5936 14:44:26.854423 TX OE : NO K
5937 14:44:26.854550 All Pass.
5938 14:44:26.854659
5939 14:44:26.854761 CH 0, Rank 1
5940 14:44:26.857836 SW Impedance : PASS
5941 14:44:26.861209 DUTY Scan : NO K
5942 14:44:26.861361 ZQ Calibration : PASS
5943 14:44:26.864344 Jitter Meter : NO K
5944 14:44:26.864488 CBT Training : PASS
5945 14:44:26.867481 Write leveling : PASS
5946 14:44:26.871172 RX DQS gating : PASS
5947 14:44:26.871303 RX DQ/DQS(RDDQC) : PASS
5948 14:44:26.874232 TX DQ/DQS : PASS
5949 14:44:26.877808 RX DATLAT : PASS
5950 14:44:26.877938 RX DQ/DQS(Engine): PASS
5951 14:44:26.881359 TX OE : NO K
5952 14:44:26.881505 All Pass.
5953 14:44:26.881617
5954 14:44:26.884397 CH 1, Rank 0
5955 14:44:26.884517 SW Impedance : PASS
5956 14:44:26.887693 DUTY Scan : NO K
5957 14:44:26.891362 ZQ Calibration : PASS
5958 14:44:26.891458 Jitter Meter : NO K
5959 14:44:26.894003 CBT Training : PASS
5960 14:44:26.897215 Write leveling : PASS
5961 14:44:26.897326 RX DQS gating : PASS
5962 14:44:26.900636 RX DQ/DQS(RDDQC) : PASS
5963 14:44:26.903984 TX DQ/DQS : PASS
5964 14:44:26.904079 RX DATLAT : PASS
5965 14:44:26.907015 RX DQ/DQS(Engine): PASS
5966 14:44:26.910381 TX OE : NO K
5967 14:44:26.910472 All Pass.
5968 14:44:26.910536
5969 14:44:26.910596 CH 1, Rank 1
5970 14:44:26.913725 SW Impedance : PASS
5971 14:44:26.917026 DUTY Scan : NO K
5972 14:44:26.917113 ZQ Calibration : PASS
5973 14:44:26.920600 Jitter Meter : NO K
5974 14:44:26.923669 CBT Training : PASS
5975 14:44:26.923761 Write leveling : PASS
5976 14:44:26.927230 RX DQS gating : PASS
5977 14:44:26.930084 RX DQ/DQS(RDDQC) : PASS
5978 14:44:26.930184 TX DQ/DQS : PASS
5979 14:44:26.934313 RX DATLAT : PASS
5980 14:44:26.934410 RX DQ/DQS(Engine): PASS
5981 14:44:26.937146 TX OE : NO K
5982 14:44:26.937240 All Pass.
5983 14:44:26.937336
5984 14:44:26.940217 DramC Write-DBI off
5985 14:44:26.943486 PER_BANK_REFRESH: Hybrid Mode
5986 14:44:26.943583 TX_TRACKING: ON
5987 14:44:26.953220 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5988 14:44:26.956969 [FAST_K] Save calibration result to emmc
5989 14:44:26.960153 dramc_set_vcore_voltage set vcore to 650000
5990 14:44:26.963161 Read voltage for 400, 6
5991 14:44:26.963269 Vio18 = 0
5992 14:44:26.966807 Vcore = 650000
5993 14:44:26.966901 Vdram = 0
5994 14:44:26.966999 Vddq = 0
5995 14:44:26.967097 Vmddr = 0
5996 14:44:26.973547 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5997 14:44:26.979817 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5998 14:44:26.979906 MEM_TYPE=3, freq_sel=20
5999 14:44:26.982702 sv_algorithm_assistance_LP4_800
6000 14:44:26.989457 ============ PULL DRAM RESETB DOWN ============
6001 14:44:26.992723 ========== PULL DRAM RESETB DOWN end =========
6002 14:44:26.995960 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6003 14:44:26.999635 ===================================
6004 14:44:27.002970 LPDDR4 DRAM CONFIGURATION
6005 14:44:27.006031 ===================================
6006 14:44:27.006114 EX_ROW_EN[0] = 0x0
6007 14:44:27.009569 EX_ROW_EN[1] = 0x0
6008 14:44:27.012394 LP4Y_EN = 0x0
6009 14:44:27.012475 WORK_FSP = 0x0
6010 14:44:27.016212 WL = 0x2
6011 14:44:27.016292 RL = 0x2
6012 14:44:27.019158 BL = 0x2
6013 14:44:27.019312 RPST = 0x0
6014 14:44:27.022592 RD_PRE = 0x0
6015 14:44:27.022673 WR_PRE = 0x1
6016 14:44:27.025999 WR_PST = 0x0
6017 14:44:27.026079 DBI_WR = 0x0
6018 14:44:27.028753 DBI_RD = 0x0
6019 14:44:27.028833 OTF = 0x1
6020 14:44:27.032482 ===================================
6021 14:44:27.035986 ===================================
6022 14:44:27.039311 ANA top config
6023 14:44:27.042181 ===================================
6024 14:44:27.045658 DLL_ASYNC_EN = 0
6025 14:44:27.045742 ALL_SLAVE_EN = 1
6026 14:44:27.048967 NEW_RANK_MODE = 1
6027 14:44:27.052055 DLL_IDLE_MODE = 1
6028 14:44:27.055823 LP45_APHY_COMB_EN = 1
6029 14:44:27.055907 TX_ODT_DIS = 1
6030 14:44:27.059119 NEW_8X_MODE = 1
6031 14:44:27.061791 ===================================
6032 14:44:27.065249 ===================================
6033 14:44:27.068660 data_rate = 800
6034 14:44:27.072161 CKR = 1
6035 14:44:27.075024 DQ_P2S_RATIO = 4
6036 14:44:27.078400 ===================================
6037 14:44:27.082445 CA_P2S_RATIO = 4
6038 14:44:27.082531 DQ_CA_OPEN = 0
6039 14:44:27.085150 DQ_SEMI_OPEN = 1
6040 14:44:27.088047 CA_SEMI_OPEN = 1
6041 14:44:27.091581 CA_FULL_RATE = 0
6042 14:44:27.094905 DQ_CKDIV4_EN = 0
6043 14:44:27.098145 CA_CKDIV4_EN = 1
6044 14:44:27.101409 CA_PREDIV_EN = 0
6045 14:44:27.101493 PH8_DLY = 0
6046 14:44:27.104762 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6047 14:44:27.107956 DQ_AAMCK_DIV = 0
6048 14:44:27.111253 CA_AAMCK_DIV = 0
6049 14:44:27.114875 CA_ADMCK_DIV = 4
6050 14:44:27.118096 DQ_TRACK_CA_EN = 0
6051 14:44:27.118180 CA_PICK = 800
6052 14:44:27.121661 CA_MCKIO = 400
6053 14:44:27.124350 MCKIO_SEMI = 400
6054 14:44:27.127964 PLL_FREQ = 3016
6055 14:44:27.131255 DQ_UI_PI_RATIO = 32
6056 14:44:27.135448 CA_UI_PI_RATIO = 32
6057 14:44:27.137721 ===================================
6058 14:44:27.141163 ===================================
6059 14:44:27.145180 memory_type:LPDDR4
6060 14:44:27.145289 GP_NUM : 10
6061 14:44:27.147917 SRAM_EN : 1
6062 14:44:27.148001 MD32_EN : 0
6063 14:44:27.151021 ===================================
6064 14:44:27.154317 [ANA_INIT] >>>>>>>>>>>>>>
6065 14:44:27.157830 <<<<<< [CONFIGURE PHASE]: ANA_TX
6066 14:44:27.161424 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6067 14:44:27.164236 ===================================
6068 14:44:27.167548 data_rate = 800,PCW = 0X7400
6069 14:44:27.170930 ===================================
6070 14:44:27.174273 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6071 14:44:27.180572 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6072 14:44:27.190677 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6073 14:44:27.193898 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6074 14:44:27.200378 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6075 14:44:27.203882 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6076 14:44:27.204250 [ANA_INIT] flow start
6077 14:44:27.206860 [ANA_INIT] PLL >>>>>>>>
6078 14:44:27.210443 [ANA_INIT] PLL <<<<<<<<
6079 14:44:27.210940 [ANA_INIT] MIDPI >>>>>>>>
6080 14:44:27.213902 [ANA_INIT] MIDPI <<<<<<<<
6081 14:44:27.217013 [ANA_INIT] DLL >>>>>>>>
6082 14:44:27.217413 [ANA_INIT] flow end
6083 14:44:27.223660 ============ LP4 DIFF to SE enter ============
6084 14:44:27.226906 ============ LP4 DIFF to SE exit ============
6085 14:44:27.227387 [ANA_INIT] <<<<<<<<<<<<<
6086 14:44:27.229899 [Flow] Enable top DCM control >>>>>
6087 14:44:27.233904 [Flow] Enable top DCM control <<<<<
6088 14:44:27.236816 Enable DLL master slave shuffle
6089 14:44:27.243341 ==============================================================
6090 14:44:27.247436 Gating Mode config
6091 14:44:27.250447 ==============================================================
6092 14:44:27.253201 Config description:
6093 14:44:27.263039 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6094 14:44:27.269876 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6095 14:44:27.273083 SELPH_MODE 0: By rank 1: By Phase
6096 14:44:27.279378 ==============================================================
6097 14:44:27.283112 GAT_TRACK_EN = 0
6098 14:44:27.286002 RX_GATING_MODE = 2
6099 14:44:27.289615 RX_GATING_TRACK_MODE = 2
6100 14:44:27.292266 SELPH_MODE = 1
6101 14:44:27.295726 PICG_EARLY_EN = 1
6102 14:44:27.295951 VALID_LAT_VALUE = 1
6103 14:44:27.302237 ==============================================================
6104 14:44:27.305393 Enter into Gating configuration >>>>
6105 14:44:27.308720 Exit from Gating configuration <<<<
6106 14:44:27.311982 Enter into DVFS_PRE_config >>>>>
6107 14:44:27.324961 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6108 14:44:27.325100 Exit from DVFS_PRE_config <<<<<
6109 14:44:27.328624 Enter into PICG configuration >>>>
6110 14:44:27.331627 Exit from PICG configuration <<<<
6111 14:44:27.335051 [RX_INPUT] configuration >>>>>
6112 14:44:27.338234 [RX_INPUT] configuration <<<<<
6113 14:44:27.345537 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6114 14:44:27.348140 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6115 14:44:27.355583 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6116 14:44:27.361122 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6117 14:44:27.367708 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6118 14:44:27.374845 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6119 14:44:27.377945 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6120 14:44:27.381012 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6121 14:44:27.384606 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6122 14:44:27.392141 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6123 14:44:27.394286 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6124 14:44:27.397932 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6125 14:44:27.401356 ===================================
6126 14:44:27.405049 LPDDR4 DRAM CONFIGURATION
6127 14:44:27.407647 ===================================
6128 14:44:27.411447 EX_ROW_EN[0] = 0x0
6129 14:44:27.411530 EX_ROW_EN[1] = 0x0
6130 14:44:27.413964 LP4Y_EN = 0x0
6131 14:44:27.414048 WORK_FSP = 0x0
6132 14:44:27.417177 WL = 0x2
6133 14:44:27.417322 RL = 0x2
6134 14:44:27.421020 BL = 0x2
6135 14:44:27.421103 RPST = 0x0
6136 14:44:27.424006 RD_PRE = 0x0
6137 14:44:27.424094 WR_PRE = 0x1
6138 14:44:27.426982 WR_PST = 0x0
6139 14:44:27.427065 DBI_WR = 0x0
6140 14:44:27.430489 DBI_RD = 0x0
6141 14:44:27.433957 OTF = 0x1
6142 14:44:27.436861 ===================================
6143 14:44:27.440491 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6144 14:44:27.443483 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6145 14:44:27.447046 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6146 14:44:27.450469 ===================================
6147 14:44:27.453288 LPDDR4 DRAM CONFIGURATION
6148 14:44:27.457410 ===================================
6149 14:44:27.460470 EX_ROW_EN[0] = 0x10
6150 14:44:27.460553 EX_ROW_EN[1] = 0x0
6151 14:44:27.463663 LP4Y_EN = 0x0
6152 14:44:27.463752 WORK_FSP = 0x0
6153 14:44:27.467242 WL = 0x2
6154 14:44:27.467324 RL = 0x2
6155 14:44:27.469828 BL = 0x2
6156 14:44:27.469910 RPST = 0x0
6157 14:44:27.473302 RD_PRE = 0x0
6158 14:44:27.473398 WR_PRE = 0x1
6159 14:44:27.476405 WR_PST = 0x0
6160 14:44:27.476487 DBI_WR = 0x0
6161 14:44:27.480103 DBI_RD = 0x0
6162 14:44:27.483234 OTF = 0x1
6163 14:44:27.486739 ===================================
6164 14:44:27.490067 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6165 14:44:27.495290 nWR fixed to 30
6166 14:44:27.498259 [ModeRegInit_LP4] CH0 RK0
6167 14:44:27.498341 [ModeRegInit_LP4] CH0 RK1
6168 14:44:27.501885 [ModeRegInit_LP4] CH1 RK0
6169 14:44:27.504652 [ModeRegInit_LP4] CH1 RK1
6170 14:44:27.504732 match AC timing 19
6171 14:44:27.511842 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6172 14:44:27.515192 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6173 14:44:27.518128 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6174 14:44:27.524699 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6175 14:44:27.528583 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6176 14:44:27.528665 ==
6177 14:44:27.531295 Dram Type= 6, Freq= 0, CH_0, rank 0
6178 14:44:27.534568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6179 14:44:27.534650 ==
6180 14:44:27.541044 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6181 14:44:27.548038 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6182 14:44:27.551150 [CA 0] Center 36 (8~64) winsize 57
6183 14:44:27.554715 [CA 1] Center 36 (8~64) winsize 57
6184 14:44:27.557778 [CA 2] Center 36 (8~64) winsize 57
6185 14:44:27.560822 [CA 3] Center 36 (8~64) winsize 57
6186 14:44:27.564120 [CA 4] Center 36 (8~64) winsize 57
6187 14:44:27.564202 [CA 5] Center 36 (8~64) winsize 57
6188 14:44:27.567349
6189 14:44:27.571103 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6190 14:44:27.571185
6191 14:44:27.574056 [CATrainingPosCal] consider 1 rank data
6192 14:44:27.577645 u2DelayCellTimex100 = 270/100 ps
6193 14:44:27.581529 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6194 14:44:27.584615 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6195 14:44:27.587290 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6196 14:44:27.590513 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6197 14:44:27.593775 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6198 14:44:27.597228 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6199 14:44:27.597351
6200 14:44:27.600726 CA PerBit enable=1, Macro0, CA PI delay=36
6201 14:44:27.603957
6202 14:44:27.604037 [CBTSetCACLKResult] CA Dly = 36
6203 14:44:27.606929 CS Dly: 1 (0~32)
6204 14:44:27.607011 ==
6205 14:44:27.610716 Dram Type= 6, Freq= 0, CH_0, rank 1
6206 14:44:27.613707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6207 14:44:27.613789 ==
6208 14:44:27.620219 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6209 14:44:27.626947 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6210 14:44:27.630349 [CA 0] Center 36 (8~64) winsize 57
6211 14:44:27.634379 [CA 1] Center 36 (8~64) winsize 57
6212 14:44:27.636711 [CA 2] Center 36 (8~64) winsize 57
6213 14:44:27.636791 [CA 3] Center 36 (8~64) winsize 57
6214 14:44:27.640312 [CA 4] Center 36 (8~64) winsize 57
6215 14:44:27.643722 [CA 5] Center 36 (8~64) winsize 57
6216 14:44:27.643804
6217 14:44:27.649930 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6218 14:44:27.650014
6219 14:44:27.653204 [CATrainingPosCal] consider 2 rank data
6220 14:44:27.656586 u2DelayCellTimex100 = 270/100 ps
6221 14:44:27.660291 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 14:44:27.663256 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 14:44:27.667491 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 14:44:27.669921 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 14:44:27.673375 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 14:44:27.676920 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 14:44:27.677126
6228 14:44:27.679730 CA PerBit enable=1, Macro0, CA PI delay=36
6229 14:44:27.679873
6230 14:44:27.682979 [CBTSetCACLKResult] CA Dly = 36
6231 14:44:27.686348 CS Dly: 1 (0~32)
6232 14:44:27.686490
6233 14:44:27.689741 ----->DramcWriteLeveling(PI) begin...
6234 14:44:27.689915 ==
6235 14:44:27.692962 Dram Type= 6, Freq= 0, CH_0, rank 0
6236 14:44:27.696454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6237 14:44:27.696543 ==
6238 14:44:27.699708 Write leveling (Byte 0): 40 => 8
6239 14:44:27.702930 Write leveling (Byte 1): 40 => 8
6240 14:44:27.706376 DramcWriteLeveling(PI) end<-----
6241 14:44:27.706542
6242 14:44:27.706620 ==
6243 14:44:27.709912 Dram Type= 6, Freq= 0, CH_0, rank 0
6244 14:44:27.712605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6245 14:44:27.712701 ==
6246 14:44:27.716559 [Gating] SW mode calibration
6247 14:44:27.722335 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6248 14:44:27.728959 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6249 14:44:27.732561 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6250 14:44:27.738858 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6251 14:44:27.742385 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6252 14:44:27.745697 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6253 14:44:27.752389 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6254 14:44:27.755770 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6255 14:44:27.758717 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6256 14:44:27.765466 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6257 14:44:27.768661 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6258 14:44:27.771965 Total UI for P1: 0, mck2ui 16
6259 14:44:27.775534 best dqsien dly found for B0: ( 0, 14, 24)
6260 14:44:27.778677 Total UI for P1: 0, mck2ui 16
6261 14:44:27.781979 best dqsien dly found for B1: ( 0, 14, 24)
6262 14:44:27.785019 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6263 14:44:27.788700 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6264 14:44:27.788787
6265 14:44:27.791958 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6266 14:44:27.795398 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6267 14:44:27.798548 [Gating] SW calibration Done
6268 14:44:27.798634 ==
6269 14:44:27.801812 Dram Type= 6, Freq= 0, CH_0, rank 0
6270 14:44:27.808048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6271 14:44:27.808140 ==
6272 14:44:27.808207 RX Vref Scan: 0
6273 14:44:27.808266
6274 14:44:27.811279 RX Vref 0 -> 0, step: 1
6275 14:44:27.811362
6276 14:44:27.814454 RX Delay -410 -> 252, step: 16
6277 14:44:27.818234 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6278 14:44:27.821500 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6279 14:44:27.827802 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6280 14:44:27.831943 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6281 14:44:27.834457 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6282 14:44:27.837736 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6283 14:44:27.844809 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6284 14:44:27.847623 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6285 14:44:27.850845 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6286 14:44:27.854144 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6287 14:44:27.860759 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6288 14:44:27.863859 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6289 14:44:27.867700 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6290 14:44:27.870737 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6291 14:44:27.877213 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6292 14:44:27.881051 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6293 14:44:27.881228 ==
6294 14:44:27.883876 Dram Type= 6, Freq= 0, CH_0, rank 0
6295 14:44:27.887353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 14:44:27.887437 ==
6297 14:44:27.890911 DQS Delay:
6298 14:44:27.891070 DQS0 = 35, DQS1 = 59
6299 14:44:27.894237 DQM Delay:
6300 14:44:27.894395 DQM0 = 6, DQM1 = 17
6301 14:44:27.894463 DQ Delay:
6302 14:44:27.897329 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6303 14:44:27.900731 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6304 14:44:27.903801 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6305 14:44:27.907111 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6306 14:44:27.907462
6307 14:44:27.907737
6308 14:44:27.907992 ==
6309 14:44:27.910367 Dram Type= 6, Freq= 0, CH_0, rank 0
6310 14:44:27.917211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6311 14:44:27.917584 ==
6312 14:44:27.917859
6313 14:44:27.918114
6314 14:44:27.918357 TX Vref Scan disable
6315 14:44:27.920578 == TX Byte 0 ==
6316 14:44:27.923820 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6317 14:44:27.927126 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6318 14:44:27.930525 == TX Byte 1 ==
6319 14:44:27.933915 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6320 14:44:27.937061 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6321 14:44:27.940392 ==
6322 14:44:27.940842 Dram Type= 6, Freq= 0, CH_0, rank 0
6323 14:44:27.946649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6324 14:44:27.947122 ==
6325 14:44:27.947486
6326 14:44:27.947783
6327 14:44:27.949981 TX Vref Scan disable
6328 14:44:27.950358 == TX Byte 0 ==
6329 14:44:27.953581 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6330 14:44:27.959844 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6331 14:44:27.960335 == TX Byte 1 ==
6332 14:44:27.963520 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6333 14:44:27.969674 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6334 14:44:27.970055
6335 14:44:27.970347 [DATLAT]
6336 14:44:27.970622 Freq=400, CH0 RK0
6337 14:44:27.970897
6338 14:44:27.972967 DATLAT Default: 0xf
6339 14:44:27.973523 0, 0xFFFF, sum = 0
6340 14:44:27.976496 1, 0xFFFF, sum = 0
6341 14:44:27.979704 2, 0xFFFF, sum = 0
6342 14:44:27.980084 3, 0xFFFF, sum = 0
6343 14:44:27.983203 4, 0xFFFF, sum = 0
6344 14:44:27.983586 5, 0xFFFF, sum = 0
6345 14:44:27.986215 6, 0xFFFF, sum = 0
6346 14:44:27.986601 7, 0xFFFF, sum = 0
6347 14:44:27.989670 8, 0xFFFF, sum = 0
6348 14:44:27.990022 9, 0xFFFF, sum = 0
6349 14:44:27.992996 10, 0xFFFF, sum = 0
6350 14:44:27.993705 11, 0xFFFF, sum = 0
6351 14:44:27.996245 12, 0xFFFF, sum = 0
6352 14:44:27.996617 13, 0x0, sum = 1
6353 14:44:27.999194 14, 0x0, sum = 2
6354 14:44:27.999551 15, 0x0, sum = 3
6355 14:44:28.002467 16, 0x0, sum = 4
6356 14:44:28.002870 best_step = 14
6357 14:44:28.003257
6358 14:44:28.003713 ==
6359 14:44:28.005872 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 14:44:28.012537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 14:44:28.012895 ==
6362 14:44:28.013168 RX Vref Scan: 1
6363 14:44:28.013471
6364 14:44:28.016339 RX Vref 0 -> 0, step: 1
6365 14:44:28.016725
6366 14:44:28.019245 RX Delay -359 -> 252, step: 8
6367 14:44:28.019845
6368 14:44:28.022199 Set Vref, RX VrefLevel [Byte0]: 55
6369 14:44:28.025630 [Byte1]: 52
6370 14:44:28.026127
6371 14:44:28.028941 Final RX Vref Byte 0 = 55 to rank0
6372 14:44:28.032191 Final RX Vref Byte 1 = 52 to rank0
6373 14:44:28.035443 Final RX Vref Byte 0 = 55 to rank1
6374 14:44:28.038952 Final RX Vref Byte 1 = 52 to rank1==
6375 14:44:28.042069 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 14:44:28.048629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 14:44:28.048978 ==
6378 14:44:28.049250 DQS Delay:
6379 14:44:28.049539 DQS0 = 44, DQS1 = 60
6380 14:44:28.052369 DQM Delay:
6381 14:44:28.052716 DQM0 = 10, DQM1 = 16
6382 14:44:28.055874 DQ Delay:
6383 14:44:28.058806 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6384 14:44:28.059211 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =12
6385 14:44:28.061902 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =12
6386 14:44:28.065002 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =24
6387 14:44:28.068517
6388 14:44:28.068865
6389 14:44:28.075196 [DQSOSCAuto] RK0, (LSB)MR18= 0x978b, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
6390 14:44:28.078170 CH0 RK0: MR19=C0C, MR18=978B
6391 14:44:28.085068 CH0_RK0: MR19=0xC0C, MR18=0x978B, DQSOSC=390, MR23=63, INC=388, DEC=258
6392 14:44:28.085537 ==
6393 14:44:28.088387 Dram Type= 6, Freq= 0, CH_0, rank 1
6394 14:44:28.091799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 14:44:28.092180 ==
6396 14:44:28.095296 [Gating] SW mode calibration
6397 14:44:28.101426 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6398 14:44:28.108147 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6399 14:44:28.111265 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6400 14:44:28.115173 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6401 14:44:28.121041 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6402 14:44:28.124733 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6403 14:44:28.127952 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6404 14:44:28.134485 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6405 14:44:28.137596 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6406 14:44:28.140864 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6407 14:44:28.147649 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6408 14:44:28.148036 Total UI for P1: 0, mck2ui 16
6409 14:44:28.154639 best dqsien dly found for B0: ( 0, 14, 24)
6410 14:44:28.155025 Total UI for P1: 0, mck2ui 16
6411 14:44:28.160970 best dqsien dly found for B1: ( 0, 14, 24)
6412 14:44:28.164111 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6413 14:44:28.167284 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6414 14:44:28.167818
6415 14:44:28.170770 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6416 14:44:28.174022 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6417 14:44:28.177979 [Gating] SW calibration Done
6418 14:44:28.178519 ==
6419 14:44:28.181043 Dram Type= 6, Freq= 0, CH_0, rank 1
6420 14:44:28.183837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 14:44:28.184407 ==
6422 14:44:28.187924 RX Vref Scan: 0
6423 14:44:28.188307
6424 14:44:28.190262 RX Vref 0 -> 0, step: 1
6425 14:44:28.190643
6426 14:44:28.190945 RX Delay -410 -> 252, step: 16
6427 14:44:28.196858 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6428 14:44:28.200156 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6429 14:44:28.204079 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6430 14:44:28.210746 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6431 14:44:28.213646 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6432 14:44:28.217201 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6433 14:44:28.220302 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6434 14:44:28.227535 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6435 14:44:28.229845 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6436 14:44:28.233142 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6437 14:44:28.236668 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6438 14:44:28.243416 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6439 14:44:28.246297 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6440 14:44:28.249804 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6441 14:44:28.253551 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6442 14:44:28.259546 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6443 14:44:28.260010 ==
6444 14:44:28.262947 Dram Type= 6, Freq= 0, CH_0, rank 1
6445 14:44:28.266721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 14:44:28.267103 ==
6447 14:44:28.269768 DQS Delay:
6448 14:44:28.270146 DQS0 = 35, DQS1 = 59
6449 14:44:28.270444 DQM Delay:
6450 14:44:28.273051 DQM0 = 5, DQM1 = 17
6451 14:44:28.273609 DQ Delay:
6452 14:44:28.275894 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6453 14:44:28.279644 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6454 14:44:28.282334 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6455 14:44:28.286095 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6456 14:44:28.286510
6457 14:44:28.286830
6458 14:44:28.287125 ==
6459 14:44:28.288919 Dram Type= 6, Freq= 0, CH_0, rank 1
6460 14:44:28.292841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 14:44:28.293290 ==
6462 14:44:28.295903
6463 14:44:28.296278
6464 14:44:28.296571 TX Vref Scan disable
6465 14:44:28.298955 == TX Byte 0 ==
6466 14:44:28.302255 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6467 14:44:28.305785 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6468 14:44:28.309146 == TX Byte 1 ==
6469 14:44:28.312833 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6470 14:44:28.315102 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6471 14:44:28.315524 ==
6472 14:44:28.318552 Dram Type= 6, Freq= 0, CH_0, rank 1
6473 14:44:28.325498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6474 14:44:28.326002 ==
6475 14:44:28.326316
6476 14:44:28.326594
6477 14:44:28.326886 TX Vref Scan disable
6478 14:44:28.328975 == TX Byte 0 ==
6479 14:44:28.332068 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6480 14:44:28.335023 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6481 14:44:28.338749 == TX Byte 1 ==
6482 14:44:28.341627 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6483 14:44:28.345179 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6484 14:44:28.345748
6485 14:44:28.348459 [DATLAT]
6486 14:44:28.348840 Freq=400, CH0 RK1
6487 14:44:28.349145
6488 14:44:28.351666 DATLAT Default: 0xe
6489 14:44:28.352082 0, 0xFFFF, sum = 0
6490 14:44:28.355546 1, 0xFFFF, sum = 0
6491 14:44:28.356155 2, 0xFFFF, sum = 0
6492 14:44:28.358484 3, 0xFFFF, sum = 0
6493 14:44:28.358904 4, 0xFFFF, sum = 0
6494 14:44:28.361650 5, 0xFFFF, sum = 0
6495 14:44:28.362205 6, 0xFFFF, sum = 0
6496 14:44:28.364753 7, 0xFFFF, sum = 0
6497 14:44:28.365179 8, 0xFFFF, sum = 0
6498 14:44:28.368230 9, 0xFFFF, sum = 0
6499 14:44:28.368672 10, 0xFFFF, sum = 0
6500 14:44:28.371437 11, 0xFFFF, sum = 0
6501 14:44:28.374919 12, 0xFFFF, sum = 0
6502 14:44:28.375341 13, 0x0, sum = 1
6503 14:44:28.378580 14, 0x0, sum = 2
6504 14:44:28.379113 15, 0x0, sum = 3
6505 14:44:28.379460 16, 0x0, sum = 4
6506 14:44:28.382307 best_step = 14
6507 14:44:28.382731
6508 14:44:28.383057 ==
6509 14:44:28.385014 Dram Type= 6, Freq= 0, CH_0, rank 1
6510 14:44:28.388032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 14:44:28.388460 ==
6512 14:44:28.391389 RX Vref Scan: 0
6513 14:44:28.391809
6514 14:44:28.394400 RX Vref 0 -> 0, step: 1
6515 14:44:28.394822
6516 14:44:28.395151 RX Delay -359 -> 252, step: 8
6517 14:44:28.403017 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6518 14:44:28.406249 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6519 14:44:28.409979 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6520 14:44:28.413452 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6521 14:44:28.420012 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6522 14:44:28.423153 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6523 14:44:28.426601 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6524 14:44:28.429901 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6525 14:44:28.437762 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6526 14:44:28.439606 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6527 14:44:28.442983 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6528 14:44:28.449244 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6529 14:44:28.452310 iDelay=209, Bit 12, Center -40 (-287 ~ 208) 496
6530 14:44:28.456773 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6531 14:44:28.459411 iDelay=209, Bit 14, Center -32 (-271 ~ 208) 480
6532 14:44:28.465774 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6533 14:44:28.466347 ==
6534 14:44:28.468766 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 14:44:28.472374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 14:44:28.472765 ==
6537 14:44:28.473071 DQS Delay:
6538 14:44:28.475543 DQS0 = 44, DQS1 = 60
6539 14:44:28.476013 DQM Delay:
6540 14:44:28.478932 DQM0 = 9, DQM1 = 15
6541 14:44:28.479320 DQ Delay:
6542 14:44:28.482121 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6543 14:44:28.485689 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6544 14:44:28.488651 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6545 14:44:28.492125 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6546 14:44:28.492512
6547 14:44:28.492813
6548 14:44:28.502007 [DQSOSCAuto] RK1, (LSB)MR18= 0x8f87, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6549 14:44:28.502480 CH0 RK1: MR19=C0C, MR18=8F87
6550 14:44:28.508788 CH0_RK1: MR19=0xC0C, MR18=0x8F87, DQSOSC=391, MR23=63, INC=386, DEC=257
6551 14:44:28.511539 [RxdqsGatingPostProcess] freq 400
6552 14:44:28.518152 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6553 14:44:28.521628 best DQS0 dly(2T, 0.5T) = (0, 10)
6554 14:44:28.524933 best DQS1 dly(2T, 0.5T) = (0, 10)
6555 14:44:28.527888 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6556 14:44:28.531709 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6557 14:44:28.534709 best DQS0 dly(2T, 0.5T) = (0, 10)
6558 14:44:28.537753 best DQS1 dly(2T, 0.5T) = (0, 10)
6559 14:44:28.541608 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6560 14:44:28.544316 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6561 14:44:28.544704 Pre-setting of DQS Precalculation
6562 14:44:28.551778 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6563 14:44:28.552314 ==
6564 14:44:28.554512 Dram Type= 6, Freq= 0, CH_1, rank 0
6565 14:44:28.557895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6566 14:44:28.558323 ==
6567 14:44:28.564184 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6568 14:44:28.570895 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6569 14:44:28.573997 [CA 0] Center 36 (8~64) winsize 57
6570 14:44:28.577384 [CA 1] Center 36 (8~64) winsize 57
6571 14:44:28.580813 [CA 2] Center 36 (8~64) winsize 57
6572 14:44:28.584005 [CA 3] Center 36 (8~64) winsize 57
6573 14:44:28.587077 [CA 4] Center 36 (8~64) winsize 57
6574 14:44:28.587465 [CA 5] Center 36 (8~64) winsize 57
6575 14:44:28.590272
6576 14:44:28.594364 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6577 14:44:28.594754
6578 14:44:28.597865 [CATrainingPosCal] consider 1 rank data
6579 14:44:28.600245 u2DelayCellTimex100 = 270/100 ps
6580 14:44:28.603476 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6581 14:44:28.606963 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6582 14:44:28.610389 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6583 14:44:28.614026 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6584 14:44:28.616853 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6585 14:44:28.620396 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6586 14:44:28.620923
6587 14:44:28.623247 CA PerBit enable=1, Macro0, CA PI delay=36
6588 14:44:28.627146
6589 14:44:28.627695 [CBTSetCACLKResult] CA Dly = 36
6590 14:44:28.631058 CS Dly: 1 (0~32)
6591 14:44:28.631587 ==
6592 14:44:28.633502 Dram Type= 6, Freq= 0, CH_1, rank 1
6593 14:44:28.637092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6594 14:44:28.637690 ==
6595 14:44:28.643591 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6596 14:44:28.649743 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6597 14:44:28.653537 [CA 0] Center 36 (8~64) winsize 57
6598 14:44:28.656259 [CA 1] Center 36 (8~64) winsize 57
6599 14:44:28.660066 [CA 2] Center 36 (8~64) winsize 57
6600 14:44:28.663428 [CA 3] Center 36 (8~64) winsize 57
6601 14:44:28.663963 [CA 4] Center 36 (8~64) winsize 57
6602 14:44:28.666511 [CA 5] Center 36 (8~64) winsize 57
6603 14:44:28.667023
6604 14:44:28.673777 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6605 14:44:28.674199
6606 14:44:28.675983 [CATrainingPosCal] consider 2 rank data
6607 14:44:28.680023 u2DelayCellTimex100 = 270/100 ps
6608 14:44:28.682848 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 14:44:28.686523 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 14:44:28.689114 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 14:44:28.692421 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 14:44:28.696088 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 14:44:28.699401 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 14:44:28.699960
6615 14:44:28.702122 CA PerBit enable=1, Macro0, CA PI delay=36
6616 14:44:28.702546
6617 14:44:28.705746 [CBTSetCACLKResult] CA Dly = 36
6618 14:44:28.709158 CS Dly: 1 (0~32)
6619 14:44:28.709666
6620 14:44:28.712356 ----->DramcWriteLeveling(PI) begin...
6621 14:44:28.712783 ==
6622 14:44:28.715369 Dram Type= 6, Freq= 0, CH_1, rank 0
6623 14:44:28.718574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6624 14:44:28.719001 ==
6625 14:44:28.721823 Write leveling (Byte 0): 40 => 8
6626 14:44:28.725465 Write leveling (Byte 1): 40 => 8
6627 14:44:28.728699 DramcWriteLeveling(PI) end<-----
6628 14:44:28.729130
6629 14:44:28.729513 ==
6630 14:44:28.732318 Dram Type= 6, Freq= 0, CH_1, rank 0
6631 14:44:28.735359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6632 14:44:28.738866 ==
6633 14:44:28.739384 [Gating] SW mode calibration
6634 14:44:28.745235 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6635 14:44:28.751595 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6636 14:44:28.754837 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6637 14:44:28.761684 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6638 14:44:28.764768 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6639 14:44:28.768050 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6640 14:44:28.774761 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6641 14:44:28.777828 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6642 14:44:28.781090 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6643 14:44:28.787737 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6644 14:44:28.791283 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6645 14:44:28.794481 Total UI for P1: 0, mck2ui 16
6646 14:44:28.797608 best dqsien dly found for B0: ( 0, 14, 24)
6647 14:44:28.800894 Total UI for P1: 0, mck2ui 16
6648 14:44:28.803873 best dqsien dly found for B1: ( 0, 14, 24)
6649 14:44:28.807579 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6650 14:44:28.811017 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6651 14:44:28.811443
6652 14:44:28.814516 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6653 14:44:28.820713 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6654 14:44:28.821137 [Gating] SW calibration Done
6655 14:44:28.821499 ==
6656 14:44:28.823769 Dram Type= 6, Freq= 0, CH_1, rank 0
6657 14:44:28.830675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 14:44:28.831193 ==
6659 14:44:28.831530 RX Vref Scan: 0
6660 14:44:28.831840
6661 14:44:28.833539 RX Vref 0 -> 0, step: 1
6662 14:44:28.833963
6663 14:44:28.837197 RX Delay -410 -> 252, step: 16
6664 14:44:28.840677 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6665 14:44:28.843479 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6666 14:44:28.850090 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6667 14:44:28.853510 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6668 14:44:28.856896 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6669 14:44:28.863489 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6670 14:44:28.866771 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6671 14:44:28.869931 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6672 14:44:28.872880 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6673 14:44:28.879838 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6674 14:44:28.883184 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6675 14:44:28.886648 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6676 14:44:28.889461 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6677 14:44:28.896490 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6678 14:44:28.899760 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6679 14:44:28.902971 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6680 14:44:28.903397 ==
6681 14:44:28.906219 Dram Type= 6, Freq= 0, CH_1, rank 0
6682 14:44:28.912560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 14:44:28.913004 ==
6684 14:44:28.913381 DQS Delay:
6685 14:44:28.916129 DQS0 = 43, DQS1 = 51
6686 14:44:28.916554 DQM Delay:
6687 14:44:28.916885 DQM0 = 13, DQM1 = 14
6688 14:44:28.919699 DQ Delay:
6689 14:44:28.922498 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6690 14:44:28.922922 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6691 14:44:28.926244 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6692 14:44:28.928940 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =16
6693 14:44:28.929395
6694 14:44:28.932659
6695 14:44:28.933192 ==
6696 14:44:28.936505 Dram Type= 6, Freq= 0, CH_1, rank 0
6697 14:44:28.939324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6698 14:44:28.939831 ==
6699 14:44:28.940170
6700 14:44:28.940481
6701 14:44:28.942236 TX Vref Scan disable
6702 14:44:28.942672 == TX Byte 0 ==
6703 14:44:28.945754 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6704 14:44:28.952689 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6705 14:44:28.953217 == TX Byte 1 ==
6706 14:44:28.955540 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6707 14:44:28.962004 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6708 14:44:28.962429 ==
6709 14:44:28.965952 Dram Type= 6, Freq= 0, CH_1, rank 0
6710 14:44:28.968929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6711 14:44:28.969392 ==
6712 14:44:28.969733
6713 14:44:28.970039
6714 14:44:28.972314 TX Vref Scan disable
6715 14:44:28.972734 == TX Byte 0 ==
6716 14:44:28.975253 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6717 14:44:28.981941 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6718 14:44:28.982363 == TX Byte 1 ==
6719 14:44:28.984910 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6720 14:44:28.991733 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6721 14:44:28.992251
6722 14:44:28.992585 [DATLAT]
6723 14:44:28.995267 Freq=400, CH1 RK0
6724 14:44:28.995690
6725 14:44:28.996016 DATLAT Default: 0xf
6726 14:44:28.998174 0, 0xFFFF, sum = 0
6727 14:44:28.998603 1, 0xFFFF, sum = 0
6728 14:44:29.002181 2, 0xFFFF, sum = 0
6729 14:44:29.002709 3, 0xFFFF, sum = 0
6730 14:44:29.005335 4, 0xFFFF, sum = 0
6731 14:44:29.005765 5, 0xFFFF, sum = 0
6732 14:44:29.008367 6, 0xFFFF, sum = 0
6733 14:44:29.008963 7, 0xFFFF, sum = 0
6734 14:44:29.011632 8, 0xFFFF, sum = 0
6735 14:44:29.012168 9, 0xFFFF, sum = 0
6736 14:44:29.014685 10, 0xFFFF, sum = 0
6737 14:44:29.018520 11, 0xFFFF, sum = 0
6738 14:44:29.018977 12, 0xFFFF, sum = 0
6739 14:44:29.021635 13, 0x0, sum = 1
6740 14:44:29.022168 14, 0x0, sum = 2
6741 14:44:29.022511 15, 0x0, sum = 3
6742 14:44:29.024401 16, 0x0, sum = 4
6743 14:44:29.024831 best_step = 14
6744 14:44:29.025160
6745 14:44:29.028084 ==
6746 14:44:29.031985 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 14:44:29.034558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 14:44:29.034996 ==
6749 14:44:29.035327 RX Vref Scan: 1
6750 14:44:29.035635
6751 14:44:29.037802 RX Vref 0 -> 0, step: 1
6752 14:44:29.038225
6753 14:44:29.040912 RX Delay -343 -> 252, step: 8
6754 14:44:29.041355
6755 14:44:29.044695 Set Vref, RX VrefLevel [Byte0]: 51
6756 14:44:29.047475 [Byte1]: 52
6757 14:44:29.051820
6758 14:44:29.052340 Final RX Vref Byte 0 = 51 to rank0
6759 14:44:29.054581 Final RX Vref Byte 1 = 52 to rank0
6760 14:44:29.058046 Final RX Vref Byte 0 = 51 to rank1
6761 14:44:29.060980 Final RX Vref Byte 1 = 52 to rank1==
6762 14:44:29.065092 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 14:44:29.070978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 14:44:29.071421 ==
6765 14:44:29.071751 DQS Delay:
6766 14:44:29.074521 DQS0 = 44, DQS1 = 52
6767 14:44:29.074949 DQM Delay:
6768 14:44:29.075282 DQM0 = 11, DQM1 = 11
6769 14:44:29.078887 DQ Delay:
6770 14:44:29.080827 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6771 14:44:29.083990 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6772 14:44:29.084417 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6773 14:44:29.090669 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6774 14:44:29.091098
6775 14:44:29.091402
6776 14:44:29.097099 [DQSOSCAuto] RK0, (LSB)MR18= 0x6e96, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 395 ps
6777 14:44:29.100616 CH1 RK0: MR19=C0C, MR18=6E96
6778 14:44:29.107321 CH1_RK0: MR19=0xC0C, MR18=0x6E96, DQSOSC=391, MR23=63, INC=386, DEC=257
6779 14:44:29.107845 ==
6780 14:44:29.110536 Dram Type= 6, Freq= 0, CH_1, rank 1
6781 14:44:29.114009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 14:44:29.114402 ==
6783 14:44:29.117002 [Gating] SW mode calibration
6784 14:44:29.123920 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6785 14:44:29.130647 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6786 14:44:29.133823 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6787 14:44:29.137427 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6788 14:44:29.143846 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6789 14:44:29.147045 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6790 14:44:29.150589 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6791 14:44:29.157233 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6792 14:44:29.160221 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6793 14:44:29.163517 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6794 14:44:29.170002 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6795 14:44:29.170493 Total UI for P1: 0, mck2ui 16
6796 14:44:29.176527 best dqsien dly found for B0: ( 0, 14, 24)
6797 14:44:29.177072 Total UI for P1: 0, mck2ui 16
6798 14:44:29.183260 best dqsien dly found for B1: ( 0, 14, 24)
6799 14:44:29.186669 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6800 14:44:29.190046 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6801 14:44:29.190465
6802 14:44:29.193165 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6803 14:44:29.196688 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6804 14:44:29.200185 [Gating] SW calibration Done
6805 14:44:29.200698 ==
6806 14:44:29.203157 Dram Type= 6, Freq= 0, CH_1, rank 1
6807 14:44:29.206689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 14:44:29.207109 ==
6809 14:44:29.209863 RX Vref Scan: 0
6810 14:44:29.210368
6811 14:44:29.210700 RX Vref 0 -> 0, step: 1
6812 14:44:29.212882
6813 14:44:29.213392 RX Delay -410 -> 252, step: 16
6814 14:44:29.219591 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6815 14:44:29.222986 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6816 14:44:29.226165 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6817 14:44:29.232932 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6818 14:44:29.236092 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6819 14:44:29.239707 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6820 14:44:29.242776 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6821 14:44:29.246634 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6822 14:44:29.252632 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6823 14:44:29.255630 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6824 14:44:29.259160 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6825 14:44:29.265701 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6826 14:44:29.268860 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6827 14:44:29.272273 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6828 14:44:29.275856 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6829 14:44:29.282226 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6830 14:44:29.282651 ==
6831 14:44:29.285541 Dram Type= 6, Freq= 0, CH_1, rank 1
6832 14:44:29.288691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 14:44:29.289115 ==
6834 14:44:29.289561 DQS Delay:
6835 14:44:29.292123 DQS0 = 43, DQS1 = 51
6836 14:44:29.292544 DQM Delay:
6837 14:44:29.295731 DQM0 = 9, DQM1 = 14
6838 14:44:29.296154 DQ Delay:
6839 14:44:29.298782 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6840 14:44:29.302044 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6841 14:44:29.304957 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6842 14:44:29.308302 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6843 14:44:29.308720
6844 14:44:29.309041
6845 14:44:29.309376 ==
6846 14:44:29.312014 Dram Type= 6, Freq= 0, CH_1, rank 1
6847 14:44:29.315031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 14:44:29.315564 ==
6849 14:44:29.315899
6850 14:44:29.316234
6851 14:44:29.318225 TX Vref Scan disable
6852 14:44:29.321560 == TX Byte 0 ==
6853 14:44:29.324943 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6854 14:44:29.328541 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6855 14:44:29.331670 == TX Byte 1 ==
6856 14:44:29.334951 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6857 14:44:29.338710 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6858 14:44:29.339126 ==
6859 14:44:29.341845 Dram Type= 6, Freq= 0, CH_1, rank 1
6860 14:44:29.344720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6861 14:44:29.348756 ==
6862 14:44:29.349472
6863 14:44:29.349961
6864 14:44:29.350276 TX Vref Scan disable
6865 14:44:29.351189 == TX Byte 0 ==
6866 14:44:29.354866 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6867 14:44:29.358155 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6868 14:44:29.361632 == TX Byte 1 ==
6869 14:44:29.364694 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6870 14:44:29.368189 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6871 14:44:29.368846
6872 14:44:29.369231 [DATLAT]
6873 14:44:29.371137 Freq=400, CH1 RK1
6874 14:44:29.371720
6875 14:44:29.375161 DATLAT Default: 0xe
6876 14:44:29.375734 0, 0xFFFF, sum = 0
6877 14:44:29.377960 1, 0xFFFF, sum = 0
6878 14:44:29.378707 2, 0xFFFF, sum = 0
6879 14:44:29.380991 3, 0xFFFF, sum = 0
6880 14:44:29.381451 4, 0xFFFF, sum = 0
6881 14:44:29.384461 5, 0xFFFF, sum = 0
6882 14:44:29.384897 6, 0xFFFF, sum = 0
6883 14:44:29.387670 7, 0xFFFF, sum = 0
6884 14:44:29.388103 8, 0xFFFF, sum = 0
6885 14:44:29.390991 9, 0xFFFF, sum = 0
6886 14:44:29.391642 10, 0xFFFF, sum = 0
6887 14:44:29.394831 11, 0xFFFF, sum = 0
6888 14:44:29.395296 12, 0xFFFF, sum = 0
6889 14:44:29.397344 13, 0x0, sum = 1
6890 14:44:29.397811 14, 0x0, sum = 2
6891 14:44:29.401188 15, 0x0, sum = 3
6892 14:44:29.401652 16, 0x0, sum = 4
6893 14:44:29.404652 best_step = 14
6894 14:44:29.405231
6895 14:44:29.405769 ==
6896 14:44:29.407508 Dram Type= 6, Freq= 0, CH_1, rank 1
6897 14:44:29.410752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 14:44:29.411168 ==
6899 14:44:29.413991 RX Vref Scan: 0
6900 14:44:29.414460
6901 14:44:29.414871 RX Vref 0 -> 0, step: 1
6902 14:44:29.415472
6903 14:44:29.417194 RX Delay -343 -> 252, step: 8
6904 14:44:29.425740 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6905 14:44:29.429364 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6906 14:44:29.432508 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6907 14:44:29.435481 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6908 14:44:29.442734 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6909 14:44:29.445657 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6910 14:44:29.448696 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6911 14:44:29.452211 iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488
6912 14:44:29.458551 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6913 14:44:29.461756 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6914 14:44:29.465647 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6915 14:44:29.472026 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6916 14:44:29.475488 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6917 14:44:29.478421 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6918 14:44:29.481558 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6919 14:44:29.488461 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6920 14:44:29.488960 ==
6921 14:44:29.491508 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 14:44:29.494813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 14:44:29.495391 ==
6924 14:44:29.495726 DQS Delay:
6925 14:44:29.498316 DQS0 = 48, DQS1 = 52
6926 14:44:29.498729 DQM Delay:
6927 14:44:29.501530 DQM0 = 12, DQM1 = 11
6928 14:44:29.501961 DQ Delay:
6929 14:44:29.504536 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6930 14:44:29.507944 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =12
6931 14:44:29.511450 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6932 14:44:29.514633 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6933 14:44:29.515049
6934 14:44:29.515369
6935 14:44:29.521178 [DQSOSCAuto] RK1, (LSB)MR18= 0x79b1, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
6936 14:44:29.524774 CH1 RK1: MR19=C0C, MR18=79B1
6937 14:44:29.530902 CH1_RK1: MR19=0xC0C, MR18=0x79B1, DQSOSC=387, MR23=63, INC=394, DEC=262
6938 14:44:29.534613 [RxdqsGatingPostProcess] freq 400
6939 14:44:29.541450 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6940 14:44:29.544185 best DQS0 dly(2T, 0.5T) = (0, 10)
6941 14:44:29.547671 best DQS1 dly(2T, 0.5T) = (0, 10)
6942 14:44:29.551169 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6943 14:44:29.554296 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6944 14:44:29.558126 best DQS0 dly(2T, 0.5T) = (0, 10)
6945 14:44:29.558642 best DQS1 dly(2T, 0.5T) = (0, 10)
6946 14:44:29.560673 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6947 14:44:29.565032 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6948 14:44:29.568130 Pre-setting of DQS Precalculation
6949 14:44:29.573867 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6950 14:44:29.580921 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6951 14:44:29.587243 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6952 14:44:29.587756
6953 14:44:29.588087
6954 14:44:29.590670 [Calibration Summary] 800 Mbps
6955 14:44:29.593629 CH 0, Rank 0
6956 14:44:29.594038 SW Impedance : PASS
6957 14:44:29.596972 DUTY Scan : NO K
6958 14:44:29.600265 ZQ Calibration : PASS
6959 14:44:29.600779 Jitter Meter : NO K
6960 14:44:29.603391 CBT Training : PASS
6961 14:44:29.603807 Write leveling : PASS
6962 14:44:29.607204 RX DQS gating : PASS
6963 14:44:29.610144 RX DQ/DQS(RDDQC) : PASS
6964 14:44:29.610561 TX DQ/DQS : PASS
6965 14:44:29.613571 RX DATLAT : PASS
6966 14:44:29.616764 RX DQ/DQS(Engine): PASS
6967 14:44:29.617181 TX OE : NO K
6968 14:44:29.620256 All Pass.
6969 14:44:29.620665
6970 14:44:29.621021 CH 0, Rank 1
6971 14:44:29.623292 SW Impedance : PASS
6972 14:44:29.623738 DUTY Scan : NO K
6973 14:44:29.626682 ZQ Calibration : PASS
6974 14:44:29.630702 Jitter Meter : NO K
6975 14:44:29.631209 CBT Training : PASS
6976 14:44:29.633131 Write leveling : NO K
6977 14:44:29.636634 RX DQS gating : PASS
6978 14:44:29.637071 RX DQ/DQS(RDDQC) : PASS
6979 14:44:29.639671 TX DQ/DQS : PASS
6980 14:44:29.643294 RX DATLAT : PASS
6981 14:44:29.643708 RX DQ/DQS(Engine): PASS
6982 14:44:29.646683 TX OE : NO K
6983 14:44:29.647098 All Pass.
6984 14:44:29.647419
6985 14:44:29.649572 CH 1, Rank 0
6986 14:44:29.650090 SW Impedance : PASS
6987 14:44:29.653237 DUTY Scan : NO K
6988 14:44:29.656083 ZQ Calibration : PASS
6989 14:44:29.656503 Jitter Meter : NO K
6990 14:44:29.659614 CBT Training : PASS
6991 14:44:29.663044 Write leveling : PASS
6992 14:44:29.663454 RX DQS gating : PASS
6993 14:44:29.666693 RX DQ/DQS(RDDQC) : PASS
6994 14:44:29.669489 TX DQ/DQS : PASS
6995 14:44:29.669907 RX DATLAT : PASS
6996 14:44:29.672657 RX DQ/DQS(Engine): PASS
6997 14:44:29.673308 TX OE : NO K
6998 14:44:29.676241 All Pass.
6999 14:44:29.676652
7000 14:44:29.676973 CH 1, Rank 1
7001 14:44:29.679268 SW Impedance : PASS
7002 14:44:29.679701 DUTY Scan : NO K
7003 14:44:29.682365 ZQ Calibration : PASS
7004 14:44:29.685827 Jitter Meter : NO K
7005 14:44:29.686242 CBT Training : PASS
7006 14:44:29.689897 Write leveling : NO K
7007 14:44:29.692966 RX DQS gating : PASS
7008 14:44:29.693559 RX DQ/DQS(RDDQC) : PASS
7009 14:44:29.696361 TX DQ/DQS : PASS
7010 14:44:29.699371 RX DATLAT : PASS
7011 14:44:29.699786 RX DQ/DQS(Engine): PASS
7012 14:44:29.703453 TX OE : NO K
7013 14:44:29.703970 All Pass.
7014 14:44:29.704330
7015 14:44:29.706074 DramC Write-DBI off
7016 14:44:29.708853 PER_BANK_REFRESH: Hybrid Mode
7017 14:44:29.709300 TX_TRACKING: ON
7018 14:44:29.718696 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7019 14:44:29.722329 [FAST_K] Save calibration result to emmc
7020 14:44:29.725724 dramc_set_vcore_voltage set vcore to 725000
7021 14:44:29.729154 Read voltage for 1600, 0
7022 14:44:29.729613 Vio18 = 0
7023 14:44:29.732038 Vcore = 725000
7024 14:44:29.732452 Vdram = 0
7025 14:44:29.732773 Vddq = 0
7026 14:44:29.733074 Vmddr = 0
7027 14:44:29.738742 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7028 14:44:29.745326 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7029 14:44:29.745819 MEM_TYPE=3, freq_sel=13
7030 14:44:29.748764 sv_algorithm_assistance_LP4_3733
7031 14:44:29.751582 ============ PULL DRAM RESETB DOWN ============
7032 14:44:29.759015 ========== PULL DRAM RESETB DOWN end =========
7033 14:44:29.761637 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7034 14:44:29.765214 ===================================
7035 14:44:29.768448 LPDDR4 DRAM CONFIGURATION
7036 14:44:29.771255 ===================================
7037 14:44:29.771679 EX_ROW_EN[0] = 0x0
7038 14:44:29.775064 EX_ROW_EN[1] = 0x0
7039 14:44:29.775482 LP4Y_EN = 0x0
7040 14:44:29.777992 WORK_FSP = 0x1
7041 14:44:29.781775 WL = 0x5
7042 14:44:29.782191 RL = 0x5
7043 14:44:29.785004 BL = 0x2
7044 14:44:29.785591 RPST = 0x0
7045 14:44:29.788294 RD_PRE = 0x0
7046 14:44:29.788710 WR_PRE = 0x1
7047 14:44:29.791167 WR_PST = 0x1
7048 14:44:29.791698 DBI_WR = 0x0
7049 14:44:29.794567 DBI_RD = 0x0
7050 14:44:29.794988 OTF = 0x1
7051 14:44:29.798150 ===================================
7052 14:44:29.801414 ===================================
7053 14:44:29.804651 ANA top config
7054 14:44:29.807518 ===================================
7055 14:44:29.807932 DLL_ASYNC_EN = 0
7056 14:44:29.811290 ALL_SLAVE_EN = 0
7057 14:44:29.814165 NEW_RANK_MODE = 1
7058 14:44:29.817906 DLL_IDLE_MODE = 1
7059 14:44:29.821016 LP45_APHY_COMB_EN = 1
7060 14:44:29.821538 TX_ODT_DIS = 0
7061 14:44:29.824138 NEW_8X_MODE = 1
7062 14:44:29.827592 ===================================
7063 14:44:29.831609 ===================================
7064 14:44:29.834468 data_rate = 3200
7065 14:44:29.837590 CKR = 1
7066 14:44:29.841149 DQ_P2S_RATIO = 8
7067 14:44:29.844664 ===================================
7068 14:44:29.847235 CA_P2S_RATIO = 8
7069 14:44:29.847655 DQ_CA_OPEN = 0
7070 14:44:29.850547 DQ_SEMI_OPEN = 0
7071 14:44:29.853961 CA_SEMI_OPEN = 0
7072 14:44:29.857487 CA_FULL_RATE = 0
7073 14:44:29.860479 DQ_CKDIV4_EN = 0
7074 14:44:29.864125 CA_CKDIV4_EN = 0
7075 14:44:29.864537 CA_PREDIV_EN = 0
7076 14:44:29.867636 PH8_DLY = 12
7077 14:44:29.870543 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7078 14:44:29.873524 DQ_AAMCK_DIV = 4
7079 14:44:29.876992 CA_AAMCK_DIV = 4
7080 14:44:29.880252 CA_ADMCK_DIV = 4
7081 14:44:29.880779 DQ_TRACK_CA_EN = 0
7082 14:44:29.883851 CA_PICK = 1600
7083 14:44:29.887257 CA_MCKIO = 1600
7084 14:44:29.890965 MCKIO_SEMI = 0
7085 14:44:29.893377 PLL_FREQ = 3068
7086 14:44:29.896601 DQ_UI_PI_RATIO = 32
7087 14:44:29.900644 CA_UI_PI_RATIO = 0
7088 14:44:29.903429 ===================================
7089 14:44:29.906739 ===================================
7090 14:44:29.909798 memory_type:LPDDR4
7091 14:44:29.910211 GP_NUM : 10
7092 14:44:29.913661 SRAM_EN : 1
7093 14:44:29.914096 MD32_EN : 0
7094 14:44:29.916105 ===================================
7095 14:44:29.919947 [ANA_INIT] >>>>>>>>>>>>>>
7096 14:44:29.923588 <<<<<< [CONFIGURE PHASE]: ANA_TX
7097 14:44:29.926873 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7098 14:44:29.929538 ===================================
7099 14:44:29.933248 data_rate = 3200,PCW = 0X7600
7100 14:44:29.935983 ===================================
7101 14:44:29.939791 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7102 14:44:29.945898 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7103 14:44:29.949167 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7104 14:44:29.955648 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7105 14:44:29.959402 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7106 14:44:29.962411 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7107 14:44:29.962880 [ANA_INIT] flow start
7108 14:44:29.965935 [ANA_INIT] PLL >>>>>>>>
7109 14:44:29.969126 [ANA_INIT] PLL <<<<<<<<
7110 14:44:29.969578 [ANA_INIT] MIDPI >>>>>>>>
7111 14:44:29.972711 [ANA_INIT] MIDPI <<<<<<<<
7112 14:44:29.975881 [ANA_INIT] DLL >>>>>>>>
7113 14:44:29.979095 [ANA_INIT] DLL <<<<<<<<
7114 14:44:29.979512 [ANA_INIT] flow end
7115 14:44:29.982163 ============ LP4 DIFF to SE enter ============
7116 14:44:29.988873 ============ LP4 DIFF to SE exit ============
7117 14:44:29.989324 [ANA_INIT] <<<<<<<<<<<<<
7118 14:44:29.992794 [Flow] Enable top DCM control >>>>>
7119 14:44:29.995630 [Flow] Enable top DCM control <<<<<
7120 14:44:29.999439 Enable DLL master slave shuffle
7121 14:44:30.005208 ==============================================================
7122 14:44:30.005670 Gating Mode config
7123 14:44:30.011932 ==============================================================
7124 14:44:30.015224 Config description:
7125 14:44:30.025134 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7126 14:44:30.032133 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7127 14:44:30.035347 SELPH_MODE 0: By rank 1: By Phase
7128 14:44:30.041452 ==============================================================
7129 14:44:30.045198 GAT_TRACK_EN = 1
7130 14:44:30.047851 RX_GATING_MODE = 2
7131 14:44:30.048264 RX_GATING_TRACK_MODE = 2
7132 14:44:30.051656 SELPH_MODE = 1
7133 14:44:30.055246 PICG_EARLY_EN = 1
7134 14:44:30.057792 VALID_LAT_VALUE = 1
7135 14:44:30.064986 ==============================================================
7136 14:44:30.068053 Enter into Gating configuration >>>>
7137 14:44:30.071115 Exit from Gating configuration <<<<
7138 14:44:30.074642 Enter into DVFS_PRE_config >>>>>
7139 14:44:30.084472 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7140 14:44:30.087619 Exit from DVFS_PRE_config <<<<<
7141 14:44:30.091337 Enter into PICG configuration >>>>
7142 14:44:30.094697 Exit from PICG configuration <<<<
7143 14:44:30.097299 [RX_INPUT] configuration >>>>>
7144 14:44:30.100984 [RX_INPUT] configuration <<<<<
7145 14:44:30.104398 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7146 14:44:30.111105 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7147 14:44:30.117177 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7148 14:44:30.123988 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7149 14:44:30.130462 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7150 14:44:30.137229 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7151 14:44:30.140552 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7152 14:44:30.143588 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7153 14:44:30.146655 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7154 14:44:30.153289 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7155 14:44:30.156378 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7156 14:44:30.159853 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7157 14:44:30.163338 ===================================
7158 14:44:30.166407 LPDDR4 DRAM CONFIGURATION
7159 14:44:30.170343 ===================================
7160 14:44:30.170757 EX_ROW_EN[0] = 0x0
7161 14:44:30.173159 EX_ROW_EN[1] = 0x0
7162 14:44:30.176059 LP4Y_EN = 0x0
7163 14:44:30.176474 WORK_FSP = 0x1
7164 14:44:30.179724 WL = 0x5
7165 14:44:30.180179 RL = 0x5
7166 14:44:30.183076 BL = 0x2
7167 14:44:30.183591 RPST = 0x0
7168 14:44:30.186091 RD_PRE = 0x0
7169 14:44:30.186508 WR_PRE = 0x1
7170 14:44:30.189478 WR_PST = 0x1
7171 14:44:30.189966 DBI_WR = 0x0
7172 14:44:30.192856 DBI_RD = 0x0
7173 14:44:30.193299 OTF = 0x1
7174 14:44:30.196276 ===================================
7175 14:44:30.199725 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7176 14:44:30.206161 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7177 14:44:30.209074 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7178 14:44:30.212610 ===================================
7179 14:44:30.215764 LPDDR4 DRAM CONFIGURATION
7180 14:44:30.219084 ===================================
7181 14:44:30.219501 EX_ROW_EN[0] = 0x10
7182 14:44:30.222159 EX_ROW_EN[1] = 0x0
7183 14:44:30.226245 LP4Y_EN = 0x0
7184 14:44:30.226655 WORK_FSP = 0x1
7185 14:44:30.228944 WL = 0x5
7186 14:44:30.229393 RL = 0x5
7187 14:44:30.231967 BL = 0x2
7188 14:44:30.232426 RPST = 0x0
7189 14:44:30.235298 RD_PRE = 0x0
7190 14:44:30.235709 WR_PRE = 0x1
7191 14:44:30.238403 WR_PST = 0x1
7192 14:44:30.238820 DBI_WR = 0x0
7193 14:44:30.241795 DBI_RD = 0x0
7194 14:44:30.242086 OTF = 0x1
7195 14:44:30.245124 ===================================
7196 14:44:30.251641 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7197 14:44:30.251879 ==
7198 14:44:30.255254 Dram Type= 6, Freq= 0, CH_0, rank 0
7199 14:44:30.261356 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7200 14:44:30.261544 ==
7201 14:44:30.261709 [Duty_Offset_Calibration]
7202 14:44:30.264890 B0:2 B1:0 CA:4
7203 14:44:30.265046
7204 14:44:30.268147 [DutyScan_Calibration_Flow] k_type=0
7205 14:44:30.276250
7206 14:44:30.276379 ==CLK 0==
7207 14:44:30.279838 Final CLK duty delay cell = -4
7208 14:44:30.282688 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7209 14:44:30.286176 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7210 14:44:30.289750 [-4] AVG Duty = 4937%(X100)
7211 14:44:30.289862
7212 14:44:30.292959 CH0 CLK Duty spec in!! Max-Min= 187%
7213 14:44:30.296249 [DutyScan_Calibration_Flow] ====Done====
7214 14:44:30.296365
7215 14:44:30.299638 [DutyScan_Calibration_Flow] k_type=1
7216 14:44:30.317132
7217 14:44:30.317315 ==DQS 0 ==
7218 14:44:30.320134 Final DQS duty delay cell = 0
7219 14:44:30.323341 [0] MAX Duty = 5218%(X100), DQS PI = 38
7220 14:44:30.326944 [0] MIN Duty = 5093%(X100), DQS PI = 14
7221 14:44:30.330171 [0] AVG Duty = 5155%(X100)
7222 14:44:30.330281
7223 14:44:30.330356 ==DQS 1 ==
7224 14:44:30.333114 Final DQS duty delay cell = 0
7225 14:44:30.336624 [0] MAX Duty = 5187%(X100), DQS PI = 2
7226 14:44:30.339667 [0] MIN Duty = 4969%(X100), DQS PI = 10
7227 14:44:30.342829 [0] AVG Duty = 5078%(X100)
7228 14:44:30.342941
7229 14:44:30.346447 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7230 14:44:30.346559
7231 14:44:30.349654 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7232 14:44:30.353088 [DutyScan_Calibration_Flow] ====Done====
7233 14:44:30.353201
7234 14:44:30.356044 [DutyScan_Calibration_Flow] k_type=3
7235 14:44:30.373993
7236 14:44:30.374132 ==DQM 0 ==
7237 14:44:30.377049 Final DQM duty delay cell = 0
7238 14:44:30.380435 [0] MAX Duty = 5124%(X100), DQS PI = 20
7239 14:44:30.383514 [0] MIN Duty = 4844%(X100), DQS PI = 54
7240 14:44:30.387079 [0] AVG Duty = 4984%(X100)
7241 14:44:30.387161
7242 14:44:30.387224 ==DQM 1 ==
7243 14:44:30.390189 Final DQM duty delay cell = 0
7244 14:44:30.393722 [0] MAX Duty = 4969%(X100), DQS PI = 0
7245 14:44:30.397061 [0] MIN Duty = 4844%(X100), DQS PI = 10
7246 14:44:30.400166 [0] AVG Duty = 4906%(X100)
7247 14:44:30.400282
7248 14:44:30.403480 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7249 14:44:30.403584
7250 14:44:30.406750 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7251 14:44:30.410838 [DutyScan_Calibration_Flow] ====Done====
7252 14:44:30.411046
7253 14:44:30.413295 [DutyScan_Calibration_Flow] k_type=2
7254 14:44:30.431326
7255 14:44:30.431768 ==DQ 0 ==
7256 14:44:30.434827 Final DQ duty delay cell = 0
7257 14:44:30.437462 [0] MAX Duty = 5124%(X100), DQS PI = 22
7258 14:44:30.440619 [0] MIN Duty = 4938%(X100), DQS PI = 12
7259 14:44:30.444350 [0] AVG Duty = 5031%(X100)
7260 14:44:30.444741
7261 14:44:30.445073 ==DQ 1 ==
7262 14:44:30.447315 Final DQ duty delay cell = 0
7263 14:44:30.451172 [0] MAX Duty = 5187%(X100), DQS PI = 2
7264 14:44:30.454516 [0] MIN Duty = 4938%(X100), DQS PI = 12
7265 14:44:30.454949 [0] AVG Duty = 5062%(X100)
7266 14:44:30.458339
7267 14:44:30.460591 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7268 14:44:30.461054
7269 14:44:30.464414 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7270 14:44:30.467221 [DutyScan_Calibration_Flow] ====Done====
7271 14:44:30.467605 ==
7272 14:44:30.470865 Dram Type= 6, Freq= 0, CH_1, rank 0
7273 14:44:30.474097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7274 14:44:30.474661 ==
7275 14:44:30.476940 [Duty_Offset_Calibration]
7276 14:44:30.477211 B0:0 B1:-1 CA:3
7277 14:44:30.477460
7278 14:44:30.480728 [DutyScan_Calibration_Flow] k_type=0
7279 14:44:30.490884
7280 14:44:30.491063 ==CLK 0==
7281 14:44:30.493674 Final CLK duty delay cell = -4
7282 14:44:30.496779 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7283 14:44:30.500063 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7284 14:44:30.503520 [-4] AVG Duty = 4922%(X100)
7285 14:44:30.503629
7286 14:44:30.507237 CH1 CLK Duty spec in!! Max-Min= 156%
7287 14:44:30.510311 [DutyScan_Calibration_Flow] ====Done====
7288 14:44:30.510412
7289 14:44:30.513587 [DutyScan_Calibration_Flow] k_type=1
7290 14:44:30.529554
7291 14:44:30.529670 ==DQS 0 ==
7292 14:44:30.533173 Final DQS duty delay cell = 0
7293 14:44:30.535853 [0] MAX Duty = 5218%(X100), DQS PI = 28
7294 14:44:30.539184 [0] MIN Duty = 4907%(X100), DQS PI = 40
7295 14:44:30.542636 [0] AVG Duty = 5062%(X100)
7296 14:44:30.542734
7297 14:44:30.542820 ==DQS 1 ==
7298 14:44:30.546383 Final DQS duty delay cell = -4
7299 14:44:30.549198 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7300 14:44:30.552747 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7301 14:44:30.556143 [-4] AVG Duty = 4922%(X100)
7302 14:44:30.556221
7303 14:44:30.559223 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7304 14:44:30.559299
7305 14:44:30.562387 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7306 14:44:30.566088 [DutyScan_Calibration_Flow] ====Done====
7307 14:44:30.566162
7308 14:44:30.569233 [DutyScan_Calibration_Flow] k_type=3
7309 14:44:30.586499
7310 14:44:30.586656 ==DQM 0 ==
7311 14:44:30.589940 Final DQM duty delay cell = 0
7312 14:44:30.593190 [0] MAX Duty = 5062%(X100), DQS PI = 32
7313 14:44:30.596694 [0] MIN Duty = 4750%(X100), DQS PI = 40
7314 14:44:30.599691 [0] AVG Duty = 4906%(X100)
7315 14:44:30.599771
7316 14:44:30.599832 ==DQM 1 ==
7317 14:44:30.602885 Final DQM duty delay cell = 0
7318 14:44:30.606368 [0] MAX Duty = 4969%(X100), DQS PI = 30
7319 14:44:30.609776 [0] MIN Duty = 4813%(X100), DQS PI = 0
7320 14:44:30.612882 [0] AVG Duty = 4891%(X100)
7321 14:44:30.612971
7322 14:44:30.616213 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7323 14:44:30.616288
7324 14:44:30.619950 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7325 14:44:30.622820 [DutyScan_Calibration_Flow] ====Done====
7326 14:44:30.622928
7327 14:44:30.626270 [DutyScan_Calibration_Flow] k_type=2
7328 14:44:30.642838
7329 14:44:30.642942 ==DQ 0 ==
7330 14:44:30.646523 Final DQ duty delay cell = -4
7331 14:44:30.649336 [-4] MAX Duty = 4938%(X100), DQS PI = 8
7332 14:44:30.652920 [-4] MIN Duty = 4813%(X100), DQS PI = 20
7333 14:44:30.656194 [-4] AVG Duty = 4875%(X100)
7334 14:44:30.656278
7335 14:44:30.656340 ==DQ 1 ==
7336 14:44:30.659396 Final DQ duty delay cell = 0
7337 14:44:30.662644 [0] MAX Duty = 5031%(X100), DQS PI = 30
7338 14:44:30.665938 [0] MIN Duty = 4844%(X100), DQS PI = 60
7339 14:44:30.668605 [0] AVG Duty = 4937%(X100)
7340 14:44:30.668680
7341 14:44:30.672432 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7342 14:44:30.672507
7343 14:44:30.675702 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7344 14:44:30.678464 [DutyScan_Calibration_Flow] ====Done====
7345 14:44:30.682346 nWR fixed to 30
7346 14:44:30.685439 [ModeRegInit_LP4] CH0 RK0
7347 14:44:30.685521 [ModeRegInit_LP4] CH0 RK1
7348 14:44:30.688539 [ModeRegInit_LP4] CH1 RK0
7349 14:44:30.691893 [ModeRegInit_LP4] CH1 RK1
7350 14:44:30.691969 match AC timing 5
7351 14:44:30.698838 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7352 14:44:30.702030 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7353 14:44:30.705242 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7354 14:44:30.711852 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7355 14:44:30.714823 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7356 14:44:30.718499 [MiockJmeterHQA]
7357 14:44:30.718619
7358 14:44:30.721601 [DramcMiockJmeter] u1RxGatingPI = 0
7359 14:44:30.721693 0 : 4255, 4029
7360 14:44:30.721761 4 : 4253, 4027
7361 14:44:30.724987 8 : 4253, 4027
7362 14:44:30.725106 12 : 4252, 4030
7363 14:44:30.728135 16 : 4255, 4030
7364 14:44:30.728237 20 : 4363, 4138
7365 14:44:30.731483 24 : 4363, 4137
7366 14:44:30.731589 28 : 4365, 4140
7367 14:44:30.731655 32 : 4252, 4027
7368 14:44:30.734981 36 : 4255, 4029
7369 14:44:30.735080 40 : 4252, 4027
7370 14:44:30.738080 44 : 4250, 4027
7371 14:44:30.738172 48 : 4250, 4026
7372 14:44:30.741515 52 : 4253, 4026
7373 14:44:30.741603 56 : 4258, 4029
7374 14:44:30.744573 60 : 4250, 4027
7375 14:44:30.744660 64 : 4252, 4029
7376 14:44:30.747816 68 : 4250, 4026
7377 14:44:30.747908 72 : 4363, 4138
7378 14:44:30.747975 76 : 4363, 4138
7379 14:44:30.751309 80 : 4250, 4027
7380 14:44:30.751402 84 : 4250, 4027
7381 14:44:30.754486 88 : 4250, 4027
7382 14:44:30.754574 92 : 4252, 4027
7383 14:44:30.757945 96 : 4250, 2373
7384 14:44:30.758032 100 : 4250, 0
7385 14:44:30.758099 104 : 4250, 0
7386 14:44:30.761020 108 : 4252, 0
7387 14:44:30.761109 112 : 4361, 0
7388 14:44:30.764093 116 : 4250, 0
7389 14:44:30.764184 120 : 4250, 0
7390 14:44:30.764251 124 : 4360, 0
7391 14:44:30.767756 128 : 4360, 0
7392 14:44:30.767840 132 : 4363, 0
7393 14:44:30.771167 136 : 4250, 0
7394 14:44:30.771245 140 : 4250, 0
7395 14:44:30.771307 144 : 4250, 0
7396 14:44:30.774827 148 : 4250, 0
7397 14:44:30.774938 152 : 4250, 0
7398 14:44:30.777822 156 : 4250, 0
7399 14:44:30.777904 160 : 4250, 0
7400 14:44:30.777970 164 : 4250, 0
7401 14:44:30.780648 168 : 4250, 0
7402 14:44:30.780731 172 : 4252, 0
7403 14:44:30.780794 176 : 4255, 0
7404 14:44:30.783964 180 : 4361, 0
7405 14:44:30.784097 184 : 4361, 0
7406 14:44:30.787423 188 : 4257, 0
7407 14:44:30.787504 192 : 4361, 0
7408 14:44:30.787566 196 : 4249, 0
7409 14:44:30.790563 200 : 4250, 0
7410 14:44:30.790666 204 : 4250, 0
7411 14:44:30.793751 208 : 4250, 0
7412 14:44:30.793856 212 : 4250, 0
7413 14:44:30.793947 216 : 4250, 0
7414 14:44:30.797444 220 : 4251, 490
7415 14:44:30.797554 224 : 4252, 4024
7416 14:44:30.800279 228 : 4252, 4030
7417 14:44:30.800357 232 : 4250, 4027
7418 14:44:30.803961 236 : 4250, 4026
7419 14:44:30.804081 240 : 4361, 4137
7420 14:44:30.807253 244 : 4250, 4027
7421 14:44:30.807331 248 : 4361, 4138
7422 14:44:30.810512 252 : 4250, 4027
7423 14:44:30.810591 256 : 4250, 4026
7424 14:44:30.813563 260 : 4250, 4027
7425 14:44:30.813638 264 : 4250, 4027
7426 14:44:30.813701 268 : 4250, 4027
7427 14:44:30.816847 272 : 4255, 4029
7428 14:44:30.816922 276 : 4250, 4027
7429 14:44:30.820245 280 : 4252, 4030
7430 14:44:30.820319 284 : 4250, 4027
7431 14:44:30.823499 288 : 4250, 4027
7432 14:44:30.823573 292 : 4361, 4137
7433 14:44:30.827049 296 : 4250, 4027
7434 14:44:30.827127 300 : 4361, 4137
7435 14:44:30.830011 304 : 4250, 4027
7436 14:44:30.830088 308 : 4250, 4026
7437 14:44:30.833497 312 : 4250, 4027
7438 14:44:30.833570 316 : 4250, 4027
7439 14:44:30.836913 320 : 4250, 4027
7440 14:44:30.836990 324 : 4250, 4027
7441 14:44:30.840136 328 : 4250, 4027
7442 14:44:30.840215 332 : 4252, 3934
7443 14:44:30.840278 336 : 4250, 1543
7444 14:44:30.843279
7445 14:44:30.843364 MIOCK jitter meter ch=0
7446 14:44:30.843430
7447 14:44:30.847115 1T = (336-100) = 236 dly cells
7448 14:44:30.853140 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7449 14:44:30.853279 ==
7450 14:44:30.856566 Dram Type= 6, Freq= 0, CH_0, rank 0
7451 14:44:30.859871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7452 14:44:30.859987 ==
7453 14:44:30.867350 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7454 14:44:30.869500 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7455 14:44:30.872868 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7456 14:44:30.880004 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7457 14:44:30.889128 [CA 0] Center 44 (14~74) winsize 61
7458 14:44:30.892350 [CA 1] Center 43 (13~74) winsize 62
7459 14:44:30.895579 [CA 2] Center 39 (10~68) winsize 59
7460 14:44:30.899301 [CA 3] Center 38 (9~68) winsize 60
7461 14:44:30.902301 [CA 4] Center 36 (6~66) winsize 61
7462 14:44:30.906340 [CA 5] Center 36 (6~66) winsize 61
7463 14:44:30.906413
7464 14:44:30.908897 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7465 14:44:30.908969
7466 14:44:30.912652 [CATrainingPosCal] consider 1 rank data
7467 14:44:30.915591 u2DelayCellTimex100 = 275/100 ps
7468 14:44:30.922661 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7469 14:44:30.925903 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7470 14:44:30.928750 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7471 14:44:30.932344 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7472 14:44:30.935783 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
7473 14:44:30.938718 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7474 14:44:30.938794
7475 14:44:30.942309 CA PerBit enable=1, Macro0, CA PI delay=36
7476 14:44:30.942379
7477 14:44:30.945474 [CBTSetCACLKResult] CA Dly = 36
7478 14:44:30.948769 CS Dly: 10 (0~41)
7479 14:44:30.951750 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7480 14:44:30.955159 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7481 14:44:30.955257 ==
7482 14:44:30.958565 Dram Type= 6, Freq= 0, CH_0, rank 1
7483 14:44:30.965180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7484 14:44:30.965280 ==
7485 14:44:30.968275 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7486 14:44:30.975631 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7487 14:44:30.978164 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7488 14:44:30.985052 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7489 14:44:30.993239 [CA 0] Center 43 (13~74) winsize 62
7490 14:44:30.996537 [CA 1] Center 43 (13~74) winsize 62
7491 14:44:30.999943 [CA 2] Center 38 (9~68) winsize 60
7492 14:44:31.003232 [CA 3] Center 38 (9~68) winsize 60
7493 14:44:31.006421 [CA 4] Center 36 (6~66) winsize 61
7494 14:44:31.009389 [CA 5] Center 36 (6~66) winsize 61
7495 14:44:31.009492
7496 14:44:31.012533 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7497 14:44:31.012614
7498 14:44:31.015812 [CATrainingPosCal] consider 2 rank data
7499 14:44:31.019362 u2DelayCellTimex100 = 275/100 ps
7500 14:44:31.025570 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7501 14:44:31.029167 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7502 14:44:31.032758 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7503 14:44:31.035914 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7504 14:44:31.039210 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
7505 14:44:31.042596 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7506 14:44:31.042670
7507 14:44:31.045514 CA PerBit enable=1, Macro0, CA PI delay=36
7508 14:44:31.045600
7509 14:44:31.049398 [CBTSetCACLKResult] CA Dly = 36
7510 14:44:31.051989 CS Dly: 11 (0~43)
7511 14:44:31.055521 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7512 14:44:31.059236 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7513 14:44:31.059350
7514 14:44:31.062435 ----->DramcWriteLeveling(PI) begin...
7515 14:44:31.062541 ==
7516 14:44:31.065571 Dram Type= 6, Freq= 0, CH_0, rank 0
7517 14:44:31.072025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7518 14:44:31.072158 ==
7519 14:44:31.075306 Write leveling (Byte 0): 35 => 35
7520 14:44:31.078402 Write leveling (Byte 1): 25 => 25
7521 14:44:31.081662 DramcWriteLeveling(PI) end<-----
7522 14:44:31.081750
7523 14:44:31.081812 ==
7524 14:44:31.084787 Dram Type= 6, Freq= 0, CH_0, rank 0
7525 14:44:31.088082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7526 14:44:31.088180 ==
7527 14:44:31.092027 [Gating] SW mode calibration
7528 14:44:31.098654 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7529 14:44:31.104817 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7530 14:44:31.108005 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7531 14:44:31.111733 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7532 14:44:31.118041 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
7533 14:44:31.121254 1 4 12 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
7534 14:44:31.124802 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7535 14:44:31.131120 1 4 20 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
7536 14:44:31.134565 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7537 14:44:31.138116 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7538 14:44:31.144684 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7539 14:44:31.147685 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7540 14:44:31.150877 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7541 14:44:31.157456 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
7542 14:44:31.160862 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7543 14:44:31.164078 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 1) (0 0)
7544 14:44:31.170677 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 1) (0 0)
7545 14:44:31.174035 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7546 14:44:31.177408 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7547 14:44:31.183959 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7548 14:44:31.187226 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
7549 14:44:31.190578 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7550 14:44:31.197210 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7551 14:44:31.200522 1 6 20 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
7552 14:44:31.203600 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7553 14:44:31.209845 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7554 14:44:31.213466 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7555 14:44:31.216770 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7556 14:44:31.223581 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7557 14:44:31.226477 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7558 14:44:31.229673 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7559 14:44:31.236531 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7560 14:44:31.239687 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7561 14:44:31.243099 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7562 14:44:31.249425 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7563 14:44:31.253458 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7564 14:44:31.256053 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7565 14:44:31.262810 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7566 14:44:31.266175 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7567 14:44:31.269058 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 14:44:31.275819 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 14:44:31.278941 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 14:44:31.282584 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 14:44:31.289095 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 14:44:31.292575 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7573 14:44:31.296012 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7574 14:44:31.302242 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7575 14:44:31.302317 Total UI for P1: 0, mck2ui 16
7576 14:44:31.308823 best dqsien dly found for B0: ( 1, 9, 10)
7577 14:44:31.312061 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7578 14:44:31.315262 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7579 14:44:31.318634 Total UI for P1: 0, mck2ui 16
7580 14:44:31.322611 best dqsien dly found for B1: ( 1, 9, 20)
7581 14:44:31.325344 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7582 14:44:31.328758 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7583 14:44:31.328830
7584 14:44:31.335303 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7585 14:44:31.338683 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7586 14:44:31.341839 [Gating] SW calibration Done
7587 14:44:31.341910 ==
7588 14:44:31.344998 Dram Type= 6, Freq= 0, CH_0, rank 0
7589 14:44:31.348563 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7590 14:44:31.348660 ==
7591 14:44:31.348748 RX Vref Scan: 0
7592 14:44:31.351537
7593 14:44:31.351610 RX Vref 0 -> 0, step: 1
7594 14:44:31.351686
7595 14:44:31.354900 RX Delay 0 -> 252, step: 8
7596 14:44:31.358292 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7597 14:44:31.361586 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7598 14:44:31.368415 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7599 14:44:31.371860 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7600 14:44:31.374475 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7601 14:44:31.378355 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7602 14:44:31.381998 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7603 14:44:31.388174 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7604 14:44:31.390977 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7605 14:44:31.394895 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
7606 14:44:31.397771 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7607 14:44:31.401163 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7608 14:44:31.408066 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7609 14:44:31.410901 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7610 14:44:31.414070 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7611 14:44:31.418029 iDelay=192, Bit 15, Center 131 (80 ~ 183) 104
7612 14:44:31.421179 ==
7613 14:44:31.421319 Dram Type= 6, Freq= 0, CH_0, rank 0
7614 14:44:31.427301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7615 14:44:31.427402 ==
7616 14:44:31.427492 DQS Delay:
7617 14:44:31.430563 DQS0 = 0, DQS1 = 0
7618 14:44:31.430639 DQM Delay:
7619 14:44:31.434464 DQM0 = 131, DQM1 = 127
7620 14:44:31.434579 DQ Delay:
7621 14:44:31.437408 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7622 14:44:31.440182 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7623 14:44:31.443938 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
7624 14:44:31.447238 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =131
7625 14:44:31.447318
7626 14:44:31.447382
7627 14:44:31.447441 ==
7628 14:44:31.450298 Dram Type= 6, Freq= 0, CH_0, rank 0
7629 14:44:31.456977 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7630 14:44:31.457091 ==
7631 14:44:31.457199
7632 14:44:31.457293
7633 14:44:31.457353 TX Vref Scan disable
7634 14:44:31.460683 == TX Byte 0 ==
7635 14:44:31.464196 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7636 14:44:31.470812 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7637 14:44:31.470889 == TX Byte 1 ==
7638 14:44:31.473736 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7639 14:44:31.480193 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7640 14:44:31.480300 ==
7641 14:44:31.483668 Dram Type= 6, Freq= 0, CH_0, rank 0
7642 14:44:31.486855 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7643 14:44:31.486953 ==
7644 14:44:31.501239
7645 14:44:31.503822 TX Vref early break, caculate TX vref
7646 14:44:31.507749 TX Vref=16, minBit 7, minWin=22, winSum=369
7647 14:44:31.510564 TX Vref=18, minBit 1, minWin=23, winSum=378
7648 14:44:31.514008 TX Vref=20, minBit 1, minWin=23, winSum=389
7649 14:44:31.516890 TX Vref=22, minBit 1, minWin=24, winSum=398
7650 14:44:31.520467 TX Vref=24, minBit 4, minWin=24, winSum=407
7651 14:44:31.526899 TX Vref=26, minBit 1, minWin=25, winSum=416
7652 14:44:31.530551 TX Vref=28, minBit 1, minWin=25, winSum=417
7653 14:44:31.533538 TX Vref=30, minBit 0, minWin=25, winSum=413
7654 14:44:31.536751 TX Vref=32, minBit 0, minWin=25, winSum=404
7655 14:44:31.540398 TX Vref=34, minBit 0, minWin=24, winSum=394
7656 14:44:31.546752 [TxChooseVref] Worse bit 1, Min win 25, Win sum 417, Final Vref 28
7657 14:44:31.546883
7658 14:44:31.550113 Final TX Range 0 Vref 28
7659 14:44:31.550188
7660 14:44:31.550248 ==
7661 14:44:31.553589 Dram Type= 6, Freq= 0, CH_0, rank 0
7662 14:44:31.556862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7663 14:44:31.556954 ==
7664 14:44:31.557030
7665 14:44:31.557104
7666 14:44:31.559780 TX Vref Scan disable
7667 14:44:31.566509 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7668 14:44:31.566594 == TX Byte 0 ==
7669 14:44:31.569821 u2DelayCellOfst[0]=10 cells (3 PI)
7670 14:44:31.572973 u2DelayCellOfst[1]=14 cells (4 PI)
7671 14:44:31.576412 u2DelayCellOfst[2]=7 cells (2 PI)
7672 14:44:31.579720 u2DelayCellOfst[3]=7 cells (2 PI)
7673 14:44:31.583114 u2DelayCellOfst[4]=7 cells (2 PI)
7674 14:44:31.586762 u2DelayCellOfst[5]=0 cells (0 PI)
7675 14:44:31.589515 u2DelayCellOfst[6]=14 cells (4 PI)
7676 14:44:31.592850 u2DelayCellOfst[7]=14 cells (4 PI)
7677 14:44:31.596542 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7678 14:44:31.599897 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7679 14:44:31.602881 == TX Byte 1 ==
7680 14:44:31.606568 u2DelayCellOfst[8]=0 cells (0 PI)
7681 14:44:31.609505 u2DelayCellOfst[9]=0 cells (0 PI)
7682 14:44:31.609607 u2DelayCellOfst[10]=3 cells (1 PI)
7683 14:44:31.612734 u2DelayCellOfst[11]=0 cells (0 PI)
7684 14:44:31.615949 u2DelayCellOfst[12]=7 cells (2 PI)
7685 14:44:31.620327 u2DelayCellOfst[13]=7 cells (2 PI)
7686 14:44:31.622930 u2DelayCellOfst[14]=14 cells (4 PI)
7687 14:44:31.625734 u2DelayCellOfst[15]=10 cells (3 PI)
7688 14:44:31.632631 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7689 14:44:31.635884 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7690 14:44:31.635986 DramC Write-DBI on
7691 14:44:31.636078 ==
7692 14:44:31.639060 Dram Type= 6, Freq= 0, CH_0, rank 0
7693 14:44:31.645431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7694 14:44:31.645522 ==
7695 14:44:31.645601
7696 14:44:31.645660
7697 14:44:31.645720 TX Vref Scan disable
7698 14:44:31.649992 == TX Byte 0 ==
7699 14:44:31.653785 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7700 14:44:31.656431 == TX Byte 1 ==
7701 14:44:31.660217 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7702 14:44:31.663533 DramC Write-DBI off
7703 14:44:31.663639
7704 14:44:31.663732 [DATLAT]
7705 14:44:31.663847 Freq=1600, CH0 RK0
7706 14:44:31.664001
7707 14:44:31.666295 DATLAT Default: 0xf
7708 14:44:31.669836 0, 0xFFFF, sum = 0
7709 14:44:31.669968 1, 0xFFFF, sum = 0
7710 14:44:31.673088 2, 0xFFFF, sum = 0
7711 14:44:31.673211 3, 0xFFFF, sum = 0
7712 14:44:31.676377 4, 0xFFFF, sum = 0
7713 14:44:31.676511 5, 0xFFFF, sum = 0
7714 14:44:31.679416 6, 0xFFFF, sum = 0
7715 14:44:31.679556 7, 0xFFFF, sum = 0
7716 14:44:31.682619 8, 0xFFFF, sum = 0
7717 14:44:31.682759 9, 0xFFFF, sum = 0
7718 14:44:31.686015 10, 0xFFFF, sum = 0
7719 14:44:31.686150 11, 0xFFFF, sum = 0
7720 14:44:31.689432 12, 0xFFFF, sum = 0
7721 14:44:31.689538 13, 0xFFFF, sum = 0
7722 14:44:31.692530 14, 0x0, sum = 1
7723 14:44:31.692629 15, 0x0, sum = 2
7724 14:44:31.696241 16, 0x0, sum = 3
7725 14:44:31.696344 17, 0x0, sum = 4
7726 14:44:31.699366 best_step = 15
7727 14:44:31.699461
7728 14:44:31.699547 ==
7729 14:44:31.702589 Dram Type= 6, Freq= 0, CH_0, rank 0
7730 14:44:31.705749 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7731 14:44:31.705880 ==
7732 14:44:31.709495 RX Vref Scan: 1
7733 14:44:31.709593
7734 14:44:31.709680 Set Vref Range= 24 -> 127
7735 14:44:31.709767
7736 14:44:31.712388 RX Vref 24 -> 127, step: 1
7737 14:44:31.712488
7738 14:44:31.715992 RX Delay 19 -> 252, step: 4
7739 14:44:31.716100
7740 14:44:31.718998 Set Vref, RX VrefLevel [Byte0]: 24
7741 14:44:31.723027 [Byte1]: 24
7742 14:44:31.723132
7743 14:44:31.725606 Set Vref, RX VrefLevel [Byte0]: 25
7744 14:44:31.729170 [Byte1]: 25
7745 14:44:31.732439
7746 14:44:31.732514 Set Vref, RX VrefLevel [Byte0]: 26
7747 14:44:31.735905 [Byte1]: 26
7748 14:44:31.740129
7749 14:44:31.740240 Set Vref, RX VrefLevel [Byte0]: 27
7750 14:44:31.743781 [Byte1]: 27
7751 14:44:31.747620
7752 14:44:31.747723 Set Vref, RX VrefLevel [Byte0]: 28
7753 14:44:31.750762 [Byte1]: 28
7754 14:44:31.755508
7755 14:44:31.755620 Set Vref, RX VrefLevel [Byte0]: 29
7756 14:44:31.758631 [Byte1]: 29
7757 14:44:31.762980
7758 14:44:31.763054 Set Vref, RX VrefLevel [Byte0]: 30
7759 14:44:31.766172 [Byte1]: 30
7760 14:44:31.770554
7761 14:44:31.770663 Set Vref, RX VrefLevel [Byte0]: 31
7762 14:44:31.774130 [Byte1]: 31
7763 14:44:31.778342
7764 14:44:31.778445 Set Vref, RX VrefLevel [Byte0]: 32
7765 14:44:31.781050 [Byte1]: 32
7766 14:44:31.785534
7767 14:44:31.785644 Set Vref, RX VrefLevel [Byte0]: 33
7768 14:44:31.788839 [Byte1]: 33
7769 14:44:31.793467
7770 14:44:31.793547 Set Vref, RX VrefLevel [Byte0]: 34
7771 14:44:31.796189 [Byte1]: 34
7772 14:44:31.801108
7773 14:44:31.801209 Set Vref, RX VrefLevel [Byte0]: 35
7774 14:44:31.804349 [Byte1]: 35
7775 14:44:31.808314
7776 14:44:31.808390 Set Vref, RX VrefLevel [Byte0]: 36
7777 14:44:31.811706 [Byte1]: 36
7778 14:44:31.815925
7779 14:44:31.816032 Set Vref, RX VrefLevel [Byte0]: 37
7780 14:44:31.819533 [Byte1]: 37
7781 14:44:31.823666
7782 14:44:31.823769 Set Vref, RX VrefLevel [Byte0]: 38
7783 14:44:31.827037 [Byte1]: 38
7784 14:44:31.830889
7785 14:44:31.830987 Set Vref, RX VrefLevel [Byte0]: 39
7786 14:44:31.834276 [Byte1]: 39
7787 14:44:31.838627
7788 14:44:31.838724 Set Vref, RX VrefLevel [Byte0]: 40
7789 14:44:31.842059 [Byte1]: 40
7790 14:44:31.846138
7791 14:44:31.846236 Set Vref, RX VrefLevel [Byte0]: 41
7792 14:44:31.849254 [Byte1]: 41
7793 14:44:31.853709
7794 14:44:31.853810 Set Vref, RX VrefLevel [Byte0]: 42
7795 14:44:31.856871 [Byte1]: 42
7796 14:44:31.861233
7797 14:44:31.861357 Set Vref, RX VrefLevel [Byte0]: 43
7798 14:44:31.864758 [Byte1]: 43
7799 14:44:31.868825
7800 14:44:31.868930 Set Vref, RX VrefLevel [Byte0]: 44
7801 14:44:31.872270 [Byte1]: 44
7802 14:44:31.876419
7803 14:44:31.876522 Set Vref, RX VrefLevel [Byte0]: 45
7804 14:44:31.879697 [Byte1]: 45
7805 14:44:31.884130
7806 14:44:31.884230 Set Vref, RX VrefLevel [Byte0]: 46
7807 14:44:31.887366 [Byte1]: 46
7808 14:44:31.891445
7809 14:44:31.891582 Set Vref, RX VrefLevel [Byte0]: 47
7810 14:44:31.894736 [Byte1]: 47
7811 14:44:31.898913
7812 14:44:31.899023 Set Vref, RX VrefLevel [Byte0]: 48
7813 14:44:31.902857 [Byte1]: 48
7814 14:44:31.907053
7815 14:44:31.907153 Set Vref, RX VrefLevel [Byte0]: 49
7816 14:44:31.910055 [Byte1]: 49
7817 14:44:31.914263
7818 14:44:31.914342 Set Vref, RX VrefLevel [Byte0]: 50
7819 14:44:31.918178 [Byte1]: 50
7820 14:44:31.921696
7821 14:44:31.921770 Set Vref, RX VrefLevel [Byte0]: 51
7822 14:44:31.925025 [Byte1]: 51
7823 14:44:31.929171
7824 14:44:31.929308 Set Vref, RX VrefLevel [Byte0]: 52
7825 14:44:31.932664 [Byte1]: 52
7826 14:44:31.937375
7827 14:44:31.937471 Set Vref, RX VrefLevel [Byte0]: 53
7828 14:44:31.940518 [Byte1]: 53
7829 14:44:31.944701
7830 14:44:31.944800 Set Vref, RX VrefLevel [Byte0]: 54
7831 14:44:31.948356 [Byte1]: 54
7832 14:44:31.952209
7833 14:44:31.952305 Set Vref, RX VrefLevel [Byte0]: 55
7834 14:44:31.955324 [Byte1]: 55
7835 14:44:31.959993
7836 14:44:31.960091 Set Vref, RX VrefLevel [Byte0]: 56
7837 14:44:31.962932 [Byte1]: 56
7838 14:44:31.968164
7839 14:44:31.968317 Set Vref, RX VrefLevel [Byte0]: 57
7840 14:44:31.970490 [Byte1]: 57
7841 14:44:31.975060
7842 14:44:31.975197 Set Vref, RX VrefLevel [Byte0]: 58
7843 14:44:31.978231 [Byte1]: 58
7844 14:44:31.982722
7845 14:44:31.982896 Set Vref, RX VrefLevel [Byte0]: 59
7846 14:44:31.985816 [Byte1]: 59
7847 14:44:31.989957
7848 14:44:31.990090 Set Vref, RX VrefLevel [Byte0]: 60
7849 14:44:31.993461 [Byte1]: 60
7850 14:44:31.998128
7851 14:44:31.998231 Set Vref, RX VrefLevel [Byte0]: 61
7852 14:44:32.000726 [Byte1]: 61
7853 14:44:32.004867
7854 14:44:32.004969 Set Vref, RX VrefLevel [Byte0]: 62
7855 14:44:32.008275 [Byte1]: 62
7856 14:44:32.012739
7857 14:44:32.012846 Set Vref, RX VrefLevel [Byte0]: 63
7858 14:44:32.016249 [Byte1]: 63
7859 14:44:32.020336
7860 14:44:32.020443 Set Vref, RX VrefLevel [Byte0]: 64
7861 14:44:32.024022 [Byte1]: 64
7862 14:44:32.027906
7863 14:44:32.028008 Set Vref, RX VrefLevel [Byte0]: 65
7864 14:44:32.031428 [Byte1]: 65
7865 14:44:32.035746
7866 14:44:32.035850 Set Vref, RX VrefLevel [Byte0]: 66
7867 14:44:32.038666 [Byte1]: 66
7868 14:44:32.042941
7869 14:44:32.043044 Set Vref, RX VrefLevel [Byte0]: 67
7870 14:44:32.046499 [Byte1]: 67
7871 14:44:32.050724
7872 14:44:32.050824 Set Vref, RX VrefLevel [Byte0]: 68
7873 14:44:32.053991 [Byte1]: 68
7874 14:44:32.058209
7875 14:44:32.058312 Set Vref, RX VrefLevel [Byte0]: 69
7876 14:44:32.061401 [Byte1]: 69
7877 14:44:32.065429
7878 14:44:32.068989 Set Vref, RX VrefLevel [Byte0]: 70
7879 14:44:32.072511 [Byte1]: 70
7880 14:44:32.072611
7881 14:44:32.075679 Set Vref, RX VrefLevel [Byte0]: 71
7882 14:44:32.078973 [Byte1]: 71
7883 14:44:32.079079
7884 14:44:32.082067 Set Vref, RX VrefLevel [Byte0]: 72
7885 14:44:32.085337 [Byte1]: 72
7886 14:44:32.085444
7887 14:44:32.088656 Set Vref, RX VrefLevel [Byte0]: 73
7888 14:44:32.092086 [Byte1]: 73
7889 14:44:32.095825
7890 14:44:32.095925 Set Vref, RX VrefLevel [Byte0]: 74
7891 14:44:32.099395 [Byte1]: 74
7892 14:44:32.103710
7893 14:44:32.103815 Final RX Vref Byte 0 = 56 to rank0
7894 14:44:32.106846 Final RX Vref Byte 1 = 58 to rank0
7895 14:44:32.110514 Final RX Vref Byte 0 = 56 to rank1
7896 14:44:32.113473 Final RX Vref Byte 1 = 58 to rank1==
7897 14:44:32.116696 Dram Type= 6, Freq= 0, CH_0, rank 0
7898 14:44:32.123160 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7899 14:44:32.123318 ==
7900 14:44:32.123436 DQS Delay:
7901 14:44:32.127091 DQS0 = 0, DQS1 = 0
7902 14:44:32.127220 DQM Delay:
7903 14:44:32.127334 DQM0 = 128, DQM1 = 124
7904 14:44:32.129852 DQ Delay:
7905 14:44:32.133201 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7906 14:44:32.137075 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
7907 14:44:32.140192 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7908 14:44:32.143125 DQ12 =132, DQ13 =128, DQ14 =134, DQ15 =130
7909 14:44:32.143198
7910 14:44:32.143260
7911 14:44:32.143318
7912 14:44:32.146640 [DramC_TX_OE_Calibration] TA2
7913 14:44:32.149710 Original DQ_B0 (3 6) =30, OEN = 27
7914 14:44:32.153086 Original DQ_B1 (3 6) =30, OEN = 27
7915 14:44:32.156418 24, 0x0, End_B0=24 End_B1=24
7916 14:44:32.160009 25, 0x0, End_B0=25 End_B1=25
7917 14:44:32.160091 26, 0x0, End_B0=26 End_B1=26
7918 14:44:32.162916 27, 0x0, End_B0=27 End_B1=27
7919 14:44:32.166663 28, 0x0, End_B0=28 End_B1=28
7920 14:44:32.169393 29, 0x0, End_B0=29 End_B1=29
7921 14:44:32.169495 30, 0x0, End_B0=30 End_B1=30
7922 14:44:32.172839 31, 0x5151, End_B0=30 End_B1=30
7923 14:44:32.176192 Byte0 end_step=30 best_step=27
7924 14:44:32.179434 Byte1 end_step=30 best_step=27
7925 14:44:32.182804 Byte0 TX OE(2T, 0.5T) = (3, 3)
7926 14:44:32.186282 Byte1 TX OE(2T, 0.5T) = (3, 3)
7927 14:44:32.186394
7928 14:44:32.186486
7929 14:44:32.193043 [DQSOSCAuto] RK0, (LSB)MR18= 0x1815, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7930 14:44:32.195733 CH0 RK0: MR19=303, MR18=1815
7931 14:44:32.202303 CH0_RK0: MR19=0x303, MR18=0x1815, DQSOSC=397, MR23=63, INC=23, DEC=15
7932 14:44:32.202379
7933 14:44:32.205464 ----->DramcWriteLeveling(PI) begin...
7934 14:44:32.205537 ==
7935 14:44:32.208891 Dram Type= 6, Freq= 0, CH_0, rank 1
7936 14:44:32.211940 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7937 14:44:32.212040 ==
7938 14:44:32.215398 Write leveling (Byte 0): 34 => 34
7939 14:44:32.219077 Write leveling (Byte 1): 26 => 26
7940 14:44:32.222138 DramcWriteLeveling(PI) end<-----
7941 14:44:32.222214
7942 14:44:32.222276 ==
7943 14:44:32.225215 Dram Type= 6, Freq= 0, CH_0, rank 1
7944 14:44:32.232235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7945 14:44:32.232312 ==
7946 14:44:32.232395 [Gating] SW mode calibration
7947 14:44:32.241846 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7948 14:44:32.245836 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7949 14:44:32.248371 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7950 14:44:32.255475 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7951 14:44:32.258221 1 4 8 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
7952 14:44:32.261851 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7953 14:44:32.268611 1 4 16 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
7954 14:44:32.271951 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7955 14:44:32.275785 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7956 14:44:32.281824 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7957 14:44:32.284654 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7958 14:44:32.288115 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7959 14:44:32.295086 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7960 14:44:32.298375 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7961 14:44:32.301519 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7962 14:44:32.307788 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
7963 14:44:32.311640 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7964 14:44:32.314766 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7965 14:44:32.321507 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7966 14:44:32.324487 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7967 14:44:32.327951 1 6 8 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
7968 14:44:32.334676 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7969 14:44:32.337777 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7970 14:44:32.340671 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7971 14:44:32.347672 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7972 14:44:32.350764 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7973 14:44:32.354065 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7974 14:44:32.360638 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7975 14:44:32.364199 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7976 14:44:32.367077 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7977 14:44:32.373576 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7978 14:44:32.377423 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7979 14:44:32.380274 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7980 14:44:32.386597 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7981 14:44:32.390095 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7982 14:44:32.393813 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7983 14:44:32.400001 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7984 14:44:32.403483 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7985 14:44:32.407034 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7986 14:44:32.413995 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7987 14:44:32.417144 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7988 14:44:32.420374 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 14:44:32.426529 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 14:44:32.429907 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 14:44:32.433167 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7992 14:44:32.439574 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7993 14:44:32.443306 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7994 14:44:32.446265 Total UI for P1: 0, mck2ui 16
7995 14:44:32.449779 best dqsien dly found for B0: ( 1, 9, 10)
7996 14:44:32.453102 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7997 14:44:32.456221 Total UI for P1: 0, mck2ui 16
7998 14:44:32.459824 best dqsien dly found for B1: ( 1, 9, 16)
7999 14:44:32.462928 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8000 14:44:32.466133 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8001 14:44:32.469606
8002 14:44:32.472906 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8003 14:44:32.476407 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8004 14:44:32.479836 [Gating] SW calibration Done
8005 14:44:32.479936 ==
8006 14:44:32.483322 Dram Type= 6, Freq= 0, CH_0, rank 1
8007 14:44:32.486206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8008 14:44:32.486305 ==
8009 14:44:32.489502 RX Vref Scan: 0
8010 14:44:32.489596
8011 14:44:32.489683 RX Vref 0 -> 0, step: 1
8012 14:44:32.489768
8013 14:44:32.492897 RX Delay 0 -> 252, step: 8
8014 14:44:32.496010 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8015 14:44:32.499027 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8016 14:44:32.506242 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8017 14:44:32.509119 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8018 14:44:32.512615 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8019 14:44:32.515680 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8020 14:44:32.519371 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8021 14:44:32.525902 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8022 14:44:32.529497 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8023 14:44:32.532155 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8024 14:44:32.535413 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8025 14:44:32.542110 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8026 14:44:32.545472 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8027 14:44:32.548708 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8028 14:44:32.551871 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8029 14:44:32.555107 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8030 14:44:32.558377 ==
8031 14:44:32.561575 Dram Type= 6, Freq= 0, CH_0, rank 1
8032 14:44:32.565083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8033 14:44:32.565185 ==
8034 14:44:32.565277 DQS Delay:
8035 14:44:32.568248 DQS0 = 0, DQS1 = 0
8036 14:44:32.568342 DQM Delay:
8037 14:44:32.571388 DQM0 = 132, DQM1 = 124
8038 14:44:32.571483 DQ Delay:
8039 14:44:32.575010 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =127
8040 14:44:32.578179 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8041 14:44:32.581646 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
8042 14:44:32.584931 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
8043 14:44:32.585031
8044 14:44:32.585121
8045 14:44:32.585208 ==
8046 14:44:32.588462 Dram Type= 6, Freq= 0, CH_0, rank 1
8047 14:44:32.594809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8048 14:44:32.594910 ==
8049 14:44:32.594999
8050 14:44:32.595083
8051 14:44:32.597904 TX Vref Scan disable
8052 14:44:32.597998 == TX Byte 0 ==
8053 14:44:32.601436 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8054 14:44:32.608370 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8055 14:44:32.608470 == TX Byte 1 ==
8056 14:44:32.611100 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8057 14:44:32.617674 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8058 14:44:32.617774 ==
8059 14:44:32.621327 Dram Type= 6, Freq= 0, CH_0, rank 1
8060 14:44:32.624118 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8061 14:44:32.624215 ==
8062 14:44:32.638086
8063 14:44:32.641803 TX Vref early break, caculate TX vref
8064 14:44:32.645269 TX Vref=16, minBit 9, minWin=22, winSum=379
8065 14:44:32.648137 TX Vref=18, minBit 9, minWin=23, winSum=390
8066 14:44:32.651750 TX Vref=20, minBit 9, minWin=24, winSum=399
8067 14:44:32.654723 TX Vref=22, minBit 10, minWin=24, winSum=405
8068 14:44:32.658408 TX Vref=24, minBit 10, minWin=24, winSum=407
8069 14:44:32.664544 TX Vref=26, minBit 4, minWin=25, winSum=415
8070 14:44:32.668101 TX Vref=28, minBit 8, minWin=25, winSum=418
8071 14:44:32.671561 TX Vref=30, minBit 0, minWin=25, winSum=413
8072 14:44:32.674783 TX Vref=32, minBit 0, minWin=24, winSum=405
8073 14:44:32.678179 TX Vref=34, minBit 1, minWin=24, winSum=394
8074 14:44:32.684998 [TxChooseVref] Worse bit 8, Min win 25, Win sum 418, Final Vref 28
8075 14:44:32.685099
8076 14:44:32.687590 Final TX Range 0 Vref 28
8077 14:44:32.687685
8078 14:44:32.687773 ==
8079 14:44:32.691382 Dram Type= 6, Freq= 0, CH_0, rank 1
8080 14:44:32.694621 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8081 14:44:32.694718 ==
8082 14:44:32.694805
8083 14:44:32.694889
8084 14:44:32.698710 TX Vref Scan disable
8085 14:44:32.704822 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8086 14:44:32.704924 == TX Byte 0 ==
8087 14:44:32.707879 u2DelayCellOfst[0]=14 cells (4 PI)
8088 14:44:32.711094 u2DelayCellOfst[1]=17 cells (5 PI)
8089 14:44:32.714525 u2DelayCellOfst[2]=10 cells (3 PI)
8090 14:44:32.717618 u2DelayCellOfst[3]=14 cells (4 PI)
8091 14:44:32.720598 u2DelayCellOfst[4]=10 cells (3 PI)
8092 14:44:32.724176 u2DelayCellOfst[5]=0 cells (0 PI)
8093 14:44:32.727606 u2DelayCellOfst[6]=17 cells (5 PI)
8094 14:44:32.730588 u2DelayCellOfst[7]=17 cells (5 PI)
8095 14:44:32.733760 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8096 14:44:32.737184 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8097 14:44:32.740416 == TX Byte 1 ==
8098 14:44:32.743593 u2DelayCellOfst[8]=0 cells (0 PI)
8099 14:44:32.746867 u2DelayCellOfst[9]=0 cells (0 PI)
8100 14:44:32.750545 u2DelayCellOfst[10]=3 cells (1 PI)
8101 14:44:32.753838 u2DelayCellOfst[11]=3 cells (1 PI)
8102 14:44:32.753943 u2DelayCellOfst[12]=7 cells (2 PI)
8103 14:44:32.756760 u2DelayCellOfst[13]=7 cells (2 PI)
8104 14:44:32.760405 u2DelayCellOfst[14]=14 cells (4 PI)
8105 14:44:32.763542 u2DelayCellOfst[15]=7 cells (2 PI)
8106 14:44:32.770201 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8107 14:44:32.773451 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8108 14:44:32.773528 DramC Write-DBI on
8109 14:44:32.776744 ==
8110 14:44:32.776822 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 14:44:32.783838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 14:44:32.783948 ==
8113 14:44:32.784041
8114 14:44:32.784128
8115 14:44:32.786505 TX Vref Scan disable
8116 14:44:32.786608 == TX Byte 0 ==
8117 14:44:32.793348 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8118 14:44:32.793472 == TX Byte 1 ==
8119 14:44:32.796625 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8120 14:44:32.799597 DramC Write-DBI off
8121 14:44:32.799696
8122 14:44:32.799784 [DATLAT]
8123 14:44:32.802885 Freq=1600, CH0 RK1
8124 14:44:32.802988
8125 14:44:32.803080 DATLAT Default: 0xf
8126 14:44:32.806189 0, 0xFFFF, sum = 0
8127 14:44:32.806266 1, 0xFFFF, sum = 0
8128 14:44:32.809521 2, 0xFFFF, sum = 0
8129 14:44:32.809617 3, 0xFFFF, sum = 0
8130 14:44:32.812746 4, 0xFFFF, sum = 0
8131 14:44:32.816890 5, 0xFFFF, sum = 0
8132 14:44:32.816999 6, 0xFFFF, sum = 0
8133 14:44:32.819389 7, 0xFFFF, sum = 0
8134 14:44:32.819490 8, 0xFFFF, sum = 0
8135 14:44:32.822712 9, 0xFFFF, sum = 0
8136 14:44:32.822823 10, 0xFFFF, sum = 0
8137 14:44:32.825871 11, 0xFFFF, sum = 0
8138 14:44:32.825953 12, 0xFFFF, sum = 0
8139 14:44:32.829738 13, 0xFFFF, sum = 0
8140 14:44:32.829816 14, 0x0, sum = 1
8141 14:44:32.832902 15, 0x0, sum = 2
8142 14:44:32.833006 16, 0x0, sum = 3
8143 14:44:32.836065 17, 0x0, sum = 4
8144 14:44:32.836150 best_step = 15
8145 14:44:32.836214
8146 14:44:32.836276 ==
8147 14:44:32.839322 Dram Type= 6, Freq= 0, CH_0, rank 1
8148 14:44:32.842514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8149 14:44:32.845953 ==
8150 14:44:32.846033 RX Vref Scan: 0
8151 14:44:32.846095
8152 14:44:32.848945 RX Vref 0 -> 0, step: 1
8153 14:44:32.849055
8154 14:44:32.852292 RX Delay 11 -> 252, step: 4
8155 14:44:32.855558 iDelay=191, Bit 0, Center 128 (79 ~ 178) 100
8156 14:44:32.858890 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8157 14:44:32.862220 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8158 14:44:32.869405 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8159 14:44:32.872578 iDelay=191, Bit 4, Center 130 (83 ~ 178) 96
8160 14:44:32.875472 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8161 14:44:32.878666 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8162 14:44:32.882068 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8163 14:44:32.888658 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8164 14:44:32.892340 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8165 14:44:32.895132 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8166 14:44:32.898474 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8167 14:44:32.902042 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8168 14:44:32.908599 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8169 14:44:32.912369 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8170 14:44:32.915011 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8171 14:44:32.915121 ==
8172 14:44:32.918680 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 14:44:32.922136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 14:44:32.925053 ==
8175 14:44:32.925161 DQS Delay:
8176 14:44:32.925252 DQS0 = 0, DQS1 = 0
8177 14:44:32.928435 DQM Delay:
8178 14:44:32.928540 DQM0 = 129, DQM1 = 124
8179 14:44:32.932010 DQ Delay:
8180 14:44:32.934830 DQ0 =128, DQ1 =132, DQ2 =124, DQ3 =126
8181 14:44:32.938348 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =134
8182 14:44:32.941336 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8183 14:44:32.944622 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =132
8184 14:44:32.944721
8185 14:44:32.944811
8186 14:44:32.944907
8187 14:44:32.947726 [DramC_TX_OE_Calibration] TA2
8188 14:44:32.951173 Original DQ_B0 (3 6) =30, OEN = 27
8189 14:44:32.954283 Original DQ_B1 (3 6) =30, OEN = 27
8190 14:44:32.957533 24, 0x0, End_B0=24 End_B1=24
8191 14:44:32.957630 25, 0x0, End_B0=25 End_B1=25
8192 14:44:32.960885 26, 0x0, End_B0=26 End_B1=26
8193 14:44:32.964397 27, 0x0, End_B0=27 End_B1=27
8194 14:44:32.967593 28, 0x0, End_B0=28 End_B1=28
8195 14:44:32.971150 29, 0x0, End_B0=29 End_B1=29
8196 14:44:32.971225 30, 0x0, End_B0=30 End_B1=30
8197 14:44:32.974419 31, 0x4545, End_B0=30 End_B1=30
8198 14:44:32.977372 Byte0 end_step=30 best_step=27
8199 14:44:32.980940 Byte1 end_step=30 best_step=27
8200 14:44:32.984058 Byte0 TX OE(2T, 0.5T) = (3, 3)
8201 14:44:32.987542 Byte1 TX OE(2T, 0.5T) = (3, 3)
8202 14:44:32.987643
8203 14:44:32.987732
8204 14:44:32.993898 [DQSOSCAuto] RK1, (LSB)MR18= 0x1816, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
8205 14:44:32.997023 CH0 RK1: MR19=303, MR18=1816
8206 14:44:33.003677 CH0_RK1: MR19=0x303, MR18=0x1816, DQSOSC=397, MR23=63, INC=23, DEC=15
8207 14:44:33.007192 [RxdqsGatingPostProcess] freq 1600
8208 14:44:33.013880 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8209 14:44:33.013959 best DQS0 dly(2T, 0.5T) = (1, 1)
8210 14:44:33.016796 best DQS1 dly(2T, 0.5T) = (1, 1)
8211 14:44:33.020133 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8212 14:44:33.023923 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8213 14:44:33.026742 best DQS0 dly(2T, 0.5T) = (1, 1)
8214 14:44:33.029988 best DQS1 dly(2T, 0.5T) = (1, 1)
8215 14:44:33.034078 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8216 14:44:33.036694 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8217 14:44:33.039737 Pre-setting of DQS Precalculation
8218 14:44:33.043793 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8219 14:44:33.043883 ==
8220 14:44:33.047340 Dram Type= 6, Freq= 0, CH_1, rank 0
8221 14:44:33.053421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8222 14:44:33.053500 ==
8223 14:44:33.056230 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8224 14:44:33.063252 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8225 14:44:33.066624 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8226 14:44:33.073125 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8227 14:44:33.081041 [CA 0] Center 42 (13~72) winsize 60
8228 14:44:33.084152 [CA 1] Center 42 (13~72) winsize 60
8229 14:44:33.087906 [CA 2] Center 38 (9~68) winsize 60
8230 14:44:33.091110 [CA 3] Center 37 (8~67) winsize 60
8231 14:44:33.094270 [CA 4] Center 38 (8~69) winsize 62
8232 14:44:33.097413 [CA 5] Center 37 (8~67) winsize 60
8233 14:44:33.097501
8234 14:44:33.100549 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8235 14:44:33.100621
8236 14:44:33.107335 [CATrainingPosCal] consider 1 rank data
8237 14:44:33.107436 u2DelayCellTimex100 = 275/100 ps
8238 14:44:33.113812 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8239 14:44:33.117513 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8240 14:44:33.120482 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8241 14:44:33.123734 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8242 14:44:33.127095 CA4 delay=38 (8~69),Diff = 1 PI (3 cell)
8243 14:44:33.130119 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8244 14:44:33.130224
8245 14:44:33.133563 CA PerBit enable=1, Macro0, CA PI delay=37
8246 14:44:33.133661
8247 14:44:33.136729 [CBTSetCACLKResult] CA Dly = 37
8248 14:44:33.140528 CS Dly: 8 (0~39)
8249 14:44:33.143515 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8250 14:44:33.147394 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8251 14:44:33.147482 ==
8252 14:44:33.150014 Dram Type= 6, Freq= 0, CH_1, rank 1
8253 14:44:33.156490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8254 14:44:33.156598 ==
8255 14:44:33.159944 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8256 14:44:33.166975 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8257 14:44:33.169940 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8258 14:44:33.176614 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8259 14:44:33.184596 [CA 0] Center 42 (12~72) winsize 61
8260 14:44:33.187589 [CA 1] Center 42 (13~72) winsize 60
8261 14:44:33.190467 [CA 2] Center 38 (8~68) winsize 61
8262 14:44:33.193742 [CA 3] Center 37 (7~67) winsize 61
8263 14:44:33.197048 [CA 4] Center 37 (7~67) winsize 61
8264 14:44:33.200963 [CA 5] Center 37 (7~67) winsize 61
8265 14:44:33.201064
8266 14:44:33.203899 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8267 14:44:33.204008
8268 14:44:33.207419 [CATrainingPosCal] consider 2 rank data
8269 14:44:33.210165 u2DelayCellTimex100 = 275/100 ps
8270 14:44:33.217642 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8271 14:44:33.220373 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8272 14:44:33.223707 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8273 14:44:33.227353 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8274 14:44:33.230308 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8275 14:44:33.233905 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8276 14:44:33.233980
8277 14:44:33.236957 CA PerBit enable=1, Macro0, CA PI delay=37
8278 14:44:33.237055
8279 14:44:33.240629 [CBTSetCACLKResult] CA Dly = 37
8280 14:44:33.243346 CS Dly: 9 (0~42)
8281 14:44:33.247351 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8282 14:44:33.249993 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8283 14:44:33.250069
8284 14:44:33.253397 ----->DramcWriteLeveling(PI) begin...
8285 14:44:33.253472 ==
8286 14:44:33.256753 Dram Type= 6, Freq= 0, CH_1, rank 0
8287 14:44:33.263056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8288 14:44:33.263160 ==
8289 14:44:33.266637 Write leveling (Byte 0): 26 => 26
8290 14:44:33.270277 Write leveling (Byte 1): 28 => 28
8291 14:44:33.270379 DramcWriteLeveling(PI) end<-----
8292 14:44:33.270444
8293 14:44:33.273180 ==
8294 14:44:33.276931 Dram Type= 6, Freq= 0, CH_1, rank 0
8295 14:44:33.279559 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8296 14:44:33.279671 ==
8297 14:44:33.283230 [Gating] SW mode calibration
8298 14:44:33.289979 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8299 14:44:33.293488 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8300 14:44:33.299597 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8301 14:44:33.302843 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8302 14:44:33.306221 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8303 14:44:33.313048 1 4 12 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
8304 14:44:33.315837 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8305 14:44:33.318971 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8306 14:44:33.325718 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8307 14:44:33.329111 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8308 14:44:33.332466 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8309 14:44:33.339011 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8310 14:44:33.342279 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8311 14:44:33.345416 1 5 12 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
8312 14:44:33.352791 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8313 14:44:33.355867 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8314 14:44:33.359483 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8315 14:44:33.365252 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8316 14:44:33.368769 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8317 14:44:33.371847 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8318 14:44:33.378310 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8319 14:44:33.381987 1 6 12 | B1->B0 | 3232 4343 | 0 1 | (0 0) (0 0)
8320 14:44:33.385432 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8321 14:44:33.391562 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8322 14:44:33.395292 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8323 14:44:33.398282 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8324 14:44:33.404634 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8325 14:44:33.408119 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8326 14:44:33.411576 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8327 14:44:33.418083 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8328 14:44:33.421366 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8329 14:44:33.424782 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8330 14:44:33.431167 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8331 14:44:33.435064 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8332 14:44:33.437939 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8333 14:44:33.444641 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8334 14:44:33.448047 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8335 14:44:33.450948 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8336 14:44:33.457654 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8337 14:44:33.460577 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8338 14:44:33.464448 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 14:44:33.470762 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 14:44:33.474354 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 14:44:33.476977 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 14:44:33.483938 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8343 14:44:33.487491 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8344 14:44:33.490378 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8345 14:44:33.493500 Total UI for P1: 0, mck2ui 16
8346 14:44:33.497225 best dqsien dly found for B0: ( 1, 9, 10)
8347 14:44:33.503611 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8348 14:44:33.506980 Total UI for P1: 0, mck2ui 16
8349 14:44:33.510235 best dqsien dly found for B1: ( 1, 9, 14)
8350 14:44:33.513209 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8351 14:44:33.516941 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8352 14:44:33.517047
8353 14:44:33.520107 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8354 14:44:33.523238 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8355 14:44:33.526703 [Gating] SW calibration Done
8356 14:44:33.526780 ==
8357 14:44:33.530456 Dram Type= 6, Freq= 0, CH_1, rank 0
8358 14:44:33.533496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8359 14:44:33.533573 ==
8360 14:44:33.536416 RX Vref Scan: 0
8361 14:44:33.536519
8362 14:44:33.539833 RX Vref 0 -> 0, step: 1
8363 14:44:33.539928
8364 14:44:33.540020 RX Delay 0 -> 252, step: 8
8365 14:44:33.546605 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8366 14:44:33.549692 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8367 14:44:33.552882 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8368 14:44:33.556203 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8369 14:44:33.559666 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8370 14:44:33.566374 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8371 14:44:33.569784 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8372 14:44:33.572983 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8373 14:44:33.575980 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8374 14:44:33.579333 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8375 14:44:33.586058 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8376 14:44:33.589192 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8377 14:44:33.593380 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8378 14:44:33.595975 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8379 14:44:33.602915 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8380 14:44:33.605840 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8381 14:44:33.605955 ==
8382 14:44:33.608837 Dram Type= 6, Freq= 0, CH_1, rank 0
8383 14:44:33.612148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8384 14:44:33.612225 ==
8385 14:44:33.615588 DQS Delay:
8386 14:44:33.615691 DQS0 = 0, DQS1 = 0
8387 14:44:33.615780 DQM Delay:
8388 14:44:33.618877 DQM0 = 134, DQM1 = 129
8389 14:44:33.618968 DQ Delay:
8390 14:44:33.622069 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8391 14:44:33.625349 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =127
8392 14:44:33.631945 DQ8 =111, DQ9 =119, DQ10 =131, DQ11 =123
8393 14:44:33.635241 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8394 14:44:33.635341
8395 14:44:33.635431
8396 14:44:33.635516 ==
8397 14:44:33.638501 Dram Type= 6, Freq= 0, CH_1, rank 0
8398 14:44:33.641821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8399 14:44:33.641899 ==
8400 14:44:33.641959
8401 14:44:33.642016
8402 14:44:33.645328 TX Vref Scan disable
8403 14:44:33.648487 == TX Byte 0 ==
8404 14:44:33.651671 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8405 14:44:33.654999 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8406 14:44:33.658314 == TX Byte 1 ==
8407 14:44:33.661505 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8408 14:44:33.665419 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8409 14:44:33.665496 ==
8410 14:44:33.668319 Dram Type= 6, Freq= 0, CH_1, rank 0
8411 14:44:33.674841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8412 14:44:33.674919 ==
8413 14:44:33.686227
8414 14:44:33.689186 TX Vref early break, caculate TX vref
8415 14:44:33.693017 TX Vref=16, minBit 8, minWin=21, winSum=368
8416 14:44:33.695899 TX Vref=18, minBit 9, minWin=22, winSum=377
8417 14:44:33.699675 TX Vref=20, minBit 8, minWin=23, winSum=386
8418 14:44:33.702624 TX Vref=22, minBit 12, minWin=23, winSum=399
8419 14:44:33.709008 TX Vref=24, minBit 9, minWin=24, winSum=407
8420 14:44:33.712842 TX Vref=26, minBit 8, minWin=24, winSum=416
8421 14:44:33.716077 TX Vref=28, minBit 0, minWin=26, winSum=420
8422 14:44:33.718875 TX Vref=30, minBit 10, minWin=25, winSum=419
8423 14:44:33.722046 TX Vref=32, minBit 0, minWin=24, winSum=405
8424 14:44:33.725868 TX Vref=34, minBit 9, minWin=23, winSum=396
8425 14:44:33.732550 [TxChooseVref] Worse bit 0, Min win 26, Win sum 420, Final Vref 28
8426 14:44:33.732648
8427 14:44:33.735510 Final TX Range 0 Vref 28
8428 14:44:33.735604
8429 14:44:33.735691 ==
8430 14:44:33.738698 Dram Type= 6, Freq= 0, CH_1, rank 0
8431 14:44:33.741940 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8432 14:44:33.742016 ==
8433 14:44:33.742077
8434 14:44:33.742133
8435 14:44:33.745478 TX Vref Scan disable
8436 14:44:33.752454 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8437 14:44:33.752586 == TX Byte 0 ==
8438 14:44:33.755834 u2DelayCellOfst[0]=17 cells (5 PI)
8439 14:44:33.758586 u2DelayCellOfst[1]=10 cells (3 PI)
8440 14:44:33.762378 u2DelayCellOfst[2]=0 cells (0 PI)
8441 14:44:33.765285 u2DelayCellOfst[3]=7 cells (2 PI)
8442 14:44:33.768680 u2DelayCellOfst[4]=7 cells (2 PI)
8443 14:44:33.771702 u2DelayCellOfst[5]=17 cells (5 PI)
8444 14:44:33.774901 u2DelayCellOfst[6]=14 cells (4 PI)
8445 14:44:33.778540 u2DelayCellOfst[7]=7 cells (2 PI)
8446 14:44:33.782296 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8447 14:44:33.785216 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8448 14:44:33.788258 == TX Byte 1 ==
8449 14:44:33.791660 u2DelayCellOfst[8]=0 cells (0 PI)
8450 14:44:33.794916 u2DelayCellOfst[9]=3 cells (1 PI)
8451 14:44:33.798230 u2DelayCellOfst[10]=10 cells (3 PI)
8452 14:44:33.798298 u2DelayCellOfst[11]=7 cells (2 PI)
8453 14:44:33.801502 u2DelayCellOfst[12]=14 cells (4 PI)
8454 14:44:33.804997 u2DelayCellOfst[13]=14 cells (4 PI)
8455 14:44:33.807923 u2DelayCellOfst[14]=17 cells (5 PI)
8456 14:44:33.811700 u2DelayCellOfst[15]=17 cells (5 PI)
8457 14:44:33.817904 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8458 14:44:33.821251 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8459 14:44:33.821380 DramC Write-DBI on
8460 14:44:33.821442 ==
8461 14:44:33.824548 Dram Type= 6, Freq= 0, CH_1, rank 0
8462 14:44:33.831144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8463 14:44:33.831242 ==
8464 14:44:33.831329
8465 14:44:33.831415
8466 14:44:33.831497 TX Vref Scan disable
8467 14:44:33.835495 == TX Byte 0 ==
8468 14:44:33.838542 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8469 14:44:33.842556 == TX Byte 1 ==
8470 14:44:33.845064 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8471 14:44:33.848422 DramC Write-DBI off
8472 14:44:33.848496
8473 14:44:33.848557 [DATLAT]
8474 14:44:33.848620 Freq=1600, CH1 RK0
8475 14:44:33.848705
8476 14:44:33.851722 DATLAT Default: 0xf
8477 14:44:33.854883 0, 0xFFFF, sum = 0
8478 14:44:33.854955 1, 0xFFFF, sum = 0
8479 14:44:33.858105 2, 0xFFFF, sum = 0
8480 14:44:33.858178 3, 0xFFFF, sum = 0
8481 14:44:33.861674 4, 0xFFFF, sum = 0
8482 14:44:33.861752 5, 0xFFFF, sum = 0
8483 14:44:33.865402 6, 0xFFFF, sum = 0
8484 14:44:33.865469 7, 0xFFFF, sum = 0
8485 14:44:33.868211 8, 0xFFFF, sum = 0
8486 14:44:33.868311 9, 0xFFFF, sum = 0
8487 14:44:33.871318 10, 0xFFFF, sum = 0
8488 14:44:33.871414 11, 0xFFFF, sum = 0
8489 14:44:33.875209 12, 0xFFFF, sum = 0
8490 14:44:33.875283 13, 0xFFFF, sum = 0
8491 14:44:33.878786 14, 0x0, sum = 1
8492 14:44:33.878892 15, 0x0, sum = 2
8493 14:44:33.881351 16, 0x0, sum = 3
8494 14:44:33.881452 17, 0x0, sum = 4
8495 14:44:33.885085 best_step = 15
8496 14:44:33.885185
8497 14:44:33.885308 ==
8498 14:44:33.888020 Dram Type= 6, Freq= 0, CH_1, rank 0
8499 14:44:33.891458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8500 14:44:33.891557 ==
8501 14:44:33.895197 RX Vref Scan: 1
8502 14:44:33.895299
8503 14:44:33.895388 Set Vref Range= 24 -> 127
8504 14:44:33.895474
8505 14:44:33.897837 RX Vref 24 -> 127, step: 1
8506 14:44:33.897903
8507 14:44:33.901236 RX Delay 11 -> 252, step: 4
8508 14:44:33.901358
8509 14:44:33.904486 Set Vref, RX VrefLevel [Byte0]: 24
8510 14:44:33.908003 [Byte1]: 24
8511 14:44:33.908101
8512 14:44:33.911214 Set Vref, RX VrefLevel [Byte0]: 25
8513 14:44:33.914946 [Byte1]: 25
8514 14:44:33.918370
8515 14:44:33.918438 Set Vref, RX VrefLevel [Byte0]: 26
8516 14:44:33.921273 [Byte1]: 26
8517 14:44:33.926114
8518 14:44:33.926190 Set Vref, RX VrefLevel [Byte0]: 27
8519 14:44:33.929223 [Byte1]: 27
8520 14:44:33.933566
8521 14:44:33.933671 Set Vref, RX VrefLevel [Byte0]: 28
8522 14:44:33.936651 [Byte1]: 28
8523 14:44:33.941118
8524 14:44:33.941358 Set Vref, RX VrefLevel [Byte0]: 29
8525 14:44:33.944196 [Byte1]: 29
8526 14:44:33.948647
8527 14:44:33.948725 Set Vref, RX VrefLevel [Byte0]: 30
8528 14:44:33.952195 [Byte1]: 30
8529 14:44:33.956259
8530 14:44:33.956355 Set Vref, RX VrefLevel [Byte0]: 31
8531 14:44:33.959348 [Byte1]: 31
8532 14:44:33.963857
8533 14:44:33.963960 Set Vref, RX VrefLevel [Byte0]: 32
8534 14:44:33.967146 [Byte1]: 32
8535 14:44:33.971324
8536 14:44:33.971426 Set Vref, RX VrefLevel [Byte0]: 33
8537 14:44:33.974630 [Byte1]: 33
8538 14:44:33.978812
8539 14:44:33.978929 Set Vref, RX VrefLevel [Byte0]: 34
8540 14:44:33.982471 [Byte1]: 34
8541 14:44:33.986783
8542 14:44:33.986883 Set Vref, RX VrefLevel [Byte0]: 35
8543 14:44:33.990171 [Byte1]: 35
8544 14:44:33.994492
8545 14:44:33.994593 Set Vref, RX VrefLevel [Byte0]: 36
8546 14:44:33.997559 [Byte1]: 36
8547 14:44:34.002013
8548 14:44:34.002116 Set Vref, RX VrefLevel [Byte0]: 37
8549 14:44:34.005345 [Byte1]: 37
8550 14:44:34.009679
8551 14:44:34.009782 Set Vref, RX VrefLevel [Byte0]: 38
8552 14:44:34.012962 [Byte1]: 38
8553 14:44:34.017329
8554 14:44:34.017435 Set Vref, RX VrefLevel [Byte0]: 39
8555 14:44:34.020586 [Byte1]: 39
8556 14:44:34.024592
8557 14:44:34.024694 Set Vref, RX VrefLevel [Byte0]: 40
8558 14:44:34.029318 [Byte1]: 40
8559 14:44:34.032308
8560 14:44:34.032405 Set Vref, RX VrefLevel [Byte0]: 41
8561 14:44:34.035749 [Byte1]: 41
8562 14:44:34.039776
8563 14:44:34.039877 Set Vref, RX VrefLevel [Byte0]: 42
8564 14:44:34.043461 [Byte1]: 42
8565 14:44:34.047428
8566 14:44:34.047528 Set Vref, RX VrefLevel [Byte0]: 43
8567 14:44:34.050674 [Byte1]: 43
8568 14:44:34.055452
8569 14:44:34.055551 Set Vref, RX VrefLevel [Byte0]: 44
8570 14:44:34.058654 [Byte1]: 44
8571 14:44:34.063054
8572 14:44:34.063151 Set Vref, RX VrefLevel [Byte0]: 45
8573 14:44:34.066003 [Byte1]: 45
8574 14:44:34.070339
8575 14:44:34.070451 Set Vref, RX VrefLevel [Byte0]: 46
8576 14:44:34.073968 [Byte1]: 46
8577 14:44:34.078093
8578 14:44:34.078199 Set Vref, RX VrefLevel [Byte0]: 47
8579 14:44:34.081578 [Byte1]: 47
8580 14:44:34.085725
8581 14:44:34.085827 Set Vref, RX VrefLevel [Byte0]: 48
8582 14:44:34.088876 [Byte1]: 48
8583 14:44:34.093648
8584 14:44:34.093758 Set Vref, RX VrefLevel [Byte0]: 49
8585 14:44:34.096622 [Byte1]: 49
8586 14:44:34.100868
8587 14:44:34.100970 Set Vref, RX VrefLevel [Byte0]: 50
8588 14:44:34.104772 [Byte1]: 50
8589 14:44:34.108647
8590 14:44:34.108747 Set Vref, RX VrefLevel [Byte0]: 51
8591 14:44:34.111997 [Byte1]: 51
8592 14:44:34.116050
8593 14:44:34.116150 Set Vref, RX VrefLevel [Byte0]: 52
8594 14:44:34.119277 [Byte1]: 52
8595 14:44:34.124122
8596 14:44:34.124223 Set Vref, RX VrefLevel [Byte0]: 53
8597 14:44:34.126750 [Byte1]: 53
8598 14:44:34.131786
8599 14:44:34.131885 Set Vref, RX VrefLevel [Byte0]: 54
8600 14:44:34.135014 [Byte1]: 54
8601 14:44:34.138881
8602 14:44:34.138956 Set Vref, RX VrefLevel [Byte0]: 55
8603 14:44:34.142768 [Byte1]: 55
8604 14:44:34.146562
8605 14:44:34.146667 Set Vref, RX VrefLevel [Byte0]: 56
8606 14:44:34.149763 [Byte1]: 56
8607 14:44:34.153989
8608 14:44:34.154089 Set Vref, RX VrefLevel [Byte0]: 57
8609 14:44:34.157240 [Byte1]: 57
8610 14:44:34.161828
8611 14:44:34.161908 Set Vref, RX VrefLevel [Byte0]: 58
8612 14:44:34.164950 [Byte1]: 58
8613 14:44:34.169251
8614 14:44:34.169366 Set Vref, RX VrefLevel [Byte0]: 59
8615 14:44:34.172553 [Byte1]: 59
8616 14:44:34.177192
8617 14:44:34.177328 Set Vref, RX VrefLevel [Byte0]: 60
8618 14:44:34.180728 [Byte1]: 60
8619 14:44:34.184690
8620 14:44:34.184790 Set Vref, RX VrefLevel [Byte0]: 61
8621 14:44:34.187958 [Byte1]: 61
8622 14:44:34.192051
8623 14:44:34.192156 Set Vref, RX VrefLevel [Byte0]: 62
8624 14:44:34.195881 [Byte1]: 62
8625 14:44:34.199912
8626 14:44:34.200015 Set Vref, RX VrefLevel [Byte0]: 63
8627 14:44:34.203167 [Byte1]: 63
8628 14:44:34.207287
8629 14:44:34.207392 Set Vref, RX VrefLevel [Byte0]: 64
8630 14:44:34.210672 [Byte1]: 64
8631 14:44:34.215960
8632 14:44:34.216062 Set Vref, RX VrefLevel [Byte0]: 65
8633 14:44:34.218653 [Byte1]: 65
8634 14:44:34.222644
8635 14:44:34.222749 Set Vref, RX VrefLevel [Byte0]: 66
8636 14:44:34.226140 [Byte1]: 66
8637 14:44:34.230653
8638 14:44:34.230766 Set Vref, RX VrefLevel [Byte0]: 67
8639 14:44:34.233551 [Byte1]: 67
8640 14:44:34.237741
8641 14:44:34.237814 Set Vref, RX VrefLevel [Byte0]: 68
8642 14:44:34.241547 [Byte1]: 68
8643 14:44:34.245457
8644 14:44:34.245535 Set Vref, RX VrefLevel [Byte0]: 69
8645 14:44:34.249207 [Byte1]: 69
8646 14:44:34.252864
8647 14:44:34.253010 Set Vref, RX VrefLevel [Byte0]: 70
8648 14:44:34.256147 [Byte1]: 70
8649 14:44:34.260587
8650 14:44:34.260689 Final RX Vref Byte 0 = 58 to rank0
8651 14:44:34.264042 Final RX Vref Byte 1 = 61 to rank0
8652 14:44:34.267229 Final RX Vref Byte 0 = 58 to rank1
8653 14:44:34.270844 Final RX Vref Byte 1 = 61 to rank1==
8654 14:44:34.273677 Dram Type= 6, Freq= 0, CH_1, rank 0
8655 14:44:34.280831 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8656 14:44:34.280943 ==
8657 14:44:34.281035 DQS Delay:
8658 14:44:34.283697 DQS0 = 0, DQS1 = 0
8659 14:44:34.283781 DQM Delay:
8660 14:44:34.283862 DQM0 = 132, DQM1 = 128
8661 14:44:34.287219 DQ Delay:
8662 14:44:34.290415 DQ0 =140, DQ1 =128, DQ2 =118, DQ3 =130
8663 14:44:34.294251 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =126
8664 14:44:34.296761 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =120
8665 14:44:34.300184 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8666 14:44:34.300267
8667 14:44:34.300330
8668 14:44:34.300388
8669 14:44:34.304487 [DramC_TX_OE_Calibration] TA2
8670 14:44:34.306827 Original DQ_B0 (3 6) =30, OEN = 27
8671 14:44:34.310064 Original DQ_B1 (3 6) =30, OEN = 27
8672 14:44:34.313520 24, 0x0, End_B0=24 End_B1=24
8673 14:44:34.317226 25, 0x0, End_B0=25 End_B1=25
8674 14:44:34.317347 26, 0x0, End_B0=26 End_B1=26
8675 14:44:34.320274 27, 0x0, End_B0=27 End_B1=27
8676 14:44:34.323209 28, 0x0, End_B0=28 End_B1=28
8677 14:44:34.326657 29, 0x0, End_B0=29 End_B1=29
8678 14:44:34.326739 30, 0x0, End_B0=30 End_B1=30
8679 14:44:34.330394 31, 0x4141, End_B0=30 End_B1=30
8680 14:44:34.333152 Byte0 end_step=30 best_step=27
8681 14:44:34.336534 Byte1 end_step=30 best_step=27
8682 14:44:34.339946 Byte0 TX OE(2T, 0.5T) = (3, 3)
8683 14:44:34.342896 Byte1 TX OE(2T, 0.5T) = (3, 3)
8684 14:44:34.342978
8685 14:44:34.343041
8686 14:44:34.349807 [DQSOSCAuto] RK0, (LSB)MR18= 0xf17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 402 ps
8687 14:44:34.352935 CH1 RK0: MR19=303, MR18=F17
8688 14:44:34.359480 CH1_RK0: MR19=0x303, MR18=0xF17, DQSOSC=398, MR23=63, INC=23, DEC=15
8689 14:44:34.359562
8690 14:44:34.362657 ----->DramcWriteLeveling(PI) begin...
8691 14:44:34.362740 ==
8692 14:44:34.366070 Dram Type= 6, Freq= 0, CH_1, rank 1
8693 14:44:34.369437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8694 14:44:34.369523 ==
8695 14:44:34.372373 Write leveling (Byte 0): 25 => 25
8696 14:44:34.375988 Write leveling (Byte 1): 27 => 27
8697 14:44:34.379270 DramcWriteLeveling(PI) end<-----
8698 14:44:34.379352
8699 14:44:34.379415 ==
8700 14:44:34.382569 Dram Type= 6, Freq= 0, CH_1, rank 1
8701 14:44:34.388890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8702 14:44:34.388972 ==
8703 14:44:34.389037 [Gating] SW mode calibration
8704 14:44:34.398679 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8705 14:44:34.401916 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8706 14:44:34.405321 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8707 14:44:34.412122 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8708 14:44:34.415194 1 4 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8709 14:44:34.418624 1 4 12 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8710 14:44:34.425374 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8711 14:44:34.428547 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8712 14:44:34.432037 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8713 14:44:34.438953 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8714 14:44:34.442109 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8715 14:44:34.444881 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8716 14:44:34.451442 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8717 14:44:34.455274 1 5 12 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8718 14:44:34.458252 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8719 14:44:34.465389 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8720 14:44:34.468945 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8721 14:44:34.471280 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8722 14:44:34.478167 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8723 14:44:34.481688 1 6 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8724 14:44:34.484813 1 6 8 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8725 14:44:34.491598 1 6 12 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
8726 14:44:34.494262 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8727 14:44:34.497862 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8728 14:44:34.504328 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8729 14:44:34.507657 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8730 14:44:34.511107 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8731 14:44:34.517453 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8732 14:44:34.521070 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8733 14:44:34.524448 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8734 14:44:34.530515 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8735 14:44:34.534277 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8736 14:44:34.537468 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8737 14:44:34.544403 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8738 14:44:34.546839 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8739 14:44:34.550365 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8740 14:44:34.557388 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8741 14:44:34.560147 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8742 14:44:34.563410 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8743 14:44:34.570417 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8744 14:44:34.573706 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8745 14:44:34.576653 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8746 14:44:34.583421 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8747 14:44:34.586503 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8748 14:44:34.590167 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8749 14:44:34.596817 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8750 14:44:34.600116 Total UI for P1: 0, mck2ui 16
8751 14:44:34.603174 best dqsien dly found for B0: ( 1, 9, 6)
8752 14:44:34.606360 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8753 14:44:34.609932 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8754 14:44:34.613319 Total UI for P1: 0, mck2ui 16
8755 14:44:34.616571 best dqsien dly found for B1: ( 1, 9, 12)
8756 14:44:34.620151 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8757 14:44:34.623095 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8758 14:44:34.626609
8759 14:44:34.629605 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8760 14:44:34.632877 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8761 14:44:34.636066 [Gating] SW calibration Done
8762 14:44:34.636148 ==
8763 14:44:34.639441 Dram Type= 6, Freq= 0, CH_1, rank 1
8764 14:44:34.642809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8765 14:44:34.642895 ==
8766 14:44:34.645986 RX Vref Scan: 0
8767 14:44:34.646067
8768 14:44:34.646131 RX Vref 0 -> 0, step: 1
8769 14:44:34.646190
8770 14:44:34.649149 RX Delay 0 -> 252, step: 8
8771 14:44:34.652407 iDelay=200, Bit 0, Center 139 (80 ~ 199) 120
8772 14:44:34.655834 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8773 14:44:34.662448 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8774 14:44:34.666073 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8775 14:44:34.669440 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8776 14:44:34.672787 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8777 14:44:34.675960 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8778 14:44:34.683074 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8779 14:44:34.685654 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8780 14:44:34.689372 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8781 14:44:34.692383 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8782 14:44:34.699014 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8783 14:44:34.702129 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8784 14:44:34.705543 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8785 14:44:34.708730 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8786 14:44:34.711980 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8787 14:44:34.715193 ==
8788 14:44:34.718827 Dram Type= 6, Freq= 0, CH_1, rank 1
8789 14:44:34.722242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8790 14:44:34.722328 ==
8791 14:44:34.722414 DQS Delay:
8792 14:44:34.725422 DQS0 = 0, DQS1 = 0
8793 14:44:34.725507 DQM Delay:
8794 14:44:34.728814 DQM0 = 133, DQM1 = 130
8795 14:44:34.728899 DQ Delay:
8796 14:44:34.731951 DQ0 =139, DQ1 =131, DQ2 =119, DQ3 =131
8797 14:44:34.734992 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =135
8798 14:44:34.738523 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8799 14:44:34.742022 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8800 14:44:34.742103
8801 14:44:34.742166
8802 14:44:34.742224 ==
8803 14:44:34.745370 Dram Type= 6, Freq= 0, CH_1, rank 1
8804 14:44:34.751913 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8805 14:44:34.751995 ==
8806 14:44:34.752059
8807 14:44:34.752119
8808 14:44:34.754926 TX Vref Scan disable
8809 14:44:34.755008 == TX Byte 0 ==
8810 14:44:34.757907 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8811 14:44:34.764605 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8812 14:44:34.764687 == TX Byte 1 ==
8813 14:44:34.768745 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8814 14:44:34.774384 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8815 14:44:34.774466 ==
8816 14:44:34.778476 Dram Type= 6, Freq= 0, CH_1, rank 1
8817 14:44:34.781385 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8818 14:44:34.781500 ==
8819 14:44:34.795479
8820 14:44:34.798848 TX Vref early break, caculate TX vref
8821 14:44:34.802111 TX Vref=16, minBit 9, minWin=22, winSum=379
8822 14:44:34.806082 TX Vref=18, minBit 9, minWin=22, winSum=384
8823 14:44:34.808908 TX Vref=20, minBit 9, minWin=22, winSum=391
8824 14:44:34.811757 TX Vref=22, minBit 9, minWin=22, winSum=401
8825 14:44:34.815235 TX Vref=24, minBit 9, minWin=24, winSum=410
8826 14:44:34.822318 TX Vref=26, minBit 9, minWin=23, winSum=414
8827 14:44:34.825169 TX Vref=28, minBit 9, minWin=25, winSum=419
8828 14:44:34.828312 TX Vref=30, minBit 9, minWin=24, winSum=414
8829 14:44:34.831684 TX Vref=32, minBit 8, minWin=24, winSum=409
8830 14:44:34.835666 TX Vref=34, minBit 0, minWin=24, winSum=401
8831 14:44:34.838354 TX Vref=36, minBit 8, minWin=23, winSum=397
8832 14:44:34.844921 [TxChooseVref] Worse bit 9, Min win 25, Win sum 419, Final Vref 28
8833 14:44:34.845008
8834 14:44:34.848206 Final TX Range 0 Vref 28
8835 14:44:34.848292
8836 14:44:34.848376 ==
8837 14:44:34.852069 Dram Type= 6, Freq= 0, CH_1, rank 1
8838 14:44:34.855024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8839 14:44:34.855109 ==
8840 14:44:34.858665
8841 14:44:34.858749
8842 14:44:34.858833 TX Vref Scan disable
8843 14:44:34.864590 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8844 14:44:34.864675 == TX Byte 0 ==
8845 14:44:34.868333 u2DelayCellOfst[0]=14 cells (4 PI)
8846 14:44:34.871878 u2DelayCellOfst[1]=10 cells (3 PI)
8847 14:44:34.874405 u2DelayCellOfst[2]=0 cells (0 PI)
8848 14:44:34.878116 u2DelayCellOfst[3]=3 cells (1 PI)
8849 14:44:34.881092 u2DelayCellOfst[4]=7 cells (2 PI)
8850 14:44:34.884361 u2DelayCellOfst[5]=14 cells (4 PI)
8851 14:44:34.888481 u2DelayCellOfst[6]=14 cells (4 PI)
8852 14:44:34.891081 u2DelayCellOfst[7]=7 cells (2 PI)
8853 14:44:34.894246 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8854 14:44:34.897647 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8855 14:44:34.901427 == TX Byte 1 ==
8856 14:44:34.903976 u2DelayCellOfst[8]=0 cells (0 PI)
8857 14:44:34.907292 u2DelayCellOfst[9]=0 cells (0 PI)
8858 14:44:34.910978 u2DelayCellOfst[10]=10 cells (3 PI)
8859 14:44:34.913874 u2DelayCellOfst[11]=7 cells (2 PI)
8860 14:44:34.917385 u2DelayCellOfst[12]=14 cells (4 PI)
8861 14:44:34.920420 u2DelayCellOfst[13]=14 cells (4 PI)
8862 14:44:34.920498 u2DelayCellOfst[14]=17 cells (5 PI)
8863 14:44:34.923731 u2DelayCellOfst[15]=14 cells (4 PI)
8864 14:44:34.930658 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8865 14:44:34.933856 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8866 14:44:34.937319 DramC Write-DBI on
8867 14:44:34.937404 ==
8868 14:44:34.940602 Dram Type= 6, Freq= 0, CH_1, rank 1
8869 14:44:34.943470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8870 14:44:34.943556 ==
8871 14:44:34.943641
8872 14:44:34.943723
8873 14:44:34.947163 TX Vref Scan disable
8874 14:44:34.947248 == TX Byte 0 ==
8875 14:44:34.953721 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8876 14:44:34.953807 == TX Byte 1 ==
8877 14:44:34.956867 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8878 14:44:34.960025 DramC Write-DBI off
8879 14:44:34.960110
8880 14:44:34.960194 [DATLAT]
8881 14:44:34.964079 Freq=1600, CH1 RK1
8882 14:44:34.964515
8883 14:44:34.964948 DATLAT Default: 0xf
8884 14:44:34.967380 0, 0xFFFF, sum = 0
8885 14:44:34.970672 1, 0xFFFF, sum = 0
8886 14:44:34.971226 2, 0xFFFF, sum = 0
8887 14:44:34.973820 3, 0xFFFF, sum = 0
8888 14:44:34.974428 4, 0xFFFF, sum = 0
8889 14:44:34.977386 5, 0xFFFF, sum = 0
8890 14:44:34.977816 6, 0xFFFF, sum = 0
8891 14:44:34.979944 7, 0xFFFF, sum = 0
8892 14:44:34.980387 8, 0xFFFF, sum = 0
8893 14:44:34.983533 9, 0xFFFF, sum = 0
8894 14:44:34.984052 10, 0xFFFF, sum = 0
8895 14:44:34.986734 11, 0xFFFF, sum = 0
8896 14:44:34.987163 12, 0xFFFF, sum = 0
8897 14:44:34.990180 13, 0xFFFF, sum = 0
8898 14:44:34.990607 14, 0x0, sum = 1
8899 14:44:34.993149 15, 0x0, sum = 2
8900 14:44:34.993626 16, 0x0, sum = 3
8901 14:44:34.996779 17, 0x0, sum = 4
8902 14:44:34.997204 best_step = 15
8903 14:44:34.997584
8904 14:44:34.997891 ==
8905 14:44:34.999821 Dram Type= 6, Freq= 0, CH_1, rank 1
8906 14:44:35.006311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8907 14:44:35.006734 ==
8908 14:44:35.007063 RX Vref Scan: 0
8909 14:44:35.007368
8910 14:44:35.009643 RX Vref 0 -> 0, step: 1
8911 14:44:35.010064
8912 14:44:35.013006 RX Delay 11 -> 252, step: 4
8913 14:44:35.016088 iDelay=195, Bit 0, Center 136 (83 ~ 190) 108
8914 14:44:35.019600 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8915 14:44:35.026141 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8916 14:44:35.029364 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8917 14:44:35.032625 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8918 14:44:35.036179 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8919 14:44:35.039873 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8920 14:44:35.045911 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8921 14:44:35.049020 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8922 14:44:35.052883 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8923 14:44:35.056023 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8924 14:44:35.058912 iDelay=195, Bit 11, Center 122 (71 ~ 174) 104
8925 14:44:35.065795 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8926 14:44:35.069445 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8927 14:44:35.072597 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8928 14:44:35.075453 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8929 14:44:35.075877 ==
8930 14:44:35.078842 Dram Type= 6, Freq= 0, CH_1, rank 1
8931 14:44:35.085592 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8932 14:44:35.086040 ==
8933 14:44:35.086418 DQS Delay:
8934 14:44:35.088916 DQS0 = 0, DQS1 = 0
8935 14:44:35.089369 DQM Delay:
8936 14:44:35.091902 DQM0 = 131, DQM1 = 128
8937 14:44:35.092322 DQ Delay:
8938 14:44:35.095340 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =128
8939 14:44:35.098768 DQ4 =128, DQ5 =142, DQ6 =138, DQ7 =128
8940 14:44:35.101766 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =122
8941 14:44:35.105196 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
8942 14:44:35.105665
8943 14:44:35.105995
8944 14:44:35.106472
8945 14:44:35.108320 [DramC_TX_OE_Calibration] TA2
8946 14:44:35.111905 Original DQ_B0 (3 6) =30, OEN = 27
8947 14:44:35.115561 Original DQ_B1 (3 6) =30, OEN = 27
8948 14:44:35.118440 24, 0x0, End_B0=24 End_B1=24
8949 14:44:35.121982 25, 0x0, End_B0=25 End_B1=25
8950 14:44:35.122525 26, 0x0, End_B0=26 End_B1=26
8951 14:44:35.125434 27, 0x0, End_B0=27 End_B1=27
8952 14:44:35.128723 28, 0x0, End_B0=28 End_B1=28
8953 14:44:35.132348 29, 0x0, End_B0=29 End_B1=29
8954 14:44:35.134842 30, 0x0, End_B0=30 End_B1=30
8955 14:44:35.135271 31, 0x4141, End_B0=30 End_B1=30
8956 14:44:35.138488 Byte0 end_step=30 best_step=27
8957 14:44:35.141513 Byte1 end_step=30 best_step=27
8958 14:44:35.145492 Byte0 TX OE(2T, 0.5T) = (3, 3)
8959 14:44:35.148362 Byte1 TX OE(2T, 0.5T) = (3, 3)
8960 14:44:35.148893
8961 14:44:35.149223
8962 14:44:35.154732 [DQSOSCAuto] RK1, (LSB)MR18= 0x101e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
8963 14:44:35.157959 CH1 RK1: MR19=303, MR18=101E
8964 14:44:35.164684 CH1_RK1: MR19=0x303, MR18=0x101E, DQSOSC=394, MR23=63, INC=23, DEC=15
8965 14:44:35.168423 [RxdqsGatingPostProcess] freq 1600
8966 14:44:35.174843 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8967 14:44:35.177465 best DQS0 dly(2T, 0.5T) = (1, 1)
8968 14:44:35.177925 best DQS1 dly(2T, 0.5T) = (1, 1)
8969 14:44:35.181395 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8970 14:44:35.184496 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8971 14:44:35.187377 best DQS0 dly(2T, 0.5T) = (1, 1)
8972 14:44:35.191526 best DQS1 dly(2T, 0.5T) = (1, 1)
8973 14:44:35.194628 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8974 14:44:35.197824 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8975 14:44:35.201229 Pre-setting of DQS Precalculation
8976 14:44:35.204389 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8977 14:44:35.214076 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8978 14:44:35.220849 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8979 14:44:35.221305
8980 14:44:35.221654
8981 14:44:35.223775 [Calibration Summary] 3200 Mbps
8982 14:44:35.224188 CH 0, Rank 0
8983 14:44:35.227245 SW Impedance : PASS
8984 14:44:35.230343 DUTY Scan : NO K
8985 14:44:35.230754 ZQ Calibration : PASS
8986 14:44:35.233589 Jitter Meter : NO K
8987 14:44:35.234020 CBT Training : PASS
8988 14:44:35.237238 Write leveling : PASS
8989 14:44:35.240560 RX DQS gating : PASS
8990 14:44:35.241067 RX DQ/DQS(RDDQC) : PASS
8991 14:44:35.244252 TX DQ/DQS : PASS
8992 14:44:35.247725 RX DATLAT : PASS
8993 14:44:35.248246 RX DQ/DQS(Engine): PASS
8994 14:44:35.250282 TX OE : PASS
8995 14:44:35.250710 All Pass.
8996 14:44:35.251042
8997 14:44:35.253921 CH 0, Rank 1
8998 14:44:35.254428 SW Impedance : PASS
8999 14:44:35.257143 DUTY Scan : NO K
9000 14:44:35.260063 ZQ Calibration : PASS
9001 14:44:35.260476 Jitter Meter : NO K
9002 14:44:35.263931 CBT Training : PASS
9003 14:44:35.266596 Write leveling : PASS
9004 14:44:35.267198 RX DQS gating : PASS
9005 14:44:35.269937 RX DQ/DQS(RDDQC) : PASS
9006 14:44:35.273113 TX DQ/DQS : PASS
9007 14:44:35.273629 RX DATLAT : PASS
9008 14:44:35.276338 RX DQ/DQS(Engine): PASS
9009 14:44:35.279988 TX OE : PASS
9010 14:44:35.280400 All Pass.
9011 14:44:35.280722
9012 14:44:35.281150 CH 1, Rank 0
9013 14:44:35.282840 SW Impedance : PASS
9014 14:44:35.286834 DUTY Scan : NO K
9015 14:44:35.287445 ZQ Calibration : PASS
9016 14:44:35.289548 Jitter Meter : NO K
9017 14:44:35.292595 CBT Training : PASS
9018 14:44:35.293049 Write leveling : PASS
9019 14:44:35.296169 RX DQS gating : PASS
9020 14:44:35.299690 RX DQ/DQS(RDDQC) : PASS
9021 14:44:35.300101 TX DQ/DQS : PASS
9022 14:44:35.302803 RX DATLAT : PASS
9023 14:44:35.305886 RX DQ/DQS(Engine): PASS
9024 14:44:35.306311 TX OE : PASS
9025 14:44:35.309197 All Pass.
9026 14:44:35.309671
9027 14:44:35.309997 CH 1, Rank 1
9028 14:44:35.312318 SW Impedance : PASS
9029 14:44:35.312729 DUTY Scan : NO K
9030 14:44:35.316153 ZQ Calibration : PASS
9031 14:44:35.319367 Jitter Meter : NO K
9032 14:44:35.319827 CBT Training : PASS
9033 14:44:35.322751 Write leveling : PASS
9034 14:44:35.323186 RX DQS gating : PASS
9035 14:44:35.325706 RX DQ/DQS(RDDQC) : PASS
9036 14:44:35.329081 TX DQ/DQS : PASS
9037 14:44:35.329590 RX DATLAT : PASS
9038 14:44:35.332353 RX DQ/DQS(Engine): PASS
9039 14:44:35.335861 TX OE : PASS
9040 14:44:35.336536 All Pass.
9041 14:44:35.337003
9042 14:44:35.338797 DramC Write-DBI on
9043 14:44:35.339207 PER_BANK_REFRESH: Hybrid Mode
9044 14:44:35.342476 TX_TRACKING: ON
9045 14:44:35.352212 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9046 14:44:35.358967 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9047 14:44:35.365245 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9048 14:44:35.368623 [FAST_K] Save calibration result to emmc
9049 14:44:35.371925 sync common calibartion params.
9050 14:44:35.375085 sync cbt_mode0:1, 1:1
9051 14:44:35.378781 dram_init: ddr_geometry: 2
9052 14:44:35.379194 dram_init: ddr_geometry: 2
9053 14:44:35.382268 dram_init: ddr_geometry: 2
9054 14:44:35.384896 0:dram_rank_size:100000000
9055 14:44:35.385342 1:dram_rank_size:100000000
9056 14:44:35.392256 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9057 14:44:35.397592 DFS_SHUFFLE_HW_MODE: ON
9058 14:44:35.398349 dramc_set_vcore_voltage set vcore to 725000
9059 14:44:35.401820 Read voltage for 1600, 0
9060 14:44:35.402271 Vio18 = 0
9061 14:44:35.402676 Vcore = 725000
9062 14:44:35.404585 Vdram = 0
9063 14:44:35.405001 Vddq = 0
9064 14:44:35.405385 Vmddr = 0
9065 14:44:35.408857 switch to 3200 Mbps bootup
9066 14:44:35.411597 [DramcRunTimeConfig]
9067 14:44:35.412155 PHYPLL
9068 14:44:35.412624 DPM_CONTROL_AFTERK: ON
9069 14:44:35.414648 PER_BANK_REFRESH: ON
9070 14:44:35.418318 REFRESH_OVERHEAD_REDUCTION: ON
9071 14:44:35.418636 CMD_PICG_NEW_MODE: OFF
9072 14:44:35.421358 XRTWTW_NEW_MODE: ON
9073 14:44:35.421656 XRTRTR_NEW_MODE: ON
9074 14:44:35.424893 TX_TRACKING: ON
9075 14:44:35.425191 RDSEL_TRACKING: OFF
9076 14:44:35.427870 DQS Precalculation for DVFS: ON
9077 14:44:35.431206 RX_TRACKING: OFF
9078 14:44:35.431529 HW_GATING DBG: ON
9079 14:44:35.434553 ZQCS_ENABLE_LP4: ON
9080 14:44:35.434849 RX_PICG_NEW_MODE: ON
9081 14:44:35.437648 TX_PICG_NEW_MODE: ON
9082 14:44:35.440792 ENABLE_RX_DCM_DPHY: ON
9083 14:44:35.444401 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9084 14:44:35.444707 DUMMY_READ_FOR_TRACKING: OFF
9085 14:44:35.447415 !!! SPM_CONTROL_AFTERK: OFF
9086 14:44:35.451589 !!! SPM could not control APHY
9087 14:44:35.453922 IMPEDANCE_TRACKING: ON
9088 14:44:35.454213 TEMP_SENSOR: ON
9089 14:44:35.457353 HW_SAVE_FOR_SR: OFF
9090 14:44:35.457648 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9091 14:44:35.464743 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9092 14:44:35.465222 Read ODT Tracking: ON
9093 14:44:35.467632 Refresh Rate DeBounce: ON
9094 14:44:35.470686 DFS_NO_QUEUE_FLUSH: ON
9095 14:44:35.471099 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9096 14:44:35.474389 ENABLE_DFS_RUNTIME_MRW: OFF
9097 14:44:35.477596 DDR_RESERVE_NEW_MODE: ON
9098 14:44:35.480619 MR_CBT_SWITCH_FREQ: ON
9099 14:44:35.481030 =========================
9100 14:44:35.500531 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9101 14:44:35.503840 dram_init: ddr_geometry: 2
9102 14:44:35.522050 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9103 14:44:35.525515 dram_init: dram init end (result: 0)
9104 14:44:35.531992 DRAM-K: Full calibration passed in 24379 msecs
9105 14:44:35.535359 MRC: failed to locate region type 0.
9106 14:44:35.535875 DRAM rank0 size:0x100000000,
9107 14:44:35.538246 DRAM rank1 size=0x100000000
9108 14:44:35.548638 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9109 14:44:35.554683 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9110 14:44:35.564821 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9111 14:44:35.571384 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9112 14:44:35.571799 DRAM rank0 size:0x100000000,
9113 14:44:35.574827 DRAM rank1 size=0x100000000
9114 14:44:35.575359 CBMEM:
9115 14:44:35.577936 IMD: root @ 0xfffff000 254 entries.
9116 14:44:35.581089 IMD: root @ 0xffffec00 62 entries.
9117 14:44:35.584459 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9118 14:44:35.590834 WARNING: RO_VPD is uninitialized or empty.
9119 14:44:35.594164 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9120 14:44:35.601961 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9121 14:44:35.614823 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9122 14:44:35.626078 BS: romstage times (exec / console): total (unknown) / 23913 ms
9123 14:44:35.626588
9124 14:44:35.626916
9125 14:44:35.637361 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9126 14:44:35.639078 ARM64: Exception handlers installed.
9127 14:44:35.642527 ARM64: Testing exception
9128 14:44:35.646470 ARM64: Done test exception
9129 14:44:35.646994 Enumerating buses...
9130 14:44:35.649087 Show all devs... Before device enumeration.
9131 14:44:35.652832 Root Device: enabled 1
9132 14:44:35.656095 CPU_CLUSTER: 0: enabled 1
9133 14:44:35.656609 CPU: 00: enabled 1
9134 14:44:35.659140 Compare with tree...
9135 14:44:35.659560 Root Device: enabled 1
9136 14:44:35.662063 CPU_CLUSTER: 0: enabled 1
9137 14:44:35.666005 CPU: 00: enabled 1
9138 14:44:35.666523 Root Device scanning...
9139 14:44:35.668849 scan_static_bus for Root Device
9140 14:44:35.672387 CPU_CLUSTER: 0 enabled
9141 14:44:35.675866 scan_static_bus for Root Device done
9142 14:44:35.679339 scan_bus: bus Root Device finished in 8 msecs
9143 14:44:35.679867 done
9144 14:44:35.685959 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9145 14:44:35.688737 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9146 14:44:35.695706 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9147 14:44:35.701874 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9148 14:44:35.702406 Allocating resources...
9149 14:44:35.705197 Reading resources...
9150 14:44:35.708833 Root Device read_resources bus 0 link: 0
9151 14:44:35.712051 DRAM rank0 size:0x100000000,
9152 14:44:35.712582 DRAM rank1 size=0x100000000
9153 14:44:35.718566 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9154 14:44:35.719033 CPU: 00 missing read_resources
9155 14:44:35.724891 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9156 14:44:35.728597 Root Device read_resources bus 0 link: 0 done
9157 14:44:35.731576 Done reading resources.
9158 14:44:35.734900 Show resources in subtree (Root Device)...After reading.
9159 14:44:35.738078 Root Device child on link 0 CPU_CLUSTER: 0
9160 14:44:35.741370 CPU_CLUSTER: 0 child on link 0 CPU: 00
9161 14:44:35.751111 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9162 14:44:35.751662 CPU: 00
9163 14:44:35.757643 Root Device assign_resources, bus 0 link: 0
9164 14:44:35.761468 CPU_CLUSTER: 0 missing set_resources
9165 14:44:35.764885 Root Device assign_resources, bus 0 link: 0 done
9166 14:44:35.767942 Done setting resources.
9167 14:44:35.770775 Show resources in subtree (Root Device)...After assigning values.
9168 14:44:35.774443 Root Device child on link 0 CPU_CLUSTER: 0
9169 14:44:35.781400 CPU_CLUSTER: 0 child on link 0 CPU: 00
9170 14:44:35.787613 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9171 14:44:35.791595 CPU: 00
9172 14:44:35.792147 Done allocating resources.
9173 14:44:35.798029 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9174 14:44:35.798462 Enabling resources...
9175 14:44:35.800806 done.
9176 14:44:35.804344 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9177 14:44:35.807595 Initializing devices...
9178 14:44:35.808114 Root Device init
9179 14:44:35.810424 init hardware done!
9180 14:44:35.810836 0x00000018: ctrlr->caps
9181 14:44:35.813771 52.000 MHz: ctrlr->f_max
9182 14:44:35.817346 0.400 MHz: ctrlr->f_min
9183 14:44:35.820386 0x40ff8080: ctrlr->voltages
9184 14:44:35.820805 sclk: 390625
9185 14:44:35.821128 Bus Width = 1
9186 14:44:35.823973 sclk: 390625
9187 14:44:35.824507 Bus Width = 1
9188 14:44:35.826859 Early init status = 3
9189 14:44:35.829940 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9190 14:44:35.833680 in-header: 03 fc 00 00 01 00 00 00
9191 14:44:35.836880 in-data: 00
9192 14:44:35.840479 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9193 14:44:35.845396 in-header: 03 fd 00 00 00 00 00 00
9194 14:44:35.848540 in-data:
9195 14:44:35.851991 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9196 14:44:35.856022 in-header: 03 fc 00 00 01 00 00 00
9197 14:44:35.859071 in-data: 00
9198 14:44:35.862348 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9199 14:44:35.868493 in-header: 03 fd 00 00 00 00 00 00
9200 14:44:35.871490 in-data:
9201 14:44:35.874607 [SSUSB] Setting up USB HOST controller...
9202 14:44:35.878229 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9203 14:44:35.881582 [SSUSB] phy power-on done.
9204 14:44:35.884865 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9205 14:44:35.891995 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9206 14:44:35.894716 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9207 14:44:35.901901 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9208 14:44:35.908377 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9209 14:44:35.914272 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9210 14:44:35.921215 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9211 14:44:35.927510 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9212 14:44:35.931371 SPM: binary array size = 0x9dc
9213 14:44:35.934308 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9214 14:44:35.941023 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9215 14:44:35.947511 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9216 14:44:35.954426 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9217 14:44:35.957035 configure_display: Starting display init
9218 14:44:35.991477 anx7625_power_on_init: Init interface.
9219 14:44:35.994762 anx7625_disable_pd_protocol: Disabled PD feature.
9220 14:44:35.998307 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9221 14:44:36.026489 anx7625_start_dp_work: Secure OCM version=00
9222 14:44:36.029235 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9223 14:44:36.043946 sp_tx_get_edid_block: EDID Block = 1
9224 14:44:36.146506 Extracted contents:
9225 14:44:36.150137 header: 00 ff ff ff ff ff ff 00
9226 14:44:36.153430 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9227 14:44:36.156362 version: 01 04
9228 14:44:36.159960 basic params: 95 1f 11 78 0a
9229 14:44:36.163454 chroma info: 76 90 94 55 54 90 27 21 50 54
9230 14:44:36.166305 established: 00 00 00
9231 14:44:36.172799 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9232 14:44:36.179899 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9233 14:44:36.183255 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9234 14:44:36.189402 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9235 14:44:36.195949 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9236 14:44:36.199119 extensions: 00
9237 14:44:36.199534 checksum: fb
9238 14:44:36.199860
9239 14:44:36.202823 Manufacturer: IVO Model 57d Serial Number 0
9240 14:44:36.205514 Made week 0 of 2020
9241 14:44:36.209725 EDID version: 1.4
9242 14:44:36.210145 Digital display
9243 14:44:36.212545 6 bits per primary color channel
9244 14:44:36.212971 DisplayPort interface
9245 14:44:36.215776 Maximum image size: 31 cm x 17 cm
9246 14:44:36.218978 Gamma: 220%
9247 14:44:36.219445 Check DPMS levels
9248 14:44:36.225524 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9249 14:44:36.228731 First detailed timing is preferred timing
9250 14:44:36.229153 Established timings supported:
9251 14:44:36.232316 Standard timings supported:
9252 14:44:36.235530 Detailed timings
9253 14:44:36.238908 Hex of detail: 383680a07038204018303c0035ae10000019
9254 14:44:36.245574 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9255 14:44:36.248602 0780 0798 07c8 0820 hborder 0
9256 14:44:36.251962 0438 043b 0447 0458 vborder 0
9257 14:44:36.255433 -hsync -vsync
9258 14:44:36.255980 Did detailed timing
9259 14:44:36.261977 Hex of detail: 000000000000000000000000000000000000
9260 14:44:36.265487 Manufacturer-specified data, tag 0
9261 14:44:36.268392 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9262 14:44:36.271326 ASCII string: InfoVision
9263 14:44:36.275298 Hex of detail: 000000fe00523134304e574635205248200a
9264 14:44:36.278348 ASCII string: R140NWF5 RH
9265 14:44:36.278906 Checksum
9266 14:44:36.281209 Checksum: 0xfb (valid)
9267 14:44:36.285217 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9268 14:44:36.288212 DSI data_rate: 832800000 bps
9269 14:44:36.294918 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9270 14:44:36.298015 anx7625_parse_edid: pixelclock(138800).
9271 14:44:36.301491 hactive(1920), hsync(48), hfp(24), hbp(88)
9272 14:44:36.304809 vactive(1080), vsync(12), vfp(3), vbp(17)
9273 14:44:36.307887 anx7625_dsi_config: config dsi.
9274 14:44:36.314305 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9275 14:44:36.329002 anx7625_dsi_config: success to config DSI
9276 14:44:36.331818 anx7625_dp_start: MIPI phy setup OK.
9277 14:44:36.335254 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9278 14:44:36.338500 mtk_ddp_mode_set invalid vrefresh 60
9279 14:44:36.341980 main_disp_path_setup
9280 14:44:36.342579 ovl_layer_smi_id_en
9281 14:44:36.345010 ovl_layer_smi_id_en
9282 14:44:36.345462 ccorr_config
9283 14:44:36.345800 aal_config
9284 14:44:36.348011 gamma_config
9285 14:44:36.348428 postmask_config
9286 14:44:36.351467 dither_config
9287 14:44:36.355527 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9288 14:44:36.361967 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9289 14:44:36.365016 Root Device init finished in 553 msecs
9290 14:44:36.367821 CPU_CLUSTER: 0 init
9291 14:44:36.374689 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9292 14:44:36.381229 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9293 14:44:36.381783 APU_MBOX 0x190000b0 = 0x10001
9294 14:44:36.384461 APU_MBOX 0x190001b0 = 0x10001
9295 14:44:36.387951 APU_MBOX 0x190005b0 = 0x10001
9296 14:44:36.390996 APU_MBOX 0x190006b0 = 0x10001
9297 14:44:36.397475 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9298 14:44:36.407549 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9299 14:44:36.419816 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9300 14:44:36.426772 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9301 14:44:36.437882 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9302 14:44:36.447557 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9303 14:44:36.450321 CPU_CLUSTER: 0 init finished in 81 msecs
9304 14:44:36.454200 Devices initialized
9305 14:44:36.457215 Show all devs... After init.
9306 14:44:36.457676 Root Device: enabled 1
9307 14:44:36.460544 CPU_CLUSTER: 0: enabled 1
9308 14:44:36.464592 CPU: 00: enabled 1
9309 14:44:36.466942 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9310 14:44:36.470197 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9311 14:44:36.473794 ELOG: NV offset 0x57f000 size 0x1000
9312 14:44:36.480028 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9313 14:44:36.486740 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9314 14:44:36.490297 ELOG: Event(17) added with size 13 at 2024-06-04 14:44:36 UTC
9315 14:44:36.496537 out: cmd=0x121: 03 db 21 01 00 00 00 00
9316 14:44:36.500406 in-header: 03 d5 00 00 2c 00 00 00
9317 14:44:36.510468 in-data: 69 71 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9318 14:44:36.516626 ELOG: Event(A1) added with size 10 at 2024-06-04 14:44:36 UTC
9319 14:44:36.523209 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9320 14:44:36.529845 ELOG: Event(A0) added with size 9 at 2024-06-04 14:44:36 UTC
9321 14:44:36.533092 elog_add_boot_reason: Logged dev mode boot
9322 14:44:36.539691 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9323 14:44:36.540319 Finalize devices...
9324 14:44:36.543250 Devices finalized
9325 14:44:36.545962 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9326 14:44:36.549419 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9327 14:44:36.553123 in-header: 03 07 00 00 08 00 00 00
9328 14:44:36.556332 in-data: aa e4 47 04 13 02 00 00
9329 14:44:36.559728 Chrome EC: UHEPI supported
9330 14:44:36.566274 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9331 14:44:36.569960 in-header: 03 a9 00 00 08 00 00 00
9332 14:44:36.572490 in-data: 84 60 60 08 00 00 00 00
9333 14:44:36.579256 ELOG: Event(91) added with size 10 at 2024-06-04 14:44:36 UTC
9334 14:44:36.583242 Chrome EC: clear events_b mask to 0x0000000020004000
9335 14:44:36.589592 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9336 14:44:36.593522 in-header: 03 fd 00 00 00 00 00 00
9337 14:44:36.596654 in-data:
9338 14:44:36.599947 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9339 14:44:36.603185 Writing coreboot table at 0xffe64000
9340 14:44:36.610386 0. 000000000010a000-0000000000113fff: RAMSTAGE
9341 14:44:36.613339 1. 0000000040000000-00000000400fffff: RAM
9342 14:44:36.616794 2. 0000000040100000-000000004032afff: RAMSTAGE
9343 14:44:36.619903 3. 000000004032b000-00000000545fffff: RAM
9344 14:44:36.623181 4. 0000000054600000-000000005465ffff: BL31
9345 14:44:36.626715 5. 0000000054660000-00000000ffe63fff: RAM
9346 14:44:36.632771 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9347 14:44:36.636525 7. 0000000100000000-000000023fffffff: RAM
9348 14:44:36.639565 Passing 5 GPIOs to payload:
9349 14:44:36.643502 NAME | PORT | POLARITY | VALUE
9350 14:44:36.649673 EC in RW | 0x000000aa | low | undefined
9351 14:44:36.652941 EC interrupt | 0x00000005 | low | undefined
9352 14:44:36.659582 TPM interrupt | 0x000000ab | high | undefined
9353 14:44:36.662748 SD card detect | 0x00000011 | high | undefined
9354 14:44:36.666512 speaker enable | 0x00000093 | high | undefined
9355 14:44:36.672337 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9356 14:44:36.676143 in-header: 03 f9 00 00 02 00 00 00
9357 14:44:36.676713 in-data: 02 00
9358 14:44:36.679117 ADC[4]: Raw value=902955 ID=7
9359 14:44:36.682589 ADC[3]: Raw value=213546 ID=1
9360 14:44:36.683013 RAM Code: 0x71
9361 14:44:36.686150 ADC[6]: Raw value=75000 ID=0
9362 14:44:36.688985 ADC[5]: Raw value=213546 ID=1
9363 14:44:36.689447 SKU Code: 0x1
9364 14:44:36.695851 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a2f1
9365 14:44:36.698948 coreboot table: 964 bytes.
9366 14:44:36.702568 IMD ROOT 0. 0xfffff000 0x00001000
9367 14:44:36.703182 IMD SMALL 1. 0xffffe000 0x00001000
9368 14:44:36.706076 RO MCACHE 2. 0xffffc000 0x00001104
9369 14:44:36.708863 CONSOLE 3. 0xfff7c000 0x00080000
9370 14:44:36.712303 FMAP 4. 0xfff7b000 0x00000452
9371 14:44:36.715760 TIME STAMP 5. 0xfff7a000 0x00000910
9372 14:44:36.718896 VBOOT WORK 6. 0xfff66000 0x00014000
9373 14:44:36.722157 RAMOOPS 7. 0xffe66000 0x00100000
9374 14:44:36.725383 COREBOOT 8. 0xffe64000 0x00002000
9375 14:44:36.728761 IMD small region:
9376 14:44:36.732030 IMD ROOT 0. 0xffffec00 0x00000400
9377 14:44:36.735148 VPD 1. 0xffffeb80 0x0000006c
9378 14:44:36.738682 MMC STATUS 2. 0xffffeb60 0x00000004
9379 14:44:36.745450 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9380 14:44:36.751765 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9381 14:44:36.790685 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9382 14:44:36.793950 Checking segment from ROM address 0x40100000
9383 14:44:36.801015 Checking segment from ROM address 0x4010001c
9384 14:44:36.803477 Loading segment from ROM address 0x40100000
9385 14:44:36.803974 code (compression=0)
9386 14:44:36.813576 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9387 14:44:36.820434 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9388 14:44:36.820937 it's not compressed!
9389 14:44:36.826647 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9390 14:44:36.833502 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9391 14:44:36.851168 Loading segment from ROM address 0x4010001c
9392 14:44:36.851681 Entry Point 0x80000000
9393 14:44:36.854079 Loaded segments
9394 14:44:36.857612 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9395 14:44:36.864550 Jumping to boot code at 0x80000000(0xffe64000)
9396 14:44:36.871147 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9397 14:44:36.877955 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9398 14:44:36.885721 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9399 14:44:36.888389 Checking segment from ROM address 0x40100000
9400 14:44:36.892192 Checking segment from ROM address 0x4010001c
9401 14:44:36.898445 Loading segment from ROM address 0x40100000
9402 14:44:36.898872 code (compression=1)
9403 14:44:36.905347 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9404 14:44:36.915110 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9405 14:44:36.915626 using LZMA
9406 14:44:36.924195 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9407 14:44:36.930358 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9408 14:44:36.933706 Loading segment from ROM address 0x4010001c
9409 14:44:36.934125 Entry Point 0x54601000
9410 14:44:36.937305 Loaded segments
9411 14:44:36.940128 NOTICE: MT8192 bl31_setup
9412 14:44:36.947459 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9413 14:44:36.950448 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9414 14:44:36.953984 WARNING: region 0:
9415 14:44:36.957006 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9416 14:44:36.957469 WARNING: region 1:
9417 14:44:36.963930 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9418 14:44:36.967463 WARNING: region 2:
9419 14:44:36.970316 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9420 14:44:36.973754 WARNING: region 3:
9421 14:44:36.980327 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9422 14:44:36.980750 WARNING: region 4:
9423 14:44:36.986894 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9424 14:44:36.987407 WARNING: region 5:
9425 14:44:36.989893 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9426 14:44:36.993357 WARNING: region 6:
9427 14:44:36.996932 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9428 14:44:36.999879 WARNING: region 7:
9429 14:44:37.003822 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9430 14:44:37.010097 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9431 14:44:37.013363 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9432 14:44:37.019620 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9433 14:44:37.023242 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9434 14:44:37.026569 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9435 14:44:37.033372 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9436 14:44:37.036260 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9437 14:44:37.043860 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9438 14:44:37.046543 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9439 14:44:37.049183 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9440 14:44:37.056196 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9441 14:44:37.059508 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9442 14:44:37.063002 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9443 14:44:37.069218 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9444 14:44:37.072596 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9445 14:44:37.079062 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9446 14:44:37.082454 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9447 14:44:37.085947 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9448 14:44:37.091800 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9449 14:44:37.095659 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9450 14:44:37.102104 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9451 14:44:37.105437 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9452 14:44:37.108627 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9453 14:44:37.115577 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9454 14:44:37.118492 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9455 14:44:37.125061 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9456 14:44:37.128536 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9457 14:44:37.131546 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9458 14:44:37.138152 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9459 14:44:37.141238 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9460 14:44:37.148010 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9461 14:44:37.151363 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9462 14:44:37.154979 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9463 14:44:37.161103 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9464 14:44:37.164805 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9465 14:44:37.167751 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9466 14:44:37.170948 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9467 14:44:37.177579 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9468 14:44:37.180997 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9469 14:44:37.184375 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9470 14:44:37.190342 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9471 14:44:37.193749 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9472 14:44:37.196787 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9473 14:44:37.200661 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9474 14:44:37.207655 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9475 14:44:37.210137 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9476 14:44:37.213697 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9477 14:44:37.216758 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9478 14:44:37.223737 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9479 14:44:37.226976 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9480 14:44:37.233446 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9481 14:44:37.237067 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9482 14:44:37.243571 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9483 14:44:37.246401 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9484 14:44:37.253076 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9485 14:44:37.256366 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9486 14:44:37.260358 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9487 14:44:37.266531 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9488 14:44:37.269649 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9489 14:44:37.276468 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9490 14:44:37.279612 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9491 14:44:37.286140 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9492 14:44:37.289353 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9493 14:44:37.295649 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9494 14:44:37.298952 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9495 14:44:37.305935 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9496 14:44:37.309338 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9497 14:44:37.312834 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9498 14:44:37.318671 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9499 14:44:37.322487 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9500 14:44:37.329218 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9501 14:44:37.332022 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9502 14:44:37.339202 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9503 14:44:37.342600 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9504 14:44:37.349233 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9505 14:44:37.351911 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9506 14:44:37.355182 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9507 14:44:37.362706 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9508 14:44:37.365084 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9509 14:44:37.371545 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9510 14:44:37.375141 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9511 14:44:37.381633 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9512 14:44:37.384569 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9513 14:44:37.391675 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9514 14:44:37.394527 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9515 14:44:37.398387 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9516 14:44:37.404799 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9517 14:44:37.408180 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9518 14:44:37.414683 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9519 14:44:37.417502 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9520 14:44:37.424937 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9521 14:44:37.427701 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9522 14:44:37.434062 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9523 14:44:37.437758 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9524 14:44:37.444405 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9525 14:44:37.447736 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9526 14:44:37.450630 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9527 14:44:37.457349 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9528 14:44:37.460640 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9529 14:44:37.463738 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9530 14:44:37.467410 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9531 14:44:37.473936 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9532 14:44:37.477417 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9533 14:44:37.484187 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9534 14:44:37.487193 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9535 14:44:37.490694 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9536 14:44:37.496671 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9537 14:44:37.500120 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9538 14:44:37.506286 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9539 14:44:37.509711 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9540 14:44:37.512983 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9541 14:44:37.519755 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9542 14:44:37.523064 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9543 14:44:37.529896 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9544 14:44:37.532904 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9545 14:44:37.536137 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9546 14:44:37.543102 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9547 14:44:37.546502 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9548 14:44:37.549445 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9549 14:44:37.556355 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9550 14:44:37.558982 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9551 14:44:37.563066 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9552 14:44:37.565917 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9553 14:44:37.573048 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9554 14:44:37.575595 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9555 14:44:37.582894 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9556 14:44:37.585585 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9557 14:44:37.589206 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9558 14:44:37.595255 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9559 14:44:37.598624 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9560 14:44:37.605405 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9561 14:44:37.608901 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9562 14:44:37.612147 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9563 14:44:37.618485 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9564 14:44:37.621778 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9565 14:44:37.628182 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9566 14:44:37.631473 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9567 14:44:37.634579 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9568 14:44:37.641573 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9569 14:44:37.644946 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9570 14:44:37.651008 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9571 14:44:37.654446 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9572 14:44:37.657726 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9573 14:44:37.664388 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9574 14:44:37.667835 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9575 14:44:37.674750 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9576 14:44:37.677633 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9577 14:44:37.681414 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9578 14:44:37.687373 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9579 14:44:37.690982 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9580 14:44:37.697728 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9581 14:44:37.700797 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9582 14:44:37.703929 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9583 14:44:37.710259 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9584 14:44:37.713467 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9585 14:44:37.720439 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9586 14:44:37.723775 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9587 14:44:37.730243 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9588 14:44:37.733374 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9589 14:44:37.736573 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9590 14:44:37.743408 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9591 14:44:37.747566 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9592 14:44:37.749898 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9593 14:44:37.756797 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9594 14:44:37.759895 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9595 14:44:37.766475 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9596 14:44:37.769872 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9597 14:44:37.776098 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9598 14:44:37.779462 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9599 14:44:37.783069 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9600 14:44:37.789333 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9601 14:44:37.792963 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9602 14:44:37.799840 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9603 14:44:37.802951 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9604 14:44:37.806229 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9605 14:44:37.812764 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9606 14:44:37.816468 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9607 14:44:37.822633 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9608 14:44:37.825565 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9609 14:44:37.828853 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9610 14:44:37.835574 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9611 14:44:37.839213 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9612 14:44:37.845346 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9613 14:44:37.849193 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9614 14:44:37.852134 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9615 14:44:37.858836 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9616 14:44:37.862213 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9617 14:44:37.868604 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9618 14:44:37.872134 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9619 14:44:37.875176 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9620 14:44:37.881830 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9621 14:44:37.885542 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9622 14:44:37.891465 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9623 14:44:37.894649 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9624 14:44:37.901642 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9625 14:44:37.904808 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9626 14:44:37.908276 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9627 14:44:37.914689 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9628 14:44:37.917945 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9629 14:44:37.924558 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9630 14:44:37.928862 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9631 14:44:37.931661 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9632 14:44:37.938500 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9633 14:44:37.941970 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9634 14:44:37.948111 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9635 14:44:37.951752 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9636 14:44:37.958280 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9637 14:44:37.960831 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9638 14:44:37.967367 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9639 14:44:37.970555 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9640 14:44:37.974021 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9641 14:44:37.980681 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9642 14:44:37.984123 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9643 14:44:37.990567 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9644 14:44:37.994232 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9645 14:44:38.000320 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9646 14:44:38.003523 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9647 14:44:38.007146 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9648 14:44:38.013766 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9649 14:44:38.016795 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9650 14:44:38.023658 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9651 14:44:38.026547 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9652 14:44:38.029915 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9653 14:44:38.036905 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9654 14:44:38.040498 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9655 14:44:38.046796 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9656 14:44:38.049800 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9657 14:44:38.056480 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9658 14:44:38.059726 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9659 14:44:38.063145 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9660 14:44:38.066564 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9661 14:44:38.073233 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9662 14:44:38.076680 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9663 14:44:38.079766 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9664 14:44:38.086223 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9665 14:44:38.089115 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9666 14:44:38.093072 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9667 14:44:38.099526 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9668 14:44:38.102904 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9669 14:44:38.106022 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9670 14:44:38.113049 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9671 14:44:38.115483 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9672 14:44:38.122402 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9673 14:44:38.125570 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9674 14:44:38.128990 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9675 14:44:38.135724 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9676 14:44:38.138752 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9677 14:44:38.145437 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9678 14:44:38.148924 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9679 14:44:38.152436 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9680 14:44:38.158468 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9681 14:44:38.161878 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9682 14:44:38.165039 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9683 14:44:38.171834 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9684 14:44:38.175008 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9685 14:44:38.182040 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9686 14:44:38.184716 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9687 14:44:38.188360 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9688 14:44:38.194775 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9689 14:44:38.198012 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9690 14:44:38.201305 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9691 14:44:38.208020 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9692 14:44:38.211494 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9693 14:44:38.214329 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9694 14:44:38.221061 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9695 14:44:38.224161 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9696 14:44:38.231135 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9697 14:44:38.234033 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9698 14:44:38.238071 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9699 14:44:38.244001 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9700 14:44:38.247615 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9701 14:44:38.250697 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9702 14:44:38.253894 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9703 14:44:38.257344 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9704 14:44:38.264120 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9705 14:44:38.267328 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9706 14:44:38.270486 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9707 14:44:38.277203 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9708 14:44:38.280201 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9709 14:44:38.283806 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9710 14:44:38.287374 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9711 14:44:38.293537 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9712 14:44:38.296765 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9713 14:44:38.303322 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9714 14:44:38.306882 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9715 14:44:38.309875 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9716 14:44:38.316862 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9717 14:44:38.319887 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9718 14:44:38.326845 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9719 14:44:38.329731 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9720 14:44:38.333423 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9721 14:44:38.339752 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9722 14:44:38.343449 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9723 14:44:38.349524 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9724 14:44:38.352891 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9725 14:44:38.360053 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9726 14:44:38.363211 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9727 14:44:38.366229 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9728 14:44:38.372727 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9729 14:44:38.376591 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9730 14:44:38.382789 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9731 14:44:38.385869 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9732 14:44:38.392566 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9733 14:44:38.395921 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9734 14:44:38.398778 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9735 14:44:38.405952 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9736 14:44:38.408866 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9737 14:44:38.415307 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9738 14:44:38.418444 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9739 14:44:38.425351 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9740 14:44:38.428777 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9741 14:44:38.431583 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9742 14:44:38.438357 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9743 14:44:38.441193 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9744 14:44:38.448132 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9745 14:44:38.451706 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9746 14:44:38.454593 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9747 14:44:38.461161 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9748 14:44:38.464938 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9749 14:44:38.471263 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9750 14:44:38.474686 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9751 14:44:38.478095 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9752 14:44:38.484618 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9753 14:44:38.488151 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9754 14:44:38.494123 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9755 14:44:38.497413 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9756 14:44:38.504596 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9757 14:44:38.508057 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9758 14:44:38.514144 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9759 14:44:38.517424 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9760 14:44:38.520646 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9761 14:44:38.527669 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9762 14:44:38.531182 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9763 14:44:38.537658 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9764 14:44:38.540778 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9765 14:44:38.544552 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9766 14:44:38.550923 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9767 14:44:38.553921 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9768 14:44:38.560613 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9769 14:44:38.563913 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9770 14:44:38.567152 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9771 14:44:38.573737 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9772 14:44:38.576779 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9773 14:44:38.584019 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9774 14:44:38.586780 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9775 14:44:38.590315 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9776 14:44:38.596742 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9777 14:44:38.600104 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9778 14:44:38.606477 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9779 14:44:38.609997 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9780 14:44:38.616436 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9781 14:44:38.619637 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9782 14:44:38.626257 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9783 14:44:38.629466 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9784 14:44:38.632995 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9785 14:44:38.639604 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9786 14:44:38.642601 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9787 14:44:38.649601 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9788 14:44:38.652399 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9789 14:44:38.659525 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9790 14:44:38.662602 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9791 14:44:38.665717 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9792 14:44:38.672871 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9793 14:44:38.675990 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9794 14:44:38.682484 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9795 14:44:38.685821 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9796 14:44:38.692022 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9797 14:44:38.695348 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9798 14:44:38.702130 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9799 14:44:38.705365 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9800 14:44:38.711912 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9801 14:44:38.715318 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9802 14:44:38.718656 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9803 14:44:38.725108 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9804 14:44:38.728467 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9805 14:44:38.735029 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9806 14:44:38.738069 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9807 14:44:38.745018 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9808 14:44:38.748198 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9809 14:44:38.754738 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9810 14:44:38.758273 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9811 14:44:38.761132 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9812 14:44:38.767663 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9813 14:44:38.771341 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9814 14:44:38.777942 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9815 14:44:38.781461 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9816 14:44:38.787754 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9817 14:44:38.791074 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9818 14:44:38.797790 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9819 14:44:38.801368 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9820 14:44:38.803941 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9821 14:44:38.811842 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9822 14:44:38.814207 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9823 14:44:38.820518 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9824 14:44:38.823897 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9825 14:44:38.830521 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9826 14:44:38.833667 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9827 14:44:38.840469 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9828 14:44:38.843602 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9829 14:44:38.850307 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9830 14:44:38.853488 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9831 14:44:38.856588 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9832 14:44:38.864006 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9833 14:44:38.866968 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9834 14:44:38.873501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9835 14:44:38.876303 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9836 14:44:38.883003 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9837 14:44:38.886411 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9838 14:44:38.892876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9839 14:44:38.896874 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9840 14:44:38.899814 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9841 14:44:38.906156 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9842 14:44:38.909533 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9843 14:44:38.916025 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9844 14:44:38.919943 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9845 14:44:38.926345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9846 14:44:38.929450 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9847 14:44:38.935982 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9848 14:44:38.938919 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9849 14:44:38.946001 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9850 14:44:38.948793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9851 14:44:38.955545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9852 14:44:38.958671 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9853 14:44:38.965373 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9854 14:44:38.969070 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9855 14:44:38.975383 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9856 14:44:38.982044 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9857 14:44:38.984975 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9858 14:44:38.992036 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9859 14:44:38.995041 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9860 14:44:39.001508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9861 14:44:39.005087 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9862 14:44:39.011626 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9863 14:44:39.014845 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9864 14:44:39.018199 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9865 14:44:39.021559 INFO: [APUAPC] vio 0
9866 14:44:39.028323 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9867 14:44:39.031263 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9868 14:44:39.034619 INFO: [APUAPC] D0_APC_0: 0x400510
9869 14:44:39.038203 INFO: [APUAPC] D0_APC_1: 0x0
9870 14:44:39.041624 INFO: [APUAPC] D0_APC_2: 0x1540
9871 14:44:39.044304 INFO: [APUAPC] D0_APC_3: 0x0
9872 14:44:39.047522 INFO: [APUAPC] D1_APC_0: 0xffffffff
9873 14:44:39.050846 INFO: [APUAPC] D1_APC_1: 0xffffffff
9874 14:44:39.054259 INFO: [APUAPC] D1_APC_2: 0x3fffff
9875 14:44:39.057585 INFO: [APUAPC] D1_APC_3: 0x0
9876 14:44:39.061142 INFO: [APUAPC] D2_APC_0: 0xffffffff
9877 14:44:39.064119 INFO: [APUAPC] D2_APC_1: 0xffffffff
9878 14:44:39.067440 INFO: [APUAPC] D2_APC_2: 0x3fffff
9879 14:44:39.071074 INFO: [APUAPC] D2_APC_3: 0x0
9880 14:44:39.074380 INFO: [APUAPC] D3_APC_0: 0xffffffff
9881 14:44:39.077524 INFO: [APUAPC] D3_APC_1: 0xffffffff
9882 14:44:39.080649 INFO: [APUAPC] D3_APC_2: 0x3fffff
9883 14:44:39.081067 INFO: [APUAPC] D3_APC_3: 0x0
9884 14:44:39.084014 INFO: [APUAPC] D4_APC_0: 0xffffffff
9885 14:44:39.090649 INFO: [APUAPC] D4_APC_1: 0xffffffff
9886 14:44:39.094124 INFO: [APUAPC] D4_APC_2: 0x3fffff
9887 14:44:39.094692 INFO: [APUAPC] D4_APC_3: 0x0
9888 14:44:39.097063 INFO: [APUAPC] D5_APC_0: 0xffffffff
9889 14:44:39.100777 INFO: [APUAPC] D5_APC_1: 0xffffffff
9890 14:44:39.103619 INFO: [APUAPC] D5_APC_2: 0x3fffff
9891 14:44:39.107515 INFO: [APUAPC] D5_APC_3: 0x0
9892 14:44:39.110487 INFO: [APUAPC] D6_APC_0: 0xffffffff
9893 14:44:39.113583 INFO: [APUAPC] D6_APC_1: 0xffffffff
9894 14:44:39.116892 INFO: [APUAPC] D6_APC_2: 0x3fffff
9895 14:44:39.119863 INFO: [APUAPC] D6_APC_3: 0x0
9896 14:44:39.123686 INFO: [APUAPC] D7_APC_0: 0xffffffff
9897 14:44:39.127487 INFO: [APUAPC] D7_APC_1: 0xffffffff
9898 14:44:39.129883 INFO: [APUAPC] D7_APC_2: 0x3fffff
9899 14:44:39.133558 INFO: [APUAPC] D7_APC_3: 0x0
9900 14:44:39.136332 INFO: [APUAPC] D8_APC_0: 0xffffffff
9901 14:44:39.140083 INFO: [APUAPC] D8_APC_1: 0xffffffff
9902 14:44:39.143171 INFO: [APUAPC] D8_APC_2: 0x3fffff
9903 14:44:39.146600 INFO: [APUAPC] D8_APC_3: 0x0
9904 14:44:39.149807 INFO: [APUAPC] D9_APC_0: 0xffffffff
9905 14:44:39.153085 INFO: [APUAPC] D9_APC_1: 0xffffffff
9906 14:44:39.156577 INFO: [APUAPC] D9_APC_2: 0x3fffff
9907 14:44:39.160091 INFO: [APUAPC] D9_APC_3: 0x0
9908 14:44:39.163065 INFO: [APUAPC] D10_APC_0: 0xffffffff
9909 14:44:39.166150 INFO: [APUAPC] D10_APC_1: 0xffffffff
9910 14:44:39.169572 INFO: [APUAPC] D10_APC_2: 0x3fffff
9911 14:44:39.173215 INFO: [APUAPC] D10_APC_3: 0x0
9912 14:44:39.176479 INFO: [APUAPC] D11_APC_0: 0xffffffff
9913 14:44:39.179245 INFO: [APUAPC] D11_APC_1: 0xffffffff
9914 14:44:39.182943 INFO: [APUAPC] D11_APC_2: 0x3fffff
9915 14:44:39.185884 INFO: [APUAPC] D11_APC_3: 0x0
9916 14:44:39.189329 INFO: [APUAPC] D12_APC_0: 0xffffffff
9917 14:44:39.192753 INFO: [APUAPC] D12_APC_1: 0xffffffff
9918 14:44:39.195632 INFO: [APUAPC] D12_APC_2: 0x3fffff
9919 14:44:39.199288 INFO: [APUAPC] D12_APC_3: 0x0
9920 14:44:39.202831 INFO: [APUAPC] D13_APC_0: 0xffffffff
9921 14:44:39.206096 INFO: [APUAPC] D13_APC_1: 0xffffffff
9922 14:44:39.209371 INFO: [APUAPC] D13_APC_2: 0x3fffff
9923 14:44:39.212483 INFO: [APUAPC] D13_APC_3: 0x0
9924 14:44:39.216214 INFO: [APUAPC] D14_APC_0: 0xffffffff
9925 14:44:39.222519 INFO: [APUAPC] D14_APC_1: 0xffffffff
9926 14:44:39.225569 INFO: [APUAPC] D14_APC_2: 0x3fffff
9927 14:44:39.225989 INFO: [APUAPC] D14_APC_3: 0x0
9928 14:44:39.232204 INFO: [APUAPC] D15_APC_0: 0xffffffff
9929 14:44:39.236269 INFO: [APUAPC] D15_APC_1: 0xffffffff
9930 14:44:39.238831 INFO: [APUAPC] D15_APC_2: 0x3fffff
9931 14:44:39.239251 INFO: [APUAPC] D15_APC_3: 0x0
9932 14:44:39.242370 INFO: [APUAPC] APC_CON: 0x4
9933 14:44:39.245967 INFO: [NOCDAPC] D0_APC_0: 0x0
9934 14:44:39.249408 INFO: [NOCDAPC] D0_APC_1: 0x0
9935 14:44:39.252392 INFO: [NOCDAPC] D1_APC_0: 0x0
9936 14:44:39.255834 INFO: [NOCDAPC] D1_APC_1: 0xfff
9937 14:44:39.258781 INFO: [NOCDAPC] D2_APC_0: 0x0
9938 14:44:39.262014 INFO: [NOCDAPC] D2_APC_1: 0xfff
9939 14:44:39.265071 INFO: [NOCDAPC] D3_APC_0: 0x0
9940 14:44:39.268486 INFO: [NOCDAPC] D3_APC_1: 0xfff
9941 14:44:39.268905 INFO: [NOCDAPC] D4_APC_0: 0x0
9942 14:44:39.271618 INFO: [NOCDAPC] D4_APC_1: 0xfff
9943 14:44:39.275159 INFO: [NOCDAPC] D5_APC_0: 0x0
9944 14:44:39.278451 INFO: [NOCDAPC] D5_APC_1: 0xfff
9945 14:44:39.281647 INFO: [NOCDAPC] D6_APC_0: 0x0
9946 14:44:39.285371 INFO: [NOCDAPC] D6_APC_1: 0xfff
9947 14:44:39.288761 INFO: [NOCDAPC] D7_APC_0: 0x0
9948 14:44:39.291795 INFO: [NOCDAPC] D7_APC_1: 0xfff
9949 14:44:39.295028 INFO: [NOCDAPC] D8_APC_0: 0x0
9950 14:44:39.298077 INFO: [NOCDAPC] D8_APC_1: 0xfff
9951 14:44:39.301359 INFO: [NOCDAPC] D9_APC_0: 0x0
9952 14:44:39.305005 INFO: [NOCDAPC] D9_APC_1: 0xfff
9953 14:44:39.305503 INFO: [NOCDAPC] D10_APC_0: 0x0
9954 14:44:39.308432 INFO: [NOCDAPC] D10_APC_1: 0xfff
9955 14:44:39.311821 INFO: [NOCDAPC] D11_APC_0: 0x0
9956 14:44:39.315023 INFO: [NOCDAPC] D11_APC_1: 0xfff
9957 14:44:39.317841 INFO: [NOCDAPC] D12_APC_0: 0x0
9958 14:44:39.321357 INFO: [NOCDAPC] D12_APC_1: 0xfff
9959 14:44:39.324429 INFO: [NOCDAPC] D13_APC_0: 0x0
9960 14:44:39.327582 INFO: [NOCDAPC] D13_APC_1: 0xfff
9961 14:44:39.331352 INFO: [NOCDAPC] D14_APC_0: 0x0
9962 14:44:39.334659 INFO: [NOCDAPC] D14_APC_1: 0xfff
9963 14:44:39.338546 INFO: [NOCDAPC] D15_APC_0: 0x0
9964 14:44:39.341252 INFO: [NOCDAPC] D15_APC_1: 0xfff
9965 14:44:39.344888 INFO: [NOCDAPC] APC_CON: 0x4
9966 14:44:39.347823 INFO: [APUAPC] set_apusys_apc done
9967 14:44:39.351164 INFO: [DEVAPC] devapc_init done
9968 14:44:39.354313 INFO: GICv3 without legacy support detected.
9969 14:44:39.357707 INFO: ARM GICv3 driver initialized in EL3
9970 14:44:39.361089 INFO: Maximum SPI INTID supported: 639
9971 14:44:39.364194 INFO: BL31: Initializing runtime services
9972 14:44:39.371590 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9973 14:44:39.374111 INFO: SPM: enable CPC mode
9974 14:44:39.380802 INFO: mcdi ready for mcusys-off-idle and system suspend
9975 14:44:39.384059 INFO: BL31: Preparing for EL3 exit to normal world
9976 14:44:39.387503 INFO: Entry point address = 0x80000000
9977 14:44:39.391420 INFO: SPSR = 0x8
9978 14:44:39.395590
9979 14:44:39.396016
9980 14:44:39.396337
9981 14:44:39.398631 Starting depthcharge on Spherion...
9982 14:44:39.399045
9983 14:44:39.399367 Wipe memory regions:
9984 14:44:39.399667
9985 14:44:39.401925 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
9986 14:44:39.402436 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
9987 14:44:39.402848 Setting prompt string to ['asurada:']
9988 14:44:39.403314 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
9989 14:44:39.404142 [0x00000040000000, 0x00000054600000)
9990 14:44:39.524537
9991 14:44:39.525036 [0x00000054660000, 0x00000080000000)
9992 14:44:39.785439
9993 14:44:39.785848 [0x000000821a7280, 0x000000ffe64000)
9994 14:44:40.529797
9995 14:44:40.530006 [0x00000100000000, 0x00000240000000)
9996 14:44:42.420773
9997 14:44:42.423807 Initializing XHCI USB controller at 0x11200000.
9998 14:44:43.463501
9999 14:44:43.466824 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10000 14:44:43.467345
10001 14:44:43.467676
10002 14:44:43.468439 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10004 14:44:43.569604 asurada: tftpboot 192.168.201.1 14167015/tftp-deploy-r735clyv/kernel/image.itb 14167015/tftp-deploy-r735clyv/kernel/cmdline
10005 14:44:43.570082 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10006 14:44:43.570372 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10007 14:44:43.575158 tftpboot 192.168.201.1 14167015/tftp-deploy-r735clyv/kernel/image.ittp-deploy-r735clyv/kernel/cmdline
10008 14:44:43.575389
10009 14:44:43.575565 Waiting for link
10010 14:44:43.732766
10011 14:44:43.733077 R8152: Initializing
10012 14:44:43.733276
10013 14:44:43.736666 Version 6 (ocp_data = 5c30)
10014 14:44:43.736847
10015 14:44:43.739585 R8152: Done initializing
10016 14:44:43.739802
10017 14:44:43.739942 Adding net device
10018 14:44:45.610037
10019 14:44:45.610545 done.
10020 14:44:45.610885
10021 14:44:45.611191 MAC: 00:24:32:30:7c:7b
10022 14:44:45.611507
10023 14:44:45.612991 Sending DHCP discover... done.
10024 14:44:45.613444
10025 14:44:45.616120 Waiting for reply... done.
10026 14:44:45.616578
10027 14:44:45.620192 Sending DHCP request... done.
10028 14:44:45.620613
10029 14:44:45.625901 Waiting for reply... done.
10030 14:44:45.626328
10031 14:44:45.626661 My ip is 192.168.201.14
10032 14:44:45.626967
10033 14:44:45.628676 The DHCP server ip is 192.168.201.1
10034 14:44:45.629094
10035 14:44:45.635570 TFTP server IP predefined by user: 192.168.201.1
10036 14:44:45.635996
10037 14:44:45.641983 Bootfile predefined by user: 14167015/tftp-deploy-r735clyv/kernel/image.itb
10038 14:44:45.642403
10039 14:44:45.645571 Sending tftp read request... done.
10040 14:44:45.645993
10041 14:44:45.652215 Waiting for the transfer...
10042 14:44:45.652746
10043 14:44:46.291529 00000000 ################################################################
10044 14:44:46.291703
10045 14:44:46.941198 00080000 ################################################################
10046 14:44:46.941777
10047 14:44:47.638282 00100000 ################################################################
10048 14:44:47.638806
10049 14:44:48.353589 00180000 ################################################################
10050 14:44:48.354122
10051 14:44:49.062989 00200000 ################################################################
10052 14:44:49.063510
10053 14:44:49.753632 00280000 ################################################################
10054 14:44:49.753898
10055 14:44:50.418307 00300000 ################################################################
10056 14:44:50.418945
10057 14:44:51.119574 00380000 ################################################################
10058 14:44:51.119710
10059 14:44:51.671884 00400000 ################################################################
10060 14:44:51.672021
10061 14:44:52.240661 00480000 ################################################################
10062 14:44:52.240817
10063 14:44:52.802826 00500000 ################################################################
10064 14:44:52.802991
10065 14:44:53.376291 00580000 ################################################################
10066 14:44:53.376458
10067 14:44:53.947265 00600000 ################################################################
10068 14:44:53.947410
10069 14:44:54.516602 00680000 ################################################################
10070 14:44:54.516738
10071 14:44:55.102395 00700000 ################################################################
10072 14:44:55.102885
10073 14:44:55.651205 00780000 ################################################################
10074 14:44:55.651343
10075 14:44:56.206179 00800000 ################################################################
10076 14:44:56.206316
10077 14:44:56.779087 00880000 ################################################################
10078 14:44:56.779239
10079 14:44:57.340926 00900000 ################################################################
10080 14:44:57.341062
10081 14:44:57.904758 00980000 ################################################################
10082 14:44:57.904892
10083 14:44:58.462036 00a00000 ################################################################
10084 14:44:58.462172
10085 14:44:59.033868 00a80000 ################################################################
10086 14:44:59.033999
10087 14:44:59.593780 00b00000 ################################################################
10088 14:44:59.593920
10089 14:45:00.149464 00b80000 ################################################################
10090 14:45:00.149605
10091 14:45:00.706508 00c00000 ################################################################
10092 14:45:00.706634
10093 14:45:01.276762 00c80000 ################################################################
10094 14:45:01.276896
10095 14:45:01.865129 00d00000 ################################################################
10096 14:45:01.865265
10097 14:45:02.439354 00d80000 ################################################################
10098 14:45:02.439484
10099 14:45:03.010719 00e00000 ################################################################
10100 14:45:03.010850
10101 14:45:03.565895 00e80000 ################################################################
10102 14:45:03.566061
10103 14:45:04.115833 00f00000 ################################################################
10104 14:45:04.115984
10105 14:45:04.654617 00f80000 ################################################################
10106 14:45:04.654748
10107 14:45:05.204552 01000000 ################################################################
10108 14:45:05.204703
10109 14:45:05.747904 01080000 ################################################################
10110 14:45:05.748048
10111 14:45:06.301203 01100000 ################################################################
10112 14:45:06.301384
10113 14:45:06.852124 01180000 ################################################################
10114 14:45:06.852295
10115 14:45:07.405176 01200000 ################################################################
10116 14:45:07.405385
10117 14:45:07.951695 01280000 ################################################################
10118 14:45:07.951849
10119 14:45:08.501268 01300000 ################################################################
10120 14:45:08.501422
10121 14:45:09.047984 01380000 ################################################################
10122 14:45:09.048128
10123 14:45:09.615317 01400000 ################################################################
10124 14:45:09.615463
10125 14:45:10.142640 01480000 ################################################################
10126 14:45:10.142779
10127 14:45:10.670331 01500000 ################################################################
10128 14:45:10.670475
10129 14:45:11.204599 01580000 ################################################################
10130 14:45:11.204736
10131 14:45:11.746258 01600000 ################################################################
10132 14:45:11.746401
10133 14:45:12.284862 01680000 ################################################################
10134 14:45:12.285023
10135 14:45:12.831404 01700000 ################################################################
10136 14:45:12.831534
10137 14:45:13.363077 01780000 ################################################################
10138 14:45:13.363238
10139 14:45:13.893117 01800000 ################################################################
10140 14:45:13.893293
10141 14:45:14.457454 01880000 ################################################################
10142 14:45:14.457593
10143 14:45:14.985879 01900000 ################################################################
10144 14:45:14.986050
10145 14:45:15.535077 01980000 ################################################################
10146 14:45:15.535246
10147 14:45:16.108841 01a00000 ################################################################
10148 14:45:16.109017
10149 14:45:16.673220 01a80000 ################################################################
10150 14:45:16.673410
10151 14:45:17.241905 01b00000 ################################################################
10152 14:45:17.242050
10153 14:45:17.785555 01b80000 ################################################################
10154 14:45:17.785694
10155 14:45:18.360956 01c00000 ################################################################
10156 14:45:18.361106
10157 14:45:18.932121 01c80000 ################################################################
10158 14:45:18.932252
10159 14:45:19.582373 01d00000 ################################################################
10160 14:45:19.582931
10161 14:45:20.282817 01d80000 ################################################################
10162 14:45:20.283332
10163 14:45:20.948625 01e00000 ################################################################
10164 14:45:20.949143
10165 14:45:21.634266 01e80000 ################################################################
10166 14:45:21.634766
10167 14:45:22.323166 01f00000 ################################################################
10168 14:45:22.323668
10169 14:45:22.960170 01f80000 ################################################################
10170 14:45:22.960771
10171 14:45:23.638598 02000000 ################################################################
10172 14:45:23.638734
10173 14:45:24.076539 02080000 ############################################## done.
10174 14:45:24.076801
10175 14:45:24.079487 The bootfile was 34455510 bytes long.
10176 14:45:24.079695
10177 14:45:24.083017 Sending tftp read request... done.
10178 14:45:24.083284
10179 14:45:24.083514 Waiting for the transfer...
10180 14:45:24.083672
10181 14:45:24.086660 00000000 # done.
10182 14:45:24.086865
10183 14:45:24.093274 Command line loaded dynamically from TFTP file: 14167015/tftp-deploy-r735clyv/kernel/cmdline
10184 14:45:24.093545
10185 14:45:24.106488 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10186 14:45:24.106736
10187 14:45:24.109643 Loading FIT.
10188 14:45:24.109883
10189 14:45:24.112790 Image ramdisk-1 has 21345597 bytes.
10190 14:45:24.113032
10191 14:45:24.116696 Image fdt-1 has 47258 bytes.
10192 14:45:24.116936
10193 14:45:24.117124 Image kernel-1 has 13060619 bytes.
10194 14:45:24.119653
10195 14:45:24.126073 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10196 14:45:24.126316
10197 14:45:24.142676 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10198 14:45:24.145783
10199 14:45:24.149228 Choosing best match conf-1 for compat google,spherion-rev2.
10200 14:45:24.153677
10201 14:45:24.158645 Connected to device vid:did:rid of 1ae0:0028:00
10202 14:45:24.165605
10203 14:45:24.168904 tpm_get_response: command 0x17b, return code 0x0
10204 14:45:24.169380
10205 14:45:24.172179 ec_init: CrosEC protocol v3 supported (256, 248)
10206 14:45:24.177120
10207 14:45:24.180320 tpm_cleanup: add release locality here.
10208 14:45:24.180743
10209 14:45:24.181069 Shutting down all USB controllers.
10210 14:45:24.183705
10211 14:45:24.184123 Removing current net device
10212 14:45:24.184451
10213 14:45:24.189828 Exiting depthcharge with code 4 at timestamp: 73991144
10214 14:45:24.190251
10215 14:45:24.193186 LZMA decompressing kernel-1 to 0x821a6718
10216 14:45:24.193675
10217 14:45:24.197022 LZMA decompressing kernel-1 to 0x40000000
10218 14:45:25.808768
10219 14:45:25.808918 jumping to kernel
10220 14:45:25.809421 end: 2.2.4 bootloader-commands (duration 00:00:46) [common]
10221 14:45:25.809521 start: 2.2.5 auto-login-action (timeout 00:03:41) [common]
10222 14:45:25.809597 Setting prompt string to ['Linux version [0-9]']
10223 14:45:25.809666 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10224 14:45:25.809734 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10225 14:45:25.889990
10226 14:45:25.893034 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10227 14:45:25.896542 start: 2.2.5.1 login-action (timeout 00:03:40) [common]
10228 14:45:25.896642 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10229 14:45:25.896714 Setting prompt string to []
10230 14:45:25.896791 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10231 14:45:25.896860 Using line separator: #'\n'#
10232 14:45:25.896953 No login prompt set.
10233 14:45:25.897012 Parsing kernel messages
10234 14:45:25.897066 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10235 14:45:25.897191 [login-action] Waiting for messages, (timeout 00:03:40)
10236 14:45:25.897297 Waiting using forced prompt support (timeout 00:01:50)
10237 14:45:25.916547 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j216541-arm64-gcc-10-defconfig-arm64-chromebook-f7c97) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024
10238 14:45:25.920521 [ 0.000000] random: crng init done
10239 14:45:25.926230 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10240 14:45:25.929782 [ 0.000000] efi: UEFI not found.
10241 14:45:25.936106 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10242 14:45:25.946033 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10243 14:45:25.953251 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10244 14:45:25.962719 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10245 14:45:25.969900 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10246 14:45:25.976144 [ 0.000000] printk: bootconsole [mtk8250] enabled
10247 14:45:25.982560 [ 0.000000] NUMA: No NUMA configuration found
10248 14:45:25.989299 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10249 14:45:25.992630 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10250 14:45:25.996058 [ 0.000000] Zone ranges:
10251 14:45:26.002811 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10252 14:45:26.006200 [ 0.000000] DMA32 empty
10253 14:45:26.012937 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10254 14:45:26.016107 [ 0.000000] Movable zone start for each node
10255 14:45:26.019443 [ 0.000000] Early memory node ranges
10256 14:45:26.025929 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10257 14:45:26.032243 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10258 14:45:26.038997 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10259 14:45:26.045703 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10260 14:45:26.049018 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10261 14:45:26.058936 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10262 14:45:26.114539 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10263 14:45:26.121440 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10264 14:45:26.128066 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10265 14:45:26.131586 [ 0.000000] psci: probing for conduit method from DT.
10266 14:45:26.137967 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10267 14:45:26.141661 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10268 14:45:26.148497 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10269 14:45:26.151136 [ 0.000000] psci: SMC Calling Convention v1.2
10270 14:45:26.158042 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10271 14:45:26.161252 [ 0.000000] Detected VIPT I-cache on CPU0
10272 14:45:26.167953 [ 0.000000] CPU features: detected: GIC system register CPU interface
10273 14:45:26.175049 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10274 14:45:26.181240 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10275 14:45:26.187746 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10276 14:45:26.194359 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10277 14:45:26.201707 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10278 14:45:26.207953 [ 0.000000] alternatives: applying boot alternatives
10279 14:45:26.210910 [ 0.000000] Fallback order for Node 0: 0
10280 14:45:26.221421 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10281 14:45:26.221560 [ 0.000000] Policy zone: Normal
10282 14:45:26.237967 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10283 14:45:26.247744 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10284 14:45:26.259070 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10285 14:45:26.269151 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10286 14:45:26.275296 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10287 14:45:26.278620 <6>[ 0.000000] software IO TLB: area num 8.
10288 14:45:26.335622 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10289 14:45:26.485698 <6>[ 0.000000] Memory: 7943344K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 409424K reserved, 32768K cma-reserved)
10290 14:45:26.492577 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10291 14:45:26.499011 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10292 14:45:26.502545 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10293 14:45:26.509062 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10294 14:45:26.515643 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10295 14:45:26.519029 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10296 14:45:26.528809 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10297 14:45:26.534916 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10298 14:45:26.542275 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10299 14:45:26.548226 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10300 14:45:26.551437 <6>[ 0.000000] GICv3: 608 SPIs implemented
10301 14:45:26.554974 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10302 14:45:26.561922 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10303 14:45:26.565020 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10304 14:45:26.571890 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10305 14:45:26.584777 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10306 14:45:26.598103 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10307 14:45:26.604310 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10308 14:45:26.612651 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10309 14:45:26.625574 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10310 14:45:26.632108 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10311 14:45:26.638810 <6>[ 0.009180] Console: colour dummy device 80x25
10312 14:45:26.648665 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10313 14:45:26.655411 <6>[ 0.024415] pid_max: default: 32768 minimum: 301
10314 14:45:26.658681 <6>[ 0.029317] LSM: Security Framework initializing
10315 14:45:26.665116 <6>[ 0.034255] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10316 14:45:26.675284 <6>[ 0.042117] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10317 14:45:26.685187 <6>[ 0.051584] cblist_init_generic: Setting adjustable number of callback queues.
10318 14:45:26.688334 <6>[ 0.059027] cblist_init_generic: Setting shift to 3 and lim to 1.
10319 14:45:26.698135 <6>[ 0.065404] cblist_init_generic: Setting adjustable number of callback queues.
10320 14:45:26.704668 <6>[ 0.072830] cblist_init_generic: Setting shift to 3 and lim to 1.
10321 14:45:26.708387 <6>[ 0.079229] rcu: Hierarchical SRCU implementation.
10322 14:45:26.714604 <6>[ 0.084245] rcu: Max phase no-delay instances is 1000.
10323 14:45:26.721338 <6>[ 0.091269] EFI services will not be available.
10324 14:45:26.724553 <6>[ 0.096257] smp: Bringing up secondary CPUs ...
10325 14:45:26.732832 <6>[ 0.101336] Detected VIPT I-cache on CPU1
10326 14:45:26.739677 <6>[ 0.101408] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10327 14:45:26.746342 <6>[ 0.101437] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10328 14:45:26.749847 <6>[ 0.101770] Detected VIPT I-cache on CPU2
10329 14:45:26.756681 <6>[ 0.101817] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10330 14:45:26.766434 <6>[ 0.101832] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10331 14:45:26.769606 <6>[ 0.102086] Detected VIPT I-cache on CPU3
10332 14:45:26.775947 <6>[ 0.102133] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10333 14:45:26.782497 <6>[ 0.102147] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10334 14:45:26.786872 <6>[ 0.102438] CPU features: detected: Spectre-v4
10335 14:45:26.792933 <6>[ 0.102444] CPU features: detected: Spectre-BHB
10336 14:45:26.796694 <6>[ 0.102448] Detected PIPT I-cache on CPU4
10337 14:45:26.803070 <6>[ 0.102499] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10338 14:45:26.809221 <6>[ 0.102514] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10339 14:45:26.816479 <6>[ 0.102793] Detected PIPT I-cache on CPU5
10340 14:45:26.822809 <6>[ 0.102856] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10341 14:45:26.829950 <6>[ 0.102872] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10342 14:45:26.832607 <6>[ 0.103155] Detected PIPT I-cache on CPU6
10343 14:45:26.840318 <6>[ 0.103221] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10344 14:45:26.846230 <6>[ 0.103237] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10345 14:45:26.852560 <6>[ 0.103534] Detected PIPT I-cache on CPU7
10346 14:45:26.859121 <6>[ 0.103599] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10347 14:45:26.866012 <6>[ 0.103615] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10348 14:45:26.868925 <6>[ 0.103662] smp: Brought up 1 node, 8 CPUs
10349 14:45:26.876131 <6>[ 0.245048] SMP: Total of 8 processors activated.
10350 14:45:26.879057 <6>[ 0.249969] CPU features: detected: 32-bit EL0 Support
10351 14:45:26.888926 <6>[ 0.255333] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10352 14:45:26.895374 <6>[ 0.264133] CPU features: detected: Common not Private translations
10353 14:45:26.902005 <6>[ 0.270609] CPU features: detected: CRC32 instructions
10354 14:45:26.905917 <6>[ 0.275994] CPU features: detected: RCpc load-acquire (LDAPR)
10355 14:45:26.911630 <6>[ 0.281954] CPU features: detected: LSE atomic instructions
10356 14:45:26.918354 <6>[ 0.287736] CPU features: detected: Privileged Access Never
10357 14:45:26.925006 <6>[ 0.293515] CPU features: detected: RAS Extension Support
10358 14:45:26.931798 <6>[ 0.299159] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10359 14:45:26.935143 <6>[ 0.306381] CPU: All CPU(s) started at EL2
10360 14:45:26.941269 <6>[ 0.310724] alternatives: applying system-wide alternatives
10361 14:45:26.950640 <6>[ 0.321574] devtmpfs: initialized
10362 14:45:26.966298 <6>[ 0.330473] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10363 14:45:26.972764 <6>[ 0.340433] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10364 14:45:26.979483 <6>[ 0.348450] pinctrl core: initialized pinctrl subsystem
10365 14:45:26.982861 <6>[ 0.355071] DMI not present or invalid.
10366 14:45:26.989707 <6>[ 0.359480] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10367 14:45:26.999168 <6>[ 0.366347] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10368 14:45:27.005900 <6>[ 0.373937] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10369 14:45:27.015664 <6>[ 0.382156] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10370 14:45:27.019369 <6>[ 0.390400] audit: initializing netlink subsys (disabled)
10371 14:45:27.028767 <5>[ 0.396095] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10372 14:45:27.035840 <6>[ 0.396797] thermal_sys: Registered thermal governor 'step_wise'
10373 14:45:27.042662 <6>[ 0.404060] thermal_sys: Registered thermal governor 'power_allocator'
10374 14:45:27.046464 <6>[ 0.410314] cpuidle: using governor menu
10375 14:45:27.052230 <6>[ 0.421276] NET: Registered PF_QIPCRTR protocol family
10376 14:45:27.059189 <6>[ 0.426759] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10377 14:45:27.062253 <6>[ 0.433863] ASID allocator initialised with 32768 entries
10378 14:45:27.069451 <6>[ 0.440434] Serial: AMBA PL011 UART driver
10379 14:45:27.078198 <4>[ 0.449158] Trying to register duplicate clock ID: 134
10380 14:45:27.136896 <6>[ 0.510442] KASLR enabled
10381 14:45:27.151078 <6>[ 0.518159] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10382 14:45:27.157931 <6>[ 0.525172] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10383 14:45:27.164551 <6>[ 0.531659] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10384 14:45:27.170856 <6>[ 0.538660] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10385 14:45:27.178169 <6>[ 0.545144] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10386 14:45:27.184452 <6>[ 0.552146] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10387 14:45:27.191238 <6>[ 0.558633] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10388 14:45:27.197474 <6>[ 0.565636] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10389 14:45:27.201189 <6>[ 0.573089] ACPI: Interpreter disabled.
10390 14:45:27.208965 <6>[ 0.579538] iommu: Default domain type: Translated
10391 14:45:27.215722 <6>[ 0.584650] iommu: DMA domain TLB invalidation policy: strict mode
10392 14:45:27.219240 <5>[ 0.591317] SCSI subsystem initialized
10393 14:45:27.225924 <6>[ 0.595568] usbcore: registered new interface driver usbfs
10394 14:45:27.232580 <6>[ 0.601297] usbcore: registered new interface driver hub
10395 14:45:27.235876 <6>[ 0.606846] usbcore: registered new device driver usb
10396 14:45:27.242879 <6>[ 0.612957] pps_core: LinuxPPS API ver. 1 registered
10397 14:45:27.252463 <6>[ 0.618149] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10398 14:45:27.255768 <6>[ 0.627492] PTP clock support registered
10399 14:45:27.259313 <6>[ 0.631734] EDAC MC: Ver: 3.0.0
10400 14:45:27.266387 <6>[ 0.636915] FPGA manager framework
10401 14:45:27.272865 <6>[ 0.640592] Advanced Linux Sound Architecture Driver Initialized.
10402 14:45:27.276746 <6>[ 0.647368] vgaarb: loaded
10403 14:45:27.282851 <6>[ 0.650523] clocksource: Switched to clocksource arch_sys_counter
10404 14:45:27.286095 <5>[ 0.656973] VFS: Disk quotas dquot_6.6.0
10405 14:45:27.293742 <6>[ 0.661160] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10406 14:45:27.295996 <6>[ 0.668352] pnp: PnP ACPI: disabled
10407 14:45:27.304334 <6>[ 0.675012] NET: Registered PF_INET protocol family
10408 14:45:27.314494 <6>[ 0.680615] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10409 14:45:27.326105 <6>[ 0.692970] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10410 14:45:27.336072 <6>[ 0.701787] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10411 14:45:27.342183 <6>[ 0.709762] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10412 14:45:27.351901 <6>[ 0.718461] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10413 14:45:27.358943 <6>[ 0.728204] TCP: Hash tables configured (established 65536 bind 65536)
10414 14:45:27.365238 <6>[ 0.735070] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10415 14:45:27.375340 <6>[ 0.742267] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10416 14:45:27.381762 <6>[ 0.749971] NET: Registered PF_UNIX/PF_LOCAL protocol family
10417 14:45:27.388982 <6>[ 0.756070] RPC: Registered named UNIX socket transport module.
10418 14:45:27.391605 <6>[ 0.762225] RPC: Registered udp transport module.
10419 14:45:27.398557 <6>[ 0.767157] RPC: Registered tcp transport module.
10420 14:45:27.404918 <6>[ 0.772089] RPC: Registered tcp NFSv4.1 backchannel transport module.
10421 14:45:27.407994 <6>[ 0.778756] PCI: CLS 0 bytes, default 64
10422 14:45:27.411119 <6>[ 0.783102] Unpacking initramfs...
10423 14:45:27.435262 <6>[ 0.802619] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10424 14:45:27.445365 <6>[ 0.811295] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10425 14:45:27.448407 <6>[ 0.820134] kvm [1]: IPA Size Limit: 40 bits
10426 14:45:27.455159 <6>[ 0.824663] kvm [1]: GICv3: no GICV resource entry
10427 14:45:27.458590 <6>[ 0.829684] kvm [1]: disabling GICv2 emulation
10428 14:45:27.465620 <6>[ 0.834370] kvm [1]: GIC system register CPU interface enabled
10429 14:45:27.468336 <6>[ 0.840538] kvm [1]: vgic interrupt IRQ18
10430 14:45:27.475194 <6>[ 0.844894] kvm [1]: VHE mode initialized successfully
10431 14:45:27.481998 <5>[ 0.851319] Initialise system trusted keyrings
10432 14:45:27.488585 <6>[ 0.856141] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10433 14:45:27.495874 <6>[ 0.866170] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10434 14:45:27.502271 <5>[ 0.872542] NFS: Registering the id_resolver key type
10435 14:45:27.505761 <5>[ 0.877850] Key type id_resolver registered
10436 14:45:27.512337 <5>[ 0.882267] Key type id_legacy registered
10437 14:45:27.519081 <6>[ 0.886551] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10438 14:45:27.525368 <6>[ 0.893473] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10439 14:45:27.532063 <6>[ 0.901174] 9p: Installing v9fs 9p2000 file system support
10440 14:45:27.568604 <5>[ 0.939023] Key type asymmetric registered
10441 14:45:27.572048 <5>[ 0.943353] Asymmetric key parser 'x509' registered
10442 14:45:27.582002 <6>[ 0.948488] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10443 14:45:27.585525 <6>[ 0.956108] io scheduler mq-deadline registered
10444 14:45:27.588761 <6>[ 0.960879] io scheduler kyber registered
10445 14:45:27.607085 <6>[ 0.977790] EINJ: ACPI disabled.
10446 14:45:27.639445 <4>[ 1.003512] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10447 14:45:27.649343 <4>[ 1.014127] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10448 14:45:27.664687 <6>[ 1.035096] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10449 14:45:27.672463 <6>[ 1.043056] printk: console [ttyS0] disabled
10450 14:45:27.700909 <6>[ 1.067685] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10451 14:45:27.707438 <6>[ 1.077158] printk: console [ttyS0] enabled
10452 14:45:27.710417 <6>[ 1.077158] printk: console [ttyS0] enabled
10453 14:45:27.717213 <6>[ 1.086052] printk: bootconsole [mtk8250] disabled
10454 14:45:27.720162 <6>[ 1.086052] printk: bootconsole [mtk8250] disabled
10455 14:45:27.726741 <6>[ 1.097092] SuperH (H)SCI(F) driver initialized
10456 14:45:27.730320 <6>[ 1.102361] msm_serial: driver initialized
10457 14:45:27.744286 <6>[ 1.111223] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10458 14:45:27.754229 <6>[ 1.119767] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10459 14:45:27.760423 <6>[ 1.128309] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10460 14:45:27.770526 <6>[ 1.136936] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10461 14:45:27.780660 <6>[ 1.145642] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10462 14:45:27.786789 <6>[ 1.154356] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10463 14:45:27.796950 <6>[ 1.162896] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10464 14:45:27.803515 <6>[ 1.171701] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10465 14:45:27.813138 <6>[ 1.180243] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10466 14:45:27.825304 <6>[ 1.195770] loop: module loaded
10467 14:45:27.832071 <6>[ 1.201743] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10468 14:45:27.854338 <4>[ 1.224998] mtk-pmic-keys: Failed to locate of_node [id: -1]
10469 14:45:27.861066 <6>[ 1.231802] megasas: 07.719.03.00-rc1
10470 14:45:27.870656 <6>[ 1.241287] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10471 14:45:27.879174 <6>[ 1.249925] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10472 14:45:27.895945 <6>[ 1.266599] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10473 14:45:27.952114 <6>[ 1.316619] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10474 14:45:28.317446 <6>[ 1.688089] Freeing initrd memory: 20840K
10475 14:45:28.333100 <6>[ 1.703991] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10476 14:45:28.343876 <6>[ 1.714908] tun: Universal TUN/TAP device driver, 1.6
10477 14:45:28.347440 <6>[ 1.720964] thunder_xcv, ver 1.0
10478 14:45:28.350446 <6>[ 1.724469] thunder_bgx, ver 1.0
10479 14:45:28.353689 <6>[ 1.727963] nicpf, ver 1.0
10480 14:45:28.364393 <6>[ 1.731963] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10481 14:45:28.367472 <6>[ 1.739440] hns3: Copyright (c) 2017 Huawei Corporation.
10482 14:45:28.374282 <6>[ 1.745027] hclge is initializing
10483 14:45:28.377551 <6>[ 1.748607] e1000: Intel(R) PRO/1000 Network Driver
10484 14:45:28.384790 <6>[ 1.753737] e1000: Copyright (c) 1999-2006 Intel Corporation.
10485 14:45:28.387662 <6>[ 1.759751] e1000e: Intel(R) PRO/1000 Network Driver
10486 14:45:28.394293 <6>[ 1.764966] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10487 14:45:28.400899 <6>[ 1.771151] igb: Intel(R) Gigabit Ethernet Network Driver
10488 14:45:28.407519 <6>[ 1.776801] igb: Copyright (c) 2007-2014 Intel Corporation.
10489 14:45:28.414174 <6>[ 1.782640] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10490 14:45:28.420997 <6>[ 1.789159] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10491 14:45:28.424004 <6>[ 1.795619] sky2: driver version 1.30
10492 14:45:28.430923 <6>[ 1.800539] usbcore: registered new device driver r8152-cfgselector
10493 14:45:28.437687 <6>[ 1.807075] usbcore: registered new interface driver r8152
10494 14:45:28.443564 <6>[ 1.812888] VFIO - User Level meta-driver version: 0.3
10495 14:45:28.450496 <6>[ 1.821123] usbcore: registered new interface driver usb-storage
10496 14:45:28.456770 <6>[ 1.827571] usbcore: registered new device driver onboard-usb-hub
10497 14:45:28.466129 <6>[ 1.836704] mt6397-rtc mt6359-rtc: registered as rtc0
10498 14:45:28.475829 <6>[ 1.842166] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T14:45:28 UTC (1717512328)
10499 14:45:28.478840 <6>[ 1.851735] i2c_dev: i2c /dev entries driver
10500 14:45:28.496034 <6>[ 1.863638] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10501 14:45:28.502811 <4>[ 1.872387] cpu cpu0: supply cpu not found, using dummy regulator
10502 14:45:28.509281 <4>[ 1.878806] cpu cpu1: supply cpu not found, using dummy regulator
10503 14:45:28.515792 <4>[ 1.885217] cpu cpu2: supply cpu not found, using dummy regulator
10504 14:45:28.522499 <4>[ 1.891632] cpu cpu3: supply cpu not found, using dummy regulator
10505 14:45:28.529515 <4>[ 1.898030] cpu cpu4: supply cpu not found, using dummy regulator
10506 14:45:28.535930 <4>[ 1.904425] cpu cpu5: supply cpu not found, using dummy regulator
10507 14:45:28.543182 <4>[ 1.910823] cpu cpu6: supply cpu not found, using dummy regulator
10508 14:45:28.549120 <4>[ 1.917222] cpu cpu7: supply cpu not found, using dummy regulator
10509 14:45:28.567367 <6>[ 1.937874] cpu cpu0: EM: created perf domain
10510 14:45:28.570643 <6>[ 1.942816] cpu cpu4: EM: created perf domain
10511 14:45:28.577981 <6>[ 1.948390] sdhci: Secure Digital Host Controller Interface driver
10512 14:45:28.584551 <6>[ 1.954820] sdhci: Copyright(c) Pierre Ossman
10513 14:45:28.591122 <6>[ 1.959779] Synopsys Designware Multimedia Card Interface Driver
10514 14:45:28.597795 <6>[ 1.966430] sdhci-pltfm: SDHCI platform and OF driver helper
10515 14:45:28.600839 <6>[ 1.966442] mmc0: CQHCI version 5.10
10516 14:45:28.607448 <6>[ 1.976510] ledtrig-cpu: registered to indicate activity on CPUs
10517 14:45:28.614294 <6>[ 1.983589] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10518 14:45:28.620776 <6>[ 1.990646] usbcore: registered new interface driver usbhid
10519 14:45:28.624514 <6>[ 1.996468] usbhid: USB HID core driver
10520 14:45:28.630731 <6>[ 2.000678] spi_master spi0: will run message pump with realtime priority
10521 14:45:28.676629 <6>[ 2.040602] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10522 14:45:28.696195 <6>[ 2.056341] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10523 14:45:28.698938 <6>[ 2.069894] mmc0: Command Queue Engine enabled
10524 14:45:28.706214 <6>[ 2.074678] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10525 14:45:28.712673 <6>[ 2.082439] mmcblk0: mmc0:0001 DA4128 116 GiB
10526 14:45:28.719224 <6>[ 2.087409] cros-ec-spi spi0.0: Chrome EC device registered
10527 14:45:28.722438 <6>[ 2.091041] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10528 14:45:28.730195 <6>[ 2.100250] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10529 14:45:28.736666 <6>[ 2.106633] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10530 14:45:28.743673 <6>[ 2.112730] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10531 14:45:28.761424 <6>[ 2.128440] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10532 14:45:28.769021 <6>[ 2.139308] NET: Registered PF_PACKET protocol family
10533 14:45:28.772657 <6>[ 2.144712] 9pnet: Installing 9P2000 support
10534 14:45:28.778589 <5>[ 2.149271] Key type dns_resolver registered
10535 14:45:28.781947 <6>[ 2.154310] registered taskstats version 1
10536 14:45:28.788510 <5>[ 2.158686] Loading compiled-in X.509 certificates
10537 14:45:28.820328 <4>[ 2.183980] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10538 14:45:28.830385 <4>[ 2.194803] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10539 14:45:28.845437 <6>[ 2.216138] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10540 14:45:28.852206 <6>[ 2.223122] xhci-mtk 11200000.usb: xHCI Host Controller
10541 14:45:28.858563 <6>[ 2.228625] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10542 14:45:28.869196 <6>[ 2.236488] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10543 14:45:28.875434 <6>[ 2.245938] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10544 14:45:28.882091 <6>[ 2.252041] xhci-mtk 11200000.usb: xHCI Host Controller
10545 14:45:28.888819 <6>[ 2.257541] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10546 14:45:28.895379 <6>[ 2.265309] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10547 14:45:28.902546 <6>[ 2.273201] hub 1-0:1.0: USB hub found
10548 14:45:28.905369 <6>[ 2.277231] hub 1-0:1.0: 1 port detected
10549 14:45:28.915637 <6>[ 2.281540] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10550 14:45:28.918808 <6>[ 2.290313] hub 2-0:1.0: USB hub found
10551 14:45:28.921946 <6>[ 2.294338] hub 2-0:1.0: 1 port detected
10552 14:45:28.930491 <6>[ 2.301373] mtk-msdc 11f70000.mmc: Got CD GPIO
10553 14:45:28.943375 <6>[ 2.310930] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10554 14:45:28.950207 <6>[ 2.318963] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10555 14:45:28.960359 <4>[ 2.326880] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10556 14:45:28.969562 <6>[ 2.336447] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10557 14:45:28.976663 <6>[ 2.344525] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10558 14:45:28.983399 <6>[ 2.352538] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10559 14:45:28.992831 <6>[ 2.360455] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10560 14:45:28.999805 <6>[ 2.368272] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10561 14:45:29.009386 <6>[ 2.376089] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10562 14:45:29.019525 <6>[ 2.386520] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10563 14:45:29.026220 <6>[ 2.394888] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10564 14:45:29.036020 <6>[ 2.403232] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10565 14:45:29.042759 <6>[ 2.411570] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10566 14:45:29.052590 <6>[ 2.419908] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10567 14:45:29.059018 <6>[ 2.428246] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10568 14:45:29.068902 <6>[ 2.436584] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10569 14:45:29.078944 <6>[ 2.444922] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10570 14:45:29.085422 <6>[ 2.453259] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10571 14:45:29.095637 <6>[ 2.461598] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10572 14:45:29.102544 <6>[ 2.469936] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10573 14:45:29.112224 <6>[ 2.478273] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10574 14:45:29.118923 <6>[ 2.486614] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10575 14:45:29.128720 <6>[ 2.494952] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10576 14:45:29.135922 <6>[ 2.503301] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10577 14:45:29.142198 <6>[ 2.512042] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10578 14:45:29.148630 <6>[ 2.519198] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10579 14:45:29.155654 <6>[ 2.525971] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10580 14:45:29.165223 <6>[ 2.532718] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10581 14:45:29.172017 <6>[ 2.539662] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10582 14:45:29.178423 <6>[ 2.546507] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10583 14:45:29.188589 <6>[ 2.555640] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10584 14:45:29.198580 <6>[ 2.564761] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10585 14:45:29.208464 <6>[ 2.574056] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10586 14:45:29.218112 <6>[ 2.583524] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10587 14:45:29.224415 <6>[ 2.592990] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10588 14:45:29.234571 <6>[ 2.602110] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10589 14:45:29.244147 <6>[ 2.611577] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10590 14:45:29.254130 <6>[ 2.620696] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10591 14:45:29.264154 <6>[ 2.629990] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10592 14:45:29.273855 <6>[ 2.640162] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10593 14:45:29.284299 <6>[ 2.651681] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10594 14:45:29.335208 <6>[ 2.702792] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10595 14:45:29.489802 <6>[ 2.860681] hub 1-1:1.0: USB hub found
10596 14:45:29.493527 <6>[ 2.865211] hub 1-1:1.0: 4 ports detected
10597 14:45:29.503222 <6>[ 2.874057] hub 1-1:1.0: USB hub found
10598 14:45:29.506693 <6>[ 2.878385] hub 1-1:1.0: 4 ports detected
10599 14:45:29.616207 <6>[ 2.983122] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10600 14:45:29.642688 <6>[ 3.013003] hub 2-1:1.0: USB hub found
10601 14:45:29.645616 <6>[ 3.017527] hub 2-1:1.0: 3 ports detected
10602 14:45:29.655215 <6>[ 3.025542] hub 2-1:1.0: USB hub found
10603 14:45:29.658029 <6>[ 3.030068] hub 2-1:1.0: 3 ports detected
10604 14:45:29.831606 <6>[ 3.198823] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10605 14:45:29.964001 <6>[ 3.334311] hub 1-1.4:1.0: USB hub found
10606 14:45:29.966927 <6>[ 3.338939] hub 1-1.4:1.0: 2 ports detected
10607 14:45:29.976240 <6>[ 3.347089] hub 1-1.4:1.0: USB hub found
10608 14:45:29.979594 <6>[ 3.351640] hub 1-1.4:1.0: 2 ports detected
10609 14:45:30.047680 <6>[ 3.414930] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10610 14:45:30.156001 <6>[ 3.523263] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10611 14:45:30.192194 <4>[ 3.559626] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10612 14:45:30.201717 <4>[ 3.568713] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10613 14:45:30.241488 <6>[ 3.612326] r8152 2-1.3:1.0 eth0: v1.12.13
10614 14:45:30.280017 <6>[ 3.646844] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10615 14:45:30.471319 <6>[ 3.838649] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10616 14:45:31.831804 <6>[ 5.203285] r8152 2-1.3:1.0 eth0: carrier on
10617 14:45:34.571142 <5>[ 5.230631] Sending DHCP requests .., OK
10618 14:45:34.577654 <6>[ 7.947061] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10619 14:45:34.580837 <6>[ 7.955410] IP-Config: Complete:
10620 14:45:34.594329 <6>[ 7.958914] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10621 14:45:34.600894 <6>[ 7.969651] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10622 14:45:34.610504 <6>[ 7.978272] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10623 14:45:34.614073 <6>[ 7.978281] nameserver0=192.168.201.1
10624 14:45:34.617497 <6>[ 7.990454] clk: Disabling unused clocks
10625 14:45:34.621067 <6>[ 7.995932] ALSA device list:
10626 14:45:34.627752 <6>[ 7.999183] No soundcards found.
10627 14:45:34.635912 <6>[ 8.007053] Freeing unused kernel memory: 8512K
10628 14:45:34.638649 <6>[ 8.012020] Run /init as init process
10629 14:45:34.671107 Starting syslogd: OK
10630 14:45:34.676133 Starting klogd: OK
10631 14:45:34.685979 Running sysctl: OK
10632 14:45:34.695681 Populating /dev using udev: <30>[ 8.065969] udevd[200]: starting version 3.2.9
10633 14:45:34.703346 <27>[ 8.074948] udevd[200]: specified user 'tss' unknown
10634 14:45:34.709746 <27>[ 8.080448] udevd[200]: specified group 'tss' unknown
10635 14:45:34.713329 <30>[ 8.086905] udevd[201]: starting eudev-3.2.9
10636 14:45:34.736263 <27>[ 8.108126] udevd[201]: specified user 'tss' unknown
10637 14:45:34.743104 <27>[ 8.113540] udevd[201]: specified group 'tss' unknown
10638 14:45:34.838677 <6>[ 8.207380] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10639 14:45:34.849727 <6>[ 8.221014] remoteproc remoteproc0: scp is available
10640 14:45:34.856074 <6>[ 8.226931] remoteproc remoteproc0: powering up scp
10641 14:45:34.865641 <6>[ 8.232898] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10642 14:45:34.872580 <6>[ 8.242098] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10643 14:45:34.899675 <6>[ 8.267823] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10644 14:45:34.906103 <6>[ 8.275553] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10645 14:45:34.915826 <6>[ 8.284297] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10646 14:45:34.922851 <6>[ 8.294061] mc: Linux media interface: v0.10
10647 14:45:34.950015 <3>[ 8.318208] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10648 14:45:34.956204 <3>[ 8.326340] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10649 14:45:34.966645 <3>[ 8.334445] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10650 14:45:34.969665 <6>[ 8.336187] Bluetooth: Core ver 2.22
10651 14:45:34.976037 <6>[ 8.338595] videodev: Linux video capture interface: v2.00
10652 14:45:34.983451 <3>[ 8.342633] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10653 14:45:34.989285 <6>[ 8.346872] NET: Registered PF_BLUETOOTH protocol family
10654 14:45:34.995978 <3>[ 8.352107] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10655 14:45:35.006409 <3>[ 8.352111] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10656 14:45:35.012681 <6>[ 8.365117] Bluetooth: HCI device and connection manager initialized
10657 14:45:35.019684 <3>[ 8.365771] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10658 14:45:35.026080 <6>[ 8.374054] Bluetooth: HCI socket layer initialized
10659 14:45:35.032693 <4>[ 8.375579] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10660 14:45:35.039263 <4>[ 8.377476] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10661 14:45:35.049392 <6>[ 8.378679] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10662 14:45:35.056203 <6>[ 8.378687] remoteproc remoteproc0: remote processor scp is now up
10663 14:45:35.062260 <6>[ 8.378696] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10664 14:45:35.069019 <3>[ 8.381916] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10665 14:45:35.076538 <6>[ 8.382366] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10666 14:45:35.086145 <3>[ 8.394813] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10667 14:45:35.089388 <6>[ 8.400170] Bluetooth: L2CAP socket layer initialized
10668 14:45:35.099681 <3>[ 8.402732] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10669 14:45:35.103455 <6>[ 8.409148] Bluetooth: SCO socket layer initialized
10670 14:45:35.113481 <3>[ 8.416380] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10671 14:45:35.119880 <6>[ 8.419956] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10672 14:45:35.126162 <6>[ 8.419964] pci_bus 0000:00: root bus resource [bus 00-ff]
10673 14:45:35.133231 <6>[ 8.419970] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10674 14:45:35.142893 <6>[ 8.419975] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10675 14:45:35.149717 <6>[ 8.420271] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10676 14:45:35.155918 <6>[ 8.420292] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10677 14:45:35.159561 <6>[ 8.420387] pci 0000:00:00.0: supports D1 D2
10678 14:45:35.166106 <6>[ 8.420391] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10679 14:45:35.175979 <6>[ 8.422570] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10680 14:45:35.182538 <6>[ 8.422745] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10681 14:45:35.189291 <6>[ 8.422780] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10682 14:45:35.195795 <6>[ 8.422889] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10683 14:45:35.202346 <6>[ 8.422908] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10684 14:45:35.208845 <6>[ 8.423065] pci 0000:01:00.0: supports D1 D2
10685 14:45:35.215494 <6>[ 8.423072] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10686 14:45:35.225820 <4>[ 8.429101] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10687 14:45:35.228794 <4>[ 8.429101] Fallback method does not support PEC.
10688 14:45:35.235767 <3>[ 8.431368] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10689 14:45:35.245622 <3>[ 8.431506] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10690 14:45:35.251926 <6>[ 8.438656] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10691 14:45:35.258517 <3>[ 8.446595] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10692 14:45:35.268375 <6>[ 8.454277] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10693 14:45:35.278172 <3>[ 8.455491] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10694 14:45:35.285216 <3>[ 8.462318] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10695 14:45:35.291380 <6>[ 8.467630] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10696 14:45:35.301423 <3>[ 8.475703] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10697 14:45:35.307851 <3>[ 8.475708] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10698 14:45:35.318024 <6>[ 8.476782] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10699 14:45:35.324868 <3>[ 8.477849] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10700 14:45:35.334399 <6>[ 8.478843] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10701 14:45:35.340950 <6>[ 8.480853] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10702 14:45:35.350936 <3>[ 8.488935] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10703 14:45:35.360651 <6>[ 8.493103] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10704 14:45:35.367348 <6>[ 8.495890] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10705 14:45:35.377484 <6>[ 8.511506] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10706 14:45:35.387406 <6>[ 8.518618] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10707 14:45:35.393905 <6>[ 8.525261] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10708 14:45:35.400792 <6>[ 8.532354] pci 0000:00:00.0: PCI bridge to [bus 01]
10709 14:45:35.406946 <6>[ 8.567525] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10710 14:45:35.413951 <6>[ 8.573174] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10711 14:45:35.427107 <6>[ 8.582185] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10712 14:45:35.433536 <6>[ 8.585336] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10713 14:45:35.440342 <6>[ 8.592286] usbcore: registered new interface driver uvcvideo
10714 14:45:35.446785 <6>[ 8.592764] usbcore: registered new interface driver btusb
10715 14:45:35.453488 <6>[ 8.593690] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10716 14:45:35.462884 <4>[ 8.593760] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10717 14:45:35.469964 <3>[ 8.593770] Bluetooth: hci0: Failed to load firmware file (-2)
10718 14:45:35.473052 <3>[ 8.593774] Bluetooth: hci0: Failed to set up firmware (-2)
10719 14:45:35.486062 <4>[ 8.593777] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10720 14:45:35.489480 <6>[ 8.606223] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10721 14:45:35.497490 <6>[ 8.868717] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10722 14:45:35.516085 <5>[ 8.884243] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10723 14:45:35.545627 <5>[ 8.914151] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10724 14:45:35.552726 <5>[ 8.921646] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10725 14:45:35.562500 <4>[ 8.930101] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10726 14:45:35.568987 <6>[ 8.939004] cfg80211: failed to load regulatory.db
10727 14:45:35.616947 <6>[ 8.985471] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10728 14:45:35.623457 <6>[ 8.993004] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10729 14:45:35.647746 <6>[ 9.019738] mt7921e 0000:01:00.0: ASIC revision: 79610010
10730 14:45:35.750337 <6>[ 9.118794] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10731 14:45:35.753282 <6>[ 9.118794]
10732 14:45:35.756953 done
10733 14:45:35.765429 Saving random seed: OK
10734 14:45:35.777211 Starting network: ip: RTNETLINK answers: File exists
10735 14:45:35.780562 FAIL
10736 14:45:35.817587 Starting dropbear sshd: <6>[ 9.189193] NET: Registered PF_INET6 protocol family
10737 14:45:35.824620 <6>[ 9.196521] Segment Routing with IPv6
10738 14:45:35.827801 <6>[ 9.200467] In-situ OAM (IOAM) with IPv6
10739 14:45:35.831701 OK
10740 14:45:35.841451 /bin/sh: can't access tty; job control turned off
10741 14:45:35.841797 Matched prompt #10: / #
10743 14:45:35.842149 Setting prompt string to ['/ #']
10744 14:45:35.842242 end: 2.2.5.1 login-action (duration 00:00:10) [common]
10746 14:45:35.842470 end: 2.2.5 auto-login-action (duration 00:00:10) [common]
10747 14:45:35.842559 start: 2.2.6 expect-shell-connection (timeout 00:03:30) [common]
10748 14:45:35.842629 Setting prompt string to ['/ #']
10749 14:45:35.842689 Forcing a shell prompt, looking for ['/ #']
10751 14:45:35.892924 / #
10752 14:45:35.893091 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10753 14:45:35.893208 Waiting using forced prompt support (timeout 00:02:30)
10754 14:45:35.898324
10755 14:45:35.898600 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10756 14:45:35.898696 start: 2.2.7 export-device-env (timeout 00:03:30) [common]
10757 14:45:35.898787 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10758 14:45:35.898872 end: 2.2 depthcharge-retry (duration 00:01:30) [common]
10759 14:45:35.898954 end: 2 depthcharge-action (duration 00:01:30) [common]
10760 14:45:35.899038 start: 3 lava-test-retry (timeout 00:01:00) [common]
10761 14:45:35.899121 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10762 14:45:35.899195 Using namespace: common
10764 14:45:35.999531 / # #
10765 14:45:35.999706 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10766 14:45:36.005109 #
10767 14:45:36.005402 Using /lava-14167015
10769 14:45:36.105758 / # export SHELL=/bin/sh
10770 14:45:36.105978 <6>[ 9.390203] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10771 14:45:36.111097 export SHELL=/bin/sh
10773 14:45:36.211641 / # . /lava-14167015/environment
10774 14:45:36.217435 . /lava-14167015/environment
10776 14:45:36.317990 / # /lava-14167015/bin/lava-test-runner /lava-14167015/0
10777 14:45:36.318141 Test shell timeout: 10s (minimum of the action and connection timeout)
10778 14:45:36.323759 /lava-14167015/bin/lava-test-runner /lava-14167015/0
10779 14:45:36.342452 + export 'TESTRUN_ID=0_dmesg'
10780 14:45:36.349138 +<8>[ 9.720117] <LAVA_SIGNAL_STARTRUN 0_dmesg 14167015_1.5.2.3.1>
10781 14:45:36.349425 Received signal: <STARTRUN> 0_dmesg 14167015_1.5.2.3.1
10782 14:45:36.349501 Starting test lava.0_dmesg (14167015_1.5.2.3.1)
10783 14:45:36.349582 Skipping test definition patterns.
10784 14:45:36.352191 cd /lava-14167015/0/tests/0_dmesg
10785 14:45:36.352292 + cat uuid
10786 14:45:36.355686 + UUID=14167015_1.5.2.3.1
10787 14:45:36.355769 + set +x
10788 14:45:36.362032 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10789 14:45:36.372405 <8>[ 9.739686] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10790 14:45:36.372661 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10792 14:45:36.390837 <8>[ 9.759111] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10793 14:45:36.391095 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10795 14:45:36.413664 <8>[ 9.782041] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10796 14:45:36.413921 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10798 14:45:36.416848 + set +x
10799 14:45:36.420054 <8>[ 9.791599] <LAVA_SIGNAL_ENDRUN 0_dmesg 14167015_1.5.2.3.1>
10800 14:45:36.420307 Received signal: <ENDRUN> 0_dmesg 14167015_1.5.2.3.1
10801 14:45:36.420385 Ending use of test pattern.
10802 14:45:36.420447 Ending test lava.0_dmesg (14167015_1.5.2.3.1), duration 0.07
10804 14:45:36.424024 <LAVA_TEST_RUNNER EXIT>
10805 14:45:36.424276 ok: lava_test_shell seems to have completed
10806 14:45:36.424378 alert: pass
crit: pass
emerg: pass
10807 14:45:36.424465 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10808 14:45:36.424549 end: 3 lava-test-retry (duration 00:00:01) [common]
10809 14:45:36.424634 start: 4 finalize (timeout 00:08:11) [common]
10810 14:45:36.424720 start: 4.1 power-off (timeout 00:00:30) [common]
10811 14:45:36.424867 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
10812 14:45:36.622053 >> Command sent successfully.
10813 14:45:36.624362 Returned 0 in 0 seconds
10814 14:45:36.724787 end: 4.1 power-off (duration 00:00:00) [common]
10816 14:45:36.725128 start: 4.2 read-feedback (timeout 00:08:11) [common]
10817 14:45:36.725440 Listened to connection for namespace 'common' for up to 1s
10818 14:45:37.725660 Finalising connection for namespace 'common'
10819 14:45:37.726330 Disconnecting from shell: Finalise
10820 14:45:37.726753 / #
10821 14:45:37.827561 end: 4.2 read-feedback (duration 00:00:01) [common]
10822 14:45:37.827769 end: 4 finalize (duration 00:00:01) [common]
10823 14:45:37.827930 Cleaning after the job
10824 14:45:37.828065 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167015/tftp-deploy-r735clyv/ramdisk
10825 14:45:37.830905 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167015/tftp-deploy-r735clyv/kernel
10826 14:45:37.840994 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167015/tftp-deploy-r735clyv/dtb
10827 14:45:37.841231 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167015/tftp-deploy-r735clyv/modules
10828 14:45:37.848836 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14167015
10829 14:45:37.894239 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14167015
10830 14:45:37.894397 Job finished correctly