Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 0
- Kernel Errors: 41
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 86
1 14:43:30.593943 lava-dispatcher, installed at version: 2024.03
2 14:43:30.594242 start: 0 validate
3 14:43:30.594443 Start time: 2024-06-04 14:43:30.594434+00:00 (UTC)
4 14:43:30.594635 Using caching service: 'http://localhost/cache/?uri=%s'
5 14:43:30.594843 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 14:43:30.854181 Using caching service: 'http://localhost/cache/?uri=%s'
7 14:43:30.854439 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 14:43:45.118780 Using caching service: 'http://localhost/cache/?uri=%s'
9 14:43:45.119759 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 14:43:45.383594 Using caching service: 'http://localhost/cache/?uri=%s'
11 14:43:45.384284 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 14:43:48.139505 validate duration: 17.55
14 14:43:48.139797 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 14:43:48.139917 start: 1.1 download-retry (timeout 00:10:00) [common]
16 14:43:48.140024 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 14:43:48.140173 Not decompressing ramdisk as can be used compressed.
18 14:43:48.140323 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 14:43:48.140455 saving as /var/lib/lava/dispatcher/tmp/14166985/tftp-deploy-pirxnrnz/ramdisk/rootfs.cpio.gz
20 14:43:48.140564 total size: 47897469 (45 MB)
21 14:43:48.397446 progress 0 % (0 MB)
22 14:43:48.419908 progress 5 % (2 MB)
23 14:43:48.439771 progress 10 % (4 MB)
24 14:43:48.453283 progress 15 % (6 MB)
25 14:43:48.466920 progress 20 % (9 MB)
26 14:43:48.480652 progress 25 % (11 MB)
27 14:43:48.495174 progress 30 % (13 MB)
28 14:43:48.509734 progress 35 % (16 MB)
29 14:43:48.523981 progress 40 % (18 MB)
30 14:43:48.538314 progress 45 % (20 MB)
31 14:43:48.552534 progress 50 % (22 MB)
32 14:43:48.566916 progress 55 % (25 MB)
33 14:43:48.581467 progress 60 % (27 MB)
34 14:43:48.595252 progress 65 % (29 MB)
35 14:43:48.609599 progress 70 % (32 MB)
36 14:43:48.623933 progress 75 % (34 MB)
37 14:43:48.638394 progress 80 % (36 MB)
38 14:43:48.652631 progress 85 % (38 MB)
39 14:43:48.667382 progress 90 % (41 MB)
40 14:43:48.681603 progress 95 % (43 MB)
41 14:43:48.695593 progress 100 % (45 MB)
42 14:43:48.695895 45 MB downloaded in 0.56 s (82.25 MB/s)
43 14:43:48.696080 end: 1.1.1 http-download (duration 00:00:01) [common]
45 14:43:48.696363 end: 1.1 download-retry (duration 00:00:01) [common]
46 14:43:48.696459 start: 1.2 download-retry (timeout 00:09:59) [common]
47 14:43:48.696553 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 14:43:48.696713 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 14:43:48.696793 saving as /var/lib/lava/dispatcher/tmp/14166985/tftp-deploy-pirxnrnz/kernel/Image
50 14:43:48.696861 total size: 54682112 (52 MB)
51 14:43:48.696939 No compression specified
52 14:43:48.698145 progress 0 % (0 MB)
53 14:43:48.713544 progress 5 % (2 MB)
54 14:43:48.728907 progress 10 % (5 MB)
55 14:43:48.744222 progress 15 % (7 MB)
56 14:43:48.759503 progress 20 % (10 MB)
57 14:43:48.774819 progress 25 % (13 MB)
58 14:43:48.789956 progress 30 % (15 MB)
59 14:43:48.805270 progress 35 % (18 MB)
60 14:43:48.820537 progress 40 % (20 MB)
61 14:43:48.835999 progress 45 % (23 MB)
62 14:43:48.851956 progress 50 % (26 MB)
63 14:43:48.867482 progress 55 % (28 MB)
64 14:43:48.882871 progress 60 % (31 MB)
65 14:43:48.898603 progress 65 % (33 MB)
66 14:43:48.914943 progress 70 % (36 MB)
67 14:43:48.931127 progress 75 % (39 MB)
68 14:43:48.948156 progress 80 % (41 MB)
69 14:43:48.965205 progress 85 % (44 MB)
70 14:43:48.982737 progress 90 % (46 MB)
71 14:43:48.999182 progress 95 % (49 MB)
72 14:43:49.015863 progress 100 % (52 MB)
73 14:43:49.016183 52 MB downloaded in 0.32 s (163.31 MB/s)
74 14:43:49.016425 end: 1.2.1 http-download (duration 00:00:00) [common]
76 14:43:49.016726 end: 1.2 download-retry (duration 00:00:00) [common]
77 14:43:49.016836 start: 1.3 download-retry (timeout 00:09:59) [common]
78 14:43:49.016939 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 14:43:49.017097 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
80 14:43:49.017188 saving as /var/lib/lava/dispatcher/tmp/14166985/tftp-deploy-pirxnrnz/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
81 14:43:49.017256 total size: 57695 (0 MB)
82 14:43:49.017330 No compression specified
83 14:43:49.018601 progress 56 % (0 MB)
84 14:43:49.018984 progress 100 % (0 MB)
85 14:43:49.019239 0 MB downloaded in 0.00 s (27.79 MB/s)
86 14:43:49.019386 end: 1.3.1 http-download (duration 00:00:00) [common]
88 14:43:49.019674 end: 1.3 download-retry (duration 00:00:00) [common]
89 14:43:49.019784 start: 1.4 download-retry (timeout 00:09:59) [common]
90 14:43:49.019889 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 14:43:49.020016 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 14:43:49.020102 saving as /var/lib/lava/dispatcher/tmp/14166985/tftp-deploy-pirxnrnz/modules/modules.tar
93 14:43:49.020177 total size: 8608920 (8 MB)
94 14:43:49.020255 Using unxz to decompress xz
95 14:43:49.024668 progress 0 % (0 MB)
96 14:43:49.045608 progress 5 % (0 MB)
97 14:43:49.075893 progress 10 % (0 MB)
98 14:43:49.109410 progress 15 % (1 MB)
99 14:43:49.136050 progress 20 % (1 MB)
100 14:43:49.162960 progress 25 % (2 MB)
101 14:43:49.190208 progress 30 % (2 MB)
102 14:43:49.217963 progress 35 % (2 MB)
103 14:43:49.248646 progress 40 % (3 MB)
104 14:43:49.275785 progress 45 % (3 MB)
105 14:43:49.303185 progress 50 % (4 MB)
106 14:43:49.332066 progress 55 % (4 MB)
107 14:43:49.362058 progress 60 % (4 MB)
108 14:43:49.391447 progress 65 % (5 MB)
109 14:43:49.421814 progress 70 % (5 MB)
110 14:43:49.453757 progress 75 % (6 MB)
111 14:43:49.486224 progress 80 % (6 MB)
112 14:43:49.515736 progress 85 % (7 MB)
113 14:43:49.545791 progress 90 % (7 MB)
114 14:43:49.575592 progress 95 % (7 MB)
115 14:43:49.604202 progress 100 % (8 MB)
116 14:43:49.610485 8 MB downloaded in 0.59 s (13.91 MB/s)
117 14:43:49.610757 end: 1.4.1 http-download (duration 00:00:01) [common]
119 14:43:49.611057 end: 1.4 download-retry (duration 00:00:01) [common]
120 14:43:49.611161 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 14:43:49.611265 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 14:43:49.611356 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 14:43:49.611464 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 14:43:49.611709 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx
125 14:43:49.611859 makedir: /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/bin
126 14:43:49.611975 makedir: /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/tests
127 14:43:49.612085 makedir: /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/results
128 14:43:49.612213 Creating /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/bin/lava-add-keys
129 14:43:49.612370 Creating /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/bin/lava-add-sources
130 14:43:49.612517 Creating /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/bin/lava-background-process-start
131 14:43:49.612664 Creating /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/bin/lava-background-process-stop
132 14:43:49.612803 Creating /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/bin/lava-common-functions
133 14:43:49.612939 Creating /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/bin/lava-echo-ipv4
134 14:43:49.613078 Creating /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/bin/lava-install-packages
135 14:43:49.613216 Creating /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/bin/lava-installed-packages
136 14:43:49.613353 Creating /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/bin/lava-os-build
137 14:43:49.613489 Creating /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/bin/lava-probe-channel
138 14:43:49.613624 Creating /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/bin/lava-probe-ip
139 14:43:49.613759 Creating /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/bin/lava-target-ip
140 14:43:49.613895 Creating /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/bin/lava-target-mac
141 14:43:49.614030 Creating /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/bin/lava-target-storage
142 14:43:49.614171 Creating /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/bin/lava-test-case
143 14:43:49.614306 Creating /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/bin/lava-test-event
144 14:43:49.614441 Creating /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/bin/lava-test-feedback
145 14:43:49.614578 Creating /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/bin/lava-test-raise
146 14:43:49.614714 Creating /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/bin/lava-test-reference
147 14:43:49.614848 Creating /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/bin/lava-test-runner
148 14:43:49.614983 Creating /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/bin/lava-test-set
149 14:43:49.615121 Creating /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/bin/lava-test-shell
150 14:43:49.615261 Updating /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/bin/lava-install-packages (oe)
151 14:43:49.615432 Updating /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/bin/lava-installed-packages (oe)
152 14:43:49.615565 Creating /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/environment
153 14:43:49.615676 LAVA metadata
154 14:43:49.615755 - LAVA_JOB_ID=14166985
155 14:43:49.615825 - LAVA_DISPATCHER_IP=192.168.201.1
156 14:43:49.615941 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 14:43:49.616016 skipped lava-vland-overlay
158 14:43:49.616099 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 14:43:49.616192 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 14:43:49.616275 skipped lava-multinode-overlay
161 14:43:49.616356 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 14:43:49.616452 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 14:43:49.616533 Loading test definitions
164 14:43:49.616635 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 14:43:49.616723 Using /lava-14166985 at stage 0
166 14:43:49.617067 uuid=14166985_1.5.2.3.1 testdef=None
167 14:43:49.617165 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 14:43:49.617258 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 14:43:49.617836 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 14:43:49.618090 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 14:43:49.618781 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 14:43:49.619041 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 14:43:49.619712 runner path: /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/0/tests/0_igt-gpu-panfrost test_uuid 14166985_1.5.2.3.1
176 14:43:49.619887 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 14:43:49.620120 Creating lava-test-runner.conf files
179 14:43:49.620192 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14166985/lava-overlay-balmmegx/lava-14166985/0 for stage 0
180 14:43:49.620291 - 0_igt-gpu-panfrost
181 14:43:49.620407 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 14:43:49.620503 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 14:43:49.628418 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 14:43:49.628545 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 14:43:49.628643 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 14:43:49.628739 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 14:43:49.628836 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 14:43:51.578770 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 14:43:51.579284 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 14:43:51.579470 extracting modules file /var/lib/lava/dispatcher/tmp/14166985/tftp-deploy-pirxnrnz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14166985/extract-overlay-ramdisk-40eym1c_/ramdisk
191 14:43:51.834416 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 14:43:51.834606 start: 1.5.5 apply-overlay-tftp (timeout 00:09:56) [common]
193 14:43:51.834710 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14166985/compress-overlay-00vrc23b/overlay-1.5.2.4.tar.gz to ramdisk
194 14:43:51.834792 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14166985/compress-overlay-00vrc23b/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14166985/extract-overlay-ramdisk-40eym1c_/ramdisk
195 14:43:51.842095 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 14:43:51.842225 start: 1.5.6 configure-preseed-file (timeout 00:09:56) [common]
197 14:43:51.842323 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 14:43:51.842423 start: 1.5.7 compress-ramdisk (timeout 00:09:56) [common]
199 14:43:51.842511 Building ramdisk /var/lib/lava/dispatcher/tmp/14166985/extract-overlay-ramdisk-40eym1c_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14166985/extract-overlay-ramdisk-40eym1c_/ramdisk
200 14:43:53.148731 >> 465919 blocks
201 14:44:00.105429 rename /var/lib/lava/dispatcher/tmp/14166985/extract-overlay-ramdisk-40eym1c_/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14166985/tftp-deploy-pirxnrnz/ramdisk/ramdisk.cpio.gz
202 14:44:00.105937 end: 1.5.7 compress-ramdisk (duration 00:00:08) [common]
203 14:44:00.106097 start: 1.5.8 prepare-kernel (timeout 00:09:48) [common]
204 14:44:00.106231 start: 1.5.8.1 prepare-fit (timeout 00:09:48) [common]
205 14:44:00.106373 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14166985/tftp-deploy-pirxnrnz/kernel/Image']
206 14:44:15.041341 Returned 0 in 14 seconds
207 14:44:15.142011 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14166985/tftp-deploy-pirxnrnz/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14166985/tftp-deploy-pirxnrnz/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14166985/tftp-deploy-pirxnrnz/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14166985/tftp-deploy-pirxnrnz/kernel/image.itb
208 14:44:16.053054 output: FIT description: Kernel Image image with one or more FDT blobs
209 14:44:16.053470 output: Created: Tue Jun 4 15:44:15 2024
210 14:44:16.053555 output: Image 0 (kernel-1)
211 14:44:16.053629 output: Description:
212 14:44:16.053703 output: Created: Tue Jun 4 15:44:15 2024
213 14:44:16.053772 output: Type: Kernel Image
214 14:44:16.053839 output: Compression: lzma compressed
215 14:44:16.053905 output: Data Size: 13060619 Bytes = 12754.51 KiB = 12.46 MiB
216 14:44:16.053972 output: Architecture: AArch64
217 14:44:16.054037 output: OS: Linux
218 14:44:16.054101 output: Load Address: 0x00000000
219 14:44:16.054163 output: Entry Point: 0x00000000
220 14:44:16.054228 output: Hash algo: crc32
221 14:44:16.054292 output: Hash value: 88dcd836
222 14:44:16.054359 output: Image 1 (fdt-1)
223 14:44:16.054423 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
224 14:44:16.054488 output: Created: Tue Jun 4 15:44:15 2024
225 14:44:16.054554 output: Type: Flat Device Tree
226 14:44:16.054615 output: Compression: uncompressed
227 14:44:16.054676 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
228 14:44:16.054738 output: Architecture: AArch64
229 14:44:16.054799 output: Hash algo: crc32
230 14:44:16.054859 output: Hash value: a9713552
231 14:44:16.054919 output: Image 2 (ramdisk-1)
232 14:44:16.054980 output: Description: unavailable
233 14:44:16.055040 output: Created: Tue Jun 4 15:44:15 2024
234 14:44:16.055101 output: Type: RAMDisk Image
235 14:44:16.055161 output: Compression: Unknown Compression
236 14:44:16.055221 output: Data Size: 61002412 Bytes = 59572.67 KiB = 58.18 MiB
237 14:44:16.055283 output: Architecture: AArch64
238 14:44:16.055343 output: OS: Linux
239 14:44:16.055415 output: Load Address: unavailable
240 14:44:16.055485 output: Entry Point: unavailable
241 14:44:16.055546 output: Hash algo: crc32
242 14:44:16.055607 output: Hash value: f5b57485
243 14:44:16.055668 output: Default Configuration: 'conf-1'
244 14:44:16.055728 output: Configuration 0 (conf-1)
245 14:44:16.055788 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
246 14:44:16.055850 output: Kernel: kernel-1
247 14:44:16.055910 output: Init Ramdisk: ramdisk-1
248 14:44:16.055971 output: FDT: fdt-1
249 14:44:16.056031 output: Loadables: kernel-1
250 14:44:16.056092 output:
251 14:44:16.056315 end: 1.5.8.1 prepare-fit (duration 00:00:16) [common]
252 14:44:16.056423 end: 1.5.8 prepare-kernel (duration 00:00:16) [common]
253 14:44:16.056541 end: 1.5 prepare-tftp-overlay (duration 00:00:26) [common]
254 14:44:16.056648 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:32) [common]
255 14:44:16.056735 No LXC device requested
256 14:44:16.056824 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 14:44:16.056918 start: 1.7 deploy-device-env (timeout 00:09:32) [common]
258 14:44:16.057007 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 14:44:16.057082 Checking files for TFTP limit of 4294967296 bytes.
260 14:44:16.057636 end: 1 tftp-deploy (duration 00:00:28) [common]
261 14:44:16.057768 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 14:44:16.057895 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 14:44:16.058052 substitutions:
264 14:44:16.058136 - {DTB}: 14166985/tftp-deploy-pirxnrnz/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
265 14:44:16.058230 - {INITRD}: 14166985/tftp-deploy-pirxnrnz/ramdisk/ramdisk.cpio.gz
266 14:44:16.058320 - {KERNEL}: 14166985/tftp-deploy-pirxnrnz/kernel/Image
267 14:44:16.058408 - {LAVA_MAC}: None
268 14:44:16.058518 - {PRESEED_CONFIG}: None
269 14:44:16.058628 - {PRESEED_LOCAL}: None
270 14:44:16.058736 - {RAMDISK}: 14166985/tftp-deploy-pirxnrnz/ramdisk/ramdisk.cpio.gz
271 14:44:16.058845 - {ROOT_PART}: None
272 14:44:16.058953 - {ROOT}: None
273 14:44:16.059060 - {SERVER_IP}: 192.168.201.1
274 14:44:16.059167 - {TEE}: None
275 14:44:16.059274 Parsed boot commands:
276 14:44:16.059379 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 14:44:16.059652 Parsed boot commands: tftpboot 192.168.201.1 14166985/tftp-deploy-pirxnrnz/kernel/image.itb 14166985/tftp-deploy-pirxnrnz/kernel/cmdline
278 14:44:16.059796 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 14:44:16.059941 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 14:44:16.060094 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 14:44:16.060241 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 14:44:16.060364 Not connected, no need to disconnect.
283 14:44:16.060497 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 14:44:16.060633 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 14:44:16.060752 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-0'
286 14:44:16.064839 Setting prompt string to ['lava-test: # ']
287 14:44:16.065311 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 14:44:16.065451 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 14:44:16.065584 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 14:44:16.065704 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 14:44:16.065925 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8183-kukui-jacuzzi-juniper-sku16-cbg-0']
292 14:44:40.155885 Returned 0 in 24 seconds
293 14:44:40.256561 end: 2.2.2.1 pdu-reboot (duration 00:00:24) [common]
295 14:44:40.257219 end: 2.2.2 reset-device (duration 00:00:24) [common]
296 14:44:40.257352 start: 2.2.3 depthcharge-start (timeout 00:04:36) [common]
297 14:44:40.257462 Setting prompt string to 'Starting depthcharge on Juniper...'
298 14:44:40.257548 Changing prompt to 'Starting depthcharge on Juniper...'
299 14:44:40.257650 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
300 14:44:40.258118 [Enter `^Ec?' for help]
301 14:44:40.258217 [DL] 00000000 00000000 010701
302 14:44:40.258336
303 14:44:40.258459
304 14:44:40.258575 F0: 102B 0000
305 14:44:40.258692
306 14:44:40.258804 F3: 1006 0033 [0200]
307 14:44:40.258917
308 14:44:40.259031 F3: 4001 00E0 [0200]
309 14:44:40.259140
310 14:44:40.259247 F3: 0000 0000
311 14:44:40.259355
312 14:44:40.259472 V0: 0000 0000 [0001]
313 14:44:40.259581
314 14:44:40.259687 00: 1027 0002
315 14:44:40.259800
316 14:44:40.259907 01: 0000 0000
317 14:44:40.260016
318 14:44:40.260122 BP: 0C00 0251 [0000]
319 14:44:40.260228
320 14:44:40.260334 G0: 1182 0000
321 14:44:40.260441
322 14:44:40.260547 EC: 0004 0000 [0001]
323 14:44:40.260652
324 14:44:40.260758 S7: 0000 0000 [0000]
325 14:44:40.260864
326 14:44:40.260969 CC: 0000 0000 [0001]
327 14:44:40.261073
328 14:44:40.261178 T0: 0000 00DB [000F]
329 14:44:40.261283
330 14:44:40.261388 Jump to BL
331 14:44:40.261493
332 14:44:40.261598
333 14:44:40.261703
334 14:44:40.261801 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
335 14:44:40.261912 ARM64: Exception handlers installed.
336 14:44:40.262020 ARM64: Testing exception
337 14:44:40.262127 ARM64: Done test exception
338 14:44:40.262233 WDT: Last reset was cold boot
339 14:44:40.262339 SPI0(PAD0) initialized at 992727 Hz
340 14:44:40.262445 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
341 14:44:40.262552 Manufacturer: ef
342 14:44:40.262658 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
343 14:44:40.262764 Probing TPM: . done!
344 14:44:40.262869 TPM ready after 0 ms
345 14:44:40.262975 Connected to device vid:did:rid of 1ae0:0028:00
346 14:44:40.263082 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1dd676c
347 14:44:40.263189 Initialized TPM device CR50 revision 0
348 14:44:40.263296 tlcl_send_startup: Startup return code is 0
349 14:44:40.263402 TPM: setup succeeded
350 14:44:40.263515 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
351 14:44:40.263623 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
352 14:44:40.263731 in-header: 03 19 00 00 08 00 00 00
353 14:44:40.263837 in-data: a2 e0 47 00 13 00 00 00
354 14:44:40.263943 Chrome EC: UHEPI supported
355 14:44:40.264049 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
356 14:44:40.264156 in-header: 03 a1 00 00 08 00 00 00
357 14:44:40.264261 in-data: 84 60 60 10 00 00 00 00
358 14:44:40.264366 Phase 1
359 14:44:40.264472 FMAP: area GBB found @ 3f5000 (12032 bytes)
360 14:44:40.264579 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
361 14:44:40.264686 VB2:vb2_check_recovery() Recovery was requested manually
362 14:44:40.264792 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
363 14:44:40.264898 Recovery requested (1009000e)
364 14:44:40.265003 tlcl_extend: response is 0
365 14:44:40.265109 tlcl_extend: response is 0
366 14:44:40.265214
367 14:44:40.265319
368 14:44:40.265424 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
369 14:44:40.265531 ARM64: Exception handlers installed.
370 14:44:40.265636 ARM64: Testing exception
371 14:44:40.265741 ARM64: Done test exception
372 14:44:40.265847 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0xc268, sec=0x2038
373 14:44:40.265953 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
374 14:44:40.266058 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
375 14:44:40.266164 [RTC]rtc_get_frequency_meter,134: input=0xf, output=915
376 14:44:40.266270 [RTC]rtc_get_frequency_meter,134: input=0x7, output=777
377 14:44:40.266375 [RTC]rtc_get_frequency_meter,134: input=0xb, output=848
378 14:44:40.266480 [RTC]rtc_get_frequency_meter,134: input=0x9, output=815
379 14:44:40.266585 [RTC]rtc_get_frequency_meter,134: input=0x8, output=796
380 14:44:40.266689 [RTC]rtc_osc_init,208: EOSC32 cali val = 0xc268
381 14:44:40.266793 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
382 14:44:40.266898 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
383 14:44:40.267003 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
384 14:44:40.267107 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
385 14:44:40.267213 in-header: 03 19 00 00 08 00 00 00
386 14:44:40.267318 in-data: a2 e0 47 00 13 00 00 00
387 14:44:40.267430 Chrome EC: UHEPI supported
388 14:44:40.267537 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
389 14:44:40.267644 in-header: 03 a1 00 00 08 00 00 00
390 14:44:40.267750 in-data: 84 60 60 10 00 00 00 00
391 14:44:40.267856 Skip loading cached calibration data
392 14:44:40.267961 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
393 14:44:40.268067 in-header: 03 a1 00 00 08 00 00 00
394 14:44:40.268173 in-data: 84 60 60 10 00 00 00 00
395 14:44:40.268278 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
396 14:44:40.268385 in-header: 03 a1 00 00 08 00 00 00
397 14:44:40.268490 in-data: 84 60 60 10 00 00 00 00
398 14:44:40.268596 ADC[3]: Raw value=216571 ID=1
399 14:44:40.268701 Manufacturer: ef
400 14:44:40.268806 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
401 14:44:40.268912 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
402 14:44:40.269018 CBFS @ 21000 size 3d4000
403 14:44:40.269124 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
404 14:44:40.269229 CBFS: Locating 'sdram-lpddr4x-H9HCNNNCPMALHR-4GB'
405 14:44:40.269335 CBFS: Found @ offset 3c700 size 44
406 14:44:40.269440 DRAM-K: Full Calibration
407 14:44:40.269545 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
408 14:44:40.269651 CBFS @ 21000 size 3d4000
409 14:44:40.269756 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
410 14:44:40.269861 CBFS: Locating 'fallback/dram'
411 14:44:40.269966 CBFS: Found @ offset 24b00 size 12268
412 14:44:40.270071 read SPI 0x45b44 0x1224c: 22774 us, 3263 KB/s, 26.104 Mbps
413 14:44:40.270177 ddr_geometry: 1, config: 0x0
414 14:44:40.270282 header.status = 0x0
415 14:44:40.270387 header.magic = 0x44524d4b (expected: 0x44524d4b)
416 14:44:40.270492 header.version = 0x5 (expected: 0x5)
417 14:44:40.270598 header.size = 0x8f0 (expected: 0x8f0)
418 14:44:40.270703 header.config = 0x0
419 14:44:40.270807 header.flags = 0x0
420 14:44:40.270912 header.checksum = 0x0
421 14:44:40.271215 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
422 14:44:40.271323 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
423 14:44:40.271441 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
424 14:44:40.271550 ddr_geometry:1
425 14:44:40.271658 [EMI] new MDL number = 1
426 14:44:40.271766 dram_cbt_mode_extern: 0
427 14:44:40.271872 dram_cbt_mode [RK0]: 0, [RK1]: 0
428 14:44:40.271978 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
429 14:44:40.272084
430 14:44:40.272191
431 14:44:40.272297 [Bianco] ETT version 0.0.0.1
432 14:44:40.272403 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
433 14:44:40.272510
434 14:44:40.272616 vSetVcoreByFreq with vcore:762500, freq=1600
435 14:44:40.272726
436 14:44:40.272831 [DramcInit]
437 14:44:40.272937 AutoRefreshCKEOff AutoREF OFF
438 14:44:40.273043 DDRPhyPLLSetting-CKEOFF
439 14:44:40.273149 DDRPhyPLLSetting-CKEON
440 14:44:40.273254
441 14:44:40.273360 Enable WDQS
442 14:44:40.273465 [ModeRegInit_LP4] CH0 RK0
443 14:44:40.273571 Write Rank0 MR13 =0x18
444 14:44:40.273677 Write Rank0 MR12 =0x5d
445 14:44:40.273782 Write Rank0 MR1 =0x56
446 14:44:40.273887 Write Rank0 MR2 =0x1a
447 14:44:40.273992 Write Rank0 MR11 =0x0
448 14:44:40.274097 Write Rank0 MR22 =0x38
449 14:44:40.274202 Write Rank0 MR14 =0x5d
450 14:44:40.274306 Write Rank0 MR3 =0x30
451 14:44:40.274410 Write Rank0 MR13 =0x58
452 14:44:40.274515 Write Rank0 MR12 =0x5d
453 14:44:40.274619 Write Rank0 MR1 =0x56
454 14:44:40.274723 Write Rank0 MR2 =0x2d
455 14:44:40.274828 Write Rank0 MR11 =0x23
456 14:44:40.274933 Write Rank0 MR22 =0x34
457 14:44:40.275037 Write Rank0 MR14 =0x10
458 14:44:40.275141 Write Rank0 MR3 =0x30
459 14:44:40.275245 Write Rank0 MR13 =0xd8
460 14:44:40.275349 [ModeRegInit_LP4] CH0 RK1
461 14:44:40.275474 Write Rank1 MR13 =0x18
462 14:44:40.275583 Write Rank1 MR12 =0x5d
463 14:44:40.275689 Write Rank1 MR1 =0x56
464 14:44:40.275795 Write Rank1 MR2 =0x1a
465 14:44:40.275901 Write Rank1 MR11 =0x0
466 14:44:40.276006 Write Rank1 MR22 =0x38
467 14:44:40.276112 Write Rank1 MR14 =0x5d
468 14:44:40.276218 Write Rank1 MR3 =0x30
469 14:44:40.276323 Write Rank1 MR13 =0x58
470 14:44:40.276428 Write Rank1 MR12 =0x5d
471 14:44:40.276533 Write Rank1 MR1 =0x56
472 14:44:40.276638 Write Rank1 MR2 =0x2d
473 14:44:40.276743 Write Rank1 MR11 =0x23
474 14:44:40.276849 Write Rank1 MR22 =0x34
475 14:44:40.276954 Write Rank1 MR14 =0x10
476 14:44:40.277064 Write Rank1 MR3 =0x30
477 14:44:40.277170 Write Rank1 MR13 =0xd8
478 14:44:40.277275 [ModeRegInit_LP4] CH1 RK0
479 14:44:40.277380 Write Rank0 MR13 =0x18
480 14:44:40.277484 Write Rank0 MR12 =0x5d
481 14:44:40.277589 Write Rank0 MR1 =0x56
482 14:44:40.277693 Write Rank0 MR2 =0x1a
483 14:44:40.277797 Write Rank0 MR11 =0x0
484 14:44:40.277902 Write Rank0 MR22 =0x38
485 14:44:40.278007 Write Rank0 MR14 =0x5d
486 14:44:40.278112 Write Rank0 MR3 =0x30
487 14:44:40.278216 Write Rank0 MR13 =0x58
488 14:44:40.278320 Write Rank0 MR12 =0x5d
489 14:44:40.278425 Write Rank0 MR1 =0x56
490 14:44:40.278529 Write Rank0 MR2 =0x2d
491 14:44:40.278633 Write Rank0 MR11 =0x23
492 14:44:40.278737 Write Rank0 MR22 =0x34
493 14:44:40.278842 Write Rank0 MR14 =0x10
494 14:44:40.278946 Write Rank0 MR3 =0x30
495 14:44:40.279050 Write Rank0 MR13 =0xd8
496 14:44:40.279155 [ModeRegInit_LP4] CH1 RK1
497 14:44:40.279259 Write Rank1 MR13 =0x18
498 14:44:40.279364 Write Rank1 MR12 =0x5d
499 14:44:40.279475 Write Rank1 MR1 =0x56
500 14:44:40.279581 Write Rank1 MR2 =0x1a
501 14:44:40.279687 Write Rank1 MR11 =0x0
502 14:44:40.279792 Write Rank1 MR22 =0x38
503 14:44:40.279896 Write Rank1 MR14 =0x5d
504 14:44:40.280001 Write Rank1 MR3 =0x30
505 14:44:40.280106 Write Rank1 MR13 =0x58
506 14:44:40.280210 Write Rank1 MR12 =0x5d
507 14:44:40.280314 Write Rank1 MR1 =0x56
508 14:44:40.280419 Write Rank1 MR2 =0x2d
509 14:44:40.280522 Write Rank1 MR11 =0x23
510 14:44:40.280627 Write Rank1 MR22 =0x34
511 14:44:40.280731 Write Rank1 MR14 =0x10
512 14:44:40.280835 Write Rank1 MR3 =0x30
513 14:44:40.280940 Write Rank1 MR13 =0xd8
514 14:44:40.281045 match AC timing 3
515 14:44:40.281151 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
516 14:44:40.281258 [MiockJmeterHQA]
517 14:44:40.281363 vSetVcoreByFreq with vcore:762500, freq=1600
518 14:44:40.281469
519 14:44:40.281574 MIOCK jitter meter ch=0
520 14:44:40.281679
521 14:44:40.281785 1T = (102-17) = 85 dly cells
522 14:44:40.281894 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 735/100 ps
523 14:44:40.282000 vSetVcoreByFreq with vcore:725000, freq=1200
524 14:44:40.282106
525 14:44:40.282211 MIOCK jitter meter ch=0
526 14:44:40.282317
527 14:44:40.282422 1T = (96-16) = 80 dly cells
528 14:44:40.282531 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 781/100 ps
529 14:44:40.282637 vSetVcoreByFreq with vcore:725000, freq=800
530 14:44:40.282744
531 14:44:40.282850 MIOCK jitter meter ch=0
532 14:44:40.282956
533 14:44:40.283061 1T = (96-16) = 80 dly cells
534 14:44:40.283170 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 781/100 ps
535 14:44:40.283276 vSetVcoreByFreq with vcore:762500, freq=1600
536 14:44:40.283382 vSetVcoreByFreq with vcore:762500, freq=1600
537 14:44:40.283494
538 14:44:40.283600 K DRVP
539 14:44:40.283705 1. OCD DRVP=0 CALOUT=0
540 14:44:40.283814 1. OCD DRVP=1 CALOUT=0
541 14:44:40.283922 1. OCD DRVP=2 CALOUT=0
542 14:44:40.284030 1. OCD DRVP=3 CALOUT=0
543 14:44:40.284138 1. OCD DRVP=4 CALOUT=0
544 14:44:40.284246 1. OCD DRVP=5 CALOUT=0
545 14:44:40.284353 1. OCD DRVP=6 CALOUT=0
546 14:44:40.284460 1. OCD DRVP=7 CALOUT=0
547 14:44:40.284568 1. OCD DRVP=8 CALOUT=0
548 14:44:40.284674 1. OCD DRVP=9 CALOUT=1
549 14:44:40.284781
550 14:44:40.284886 1. OCD DRVP calibration OK! DRVP=9
551 14:44:40.284994
552 14:44:40.285100
553 14:44:40.285204
554 14:44:40.285308 K ODTN
555 14:44:40.285413 3. OCD ODTN=0 ,CALOUT=1
556 14:44:40.285521 3. OCD ODTN=1 ,CALOUT=1
557 14:44:40.285628 3. OCD ODTN=2 ,CALOUT=1
558 14:44:40.285735 3. OCD ODTN=3 ,CALOUT=1
559 14:44:40.285842 3. OCD ODTN=4 ,CALOUT=1
560 14:44:40.285950 3. OCD ODTN=5 ,CALOUT=1
561 14:44:40.286057 3. OCD ODTN=6 ,CALOUT=1
562 14:44:40.286164 3. OCD ODTN=7 ,CALOUT=0
563 14:44:40.286271
564 14:44:40.286376 3. OCD ODTN calibration OK! ODTN=7
565 14:44:40.286484
566 14:44:40.286589 [SwImpedanceCal] DRVP=9, DRVN=9, ODTN=7
567 14:44:40.286695 term_option=0, Reg: DRVP=9, DRVN=7, ODTN=15
568 14:44:40.286801 term_option=0, Reg: DRVP=9, DRVN=7, ODTN=15 (After Adjust)
569 14:44:40.286907
570 14:44:40.287013 K DRVP
571 14:44:40.287119 1. OCD DRVP=0 CALOUT=0
572 14:44:40.287227 1. OCD DRVP=1 CALOUT=0
573 14:44:40.287336 1. OCD DRVP=2 CALOUT=0
574 14:44:40.287453 1. OCD DRVP=3 CALOUT=0
575 14:44:40.287561 1. OCD DRVP=4 CALOUT=0
576 14:44:40.287669 1. OCD DRVP=5 CALOUT=0
577 14:44:40.287776 1. OCD DRVP=6 CALOUT=0
578 14:44:40.287884 1. OCD DRVP=7 CALOUT=0
579 14:44:40.287991 1. OCD DRVP=8 CALOUT=0
580 14:44:40.288098 1. OCD DRVP=9 CALOUT=0
581 14:44:40.288206 1. OCD DRVP=10 CALOUT=0
582 14:44:40.288312 1. OCD DRVP=11 CALOUT=1
583 14:44:40.288420
584 14:44:40.288524 1. OCD DRVP calibration OK! DRVP=11
585 14:44:40.288632
586 14:44:40.288736
587 14:44:40.288840
588 14:44:40.288944 K ODTN
589 14:44:40.289049 3. OCD ODTN=0 ,CALOUT=1
590 14:44:40.289350 3. OCD ODTN=1 ,CALOUT=1
591 14:44:40.289463 3. OCD ODTN=2 ,CALOUT=1
592 14:44:40.289575 3. OCD ODTN=3 ,CALOUT=1
593 14:44:40.289685 3. OCD ODTN=4 ,CALOUT=1
594 14:44:40.289794 3. OCD ODTN=5 ,CALOUT=1
595 14:44:40.289903 3. OCD ODTN=6 ,CALOUT=1
596 14:44:40.290011 3. OCD ODTN=7 ,CALOUT=1
597 14:44:40.290122 3. OCD ODTN=8 ,CALOUT=1
598 14:44:40.290231 3. OCD ODTN=9 ,CALOUT=1
599 14:44:40.290340 3. OCD ODTN=10 ,CALOUT=1
600 14:44:40.290448 3. OCD ODTN=11 ,CALOUT=1
601 14:44:40.290556 3. OCD ODTN=12 ,CALOUT=1
602 14:44:40.290664 3. OCD ODTN=13 ,CALOUT=1
603 14:44:40.290772 3. OCD ODTN=14 ,CALOUT=1
604 14:44:40.290880 3. OCD ODTN=15 ,CALOUT=0
605 14:44:40.290988
606 14:44:40.291094 3. OCD ODTN calibration OK! ODTN=15
607 14:44:40.291203
608 14:44:40.291308 [SwImpedanceCal] DRVP=11, DRVN=9, ODTN=15
609 14:44:40.291425 term_option=1, Reg: DRVP=11, DRVN=9, ODTN=15
610 14:44:40.291534 term_option=1, Reg: DRVP=11, DRVN=9, ODTN=15 (After Adjust)
611 14:44:40.291641
612 14:44:40.291747 [DramcInit]
613 14:44:40.291854 AutoRefreshCKEOff AutoREF OFF
614 14:44:40.291959 DDRPhyPLLSetting-CKEOFF
615 14:44:40.292065 DDRPhyPLLSetting-CKEON
616 14:44:40.292170
617 14:44:40.292275 Enable WDQS
618 14:44:40.292380 ==
619 14:44:40.292485 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
620 14:44:40.292591 fsp= 1, odt_onoff= 1, Byte mode= 0
621 14:44:40.292698 ==
622 14:44:40.292804 [Duty_Offset_Calibration]
623 14:44:40.292909
624 14:44:40.293014 ===========================
625 14:44:40.293120 B0:1 B1:1 CA:1
626 14:44:40.293225 ==
627 14:44:40.293331 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
628 14:44:40.293436 fsp= 1, odt_onoff= 1, Byte mode= 0
629 14:44:40.293542 ==
630 14:44:40.293648 [Duty_Offset_Calibration]
631 14:44:40.293753
632 14:44:40.293859 ===========================
633 14:44:40.293968 B0:1 B1:0 CA:2
634 14:44:40.294074 [ModeRegInit_LP4] CH0 RK0
635 14:44:40.294180 Write Rank0 MR13 =0x18
636 14:44:40.294286 Write Rank0 MR12 =0x5d
637 14:44:40.294391 Write Rank0 MR1 =0x56
638 14:44:40.294496 Write Rank0 MR2 =0x1a
639 14:44:40.294602 Write Rank0 MR11 =0x0
640 14:44:40.294707 Write Rank0 MR22 =0x38
641 14:44:40.294813 Write Rank0 MR14 =0x5d
642 14:44:40.294918 Write Rank0 MR3 =0x30
643 14:44:40.295023 Write Rank0 MR13 =0x58
644 14:44:40.295128 Write Rank0 MR12 =0x5d
645 14:44:40.295235 Write Rank0 MR1 =0x56
646 14:44:40.295340 Write Rank0 MR2 =0x2d
647 14:44:40.295451 Write Rank0 MR11 =0x23
648 14:44:40.295557 Write Rank0 MR22 =0x34
649 14:44:40.295661 Write Rank0 MR14 =0x10
650 14:44:40.295766 Write Rank0 MR3 =0x30
651 14:44:40.295870 Write Rank0 MR13 =0xd8
652 14:44:40.295975 [ModeRegInit_LP4] CH0 RK1
653 14:44:40.296080 Write Rank1 MR13 =0x18
654 14:44:40.296184 Write Rank1 MR12 =0x5d
655 14:44:40.296289 Write Rank1 MR1 =0x56
656 14:44:40.296393 Write Rank1 MR2 =0x1a
657 14:44:40.296497 Write Rank1 MR11 =0x0
658 14:44:40.296601 Write Rank1 MR22 =0x38
659 14:44:40.296705 Write Rank1 MR14 =0x5d
660 14:44:40.296810 Write Rank1 MR3 =0x30
661 14:44:40.296914 Write Rank1 MR13 =0x58
662 14:44:40.297019 Write Rank1 MR12 =0x5d
663 14:44:40.297123 Write Rank1 MR1 =0x56
664 14:44:40.297228 Write Rank1 MR2 =0x2d
665 14:44:40.297332 Write Rank1 MR11 =0x23
666 14:44:40.297437 Write Rank1 MR22 =0x34
667 14:44:40.297541 Write Rank1 MR14 =0x10
668 14:44:40.297645 Write Rank1 MR3 =0x30
669 14:44:40.297749 Write Rank1 MR13 =0xd8
670 14:44:40.297853 [ModeRegInit_LP4] CH1 RK0
671 14:44:40.297958 Write Rank0 MR13 =0x18
672 14:44:40.298062 Write Rank0 MR12 =0x5d
673 14:44:40.298166 Write Rank0 MR1 =0x56
674 14:44:40.298270 Write Rank0 MR2 =0x1a
675 14:44:40.298374 Write Rank0 MR11 =0x0
676 14:44:40.298479 Write Rank0 MR22 =0x38
677 14:44:40.298583 Write Rank0 MR14 =0x5d
678 14:44:40.298687 Write Rank0 MR3 =0x30
679 14:44:40.298791 Write Rank0 MR13 =0x58
680 14:44:40.298895 Write Rank0 MR12 =0x5d
681 14:44:40.299000 Write Rank0 MR1 =0x56
682 14:44:40.299104 Write Rank0 MR2 =0x2d
683 14:44:40.299208 Write Rank0 MR11 =0x23
684 14:44:40.299312 Write Rank0 MR22 =0x34
685 14:44:40.299423 Write Rank0 MR14 =0x10
686 14:44:40.299507 Write Rank0 MR3 =0x30
687 14:44:40.299591 Write Rank0 MR13 =0xd8
688 14:44:40.299674 [ModeRegInit_LP4] CH1 RK1
689 14:44:40.299758 Write Rank1 MR13 =0x18
690 14:44:40.299862 Write Rank1 MR12 =0x5d
691 14:44:40.299967 Write Rank1 MR1 =0x56
692 14:44:40.300072 Write Rank1 MR2 =0x1a
693 14:44:40.300176 Write Rank1 MR11 =0x0
694 14:44:40.300280 Write Rank1 MR22 =0x38
695 14:44:40.300384 Write Rank1 MR14 =0x5d
696 14:44:40.300489 Write Rank1 MR3 =0x30
697 14:44:40.300593 Write Rank1 MR13 =0x58
698 14:44:40.300697 Write Rank1 MR12 =0x5d
699 14:44:40.300802 Write Rank1 MR1 =0x56
700 14:44:40.300906 Write Rank1 MR2 =0x2d
701 14:44:40.301010 Write Rank1 MR11 =0x23
702 14:44:40.301115 Write Rank1 MR22 =0x34
703 14:44:40.301219 Write Rank1 MR14 =0x10
704 14:44:40.301323 Write Rank1 MR3 =0x30
705 14:44:40.301427 Write Rank1 MR13 =0xd8
706 14:44:40.301531 match AC timing 3
707 14:44:40.301636 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
708 14:44:40.301741 DramC Write-DBI off
709 14:44:40.301846 DramC Read-DBI off
710 14:44:40.301950 Write Rank0 MR13 =0x59
711 14:44:40.302054 ==
712 14:44:40.302161 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
713 14:44:40.302267 fsp= 1, odt_onoff= 1, Byte mode= 0
714 14:44:40.302373 ==
715 14:44:40.302478 === u2Vref_new: 0x56 --> 0x2d
716 14:44:40.302585 === u2Vref_new: 0x58 --> 0x38
717 14:44:40.302691 === u2Vref_new: 0x5a --> 0x39
718 14:44:40.302796 === u2Vref_new: 0x5c --> 0x3c
719 14:44:40.302901 === u2Vref_new: 0x5e --> 0x3d
720 14:44:40.303006 === u2Vref_new: 0x60 --> 0xa0
721 14:44:40.303111 [CA 0] Center 34 (6~63) winsize 58
722 14:44:40.303216 [CA 1] Center 36 (9~63) winsize 55
723 14:44:40.303321 [CA 2] Center 29 (0~58) winsize 59
724 14:44:40.303433 [CA 3] Center 24 (-3~52) winsize 56
725 14:44:40.303540 [CA 4] Center 25 (-3~54) winsize 58
726 14:44:40.303646 [CA 5] Center 30 (0~60) winsize 61
727 14:44:40.303751
728 14:44:40.303856 [CATrainingPosCal] consider 1 rank data
729 14:44:40.303962 u2DelayCellTimex100 = 735/100 ps
730 14:44:40.304068 CA0 delay=34 (6~63),Diff = 10 PI (13 cell)
731 14:44:40.304174 CA1 delay=36 (9~63),Diff = 12 PI (15 cell)
732 14:44:40.304279 CA2 delay=29 (0~58),Diff = 5 PI (6 cell)
733 14:44:40.304384 CA3 delay=24 (-3~52),Diff = 0 PI (0 cell)
734 14:44:40.304489 CA4 delay=25 (-3~54),Diff = 1 PI (1 cell)
735 14:44:40.304595 CA5 delay=30 (0~60),Diff = 6 PI (7 cell)
736 14:44:40.304700
737 14:44:40.304805 CA PerBit enable=1, Macro0, CA PI delay=24
738 14:44:40.304910 === u2Vref_new: 0x5e --> 0x3d
739 14:44:40.305016
740 14:44:40.305121 Vref(ca) range 1: 30
741 14:44:40.305226
742 14:44:40.305331 CS Dly= 9 (40-0-32)
743 14:44:40.305436 Write Rank0 MR13 =0xd8
744 14:44:40.305541 Write Rank0 MR13 =0xd8
745 14:44:40.305646 Write Rank0 MR12 =0x5e
746 14:44:40.305750 Write Rank1 MR13 =0x59
747 14:44:40.305855 ==
748 14:44:40.305960 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
749 14:44:40.306275 fsp= 1, odt_onoff= 1, Byte mode= 0
750 14:44:40.306382 ==
751 14:44:40.306491 === u2Vref_new: 0x56 --> 0x2d
752 14:44:40.306599 === u2Vref_new: 0x58 --> 0x38
753 14:44:40.306707 === u2Vref_new: 0x5a --> 0x39
754 14:44:40.306814 === u2Vref_new: 0x5c --> 0x3c
755 14:44:40.306921 === u2Vref_new: 0x5e --> 0x3d
756 14:44:40.307027 === u2Vref_new: 0x60 --> 0xa0
757 14:44:40.307133 [CA 0] Center 36 (9~63) winsize 55
758 14:44:40.307239 [CA 1] Center 36 (9~63) winsize 55
759 14:44:40.307345 [CA 2] Center 31 (2~60) winsize 59
760 14:44:40.307464 [CA 3] Center 26 (-2~54) winsize 57
761 14:44:40.307571 [CA 4] Center 26 (-2~54) winsize 57
762 14:44:40.307676 [CA 5] Center 31 (2~61) winsize 60
763 14:44:40.307782
764 14:44:40.307887 [CATrainingPosCal] consider 2 rank data
765 14:44:40.307992 u2DelayCellTimex100 = 735/100 ps
766 14:44:40.308097 CA0 delay=36 (9~63),Diff = 11 PI (14 cell)
767 14:44:40.308203 CA1 delay=36 (9~63),Diff = 11 PI (14 cell)
768 14:44:40.308309 CA2 delay=30 (2~58),Diff = 5 PI (6 cell)
769 14:44:40.308414 CA3 delay=25 (-2~52),Diff = 0 PI (0 cell)
770 14:44:40.308519 CA4 delay=26 (-2~54),Diff = 1 PI (1 cell)
771 14:44:40.308625 CA5 delay=31 (2~60),Diff = 6 PI (7 cell)
772 14:44:40.308729
773 14:44:40.308835 CA PerBit enable=1, Macro0, CA PI delay=25
774 14:44:40.308940 === u2Vref_new: 0x5c --> 0x3c
775 14:44:40.309045
776 14:44:40.309151 Vref(ca) range 1: 28
777 14:44:40.309255
778 14:44:40.309360 CS Dly= 7 (38-0-32)
779 14:44:40.309465 Write Rank1 MR13 =0xd8
780 14:44:40.309570 Write Rank1 MR13 =0xd8
781 14:44:40.309674 Write Rank1 MR12 =0x5c
782 14:44:40.309779 [RankSwap] Rank num 2, (Multi 1), Rank 0
783 14:44:40.309884 Write Rank0 MR2 =0xad
784 14:44:40.309989 [Write Leveling]
785 14:44:40.310093 delay byte0 byte1 byte2 byte3
786 14:44:40.310198
787 14:44:40.310303 10 0 0
788 14:44:40.310410 11 0 0
789 14:44:40.310518 12 0 0
790 14:44:40.310625 13 0 0
791 14:44:40.310732 14 0 0
792 14:44:40.310838 15 0 0
793 14:44:40.310945 16 0 0
794 14:44:40.311051 17 0 0
795 14:44:40.311158 18 0 0
796 14:44:40.311264 19 0 0
797 14:44:40.311371 20 0 0
798 14:44:40.311485 21 0 0
799 14:44:40.311593 22 0 0
800 14:44:40.311700 23 0 ff
801 14:44:40.311807 24 0 ff
802 14:44:40.311914 25 0 ff
803 14:44:40.312021 26 0 ff
804 14:44:40.312128 27 0 ff
805 14:44:40.312234 28 0 ff
806 14:44:40.312342 29 0 ff
807 14:44:40.312449 30 0 ff
808 14:44:40.312555 31 0 ff
809 14:44:40.312662 32 ff ff
810 14:44:40.312768 33 ff ff
811 14:44:40.312875 34 ff ff
812 14:44:40.312981 35 ff ff
813 14:44:40.313090 36 ff ff
814 14:44:40.313196 37 ff ff
815 14:44:40.313302 38 ff ff
816 14:44:40.313409 pass bytecount = 0xff (0xff: all bytes pass)
817 14:44:40.313514
818 14:44:40.313620 DQS0 dly: 32
819 14:44:40.313725 DQS1 dly: 23
820 14:44:40.313829 Write Rank0 MR2 =0x2d
821 14:44:40.313935 [RankSwap] Rank num 2, (Multi 1), Rank 0
822 14:44:40.314040 Write Rank0 MR1 =0xd6
823 14:44:40.314145 [Gating]
824 14:44:40.314250 ==
825 14:44:40.314355 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
826 14:44:40.314461 fsp= 1, odt_onoff= 1, Byte mode= 0
827 14:44:40.314567 ==
828 14:44:40.314672 3 1 0 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
829 14:44:40.314780 3 1 4 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
830 14:44:40.314888 3 1 8 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
831 14:44:40.314996 3 1 12 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
832 14:44:40.315104 3 1 16 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
833 14:44:40.315212 3 1 20 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
834 14:44:40.315319 3 1 24 |1313 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
835 14:44:40.315435 3 1 28 |201 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
836 14:44:40.315544 3 2 0 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
837 14:44:40.315652 3 2 4 |3534 403 |(11 11)(11 11) |(0 0)(1 1)| 0
838 14:44:40.315760 3 2 8 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
839 14:44:40.315868 3 2 12 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
840 14:44:40.315977 3 2 16 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
841 14:44:40.316084 3 2 20 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
842 14:44:40.316192 3 2 24 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
843 14:44:40.316304 3 2 28 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
844 14:44:40.316415 3 3 0 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
845 14:44:40.316523 3 3 4 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
846 14:44:40.316631 3 3 8 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
847 14:44:40.316741 [Byte 1] Lead/lag falling Transition (3, 3, 8)
848 14:44:40.316847 3 3 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
849 14:44:40.316955 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
850 14:44:40.317062 3 3 20 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
851 14:44:40.317170 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
852 14:44:40.317277 3 3 28 |403 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
853 14:44:40.317385 3 4 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
854 14:44:40.317491 3 4 4 |3d3d c0c |(11 11)(11 11) |(1 1)(1 1)| 0
855 14:44:40.317599 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
856 14:44:40.317706 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
857 14:44:40.317814 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
858 14:44:40.317921 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
859 14:44:40.318028 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
860 14:44:40.318135 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
861 14:44:40.318243 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
862 14:44:40.318350 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
863 14:44:40.318458 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
864 14:44:40.318565 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
865 14:44:40.318672 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
866 14:44:40.318780 [Byte 0] Lead/lag falling Transition (3, 5, 16)
867 14:44:40.318885 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
868 14:44:40.318992 3 5 24 |2221 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
869 14:44:40.319100 [Byte 0] Lead/lag Transition tap number (3)
870 14:44:40.319205 [Byte 1] Lead/lag falling Transition (3, 5, 24)
871 14:44:40.319310 3 5 28 |4646 3d3d |(0 0)(11 11) |(0 0)(1 0)| 0
872 14:44:40.319428 [Byte 0]First pass (3, 5, 28)
873 14:44:40.319737 [Byte 1] Lead/lag Transition tap number (2)
874 14:44:40.319846 3 6 0 |4646 3e3d |(0 0)(11 11) |(0 0)(0 0)| 0
875 14:44:40.319936 3 6 4 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
876 14:44:40.320024 3 6 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
877 14:44:40.320111 [Byte 1]First pass (3, 6, 8)
878 14:44:40.320218 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
879 14:44:40.320328 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
880 14:44:40.320414 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
881 14:44:40.320523 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
882 14:44:40.320632 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
883 14:44:40.320741 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
884 14:44:40.320849 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
885 14:44:40.320958 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
886 14:44:40.321066 All bytes gating window > 1UI, Early break!
887 14:44:40.321172
888 14:44:40.321278 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 22)
889 14:44:40.321384
890 14:44:40.321489 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 28)
891 14:44:40.321595
892 14:44:40.321700
893 14:44:40.321804
894 14:44:40.321909 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 22)
895 14:44:40.322015
896 14:44:40.322120 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 28)
897 14:44:40.322226
898 14:44:40.322330
899 14:44:40.322435 Write Rank0 MR1 =0x56
900 14:44:40.322539
901 14:44:40.322644 best RODT dly(2T, 0.5T) = (2, 2)
902 14:44:40.322749
903 14:44:40.322854 best RODT dly(2T, 0.5T) = (2, 2)
904 14:44:40.322959 ==
905 14:44:40.323064 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
906 14:44:40.323170 fsp= 1, odt_onoff= 1, Byte mode= 0
907 14:44:40.323275 ==
908 14:44:40.323381 Start DQ dly to find pass range UseTestEngine =0
909 14:44:40.323495 x-axis: bit #, y-axis: DQ dly (-127~63)
910 14:44:40.323603 RX Vref Scan = 0
911 14:44:40.323708 -26, [0] xxxxxxxx xxxxxxxx [MSB]
912 14:44:40.323817 -25, [0] xxxxxxxx xxxxxxxx [MSB]
913 14:44:40.323926 -24, [0] xxxxxxxx xxxxxxxx [MSB]
914 14:44:40.324034 -23, [0] xxxxxxxx xxxxxxxx [MSB]
915 14:44:40.324142 -22, [0] xxxxxxxx xxxxxxxx [MSB]
916 14:44:40.324250 -21, [0] xxxxxxxx xxxxxxxx [MSB]
917 14:44:40.324357 -20, [0] xxxxxxxx xxxxxxxx [MSB]
918 14:44:40.324464 -19, [0] xxxxxxxx xxxxxxxx [MSB]
919 14:44:40.324571 -18, [0] xxxxxxxx xxxxxxxx [MSB]
920 14:44:40.324678 -17, [0] xxxxxxxx xxxxxxxx [MSB]
921 14:44:40.324784 -16, [0] xxxxxxxx xxxxxxxx [MSB]
922 14:44:40.324891 -15, [0] xxxxxxxx xxxxxxxx [MSB]
923 14:44:40.324999 -14, [0] xxxxxxxx xxxxxxxx [MSB]
924 14:44:40.325105 -13, [0] xxxxxxxx xxxxxxxx [MSB]
925 14:44:40.325212 -12, [0] xxxxxxxx xxxxxxxx [MSB]
926 14:44:40.325319 -11, [0] xxxxxxxx xxxxxxxx [MSB]
927 14:44:40.325426 -10, [0] xxxxxxxx xxxxxxxx [MSB]
928 14:44:40.325533 -9, [0] xxxxxxxx xxxxxxxx [MSB]
929 14:44:40.325639 -8, [0] xxxxxxxx xxxxxxxx [MSB]
930 14:44:40.325747 -7, [0] xxxxxxxx xxxxxxxx [MSB]
931 14:44:40.325854 -6, [0] xxxxxxxx xxxxxxxx [MSB]
932 14:44:40.325961 -5, [0] xxxxxxxx xxxxxxxx [MSB]
933 14:44:40.326068 -4, [0] xxxxxxxx xxxxxxxx [MSB]
934 14:44:40.326174 -3, [0] xxxxxxxx oxxxxxxx [MSB]
935 14:44:40.326281 -2, [0] xxxoxxxx oxxxxxxx [MSB]
936 14:44:40.326387 -1, [0] xxxoxxxx oxxxxxxx [MSB]
937 14:44:40.326493 0, [0] xxxoxoxx ooxoxxxx [MSB]
938 14:44:40.326600 1, [0] xxxoxoox ooxoooxx [MSB]
939 14:44:40.326706 2, [0] xxxoxoox ooxoooxx [MSB]
940 14:44:40.326813 3, [0] xxxoxoox ooxoooxx [MSB]
941 14:44:40.326919 4, [0] xxxoxooo ooxoooox [MSB]
942 14:44:40.327027 5, [0] xooooooo ooxooooo [MSB]
943 14:44:40.327137 6, [0] xooooooo ooxooooo [MSB]
944 14:44:40.327243 7, [0] oooooooo ooxooooo [MSB]
945 14:44:40.327350 32, [0] oooxoooo oooooooo [MSB]
946 14:44:40.327464 33, [0] oooxoooo xooooooo [MSB]
947 14:44:40.327572 34, [0] oooxoooo xooooooo [MSB]
948 14:44:40.327681 35, [0] oooxoxoo xooooooo [MSB]
949 14:44:40.327789 36, [0] oooxoxoo xooxoooo [MSB]
950 14:44:40.327896 37, [0] oooxoxxx xxoxoooo [MSB]
951 14:44:40.328003 38, [0] oooxoxxx xxoxxoxo [MSB]
952 14:44:40.328110 39, [0] oooxxxxx xxoxxxxo [MSB]
953 14:44:40.328216 40, [0] xooxxxxx xxoxxxxo [MSB]
954 14:44:40.328323 41, [0] xxxxxxxx xxoxxxxo [MSB]
955 14:44:40.328429 42, [0] xxxxxxxx xxoxxxxx [MSB]
956 14:44:40.328536 43, [0] xxxxxxxx xxoxxxxx [MSB]
957 14:44:40.328642 44, [0] xxxxxxxx xxxxxxxx [MSB]
958 14:44:40.328749 iDelay=44, Bit 0, Center 23 (7 ~ 39) 33
959 14:44:40.328853 iDelay=44, Bit 1, Center 22 (5 ~ 40) 36
960 14:44:40.328957 iDelay=44, Bit 2, Center 22 (5 ~ 40) 36
961 14:44:40.329061 iDelay=44, Bit 3, Center 14 (-2 ~ 31) 34
962 14:44:40.329165 iDelay=44, Bit 4, Center 21 (5 ~ 38) 34
963 14:44:40.329269 iDelay=44, Bit 5, Center 17 (0 ~ 34) 35
964 14:44:40.329373 iDelay=44, Bit 6, Center 18 (1 ~ 36) 36
965 14:44:40.329477 iDelay=44, Bit 7, Center 20 (4 ~ 36) 33
966 14:44:40.329581 iDelay=44, Bit 8, Center 14 (-3 ~ 32) 36
967 14:44:40.329686 iDelay=44, Bit 9, Center 18 (0 ~ 36) 37
968 14:44:40.329790 iDelay=44, Bit 10, Center 25 (8 ~ 43) 36
969 14:44:40.329893 iDelay=44, Bit 11, Center 17 (0 ~ 35) 36
970 14:44:40.329997 iDelay=44, Bit 12, Center 19 (1 ~ 37) 37
971 14:44:40.330101 iDelay=44, Bit 13, Center 19 (1 ~ 38) 38
972 14:44:40.330205 iDelay=44, Bit 14, Center 20 (4 ~ 37) 34
973 14:44:40.330309 iDelay=44, Bit 15, Center 23 (5 ~ 41) 37
974 14:44:40.330413 ==
975 14:44:40.330518 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
976 14:44:40.330624 fsp= 1, odt_onoff= 1, Byte mode= 0
977 14:44:40.330729 ==
978 14:44:40.330834 DQS Delay:
979 14:44:40.330938 DQS0 = 0, DQS1 = 0
980 14:44:40.331042 DQM Delay:
981 14:44:40.331146 DQM0 = 19, DQM1 = 19
982 14:44:40.331250 DQ Delay:
983 14:44:40.331355 DQ0 =23, DQ1 =22, DQ2 =22, DQ3 =14
984 14:44:40.331466 DQ4 =21, DQ5 =17, DQ6 =18, DQ7 =20
985 14:44:40.331571 DQ8 =14, DQ9 =18, DQ10 =25, DQ11 =17
986 14:44:40.331676 DQ12 =19, DQ13 =19, DQ14 =20, DQ15 =23
987 14:44:40.331781
988 14:44:40.331886
989 14:44:40.331991 DramC Write-DBI off
990 14:44:40.332096 ==
991 14:44:40.332201 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
992 14:44:40.332307 fsp= 1, odt_onoff= 1, Byte mode= 0
993 14:44:40.332413 ==
994 14:44:40.332518 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
995 14:44:40.332623
996 14:44:40.332728 Begin, DQ Scan Range 919~1175
997 14:44:40.332833
998 14:44:40.332937
999 14:44:40.333040 TX Vref Scan disable
1000 14:44:40.333146 919 |3 4 23|[0] xxxxxxxx xxxxxxxx [MSB]
1001 14:44:40.333254 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1002 14:44:40.333362 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1003 14:44:40.333470 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1004 14:44:40.333778 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1005 14:44:40.333890 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1006 14:44:40.334003 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1007 14:44:40.334113 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1008 14:44:40.334222 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1009 14:44:40.334331 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1010 14:44:40.334440 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1011 14:44:40.334549 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1012 14:44:40.334658 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1013 14:44:40.334767 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1014 14:44:40.334876 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1015 14:44:40.334984 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1016 14:44:40.335093 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1017 14:44:40.335204 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1018 14:44:40.335314 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1019 14:44:40.335432 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1020 14:44:40.335521 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1021 14:44:40.335608 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1022 14:44:40.335694 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1023 14:44:40.335779 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1024 14:44:40.335892 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1025 14:44:40.336010 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1026 14:44:40.336122 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1027 14:44:40.336232 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1028 14:44:40.336347 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1029 14:44:40.336434 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1030 14:44:40.336522 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1031 14:44:40.336612 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1032 14:44:40.336702 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1033 14:44:40.336810 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1034 14:44:40.336923 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1035 14:44:40.337032 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1036 14:44:40.337140 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1037 14:44:40.337248 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1038 14:44:40.337355 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1039 14:44:40.337462 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1040 14:44:40.337569 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1041 14:44:40.337676 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1042 14:44:40.337782 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1043 14:44:40.337889 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1044 14:44:40.337995 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1045 14:44:40.338101 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1046 14:44:40.338206 965 |3 6 5|[0] xxxxxxxx oxxoxxxx [MSB]
1047 14:44:40.338312 966 |3 6 6|[0] xxxxxxxx oxxoxxxx [MSB]
1048 14:44:40.338417 967 |3 6 7|[0] xxxxxxxx ooxoooox [MSB]
1049 14:44:40.338522 968 |3 6 8|[0] xxxxxxxx ooxoooox [MSB]
1050 14:44:40.338628 969 |3 6 9|[0] xxxxxxxx ooxooooo [MSB]
1051 14:44:40.338733 970 |3 6 10|[0] xxxxxxxx oooooooo [MSB]
1052 14:44:40.338839 971 |3 6 11|[0] xxxxxxxx oooooooo [MSB]
1053 14:44:40.338945 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB]
1054 14:44:40.339050 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
1055 14:44:40.339156 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
1056 14:44:40.339262 975 |3 6 15|[0] xxxoxoox oooooooo [MSB]
1057 14:44:40.339367 976 |3 6 16|[0] xooooooo oooooooo [MSB]
1058 14:44:40.339485 984 |3 6 24|[0] oooooooo xooooooo [MSB]
1059 14:44:40.339596 985 |3 6 25|[0] oooooooo xooxoooo [MSB]
1060 14:44:40.339703 986 |3 6 26|[0] oooooooo xxxxxxxx [MSB]
1061 14:44:40.339814 987 |3 6 27|[0] oooooooo xxxxxxxx [MSB]
1062 14:44:40.339921 988 |3 6 28|[0] oooooooo xxxxxxxx [MSB]
1063 14:44:40.340030 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
1064 14:44:40.340142 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1065 14:44:40.340248 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1066 14:44:40.340354 992 |3 6 32|[0] oooxoooo xxxxxxxx [MSB]
1067 14:44:40.340466 993 |3 6 33|[0] oooxoooo xxxxxxxx [MSB]
1068 14:44:40.340572 994 |3 6 34|[0] oooxoxoo xxxxxxxx [MSB]
1069 14:44:40.340678 995 |3 6 35|[0] oooxoxxo xxxxxxxx [MSB]
1070 14:44:40.340783 996 |3 6 36|[0] oooxxxxx xxxxxxxx [MSB]
1071 14:44:40.340892 997 |3 6 37|[0] xxxxxxxx xxxxxxxx [MSB]
1072 14:44:40.340998 Byte0, DQ PI dly=984, DQM PI dly= 984
1073 14:44:40.341101 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
1074 14:44:40.341206
1075 14:44:40.341309 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
1076 14:44:40.341413
1077 14:44:40.341516 Byte1, DQ PI dly=975, DQM PI dly= 975
1078 14:44:40.341620 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 15)
1079 14:44:40.341724
1080 14:44:40.341827 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 15)
1081 14:44:40.341931
1082 14:44:40.342034 ==
1083 14:44:40.342137 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1084 14:44:40.342246 fsp= 1, odt_onoff= 1, Byte mode= 0
1085 14:44:40.342350 ==
1086 14:44:40.342457 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1087 14:44:40.342561
1088 14:44:40.342668 Begin, DQ Scan Range 951~1015
1089 14:44:40.342775 Write Rank0 MR14 =0x0
1090 14:44:40.342885
1091 14:44:40.342989 CH=0, VrefRange= 0, VrefLevel = 0
1092 14:44:40.343093 TX Bit0 (978~992) 15 985, Bit8 (967~976) 10 971,
1093 14:44:40.343197 TX Bit1 (977~992) 16 984, Bit9 (968~982) 15 975,
1094 14:44:40.343305 TX Bit2 (978~992) 15 985, Bit10 (974~985) 12 979,
1095 14:44:40.343415 TX Bit3 (975~985) 11 980, Bit11 (967~980) 14 973,
1096 14:44:40.343525 TX Bit4 (978~991) 14 984, Bit12 (969~982) 14 975,
1097 14:44:40.343632 TX Bit5 (976~989) 14 982, Bit13 (969~982) 14 975,
1098 14:44:40.343741 TX Bit6 (977~990) 14 983, Bit14 (968~983) 16 975,
1099 14:44:40.343847 TX Bit7 (978~991) 14 984, Bit15 (973~984) 12 978,
1100 14:44:40.343951
1101 14:44:40.344054 Write Rank0 MR14 =0x2
1102 14:44:40.344157
1103 14:44:40.344260 CH=0, VrefRange= 0, VrefLevel = 2
1104 14:44:40.344363 TX Bit0 (978~993) 16 985, Bit8 (967~977) 11 972,
1105 14:44:40.344468 TX Bit1 (977~992) 16 984, Bit9 (968~983) 16 975,
1106 14:44:40.344572 TX Bit2 (978~993) 16 985, Bit10 (974~986) 13 980,
1107 14:44:40.344676 TX Bit3 (974~986) 13 980, Bit11 (967~981) 15 974,
1108 14:44:40.344780 TX Bit4 (977~992) 16 984, Bit12 (969~982) 14 975,
1109 14:44:40.344884 TX Bit5 (976~991) 16 983, Bit13 (968~983) 16 975,
1110 14:44:40.345188 TX Bit6 (977~991) 15 984, Bit14 (968~983) 16 975,
1111 14:44:40.345294 TX Bit7 (978~991) 14 984, Bit15 (973~985) 13 979,
1112 14:44:40.345401
1113 14:44:40.345506 Write Rank0 MR14 =0x4
1114 14:44:40.345611
1115 14:44:40.345715 CH=0, VrefRange= 0, VrefLevel = 4
1116 14:44:40.345820 TX Bit0 (978~994) 17 986, Bit8 (966~979) 14 972,
1117 14:44:40.345926 TX Bit1 (977~992) 16 984, Bit9 (968~983) 16 975,
1118 14:44:40.346031 TX Bit2 (977~993) 17 985, Bit10 (972~987) 16 979,
1119 14:44:40.346136 TX Bit3 (974~988) 15 981, Bit11 (967~982) 16 974,
1120 14:44:40.346241 TX Bit4 (977~992) 16 984, Bit12 (969~983) 15 976,
1121 14:44:40.346369 TX Bit5 (976~991) 16 983, Bit13 (968~983) 16 975,
1122 14:44:40.346502 TX Bit6 (976~991) 16 983, Bit14 (968~984) 17 976,
1123 14:44:40.346609 TX Bit7 (977~992) 16 984, Bit15 (972~985) 14 978,
1124 14:44:40.346715
1125 14:44:40.346819 Write Rank0 MR14 =0x6
1126 14:44:40.346933
1127 14:44:40.347037 CH=0, VrefRange= 0, VrefLevel = 6
1128 14:44:40.347177 TX Bit0 (978~994) 17 986, Bit8 (966~979) 14 972,
1129 14:44:40.347296 TX Bit1 (977~993) 17 985, Bit9 (967~983) 17 975,
1130 14:44:40.347422 TX Bit2 (978~994) 17 986, Bit10 (972~988) 17 980,
1131 14:44:40.347509 TX Bit3 (973~988) 16 980, Bit11 (967~982) 16 974,
1132 14:44:40.347594 TX Bit4 (977~992) 16 984, Bit12 (968~983) 16 975,
1133 14:44:40.347695 TX Bit5 (975~992) 18 983, Bit13 (968~984) 17 976,
1134 14:44:40.347784 TX Bit6 (976~992) 17 984, Bit14 (968~984) 17 976,
1135 14:44:40.347889 TX Bit7 (977~993) 17 985, Bit15 (971~987) 17 979,
1136 14:44:40.348002
1137 14:44:40.348132 Write Rank0 MR14 =0x8
1138 14:44:40.348245
1139 14:44:40.348360 CH=0, VrefRange= 0, VrefLevel = 8
1140 14:44:40.348486 TX Bit0 (978~995) 18 986, Bit8 (965~981) 17 973,
1141 14:44:40.348599 TX Bit1 (977~994) 18 985, Bit9 (967~984) 18 975,
1142 14:44:40.348707 TX Bit2 (978~995) 18 986, Bit10 (971~989) 19 980,
1143 14:44:40.348817 TX Bit3 (973~990) 18 981, Bit11 (966~983) 18 974,
1144 14:44:40.348922 TX Bit4 (977~993) 17 985, Bit12 (968~984) 17 976,
1145 14:44:40.349028 TX Bit5 (975~992) 18 983, Bit13 (968~984) 17 976,
1146 14:44:40.349136 TX Bit6 (976~992) 17 984, Bit14 (967~985) 19 976,
1147 14:44:40.349242 TX Bit7 (977~993) 17 985, Bit15 (971~988) 18 979,
1148 14:44:40.349347
1149 14:44:40.349451 Write Rank0 MR14 =0xa
1150 14:44:40.349555
1151 14:44:40.349659 CH=0, VrefRange= 0, VrefLevel = 10
1152 14:44:40.349763 TX Bit0 (977~995) 19 986, Bit8 (965~982) 18 973,
1153 14:44:40.349868 TX Bit1 (977~994) 18 985, Bit9 (967~984) 18 975,
1154 14:44:40.349973 TX Bit2 (977~995) 19 986, Bit10 (971~989) 19 980,
1155 14:44:40.350078 TX Bit3 (972~990) 19 981, Bit11 (966~983) 18 974,
1156 14:44:40.350188 TX Bit4 (977~993) 17 985, Bit12 (968~984) 17 976,
1157 14:44:40.350296 TX Bit5 (975~992) 18 983, Bit13 (968~984) 17 976,
1158 14:44:40.350401 TX Bit6 (976~992) 17 984, Bit14 (967~985) 19 976,
1159 14:44:40.350509 TX Bit7 (977~993) 17 985, Bit15 (970~988) 19 979,
1160 14:44:40.350618
1161 14:44:40.350725 Write Rank0 MR14 =0xc
1162 14:44:40.350829
1163 14:44:40.350936 CH=0, VrefRange= 0, VrefLevel = 12
1164 14:44:40.351040 TX Bit0 (977~996) 20 986, Bit8 (965~982) 18 973,
1165 14:44:40.351149 TX Bit1 (976~995) 20 985, Bit9 (967~985) 19 976,
1166 14:44:40.351253 TX Bit2 (977~996) 20 986, Bit10 (970~990) 21 980,
1167 14:44:40.351358 TX Bit3 (972~991) 20 981, Bit11 (966~983) 18 974,
1168 14:44:40.351479 TX Bit4 (976~994) 19 985, Bit12 (968~984) 17 976,
1169 14:44:40.351586 TX Bit5 (974~993) 20 983, Bit13 (967~985) 19 976,
1170 14:44:40.351695 TX Bit6 (975~993) 19 984, Bit14 (967~986) 20 976,
1171 14:44:40.351823 TX Bit7 (977~994) 18 985, Bit15 (970~989) 20 979,
1172 14:44:40.351950
1173 14:44:40.352060 Write Rank0 MR14 =0xe
1174 14:44:40.352170
1175 14:44:40.352276 CH=0, VrefRange= 0, VrefLevel = 14
1176 14:44:40.352411 TX Bit0 (977~997) 21 987, Bit8 (964~983) 20 973,
1177 14:44:40.352538 TX Bit1 (976~996) 21 986, Bit9 (967~985) 19 976,
1178 14:44:40.352672 TX Bit2 (977~997) 21 987, Bit10 (971~990) 20 980,
1179 14:44:40.352780 TX Bit3 (971~991) 21 981, Bit11 (966~984) 19 975,
1180 14:44:40.352904 TX Bit4 (976~995) 20 985, Bit12 (967~985) 19 976,
1181 14:44:40.353025 TX Bit5 (974~993) 20 983, Bit13 (967~985) 19 976,
1182 14:44:40.353158 TX Bit6 (975~993) 19 984, Bit14 (967~986) 20 976,
1183 14:44:40.353266 TX Bit7 (976~994) 19 985, Bit15 (970~990) 21 980,
1184 14:44:40.353372
1185 14:44:40.353477 Write Rank0 MR14 =0x10
1186 14:44:40.353607
1187 14:44:40.353713 CH=0, VrefRange= 0, VrefLevel = 16
1188 14:44:40.353819 TX Bit0 (977~997) 21 987, Bit8 (964~983) 20 973,
1189 14:44:40.353925 TX Bit1 (976~996) 21 986, Bit9 (967~985) 19 976,
1190 14:44:40.354030 TX Bit2 (977~997) 21 987, Bit10 (970~990) 21 980,
1191 14:44:40.354135 TX Bit3 (972~991) 20 981, Bit11 (965~984) 20 974,
1192 14:44:40.354247 TX Bit4 (976~995) 20 985, Bit12 (967~985) 19 976,
1193 14:44:40.354364 TX Bit5 (974~993) 20 983, Bit13 (967~986) 20 976,
1194 14:44:40.354464 TX Bit6 (975~994) 20 984, Bit14 (967~987) 21 977,
1195 14:44:40.354565 TX Bit7 (976~995) 20 985, Bit15 (970~990) 21 980,
1196 14:44:40.354683
1197 14:44:40.354806 Write Rank0 MR14 =0x12
1198 14:44:40.354906
1199 14:44:40.355001 CH=0, VrefRange= 0, VrefLevel = 18
1200 14:44:40.355096 TX Bit0 (977~998) 22 987, Bit8 (963~983) 21 973,
1201 14:44:40.355201 TX Bit1 (976~997) 22 986, Bit9 (966~986) 21 976,
1202 14:44:40.355297 TX Bit2 (976~998) 23 987, Bit10 (970~991) 22 980,
1203 14:44:40.355393 TX Bit3 (970~992) 23 981, Bit11 (965~985) 21 975,
1204 14:44:40.355503 TX Bit4 (976~996) 21 986, Bit12 (967~986) 20 976,
1205 14:44:40.355598 TX Bit5 (973~994) 22 983, Bit13 (967~986) 20 976,
1206 14:44:40.355693 TX Bit6 (974~994) 21 984, Bit14 (966~988) 23 977,
1207 14:44:40.355788 TX Bit7 (976~995) 20 985, Bit15 (969~990) 22 979,
1208 14:44:40.355882
1209 14:44:40.355975 Write Rank0 MR14 =0x14
1210 14:44:40.356071
1211 14:44:40.356172 CH=0, VrefRange= 0, VrefLevel = 20
1212 14:44:40.356276 TX Bit0 (976~999) 24 987, Bit8 (963~984) 22 973,
1213 14:44:40.356584 TX Bit1 (976~997) 22 986, Bit9 (966~986) 21 976,
1214 14:44:40.356708 TX Bit2 (976~998) 23 987, Bit10 (969~991) 23 980,
1215 14:44:40.356804 TX Bit3 (970~992) 23 981, Bit11 (965~985) 21 975,
1216 14:44:40.356912 TX Bit4 (976~997) 22 986, Bit12 (967~987) 21 977,
1217 14:44:40.357018 TX Bit5 (973~994) 22 983, Bit13 (967~987) 21 977,
1218 14:44:40.357124 TX Bit6 (975~995) 21 985, Bit14 (966~989) 24 977,
1219 14:44:40.357229 TX Bit7 (976~996) 21 986, Bit15 (969~990) 22 979,
1220 14:44:40.357333
1221 14:44:40.357437 Write Rank0 MR14 =0x16
1222 14:44:40.357540
1223 14:44:40.357644 CH=0, VrefRange= 0, VrefLevel = 22
1224 14:44:40.357748 TX Bit0 (976~999) 24 987, Bit8 (962~984) 23 973,
1225 14:44:40.357852 TX Bit1 (975~998) 24 986, Bit9 (966~987) 22 976,
1226 14:44:40.357956 TX Bit2 (976~999) 24 987, Bit10 (969~991) 23 980,
1227 14:44:40.358060 TX Bit3 (969~992) 24 980, Bit11 (964~986) 23 975,
1228 14:44:40.358164 TX Bit4 (975~997) 23 986, Bit12 (967~988) 22 977,
1229 14:44:40.358268 TX Bit5 (973~994) 22 983, Bit13 (966~988) 23 977,
1230 14:44:40.358371 TX Bit6 (974~996) 23 985, Bit14 (966~989) 24 977,
1231 14:44:40.358475 TX Bit7 (976~997) 22 986, Bit15 (969~991) 23 980,
1232 14:44:40.358604
1233 14:44:40.358724 Write Rank0 MR14 =0x18
1234 14:44:40.358842
1235 14:44:40.358948 CH=0, VrefRange= 0, VrefLevel = 24
1236 14:44:40.359053 TX Bit0 (976~999) 24 987, Bit8 (962~984) 23 973,
1237 14:44:40.359168 TX Bit1 (976~999) 24 987, Bit9 (965~988) 24 976,
1238 14:44:40.359274 TX Bit2 (976~999) 24 987, Bit10 (968~992) 25 980,
1239 14:44:40.359380 TX Bit3 (969~993) 25 981, Bit11 (964~986) 23 975,
1240 14:44:40.359510 TX Bit4 (975~998) 24 986, Bit12 (967~989) 23 978,
1241 14:44:40.359616 TX Bit5 (972~995) 24 983, Bit13 (966~988) 23 977,
1242 14:44:40.359721 TX Bit6 (974~996) 23 985, Bit14 (966~990) 25 978,
1243 14:44:40.359826 TX Bit7 (976~998) 23 987, Bit15 (969~991) 23 980,
1244 14:44:40.359931
1245 14:44:40.360035 Write Rank0 MR14 =0x1a
1246 14:44:40.360138
1247 14:44:40.360241 CH=0, VrefRange= 0, VrefLevel = 26
1248 14:44:40.360345 TX Bit0 (976~999) 24 987, Bit8 (961~985) 25 973,
1249 14:44:40.360450 TX Bit1 (975~999) 25 987, Bit9 (965~988) 24 976,
1250 14:44:40.360554 TX Bit2 (976~999) 24 987, Bit10 (969~992) 24 980,
1251 14:44:40.360659 TX Bit3 (969~993) 25 981, Bit11 (964~987) 24 975,
1252 14:44:40.360763 TX Bit4 (975~998) 24 986, Bit12 (966~989) 24 977,
1253 14:44:40.360867 TX Bit5 (972~995) 24 983, Bit13 (966~989) 24 977,
1254 14:44:40.360996 TX Bit6 (973~996) 24 984, Bit14 (966~990) 25 978,
1255 14:44:40.361126 TX Bit7 (975~998) 24 986, Bit15 (968~991) 24 979,
1256 14:44:40.361232
1257 14:44:40.361336 Write Rank0 MR14 =0x1c
1258 14:44:40.361445
1259 14:44:40.361574 CH=0, VrefRange= 0, VrefLevel = 28
1260 14:44:40.361685 TX Bit0 (976~999) 24 987, Bit8 (961~985) 25 973,
1261 14:44:40.361791 TX Bit1 (975~999) 25 987, Bit9 (965~988) 24 976,
1262 14:44:40.361896 TX Bit2 (976~999) 24 987, Bit10 (969~992) 24 980,
1263 14:44:40.362001 TX Bit3 (969~993) 25 981, Bit11 (964~987) 24 975,
1264 14:44:40.362105 TX Bit4 (975~998) 24 986, Bit12 (966~989) 24 977,
1265 14:44:40.362210 TX Bit5 (972~995) 24 983, Bit13 (966~989) 24 977,
1266 14:44:40.362314 TX Bit6 (973~996) 24 984, Bit14 (966~990) 25 978,
1267 14:44:40.362418 TX Bit7 (975~998) 24 986, Bit15 (968~991) 24 979,
1268 14:44:40.362521
1269 14:44:40.362624 Write Rank0 MR14 =0x1e
1270 14:44:40.362731
1271 14:44:40.362834 CH=0, VrefRange= 0, VrefLevel = 30
1272 14:44:40.362941 TX Bit0 (976~1000) 25 988, Bit8 (962~985) 24 973,
1273 14:44:40.363046 TX Bit1 (976~999) 24 987, Bit9 (965~988) 24 976,
1274 14:44:40.363150 TX Bit2 (976~999) 24 987, Bit10 (968~993) 26 980,
1275 14:44:40.363262 TX Bit3 (969~993) 25 981, Bit11 (963~986) 24 974,
1276 14:44:40.363369 TX Bit4 (975~999) 25 987, Bit12 (966~990) 25 978,
1277 14:44:40.363481 TX Bit5 (972~995) 24 983, Bit13 (965~988) 24 976,
1278 14:44:40.363585 TX Bit6 (973~998) 26 985, Bit14 (966~990) 25 978,
1279 14:44:40.363689 TX Bit7 (975~999) 25 987, Bit15 (968~992) 25 980,
1280 14:44:40.363793
1281 14:44:40.363895 Write Rank0 MR14 =0x20
1282 14:44:40.363999
1283 14:44:40.364101 CH=0, VrefRange= 0, VrefLevel = 32
1284 14:44:40.364203 TX Bit0 (976~1000) 25 988, Bit8 (962~985) 24 973,
1285 14:44:40.364307 TX Bit1 (976~999) 24 987, Bit9 (965~988) 24 976,
1286 14:44:40.364412 TX Bit2 (976~999) 24 987, Bit10 (968~993) 26 980,
1287 14:44:40.364515 TX Bit3 (969~993) 25 981, Bit11 (963~986) 24 974,
1288 14:44:40.364619 TX Bit4 (975~999) 25 987, Bit12 (966~990) 25 978,
1289 14:44:40.364723 TX Bit5 (972~995) 24 983, Bit13 (965~988) 24 976,
1290 14:44:40.364826 TX Bit6 (973~998) 26 985, Bit14 (966~990) 25 978,
1291 14:44:40.364929 TX Bit7 (975~999) 25 987, Bit15 (968~992) 25 980,
1292 14:44:40.365032
1293 14:44:40.365134 Write Rank0 MR14 =0x22
1294 14:44:40.365237
1295 14:44:40.365340 CH=0, VrefRange= 0, VrefLevel = 34
1296 14:44:40.365471 TX Bit0 (976~1000) 25 988, Bit8 (962~985) 24 973,
1297 14:44:40.365598 TX Bit1 (976~999) 24 987, Bit9 (965~988) 24 976,
1298 14:44:40.365701 TX Bit2 (976~999) 24 987, Bit10 (968~993) 26 980,
1299 14:44:40.365800 TX Bit3 (969~993) 25 981, Bit11 (963~986) 24 974,
1300 14:44:40.365901 TX Bit4 (975~999) 25 987, Bit12 (966~990) 25 978,
1301 14:44:40.366019 TX Bit5 (972~995) 24 983, Bit13 (965~988) 24 976,
1302 14:44:40.366121 TX Bit6 (973~998) 26 985, Bit14 (966~990) 25 978,
1303 14:44:40.366218 TX Bit7 (975~999) 25 987, Bit15 (968~992) 25 980,
1304 14:44:40.366322
1305 14:44:40.366428 Write Rank0 MR14 =0x24
1306 14:44:40.366524
1307 14:44:40.366619 CH=0, VrefRange= 0, VrefLevel = 36
1308 14:44:40.366738 TX Bit0 (976~1000) 25 988, Bit8 (962~985) 24 973,
1309 14:44:40.366838 TX Bit1 (976~999) 24 987, Bit9 (965~988) 24 976,
1310 14:44:40.366935 TX Bit2 (976~999) 24 987, Bit10 (968~993) 26 980,
1311 14:44:40.367036 TX Bit3 (969~993) 25 981, Bit11 (963~986) 24 974,
1312 14:44:40.367343 TX Bit4 (975~999) 25 987, Bit12 (966~990) 25 978,
1313 14:44:40.367463 TX Bit5 (972~995) 24 983, Bit13 (965~988) 24 976,
1314 14:44:40.367564 TX Bit6 (973~998) 26 985, Bit14 (966~990) 25 978,
1315 14:44:40.367661 TX Bit7 (975~999) 25 987, Bit15 (968~992) 25 980,
1316 14:44:40.367758
1317 14:44:40.367853
1318 14:44:40.367947 TX Vref found, early break! 367< 375
1319 14:44:40.368043 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
1320 14:44:40.368139 u1DelayCellOfst[0]=9 cells (7 PI)
1321 14:44:40.368234 u1DelayCellOfst[1]=7 cells (6 PI)
1322 14:44:40.368329 u1DelayCellOfst[2]=7 cells (6 PI)
1323 14:44:40.368425 u1DelayCellOfst[3]=0 cells (0 PI)
1324 14:44:40.368541 u1DelayCellOfst[4]=7 cells (6 PI)
1325 14:44:40.368644 u1DelayCellOfst[5]=2 cells (2 PI)
1326 14:44:40.368755 u1DelayCellOfst[6]=5 cells (4 PI)
1327 14:44:40.368868 u1DelayCellOfst[7]=7 cells (6 PI)
1328 14:44:40.368965 Byte0, DQ PI dly=981, DQM PI dly= 984
1329 14:44:40.369061 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
1330 14:44:40.369162
1331 14:44:40.369271 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
1332 14:44:40.369391
1333 14:44:40.369486 u1DelayCellOfst[8]=0 cells (0 PI)
1334 14:44:40.369580 u1DelayCellOfst[9]=3 cells (3 PI)
1335 14:44:40.369675 u1DelayCellOfst[10]=9 cells (7 PI)
1336 14:44:40.369770 u1DelayCellOfst[11]=1 cells (1 PI)
1337 14:44:40.369865 u1DelayCellOfst[12]=6 cells (5 PI)
1338 14:44:40.369964 u1DelayCellOfst[13]=3 cells (3 PI)
1339 14:44:40.370060 u1DelayCellOfst[14]=6 cells (5 PI)
1340 14:44:40.370158 u1DelayCellOfst[15]=9 cells (7 PI)
1341 14:44:40.370251 Byte1, DQ PI dly=973, DQM PI dly= 976
1342 14:44:40.370344 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 13)
1343 14:44:40.370443
1344 14:44:40.370539 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 13)
1345 14:44:40.370637
1346 14:44:40.370732 Write Rank0 MR14 =0x1e
1347 14:44:40.370826
1348 14:44:40.370919 Final TX Range 0 Vref 30
1349 14:44:40.371012
1350 14:44:40.371105 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1351 14:44:40.371201
1352 14:44:40.371295 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1353 14:44:40.371390 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1354 14:44:40.371504 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1355 14:44:40.371601 Write Rank0 MR3 =0xb0
1356 14:44:40.371697 DramC Write-DBI on
1357 14:44:40.371790 ==
1358 14:44:40.371885 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1359 14:44:40.371979 fsp= 1, odt_onoff= 1, Byte mode= 0
1360 14:44:40.372097 ==
1361 14:44:40.372219 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1362 14:44:40.372318
1363 14:44:40.372408 Begin, DQ Scan Range 696~760
1364 14:44:40.372498
1365 14:44:40.372614
1366 14:44:40.372735 TX Vref Scan disable
1367 14:44:40.372834 696 |2 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1368 14:44:40.372934 697 |2 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1369 14:44:40.373032 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1370 14:44:40.373130 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1371 14:44:40.373244 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1372 14:44:40.373345 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1373 14:44:40.373442 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1374 14:44:40.373538 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1375 14:44:40.373660 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1376 14:44:40.373756 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1377 14:44:40.373863 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1378 14:44:40.373973 707 |2 6 3|[0] xxxxxxxx oooooooo [MSB]
1379 14:44:40.374083 708 |2 6 4|[0] xxxxxxxx oooooooo [MSB]
1380 14:44:40.374196 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB]
1381 14:44:40.374306 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
1382 14:44:40.374420 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
1383 14:44:40.374538 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
1384 14:44:40.374662 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1385 14:44:40.374777 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
1386 14:44:40.374878 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
1387 14:44:40.374977 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
1388 14:44:40.375074 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
1389 14:44:40.375185 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
1390 14:44:40.375282 734 |2 6 30|[0] oooooooo xxxxxxxx [MSB]
1391 14:44:40.375378 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB]
1392 14:44:40.375510 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
1393 14:44:40.375609 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
1394 14:44:40.375706 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
1395 14:44:40.375824 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1396 14:44:40.375935 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1397 14:44:40.376048 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1398 14:44:40.376162 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
1399 14:44:40.376259 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
1400 14:44:40.376362 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
1401 14:44:40.376466 745 |2 6 41|[0] xxxxxxxx xxxxxxxx [MSB]
1402 14:44:40.376584 Byte0, DQ PI dly=731, DQM PI dly= 731
1403 14:44:40.376684 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 27)
1404 14:44:40.376779
1405 14:44:40.376872 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 27)
1406 14:44:40.376965
1407 14:44:40.377058 Byte1, DQ PI dly=720, DQM PI dly= 720
1408 14:44:40.377160 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 16)
1409 14:44:40.377259
1410 14:44:40.377352 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 16)
1411 14:44:40.377445
1412 14:44:40.377539 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1413 14:44:40.377637 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1414 14:44:40.377732 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1415 14:44:40.377831 Write Rank0 MR3 =0x30
1416 14:44:40.377923 DramC Write-DBI off
1417 14:44:40.378018
1418 14:44:40.378115 [DATLAT]
1419 14:44:40.378215 Freq=1600, CH0 RK0, use_rxtx_scan=0
1420 14:44:40.378314
1421 14:44:40.378406 DATLAT Default: 0xf
1422 14:44:40.378502 7, 0xFFFF, sum=0
1423 14:44:40.378599 8, 0xFFFF, sum=0
1424 14:44:40.378694 9, 0xFFFF, sum=0
1425 14:44:40.378792 10, 0xFFFF, sum=0
1426 14:44:40.378891 11, 0xFFFF, sum=0
1427 14:44:40.379006 12, 0xFFFF, sum=0
1428 14:44:40.379118 13, 0xFFFF, sum=0
1429 14:44:40.379227 14, 0x0, sum=1
1430 14:44:40.379324 15, 0x0, sum=2
1431 14:44:40.379437 16, 0x0, sum=3
1432 14:44:40.379503 17, 0x0, sum=4
1433 14:44:40.379589 pattern=2 first_step=14 total pass=5 best_step=16
1434 14:44:40.379660 ==
1435 14:44:40.379939 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1436 14:44:40.380010 fsp= 1, odt_onoff= 1, Byte mode= 0
1437 14:44:40.380082 ==
1438 14:44:40.380145 Start DQ dly to find pass range UseTestEngine =1
1439 14:44:40.380207 x-axis: bit #, y-axis: DQ dly (-127~63)
1440 14:44:40.380269 RX Vref Scan = 1
1441 14:44:40.380331
1442 14:44:40.380391 RX Vref found, early break!
1443 14:44:40.380452
1444 14:44:40.380529 Final RX Vref 12, apply to both rank0 and 1
1445 14:44:40.380592 ==
1446 14:44:40.380653 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1447 14:44:40.380714 fsp= 1, odt_onoff= 1, Byte mode= 0
1448 14:44:40.380793 ==
1449 14:44:40.380855 DQS Delay:
1450 14:44:40.380929 DQS0 = 0, DQS1 = 0
1451 14:44:40.381004 DQM Delay:
1452 14:44:40.381065 DQM0 = 19, DQM1 = 18
1453 14:44:40.381126 DQ Delay:
1454 14:44:40.381187 DQ0 =22, DQ1 =21, DQ2 =21, DQ3 =15
1455 14:44:40.381247 DQ4 =21, DQ5 =17, DQ6 =19, DQ7 =20
1456 14:44:40.381308 DQ8 =14, DQ9 =16, DQ10 =25, DQ11 =16
1457 14:44:40.381377 DQ12 =19, DQ13 =18, DQ14 =20, DQ15 =22
1458 14:44:40.381437
1459 14:44:40.381514
1460 14:44:40.381574
1461 14:44:40.381634 [DramC_TX_OE_Calibration] TA2
1462 14:44:40.381694 Original DQ_B0 (3 6) =30, OEN = 27
1463 14:44:40.381756 Original DQ_B1 (3 6) =30, OEN = 27
1464 14:44:40.381816 23, 0x0, End_B0=23 End_B1=23
1465 14:44:40.381878 24, 0x0, End_B0=24 End_B1=24
1466 14:44:40.381939 25, 0x0, End_B0=25 End_B1=25
1467 14:44:40.382000 26, 0x0, End_B0=26 End_B1=26
1468 14:44:40.382061 27, 0x0, End_B0=27 End_B1=27
1469 14:44:40.382123 28, 0x0, End_B0=28 End_B1=28
1470 14:44:40.382184 29, 0x0, End_B0=29 End_B1=29
1471 14:44:40.382245 30, 0x0, End_B0=30 End_B1=30
1472 14:44:40.382306 31, 0xFFFF, End_B0=30 End_B1=30
1473 14:44:40.382387 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1474 14:44:40.382450 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1475 14:44:40.382533
1476 14:44:40.382596
1477 14:44:40.382656 Write Rank0 MR23 =0x3f
1478 14:44:40.382717 [DQSOSC]
1479 14:44:40.382777 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
1480 14:44:40.382838 CH0_RK0: MR19=0x303, MR18=0x1414, DQSOSC=399, MR23=63, INC=15, DEC=23
1481 14:44:40.382907 Write Rank0 MR23 =0x3f
1482 14:44:40.382982 [DQSOSC]
1483 14:44:40.383061 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
1484 14:44:40.383129 CH0 RK0: MR19=303, MR18=1414
1485 14:44:40.383201 [RankSwap] Rank num 2, (Multi 1), Rank 1
1486 14:44:40.383263 Write Rank0 MR2 =0xad
1487 14:44:40.383336 [Write Leveling]
1488 14:44:40.383402 delay byte0 byte1 byte2 byte3
1489 14:44:40.383474
1490 14:44:40.383535 10 0 0
1491 14:44:40.383602 11 0 0
1492 14:44:40.383666 12 0 0
1493 14:44:40.383750 13 0 0
1494 14:44:40.383818 14 0 0
1495 14:44:40.383880 15 0 0
1496 14:44:40.383941 16 0 0
1497 14:44:40.384002 17 0 0
1498 14:44:40.384063 18 0 0
1499 14:44:40.384125 19 0 0
1500 14:44:40.384185 20 0 0
1501 14:44:40.384247 21 0 0
1502 14:44:40.384307 22 0 0
1503 14:44:40.384368 23 0 0
1504 14:44:40.384429 24 0 ff
1505 14:44:40.384490 25 0 ff
1506 14:44:40.384550 26 ff ff
1507 14:44:40.384611 27 ff ff
1508 14:44:40.384672 28 ff ff
1509 14:44:40.384733 29 ff ff
1510 14:44:40.384794 30 ff ff
1511 14:44:40.384855 31 ff ff
1512 14:44:40.384916 32 ff ff
1513 14:44:40.384977 pass bytecount = 0xff (0xff: all bytes pass)
1514 14:44:40.385037
1515 14:44:40.385096 DQS0 dly: 26
1516 14:44:40.385156 DQS1 dly: 24
1517 14:44:40.385216 Write Rank0 MR2 =0x2d
1518 14:44:40.385276 [RankSwap] Rank num 2, (Multi 1), Rank 0
1519 14:44:40.385336 Write Rank1 MR1 =0xd6
1520 14:44:40.385395 [Gating]
1521 14:44:40.385455 ==
1522 14:44:40.385515 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1523 14:44:40.385575 fsp= 1, odt_onoff= 1, Byte mode= 0
1524 14:44:40.385636 ==
1525 14:44:40.385695 3 1 0 |2c2b 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1526 14:44:40.385757 3 1 4 |2c2b 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1527 14:44:40.385819 3 1 8 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
1528 14:44:40.385880 3 1 12 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
1529 14:44:40.385942 3 1 16 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
1530 14:44:40.386003 3 1 20 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1531 14:44:40.386065 3 1 24 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1532 14:44:40.386126 3 1 28 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1533 14:44:40.386187 3 2 0 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1534 14:44:40.386250 3 2 4 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1535 14:44:40.386312 3 2 8 |404 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1536 14:44:40.386373 3 2 12 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1537 14:44:40.386435 3 2 16 |3534 706 |(11 11)(11 11) |(0 0)(1 1)| 0
1538 14:44:40.386496 3 2 20 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1539 14:44:40.386557 3 2 24 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1540 14:44:40.386618 3 2 28 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1541 14:44:40.386680 3 3 0 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1542 14:44:40.386741 3 3 4 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1543 14:44:40.386802 3 3 8 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1544 14:44:40.386864 3 3 12 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1545 14:44:40.386925 3 3 16 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1546 14:44:40.386987 3 3 20 |3534 909 |(11 11)(11 11) |(0 0)(1 1)| 0
1547 14:44:40.387047 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1548 14:44:40.387109 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1549 14:44:40.387171 [Byte 1] Lead/lag falling Transition (3, 3, 28)
1550 14:44:40.387231 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1551 14:44:40.387292 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1552 14:44:40.387354 3 4 8 |1717 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
1553 14:44:40.387426 3 4 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
1554 14:44:40.387490 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1555 14:44:40.387552 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1556 14:44:40.387614 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1557 14:44:40.387675 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1558 14:44:40.387737 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1559 14:44:40.387798 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1560 14:44:40.387860 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1561 14:44:40.388119 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1562 14:44:40.388188 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1563 14:44:40.388251 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1564 14:44:40.388313 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1565 14:44:40.388374 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1566 14:44:40.388436 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1567 14:44:40.388497 [Byte 0] Lead/lag falling Transition (3, 6, 0)
1568 14:44:40.388559 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
1569 14:44:40.388622 [Byte 1] Lead/lag falling Transition (3, 6, 4)
1570 14:44:40.388683 3 6 8 |1414 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
1571 14:44:40.388745 [Byte 0] Lead/lag Transition tap number (3)
1572 14:44:40.388805 [Byte 1] Lead/lag Transition tap number (2)
1573 14:44:40.388865 3 6 12 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
1574 14:44:40.388927 [Byte 0]First pass (3, 6, 12)
1575 14:44:40.388987 3 6 16 |4646 808 |(0 0)(11 11) |(0 0)(0 0)| 0
1576 14:44:40.389049 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1577 14:44:40.389110 [Byte 1]First pass (3, 6, 20)
1578 14:44:40.389170 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1579 14:44:40.389231 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1580 14:44:40.389293 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1581 14:44:40.389354 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1582 14:44:40.389415 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1583 14:44:40.389476 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1584 14:44:40.389537 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1585 14:44:40.389599 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1586 14:44:40.389660 All bytes gating window > 1UI, Early break!
1587 14:44:40.389721
1588 14:44:40.389780 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 6)
1589 14:44:40.389840
1590 14:44:40.389900 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 8)
1591 14:44:40.389960
1592 14:44:40.390020
1593 14:44:40.390079
1594 14:44:40.390138 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 6)
1595 14:44:40.390199
1596 14:44:40.390259 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 8)
1597 14:44:40.390319
1598 14:44:40.390378
1599 14:44:40.390438 Write Rank1 MR1 =0x56
1600 14:44:40.390498
1601 14:44:40.390557 best RODT dly(2T, 0.5T) = (2, 3)
1602 14:44:40.390617
1603 14:44:40.390676 best RODT dly(2T, 0.5T) = (2, 3)
1604 14:44:40.390736 ==
1605 14:44:40.390796 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1606 14:44:40.390857 fsp= 1, odt_onoff= 1, Byte mode= 0
1607 14:44:40.390917 ==
1608 14:44:40.390978 Start DQ dly to find pass range UseTestEngine =0
1609 14:44:40.391039 x-axis: bit #, y-axis: DQ dly (-127~63)
1610 14:44:40.391100 RX Vref Scan = 0
1611 14:44:40.391160 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1612 14:44:40.391222 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1613 14:44:40.391283 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1614 14:44:40.391345 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1615 14:44:40.391413 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1616 14:44:40.391478 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1617 14:44:40.391539 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1618 14:44:40.391600 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1619 14:44:40.391661 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1620 14:44:40.391722 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1621 14:44:40.391783 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1622 14:44:40.391845 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1623 14:44:40.391905 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1624 14:44:40.391966 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1625 14:44:40.392028 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1626 14:44:40.392088 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1627 14:44:40.392148 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1628 14:44:40.392210 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1629 14:44:40.392271 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1630 14:44:40.392332 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1631 14:44:40.392393 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1632 14:44:40.392454 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1633 14:44:40.392515 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1634 14:44:40.392576 -3, [0] xxxxxxxx xxxxxxxx [MSB]
1635 14:44:40.392637 -2, [0] xxxoxxxx oxxoxxxx [MSB]
1636 14:44:40.392698 -1, [0] xxxoxxxx oxxoxxxx [MSB]
1637 14:44:40.392759 0, [0] xxxoxoxx oxxoxxxx [MSB]
1638 14:44:40.392820 1, [0] xxxoxoxx ooxoooxx [MSB]
1639 14:44:40.392882 2, [0] xxxoxooo ooxoooox [MSB]
1640 14:44:40.392943 3, [0] xxxooooo ooxoooox [MSB]
1641 14:44:40.393004 4, [0] xoxooooo ooxoooox [MSB]
1642 14:44:40.393065 5, [0] oooooooo ooxooooo [MSB]
1643 14:44:40.393125 6, [0] oooooooo ooxooooo [MSB]
1644 14:44:40.393186 33, [0] oooooooo xooooooo [MSB]
1645 14:44:40.393247 34, [0] oooxoooo xooooooo [MSB]
1646 14:44:40.393308 35, [0] oooxoooo xooooooo [MSB]
1647 14:44:40.393370 36, [0] oooxoooo xooxoooo [MSB]
1648 14:44:40.393431 37, [0] oooxoxoo xxoxoxoo [MSB]
1649 14:44:40.393491 38, [0] oooxoxoo xxoxxxxo [MSB]
1650 14:44:40.393552 39, [0] oooxoxox xxoxxxxo [MSB]
1651 14:44:40.393613 40, [0] oooxoxxx xxoxxxxo [MSB]
1652 14:44:40.393674 41, [0] oxxxoxxx xxoxxxxx [MSB]
1653 14:44:40.393735 42, [0] oxxxxxxx xxoxxxxx [MSB]
1654 14:44:40.393795 43, [0] xxxxxxxx xxoxxxxx [MSB]
1655 14:44:40.393857 44, [0] xxxxxxxx xxoxxxxx [MSB]
1656 14:44:40.393918 45, [0] xxxxxxxx xxxxxxxx [MSB]
1657 14:44:40.393978 iDelay=45, Bit 0, Center 23 (5 ~ 42) 38
1658 14:44:40.394045 iDelay=45, Bit 1, Center 22 (4 ~ 40) 37
1659 14:44:40.394111 iDelay=45, Bit 2, Center 22 (5 ~ 40) 36
1660 14:44:40.394172 iDelay=45, Bit 3, Center 15 (-2 ~ 33) 36
1661 14:44:40.394232 iDelay=45, Bit 4, Center 22 (3 ~ 41) 39
1662 14:44:40.394292 iDelay=45, Bit 5, Center 18 (0 ~ 36) 37
1663 14:44:40.394352 iDelay=45, Bit 6, Center 20 (2 ~ 39) 38
1664 14:44:40.394412 iDelay=45, Bit 7, Center 20 (2 ~ 38) 37
1665 14:44:40.394472 iDelay=45, Bit 8, Center 15 (-2 ~ 32) 35
1666 14:44:40.394532 iDelay=45, Bit 9, Center 18 (1 ~ 36) 36
1667 14:44:40.394593 iDelay=45, Bit 10, Center 25 (7 ~ 44) 38
1668 14:44:40.394652 iDelay=45, Bit 11, Center 16 (-2 ~ 35) 38
1669 14:44:40.394713 iDelay=45, Bit 12, Center 19 (1 ~ 37) 37
1670 14:44:40.394773 iDelay=45, Bit 13, Center 18 (1 ~ 36) 36
1671 14:44:40.394833 iDelay=45, Bit 14, Center 19 (2 ~ 37) 36
1672 14:44:40.394893 iDelay=45, Bit 15, Center 22 (5 ~ 40) 36
1673 14:44:40.394953 ==
1674 14:44:40.395012 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1675 14:44:40.395073 fsp= 1, odt_onoff= 1, Byte mode= 0
1676 14:44:40.395134 ==
1677 14:44:40.395194 DQS Delay:
1678 14:44:40.395254 DQS0 = 0, DQS1 = 0
1679 14:44:40.395314 DQM Delay:
1680 14:44:40.395374 DQM0 = 20, DQM1 = 19
1681 14:44:40.395443 DQ Delay:
1682 14:44:40.395504 DQ0 =23, DQ1 =22, DQ2 =22, DQ3 =15
1683 14:44:40.395764 DQ4 =22, DQ5 =18, DQ6 =20, DQ7 =20
1684 14:44:40.395835 DQ8 =15, DQ9 =18, DQ10 =25, DQ11 =16
1685 14:44:40.395898 DQ12 =19, DQ13 =18, DQ14 =19, DQ15 =22
1686 14:44:40.395961
1687 14:44:40.396022
1688 14:44:40.396082 DramC Write-DBI off
1689 14:44:40.396142 ==
1690 14:44:40.396203 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1691 14:44:40.396264 fsp= 1, odt_onoff= 1, Byte mode= 0
1692 14:44:40.396326 ==
1693 14:44:40.396386 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1694 14:44:40.396447
1695 14:44:40.396507 Begin, DQ Scan Range 920~1176
1696 14:44:40.396566
1697 14:44:40.396626
1698 14:44:40.396685 TX Vref Scan disable
1699 14:44:40.396746 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1700 14:44:40.396808 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1701 14:44:40.396869 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1702 14:44:40.396931 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1703 14:44:40.396992 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1704 14:44:40.397053 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1705 14:44:40.397115 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1706 14:44:40.397176 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1707 14:44:40.397237 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1708 14:44:40.397298 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1709 14:44:40.397360 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1710 14:44:40.397421 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1711 14:44:40.397482 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1712 14:44:40.397543 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1713 14:44:40.397604 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1714 14:44:40.397665 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1715 14:44:40.397726 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1716 14:44:40.397787 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1717 14:44:40.397847 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1718 14:44:40.397908 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1719 14:44:40.397969 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1720 14:44:40.398030 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1721 14:44:40.398091 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1722 14:44:40.398152 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1723 14:44:40.398213 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1724 14:44:40.398274 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1725 14:44:40.398336 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1726 14:44:40.398397 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1727 14:44:40.398458 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1728 14:44:40.398520 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1729 14:44:40.398581 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1730 14:44:40.398642 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1731 14:44:40.398704 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1732 14:44:40.398765 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1733 14:44:40.398825 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1734 14:44:40.398886 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1735 14:44:40.398981 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1736 14:44:40.399079 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1737 14:44:40.399177 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1738 14:44:40.399273 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1739 14:44:40.399369 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1740 14:44:40.399458 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1741 14:44:40.399521 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1742 14:44:40.399583 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1743 14:44:40.399645 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1744 14:44:40.399705 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1745 14:44:40.399767 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1746 14:44:40.399828 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1747 14:44:40.399889 968 |3 6 8|[0] xxxxxxxx oxxoxxxx [MSB]
1748 14:44:40.399950 969 |3 6 9|[0] xxxxxxxx ooxooxxx [MSB]
1749 14:44:40.400010 970 |3 6 10|[0] xxxxxxxx ooxoooox [MSB]
1750 14:44:40.400072 971 |3 6 11|[0] xxxxxxxx ooxoooox [MSB]
1751 14:44:40.400133 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB]
1752 14:44:40.400194 973 |3 6 13|[0] xxxooooo ooxoooox [MSB]
1753 14:44:40.400255 974 |3 6 14|[0] xoxooooo ooxooooo [MSB]
1754 14:44:40.400317 975 |3 6 15|[0] xoxooooo oooooooo [MSB]
1755 14:44:40.400379 987 |3 6 27|[0] oooooooo xooooooo [MSB]
1756 14:44:40.400440 988 |3 6 28|[0] oooooooo xxxxxxxx [MSB]
1757 14:44:40.400502 989 |3 6 29|[0] oooxoooo xxxxxxxx [MSB]
1758 14:44:40.400563 990 |3 6 30|[0] oooxoooo xxxxxxxx [MSB]
1759 14:44:40.400624 991 |3 6 31|[0] oooxoxoo xxxxxxxx [MSB]
1760 14:44:40.400686 992 |3 6 32|[0] xxxxxxxx xxxxxxxx [MSB]
1761 14:44:40.400749 Byte0, DQ PI dly=981, DQM PI dly= 981
1762 14:44:40.400809 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
1763 14:44:40.400870
1764 14:44:40.400930 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
1765 14:44:40.400991
1766 14:44:40.401050 Byte1, DQ PI dly=979, DQM PI dly= 979
1767 14:44:40.401110 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
1768 14:44:40.401170
1769 14:44:40.401230 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
1770 14:44:40.401291
1771 14:44:40.401351 ==
1772 14:44:40.401410 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1773 14:44:40.401471 fsp= 1, odt_onoff= 1, Byte mode= 0
1774 14:44:40.401531 ==
1775 14:44:40.401591 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1776 14:44:40.401651
1777 14:44:40.401710 Begin, DQ Scan Range 955~1019
1778 14:44:40.401770 Write Rank1 MR14 =0x0
1779 14:44:40.401830
1780 14:44:40.401890 CH=0, VrefRange= 0, VrefLevel = 0
1781 14:44:40.401950 TX Bit0 (977~991) 15 984, Bit8 (969~982) 14 975,
1782 14:44:40.402010 TX Bit1 (977~988) 12 982, Bit9 (971~984) 14 977,
1783 14:44:40.402071 TX Bit2 (977~989) 13 983, Bit10 (977~985) 9 981,
1784 14:44:40.402131 TX Bit3 (971~982) 12 976, Bit11 (971~983) 13 977,
1785 14:44:40.402191 TX Bit4 (976~988) 13 982, Bit12 (973~985) 13 979,
1786 14:44:40.402252 TX Bit5 (973~984) 12 978, Bit13 (975~983) 9 979,
1787 14:44:40.402313 TX Bit6 (975~987) 13 981, Bit14 (974~985) 12 979,
1788 14:44:40.402373 TX Bit7 (976~989) 14 982, Bit15 (976~985) 10 980,
1789 14:44:40.402433
1790 14:44:40.402493 Write Rank1 MR14 =0x2
1791 14:44:40.402553
1792 14:44:40.402612 CH=0, VrefRange= 0, VrefLevel = 2
1793 14:44:40.402673 TX Bit0 (977~991) 15 984, Bit8 (969~983) 15 976,
1794 14:44:40.402733 TX Bit1 (976~988) 13 982, Bit9 (970~985) 16 977,
1795 14:44:40.402794 TX Bit2 (977~990) 14 983, Bit10 (976~990) 15 983,
1796 14:44:40.402855 TX Bit3 (970~983) 14 976, Bit11 (970~983) 14 976,
1797 14:44:40.403114 TX Bit4 (976~988) 13 982, Bit12 (973~985) 13 979,
1798 14:44:40.403182 TX Bit5 (973~986) 14 979, Bit13 (974~983) 10 978,
1799 14:44:40.403245 TX Bit6 (974~987) 14 980, Bit14 (974~985) 12 979,
1800 14:44:40.403306 TX Bit7 (975~990) 16 982, Bit15 (976~990) 15 983,
1801 14:44:40.403367
1802 14:44:40.403443 Write Rank1 MR14 =0x4
1803 14:44:40.403505
1804 14:44:40.403565 CH=0, VrefRange= 0, VrefLevel = 4
1805 14:44:40.403626 TX Bit0 (977~991) 15 984, Bit8 (969~983) 15 976,
1806 14:44:40.403687 TX Bit1 (976~990) 15 983, Bit9 (970~985) 16 977,
1807 14:44:40.403748 TX Bit2 (977~991) 15 984, Bit10 (976~990) 15 983,
1808 14:44:40.403810 TX Bit3 (970~984) 15 977, Bit11 (969~984) 16 976,
1809 14:44:40.403870 TX Bit4 (975~990) 16 982, Bit12 (972~986) 15 979,
1810 14:44:40.403930 TX Bit5 (972~986) 15 979, Bit13 (973~984) 12 978,
1811 14:44:40.403991 TX Bit6 (973~989) 17 981, Bit14 (973~986) 14 979,
1812 14:44:40.404052 TX Bit7 (975~990) 16 982, Bit15 (976~990) 15 983,
1813 14:44:40.404112
1814 14:44:40.404171 Write Rank1 MR14 =0x6
1815 14:44:40.404230
1816 14:44:40.404290 CH=0, VrefRange= 0, VrefLevel = 6
1817 14:44:40.404350 TX Bit0 (976~992) 17 984, Bit8 (969~984) 16 976,
1818 14:44:40.404411 TX Bit1 (976~990) 15 983, Bit9 (970~986) 17 978,
1819 14:44:40.404471 TX Bit2 (977~991) 15 984, Bit10 (976~991) 16 983,
1820 14:44:40.404532 TX Bit3 (969~984) 16 976, Bit11 (969~984) 16 976,
1821 14:44:40.404593 TX Bit4 (975~991) 17 983, Bit12 (972~987) 16 979,
1822 14:44:40.404653 TX Bit5 (972~987) 16 979, Bit13 (973~984) 12 978,
1823 14:44:40.404713 TX Bit6 (973~990) 18 981, Bit14 (972~987) 16 979,
1824 14:44:40.404773 TX Bit7 (974~991) 18 982, Bit15 (975~991) 17 983,
1825 14:44:40.404834
1826 14:44:40.404894 Write Rank1 MR14 =0x8
1827 14:44:40.404953
1828 14:44:40.405013 CH=0, VrefRange= 0, VrefLevel = 8
1829 14:44:40.405073 TX Bit0 (976~993) 18 984, Bit8 (969~984) 16 976,
1830 14:44:40.405134 TX Bit1 (975~991) 17 983, Bit9 (970~987) 18 978,
1831 14:44:40.405194 TX Bit2 (976~991) 16 983, Bit10 (976~991) 16 983,
1832 14:44:40.405254 TX Bit3 (970~985) 16 977, Bit11 (969~984) 16 976,
1833 14:44:40.405314 TX Bit4 (975~991) 17 983, Bit12 (971~988) 18 979,
1834 14:44:40.405373 TX Bit5 (971~989) 19 980, Bit13 (972~984) 13 978,
1835 14:44:40.405435 TX Bit6 (972~990) 19 981, Bit14 (972~988) 17 980,
1836 14:44:40.405495 TX Bit7 (974~991) 18 982, Bit15 (975~991) 17 983,
1837 14:44:40.405555
1838 14:44:40.405615 Write Rank1 MR14 =0xa
1839 14:44:40.405674
1840 14:44:40.405733 CH=0, VrefRange= 0, VrefLevel = 10
1841 14:44:40.405792 TX Bit0 (976~993) 18 984, Bit8 (968~985) 18 976,
1842 14:44:40.405853 TX Bit1 (975~991) 17 983, Bit9 (969~987) 19 978,
1843 14:44:40.405913 TX Bit2 (976~992) 17 984, Bit10 (976~992) 17 984,
1844 14:44:40.405973 TX Bit3 (969~986) 18 977, Bit11 (969~985) 17 977,
1845 14:44:40.406033 TX Bit4 (974~991) 18 982, Bit12 (970~989) 20 979,
1846 14:44:40.406094 TX Bit5 (971~989) 19 980, Bit13 (971~986) 16 978,
1847 14:44:40.406155 TX Bit6 (972~990) 19 981, Bit14 (971~989) 19 980,
1848 14:44:40.406215 TX Bit7 (973~991) 19 982, Bit15 (974~991) 18 982,
1849 14:44:40.406275
1850 14:44:40.406335 Write Rank1 MR14 =0xc
1851 14:44:40.406394
1852 14:44:40.406453 CH=0, VrefRange= 0, VrefLevel = 12
1853 14:44:40.406512 TX Bit0 (976~993) 18 984, Bit8 (968~985) 18 976,
1854 14:44:40.406572 TX Bit1 (975~992) 18 983, Bit9 (969~989) 21 979,
1855 14:44:40.406632 TX Bit2 (976~992) 17 984, Bit10 (975~992) 18 983,
1856 14:44:40.406693 TX Bit3 (969~987) 19 978, Bit11 (969~986) 18 977,
1857 14:44:40.406753 TX Bit4 (974~992) 19 983, Bit12 (970~989) 20 979,
1858 14:44:40.406813 TX Bit5 (971~990) 20 980, Bit13 (971~986) 16 978,
1859 14:44:40.406873 TX Bit6 (972~991) 20 981, Bit14 (971~989) 19 980,
1860 14:44:40.406933 TX Bit7 (973~992) 20 982, Bit15 (975~992) 18 983,
1861 14:44:40.406994
1862 14:44:40.407053 Write Rank1 MR14 =0xe
1863 14:44:40.407113
1864 14:44:40.407172 CH=0, VrefRange= 0, VrefLevel = 14
1865 14:44:40.407233 TX Bit0 (976~994) 19 985, Bit8 (968~986) 19 977,
1866 14:44:40.407293 TX Bit1 (975~992) 18 983, Bit9 (969~989) 21 979,
1867 14:44:40.407353 TX Bit2 (976~993) 18 984, Bit10 (975~992) 18 983,
1868 14:44:40.407423 TX Bit3 (969~987) 19 978, Bit11 (968~986) 19 977,
1869 14:44:40.407485 TX Bit4 (973~992) 20 982, Bit12 (970~990) 21 980,
1870 14:44:40.407546 TX Bit5 (970~990) 21 980, Bit13 (971~987) 17 979,
1871 14:44:40.407607 TX Bit6 (972~991) 20 981, Bit14 (970~990) 21 980,
1872 14:44:40.407668 TX Bit7 (974~992) 19 983, Bit15 (974~992) 19 983,
1873 14:44:40.407728
1874 14:44:40.407787 Write Rank1 MR14 =0x10
1875 14:44:40.407847
1876 14:44:40.407906 CH=0, VrefRange= 0, VrefLevel = 16
1877 14:44:40.407967 TX Bit0 (976~994) 19 985, Bit8 (967~986) 20 976,
1878 14:44:40.408027 TX Bit1 (974~993) 20 983, Bit9 (969~990) 22 979,
1879 14:44:40.408087 TX Bit2 (976~993) 18 984, Bit10 (975~992) 18 983,
1880 14:44:40.408148 TX Bit3 (968~987) 20 977, Bit11 (968~986) 19 977,
1881 14:44:40.408208 TX Bit4 (973~993) 21 983, Bit12 (969~990) 22 979,
1882 14:44:40.408269 TX Bit5 (970~991) 22 980, Bit13 (971~988) 18 979,
1883 14:44:40.408328 TX Bit6 (971~992) 22 981, Bit14 (970~990) 21 980,
1884 14:44:40.408388 TX Bit7 (972~993) 22 982, Bit15 (974~993) 20 983,
1885 14:44:40.408449
1886 14:44:40.408509 Write Rank1 MR14 =0x12
1887 14:44:40.408568
1888 14:44:40.408627 CH=0, VrefRange= 0, VrefLevel = 18
1889 14:44:40.408688 TX Bit0 (975~995) 21 985, Bit8 (967~987) 21 977,
1890 14:44:40.408748 TX Bit1 (974~993) 20 983, Bit9 (969~990) 22 979,
1891 14:44:40.408809 TX Bit2 (976~994) 19 985, Bit10 (975~993) 19 984,
1892 14:44:40.408869 TX Bit3 (968~987) 20 977, Bit11 (968~988) 21 978,
1893 14:44:40.408930 TX Bit4 (972~993) 22 982, Bit12 (969~990) 22 979,
1894 14:44:40.408990 TX Bit5 (970~991) 22 980, Bit13 (970~989) 20 979,
1895 14:44:40.409051 TX Bit6 (971~992) 22 981, Bit14 (970~991) 22 980,
1896 14:44:40.409111 TX Bit7 (972~993) 22 982, Bit15 (974~993) 20 983,
1897 14:44:40.409171
1898 14:44:40.409425 Write Rank1 MR14 =0x14
1899 14:44:40.409493
1900 14:44:40.409555 CH=0, VrefRange= 0, VrefLevel = 20
1901 14:44:40.409616 TX Bit0 (975~995) 21 985, Bit8 (967~988) 22 977,
1902 14:44:40.409677 TX Bit1 (973~993) 21 983, Bit9 (969~990) 22 979,
1903 14:44:40.409737 TX Bit2 (975~994) 20 984, Bit10 (974~994) 21 984,
1904 14:44:40.409798 TX Bit3 (968~989) 22 978, Bit11 (968~989) 22 978,
1905 14:44:40.409858 TX Bit4 (972~993) 22 982, Bit12 (969~991) 23 980,
1906 14:44:40.409919 TX Bit5 (970~991) 22 980, Bit13 (970~990) 21 980,
1907 14:44:40.553700 TX Bit6 (971~992) 22 981, Bit14 (969~991) 23 980,
1908 14:44:40.553889 TX Bit7 (971~994) 24 982, Bit15 (973~994) 22 983,
1909 14:44:40.554013
1910 14:44:40.554129 Write Rank1 MR14 =0x16
1911 14:44:40.554243
1912 14:44:40.554355 CH=0, VrefRange= 0, VrefLevel = 22
1913 14:44:40.554465 TX Bit0 (975~996) 22 985, Bit8 (967~989) 23 978,
1914 14:44:40.554578 TX Bit1 (973~994) 22 983, Bit9 (968~991) 24 979,
1915 14:44:40.554690 TX Bit2 (975~994) 20 984, Bit10 (974~995) 22 984,
1916 14:44:40.554801 TX Bit3 (968~989) 22 978, Bit11 (968~989) 22 978,
1917 14:44:40.554911 TX Bit4 (972~994) 23 983, Bit12 (969~991) 23 980,
1918 14:44:40.555020 TX Bit5 (969~992) 24 980, Bit13 (970~990) 21 980,
1919 14:44:40.555131 TX Bit6 (970~993) 24 981, Bit14 (969~991) 23 980,
1920 14:44:40.555240 TX Bit7 (971~994) 24 982, Bit15 (972~994) 23 983,
1921 14:44:40.555350
1922 14:44:40.555475 Write Rank1 MR14 =0x18
1923 14:44:40.555586
1924 14:44:40.555696 CH=0, VrefRange= 0, VrefLevel = 24
1925 14:44:40.555807 TX Bit0 (974~997) 24 985, Bit8 (967~990) 24 978,
1926 14:44:40.555917 TX Bit1 (973~994) 22 983, Bit9 (968~991) 24 979,
1927 14:44:40.556027 TX Bit2 (975~995) 21 985, Bit10 (973~996) 24 984,
1928 14:44:40.556137 TX Bit3 (967~990) 24 978, Bit11 (967~990) 24 978,
1929 14:44:40.556245 TX Bit4 (971~994) 24 982, Bit12 (969~991) 23 980,
1930 14:44:40.556354 TX Bit5 (969~992) 24 980, Bit13 (969~990) 22 979,
1931 14:44:40.556462 TX Bit6 (970~993) 24 981, Bit14 (969~992) 24 980,
1932 14:44:40.556571 TX Bit7 (971~994) 24 982, Bit15 (973~995) 23 984,
1933 14:44:40.556680
1934 14:44:40.556787 Write Rank1 MR14 =0x1a
1935 14:44:40.556895
1936 14:44:40.557003 CH=0, VrefRange= 0, VrefLevel = 26
1937 14:44:40.557112 TX Bit0 (974~997) 24 985, Bit8 (966~990) 25 978,
1938 14:44:40.557221 TX Bit1 (972~995) 24 983, Bit9 (968~991) 24 979,
1939 14:44:40.557331 TX Bit2 (975~996) 22 985, Bit10 (973~996) 24 984,
1940 14:44:40.557440 TX Bit3 (967~991) 25 979, Bit11 (967~990) 24 978,
1941 14:44:40.557550 TX Bit4 (971~995) 25 983, Bit12 (968~991) 24 979,
1942 14:44:40.557659 TX Bit5 (969~992) 24 980, Bit13 (969~990) 22 979,
1943 14:44:40.557767 TX Bit6 (970~994) 25 982, Bit14 (969~991) 23 980,
1944 14:44:40.557874 TX Bit7 (971~995) 25 983, Bit15 (972~995) 24 983,
1945 14:44:40.557981
1946 14:44:40.558088 Write Rank1 MR14 =0x1c
1947 14:44:40.558196
1948 14:44:40.558303 CH=0, VrefRange= 0, VrefLevel = 28
1949 14:44:40.558412 TX Bit0 (973~998) 26 985, Bit8 (967~990) 24 978,
1950 14:44:40.558521 TX Bit1 (972~995) 24 983, Bit9 (968~991) 24 979,
1951 14:44:40.558631 TX Bit2 (974~996) 23 985, Bit10 (973~996) 24 984,
1952 14:44:40.558740 TX Bit3 (967~991) 25 979, Bit11 (967~990) 24 978,
1953 14:44:40.558850 TX Bit4 (971~995) 25 983, Bit12 (968~992) 25 980,
1954 14:44:40.558958 TX Bit5 (969~993) 25 981, Bit13 (969~991) 23 980,
1955 14:44:40.559066 TX Bit6 (970~994) 25 982, Bit14 (968~992) 25 980,
1956 14:44:40.559173 TX Bit7 (970~995) 26 982, Bit15 (971~996) 26 983,
1957 14:44:40.559280
1958 14:44:40.559387 Write Rank1 MR14 =0x1e
1959 14:44:40.559502
1960 14:44:40.559610 CH=0, VrefRange= 0, VrefLevel = 30
1961 14:44:40.559717 TX Bit0 (973~998) 26 985, Bit8 (966~990) 25 978,
1962 14:44:40.559825 TX Bit1 (972~996) 25 984, Bit9 (968~991) 24 979,
1963 14:44:40.559934 TX Bit2 (974~997) 24 985, Bit10 (972~997) 26 984,
1964 14:44:40.560044 TX Bit3 (967~991) 25 979, Bit11 (967~991) 25 979,
1965 14:44:40.560152 TX Bit4 (970~996) 27 983, Bit12 (968~992) 25 980,
1966 14:44:40.560261 TX Bit5 (969~993) 25 981, Bit13 (969~991) 23 980,
1967 14:44:40.560369 TX Bit6 (969~994) 26 981, Bit14 (968~992) 25 980,
1968 14:44:40.560477 TX Bit7 (970~996) 27 983, Bit15 (970~996) 27 983,
1969 14:44:40.560584
1970 14:44:40.560690 Write Rank1 MR14 =0x20
1971 14:44:40.560797
1972 14:44:40.560904 CH=0, VrefRange= 0, VrefLevel = 32
1973 14:44:40.561011 TX Bit0 (973~998) 26 985, Bit8 (966~990) 25 978,
1974 14:44:40.561120 TX Bit1 (972~996) 25 984, Bit9 (968~991) 24 979,
1975 14:44:40.561230 TX Bit2 (974~997) 24 985, Bit10 (972~997) 26 984,
1976 14:44:40.561338 TX Bit3 (967~991) 25 979, Bit11 (967~991) 25 979,
1977 14:44:40.561445 TX Bit4 (970~996) 27 983, Bit12 (968~992) 25 980,
1978 14:44:40.561552 TX Bit5 (969~993) 25 981, Bit13 (969~991) 23 980,
1979 14:44:40.561661 TX Bit6 (969~994) 26 981, Bit14 (968~992) 25 980,
1980 14:44:40.561770 TX Bit7 (970~996) 27 983, Bit15 (970~996) 27 983,
1981 14:44:40.561878
1982 14:44:40.561984 Write Rank1 MR14 =0x22
1983 14:44:40.562091
1984 14:44:40.562198 CH=0, VrefRange= 0, VrefLevel = 34
1985 14:44:40.562306 TX Bit0 (973~998) 26 985, Bit8 (966~990) 25 978,
1986 14:44:40.562415 TX Bit1 (972~996) 25 984, Bit9 (968~991) 24 979,
1987 14:44:40.562522 TX Bit2 (974~997) 24 985, Bit10 (972~997) 26 984,
1988 14:44:40.562629 TX Bit3 (967~991) 25 979, Bit11 (967~991) 25 979,
1989 14:44:40.562738 TX Bit4 (970~996) 27 983, Bit12 (968~992) 25 980,
1990 14:44:40.562846 TX Bit5 (969~993) 25 981, Bit13 (969~991) 23 980,
1991 14:44:40.562954 TX Bit6 (969~994) 26 981, Bit14 (968~992) 25 980,
1992 14:44:40.563064 TX Bit7 (970~996) 27 983, Bit15 (970~996) 27 983,
1993 14:44:40.563171
1994 14:44:40.563278 Write Rank1 MR14 =0x24
1995 14:44:40.563384
1996 14:44:40.563497 CH=0, VrefRange= 0, VrefLevel = 36
1997 14:44:40.563606 TX Bit0 (973~998) 26 985, Bit8 (966~990) 25 978,
1998 14:44:40.563717 TX Bit1 (972~996) 25 984, Bit9 (968~991) 24 979,
1999 14:44:40.564050 TX Bit2 (974~997) 24 985, Bit10 (972~997) 26 984,
2000 14:44:40.564171 TX Bit3 (967~991) 25 979, Bit11 (967~991) 25 979,
2001 14:44:40.564286 TX Bit4 (970~996) 27 983, Bit12 (968~992) 25 980,
2002 14:44:40.564398 TX Bit5 (969~993) 25 981, Bit13 (969~991) 23 980,
2003 14:44:40.564508 TX Bit6 (969~994) 26 981, Bit14 (968~992) 25 980,
2004 14:44:40.564618 TX Bit7 (970~996) 27 983, Bit15 (970~996) 27 983,
2005 14:44:40.564727
2006 14:44:40.564833 Write Rank1 MR14 =0x26
2007 14:44:40.564941
2008 14:44:40.565047 CH=0, VrefRange= 0, VrefLevel = 38
2009 14:44:40.565155 TX Bit0 (973~998) 26 985, Bit8 (966~990) 25 978,
2010 14:44:40.565264 TX Bit1 (972~996) 25 984, Bit9 (968~991) 24 979,
2011 14:44:40.565374 TX Bit2 (974~997) 24 985, Bit10 (972~997) 26 984,
2012 14:44:40.565483 TX Bit3 (967~991) 25 979, Bit11 (967~991) 25 979,
2013 14:44:40.565593 TX Bit4 (970~996) 27 983, Bit12 (968~992) 25 980,
2014 14:44:40.565702 TX Bit5 (969~993) 25 981, Bit13 (969~991) 23 980,
2015 14:44:40.565810 TX Bit6 (969~994) 26 981, Bit14 (968~992) 25 980,
2016 14:44:40.565919 TX Bit7 (970~996) 27 983, Bit15 (970~996) 27 983,
2017 14:44:40.566027
2018 14:44:40.566134
2019 14:44:40.566239 TX Vref found, early break! 378< 384
2020 14:44:40.566348 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
2021 14:44:40.566432 u1DelayCellOfst[0]=7 cells (6 PI)
2022 14:44:40.566517 u1DelayCellOfst[1]=6 cells (5 PI)
2023 14:44:40.566599 u1DelayCellOfst[2]=7 cells (6 PI)
2024 14:44:40.566682 u1DelayCellOfst[3]=0 cells (0 PI)
2025 14:44:40.566764 u1DelayCellOfst[4]=5 cells (4 PI)
2026 14:44:40.566869 u1DelayCellOfst[5]=2 cells (2 PI)
2027 14:44:40.566973 u1DelayCellOfst[6]=2 cells (2 PI)
2028 14:44:40.567077 u1DelayCellOfst[7]=5 cells (4 PI)
2029 14:44:40.567181 Byte0, DQ PI dly=979, DQM PI dly= 982
2030 14:44:40.567285 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
2031 14:44:40.567390
2032 14:44:40.567502 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
2033 14:44:40.567608
2034 14:44:40.567712 u1DelayCellOfst[8]=0 cells (0 PI)
2035 14:44:40.567815 u1DelayCellOfst[9]=1 cells (1 PI)
2036 14:44:40.567919 u1DelayCellOfst[10]=7 cells (6 PI)
2037 14:44:40.568022 u1DelayCellOfst[11]=1 cells (1 PI)
2038 14:44:40.568125 u1DelayCellOfst[12]=2 cells (2 PI)
2039 14:44:40.568227 u1DelayCellOfst[13]=2 cells (2 PI)
2040 14:44:40.568330 u1DelayCellOfst[14]=2 cells (2 PI)
2041 14:44:40.568433 u1DelayCellOfst[15]=6 cells (5 PI)
2042 14:44:40.568536 Byte1, DQ PI dly=978, DQM PI dly= 981
2043 14:44:40.568639 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
2044 14:44:40.568743
2045 14:44:40.568846 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
2046 14:44:40.568951
2047 14:44:40.569054 Write Rank1 MR14 =0x1e
2048 14:44:40.569157
2049 14:44:40.569260 Final TX Range 0 Vref 30
2050 14:44:40.569364
2051 14:44:40.569467 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2052 14:44:40.569571
2053 14:44:40.569674 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2054 14:44:40.569779 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2055 14:44:40.569884 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2056 14:44:40.569988 Write Rank1 MR3 =0xb0
2057 14:44:40.570091 DramC Write-DBI on
2058 14:44:40.570194 ==
2059 14:44:40.570298 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2060 14:44:40.570401 fsp= 1, odt_onoff= 1, Byte mode= 0
2061 14:44:40.570505 ==
2062 14:44:40.570608 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2063 14:44:40.570712
2064 14:44:40.570815 Begin, DQ Scan Range 701~765
2065 14:44:40.570918
2066 14:44:40.571021
2067 14:44:40.571123 TX Vref Scan disable
2068 14:44:40.571226 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2069 14:44:40.571332 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2070 14:44:40.571447 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2071 14:44:40.571555 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2072 14:44:40.571662 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2073 14:44:40.571769 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2074 14:44:40.571875 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2075 14:44:40.571981 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2076 14:44:40.572087 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2077 14:44:40.572193 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2078 14:44:40.572299 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2079 14:44:40.572404 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2080 14:44:40.572510 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2081 14:44:40.572615 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2082 14:44:40.572721 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
2083 14:44:40.572825 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2084 14:44:40.572931 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2085 14:44:40.573037 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2086 14:44:40.573143 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2087 14:44:40.573248 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2088 14:44:40.573353 742 |2 6 38|[0] xxxxxxxx xxxxxxxx [MSB]
2089 14:44:40.573459 Byte0, DQ PI dly=728, DQM PI dly= 728
2090 14:44:40.573562 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 24)
2091 14:44:40.573665
2092 14:44:40.573768 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 24)
2093 14:44:40.573871
2094 14:44:40.573974 Byte1, DQ PI dly=723, DQM PI dly= 723
2095 14:44:40.574077 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 19)
2096 14:44:40.574180
2097 14:44:40.574282 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 19)
2098 14:44:40.574386
2099 14:44:40.574489 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2100 14:44:40.574592 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2101 14:44:40.574696 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2102 14:44:40.574799 Write Rank1 MR3 =0x30
2103 14:44:40.574901 DramC Write-DBI off
2104 14:44:40.575004
2105 14:44:40.575106 [DATLAT]
2106 14:44:40.575208 Freq=1600, CH0 RK1, use_rxtx_scan=0
2107 14:44:40.575311
2108 14:44:40.575419 DATLAT Default: 0x10
2109 14:44:40.575523 7, 0xFFFF, sum=0
2110 14:44:40.575628 8, 0xFFFF, sum=0
2111 14:44:40.575733 9, 0xFFFF, sum=0
2112 14:44:40.575839 10, 0xFFFF, sum=0
2113 14:44:40.575944 11, 0xFFFF, sum=0
2114 14:44:40.576049 12, 0xFFFF, sum=0
2115 14:44:40.576154 13, 0xFFFF, sum=0
2116 14:44:40.576260 14, 0x0, sum=1
2117 14:44:40.576365 15, 0x0, sum=2
2118 14:44:40.576470 16, 0x0, sum=3
2119 14:44:40.576574 17, 0x0, sum=4
2120 14:44:40.576679 pattern=2 first_step=14 total pass=5 best_step=16
2121 14:44:40.576782 ==
2122 14:44:40.577089 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2123 14:44:40.577195 fsp= 1, odt_onoff= 1, Byte mode= 0
2124 14:44:40.577303 ==
2125 14:44:40.577413 Start DQ dly to find pass range UseTestEngine =1
2126 14:44:40.577513 x-axis: bit #, y-axis: DQ dly (-127~63)
2127 14:44:40.577609 RX Vref Scan = 0
2128 14:44:40.577704 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2129 14:44:40.577802 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2130 14:44:40.577901 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2131 14:44:40.578006 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2132 14:44:40.578112 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2133 14:44:40.578217 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2134 14:44:40.578323 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2135 14:44:40.578429 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2136 14:44:40.578534 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2137 14:44:40.578638 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2138 14:44:40.578743 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2139 14:44:40.578849 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2140 14:44:40.578954 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2141 14:44:40.579059 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2142 14:44:40.579164 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2143 14:44:40.579268 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2144 14:44:40.579373 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2145 14:44:40.579488 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2146 14:44:40.579574 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2147 14:44:40.579660 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2148 14:44:40.579744 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2149 14:44:40.579827 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2150 14:44:40.579933 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2151 14:44:40.580038 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2152 14:44:40.580143 -2, [0] xxxoxxxx oxxoxxxx [MSB]
2153 14:44:40.580248 -1, [0] xxxoxxxx oxxoxxxx [MSB]
2154 14:44:40.580354 0, [0] xxxoxxxx oxxoxxxx [MSB]
2155 14:44:40.580459 1, [0] xxxoxoxx ooxoooxx [MSB]
2156 14:44:40.580565 2, [0] xxxoxoxx ooxoooxx [MSB]
2157 14:44:40.580671 3, [0] xxxoxooo ooxoooox [MSB]
2158 14:44:40.580777 4, [0] xxxoxooo ooxoooox [MSB]
2159 14:44:40.580886 5, [0] xoxooooo ooxoooox [MSB]
2160 14:44:40.580993 6, [0] oooooooo ooxooooo [MSB]
2161 14:44:40.581099 33, [0] oooooooo xooooooo [MSB]
2162 14:44:40.581205 34, [0] oooxoooo xooooooo [MSB]
2163 14:44:40.581311 35, [0] oooxoxoo xooxoooo [MSB]
2164 14:44:40.581417 36, [0] oooxoxoo xooxoxoo [MSB]
2165 14:44:40.581523 37, [0] oooxoxoo xxoxoxoo [MSB]
2166 14:44:40.581628 38, [0] oooxoxxo xxoxxxxo [MSB]
2167 14:44:40.581733 39, [0] oxxxoxxx xxoxxxxo [MSB]
2168 14:44:40.581838 40, [0] oxxxxxxx xxoxxxxx [MSB]
2169 14:44:40.581943 41, [0] xxxxxxxx xxoxxxxx [MSB]
2170 14:44:40.582048 42, [0] xxxxxxxx xxoxxxxx [MSB]
2171 14:44:40.582153 43, [0] xxxxxxxx xxoxxxxx [MSB]
2172 14:44:40.582258 44, [0] xxxxxxxx xxxxxxxx [MSB]
2173 14:44:40.582364 iDelay=44, Bit 0, Center 23 (6 ~ 40) 35
2174 14:44:40.582466 iDelay=44, Bit 1, Center 21 (5 ~ 38) 34
2175 14:44:40.582570 iDelay=44, Bit 2, Center 22 (6 ~ 38) 33
2176 14:44:40.582673 iDelay=44, Bit 3, Center 15 (-2 ~ 33) 36
2177 14:44:40.582775 iDelay=44, Bit 4, Center 22 (5 ~ 39) 35
2178 14:44:40.582878 iDelay=44, Bit 5, Center 17 (1 ~ 34) 34
2179 14:44:40.582981 iDelay=44, Bit 6, Center 20 (3 ~ 37) 35
2180 14:44:40.583084 iDelay=44, Bit 7, Center 20 (3 ~ 38) 36
2181 14:44:40.583186 iDelay=44, Bit 8, Center 15 (-2 ~ 32) 35
2182 14:44:40.583289 iDelay=44, Bit 9, Center 18 (1 ~ 36) 36
2183 14:44:40.583392 iDelay=44, Bit 10, Center 25 (7 ~ 43) 37
2184 14:44:40.583500 iDelay=44, Bit 11, Center 16 (-2 ~ 34) 37
2185 14:44:40.583604 iDelay=44, Bit 12, Center 19 (1 ~ 37) 37
2186 14:44:40.583706 iDelay=44, Bit 13, Center 18 (1 ~ 35) 35
2187 14:44:40.583809 iDelay=44, Bit 14, Center 20 (3 ~ 37) 35
2188 14:44:40.583911 iDelay=44, Bit 15, Center 22 (6 ~ 39) 34
2189 14:44:40.584014 ==
2190 14:44:40.584117 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2191 14:44:40.584221 fsp= 1, odt_onoff= 1, Byte mode= 0
2192 14:44:40.584325 ==
2193 14:44:40.584428 DQS Delay:
2194 14:44:40.584530 DQS0 = 0, DQS1 = 0
2195 14:44:40.584633 DQM Delay:
2196 14:44:40.584736 DQM0 = 20, DQM1 = 19
2197 14:44:40.584838 DQ Delay:
2198 14:44:40.584941 DQ0 =23, DQ1 =21, DQ2 =22, DQ3 =15
2199 14:44:40.585043 DQ4 =22, DQ5 =17, DQ6 =20, DQ7 =20
2200 14:44:40.585147 DQ8 =15, DQ9 =18, DQ10 =25, DQ11 =16
2201 14:44:40.585250 DQ12 =19, DQ13 =18, DQ14 =20, DQ15 =22
2202 14:44:40.585352
2203 14:44:40.585455
2204 14:44:40.585557
2205 14:44:40.585659 [DramC_TX_OE_Calibration] TA2
2206 14:44:40.585761 Original DQ_B0 (3 6) =30, OEN = 27
2207 14:44:40.585883 Original DQ_B1 (3 6) =30, OEN = 27
2208 14:44:40.585988 23, 0x0, End_B0=23 End_B1=23
2209 14:44:40.586095 24, 0x0, End_B0=24 End_B1=24
2210 14:44:40.586203 25, 0x0, End_B0=25 End_B1=25
2211 14:44:40.589401 26, 0x0, End_B0=26 End_B1=26
2212 14:44:40.592592 27, 0x0, End_B0=27 End_B1=27
2213 14:44:40.596316 28, 0x0, End_B0=28 End_B1=28
2214 14:44:40.599350 29, 0x0, End_B0=29 End_B1=29
2215 14:44:40.599457 30, 0x0, End_B0=30 End_B1=30
2216 14:44:40.602234 31, 0xFFFF, End_B0=30 End_B1=30
2217 14:44:40.609225 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2218 14:44:40.612794 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2219 14:44:40.615878
2220 14:44:40.615972
2221 14:44:40.616069 Write Rank1 MR23 =0x3f
2222 14:44:40.616160 [DQSOSC]
2223 14:44:40.625837 [DQSOSCAuto] RK1, (LSB)MR18= 0xd8d8, (MSB)MR19= 0x202, tDQSOscB0 = 432 ps tDQSOscB1 = 432 ps
2224 14:44:40.632858 CH0_RK1: MR19=0x202, MR18=0xD8D8, DQSOSC=432, MR23=63, INC=13, DEC=19
2225 14:44:40.632954 Write Rank1 MR23 =0x3f
2226 14:44:40.635790 [DQSOSC]
2227 14:44:40.642776 [DQSOSCAuto] RK1, (LSB)MR18= 0xdbdb, (MSB)MR19= 0x202, tDQSOscB0 = 430 ps tDQSOscB1 = 430 ps
2228 14:44:40.645867 CH0 RK1: MR19=202, MR18=DBDB
2229 14:44:40.649171 [RxdqsGatingPostProcess] freq 1600
2230 14:44:40.652783 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2231 14:44:40.656169 Rank: 0
2232 14:44:40.656264 best DQS0 dly(2T, 0.5T) = (2, 5)
2233 14:44:40.658978 best DQS1 dly(2T, 0.5T) = (2, 5)
2234 14:44:40.662547 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
2235 14:44:40.666241 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
2236 14:44:40.669010 Rank: 1
2237 14:44:40.669105 best DQS0 dly(2T, 0.5T) = (2, 6)
2238 14:44:40.672512 best DQS1 dly(2T, 0.5T) = (2, 6)
2239 14:44:40.676051 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2240 14:44:40.679523 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2241 14:44:40.685771 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2242 14:44:40.689200 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2243 14:44:40.692400 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2244 14:44:40.696018 Write Rank0 MR13 =0x59
2245 14:44:40.696113 ==
2246 14:44:40.699106 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2247 14:44:40.702512 fsp= 1, odt_onoff= 1, Byte mode= 0
2248 14:44:40.702607 ==
2249 14:44:40.705671 === u2Vref_new: 0x56 --> 0x3a
2250 14:44:40.709297 === u2Vref_new: 0x58 --> 0x58
2251 14:44:40.712812 === u2Vref_new: 0x5a --> 0x5a
2252 14:44:40.715743 === u2Vref_new: 0x5c --> 0x78
2253 14:44:40.719215 === u2Vref_new: 0x5e --> 0x7a
2254 14:44:40.723100 === u2Vref_new: 0x60 --> 0x90
2255 14:44:40.726184 [CA 0] Center 38 (13~63) winsize 51
2256 14:44:40.729119 [CA 1] Center 37 (12~63) winsize 52
2257 14:44:40.732702 [CA 2] Center 34 (6~63) winsize 58
2258 14:44:40.735833 [CA 3] Center 34 (6~63) winsize 58
2259 14:44:40.735919 [CA 4] Center 34 (6~63) winsize 58
2260 14:44:40.739102 [CA 5] Center 28 (-2~59) winsize 62
2261 14:44:40.739187
2262 14:44:40.746258 [CATrainingPosCal] consider 1 rank data
2263 14:44:40.746350 u2DelayCellTimex100 = 735/100 ps
2264 14:44:40.752509 CA0 delay=38 (13~63),Diff = 10 PI (13 cell)
2265 14:44:40.756444 CA1 delay=37 (12~63),Diff = 9 PI (11 cell)
2266 14:44:40.759537 CA2 delay=34 (6~63),Diff = 6 PI (7 cell)
2267 14:44:40.762865 CA3 delay=34 (6~63),Diff = 6 PI (7 cell)
2268 14:44:40.765864 CA4 delay=34 (6~63),Diff = 6 PI (7 cell)
2269 14:44:40.769212 CA5 delay=28 (-2~59),Diff = 0 PI (0 cell)
2270 14:44:40.769298
2271 14:44:40.772608 CA PerBit enable=1, Macro0, CA PI delay=28
2272 14:44:40.776196 === u2Vref_new: 0x5e --> 0x7a
2273 14:44:40.776298
2274 14:44:40.779127 Vref(ca) range 1: 30
2275 14:44:40.779222
2276 14:44:40.779337 CS Dly= 11 (42-0-32)
2277 14:44:40.782794 Write Rank0 MR13 =0xd8
2278 14:44:40.786083 Write Rank0 MR13 =0xd8
2279 14:44:40.786178 Write Rank0 MR12 =0x5e
2280 14:44:40.789159 Write Rank1 MR13 =0x59
2281 14:44:40.789254 ==
2282 14:44:40.792754 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2283 14:44:40.796112 fsp= 1, odt_onoff= 1, Byte mode= 0
2284 14:44:40.796208 ==
2285 14:44:40.799706 === u2Vref_new: 0x56 --> 0x3a
2286 14:44:40.802820 === u2Vref_new: 0x58 --> 0x58
2287 14:44:40.805943 === u2Vref_new: 0x5a --> 0x5a
2288 14:44:40.809596 === u2Vref_new: 0x5c --> 0x78
2289 14:44:40.812969 === u2Vref_new: 0x5e --> 0x7a
2290 14:44:40.816233 === u2Vref_new: 0x60 --> 0x90
2291 14:44:40.819071 [CA 0] Center 37 (12~63) winsize 52
2292 14:44:40.822594 [CA 1] Center 37 (12~63) winsize 52
2293 14:44:40.826081 [CA 2] Center 34 (6~63) winsize 58
2294 14:44:40.829342 [CA 3] Center 34 (6~63) winsize 58
2295 14:44:40.833216 [CA 4] Center 34 (6~63) winsize 58
2296 14:44:40.836066 [CA 5] Center 27 (-2~57) winsize 60
2297 14:44:40.836158
2298 14:44:40.839612 [CATrainingPosCal] consider 2 rank data
2299 14:44:40.842503 u2DelayCellTimex100 = 735/100 ps
2300 14:44:40.845893 CA0 delay=38 (13~63),Diff = 11 PI (14 cell)
2301 14:44:40.849934 CA1 delay=37 (12~63),Diff = 10 PI (13 cell)
2302 14:44:40.852684 CA2 delay=34 (6~63),Diff = 7 PI (9 cell)
2303 14:44:40.856049 CA3 delay=34 (6~63),Diff = 7 PI (9 cell)
2304 14:44:40.859630 CA4 delay=34 (6~63),Diff = 7 PI (9 cell)
2305 14:44:40.863109 CA5 delay=27 (-2~57),Diff = 0 PI (0 cell)
2306 14:44:40.863200
2307 14:44:40.869400 CA PerBit enable=1, Macro0, CA PI delay=27
2308 14:44:40.869492 === u2Vref_new: 0x60 --> 0x90
2309 14:44:40.869567
2310 14:44:40.873133 Vref(ca) range 1: 32
2311 14:44:40.873225
2312 14:44:40.876186 CS Dly= 11 (42-0-32)
2313 14:44:40.876277 Write Rank1 MR13 =0xd8
2314 14:44:40.879419 Write Rank1 MR13 =0xd8
2315 14:44:40.879510 Write Rank1 MR12 =0x60
2316 14:44:40.883283 [RankSwap] Rank num 2, (Multi 1), Rank 0
2317 14:44:40.886363 Write Rank0 MR2 =0xad
2318 14:44:40.889607 [Write Leveling]
2319 14:44:40.889699 delay byte0 byte1 byte2 byte3
2320 14:44:40.889772
2321 14:44:40.893010 10 0 0
2322 14:44:40.893102 11 0 0
2323 14:44:40.896686 12 0 0
2324 14:44:40.896779 13 0 0
2325 14:44:40.899789 14 0 0
2326 14:44:40.899881 15 0 0
2327 14:44:40.899955 16 0 0
2328 14:44:40.903072 17 0 0
2329 14:44:40.903165 18 0 0
2330 14:44:40.906162 19 0 0
2331 14:44:40.906255 20 0 0
2332 14:44:40.906329 21 0 0
2333 14:44:40.909698 22 0 0
2334 14:44:40.909790 23 0 0
2335 14:44:40.913183 24 0 ff
2336 14:44:40.913276 25 0 ff
2337 14:44:40.916253 26 0 ff
2338 14:44:40.916346 27 0 ff
2339 14:44:40.916420 28 0 ff
2340 14:44:40.919913 29 0 ff
2341 14:44:40.920005 30 0 ff
2342 14:44:40.923094 31 0 ff
2343 14:44:40.923187 32 0 ff
2344 14:44:40.926710 33 ff ff
2345 14:44:40.926802 34 ff ff
2346 14:44:40.929485 35 ff ff
2347 14:44:40.929578 36 ff ff
2348 14:44:40.933190 37 ff ff
2349 14:44:40.933283 38 ff ff
2350 14:44:40.936214 39 ff ff
2351 14:44:40.939428 pass bytecount = 0xff (0xff: all bytes pass)
2352 14:44:40.939519
2353 14:44:40.939592 DQS0 dly: 33
2354 14:44:40.939660 DQS1 dly: 24
2355 14:44:40.942782 Write Rank0 MR2 =0x2d
2356 14:44:40.946313 [RankSwap] Rank num 2, (Multi 1), Rank 0
2357 14:44:40.949713 Write Rank0 MR1 =0xd6
2358 14:44:40.949804 [Gating]
2359 14:44:40.949877 ==
2360 14:44:40.956389 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2361 14:44:40.959438 fsp= 1, odt_onoff= 1, Byte mode= 0
2362 14:44:40.959531 ==
2363 14:44:40.962874 3 1 0 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
2364 14:44:40.966355 3 1 4 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
2365 14:44:40.972782 3 1 8 |3534 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
2366 14:44:40.976198 3 1 12 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
2367 14:44:40.979722 3 1 16 |3534 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
2368 14:44:40.983138 3 1 20 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2369 14:44:40.989433 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2370 14:44:40.992729 3 1 28 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2371 14:44:40.996008 3 2 0 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2372 14:44:41.002909 3 2 4 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2373 14:44:41.006398 3 2 8 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2374 14:44:41.009336 3 2 12 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2375 14:44:41.016196 3 2 16 |201 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2376 14:44:41.019319 3 2 20 |e0e 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2377 14:44:41.022663 3 2 24 |3d3d 2c2c |(11 11)(11 0) |(1 1)(0 0)| 0
2378 14:44:41.029284 3 2 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2379 14:44:41.032636 3 3 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2380 14:44:41.036346 3 3 4 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2381 14:44:41.039610 3 3 8 |1e1e 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2382 14:44:41.046221 3 3 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2383 14:44:41.049645 3 3 16 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2384 14:44:41.053013 3 3 20 |201 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2385 14:44:41.059734 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2386 14:44:41.063041 [Byte 0] Lead/lag falling Transition (3, 3, 24)
2387 14:44:41.066543 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
2388 14:44:41.070161 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
2389 14:44:41.076790 [Byte 1] Lead/lag Transition tap number (1)
2390 14:44:41.079728 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2391 14:44:41.083090 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2392 14:44:41.089724 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2393 14:44:41.093258 3 4 16 |b0a 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2394 14:44:41.096563 3 4 20 |e0d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2395 14:44:41.099554 3 4 24 |3d3d 1413 |(11 11)(11 11) |(1 1)(1 1)| 0
2396 14:44:41.106535 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2397 14:44:41.109819 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2398 14:44:41.113076 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2399 14:44:41.119551 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2400 14:44:41.122927 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2401 14:44:41.126300 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2402 14:44:41.132604 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2403 14:44:41.136167 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2404 14:44:41.139755 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2405 14:44:41.146347 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2406 14:44:41.149745 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2407 14:44:41.153192 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2408 14:44:41.156338 [Byte 0] Lead/lag Transition tap number (1)
2409 14:44:41.162929 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2410 14:44:41.166221 3 6 16 |3c3b 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2411 14:44:41.169350 [Byte 1] Lead/lag falling Transition (3, 6, 16)
2412 14:44:41.176302 3 6 20 |e0e 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2413 14:44:41.179294 [Byte 1] Lead/lag Transition tap number (2)
2414 14:44:41.182843 3 6 24 |4646 2928 |(0 0)(11 11) |(0 0)(0 0)| 0
2415 14:44:41.186563 [Byte 0]First pass (3, 6, 24)
2416 14:44:41.189397 3 6 28 |4646 a0a |(0 0)(11 11) |(0 0)(0 0)| 0
2417 14:44:41.192572 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2418 14:44:41.195961 [Byte 1]First pass (3, 7, 0)
2419 14:44:41.199525 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2420 14:44:41.202646 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2421 14:44:41.209472 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2422 14:44:41.213025 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2423 14:44:41.215972 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2424 14:44:41.219348 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2425 14:44:41.222655 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2426 14:44:41.229370 4 0 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2427 14:44:41.232617 All bytes gating window > 1UI, Early break!
2428 14:44:41.232703
2429 14:44:41.235927 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 10)
2430 14:44:41.236010
2431 14:44:41.239079 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 20)
2432 14:44:41.239162
2433 14:44:41.239250
2434 14:44:41.239363
2435 14:44:41.242811 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 10)
2436 14:44:41.242897
2437 14:44:41.249103 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 20)
2438 14:44:41.249195
2439 14:44:41.249291
2440 14:44:41.249379 Write Rank0 MR1 =0x56
2441 14:44:41.249464
2442 14:44:41.253067 best RODT dly(2T, 0.5T) = (2, 3)
2443 14:44:41.253150
2444 14:44:41.255879 best RODT dly(2T, 0.5T) = (2, 3)
2445 14:44:41.255956 ==
2446 14:44:41.262507 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2447 14:44:41.266088 fsp= 1, odt_onoff= 1, Byte mode= 0
2448 14:44:41.266167 ==
2449 14:44:41.269703 Start DQ dly to find pass range UseTestEngine =0
2450 14:44:41.273105 x-axis: bit #, y-axis: DQ dly (-127~63)
2451 14:44:41.275891 RX Vref Scan = 0
2452 14:44:41.279279 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2453 14:44:41.279365 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2454 14:44:41.282898 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2455 14:44:41.285849 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2456 14:44:41.289005 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2457 14:44:41.292402 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2458 14:44:41.295817 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2459 14:44:41.299172 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2460 14:44:41.302776 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2461 14:44:41.302872 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2462 14:44:41.305645 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2463 14:44:41.309348 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2464 14:44:41.312424 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2465 14:44:41.316023 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2466 14:44:41.319271 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2467 14:44:41.322807 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2468 14:44:41.326723 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2469 14:44:41.326821 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2470 14:44:41.329566 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2471 14:44:41.332937 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2472 14:44:41.336397 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2473 14:44:41.339228 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2474 14:44:41.342930 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2475 14:44:41.343028 -3, [0] xxxxxxxx xxxxxxxo [MSB]
2476 14:44:41.346090 -2, [0] xxxxxxxx xxxxxxxo [MSB]
2477 14:44:41.349440 -1, [0] xxxoxxxx xoxxxxxo [MSB]
2478 14:44:41.353108 0, [0] xxxoxxxx ooxxxxxo [MSB]
2479 14:44:41.356050 1, [0] xxooxxxx ooxxxxxo [MSB]
2480 14:44:41.359152 2, [0] xxooxxxx oooxxxxo [MSB]
2481 14:44:41.362836 3, [0] xxooxxxx oooxxxxo [MSB]
2482 14:44:41.362934 4, [0] oxooxxxo oooxxxxo [MSB]
2483 14:44:41.365906 6, [0] oooooooo ooooooxo [MSB]
2484 14:44:41.369058 32, [0] oooooooo ooooooox [MSB]
2485 14:44:41.373090 33, [0] oooooooo ooooooox [MSB]
2486 14:44:41.375997 34, [0] oooooooo ooooooox [MSB]
2487 14:44:41.379436 35, [0] oooxoooo oxooooox [MSB]
2488 14:44:41.379534 36, [0] oooxoooo xxooooox [MSB]
2489 14:44:41.382920 37, [0] ooxxoooo xxooooox [MSB]
2490 14:44:41.385952 38, [0] ooxxoooo xxooooox [MSB]
2491 14:44:41.389386 39, [0] ooxxooox xxxoooox [MSB]
2492 14:44:41.392917 40, [0] oxxxxoox xxxoooox [MSB]
2493 14:44:41.396190 41, [0] oxxxxoox xxxxxxox [MSB]
2494 14:44:41.399639 42, [0] xxxxxxox xxxxxxxx [MSB]
2495 14:44:41.399747 43, [0] xxxxxxxx xxxxxxxx [MSB]
2496 14:44:41.405815 iDelay=43, Bit 0, Center 22 (4 ~ 41) 38
2497 14:44:41.409327 iDelay=43, Bit 1, Center 22 (5 ~ 39) 35
2498 14:44:41.412407 iDelay=43, Bit 2, Center 18 (1 ~ 36) 36
2499 14:44:41.415900 iDelay=43, Bit 3, Center 16 (-1 ~ 34) 36
2500 14:44:41.419334 iDelay=43, Bit 4, Center 22 (5 ~ 39) 35
2501 14:44:41.422309 iDelay=43, Bit 5, Center 23 (5 ~ 41) 37
2502 14:44:41.425831 iDelay=43, Bit 6, Center 23 (5 ~ 42) 38
2503 14:44:41.428980 iDelay=43, Bit 7, Center 21 (4 ~ 38) 35
2504 14:44:41.432344 iDelay=43, Bit 8, Center 17 (0 ~ 35) 36
2505 14:44:41.435753 iDelay=43, Bit 9, Center 16 (-1 ~ 34) 36
2506 14:44:41.439381 iDelay=43, Bit 10, Center 20 (2 ~ 38) 37
2507 14:44:41.442249 iDelay=43, Bit 11, Center 22 (5 ~ 40) 36
2508 14:44:41.445866 iDelay=43, Bit 12, Center 22 (5 ~ 40) 36
2509 14:44:41.452239 iDelay=43, Bit 13, Center 22 (5 ~ 40) 36
2510 14:44:41.455945 iDelay=43, Bit 14, Center 24 (7 ~ 41) 35
2511 14:44:41.458986 iDelay=43, Bit 15, Center 14 (-3 ~ 31) 35
2512 14:44:41.459105 ==
2513 14:44:41.462362 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2514 14:44:41.465584 fsp= 1, odt_onoff= 1, Byte mode= 0
2515 14:44:41.465695 ==
2516 14:44:41.468970 DQS Delay:
2517 14:44:41.469069 DQS0 = 0, DQS1 = 0
2518 14:44:41.472080 DQM Delay:
2519 14:44:41.472161 DQM0 = 20, DQM1 = 19
2520 14:44:41.472230 DQ Delay:
2521 14:44:41.475536 DQ0 =22, DQ1 =22, DQ2 =18, DQ3 =16
2522 14:44:41.478934 DQ4 =22, DQ5 =23, DQ6 =23, DQ7 =21
2523 14:44:41.482481 DQ8 =17, DQ9 =16, DQ10 =20, DQ11 =22
2524 14:44:41.485376 DQ12 =22, DQ13 =22, DQ14 =24, DQ15 =14
2525 14:44:41.485460
2526 14:44:41.485548
2527 14:44:41.488697 DramC Write-DBI off
2528 14:44:41.488789 ==
2529 14:44:41.492187 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2530 14:44:41.495542 fsp= 1, odt_onoff= 1, Byte mode= 0
2531 14:44:41.498450 ==
2532 14:44:41.501828 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2533 14:44:41.501930
2534 14:44:41.505271 Begin, DQ Scan Range 920~1176
2535 14:44:41.505366
2536 14:44:41.505463
2537 14:44:41.505554 TX Vref Scan disable
2538 14:44:41.508795 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
2539 14:44:41.515325 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
2540 14:44:41.518949 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
2541 14:44:41.521767 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
2542 14:44:41.525251 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
2543 14:44:41.528646 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
2544 14:44:41.531640 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
2545 14:44:41.535120 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
2546 14:44:41.538469 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
2547 14:44:41.541820 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2548 14:44:41.545456 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2549 14:44:41.548614 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2550 14:44:41.552102 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2551 14:44:41.555165 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2552 14:44:41.558615 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2553 14:44:41.562339 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2554 14:44:41.565165 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2555 14:44:41.568624 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2556 14:44:41.575049 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2557 14:44:41.578487 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2558 14:44:41.581834 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2559 14:44:41.585052 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2560 14:44:41.588453 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2561 14:44:41.591732 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2562 14:44:41.595082 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2563 14:44:41.598200 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2564 14:44:41.601921 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2565 14:44:41.605038 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2566 14:44:41.608474 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2567 14:44:41.611432 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2568 14:44:41.614736 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2569 14:44:41.618104 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2570 14:44:41.621795 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2571 14:44:41.628158 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2572 14:44:41.631735 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2573 14:44:41.635026 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2574 14:44:41.638103 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2575 14:44:41.641519 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2576 14:44:41.645274 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2577 14:44:41.648171 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2578 14:44:41.651662 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2579 14:44:41.655252 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2580 14:44:41.658045 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2581 14:44:41.661572 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2582 14:44:41.665044 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2583 14:44:41.668633 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2584 14:44:41.671613 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2585 14:44:41.675275 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2586 14:44:41.678182 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2587 14:44:41.681394 969 |3 6 9|[0] xxxxxxxx xxxxxxxo [MSB]
2588 14:44:41.685020 970 |3 6 10|[0] xxxxxxxx ooxxxxxo [MSB]
2589 14:44:41.688545 971 |3 6 11|[0] xxxxxxxx ooxxxxxo [MSB]
2590 14:44:41.691829 972 |3 6 12|[0] xxxxxxxx oooxxxoo [MSB]
2591 14:44:41.694963 973 |3 6 13|[0] xxxxxxxx oooxoxoo [MSB]
2592 14:44:41.701898 974 |3 6 14|[0] xxxxxxxx oooooxoo [MSB]
2593 14:44:41.704889 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
2594 14:44:41.708344 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
2595 14:44:41.711859 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
2596 14:44:41.715085 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
2597 14:44:41.718762 979 |3 6 19|[0] xxxxxxxx oooooooo [MSB]
2598 14:44:41.721610 980 |3 6 20|[0] xxxxxxxx oooooooo [MSB]
2599 14:44:41.725099 981 |3 6 21|[0] xooooxoo oooooooo [MSB]
2600 14:44:41.728017 982 |3 6 22|[0] oooooxoo oooooooo [MSB]
2601 14:44:41.731566 986 |3 6 26|[0] oooooooo ooooooox [MSB]
2602 14:44:41.734941 987 |3 6 27|[0] oooooooo ooooooox [MSB]
2603 14:44:41.738346 988 |3 6 28|[0] oooooooo oxooooox [MSB]
2604 14:44:41.741685 989 |3 6 29|[0] oooooooo xxooooox [MSB]
2605 14:44:41.744795 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
2606 14:44:41.751862 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
2607 14:44:41.754948 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
2608 14:44:41.757899 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
2609 14:44:41.761433 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
2610 14:44:41.764551 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
2611 14:44:41.768118 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
2612 14:44:41.771772 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
2613 14:44:41.774637 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
2614 14:44:41.778201 999 |3 6 39|[0] oooxoooo xxxxxxxx [MSB]
2615 14:44:41.781422 1000 |3 6 40|[0] oooxoooo xxxxxxxx [MSB]
2616 14:44:41.784773 1001 |3 6 41|[0] ooxxooox xxxxxxxx [MSB]
2617 14:44:41.787805 1002 |3 6 42|[0] xxxxxxxx xxxxxxxx [MSB]
2618 14:44:41.791723 Byte0, DQ PI dly=990, DQM PI dly= 990
2619 14:44:41.798146 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 30)
2620 14:44:41.798258
2621 14:44:41.801355 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 30)
2622 14:44:41.801471
2623 14:44:41.804664 Byte1, DQ PI dly=979, DQM PI dly= 979
2624 14:44:41.807898 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
2625 14:44:41.808012
2626 14:44:41.815053 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
2627 14:44:41.815174
2628 14:44:41.815276 ==
2629 14:44:41.818390 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2630 14:44:41.821610 fsp= 1, odt_onoff= 1, Byte mode= 0
2631 14:44:41.821724 ==
2632 14:44:41.828020 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2633 14:44:41.828138
2634 14:44:41.828239 Begin, DQ Scan Range 955~1019
2635 14:44:41.831412 Write Rank0 MR14 =0x0
2636 14:44:41.840512
2637 14:44:41.840630 CH=1, VrefRange= 0, VrefLevel = 0
2638 14:44:41.847088 TX Bit0 (984~999) 16 991, Bit8 (973~984) 12 978,
2639 14:44:41.850254 TX Bit1 (983~996) 14 989, Bit9 (974~983) 10 978,
2640 14:44:41.856795 TX Bit2 (981~995) 15 988, Bit10 (976~986) 11 981,
2641 14:44:41.860435 TX Bit3 (979~992) 14 985, Bit11 (976~987) 12 981,
2642 14:44:41.863581 TX Bit4 (983~997) 15 990, Bit12 (975~987) 13 981,
2643 14:44:41.870302 TX Bit5 (985~998) 14 991, Bit13 (977~987) 11 982,
2644 14:44:41.873941 TX Bit6 (983~997) 15 990, Bit14 (975~986) 12 980,
2645 14:44:41.876802 TX Bit7 (984~996) 13 990, Bit15 (970~979) 10 974,
2646 14:44:41.876895
2647 14:44:41.880424 Write Rank0 MR14 =0x2
2648 14:44:41.889035
2649 14:44:41.889127 CH=1, VrefRange= 0, VrefLevel = 2
2650 14:44:41.896003 TX Bit0 (984~1000) 17 992, Bit8 (972~984) 13 978,
2651 14:44:41.899433 TX Bit1 (983~997) 15 990, Bit9 (973~983) 11 978,
2652 14:44:41.906029 TX Bit2 (980~996) 17 988, Bit10 (975~987) 13 981,
2653 14:44:41.909196 TX Bit3 (979~993) 15 986, Bit11 (975~987) 13 981,
2654 14:44:41.912924 TX Bit4 (982~998) 17 990, Bit12 (976~988) 13 982,
2655 14:44:41.919003 TX Bit5 (984~999) 16 991, Bit13 (977~988) 12 982,
2656 14:44:41.922562 TX Bit6 (983~998) 16 990, Bit14 (975~987) 13 981,
2657 14:44:41.925978 TX Bit7 (983~997) 15 990, Bit15 (969~980) 12 974,
2658 14:44:41.929105
2659 14:44:41.929197 Write Rank0 MR14 =0x4
2660 14:44:41.938140
2661 14:44:41.938231 CH=1, VrefRange= 0, VrefLevel = 4
2662 14:44:41.945049 TX Bit0 (983~1000) 18 991, Bit8 (972~985) 14 978,
2663 14:44:41.948739 TX Bit1 (982~998) 17 990, Bit9 (973~984) 12 978,
2664 14:44:41.955115 TX Bit2 (980~997) 18 988, Bit10 (975~988) 14 981,
2665 14:44:41.958120 TX Bit3 (978~993) 16 985, Bit11 (976~989) 14 982,
2666 14:44:41.961425 TX Bit4 (982~999) 18 990, Bit12 (975~989) 15 982,
2667 14:44:41.968623 TX Bit5 (984~999) 16 991, Bit13 (976~990) 15 983,
2668 14:44:41.971788 TX Bit6 (983~998) 16 990, Bit14 (975~987) 13 981,
2669 14:44:41.975114 TX Bit7 (983~998) 16 990, Bit15 (969~982) 14 975,
2670 14:44:41.977906
2671 14:44:41.977997 Write Rank0 MR14 =0x6
2672 14:44:41.987335
2673 14:44:41.987435 CH=1, VrefRange= 0, VrefLevel = 6
2674 14:44:41.994468 TX Bit0 (983~1000) 18 991, Bit8 (971~985) 15 978,
2675 14:44:41.997284 TX Bit1 (982~998) 17 990, Bit9 (971~984) 14 977,
2676 14:44:42.003824 TX Bit2 (979~997) 19 988, Bit10 (974~988) 15 981,
2677 14:44:42.007510 TX Bit3 (978~994) 17 986, Bit11 (976~990) 15 983,
2678 14:44:42.010864 TX Bit4 (982~999) 18 990, Bit12 (974~990) 17 982,
2679 14:44:42.017312 TX Bit5 (984~999) 16 991, Bit13 (976~990) 15 983,
2680 14:44:42.021077 TX Bit6 (982~999) 18 990, Bit14 (974~988) 15 981,
2681 14:44:42.024633 TX Bit7 (983~997) 15 990, Bit15 (968~983) 16 975,
2682 14:44:42.027373
2683 14:44:42.027474 Write Rank0 MR14 =0x8
2684 14:44:42.036775
2685 14:44:42.036867 CH=1, VrefRange= 0, VrefLevel = 8
2686 14:44:42.043639 TX Bit0 (983~1001) 19 992, Bit8 (971~986) 16 978,
2687 14:44:42.046753 TX Bit1 (982~999) 18 990, Bit9 (972~985) 14 978,
2688 14:44:42.053312 TX Bit2 (979~999) 21 989, Bit10 (974~990) 17 982,
2689 14:44:42.056696 TX Bit3 (978~995) 18 986, Bit11 (975~990) 16 982,
2690 14:44:42.059749 TX Bit4 (982~1000) 19 991, Bit12 (974~991) 18 982,
2691 14:44:42.066694 TX Bit5 (984~1000) 17 992, Bit13 (976~990) 15 983,
2692 14:44:42.070336 TX Bit6 (982~999) 18 990, Bit14 (974~989) 16 981,
2693 14:44:42.076627 TX Bit7 (982~999) 18 990, Bit15 (968~983) 16 975,
2694 14:44:42.076723
2695 14:44:42.076819 Write Rank0 MR14 =0xa
2696 14:44:42.086671
2697 14:44:42.089657 CH=1, VrefRange= 0, VrefLevel = 10
2698 14:44:42.092706 TX Bit0 (983~1001) 19 992, Bit8 (971~986) 16 978,
2699 14:44:42.096155 TX Bit1 (981~999) 19 990, Bit9 (970~985) 16 977,
2700 14:44:42.102950 TX Bit2 (979~999) 21 989, Bit10 (974~990) 17 982,
2701 14:44:42.106264 TX Bit3 (978~995) 18 986, Bit11 (975~991) 17 983,
2702 14:44:42.109226 TX Bit4 (981~1000) 20 990, Bit12 (975~991) 17 983,
2703 14:44:42.116456 TX Bit5 (983~1000) 18 991, Bit13 (976~991) 16 983,
2704 14:44:42.119392 TX Bit6 (982~999) 18 990, Bit14 (973~990) 18 981,
2705 14:44:42.126158 TX Bit7 (982~999) 18 990, Bit15 (968~984) 17 976,
2706 14:44:42.126254
2707 14:44:42.126351 Write Rank0 MR14 =0xc
2708 14:44:42.136299
2709 14:44:42.139263 CH=1, VrefRange= 0, VrefLevel = 12
2710 14:44:42.142726 TX Bit0 (983~1001) 19 992, Bit8 (971~986) 16 978,
2711 14:44:42.146193 TX Bit1 (981~999) 19 990, Bit9 (970~985) 16 977,
2712 14:44:42.152883 TX Bit2 (979~999) 21 989, Bit10 (974~990) 17 982,
2713 14:44:42.156069 TX Bit3 (978~995) 18 986, Bit11 (975~991) 17 983,
2714 14:44:42.159328 TX Bit4 (981~1000) 20 990, Bit12 (975~991) 17 983,
2715 14:44:42.165713 TX Bit5 (983~1000) 18 991, Bit13 (976~991) 16 983,
2716 14:44:42.169216 TX Bit6 (982~999) 18 990, Bit14 (973~990) 18 981,
2717 14:44:42.175608 TX Bit7 (982~999) 18 990, Bit15 (968~984) 17 976,
2718 14:44:42.175704
2719 14:44:42.175800 Write Rank0 MR14 =0xe
2720 14:44:42.185876
2721 14:44:42.188915 CH=1, VrefRange= 0, VrefLevel = 14
2722 14:44:42.192471 TX Bit0 (982~1002) 21 992, Bit8 (970~988) 19 979,
2723 14:44:42.195725 TX Bit1 (980~1000) 21 990, Bit9 (970~986) 17 978,
2724 14:44:42.202733 TX Bit2 (978~1000) 23 989, Bit10 (973~991) 19 982,
2725 14:44:42.206077 TX Bit3 (977~997) 21 987, Bit11 (974~991) 18 982,
2726 14:44:42.208885 TX Bit4 (980~1001) 22 990, Bit12 (973~992) 20 982,
2727 14:44:42.215640 TX Bit5 (983~1001) 19 992, Bit13 (975~992) 18 983,
2728 14:44:42.218702 TX Bit6 (981~1000) 20 990, Bit14 (972~991) 20 981,
2729 14:44:42.225412 TX Bit7 (981~1000) 20 990, Bit15 (968~985) 18 976,
2730 14:44:42.225505
2731 14:44:42.225577 Write Rank0 MR14 =0x10
2732 14:44:42.235894
2733 14:44:42.235986 CH=1, VrefRange= 0, VrefLevel = 16
2734 14:44:42.242419 TX Bit0 (982~1002) 21 992, Bit8 (970~988) 19 979,
2735 14:44:42.245766 TX Bit1 (981~1000) 20 990, Bit9 (970~987) 18 978,
2736 14:44:42.252565 TX Bit2 (978~1000) 23 989, Bit10 (972~991) 20 981,
2737 14:44:42.255739 TX Bit3 (977~998) 22 987, Bit11 (973~992) 20 982,
2738 14:44:42.259399 TX Bit4 (979~1001) 23 990, Bit12 (972~992) 21 982,
2739 14:44:42.265788 TX Bit5 (983~1001) 19 992, Bit13 (975~992) 18 983,
2740 14:44:42.268973 TX Bit6 (981~1001) 21 991, Bit14 (972~992) 21 982,
2741 14:44:42.275605 TX Bit7 (980~1000) 21 990, Bit15 (967~985) 19 976,
2742 14:44:42.275698
2743 14:44:42.275771 Write Rank0 MR14 =0x12
2744 14:44:42.286054
2745 14:44:42.289327 CH=1, VrefRange= 0, VrefLevel = 18
2746 14:44:42.292956 TX Bit0 (982~1003) 22 992, Bit8 (970~989) 20 979,
2747 14:44:42.296298 TX Bit1 (979~1001) 23 990, Bit9 (970~987) 18 978,
2748 14:44:42.302929 TX Bit2 (978~1000) 23 989, Bit10 (971~992) 22 981,
2749 14:44:42.306403 TX Bit3 (977~998) 22 987, Bit11 (973~992) 20 982,
2750 14:44:42.309299 TX Bit4 (980~1002) 23 991, Bit12 (972~993) 22 982,
2751 14:44:42.316264 TX Bit5 (982~1002) 21 992, Bit13 (975~992) 18 983,
2752 14:44:42.319674 TX Bit6 (980~1001) 22 990, Bit14 (971~992) 22 981,
2753 14:44:42.326258 TX Bit7 (980~1001) 22 990, Bit15 (967~985) 19 976,
2754 14:44:42.326352
2755 14:44:42.326425 Write Rank0 MR14 =0x14
2756 14:44:42.336618
2757 14:44:42.340007 CH=1, VrefRange= 0, VrefLevel = 20
2758 14:44:42.343589 TX Bit0 (982~1004) 23 993, Bit8 (969~990) 22 979,
2759 14:44:42.346624 TX Bit1 (979~1001) 23 990, Bit9 (970~988) 19 979,
2760 14:44:42.353130 TX Bit2 (978~1001) 24 989, Bit10 (971~992) 22 981,
2761 14:44:42.356336 TX Bit3 (977~999) 23 988, Bit11 (972~992) 21 982,
2762 14:44:42.360371 TX Bit4 (979~1002) 24 990, Bit12 (972~993) 22 982,
2763 14:44:42.366725 TX Bit5 (982~1003) 22 992, Bit13 (974~993) 20 983,
2764 14:44:42.370023 TX Bit6 (980~1001) 22 990, Bit14 (971~992) 22 981,
2765 14:44:42.376462 TX Bit7 (980~1001) 22 990, Bit15 (967~986) 20 976,
2766 14:44:42.376554
2767 14:44:42.376629 Write Rank0 MR14 =0x16
2768 14:44:42.387076
2769 14:44:42.390370 CH=1, VrefRange= 0, VrefLevel = 22
2770 14:44:42.393772 TX Bit0 (981~1004) 24 992, Bit8 (969~990) 22 979,
2771 14:44:42.397239 TX Bit1 (978~1002) 25 990, Bit9 (970~989) 20 979,
2772 14:44:42.403601 TX Bit2 (977~1001) 25 989, Bit10 (971~992) 22 981,
2773 14:44:42.406915 TX Bit3 (977~999) 23 988, Bit11 (972~993) 22 982,
2774 14:44:42.410380 TX Bit4 (979~1003) 25 991, Bit12 (972~994) 23 983,
2775 14:44:42.416863 TX Bit5 (982~1003) 22 992, Bit13 (973~993) 21 983,
2776 14:44:42.420342 TX Bit6 (979~1002) 24 990, Bit14 (971~993) 23 982,
2777 14:44:42.426843 TX Bit7 (980~1001) 22 990, Bit15 (967~986) 20 976,
2778 14:44:42.426936
2779 14:44:42.427009 Write Rank0 MR14 =0x18
2780 14:44:42.437861
2781 14:44:42.441113 CH=1, VrefRange= 0, VrefLevel = 24
2782 14:44:42.444046 TX Bit0 (980~1005) 26 992, Bit8 (969~991) 23 980,
2783 14:44:42.447427 TX Bit1 (978~1002) 25 990, Bit9 (969~990) 22 979,
2784 14:44:42.453945 TX Bit2 (977~1001) 25 989, Bit10 (971~993) 23 982,
2785 14:44:42.457491 TX Bit3 (976~999) 24 987, Bit11 (971~993) 23 982,
2786 14:44:42.460850 TX Bit4 (979~1002) 24 990, Bit12 (971~994) 24 982,
2787 14:44:42.467223 TX Bit5 (981~1004) 24 992, Bit13 (973~993) 21 983,
2788 14:44:42.471105 TX Bit6 (979~1002) 24 990, Bit14 (970~993) 24 981,
2789 14:44:42.476994 TX Bit7 (979~1002) 24 990, Bit15 (966~987) 22 976,
2790 14:44:42.477085
2791 14:44:42.477165 Write Rank0 MR14 =0x1a
2792 14:44:42.488277
2793 14:44:42.488379 CH=1, VrefRange= 0, VrefLevel = 26
2794 14:44:42.494758 TX Bit0 (980~1005) 26 992, Bit8 (969~991) 23 980,
2795 14:44:42.498365 TX Bit1 (978~1003) 26 990, Bit9 (969~990) 22 979,
2796 14:44:42.504863 TX Bit2 (977~1002) 26 989, Bit10 (971~993) 23 982,
2797 14:44:42.508112 TX Bit3 (976~1000) 25 988, Bit11 (971~994) 24 982,
2798 14:44:42.511515 TX Bit4 (978~1003) 26 990, Bit12 (971~994) 24 982,
2799 14:44:42.517898 TX Bit5 (981~1004) 24 992, Bit13 (973~994) 22 983,
2800 14:44:42.521299 TX Bit6 (979~1003) 25 991, Bit14 (970~993) 24 981,
2801 14:44:42.528162 TX Bit7 (979~1003) 25 991, Bit15 (966~988) 23 977,
2802 14:44:42.528256
2803 14:44:42.528329 Write Rank0 MR14 =0x1c
2804 14:44:42.538799
2805 14:44:42.542305 CH=1, VrefRange= 0, VrefLevel = 28
2806 14:44:42.546102 TX Bit0 (979~1006) 28 992, Bit8 (969~992) 24 980,
2807 14:44:42.549261 TX Bit1 (978~1003) 26 990, Bit9 (969~991) 23 980,
2808 14:44:42.555582 TX Bit2 (977~1002) 26 989, Bit10 (970~993) 24 981,
2809 14:44:42.558635 TX Bit3 (976~1000) 25 988, Bit11 (970~994) 25 982,
2810 14:44:42.562215 TX Bit4 (978~1004) 27 991, Bit12 (970~994) 25 982,
2811 14:44:42.568680 TX Bit5 (980~1004) 25 992, Bit13 (972~994) 23 983,
2812 14:44:42.572448 TX Bit6 (979~1003) 25 991, Bit14 (970~994) 25 982,
2813 14:44:42.578539 TX Bit7 (979~1003) 25 991, Bit15 (966~988) 23 977,
2814 14:44:42.578632
2815 14:44:42.578705 Write Rank0 MR14 =0x1e
2816 14:44:42.589848
2817 14:44:42.592938 CH=1, VrefRange= 0, VrefLevel = 30
2818 14:44:42.596507 TX Bit0 (979~1006) 28 992, Bit8 (969~992) 24 980,
2819 14:44:42.599519 TX Bit1 (978~1003) 26 990, Bit9 (969~991) 23 980,
2820 14:44:42.606372 TX Bit2 (977~1002) 26 989, Bit10 (970~994) 25 982,
2821 14:44:42.610022 TX Bit3 (976~1000) 25 988, Bit11 (970~994) 25 982,
2822 14:44:42.616196 TX Bit4 (979~1004) 26 991, Bit12 (970~994) 25 982,
2823 14:44:42.619730 TX Bit5 (980~1006) 27 993, Bit13 (972~994) 23 983,
2824 14:44:42.623140 TX Bit6 (978~1004) 27 991, Bit14 (971~994) 24 982,
2825 14:44:42.629714 TX Bit7 (978~1003) 26 990, Bit15 (966~988) 23 977,
2826 14:44:42.629807
2827 14:44:42.629881 Write Rank0 MR14 =0x20
2828 14:44:42.640942
2829 14:44:42.643817 CH=1, VrefRange= 0, VrefLevel = 32
2830 14:44:42.647439 TX Bit0 (979~1006) 28 992, Bit8 (969~992) 24 980,
2831 14:44:42.650779 TX Bit1 (978~1003) 26 990, Bit9 (969~991) 23 980,
2832 14:44:42.657234 TX Bit2 (977~1002) 26 989, Bit10 (970~994) 25 982,
2833 14:44:42.660791 TX Bit3 (976~1000) 25 988, Bit11 (970~994) 25 982,
2834 14:44:42.664232 TX Bit4 (979~1004) 26 991, Bit12 (970~994) 25 982,
2835 14:44:42.670897 TX Bit5 (980~1006) 27 993, Bit13 (972~994) 23 983,
2836 14:44:42.674079 TX Bit6 (978~1004) 27 991, Bit14 (971~994) 24 982,
2837 14:44:42.680436 TX Bit7 (978~1003) 26 990, Bit15 (966~988) 23 977,
2838 14:44:42.680529
2839 14:44:42.680602 Write Rank0 MR14 =0x22
2840 14:44:42.691357
2841 14:44:42.695025 CH=1, VrefRange= 0, VrefLevel = 34
2842 14:44:42.698015 TX Bit0 (979~1006) 28 992, Bit8 (969~992) 24 980,
2843 14:44:42.701602 TX Bit1 (978~1003) 26 990, Bit9 (969~991) 23 980,
2844 14:44:42.707873 TX Bit2 (977~1002) 26 989, Bit10 (970~994) 25 982,
2845 14:44:42.711391 TX Bit3 (976~1000) 25 988, Bit11 (970~994) 25 982,
2846 14:44:42.715007 TX Bit4 (979~1004) 26 991, Bit12 (970~994) 25 982,
2847 14:44:42.721552 TX Bit5 (980~1006) 27 993, Bit13 (972~994) 23 983,
2848 14:44:42.725012 TX Bit6 (978~1004) 27 991, Bit14 (971~994) 24 982,
2849 14:44:42.731050 TX Bit7 (978~1003) 26 990, Bit15 (966~988) 23 977,
2850 14:44:42.731144
2851 14:44:42.731216 Write Rank0 MR14 =0x24
2852 14:44:42.742627
2853 14:44:42.745577 CH=1, VrefRange= 0, VrefLevel = 36
2854 14:44:42.749075 TX Bit0 (979~1006) 28 992, Bit8 (969~992) 24 980,
2855 14:44:42.752725 TX Bit1 (978~1003) 26 990, Bit9 (969~991) 23 980,
2856 14:44:42.759061 TX Bit2 (977~1002) 26 989, Bit10 (970~994) 25 982,
2857 14:44:42.762464 TX Bit3 (976~1000) 25 988, Bit11 (970~994) 25 982,
2858 14:44:42.765882 TX Bit4 (979~1004) 26 991, Bit12 (970~994) 25 982,
2859 14:44:42.772389 TX Bit5 (980~1006) 27 993, Bit13 (972~994) 23 983,
2860 14:44:42.775699 TX Bit6 (978~1004) 27 991, Bit14 (971~994) 24 982,
2861 14:44:42.782594 TX Bit7 (978~1003) 26 990, Bit15 (966~988) 23 977,
2862 14:44:42.782689
2863 14:44:42.782762 Write Rank0 MR14 =0x26
2864 14:44:42.793141
2865 14:44:42.796589 CH=1, VrefRange= 0, VrefLevel = 38
2866 14:44:42.800351 TX Bit0 (979~1006) 28 992, Bit8 (969~992) 24 980,
2867 14:44:42.803049 TX Bit1 (978~1003) 26 990, Bit9 (969~991) 23 980,
2868 14:44:42.809707 TX Bit2 (977~1002) 26 989, Bit10 (970~994) 25 982,
2869 14:44:42.813339 TX Bit3 (976~1000) 25 988, Bit11 (970~994) 25 982,
2870 14:44:42.816615 TX Bit4 (979~1004) 26 991, Bit12 (970~994) 25 982,
2871 14:44:42.823140 TX Bit5 (980~1006) 27 993, Bit13 (972~994) 23 983,
2872 14:44:42.826576 TX Bit6 (978~1004) 27 991, Bit14 (971~994) 24 982,
2873 14:44:42.832958 TX Bit7 (978~1003) 26 990, Bit15 (966~988) 23 977,
2874 14:44:42.833051
2875 14:44:42.833124
2876 14:44:42.836314 TX Vref found, early break! 378< 382
2877 14:44:42.839994 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
2878 14:44:42.842736 u1DelayCellOfst[0]=5 cells (4 PI)
2879 14:44:42.846421 u1DelayCellOfst[1]=2 cells (2 PI)
2880 14:44:42.849767 u1DelayCellOfst[2]=1 cells (1 PI)
2881 14:44:42.853227 u1DelayCellOfst[3]=0 cells (0 PI)
2882 14:44:42.856321 u1DelayCellOfst[4]=3 cells (3 PI)
2883 14:44:42.859427 u1DelayCellOfst[5]=6 cells (5 PI)
2884 14:44:42.862870 u1DelayCellOfst[6]=3 cells (3 PI)
2885 14:44:42.862962 u1DelayCellOfst[7]=2 cells (2 PI)
2886 14:44:42.866370 Byte0, DQ PI dly=988, DQM PI dly= 990
2887 14:44:42.872730 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28)
2888 14:44:42.872821
2889 14:44:42.876186 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28)
2890 14:44:42.876267
2891 14:44:42.879762 u1DelayCellOfst[8]=3 cells (3 PI)
2892 14:44:42.882631 u1DelayCellOfst[9]=3 cells (3 PI)
2893 14:44:42.886160 u1DelayCellOfst[10]=6 cells (5 PI)
2894 14:44:42.889498 u1DelayCellOfst[11]=6 cells (5 PI)
2895 14:44:42.892943 u1DelayCellOfst[12]=6 cells (5 PI)
2896 14:44:42.896154 u1DelayCellOfst[13]=7 cells (6 PI)
2897 14:44:42.899530 u1DelayCellOfst[14]=6 cells (5 PI)
2898 14:44:42.902682 u1DelayCellOfst[15]=0 cells (0 PI)
2899 14:44:42.905880 Byte1, DQ PI dly=977, DQM PI dly= 980
2900 14:44:42.909839 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
2901 14:44:42.909927
2902 14:44:42.913314 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
2903 14:44:42.913395
2904 14:44:42.916427 Write Rank0 MR14 =0x1e
2905 14:44:42.916503
2906 14:44:42.919638 Final TX Range 0 Vref 30
2907 14:44:42.919713
2908 14:44:42.925824 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2909 14:44:42.925913
2910 14:44:42.932724 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2911 14:44:42.939133 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2912 14:44:42.946064 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2913 14:44:42.946152 Write Rank0 MR3 =0xb0
2914 14:44:42.949644 DramC Write-DBI on
2915 14:44:42.949729 ==
2916 14:44:42.956203 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2917 14:44:42.956287 fsp= 1, odt_onoff= 1, Byte mode= 0
2918 14:44:42.959020 ==
2919 14:44:42.962697 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2920 14:44:42.962779
2921 14:44:42.966085 Begin, DQ Scan Range 700~764
2922 14:44:42.966159
2923 14:44:42.966226
2924 14:44:42.966295 TX Vref Scan disable
2925 14:44:42.969052 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2926 14:44:42.975790 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2927 14:44:42.979282 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2928 14:44:42.982420 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2929 14:44:42.985872 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2930 14:44:42.988833 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2931 14:44:42.992242 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2932 14:44:42.995929 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2933 14:44:42.999234 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2934 14:44:43.002363 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2935 14:44:43.006022 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2936 14:44:43.009039 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2937 14:44:43.012467 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2938 14:44:43.015653 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2939 14:44:43.018686 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2940 14:44:43.022491 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2941 14:44:43.025753 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2942 14:44:43.029042 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2943 14:44:43.032076 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
2944 14:44:43.035852 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
2945 14:44:43.038815 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
2946 14:44:43.045370 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
2947 14:44:43.048832 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
2948 14:44:43.052068 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2949 14:44:43.055572 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2950 14:44:43.058931 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2951 14:44:43.065597 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2952 14:44:43.069025 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2953 14:44:43.071962 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2954 14:44:43.075427 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2955 14:44:43.078876 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
2956 14:44:43.082262 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
2957 14:44:43.085873 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
2958 14:44:43.088619 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
2959 14:44:43.092372 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
2960 14:44:43.095639 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
2961 14:44:43.099066 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
2962 14:44:43.101814 751 |2 6 47|[0] xxxxxxxx xxxxxxxx [MSB]
2963 14:44:43.105164 Byte0, DQ PI dly=736, DQM PI dly= 736
2964 14:44:43.112124 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 32)
2965 14:44:43.112218
2966 14:44:43.115367 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 32)
2967 14:44:43.115483
2968 14:44:43.118722 Byte1, DQ PI dly=724, DQM PI dly= 724
2969 14:44:43.122087 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 20)
2970 14:44:43.122180
2971 14:44:43.128838 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 20)
2972 14:44:43.128933
2973 14:44:43.135226 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2974 14:44:43.141848 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2975 14:44:43.148404 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2976 14:44:43.148493 Write Rank0 MR3 =0x30
2977 14:44:43.151488 DramC Write-DBI off
2978 14:44:43.151579
2979 14:44:43.151652 [DATLAT]
2980 14:44:43.154882 Freq=1600, CH1 RK0, use_rxtx_scan=0
2981 14:44:43.154965
2982 14:44:43.158149 DATLAT Default: 0xf
2983 14:44:43.158243 7, 0xFFFF, sum=0
2984 14:44:43.161903 8, 0xFFFF, sum=0
2985 14:44:43.162000 9, 0xFFFF, sum=0
2986 14:44:43.165486 10, 0xFFFF, sum=0
2987 14:44:43.165575 11, 0xFFFF, sum=0
2988 14:44:43.168246 12, 0xFFFF, sum=0
2989 14:44:43.168346 13, 0xFFFF, sum=0
2990 14:44:43.171987 14, 0x0, sum=1
2991 14:44:43.172093 15, 0x0, sum=2
2992 14:44:43.172173 16, 0x0, sum=3
2993 14:44:43.175318 17, 0x0, sum=4
2994 14:44:43.178255 pattern=2 first_step=14 total pass=5 best_step=16
2995 14:44:43.178376 ==
2996 14:44:43.185327 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2997 14:44:43.188613 fsp= 1, odt_onoff= 1, Byte mode= 0
2998 14:44:43.188707 ==
2999 14:44:43.192009 Start DQ dly to find pass range UseTestEngine =1
3000 14:44:43.195186 x-axis: bit #, y-axis: DQ dly (-127~63)
3001 14:44:43.198553 RX Vref Scan = 1
3002 14:44:43.304562
3003 14:44:43.304702 RX Vref found, early break!
3004 14:44:43.304782
3005 14:44:43.310938 Final RX Vref 11, apply to both rank0 and 1
3006 14:44:43.311034 ==
3007 14:44:43.314290 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3008 14:44:43.317682 fsp= 1, odt_onoff= 1, Byte mode= 0
3009 14:44:43.317770 ==
3010 14:44:43.317847 DQS Delay:
3011 14:44:43.321111 DQS0 = 0, DQS1 = 0
3012 14:44:43.321194 DQM Delay:
3013 14:44:43.324895 DQM0 = 21, DQM1 = 19
3014 14:44:43.324981 DQ Delay:
3015 14:44:43.328223 DQ0 =22, DQ1 =22, DQ2 =18, DQ3 =17
3016 14:44:43.331152 DQ4 =22, DQ5 =23, DQ6 =23, DQ7 =21
3017 14:44:43.334736 DQ8 =17, DQ9 =16, DQ10 =20, DQ11 =22
3018 14:44:43.337747 DQ12 =22, DQ13 =21, DQ14 =23, DQ15 =13
3019 14:44:43.337827
3020 14:44:43.337902
3021 14:44:43.337970
3022 14:44:43.341271 [DramC_TX_OE_Calibration] TA2
3023 14:44:43.344353 Original DQ_B0 (3 6) =30, OEN = 27
3024 14:44:43.347979 Original DQ_B1 (3 6) =30, OEN = 27
3025 14:44:43.351271 23, 0x0, End_B0=23 End_B1=23
3026 14:44:43.351362 24, 0x0, End_B0=24 End_B1=24
3027 14:44:43.354515 25, 0x0, End_B0=25 End_B1=25
3028 14:44:43.357898 26, 0x0, End_B0=26 End_B1=26
3029 14:44:43.361231 27, 0x0, End_B0=27 End_B1=27
3030 14:44:43.361331 28, 0x0, End_B0=28 End_B1=28
3031 14:44:43.364719 29, 0x0, End_B0=29 End_B1=29
3032 14:44:43.367632 30, 0x0, End_B0=30 End_B1=30
3033 14:44:43.371351 31, 0xFFFF, End_B0=30 End_B1=30
3034 14:44:43.377556 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3035 14:44:43.380970 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3036 14:44:43.381064
3037 14:44:43.381167
3038 14:44:43.384685 Write Rank0 MR23 =0x3f
3039 14:44:43.384796 [DQSOSC]
3040 14:44:43.394389 [DQSOSCAuto] RK0, (LSB)MR18= 0xbfbf, (MSB)MR19= 0x202, tDQSOscB0 = 448 ps tDQSOscB1 = 448 ps
3041 14:44:43.397989 CH1_RK0: MR19=0x202, MR18=0xBFBF, DQSOSC=448, MR23=63, INC=12, DEC=18
3042 14:44:43.400992 Write Rank0 MR23 =0x3f
3043 14:44:43.401086 [DQSOSC]
3044 14:44:43.411102 [DQSOSCAuto] RK0, (LSB)MR18= 0xc1c1, (MSB)MR19= 0x202, tDQSOscB0 = 446 ps tDQSOscB1 = 446 ps
3045 14:44:43.414163 CH1 RK0: MR19=202, MR18=C1C1
3046 14:44:43.417683 [RankSwap] Rank num 2, (Multi 1), Rank 1
3047 14:44:43.417795 Write Rank0 MR2 =0xad
3048 14:44:43.421206 [Write Leveling]
3049 14:44:43.424391 delay byte0 byte1 byte2 byte3
3050 14:44:43.424478
3051 14:44:43.424550 10 0 0
3052 14:44:43.427860 11 0 0
3053 14:44:43.427955 12 0 0
3054 14:44:43.428030 13 0 0
3055 14:44:43.430755 14 0 0
3056 14:44:43.430849 15 0 0
3057 14:44:43.434299 16 0 0
3058 14:44:43.434393 17 0 0
3059 14:44:43.434468 18 0 0
3060 14:44:43.437825 19 0 0
3061 14:44:43.437918 20 0 0
3062 14:44:43.441082 21 0 0
3063 14:44:43.441175 22 0 0
3064 14:44:43.444269 23 0 0
3065 14:44:43.444363 24 0 ff
3066 14:44:43.444438 25 0 ff
3067 14:44:43.447307 26 0 ff
3068 14:44:43.447439 27 0 ff
3069 14:44:43.450697 28 0 ff
3070 14:44:43.450791 29 0 ff
3071 14:44:43.454096 30 0 ff
3072 14:44:43.454196 31 0 ff
3073 14:44:43.454273 32 0 ff
3074 14:44:43.457833 33 0 ff
3075 14:44:43.457957 34 ff ff
3076 14:44:43.460987 35 ff ff
3077 14:44:43.461099 36 ff ff
3078 14:44:43.463999 37 ff ff
3079 14:44:43.464093 38 ff ff
3080 14:44:43.467739 39 ff ff
3081 14:44:43.467832 40 ff ff
3082 14:44:43.470561 pass bytecount = 0xff (0xff: all bytes pass)
3083 14:44:43.470653
3084 14:44:43.473965 DQS0 dly: 34
3085 14:44:43.474057 DQS1 dly: 24
3086 14:44:43.477747 Write Rank0 MR2 =0x2d
3087 14:44:43.481201 [RankSwap] Rank num 2, (Multi 1), Rank 0
3088 14:44:43.481299 Write Rank1 MR1 =0xd6
3089 14:44:43.484356 [Gating]
3090 14:44:43.484447 ==
3091 14:44:43.487642 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3092 14:44:43.490491 fsp= 1, odt_onoff= 1, Byte mode= 0
3093 14:44:43.490583 ==
3094 14:44:43.497460 3 1 0 |3534 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
3095 14:44:43.500858 3 1 4 |3535 2c2b |(0 0)(11 11) |(1 1)(0 0)| 0
3096 14:44:43.504298 3 1 8 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3097 14:44:43.507835 3 1 12 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3098 14:44:43.514238 3 1 16 |3535 2c2b |(0 0)(11 11) |(0 1)(1 0)| 0
3099 14:44:43.517771 3 1 20 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3100 14:44:43.520796 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3101 14:44:43.527521 3 1 28 |1312 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3102 14:44:43.530932 3 2 0 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3103 14:44:43.534428 3 2 4 |3535 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3104 14:44:43.537646 3 2 8 |707 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3105 14:44:43.544381 3 2 12 |3d3d 302 |(0 0)(11 11) |(1 1)(0 0)| 0
3106 14:44:43.547300 3 2 16 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3107 14:44:43.551038 3 2 20 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3108 14:44:43.557954 3 2 24 |3d3d 3534 |(0 0)(11 11) |(1 1)(0 0)| 0
3109 14:44:43.560696 3 2 28 |3d3d 3534 |(0 0)(11 11) |(1 1)(0 0)| 0
3110 14:44:43.564063 3 3 0 |3d3d 3534 |(0 0)(11 11) |(1 1)(0 0)| 0
3111 14:44:43.567281 3 3 4 |3d3d 3534 |(0 0)(11 11) |(1 1)(1 1)| 0
3112 14:44:43.574347 3 3 8 |504 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3113 14:44:43.577619 3 3 12 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3114 14:44:43.580874 [Byte 0] Lead/lag falling Transition (3, 3, 12)
3115 14:44:43.587635 3 3 16 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
3116 14:44:43.591091 [Byte 1] Lead/lag Transition tap number (1)
3117 14:44:43.594242 3 3 20 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3118 14:44:43.597758 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3119 14:44:43.603990 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3120 14:44:43.607368 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3121 14:44:43.610839 3 4 4 |504 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3122 14:44:43.617262 3 4 8 |e0e 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3123 14:44:43.620692 3 4 12 |3d3d 504 |(11 11)(11 11) |(1 1)(1 1)| 0
3124 14:44:43.623944 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3125 14:44:43.627158 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3126 14:44:43.634156 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3127 14:44:43.637728 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3128 14:44:43.640703 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3129 14:44:43.647329 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3130 14:44:43.650999 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3131 14:44:43.654209 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3132 14:44:43.660856 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3133 14:44:43.664288 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3134 14:44:43.667413 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3135 14:44:43.674233 [Byte 0] Lead/lag falling Transition (3, 5, 24)
3136 14:44:43.677385 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3137 14:44:43.680898 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3138 14:44:43.684014 [Byte 0] Lead/lag Transition tap number (3)
3139 14:44:43.690612 3 6 4 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
3140 14:44:43.693688 [Byte 1] Lead/lag falling Transition (3, 6, 4)
3141 14:44:43.696837 3 6 8 |4646 3d3d |(0 0)(11 11) |(0 0)(1 0)| 0
3142 14:44:43.700604 [Byte 0]First pass (3, 6, 8)
3143 14:44:43.704016 [Byte 1] Lead/lag Transition tap number (2)
3144 14:44:43.706876 3 6 12 |4646 3e3d |(0 0)(11 11) |(0 0)(0 0)| 0
3145 14:44:43.713832 3 6 16 |4646 606 |(0 0)(11 11) |(0 0)(0 0)| 0
3146 14:44:43.717348 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3147 14:44:43.720425 [Byte 1]First pass (3, 6, 20)
3148 14:44:43.723686 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3149 14:44:43.727091 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3150 14:44:43.730312 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3151 14:44:43.733680 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3152 14:44:43.740599 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3153 14:44:43.743565 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3154 14:44:43.746952 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3155 14:44:43.750194 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3156 14:44:43.754041 All bytes gating window > 1UI, Early break!
3157 14:44:43.754133
3158 14:44:43.760094 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 30)
3159 14:44:43.760187
3160 14:44:43.764125 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 8)
3161 14:44:43.764218
3162 14:44:43.764291
3163 14:44:43.764359
3164 14:44:43.767166 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 30)
3165 14:44:43.767258
3166 14:44:43.770304 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 8)
3167 14:44:43.770397
3168 14:44:43.770470
3169 14:44:43.773774 Write Rank1 MR1 =0x56
3170 14:44:43.773866
3171 14:44:43.776815 best RODT dly(2T, 0.5T) = (2, 2)
3172 14:44:43.776911
3173 14:44:43.780720 best RODT dly(2T, 0.5T) = (2, 3)
3174 14:44:43.780812 ==
3175 14:44:43.783567 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3176 14:44:43.786838 fsp= 1, odt_onoff= 1, Byte mode= 0
3177 14:44:43.786931 ==
3178 14:44:43.793925 Start DQ dly to find pass range UseTestEngine =0
3179 14:44:43.796754 x-axis: bit #, y-axis: DQ dly (-127~63)
3180 14:44:43.796847 RX Vref Scan = 0
3181 14:44:43.800331 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3182 14:44:43.803604 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3183 14:44:43.807071 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3184 14:44:43.810298 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3185 14:44:43.813702 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3186 14:44:43.813796 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3187 14:44:43.816642 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3188 14:44:43.820183 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3189 14:44:43.823906 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3190 14:44:43.826748 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3191 14:44:43.830034 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3192 14:44:43.833618 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3193 14:44:43.837005 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3194 14:44:43.840441 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3195 14:44:43.840535 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3196 14:44:43.843306 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3197 14:44:43.846906 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3198 14:44:43.850572 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3199 14:44:43.853421 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3200 14:44:43.857048 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3201 14:44:43.860508 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3202 14:44:43.860602 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3203 14:44:43.863387 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3204 14:44:43.867186 -3, [0] xxxxxxxx xxxxxxxo [MSB]
3205 14:44:43.869995 -2, [0] xxxoxxxx xoxxxxxo [MSB]
3206 14:44:43.873399 -1, [0] xxxoxxxx xoxxxxxo [MSB]
3207 14:44:43.877229 0, [0] xxooxxxx ooxxxxxo [MSB]
3208 14:44:43.880088 1, [0] xxooxxxx ooxxxxxo [MSB]
3209 14:44:43.880182 2, [0] xxooxxxo ooxxxxxo [MSB]
3210 14:44:43.883384 3, [0] xxooxxxo oooxxxxo [MSB]
3211 14:44:43.886807 4, [0] oxoooxxo oooxoxxo [MSB]
3212 14:44:43.890316 32, [0] oooooooo ooooooox [MSB]
3213 14:44:43.893429 33, [0] oooooooo ooooooox [MSB]
3214 14:44:43.896864 34, [0] oooooooo ooooooox [MSB]
3215 14:44:43.896957 35, [0] oooxoooo oxooooox [MSB]
3216 14:44:43.900151 36, [0] oooxoooo xxooooox [MSB]
3217 14:44:43.903114 37, [0] ooxxoooo xxooooox [MSB]
3218 14:44:43.906891 38, [0] ooxxoooo xxooooox [MSB]
3219 14:44:43.909885 39, [0] oxxxooox xxooooox [MSB]
3220 14:44:43.913803 40, [0] oxxxxoox xxxoooox [MSB]
3221 14:44:43.916818 41, [0] oxxxxoox xxxxxxox [MSB]
3222 14:44:43.916912 42, [0] xxxxxxxx xxxxxxxx [MSB]
3223 14:44:43.923377 iDelay=42, Bit 0, Center 22 (4 ~ 41) 38
3224 14:44:43.926656 iDelay=42, Bit 1, Center 21 (5 ~ 38) 34
3225 14:44:43.930069 iDelay=42, Bit 2, Center 18 (0 ~ 36) 37
3226 14:44:43.932985 iDelay=42, Bit 3, Center 16 (-2 ~ 34) 37
3227 14:44:43.936444 iDelay=42, Bit 4, Center 21 (4 ~ 39) 36
3228 14:44:43.939724 iDelay=42, Bit 5, Center 23 (5 ~ 41) 37
3229 14:44:43.943018 iDelay=42, Bit 6, Center 23 (5 ~ 41) 37
3230 14:44:43.946348 iDelay=42, Bit 7, Center 20 (2 ~ 38) 37
3231 14:44:43.950033 iDelay=42, Bit 8, Center 17 (0 ~ 35) 36
3232 14:44:43.952920 iDelay=42, Bit 9, Center 16 (-2 ~ 34) 37
3233 14:44:43.956044 iDelay=42, Bit 10, Center 21 (3 ~ 39) 37
3234 14:44:43.959391 iDelay=42, Bit 11, Center 22 (5 ~ 40) 36
3235 14:44:43.966452 iDelay=42, Bit 12, Center 22 (4 ~ 40) 37
3236 14:44:43.969149 iDelay=42, Bit 13, Center 22 (5 ~ 40) 36
3237 14:44:43.972698 iDelay=42, Bit 14, Center 23 (5 ~ 41) 37
3238 14:44:43.975676 iDelay=42, Bit 15, Center 14 (-3 ~ 31) 35
3239 14:44:43.975768 ==
3240 14:44:43.979105 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3241 14:44:43.982626 fsp= 1, odt_onoff= 1, Byte mode= 0
3242 14:44:43.985947 ==
3243 14:44:43.986039 DQS Delay:
3244 14:44:43.986113 DQS0 = 0, DQS1 = 0
3245 14:44:43.988929 DQM Delay:
3246 14:44:43.989021 DQM0 = 20, DQM1 = 19
3247 14:44:43.992355 DQ Delay:
3248 14:44:43.992447 DQ0 =22, DQ1 =21, DQ2 =18, DQ3 =16
3249 14:44:43.995814 DQ4 =21, DQ5 =23, DQ6 =23, DQ7 =20
3250 14:44:43.998960 DQ8 =17, DQ9 =16, DQ10 =21, DQ11 =22
3251 14:44:44.002592 DQ12 =22, DQ13 =22, DQ14 =23, DQ15 =14
3252 14:44:44.002684
3253 14:44:44.005605
3254 14:44:44.005697 DramC Write-DBI off
3255 14:44:44.005770 ==
3256 14:44:44.012541 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3257 14:44:44.015945 fsp= 1, odt_onoff= 1, Byte mode= 0
3258 14:44:44.016038 ==
3259 14:44:44.019276 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3260 14:44:44.019397
3261 14:44:44.022835 Begin, DQ Scan Range 920~1176
3262 14:44:44.022927
3263 14:44:44.023000
3264 14:44:44.023069 TX Vref Scan disable
3265 14:44:44.028959 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
3266 14:44:44.032669 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
3267 14:44:44.035963 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
3268 14:44:44.039333 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
3269 14:44:44.042427 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
3270 14:44:44.045952 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
3271 14:44:44.048783 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
3272 14:44:44.052107 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
3273 14:44:44.055691 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3274 14:44:44.058712 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3275 14:44:44.062255 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3276 14:44:44.065799 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3277 14:44:44.069163 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3278 14:44:44.072104 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3279 14:44:44.075699 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3280 14:44:44.081992 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3281 14:44:44.085478 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3282 14:44:44.088938 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3283 14:44:44.092636 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3284 14:44:44.095571 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3285 14:44:44.098663 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3286 14:44:44.101988 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3287 14:44:44.105475 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3288 14:44:44.108781 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3289 14:44:44.111995 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3290 14:44:44.115016 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3291 14:44:44.118437 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3292 14:44:44.121795 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3293 14:44:44.125294 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3294 14:44:44.128661 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3295 14:44:44.135329 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3296 14:44:44.138760 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3297 14:44:44.141849 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3298 14:44:44.145169 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3299 14:44:44.148516 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3300 14:44:44.152213 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3301 14:44:44.155326 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3302 14:44:44.158578 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3303 14:44:44.161691 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3304 14:44:44.165327 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3305 14:44:44.168747 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3306 14:44:44.171647 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3307 14:44:44.175132 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3308 14:44:44.178056 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3309 14:44:44.181536 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3310 14:44:44.185065 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3311 14:44:44.188518 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3312 14:44:44.191325 967 |3 6 7|[0] xxxxxxxx xxxxxxxo [MSB]
3313 14:44:44.194952 968 |3 6 8|[0] xxxxxxxx oxxxxxxo [MSB]
3314 14:44:44.198066 969 |3 6 9|[0] xxxxxxxx ooxxxxxo [MSB]
3315 14:44:44.204945 970 |3 6 10|[0] xxxxxxxx oooxxxxo [MSB]
3316 14:44:44.208132 971 |3 6 11|[0] xxxxxxxx oooooxoo [MSB]
3317 14:44:44.211479 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB]
3318 14:44:44.214505 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
3319 14:44:44.218286 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
3320 14:44:44.221492 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
3321 14:44:44.224703 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
3322 14:44:44.228068 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
3323 14:44:44.231487 978 |3 6 18|[0] xooooxxx oooooooo [MSB]
3324 14:44:44.234804 979 |3 6 19|[0] ooooooox oooooooo [MSB]
3325 14:44:44.238143 985 |3 6 25|[0] oooooooo ooooooox [MSB]
3326 14:44:44.241558 986 |3 6 26|[0] oooooooo ooooooox [MSB]
3327 14:44:44.248213 987 |3 6 27|[0] oooooooo ooooooox [MSB]
3328 14:44:44.251693 988 |3 6 28|[0] oooooooo xxooooox [MSB]
3329 14:44:44.254968 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
3330 14:44:44.258121 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
3331 14:44:44.261251 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
3332 14:44:44.264521 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
3333 14:44:44.268192 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
3334 14:44:44.271138 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
3335 14:44:44.274896 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
3336 14:44:44.278260 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
3337 14:44:44.281165 997 |3 6 37|[0] oooxoooo xxxxxxxx [MSB]
3338 14:44:44.284844 998 |3 6 38|[0] oooxoooo xxxxxxxx [MSB]
3339 14:44:44.287768 999 |3 6 39|[0] oooxoooo xxxxxxxx [MSB]
3340 14:44:44.291246 1000 |3 6 40|[0] ooxxooox xxxxxxxx [MSB]
3341 14:44:44.294583 1001 |3 6 41|[0] oxxxxoxx xxxxxxxx [MSB]
3342 14:44:44.301794 1002 |3 6 42|[0] xxxxxxxx xxxxxxxx [MSB]
3343 14:44:44.304722 Byte0, DQ PI dly=988, DQM PI dly= 988
3344 14:44:44.308176 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28)
3345 14:44:44.308268
3346 14:44:44.311471 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28)
3347 14:44:44.311564
3348 14:44:44.314938 Byte1, DQ PI dly=977, DQM PI dly= 977
3349 14:44:44.321358 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
3350 14:44:44.321452
3351 14:44:44.324696 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
3352 14:44:44.324794
3353 14:44:44.324867 ==
3354 14:44:44.331107 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3355 14:44:44.331199 fsp= 1, odt_onoff= 1, Byte mode= 0
3356 14:44:44.334357 ==
3357 14:44:44.337994 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3358 14:44:44.338087
3359 14:44:44.341507 Begin, DQ Scan Range 953~1017
3360 14:44:44.341599 Write Rank1 MR14 =0x0
3361 14:44:44.351530
3362 14:44:44.351622 CH=1, VrefRange= 0, VrefLevel = 0
3363 14:44:44.358051 TX Bit0 (983~998) 16 990, Bit8 (970~984) 15 977,
3364 14:44:44.361445 TX Bit1 (982~996) 15 989, Bit9 (971~984) 14 977,
3365 14:44:44.368359 TX Bit2 (979~993) 15 986, Bit10 (974~985) 12 979,
3366 14:44:44.371326 TX Bit3 (978~990) 13 984, Bit11 (975~986) 12 980,
3367 14:44:44.374819 TX Bit4 (981~995) 15 988, Bit12 (976~985) 10 980,
3368 14:44:44.381264 TX Bit5 (983~998) 16 990, Bit13 (976~987) 12 981,
3369 14:44:44.384234 TX Bit6 (982~997) 16 989, Bit14 (975~984) 10 979,
3370 14:44:44.387964 TX Bit7 (984~994) 11 989, Bit15 (968~978) 11 973,
3371 14:44:44.388057
3372 14:44:44.391422 Write Rank1 MR14 =0x2
3373 14:44:44.400644
3374 14:44:44.400736 CH=1, VrefRange= 0, VrefLevel = 2
3375 14:44:44.406600 TX Bit0 (982~998) 17 990, Bit8 (970~984) 15 977,
3376 14:44:44.410105 TX Bit1 (981~997) 17 989, Bit9 (970~984) 15 977,
3377 14:44:44.416966 TX Bit2 (978~994) 17 986, Bit10 (974~985) 12 979,
3378 14:44:44.420273 TX Bit3 (978~991) 14 984, Bit11 (974~987) 14 980,
3379 14:44:44.423672 TX Bit4 (980~996) 17 988, Bit12 (975~985) 11 980,
3380 14:44:44.430237 TX Bit5 (982~998) 17 990, Bit13 (974~988) 15 981,
3381 14:44:44.433253 TX Bit6 (981~998) 18 989, Bit14 (974~985) 12 979,
3382 14:44:44.436611 TX Bit7 (983~995) 13 989, Bit15 (968~979) 12 973,
3383 14:44:44.436705
3384 14:44:44.440030 Write Rank1 MR14 =0x4
3385 14:44:44.449485
3386 14:44:44.449577 CH=1, VrefRange= 0, VrefLevel = 4
3387 14:44:44.456514 TX Bit0 (981~999) 19 990, Bit8 (970~984) 15 977,
3388 14:44:44.459414 TX Bit1 (980~998) 19 989, Bit9 (970~984) 15 977,
3389 14:44:44.466390 TX Bit2 (978~995) 18 986, Bit10 (973~986) 14 979,
3390 14:44:44.469568 TX Bit3 (978~992) 15 985, Bit11 (974~987) 14 980,
3391 14:44:44.473144 TX Bit4 (980~997) 18 988, Bit12 (974~986) 13 980,
3392 14:44:44.479688 TX Bit5 (982~999) 18 990, Bit13 (974~989) 16 981,
3393 14:44:44.483112 TX Bit6 (980~998) 19 989, Bit14 (974~985) 12 979,
3394 14:44:44.486038 TX Bit7 (983~996) 14 989, Bit15 (968~979) 12 973,
3395 14:44:44.486131
3396 14:44:44.489698 Write Rank1 MR14 =0x6
3397 14:44:44.498638
3398 14:44:44.498730 CH=1, VrefRange= 0, VrefLevel = 6
3399 14:44:44.505579 TX Bit0 (982~999) 18 990, Bit8 (969~985) 17 977,
3400 14:44:44.509011 TX Bit1 (980~998) 19 989, Bit9 (970~985) 16 977,
3401 14:44:44.515374 TX Bit2 (978~996) 19 987, Bit10 (973~987) 15 980,
3402 14:44:44.519014 TX Bit3 (977~992) 16 984, Bit11 (973~988) 16 980,
3403 14:44:44.521926 TX Bit4 (979~998) 20 988, Bit12 (974~987) 14 980,
3404 14:44:44.528486 TX Bit5 (981~999) 19 990, Bit13 (974~989) 16 981,
3405 14:44:44.531884 TX Bit6 (980~998) 19 989, Bit14 (973~986) 14 979,
3406 14:44:44.535745 TX Bit7 (983~997) 15 990, Bit15 (968~980) 13 974,
3407 14:44:44.535838
3408 14:44:44.538647 Write Rank1 MR14 =0x8
3409 14:44:44.548608
3410 14:44:44.548700 CH=1, VrefRange= 0, VrefLevel = 8
3411 14:44:44.555066 TX Bit0 (981~1000) 20 990, Bit8 (969~985) 17 977,
3412 14:44:44.558550 TX Bit1 (980~998) 19 989, Bit9 (970~985) 16 977,
3413 14:44:44.564829 TX Bit2 (978~997) 20 987, Bit10 (972~987) 16 979,
3414 14:44:44.568041 TX Bit3 (978~993) 16 985, Bit11 (973~989) 17 981,
3415 14:44:44.571688 TX Bit4 (979~998) 20 988, Bit12 (974~988) 15 981,
3416 14:44:44.578349 TX Bit5 (981~999) 19 990, Bit13 (973~990) 18 981,
3417 14:44:44.581391 TX Bit6 (980~999) 20 989, Bit14 (972~987) 16 979,
3418 14:44:44.584776 TX Bit7 (982~998) 17 990, Bit15 (968~982) 15 975,
3419 14:44:44.584888
3420 14:44:44.587993 Write Rank1 MR14 =0xa
3421 14:44:44.597750
3422 14:44:44.601210 CH=1, VrefRange= 0, VrefLevel = 10
3423 14:44:44.604203 TX Bit0 (981~1000) 20 990, Bit8 (969~986) 18 977,
3424 14:44:44.607692 TX Bit1 (979~999) 21 989, Bit9 (969~985) 17 977,
3425 14:44:44.614170 TX Bit2 (978~997) 20 987, Bit10 (971~988) 18 979,
3426 14:44:44.617761 TX Bit3 (977~993) 17 985, Bit11 (972~990) 19 981,
3427 14:44:44.620606 TX Bit4 (979~998) 20 988, Bit12 (973~989) 17 981,
3428 14:44:44.627223 TX Bit5 (980~1000) 21 990, Bit13 (973~990) 18 981,
3429 14:44:44.630671 TX Bit6 (980~999) 20 989, Bit14 (972~988) 17 980,
3430 14:44:44.637274 TX Bit7 (982~998) 17 990, Bit15 (967~983) 17 975,
3431 14:44:44.637370
3432 14:44:44.637444 Write Rank1 MR14 =0xc
3433 14:44:44.647759
3434 14:44:44.647845 CH=1, VrefRange= 0, VrefLevel = 12
3435 14:44:44.654300 TX Bit0 (980~1000) 21 990, Bit8 (969~986) 18 977,
3436 14:44:44.657305 TX Bit1 (979~999) 21 989, Bit9 (969~986) 18 977,
3437 14:44:44.664252 TX Bit2 (978~998) 21 988, Bit10 (971~989) 19 980,
3438 14:44:44.667604 TX Bit3 (977~994) 18 985, Bit11 (972~990) 19 981,
3439 14:44:44.670775 TX Bit4 (978~999) 22 988, Bit12 (972~990) 19 981,
3440 14:44:44.677420 TX Bit5 (980~1000) 21 990, Bit13 (972~991) 20 981,
3441 14:44:44.680764 TX Bit6 (979~1000) 22 989, Bit14 (971~989) 19 980,
3442 14:44:44.687260 TX Bit7 (981~998) 18 989, Bit15 (967~984) 18 975,
3443 14:44:44.687352
3444 14:44:44.687439 Write Rank1 MR14 =0xe
3445 14:44:44.697253
3446 14:44:44.700570 CH=1, VrefRange= 0, VrefLevel = 14
3447 14:44:44.703884 TX Bit0 (980~1001) 22 990, Bit8 (969~987) 19 978,
3448 14:44:44.707524 TX Bit1 (978~1000) 23 989, Bit9 (969~986) 18 977,
3449 14:44:44.713659 TX Bit2 (978~998) 21 988, Bit10 (971~989) 19 980,
3450 14:44:44.717557 TX Bit3 (977~995) 19 986, Bit11 (971~991) 21 981,
3451 14:44:44.720755 TX Bit4 (978~999) 22 988, Bit12 (971~990) 20 980,
3452 14:44:44.727258 TX Bit5 (980~1001) 22 990, Bit13 (972~991) 20 981,
3453 14:44:44.730799 TX Bit6 (979~1000) 22 989, Bit14 (971~990) 20 980,
3454 14:44:44.737037 TX Bit7 (980~999) 20 989, Bit15 (966~984) 19 975,
3455 14:44:44.737130
3456 14:44:44.737203 Write Rank1 MR14 =0x10
3457 14:44:44.747744
3458 14:44:44.750548 CH=1, VrefRange= 0, VrefLevel = 16
3459 14:44:44.754068 TX Bit0 (979~1001) 23 990, Bit8 (968~987) 20 977,
3460 14:44:44.757508 TX Bit1 (978~1000) 23 989, Bit9 (969~987) 19 978,
3461 14:44:44.764091 TX Bit2 (977~999) 23 988, Bit10 (970~990) 21 980,
3462 14:44:44.767242 TX Bit3 (976~995) 20 985, Bit11 (971~991) 21 981,
3463 14:44:44.770503 TX Bit4 (978~1000) 23 989, Bit12 (971~991) 21 981,
3464 14:44:44.777039 TX Bit5 (979~1001) 23 990, Bit13 (971~992) 22 981,
3465 14:44:44.780742 TX Bit6 (979~1000) 22 989, Bit14 (971~990) 20 980,
3466 14:44:44.787054 TX Bit7 (980~999) 20 989, Bit15 (966~984) 19 975,
3467 14:44:44.787144
3468 14:44:44.787216 Write Rank1 MR14 =0x12
3469 14:44:44.797974
3470 14:44:44.801020 CH=1, VrefRange= 0, VrefLevel = 18
3471 14:44:44.804390 TX Bit0 (979~1002) 24 990, Bit8 (968~988) 21 978,
3472 14:44:44.807877 TX Bit1 (978~1000) 23 989, Bit9 (969~988) 20 978,
3473 14:44:44.814352 TX Bit2 (977~999) 23 988, Bit10 (970~991) 22 980,
3474 14:44:44.817988 TX Bit3 (976~997) 22 986, Bit11 (971~991) 21 981,
3475 14:44:44.820781 TX Bit4 (978~1000) 23 989, Bit12 (971~991) 21 981,
3476 14:44:44.827448 TX Bit5 (979~1002) 24 990, Bit13 (971~992) 22 981,
3477 14:44:44.831049 TX Bit6 (979~1000) 22 989, Bit14 (970~991) 22 980,
3478 14:44:44.837566 TX Bit7 (980~999) 20 989, Bit15 (966~984) 19 975,
3479 14:44:44.837657
3480 14:44:44.837729 Write Rank1 MR14 =0x14
3481 14:44:44.848322
3482 14:44:44.851593 CH=1, VrefRange= 0, VrefLevel = 20
3483 14:44:44.854779 TX Bit0 (979~1002) 24 990, Bit8 (968~988) 21 978,
3484 14:44:44.857699 TX Bit1 (978~1001) 24 989, Bit9 (969~988) 20 978,
3485 14:44:44.864584 TX Bit2 (977~999) 23 988, Bit10 (970~991) 22 980,
3486 14:44:44.868041 TX Bit3 (976~998) 23 987, Bit11 (970~992) 23 981,
3487 14:44:44.871238 TX Bit4 (978~1000) 23 989, Bit12 (970~991) 22 980,
3488 14:44:44.878051 TX Bit5 (979~1002) 24 990, Bit13 (970~992) 23 981,
3489 14:44:44.881106 TX Bit6 (979~1001) 23 990, Bit14 (970~991) 22 980,
3490 14:44:44.887818 TX Bit7 (979~1000) 22 989, Bit15 (966~985) 20 975,
3491 14:44:44.887909
3492 14:44:44.887980 Write Rank1 MR14 =0x16
3493 14:44:44.898547
3494 14:44:44.901896 CH=1, VrefRange= 0, VrefLevel = 22
3495 14:44:44.905273 TX Bit0 (978~1003) 26 990, Bit8 (968~989) 22 978,
3496 14:44:44.908730 TX Bit1 (978~1001) 24 989, Bit9 (969~989) 21 979,
3497 14:44:44.915634 TX Bit2 (977~1000) 24 988, Bit10 (970~991) 22 980,
3498 14:44:44.918337 TX Bit3 (976~998) 23 987, Bit11 (970~992) 23 981,
3499 14:44:44.921696 TX Bit4 (978~1001) 24 989, Bit12 (970~992) 23 981,
3500 14:44:44.928992 TX Bit5 (978~1003) 26 990, Bit13 (970~992) 23 981,
3501 14:44:44.931874 TX Bit6 (978~1001) 24 989, Bit14 (970~991) 22 980,
3502 14:44:44.938374 TX Bit7 (978~1000) 23 989, Bit15 (965~985) 21 975,
3503 14:44:44.938461
3504 14:44:44.938533 Write Rank1 MR14 =0x18
3505 14:44:44.949194
3506 14:44:44.952583 CH=1, VrefRange= 0, VrefLevel = 24
3507 14:44:44.956233 TX Bit0 (978~1003) 26 990, Bit8 (968~990) 23 979,
3508 14:44:44.959277 TX Bit1 (978~1002) 25 990, Bit9 (968~990) 23 979,
3509 14:44:44.966039 TX Bit2 (977~1000) 24 988, Bit10 (970~992) 23 981,
3510 14:44:44.969736 TX Bit3 (975~998) 24 986, Bit11 (970~992) 23 981,
3511 14:44:44.972478 TX Bit4 (978~1001) 24 989, Bit12 (970~992) 23 981,
3512 14:44:44.979204 TX Bit5 (978~1003) 26 990, Bit13 (970~993) 24 981,
3513 14:44:44.982487 TX Bit6 (978~1002) 25 990, Bit14 (970~992) 23 981,
3514 14:44:44.989419 TX Bit7 (978~1000) 23 989, Bit15 (965~986) 22 975,
3515 14:44:44.989511
3516 14:44:44.989585 Write Rank1 MR14 =0x1a
3517 14:44:45.000334
3518 14:44:45.003510 CH=1, VrefRange= 0, VrefLevel = 26
3519 14:44:45.006602 TX Bit0 (978~1004) 27 991, Bit8 (967~991) 25 979,
3520 14:44:45.010142 TX Bit1 (978~1002) 25 990, Bit9 (968~990) 23 979,
3521 14:44:45.016925 TX Bit2 (977~1000) 24 988, Bit10 (969~992) 24 980,
3522 14:44:45.020417 TX Bit3 (975~998) 24 986, Bit11 (970~992) 23 981,
3523 14:44:45.023553 TX Bit4 (977~1002) 26 989, Bit12 (970~992) 23 981,
3524 14:44:45.029825 TX Bit5 (978~1003) 26 990, Bit13 (970~993) 24 981,
3525 14:44:45.033633 TX Bit6 (978~1002) 25 990, Bit14 (970~992) 23 981,
3526 14:44:45.040248 TX Bit7 (978~1001) 24 989, Bit15 (965~986) 22 975,
3527 14:44:45.040341
3528 14:44:45.040414 Write Rank1 MR14 =0x1c
3529 14:44:45.051340
3530 14:44:45.051440 CH=1, VrefRange= 0, VrefLevel = 28
3531 14:44:45.057976 TX Bit0 (978~1005) 28 991, Bit8 (967~991) 25 979,
3532 14:44:45.061524 TX Bit1 (977~1002) 26 989, Bit9 (968~990) 23 979,
3533 14:44:45.067887 TX Bit2 (977~1001) 25 989, Bit10 (969~992) 24 980,
3534 14:44:45.071120 TX Bit3 (975~999) 25 987, Bit11 (970~993) 24 981,
3535 14:44:45.074835 TX Bit4 (977~1002) 26 989, Bit12 (970~992) 23 981,
3536 14:44:45.081221 TX Bit5 (978~1004) 27 991, Bit13 (970~993) 24 981,
3537 14:44:45.084862 TX Bit6 (977~1003) 27 990, Bit14 (970~992) 23 981,
3538 14:44:45.091066 TX Bit7 (978~1002) 25 990, Bit15 (964~987) 24 975,
3539 14:44:45.091159
3540 14:44:45.091232 Write Rank1 MR14 =0x1e
3541 14:44:45.102269
3542 14:44:45.105696 CH=1, VrefRange= 0, VrefLevel = 30
3543 14:44:45.109061 TX Bit0 (978~1005) 28 991, Bit8 (968~991) 24 979,
3544 14:44:45.112402 TX Bit1 (977~1003) 27 990, Bit9 (967~990) 24 978,
3545 14:44:45.118942 TX Bit2 (977~1001) 25 989, Bit10 (969~992) 24 980,
3546 14:44:45.122443 TX Bit3 (974~999) 26 986, Bit11 (969~993) 25 981,
3547 14:44:45.125634 TX Bit4 (978~1003) 26 990, Bit12 (970~993) 24 981,
3548 14:44:45.132340 TX Bit5 (978~1004) 27 991, Bit13 (970~993) 24 981,
3549 14:44:45.135346 TX Bit6 (977~1003) 27 990, Bit14 (969~993) 25 981,
3550 14:44:45.141978 TX Bit7 (978~1002) 25 990, Bit15 (964~987) 24 975,
3551 14:44:45.142065
3552 14:44:45.142137 Write Rank1 MR14 =0x20
3553 14:44:45.153299
3554 14:44:45.156740 CH=1, VrefRange= 0, VrefLevel = 32
3555 14:44:45.160118 TX Bit0 (978~1005) 28 991, Bit8 (968~991) 24 979,
3556 14:44:45.163374 TX Bit1 (977~1003) 27 990, Bit9 (967~990) 24 978,
3557 14:44:45.169818 TX Bit2 (977~1001) 25 989, Bit10 (969~992) 24 980,
3558 14:44:45.173438 TX Bit3 (974~999) 26 986, Bit11 (969~993) 25 981,
3559 14:44:45.176592 TX Bit4 (978~1003) 26 990, Bit12 (970~993) 24 981,
3560 14:44:45.182943 TX Bit5 (978~1004) 27 991, Bit13 (970~993) 24 981,
3561 14:44:45.186344 TX Bit6 (977~1003) 27 990, Bit14 (969~993) 25 981,
3562 14:44:45.193474 TX Bit7 (978~1002) 25 990, Bit15 (964~987) 24 975,
3563 14:44:45.193560
3564 14:44:45.193635 Write Rank1 MR14 =0x22
3565 14:44:45.204397
3566 14:44:45.207304 CH=1, VrefRange= 0, VrefLevel = 34
3567 14:44:45.210765 TX Bit0 (978~1005) 28 991, Bit8 (968~991) 24 979,
3568 14:44:45.214276 TX Bit1 (977~1003) 27 990, Bit9 (967~990) 24 978,
3569 14:44:45.220575 TX Bit2 (977~1001) 25 989, Bit10 (969~992) 24 980,
3570 14:44:45.224191 TX Bit3 (974~999) 26 986, Bit11 (969~993) 25 981,
3571 14:44:45.227182 TX Bit4 (978~1003) 26 990, Bit12 (970~993) 24 981,
3572 14:44:45.233895 TX Bit5 (978~1004) 27 991, Bit13 (970~993) 24 981,
3573 14:44:45.237279 TX Bit6 (977~1003) 27 990, Bit14 (969~993) 25 981,
3574 14:44:45.243945 TX Bit7 (978~1002) 25 990, Bit15 (964~987) 24 975,
3575 14:44:45.244036
3576 14:44:45.244108 Write Rank1 MR14 =0x24
3577 14:44:45.254867
3578 14:44:45.258186 CH=1, VrefRange= 0, VrefLevel = 36
3579 14:44:45.261723 TX Bit0 (978~1005) 28 991, Bit8 (968~991) 24 979,
3580 14:44:45.264604 TX Bit1 (977~1003) 27 990, Bit9 (967~990) 24 978,
3581 14:44:45.271484 TX Bit2 (977~1001) 25 989, Bit10 (969~992) 24 980,
3582 14:44:45.274834 TX Bit3 (974~999) 26 986, Bit11 (969~993) 25 981,
3583 14:44:45.278302 TX Bit4 (978~1003) 26 990, Bit12 (970~993) 24 981,
3584 14:44:45.285349 TX Bit5 (978~1004) 27 991, Bit13 (970~993) 24 981,
3585 14:44:45.288194 TX Bit6 (977~1003) 27 990, Bit14 (969~993) 25 981,
3586 14:44:45.294802 TX Bit7 (978~1002) 25 990, Bit15 (964~987) 24 975,
3587 14:44:45.294895
3588 14:44:45.294969 Write Rank1 MR14 =0x26
3589 14:44:45.305879
3590 14:44:45.308888 CH=1, VrefRange= 0, VrefLevel = 38
3591 14:44:45.312932 TX Bit0 (978~1005) 28 991, Bit8 (968~991) 24 979,
3592 14:44:45.315737 TX Bit1 (977~1003) 27 990, Bit9 (967~990) 24 978,
3593 14:44:45.322424 TX Bit2 (977~1001) 25 989, Bit10 (969~992) 24 980,
3594 14:44:45.325443 TX Bit3 (974~999) 26 986, Bit11 (969~993) 25 981,
3595 14:44:45.328901 TX Bit4 (978~1003) 26 990, Bit12 (970~993) 24 981,
3596 14:44:45.335630 TX Bit5 (978~1004) 27 991, Bit13 (970~993) 24 981,
3597 14:44:45.338975 TX Bit6 (977~1003) 27 990, Bit14 (969~993) 25 981,
3598 14:44:45.345687 TX Bit7 (978~1002) 25 990, Bit15 (964~987) 24 975,
3599 14:44:45.345779
3600 14:44:45.345852
3601 14:44:45.348970 TX Vref found, early break! 379< 384
3602 14:44:45.352090 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
3603 14:44:45.355758 u1DelayCellOfst[0]=6 cells (5 PI)
3604 14:44:45.358655 u1DelayCellOfst[1]=5 cells (4 PI)
3605 14:44:45.362195 u1DelayCellOfst[2]=3 cells (3 PI)
3606 14:44:45.365451 u1DelayCellOfst[3]=0 cells (0 PI)
3607 14:44:45.368830 u1DelayCellOfst[4]=5 cells (4 PI)
3608 14:44:45.371784 u1DelayCellOfst[5]=6 cells (5 PI)
3609 14:44:45.375381 u1DelayCellOfst[6]=5 cells (4 PI)
3610 14:44:45.375508 u1DelayCellOfst[7]=5 cells (4 PI)
3611 14:44:45.378705 Byte0, DQ PI dly=986, DQM PI dly= 988
3612 14:44:45.385371 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
3613 14:44:45.385463
3614 14:44:45.388915 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
3615 14:44:45.389007
3616 14:44:45.392613 u1DelayCellOfst[8]=5 cells (4 PI)
3617 14:44:45.395308 u1DelayCellOfst[9]=3 cells (3 PI)
3618 14:44:45.398669 u1DelayCellOfst[10]=6 cells (5 PI)
3619 14:44:45.402083 u1DelayCellOfst[11]=7 cells (6 PI)
3620 14:44:45.405846 u1DelayCellOfst[12]=7 cells (6 PI)
3621 14:44:45.408627 u1DelayCellOfst[13]=7 cells (6 PI)
3622 14:44:45.411927 u1DelayCellOfst[14]=7 cells (6 PI)
3623 14:44:45.415584 u1DelayCellOfst[15]=0 cells (0 PI)
3624 14:44:45.418835 Byte1, DQ PI dly=975, DQM PI dly= 978
3625 14:44:45.422075 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 15)
3626 14:44:45.422167
3627 14:44:45.425391 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 15)
3628 14:44:45.425482
3629 14:44:45.428763 Write Rank1 MR14 =0x1e
3630 14:44:45.428854
3631 14:44:45.432413 Final TX Range 0 Vref 30
3632 14:44:45.432510
3633 14:44:45.438840 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3634 14:44:45.438931
3635 14:44:45.445369 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3636 14:44:45.452120 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3637 14:44:45.458704 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3638 14:44:45.458795 Write Rank1 MR3 =0xb0
3639 14:44:45.461883 DramC Write-DBI on
3640 14:44:45.461974 ==
3641 14:44:45.465439 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3642 14:44:45.468650 fsp= 1, odt_onoff= 1, Byte mode= 0
3643 14:44:45.471937 ==
3644 14:44:45.475136 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3645 14:44:45.475227
3646 14:44:45.478786 Begin, DQ Scan Range 698~762
3647 14:44:45.478877
3648 14:44:45.478950
3649 14:44:45.479030 TX Vref Scan disable
3650 14:44:45.481809 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3651 14:44:45.485242 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3652 14:44:45.492006 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3653 14:44:45.495462 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3654 14:44:45.498442 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3655 14:44:45.502181 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3656 14:44:45.505319 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3657 14:44:45.509054 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3658 14:44:45.511696 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3659 14:44:45.515039 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3660 14:44:45.518696 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3661 14:44:45.522173 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3662 14:44:45.525134 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3663 14:44:45.528737 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
3664 14:44:45.532156 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
3665 14:44:45.535222 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
3666 14:44:45.539011 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
3667 14:44:45.541880 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
3668 14:44:45.545511 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3669 14:44:45.548716 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
3670 14:44:45.551742 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3671 14:44:45.555188 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3672 14:44:45.558745 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3673 14:44:45.564925 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3674 14:44:45.568383 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
3675 14:44:45.571702 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
3676 14:44:45.575157 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
3677 14:44:45.581754 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
3678 14:44:45.585318 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
3679 14:44:45.588115 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
3680 14:44:45.591822 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
3681 14:44:45.594696 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3682 14:44:45.598241 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3683 14:44:45.601626 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3684 14:44:45.605096 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3685 14:44:45.608135 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3686 14:44:45.611571 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3687 14:44:45.615142 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3688 14:44:45.618008 750 |2 6 46|[0] xxxxxxxx xxxxxxxx [MSB]
3689 14:44:45.621434 Byte0, DQ PI dly=735, DQM PI dly= 735
3690 14:44:45.628509 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 31)
3691 14:44:45.628655
3692 14:44:45.631393 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 31)
3693 14:44:45.631567
3694 14:44:45.634834 Byte1, DQ PI dly=723, DQM PI dly= 723
3695 14:44:45.637726 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 19)
3696 14:44:45.637847
3697 14:44:45.644508 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 19)
3698 14:44:45.644632
3699 14:44:45.651138 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3700 14:44:45.658284 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3701 14:44:45.665118 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3702 14:44:45.665212 Write Rank1 MR3 =0x30
3703 14:44:45.667971 DramC Write-DBI off
3704 14:44:45.668063
3705 14:44:45.668136 [DATLAT]
3706 14:44:45.671517 Freq=1600, CH1 RK1, use_rxtx_scan=0
3707 14:44:45.671611
3708 14:44:45.674636 DATLAT Default: 0x10
3709 14:44:45.674727 7, 0xFFFF, sum=0
3710 14:44:45.677792 8, 0xFFFF, sum=0
3711 14:44:45.677889 9, 0xFFFF, sum=0
3712 14:44:45.681182 10, 0xFFFF, sum=0
3713 14:44:45.681276 11, 0xFFFF, sum=0
3714 14:44:45.685007 12, 0xFFFF, sum=0
3715 14:44:45.685100 13, 0xFFFF, sum=0
3716 14:44:45.687616 14, 0x0, sum=1
3717 14:44:45.687713 15, 0x0, sum=2
3718 14:44:45.687812 16, 0x0, sum=3
3719 14:44:45.691150 17, 0x0, sum=4
3720 14:44:45.694358 pattern=2 first_step=14 total pass=5 best_step=16
3721 14:44:45.694452 ==
3722 14:44:45.701155 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3723 14:44:45.704655 fsp= 1, odt_onoff= 1, Byte mode= 0
3724 14:44:45.704750 ==
3725 14:44:45.707865 Start DQ dly to find pass range UseTestEngine =1
3726 14:44:45.711062 x-axis: bit #, y-axis: DQ dly (-127~63)
3727 14:44:45.714531 RX Vref Scan = 0
3728 14:44:45.717590 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3729 14:44:45.717687 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3730 14:44:45.721048 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3731 14:44:45.724694 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3732 14:44:45.727946 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3733 14:44:45.731015 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3734 14:44:45.734599 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3735 14:44:45.737445 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3736 14:44:45.741006 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3737 14:44:45.741104 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3738 14:44:45.744164 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3739 14:44:45.747707 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3740 14:44:45.750835 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3741 14:44:45.754189 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3742 14:44:45.757900 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3743 14:44:45.761439 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3744 14:44:45.763988 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3745 14:44:45.767899 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3746 14:44:45.767997 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3747 14:44:45.770679 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3748 14:44:45.774473 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3749 14:44:45.777553 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3750 14:44:45.780818 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3751 14:44:45.784425 -3, [0] xxxxxxxx xxxxxxxo [MSB]
3752 14:44:45.787741 -2, [0] xxxoxxxx xoxxxxxo [MSB]
3753 14:44:45.787837 -1, [0] xxxoxxxx xoxxxxxo [MSB]
3754 14:44:45.790640 0, [0] xxxoxxxx ooxxxxxo [MSB]
3755 14:44:45.794112 1, [0] xxooxxxx ooxxxxxo [MSB]
3756 14:44:45.797655 2, [0] xxooxxxx ooxxxxxo [MSB]
3757 14:44:45.800569 3, [0] xxooxxxo ooxxxxxo [MSB]
3758 14:44:45.804204 4, [0] oooooxxo ooooooxo [MSB]
3759 14:44:45.807144 32, [0] oooooooo ooooooox [MSB]
3760 14:44:45.810841 33, [0] oooooooo ooooooox [MSB]
3761 14:44:45.813955 34, [0] oooooooo ooooooox [MSB]
3762 14:44:45.817401 35, [0] oooxoooo oxooooox [MSB]
3763 14:44:45.820289 36, [0] oooxoooo xxooooox [MSB]
3764 14:44:45.820383 37, [0] ooxxoooo xxooooox [MSB]
3765 14:44:45.823838 38, [0] ooxxoooo xxooooox [MSB]
3766 14:44:45.827150 39, [0] ooxxooox xxxoooox [MSB]
3767 14:44:45.830303 40, [0] oxxxxoox xxxooxox [MSB]
3768 14:44:45.833713 41, [0] xxxxxxox xxxxxxxx [MSB]
3769 14:44:45.837226 42, [0] xxxxxxxx xxxxxxxx [MSB]
3770 14:44:45.840708 iDelay=42, Bit 0, Center 22 (4 ~ 40) 37
3771 14:44:45.843661 iDelay=42, Bit 1, Center 21 (4 ~ 39) 36
3772 14:44:45.847217 iDelay=42, Bit 2, Center 18 (1 ~ 36) 36
3773 14:44:45.850714 iDelay=42, Bit 3, Center 16 (-2 ~ 34) 37
3774 14:44:45.853603 iDelay=42, Bit 4, Center 21 (4 ~ 39) 36
3775 14:44:45.857143 iDelay=42, Bit 5, Center 22 (5 ~ 40) 36
3776 14:44:45.860670 iDelay=42, Bit 6, Center 23 (5 ~ 41) 37
3777 14:44:45.863643 iDelay=42, Bit 7, Center 20 (3 ~ 38) 36
3778 14:44:45.866967 iDelay=42, Bit 8, Center 17 (0 ~ 35) 36
3779 14:44:45.870352 iDelay=42, Bit 9, Center 16 (-2 ~ 34) 37
3780 14:44:45.873644 iDelay=42, Bit 10, Center 21 (4 ~ 38) 35
3781 14:44:45.880020 iDelay=42, Bit 11, Center 22 (4 ~ 40) 37
3782 14:44:45.883505 iDelay=42, Bit 12, Center 22 (4 ~ 40) 37
3783 14:44:45.886761 iDelay=42, Bit 13, Center 21 (4 ~ 39) 36
3784 14:44:45.890586 iDelay=42, Bit 14, Center 22 (5 ~ 40) 36
3785 14:44:45.893876 iDelay=42, Bit 15, Center 14 (-3 ~ 31) 35
3786 14:44:45.893971 ==
3787 14:44:45.897179 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3788 14:44:45.900238 fsp= 1, odt_onoff= 1, Byte mode= 0
3789 14:44:45.903567 ==
3790 14:44:45.903662 DQS Delay:
3791 14:44:45.903758 DQS0 = 0, DQS1 = 0
3792 14:44:45.907215 DQM Delay:
3793 14:44:45.907310 DQM0 = 20, DQM1 = 19
3794 14:44:45.910484 DQ Delay:
3795 14:44:45.910579 DQ0 =22, DQ1 =21, DQ2 =18, DQ3 =16
3796 14:44:45.913657 DQ4 =21, DQ5 =22, DQ6 =23, DQ7 =20
3797 14:44:45.916567 DQ8 =17, DQ9 =16, DQ10 =21, DQ11 =22
3798 14:44:45.920048 DQ12 =22, DQ13 =21, DQ14 =22, DQ15 =14
3799 14:44:45.923547
3800 14:44:45.923641
3801 14:44:45.923737
3802 14:44:45.923827 [DramC_TX_OE_Calibration] TA2
3803 14:44:45.926627 Original DQ_B0 (3 6) =30, OEN = 27
3804 14:44:45.929862 Original DQ_B1 (3 6) =30, OEN = 27
3805 14:44:45.933521 23, 0x0, End_B0=23 End_B1=23
3806 14:44:45.936623 24, 0x0, End_B0=24 End_B1=24
3807 14:44:45.940071 25, 0x0, End_B0=25 End_B1=25
3808 14:44:45.940168 26, 0x0, End_B0=26 End_B1=26
3809 14:44:45.943595 27, 0x0, End_B0=27 End_B1=27
3810 14:44:45.947049 28, 0x0, End_B0=28 End_B1=28
3811 14:44:45.949828 29, 0x0, End_B0=29 End_B1=29
3812 14:44:45.949925 30, 0x0, End_B0=30 End_B1=30
3813 14:44:45.953259 31, 0xFFFF, End_B0=30 End_B1=30
3814 14:44:45.959795 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3815 14:44:45.966777 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3816 14:44:45.966873
3817 14:44:45.966969
3818 14:44:45.967080 Write Rank1 MR23 =0x3f
3819 14:44:45.969795 [DQSOSC]
3820 14:44:45.976441 [DQSOSCAuto] RK1, (LSB)MR18= 0xcdcd, (MSB)MR19= 0x202, tDQSOscB0 = 439 ps tDQSOscB1 = 439 ps
3821 14:44:45.983354 CH1_RK1: MR19=0x202, MR18=0xCDCD, DQSOSC=439, MR23=63, INC=12, DEC=19
3822 14:44:45.986650 Write Rank1 MR23 =0x3f
3823 14:44:45.986745 [DQSOSC]
3824 14:44:45.993082 [DQSOSCAuto] RK1, (LSB)MR18= 0xcece, (MSB)MR19= 0x202, tDQSOscB0 = 438 ps tDQSOscB1 = 438 ps
3825 14:44:45.996178 CH1 RK1: MR19=202, MR18=CECE
3826 14:44:46.000113 [RxdqsGatingPostProcess] freq 1600
3827 14:44:46.006774 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3828 14:44:46.006870 Rank: 0
3829 14:44:46.009892 best DQS0 dly(2T, 0.5T) = (2, 6)
3830 14:44:46.013013 best DQS1 dly(2T, 0.5T) = (2, 6)
3831 14:44:46.016469 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3832 14:44:46.019757 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3833 14:44:46.019879 Rank: 1
3834 14:44:46.022944 best DQS0 dly(2T, 0.5T) = (2, 5)
3835 14:44:46.026818 best DQS1 dly(2T, 0.5T) = (2, 6)
3836 14:44:46.030106 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
3837 14:44:46.030202 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3838 14:44:46.036478 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3839 14:44:46.039817 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3840 14:44:46.042872 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3841 14:44:46.042966
3842 14:44:46.043062
3843 14:44:46.046431 [Calibration Summary] Freqency 1600
3844 14:44:46.050081 CH 0, Rank 0
3845 14:44:46.050175 All Pass.
3846 14:44:46.050273
3847 14:44:46.050363 CH 0, Rank 1
3848 14:44:46.052930 All Pass.
3849 14:44:46.053024
3850 14:44:46.053120 CH 1, Rank 0
3851 14:44:46.053210 All Pass.
3852 14:44:46.056482
3853 14:44:46.056576 CH 1, Rank 1
3854 14:44:46.056673 All Pass.
3855 14:44:46.056764
3856 14:44:46.062882 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3857 14:44:46.069990 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3858 14:44:46.076557 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3859 14:44:46.079788 Write Rank0 MR3 =0xb0
3860 14:44:46.086164 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3861 14:44:46.093214 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3862 14:44:46.099945 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3863 14:44:46.103239 Write Rank1 MR3 =0xb0
3864 14:44:46.109787 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3865 14:44:46.116641 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3866 14:44:46.123187 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3867 14:44:46.123283 Write Rank0 MR3 =0xb0
3868 14:44:46.129607 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3869 14:44:46.136226 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3870 14:44:46.146550 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3871 14:44:46.146646 Write Rank1 MR3 =0xb0
3872 14:44:46.149597 DramC Write-DBI on
3873 14:44:46.153094 [GetDramInforAfterCalByMRR] Vendor 6.
3874 14:44:46.156484 [GetDramInforAfterCalByMRR] Revision 505.
3875 14:44:46.156580 MR8 1111
3876 14:44:46.162789 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3877 14:44:46.162881 MR8 1111
3878 14:44:46.166233 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3879 14:44:46.169802 MR8 1111
3880 14:44:46.172656 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3881 14:44:46.172748 MR8 1111
3882 14:44:46.179397 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3883 14:44:46.186290 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3884 14:44:46.189221 Write Rank0 MR13 =0xd0
3885 14:44:46.192675 Write Rank1 MR13 =0xd0
3886 14:44:46.192767 Write Rank0 MR13 =0xd0
3887 14:44:46.196111 Write Rank1 MR13 =0xd0
3888 14:44:46.199233 Save calibration result to emmc
3889 14:44:46.199324
3890 14:44:46.199397
3891 14:44:46.202670 [DramcModeReg_Check] Freq_1600, FSP_1
3892 14:44:46.202760 FSP_1, CH_0, RK0
3893 14:44:46.205971 Write Rank0 MR13 =0xd8
3894 14:44:46.209329 MR12 = 0x5e (global = 0x5e) match
3895 14:44:46.212401 MR14 = 0x1e (global = 0x1e) match
3896 14:44:46.212494 FSP_1, CH_0, RK1
3897 14:44:46.215761 Write Rank1 MR13 =0xd8
3898 14:44:46.219262 MR12 = 0x5c (global = 0x5c) match
3899 14:44:46.222692 MR14 = 0x1e (global = 0x1e) match
3900 14:44:46.222783 FSP_1, CH_1, RK0
3901 14:44:46.225744 Write Rank0 MR13 =0xd8
3902 14:44:46.229213 MR12 = 0x5e (global = 0x5e) match
3903 14:44:46.232210 MR14 = 0x1e (global = 0x1e) match
3904 14:44:46.232302 FSP_1, CH_1, RK1
3905 14:44:46.235858 Write Rank1 MR13 =0xd8
3906 14:44:46.238931 MR12 = 0x60 (global = 0x60) match
3907 14:44:46.242282 MR14 = 0x1e (global = 0x1e) match
3908 14:44:46.242373
3909 14:44:46.245968 [MEM_TEST] 02: After DFS, before run time config
3910 14:44:46.257646 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3911 14:44:46.257738
3912 14:44:46.257810 [TA2_TEST]
3913 14:44:46.257877 === TA2 HW
3914 14:44:46.260791 TA2 PAT: XTALK
3915 14:44:46.264046 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
3916 14:44:46.270585 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
3917 14:44:46.274159 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
3918 14:44:46.280893 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
3919 14:44:46.280984
3920 14:44:46.281056
3921 14:44:46.281123 Settings after calibration
3922 14:44:46.281188
3923 14:44:46.284094 [DramcRunTimeConfig]
3924 14:44:46.287473 TransferPLLToSPMControl - MODE SW PHYPLL
3925 14:44:46.290432 TX_TRACKING: ON
3926 14:44:46.290522 RX_TRACKING: ON
3927 14:44:46.290595 HW_GATING: ON
3928 14:44:46.294092 HW_GATING DBG: OFF
3929 14:44:46.294183 ddr_geometry:1
3930 14:44:46.297015 ddr_geometry:1
3931 14:44:46.297105 ddr_geometry:1
3932 14:44:46.300603 ddr_geometry:1
3933 14:44:46.300694 ddr_geometry:1
3934 14:44:46.300766 ddr_geometry:1
3935 14:44:46.303953 ddr_geometry:1
3936 14:44:46.304043 ddr_geometry:1
3937 14:44:46.307280 High Freq DUMMY_READ_FOR_TRACKING: ON
3938 14:44:46.310380 ZQCS_ENABLE_LP4: OFF
3939 14:44:46.313750 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
3940 14:44:46.317150 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
3941 14:44:46.317241 SPM_CONTROL_AFTERK: ON
3942 14:44:46.320251 IMPEDANCE_TRACKING: ON
3943 14:44:46.320341 TEMP_SENSOR: ON
3944 14:44:46.323420 PER_BANK_REFRESH: ON
3945 14:44:46.323512 HW_SAVE_FOR_SR: ON
3946 14:44:46.330496 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3947 14:44:46.330587 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
3948 14:44:46.336860 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
3949 14:44:46.336951 Read ODT Tracking: ON
3950 14:44:46.340240 =========================
3951 14:44:46.340330
3952 14:44:46.340403 [TA2_TEST]
3953 14:44:46.340470 === TA2 HW
3954 14:44:46.346954 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
3955 14:44:46.350326 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
3956 14:44:46.356894 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
3957 14:44:46.360214 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
3958 14:44:46.360304
3959 14:44:46.363520 [MEM_TEST] 03: After run time config
3960 14:44:46.375298 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3961 14:44:46.378784 [complex_mem_test] start addr:0x40024000, len:131072
3962 14:44:46.582927 1st complex R/W mem test pass
3963 14:44:46.589641 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
3964 14:44:46.592844 sync preloader write leveling
3965 14:44:46.596224 sync preloader cbt_mr12
3966 14:44:46.599343 sync preloader cbt_clk_dly
3967 14:44:46.599441 sync preloader cbt_cmd_dly
3968 14:44:46.602814 sync preloader cbt_cs
3969 14:44:46.606004 sync preloader cbt_ca_perbit_delay
3970 14:44:46.606095 sync preloader clk_delay
3971 14:44:46.609192 sync preloader dqs_delay
3972 14:44:46.612887 sync preloader u1Gating2T_Save
3973 14:44:46.616212 sync preloader u1Gating05T_Save
3974 14:44:46.619272 sync preloader u1Gatingfine_tune_Save
3975 14:44:46.622683 sync preloader u1Gatingucpass_count_Save
3976 14:44:46.626124 sync preloader u1TxWindowPerbitVref_Save
3977 14:44:46.629850 sync preloader u1TxCenter_min_Save
3978 14:44:46.633295 sync preloader u1TxCenter_max_Save
3979 14:44:46.636541 sync preloader u1Txwin_center_Save
3980 14:44:46.639734 sync preloader u1Txfirst_pass_Save
3981 14:44:46.642576 sync preloader u1Txlast_pass_Save
3982 14:44:46.642666 sync preloader u1RxDatlat_Save
3983 14:44:46.646313 sync preloader u1RxWinPerbitVref_Save
3984 14:44:46.652690 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3985 14:44:46.656148 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3986 14:44:46.659613 sync preloader delay_cell_unit
3987 14:44:46.665983 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
3988 14:44:46.669221 sync preloader write leveling
3989 14:44:46.669344 sync preloader cbt_mr12
3990 14:44:46.672539 sync preloader cbt_clk_dly
3991 14:44:46.675762 sync preloader cbt_cmd_dly
3992 14:44:46.675896 sync preloader cbt_cs
3993 14:44:46.679144 sync preloader cbt_ca_perbit_delay
3994 14:44:46.682609 sync preloader clk_delay
3995 14:44:46.685607 sync preloader dqs_delay
3996 14:44:46.685735 sync preloader u1Gating2T_Save
3997 14:44:46.689210 sync preloader u1Gating05T_Save
3998 14:44:46.692727 sync preloader u1Gatingfine_tune_Save
3999 14:44:46.695646 sync preloader u1Gatingucpass_count_Save
4000 14:44:46.702140 sync preloader u1TxWindowPerbitVref_Save
4001 14:44:46.705816 sync preloader u1TxCenter_min_Save
4002 14:44:46.705907 sync preloader u1TxCenter_max_Save
4003 14:44:46.708996 sync preloader u1Txwin_center_Save
4004 14:44:46.712547 sync preloader u1Txfirst_pass_Save
4005 14:44:46.715297 sync preloader u1Txlast_pass_Save
4006 14:44:46.718712 sync preloader u1RxDatlat_Save
4007 14:44:46.722034 sync preloader u1RxWinPerbitVref_Save
4008 14:44:46.725413 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4009 14:44:46.731983 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4010 14:44:46.732075 sync preloader delay_cell_unit
4011 14:44:46.738731 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
4012 14:44:46.741995 sync preloader write leveling
4013 14:44:46.745590 sync preloader cbt_mr12
4014 14:44:46.748925 sync preloader cbt_clk_dly
4015 14:44:46.749016 sync preloader cbt_cmd_dly
4016 14:44:46.751937 sync preloader cbt_cs
4017 14:44:46.755764 sync preloader cbt_ca_perbit_delay
4018 14:44:46.758698 sync preloader clk_delay
4019 14:44:46.758789 sync preloader dqs_delay
4020 14:44:46.762139 sync preloader u1Gating2T_Save
4021 14:44:46.765590 sync preloader u1Gating05T_Save
4022 14:44:46.769095 sync preloader u1Gatingfine_tune_Save
4023 14:44:46.772090 sync preloader u1Gatingucpass_count_Save
4024 14:44:46.775337 sync preloader u1TxWindowPerbitVref_Save
4025 14:44:46.778771 sync preloader u1TxCenter_min_Save
4026 14:44:46.782166 sync preloader u1TxCenter_max_Save
4027 14:44:46.785226 sync preloader u1Txwin_center_Save
4028 14:44:46.788796 sync preloader u1Txfirst_pass_Save
4029 14:44:46.791779 sync preloader u1Txlast_pass_Save
4030 14:44:46.795085 sync preloader u1RxDatlat_Save
4031 14:44:46.798524 sync preloader u1RxWinPerbitVref_Save
4032 14:44:46.802040 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4033 14:44:46.805301 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4034 14:44:46.808748 sync preloader delay_cell_unit
4035 14:44:46.812142 just_for_test_dump_coreboot_params dump all params
4036 14:44:46.815361 dump source = 0x0
4037 14:44:46.815459 dump params frequency:1600
4038 14:44:46.818952 dump params rank number:2
4039 14:44:46.819043
4040 14:44:46.821840 dump params write leveling
4041 14:44:46.825294 write leveling[0][0][0] = 0x20
4042 14:44:46.828643 write leveling[0][0][1] = 0x17
4043 14:44:46.828735 write leveling[0][1][0] = 0x1a
4044 14:44:46.832198 write leveling[0][1][1] = 0x18
4045 14:44:46.835221 write leveling[1][0][0] = 0x21
4046 14:44:46.838649 write leveling[1][0][1] = 0x18
4047 14:44:46.841949 write leveling[1][1][0] = 0x22
4048 14:44:46.845109 write leveling[1][1][1] = 0x18
4049 14:44:46.845199 dump params cbt_cs
4050 14:44:46.848579 cbt_cs[0][0] = 0x8
4051 14:44:46.848669 cbt_cs[0][1] = 0x8
4052 14:44:46.851959 cbt_cs[1][0] = 0xb
4053 14:44:46.852050 cbt_cs[1][1] = 0xb
4054 14:44:46.855182 dump params cbt_mr12
4055 14:44:46.855309 cbt_mr12[0][0] = 0x1e
4056 14:44:46.858343 cbt_mr12[0][1] = 0x1c
4057 14:44:46.861568 cbt_mr12[1][0] = 0x1e
4058 14:44:46.861659 cbt_mr12[1][1] = 0x20
4059 14:44:46.865305 dump params tx window
4060 14:44:46.868511 tx_center_min[0][0][0] = 981
4061 14:44:46.868602 tx_center_max[0][0][0] = 988
4062 14:44:46.871795 tx_center_min[0][0][1] = 973
4063 14:44:46.875265 tx_center_max[0][0][1] = 980
4064 14:44:46.878091 tx_center_min[0][1][0] = 979
4065 14:44:46.878183 tx_center_max[0][1][0] = 985
4066 14:44:46.881711 tx_center_min[0][1][1] = 978
4067 14:44:46.885016 tx_center_max[0][1][1] = 984
4068 14:44:46.888052 tx_center_min[1][0][0] = 988
4069 14:44:46.891740 tx_center_max[1][0][0] = 993
4070 14:44:46.891832 tx_center_min[1][0][1] = 977
4071 14:44:46.894987 tx_center_max[1][0][1] = 983
4072 14:44:46.898040 tx_center_min[1][1][0] = 986
4073 14:44:46.901422 tx_center_max[1][1][0] = 991
4074 14:44:46.904709 tx_center_min[1][1][1] = 975
4075 14:44:46.904800 tx_center_max[1][1][1] = 981
4076 14:44:46.908305 dump params tx window
4077 14:44:46.911623 tx_win_center[0][0][0] = 988
4078 14:44:46.914648 tx_first_pass[0][0][0] = 976
4079 14:44:46.914739 tx_last_pass[0][0][0] = 1000
4080 14:44:46.917990 tx_win_center[0][0][1] = 987
4081 14:44:46.921399 tx_first_pass[0][0][1] = 976
4082 14:44:46.924906 tx_last_pass[0][0][1] = 999
4083 14:44:46.924998 tx_win_center[0][0][2] = 987
4084 14:44:46.928508 tx_first_pass[0][0][2] = 976
4085 14:44:46.931511 tx_last_pass[0][0][2] = 999
4086 14:44:46.935155 tx_win_center[0][0][3] = 981
4087 14:44:46.938269 tx_first_pass[0][0][3] = 969
4088 14:44:46.938360 tx_last_pass[0][0][3] = 993
4089 14:44:46.941677 tx_win_center[0][0][4] = 987
4090 14:44:46.945054 tx_first_pass[0][0][4] = 975
4091 14:44:46.948058 tx_last_pass[0][0][4] = 999
4092 14:44:46.948149 tx_win_center[0][0][5] = 983
4093 14:44:46.951611 tx_first_pass[0][0][5] = 972
4094 14:44:46.955244 tx_last_pass[0][0][5] = 995
4095 14:44:46.958247 tx_win_center[0][0][6] = 985
4096 14:44:46.961280 tx_first_pass[0][0][6] = 973
4097 14:44:46.961374 tx_last_pass[0][0][6] = 998
4098 14:44:46.964804 tx_win_center[0][0][7] = 987
4099 14:44:46.968094 tx_first_pass[0][0][7] = 975
4100 14:44:46.971311 tx_last_pass[0][0][7] = 999
4101 14:44:46.971409 tx_win_center[0][0][8] = 973
4102 14:44:46.974588 tx_first_pass[0][0][8] = 962
4103 14:44:46.977964 tx_last_pass[0][0][8] = 985
4104 14:44:46.981285 tx_win_center[0][0][9] = 976
4105 14:44:46.984464 tx_first_pass[0][0][9] = 965
4106 14:44:46.984566 tx_last_pass[0][0][9] = 988
4107 14:44:46.987908 tx_win_center[0][0][10] = 980
4108 14:44:46.991340 tx_first_pass[0][0][10] = 968
4109 14:44:46.994975 tx_last_pass[0][0][10] = 993
4110 14:44:46.997688 tx_win_center[0][0][11] = 974
4111 14:44:46.997779 tx_first_pass[0][0][11] = 963
4112 14:44:47.001175 tx_last_pass[0][0][11] = 986
4113 14:44:47.004759 tx_win_center[0][0][12] = 978
4114 14:44:47.007811 tx_first_pass[0][0][12] = 966
4115 14:44:47.011376 tx_last_pass[0][0][12] = 990
4116 14:44:47.011481 tx_win_center[0][0][13] = 976
4117 14:44:47.014738 tx_first_pass[0][0][13] = 965
4118 14:44:47.017788 tx_last_pass[0][0][13] = 988
4119 14:44:47.021201 tx_win_center[0][0][14] = 978
4120 14:44:47.024652 tx_first_pass[0][0][14] = 966
4121 14:44:47.024743 tx_last_pass[0][0][14] = 990
4122 14:44:47.028239 tx_win_center[0][0][15] = 980
4123 14:44:47.031326 tx_first_pass[0][0][15] = 968
4124 14:44:47.034553 tx_last_pass[0][0][15] = 992
4125 14:44:47.038180 tx_win_center[0][1][0] = 985
4126 14:44:47.038271 tx_first_pass[0][1][0] = 973
4127 14:44:47.041386 tx_last_pass[0][1][0] = 998
4128 14:44:47.044412 tx_win_center[0][1][1] = 984
4129 14:44:47.048116 tx_first_pass[0][1][1] = 972
4130 14:44:47.048207 tx_last_pass[0][1][1] = 996
4131 14:44:47.051464 tx_win_center[0][1][2] = 985
4132 14:44:47.054277 tx_first_pass[0][1][2] = 974
4133 14:44:47.057857 tx_last_pass[0][1][2] = 997
4134 14:44:47.061574 tx_win_center[0][1][3] = 979
4135 14:44:47.061665 tx_first_pass[0][1][3] = 967
4136 14:44:47.064353 tx_last_pass[0][1][3] = 991
4137 14:44:47.067577 tx_win_center[0][1][4] = 983
4138 14:44:47.071049 tx_first_pass[0][1][4] = 970
4139 14:44:47.071140 tx_last_pass[0][1][4] = 996
4140 14:44:47.074454 tx_win_center[0][1][5] = 981
4141 14:44:47.077734 tx_first_pass[0][1][5] = 969
4142 14:44:47.081437 tx_last_pass[0][1][5] = 993
4143 14:44:47.084522 tx_win_center[0][1][6] = 981
4144 14:44:47.084614 tx_first_pass[0][1][6] = 969
4145 14:44:47.087570 tx_last_pass[0][1][6] = 994
4146 14:44:47.091339 tx_win_center[0][1][7] = 983
4147 14:44:47.094280 tx_first_pass[0][1][7] = 970
4148 14:44:47.094371 tx_last_pass[0][1][7] = 996
4149 14:44:47.097818 tx_win_center[0][1][8] = 978
4150 14:44:47.100949 tx_first_pass[0][1][8] = 966
4151 14:44:47.104181 tx_last_pass[0][1][8] = 990
4152 14:44:47.107877 tx_win_center[0][1][9] = 979
4153 14:44:47.107968 tx_first_pass[0][1][9] = 968
4154 14:44:47.110837 tx_last_pass[0][1][9] = 991
4155 14:44:47.114141 tx_win_center[0][1][10] = 984
4156 14:44:47.117546 tx_first_pass[0][1][10] = 972
4157 14:44:47.120993 tx_last_pass[0][1][10] = 997
4158 14:44:47.121085 tx_win_center[0][1][11] = 979
4159 14:44:47.124399 tx_first_pass[0][1][11] = 967
4160 14:44:47.127784 tx_last_pass[0][1][11] = 991
4161 14:44:47.130707 tx_win_center[0][1][12] = 980
4162 14:44:47.134207 tx_first_pass[0][1][12] = 968
4163 14:44:47.134299 tx_last_pass[0][1][12] = 992
4164 14:44:47.137665 tx_win_center[0][1][13] = 980
4165 14:44:47.140824 tx_first_pass[0][1][13] = 969
4166 14:44:47.144084 tx_last_pass[0][1][13] = 991
4167 14:44:47.147525 tx_win_center[0][1][14] = 980
4168 14:44:47.147616 tx_first_pass[0][1][14] = 968
4169 14:44:47.150836 tx_last_pass[0][1][14] = 992
4170 14:44:47.154298 tx_win_center[0][1][15] = 983
4171 14:44:47.157912 tx_first_pass[0][1][15] = 970
4172 14:44:47.160724 tx_last_pass[0][1][15] = 996
4173 14:44:47.160815 tx_win_center[1][0][0] = 992
4174 14:44:47.164373 tx_first_pass[1][0][0] = 979
4175 14:44:47.167739 tx_last_pass[1][0][0] = 1006
4176 14:44:47.170637 tx_win_center[1][0][1] = 990
4177 14:44:47.174153 tx_first_pass[1][0][1] = 978
4178 14:44:47.174244 tx_last_pass[1][0][1] = 1003
4179 14:44:47.177695 tx_win_center[1][0][2] = 989
4180 14:44:47.180535 tx_first_pass[1][0][2] = 977
4181 14:44:47.183980 tx_last_pass[1][0][2] = 1002
4182 14:44:47.184072 tx_win_center[1][0][3] = 988
4183 14:44:47.187266 tx_first_pass[1][0][3] = 976
4184 14:44:47.191027 tx_last_pass[1][0][3] = 1000
4185 14:44:47.193871 tx_win_center[1][0][4] = 991
4186 14:44:47.197395 tx_first_pass[1][0][4] = 979
4187 14:44:47.197487 tx_last_pass[1][0][4] = 1004
4188 14:44:47.200935 tx_win_center[1][0][5] = 993
4189 14:44:47.204031 tx_first_pass[1][0][5] = 980
4190 14:44:47.207512 tx_last_pass[1][0][5] = 1006
4191 14:44:47.211085 tx_win_center[1][0][6] = 991
4192 14:44:47.211176 tx_first_pass[1][0][6] = 978
4193 14:44:47.214288 tx_last_pass[1][0][6] = 1004
4194 14:44:47.217505 tx_win_center[1][0][7] = 990
4195 14:44:47.220653 tx_first_pass[1][0][7] = 978
4196 14:44:47.220745 tx_last_pass[1][0][7] = 1003
4197 14:44:47.223758 tx_win_center[1][0][8] = 980
4198 14:44:47.227512 tx_first_pass[1][0][8] = 969
4199 14:44:47.230837 tx_last_pass[1][0][8] = 992
4200 14:44:47.234062 tx_win_center[1][0][9] = 980
4201 14:44:47.234154 tx_first_pass[1][0][9] = 969
4202 14:44:47.237573 tx_last_pass[1][0][9] = 991
4203 14:44:47.240796 tx_win_center[1][0][10] = 982
4204 14:44:47.243992 tx_first_pass[1][0][10] = 970
4205 14:44:47.247184 tx_last_pass[1][0][10] = 994
4206 14:44:47.247275 tx_win_center[1][0][11] = 982
4207 14:44:47.250323 tx_first_pass[1][0][11] = 970
4208 14:44:47.253832 tx_last_pass[1][0][11] = 994
4209 14:44:47.257262 tx_win_center[1][0][12] = 982
4210 14:44:47.260190 tx_first_pass[1][0][12] = 970
4211 14:44:47.260281 tx_last_pass[1][0][12] = 994
4212 14:44:47.263743 tx_win_center[1][0][13] = 983
4213 14:44:47.267341 tx_first_pass[1][0][13] = 972
4214 14:44:47.270192 tx_last_pass[1][0][13] = 994
4215 14:44:47.273595 tx_win_center[1][0][14] = 982
4216 14:44:47.273686 tx_first_pass[1][0][14] = 971
4217 14:44:47.277151 tx_last_pass[1][0][14] = 994
4218 14:44:47.280283 tx_win_center[1][0][15] = 977
4219 14:44:47.283610 tx_first_pass[1][0][15] = 966
4220 14:44:47.287015 tx_last_pass[1][0][15] = 988
4221 14:44:47.287106 tx_win_center[1][1][0] = 991
4222 14:44:47.290772 tx_first_pass[1][1][0] = 978
4223 14:44:47.293355 tx_last_pass[1][1][0] = 1005
4224 14:44:47.296779 tx_win_center[1][1][1] = 990
4225 14:44:47.300067 tx_first_pass[1][1][1] = 977
4226 14:44:47.300159 tx_last_pass[1][1][1] = 1003
4227 14:44:47.303683 tx_win_center[1][1][2] = 989
4228 14:44:47.306683 tx_first_pass[1][1][2] = 977
4229 14:44:47.309873 tx_last_pass[1][1][2] = 1001
4230 14:44:47.313478 tx_win_center[1][1][3] = 986
4231 14:44:47.313570 tx_first_pass[1][1][3] = 974
4232 14:44:47.317061 tx_last_pass[1][1][3] = 999
4233 14:44:47.320445 tx_win_center[1][1][4] = 990
4234 14:44:47.323799 tx_first_pass[1][1][4] = 978
4235 14:44:47.323890 tx_last_pass[1][1][4] = 1003
4236 14:44:47.326656 tx_win_center[1][1][5] = 991
4237 14:44:47.329827 tx_first_pass[1][1][5] = 978
4238 14:44:47.333182 tx_last_pass[1][1][5] = 1004
4239 14:44:47.336580 tx_win_center[1][1][6] = 990
4240 14:44:47.336671 tx_first_pass[1][1][6] = 977
4241 14:44:47.339833 tx_last_pass[1][1][6] = 1003
4242 14:44:47.343239 tx_win_center[1][1][7] = 990
4243 14:44:47.346418 tx_first_pass[1][1][7] = 978
4244 14:44:47.349844 tx_last_pass[1][1][7] = 1002
4245 14:44:47.349936 tx_win_center[1][1][8] = 979
4246 14:44:47.353147 tx_first_pass[1][1][8] = 968
4247 14:44:47.356413 tx_last_pass[1][1][8] = 991
4248 14:44:47.360133 tx_win_center[1][1][9] = 978
4249 14:44:47.360224 tx_first_pass[1][1][9] = 967
4250 14:44:47.363015 tx_last_pass[1][1][9] = 990
4251 14:44:47.366376 tx_win_center[1][1][10] = 980
4252 14:44:47.369962 tx_first_pass[1][1][10] = 969
4253 14:44:47.373402 tx_last_pass[1][1][10] = 992
4254 14:44:47.373494 tx_win_center[1][1][11] = 981
4255 14:44:47.376502 tx_first_pass[1][1][11] = 969
4256 14:44:47.380072 tx_last_pass[1][1][11] = 993
4257 14:44:47.383521 tx_win_center[1][1][12] = 981
4258 14:44:47.386287 tx_first_pass[1][1][12] = 970
4259 14:44:47.386380 tx_last_pass[1][1][12] = 993
4260 14:44:47.389884 tx_win_center[1][1][13] = 981
4261 14:44:47.393382 tx_first_pass[1][1][13] = 970
4262 14:44:47.396237 tx_last_pass[1][1][13] = 993
4263 14:44:47.399805 tx_win_center[1][1][14] = 981
4264 14:44:47.399897 tx_first_pass[1][1][14] = 969
4265 14:44:47.403425 tx_last_pass[1][1][14] = 993
4266 14:44:47.406776 tx_win_center[1][1][15] = 975
4267 14:44:47.410164 tx_first_pass[1][1][15] = 964
4268 14:44:47.413039 tx_last_pass[1][1][15] = 987
4269 14:44:47.413130 dump params rx window
4270 14:44:47.416371 rx_firspass[0][0][0] = 5
4271 14:44:47.419886 rx_lastpass[0][0][0] = 38
4272 14:44:47.419986 rx_firspass[0][0][1] = 5
4273 14:44:47.423266 rx_lastpass[0][0][1] = 36
4274 14:44:47.426778 rx_firspass[0][0][2] = 6
4275 14:44:47.426869 rx_lastpass[0][0][2] = 36
4276 14:44:47.429830 rx_firspass[0][0][3] = -2
4277 14:44:47.433388 rx_lastpass[0][0][3] = 31
4278 14:44:47.436476 rx_firspass[0][0][4] = 5
4279 14:44:47.436566 rx_lastpass[0][0][4] = 36
4280 14:44:47.440108 rx_firspass[0][0][5] = 1
4281 14:44:47.443275 rx_lastpass[0][0][5] = 32
4282 14:44:47.443365 rx_firspass[0][0][6] = 3
4283 14:44:47.446644 rx_lastpass[0][0][6] = 34
4284 14:44:47.450012 rx_firspass[0][0][7] = 5
4285 14:44:47.450103 rx_lastpass[0][0][7] = 36
4286 14:44:47.453656 rx_firspass[0][0][8] = -3
4287 14:44:47.456842 rx_lastpass[0][0][8] = 32
4288 14:44:47.456934 rx_firspass[0][0][9] = 1
4289 14:44:47.460064 rx_lastpass[0][0][9] = 32
4290 14:44:47.463176 rx_firspass[0][0][10] = 8
4291 14:44:47.466808 rx_lastpass[0][0][10] = 41
4292 14:44:47.466899 rx_firspass[0][0][11] = 1
4293 14:44:47.470209 rx_lastpass[0][0][11] = 32
4294 14:44:47.473575 rx_firspass[0][0][12] = 2
4295 14:44:47.476439 rx_lastpass[0][0][12] = 36
4296 14:44:47.476533 rx_firspass[0][0][13] = 3
4297 14:44:47.479966 rx_lastpass[0][0][13] = 33
4298 14:44:47.483516 rx_firspass[0][0][14] = 2
4299 14:44:47.483606 rx_lastpass[0][0][14] = 37
4300 14:44:47.486504 rx_firspass[0][0][15] = 5
4301 14:44:47.490048 rx_lastpass[0][0][15] = 37
4302 14:44:47.492947 rx_firspass[0][1][0] = 6
4303 14:44:47.493037 rx_lastpass[0][1][0] = 40
4304 14:44:47.496602 rx_firspass[0][1][1] = 5
4305 14:44:47.499551 rx_lastpass[0][1][1] = 38
4306 14:44:47.499662 rx_firspass[0][1][2] = 6
4307 14:44:47.502950 rx_lastpass[0][1][2] = 38
4308 14:44:47.506620 rx_firspass[0][1][3] = -2
4309 14:44:47.509919 rx_lastpass[0][1][3] = 33
4310 14:44:47.510009 rx_firspass[0][1][4] = 5
4311 14:44:47.513546 rx_lastpass[0][1][4] = 39
4312 14:44:47.516187 rx_firspass[0][1][5] = 1
4313 14:44:47.516277 rx_lastpass[0][1][5] = 34
4314 14:44:47.519942 rx_firspass[0][1][6] = 3
4315 14:44:47.522966 rx_lastpass[0][1][6] = 37
4316 14:44:47.523056 rx_firspass[0][1][7] = 3
4317 14:44:47.526237 rx_lastpass[0][1][7] = 38
4318 14:44:47.529905 rx_firspass[0][1][8] = -2
4319 14:44:47.533232 rx_lastpass[0][1][8] = 32
4320 14:44:47.533323 rx_firspass[0][1][9] = 1
4321 14:44:47.536091 rx_lastpass[0][1][9] = 36
4322 14:44:47.539708 rx_firspass[0][1][10] = 7
4323 14:44:47.539805 rx_lastpass[0][1][10] = 43
4324 14:44:47.542993 rx_firspass[0][1][11] = -2
4325 14:44:47.546285 rx_lastpass[0][1][11] = 34
4326 14:44:47.549289 rx_firspass[0][1][12] = 1
4327 14:44:47.549380 rx_lastpass[0][1][12] = 37
4328 14:44:47.552843 rx_firspass[0][1][13] = 1
4329 14:44:47.555821 rx_lastpass[0][1][13] = 35
4330 14:44:47.559285 rx_firspass[0][1][14] = 3
4331 14:44:47.559375 rx_lastpass[0][1][14] = 37
4332 14:44:47.563062 rx_firspass[0][1][15] = 6
4333 14:44:47.565951 rx_lastpass[0][1][15] = 39
4334 14:44:47.566042 rx_firspass[1][0][0] = 5
4335 14:44:47.569724 rx_lastpass[1][0][0] = 38
4336 14:44:47.572897 rx_firspass[1][0][1] = 5
4337 14:44:47.576089 rx_lastpass[1][0][1] = 38
4338 14:44:47.576202 rx_firspass[1][0][2] = 2
4339 14:44:47.579244 rx_lastpass[1][0][2] = 35
4340 14:44:47.582664 rx_firspass[1][0][3] = 0
4341 14:44:47.582754 rx_lastpass[1][0][3] = 33
4342 14:44:47.586237 rx_firspass[1][0][4] = 5
4343 14:44:47.589152 rx_lastpass[1][0][4] = 38
4344 14:44:47.589243 rx_firspass[1][0][5] = 7
4345 14:44:47.592752 rx_lastpass[1][0][5] = 39
4346 14:44:47.596103 rx_firspass[1][0][6] = 7
4347 14:44:47.599199 rx_lastpass[1][0][6] = 40
4348 14:44:47.599289 rx_firspass[1][0][7] = 5
4349 14:44:47.602511 rx_lastpass[1][0][7] = 38
4350 14:44:47.605847 rx_firspass[1][0][8] = 1
4351 14:44:47.605937 rx_lastpass[1][0][8] = 33
4352 14:44:47.609288 rx_firspass[1][0][9] = 1
4353 14:44:47.612955 rx_lastpass[1][0][9] = 32
4354 14:44:47.613045 rx_firspass[1][0][10] = 5
4355 14:44:47.616082 rx_lastpass[1][0][10] = 35
4356 14:44:47.619069 rx_firspass[1][0][11] = 5
4357 14:44:47.622807 rx_lastpass[1][0][11] = 38
4358 14:44:47.622898 rx_firspass[1][0][12] = 6
4359 14:44:47.626072 rx_lastpass[1][0][12] = 38
4360 14:44:47.628912 rx_firspass[1][0][13] = 6
4361 14:44:47.632895 rx_lastpass[1][0][13] = 37
4362 14:44:47.632985 rx_firspass[1][0][14] = 7
4363 14:44:47.635734 rx_lastpass[1][0][14] = 38
4364 14:44:47.639178 rx_firspass[1][0][15] = -3
4365 14:44:47.642611 rx_lastpass[1][0][15] = 30
4366 14:44:47.642702 rx_firspass[1][1][0] = 4
4367 14:44:47.645953 rx_lastpass[1][1][0] = 40
4368 14:44:47.649070 rx_firspass[1][1][1] = 4
4369 14:44:47.649162 rx_lastpass[1][1][1] = 39
4370 14:44:47.652338 rx_firspass[1][1][2] = 1
4371 14:44:47.655707 rx_lastpass[1][1][2] = 36
4372 14:44:47.655841 rx_firspass[1][1][3] = -2
4373 14:44:47.658956 rx_lastpass[1][1][3] = 34
4374 14:44:47.662156 rx_firspass[1][1][4] = 4
4375 14:44:47.665776 rx_lastpass[1][1][4] = 39
4376 14:44:47.665867 rx_firspass[1][1][5] = 5
4377 14:44:47.669263 rx_lastpass[1][1][5] = 40
4378 14:44:47.672294 rx_firspass[1][1][6] = 5
4379 14:44:47.672385 rx_lastpass[1][1][6] = 41
4380 14:44:47.675839 rx_firspass[1][1][7] = 3
4381 14:44:47.678670 rx_lastpass[1][1][7] = 38
4382 14:44:47.678761 rx_firspass[1][1][8] = 0
4383 14:44:47.682110 rx_lastpass[1][1][8] = 35
4384 14:44:47.685461 rx_firspass[1][1][9] = -2
4385 14:44:47.688597 rx_lastpass[1][1][9] = 34
4386 14:44:47.688688 rx_firspass[1][1][10] = 4
4387 14:44:47.691789 rx_lastpass[1][1][10] = 38
4388 14:44:47.695201 rx_firspass[1][1][11] = 4
4389 14:44:47.698829 rx_lastpass[1][1][11] = 40
4390 14:44:47.698929 rx_firspass[1][1][12] = 4
4391 14:44:47.701838 rx_lastpass[1][1][12] = 40
4392 14:44:47.705205 rx_firspass[1][1][13] = 4
4393 14:44:47.708574 rx_lastpass[1][1][13] = 39
4394 14:44:47.708666 rx_firspass[1][1][14] = 5
4395 14:44:47.712044 rx_lastpass[1][1][14] = 40
4396 14:44:47.715087 rx_firspass[1][1][15] = -3
4397 14:44:47.715214 rx_lastpass[1][1][15] = 31
4398 14:44:47.718550 dump params clk_delay
4399 14:44:47.721874 clk_delay[0] = 1
4400 14:44:47.721994 clk_delay[1] = 0
4401 14:44:47.725720 dump params dqs_delay
4402 14:44:47.725816 dqs_delay[0][0] = -2
4403 14:44:47.728758 dqs_delay[0][1] = 0
4404 14:44:47.728849 dqs_delay[1][0] = 0
4405 14:44:47.732101 dqs_delay[1][1] = 0
4406 14:44:47.735090 dump params delay_cell_unit = 735
4407 14:44:47.735210 dump source = 0x0
4408 14:44:47.738566 dump params frequency:1200
4409 14:44:47.741688 dump params rank number:2
4410 14:44:47.741797
4411 14:44:47.741897 dump params write leveling
4412 14:44:47.745214 write leveling[0][0][0] = 0x0
4413 14:44:47.748605 write leveling[0][0][1] = 0x0
4414 14:44:47.751540 write leveling[0][1][0] = 0x0
4415 14:44:47.755192 write leveling[0][1][1] = 0x0
4416 14:44:47.755312 write leveling[1][0][0] = 0x0
4417 14:44:47.758673 write leveling[1][0][1] = 0x0
4418 14:44:47.761883 write leveling[1][1][0] = 0x0
4419 14:44:47.765181 write leveling[1][1][1] = 0x0
4420 14:44:47.765264 dump params cbt_cs
4421 14:44:47.768121 cbt_cs[0][0] = 0x0
4422 14:44:47.768199 cbt_cs[0][1] = 0x0
4423 14:44:47.771539 cbt_cs[1][0] = 0x0
4424 14:44:47.771620 cbt_cs[1][1] = 0x0
4425 14:44:47.774809 dump params cbt_mr12
4426 14:44:47.778381 cbt_mr12[0][0] = 0x0
4427 14:44:47.778488 cbt_mr12[0][1] = 0x0
4428 14:44:47.781805 cbt_mr12[1][0] = 0x0
4429 14:44:47.781910 cbt_mr12[1][1] = 0x0
4430 14:44:47.784667 dump params tx window
4431 14:44:47.788035 tx_center_min[0][0][0] = 0
4432 14:44:47.788120 tx_center_max[0][0][0] = 0
4433 14:44:47.791464 tx_center_min[0][0][1] = 0
4434 14:44:47.794966 tx_center_max[0][0][1] = 0
4435 14:44:47.798271 tx_center_min[0][1][0] = 0
4436 14:44:47.798381 tx_center_max[0][1][0] = 0
4437 14:44:47.801638 tx_center_min[0][1][1] = 0
4438 14:44:47.804955 tx_center_max[0][1][1] = 0
4439 14:44:47.808416 tx_center_min[1][0][0] = 0
4440 14:44:47.808496 tx_center_max[1][0][0] = 0
4441 14:44:47.811355 tx_center_min[1][0][1] = 0
4442 14:44:47.815036 tx_center_max[1][0][1] = 0
4443 14:44:47.815151 tx_center_min[1][1][0] = 0
4444 14:44:47.818048 tx_center_max[1][1][0] = 0
4445 14:44:47.821651 tx_center_min[1][1][1] = 0
4446 14:44:47.824598 tx_center_max[1][1][1] = 0
4447 14:44:47.824689 dump params tx window
4448 14:44:47.828228 tx_win_center[0][0][0] = 0
4449 14:44:47.831629 tx_first_pass[0][0][0] = 0
4450 14:44:47.834533 tx_last_pass[0][0][0] = 0
4451 14:44:47.834625 tx_win_center[0][0][1] = 0
4452 14:44:47.838208 tx_first_pass[0][0][1] = 0
4453 14:44:47.841415 tx_last_pass[0][0][1] = 0
4454 14:44:47.841506 tx_win_center[0][0][2] = 0
4455 14:44:47.844937 tx_first_pass[0][0][2] = 0
4456 14:44:47.848302 tx_last_pass[0][0][2] = 0
4457 14:44:47.851297 tx_win_center[0][0][3] = 0
4458 14:44:47.851417 tx_first_pass[0][0][3] = 0
4459 14:44:47.854490 tx_last_pass[0][0][3] = 0
4460 14:44:47.857916 tx_win_center[0][0][4] = 0
4461 14:44:47.861578 tx_first_pass[0][0][4] = 0
4462 14:44:47.861669 tx_last_pass[0][0][4] = 0
4463 14:44:47.864349 tx_win_center[0][0][5] = 0
4464 14:44:47.867796 tx_first_pass[0][0][5] = 0
4465 14:44:47.867888 tx_last_pass[0][0][5] = 0
4466 14:44:47.871320 tx_win_center[0][0][6] = 0
4467 14:44:47.874404 tx_first_pass[0][0][6] = 0
4468 14:44:47.877878 tx_last_pass[0][0][6] = 0
4469 14:44:47.877961 tx_win_center[0][0][7] = 0
4470 14:44:47.881513 tx_first_pass[0][0][7] = 0
4471 14:44:47.884663 tx_last_pass[0][0][7] = 0
4472 14:44:47.884744 tx_win_center[0][0][8] = 0
4473 14:44:47.887746 tx_first_pass[0][0][8] = 0
4474 14:44:47.891288 tx_last_pass[0][0][8] = 0
4475 14:44:47.894201 tx_win_center[0][0][9] = 0
4476 14:44:47.894319 tx_first_pass[0][0][9] = 0
4477 14:44:47.898219 tx_last_pass[0][0][9] = 0
4478 14:44:47.901269 tx_win_center[0][0][10] = 0
4479 14:44:47.904384 tx_first_pass[0][0][10] = 0
4480 14:44:47.904463 tx_last_pass[0][0][10] = 0
4481 14:44:47.907842 tx_win_center[0][0][11] = 0
4482 14:44:47.911345 tx_first_pass[0][0][11] = 0
4483 14:44:47.914572 tx_last_pass[0][0][11] = 0
4484 14:44:47.914692 tx_win_center[0][0][12] = 0
4485 14:44:47.917813 tx_first_pass[0][0][12] = 0
4486 14:44:47.921565 tx_last_pass[0][0][12] = 0
4487 14:44:47.924589 tx_win_center[0][0][13] = 0
4488 14:44:47.924681 tx_first_pass[0][0][13] = 0
4489 14:44:47.927895 tx_last_pass[0][0][13] = 0
4490 14:44:47.931241 tx_win_center[0][0][14] = 0
4491 14:44:47.934879 tx_first_pass[0][0][14] = 0
4492 14:44:47.934971 tx_last_pass[0][0][14] = 0
4493 14:44:47.938030 tx_win_center[0][0][15] = 0
4494 14:44:47.941528 tx_first_pass[0][0][15] = 0
4495 14:44:47.944497 tx_last_pass[0][0][15] = 0
4496 14:44:47.944589 tx_win_center[0][1][0] = 0
4497 14:44:47.948249 tx_first_pass[0][1][0] = 0
4498 14:44:47.951550 tx_last_pass[0][1][0] = 0
4499 14:44:47.951669 tx_win_center[0][1][1] = 0
4500 14:44:47.954765 tx_first_pass[0][1][1] = 0
4501 14:44:47.958022 tx_last_pass[0][1][1] = 0
4502 14:44:47.961289 tx_win_center[0][1][2] = 0
4503 14:44:47.961410 tx_first_pass[0][1][2] = 0
4504 14:44:47.965244 tx_last_pass[0][1][2] = 0
4505 14:44:47.968077 tx_win_center[0][1][3] = 0
4506 14:44:47.971522 tx_first_pass[0][1][3] = 0
4507 14:44:47.971614 tx_last_pass[0][1][3] = 0
4508 14:44:47.974437 tx_win_center[0][1][4] = 0
4509 14:44:47.978032 tx_first_pass[0][1][4] = 0
4510 14:44:47.978152 tx_last_pass[0][1][4] = 0
4511 14:44:47.981541 tx_win_center[0][1][5] = 0
4512 14:44:47.984717 tx_first_pass[0][1][5] = 0
4513 14:44:47.988207 tx_last_pass[0][1][5] = 0
4514 14:44:47.988313 tx_win_center[0][1][6] = 0
4515 14:44:47.991163 tx_first_pass[0][1][6] = 0
4516 14:44:47.994680 tx_last_pass[0][1][6] = 0
4517 14:44:47.997621 tx_win_center[0][1][7] = 0
4518 14:44:47.997703 tx_first_pass[0][1][7] = 0
4519 14:44:48.000948 tx_last_pass[0][1][7] = 0
4520 14:44:48.004619 tx_win_center[0][1][8] = 0
4521 14:44:48.004715 tx_first_pass[0][1][8] = 0
4522 14:44:48.007836 tx_last_pass[0][1][8] = 0
4523 14:44:48.010909 tx_win_center[0][1][9] = 0
4524 14:44:48.014477 tx_first_pass[0][1][9] = 0
4525 14:44:48.014560 tx_last_pass[0][1][9] = 0
4526 14:44:48.017891 tx_win_center[0][1][10] = 0
4527 14:44:48.021232 tx_first_pass[0][1][10] = 0
4528 14:44:48.024435 tx_last_pass[0][1][10] = 0
4529 14:44:48.024520 tx_win_center[0][1][11] = 0
4530 14:44:48.027577 tx_first_pass[0][1][11] = 0
4531 14:44:48.031162 tx_last_pass[0][1][11] = 0
4532 14:44:48.034229 tx_win_center[0][1][12] = 0
4533 14:44:48.034309 tx_first_pass[0][1][12] = 0
4534 14:44:48.037763 tx_last_pass[0][1][12] = 0
4535 14:44:48.041165 tx_win_center[0][1][13] = 0
4536 14:44:48.044587 tx_first_pass[0][1][13] = 0
4537 14:44:48.044678 tx_last_pass[0][1][13] = 0
4538 14:44:48.047551 tx_win_center[0][1][14] = 0
4539 14:44:48.050792 tx_first_pass[0][1][14] = 0
4540 14:44:48.053986 tx_last_pass[0][1][14] = 0
4541 14:44:48.054077 tx_win_center[0][1][15] = 0
4542 14:44:48.057718 tx_first_pass[0][1][15] = 0
4543 14:44:48.060682 tx_last_pass[0][1][15] = 0
4544 14:44:48.064327 tx_win_center[1][0][0] = 0
4545 14:44:48.064419 tx_first_pass[1][0][0] = 0
4546 14:44:48.067363 tx_last_pass[1][0][0] = 0
4547 14:44:48.070787 tx_win_center[1][0][1] = 0
4548 14:44:48.074186 tx_first_pass[1][0][1] = 0
4549 14:44:48.074313 tx_last_pass[1][0][1] = 0
4550 14:44:48.077511 tx_win_center[1][0][2] = 0
4551 14:44:48.080828 tx_first_pass[1][0][2] = 0
4552 14:44:48.080914 tx_last_pass[1][0][2] = 0
4553 14:44:48.084160 tx_win_center[1][0][3] = 0
4554 14:44:48.087854 tx_first_pass[1][0][3] = 0
4555 14:44:48.090778 tx_last_pass[1][0][3] = 0
4556 14:44:48.090870 tx_win_center[1][0][4] = 0
4557 14:44:48.094464 tx_first_pass[1][0][4] = 0
4558 14:44:48.097402 tx_last_pass[1][0][4] = 0
4559 14:44:48.097494 tx_win_center[1][0][5] = 0
4560 14:44:48.101026 tx_first_pass[1][0][5] = 0
4561 14:44:48.104143 tx_last_pass[1][0][5] = 0
4562 14:44:48.107490 tx_win_center[1][0][6] = 0
4563 14:44:48.107581 tx_first_pass[1][0][6] = 0
4564 14:44:48.110883 tx_last_pass[1][0][6] = 0
4565 14:44:48.114486 tx_win_center[1][0][7] = 0
4566 14:44:48.117368 tx_first_pass[1][0][7] = 0
4567 14:44:48.117460 tx_last_pass[1][0][7] = 0
4568 14:44:48.120968 tx_win_center[1][0][8] = 0
4569 14:44:48.124234 tx_first_pass[1][0][8] = 0
4570 14:44:48.124332 tx_last_pass[1][0][8] = 0
4571 14:44:48.127679 tx_win_center[1][0][9] = 0
4572 14:44:48.131272 tx_first_pass[1][0][9] = 0
4573 14:44:48.134102 tx_last_pass[1][0][9] = 0
4574 14:44:48.134204 tx_win_center[1][0][10] = 0
4575 14:44:48.137383 tx_first_pass[1][0][10] = 0
4576 14:44:48.140751 tx_last_pass[1][0][10] = 0
4577 14:44:48.144619 tx_win_center[1][0][11] = 0
4578 14:44:48.144706 tx_first_pass[1][0][11] = 0
4579 14:44:48.147684 tx_last_pass[1][0][11] = 0
4580 14:44:48.151010 tx_win_center[1][0][12] = 0
4581 14:44:48.154015 tx_first_pass[1][0][12] = 0
4582 14:44:48.154099 tx_last_pass[1][0][12] = 0
4583 14:44:48.157387 tx_win_center[1][0][13] = 0
4584 14:44:48.160886 tx_first_pass[1][0][13] = 0
4585 14:44:48.164056 tx_last_pass[1][0][13] = 0
4586 14:44:48.164142 tx_win_center[1][0][14] = 0
4587 14:44:48.167528 tx_first_pass[1][0][14] = 0
4588 14:44:48.170964 tx_last_pass[1][0][14] = 0
4589 14:44:48.174206 tx_win_center[1][0][15] = 0
4590 14:44:48.174292 tx_first_pass[1][0][15] = 0
4591 14:44:48.177590 tx_last_pass[1][0][15] = 0
4592 14:44:48.180734 tx_win_center[1][1][0] = 0
4593 14:44:48.184486 tx_first_pass[1][1][0] = 0
4594 14:44:48.184579 tx_last_pass[1][1][0] = 0
4595 14:44:48.187857 tx_win_center[1][1][1] = 0
4596 14:44:48.191131 tx_first_pass[1][1][1] = 0
4597 14:44:48.191216 tx_last_pass[1][1][1] = 0
4598 14:44:48.193952 tx_win_center[1][1][2] = 0
4599 14:44:48.197610 tx_first_pass[1][1][2] = 0
4600 14:44:48.200575 tx_last_pass[1][1][2] = 0
4601 14:44:48.200667 tx_win_center[1][1][3] = 0
4602 14:44:48.203948 tx_first_pass[1][1][3] = 0
4603 14:44:48.207618 tx_last_pass[1][1][3] = 0
4604 14:44:48.210885 tx_win_center[1][1][4] = 0
4605 14:44:48.210976 tx_first_pass[1][1][4] = 0
4606 14:44:48.214124 tx_last_pass[1][1][4] = 0
4607 14:44:48.217515 tx_win_center[1][1][5] = 0
4608 14:44:48.217607 tx_first_pass[1][1][5] = 0
4609 14:44:48.220487 tx_last_pass[1][1][5] = 0
4610 14:44:48.224008 tx_win_center[1][1][6] = 0
4611 14:44:48.227424 tx_first_pass[1][1][6] = 0
4612 14:44:48.227516 tx_last_pass[1][1][6] = 0
4613 14:44:48.230484 tx_win_center[1][1][7] = 0
4614 14:44:48.234016 tx_first_pass[1][1][7] = 0
4615 14:44:48.237060 tx_last_pass[1][1][7] = 0
4616 14:44:48.237152 tx_win_center[1][1][8] = 0
4617 14:44:48.240702 tx_first_pass[1][1][8] = 0
4618 14:44:48.243853 tx_last_pass[1][1][8] = 0
4619 14:44:48.243945 tx_win_center[1][1][9] = 0
4620 14:44:48.247517 tx_first_pass[1][1][9] = 0
4621 14:44:48.250817 tx_last_pass[1][1][9] = 0
4622 14:44:48.254053 tx_win_center[1][1][10] = 0
4623 14:44:48.254144 tx_first_pass[1][1][10] = 0
4624 14:44:48.257179 tx_last_pass[1][1][10] = 0
4625 14:44:48.260890 tx_win_center[1][1][11] = 0
4626 14:44:48.264013 tx_first_pass[1][1][11] = 0
4627 14:44:48.264110 tx_last_pass[1][1][11] = 0
4628 14:44:48.267001 tx_win_center[1][1][12] = 0
4629 14:44:48.270697 tx_first_pass[1][1][12] = 0
4630 14:44:48.273985 tx_last_pass[1][1][12] = 0
4631 14:44:48.274070 tx_win_center[1][1][13] = 0
4632 14:44:48.277114 tx_first_pass[1][1][13] = 0
4633 14:44:48.280645 tx_last_pass[1][1][13] = 0
4634 14:44:48.283691 tx_win_center[1][1][14] = 0
4635 14:44:48.283776 tx_first_pass[1][1][14] = 0
4636 14:44:48.287186 tx_last_pass[1][1][14] = 0
4637 14:44:48.290720 tx_win_center[1][1][15] = 0
4638 14:44:48.294106 tx_first_pass[1][1][15] = 0
4639 14:44:48.294197 tx_last_pass[1][1][15] = 0
4640 14:44:48.297527 dump params rx window
4641 14:44:48.300475 rx_firspass[0][0][0] = 0
4642 14:44:48.300572 rx_lastpass[0][0][0] = 0
4643 14:44:48.303738 rx_firspass[0][0][1] = 0
4644 14:44:48.307119 rx_lastpass[0][0][1] = 0
4645 14:44:48.307226 rx_firspass[0][0][2] = 0
4646 14:44:48.310902 rx_lastpass[0][0][2] = 0
4647 14:44:48.313663 rx_firspass[0][0][3] = 0
4648 14:44:48.317152 rx_lastpass[0][0][3] = 0
4649 14:44:48.317231 rx_firspass[0][0][4] = 0
4650 14:44:48.320557 rx_lastpass[0][0][4] = 0
4651 14:44:48.323867 rx_firspass[0][0][5] = 0
4652 14:44:48.323955 rx_lastpass[0][0][5] = 0
4653 14:44:48.327190 rx_firspass[0][0][6] = 0
4654 14:44:48.330269 rx_lastpass[0][0][6] = 0
4655 14:44:48.330361 rx_firspass[0][0][7] = 0
4656 14:44:48.333964 rx_lastpass[0][0][7] = 0
4657 14:44:48.337069 rx_firspass[0][0][8] = 0
4658 14:44:48.337160 rx_lastpass[0][0][8] = 0
4659 14:44:48.340722 rx_firspass[0][0][9] = 0
4660 14:44:48.343901 rx_lastpass[0][0][9] = 0
4661 14:44:48.343993 rx_firspass[0][0][10] = 0
4662 14:44:48.347068 rx_lastpass[0][0][10] = 0
4663 14:44:48.350772 rx_firspass[0][0][11] = 0
4664 14:44:48.354123 rx_lastpass[0][0][11] = 0
4665 14:44:48.354237 rx_firspass[0][0][12] = 0
4666 14:44:48.357179 rx_lastpass[0][0][12] = 0
4667 14:44:48.360565 rx_firspass[0][0][13] = 0
4668 14:44:48.360647 rx_lastpass[0][0][13] = 0
4669 14:44:48.363895 rx_firspass[0][0][14] = 0
4670 14:44:48.367159 rx_lastpass[0][0][14] = 0
4671 14:44:48.370723 rx_firspass[0][0][15] = 0
4672 14:44:48.370815 rx_lastpass[0][0][15] = 0
4673 14:44:48.373802 rx_firspass[0][1][0] = 0
4674 14:44:48.377226 rx_lastpass[0][1][0] = 0
4675 14:44:48.377320 rx_firspass[0][1][1] = 0
4676 14:44:48.380579 rx_lastpass[0][1][1] = 0
4677 14:44:48.383808 rx_firspass[0][1][2] = 0
4678 14:44:48.383929 rx_lastpass[0][1][2] = 0
4679 14:44:48.387125 rx_firspass[0][1][3] = 0
4680 14:44:48.390782 rx_lastpass[0][1][3] = 0
4681 14:44:48.390894 rx_firspass[0][1][4] = 0
4682 14:44:48.393654 rx_lastpass[0][1][4] = 0
4683 14:44:48.397157 rx_firspass[0][1][5] = 0
4684 14:44:48.400138 rx_lastpass[0][1][5] = 0
4685 14:44:48.400219 rx_firspass[0][1][6] = 0
4686 14:44:48.403484 rx_lastpass[0][1][6] = 0
4687 14:44:48.406960 rx_firspass[0][1][7] = 0
4688 14:44:48.407077 rx_lastpass[0][1][7] = 0
4689 14:44:48.410529 rx_firspass[0][1][8] = 0
4690 14:44:48.413674 rx_lastpass[0][1][8] = 0
4691 14:44:48.413768 rx_firspass[0][1][9] = 0
4692 14:44:48.417132 rx_lastpass[0][1][9] = 0
4693 14:44:48.419876 rx_firspass[0][1][10] = 0
4694 14:44:48.419967 rx_lastpass[0][1][10] = 0
4695 14:44:48.423574 rx_firspass[0][1][11] = 0
4696 14:44:48.426882 rx_lastpass[0][1][11] = 0
4697 14:44:48.430423 rx_firspass[0][1][12] = 0
4698 14:44:48.430547 rx_lastpass[0][1][12] = 0
4699 14:44:48.433189 rx_firspass[0][1][13] = 0
4700 14:44:48.437106 rx_lastpass[0][1][13] = 0
4701 14:44:48.437192 rx_firspass[0][1][14] = 0
4702 14:44:48.439950 rx_lastpass[0][1][14] = 0
4703 14:44:48.443387 rx_firspass[0][1][15] = 0
4704 14:44:48.447003 rx_lastpass[0][1][15] = 0
4705 14:44:48.447118 rx_firspass[1][0][0] = 0
4706 14:44:48.450449 rx_lastpass[1][0][0] = 0
4707 14:44:48.453138 rx_firspass[1][0][1] = 0
4708 14:44:48.453219 rx_lastpass[1][0][1] = 0
4709 14:44:48.456733 rx_firspass[1][0][2] = 0
4710 14:44:48.460249 rx_lastpass[1][0][2] = 0
4711 14:44:48.460336 rx_firspass[1][0][3] = 0
4712 14:44:48.463072 rx_lastpass[1][0][3] = 0
4713 14:44:48.466587 rx_firspass[1][0][4] = 0
4714 14:44:48.466699 rx_lastpass[1][0][4] = 0
4715 14:44:48.469747 rx_firspass[1][0][5] = 0
4716 14:44:48.473154 rx_lastpass[1][0][5] = 0
4717 14:44:48.476350 rx_firspass[1][0][6] = 0
4718 14:44:48.476442 rx_lastpass[1][0][6] = 0
4719 14:44:48.480255 rx_firspass[1][0][7] = 0
4720 14:44:48.483053 rx_lastpass[1][0][7] = 0
4721 14:44:48.483181 rx_firspass[1][0][8] = 0
4722 14:44:48.486356 rx_lastpass[1][0][8] = 0
4723 14:44:48.489824 rx_firspass[1][0][9] = 0
4724 14:44:48.489915 rx_lastpass[1][0][9] = 0
4725 14:44:48.493128 rx_firspass[1][0][10] = 0
4726 14:44:48.496515 rx_lastpass[1][0][10] = 0
4727 14:44:48.496607 rx_firspass[1][0][11] = 0
4728 14:44:48.499793 rx_lastpass[1][0][11] = 0
4729 14:44:48.503328 rx_firspass[1][0][12] = 0
4730 14:44:48.506342 rx_lastpass[1][0][12] = 0
4731 14:44:48.506432 rx_firspass[1][0][13] = 0
4732 14:44:48.509615 rx_lastpass[1][0][13] = 0
4733 14:44:48.512956 rx_firspass[1][0][14] = 0
4734 14:44:48.513047 rx_lastpass[1][0][14] = 0
4735 14:44:48.516426 rx_firspass[1][0][15] = 0
4736 14:44:48.519641 rx_lastpass[1][0][15] = 0
4737 14:44:48.523229 rx_firspass[1][1][0] = 0
4738 14:44:48.523320 rx_lastpass[1][1][0] = 0
4739 14:44:48.526592 rx_firspass[1][1][1] = 0
4740 14:44:48.530233 rx_lastpass[1][1][1] = 0
4741 14:44:48.530323 rx_firspass[1][1][2] = 0
4742 14:44:48.533571 rx_lastpass[1][1][2] = 0
4743 14:44:48.536276 rx_firspass[1][1][3] = 0
4744 14:44:48.536367 rx_lastpass[1][1][3] = 0
4745 14:44:48.539903 rx_firspass[1][1][4] = 0
4746 14:44:48.543345 rx_lastpass[1][1][4] = 0
4747 14:44:48.543445 rx_firspass[1][1][5] = 0
4748 14:44:48.546226 rx_lastpass[1][1][5] = 0
4749 14:44:48.549772 rx_firspass[1][1][6] = 0
4750 14:44:48.552684 rx_lastpass[1][1][6] = 0
4751 14:44:48.552775 rx_firspass[1][1][7] = 0
4752 14:44:48.556164 rx_lastpass[1][1][7] = 0
4753 14:44:48.559616 rx_firspass[1][1][8] = 0
4754 14:44:48.559708 rx_lastpass[1][1][8] = 0
4755 14:44:48.563243 rx_firspass[1][1][9] = 0
4756 14:44:48.566635 rx_lastpass[1][1][9] = 0
4757 14:44:48.566729 rx_firspass[1][1][10] = 0
4758 14:44:48.569363 rx_lastpass[1][1][10] = 0
4759 14:44:48.572918 rx_firspass[1][1][11] = 0
4760 14:44:48.576168 rx_lastpass[1][1][11] = 0
4761 14:44:48.576260 rx_firspass[1][1][12] = 0
4762 14:44:48.579640 rx_lastpass[1][1][12] = 0
4763 14:44:48.582567 rx_firspass[1][1][13] = 0
4764 14:44:48.582662 rx_lastpass[1][1][13] = 0
4765 14:44:48.585947 rx_firspass[1][1][14] = 0
4766 14:44:48.589430 rx_lastpass[1][1][14] = 0
4767 14:44:48.593114 rx_firspass[1][1][15] = 0
4768 14:44:48.593207 rx_lastpass[1][1][15] = 0
4769 14:44:48.596499 dump params clk_delay
4770 14:44:48.596590 clk_delay[0] = 0
4771 14:44:48.599235 clk_delay[1] = 0
4772 14:44:48.599327 dump params dqs_delay
4773 14:44:48.602658 dqs_delay[0][0] = 0
4774 14:44:48.602756 dqs_delay[0][1] = 0
4775 14:44:48.606413 dqs_delay[1][0] = 0
4776 14:44:48.609408 dqs_delay[1][1] = 0
4777 14:44:48.609501 dump params delay_cell_unit = 735
4778 14:44:48.612510 dump source = 0x0
4779 14:44:48.616239 dump params frequency:800
4780 14:44:48.616331 dump params rank number:2
4781 14:44:48.616405
4782 14:44:48.619732 dump params write leveling
4783 14:44:48.622493 write leveling[0][0][0] = 0x0
4784 14:44:48.626076 write leveling[0][0][1] = 0x0
4785 14:44:48.629634 write leveling[0][1][0] = 0x0
4786 14:44:48.629720 write leveling[0][1][1] = 0x0
4787 14:44:48.632500 write leveling[1][0][0] = 0x0
4788 14:44:48.636044 write leveling[1][0][1] = 0x0
4789 14:44:48.639553 write leveling[1][1][0] = 0x0
4790 14:44:48.642831 write leveling[1][1][1] = 0x0
4791 14:44:48.642917 dump params cbt_cs
4792 14:44:48.645984 cbt_cs[0][0] = 0x0
4793 14:44:48.646076 cbt_cs[0][1] = 0x0
4794 14:44:48.649245 cbt_cs[1][0] = 0x0
4795 14:44:48.649337 cbt_cs[1][1] = 0x0
4796 14:44:48.652714 dump params cbt_mr12
4797 14:44:48.652805 cbt_mr12[0][0] = 0x0
4798 14:44:48.655728 cbt_mr12[0][1] = 0x0
4799 14:44:48.655819 cbt_mr12[1][0] = 0x0
4800 14:44:48.659215 cbt_mr12[1][1] = 0x0
4801 14:44:48.662855 dump params tx window
4802 14:44:48.662945 tx_center_min[0][0][0] = 0
4803 14:44:48.665860 tx_center_max[0][0][0] = 0
4804 14:44:48.669242 tx_center_min[0][0][1] = 0
4805 14:44:48.672790 tx_center_max[0][0][1] = 0
4806 14:44:48.672880 tx_center_min[0][1][0] = 0
4807 14:44:48.675686 tx_center_max[0][1][0] = 0
4808 14:44:48.679166 tx_center_min[0][1][1] = 0
4809 14:44:48.682525 tx_center_max[0][1][1] = 0
4810 14:44:48.682639 tx_center_min[1][0][0] = 0
4811 14:44:48.685940 tx_center_max[1][0][0] = 0
4812 14:44:48.689513 tx_center_min[1][0][1] = 0
4813 14:44:48.689638 tx_center_max[1][0][1] = 0
4814 14:44:48.692537 tx_center_min[1][1][0] = 0
4815 14:44:48.695948 tx_center_max[1][1][0] = 0
4816 14:44:48.699305 tx_center_min[1][1][1] = 0
4817 14:44:48.699389 tx_center_max[1][1][1] = 0
4818 14:44:48.702221 dump params tx window
4819 14:44:48.705667 tx_win_center[0][0][0] = 0
4820 14:44:48.708783 tx_first_pass[0][0][0] = 0
4821 14:44:48.708876 tx_last_pass[0][0][0] = 0
4822 14:44:48.712188 tx_win_center[0][0][1] = 0
4823 14:44:48.715562 tx_first_pass[0][0][1] = 0
4824 14:44:48.715672 tx_last_pass[0][0][1] = 0
4825 14:44:48.719358 tx_win_center[0][0][2] = 0
4826 14:44:48.722166 tx_first_pass[0][0][2] = 0
4827 14:44:48.725531 tx_last_pass[0][0][2] = 0
4828 14:44:48.725624 tx_win_center[0][0][3] = 0
4829 14:44:48.729044 tx_first_pass[0][0][3] = 0
4830 14:44:48.732494 tx_last_pass[0][0][3] = 0
4831 14:44:48.732586 tx_win_center[0][0][4] = 0
4832 14:44:48.736042 tx_first_pass[0][0][4] = 0
4833 14:44:48.739314 tx_last_pass[0][0][4] = 0
4834 14:44:48.742558 tx_win_center[0][0][5] = 0
4835 14:44:48.742651 tx_first_pass[0][0][5] = 0
4836 14:44:48.745595 tx_last_pass[0][0][5] = 0
4837 14:44:48.748618 tx_win_center[0][0][6] = 0
4838 14:44:48.752024 tx_first_pass[0][0][6] = 0
4839 14:44:48.752117 tx_last_pass[0][0][6] = 0
4840 14:44:48.755751 tx_win_center[0][0][7] = 0
4841 14:44:48.759027 tx_first_pass[0][0][7] = 0
4842 14:44:48.759117 tx_last_pass[0][0][7] = 0
4843 14:44:48.762145 tx_win_center[0][0][8] = 0
4844 14:44:48.765817 tx_first_pass[0][0][8] = 0
4845 14:44:48.768816 tx_last_pass[0][0][8] = 0
4846 14:44:48.768942 tx_win_center[0][0][9] = 0
4847 14:44:48.771892 tx_first_pass[0][0][9] = 0
4848 14:44:48.775237 tx_last_pass[0][0][9] = 0
4849 14:44:48.778727 tx_win_center[0][0][10] = 0
4850 14:44:48.778850 tx_first_pass[0][0][10] = 0
4851 14:44:48.782056 tx_last_pass[0][0][10] = 0
4852 14:44:48.785552 tx_win_center[0][0][11] = 0
4853 14:44:48.788429 tx_first_pass[0][0][11] = 0
4854 14:44:48.788523 tx_last_pass[0][0][11] = 0
4855 14:44:48.791717 tx_win_center[0][0][12] = 0
4856 14:44:48.795398 tx_first_pass[0][0][12] = 0
4857 14:44:48.798764 tx_last_pass[0][0][12] = 0
4858 14:44:48.798855 tx_win_center[0][0][13] = 0
4859 14:44:48.801778 tx_first_pass[0][0][13] = 0
4860 14:44:48.805333 tx_last_pass[0][0][13] = 0
4861 14:44:48.808710 tx_win_center[0][0][14] = 0
4862 14:44:48.808796 tx_first_pass[0][0][14] = 0
4863 14:44:48.812135 tx_last_pass[0][0][14] = 0
4864 14:44:48.815546 tx_win_center[0][0][15] = 0
4865 14:44:48.818559 tx_first_pass[0][0][15] = 0
4866 14:44:48.818645 tx_last_pass[0][0][15] = 0
4867 14:44:48.822134 tx_win_center[0][1][0] = 0
4868 14:44:48.825516 tx_first_pass[0][1][0] = 0
4869 14:44:48.828746 tx_last_pass[0][1][0] = 0
4870 14:44:48.828831 tx_win_center[0][1][1] = 0
4871 14:44:48.832281 tx_first_pass[0][1][1] = 0
4872 14:44:48.835189 tx_last_pass[0][1][1] = 0
4873 14:44:48.835272 tx_win_center[0][1][2] = 0
4874 14:44:48.838727 tx_first_pass[0][1][2] = 0
4875 14:44:48.842242 tx_last_pass[0][1][2] = 0
4876 14:44:48.845695 tx_win_center[0][1][3] = 0
4877 14:44:48.845786 tx_first_pass[0][1][3] = 0
4878 14:44:48.848531 tx_last_pass[0][1][3] = 0
4879 14:44:48.852007 tx_win_center[0][1][4] = 0
4880 14:44:48.855680 tx_first_pass[0][1][4] = 0
4881 14:44:48.855772 tx_last_pass[0][1][4] = 0
4882 14:44:48.858595 tx_win_center[0][1][5] = 0
4883 14:44:48.862121 tx_first_pass[0][1][5] = 0
4884 14:44:48.862213 tx_last_pass[0][1][5] = 0
4885 14:44:48.865132 tx_win_center[0][1][6] = 0
4886 14:44:48.868775 tx_first_pass[0][1][6] = 0
4887 14:44:48.871980 tx_last_pass[0][1][6] = 0
4888 14:44:48.872071 tx_win_center[0][1][7] = 0
4889 14:44:48.875357 tx_first_pass[0][1][7] = 0
4890 14:44:48.878803 tx_last_pass[0][1][7] = 0
4891 14:44:48.878895 tx_win_center[0][1][8] = 0
4892 14:44:48.882217 tx_first_pass[0][1][8] = 0
4893 14:44:48.885698 tx_last_pass[0][1][8] = 0
4894 14:44:48.888547 tx_win_center[0][1][9] = 0
4895 14:44:48.888638 tx_first_pass[0][1][9] = 0
4896 14:44:48.891862 tx_last_pass[0][1][9] = 0
4897 14:44:48.895277 tx_win_center[0][1][10] = 0
4898 14:44:48.898782 tx_first_pass[0][1][10] = 0
4899 14:44:48.898874 tx_last_pass[0][1][10] = 0
4900 14:44:48.902457 tx_win_center[0][1][11] = 0
4901 14:44:48.905809 tx_first_pass[0][1][11] = 0
4902 14:44:48.908532 tx_last_pass[0][1][11] = 0
4903 14:44:48.908629 tx_win_center[0][1][12] = 0
4904 14:44:48.911946 tx_first_pass[0][1][12] = 0
4905 14:44:48.915586 tx_last_pass[0][1][12] = 0
4906 14:44:48.918786 tx_win_center[0][1][13] = 0
4907 14:44:48.918878 tx_first_pass[0][1][13] = 0
4908 14:44:48.922040 tx_last_pass[0][1][13] = 0
4909 14:44:48.925536 tx_win_center[0][1][14] = 0
4910 14:44:48.928895 tx_first_pass[0][1][14] = 0
4911 14:44:48.929016 tx_last_pass[0][1][14] = 0
4912 14:44:48.932055 tx_win_center[0][1][15] = 0
4913 14:44:48.935272 tx_first_pass[0][1][15] = 0
4914 14:44:48.938773 tx_last_pass[0][1][15] = 0
4915 14:44:48.938854 tx_win_center[1][0][0] = 0
4916 14:44:48.942154 tx_first_pass[1][0][0] = 0
4917 14:44:48.945485 tx_last_pass[1][0][0] = 0
4918 14:44:48.945606 tx_win_center[1][0][1] = 0
4919 14:44:48.948804 tx_first_pass[1][0][1] = 0
4920 14:44:48.952016 tx_last_pass[1][0][1] = 0
4921 14:44:48.955173 tx_win_center[1][0][2] = 0
4922 14:44:48.955265 tx_first_pass[1][0][2] = 0
4923 14:44:48.958839 tx_last_pass[1][0][2] = 0
4924 14:44:48.961987 tx_win_center[1][0][3] = 0
4925 14:44:48.965079 tx_first_pass[1][0][3] = 0
4926 14:44:48.965180 tx_last_pass[1][0][3] = 0
4927 14:44:48.968665 tx_win_center[1][0][4] = 0
4928 14:44:48.971950 tx_first_pass[1][0][4] = 0
4929 14:44:48.972071 tx_last_pass[1][0][4] = 0
4930 14:44:48.975371 tx_win_center[1][0][5] = 0
4931 14:44:48.978342 tx_first_pass[1][0][5] = 0
4932 14:44:48.981929 tx_last_pass[1][0][5] = 0
4933 14:44:48.982021 tx_win_center[1][0][6] = 0
4934 14:44:48.985424 tx_first_pass[1][0][6] = 0
4935 14:44:48.988925 tx_last_pass[1][0][6] = 0
4936 14:44:48.992497 tx_win_center[1][0][7] = 0
4937 14:44:48.992589 tx_first_pass[1][0][7] = 0
4938 14:44:48.995102 tx_last_pass[1][0][7] = 0
4939 14:44:48.998554 tx_win_center[1][0][8] = 0
4940 14:44:48.998645 tx_first_pass[1][0][8] = 0
4941 14:44:49.001953 tx_last_pass[1][0][8] = 0
4942 14:44:49.004988 tx_win_center[1][0][9] = 0
4943 14:44:49.008640 tx_first_pass[1][0][9] = 0
4944 14:44:49.008730 tx_last_pass[1][0][9] = 0
4945 14:44:49.011995 tx_win_center[1][0][10] = 0
4946 14:44:49.014984 tx_first_pass[1][0][10] = 0
4947 14:44:49.018493 tx_last_pass[1][0][10] = 0
4948 14:44:49.018584 tx_win_center[1][0][11] = 0
4949 14:44:49.021548 tx_first_pass[1][0][11] = 0
4950 14:44:49.024985 tx_last_pass[1][0][11] = 0
4951 14:44:49.028515 tx_win_center[1][0][12] = 0
4952 14:44:49.028608 tx_first_pass[1][0][12] = 0
4953 14:44:49.032048 tx_last_pass[1][0][12] = 0
4954 14:44:49.035104 tx_win_center[1][0][13] = 0
4955 14:44:49.038448 tx_first_pass[1][0][13] = 0
4956 14:44:49.038540 tx_last_pass[1][0][13] = 0
4957 14:44:49.042244 tx_win_center[1][0][14] = 0
4958 14:44:49.044929 tx_first_pass[1][0][14] = 0
4959 14:44:49.048288 tx_last_pass[1][0][14] = 0
4960 14:44:49.048379 tx_win_center[1][0][15] = 0
4961 14:44:49.051896 tx_first_pass[1][0][15] = 0
4962 14:44:49.054925 tx_last_pass[1][0][15] = 0
4963 14:44:49.058133 tx_win_center[1][1][0] = 0
4964 14:44:49.058225 tx_first_pass[1][1][0] = 0
4965 14:44:49.061488 tx_last_pass[1][1][0] = 0
4966 14:44:49.064796 tx_win_center[1][1][1] = 0
4967 14:44:49.068003 tx_first_pass[1][1][1] = 0
4968 14:44:49.068094 tx_last_pass[1][1][1] = 0
4969 14:44:49.071546 tx_win_center[1][1][2] = 0
4970 14:44:49.074857 tx_first_pass[1][1][2] = 0
4971 14:44:49.074949 tx_last_pass[1][1][2] = 0
4972 14:44:49.078233 tx_win_center[1][1][3] = 0
4973 14:44:49.081703 tx_first_pass[1][1][3] = 0
4974 14:44:49.084646 tx_last_pass[1][1][3] = 0
4975 14:44:49.084737 tx_win_center[1][1][4] = 0
4976 14:44:49.088333 tx_first_pass[1][1][4] = 0
4977 14:44:49.091885 tx_last_pass[1][1][4] = 0
4978 14:44:49.091977 tx_win_center[1][1][5] = 0
4979 14:44:49.095210 tx_first_pass[1][1][5] = 0
4980 14:44:49.098090 tx_last_pass[1][1][5] = 0
4981 14:44:49.101454 tx_win_center[1][1][6] = 0
4982 14:44:49.101546 tx_first_pass[1][1][6] = 0
4983 14:44:49.104606 tx_last_pass[1][1][6] = 0
4984 14:44:49.108107 tx_win_center[1][1][7] = 0
4985 14:44:49.111459 tx_first_pass[1][1][7] = 0
4986 14:44:49.111551 tx_last_pass[1][1][7] = 0
4987 14:44:49.114934 tx_win_center[1][1][8] = 0
4988 14:44:49.117770 tx_first_pass[1][1][8] = 0
4989 14:44:49.121406 tx_last_pass[1][1][8] = 0
4990 14:44:49.121498 tx_win_center[1][1][9] = 0
4991 14:44:49.124908 tx_first_pass[1][1][9] = 0
4992 14:44:49.127740 tx_last_pass[1][1][9] = 0
4993 14:44:49.127832 tx_win_center[1][1][10] = 0
4994 14:44:49.131299 tx_first_pass[1][1][10] = 0
4995 14:44:49.134428 tx_last_pass[1][1][10] = 0
4996 14:44:49.138018 tx_win_center[1][1][11] = 0
4997 14:44:49.138110 tx_first_pass[1][1][11] = 0
4998 14:44:49.141463 tx_last_pass[1][1][11] = 0
4999 14:44:49.144338 tx_win_center[1][1][12] = 0
5000 14:44:49.147984 tx_first_pass[1][1][12] = 0
5001 14:44:49.148075 tx_last_pass[1][1][12] = 0
5002 14:44:49.151469 tx_win_center[1][1][13] = 0
5003 14:44:49.154928 tx_first_pass[1][1][13] = 0
5004 14:44:49.157619 tx_last_pass[1][1][13] = 0
5005 14:44:49.157711 tx_win_center[1][1][14] = 0
5006 14:44:49.160825 tx_first_pass[1][1][14] = 0
5007 14:44:49.164639 tx_last_pass[1][1][14] = 0
5008 14:44:49.167835 tx_win_center[1][1][15] = 0
5009 14:44:49.171308 tx_first_pass[1][1][15] = 0
5010 14:44:49.171434 tx_last_pass[1][1][15] = 0
5011 14:44:49.174561 dump params rx window
5012 14:44:49.177844 rx_firspass[0][0][0] = 0
5013 14:44:49.177936 rx_lastpass[0][0][0] = 0
5014 14:44:49.181266 rx_firspass[0][0][1] = 0
5015 14:44:49.184206 rx_lastpass[0][0][1] = 0
5016 14:44:49.184297 rx_firspass[0][0][2] = 0
5017 14:44:49.188105 rx_lastpass[0][0][2] = 0
5018 14:44:49.191004 rx_firspass[0][0][3] = 0
5019 14:44:49.191125 rx_lastpass[0][0][3] = 0
5020 14:44:49.194191 rx_firspass[0][0][4] = 0
5021 14:44:49.197482 rx_lastpass[0][0][4] = 0
5022 14:44:49.197602 rx_firspass[0][0][5] = 0
5023 14:44:49.200981 rx_lastpass[0][0][5] = 0
5024 14:44:49.204387 rx_firspass[0][0][6] = 0
5025 14:44:49.204478 rx_lastpass[0][0][6] = 0
5026 14:44:49.207658 rx_firspass[0][0][7] = 0
5027 14:44:49.211124 rx_lastpass[0][0][7] = 0
5028 14:44:49.211240 rx_firspass[0][0][8] = 0
5029 14:44:49.214504 rx_lastpass[0][0][8] = 0
5030 14:44:49.217807 rx_firspass[0][0][9] = 0
5031 14:44:49.221310 rx_lastpass[0][0][9] = 0
5032 14:44:49.221443 rx_firspass[0][0][10] = 0
5033 14:44:49.224325 rx_lastpass[0][0][10] = 0
5034 14:44:49.228098 rx_firspass[0][0][11] = 0
5035 14:44:49.228189 rx_lastpass[0][0][11] = 0
5036 14:44:49.231281 rx_firspass[0][0][12] = 0
5037 14:44:49.233992 rx_lastpass[0][0][12] = 0
5038 14:44:49.237596 rx_firspass[0][0][13] = 0
5039 14:44:49.237686 rx_lastpass[0][0][13] = 0
5040 14:44:49.241167 rx_firspass[0][0][14] = 0
5041 14:44:49.244729 rx_lastpass[0][0][14] = 0
5042 14:44:49.244820 rx_firspass[0][0][15] = 0
5043 14:44:49.247439 rx_lastpass[0][0][15] = 0
5044 14:44:49.251081 rx_firspass[0][1][0] = 0
5045 14:44:49.251202 rx_lastpass[0][1][0] = 0
5046 14:44:49.254673 rx_firspass[0][1][1] = 0
5047 14:44:49.257730 rx_lastpass[0][1][1] = 0
5048 14:44:49.260905 rx_firspass[0][1][2] = 0
5049 14:44:49.261026 rx_lastpass[0][1][2] = 0
5050 14:44:49.263943 rx_firspass[0][1][3] = 0
5051 14:44:49.267360 rx_lastpass[0][1][3] = 0
5052 14:44:49.267472 rx_firspass[0][1][4] = 0
5053 14:44:49.271128 rx_lastpass[0][1][4] = 0
5054 14:44:49.274244 rx_firspass[0][1][5] = 0
5055 14:44:49.274365 rx_lastpass[0][1][5] = 0
5056 14:44:49.277171 rx_firspass[0][1][6] = 0
5057 14:44:49.280836 rx_lastpass[0][1][6] = 0
5058 14:44:49.280958 rx_firspass[0][1][7] = 0
5059 14:44:49.284291 rx_lastpass[0][1][7] = 0
5060 14:44:49.287412 rx_firspass[0][1][8] = 0
5061 14:44:49.290414 rx_lastpass[0][1][8] = 0
5062 14:44:49.290547 rx_firspass[0][1][9] = 0
5063 14:44:49.293866 rx_lastpass[0][1][9] = 0
5064 14:44:49.297400 rx_firspass[0][1][10] = 0
5065 14:44:49.297482 rx_lastpass[0][1][10] = 0
5066 14:44:49.300633 rx_firspass[0][1][11] = 0
5067 14:44:49.304510 rx_lastpass[0][1][11] = 0
5068 14:44:49.304600 rx_firspass[0][1][12] = 0
5069 14:44:49.307447 rx_lastpass[0][1][12] = 0
5070 14:44:49.310683 rx_firspass[0][1][13] = 0
5071 14:44:49.314164 rx_lastpass[0][1][13] = 0
5072 14:44:49.314275 rx_firspass[0][1][14] = 0
5073 14:44:49.317417 rx_lastpass[0][1][14] = 0
5074 14:44:49.320637 rx_firspass[0][1][15] = 0
5075 14:44:49.320731 rx_lastpass[0][1][15] = 0
5076 14:44:49.324018 rx_firspass[1][0][0] = 0
5077 14:44:49.327287 rx_lastpass[1][0][0] = 0
5078 14:44:49.327452 rx_firspass[1][0][1] = 0
5079 14:44:49.330858 rx_lastpass[1][0][1] = 0
5080 14:44:49.333953 rx_firspass[1][0][2] = 0
5081 14:44:49.337390 rx_lastpass[1][0][2] = 0
5082 14:44:49.337489 rx_firspass[1][0][3] = 0
5083 14:44:49.340890 rx_lastpass[1][0][3] = 0
5084 14:44:49.344114 rx_firspass[1][0][4] = 0
5085 14:44:49.344239 rx_lastpass[1][0][4] = 0
5086 14:44:49.347365 rx_firspass[1][0][5] = 0
5087 14:44:49.350984 rx_lastpass[1][0][5] = 0
5088 14:44:49.351121 rx_firspass[1][0][6] = 0
5089 14:44:49.354122 rx_lastpass[1][0][6] = 0
5090 14:44:49.357534 rx_firspass[1][0][7] = 0
5091 14:44:49.357632 rx_lastpass[1][0][7] = 0
5092 14:44:49.360448 rx_firspass[1][0][8] = 0
5093 14:44:49.364056 rx_lastpass[1][0][8] = 0
5094 14:44:49.364154 rx_firspass[1][0][9] = 0
5095 14:44:49.367315 rx_lastpass[1][0][9] = 0
5096 14:44:49.370694 rx_firspass[1][0][10] = 0
5097 14:44:49.373829 rx_lastpass[1][0][10] = 0
5098 14:44:49.373928 rx_firspass[1][0][11] = 0
5099 14:44:49.377037 rx_lastpass[1][0][11] = 0
5100 14:44:49.380666 rx_firspass[1][0][12] = 0
5101 14:44:49.380757 rx_lastpass[1][0][12] = 0
5102 14:44:49.383964 rx_firspass[1][0][13] = 0
5103 14:44:49.387375 rx_lastpass[1][0][13] = 0
5104 14:44:49.390397 rx_firspass[1][0][14] = 0
5105 14:44:49.390492 rx_lastpass[1][0][14] = 0
5106 14:44:49.393747 rx_firspass[1][0][15] = 0
5107 14:44:49.397294 rx_lastpass[1][0][15] = 0
5108 14:44:49.397385 rx_firspass[1][1][0] = 0
5109 14:44:49.400326 rx_lastpass[1][1][0] = 0
5110 14:44:49.403639 rx_firspass[1][1][1] = 0
5111 14:44:49.403730 rx_lastpass[1][1][1] = 0
5112 14:44:49.407250 rx_firspass[1][1][2] = 0
5113 14:44:49.410729 rx_lastpass[1][1][2] = 0
5114 14:44:49.414036 rx_firspass[1][1][3] = 0
5115 14:44:49.414139 rx_lastpass[1][1][3] = 0
5116 14:44:49.416980 rx_firspass[1][1][4] = 0
5117 14:44:49.420441 rx_lastpass[1][1][4] = 0
5118 14:44:49.420532 rx_firspass[1][1][5] = 0
5119 14:44:49.424117 rx_lastpass[1][1][5] = 0
5120 14:44:49.426970 rx_firspass[1][1][6] = 0
5121 14:44:49.427061 rx_lastpass[1][1][6] = 0
5122 14:44:49.430495 rx_firspass[1][1][7] = 0
5123 14:44:49.433888 rx_lastpass[1][1][7] = 0
5124 14:44:49.433979 rx_firspass[1][1][8] = 0
5125 14:44:49.437338 rx_lastpass[1][1][8] = 0
5126 14:44:49.440393 rx_firspass[1][1][9] = 0
5127 14:44:49.440484 rx_lastpass[1][1][9] = 0
5128 14:44:49.443530 rx_firspass[1][1][10] = 0
5129 14:44:49.446983 rx_lastpass[1][1][10] = 0
5130 14:44:49.449961 rx_firspass[1][1][11] = 0
5131 14:44:49.450056 rx_lastpass[1][1][11] = 0
5132 14:44:49.453547 rx_firspass[1][1][12] = 0
5133 14:44:49.456759 rx_lastpass[1][1][12] = 0
5134 14:44:49.456850 rx_firspass[1][1][13] = 0
5135 14:44:49.460129 rx_lastpass[1][1][13] = 0
5136 14:44:49.463725 rx_firspass[1][1][14] = 0
5137 14:44:49.466684 rx_lastpass[1][1][14] = 0
5138 14:44:49.466774 rx_firspass[1][1][15] = 0
5139 14:44:49.470118 rx_lastpass[1][1][15] = 0
5140 14:44:49.473211 dump params clk_delay
5141 14:44:49.473326 clk_delay[0] = 0
5142 14:44:49.476631 clk_delay[1] = 0
5143 14:44:49.476751 dump params dqs_delay
5144 14:44:49.480280 dqs_delay[0][0] = 0
5145 14:44:49.480370 dqs_delay[0][1] = 0
5146 14:44:49.483474 dqs_delay[1][0] = 0
5147 14:44:49.483566 dqs_delay[1][1] = 0
5148 14:44:49.486927 dump params delay_cell_unit = 735
5149 14:44:49.489861 mt_set_emi_preloader end
5150 14:44:49.493325 [mt_mem_init] dram size: 0x100000000, rank number: 2
5151 14:44:49.499868 [complex_mem_test] start addr:0x40000000, len:20480
5152 14:44:49.536039 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
5153 14:44:49.542350 [complex_mem_test] start addr:0x80000000, len:20480
5154 14:44:49.578405 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
5155 14:44:49.585085 [complex_mem_test] start addr:0xc0000000, len:20480
5156 14:44:49.620525 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
5157 14:44:49.627020 [complex_mem_test] start addr:0x56000000, len:8192
5158 14:44:49.644007 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
5159 14:44:49.644100 ddr_geometry:1
5160 14:44:49.650158 [complex_mem_test] start addr:0x80000000, len:8192
5161 14:44:49.667168 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
5162 14:44:49.670700 dram_init: dram init end (result: 0)
5163 14:44:49.677320 Successfully loaded DRAM blobs and ran DRAM calibration
5164 14:44:49.687481 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
5165 14:44:49.687603 CBMEM:
5166 14:44:49.690502 IMD: root @ 00000000fffff000 254 entries.
5167 14:44:49.694329 IMD: root @ 00000000ffffec00 62 entries.
5168 14:44:49.700719 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
5169 14:44:49.707114 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
5170 14:44:49.710488 in-header: 03 a1 00 00 08 00 00 00
5171 14:44:49.714153 in-data: 84 60 60 10 00 00 00 00
5172 14:44:49.717261 Chrome EC: clear events_b mask to 0x0000000020004000
5173 14:44:49.724963 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
5174 14:44:49.728561 in-header: 03 fd 00 00 00 00 00 00
5175 14:44:49.728652 in-data:
5176 14:44:49.734768 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5177 14:44:49.734901 CBFS @ 21000 size 3d4000
5178 14:44:49.741134 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5179 14:44:49.744691 CBFS: Locating 'fallback/ramstage'
5180 14:44:49.747598 CBFS: Found @ offset 10d40 size d563
5181 14:44:49.769116 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
5182 14:44:49.781410 Accumulated console time in romstage 13606 ms
5183 14:44:49.781520
5184 14:44:49.781604
5185 14:44:49.791375 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
5186 14:44:49.794508 ARM64: Exception handlers installed.
5187 14:44:49.794601 ARM64: Testing exception
5188 14:44:49.797753 ARM64: Done test exception
5189 14:44:49.801473 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
5190 14:44:49.804376 Manufacturer: ef
5191 14:44:49.807979 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
5192 14:44:49.814614 WARNING: RO_VPD is uninitialized or empty.
5193 14:44:49.817605 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5194 14:44:49.820974 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5195 14:44:49.831032 read SPI 0x550600 0x3a00: 4532 us, 3276 KB/s, 26.208 Mbps
5196 14:44:49.834514 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5197 14:44:49.840874 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5198 14:44:49.840968 Enumerating buses...
5199 14:44:49.847694 Show all devs... Before device enumeration.
5200 14:44:49.847787 Root Device: enabled 1
5201 14:44:49.850945 CPU_CLUSTER: 0: enabled 1
5202 14:44:49.851066 CPU: 00: enabled 1
5203 14:44:49.854635 Compare with tree...
5204 14:44:49.857723 Root Device: enabled 1
5205 14:44:49.857815 CPU_CLUSTER: 0: enabled 1
5206 14:44:49.861378 CPU: 00: enabled 1
5207 14:44:49.864855 Root Device scanning...
5208 14:44:49.864947 root_dev_scan_bus for Root Device
5209 14:44:49.867737 CPU_CLUSTER: 0 enabled
5210 14:44:49.871380 root_dev_scan_bus for Root Device done
5211 14:44:49.877834 scan_bus: scanning of bus Root Device took 10689 usecs
5212 14:44:49.877926 done
5213 14:44:49.880816 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5214 14:44:49.884560 Allocating resources...
5215 14:44:49.884652 Reading resources...
5216 14:44:49.887964 Root Device read_resources bus 0 link: 0
5217 14:44:49.894270 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5218 14:44:49.894363 CPU: 00 missing read_resources
5219 14:44:49.900791 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5220 14:44:49.904254 Root Device read_resources bus 0 link: 0 done
5221 14:44:49.907972 Done reading resources.
5222 14:44:49.910721 Show resources in subtree (Root Device)...After reading.
5223 14:44:49.914390 Root Device child on link 0 CPU_CLUSTER: 0
5224 14:44:49.917697 CPU_CLUSTER: 0 child on link 0 CPU: 00
5225 14:44:49.927320 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5226 14:44:49.927426 CPU: 00
5227 14:44:49.930870 Setting resources...
5228 14:44:49.934066 Root Device assign_resources, bus 0 link: 0
5229 14:44:49.937871 CPU_CLUSTER: 0 missing set_resources
5230 14:44:49.941171 Root Device assign_resources, bus 0 link: 0
5231 14:44:49.944574 Done setting resources.
5232 14:44:49.951100 Show resources in subtree (Root Device)...After assigning values.
5233 14:44:49.954463 Root Device child on link 0 CPU_CLUSTER: 0
5234 14:44:49.957763 CPU_CLUSTER: 0 child on link 0 CPU: 00
5235 14:44:49.964204 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5236 14:44:49.967584 CPU: 00
5237 14:44:49.967678 Done allocating resources.
5238 14:44:49.974322 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5239 14:44:49.974415 Enabling resources...
5240 14:44:49.977603 done.
5241 14:44:49.981368 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5242 14:44:49.984391 Initializing devices...
5243 14:44:49.984483 Root Device init ...
5244 14:44:49.987770 mainboard_init: Starting display init.
5245 14:44:49.990975 ADC[4]: Raw value=75746 ID=0
5246 14:44:50.013792 anx7625_power_on_init: Init interface.
5247 14:44:50.017357 anx7625_disable_pd_protocol: Disabled PD feature.
5248 14:44:50.023588 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5249 14:44:50.070785 anx7625_start_dp_work: Secure OCM version=00
5250 14:44:50.074099 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5251 14:44:50.091324 sp_tx_get_edid_block: EDID Block = 1
5252 14:44:50.208188 Extracted contents:
5253 14:44:50.211517 header: 00 ff ff ff ff ff ff 00
5254 14:44:50.214946 serial number: 06 af 5c 14 00 00 00 00 00 1a
5255 14:44:50.218366 version: 01 04
5256 14:44:50.221381 basic params: 95 1a 0e 78 02
5257 14:44:50.224634 chroma info: 99 85 95 55 56 92 28 22 50 54
5258 14:44:50.227876 established: 00 00 00
5259 14:44:50.234722 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5260 14:44:50.237947 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5261 14:44:50.244848 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5262 14:44:50.251425 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5263 14:44:50.257681 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5264 14:44:50.261391 extensions: 00
5265 14:44:50.261484 checksum: ae
5266 14:44:50.261558
5267 14:44:50.264765 Manufacturer: AUO Model 145c Serial Number 0
5268 14:44:50.267545 Made week 0 of 2016
5269 14:44:50.267637 EDID version: 1.4
5270 14:44:50.271232 Digital display
5271 14:44:50.274459 6 bits per primary color channel
5272 14:44:50.274553 DisplayPort interface
5273 14:44:50.277539 Maximum image size: 26 cm x 14 cm
5274 14:44:50.281194 Gamma: 220%
5275 14:44:50.281286 Check DPMS levels
5276 14:44:50.284663 Supported color formats: RGB 4:4:4
5277 14:44:50.287706 First detailed timing is preferred timing
5278 14:44:50.290917 Established timings supported:
5279 14:44:50.294322 Standard timings supported:
5280 14:44:50.294414 Detailed timings
5281 14:44:50.300858 Hex of detail: ce1d56ea50001a3030204600009010000018
5282 14:44:50.304294 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5283 14:44:50.307587 0556 0586 05a6 0640 hborder 0
5284 14:44:50.311131 0300 0304 030a 031a vborder 0
5285 14:44:50.314596 -hsync -vsync
5286 14:44:50.317473 Did detailed timing
5287 14:44:50.320993 Hex of detail: 0000000f0000000000000000000000000020
5288 14:44:50.324101 Manufacturer-specified data, tag 15
5289 14:44:50.331230 Hex of detail: 000000fe0041554f0a202020202020202020
5290 14:44:50.331322 ASCII string: AUO
5291 14:44:50.334272 Hex of detail: 000000fe004231313658414230312e34200a
5292 14:44:50.337812 ASCII string: B116XAB01.4
5293 14:44:50.337904 Checksum
5294 14:44:50.341144 Checksum: 0xae (valid)
5295 14:44:50.347728 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5296 14:44:50.347821 DSI data_rate: 457800000 bps
5297 14:44:50.355442 anx7625_parse_edid: set default k value to 0x3d for panel
5298 14:44:50.358305 anx7625_parse_edid: pixelclock(76300).
5299 14:44:50.361738 hactive(1366), hsync(32), hfp(48), hbp(154)
5300 14:44:50.365206 vactive(768), vsync(6), vfp(4), vbp(16)
5301 14:44:50.368654 anx7625_dsi_config: config dsi.
5302 14:44:50.376519 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5303 14:44:50.397397 anx7625_dsi_config: success to config DSI
5304 14:44:50.400825 anx7625_dp_start: MIPI phy setup OK.
5305 14:44:50.403954 [SSUSB] Setting up USB HOST controller...
5306 14:44:50.407218 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5307 14:44:50.410894 [SSUSB] phy power-on done.
5308 14:44:50.414780 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5309 14:44:50.417834 in-header: 03 fc 01 00 00 00 00 00
5310 14:44:50.417926 in-data:
5311 14:44:50.421262 handle_proto3_response: EC response with error code: 1
5312 14:44:50.424584 SPM: pcm index = 1
5313 14:44:50.428052 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5314 14:44:50.431720 CBFS @ 21000 size 3d4000
5315 14:44:50.437779 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5316 14:44:50.441168 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5317 14:44:50.444833 CBFS: Found @ offset 1e7c0 size 1026
5318 14:44:50.451257 read SPI 0x3f808 0x1026: 1271 us, 3252 KB/s, 26.016 Mbps
5319 14:44:50.454915 SPM: binary array size = 2988
5320 14:44:50.457921 SPM: version = pcm_allinone_v1.17.2_20180829
5321 14:44:50.461112 SPM binary loaded in 32 msecs
5322 14:44:50.468878 spm_kick_im_to_fetch: ptr = 000000004021eec2
5323 14:44:50.471847 spm_kick_im_to_fetch: len = 2988
5324 14:44:50.471938 SPM: spm_kick_pcm_to_run
5325 14:44:50.474890 SPM: spm_kick_pcm_to_run done
5326 14:44:50.478402 SPM: spm_init done in 52 msecs
5327 14:44:50.481494 Root Device init finished in 494996 usecs
5328 14:44:50.485059 CPU_CLUSTER: 0 init ...
5329 14:44:50.495021 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5330 14:44:50.498370 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5331 14:44:50.501563 CBFS @ 21000 size 3d4000
5332 14:44:50.505108 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5333 14:44:50.508385 CBFS: Locating 'sspm.bin'
5334 14:44:50.511505 CBFS: Found @ offset 208c0 size 41cb
5335 14:44:50.521743 read SPI 0x418f8 0x41cb: 5141 us, 3276 KB/s, 26.208 Mbps
5336 14:44:50.529505 CPU_CLUSTER: 0 init finished in 42800 usecs
5337 14:44:50.529636 Devices initialized
5338 14:44:50.532984 Show all devs... After init.
5339 14:44:50.536537 Root Device: enabled 1
5340 14:44:50.536622 CPU_CLUSTER: 0: enabled 1
5341 14:44:50.539420 CPU: 00: enabled 1
5342 14:44:50.542984 BS: BS_DEV_INIT times (ms): entry 0 run 224 exit 0
5343 14:44:50.545890 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5344 14:44:50.549235 ELOG: NV offset 0x558000 size 0x1000
5345 14:44:50.557205 read SPI 0x558000 0x1000: 1263 us, 3243 KB/s, 25.944 Mbps
5346 14:44:50.563979 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5347 14:44:50.567333 ELOG: Event(17) added with size 13 at 2024-06-04 14:43:53 UTC
5348 14:44:50.570384 out: cmd=0x121: 03 db 21 01 00 00 00 00
5349 14:44:50.573889 in-header: 03 00 00 00 2c 00 00 00
5350 14:44:50.587614 in-data: 66 4b 00 00 00 00 00 00 02 10 00 00 06 80 00 00 8f 4c 01 00 06 80 00 00 f5 a2 02 00 06 80 00 00 47 87 03 00 06 80 00 00 2d 7c 07 00
5351 14:44:50.590822 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5352 14:44:50.594163 in-header: 03 19 00 00 08 00 00 00
5353 14:44:50.597286 in-data: a2 e0 47 00 13 00 00 00
5354 14:44:50.600783 Chrome EC: UHEPI supported
5355 14:44:50.607233 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5356 14:44:50.610259 in-header: 03 e1 00 00 08 00 00 00
5357 14:44:50.613747 in-data: 84 20 60 10 00 00 00 00
5358 14:44:50.617145 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5359 14:44:50.623837 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5360 14:44:50.627219 in-header: 03 e1 00 00 08 00 00 00
5361 14:44:50.630336 in-data: 84 20 60 10 00 00 00 00
5362 14:44:50.637044 ELOG: Event(A1) added with size 10 at 2024-06-04 14:43:53 UTC
5363 14:44:50.643895 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5364 14:44:50.647026 ELOG: Event(A0) added with size 9 at 2024-06-04 14:43:53 UTC
5365 14:44:50.653604 elog_add_boot_reason: Logged dev mode boot
5366 14:44:50.653697 Finalize devices...
5367 14:44:50.656965 Devices finalized
5368 14:44:50.660323 BS: BS_POST_DEVICE times (ms): entry 2 run 0 exit 0
5369 14:44:50.664213 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5370 14:44:50.670686 ELOG: Event(91) added with size 10 at 2024-06-04 14:43:53 UTC
5371 14:44:50.673567 Writing coreboot table at 0xffeda000
5372 14:44:50.677099 0. 0000000000114000-000000000011efff: RAMSTAGE
5373 14:44:50.683263 1. 0000000040000000-000000004023cfff: RAMSTAGE
5374 14:44:50.687007 2. 000000004023d000-00000000545fffff: RAM
5375 14:44:50.690666 3. 0000000054600000-000000005465ffff: BL31
5376 14:44:50.693553 4. 0000000054660000-00000000ffed9fff: RAM
5377 14:44:50.700166 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5378 14:44:50.703388 6. 0000000100000000-000000013fffffff: RAM
5379 14:44:50.707044 Passing 5 GPIOs to payload:
5380 14:44:50.709921 NAME | PORT | POLARITY | VALUE
5381 14:44:50.713855 write protect | 0x00000096 | low | high
5382 14:44:50.719755 EC in RW | 0x000000b1 | high | undefined
5383 14:44:50.723301 EC interrupt | 0x00000097 | low | undefined
5384 14:44:50.729707 TPM interrupt | 0x00000099 | high | undefined
5385 14:44:50.733414 speaker enable | 0x000000af | high | undefined
5386 14:44:50.736845 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5387 14:44:50.739779 in-header: 03 f7 00 00 02 00 00 00
5388 14:44:50.743302 in-data: 04 00
5389 14:44:50.743428 Board ID: 4
5390 14:44:50.746432 ADC[3]: Raw value=215504 ID=1
5391 14:44:50.746524 RAM code: 1
5392 14:44:50.746598 SKU ID: 16
5393 14:44:50.753085 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5394 14:44:50.753178 CBFS @ 21000 size 3d4000
5395 14:44:50.759651 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5396 14:44:50.766659 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum fd05
5397 14:44:50.766753 coreboot table: 940 bytes.
5398 14:44:50.773137 IMD ROOT 0. 00000000fffff000 00001000
5399 14:44:50.776564 IMD SMALL 1. 00000000ffffe000 00001000
5400 14:44:50.779896 CONSOLE 2. 00000000fffde000 00020000
5401 14:44:50.783065 FMAP 3. 00000000fffdd000 0000047c
5402 14:44:50.786673 TIME STAMP 4. 00000000fffdc000 00000910
5403 14:44:50.789602 RAMOOPS 5. 00000000ffedc000 00100000
5404 14:44:50.793013 COREBOOT 6. 00000000ffeda000 00002000
5405 14:44:50.796294 IMD small region:
5406 14:44:50.799889 IMD ROOT 0. 00000000ffffec00 00000400
5407 14:44:50.802788 VBOOT WORK 1. 00000000ffffeb00 00000100
5408 14:44:50.806308 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5409 14:44:50.809349 VPD 3. 00000000ffffea60 0000006c
5410 14:44:50.815913 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5411 14:44:50.822656 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5412 14:44:50.825992 in-header: 03 e1 00 00 08 00 00 00
5413 14:44:50.829189 in-data: 84 20 60 10 00 00 00 00
5414 14:44:50.832885 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5415 14:44:50.835981 CBFS @ 21000 size 3d4000
5416 14:44:50.839268 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5417 14:44:50.843029 CBFS: Locating 'fallback/payload'
5418 14:44:50.848219 CBFS: Found @ offset dc040 size 439a0
5419 14:44:50.938906 read SPI 0xfd078 0x439a0: 84379 us, 3281 KB/s, 26.248 Mbps
5420 14:44:50.942749 Checking segment from ROM address 0x0000000040003a00
5421 14:44:50.949220 Checking segment from ROM address 0x0000000040003a1c
5422 14:44:50.952626 Loading segment from ROM address 0x0000000040003a00
5423 14:44:50.955401 code (compression=0)
5424 14:44:50.965630 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5425 14:44:50.972109 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5426 14:44:50.975720 it's not compressed!
5427 14:44:50.979101 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5428 14:44:50.985384 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5429 14:44:50.993494 Loading segment from ROM address 0x0000000040003a1c
5430 14:44:50.996806 Entry Point 0x0000000080000000
5431 14:44:50.996897 Loaded segments
5432 14:44:51.003582 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5433 14:44:51.006859 Jumping to boot code at 0000000080000000(00000000ffeda000)
5434 14:44:51.016669 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5435 14:44:51.020390 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5436 14:44:51.023340 CBFS @ 21000 size 3d4000
5437 14:44:51.029891 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5438 14:44:51.033300 CBFS: Locating 'fallback/bl31'
5439 14:44:51.036366 CBFS: Found @ offset 36dc0 size 5820
5440 14:44:51.047295 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5441 14:44:51.051198 Checking segment from ROM address 0x0000000040003a00
5442 14:44:51.057819 Checking segment from ROM address 0x0000000040003a1c
5443 14:44:51.060982 Loading segment from ROM address 0x0000000040003a00
5444 14:44:51.063867 code (compression=1)
5445 14:44:51.070586 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5446 14:44:51.080701 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5447 14:44:51.080794 using LZMA
5448 14:44:51.089433 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5449 14:44:51.096083 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5450 14:44:51.099796 Loading segment from ROM address 0x0000000040003a1c
5451 14:44:51.102465 Entry Point 0x0000000054601000
5452 14:44:51.102557 Loaded segments
5453 14:44:51.105972 NOTICE: MT8183 bl31_setup
5454 14:44:51.113351 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5455 14:44:51.116230 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5456 14:44:51.119710 INFO: [DEVAPC] dump DEVAPC registers:
5457 14:44:51.129583 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5458 14:44:51.136243 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5459 14:44:51.146550 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5460 14:44:51.152839 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5461 14:44:51.163178 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5462 14:44:51.169953 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5463 14:44:51.179565 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5464 14:44:51.186081 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5465 14:44:51.193008 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5466 14:44:51.202510 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5467 14:44:51.209456 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5468 14:44:51.219329 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5469 14:44:51.225684 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5470 14:44:51.236065 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5471 14:44:51.242893 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5472 14:44:51.249270 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5473 14:44:51.255749 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5474 14:44:51.262550 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5475 14:44:51.272088 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5476 14:44:51.279003 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5477 14:44:51.285328 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5478 14:44:51.291929 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5479 14:44:51.295676 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5480 14:44:51.298511 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5481 14:44:51.301938 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5482 14:44:51.305120 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5483 14:44:51.308652 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5484 14:44:51.315160 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5485 14:44:51.322026 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5486 14:44:51.322135 WARNING: region 0:
5487 14:44:51.325233 WARNING: apc:0x168, sa:0x0, ea:0xfff
5488 14:44:51.328653 WARNING: region 1:
5489 14:44:51.332135 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5490 14:44:51.332227 WARNING: region 2:
5491 14:44:51.335201 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5492 14:44:51.338537 WARNING: region 3:
5493 14:44:51.341939 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5494 14:44:51.345156 WARNING: region 4:
5495 14:44:51.348491 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5496 14:44:51.348582 WARNING: region 5:
5497 14:44:51.351941 WARNING: apc:0x0, sa:0x0, ea:0x0
5498 14:44:51.355352 WARNING: region 6:
5499 14:44:51.358215 WARNING: apc:0x0, sa:0x0, ea:0x0
5500 14:44:51.358306 WARNING: region 7:
5501 14:44:51.361780 WARNING: apc:0x0, sa:0x0, ea:0x0
5502 14:44:51.368641 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5503 14:44:51.371727 INFO: SPM: enable SPMC mode
5504 14:44:51.375269 NOTICE: spm_boot_init() start
5505 14:44:51.378560 NOTICE: spm_boot_init() end
5506 14:44:51.381518 INFO: BL31: Initializing runtime services
5507 14:44:51.388238 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5508 14:44:51.391808 INFO: BL31: Preparing for EL3 exit to normal world
5509 14:44:51.394948 INFO: Entry point address = 0x80000000
5510 14:44:51.398354 INFO: SPSR = 0x8
5511 14:44:51.419700
5512 14:44:51.419796
5513 14:44:51.419871
5514 14:44:51.420359 end: 2.2.3 depthcharge-start (duration 00:00:11) [common]
5515 14:44:51.420470 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
5516 14:44:51.420561 Setting prompt string to ['jacuzzi:']
5517 14:44:51.420648 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:25)
5518 14:44:51.423147 Starting depthcharge on Juniper...
5519 14:44:51.423240
5520 14:44:51.426048 vboot_handoff: creating legacy vboot_handoff structure
5521 14:44:51.426141
5522 14:44:51.429663 ec_init(0): CrosEC protocol v3 supported (544, 544)
5523 14:44:51.429755
5524 14:44:51.433197 Wipe memory regions:
5525 14:44:51.433288
5526 14:44:51.436087 [0x00000040000000, 0x00000054600000)
5527 14:44:51.479317
5528 14:44:51.479423 [0x00000054660000, 0x00000080000000)
5529 14:44:51.570285
5530 14:44:51.570431 [0x000000811994a0, 0x000000ffeda000)
5531 14:44:51.829641
5532 14:44:51.829788 [0x00000100000000, 0x00000140000000)
5533 14:44:51.962373
5534 14:44:51.965152 Initializing XHCI USB controller at 0x11200000.
5535 14:44:51.988633
5536 14:44:51.991915 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5537 14:44:51.992009
5538 14:44:51.992086
5539 14:44:51.992378 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5541 14:44:52.092765 jacuzzi: tftpboot 192.168.201.1 14166985/tftp-deploy-pirxnrnz/kernel/image.itb 14166985/tftp-deploy-pirxnrnz/kernel/cmdline
5542 14:44:52.092926 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5543 14:44:52.093018 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
5544 14:44:52.097254 tftpboot 192.168.201.1 14166985/tftp-deploy-pirxnrnz/kernel/image.ittp-deploy-pirxnrnz/kernel/cmdline
5545 14:44:52.097349
5546 14:44:52.097422 Waiting for link
5547 14:44:52.502297
5548 14:44:52.502455 R8152: Initializing
5549 14:44:52.502531
5550 14:44:52.505922 Version 9 (ocp_data = 6010)
5551 14:44:52.506015
5552 14:44:52.508728 R8152: Done initializing
5553 14:44:52.508821
5554 14:44:52.508894 Adding net device
5555 14:44:52.894474
5556 14:44:52.894637 done.
5557 14:44:52.894713
5558 14:44:52.894782 MAC: 00:e0:4c:68:0b:b9
5559 14:44:52.894849
5560 14:44:52.898026 Sending DHCP discover... done.
5561 14:44:52.898120
5562 14:44:52.900943 Waiting for reply... done.
5563 14:44:52.901036
5564 14:44:52.904415 Sending DHCP request... done.
5565 14:44:52.904523
5566 14:44:52.909802 Waiting for reply... done.
5567 14:44:52.909904
5568 14:44:52.909978 My ip is 192.168.201.13
5569 14:44:52.910047
5570 14:44:52.912978 The DHCP server ip is 192.168.201.1
5571 14:44:52.913071
5572 14:44:52.919320 TFTP server IP predefined by user: 192.168.201.1
5573 14:44:52.919420
5574 14:44:52.926403 Bootfile predefined by user: 14166985/tftp-deploy-pirxnrnz/kernel/image.itb
5575 14:44:52.926495
5576 14:44:52.926568 Sending tftp read request... done.
5577 14:44:52.929608
5578 14:44:52.932617 Waiting for the transfer...
5579 14:44:52.932709
5580 14:44:53.190146 00000000 ################################################################
5581 14:44:53.190289
5582 14:44:53.448434 00080000 ################################################################
5583 14:44:53.448591
5584 14:44:53.693797 00100000 ################################################################
5585 14:44:53.693957
5586 14:44:53.936560 00180000 ################################################################
5587 14:44:53.936721
5588 14:44:54.183709 00200000 ################################################################
5589 14:44:54.183866
5590 14:44:54.430196 00280000 ################################################################
5591 14:44:54.430354
5592 14:44:54.676891 00300000 ################################################################
5593 14:44:54.677068
5594 14:44:54.925109 00380000 ################################################################
5595 14:44:54.925288
5596 14:44:55.174548 00400000 ################################################################
5597 14:44:55.174726
5598 14:44:55.423311 00480000 ################################################################
5599 14:44:55.423501
5600 14:44:55.673097 00500000 ################################################################
5601 14:44:55.673255
5602 14:44:55.923087 00580000 ################################################################
5603 14:44:55.923237
5604 14:44:56.172452 00600000 ################################################################
5605 14:44:56.172607
5606 14:44:56.423041 00680000 ################################################################
5607 14:44:56.423232
5608 14:44:56.684538 00700000 ################################################################
5609 14:44:56.684724
5610 14:44:56.946292 00780000 ################################################################
5611 14:44:56.946443
5612 14:44:57.192811 00800000 ################################################################
5613 14:44:57.192957
5614 14:44:57.439036 00880000 ################################################################
5615 14:44:57.439184
5616 14:44:57.685450 00900000 ################################################################
5617 14:44:57.685611
5618 14:44:57.932682 00980000 ################################################################
5619 14:44:57.932837
5620 14:44:58.181099 00a00000 ################################################################
5621 14:44:58.181254
5622 14:44:58.458217 00a80000 ################################################################
5623 14:44:58.458378
5624 14:44:58.753633 00b00000 ################################################################
5625 14:44:58.753785
5626 14:44:59.047722 00b80000 ################################################################
5627 14:44:59.047873
5628 14:44:59.309388 00c00000 ################################################################
5629 14:44:59.309547
5630 14:44:59.604086 00c80000 ################################################################
5631 14:44:59.604251
5632 14:44:59.994848 00d00000 ################################################################
5633 14:44:59.995373
5634 14:45:00.379245 00d80000 ################################################################
5635 14:45:00.379790
5636 14:45:00.769091 00e00000 ################################################################
5637 14:45:00.769624
5638 14:45:01.213658 00e80000 ################################################################
5639 14:45:01.214264
5640 14:45:01.568378 00f00000 ################################################################
5641 14:45:01.568966
5642 14:45:01.980399 00f80000 ################################################################
5643 14:45:01.980911
5644 14:45:02.333796 01000000 ################################################################
5645 14:45:02.333969
5646 14:45:02.625742 01080000 ################################################################
5647 14:45:02.625916
5648 14:45:02.924508 01100000 ################################################################
5649 14:45:02.924652
5650 14:45:03.227288 01180000 ################################################################
5651 14:45:03.227470
5652 14:45:03.523743 01200000 ################################################################
5653 14:45:03.523890
5654 14:45:03.865490 01280000 ################################################################
5655 14:45:03.866007
5656 14:45:04.275757 01300000 ################################################################
5657 14:45:04.276262
5658 14:45:04.654905 01380000 ################################################################
5659 14:45:04.655459
5660 14:45:05.047980 01400000 ################################################################
5661 14:45:05.048506
5662 14:45:05.445371 01480000 ################################################################
5663 14:45:05.445873
5664 14:45:05.848719 01500000 ################################################################
5665 14:45:05.849258
5666 14:45:06.209749 01580000 ################################################################
5667 14:45:06.209912
5668 14:45:06.477480 01600000 ################################################################
5669 14:45:06.477628
5670 14:45:06.734037 01680000 ################################################################
5671 14:45:06.734194
5672 14:45:07.016514 01700000 ################################################################
5673 14:45:07.016672
5674 14:45:07.284279 01780000 ################################################################
5675 14:45:07.284440
5676 14:45:07.545222 01800000 ################################################################
5677 14:45:07.545363
5678 14:45:07.827309 01880000 ################################################################
5679 14:45:07.827475
5680 14:45:08.136732 01900000 ################################################################
5681 14:45:08.137251
5682 14:45:08.544997 01980000 ################################################################
5683 14:45:08.545516
5684 14:45:08.946390 01a00000 ################################################################
5685 14:45:08.946948
5686 14:45:09.336686 01a80000 ################################################################
5687 14:45:09.337225
5688 14:45:09.736549 01b00000 ################################################################
5689 14:45:09.737152
5690 14:45:10.041079 01b80000 ################################################################
5691 14:45:10.041237
5692 14:45:10.324974 01c00000 ################################################################
5693 14:45:10.325131
5694 14:45:10.628040 01c80000 ################################################################
5695 14:45:10.628189
5696 14:45:10.914568 01d00000 ################################################################
5697 14:45:10.914740
5698 14:45:11.218169 01d80000 ################################################################
5699 14:45:11.218330
5700 14:45:11.523015 01e00000 ################################################################
5701 14:45:11.523178
5702 14:45:11.826422 01e80000 ################################################################
5703 14:45:11.826623
5704 14:45:12.125987 01f00000 ################################################################
5705 14:45:12.126146
5706 14:45:12.420635 01f80000 ################################################################
5707 14:45:12.420803
5708 14:45:12.833309 02000000 ################################################################
5709 14:45:12.834037
5710 14:45:13.175982 02080000 ################################################################
5711 14:45:13.176518
5712 14:45:13.559267 02100000 ################################################################
5713 14:45:13.559935
5714 14:45:13.951435 02180000 ################################################################
5715 14:45:13.952179
5716 14:45:14.359836 02200000 ################################################################
5717 14:45:14.360352
5718 14:45:14.778355 02280000 ################################################################
5719 14:45:14.778905
5720 14:45:15.049712 02300000 ################################################################
5721 14:45:15.049900
5722 14:45:15.299447 02380000 ################################################################
5723 14:45:15.299586
5724 14:45:15.544711 02400000 ################################################################
5725 14:45:15.544864
5726 14:45:15.799294 02480000 ################################################################
5727 14:45:15.799446
5728 14:45:16.047361 02500000 ################################################################
5729 14:45:16.047588
5730 14:45:16.291886 02580000 ################################################################
5731 14:45:16.292050
5732 14:45:16.550917 02600000 ################################################################
5733 14:45:16.551066
5734 14:45:16.838012 02680000 ################################################################
5735 14:45:16.838151
5736 14:45:17.118949 02700000 ################################################################
5737 14:45:17.119111
5738 14:45:17.385917 02780000 ################################################################
5739 14:45:17.386080
5740 14:45:17.651338 02800000 ################################################################
5741 14:45:17.651495
5742 14:45:17.940570 02880000 ################################################################
5743 14:45:17.940732
5744 14:45:18.200006 02900000 ################################################################
5745 14:45:18.200168
5746 14:45:18.459424 02980000 ################################################################
5747 14:45:18.459565
5748 14:45:18.731082 02a00000 ################################################################
5749 14:45:18.731224
5750 14:45:19.015030 02a80000 ################################################################
5751 14:45:19.015172
5752 14:45:19.301217 02b00000 ################################################################
5753 14:45:19.301356
5754 14:45:19.594430 02b80000 ################################################################
5755 14:45:19.594584
5756 14:45:20.004377 02c00000 ################################################################
5757 14:45:20.004895
5758 14:45:20.334209 02c80000 ################################################################
5759 14:45:20.334578
5760 14:45:20.731787 02d00000 ################################################################
5761 14:45:20.732293
5762 14:45:21.041910 02d80000 ################################################################
5763 14:45:21.042066
5764 14:45:21.334499 02e00000 ################################################################
5765 14:45:21.334657
5766 14:45:21.595875 02e80000 ################################################################
5767 14:45:21.596025
5768 14:45:21.870636 02f00000 ################################################################
5769 14:45:21.870794
5770 14:45:22.137170 02f80000 ################################################################
5771 14:45:22.137355
5772 14:45:22.396358 03000000 ################################################################
5773 14:45:22.396544
5774 14:45:22.656370 03080000 ################################################################
5775 14:45:22.656541
5776 14:45:22.916164 03100000 ################################################################
5777 14:45:22.916320
5778 14:45:23.175348 03180000 ################################################################
5779 14:45:23.175540
5780 14:45:23.437070 03200000 ################################################################
5781 14:45:23.437224
5782 14:45:23.692559 03280000 ################################################################
5783 14:45:23.692709
5784 14:45:23.958850 03300000 ################################################################
5785 14:45:23.959007
5786 14:45:24.244824 03380000 ################################################################
5787 14:45:24.244983
5788 14:45:24.519214 03400000 ################################################################
5789 14:45:24.519370
5790 14:45:24.773633 03480000 ################################################################
5791 14:45:24.773794
5792 14:45:25.037878 03500000 ################################################################
5793 14:45:25.038020
5794 14:45:25.302739 03580000 ################################################################
5795 14:45:25.302885
5796 14:45:25.573591 03600000 ################################################################
5797 14:45:25.573761
5798 14:45:25.827582 03680000 ################################################################
5799 14:45:25.827727
5800 14:45:26.085244 03700000 ################################################################
5801 14:45:26.085394
5802 14:45:26.340738 03780000 ################################################################
5803 14:45:26.340883
5804 14:45:26.638406 03800000 ################################################################
5805 14:45:26.638561
5806 14:45:26.994290 03880000 ################################################################
5807 14:45:26.994456
5808 14:45:27.339521 03900000 ################################################################
5809 14:45:27.339697
5810 14:45:27.669776 03980000 ################################################################
5811 14:45:27.669929
5812 14:45:27.996360 03a00000 ################################################################
5813 14:45:27.996514
5814 14:45:28.262958 03a80000 ################################################################
5815 14:45:28.263097
5816 14:45:28.520131 03b00000 ################################################################
5817 14:45:28.520275
5818 14:45:28.780153 03b80000 ################################################################
5819 14:45:28.780313
5820 14:45:29.040552 03c00000 ################################################################
5821 14:45:29.040698
5822 14:45:29.298718 03c80000 ################################################################
5823 14:45:29.298866
5824 14:45:29.599200 03d00000 ################################################################
5825 14:45:29.599370
5826 14:45:29.935937 03d80000 ################################################################
5827 14:45:29.936114
5828 14:45:30.264830 03e00000 ################################################################
5829 14:45:30.265013
5830 14:45:30.599925 03e80000 ################################################################
5831 14:45:30.600076
5832 14:45:30.927341 03f00000 ################################################################
5833 14:45:30.927493
5834 14:45:31.202545 03f80000 ################################################################
5835 14:45:31.202695
5836 14:45:31.473813 04000000 ################################################################
5837 14:45:31.473953
5838 14:45:31.735041 04080000 ################################################################
5839 14:45:31.735211
5840 14:45:32.007503 04100000 ################################################################
5841 14:45:32.007647
5842 14:45:32.264485 04180000 ################################################################
5843 14:45:32.264644
5844 14:45:32.524848 04200000 ################################################################
5845 14:45:32.525037
5846 14:45:32.810346 04280000 ################################################################
5847 14:45:32.810534
5848 14:45:33.077862 04300000 ################################################################
5849 14:45:33.078049
5850 14:45:33.335781 04380000 ################################################################
5851 14:45:33.335937
5852 14:45:33.606848 04400000 ################################################################
5853 14:45:33.606996
5854 14:45:33.880497 04480000 ################################################################
5855 14:45:33.880680
5856 14:45:34.175889 04500000 ################################################################
5857 14:45:34.176034
5858 14:45:34.455539 04580000 ################################################################
5859 14:45:34.455696
5860 14:45:34.712646 04600000 ################################################################
5861 14:45:34.712819
5862 14:45:34.810209 04680000 ######################### done.
5863 14:45:34.810353
5864 14:45:34.813607 The bootfile was 74122774 bytes long.
5865 14:45:34.813702
5866 14:45:34.816645 Sending tftp read request... done.
5867 14:45:34.816738
5868 14:45:34.820076 Waiting for the transfer...
5869 14:45:34.820169
5870 14:45:34.820243 00000000 # done.
5871 14:45:34.820315
5872 14:45:34.830237 Command line loaded dynamically from TFTP file: 14166985/tftp-deploy-pirxnrnz/kernel/cmdline
5873 14:45:34.830337
5874 14:45:34.846504 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
5875 14:45:34.846610
5876 14:45:34.846685 Loading FIT.
5877 14:45:34.846754
5878 14:45:34.849961 Image ramdisk-1 has 61002412 bytes.
5879 14:45:34.850054
5880 14:45:34.853612 Image fdt-1 has 57695 bytes.
5881 14:45:34.853705
5882 14:45:34.856963 Image kernel-1 has 13060619 bytes.
5883 14:45:34.857056
5884 14:45:34.863254 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5885 14:45:34.863349
5886 14:45:34.876715 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5887 14:45:34.876816
5888 14:45:34.883005 Choosing best match conf-1 for compat google,juniper-sku16.
5889 14:45:34.883127
5890 14:45:34.890975 Connected to device vid:did:rid of 1ae0:0028:00
5891 14:45:34.898428
5892 14:45:34.901940 tpm_get_response: command 0x17b, return code 0x0
5893 14:45:34.902036
5894 14:45:34.905374 tpm_cleanup: add release locality here.
5895 14:45:34.905497
5896 14:45:34.908796 Shutting down all USB controllers.
5897 14:45:34.908915
5898 14:45:34.911839 Removing current net device
5899 14:45:34.911932
5900 14:45:34.915198 Exiting depthcharge with code 4 at timestamp: 60747354
5901 14:45:34.915290
5902 14:45:34.918856 LZMA decompressing kernel-1 to 0x80193568
5903 14:45:34.918976
5904 14:45:34.925091 LZMA decompressing kernel-1 to 0x40000000
5905 14:45:36.782948
5906 14:45:36.783113 jumping to kernel
5907 14:45:36.783694 end: 2.2.4 bootloader-commands (duration 00:00:45) [common]
5908 14:45:36.783806 start: 2.2.5 auto-login-action (timeout 00:03:39) [common]
5909 14:45:36.783891 Setting prompt string to ['Linux version [0-9]']
5910 14:45:36.783968 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5911 14:45:36.784046 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5912 14:45:36.858704
5913 14:45:36.861847 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5914 14:45:36.865199 start: 2.2.5.1 login-action (timeout 00:03:39) [common]
5915 14:45:36.865313 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5916 14:45:36.865403 Setting prompt string to []
5917 14:45:36.865493 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5918 14:45:36.865576 Using line separator: #'\n'#
5919 14:45:36.865644 No login prompt set.
5920 14:45:36.865714 Parsing kernel messages
5921 14:45:36.865777 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5922 14:45:36.865894 [login-action] Waiting for messages, (timeout 00:03:39)
5923 14:45:36.865968 Waiting using forced prompt support (timeout 00:01:50)
5924 14:45:36.884972 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j216541-arm64-gcc-10-defconfig-arm64-chromebook-f7c97) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024
5925 14:45:36.888273 [ 0.000000] random: crng init done
5926 14:45:36.895006 [ 0.000000] Machine model: Google juniper sku16 board
5927 14:45:36.898618 [ 0.000000] efi: UEFI not found.
5928 14:45:36.905209 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5929 14:45:36.911285 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5930 14:45:36.921555 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5931 14:45:36.924877 [ 0.000000] printk: bootconsole [mtk8250] enabled
5932 14:45:36.932895 [ 0.000000] NUMA: No NUMA configuration found
5933 14:45:36.939773 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5934 14:45:36.946190 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff]
5935 14:45:36.946286 [ 0.000000] Zone ranges:
5936 14:45:36.953197 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5937 14:45:36.956585 [ 0.000000] DMA32 empty
5938 14:45:36.963427 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5939 14:45:36.966364 [ 0.000000] Movable zone start for each node
5940 14:45:36.969700 [ 0.000000] Early memory node ranges
5941 14:45:36.976621 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5942 14:45:36.982921 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5943 14:45:36.989799 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5944 14:45:36.996372 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5945 14:45:37.002947 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5946 14:45:37.009643 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5947 14:45:37.025724 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5948 14:45:37.032136 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5949 14:45:37.038990 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5950 14:45:37.042487 [ 0.000000] psci: probing for conduit method from DT.
5951 14:45:37.049172 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5952 14:45:37.052229 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5953 14:45:37.058926 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5954 14:45:37.062229 [ 0.000000] psci: SMC Calling Convention v1.1
5955 14:45:37.068644 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5956 14:45:37.072079 [ 0.000000] Detected VIPT I-cache on CPU0
5957 14:45:37.078932 [ 0.000000] CPU features: detected: GIC system register CPU interface
5958 14:45:37.085320 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5959 14:45:37.091942 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5960 14:45:37.098474 [ 0.000000] CPU features: detected: ARM erratum 845719
5961 14:45:37.101827 [ 0.000000] alternatives: applying boot alternatives
5962 14:45:37.104941 [ 0.000000] Fallback order for Node 0: 0
5963 14:45:37.111435 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5964 14:45:37.114978 [ 0.000000] Policy zone: Normal
5965 14:45:37.134646 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
5966 14:45:37.147908 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5967 14:45:37.154656 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5968 14:45:37.164509 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5969 14:45:37.171237 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
5970 14:45:37.174410 <6>[ 0.000000] software IO TLB: area num 8.
5971 14:45:37.200252 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5972 14:45:37.258001 <6>[ 0.000000] Memory: 3855628K/4191232K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 302836K reserved, 32768K cma-reserved)
5973 14:45:37.264980 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5974 14:45:37.271773 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5975 14:45:37.274682 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5976 14:45:37.281317 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5977 14:45:37.288187 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5978 14:45:37.291505 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5979 14:45:37.301291 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5980 14:45:37.308185 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5981 14:45:37.314350 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5982 14:45:37.324696 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5983 14:45:37.328080 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5984 14:45:37.331409 <6>[ 0.000000] GICv3: 640 SPIs implemented
5985 14:45:37.337522 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5986 14:45:37.341069 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5987 14:45:37.344675 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5988 14:45:37.354551 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5989 14:45:37.364024 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5990 14:45:37.377572 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5991 14:45:37.383983 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5992 14:45:37.394989 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5993 14:45:37.408712 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5994 14:45:37.415032 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5995 14:45:37.422002 <6>[ 0.009477] Console: colour dummy device 80x25
5996 14:45:37.425413 <6>[ 0.014532] printk: console [tty1] enabled
5997 14:45:37.435307 <6>[ 0.018921] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5998 14:45:37.441867 <6>[ 0.029385] pid_max: default: 32768 minimum: 301
5999 14:45:37.445383 <6>[ 0.034267] LSM: Security Framework initializing
6000 14:45:37.455283 <6>[ 0.039182] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
6001 14:45:37.461737 <6>[ 0.046805] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
6002 14:45:37.468378 <4>[ 0.055689] cacheinfo: Unable to detect cache hierarchy for CPU 0
6003 14:45:37.478706 <6>[ 0.062316] cblist_init_generic: Setting adjustable number of callback queues.
6004 14:45:37.484911 <6>[ 0.069762] cblist_init_generic: Setting shift to 3 and lim to 1.
6005 14:45:37.492163 <6>[ 0.076115] cblist_init_generic: Setting adjustable number of callback queues.
6006 14:45:37.498441 <6>[ 0.083559] cblist_init_generic: Setting shift to 3 and lim to 1.
6007 14:45:37.501721 <6>[ 0.089957] rcu: Hierarchical SRCU implementation.
6008 14:45:37.508051 <6>[ 0.094983] rcu: Max phase no-delay instances is 1000.
6009 14:45:37.515372 <6>[ 0.102925] EFI services will not be available.
6010 14:45:37.518763 <6>[ 0.107875] smp: Bringing up secondary CPUs ...
6011 14:45:37.529108 <6>[ 0.113113] Detected VIPT I-cache on CPU1
6012 14:45:37.535752 <4>[ 0.113160] cacheinfo: Unable to detect cache hierarchy for CPU 1
6013 14:45:37.542048 <6>[ 0.113170] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
6014 14:45:37.548932 <6>[ 0.113201] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
6015 14:45:37.552289 <6>[ 0.113680] Detected VIPT I-cache on CPU2
6016 14:45:37.558958 <4>[ 0.113712] cacheinfo: Unable to detect cache hierarchy for CPU 2
6017 14:45:37.565324 <6>[ 0.113717] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
6018 14:45:37.572415 <6>[ 0.113729] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
6019 14:45:37.575398 <6>[ 0.114176] Detected VIPT I-cache on CPU3
6020 14:45:37.581870 <4>[ 0.114206] cacheinfo: Unable to detect cache hierarchy for CPU 3
6021 14:45:37.591965 <6>[ 0.114211] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
6022 14:45:37.598750 <6>[ 0.114222] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
6023 14:45:37.602424 <6>[ 0.114798] CPU features: detected: Spectre-v2
6024 14:45:37.605414 <6>[ 0.114808] CPU features: detected: Spectre-BHB
6025 14:45:37.612217 <6>[ 0.114812] CPU features: detected: ARM erratum 858921
6026 14:45:37.615301 <6>[ 0.114818] Detected VIPT I-cache on CPU4
6027 14:45:37.621972 <4>[ 0.114865] cacheinfo: Unable to detect cache hierarchy for CPU 4
6028 14:45:37.629169 <6>[ 0.114873] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
6029 14:45:37.635329 <6>[ 0.114881] arch_timer: Enabling local workaround for ARM erratum 858921
6030 14:45:37.642234 <6>[ 0.114891] arch_timer: CPU4: Trapping CNTVCT access
6031 14:45:37.648747 <6>[ 0.114899] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
6032 14:45:37.651961 <6>[ 0.115384] Detected VIPT I-cache on CPU5
6033 14:45:37.658496 <4>[ 0.115425] cacheinfo: Unable to detect cache hierarchy for CPU 5
6034 14:45:37.665266 <6>[ 0.115431] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
6035 14:45:37.672277 <6>[ 0.115438] arch_timer: Enabling local workaround for ARM erratum 858921
6036 14:45:37.678659 <6>[ 0.115444] arch_timer: CPU5: Trapping CNTVCT access
6037 14:45:37.685533 <6>[ 0.115449] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
6038 14:45:37.688876 <6>[ 0.115884] Detected VIPT I-cache on CPU6
6039 14:45:37.695645 <4>[ 0.115930] cacheinfo: Unable to detect cache hierarchy for CPU 6
6040 14:45:37.702141 <6>[ 0.115936] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
6041 14:45:37.708553 <6>[ 0.115943] arch_timer: Enabling local workaround for ARM erratum 858921
6042 14:45:37.714804 <6>[ 0.115949] arch_timer: CPU6: Trapping CNTVCT access
6043 14:45:37.721749 <6>[ 0.115954] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
6044 14:45:37.724682 <6>[ 0.116485] Detected VIPT I-cache on CPU7
6045 14:45:37.731946 <4>[ 0.116530] cacheinfo: Unable to detect cache hierarchy for CPU 7
6046 14:45:37.738381 <6>[ 0.116536] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
6047 14:45:37.748047 <6>[ 0.116543] arch_timer: Enabling local workaround for ARM erratum 858921
6048 14:45:37.751785 <6>[ 0.116549] arch_timer: CPU7: Trapping CNTVCT access
6049 14:45:37.758254 <6>[ 0.116554] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
6050 14:45:37.761418 <6>[ 0.116602] smp: Brought up 1 node, 8 CPUs
6051 14:45:37.767917 <6>[ 0.355513] SMP: Total of 8 processors activated.
6052 14:45:37.774769 <6>[ 0.360448] CPU features: detected: 32-bit EL0 Support
6053 14:45:37.777832 <6>[ 0.365828] CPU features: detected: 32-bit EL1 Support
6054 14:45:37.784789 <6>[ 0.371196] CPU features: detected: CRC32 instructions
6055 14:45:37.787726 <6>[ 0.376622] CPU: All CPU(s) started at EL2
6056 14:45:37.794850 <6>[ 0.380960] alternatives: applying system-wide alternatives
6057 14:45:37.801709 <6>[ 0.389035] devtmpfs: initialized
6058 14:45:37.813826 <6>[ 0.397975] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
6059 14:45:37.823695 <6>[ 0.407922] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
6060 14:45:37.826928 <6>[ 0.415649] pinctrl core: initialized pinctrl subsystem
6061 14:45:37.835371 <6>[ 0.422768] DMI not present or invalid.
6062 14:45:37.841816 <6>[ 0.427136] NET: Registered PF_NETLINK/PF_ROUTE protocol family
6063 14:45:37.848761 <6>[ 0.434031] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
6064 14:45:37.855555 <6>[ 0.441560] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
6065 14:45:37.865978 <6>[ 0.449812] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
6066 14:45:37.872170 <6>[ 0.457990] audit: initializing netlink subsys (disabled)
6067 14:45:37.878907 <5>[ 0.463694] audit: type=2000 audit(0.328:1): state=initialized audit_enabled=0 res=1
6068 14:45:37.885734 <6>[ 0.464667] thermal_sys: Registered thermal governor 'step_wise'
6069 14:45:37.892170 <6>[ 0.471660] thermal_sys: Registered thermal governor 'power_allocator'
6070 14:45:37.895662 <6>[ 0.477957] cpuidle: using governor menu
6071 14:45:37.901920 <6>[ 0.488918] NET: Registered PF_QIPCRTR protocol family
6072 14:45:37.908930 <6>[ 0.494401] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
6073 14:45:37.915316 <6>[ 0.501498] ASID allocator initialised with 32768 entries
6074 14:45:37.918570 <6>[ 0.508266] Serial: AMBA PL011 UART driver
6075 14:45:37.930854 <4>[ 0.518679] Trying to register duplicate clock ID: 113
6076 14:45:37.991085 <6>[ 0.575434] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6077 14:45:38.005460 <6>[ 0.589786] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6078 14:45:38.008875 <6>[ 0.599525] KASLR enabled
6079 14:45:38.023307 <6>[ 0.607543] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
6080 14:45:38.029848 <6>[ 0.614544] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
6081 14:45:38.036870 <6>[ 0.621021] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
6082 14:45:38.042901 <6>[ 0.628012] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
6083 14:45:38.049896 <6>[ 0.634486] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
6084 14:45:38.056302 <6>[ 0.641476] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
6085 14:45:38.063035 <6>[ 0.647951] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
6086 14:45:38.069834 <6>[ 0.654941] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
6087 14:45:38.073194 <6>[ 0.662507] ACPI: Interpreter disabled.
6088 14:45:38.083031 <6>[ 0.670487] iommu: Default domain type: Translated
6089 14:45:38.089767 <6>[ 0.675593] iommu: DMA domain TLB invalidation policy: strict mode
6090 14:45:38.093096 <5>[ 0.682224] SCSI subsystem initialized
6091 14:45:38.099714 <6>[ 0.686638] usbcore: registered new interface driver usbfs
6092 14:45:38.106267 <6>[ 0.692365] usbcore: registered new interface driver hub
6093 14:45:38.109653 <6>[ 0.697907] usbcore: registered new device driver usb
6094 14:45:38.116627 <6>[ 0.704207] pps_core: LinuxPPS API ver. 1 registered
6095 14:45:38.126430 <6>[ 0.709392] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
6096 14:45:38.130031 <6>[ 0.718716] PTP clock support registered
6097 14:45:38.132929 <6>[ 0.722969] EDAC MC: Ver: 3.0.0
6098 14:45:38.140946 <6>[ 0.728612] FPGA manager framework
6099 14:45:38.147698 <6>[ 0.732297] Advanced Linux Sound Architecture Driver Initialized.
6100 14:45:38.151208 <6>[ 0.739042] vgaarb: loaded
6101 14:45:38.154554 <6>[ 0.742166] clocksource: Switched to clocksource arch_sys_counter
6102 14:45:38.161407 <5>[ 0.748604] VFS: Disk quotas dquot_6.6.0
6103 14:45:38.167582 <6>[ 0.752778] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
6104 14:45:38.171132 <6>[ 0.759951] pnp: PnP ACPI: disabled
6105 14:45:38.179185 <6>[ 0.766779] NET: Registered PF_INET protocol family
6106 14:45:38.185898 <6>[ 0.772012] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
6107 14:45:38.197871 <6>[ 0.781920] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
6108 14:45:38.207372 <6>[ 0.790673] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
6109 14:45:38.214174 <6>[ 0.798623] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
6110 14:45:38.221286 <6>[ 0.806855] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
6111 14:45:38.227717 <6>[ 0.814947] TCP: Hash tables configured (established 32768 bind 32768)
6112 14:45:38.237630 <6>[ 0.821773] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
6113 14:45:38.244137 <6>[ 0.828743] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
6114 14:45:38.250791 <6>[ 0.836225] NET: Registered PF_UNIX/PF_LOCAL protocol family
6115 14:45:38.257430 <6>[ 0.842322] RPC: Registered named UNIX socket transport module.
6116 14:45:38.260803 <6>[ 0.848467] RPC: Registered udp transport module.
6117 14:45:38.267278 <6>[ 0.853392] RPC: Registered tcp transport module.
6118 14:45:38.274067 <6>[ 0.858315] RPC: Registered tcp NFSv4.1 backchannel transport module.
6119 14:45:38.277079 <6>[ 0.864967] PCI: CLS 0 bytes, default 64
6120 14:45:38.280576 <6>[ 0.869217] Unpacking initramfs...
6121 14:45:38.290705 <6>[ 0.873270] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
6122 14:45:38.297155 <6>[ 0.881990] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
6123 14:45:38.303771 <6>[ 0.890897] kvm [1]: IPA Size Limit: 40 bits
6124 14:45:38.307184 <6>[ 0.897219] kvm [1]: vgic-v2@c420000
6125 14:45:38.314217 <6>[ 0.901043] kvm [1]: GIC system register CPU interface enabled
6126 14:45:38.320290 <6>[ 0.907221] kvm [1]: vgic interrupt IRQ18
6127 14:45:38.323292 <6>[ 0.911586] kvm [1]: Hyp mode initialized successfully
6128 14:45:38.330054 <5>[ 0.917884] Initialise system trusted keyrings
6129 14:45:38.337233 <6>[ 0.922661] workingset: timestamp_bits=42 max_order=20 bucket_order=0
6130 14:45:38.345101 <6>[ 0.932598] squashfs: version 4.0 (2009/01/31) Phillip Lougher
6131 14:45:38.352107 <5>[ 0.938990] NFS: Registering the id_resolver key type
6132 14:45:38.354925 <5>[ 0.944292] Key type id_resolver registered
6133 14:45:38.361636 <5>[ 0.948704] Key type id_legacy registered
6134 14:45:38.368073 <6>[ 0.952997] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
6135 14:45:38.374930 <6>[ 0.959914] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
6136 14:45:38.381877 <6>[ 0.967644] 9p: Installing v9fs 9p2000 file system support
6137 14:45:38.409011 <5>[ 0.996566] Key type asymmetric registered
6138 14:45:38.412445 <5>[ 1.000901] Asymmetric key parser 'x509' registered
6139 14:45:38.422444 <6>[ 1.006051] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
6140 14:45:38.425805 <6>[ 1.013662] io scheduler mq-deadline registered
6141 14:45:38.428632 <6>[ 1.018417] io scheduler kyber registered
6142 14:45:38.451521 <6>[ 1.039141] EINJ: ACPI disabled.
6143 14:45:38.457957 <4>[ 1.042871] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
6144 14:45:38.495791 <6>[ 1.083444] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
6145 14:45:38.504454 <6>[ 1.091863] printk: console [ttyS0] disabled
6146 14:45:38.532208 <6>[ 1.116509] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
6147 14:45:38.539259 <6>[ 1.125982] printk: console [ttyS0] enabled
6148 14:45:38.542138 <6>[ 1.125982] printk: console [ttyS0] enabled
6149 14:45:38.549003 <6>[ 1.134903] printk: bootconsole [mtk8250] disabled
6150 14:45:38.552405 <6>[ 1.134903] printk: bootconsole [mtk8250] disabled
6151 14:45:38.562070 <3>[ 1.145420] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
6152 14:45:38.568564 <3>[ 1.153798] mt6577-uart 11003000.serial: Error applying setting, reverse things back
6153 14:45:38.598253 <6>[ 1.182184] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
6154 14:45:38.604767 <6>[ 1.191828] serial serial0: tty port ttyS1 registered
6155 14:45:38.611021 <6>[ 1.198412] SuperH (H)SCI(F) driver initialized
6156 14:45:38.614484 <6>[ 1.203918] msm_serial: driver initialized
6157 14:45:38.629878 <6>[ 1.214238] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
6158 14:45:38.640074 <6>[ 1.222828] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
6159 14:45:38.646971 <6>[ 1.231404] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
6160 14:45:38.656629 <6>[ 1.239971] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
6161 14:45:38.663204 <6>[ 1.248626] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
6162 14:45:38.673327 <6>[ 1.257286] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
6163 14:45:38.683126 <6>[ 1.266024] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
6164 14:45:38.689641 <6>[ 1.274762] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
6165 14:45:38.699596 <6>[ 1.283328] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
6166 14:45:38.709425 <6>[ 1.292127] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
6167 14:45:38.717118 <4>[ 1.304515] cacheinfo: Unable to detect cache hierarchy for CPU 0
6168 14:45:38.726435 <6>[ 1.313843] loop: module loaded
6169 14:45:38.738132 <6>[ 1.325739] vsim1: Bringing 1800000uV into 2700000-2700000uV
6170 14:45:38.756182 <6>[ 1.343606] megasas: 07.719.03.00-rc1
6171 14:45:38.764802 <6>[ 1.352270] spi-nor spi1.0: w25q64dw (8192 Kbytes)
6172 14:45:38.777965 <6>[ 1.365563] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
6173 14:45:38.795118 <6>[ 1.382333] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
6174 14:45:38.851800 <6>[ 1.432556] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1d
6175 14:45:40.331198 <6>[ 2.918894] Freeing initrd memory: 59572K
6176 14:45:40.346835 <4>[ 2.930913] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
6177 14:45:40.353472 <4>[ 2.940161] CPU: 7 PID: 1 Comm: swapper/0 Not tainted 6.1.91-cip21 #1
6178 14:45:40.359800 <4>[ 2.946860] Hardware name: Google juniper sku16 board (DT)
6179 14:45:40.363224 <4>[ 2.952599] Call trace:
6180 14:45:40.366679 <4>[ 2.955299] dump_backtrace.part.0+0xe0/0xf0
6181 14:45:40.370197 <4>[ 2.959834] show_stack+0x18/0x30
6182 14:45:40.373131 <4>[ 2.963407] dump_stack_lvl+0x68/0x84
6183 14:45:40.380011 <4>[ 2.967328] dump_stack+0x18/0x34
6184 14:45:40.383281 <4>[ 2.970898] sysfs_warn_dup+0x64/0x80
6185 14:45:40.386623 <4>[ 2.974819] sysfs_do_create_link_sd+0xf0/0x100
6186 14:45:40.389669 <4>[ 2.979606] sysfs_create_link+0x20/0x40
6187 14:45:40.396655 <4>[ 2.983785] bus_add_device+0x68/0x10c
6188 14:45:40.399696 <4>[ 2.987792] device_add+0x340/0x7ac
6189 14:45:40.403395 <4>[ 2.991535] of_device_add+0x44/0x60
6190 14:45:40.409662 <4>[ 2.995368] of_platform_device_create_pdata+0x90/0x120
6191 14:45:40.413140 <4>[ 3.000850] of_platform_bus_create+0x170/0x370
6192 14:45:40.416779 <4>[ 3.005636] of_platform_populate+0x50/0xfc
6193 14:45:40.423129 <4>[ 3.010076] parse_mtd_partitions+0x1dc/0x510
6194 14:45:40.426481 <4>[ 3.014689] mtd_device_parse_register+0xf8/0x2e0
6195 14:45:40.429952 <4>[ 3.019647] spi_nor_probe+0x21c/0x2f0
6196 14:45:40.436481 <4>[ 3.023653] spi_mem_probe+0x6c/0xb0
6197 14:45:40.439552 <4>[ 3.027485] spi_probe+0x84/0xe4
6198 14:45:40.443284 <4>[ 3.030967] really_probe+0xbc/0x2e0
6199 14:45:40.446471 <4>[ 3.034797] __driver_probe_device+0x78/0x11c
6200 14:45:40.452881 <4>[ 3.039409] driver_probe_device+0xd8/0x160
6201 14:45:40.456347 <4>[ 3.043846] __device_attach_driver+0xb8/0x134
6202 14:45:40.459306 <4>[ 3.048545] bus_for_each_drv+0x78/0xd0
6203 14:45:40.462667 <4>[ 3.052635] __device_attach+0xa8/0x1c0
6204 14:45:40.469495 <4>[ 3.056725] device_initial_probe+0x14/0x20
6205 14:45:40.472663 <4>[ 3.061163] bus_probe_device+0x9c/0xa4
6206 14:45:40.475903 <4>[ 3.065253] device_add+0x3ac/0x7ac
6207 14:45:40.479532 <4>[ 3.068995] __spi_add_device+0x78/0x120
6208 14:45:40.485760 <4>[ 3.073173] spi_add_device+0x40/0x7c
6209 14:45:40.488947 <4>[ 3.077090] spi_register_controller+0x610/0xad0
6210 14:45:40.495826 <4>[ 3.081963] devm_spi_register_controller+0x4c/0xa4
6211 14:45:40.499294 <4>[ 3.087095] mtk_spi_probe+0x3f8/0x650
6212 14:45:40.502665 <4>[ 3.091099] platform_probe+0x68/0xe0
6213 14:45:40.505540 <4>[ 3.095017] really_probe+0xbc/0x2e0
6214 14:45:40.512348 <4>[ 3.098847] __driver_probe_device+0x78/0x11c
6215 14:45:40.515520 <4>[ 3.103458] driver_probe_device+0xd8/0x160
6216 14:45:40.519152 <4>[ 3.107896] __driver_attach+0x94/0x19c
6217 14:45:40.522459 <4>[ 3.111986] bus_for_each_dev+0x70/0xd0
6218 14:45:40.529260 <4>[ 3.116076] driver_attach+0x24/0x30
6219 14:45:40.532415 <4>[ 3.119906] bus_add_driver+0x154/0x20c
6220 14:45:40.535626 <4>[ 3.123996] driver_register+0x78/0x130
6221 14:45:40.541944 <4>[ 3.128086] __platform_driver_register+0x28/0x34
6222 14:45:40.545330 <4>[ 3.133046] mtk_spi_driver_init+0x1c/0x28
6223 14:45:40.548723 <4>[ 3.137400] do_one_initcall+0x50/0x1d0
6224 14:45:40.552011 <4>[ 3.141490] kernel_init_freeable+0x21c/0x288
6225 14:45:40.558754 <4>[ 3.146103] kernel_init+0x24/0x12c
6226 14:45:40.561815 <4>[ 3.149848] ret_from_fork+0x10/0x20
6227 14:45:40.571590 <6>[ 3.158802] tun: Universal TUN/TAP device driver, 1.6
6228 14:45:40.574897 <6>[ 3.165078] thunder_xcv, ver 1.0
6229 14:45:40.577941 <6>[ 3.168594] thunder_bgx, ver 1.0
6230 14:45:40.581289 <6>[ 3.172098] nicpf, ver 1.0
6231 14:45:40.592143 <6>[ 3.176459] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
6232 14:45:40.595901 <6>[ 3.183943] hns3: Copyright (c) 2017 Huawei Corporation.
6233 14:45:40.602280 <6>[ 3.189540] hclge is initializing
6234 14:45:40.605920 <6>[ 3.193129] e1000: Intel(R) PRO/1000 Network Driver
6235 14:45:40.612157 <6>[ 3.198265] e1000: Copyright (c) 1999-2006 Intel Corporation.
6236 14:45:40.615610 <6>[ 3.204287] e1000e: Intel(R) PRO/1000 Network Driver
6237 14:45:40.622580 <6>[ 3.209509] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
6238 14:45:40.629053 <6>[ 3.215702] igb: Intel(R) Gigabit Ethernet Network Driver
6239 14:45:40.635519 <6>[ 3.221356] igb: Copyright (c) 2007-2014 Intel Corporation.
6240 14:45:40.642346 <6>[ 3.227199] igbvf: Intel(R) Gigabit Virtual Function Network Driver
6241 14:45:40.649024 <6>[ 3.233721] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
6242 14:45:40.652092 <6>[ 3.240273] sky2: driver version 1.30
6243 14:45:40.658554 <6>[ 3.245518] usbcore: registered new device driver r8152-cfgselector
6244 14:45:40.665452 <6>[ 3.252060] usbcore: registered new interface driver r8152
6245 14:45:40.672090 <6>[ 3.257885] VFIO - User Level meta-driver version: 0.3
6246 14:45:40.679038 <6>[ 3.265675] mtu3 11201000.usb: uwk - reg:0x420, version:101
6247 14:45:40.685272 <4>[ 3.271550] mtu3 11201000.usb: supply vbus not found, using dummy regulator
6248 14:45:40.691933 <6>[ 3.278831] mtu3 11201000.usb: dr_mode: 1, drd: auto
6249 14:45:40.698707 <6>[ 3.284056] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
6250 14:45:40.701895 <6>[ 3.290243] mtu3 11201000.usb: usb3-drd: 0
6251 14:45:40.711512 <6>[ 3.295762] mtu3 11201000.usb: xHCI platform device register success...
6252 14:45:40.718488 <4>[ 3.304386] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
6253 14:45:40.724803 <6>[ 3.312340] xhci-mtk 11200000.usb: xHCI Host Controller
6254 14:45:40.731877 <6>[ 3.317870] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
6255 14:45:40.738312 <6>[ 3.325592] xhci-mtk 11200000.usb: USB3 root hub has no ports
6256 14:45:40.748357 <6>[ 3.331600] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
6257 14:45:40.754647 <6>[ 3.341023] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
6258 14:45:40.761720 <6>[ 3.347094] xhci-mtk 11200000.usb: xHCI Host Controller
6259 14:45:40.767859 <6>[ 3.352590] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
6260 14:45:40.774750 <6>[ 3.360249] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
6261 14:45:40.777993 <6>[ 3.367063] hub 1-0:1.0: USB hub found
6262 14:45:40.781229 <6>[ 3.371092] hub 1-0:1.0: 1 port detected
6263 14:45:40.792161 <6>[ 3.376418] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
6264 14:45:40.795601 <6>[ 3.385036] hub 2-0:1.0: USB hub found
6265 14:45:40.805549 <3>[ 3.389064] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
6266 14:45:40.812104 <6>[ 3.396947] usbcore: registered new interface driver usb-storage
6267 14:45:40.818325 <6>[ 3.403532] usbcore: registered new device driver onboard-usb-hub
6268 14:45:40.833809 <4>[ 3.418260] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
6269 14:45:40.843337 <6>[ 3.430566] mt6397-rtc mt6358-rtc: registered as rtc0
6270 14:45:40.852778 <6>[ 3.436046] mt6397-rtc mt6358-rtc: setting system clock to 2024-06-04T14:44:43 UTC (1717512283)
6271 14:45:40.859768 <6>[ 3.445923] i2c_dev: i2c /dev entries driver
6272 14:45:40.869516 <6>[ 3.452360] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6273 14:45:40.876280 <6>[ 3.460683] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6274 14:45:40.883010 <6>[ 3.469587] i2c 4-0058: Fixed dependency cycle(s) with /panel
6275 14:45:40.889596 <6>[ 3.475620] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
6276 14:45:40.899545 <3>[ 3.483068] anx7625 4-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
6277 14:45:40.916116 <6>[ 3.500096] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6278 14:45:40.924265 <6>[ 3.511567] cpu cpu0: EM: created perf domain
6279 14:45:40.934144 <6>[ 3.517032] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
6280 14:45:40.941138 <6>[ 3.528321] cpu cpu4: EM: created perf domain
6281 14:45:40.948063 <6>[ 3.535253] sdhci: Secure Digital Host Controller Interface driver
6282 14:45:40.954141 <6>[ 3.541763] sdhci: Copyright(c) Pierre Ossman
6283 14:45:40.961074 <6>[ 3.547166] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
6284 14:45:40.967673 <6>[ 3.547255] Synopsys Designware Multimedia Card Interface Driver
6285 14:45:40.974396 <6>[ 3.559768] sdhci-pltfm: SDHCI platform and OF driver helper
6286 14:45:40.980802 <6>[ 3.567721] ledtrig-cpu: registered to indicate activity on CPUs
6287 14:45:40.987949 <6>[ 3.575471] usbcore: registered new interface driver usbhid
6288 14:45:40.991333 <6>[ 3.581319] usbhid: USB HID core driver
6289 14:45:41.002087 <6>[ 3.585639] spi_master spi2: will run message pump with realtime priority
6290 14:45:41.009545 <4>[ 3.585787] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
6291 14:45:41.016225 <4>[ 3.599978] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
6292 14:45:41.029342 <6>[ 3.605756] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
6293 14:45:41.042656 <6>[ 3.622862] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
6294 14:45:41.049274 <4>[ 3.635009] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6295 14:45:41.055730 <6>[ 3.637707] cros-ec-spi spi2.0: Chrome EC device registered
6296 14:45:41.069649 <4>[ 3.653617] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6297 14:45:41.081150 <4>[ 3.665400] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6298 14:45:41.088101 <4>[ 3.674080] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6299 14:45:41.094842 <6>[ 3.678643] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x13014
6300 14:45:41.101433 <6>[ 3.683289] mmc1: new ultra high speed SDR104 SDIO card at address 0001
6301 14:45:41.104723 <6>[ 3.687681] mmc0: new HS400 MMC card at address 0001
6302 14:45:41.111589 <6>[ 3.699085] mmcblk0: mmc0:0001 DA4032 29.1 GiB
6303 14:45:41.121909 <6>[ 3.709599] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
6304 14:45:41.129814 <6>[ 3.717394] mmcblk0boot0: mmc0:0001 DA4032 4.00 MiB
6305 14:45:41.139902 <6>[ 3.718400] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
6306 14:45:41.143024 <6>[ 3.724198] mmcblk0boot1: mmc0:0001 DA4032 4.00 MiB
6307 14:45:41.156657 <6>[ 3.734822] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6308 14:45:41.160197 <6>[ 3.737726] mmcblk0rpmb: mmc0:0001 DA4032 16.0 MiB, chardev (507:0)
6309 14:45:41.172921 <6>[ 3.746140] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
6310 14:45:41.182841 <6>[ 3.746440] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
6311 14:45:41.189765 <6>[ 3.748692] NET: Registered PF_PACKET protocol family
6312 14:45:41.193190 <6>[ 3.781301] 9pnet: Installing 9P2000 support
6313 14:45:41.196572 <5>[ 3.785860] Key type dns_resolver registered
6314 14:45:41.203381 <6>[ 3.790861] registered taskstats version 1
6315 14:45:41.206748 <5>[ 3.795231] Loading compiled-in X.509 certificates
6316 14:45:41.213616 <6>[ 3.798180] usb 1-1: new high-speed USB device number 2 using xhci-mtk
6317 14:45:41.245616 <3>[ 3.829362] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
6318 14:45:41.272847 <4>[ 3.857062] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6319 14:45:41.286823 <6>[ 3.867674] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6320 14:45:41.300535 <6>[ 3.880546] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6321 14:45:41.313682 <3>[ 3.892226] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6322 14:45:41.328187 <3>[ 3.908618] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6323 14:45:41.334556 <3>[ 3.921379] debugfs: File 'Playback' in directory 'dapm' already present!
6324 14:45:41.344395 <3>[ 3.928460] debugfs: File 'Capture' in directory 'dapm' already present!
6325 14:45:41.358709 <6>[ 3.939334] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input4
6326 14:45:41.370086 <6>[ 3.953777] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
6327 14:45:41.373432 <6>[ 3.958056] hub 1-1:1.0: USB hub found
6328 14:45:41.382806 <6>[ 3.962378] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
6329 14:45:41.386171 <6>[ 3.966793] hub 1-1:1.0: 3 ports detected
6330 14:45:41.396100 <6>[ 3.974914] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
6331 14:45:41.402841 <6>[ 3.987649] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
6332 14:45:41.412594 <6>[ 3.996234] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
6333 14:45:41.419352 <6>[ 4.004769] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
6334 14:45:41.429379 <6>[ 4.013302] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
6335 14:45:41.435618 <6>[ 4.022677] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
6336 14:45:41.442630 <6>[ 4.030213] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
6337 14:45:41.450041 <6>[ 4.037502] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
6338 14:45:41.460790 <6>[ 4.044752] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
6339 14:45:41.467213 <6>[ 4.052174] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
6340 14:45:41.474268 <6>[ 4.060454] panfrost 13040000.gpu: clock rate = 511999970
6341 14:45:41.484318 <6>[ 4.066164] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
6342 14:45:41.490856 <6>[ 4.076416] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
6343 14:45:41.500735 <6>[ 4.084445] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
6344 14:45:41.513862 <6>[ 4.092878] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
6345 14:45:41.520605 <6>[ 4.104956] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
6346 14:45:41.531791 <6>[ 4.116089] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6347 14:45:41.541920 <6>[ 4.125045] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6348 14:45:41.551580 <6>[ 4.134194] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6349 14:45:41.558647 <6>[ 4.143325] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6350 14:45:41.568148 <6>[ 4.152453] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6351 14:45:41.578499 <6>[ 4.161752] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6352 14:45:41.588483 <6>[ 4.171053] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6353 14:45:41.598426 <6>[ 4.180527] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6354 14:45:41.608417 <6>[ 4.190000] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6355 14:45:41.614931 <6>[ 4.199126] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6356 14:45:41.687247 <6>[ 4.271381] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6357 14:45:41.697732 <6>[ 4.280270] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6358 14:45:41.708073 <6>[ 4.292102] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6359 14:45:41.725680 <6>[ 4.310185] usb 1-1.2: new high-speed USB device number 3 using xhci-mtk
6360 14:45:42.405095 <6>[ 4.502423] r8152-cfgselector 1-1.2: reset high-speed USB device number 3 using xhci-mtk
6361 14:45:42.414589 <4>[ 4.619573] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6362 14:45:42.421863 <4>[ 4.619592] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6363 14:45:42.427870 <6>[ 4.655984] r8152 1-1.2:1.0 eth0: v1.12.13
6364 14:45:42.434409 <6>[ 4.734333] usb 1-1.3: new high-speed USB device number 4 using xhci-mtk
6365 14:45:42.441351 <6>[ 4.972382] Console: switching to colour frame buffer device 170x48
6366 14:45:42.448253 <6>[ 5.033020] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6367 14:45:42.466145 <6>[ 5.049667] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input5
6368 14:45:42.472461 <6>[ 5.058035] input: volume-buttons as /devices/platform/volume-buttons/input/input6
6369 14:45:43.665116 <6>[ 6.252586] r8152 1-1.2:1.0 eth0: carrier on
6370 14:45:43.711269 <5>[ 6.282206] Sending DHCP requests ., OK
6371 14:45:43.717520 <6>[ 6.302423] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.13
6372 14:45:43.720753 <6>[ 6.310856] IP-Config: Complete:
6373 14:45:43.734098 <6>[ 6.314427] device=eth0, hwaddr=00:e0:4c:68:0b:b9, ipaddr=192.168.201.13, mask=255.255.255.0, gw=192.168.201.1
6374 14:45:43.740929 <6>[ 6.325327] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-0, domain=lava-rack, nis-domain=(none)
6375 14:45:43.750742 <6>[ 6.334810] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6376 14:45:43.754350 <6>[ 6.334820] nameserver0=192.168.201.1
6377 14:45:43.757807 <6>[ 6.347189] clk: Disabling unused clocks
6378 14:45:43.761950 <6>[ 6.352331] ALSA device list:
6379 14:45:43.771746 <6>[ 6.358918] #0: mt8183_mt6358_ts3a227_max98357
6380 14:45:43.783030 <6>[ 6.370516] Freeing unused kernel memory: 8512K
6381 14:45:43.790700 <6>[ 6.378119] Run /init as init process
6382 14:45:43.826622 <6>[ 6.414114] NET: Registered PF_INET6 protocol family
6383 14:45:43.834915 <6>[ 6.421858] Segment Routing with IPv6
6384 14:45:43.837536 <6>[ 6.426710] In-situ OAM (IOAM) with IPv6
6385 14:45:43.884091 <30>[ 6.444967] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6386 14:45:43.895817 <30>[ 6.482961] systemd[1]: Detected architecture arm64.
6387 14:45:43.895952
6388 14:45:43.902532 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6389 14:45:43.902646
6390 14:45:43.919170 <30>[ 6.506415] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6391 14:45:44.067037 <30>[ 6.650587] systemd[1]: Queued start job for default target graphical.target.
6392 14:45:44.096445 <30>[ 6.680366] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6393 14:45:44.106205 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6394 14:45:44.122879 <30>[ 6.707003] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6395 14:45:44.132643 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6396 14:45:44.151602 <30>[ 6.735528] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6397 14:45:44.162678 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6398 14:45:44.179413 <30>[ 6.763115] systemd[1]: Created slice user.slice - User and Session Slice.
6399 14:45:44.189176 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6400 14:45:44.210096 <30>[ 6.790649] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6401 14:45:44.221422 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6402 14:45:44.242768 <30>[ 6.823312] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6403 14:45:44.254577 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6404 14:45:44.281208 <30>[ 6.854849] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6405 14:45:44.299183 <30>[ 6.883215] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6406 14:45:44.306801 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6407 14:45:44.326912 <30>[ 6.910422] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6408 14:45:44.339574 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6409 14:45:44.358974 <30>[ 6.942813] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6410 14:45:44.373238 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6411 14:45:44.387125 <30>[ 6.974432] systemd[1]: Reached target paths.target - Path Units.
6412 14:45:44.401801 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6413 14:45:44.418365 <30>[ 7.002390] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6414 14:45:44.431033 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6415 14:45:44.447678 <30>[ 7.034712] systemd[1]: Reached target slices.target - Slice Units.
6416 14:45:44.462720 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6417 14:45:44.475084 <30>[ 7.062426] systemd[1]: Reached target swap.target - Swaps.
6418 14:45:44.485731 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6419 14:45:44.506440 <30>[ 7.090450] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6420 14:45:44.520060 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6421 14:45:44.539619 <30>[ 7.123365] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6422 14:45:44.553565 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6423 14:45:44.572843 <30>[ 7.156864] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6424 14:45:44.586372 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6425 14:45:44.603383 <30>[ 7.187136] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6426 14:45:44.617459 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6427 14:45:44.635178 <30>[ 7.218992] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6428 14:45:44.647102 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6429 14:45:44.667233 <30>[ 7.251045] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6430 14:45:44.680453 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6431 14:45:44.699207 <30>[ 7.282876] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6432 14:45:44.712053 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6433 14:45:44.754575 <30>[ 7.338718] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6434 14:45:44.767673 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6435 14:45:44.791809 <30>[ 7.375991] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6436 14:45:44.805029 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6437 14:45:44.846300 <30>[ 7.430536] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6438 14:45:44.857482 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6439 14:45:44.881145 <30>[ 7.458608] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6440 14:45:44.901255 <30>[ 7.485216] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6441 14:45:44.913670 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6442 14:45:44.935505 <30>[ 7.519641] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6443 14:45:44.948847 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6444 14:45:44.998848 <30>[ 7.582715] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6445 14:45:45.014163 Starting [0;1;39mmodpr<6>[ 7.596657] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6446 14:45:45.018858 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6447 14:45:45.044612 <30>[ 7.628672] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6448 14:45:45.055561 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
6449 14:45:45.080540 <30>[ 7.664463] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6450 14:45:45.094832 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6451 14:45:45.135083 <30>[ 7.718859] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6452 14:45:45.146464 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6453 14:45:45.171963 <30>[ 7.756207] systemd[1]: Starting systemd-journald.service - Journal Service...
6454 14:45:45.183028 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6455 14:45:45.202166 <30>[ 7.786048] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6456 14:45:45.212673 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6457 14:45:45.238104 <30>[ 7.818880] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6458 14:45:45.249115 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6459 14:45:45.298974 <30>[ 7.882809] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6460 14:45:45.311834 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
6461 14:45:45.334618 <30>[ 7.918276] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6462 14:45:45.347110 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
6463 14:45:45.366552 <30>[ 7.949998] systemd[1]: Started systemd-journald.service - Journal Service.
6464 14:45:45.375857 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6465 14:45:45.396565 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
6466 14:45:45.415126 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
6467 14:45:45.435014 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
6468 14:45:45.451974 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
6469 14:45:45.473556 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
6470 14:45:45.497448 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6471 14:45:45.517315 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6472 14:45:45.541931 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6473 14:45:45.561134 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6474 14:45:45.580389 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6475 14:45:45.600192 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6476 14:45:45.621589 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6477 14:45:45.663139 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
6478 14:45:45.684834 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
6479 14:45:45.708212 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
6480 14:45:45.723345 See 'systemctl status systemd-remount-fs.service' for details.
6481 14:45:45.744823 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6482 14:45:45.763709 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6483 14:45:45.783977 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6484 14:45:45.840309 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
6485 14:45:45.852962 <46>[ 8.436950] systemd-journald[199]: Received client request to flush runtime journal.
6486 14:45:45.871913 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
6487 14:45:45.890303 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
6488 14:45:45.915285 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6489 14:45:45.932853 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6490 14:45:45.952786 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
6491 14:45:45.995355 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6492 14:45:46.026468 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
6493 14:45:46.048596 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6494 14:45:46.071366 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6495 14:45:46.116134 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6496 14:45:46.139675 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6497 14:45:46.166754 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6498 14:45:46.203581 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
6499 14:45:46.229592 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
6500 14:45:46.248008 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
6501 14:45:46.280476 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6502 14:45:46.313404 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6503 14:45:46.333843 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
6504 14:45:46.422385 <3>[ 9.009669] mtk-scp 10500000.scp: invalid resource
6505 14:45:46.428898 <3>[ 9.013188] thermal_sys: Failed to find 'trips' node
6506 14:45:46.435429 <6>[ 9.015075] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6507 14:45:46.442349 <3>[ 9.020079] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6508 14:45:46.459981 <3>[ 9.039558] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6509 14:45:46.466572 <3>[ 9.041257] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6510 14:45:46.473456 <6>[ 9.043393] remoteproc remoteproc0: scp is available
6511 14:45:46.479971 <4>[ 9.043521] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6512 14:45:46.486350 <6>[ 9.043530] remoteproc remoteproc0: powering up scp
6513 14:45:46.492890 <4>[ 9.043559] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6514 14:45:46.499938 <3>[ 9.043564] remoteproc remoteproc0: request_firmware failed: -2
6515 14:45:46.506595 <3>[ 9.050597] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6516 14:45:46.513107 <4>[ 9.059022] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6517 14:45:46.526875 <3>[ 9.064249] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6518 14:45:46.533494 <4>[ 9.074421] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6519 14:45:46.540051 <3>[ 9.077909] elan_i2c 2-0015: Error applying setting, reverse things back
6520 14:45:46.546810 <3>[ 9.086937] thermal_sys: Failed to find 'trips' node
6521 14:45:46.553061 <4>[ 9.090611] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6522 14:45:46.560322 <3>[ 9.093011] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6523 14:45:46.567166 <3>[ 9.099362] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6524 14:45:46.576717 <3>[ 9.107197] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6525 14:45:46.580041 <6>[ 9.111770] mc: Linux media interface: v0.10
6526 14:45:46.590500 <3>[ 9.118097] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6527 14:45:46.600466 <3>[ 9.125131] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6528 14:45:46.606690 <3>[ 9.129762] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6529 14:45:46.613473 <4>[ 9.132550] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6530 14:45:46.623399 <6>[ 9.133959] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6531 14:45:46.629597 <5>[ 9.137394] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6532 14:45:46.640101 <3>[ 9.137456] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6533 14:45:46.647054 <5>[ 9.152903] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6534 14:45:46.656271 <3>[ 9.153386] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6535 14:45:46.667301 <5>[ 9.161602] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6536 14:45:46.677802 <3>[ 9.169176] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6537 14:45:46.684823 <6>[ 9.170149] videodev: Linux video capture interface: v2.00
6538 14:45:46.695646 <6>[ 9.170260] cs_system_cfg: CoreSight Configuration manager initialised
6539 14:45:46.705437 <4>[ 9.173750] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6540 14:45:46.715377 <3>[ 9.182228] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6541 14:45:46.721900 <6>[ 9.190704] cfg80211: failed to load regulatory.db
6542 14:45:46.732532 <3>[ 9.199282] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6543 14:45:46.742322 <6>[ 9.239051] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7
6544 14:45:46.803434 [[0;32m OK [0m] Created slice [0;1;39msyste<6>[ 9.387036] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6545 14:45:46.806544 m-syste…- Slice /system/systemd-backlight.
6546 14:45:46.816552 <6>[ 9.399062] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6547 14:45:46.819760 <6>[ 9.401577] Bluetooth: Core ver 2.22
6548 14:45:46.829500 <6>[ 9.416647] NET: Registered PF_BLUETOOTH protocol family
6549 14:45:46.839251 [[0;32m OK [<6>[ 9.417483] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6550 14:45:46.846233 0m] Reached targ<6>[ 9.422254] Bluetooth: HCI device and connection manager initialized
6551 14:45:46.852628 et [0;1;39msoun<6>[ 9.433592] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6552 14:45:46.862795 d.target[0m - S<6>[ 9.433728] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6553 14:45:46.862923 ound Card.
6554 14:45:46.872743 <6>[ 9.435305] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video0
6555 14:45:46.875988 <6>[ 9.439333] Bluetooth: HCI socket layer initialized
6556 14:45:46.887348 <6>[ 9.446679] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video1 (81,1)
6557 14:45:46.893575 <6>[ 9.455316] Bluetooth: L2CAP socket layer initialized
6558 14:45:46.900575 <6>[ 9.455320] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6559 14:45:46.907384 <6>[ 9.455341] Bluetooth: SCO socket layer initialized
6560 14:45:46.913676 <6>[ 9.455499] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6561 14:45:46.920323 <6>[ 9.456837] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6562 14:45:46.943927 <46>[ 9.460468] systemd-journald[199]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.1 (1537 of 2047 items, 524288 file size, 341 bytes per hash table item), suggesting rotation.
6563 14:45:46.957550 <46>[ 9.460496] systemd-journald[199]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
6564 14:45:46.971249 <6>[ 9.475223] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6565 14:45:46.981611 <6>[ 9.480084] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6566 14:45:46.987838 <6>[ 9.485220] usbcore: registered new interface driver uvcvideo
6567 14:45:46.995644 <6>[ 9.485363] Bluetooth: HCI UART driver ver 2.3
6568 14:45:47.002748 <6>[ 9.485369] Bluetooth: HCI UART protocol H4 registered
6569 14:45:47.010246 <6>[ 9.485406] Bluetooth: HCI UART protocol LL registered
6570 14:45:47.017140 <6>[ 9.485422] Bluetooth: HCI UART protocol Three-wire (H5) registered
6571 14:45:47.025313 <6>[ 9.485782] Bluetooth: HCI UART protocol Broadcom registered
6572 14:45:47.033445 <6>[ 9.485807] Bluetooth: HCI UART protocol QCA registered
6573 14:45:47.040949 <6>[ 9.485819] Bluetooth: HCI UART protocol Marvell registered
6574 14:45:47.048614 <6>[ 9.487663] Bluetooth: hci0: setting up ROME/QCA6390
6575 14:45:47.061058 <6>[ 9.493212] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6576 14:45:47.071259 <6>[ 9.506881] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6577 14:45:47.083200 <6>[ 9.507258] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6578 14:45:47.093592 <6>[ 9.513403] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6579 14:45:47.131355 [[0;32m OK [<6>[ 9.711716] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6580 14:45:47.137327 0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
6581 14:45:47.145542 <3>[ 9.731762] Bluetooth: hci0: Frame reassembly failed (-84)
6582 14:45:47.153515 <4>[ 9.732194] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6583 14:45:47.160388 <4>[ 9.732194] Fallback method does not support PEC.
6584 14:45:47.167388 <3>[ 9.735602] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6585 14:45:47.177917 <3>[ 9.743310] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6586 14:45:47.201215 <3>[ 9.784165] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6587 14:45:47.216904 Starting [0;1;39msystemd-backlight…ess of backlight:backlight_lcd0...
6588 14:45:47.248412 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6589 14:45:47.285886 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
6590 14:45:47.309418 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initiali<6>[ 9.893105] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6591 14:45:47.309810 zation.
6592 14:45:47.327767 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6593 14:45:47.346860 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
6594 14:45:47.362332 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6595 14:45:47.379082 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
6596 14:45:47.398239 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
6597 14:45:47.407967 <6>[ 9.994849] Bluetooth: hci0: QCA Product ID :0x00000008
6598 14:45:47.415051 <6>[ 10.002301] Bluetooth: hci0: QCA SOC Version :0x00000044
6599 14:45:47.421695 <6>[ 10.002308] Bluetooth: hci0: QCA ROM Version :0x00000302
6600 14:45:47.429295 [[0;32m OK [0m] Listening on<6>[ 10.002312] Bluetooth: hci0: QCA Patch Version:0x00000111
6601 14:45:47.439335 [0;1;39msystemd-rfkil…l Swit<6>[ 10.002321] Bluetooth: hci0: QCA controller version 0x00440302
6602 14:45:47.442838 ch Status /dev/rfkill Watch.
6603 14:45:47.449321 <6>[ 10.034234] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6604 14:45:47.459786 <4>[ 10.042788] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6605 14:45:47.469246 [[0;32m OK [<3>[ 10.053429] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6606 14:45:47.476024 0m] Reached targ<3>[ 10.062970] Bluetooth: hci0: QCA Failed to download patch (-2)
6607 14:45:47.482272 et [0;1;39mbasic.target[0m - Basic System.
6608 14:45:47.515780 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
6609 14:45:47.543871 <3>[ 10.126208] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6610 14:45:47.550153 <3>[ 10.129483] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6611 14:45:47.561573 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6612 14:45:47.574048 <3>[ 10.155834] power_supply sbs-12-000b: driver failed to report `current_avg' property: -5
6613 14:45:47.580491 <3>[ 10.161169] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6614 14:45:47.600155 Starting [0;1;39msystemd-user-sess…vice[0m - Permit<3>[ 10.183927] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6615 14:45:47.603330 User Sessions...
6616 14:45:47.620736 <3>[ 10.203870] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6617 14:45:47.632069 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6618 14:45:47.644636 <3>[ 10.225302] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6619 14:45:47.665004 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6620 14:45:47.712926 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6621 14:45:47.758137 <6>[ 10.341705] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6622 14:45:47.776141 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6623 14:45:47.796133 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6624 14:45:47.840690 Starting [0;1;39msyste<4>[ 10.426192] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6625 14:45:47.846848 md-rfkill.se…Load/Save RF Kill Switch Status...
6626 14:45:47.860680 <4>[ 10.444259] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6627 14:45:47.874649 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load<4>[ 10.458209] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6628 14:45:47.877676 /Save RF Kill Switch Status.
6629 14:45:47.884193 <4>[ 10.470221] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6630 14:45:47.895922 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6631 14:45:47.917950 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6632 14:45:47.928098 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6633 14:45:47.968283 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6634 14:45:48.008253 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6635 14:45:48.053501
6636 14:45:48.056875 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6637 14:45:48.057414
6638 14:45:48.059650 debian-bookworm-arm64 login: root (automatic login)
6639 14:45:48.060136
6640 14:45:48.077955 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024 aarch64
6641 14:45:48.078577
6642 14:45:48.084559 The programs included with the Debian GNU/Linux system are free software;
6643 14:45:48.091401 the exact distribution terms for each program are described in the
6644 14:45:48.094206 individual files in /usr/share/doc/*/copyright.
6645 14:45:48.094588
6646 14:45:48.101179 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6647 14:45:48.104158 permitted by applicable law.
6648 14:45:48.105397 Matched prompt #10: / #
6650 14:45:48.106325 Setting prompt string to ['/ #']
6651 14:45:48.106728 end: 2.2.5.1 login-action (duration 00:00:11) [common]
6653 14:45:48.107750 end: 2.2.5 auto-login-action (duration 00:00:11) [common]
6654 14:45:48.108169 start: 2.2.6 expect-shell-connection (timeout 00:03:28) [common]
6655 14:45:48.108501 Setting prompt string to ['/ #']
6656 14:45:48.108787 Forcing a shell prompt, looking for ['/ #']
6658 14:45:48.159508 / #
6659 14:45:48.160114 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6660 14:45:48.160507 Waiting using forced prompt support (timeout 00:02:30)
6661 14:45:48.166131
6662 14:45:48.166895 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6663 14:45:48.167385 start: 2.2.7 export-device-env (timeout 00:03:28) [common]
6664 14:45:48.167893 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6665 14:45:48.168330 end: 2.2 depthcharge-retry (duration 00:01:32) [common]
6666 14:45:48.168868 end: 2 depthcharge-action (duration 00:01:32) [common]
6667 14:45:48.169400 start: 3 lava-test-retry (timeout 00:08:00) [common]
6668 14:45:48.169959 start: 3.1 lava-test-shell (timeout 00:08:00) [common]
6669 14:45:48.170364 Using namespace: common
6671 14:45:48.271566 / # #
6672 14:45:48.272209 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
6673 14:45:48.278786 #
6674 14:45:48.279555 Using /lava-14166985
6676 14:45:48.380535 / # export SHELL=/bin/sh
6677 14:45:48.386569 export SHELL=/bin/sh
6679 14:45:48.488057 / # . /lava-14166985/environment
6680 14:45:48.494077 . /lava-14166985/environment
6682 14:45:48.595583 / # /lava-14166985/bin/lava-test-runner /lava-14166985/0
6683 14:45:48.596170 Test shell timeout: 10s (minimum of the action and connection timeout)
6684 14:45:48.601805 /lava-14166985/bin/lava-test-runner /lava-14166985/0
6685 14:45:48.634765 + export TESTRUN_ID=0_igt-gpu-pa<8>[ 11.220808] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 14166985_1.5.2.3.1>
6686 14:45:48.635209 Received signal: <STARTRUN> 0_igt-gpu-panfrost 14166985_1.5.2.3.1
6687 14:45:48.635296 Starting test lava.0_igt-gpu-panfrost (14166985_1.5.2.3.1)
6688 14:45:48.635390 Skipping test definition patterns.
6689 14:45:48.637988 nfrost
6690 14:45:48.641561 + cd /lava-14166985/0/tests/0_igt-gpu-panfrost
6691 14:45:48.641656 + cat uuid
6692 14:45:48.644694 + UUID=14166985_1.5.2.3.1
6693 14:45:48.644789 + set +x
6694 14:45:48.654828 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
6695 14:45:48.661905 <8>[ 11.249115] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
6696 14:45:48.662176 Received signal: <TESTSET> START panfrost_gem_new
6697 14:45:48.662258 Starting test_set panfrost_gem_new
6698 14:45:48.685334 <6>[ 11.272146] Console: switching to colour dummy device 80x25
6699 14:45:48.691459 <14>[ 11.278213] [IGT] panfrost_gem_new: executing
6700 14:45:48.699155 IGT-Version: 1.2<14>[ 11.283246] [IGT] panfrost_gem_new: starting subtest gem-new-4096
6701 14:45:48.708149 8-ga44ebfe (aarc<14>[ 11.291270] [IGT] panfrost_gem_new: finished subtest gem-new-4096, SUCCESS
6702 14:45:48.714851 h64) (Linux: 6.1<14>[ 11.300053] [IGT] panfrost_gem_new: exiting, ret=0
6703 14:45:48.714958 .91-cip21 aarch64)
6704 14:45:48.721768 Using IGT_SRANDOM=1717512291 for randomisation
6705 14:45:48.721862 Opened device: /dev/dri/card0
6706 14:45:48.725167 Starting subtest: gem-new-4096
6707 14:45:48.731728 [1mSubtest gem-new-4096: SUCCESS (0.000s)[0m
6708 14:45:48.758702 <6>[ 11.329236] Console: switching to colour frame buffer device 170x48
6709 14:45:48.774789 <8>[ 11.358560] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=pass>
6710 14:45:48.775540 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=pass
6712 14:45:48.796136 <6>[ 11.382915] Console: switching to colour dummy device 80x25
6713 14:45:48.802908 <14>[ 11.389066] [IGT] panfrost_gem_new: executing
6714 14:45:48.809243 IGT-Version: 1.2<14>[ 11.394116] [IGT] panfrost_gem_new: starting subtest gem-new-0
6715 14:45:48.815792 <14>[ 11.401525] [IGT] panfrost_gem_new: finished subtest gem-new-0, SUCCESS
6716 14:45:48.822989 8-ga44ebfe (aarc<14>[ 11.408854] [IGT] panfrost_gem_new: exiting, ret=0
6717 14:45:48.826230 h64) (Linux: 6.1.91-cip21 aarch64)
6718 14:45:48.829362 Using IGT_SRANDOM=1717512291 for randomisation
6719 14:45:48.833036 Opened device: /dev/dri/card0
6720 14:45:48.836216 Starting subtest: gem-new-0
6721 14:45:48.839326 [1mSubtest gem-new-0: SUCCESS (0.000s)[0m
6722 14:45:48.878273 <6>[ 11.445898] Console: switching to colour frame buffer device 170x48
6723 14:45:48.891440 <8>[ 11.478064] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=pass>
6724 14:45:48.892193 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=pass
6726 14:45:48.915213 <6>[ 11.502247] Console: switching to colour dummy device 80x25
6727 14:45:48.922081 <14>[ 11.508487] [IGT] panfrost_gem_new: executing
6728 14:45:48.928721 IGT-Version: 1.2<14>[ 11.513891] [IGT] panfrost_gem_new: starting subtest gem-new-zeroed
6729 14:45:48.938957 8-ga44ebfe (aarc<14>[ 11.523265] [IGT] panfrost_gem_new: finished subtest gem-new-zeroed, SUCCESS
6730 14:45:48.945179 h64) (Linux: 6.1<14>[ 11.530994] [IGT] panfrost_gem_new: exiting, ret=0
6731 14:45:48.948301 .91-cip21 aarch64)
6732 14:45:48.952303 Using IGT_SRANDOM=1717512292 for randomisation
6733 14:45:48.955536 Opened device: /dev/dri/card0
6734 14:45:48.959079 Starting subtest: gem-new-zeroed
6735 14:45:48.961401 [1mSubtest gem-new-zeroed: SUCCESS (0.001s)[0m
6736 14:45:48.992455 <6>[ 11.562215] Console: switching to colour frame buffer device 170x48
6737 14:45:49.008584 <8>[ 11.591883] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=pass>
6738 14:45:49.009439 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=pass
6740 14:45:49.014871 <8>[ 11.601851] <LAVA_SIGNAL_TESTSET STOP>
6741 14:45:49.015718 Received signal: <TESTSET> STOP
6742 14:45:49.016103 Closing test_set panfrost_gem_new
6743 14:45:49.051467 <8>[ 11.637783] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
6744 14:45:49.052293 Received signal: <TESTSET> START panfrost_get_param
6745 14:45:49.052658 Starting test_set panfrost_get_param
6746 14:45:49.086787 <6>[ 11.673453] Console: switching to colour dummy device 80x25
6747 14:45:49.093953 <14>[ 11.679825] [IGT] panfrost_get_param: executing
6748 14:45:49.100294 IGT-Version: 1.2<14>[ 11.685555] [IGT] panfrost_get_param: starting subtest base-params
6749 14:45:49.109783 8-ga44ebfe (aarc<14>[ 11.692809] [IGT] panfrost_get_param: finished subtest base-params, SUCCESS
6750 14:45:49.116471 h64) (Linux: 6.1<14>[ 11.701985] [IGT] panfrost_get_param: exiting, ret=0
6751 14:45:49.119813 .91-cip21 aarch64)
6752 14:45:49.123227 Using IGT_SRANDOM=1717512292 for randomisation
6753 14:45:49.126421 Opened device: /dev/dri/card0
6754 14:45:49.126838 Starting subtest: base-params
6755 14:45:49.132865 [1mSubtest base-params: SUCCESS (0.000s)[0m
6756 14:45:49.158170 <6>[ 11.728182] Console: switching to colour frame buffer device 170x48
6757 14:45:49.172091 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=pass
6759 14:45:49.174927 <8>[ 11.758545] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=pass>
6760 14:45:49.208401 <6>[ 11.794675] Console: switching to colour dummy device 80x25
6761 14:45:49.215146 <14>[ 11.800803] [IGT] panfrost_get_param: executing
6762 14:45:49.221322 IGT-Version: 1.2<14>[ 11.806666] [IGT] panfrost_get_param: starting subtest get-bad-param
6763 14:45:49.231259 8-ga44ebfe (aarc<14>[ 11.814235] [IGT] panfrost_get_param: finished subtest get-bad-param, SUCCESS
6764 14:45:49.238462 h64) (Linux: 6.1<14>[ 11.823466] [IGT] panfrost_get_param: exiting, ret=0
6765 14:45:49.241672 .91-cip21 aarch64)
6766 14:45:49.244512 Using IGT_SRANDOM=1717512292 for randomisation
6767 14:45:49.248269 Opened device: /dev/dri/card0
6768 14:45:49.251336 Starting subtest: get-bad-param
6769 14:45:49.254630 [1mSubtest get-bad-param: SUCCESS (0.000s)[0m
6770 14:45:49.293963 <6>[ 11.861371] Console: switching to colour frame buffer device 170x48
6771 14:45:49.310274 <8>[ 11.893429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=pass>
6772 14:45:49.311070 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=pass
6774 14:45:49.330559 <6>[ 11.917434] Console: switching to colour dummy device 80x25
6775 14:45:49.337689 <14>[ 11.923588] [IGT] panfrost_get_param: executing
6776 14:45:49.344135 IGT-Version: 1.2<14>[ 11.928788] [IGT] panfrost_get_param: starting subtest get-bad-padding
6777 14:45:49.354267 <14>[ 11.936908] [IGT] panfrost_get_param: finished subtest get-bad-padding, SUCCESS
6778 14:45:49.360486 8-ga44ebfe (aarc<14>[ 11.944917] [IGT] panfrost_get_param: exiting, ret=0
6779 14:45:49.363461 h64) (Linux: 6.1.91-cip21 aarch64)
6780 14:45:49.366919 Using IGT_SRANDOM=1717512292 for randomisation
6781 14:45:49.370290 Opened device: /dev/dri/card0
6782 14:45:49.374072 Starting subtest: get-bad-padding
6783 14:45:49.377070 [1mSubtest get-bad-padding: SUCCESS (0.000s)[0m
6784 14:45:49.407278 <6>[ 11.977600] Console: switching to colour frame buffer device 170x48
6785 14:45:49.425960 <8>[ 12.009502] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=pass>
6786 14:45:49.426753 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=pass
6788 14:45:49.432889 <8>[ 12.019675] <LAVA_SIGNAL_TESTSET STOP>
6789 14:45:49.433693 Received signal: <TESTSET> STOP
6790 14:45:49.434143 Closing test_set panfrost_get_param
6791 14:45:49.459022 <8>[ 12.046102] <LAVA_SIGNAL_TESTSET START panfrost_prime>
6792 14:45:49.459540 Received signal: <TESTSET> START panfrost_prime
6793 14:45:49.459790 Starting test_set panfrost_prime
6794 14:45:49.493377 <6>[ 12.080335] Console: switching to colour dummy device 80x25
6795 14:45:49.499878 <14>[ 12.086305] [IGT] panfrost_prime: executing
6796 14:45:49.506747 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
6797 14:45:49.510263 Using IGT_SRANDOM=1717512292 for randomisation
6798 14:45:49.513666 Opened device: /dev/dri/card0
6799 14:45:49.521965 <14>[ 12.108735] [IGT] panfrost_prime: starting subtest gem-prime-import
6800 14:45:49.525434 Starting subtest: gem-prime-import
6801 14:45:49.542072 (panfrost_prime:352) CRITICAL: Test assertion failure function igt_has_dumb,<14>[ 12.123918] [IGT] panfrost_prime: finished subtest gem-prime-import, FAIL
6802 14:45:49.548423 file ../tests/p<14>[ 12.133022] [IGT] panfrost_prime: exiting, ret=98
6803 14:45:49.548839 anfrost_prime.c:44:
6804 14:45:49.558554 (panfrost_prime:352) CRITICAL: Failed assertion: ret == 0 || errno == EINVAL || errno == EOPNOTSUPP
6805 14:45:49.565571 (panfrost_prime:352) CRITICAL: Last errno: 9, Bad file descriptor
6806 14:45:49.566094 Stack trace:
6807 14:45:49.568488 #0 ../lib/igt_core.c:1989 __igt_fail_assert()
6808 14:45:49.571743 #1 [<unknown>+0xd6d91358]
6809 14:45:49.575760 #2 [<unknown>+0xd6d90f2c]
6810 14:45:49.578581 #3 [__libc_init_first+0x80]
6811 14:45:49.581623 #4 [__libc_start_main+0x98]
6812 14:45:49.582040 #5 [<unknown>+0xd6d90f70]
6813 14:45:49.585200 Subtest gem-prime-import failed.
6814 14:45:49.595257 **** DEBUG **<6>[ 12.161133] Console: switching to colour frame buffer device 170x48
6815 14:45:49.595886 **
6816 14:45:49.611937 (panfrost_prime:352) CRITICAL: Test assertion failure function igt_has_dumb, file ../tests/panfrost_prime.c:<8>[ 12.194122] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=fail>
6817 14:45:49.612473 44:
6818 14:45:49.613087 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=fail
6820 14:45:49.618794 (panfrost_prime:352) CRITIC<8>[ 12.204913] <LAVA_SIGNAL_TESTSET STOP>
6821 14:45:49.619655 Received signal: <TESTSET> STOP
6822 14:45:49.620047 Closing test_set panfrost_prime
6823 14:45:49.624736 AL: Failed assertion: ret == 0 || errno == EINVAL || errno == EOPNOTSUPP
6824 14:45:49.631508 (panfrost_prime:352) CRITICAL: Last errno: 9, Bad file descriptor
6825 14:45:49.634928 (panfrost_prime:352) igt_core-INFO: Stack trace:
6826 14:45:49.641733 (panfrost_prime:352) igt_core-INFO: #0 ../lib/igt_core.c:1989 __igt_fail_assert()
6827 14:45:49.648113 (panfrost_prime:352) igt_core-INFO: #1 [<unknown>+0xd6d91358]
6828 14:45:49.657974 (panfrost_prime:352) igt_core-INFO: #2 [<unknown>+0xd6d90<8>[ 12.244587] <LAVA_SIGNAL_TESTSET START panfrost_submit>
6829 14:45:49.658536 f2c]
6830 14:45:49.659140 Received signal: <TESTSET> START panfrost_submit
6831 14:45:49.659516 Starting test_set panfrost_submit
6832 14:45:49.664651 (panfrost_prime:352) igt_core-INFO: #3 [__libc_init_first+0x80]
6833 14:45:49.671253 (panfrost_prime:352) igt_core-INFO: #4 [__libc_start_main+0x98]
6834 14:45:49.681404 (panfrost_prime:352) igt_core-INFO: #5 [<unknown>+<6>[ 12.266889] Console: switching to colour dummy device 80x25
6835 14:45:49.684991 0xd6d90f70]
6836 14:45:49.687841 ***<14>[ 12.274084] [IGT] panfrost_submit: executing
6837 14:45:49.688436 * END ****
6838 14:45:49.694446 [<14>[ 12.280320] [IGT] panfrost_submit: starting subtest pan-submit
6839 14:45:49.704657 1mSubtest gem-pr<14>[ 12.288570] [IGT] panfrost_submit: finished subtest pan-submit, SUCCESS
6840 14:45:49.711170 ime-import: FAIL<14>[ 12.296114] [IGT] panfrost_submit: exiting, ret=0
6841 14:45:49.711661 (0.008s)[0m
6842 14:45:49.721017 (panfrost_prime:352) drmtest-WARNING: Don't attempt to close standard/invalid file descriptor: -1
6843 14:45:49.727743 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
6844 14:45:49.730706 Using IGT_SRANDOM=1717512292 for randomisation
6845 14:45:49.734468 Opened device: /dev/dri/card0
6846 14:45:49.737946 Starting subtest: pan-submit
6847 14:45:49.740778 [1mSubtest pan-submit: SUCCESS (0.001s)[0m
6848 14:45:49.756880 <6>[ 12.326485] Console: switching to colour frame buffer device 170x48
6849 14:45:49.770241 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=pass
6851 14:45:49.772963 <8>[ 12.356669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=pass>
6852 14:45:49.793611 <6>[ 12.380472] Console: switching to colour dummy device 80x25
6853 14:45:49.800919 <14>[ 12.386746] [IGT] panfrost_submit: executing
6854 14:45:49.810325 IGT-Version: 1.2<14>[ 12.392068] [IGT] panfrost_submit: starting subtest pan-submit-error-no-jc
6855 14:45:49.816767 8-ga44ebfe (aarc<14>[ 12.400877] [IGT] panfrost_submit: finished subtest pan-submit-error-no-jc, SUCCESS
6856 14:45:49.823658 h64) (Linux: 6.1<14>[ 12.410557] [IGT] panfrost_submit: exiting, ret=0
6857 14:45:49.827104 .91-cip21 aarch64)
6858 14:45:49.829988 Using IGT_SRANDOM=1717512292 for randomisation
6859 14:45:49.834047 Opened device: /dev/dri/card0
6860 14:45:49.836554 Starting subtest: pan-submit-error-no-jc
6861 14:45:49.843706 [1mSubtest pan-submit-error-no-jc: SUCCESS (0.000s)[0m
6862 14:45:49.873270 <6>[ 12.443222] Console: switching to colour frame buffer device 170x48
6863 14:45:49.889338 <8>[ 12.472893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=pass>
6864 14:45:49.890297 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=pass
6866 14:45:49.910600 <6>[ 12.497385] Console: switching to colour dummy device 80x25
6867 14:45:49.917057 <14>[ 12.503353] [IGT] panfrost_submit: executing
6868 14:45:49.927433 IGT-Version: 1.2<14>[ 12.508292] [IGT] panfrost_submit: starting subtest pan-submit-error-bad-in-syncs
6869 14:45:49.937349 8-ga44ebfe (aarc<14>[ 12.517648] [IGT] panfrost_submit: finished subtest pan-submit-error-bad-in-syncs, SUCCESS
6870 14:45:49.944343 h64) (Linux: 6.1<14>[ 12.527839] [IGT] panfrost_submit: exiting, ret=0
6871 14:45:49.944870 .91-cip21 aarch64)
6872 14:45:49.947158 Using IGT_SRANDOM=1717512293 for randomisation
6873 14:45:49.950340 Opened device: /dev/dri/card0
6874 14:45:49.957048 Starting subtest: pan-submit-error-bad-in-syncs
6875 14:45:49.960112 [1mSubtest pan-submit-error-bad-in-syncs: SUCCESS (0.000s)[0m
6876 14:45:49.989589 <6>[ 12.559225] Console: switching to colour frame buffer device 170x48
6877 14:45:50.005031 <8>[ 12.588729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=pass>
6878 14:45:50.005835 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=pass
6880 14:45:50.038724 <6>[ 12.624971] Console: switching to colour dummy device 80x25
6881 14:45:50.045039 <14>[ 12.631076] [IGT] panfrost_submit: executing
6882 14:45:50.054858 IGT-Version: 1.2<14>[ 12.636795] [IGT] panfrost_submit: starting subtest pan-submit-error-bad-bo-handles
6883 14:45:50.064697 8-ga44ebfe (aarc<14>[ 12.646551] [IGT] panfrost_submit: finished subtest pan-submit-error-bad-bo-handles, SUCCESS
6884 14:45:50.071693 h64) (Linux: 6.1<14>[ 12.656980] [IGT] panfrost_submit: exiting, ret=0
6885 14:45:50.072225 .91-cip21 aarch64)
6886 14:45:50.078256 Using IGT_SRANDOM=1717512293 for randomisation
6887 14:45:50.078785 Opened device: /dev/dri/card0
6888 14:45:50.084900 Starting subtest: pan-submit-error-bad-bo-handles
6889 14:45:50.091962 [1mSubtest pan-submit-error-bad-bo-handles: SUCCESS (0.000s)[0m
6890 14:45:50.122580 <6>[ 12.692533] Console: switching to colour frame buffer device 170x48
6891 14:45:50.141457 <8>[ 12.724938] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=pass>
6892 14:45:50.142292 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=pass
6894 14:45:50.175803 <6>[ 12.762278] Console: switching to colour dummy device 80x25
6895 14:45:50.182558 <14>[ 12.768233] [IGT] panfrost_submit: executing
6896 14:45:50.192240 IGT-Version: 1.2<14>[ 12.773846] [IGT] panfrost_submit: starting subtest pan-submit-error-bad-requirements
6897 14:45:50.202646 8-ga44ebfe (aarc<14>[ 12.782822] [IGT] panfrost_submit: finished subtest pan-submit-error-bad-requirements, SUCCESS
6898 14:45:50.209402 h64) (Linux: 6.1<14>[ 12.793339] [IGT] panfrost_submit: exiting, ret=0
6899 14:45:50.209937 .91-cip21 aarch64)
6900 14:45:50.212047 Using IGT_SRANDOM=1717512293 for randomisation
6901 14:45:50.215835 Opened device: /dev/dri/card0
6902 14:45:50.222263 Starting subtest: pan-submit-error-bad-requirements
6903 14:45:50.228510 [1mSubtest pan-submit-error-bad-requirements: SUCCESS (0.000s)[0m
6904 14:45:50.255061 <6>[ 12.825337] Console: switching to colour frame buffer device 170x48
6905 14:45:50.273251 <8>[ 12.856694] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=pass>
6906 14:45:50.274081 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=pass
6908 14:45:50.307368 <6>[ 12.893954] Console: switching to colour dummy device 80x25
6909 14:45:50.314068 <14>[ 12.899914] [IGT] panfrost_submit: executing
6910 14:45:50.320620 IGT-Version: 1.2<14>[ 12.905329] [IGT] panfrost_submit: starting subtest pan-submit-error-bad-out-sync
6911 14:45:50.330392 8-ga44ebfe (aarc<14>[ 12.914524] [IGT] panfrost_submit: finished subtest pan-submit-error-bad-out-sync, SUCCESS
6912 14:45:50.337429 h64) (Linux: 6.1<14>[ 12.924424] [IGT] panfrost_submit: exiting, ret=0
6913 14:45:50.340668 .91-cip21 aarch64)
6914 14:45:50.343996 Using IGT_SRANDOM=1717512293 for randomisation
6915 14:45:50.347473 Opened device: /dev/dri/card0
6916 14:45:50.350684 Starting subtest: pan-submit-error-bad-out-sync
6917 14:45:50.357340 [1mSubtest pan-submit-error-bad-out-sync: SUCCESS (0.000s)[0m
6918 14:45:50.390857 <6>[ 12.958598] Console: switching to colour frame buffer device 170x48
6919 14:45:50.410399 <8>[ 12.993637] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=pass>
6920 14:45:50.411214 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=pass
6922 14:45:50.431708 <6>[ 13.018684] Console: switching to colour dummy device 80x25
6923 14:45:50.439192 <14>[ 13.024833] [IGT] panfrost_submit: executing
6924 14:45:50.445449 IGT-Version: 1.2<14>[ 13.029776] [IGT] panfrost_submit: starting subtest pan-reset
6925 14:45:50.448985 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
6926 14:45:50.455954 Using IGT_SRANDOM=1717512293 for randomisation
6927 14:45:50.458415 Opened device: /dev/dri/card0
6928 14:45:50.458840 Starting subtest: pan-reset
6929 14:45:50.966695 <3>[ 13.546954] panfrost 13040000.gpu: gpu sched timeout, js=1, config=0x7300, status=0x8, head=0x2000000, tail=0x2000040, sched_job=000000004b7d7403
6930 14:45:50.982415 [1mSubtest pan-<14>[ 13.565565] [IGT] panfrost_submit: finished subtest pan-reset, SUCCESS
6931 14:45:50.988789 reset: SUCCESS (<14>[ 13.573903] [IGT] panfrost_submit: exiting, ret=0
6932 14:45:50.989326 0.528s)[0m
6933 14:45:51.042084 <6>[ 13.611573] Console: switching to colour frame buffer device 170x48
6934 14:45:51.057417 <8>[ 13.643807] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=pass>
6935 14:45:51.058277 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=pass
6937 14:45:51.082041 <6>[ 13.668669] Console: switching to colour dummy device 80x25
6938 14:45:51.088636 <14>[ 13.674618] [IGT] panfrost_submit: executing
6939 14:45:51.095519 IGT-Version: 1.2<14>[ 13.679754] [IGT] panfrost_submit: starting subtest pan-submit-and-close
6940 14:45:51.105486 8-ga44ebfe (aarc<14>[ 13.688712] [IGT] panfrost_submit: finished subtest pan-submit-and-close, SUCCESS
6941 14:45:51.112188 <14>[ 13.697460] [IGT] panfrost_submit: exiting, ret=0
6942 14:45:51.115544 h64) (Linux: 6.1.91-cip21 aarch64)
6943 14:45:51.118703 Using IGT_SRANDOM=1717512294 for randomisation
6944 14:45:51.122143 Opened device: /dev/dri/card0
6945 14:45:51.125635 Starting subtest: pan-submit-and-close
6946 14:45:51.128762 [1mSubtest pan-submit-and-close: SUCCESS (0.001s)[0m
6947 14:45:51.153114 <6>[ 13.722985] Console: switching to colour frame buffer device 170x48
6948 14:45:51.168900 <8>[ 13.752385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=pass>
6949 14:45:51.169754 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=pass
6951 14:45:51.191552 <6>[ 13.778333] Console: switching to colour dummy device 80x25
6952 14:45:51.198252 <14>[ 13.784584] [IGT] panfrost_submit: executing
6953 14:45:51.207899 IGT-Version: 1.2<14>[ 13.789751] [IGT] panfrost_submit: starting subtest pan-unhandled-pagefault
6954 14:45:51.211340 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
6955 14:45:51.215213 Using IGT_SRANDOM=1717512294 for randomisation
6956 14:45:51.218461 Opened device: /dev/dri/card0
6957 14:45:51.221509 Starting subtest: pan-unhandled-pagefault
6958 14:45:51.326619 (panfrost_submit:384) CRITICAL: Test assertion failure function __igt_unique____real_main65, fil<14>[ 13.910414] [IGT] panfrost_submit: finished subtest pan-unhandled-pagefault, FAIL
6959 14:45:51.333493 e ../tests/panfr<14>[ 13.919208] [IGT] panfrost_submit: exiting, ret=98
6960 14:45:51.336477 ost_submit.c:178:
6961 14:45:51.349263 (panfrost_submit:384) CRITICAL: Failed assertion: syncobj_wait(fd, &submit->args->out_sync, 1, abs_timeout(SHORT_TIME_NSEC), 0, NULL)
6962 14:45:51.349782 Stack trace:
6963 14:45:51.352819 #0 ../lib/igt_core.c:1989 __igt_fail_assert()
6964 14:45:51.356191 #1 [<unknown>+0xdb001980]
6965 14:45:51.359521 #2 [<unknown>+0xdb000dec]
6966 14:45:51.362540 #3 [__libc_init_first+0x80]
6967 14:45:51.366002 #4 [__libc_start_main+0x98]
6968 14:45:51.366535 #5 [<unknown>+0xdb000e30]
6969 14:45:51.369269 Subtest pan-unhandled-pagefault failed.
6970 14:45:51.372401 **** DEBUG ****
6971 14:45:51.382667 (panfrost_submit:384) CRITICAL: Test assertion failure function __igt_unique____real_main65, file ../tests/panfrost_submit.c:178:
6972 14:45:51.392680 (panf<6>[ 13.956175] Console: switching to colour frame buffer device 170x48
6973 14:45:51.405669 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=fail
6975 14:45:51.408964 rost_submit:384) CRITICAL: Failed assertion: syncobj_wait(fd, &submit->args->out_sync, 1, abs_ti<8>[ 13.990347] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=fail>
6976 14:45:51.415972 meout(SHORT_TIME_NSEC), 0, NULL)<8>[ 14.001384] <LAVA_SIGNAL_TESTSET STOP>
6977 14:45:51.416495
6978 14:45:51.417097 Received signal: <TESTSET> STOP
6979 14:45:51.417437 Closing test_set panfrost_submit
6980 14:45:51.422010 (panfrost_subm<8>[ 14.007120] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 14166985_1.5.2.3.1>
6981 14:45:51.422690 Received signal: <ENDRUN> 0_igt-gpu-panfrost 14166985_1.5.2.3.1
6982 14:45:51.423082 Ending use of test pattern.
6983 14:45:51.423401 Ending test lava.0_igt-gpu-panfrost (14166985_1.5.2.3.1), duration 2.79
6985 14:45:51.425362 it:384) igt_core-INFO: Stack trace:
6986 14:45:51.432290 (panfrost_submit:384) igt_core-INFO: #0 ../lib/igt_core.c:1989 __igt_fail_assert()
6987 14:45:51.439148 (panfrost_submit:384) igt_core-INFO: #1 [<unknown>+0xdb001980]
6988 14:45:51.445639 (panfrost_submit:384) igt_core-INFO: #2 [<unknown>+0xdb000dec]
6989 14:45:51.452314 (panfrost_submit:384) igt_core-INFO: #3 [__libc_init_first+0x80]
6990 14:45:51.458420 (panfrost_submit:384) igt_core-INFO: #4 [__libc_start_main+0x98]
6991 14:45:51.465455 (panfrost_submit:384) igt_core-INFO: #5 [<unknown>+0xdb000e30]
6992 14:45:51.465980 **** END ****
6993 14:45:51.472051 [1mSubtest pan-unhandled-pagefault: FAIL (0.112s)[0m
6994 14:45:51.472479 + set +x
6995 14:45:51.475476 <LAVA_TEST_RUNNER EXIT>
6996 14:45:51.476314 ok: lava_test_shell seems to have completed
6997 14:45:51.478051 base-params:
result: pass
set: panfrost_get_param
gem-new-0:
result: pass
set: panfrost_gem_new
gem-new-4096:
result: pass
set: panfrost_gem_new
gem-new-zeroed:
result: pass
set: panfrost_gem_new
gem-prime-import:
result: fail
set: panfrost_prime
get-bad-padding:
result: pass
set: panfrost_get_param
get-bad-param:
result: pass
set: panfrost_get_param
pan-reset:
result: pass
set: panfrost_submit
pan-submit:
result: pass
set: panfrost_submit
pan-submit-and-close:
result: pass
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: pass
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: pass
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: pass
set: panfrost_submit
pan-submit-error-bad-requirements:
result: pass
set: panfrost_submit
pan-submit-error-no-jc:
result: pass
set: panfrost_submit
pan-unhandled-pagefault:
result: fail
set: panfrost_submit
6998 14:45:51.478611 end: 3.1 lava-test-shell (duration 00:00:03) [common]
6999 14:45:51.479065 end: 3 lava-test-retry (duration 00:00:03) [common]
7000 14:45:51.479685 start: 4 finalize (timeout 00:07:57) [common]
7001 14:45:51.480154 start: 4.1 power-off (timeout 00:00:30) [common]
7002 14:45:51.480997 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-0', '--port=1', '--command=off']
7003 14:45:52.760192 >> Command sent successfully.
7004 14:45:52.770521 Returned 0 in 1 seconds
7005 14:45:52.871779 end: 4.1 power-off (duration 00:00:01) [common]
7007 14:45:52.873264 start: 4.2 read-feedback (timeout 00:07:55) [common]
7008 14:45:52.874595 Listened to connection for namespace 'common' for up to 1s
7010 14:45:52.876153 Listened to connection for namespace 'common' for up to 1s
7011 14:45:53.875286 Finalising connection for namespace 'common'
7012 14:45:53.875986 Disconnecting from shell: Finalise
7013 14:45:53.976968 end: 4.2 read-feedback (duration 00:00:01) [common]
7014 14:45:53.977617 end: 4 finalize (duration 00:00:02) [common]
7015 14:45:53.978180 Cleaning after the job
7016 14:45:53.978648 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166985/tftp-deploy-pirxnrnz/ramdisk
7017 14:45:54.005169 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166985/tftp-deploy-pirxnrnz/kernel
7018 14:45:54.030454 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166985/tftp-deploy-pirxnrnz/dtb
7019 14:45:54.030727 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166985/tftp-deploy-pirxnrnz/modules
7020 14:45:54.036981 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14166985
7021 14:45:54.152742 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14166985
7022 14:45:54.152937 Job finished correctly