Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 29
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 22
1 14:46:03.457683 lava-dispatcher, installed at version: 2024.03
2 14:46:03.457885 start: 0 validate
3 14:46:03.458018 Start time: 2024-06-04 14:46:03.458011+00:00 (UTC)
4 14:46:03.458148 Using caching service: 'http://localhost/cache/?uri=%s'
5 14:46:03.458280 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 14:46:03.718761 Using caching service: 'http://localhost/cache/?uri=%s'
7 14:46:03.718992 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 14:46:03.978446 Using caching service: 'http://localhost/cache/?uri=%s'
9 14:46:03.978674 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 14:46:04.238931 Using caching service: 'http://localhost/cache/?uri=%s'
11 14:46:04.239135 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 14:46:04.499764 validate duration: 1.04
14 14:46:04.500178 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 14:46:04.500417 start: 1.1 download-retry (timeout 00:10:00) [common]
16 14:46:04.500587 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 14:46:04.500794 Not decompressing ramdisk as can be used compressed.
18 14:46:04.500914 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 14:46:04.501012 saving as /var/lib/lava/dispatcher/tmp/14167035/tftp-deploy-3rgjmpmz/ramdisk/rootfs.cpio.gz
20 14:46:04.501129 total size: 47897469 (45 MB)
21 14:46:04.507270 progress 0 % (0 MB)
22 14:46:04.520427 progress 5 % (2 MB)
23 14:46:04.533219 progress 10 % (4 MB)
24 14:46:04.546197 progress 15 % (6 MB)
25 14:46:04.559020 progress 20 % (9 MB)
26 14:46:04.571728 progress 25 % (11 MB)
27 14:46:04.584438 progress 30 % (13 MB)
28 14:46:04.597620 progress 35 % (16 MB)
29 14:46:04.611293 progress 40 % (18 MB)
30 14:46:04.625059 progress 45 % (20 MB)
31 14:46:04.638693 progress 50 % (22 MB)
32 14:46:04.652330 progress 55 % (25 MB)
33 14:46:04.665470 progress 60 % (27 MB)
34 14:46:04.678390 progress 65 % (29 MB)
35 14:46:04.691142 progress 70 % (32 MB)
36 14:46:04.703804 progress 75 % (34 MB)
37 14:46:04.716618 progress 80 % (36 MB)
38 14:46:04.729874 progress 85 % (38 MB)
39 14:46:04.742545 progress 90 % (41 MB)
40 14:46:04.754999 progress 95 % (43 MB)
41 14:46:04.767546 progress 100 % (45 MB)
42 14:46:04.767781 45 MB downloaded in 0.27 s (171.30 MB/s)
43 14:46:04.767952 end: 1.1.1 http-download (duration 00:00:00) [common]
45 14:46:04.768306 end: 1.1 download-retry (duration 00:00:00) [common]
46 14:46:04.768423 start: 1.2 download-retry (timeout 00:10:00) [common]
47 14:46:04.768535 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 14:46:04.768698 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 14:46:04.768799 saving as /var/lib/lava/dispatcher/tmp/14167035/tftp-deploy-3rgjmpmz/kernel/Image
50 14:46:04.768888 total size: 54682112 (52 MB)
51 14:46:04.768979 No compression specified
52 14:46:04.770268 progress 0 % (0 MB)
53 14:46:04.784774 progress 5 % (2 MB)
54 14:46:04.799303 progress 10 % (5 MB)
55 14:46:04.813880 progress 15 % (7 MB)
56 14:46:04.828606 progress 20 % (10 MB)
57 14:46:04.844603 progress 25 % (13 MB)
58 14:46:04.860308 progress 30 % (15 MB)
59 14:46:04.875635 progress 35 % (18 MB)
60 14:46:04.891268 progress 40 % (20 MB)
61 14:46:04.907062 progress 45 % (23 MB)
62 14:46:04.923113 progress 50 % (26 MB)
63 14:46:04.939495 progress 55 % (28 MB)
64 14:46:04.955940 progress 60 % (31 MB)
65 14:46:04.971775 progress 65 % (33 MB)
66 14:46:04.988069 progress 70 % (36 MB)
67 14:46:05.003901 progress 75 % (39 MB)
68 14:46:05.020201 progress 80 % (41 MB)
69 14:46:05.036158 progress 85 % (44 MB)
70 14:46:05.051822 progress 90 % (46 MB)
71 14:46:05.067342 progress 95 % (49 MB)
72 14:46:05.082936 progress 100 % (52 MB)
73 14:46:05.083221 52 MB downloaded in 0.31 s (165.91 MB/s)
74 14:46:05.083432 end: 1.2.1 http-download (duration 00:00:00) [common]
76 14:46:05.083837 end: 1.2 download-retry (duration 00:00:00) [common]
77 14:46:05.083953 start: 1.3 download-retry (timeout 00:09:59) [common]
78 14:46:05.084081 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 14:46:05.084247 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 14:46:05.084347 saving as /var/lib/lava/dispatcher/tmp/14167035/tftp-deploy-3rgjmpmz/dtb/mt8192-asurada-spherion-r0.dtb
81 14:46:05.084438 total size: 47258 (0 MB)
82 14:46:05.084499 No compression specified
83 14:46:05.086047 progress 69 % (0 MB)
84 14:46:05.086374 progress 100 % (0 MB)
85 14:46:05.086571 0 MB downloaded in 0.00 s (21.15 MB/s)
86 14:46:05.086750 end: 1.3.1 http-download (duration 00:00:00) [common]
88 14:46:05.087125 end: 1.3 download-retry (duration 00:00:00) [common]
89 14:46:05.087239 start: 1.4 download-retry (timeout 00:09:59) [common]
90 14:46:05.087357 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 14:46:05.087509 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 14:46:05.087674 saving as /var/lib/lava/dispatcher/tmp/14167035/tftp-deploy-3rgjmpmz/modules/modules.tar
93 14:46:05.087779 total size: 8608920 (8 MB)
94 14:46:05.087889 Using unxz to decompress xz
95 14:46:05.092590 progress 0 % (0 MB)
96 14:46:05.112239 progress 5 % (0 MB)
97 14:46:05.140648 progress 10 % (0 MB)
98 14:46:05.171437 progress 15 % (1 MB)
99 14:46:05.195754 progress 20 % (1 MB)
100 14:46:05.220423 progress 25 % (2 MB)
101 14:46:05.245019 progress 30 % (2 MB)
102 14:46:05.269756 progress 35 % (2 MB)
103 14:46:05.296755 progress 40 % (3 MB)
104 14:46:05.320326 progress 45 % (3 MB)
105 14:46:05.345614 progress 50 % (4 MB)
106 14:46:05.371457 progress 55 % (4 MB)
107 14:46:05.396337 progress 60 % (4 MB)
108 14:46:05.421821 progress 65 % (5 MB)
109 14:46:05.447708 progress 70 % (5 MB)
110 14:46:05.474289 progress 75 % (6 MB)
111 14:46:05.501015 progress 80 % (6 MB)
112 14:46:05.527153 progress 85 % (7 MB)
113 14:46:05.554105 progress 90 % (7 MB)
114 14:46:05.580022 progress 95 % (7 MB)
115 14:46:05.605674 progress 100 % (8 MB)
116 14:46:05.611440 8 MB downloaded in 0.52 s (15.68 MB/s)
117 14:46:05.611688 end: 1.4.1 http-download (duration 00:00:01) [common]
119 14:46:05.611959 end: 1.4 download-retry (duration 00:00:01) [common]
120 14:46:05.612061 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 14:46:05.612209 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 14:46:05.612299 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 14:46:05.612397 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 14:46:05.612633 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp
125 14:46:05.612771 makedir: /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/bin
126 14:46:05.612877 makedir: /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/tests
127 14:46:05.612982 makedir: /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/results
128 14:46:05.613119 Creating /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/bin/lava-add-keys
129 14:46:05.613297 Creating /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/bin/lava-add-sources
130 14:46:05.613441 Creating /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/bin/lava-background-process-start
131 14:46:05.613581 Creating /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/bin/lava-background-process-stop
132 14:46:05.613712 Creating /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/bin/lava-common-functions
133 14:46:05.613839 Creating /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/bin/lava-echo-ipv4
134 14:46:05.613968 Creating /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/bin/lava-install-packages
135 14:46:05.614097 Creating /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/bin/lava-installed-packages
136 14:46:05.614257 Creating /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/bin/lava-os-build
137 14:46:05.614399 Creating /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/bin/lava-probe-channel
138 14:46:05.614533 Creating /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/bin/lava-probe-ip
139 14:46:05.614655 Creating /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/bin/lava-target-ip
140 14:46:05.614784 Creating /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/bin/lava-target-mac
141 14:46:05.614919 Creating /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/bin/lava-target-storage
142 14:46:05.615091 Creating /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/bin/lava-test-case
143 14:46:05.615213 Creating /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/bin/lava-test-event
144 14:46:05.615340 Creating /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/bin/lava-test-feedback
145 14:46:05.615469 Creating /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/bin/lava-test-raise
146 14:46:05.615589 Creating /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/bin/lava-test-reference
147 14:46:05.615719 Creating /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/bin/lava-test-runner
148 14:46:05.615851 Creating /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/bin/lava-test-set
149 14:46:05.615977 Creating /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/bin/lava-test-shell
150 14:46:05.616110 Updating /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/bin/lava-install-packages (oe)
151 14:46:05.616273 Updating /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/bin/lava-installed-packages (oe)
152 14:46:05.616397 Creating /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/environment
153 14:46:05.616495 LAVA metadata
154 14:46:05.616566 - LAVA_JOB_ID=14167035
155 14:46:05.616638 - LAVA_DISPATCHER_IP=192.168.201.1
156 14:46:05.616735 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 14:46:05.616814 skipped lava-vland-overlay
158 14:46:05.616888 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 14:46:05.616975 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 14:46:05.617049 skipped lava-multinode-overlay
161 14:46:05.617120 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 14:46:05.617212 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 14:46:05.617322 Loading test definitions
164 14:46:05.617421 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 14:46:05.617494 Using /lava-14167035 at stage 0
166 14:46:05.617824 uuid=14167035_1.5.2.3.1 testdef=None
167 14:46:05.617911 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 14:46:05.618008 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 14:46:05.618561 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 14:46:05.618790 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 14:46:05.619426 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 14:46:05.619669 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 14:46:05.620356 runner path: /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/0/tests/0_igt-gpu-panfrost test_uuid 14167035_1.5.2.3.1
176 14:46:05.620556 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 14:46:05.620904 Creating lava-test-runner.conf files
179 14:46:05.620994 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14167035/lava-overlay-okme3ogp/lava-14167035/0 for stage 0
180 14:46:05.621119 - 0_igt-gpu-panfrost
181 14:46:05.621315 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 14:46:05.621409 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 14:46:05.628999 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 14:46:05.629112 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 14:46:05.629203 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 14:46:05.629331 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 14:46:05.629416 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 14:46:07.399314 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 14:46:07.399689 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 14:46:07.399848 extracting modules file /var/lib/lava/dispatcher/tmp/14167035/tftp-deploy-3rgjmpmz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14167035/extract-overlay-ramdisk-i4sy92i4/ramdisk
191 14:46:07.640560 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 14:46:07.640730 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 14:46:07.640833 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14167035/compress-overlay-edfm5rj3/overlay-1.5.2.4.tar.gz to ramdisk
194 14:46:07.640914 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14167035/compress-overlay-edfm5rj3/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14167035/extract-overlay-ramdisk-i4sy92i4/ramdisk
195 14:46:07.648072 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 14:46:07.648188 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 14:46:07.648284 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 14:46:07.648373 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 14:46:07.648457 Building ramdisk /var/lib/lava/dispatcher/tmp/14167035/extract-overlay-ramdisk-i4sy92i4/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14167035/extract-overlay-ramdisk-i4sy92i4/ramdisk
200 14:46:08.882143 >> 465919 blocks
201 14:46:15.197526 rename /var/lib/lava/dispatcher/tmp/14167035/extract-overlay-ramdisk-i4sy92i4/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14167035/tftp-deploy-3rgjmpmz/ramdisk/ramdisk.cpio.gz
202 14:46:15.197984 end: 1.5.7 compress-ramdisk (duration 00:00:08) [common]
203 14:46:15.198115 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 14:46:15.198215 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 14:46:15.198334 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14167035/tftp-deploy-3rgjmpmz/kernel/Image']
206 14:46:28.372009 Returned 0 in 13 seconds
207 14:46:28.472615 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14167035/tftp-deploy-3rgjmpmz/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14167035/tftp-deploy-3rgjmpmz/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14167035/tftp-deploy-3rgjmpmz/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14167035/tftp-deploy-3rgjmpmz/kernel/image.itb
208 14:46:29.341941 output: FIT description: Kernel Image image with one or more FDT blobs
209 14:46:29.342308 output: Created: Tue Jun 4 15:46:29 2024
210 14:46:29.342394 output: Image 0 (kernel-1)
211 14:46:29.342458 output: Description:
212 14:46:29.342526 output: Created: Tue Jun 4 15:46:29 2024
213 14:46:29.342587 output: Type: Kernel Image
214 14:46:29.342649 output: Compression: lzma compressed
215 14:46:29.342712 output: Data Size: 13060619 Bytes = 12754.51 KiB = 12.46 MiB
216 14:46:29.342776 output: Architecture: AArch64
217 14:46:29.342832 output: OS: Linux
218 14:46:29.342898 output: Load Address: 0x00000000
219 14:46:29.342956 output: Entry Point: 0x00000000
220 14:46:29.343012 output: Hash algo: crc32
221 14:46:29.343077 output: Hash value: 88dcd836
222 14:46:29.343140 output: Image 1 (fdt-1)
223 14:46:29.343194 output: Description: mt8192-asurada-spherion-r0
224 14:46:29.343251 output: Created: Tue Jun 4 15:46:29 2024
225 14:46:29.343324 output: Type: Flat Device Tree
226 14:46:29.343377 output: Compression: uncompressed
227 14:46:29.343429 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 14:46:29.343487 output: Architecture: AArch64
229 14:46:29.343540 output: Hash algo: crc32
230 14:46:29.343592 output: Hash value: 0f8e4d2e
231 14:46:29.343643 output: Image 2 (ramdisk-1)
232 14:46:29.343706 output: Description: unavailable
233 14:46:29.343759 output: Created: Tue Jun 4 15:46:29 2024
234 14:46:29.343811 output: Type: RAMDisk Image
235 14:46:29.343870 output: Compression: Unknown Compression
236 14:46:29.343923 output: Data Size: 60993907 Bytes = 59564.36 KiB = 58.17 MiB
237 14:46:29.343975 output: Architecture: AArch64
238 14:46:29.344026 output: OS: Linux
239 14:46:29.344085 output: Load Address: unavailable
240 14:46:29.344136 output: Entry Point: unavailable
241 14:46:29.344187 output: Hash algo: crc32
242 14:46:29.344244 output: Hash value: 625f83ca
243 14:46:29.344297 output: Default Configuration: 'conf-1'
244 14:46:29.344348 output: Configuration 0 (conf-1)
245 14:46:29.344400 output: Description: mt8192-asurada-spherion-r0
246 14:46:29.344458 output: Kernel: kernel-1
247 14:46:29.344511 output: Init Ramdisk: ramdisk-1
248 14:46:29.344562 output: FDT: fdt-1
249 14:46:29.344613 output: Loadables: kernel-1
250 14:46:29.344675 output:
251 14:46:29.344883 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 14:46:29.344976 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 14:46:29.345088 end: 1.5 prepare-tftp-overlay (duration 00:00:24) [common]
254 14:46:29.345178 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:35) [common]
255 14:46:29.345271 No LXC device requested
256 14:46:29.345398 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 14:46:29.345482 start: 1.7 deploy-device-env (timeout 00:09:35) [common]
258 14:46:29.345561 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 14:46:29.345634 Checking files for TFTP limit of 4294967296 bytes.
260 14:46:29.346144 end: 1 tftp-deploy (duration 00:00:25) [common]
261 14:46:29.346255 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 14:46:29.346347 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 14:46:29.346488 substitutions:
264 14:46:29.346563 - {DTB}: 14167035/tftp-deploy-3rgjmpmz/dtb/mt8192-asurada-spherion-r0.dtb
265 14:46:29.346628 - {INITRD}: 14167035/tftp-deploy-3rgjmpmz/ramdisk/ramdisk.cpio.gz
266 14:46:29.346707 - {KERNEL}: 14167035/tftp-deploy-3rgjmpmz/kernel/Image
267 14:46:29.346814 - {LAVA_MAC}: None
268 14:46:29.346902 - {PRESEED_CONFIG}: None
269 14:46:29.347000 - {PRESEED_LOCAL}: None
270 14:46:29.347090 - {RAMDISK}: 14167035/tftp-deploy-3rgjmpmz/ramdisk/ramdisk.cpio.gz
271 14:46:29.347164 - {ROOT_PART}: None
272 14:46:29.347222 - {ROOT}: None
273 14:46:29.347277 - {SERVER_IP}: 192.168.201.1
274 14:46:29.347340 - {TEE}: None
275 14:46:29.347393 Parsed boot commands:
276 14:46:29.347446 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 14:46:29.347628 Parsed boot commands: tftpboot 192.168.201.1 14167035/tftp-deploy-3rgjmpmz/kernel/image.itb 14167035/tftp-deploy-3rgjmpmz/kernel/cmdline
278 14:46:29.347730 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 14:46:29.347816 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 14:46:29.347913 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 14:46:29.348000 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 14:46:29.348073 Not connected, no need to disconnect.
283 14:46:29.348154 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 14:46:29.348230 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 14:46:29.348305 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
286 14:46:29.352049 Setting prompt string to ['lava-test: # ']
287 14:46:29.352422 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 14:46:29.352535 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 14:46:29.352638 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 14:46:29.352734 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 14:46:29.352946 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-2']
292 14:46:43.280671 Returned 0 in 13 seconds
293 14:46:43.381371 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 14:46:43.381995 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 14:46:43.382095 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 14:46:43.382198 Setting prompt string to 'Starting depthcharge on Spherion...'
298 14:46:43.382296 Changing prompt to 'Starting depthcharge on Spherion...'
299 14:46:43.382398 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 14:46:43.383031 [Enter `^Ec?' for help]
301 14:46:43.383175
302 14:46:43.383293
303 14:46:43.383404 F0: 102B 0000
304 14:46:43.383500
305 14:46:43.383593 F3: 1001 0000 [0200]
306 14:46:43.383678
307 14:46:43.383753 F3: 1001 0000
308 14:46:43.383819
309 14:46:43.383875 F7: 102D 0000
310 14:46:43.383938
311 14:46:43.383992 F1: 0000 0000
312 14:46:43.384046
313 14:46:43.384098 V0: 0000 0000 [0001]
314 14:46:43.384163
315 14:46:43.384216 00: 0007 8000
316 14:46:43.384271
317 14:46:43.384334 01: 0000 0000
318 14:46:43.384388
319 14:46:43.384441 BP: 0C00 0209 [0000]
320 14:46:43.384499
321 14:46:43.384552 G0: 1182 0000
322 14:46:43.384604
323 14:46:43.384656 EC: 0000 0021 [4000]
324 14:46:43.384714
325 14:46:43.384767 S7: 0000 0000 [0000]
326 14:46:43.384819
327 14:46:43.384871 CC: 0000 0000 [0001]
328 14:46:43.384931
329 14:46:43.384983 T0: 0000 0040 [010F]
330 14:46:43.385036
331 14:46:43.385094 Jump to BL
332 14:46:43.385147
333 14:46:43.385199
334 14:46:43.385250
335 14:46:43.385350 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 14:46:43.385406 ARM64: Exception handlers installed.
337 14:46:43.385466 ARM64: Testing exception
338 14:46:43.385520 ARM64: Done test exception
339 14:46:43.385572 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 14:46:43.385648 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 14:46:43.385742 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 14:46:43.385801 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 14:46:43.385864 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 14:46:43.385918 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 14:46:43.385971 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 14:46:43.386024 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 14:46:43.386085 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 14:46:43.386138 WDT: Last reset was cold boot
349 14:46:43.386191 SPI1(PAD0) initialized at 2873684 Hz
350 14:46:43.386251 SPI5(PAD0) initialized at 992727 Hz
351 14:46:43.386304 VBOOT: Loading verstage.
352 14:46:43.386357 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 14:46:43.386416 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 14:46:43.386471 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 14:46:43.386524 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 14:46:43.386577 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 14:46:43.386637 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 14:46:43.386690 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
359 14:46:43.386743
360 14:46:43.386802
361 14:46:43.386855 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 14:46:43.386908 ARM64: Exception handlers installed.
363 14:46:43.386970 ARM64: Testing exception
364 14:46:43.387033 ARM64: Done test exception
365 14:46:43.387086 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 14:46:43.387138 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 14:46:43.387198 Probing TPM: . done!
368 14:46:43.387251 TPM ready after 0 ms
369 14:46:43.387303 Connected to device vid:did:rid of 1ae0:0028:00
370 14:46:43.387356 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
371 14:46:43.387417 Initialized TPM device CR50 revision 0
372 14:46:43.387470 tlcl_send_startup: Startup return code is 0
373 14:46:43.387522 TPM: setup succeeded
374 14:46:43.387585 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 14:46:43.387651 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 14:46:43.387797 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 14:46:43.387869 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 14:46:43.387951 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 14:46:43.388023 in-header: 03 07 00 00 08 00 00 00
380 14:46:43.388076 in-data: aa e4 47 04 13 02 00 00
381 14:46:43.388136 Chrome EC: UHEPI supported
382 14:46:43.388190 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 14:46:43.388243 in-header: 03 a9 00 00 08 00 00 00
384 14:46:43.388295 in-data: 84 60 60 08 00 00 00 00
385 14:46:43.388354 Phase 1
386 14:46:43.388407 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 14:46:43.388460 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 14:46:43.388522 VB2:vb2_check_recovery() Recovery was requested manually
389 14:46:43.388578 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 14:46:43.388630 Recovery requested (1009000e)
391 14:46:43.388683 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 14:46:43.388743 tlcl_extend: response is 0
393 14:46:43.388796 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 14:46:43.388849 tlcl_extend: response is 0
395 14:46:43.388900 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 14:46:43.388961 read SPI 0x210d4 0x2173b: 15140 us, 9050 KB/s, 72.400 Mbps
397 14:46:43.389014 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 14:46:43.389066
399 14:46:43.389125
400 14:46:43.389178 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 14:46:43.389232 ARM64: Exception handlers installed.
402 14:46:43.389334 ARM64: Testing exception
403 14:46:43.389387 ARM64: Done test exception
404 14:46:43.389440 pmic_efuse_setting: Set efuses in 11 msecs
405 14:46:43.389499 pmwrap_interface_init: Select PMIF_VLD_RDY
406 14:46:43.389552 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 14:46:43.389609 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 14:46:43.389872 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 14:46:43.389982 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 14:46:43.390096 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 14:46:43.390203 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 14:46:43.390315 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 14:46:43.390421 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 14:46:43.390522 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 14:46:43.390612 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 14:46:43.390702 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 14:46:43.390786 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 14:46:43.390876 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 14:46:43.390959 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 14:46:43.391052 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 14:46:43.391119 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 14:46:43.391172 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 14:46:43.391236 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 14:46:43.391290 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 14:46:43.391343 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 14:46:43.391395 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 14:46:43.391455 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 14:46:43.391508 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 14:46:43.391560 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 14:46:43.391629 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 14:46:43.391762 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 14:46:43.391898 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 14:46:43.391973 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 14:46:43.392041 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 14:46:43.392117 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 14:46:43.392214 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 14:46:43.392283 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 14:46:43.392346 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 14:46:43.392440 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 14:46:43.392523 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 14:46:43.392613 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 14:46:43.392697 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 14:46:43.392787 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 14:46:43.392873 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 14:46:43.392962 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 14:46:43.393045 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 14:46:43.393133 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 14:46:43.393251 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 14:46:43.393353 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 14:46:43.393452 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 14:46:43.393579 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 14:46:43.393668 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 14:46:43.393766 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 14:46:43.393849 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 14:46:43.393942 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 14:46:43.394025 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 14:46:43.394115 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 14:46:43.394201 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 14:46:43.394291 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 14:46:43.394376 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 14:46:43.394460 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 14:46:43.394549 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 14:46:43.394632 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 14:46:43.394721 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 14:46:43.394804 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x2f
466 14:46:43.394893 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 14:46:43.394976 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
468 14:46:43.395070 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 14:46:43.395154 [RTC]rtc_get_frequency_meter,154: input=15, output=852
470 14:46:43.395237 [RTC]rtc_get_frequency_meter,154: input=7, output=725
471 14:46:43.395329 [RTC]rtc_get_frequency_meter,154: input=11, output=789
472 14:46:43.395412 [RTC]rtc_get_frequency_meter,154: input=13, output=821
473 14:46:43.395501 [RTC]rtc_get_frequency_meter,154: input=12, output=804
474 14:46:43.395584 [RTC]rtc_get_frequency_meter,154: input=11, output=789
475 14:46:43.395674 [RTC]rtc_get_frequency_meter,154: input=12, output=804
476 14:46:43.395756 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
477 14:46:43.395845 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
478 14:46:43.396134 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 14:46:43.396236 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 14:46:43.396321 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 14:46:43.396413 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 14:46:43.396497 ADC[4]: Raw value=904802 ID=7
483 14:46:43.396579 ADC[3]: Raw value=213916 ID=1
484 14:46:43.396669 RAM Code: 0x71
485 14:46:43.396752 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 14:46:43.396844 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 14:46:43.396929 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 14:46:43.397024 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 14:46:43.397108 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 14:46:43.397198 in-header: 03 07 00 00 08 00 00 00
491 14:46:43.397302 in-data: aa e4 47 04 13 02 00 00
492 14:46:43.397380 Chrome EC: UHEPI supported
493 14:46:43.397433 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 14:46:43.397487 in-header: 03 a9 00 00 08 00 00 00
495 14:46:43.397540 in-data: 84 60 60 08 00 00 00 00
496 14:46:43.397599 MRC: failed to locate region type 0.
497 14:46:43.397653 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 14:46:43.397706 DRAM-K: Running full calibration
499 14:46:43.397768 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 14:46:43.397820 header.status = 0x0
501 14:46:43.397873 header.version = 0x6 (expected: 0x6)
502 14:46:43.397925 header.size = 0xd00 (expected: 0xd00)
503 14:46:43.397985 header.flags = 0x0
504 14:46:43.398037 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 14:46:43.398089 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
506 14:46:43.398150 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 14:46:43.398216 dram_init: ddr_geometry: 2
508 14:46:43.398272 [EMI] MDL number = 2
509 14:46:43.398331 [EMI] Get MDL freq = 0
510 14:46:43.398385 dram_init: ddr_type: 0
511 14:46:43.398438 is_discrete_lpddr4: 1
512 14:46:43.398512 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 14:46:43.398579
514 14:46:43.398633
515 14:46:43.398684 [Bian_co] ETT version 0.0.0.1
516 14:46:43.398744 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 14:46:43.398797
518 14:46:43.398850 dramc_set_vcore_voltage set vcore to 650000
519 14:46:43.398912 Read voltage for 800, 4
520 14:46:43.398967 Vio18 = 0
521 14:46:43.399019 Vcore = 650000
522 14:46:43.399079 Vdram = 0
523 14:46:43.399133 Vddq = 0
524 14:46:43.399185 Vmddr = 0
525 14:46:43.399237 dram_init: config_dvfs: 1
526 14:46:43.399295 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 14:46:43.399349 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 14:46:43.399402 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
529 14:46:43.399454 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
530 14:46:43.399515 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
531 14:46:43.399567 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
532 14:46:43.399619 MEM_TYPE=3, freq_sel=18
533 14:46:43.399678 sv_algorithm_assistance_LP4_1600
534 14:46:43.399731 ============ PULL DRAM RESETB DOWN ============
535 14:46:43.399786 ========== PULL DRAM RESETB DOWN end =========
536 14:46:43.399839 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 14:46:43.399904 ===================================
538 14:46:43.399956 LPDDR4 DRAM CONFIGURATION
539 14:46:43.400008 ===================================
540 14:46:43.400068 EX_ROW_EN[0] = 0x0
541 14:46:43.400121 EX_ROW_EN[1] = 0x0
542 14:46:43.400172 LP4Y_EN = 0x0
543 14:46:43.400224 WORK_FSP = 0x0
544 14:46:43.400290 WL = 0x2
545 14:46:43.400342 RL = 0x2
546 14:46:43.400394 BL = 0x2
547 14:46:43.400453 RPST = 0x0
548 14:46:43.400506 RD_PRE = 0x0
549 14:46:43.400559 WR_PRE = 0x1
550 14:46:43.400611 WR_PST = 0x0
551 14:46:43.400677 DBI_WR = 0x0
552 14:46:43.400729 DBI_RD = 0x0
553 14:46:43.400781 OTF = 0x1
554 14:46:43.400845 ===================================
555 14:46:43.400898 ===================================
556 14:46:43.400950 ANA top config
557 14:46:43.401007 ===================================
558 14:46:43.401061 DLL_ASYNC_EN = 0
559 14:46:43.401114 ALL_SLAVE_EN = 1
560 14:46:43.401166 NEW_RANK_MODE = 1
561 14:46:43.401226 DLL_IDLE_MODE = 1
562 14:46:43.401308 LP45_APHY_COMB_EN = 1
563 14:46:43.401374 TX_ODT_DIS = 1
564 14:46:43.401434 NEW_8X_MODE = 1
565 14:46:43.401488 ===================================
566 14:46:43.401540 ===================================
567 14:46:43.401599 data_rate = 1600
568 14:46:43.401652 CKR = 1
569 14:46:43.401704 DQ_P2S_RATIO = 8
570 14:46:43.401756 ===================================
571 14:46:43.401815 CA_P2S_RATIO = 8
572 14:46:43.401867 DQ_CA_OPEN = 0
573 14:46:43.401919 DQ_SEMI_OPEN = 0
574 14:46:43.401981 CA_SEMI_OPEN = 0
575 14:46:43.402034 CA_FULL_RATE = 0
576 14:46:43.402087 DQ_CKDIV4_EN = 1
577 14:46:43.402138 CA_CKDIV4_EN = 1
578 14:46:43.402200 CA_PREDIV_EN = 0
579 14:46:43.402253 PH8_DLY = 0
580 14:46:43.402305 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 14:46:43.402363 DQ_AAMCK_DIV = 4
582 14:46:43.402416 CA_AAMCK_DIV = 4
583 14:46:43.402469 CA_ADMCK_DIV = 4
584 14:46:43.402521 DQ_TRACK_CA_EN = 0
585 14:46:43.402580 CA_PICK = 800
586 14:46:43.402632 CA_MCKIO = 800
587 14:46:43.402684 MCKIO_SEMI = 0
588 14:46:43.402742 PLL_FREQ = 3068
589 14:46:43.402796 DQ_UI_PI_RATIO = 32
590 14:46:43.402848 CA_UI_PI_RATIO = 0
591 14:46:43.402900 ===================================
592 14:46:43.402960 ===================================
593 14:46:43.403013 memory_type:LPDDR4
594 14:46:43.403065 GP_NUM : 10
595 14:46:43.403122 SRAM_EN : 1
596 14:46:43.403176 MD32_EN : 0
597 14:46:43.403443 ===================================
598 14:46:43.403512 [ANA_INIT] >>>>>>>>>>>>>>
599 14:46:43.403567 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 14:46:43.403623 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 14:46:43.403676 ===================================
602 14:46:43.403737 data_rate = 1600,PCW = 0X7600
603 14:46:43.403790 ===================================
604 14:46:43.403878 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 14:46:43.403937 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 14:46:43.403992 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 14:46:43.404045 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 14:46:43.404138 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 14:46:43.404191 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 14:46:43.404244 [ANA_INIT] flow start
611 14:46:43.404308 [ANA_INIT] PLL >>>>>>>>
612 14:46:43.404360 [ANA_INIT] PLL <<<<<<<<
613 14:46:43.404413 [ANA_INIT] MIDPI >>>>>>>>
614 14:46:43.404471 [ANA_INIT] MIDPI <<<<<<<<
615 14:46:43.404525 [ANA_INIT] DLL >>>>>>>>
616 14:46:43.404576 [ANA_INIT] flow end
617 14:46:43.404628 ============ LP4 DIFF to SE enter ============
618 14:46:43.404690 ============ LP4 DIFF to SE exit ============
619 14:46:43.404744 [ANA_INIT] <<<<<<<<<<<<<
620 14:46:43.404796 [Flow] Enable top DCM control >>>>>
621 14:46:43.404854 [Flow] Enable top DCM control <<<<<
622 14:46:43.404908 Enable DLL master slave shuffle
623 14:46:43.404960 ==============================================================
624 14:46:43.405013 Gating Mode config
625 14:46:43.405073 ==============================================================
626 14:46:43.405126 Config description:
627 14:46:43.405178 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 14:46:43.405237 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 14:46:43.405349 SELPH_MODE 0: By rank 1: By Phase
630 14:46:43.405404 ==============================================================
631 14:46:43.405465 GAT_TRACK_EN = 1
632 14:46:43.405518 RX_GATING_MODE = 2
633 14:46:43.405570 RX_GATING_TRACK_MODE = 2
634 14:46:43.405630 SELPH_MODE = 1
635 14:46:43.405683 PICG_EARLY_EN = 1
636 14:46:43.405735 VALID_LAT_VALUE = 1
637 14:46:43.405787 ==============================================================
638 14:46:43.405847 Enter into Gating configuration >>>>
639 14:46:43.405899 Exit from Gating configuration <<<<
640 14:46:43.405952 Enter into DVFS_PRE_config >>>>>
641 14:46:43.406017 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 14:46:43.406074 Exit from DVFS_PRE_config <<<<<
643 14:46:43.406127 Enter into PICG configuration >>>>
644 14:46:43.406179 Exit from PICG configuration <<<<
645 14:46:43.406242 [RX_INPUT] configuration >>>>>
646 14:46:43.406295 [RX_INPUT] configuration <<<<<
647 14:46:43.406347 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 14:46:43.406407 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 14:46:43.406460 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 14:46:43.406513 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 14:46:43.406564 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 14:46:43.406624 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 14:46:43.406676 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 14:46:43.406727 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 14:46:43.406790 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 14:46:43.406843 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 14:46:43.406895 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 14:46:43.406953 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 14:46:43.407007 ===================================
660 14:46:43.407059 LPDDR4 DRAM CONFIGURATION
661 14:46:43.407111 ===================================
662 14:46:43.407169 EX_ROW_EN[0] = 0x0
663 14:46:43.407223 EX_ROW_EN[1] = 0x0
664 14:46:43.407275 LP4Y_EN = 0x0
665 14:46:43.407326 WORK_FSP = 0x0
666 14:46:43.407386 WL = 0x2
667 14:46:43.407448 RL = 0x2
668 14:46:43.407502 BL = 0x2
669 14:46:43.407560 RPST = 0x0
670 14:46:43.407613 RD_PRE = 0x0
671 14:46:43.407665 WR_PRE = 0x1
672 14:46:43.407725 WR_PST = 0x0
673 14:46:43.407780 DBI_WR = 0x0
674 14:46:43.407831 DBI_RD = 0x0
675 14:46:43.407883 OTF = 0x1
676 14:46:43.407943 ===================================
677 14:46:43.407996 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 14:46:43.408049 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 14:46:43.408101 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 14:46:43.408161 ===================================
681 14:46:43.408213 LPDDR4 DRAM CONFIGURATION
682 14:46:43.408265 ===================================
683 14:46:43.408324 EX_ROW_EN[0] = 0x10
684 14:46:43.408377 EX_ROW_EN[1] = 0x0
685 14:46:43.408428 LP4Y_EN = 0x0
686 14:46:43.408480 WORK_FSP = 0x0
687 14:46:43.408539 WL = 0x2
688 14:46:43.408592 RL = 0x2
689 14:46:43.408663 BL = 0x2
690 14:46:43.408724 RPST = 0x0
691 14:46:43.408777 RD_PRE = 0x0
692 14:46:43.408828 WR_PRE = 0x1
693 14:46:43.408919 WR_PST = 0x0
694 14:46:43.408972 DBI_WR = 0x0
695 14:46:43.409025 DBI_RD = 0x0
696 14:46:43.409083 OTF = 0x1
697 14:46:43.409136 ===================================
698 14:46:43.409189 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 14:46:43.409242 nWR fixed to 40
700 14:46:43.409309 [ModeRegInit_LP4] CH0 RK0
701 14:46:43.409363 [ModeRegInit_LP4] CH0 RK1
702 14:46:43.409415 [ModeRegInit_LP4] CH1 RK0
703 14:46:43.409473 [ModeRegInit_LP4] CH1 RK1
704 14:46:43.409527 match AC timing 13
705 14:46:43.409579 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 14:46:43.409841 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 14:46:43.409949 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 14:46:43.410064 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 14:46:43.410172 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 14:46:43.410290 [EMI DOE] emi_dcm 0
711 14:46:43.410392 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 14:46:43.410504 ==
713 14:46:43.410617 Dram Type= 6, Freq= 0, CH_0, rank 0
714 14:46:43.410723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 14:46:43.410838 ==
716 14:46:43.410945 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 14:46:43.411053 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 14:46:43.411137 [CA 0] Center 37 (7~68) winsize 62
719 14:46:43.411231 [CA 1] Center 37 (6~68) winsize 63
720 14:46:43.411345 [CA 2] Center 34 (4~65) winsize 62
721 14:46:43.411436 [CA 3] Center 34 (4~65) winsize 62
722 14:46:43.411518 [CA 4] Center 33 (3~64) winsize 62
723 14:46:43.411607 [CA 5] Center 33 (3~64) winsize 62
724 14:46:43.411689
725 14:46:43.411777 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 14:46:43.411859
727 14:46:43.411941 [CATrainingPosCal] consider 1 rank data
728 14:46:43.412030 u2DelayCellTimex100 = 270/100 ps
729 14:46:43.412114 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 14:46:43.412208 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
731 14:46:43.412291 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
732 14:46:43.412381 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 14:46:43.412463 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
734 14:46:43.412552 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 14:46:43.412633
736 14:46:43.412720 CA PerBit enable=1, Macro0, CA PI delay=33
737 14:46:43.412803
738 14:46:43.412884 [CBTSetCACLKResult] CA Dly = 33
739 14:46:43.412972 CS Dly: 5 (0~36)
740 14:46:43.413053 ==
741 14:46:43.413142 Dram Type= 6, Freq= 0, CH_0, rank 1
742 14:46:43.413242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 14:46:43.413381 ==
744 14:46:43.413502 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 14:46:43.413602 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 14:46:43.413707 [CA 0] Center 38 (7~69) winsize 63
747 14:46:43.413804 [CA 1] Center 37 (7~68) winsize 62
748 14:46:43.413910 [CA 2] Center 35 (4~66) winsize 63
749 14:46:43.414009 [CA 3] Center 35 (4~66) winsize 63
750 14:46:43.414115 [CA 4] Center 34 (3~65) winsize 63
751 14:46:43.414211 [CA 5] Center 33 (3~64) winsize 62
752 14:46:43.414344
753 14:46:43.414438 [CmdBusTrainingLP45] Vref(ca) range 1: 32
754 14:46:43.414526
755 14:46:43.414625 [CATrainingPosCal] consider 2 rank data
756 14:46:43.414690 u2DelayCellTimex100 = 270/100 ps
757 14:46:43.414743 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 14:46:43.414795 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 14:46:43.414856 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
760 14:46:43.414908 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 14:46:43.414961 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
762 14:46:43.415013 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 14:46:43.415073
764 14:46:43.415125 CA PerBit enable=1, Macro0, CA PI delay=33
765 14:46:43.415177
766 14:46:43.415236 [CBTSetCACLKResult] CA Dly = 33
767 14:46:43.415289 CS Dly: 6 (0~38)
768 14:46:43.415340
769 14:46:43.415392 ----->DramcWriteLeveling(PI) begin...
770 14:46:43.415455 ==
771 14:46:43.415509 Dram Type= 6, Freq= 0, CH_0, rank 0
772 14:46:43.415561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 14:46:43.415625 ==
774 14:46:43.415679 Write leveling (Byte 0): 31 => 31
775 14:46:43.415732 Write leveling (Byte 1): 25 => 25
776 14:46:43.415783 DramcWriteLeveling(PI) end<-----
777 14:46:43.415843
778 14:46:43.415896 ==
779 14:46:43.415948 Dram Type= 6, Freq= 0, CH_0, rank 0
780 14:46:43.416007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 14:46:43.416060 ==
782 14:46:43.416113 [Gating] SW mode calibration
783 14:46:43.416166 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 14:46:43.416225 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 14:46:43.416278 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 14:46:43.416330 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
787 14:46:43.416389 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
788 14:46:43.416442 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 14:46:43.416495 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 14:46:43.416552 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 14:46:43.416606 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 14:46:43.416658 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 14:46:43.416710 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 14:46:43.416774 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 14:46:43.416828 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 14:46:43.416902 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 14:46:43.416979 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 14:46:43.417032 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 14:46:43.417084 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 14:46:43.417142 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 14:46:43.417195 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 14:46:43.417247 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 14:46:43.417347 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
804 14:46:43.417400 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
805 14:46:43.417452 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 14:46:43.417504 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 14:46:43.417563 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 14:46:43.417616 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 14:46:43.417668 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 14:46:43.417726 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 14:46:43.417780 0 9 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
812 14:46:43.417832 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
813 14:46:43.417884 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 14:46:43.418166 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 14:46:43.418240 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 14:46:43.418305 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 14:46:43.418359 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 14:46:43.418412 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 0) (0 1)
819 14:46:43.418465 0 10 8 | B1->B0 | 3232 2424 | 1 0 | (1 1) (0 0)
820 14:46:43.418525 0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
821 14:46:43.418578 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 14:46:43.418631 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 14:46:43.418690 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 14:46:43.418743 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 14:46:43.418795 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 14:46:43.418847 0 11 4 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
827 14:46:43.418906 0 11 8 | B1->B0 | 2929 3f3f | 0 0 | (0 0) (0 0)
828 14:46:43.418958 0 11 12 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
829 14:46:43.419010 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 14:46:43.419072 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 14:46:43.419126 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 14:46:43.419178 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 14:46:43.419235 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 14:46:43.419320 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
835 14:46:43.419387 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 14:46:43.419446 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 14:46:43.419518 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 14:46:43.419584 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 14:46:43.419687 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 14:46:43.419741 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 14:46:43.419830 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 14:46:43.419921 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 14:46:43.419977 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 14:46:43.420037 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 14:46:43.420091 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 14:46:43.420144 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 14:46:43.420197 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 14:46:43.420258 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 14:46:43.420311 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 14:46:43.420365 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
851 14:46:43.420425 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
852 14:46:43.420491 Total UI for P1: 0, mck2ui 16
853 14:46:43.420544 best dqsien dly found for B0: ( 0, 14, 4)
854 14:46:43.420617 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
855 14:46:43.420685 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 14:46:43.420737 Total UI for P1: 0, mck2ui 16
857 14:46:43.420816 best dqsien dly found for B1: ( 0, 14, 10)
858 14:46:43.420872 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 14:46:43.420925 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 14:46:43.420988
861 14:46:43.421057 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 14:46:43.421111 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 14:46:43.421183 [Gating] SW calibration Done
864 14:46:43.421238 ==
865 14:46:43.421320 Dram Type= 6, Freq= 0, CH_0, rank 0
866 14:46:43.421398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 14:46:43.421465 ==
868 14:46:43.421518 RX Vref Scan: 0
869 14:46:43.421591
870 14:46:43.421659 RX Vref 0 -> 0, step: 1
871 14:46:43.421710
872 14:46:43.421784 RX Delay -130 -> 252, step: 16
873 14:46:43.421851 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 14:46:43.421904 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 14:46:43.421978 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 14:46:43.422045 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 14:46:43.422097 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 14:46:43.422179 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 14:46:43.422233 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 14:46:43.422286 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
881 14:46:43.422351 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 14:46:43.422405 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
883 14:46:43.422458 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 14:46:43.422517 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 14:46:43.422572 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 14:46:43.422624 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 14:46:43.422677 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 14:46:43.422738 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 14:46:43.422803 ==
890 14:46:43.422856 Dram Type= 6, Freq= 0, CH_0, rank 0
891 14:46:43.422929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 14:46:43.422996 ==
893 14:46:43.423048 DQS Delay:
894 14:46:43.423122 DQS0 = 0, DQS1 = 0
895 14:46:43.423188 DQM Delay:
896 14:46:43.423240 DQM0 = 87, DQM1 = 75
897 14:46:43.423312 DQ Delay:
898 14:46:43.423380 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 14:46:43.423432 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
900 14:46:43.423522 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
901 14:46:43.423589 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
902 14:46:43.423641
903 14:46:43.423702
904 14:46:43.423755 ==
905 14:46:43.423807 Dram Type= 6, Freq= 0, CH_0, rank 0
906 14:46:43.423866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 14:46:43.423920 ==
908 14:46:43.423973
909 14:46:43.424025
910 14:46:43.424084 TX Vref Scan disable
911 14:46:43.424136 == TX Byte 0 ==
912 14:46:43.424188 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
913 14:46:43.424246 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
914 14:46:43.424300 == TX Byte 1 ==
915 14:46:43.424351 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
916 14:46:43.424404 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
917 14:46:43.424491 ==
918 14:46:43.424616 Dram Type= 6, Freq= 0, CH_0, rank 0
919 14:46:43.424707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 14:46:43.424789 ==
921 14:46:43.424879 TX Vref=22, minBit 1, minWin=27, winSum=441
922 14:46:43.425163 TX Vref=24, minBit 1, minWin=27, winSum=443
923 14:46:43.425282 TX Vref=26, minBit 1, minWin=27, winSum=446
924 14:46:43.425354 TX Vref=28, minBit 1, minWin=27, winSum=447
925 14:46:43.425432 TX Vref=30, minBit 3, minWin=27, winSum=448
926 14:46:43.425500 TX Vref=32, minBit 4, minWin=27, winSum=450
927 14:46:43.425554 [TxChooseVref] Worse bit 4, Min win 27, Win sum 450, Final Vref 32
928 14:46:43.425630
929 14:46:43.425699 Final TX Range 1 Vref 32
930 14:46:43.425753
931 14:46:43.425830 ==
932 14:46:43.425898 Dram Type= 6, Freq= 0, CH_0, rank 0
933 14:46:43.425951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 14:46:43.426032 ==
935 14:46:43.426099
936 14:46:43.426174
937 14:46:43.426241 TX Vref Scan disable
938 14:46:43.426294 == TX Byte 0 ==
939 14:46:43.426351 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
940 14:46:43.426424 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
941 14:46:43.426477 == TX Byte 1 ==
942 14:46:43.426537 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
943 14:46:43.426597 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
944 14:46:43.426650
945 14:46:43.426703 [DATLAT]
946 14:46:43.426764 Freq=800, CH0 RK0
947 14:46:43.426818
948 14:46:43.426878 DATLAT Default: 0xa
949 14:46:43.426943 0, 0xFFFF, sum = 0
950 14:46:43.427015 1, 0xFFFF, sum = 0
951 14:46:43.427068 2, 0xFFFF, sum = 0
952 14:46:43.427143 3, 0xFFFF, sum = 0
953 14:46:43.427198 4, 0xFFFF, sum = 0
954 14:46:43.427265 5, 0xFFFF, sum = 0
955 14:46:43.427340 6, 0xFFFF, sum = 0
956 14:46:43.427408 7, 0xFFFF, sum = 0
957 14:46:43.427461 8, 0xFFFF, sum = 0
958 14:46:43.427536 9, 0x0, sum = 1
959 14:46:43.427604 10, 0x0, sum = 2
960 14:46:43.427657 11, 0x0, sum = 3
961 14:46:43.427739 12, 0x0, sum = 4
962 14:46:43.427808 best_step = 10
963 14:46:43.427859
964 14:46:43.427939 ==
965 14:46:43.428005 Dram Type= 6, Freq= 0, CH_0, rank 0
966 14:46:43.428058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 14:46:43.428144 ==
968 14:46:43.428226 RX Vref Scan: 1
969 14:46:43.428303
970 14:46:43.428357 Set Vref Range= 32 -> 127
971 14:46:43.428410
972 14:46:43.428470 RX Vref 32 -> 127, step: 1
973 14:46:43.428525
974 14:46:43.428578 RX Delay -111 -> 252, step: 8
975 14:46:43.428632
976 14:46:43.428692 Set Vref, RX VrefLevel [Byte0]: 32
977 14:46:43.428747 [Byte1]: 32
978 14:46:43.428801
979 14:46:43.428860 Set Vref, RX VrefLevel [Byte0]: 33
980 14:46:43.428928 [Byte1]: 33
981 14:46:43.428980
982 14:46:43.429032 Set Vref, RX VrefLevel [Byte0]: 34
983 14:46:43.429116 [Byte1]: 34
984 14:46:43.429169
985 14:46:43.429231 Set Vref, RX VrefLevel [Byte0]: 35
986 14:46:43.429310 [Byte1]: 35
987 14:46:43.429363
988 14:46:43.429416 Set Vref, RX VrefLevel [Byte0]: 36
989 14:46:43.429493 [Byte1]: 36
990 14:46:43.429559
991 14:46:43.429632 Set Vref, RX VrefLevel [Byte0]: 37
992 14:46:43.429687 [Byte1]: 37
993 14:46:43.429792
994 14:46:43.429851 Set Vref, RX VrefLevel [Byte0]: 38
995 14:46:43.429911 [Byte1]: 38
996 14:46:43.429963
997 14:46:43.430023 Set Vref, RX VrefLevel [Byte0]: 39
998 14:46:43.430076 [Byte1]: 39
999 14:46:43.430164
1000 14:46:43.430245 Set Vref, RX VrefLevel [Byte0]: 40
1001 14:46:43.430325 [Byte1]: 40
1002 14:46:43.430408
1003 14:46:43.430463 Set Vref, RX VrefLevel [Byte0]: 41
1004 14:46:43.430516 [Byte1]: 41
1005 14:46:43.430574
1006 14:46:43.430628 Set Vref, RX VrefLevel [Byte0]: 42
1007 14:46:43.430681 [Byte1]: 42
1008 14:46:43.430733
1009 14:46:43.430792 Set Vref, RX VrefLevel [Byte0]: 43
1010 14:46:43.430845 [Byte1]: 43
1011 14:46:43.430897
1012 14:46:43.430955 Set Vref, RX VrefLevel [Byte0]: 44
1013 14:46:43.431009 [Byte1]: 44
1014 14:46:43.431060
1015 14:46:43.431112 Set Vref, RX VrefLevel [Byte0]: 45
1016 14:46:43.431170 [Byte1]: 45
1017 14:46:43.431225
1018 14:46:43.431278 Set Vref, RX VrefLevel [Byte0]: 46
1019 14:46:43.431341 [Byte1]: 46
1020 14:46:43.431396
1021 14:46:43.431448 Set Vref, RX VrefLevel [Byte0]: 47
1022 14:46:43.431500 [Byte1]: 47
1023 14:46:43.431559
1024 14:46:43.431612 Set Vref, RX VrefLevel [Byte0]: 48
1025 14:46:43.431671 [Byte1]: 48
1026 14:46:43.431734
1027 14:46:43.431788 Set Vref, RX VrefLevel [Byte0]: 49
1028 14:46:43.431840 [Byte1]: 49
1029 14:46:43.431892
1030 14:46:43.431951 Set Vref, RX VrefLevel [Byte0]: 50
1031 14:46:43.432003 [Byte1]: 50
1032 14:46:43.432055
1033 14:46:43.432111 Set Vref, RX VrefLevel [Byte0]: 51
1034 14:46:43.432182 [Byte1]: 51
1035 14:46:43.432249
1036 14:46:43.432306 Set Vref, RX VrefLevel [Byte0]: 52
1037 14:46:43.432359 [Byte1]: 52
1038 14:46:43.432410
1039 14:46:43.432461 Set Vref, RX VrefLevel [Byte0]: 53
1040 14:46:43.432520 [Byte1]: 53
1041 14:46:43.432572
1042 14:46:43.432623 Set Vref, RX VrefLevel [Byte0]: 54
1043 14:46:43.432680 [Byte1]: 54
1044 14:46:43.432733
1045 14:46:43.432784 Set Vref, RX VrefLevel [Byte0]: 55
1046 14:46:43.432835 [Byte1]: 55
1047 14:46:43.432892
1048 14:46:43.432945 Set Vref, RX VrefLevel [Byte0]: 56
1049 14:46:43.432996 [Byte1]: 56
1050 14:46:43.433048
1051 14:46:43.433112 Set Vref, RX VrefLevel [Byte0]: 57
1052 14:46:43.433164 [Byte1]: 57
1053 14:46:43.433215
1054 14:46:43.433299 Set Vref, RX VrefLevel [Byte0]: 58
1055 14:46:43.433367 [Byte1]: 58
1056 14:46:43.433418
1057 14:46:43.433476 Set Vref, RX VrefLevel [Byte0]: 59
1058 14:46:43.433529 [Byte1]: 59
1059 14:46:43.433580
1060 14:46:43.433691 Set Vref, RX VrefLevel [Byte0]: 60
1061 14:46:43.433759 [Byte1]: 60
1062 14:46:43.433811
1063 14:46:43.433873 Set Vref, RX VrefLevel [Byte0]: 61
1064 14:46:43.433926 [Byte1]: 61
1065 14:46:43.433977
1066 14:46:43.434035 Set Vref, RX VrefLevel [Byte0]: 62
1067 14:46:43.434088 [Byte1]: 62
1068 14:46:43.434150
1069 14:46:43.434204 Set Vref, RX VrefLevel [Byte0]: 63
1070 14:46:43.434263 [Byte1]: 63
1071 14:46:43.434314
1072 14:46:43.434366 Set Vref, RX VrefLevel [Byte0]: 64
1073 14:46:43.434428 [Byte1]: 64
1074 14:46:43.434481
1075 14:46:43.434532 Set Vref, RX VrefLevel [Byte0]: 65
1076 14:46:43.434584 [Byte1]: 65
1077 14:46:43.434645
1078 14:46:43.434697 Set Vref, RX VrefLevel [Byte0]: 66
1079 14:46:43.434749 [Byte1]: 66
1080 14:46:43.434806
1081 14:46:43.434858 Set Vref, RX VrefLevel [Byte0]: 67
1082 14:46:43.434910 [Byte1]: 67
1083 14:46:43.434961
1084 14:46:43.435020 Set Vref, RX VrefLevel [Byte0]: 68
1085 14:46:43.435094 [Byte1]: 68
1086 14:46:43.435160
1087 14:46:43.435220 Set Vref, RX VrefLevel [Byte0]: 69
1088 14:46:43.435272 [Byte1]: 69
1089 14:46:43.435353
1090 14:46:43.435632 Set Vref, RX VrefLevel [Byte0]: 70
1091 14:46:43.435706 [Byte1]: 70
1092 14:46:43.435813
1093 14:46:43.435879 Set Vref, RX VrefLevel [Byte0]: 71
1094 14:46:43.435932 [Byte1]: 71
1095 14:46:43.436007
1096 14:46:43.436073 Set Vref, RX VrefLevel [Byte0]: 72
1097 14:46:43.436158 [Byte1]: 72
1098 14:46:43.436218
1099 14:46:43.436271 Set Vref, RX VrefLevel [Byte0]: 73
1100 14:46:43.436360 [Byte1]: 73
1101 14:46:43.436428
1102 14:46:43.436479 Set Vref, RX VrefLevel [Byte0]: 74
1103 14:46:43.436536 [Byte1]: 74
1104 14:46:43.436588
1105 14:46:43.436639 Final RX Vref Byte 0 = 56 to rank0
1106 14:46:43.436691 Final RX Vref Byte 1 = 61 to rank0
1107 14:46:43.436750 Final RX Vref Byte 0 = 56 to rank1
1108 14:46:43.436802 Final RX Vref Byte 1 = 61 to rank1==
1109 14:46:43.436853 Dram Type= 6, Freq= 0, CH_0, rank 0
1110 14:46:43.436905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1111 14:46:43.436984 ==
1112 14:46:43.437053 DQS Delay:
1113 14:46:43.437111 DQS0 = 0, DQS1 = 0
1114 14:46:43.437164 DQM Delay:
1115 14:46:43.437215 DQM0 = 88, DQM1 = 76
1116 14:46:43.437317 DQ Delay:
1117 14:46:43.437372 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1118 14:46:43.437424 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1119 14:46:43.437483 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =72
1120 14:46:43.437536 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1121 14:46:43.437587
1122 14:46:43.437638
1123 14:46:43.437695 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
1124 14:46:43.437764 CH0 RK0: MR19=606, MR18=2F28
1125 14:46:43.437830 CH0_RK0: MR19=0x606, MR18=0x2F28, DQSOSC=397, MR23=63, INC=93, DEC=62
1126 14:46:43.437906
1127 14:46:43.437971 ----->DramcWriteLeveling(PI) begin...
1128 14:46:43.438024 ==
1129 14:46:43.438096 Dram Type= 6, Freq= 0, CH_0, rank 1
1130 14:46:43.438163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1131 14:46:43.438216 ==
1132 14:46:43.438274 Write leveling (Byte 0): 33 => 33
1133 14:46:43.438326 Write leveling (Byte 1): 27 => 27
1134 14:46:43.438377 DramcWriteLeveling(PI) end<-----
1135 14:46:43.438428
1136 14:46:43.438494 ==
1137 14:46:43.438546 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 14:46:43.438597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 14:46:43.438656 ==
1140 14:46:43.438708 [Gating] SW mode calibration
1141 14:46:43.438760 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1142 14:46:43.438818 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1143 14:46:43.438871 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1144 14:46:43.438923 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1145 14:46:43.438975 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1146 14:46:43.439032 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 14:46:43.439085 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 14:46:43.439136 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 14:46:43.439188 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 14:46:43.439250 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 14:46:43.439302 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 14:46:43.439353 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 14:46:43.439410 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 14:46:43.439463 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 14:46:43.439515 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 14:46:43.439566 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 14:46:43.439625 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 14:46:43.439689 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 14:46:43.439742 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 14:46:43.439800 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1161 14:46:43.439853 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1162 14:46:43.439905 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 14:46:43.439956 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 14:46:43.440016 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 14:46:43.440068 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 14:46:43.440120 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 14:46:43.440177 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 14:46:43.440229 0 9 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
1169 14:46:43.440281 0 9 8 | B1->B0 | 2424 3434 | 1 0 | (1 1) (0 0)
1170 14:46:43.440332 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1171 14:46:43.440390 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1172 14:46:43.440442 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 14:46:43.440499 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 14:46:43.440559 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 14:46:43.440648 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 14:46:43.440699 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 1)
1177 14:46:43.440757 0 10 8 | B1->B0 | 3030 2424 | 1 0 | (1 0) (0 0)
1178 14:46:43.440846 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1179 14:46:43.440897 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 14:46:43.440970 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 14:46:43.441024 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 14:46:43.441077 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 14:46:43.441135 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 14:46:43.441190 0 11 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
1185 14:46:43.441244 0 11 8 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
1186 14:46:43.441345 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1187 14:46:43.441412 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 14:46:43.441464 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 14:46:43.441535 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 14:46:43.441603 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 14:46:43.441654 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 14:46:43.441984 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 14:46:43.442088 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1194 14:46:43.442166 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 14:46:43.442219 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 14:46:43.442279 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 14:46:43.442334 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 14:46:43.442387 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 14:46:43.442439 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 14:46:43.442501 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 14:46:43.442555 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 14:46:43.442608 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 14:46:43.442669 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 14:46:43.442724 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 14:46:43.442777 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 14:46:43.442830 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 14:46:43.442890 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 14:46:43.442943 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 14:46:43.442996 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 14:46:43.443048 Total UI for P1: 0, mck2ui 16
1211 14:46:43.443109 best dqsien dly found for B0: ( 0, 14, 6)
1212 14:46:43.443162 Total UI for P1: 0, mck2ui 16
1213 14:46:43.443215 best dqsien dly found for B1: ( 0, 14, 6)
1214 14:46:43.443275 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1215 14:46:43.443329 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1216 14:46:43.443393
1217 14:46:43.443454 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1218 14:46:43.443520 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1219 14:46:43.443575 [Gating] SW calibration Done
1220 14:46:43.443646 ==
1221 14:46:43.443713 Dram Type= 6, Freq= 0, CH_0, rank 1
1222 14:46:43.443764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1223 14:46:43.443816 ==
1224 14:46:43.443909 RX Vref Scan: 0
1225 14:46:43.443961
1226 14:46:43.444033 RX Vref 0 -> 0, step: 1
1227 14:46:43.444087
1228 14:46:43.444138 RX Delay -130 -> 252, step: 16
1229 14:46:43.444192 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1230 14:46:43.444251 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1231 14:46:43.444305 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1232 14:46:43.444370 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1233 14:46:43.444455 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1234 14:46:43.444507 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1235 14:46:43.444558 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1236 14:46:43.444630 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1237 14:46:43.444696 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1238 14:46:43.444747 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1239 14:46:43.444821 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1240 14:46:43.444887 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1241 14:46:43.444938 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1242 14:46:43.445011 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1243 14:46:43.445064 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1244 14:46:43.445117 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1245 14:46:43.445178 ==
1246 14:46:43.445232 Dram Type= 6, Freq= 0, CH_0, rank 1
1247 14:46:43.445313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1248 14:46:43.445391 ==
1249 14:46:43.445458 DQS Delay:
1250 14:46:43.445509 DQS0 = 0, DQS1 = 0
1251 14:46:43.445567 DQM Delay:
1252 14:46:43.445679 DQM0 = 85, DQM1 = 76
1253 14:46:43.445754 DQ Delay:
1254 14:46:43.445839 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1255 14:46:43.445892 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
1256 14:46:43.445980 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1257 14:46:43.446046 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1258 14:46:43.446097
1259 14:46:43.446212
1260 14:46:43.446279 ==
1261 14:46:43.446352 Dram Type= 6, Freq= 0, CH_0, rank 1
1262 14:46:43.446419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1263 14:46:43.446471 ==
1264 14:46:43.446573
1265 14:46:43.446627
1266 14:46:43.446679 TX Vref Scan disable
1267 14:46:43.446765 == TX Byte 0 ==
1268 14:46:43.446817 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1269 14:46:43.446870 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1270 14:46:43.446944 == TX Byte 1 ==
1271 14:46:43.447009 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1272 14:46:43.447061 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1273 14:46:43.447134 ==
1274 14:46:43.447187 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 14:46:43.447240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 14:46:43.447300 ==
1277 14:46:43.447354 TX Vref=22, minBit 1, minWin=27, winSum=443
1278 14:46:43.447409 TX Vref=24, minBit 2, minWin=27, winSum=446
1279 14:46:43.447468 TX Vref=26, minBit 1, minWin=27, winSum=450
1280 14:46:43.447523 TX Vref=28, minBit 2, minWin=27, winSum=451
1281 14:46:43.447577 TX Vref=30, minBit 4, minWin=27, winSum=449
1282 14:46:43.447630 TX Vref=32, minBit 4, minWin=27, winSum=450
1283 14:46:43.447689 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 28
1284 14:46:43.447743
1285 14:46:43.447796 Final TX Range 1 Vref 28
1286 14:46:43.447848
1287 14:46:43.447914 ==
1288 14:46:43.447966 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 14:46:43.448019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 14:46:43.448084 ==
1291 14:46:43.448148
1292 14:46:43.448202
1293 14:46:43.448263 TX Vref Scan disable
1294 14:46:43.448317 == TX Byte 0 ==
1295 14:46:43.448370 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1296 14:46:43.448430 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1297 14:46:43.448484 == TX Byte 1 ==
1298 14:46:43.448537 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1299 14:46:43.448589 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1300 14:46:43.448649
1301 14:46:43.448701 [DATLAT]
1302 14:46:43.448753 Freq=800, CH0 RK1
1303 14:46:43.448812
1304 14:46:43.448865 DATLAT Default: 0xa
1305 14:46:43.448917 0, 0xFFFF, sum = 0
1306 14:46:43.448971 1, 0xFFFF, sum = 0
1307 14:46:43.449031 2, 0xFFFF, sum = 0
1308 14:46:43.449085 3, 0xFFFF, sum = 0
1309 14:46:43.449137 4, 0xFFFF, sum = 0
1310 14:46:43.449201 5, 0xFFFF, sum = 0
1311 14:46:43.449263 6, 0xFFFF, sum = 0
1312 14:46:43.449320 7, 0xFFFF, sum = 0
1313 14:46:43.449373 8, 0xFFFF, sum = 0
1314 14:46:43.449437 9, 0x0, sum = 1
1315 14:46:43.449491 10, 0x0, sum = 2
1316 14:46:43.449544 11, 0x0, sum = 3
1317 14:46:43.449603 12, 0x0, sum = 4
1318 14:46:43.449657 best_step = 10
1319 14:46:43.449727
1320 14:46:43.449818 ==
1321 14:46:43.449900 Dram Type= 6, Freq= 0, CH_0, rank 1
1322 14:46:43.449989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1323 14:46:43.450073 ==
1324 14:46:43.450163 RX Vref Scan: 0
1325 14:46:43.450231
1326 14:46:43.450283 RX Vref 0 -> 0, step: 1
1327 14:46:43.450336
1328 14:46:43.450604 RX Delay -95 -> 252, step: 8
1329 14:46:43.450666 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1330 14:46:43.450720 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1331 14:46:43.450782 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1332 14:46:43.450835 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1333 14:46:43.450887 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1334 14:46:43.450946 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1335 14:46:43.450999 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1336 14:46:43.451065 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1337 14:46:43.451174 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1338 14:46:43.451262 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1339 14:46:43.451338 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1340 14:46:43.451392 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1341 14:46:43.451444 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1342 14:46:43.451502 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1343 14:46:43.451554 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1344 14:46:43.451606 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1345 14:46:43.451658 ==
1346 14:46:43.451717 Dram Type= 6, Freq= 0, CH_0, rank 1
1347 14:46:43.451770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1348 14:46:43.451822 ==
1349 14:46:43.451885 DQS Delay:
1350 14:46:43.451938 DQS0 = 0, DQS1 = 0
1351 14:46:43.451990 DQM Delay:
1352 14:46:43.452041 DQM0 = 86, DQM1 = 76
1353 14:46:43.452111 DQ Delay:
1354 14:46:43.452193 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1355 14:46:43.452267 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1356 14:46:43.452321 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1357 14:46:43.452376 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1358 14:46:43.452428
1359 14:46:43.452481
1360 14:46:43.452539 [DQSOSCAuto] RK1, (LSB)MR18= 0x2825, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
1361 14:46:43.452594 CH0 RK1: MR19=606, MR18=2825
1362 14:46:43.452646 CH0_RK1: MR19=0x606, MR18=0x2825, DQSOSC=399, MR23=63, INC=92, DEC=61
1363 14:46:43.452699 [RxdqsGatingPostProcess] freq 800
1364 14:46:43.452758 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1365 14:46:43.452811 Pre-setting of DQS Precalculation
1366 14:46:43.452863 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1367 14:46:43.452926 ==
1368 14:46:43.452980 Dram Type= 6, Freq= 0, CH_1, rank 0
1369 14:46:43.453032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 14:46:43.453104 ==
1371 14:46:43.453159 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1372 14:46:43.453212 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1373 14:46:43.453277 [CA 0] Center 36 (6~67) winsize 62
1374 14:46:43.453341 [CA 1] Center 37 (6~68) winsize 63
1375 14:46:43.453395 [CA 2] Center 35 (4~66) winsize 63
1376 14:46:43.453448 [CA 3] Center 34 (4~65) winsize 62
1377 14:46:43.453508 [CA 4] Center 35 (4~66) winsize 63
1378 14:46:43.453561 [CA 5] Center 34 (4~65) winsize 62
1379 14:46:43.453613
1380 14:46:43.453670 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1381 14:46:43.453725
1382 14:46:43.453776 [CATrainingPosCal] consider 1 rank data
1383 14:46:43.453828 u2DelayCellTimex100 = 270/100 ps
1384 14:46:43.453891 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1385 14:46:43.453944 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1386 14:46:43.453996 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1387 14:46:43.454048 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1388 14:46:43.454113 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
1389 14:46:43.454167 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1390 14:46:43.454219
1391 14:46:43.454277 CA PerBit enable=1, Macro0, CA PI delay=34
1392 14:46:43.454330
1393 14:46:43.454381 [CBTSetCACLKResult] CA Dly = 34
1394 14:46:43.454433 CS Dly: 4 (0~35)
1395 14:46:43.454492 ==
1396 14:46:43.454544 Dram Type= 6, Freq= 0, CH_1, rank 1
1397 14:46:43.454596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1398 14:46:43.454660 ==
1399 14:46:43.454715 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1400 14:46:43.454767 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1401 14:46:43.454828 [CA 0] Center 36 (6~67) winsize 62
1402 14:46:43.454883 [CA 1] Center 36 (6~67) winsize 62
1403 14:46:43.454935 [CA 2] Center 35 (4~66) winsize 63
1404 14:46:43.454987 [CA 3] Center 34 (4~65) winsize 62
1405 14:46:43.455046 [CA 4] Center 34 (4~65) winsize 62
1406 14:46:43.455099 [CA 5] Center 34 (4~65) winsize 62
1407 14:46:43.455152
1408 14:46:43.455203 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1409 14:46:43.455263
1410 14:46:43.455315 [CATrainingPosCal] consider 2 rank data
1411 14:46:43.455367 u2DelayCellTimex100 = 270/100 ps
1412 14:46:43.455424 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1413 14:46:43.455478 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1414 14:46:43.455531 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1415 14:46:43.455583 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1416 14:46:43.455643 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1417 14:46:43.455695 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1418 14:46:43.455747
1419 14:46:43.455804 CA PerBit enable=1, Macro0, CA PI delay=34
1420 14:46:43.455858
1421 14:46:43.455909 [CBTSetCACLKResult] CA Dly = 34
1422 14:46:43.455961 CS Dly: 5 (0~37)
1423 14:46:43.456025
1424 14:46:43.456078 ----->DramcWriteLeveling(PI) begin...
1425 14:46:43.456136 ==
1426 14:46:43.456206 Dram Type= 6, Freq= 0, CH_1, rank 0
1427 14:46:43.456285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1428 14:46:43.456343 ==
1429 14:46:43.456403 Write leveling (Byte 0): 27 => 27
1430 14:46:43.456456 Write leveling (Byte 1): 27 => 27
1431 14:46:43.456508 DramcWriteLeveling(PI) end<-----
1432 14:46:43.456567
1433 14:46:43.456619 ==
1434 14:46:43.456671 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 14:46:43.456723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 14:46:43.456782 ==
1437 14:46:43.456835 [Gating] SW mode calibration
1438 14:46:43.456887 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1439 14:46:43.456946 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1440 14:46:43.457000 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1441 14:46:43.457053 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1442 14:46:43.457104 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 14:46:43.457163 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 14:46:43.457216 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 14:46:43.457475 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 14:46:43.457546 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 14:46:43.457601 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 14:46:43.457654 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 14:46:43.457707 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 14:46:43.457767 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 14:46:43.457819 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 14:46:43.457872 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 14:46:43.457931 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 14:46:43.457984 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 14:46:43.458036 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 14:46:43.458088 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 14:46:43.458155 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1458 14:46:43.458208 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1459 14:46:43.458261 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 14:46:43.458320 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 14:46:43.458372 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 14:46:43.458423 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 14:46:43.458476 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 14:46:43.458535 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 14:46:43.458588 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 14:46:43.458639 0 9 8 | B1->B0 | 2d2d 3333 | 0 1 | (0 0) (1 1)
1467 14:46:43.458700 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1468 14:46:43.458752 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 14:46:43.458804 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 14:46:43.458855 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 14:46:43.458914 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 14:46:43.458966 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 14:46:43.459018 0 10 4 | B1->B0 | 3434 3030 | 0 0 | (0 1) (0 0)
1474 14:46:43.459076 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1475 14:46:43.459129 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 14:46:43.459181 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 14:46:43.459233 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 14:46:43.459299 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 14:46:43.459352 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 14:46:43.459404 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 14:46:43.459463 0 11 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1482 14:46:43.459516 0 11 8 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
1483 14:46:43.459568 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1484 14:46:43.459625 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 14:46:43.459679 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 14:46:43.459732 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 14:46:43.459783 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 14:46:43.459841 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 14:46:43.459894 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1490 14:46:43.459946 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1491 14:46:43.459998 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 14:46:43.460064 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 14:46:43.460121 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 14:46:43.460217 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 14:46:43.460315 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 14:46:43.460375 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 14:46:43.460438 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 14:46:43.460491 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 14:46:43.460544 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 14:46:43.460602 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 14:46:43.460656 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 14:46:43.460708 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 14:46:43.460760 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 14:46:43.460823 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 14:46:43.460876 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1506 14:46:43.460928 Total UI for P1: 0, mck2ui 16
1507 14:46:43.460988 best dqsien dly found for B0: ( 0, 14, 2)
1508 14:46:43.461041 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 14:46:43.461094 Total UI for P1: 0, mck2ui 16
1510 14:46:43.461146 best dqsien dly found for B1: ( 0, 14, 4)
1511 14:46:43.461205 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1512 14:46:43.461266 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1513 14:46:43.461321
1514 14:46:43.461383 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1515 14:46:43.461436 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1516 14:46:43.461488 [Gating] SW calibration Done
1517 14:46:43.461540 ==
1518 14:46:43.461609 Dram Type= 6, Freq= 0, CH_1, rank 0
1519 14:46:43.461665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1520 14:46:43.461719 ==
1521 14:46:43.461784 RX Vref Scan: 0
1522 14:46:43.461837
1523 14:46:43.461888 RX Vref 0 -> 0, step: 1
1524 14:46:43.461945
1525 14:46:43.461999 RX Delay -130 -> 252, step: 16
1526 14:46:43.462051 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1527 14:46:43.462105 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1528 14:46:43.462173 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1529 14:46:43.462227 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1530 14:46:43.462279 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1531 14:46:43.462338 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1532 14:46:43.462391 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1533 14:46:43.462444 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1534 14:46:43.462496 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1535 14:46:43.462749 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1536 14:46:43.462808 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1537 14:46:43.462861 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1538 14:46:43.462927 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1539 14:46:43.462981 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1540 14:46:43.463064 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1541 14:46:43.463178 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1542 14:46:43.463288 ==
1543 14:46:43.463394 Dram Type= 6, Freq= 0, CH_1, rank 0
1544 14:46:43.463513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1545 14:46:43.463618 ==
1546 14:46:43.463731 DQS Delay:
1547 14:46:43.463836 DQS0 = 0, DQS1 = 0
1548 14:46:43.463928 DQM Delay:
1549 14:46:43.464010 DQM0 = 89, DQM1 = 84
1550 14:46:43.464098 DQ Delay:
1551 14:46:43.464189 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1552 14:46:43.464284 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1553 14:46:43.464367 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1554 14:46:43.464457 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1555 14:46:43.464538
1556 14:46:43.464618
1557 14:46:43.464705 ==
1558 14:46:43.464787 Dram Type= 6, Freq= 0, CH_1, rank 0
1559 14:46:43.464875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1560 14:46:43.464958 ==
1561 14:46:43.465046
1562 14:46:43.465127
1563 14:46:43.465217 TX Vref Scan disable
1564 14:46:43.465310 == TX Byte 0 ==
1565 14:46:43.465400 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1566 14:46:43.465484 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1567 14:46:43.465565 == TX Byte 1 ==
1568 14:46:43.465655 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1569 14:46:43.465737 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1570 14:46:43.465824 ==
1571 14:46:43.465906 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 14:46:43.465994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 14:46:43.466076 ==
1574 14:46:43.466168 TX Vref=22, minBit 1, minWin=27, winSum=442
1575 14:46:43.466226 TX Vref=24, minBit 0, minWin=27, winSum=444
1576 14:46:43.466279 TX Vref=26, minBit 1, minWin=27, winSum=451
1577 14:46:43.466332 TX Vref=28, minBit 0, minWin=27, winSum=451
1578 14:46:43.466393 TX Vref=30, minBit 1, minWin=27, winSum=453
1579 14:46:43.466446 TX Vref=32, minBit 1, minWin=27, winSum=451
1580 14:46:43.466498 [TxChooseVref] Worse bit 1, Min win 27, Win sum 453, Final Vref 30
1581 14:46:43.466558
1582 14:46:43.466611 Final TX Range 1 Vref 30
1583 14:46:43.466663
1584 14:46:43.466714 ==
1585 14:46:43.466773 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 14:46:43.466826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 14:46:43.466878 ==
1588 14:46:43.466953
1589 14:46:43.467010
1590 14:46:43.467062 TX Vref Scan disable
1591 14:46:43.467116 == TX Byte 0 ==
1592 14:46:43.467184 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1593 14:46:43.467236 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1594 14:46:43.467289 == TX Byte 1 ==
1595 14:46:43.467349 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1596 14:46:43.467402 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1597 14:46:43.467453
1598 14:46:43.467511 [DATLAT]
1599 14:46:43.467565 Freq=800, CH1 RK0
1600 14:46:43.467617
1601 14:46:43.467670 DATLAT Default: 0xa
1602 14:46:43.467729 0, 0xFFFF, sum = 0
1603 14:46:43.467783 1, 0xFFFF, sum = 0
1604 14:46:43.467836 2, 0xFFFF, sum = 0
1605 14:46:43.467895 3, 0xFFFF, sum = 0
1606 14:46:43.467950 4, 0xFFFF, sum = 0
1607 14:46:43.468003 5, 0xFFFF, sum = 0
1608 14:46:43.468055 6, 0xFFFF, sum = 0
1609 14:46:43.468114 7, 0xFFFF, sum = 0
1610 14:46:43.468167 8, 0xFFFF, sum = 0
1611 14:46:43.468219 9, 0x0, sum = 1
1612 14:46:43.468283 10, 0x0, sum = 2
1613 14:46:43.468338 11, 0x0, sum = 3
1614 14:46:43.468391 12, 0x0, sum = 4
1615 14:46:43.468444 best_step = 10
1616 14:46:43.468506
1617 14:46:43.468558 ==
1618 14:46:43.468610 Dram Type= 6, Freq= 0, CH_1, rank 0
1619 14:46:43.468669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1620 14:46:43.468722 ==
1621 14:46:43.468774 RX Vref Scan: 1
1622 14:46:43.468825
1623 14:46:43.468885 Set Vref Range= 32 -> 127
1624 14:46:43.468937
1625 14:46:43.468989 RX Vref 32 -> 127, step: 1
1626 14:46:43.469046
1627 14:46:43.469099 RX Delay -95 -> 252, step: 8
1628 14:46:43.469151
1629 14:46:43.469202 Set Vref, RX VrefLevel [Byte0]: 32
1630 14:46:43.469299 [Byte1]: 32
1631 14:46:43.469354
1632 14:46:43.469406 Set Vref, RX VrefLevel [Byte0]: 33
1633 14:46:43.469466 [Byte1]: 33
1634 14:46:43.469518
1635 14:46:43.469569 Set Vref, RX VrefLevel [Byte0]: 34
1636 14:46:43.469631 [Byte1]: 34
1637 14:46:43.469685
1638 14:46:43.469736 Set Vref, RX VrefLevel [Byte0]: 35
1639 14:46:43.469787 [Byte1]: 35
1640 14:46:43.469847
1641 14:46:43.469899 Set Vref, RX VrefLevel [Byte0]: 36
1642 14:46:43.469951 [Byte1]: 36
1643 14:46:43.470009
1644 14:46:43.470061 Set Vref, RX VrefLevel [Byte0]: 37
1645 14:46:43.470113 [Byte1]: 37
1646 14:46:43.470166
1647 14:46:43.470226 Set Vref, RX VrefLevel [Byte0]: 38
1648 14:46:43.470278 [Byte1]: 38
1649 14:46:43.470330
1650 14:46:43.470387 Set Vref, RX VrefLevel [Byte0]: 39
1651 14:46:43.470441 [Byte1]: 39
1652 14:46:43.470492
1653 14:46:43.470543 Set Vref, RX VrefLevel [Byte0]: 40
1654 14:46:43.470601 [Byte1]: 40
1655 14:46:43.470653
1656 14:46:43.470705 Set Vref, RX VrefLevel [Byte0]: 41
1657 14:46:43.470757 [Byte1]: 41
1658 14:46:43.470816
1659 14:46:43.470868 Set Vref, RX VrefLevel [Byte0]: 42
1660 14:46:43.470920 [Byte1]: 42
1661 14:46:43.470981
1662 14:46:43.471032 Set Vref, RX VrefLevel [Byte0]: 43
1663 14:46:43.471084 [Byte1]: 43
1664 14:46:43.471136
1665 14:46:43.471194 Set Vref, RX VrefLevel [Byte0]: 44
1666 14:46:43.471247 [Byte1]: 44
1667 14:46:43.471298
1668 14:46:43.471356 Set Vref, RX VrefLevel [Byte0]: 45
1669 14:46:43.471409 [Byte1]: 45
1670 14:46:43.471461
1671 14:46:43.471512 Set Vref, RX VrefLevel [Byte0]: 46
1672 14:46:43.471571 [Byte1]: 46
1673 14:46:43.471623
1674 14:46:43.471674 Set Vref, RX VrefLevel [Byte0]: 47
1675 14:46:43.471731 [Byte1]: 47
1676 14:46:43.471784
1677 14:46:43.471836 Set Vref, RX VrefLevel [Byte0]: 48
1678 14:46:43.471887 [Byte1]: 48
1679 14:46:43.471946
1680 14:46:43.471998 Set Vref, RX VrefLevel [Byte0]: 49
1681 14:46:43.472065 [Byte1]: 49
1682 14:46:43.472162
1683 14:46:43.472244 Set Vref, RX VrefLevel [Byte0]: 50
1684 14:46:43.472348 [Byte1]: 50
1685 14:46:43.472441
1686 14:46:43.472506 Set Vref, RX VrefLevel [Byte0]: 51
1687 14:46:43.472561 [Byte1]: 51
1688 14:46:43.472615
1689 14:46:43.472667 Set Vref, RX VrefLevel [Byte0]: 52
1690 14:46:43.472727 [Byte1]: 52
1691 14:46:43.472780
1692 14:46:43.472831 Set Vref, RX VrefLevel [Byte0]: 53
1693 14:46:43.472922 [Byte1]: 53
1694 14:46:43.473004
1695 14:46:43.473096 Set Vref, RX VrefLevel [Byte0]: 54
1696 14:46:43.473179 [Byte1]: 54
1697 14:46:43.473272
1698 14:46:43.473536 Set Vref, RX VrefLevel [Byte0]: 55
1699 14:46:43.473654 [Byte1]: 55
1700 14:46:43.473760
1701 14:46:43.473872 Set Vref, RX VrefLevel [Byte0]: 56
1702 14:46:43.473977 [Byte1]: 56
1703 14:46:43.474078
1704 14:46:43.474166 Set Vref, RX VrefLevel [Byte0]: 57
1705 14:46:43.474256 [Byte1]: 57
1706 14:46:43.474339
1707 14:46:43.474427 Set Vref, RX VrefLevel [Byte0]: 58
1708 14:46:43.474510 [Byte1]: 58
1709 14:46:43.474591
1710 14:46:43.474679 Set Vref, RX VrefLevel [Byte0]: 59
1711 14:46:43.474761 [Byte1]: 59
1712 14:46:43.474849
1713 14:46:43.474931 Set Vref, RX VrefLevel [Byte0]: 60
1714 14:46:43.475018 [Byte1]: 60
1715 14:46:43.475100
1716 14:46:43.475187 Set Vref, RX VrefLevel [Byte0]: 61
1717 14:46:43.475270 [Byte1]: 61
1718 14:46:43.475351
1719 14:46:43.475438 Set Vref, RX VrefLevel [Byte0]: 62
1720 14:46:43.475520 [Byte1]: 62
1721 14:46:43.475612
1722 14:46:43.475701 Set Vref, RX VrefLevel [Byte0]: 63
1723 14:46:43.475791 [Byte1]: 63
1724 14:46:43.475872
1725 14:46:43.475959 Set Vref, RX VrefLevel [Byte0]: 64
1726 14:46:43.476041 [Byte1]: 64
1727 14:46:43.476122
1728 14:46:43.476210 Set Vref, RX VrefLevel [Byte0]: 65
1729 14:46:43.476291 [Byte1]: 65
1730 14:46:43.476380
1731 14:46:43.476462 Set Vref, RX VrefLevel [Byte0]: 66
1732 14:46:43.476554 [Byte1]: 66
1733 14:46:43.476641
1734 14:46:43.476735 Set Vref, RX VrefLevel [Byte0]: 67
1735 14:46:43.476819 [Byte1]: 67
1736 14:46:43.476905
1737 14:46:43.476995 Set Vref, RX VrefLevel [Byte0]: 68
1738 14:46:43.477076 [Byte1]: 68
1739 14:46:43.477164
1740 14:46:43.477245 Set Vref, RX VrefLevel [Byte0]: 69
1741 14:46:43.477319 [Byte1]: 69
1742 14:46:43.477372
1743 14:46:43.477424 Set Vref, RX VrefLevel [Byte0]: 70
1744 14:46:43.477477 [Byte1]: 70
1745 14:46:43.477552
1746 14:46:43.477605 Set Vref, RX VrefLevel [Byte0]: 71
1747 14:46:43.477672 [Byte1]: 71
1748 14:46:43.477747
1749 14:46:43.477807 Set Vref, RX VrefLevel [Byte0]: 72
1750 14:46:43.477860 [Byte1]: 72
1751 14:46:43.477921
1752 14:46:43.477973 Set Vref, RX VrefLevel [Byte0]: 73
1753 14:46:43.478025 [Byte1]: 73
1754 14:46:43.478086
1755 14:46:43.478139 Final RX Vref Byte 0 = 60 to rank0
1756 14:46:43.478192 Final RX Vref Byte 1 = 58 to rank0
1757 14:46:43.478244 Final RX Vref Byte 0 = 60 to rank1
1758 14:46:43.478304 Final RX Vref Byte 1 = 58 to rank1==
1759 14:46:43.478357 Dram Type= 6, Freq= 0, CH_1, rank 0
1760 14:46:43.478409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1761 14:46:43.478469 ==
1762 14:46:43.478522 DQS Delay:
1763 14:46:43.478574 DQS0 = 0, DQS1 = 0
1764 14:46:43.478626 DQM Delay:
1765 14:46:43.478685 DQM0 = 87, DQM1 = 81
1766 14:46:43.478737 DQ Delay:
1767 14:46:43.478789 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
1768 14:46:43.478848 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1769 14:46:43.478901 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =72
1770 14:46:43.478966 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1771 14:46:43.479019
1772 14:46:43.479080
1773 14:46:43.479131 [DQSOSCAuto] RK0, (LSB)MR18= 0x192c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1774 14:46:43.479185 CH1 RK0: MR19=606, MR18=192C
1775 14:46:43.479245 CH1_RK0: MR19=0x606, MR18=0x192C, DQSOSC=398, MR23=63, INC=93, DEC=62
1776 14:46:43.479298
1777 14:46:43.479350 ----->DramcWriteLeveling(PI) begin...
1778 14:46:43.479402 ==
1779 14:46:43.479464 Dram Type= 6, Freq= 0, CH_1, rank 1
1780 14:46:43.479517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1781 14:46:43.479570 ==
1782 14:46:43.479629 Write leveling (Byte 0): 24 => 24
1783 14:46:43.479682 Write leveling (Byte 1): 29 => 29
1784 14:46:43.479740 DramcWriteLeveling(PI) end<-----
1785 14:46:43.479798
1786 14:46:43.479852 ==
1787 14:46:43.479904 Dram Type= 6, Freq= 0, CH_1, rank 1
1788 14:46:43.479955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1789 14:46:43.480020 ==
1790 14:46:43.480072 [Gating] SW mode calibration
1791 14:46:43.480124 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1792 14:46:43.480184 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1793 14:46:43.480237 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1794 14:46:43.480290 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1795 14:46:43.480342 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1796 14:46:43.480403 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1797 14:46:43.480455 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1798 14:46:43.480507 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1799 14:46:43.480565 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 14:46:43.480619 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 14:46:43.480671 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 14:46:43.480722 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 14:46:43.480781 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 14:46:43.480834 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 14:46:43.480886 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 14:46:43.480947 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 14:46:43.481001 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 14:46:43.481053 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 14:46:43.481106 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1810 14:46:43.481165 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1811 14:46:43.481218 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 14:46:43.481278 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 14:46:43.481338 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 14:46:43.481392 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 14:46:43.481444 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 14:46:43.481496 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 14:46:43.481555 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 14:46:43.481608 0 9 4 | B1->B0 | 2323 2524 | 0 1 | (0 0) (1 1)
1819 14:46:43.481659 0 9 8 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
1820 14:46:43.481721 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1821 14:46:43.481788 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1822 14:46:43.482041 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1823 14:46:43.482145 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1824 14:46:43.482253 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 14:46:43.482368 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1826 14:46:43.482473 0 10 4 | B1->B0 | 3434 2c2c | 0 0 | (0 1) (0 0)
1827 14:46:43.482575 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1828 14:46:43.482681 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 14:46:43.482767 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 14:46:43.482840 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 14:46:43.482902 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 14:46:43.482956 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 14:46:43.483008 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1834 14:46:43.483073 0 11 4 | B1->B0 | 2f2f 3c3c | 0 0 | (0 0) (1 1)
1835 14:46:43.483127 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1836 14:46:43.483180 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1837 14:46:43.483232 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1838 14:46:43.483295 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1839 14:46:43.483348 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1840 14:46:43.483400 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 14:46:43.483458 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 14:46:43.483512 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1843 14:46:43.483564 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1844 14:46:43.483622 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1845 14:46:43.483676 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1846 14:46:43.483731 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1847 14:46:43.483801 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 14:46:43.483894 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 14:46:43.483977 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 14:46:43.484066 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 14:46:43.484148 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 14:46:43.484235 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 14:46:43.484318 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 14:46:43.484409 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 14:46:43.484493 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 14:46:43.484574 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 14:46:43.484664 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 14:46:43.484747 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1859 14:46:43.484837 Total UI for P1: 0, mck2ui 16
1860 14:46:43.484920 best dqsien dly found for B0: ( 0, 14, 2)
1861 14:46:43.485010 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 14:46:43.485091 Total UI for P1: 0, mck2ui 16
1863 14:46:43.485180 best dqsien dly found for B1: ( 0, 14, 4)
1864 14:46:43.485272 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1865 14:46:43.485328 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1866 14:46:43.485388
1867 14:46:43.485441 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1868 14:46:43.485494 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1869 14:46:43.485546 [Gating] SW calibration Done
1870 14:46:43.485605 ==
1871 14:46:43.485658 Dram Type= 6, Freq= 0, CH_1, rank 1
1872 14:46:43.485710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1873 14:46:43.485781 ==
1874 14:46:43.485836 RX Vref Scan: 0
1875 14:46:43.485888
1876 14:46:43.485946 RX Vref 0 -> 0, step: 1
1877 14:46:43.486000
1878 14:46:43.486052 RX Delay -130 -> 252, step: 16
1879 14:46:43.486105 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1880 14:46:43.486164 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1881 14:46:43.486231 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1882 14:46:43.486284 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1883 14:46:43.486343 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1884 14:46:43.486396 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1885 14:46:43.486447 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1886 14:46:43.486499 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1887 14:46:43.486558 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1888 14:46:43.486611 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1889 14:46:43.486663 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1890 14:46:43.486722 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1891 14:46:43.486775 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1892 14:46:43.486827 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1893 14:46:43.486884 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1894 14:46:43.486938 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1895 14:46:43.486990 ==
1896 14:46:43.487041 Dram Type= 6, Freq= 0, CH_1, rank 1
1897 14:46:43.487105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1898 14:46:43.487160 ==
1899 14:46:43.487212 DQS Delay:
1900 14:46:43.487263 DQS0 = 0, DQS1 = 0
1901 14:46:43.487326 DQM Delay:
1902 14:46:43.487378 DQM0 = 85, DQM1 = 84
1903 14:46:43.487429 DQ Delay:
1904 14:46:43.487489 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =77
1905 14:46:43.487541 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1906 14:46:43.487593 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1907 14:46:43.487645 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1908 14:46:43.487704
1909 14:46:43.487763
1910 14:46:43.487814 ==
1911 14:46:43.487876 Dram Type= 6, Freq= 0, CH_1, rank 1
1912 14:46:43.487947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1913 14:46:43.488003 ==
1914 14:46:43.488064
1915 14:46:43.488121
1916 14:46:43.488203 TX Vref Scan disable
1917 14:46:43.488292 == TX Byte 0 ==
1918 14:46:43.488374 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1919 14:46:43.740706 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1920 14:46:43.741369 == TX Byte 1 ==
1921 14:46:43.741881 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1922 14:46:43.742554 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1923 14:46:43.743205 ==
1924 14:46:43.743783 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 14:46:43.744419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 14:46:43.745014 ==
1927 14:46:43.745572 TX Vref=22, minBit 0, minWin=27, winSum=443
1928 14:46:43.745962 TX Vref=24, minBit 0, minWin=27, winSum=446
1929 14:46:43.746411 TX Vref=26, minBit 1, minWin=27, winSum=449
1930 14:46:43.747407 TX Vref=28, minBit 0, minWin=28, winSum=456
1931 14:46:43.748031 TX Vref=30, minBit 3, minWin=27, winSum=453
1932 14:46:43.748643 TX Vref=32, minBit 3, minWin=27, winSum=453
1933 14:46:43.749298 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 28
1934 14:46:43.749885
1935 14:46:43.750525 Final TX Range 1 Vref 28
1936 14:46:43.751104
1937 14:46:43.751621 ==
1938 14:46:43.752089 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 14:46:43.752814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 14:46:43.753398 ==
1941 14:46:43.753989
1942 14:46:43.754621
1943 14:46:43.755191 TX Vref Scan disable
1944 14:46:43.755768 == TX Byte 0 ==
1945 14:46:43.756411 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1946 14:46:43.757021 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1947 14:46:43.757633 == TX Byte 1 ==
1948 14:46:43.758215 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1949 14:46:43.758824 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1950 14:46:43.759325
1951 14:46:43.759782 [DATLAT]
1952 14:46:43.760251 Freq=800, CH1 RK1
1953 14:46:43.760755
1954 14:46:43.761207 DATLAT Default: 0xa
1955 14:46:43.761475 0, 0xFFFF, sum = 0
1956 14:46:43.761796 1, 0xFFFF, sum = 0
1957 14:46:43.762139 2, 0xFFFF, sum = 0
1958 14:46:43.762493 3, 0xFFFF, sum = 0
1959 14:46:43.762812 4, 0xFFFF, sum = 0
1960 14:46:43.763129 5, 0xFFFF, sum = 0
1961 14:46:43.763443 6, 0xFFFF, sum = 0
1962 14:46:43.763754 7, 0xFFFF, sum = 0
1963 14:46:43.764069 8, 0xFFFF, sum = 0
1964 14:46:43.764380 9, 0x0, sum = 1
1965 14:46:43.764693 10, 0x0, sum = 2
1966 14:46:43.765017 11, 0x0, sum = 3
1967 14:46:43.765351 12, 0x0, sum = 4
1968 14:46:43.765575 best_step = 10
1969 14:46:43.765823
1970 14:46:43.766081 ==
1971 14:46:43.766360 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 14:46:43.766600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 14:46:43.766835 ==
1974 14:46:43.767085 RX Vref Scan: 0
1975 14:46:43.767312
1976 14:46:43.767542 RX Vref 0 -> 0, step: 1
1977 14:46:43.767770
1978 14:46:43.768005 RX Delay -95 -> 252, step: 8
1979 14:46:43.768245 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1980 14:46:43.768478 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1981 14:46:43.768712 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1982 14:46:43.768969 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1983 14:46:43.769236 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1984 14:46:43.769433 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1985 14:46:43.769595 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1986 14:46:43.769747 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1987 14:46:43.769904 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1988 14:46:43.770115 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
1989 14:46:43.770352 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
1990 14:46:43.770586 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1991 14:46:43.770822 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1992 14:46:43.771054 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1993 14:46:43.771278 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1994 14:46:43.771466 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1995 14:46:43.771648 ==
1996 14:46:43.771834 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 14:46:43.772050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 14:46:43.772244 ==
1999 14:46:43.772426 DQS Delay:
2000 14:46:43.772557 DQS0 = 0, DQS1 = 0
2001 14:46:43.772703 DQM Delay:
2002 14:46:43.772890 DQM0 = 86, DQM1 = 83
2003 14:46:43.773091 DQ Delay:
2004 14:46:43.773337 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2005 14:46:43.773521 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2006 14:46:43.773698 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =76
2007 14:46:43.773852 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2008 14:46:43.774073
2009 14:46:43.774282
2010 14:46:43.774498 [DQSOSCAuto] RK1, (LSB)MR18= 0x233f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 401 ps
2011 14:46:43.774717 CH1 RK1: MR19=606, MR18=233F
2012 14:46:43.774938 CH1_RK1: MR19=0x606, MR18=0x233F, DQSOSC=393, MR23=63, INC=95, DEC=63
2013 14:46:43.775155 [RxdqsGatingPostProcess] freq 800
2014 14:46:43.775367 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2015 14:46:43.775580 Pre-setting of DQS Precalculation
2016 14:46:43.775792 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2017 14:46:43.776029 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2018 14:46:43.776250 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2019 14:46:43.776429
2020 14:46:43.776603
2021 14:46:43.776781 [Calibration Summary] 1600 Mbps
2022 14:46:43.776957 CH 0, Rank 0
2023 14:46:43.777135 SW Impedance : PASS
2024 14:46:43.777317 DUTY Scan : NO K
2025 14:46:43.777495 ZQ Calibration : PASS
2026 14:46:43.777668 Jitter Meter : NO K
2027 14:46:43.777833 CBT Training : PASS
2028 14:46:43.778024 Write leveling : PASS
2029 14:46:43.778189 RX DQS gating : PASS
2030 14:46:43.778367 RX DQ/DQS(RDDQC) : PASS
2031 14:46:43.778545 TX DQ/DQS : PASS
2032 14:46:43.778721 RX DATLAT : PASS
2033 14:46:43.778901 RX DQ/DQS(Engine): PASS
2034 14:46:43.779092 TX OE : NO K
2035 14:46:43.779272 All Pass.
2036 14:46:43.779450
2037 14:46:43.779623 CH 0, Rank 1
2038 14:46:43.779792 SW Impedance : PASS
2039 14:46:43.779965 DUTY Scan : NO K
2040 14:46:43.780130 ZQ Calibration : PASS
2041 14:46:43.780303 Jitter Meter : NO K
2042 14:46:43.780480 CBT Training : PASS
2043 14:46:43.780656 Write leveling : PASS
2044 14:46:43.780834 RX DQS gating : PASS
2045 14:46:43.781013 RX DQ/DQS(RDDQC) : PASS
2046 14:46:43.781197 TX DQ/DQS : PASS
2047 14:46:43.781364 RX DATLAT : PASS
2048 14:46:43.781508 RX DQ/DQS(Engine): PASS
2049 14:46:43.781639 TX OE : NO K
2050 14:46:43.781774 All Pass.
2051 14:46:43.781899
2052 14:46:43.781984 CH 1, Rank 0
2053 14:46:43.782074 SW Impedance : PASS
2054 14:46:43.782161 DUTY Scan : NO K
2055 14:46:43.782249 ZQ Calibration : PASS
2056 14:46:43.782336 Jitter Meter : NO K
2057 14:46:43.782422 CBT Training : PASS
2058 14:46:43.782511 Write leveling : PASS
2059 14:46:43.782593 RX DQS gating : PASS
2060 14:46:43.782701 RX DQ/DQS(RDDQC) : PASS
2061 14:46:43.782785 TX DQ/DQS : PASS
2062 14:46:43.782879 RX DATLAT : PASS
2063 14:46:43.782961 RX DQ/DQS(Engine): PASS
2064 14:46:43.783079 TX OE : NO K
2065 14:46:43.783217 All Pass.
2066 14:46:43.783345
2067 14:46:43.783478 CH 1, Rank 1
2068 14:46:43.783606 SW Impedance : PASS
2069 14:46:43.783693 DUTY Scan : NO K
2070 14:46:43.783782 ZQ Calibration : PASS
2071 14:46:43.783867 Jitter Meter : NO K
2072 14:46:43.783949 CBT Training : PASS
2073 14:46:43.784046 Write leveling : PASS
2074 14:46:43.784130 RX DQS gating : PASS
2075 14:46:43.784225 RX DQ/DQS(RDDQC) : PASS
2076 14:46:43.784308 TX DQ/DQS : PASS
2077 14:46:43.784402 RX DATLAT : PASS
2078 14:46:43.784485 RX DQ/DQS(Engine): PASS
2079 14:46:43.784579 TX OE : NO K
2080 14:46:43.784664 All Pass.
2081 14:46:43.784759
2082 14:46:43.784888 DramC Write-DBI off
2083 14:46:43.785023 PER_BANK_REFRESH: Hybrid Mode
2084 14:46:43.785391 TX_TRACKING: ON
2085 14:46:43.785489 [GetDramInforAfterCalByMRR] Vendor 6.
2086 14:46:43.785585 [GetDramInforAfterCalByMRR] Revision 606.
2087 14:46:43.785668 [GetDramInforAfterCalByMRR] Revision 2 0.
2088 14:46:43.785765 MR0 0x3b3b
2089 14:46:43.785847 MR8 0x5151
2090 14:46:43.785941 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2091 14:46:43.786039
2092 14:46:43.786134 MR0 0x3b3b
2093 14:46:43.786225 MR8 0x5151
2094 14:46:43.786307 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2095 14:46:43.786381
2096 14:46:43.786455 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2097 14:46:43.786537 [FAST_K] Save calibration result to emmc
2098 14:46:43.786610 [FAST_K] Save calibration result to emmc
2099 14:46:43.786694 dram_init: config_dvfs: 1
2100 14:46:43.786768 dramc_set_vcore_voltage set vcore to 662500
2101 14:46:43.786844 Read voltage for 1200, 2
2102 14:46:43.786922 Vio18 = 0
2103 14:46:43.786993 Vcore = 662500
2104 14:46:43.787075 Vdram = 0
2105 14:46:43.787160 Vddq = 0
2106 14:46:43.787239 Vmddr = 0
2107 14:46:43.787314 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2108 14:46:43.787387 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2109 14:46:43.787474 MEM_TYPE=3, freq_sel=15
2110 14:46:43.787547 sv_algorithm_assistance_LP4_1600
2111 14:46:43.787627 ============ PULL DRAM RESETB DOWN ============
2112 14:46:43.787701 ========== PULL DRAM RESETB DOWN end =========
2113 14:46:43.787775 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2114 14:46:43.787857 ===================================
2115 14:46:43.787931 LPDDR4 DRAM CONFIGURATION
2116 14:46:43.788009 ===================================
2117 14:46:43.788084 EX_ROW_EN[0] = 0x0
2118 14:46:43.788156 EX_ROW_EN[1] = 0x0
2119 14:46:43.788243 LP4Y_EN = 0x0
2120 14:46:43.788316 WORK_FSP = 0x0
2121 14:46:43.788396 WL = 0x4
2122 14:46:43.788483 RL = 0x4
2123 14:46:43.788559 BL = 0x2
2124 14:46:43.788638 RPST = 0x0
2125 14:46:43.788710 RD_PRE = 0x0
2126 14:46:43.788789 WR_PRE = 0x1
2127 14:46:43.788863 WR_PST = 0x0
2128 14:46:43.788943 DBI_WR = 0x0
2129 14:46:43.789018 DBI_RD = 0x0
2130 14:46:43.789090 OTF = 0x1
2131 14:46:43.789186 ===================================
2132 14:46:43.789271 ===================================
2133 14:46:43.789355 ANA top config
2134 14:46:43.789429 ===================================
2135 14:46:43.789502 DLL_ASYNC_EN = 0
2136 14:46:43.789583 ALL_SLAVE_EN = 0
2137 14:46:43.789655 NEW_RANK_MODE = 1
2138 14:46:43.789739 DLL_IDLE_MODE = 1
2139 14:46:43.789813 LP45_APHY_COMB_EN = 1
2140 14:46:43.789885 TX_ODT_DIS = 1
2141 14:46:43.789965 NEW_8X_MODE = 1
2142 14:46:43.790038 ===================================
2143 14:46:43.790118 ===================================
2144 14:46:43.790192 data_rate = 2400
2145 14:46:43.790264 CKR = 1
2146 14:46:43.790344 DQ_P2S_RATIO = 8
2147 14:46:43.790417 ===================================
2148 14:46:43.790496 CA_P2S_RATIO = 8
2149 14:46:43.790570 DQ_CA_OPEN = 0
2150 14:46:43.790641 DQ_SEMI_OPEN = 0
2151 14:46:43.790720 CA_SEMI_OPEN = 0
2152 14:46:43.790792 CA_FULL_RATE = 0
2153 14:46:43.790871 DQ_CKDIV4_EN = 0
2154 14:46:43.790946 CA_CKDIV4_EN = 0
2155 14:46:43.791017 CA_PREDIV_EN = 0
2156 14:46:43.791105 PH8_DLY = 17
2157 14:46:43.791209 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2158 14:46:43.791283 DQ_AAMCK_DIV = 4
2159 14:46:43.791349 CA_AAMCK_DIV = 4
2160 14:46:43.791413 CA_ADMCK_DIV = 4
2161 14:46:43.791484 DQ_TRACK_CA_EN = 0
2162 14:46:43.791548 CA_PICK = 1200
2163 14:46:43.791612 CA_MCKIO = 1200
2164 14:46:43.791683 MCKIO_SEMI = 0
2165 14:46:43.791747 PLL_FREQ = 2366
2166 14:46:43.791816 DQ_UI_PI_RATIO = 32
2167 14:46:43.791885 CA_UI_PI_RATIO = 0
2168 14:46:43.791950 ===================================
2169 14:46:43.792020 ===================================
2170 14:46:43.792087 memory_type:LPDDR4
2171 14:46:43.792151 GP_NUM : 10
2172 14:46:43.792221 SRAM_EN : 1
2173 14:46:43.792286 MD32_EN : 0
2174 14:46:43.792349 ===================================
2175 14:46:43.792424 [ANA_INIT] >>>>>>>>>>>>>>
2176 14:46:43.792500 <<<<<< [CONFIGURE PHASE]: ANA_TX
2177 14:46:43.792567 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2178 14:46:43.792639 ===================================
2179 14:46:43.792704 data_rate = 2400,PCW = 0X5b00
2180 14:46:43.792774 ===================================
2181 14:46:43.792843 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2182 14:46:43.792907 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2183 14:46:43.792979 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2184 14:46:43.793045 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2185 14:46:43.793114 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2186 14:46:43.793194 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2187 14:46:43.793264 [ANA_INIT] flow start
2188 14:46:43.793329 [ANA_INIT] PLL >>>>>>>>
2189 14:46:43.793409 [ANA_INIT] PLL <<<<<<<<
2190 14:46:43.793475 [ANA_INIT] MIDPI >>>>>>>>
2191 14:46:43.793542 [ANA_INIT] MIDPI <<<<<<<<
2192 14:46:43.793609 [ANA_INIT] DLL >>>>>>>>
2193 14:46:43.793673 [ANA_INIT] DLL <<<<<<<<
2194 14:46:43.793742 [ANA_INIT] flow end
2195 14:46:43.793808 ============ LP4 DIFF to SE enter ============
2196 14:46:43.793873 ============ LP4 DIFF to SE exit ============
2197 14:46:43.793947 [ANA_INIT] <<<<<<<<<<<<<
2198 14:46:43.794014 [Flow] Enable top DCM control >>>>>
2199 14:46:43.794079 [Flow] Enable top DCM control <<<<<
2200 14:46:43.794152 Enable DLL master slave shuffle
2201 14:46:43.794217 ==============================================================
2202 14:46:43.794282 Gating Mode config
2203 14:46:43.794354 ==============================================================
2204 14:46:43.794419 Config description:
2205 14:46:43.794484 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2206 14:46:43.794557 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2207 14:46:43.794831 SELPH_MODE 0: By rank 1: By Phase
2208 14:46:43.794911 ==============================================================
2209 14:46:43.794980 GAT_TRACK_EN = 1
2210 14:46:43.795045 RX_GATING_MODE = 2
2211 14:46:43.795133 RX_GATING_TRACK_MODE = 2
2212 14:46:43.795199 SELPH_MODE = 1
2213 14:46:43.795269 PICG_EARLY_EN = 1
2214 14:46:43.795339 VALID_LAT_VALUE = 1
2215 14:46:43.795403 ==============================================================
2216 14:46:43.795474 Enter into Gating configuration >>>>
2217 14:46:43.795540 Exit from Gating configuration <<<<
2218 14:46:43.795605 Enter into DVFS_PRE_config >>>>>
2219 14:46:43.795680 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2220 14:46:43.795788 Exit from DVFS_PRE_config <<<<<
2221 14:46:43.795880 Enter into PICG configuration >>>>
2222 14:46:43.795947 Exit from PICG configuration <<<<
2223 14:46:43.796011 [RX_INPUT] configuration >>>>>
2224 14:46:43.796084 [RX_INPUT] configuration <<<<<
2225 14:46:43.796149 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2226 14:46:43.796227 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2227 14:46:43.796289 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2228 14:46:43.796347 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2229 14:46:43.796406 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2230 14:46:43.796471 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2231 14:46:43.796530 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2232 14:46:43.796588 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2233 14:46:43.796656 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2234 14:46:43.796715 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2235 14:46:43.796773 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2236 14:46:43.796838 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2237 14:46:43.796897 ===================================
2238 14:46:43.796955 LPDDR4 DRAM CONFIGURATION
2239 14:46:43.797018 ===================================
2240 14:46:43.797077 EX_ROW_EN[0] = 0x0
2241 14:46:43.797150 EX_ROW_EN[1] = 0x0
2242 14:46:43.797270 LP4Y_EN = 0x0
2243 14:46:43.797364 WORK_FSP = 0x0
2244 14:46:43.797476 WL = 0x4
2245 14:46:43.797569 RL = 0x4
2246 14:46:43.797677 BL = 0x2
2247 14:46:43.797770 RPST = 0x0
2248 14:46:43.797874 RD_PRE = 0x0
2249 14:46:43.797969 WR_PRE = 0x1
2250 14:46:43.798074 WR_PST = 0x0
2251 14:46:43.798174 DBI_WR = 0x0
2252 14:46:43.798273 DBI_RD = 0x0
2253 14:46:43.798373 OTF = 0x1
2254 14:46:43.798448 ===================================
2255 14:46:43.798520 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2256 14:46:43.798616 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2257 14:46:43.798676 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2258 14:46:43.798745 ===================================
2259 14:46:43.798830 LPDDR4 DRAM CONFIGURATION
2260 14:46:43.798889 ===================================
2261 14:46:43.799017 EX_ROW_EN[0] = 0x10
2262 14:46:43.799148 EX_ROW_EN[1] = 0x0
2263 14:46:43.799278 LP4Y_EN = 0x0
2264 14:46:43.799408 WORK_FSP = 0x0
2265 14:46:43.799536 WL = 0x4
2266 14:46:43.799664 RL = 0x4
2267 14:46:43.799765 BL = 0x2
2268 14:46:43.799856 RPST = 0x0
2269 14:46:43.799955 RD_PRE = 0x0
2270 14:46:43.800046 WR_PRE = 0x1
2271 14:46:43.800144 WR_PST = 0x0
2272 14:46:43.800234 DBI_WR = 0x0
2273 14:46:43.800311 DBI_RD = 0x0
2274 14:46:43.800370 OTF = 0x1
2275 14:46:43.800428 ===================================
2276 14:46:43.800517 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2277 14:46:43.800608 ==
2278 14:46:43.800707 Dram Type= 6, Freq= 0, CH_0, rank 0
2279 14:46:43.800799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2280 14:46:43.800898 ==
2281 14:46:43.800989 [Duty_Offset_Calibration]
2282 14:46:43.801087 B0:2 B1:0 CA:4
2283 14:46:43.801191
2284 14:46:43.801281 [DutyScan_Calibration_Flow] k_type=0
2285 14:46:43.801337
2286 14:46:43.801390 ==CLK 0==
2287 14:46:43.801459 Final CLK duty delay cell = -4
2288 14:46:43.801514 [-4] MAX Duty = 5031%(X100), DQS PI = 32
2289 14:46:43.801567 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2290 14:46:43.801632 [-4] AVG Duty = 4937%(X100)
2291 14:46:43.801686
2292 14:46:43.801739 CH0 CLK Duty spec in!! Max-Min= 187%
2293 14:46:43.801793 [DutyScan_Calibration_Flow] ====Done====
2294 14:46:43.801881
2295 14:46:43.801963 [DutyScan_Calibration_Flow] k_type=1
2296 14:46:43.802053
2297 14:46:43.802134 ==DQS 0 ==
2298 14:46:43.802223 Final DQS duty delay cell = 0
2299 14:46:43.802306 [0] MAX Duty = 5156%(X100), DQS PI = 18
2300 14:46:43.802394 [0] MIN Duty = 5093%(X100), DQS PI = 0
2301 14:46:43.802476 [0] AVG Duty = 5124%(X100)
2302 14:46:43.802558
2303 14:46:43.802644 ==DQS 1 ==
2304 14:46:43.802736 Final DQS duty delay cell = 0
2305 14:46:43.802828 [0] MAX Duty = 5125%(X100), DQS PI = 4
2306 14:46:43.802910 [0] MIN Duty = 4969%(X100), DQS PI = 14
2307 14:46:43.802998 [0] AVG Duty = 5047%(X100)
2308 14:46:43.803079
2309 14:46:43.803166 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2310 14:46:43.803249
2311 14:46:43.803335 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2312 14:46:43.803421 [DutyScan_Calibration_Flow] ====Done====
2313 14:46:43.803501
2314 14:46:43.803590 [DutyScan_Calibration_Flow] k_type=3
2315 14:46:43.803672
2316 14:46:43.803760 ==DQM 0 ==
2317 14:46:43.803842 Final DQM duty delay cell = 0
2318 14:46:43.803936 [0] MAX Duty = 5062%(X100), DQS PI = 18
2319 14:46:43.804020 [0] MIN Duty = 4844%(X100), DQS PI = 52
2320 14:46:43.804107 [0] AVG Duty = 4953%(X100)
2321 14:46:43.804190
2322 14:46:43.804270 ==DQM 1 ==
2323 14:46:43.804343 Final DQM duty delay cell = 0
2324 14:46:43.804398 [0] MAX Duty = 4969%(X100), DQS PI = 2
2325 14:46:43.804449 [0] MIN Duty = 4875%(X100), DQS PI = 20
2326 14:46:43.804526 [0] AVG Duty = 4922%(X100)
2327 14:46:43.804588
2328 14:46:43.804643 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2329 14:46:43.804717
2330 14:46:43.804799 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2331 14:46:43.804887 [DutyScan_Calibration_Flow] ====Done====
2332 14:46:43.804970
2333 14:46:43.805055 [DutyScan_Calibration_Flow] k_type=2
2334 14:46:43.805139
2335 14:46:43.805219 ==DQ 0 ==
2336 14:46:43.805303 Final DQ duty delay cell = 0
2337 14:46:43.805360 [0] MAX Duty = 5125%(X100), DQS PI = 18
2338 14:46:43.805414 [0] MIN Duty = 4969%(X100), DQS PI = 52
2339 14:46:43.805687 [0] AVG Duty = 5047%(X100)
2340 14:46:43.805749
2341 14:46:43.805806 ==DQ 1 ==
2342 14:46:43.805895 Final DQ duty delay cell = 0
2343 14:46:43.805979 [0] MAX Duty = 5156%(X100), DQS PI = 6
2344 14:46:43.806068 [0] MIN Duty = 4938%(X100), DQS PI = 14
2345 14:46:43.806150 [0] AVG Duty = 5047%(X100)
2346 14:46:43.806252
2347 14:46:43.806334 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2348 14:46:43.806420
2349 14:46:43.806502 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2350 14:46:43.806584 [DutyScan_Calibration_Flow] ====Done====
2351 14:46:43.806678 ==
2352 14:46:43.806766 Dram Type= 6, Freq= 0, CH_1, rank 0
2353 14:46:43.806854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2354 14:46:43.806935 ==
2355 14:46:43.807022 [Duty_Offset_Calibration]
2356 14:46:43.807102 B0:0 B1:-1 CA:3
2357 14:46:43.807188
2358 14:46:43.807269 [DutyScan_Calibration_Flow] k_type=0
2359 14:46:43.807348
2360 14:46:43.807434 ==CLK 0==
2361 14:46:43.807515 Final CLK duty delay cell = -4
2362 14:46:43.807603 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2363 14:46:43.807684 [-4] MIN Duty = 4876%(X100), DQS PI = 34
2364 14:46:43.807770 [-4] AVG Duty = 4938%(X100)
2365 14:46:43.807851
2366 14:46:43.807930 CH1 CLK Duty spec in!! Max-Min= 124%
2367 14:46:43.808018 [DutyScan_Calibration_Flow] ====Done====
2368 14:46:43.808098
2369 14:46:43.808186 [DutyScan_Calibration_Flow] k_type=1
2370 14:46:43.808265
2371 14:46:43.808347 ==DQS 0 ==
2372 14:46:43.808402 Final DQS duty delay cell = 0
2373 14:46:43.808454 [0] MAX Duty = 5156%(X100), DQS PI = 18
2374 14:46:43.808525 [0] MIN Duty = 4907%(X100), DQS PI = 38
2375 14:46:43.808581 [0] AVG Duty = 5031%(X100)
2376 14:46:43.808632
2377 14:46:43.808682 ==DQS 1 ==
2378 14:46:43.808762 Final DQS duty delay cell = 0
2379 14:46:43.808857 [0] MAX Duty = 5156%(X100), DQS PI = 8
2380 14:46:43.808948 [0] MIN Duty = 5000%(X100), DQS PI = 24
2381 14:46:43.809029 [0] AVG Duty = 5078%(X100)
2382 14:46:43.809114
2383 14:46:43.809195 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2384 14:46:43.809321
2385 14:46:43.809391 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2386 14:46:43.809442 [DutyScan_Calibration_Flow] ====Done====
2387 14:46:43.809507
2388 14:46:43.809559 [DutyScan_Calibration_Flow] k_type=3
2389 14:46:43.809619
2390 14:46:43.809675 ==DQM 0 ==
2391 14:46:43.809735 Final DQM duty delay cell = 0
2392 14:46:43.809787 [0] MAX Duty = 5031%(X100), DQS PI = 28
2393 14:46:43.809838 [0] MIN Duty = 4813%(X100), DQS PI = 36
2394 14:46:43.809926 [0] AVG Duty = 4922%(X100)
2395 14:46:43.810006
2396 14:46:43.810093 ==DQM 1 ==
2397 14:46:43.810173 Final DQM duty delay cell = 0
2398 14:46:43.810261 [0] MAX Duty = 5000%(X100), DQS PI = 34
2399 14:46:43.810343 [0] MIN Duty = 4844%(X100), DQS PI = 0
2400 14:46:43.810423 [0] AVG Duty = 4922%(X100)
2401 14:46:43.810510
2402 14:46:43.810590 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2403 14:46:43.810678
2404 14:46:43.810759 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2405 14:46:43.810844 [DutyScan_Calibration_Flow] ====Done====
2406 14:46:43.810925
2407 14:46:43.811004 [DutyScan_Calibration_Flow] k_type=2
2408 14:46:43.811091
2409 14:46:43.811170 ==DQ 0 ==
2410 14:46:43.811258 Final DQ duty delay cell = -4
2411 14:46:43.811340 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2412 14:46:43.811428 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2413 14:46:43.811509 [-4] AVG Duty = 4937%(X100)
2414 14:46:43.811595
2415 14:46:43.811676 ==DQ 1 ==
2416 14:46:43.811756 Final DQ duty delay cell = 4
2417 14:46:43.811854 [4] MAX Duty = 5187%(X100), DQS PI = 34
2418 14:46:43.811935 [4] MIN Duty = 5062%(X100), DQS PI = 0
2419 14:46:43.812024 [4] AVG Duty = 5124%(X100)
2420 14:46:43.812103
2421 14:46:43.812190 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2422 14:46:43.812272
2423 14:46:43.812352 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2424 14:46:43.812418 [DutyScan_Calibration_Flow] ====Done====
2425 14:46:43.812469 nWR fixed to 30
2426 14:46:43.812521 [ModeRegInit_LP4] CH0 RK0
2427 14:46:43.812587 [ModeRegInit_LP4] CH0 RK1
2428 14:46:43.812639 [ModeRegInit_LP4] CH1 RK0
2429 14:46:43.812691 [ModeRegInit_LP4] CH1 RK1
2430 14:46:43.812746 match AC timing 7
2431 14:46:43.812833 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2432 14:46:43.812913 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2433 14:46:43.813002 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2434 14:46:43.813084 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2435 14:46:43.813174 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2436 14:46:43.813254 ==
2437 14:46:43.813367 Dram Type= 6, Freq= 0, CH_0, rank 0
2438 14:46:43.813421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2439 14:46:43.813473 ==
2440 14:46:43.813536 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2441 14:46:43.813589 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2442 14:46:43.813641 [CA 0] Center 39 (9~70) winsize 62
2443 14:46:43.813697 [CA 1] Center 39 (9~69) winsize 61
2444 14:46:43.813758 [CA 2] Center 35 (5~66) winsize 62
2445 14:46:43.813810 [CA 3] Center 35 (5~66) winsize 62
2446 14:46:43.813862 [CA 4] Center 33 (3~64) winsize 62
2447 14:46:43.813932 [CA 5] Center 33 (3~64) winsize 62
2448 14:46:43.814012
2449 14:46:43.814098 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2450 14:46:43.814182
2451 14:46:43.814262 [CATrainingPosCal] consider 1 rank data
2452 14:46:43.814351 u2DelayCellTimex100 = 270/100 ps
2453 14:46:43.814431 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2454 14:46:43.814519 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2455 14:46:43.814600 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2456 14:46:43.814697 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2457 14:46:43.814778 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2458 14:46:43.814862 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2459 14:46:43.814944
2460 14:46:43.815024 CA PerBit enable=1, Macro0, CA PI delay=33
2461 14:46:43.815113
2462 14:46:43.815193 [CBTSetCACLKResult] CA Dly = 33
2463 14:46:43.815280 CS Dly: 7 (0~38)
2464 14:46:43.815360 ==
2465 14:46:43.815446 Dram Type= 6, Freq= 0, CH_0, rank 1
2466 14:46:43.815529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2467 14:46:43.815609 ==
2468 14:46:43.815699 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2469 14:46:43.815790 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2470 14:46:43.815880 [CA 0] Center 39 (9~70) winsize 62
2471 14:46:43.815961 [CA 1] Center 39 (9~70) winsize 62
2472 14:46:43.816048 [CA 2] Center 35 (5~66) winsize 62
2473 14:46:43.816129 [CA 3] Center 35 (5~66) winsize 62
2474 14:46:43.816216 [CA 4] Center 34 (4~65) winsize 62
2475 14:46:43.816297 [CA 5] Center 33 (3~63) winsize 61
2476 14:46:43.816380
2477 14:46:43.816464 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2478 14:46:43.816543
2479 14:46:43.816632 [CATrainingPosCal] consider 2 rank data
2480 14:46:43.816713 u2DelayCellTimex100 = 270/100 ps
2481 14:46:43.816802 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2482 14:46:43.817083 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2483 14:46:43.817176 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2484 14:46:43.817268 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2485 14:46:43.817364 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2486 14:46:43.817421 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2487 14:46:43.817472
2488 14:46:43.817522 CA PerBit enable=1, Macro0, CA PI delay=33
2489 14:46:43.817595
2490 14:46:43.817648 [CBTSetCACLKResult] CA Dly = 33
2491 14:46:43.817699 CS Dly: 8 (0~41)
2492 14:46:43.817772
2493 14:46:43.817824 ----->DramcWriteLeveling(PI) begin...
2494 14:46:43.817877 ==
2495 14:46:43.817935 Dram Type= 6, Freq= 0, CH_0, rank 0
2496 14:46:43.818020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2497 14:46:43.818100 ==
2498 14:46:43.818174 Write leveling (Byte 0): 33 => 33
2499 14:46:43.818227 Write leveling (Byte 1): 27 => 27
2500 14:46:43.818278 DramcWriteLeveling(PI) end<-----
2501 14:46:43.818363
2502 14:46:43.818443 ==
2503 14:46:43.818544 Dram Type= 6, Freq= 0, CH_0, rank 0
2504 14:46:43.818626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2505 14:46:43.818710 ==
2506 14:46:43.818764 [Gating] SW mode calibration
2507 14:46:43.818816 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2508 14:46:43.818872 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2509 14:46:43.818936 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2510 14:46:43.818988 0 15 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2511 14:46:43.819040 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2512 14:46:43.819112 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2513 14:46:43.819165 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2514 14:46:43.819217 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2515 14:46:43.819273 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2516 14:46:43.819335 0 15 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 1)
2517 14:46:43.819387 1 0 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
2518 14:46:43.819439 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2519 14:46:43.819511 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2520 14:46:43.819562 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2521 14:46:43.819613 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2522 14:46:43.819677 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 14:46:43.819759 1 0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2524 14:46:43.819843 1 0 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
2525 14:46:43.819905 1 1 0 | B1->B0 | 2a2a 4646 | 1 0 | (0 0) (0 0)
2526 14:46:43.819964 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2527 14:46:43.820015 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2528 14:46:43.820103 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2529 14:46:43.820184 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2530 14:46:43.820274 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 14:46:43.820356 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 14:46:43.820441 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2533 14:46:43.820496 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2534 14:46:43.820547 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2535 14:46:43.820598 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2536 14:46:43.820680 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2537 14:46:43.820733 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2538 14:46:43.820784 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 14:46:43.820871 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 14:46:43.820952 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 14:46:43.821044 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 14:46:43.821125 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 14:46:43.821215 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 14:46:43.821334 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 14:46:43.821396 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 14:46:43.821452 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 14:46:43.821514 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2548 14:46:43.821573 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2549 14:46:43.821659 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2550 14:46:43.821739 Total UI for P1: 0, mck2ui 16
2551 14:46:43.821829 best dqsien dly found for B0: ( 1, 3, 26)
2552 14:46:43.821910 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2553 14:46:43.821996 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 14:46:43.822050 Total UI for P1: 0, mck2ui 16
2555 14:46:43.822102 best dqsien dly found for B1: ( 1, 4, 2)
2556 14:46:43.822163 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2557 14:46:43.822219 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2558 14:46:43.822270
2559 14:46:43.822321 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2560 14:46:43.822393 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2561 14:46:43.822446 [Gating] SW calibration Done
2562 14:46:43.822497 ==
2563 14:46:43.822571 Dram Type= 6, Freq= 0, CH_0, rank 0
2564 14:46:43.822630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2565 14:46:43.822695 ==
2566 14:46:43.822769 RX Vref Scan: 0
2567 14:46:43.822850
2568 14:46:43.822937 RX Vref 0 -> 0, step: 1
2569 14:46:43.822992
2570 14:46:43.823043 RX Delay -40 -> 252, step: 8
2571 14:46:43.823094 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2572 14:46:43.823165 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2573 14:46:43.823218 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2574 14:46:43.823268 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2575 14:46:43.823348 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2576 14:46:43.823429 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2577 14:46:43.823517 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2578 14:46:43.823599 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2579 14:46:43.823680 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2580 14:46:43.823750 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2581 14:46:43.823801 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2582 14:46:43.823852 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2583 14:46:43.823921 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2584 14:46:43.824168 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2585 14:46:43.824228 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2586 14:46:43.824301 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2587 14:46:43.824355 ==
2588 14:46:43.824406 Dram Type= 6, Freq= 0, CH_0, rank 0
2589 14:46:43.824468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2590 14:46:43.824554 ==
2591 14:46:43.824636 DQS Delay:
2592 14:46:43.824703 DQS0 = 0, DQS1 = 0
2593 14:46:43.824765 DQM Delay:
2594 14:46:43.824817 DQM0 = 117, DQM1 = 108
2595 14:46:43.824889 DQ Delay:
2596 14:46:43.824942 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2597 14:46:43.825000 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2598 14:46:43.825088 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2599 14:46:43.825169 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =115
2600 14:46:43.825267
2601 14:46:43.825341
2602 14:46:43.825393 ==
2603 14:46:43.825444 Dram Type= 6, Freq= 0, CH_0, rank 0
2604 14:46:43.825509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2605 14:46:43.825564 ==
2606 14:46:43.825615
2607 14:46:43.825665
2608 14:46:43.825733 TX Vref Scan disable
2609 14:46:43.825785 == TX Byte 0 ==
2610 14:46:43.825836 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2611 14:46:43.825910 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2612 14:46:43.825963 == TX Byte 1 ==
2613 14:46:43.826015 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2614 14:46:43.826079 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2615 14:46:43.826133 ==
2616 14:46:43.826185 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 14:46:43.826241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 14:46:43.826310 ==
2619 14:46:43.826362 TX Vref=22, minBit 4, minWin=25, winSum=414
2620 14:46:43.826414 TX Vref=24, minBit 10, minWin=24, winSum=417
2621 14:46:43.826485 TX Vref=26, minBit 13, minWin=25, winSum=424
2622 14:46:43.826538 TX Vref=28, minBit 5, minWin=26, winSum=430
2623 14:46:43.826589 TX Vref=30, minBit 15, minWin=26, winSum=434
2624 14:46:43.826658 TX Vref=32, minBit 5, minWin=26, winSum=430
2625 14:46:43.826711 [TxChooseVref] Worse bit 15, Min win 26, Win sum 434, Final Vref 30
2626 14:46:43.826800
2627 14:46:43.826880 Final TX Range 1 Vref 30
2628 14:46:43.826969
2629 14:46:43.827049 ==
2630 14:46:43.827140 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 14:46:43.827221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 14:46:43.827305 ==
2633 14:46:43.827365
2634 14:46:43.827416
2635 14:46:43.827466 TX Vref Scan disable
2636 14:46:43.827538 == TX Byte 0 ==
2637 14:46:43.827590 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2638 14:46:43.827641 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2639 14:46:43.827707 == TX Byte 1 ==
2640 14:46:43.827763 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2641 14:46:43.827815 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2642 14:46:43.827866
2643 14:46:43.827938 [DATLAT]
2644 14:46:43.827989 Freq=1200, CH0 RK0
2645 14:46:43.828040
2646 14:46:43.828110 DATLAT Default: 0xd
2647 14:46:43.828162 0, 0xFFFF, sum = 0
2648 14:46:43.828215 1, 0xFFFF, sum = 0
2649 14:46:43.828281 2, 0xFFFF, sum = 0
2650 14:46:43.828337 3, 0xFFFF, sum = 0
2651 14:46:43.828398 4, 0xFFFF, sum = 0
2652 14:46:43.828472 5, 0xFFFF, sum = 0
2653 14:46:43.828555 6, 0xFFFF, sum = 0
2654 14:46:43.828652 7, 0xFFFF, sum = 0
2655 14:46:43.828738 8, 0xFFFF, sum = 0
2656 14:46:43.828823 9, 0xFFFF, sum = 0
2657 14:46:43.828911 10, 0xFFFF, sum = 0
2658 14:46:43.828993 11, 0xFFFF, sum = 0
2659 14:46:43.829069 12, 0x0, sum = 1
2660 14:46:43.829122 13, 0x0, sum = 2
2661 14:46:43.829174 14, 0x0, sum = 3
2662 14:46:43.829246 15, 0x0, sum = 4
2663 14:46:43.829345 best_step = 13
2664 14:46:43.829401
2665 14:46:43.829464 ==
2666 14:46:43.829516 Dram Type= 6, Freq= 0, CH_0, rank 0
2667 14:46:43.829567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2668 14:46:43.829637 ==
2669 14:46:43.829691 RX Vref Scan: 1
2670 14:46:43.829742
2671 14:46:43.829804 Set Vref Range= 32 -> 127
2672 14:46:43.829859
2673 14:46:43.829909 RX Vref 32 -> 127, step: 1
2674 14:46:43.829960
2675 14:46:43.830032 RX Delay -21 -> 252, step: 4
2676 14:46:43.830084
2677 14:46:43.830134 Set Vref, RX VrefLevel [Byte0]: 32
2678 14:46:43.830211 [Byte1]: 32
2679 14:46:43.830291
2680 14:46:43.830385 Set Vref, RX VrefLevel [Byte0]: 33
2681 14:46:43.830467 [Byte1]: 33
2682 14:46:43.830547
2683 14:46:43.830619 Set Vref, RX VrefLevel [Byte0]: 34
2684 14:46:43.830672 [Byte1]: 34
2685 14:46:43.830723
2686 14:46:43.830799 Set Vref, RX VrefLevel [Byte0]: 35
2687 14:46:43.830880 [Byte1]: 35
2688 14:46:43.830968
2689 14:46:43.831023 Set Vref, RX VrefLevel [Byte0]: 36
2690 14:46:43.831075 [Byte1]: 36
2691 14:46:43.831125
2692 14:46:43.831199 Set Vref, RX VrefLevel [Byte0]: 37
2693 14:46:43.831251 [Byte1]: 37
2694 14:46:43.831313
2695 14:46:43.831388 Set Vref, RX VrefLevel [Byte0]: 38
2696 14:46:43.831441 [Byte1]: 38
2697 14:46:43.831492
2698 14:46:43.831564 Set Vref, RX VrefLevel [Byte0]: 39
2699 14:46:43.831618 [Byte1]: 39
2700 14:46:43.831669
2701 14:46:43.831731 Set Vref, RX VrefLevel [Byte0]: 40
2702 14:46:43.831790 [Byte1]: 40
2703 14:46:43.831841
2704 14:46:43.831898 Set Vref, RX VrefLevel [Byte0]: 41
2705 14:46:43.831985 [Byte1]: 41
2706 14:46:43.832064
2707 14:46:43.832155 Set Vref, RX VrefLevel [Byte0]: 42
2708 14:46:43.832236 [Byte1]: 42
2709 14:46:43.832323
2710 14:46:43.832376 Set Vref, RX VrefLevel [Byte0]: 43
2711 14:46:43.832427 [Byte1]: 43
2712 14:46:43.832480
2713 14:46:43.832568 Set Vref, RX VrefLevel [Byte0]: 44
2714 14:46:43.832648 [Byte1]: 44
2715 14:46:43.832727
2716 14:46:43.832780 Set Vref, RX VrefLevel [Byte0]: 45
2717 14:46:43.832832 [Byte1]: 45
2718 14:46:43.832900
2719 14:46:43.832954 Set Vref, RX VrefLevel [Byte0]: 46
2720 14:46:43.833004 [Byte1]: 46
2721 14:46:43.833059
2722 14:46:43.833148 Set Vref, RX VrefLevel [Byte0]: 47
2723 14:46:43.833228 [Byte1]: 47
2724 14:46:43.833345
2725 14:46:43.833398 Set Vref, RX VrefLevel [Byte0]: 48
2726 14:46:43.833461 [Byte1]: 48
2727 14:46:43.833517
2728 14:46:43.833568 Set Vref, RX VrefLevel [Byte0]: 49
2729 14:46:43.833624 [Byte1]: 49
2730 14:46:43.833712
2731 14:46:43.833791 Set Vref, RX VrefLevel [Byte0]: 50
2732 14:46:43.833881 [Byte1]: 50
2733 14:46:43.833960
2734 14:46:43.834048 Set Vref, RX VrefLevel [Byte0]: 51
2735 14:46:43.834102 [Byte1]: 51
2736 14:46:43.834154
2737 14:46:43.834207 Set Vref, RX VrefLevel [Byte0]: 52
2738 14:46:43.834295 [Byte1]: 52
2739 14:46:43.834374
2740 14:46:43.834455 Set Vref, RX VrefLevel [Byte0]: 53
2741 14:46:43.834509 [Byte1]: 53
2742 14:46:43.834561
2743 14:46:43.834633 Set Vref, RX VrefLevel [Byte0]: 54
2744 14:46:43.834697 [Byte1]: 54
2745 14:46:43.834748
2746 14:46:43.834815 Set Vref, RX VrefLevel [Byte0]: 55
2747 14:46:43.834870 [Byte1]: 55
2748 14:46:43.834921
2749 14:46:43.835180 Set Vref, RX VrefLevel [Byte0]: 56
2750 14:46:43.835271 [Byte1]: 56
2751 14:46:43.835353
2752 14:46:43.835443 Set Vref, RX VrefLevel [Byte0]: 57
2753 14:46:43.835523 [Byte1]: 57
2754 14:46:43.835674
2755 14:46:43.835780 Set Vref, RX VrefLevel [Byte0]: 58
2756 14:46:43.835862 [Byte1]: 58
2757 14:46:43.835945
2758 14:46:43.836031 Set Vref, RX VrefLevel [Byte0]: 59
2759 14:46:43.836111 [Byte1]: 59
2760 14:46:43.836202
2761 14:46:43.836282 Set Vref, RX VrefLevel [Byte0]: 60
2762 14:46:43.836372 [Byte1]: 60
2763 14:46:43.836451
2764 14:46:43.836539 Set Vref, RX VrefLevel [Byte0]: 61
2765 14:46:43.836622 [Byte1]: 61
2766 14:46:43.836708
2767 14:46:43.836792 Set Vref, RX VrefLevel [Byte0]: 62
2768 14:46:43.836872 [Byte1]: 62
2769 14:46:43.836962
2770 14:46:43.837042 Set Vref, RX VrefLevel [Byte0]: 63
2771 14:46:43.837135 [Byte1]: 63
2772 14:46:43.837215
2773 14:46:43.837360 Set Vref, RX VrefLevel [Byte0]: 64
2774 14:46:43.837415 [Byte1]: 64
2775 14:46:43.837467
2776 14:46:43.837542 Set Vref, RX VrefLevel [Byte0]: 65
2777 14:46:43.837594 [Byte1]: 65
2778 14:46:43.837645
2779 14:46:43.837718 Set Vref, RX VrefLevel [Byte0]: 66
2780 14:46:43.837771 [Byte1]: 66
2781 14:46:43.837822
2782 14:46:43.837891 Set Vref, RX VrefLevel [Byte0]: 67
2783 14:46:43.837946 [Byte1]: 67
2784 14:46:43.837998
2785 14:46:43.838060 Final RX Vref Byte 0 = 57 to rank0
2786 14:46:43.838120 Final RX Vref Byte 1 = 58 to rank0
2787 14:46:43.838172 Final RX Vref Byte 0 = 57 to rank1
2788 14:46:43.838223 Final RX Vref Byte 1 = 58 to rank1==
2789 14:46:43.838301 Dram Type= 6, Freq= 0, CH_0, rank 0
2790 14:46:43.838354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2791 14:46:43.838406 ==
2792 14:46:43.838490 DQS Delay:
2793 14:46:43.838542 DQS0 = 0, DQS1 = 0
2794 14:46:43.838593 DQM Delay:
2795 14:46:43.838665 DQM0 = 117, DQM1 = 105
2796 14:46:43.838718 DQ Delay:
2797 14:46:43.838769 DQ0 =118, DQ1 =118, DQ2 =114, DQ3 =112
2798 14:46:43.838845 DQ4 =120, DQ5 =112, DQ6 =126, DQ7 =120
2799 14:46:43.838926 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2800 14:46:43.839007 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =112
2801 14:46:43.839097
2802 14:46:43.839176
2803 14:46:43.839269 [DQSOSCAuto] RK0, (LSB)MR18= 0x3ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2804 14:46:43.839350 CH0 RK0: MR19=403, MR18=3FF
2805 14:46:43.839437 CH0_RK0: MR19=0x403, MR18=0x3FF, DQSOSC=408, MR23=63, INC=39, DEC=26
2806 14:46:43.839491
2807 14:46:43.839541 ----->DramcWriteLeveling(PI) begin...
2808 14:46:43.839605 ==
2809 14:46:43.839664 Dram Type= 6, Freq= 0, CH_0, rank 1
2810 14:46:43.839716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2811 14:46:43.839776 ==
2812 14:46:43.839835 Write leveling (Byte 0): 32 => 32
2813 14:46:43.839886 Write leveling (Byte 1): 27 => 27
2814 14:46:43.839937 DramcWriteLeveling(PI) end<-----
2815 14:46:43.840010
2816 14:46:43.840064 ==
2817 14:46:43.840115 Dram Type= 6, Freq= 0, CH_0, rank 1
2818 14:46:43.840183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2819 14:46:43.840238 ==
2820 14:46:43.840289 [Gating] SW mode calibration
2821 14:46:43.840340 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2822 14:46:43.840414 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2823 14:46:43.840468 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2824 14:46:43.840520 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2825 14:46:43.840610 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2826 14:46:43.840691 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2827 14:46:43.840782 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2828 14:46:43.840863 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2829 14:46:43.840961 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2830 14:46:43.841043 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
2831 14:46:43.841129 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2832 14:46:43.841214 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2833 14:46:43.841343 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2834 14:46:43.841402 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2835 14:46:43.841454 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2836 14:46:43.841524 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2837 14:46:43.841579 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2838 14:46:43.841630 1 0 28 | B1->B0 | 2827 4646 | 1 0 | (0 0) (0 0)
2839 14:46:43.841681 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2840 14:46:43.841756 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2841 14:46:43.841808 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2842 14:46:43.841859 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2843 14:46:43.841938 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2844 14:46:43.841991 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2845 14:46:43.842042 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2846 14:46:43.842108 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2847 14:46:43.842163 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2848 14:46:43.842214 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2849 14:46:43.842265 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2850 14:46:43.842340 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2851 14:46:43.842393 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2852 14:46:43.842444 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2853 14:46:43.842522 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2854 14:46:43.842575 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2855 14:46:43.842627 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2856 14:46:43.842703 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 14:46:43.842787 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 14:46:43.842879 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 14:46:43.842960 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 14:46:43.843043 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 14:46:43.843113 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2862 14:46:43.843358 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2863 14:46:43.843418 Total UI for P1: 0, mck2ui 16
2864 14:46:43.843497 best dqsien dly found for B0: ( 1, 3, 24)
2865 14:46:43.843550 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2866 14:46:43.843603 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 14:46:43.843679 Total UI for P1: 0, mck2ui 16
2868 14:46:43.843732 best dqsien dly found for B1: ( 1, 3, 30)
2869 14:46:43.843784 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2870 14:46:43.843859 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2871 14:46:43.843913
2872 14:46:43.843963 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2873 14:46:43.844038 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2874 14:46:43.844093 [Gating] SW calibration Done
2875 14:46:43.844145 ==
2876 14:46:43.844204 Dram Type= 6, Freq= 0, CH_0, rank 1
2877 14:46:43.844292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2878 14:46:43.844372 ==
2879 14:46:43.844465 RX Vref Scan: 0
2880 14:46:43.844545
2881 14:46:43.844647 RX Vref 0 -> 0, step: 1
2882 14:46:43.844728
2883 14:46:43.844818 RX Delay -40 -> 252, step: 8
2884 14:46:43.844899 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2885 14:46:43.844990 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2886 14:46:43.845045 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2887 14:46:43.845096 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2888 14:46:43.845150 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2889 14:46:43.845240 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2890 14:46:43.845352 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2891 14:46:43.845426 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2892 14:46:43.845477 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2893 14:46:43.845548 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2894 14:46:43.845614 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2895 14:46:43.845666 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2896 14:46:43.845717 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2897 14:46:43.845792 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2898 14:46:43.845844 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2899 14:46:43.845895 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2900 14:46:43.845974 ==
2901 14:46:43.846027 Dram Type= 6, Freq= 0, CH_0, rank 1
2902 14:46:43.846079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2903 14:46:43.846152 ==
2904 14:46:43.846206 DQS Delay:
2905 14:46:43.846257 DQS0 = 0, DQS1 = 0
2906 14:46:43.846331 DQM Delay:
2907 14:46:43.846392 DQM0 = 117, DQM1 = 109
2908 14:46:43.846444 DQ Delay:
2909 14:46:43.846499 DQ0 =111, DQ1 =119, DQ2 =115, DQ3 =111
2910 14:46:43.846567 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =127
2911 14:46:43.846623 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2912 14:46:43.846711 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
2913 14:46:43.846768
2914 14:46:43.846819
2915 14:46:43.846869 ==
2916 14:46:43.846947 Dram Type= 6, Freq= 0, CH_0, rank 1
2917 14:46:43.846999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2918 14:46:43.847052 ==
2919 14:46:43.847133
2920 14:46:43.847186
2921 14:46:43.847237 TX Vref Scan disable
2922 14:46:43.847310 == TX Byte 0 ==
2923 14:46:43.847363 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2924 14:46:43.847415 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2925 14:46:43.847478 == TX Byte 1 ==
2926 14:46:43.847539 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2927 14:46:43.847590 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2928 14:46:43.847648 ==
2929 14:46:43.847711 Dram Type= 6, Freq= 0, CH_0, rank 1
2930 14:46:43.847762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2931 14:46:43.847813 ==
2932 14:46:43.847891 TX Vref=22, minBit 10, minWin=25, winSum=415
2933 14:46:43.847956 TX Vref=24, minBit 4, minWin=25, winSum=416
2934 14:46:43.947395 TX Vref=26, minBit 2, minWin=26, winSum=427
2935 14:46:43.947528 TX Vref=28, minBit 0, minWin=26, winSum=424
2936 14:46:43.947593 TX Vref=30, minBit 10, minWin=25, winSum=424
2937 14:46:43.947652 TX Vref=32, minBit 5, minWin=26, winSum=426
2938 14:46:43.947716 [TxChooseVref] Worse bit 2, Min win 26, Win sum 427, Final Vref 26
2939 14:46:43.947773
2940 14:46:43.947828 Final TX Range 1 Vref 26
2941 14:46:43.947886
2942 14:46:43.947941 ==
2943 14:46:43.947994 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 14:46:43.948049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 14:46:43.948104 ==
2946 14:46:43.948156
2947 14:46:43.948207
2948 14:46:43.948263 TX Vref Scan disable
2949 14:46:43.948319 == TX Byte 0 ==
2950 14:46:43.948371 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2951 14:46:43.948424 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2952 14:46:43.948482 == TX Byte 1 ==
2953 14:46:43.948534 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2954 14:46:43.948586 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2955 14:46:43.948639
2956 14:46:43.948692 [DATLAT]
2957 14:46:43.948744 Freq=1200, CH0 RK1
2958 14:46:43.948796
2959 14:46:43.948851 DATLAT Default: 0xd
2960 14:46:43.948903 0, 0xFFFF, sum = 0
2961 14:46:43.948956 1, 0xFFFF, sum = 0
2962 14:46:43.949009 2, 0xFFFF, sum = 0
2963 14:46:43.949067 3, 0xFFFF, sum = 0
2964 14:46:43.949119 4, 0xFFFF, sum = 0
2965 14:46:43.949171 5, 0xFFFF, sum = 0
2966 14:46:43.949227 6, 0xFFFF, sum = 0
2967 14:46:43.949287 7, 0xFFFF, sum = 0
2968 14:46:43.949377 8, 0xFFFF, sum = 0
2969 14:46:43.949438 9, 0xFFFF, sum = 0
2970 14:46:43.949490 10, 0xFFFF, sum = 0
2971 14:46:43.949542 11, 0xFFFF, sum = 0
2972 14:46:43.949594 12, 0x0, sum = 1
2973 14:46:43.949651 13, 0x0, sum = 2
2974 14:46:43.949703 14, 0x0, sum = 3
2975 14:46:43.949755 15, 0x0, sum = 4
2976 14:46:43.949822 best_step = 13
2977 14:46:43.949875
2978 14:46:43.949925 ==
2979 14:46:43.949976 Dram Type= 6, Freq= 0, CH_0, rank 1
2980 14:46:43.950033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2981 14:46:43.950085 ==
2982 14:46:43.950136 RX Vref Scan: 0
2983 14:46:43.950195
2984 14:46:43.950246 RX Vref 0 -> 0, step: 1
2985 14:46:43.950297
2986 14:46:43.950348 RX Delay -21 -> 252, step: 4
2987 14:46:43.950406 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
2988 14:46:43.950458 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
2989 14:46:43.950509 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
2990 14:46:43.950564 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
2991 14:46:43.950619 iDelay=195, Bit 4, Center 116 (51 ~ 182) 132
2992 14:46:43.950670 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
2993 14:46:43.950721 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
2994 14:46:43.950791 iDelay=195, Bit 7, Center 120 (51 ~ 190) 140
2995 14:46:43.950873 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
2996 14:46:43.950957 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
2997 14:46:43.951039 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2998 14:46:43.951120 iDelay=195, Bit 11, Center 100 (31 ~ 170) 140
2999 14:46:43.951208 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3000 14:46:43.951305 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3001 14:46:43.951612 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3002 14:46:43.951733 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3003 14:46:43.951814 ==
3004 14:46:43.951896 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 14:46:43.951981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 14:46:43.952062 ==
3007 14:46:43.952145 DQS Delay:
3008 14:46:43.952225 DQS0 = 0, DQS1 = 0
3009 14:46:43.952309 DQM Delay:
3010 14:46:43.952390 DQM0 = 116, DQM1 = 106
3011 14:46:43.952470 DQ Delay:
3012 14:46:43.952554 DQ0 =114, DQ1 =118, DQ2 =112, DQ3 =114
3013 14:46:43.952634 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =120
3014 14:46:43.952717 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
3015 14:46:43.952810 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =112
3016 14:46:43.952893
3017 14:46:43.952972
3018 14:46:43.953064 [DQSOSCAuto] RK1, (LSB)MR18= 0x1ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
3019 14:46:43.953148 CH0 RK1: MR19=403, MR18=1FF
3020 14:46:43.953229 CH0_RK1: MR19=0x403, MR18=0x1FF, DQSOSC=409, MR23=63, INC=39, DEC=26
3021 14:46:43.953354 [RxdqsGatingPostProcess] freq 1200
3022 14:46:43.953436 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3023 14:46:43.953520 best DQS0 dly(2T, 0.5T) = (0, 11)
3024 14:46:43.953601 best DQS1 dly(2T, 0.5T) = (0, 12)
3025 14:46:43.953687 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3026 14:46:43.953768 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3027 14:46:43.953853 best DQS0 dly(2T, 0.5T) = (0, 11)
3028 14:46:43.953934 best DQS1 dly(2T, 0.5T) = (0, 11)
3029 14:46:43.954015 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3030 14:46:43.954097 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3031 14:46:43.954178 Pre-setting of DQS Precalculation
3032 14:46:43.954262 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3033 14:46:43.954343 ==
3034 14:46:43.954426 Dram Type= 6, Freq= 0, CH_1, rank 0
3035 14:46:43.954508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3036 14:46:43.954590 ==
3037 14:46:43.954673 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3038 14:46:43.954759 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3039 14:46:43.954852 [CA 0] Center 38 (8~68) winsize 61
3040 14:46:43.954906 [CA 1] Center 37 (7~68) winsize 62
3041 14:46:43.954958 [CA 2] Center 35 (5~65) winsize 61
3042 14:46:43.955018 [CA 3] Center 34 (4~64) winsize 61
3043 14:46:43.955070 [CA 4] Center 34 (4~65) winsize 62
3044 14:46:43.955122 [CA 5] Center 34 (4~64) winsize 61
3045 14:46:43.955177
3046 14:46:43.955230 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3047 14:46:43.955282
3048 14:46:43.955333 [CATrainingPosCal] consider 1 rank data
3049 14:46:43.955392 u2DelayCellTimex100 = 270/100 ps
3050 14:46:43.955445 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3051 14:46:43.955497 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3052 14:46:43.955552 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3053 14:46:43.955605 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3054 14:46:43.955657 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3055 14:46:43.955708 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3056 14:46:43.955764
3057 14:46:43.955817 CA PerBit enable=1, Macro0, CA PI delay=34
3058 14:46:43.955869
3059 14:46:43.955923 [CBTSetCACLKResult] CA Dly = 34
3060 14:46:43.955978 CS Dly: 5 (0~36)
3061 14:46:43.956029 ==
3062 14:46:43.956080 Dram Type= 6, Freq= 0, CH_1, rank 1
3063 14:46:43.956134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3064 14:46:43.956189 ==
3065 14:46:43.956240 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3066 14:46:43.956302 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3067 14:46:43.956387 [CA 0] Center 37 (7~68) winsize 62
3068 14:46:43.956468 [CA 1] Center 38 (8~68) winsize 61
3069 14:46:43.956552 [CA 2] Center 35 (5~65) winsize 61
3070 14:46:43.956632 [CA 3] Center 33 (3~64) winsize 62
3071 14:46:43.956715 [CA 4] Center 34 (4~64) winsize 61
3072 14:46:43.956810 [CA 5] Center 33 (4~63) winsize 60
3073 14:46:43.956890
3074 14:46:43.956948 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3075 14:46:43.957001
3076 14:46:43.957052 [CATrainingPosCal] consider 2 rank data
3077 14:46:43.957113 u2DelayCellTimex100 = 270/100 ps
3078 14:46:43.957195 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3079 14:46:43.957303 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3080 14:46:43.957373 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3081 14:46:43.957425 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3082 14:46:43.957481 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3083 14:46:43.957535 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3084 14:46:43.957587
3085 14:46:43.957637 CA PerBit enable=1, Macro0, CA PI delay=33
3086 14:46:43.957699
3087 14:46:43.957751 [CBTSetCACLKResult] CA Dly = 33
3088 14:46:43.957802 CS Dly: 6 (0~39)
3089 14:46:43.957855
3090 14:46:43.957910 ----->DramcWriteLeveling(PI) begin...
3091 14:46:43.957963 ==
3092 14:46:43.958015 Dram Type= 6, Freq= 0, CH_1, rank 0
3093 14:46:43.958073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3094 14:46:43.958126 ==
3095 14:46:43.958177 Write leveling (Byte 0): 24 => 24
3096 14:46:43.958228 Write leveling (Byte 1): 27 => 27
3097 14:46:43.958286 DramcWriteLeveling(PI) end<-----
3098 14:46:43.958337
3099 14:46:43.958387 ==
3100 14:46:43.958445 Dram Type= 6, Freq= 0, CH_1, rank 0
3101 14:46:43.958498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3102 14:46:43.958550 ==
3103 14:46:43.958601 [Gating] SW mode calibration
3104 14:46:43.958659 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3105 14:46:43.958713 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3106 14:46:43.958782 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3107 14:46:43.958875 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3108 14:46:43.958971 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3109 14:46:43.959059 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3110 14:46:43.959141 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3111 14:46:43.959225 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3112 14:46:43.959307 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3113 14:46:43.959389 0 15 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
3114 14:46:43.959473 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3115 14:46:43.959553 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3116 14:46:43.959622 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3117 14:46:43.959675 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3118 14:46:43.959934 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3119 14:46:43.960022 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3120 14:46:43.960081 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3121 14:46:43.960135 1 0 28 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3122 14:46:43.960218 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3123 14:46:43.960273 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3124 14:46:43.960326 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3125 14:46:43.960407 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3126 14:46:43.960461 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3127 14:46:43.960513 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3128 14:46:43.960587 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3129 14:46:43.960645 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3130 14:46:43.960698 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3131 14:46:43.960783 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3132 14:46:43.960866 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3133 14:46:43.960955 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3134 14:46:43.961041 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3135 14:46:43.961126 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3136 14:46:43.961217 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3137 14:46:43.961322 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3138 14:46:43.961409 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 14:46:43.961462 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 14:46:43.961524 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 14:46:43.961593 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 14:46:43.961645 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 14:46:43.961702 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 14:46:43.961776 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3145 14:46:43.961828 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3146 14:46:43.961893 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 14:46:43.961969 Total UI for P1: 0, mck2ui 16
3148 14:46:43.962022 best dqsien dly found for B0: ( 1, 3, 26)
3149 14:46:43.962080 Total UI for P1: 0, mck2ui 16
3150 14:46:43.962157 best dqsien dly found for B1: ( 1, 3, 26)
3151 14:46:43.962210 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3152 14:46:43.962262 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3153 14:46:43.962357
3154 14:46:43.962438 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3155 14:46:43.962535 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3156 14:46:43.962616 [Gating] SW calibration Done
3157 14:46:43.962710 ==
3158 14:46:43.962791 Dram Type= 6, Freq= 0, CH_1, rank 0
3159 14:46:43.962887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3160 14:46:43.962969 ==
3161 14:46:43.963054 RX Vref Scan: 0
3162 14:46:43.963127
3163 14:46:43.963179 RX Vref 0 -> 0, step: 1
3164 14:46:43.963243
3165 14:46:43.963318 RX Delay -40 -> 252, step: 8
3166 14:46:43.963372 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3167 14:46:43.963428 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3168 14:46:43.963504 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3169 14:46:43.963557 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3170 14:46:43.963608 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3171 14:46:43.963693 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3172 14:46:43.963746 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3173 14:46:43.963805 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3174 14:46:43.963877 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3175 14:46:43.963929 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3176 14:46:43.963981 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3177 14:46:43.964065 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3178 14:46:43.964119 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3179 14:46:43.964171 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3180 14:46:43.964267 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3181 14:46:43.964349 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3182 14:46:43.964443 ==
3183 14:46:43.964525 Dram Type= 6, Freq= 0, CH_1, rank 0
3184 14:46:43.964622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3185 14:46:43.964704 ==
3186 14:46:43.964791 DQS Delay:
3187 14:46:43.964855 DQS0 = 0, DQS1 = 0
3188 14:46:43.964907 DQM Delay:
3189 14:46:43.964962 DQM0 = 116, DQM1 = 112
3190 14:46:43.965043 DQ Delay:
3191 14:46:43.965096 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =119
3192 14:46:43.965151 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3193 14:46:43.965244 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3194 14:46:43.965311 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3195 14:46:43.965383
3196 14:46:43.965443
3197 14:46:43.965495 ==
3198 14:46:43.965577 Dram Type= 6, Freq= 0, CH_1, rank 0
3199 14:46:43.965632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3200 14:46:43.965685 ==
3201 14:46:43.965744
3202 14:46:43.965812
3203 14:46:43.965864 TX Vref Scan disable
3204 14:46:43.965922 == TX Byte 0 ==
3205 14:46:43.966015 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3206 14:46:43.966097 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3207 14:46:43.966193 == TX Byte 1 ==
3208 14:46:43.966274 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3209 14:46:43.966367 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3210 14:46:43.966422 ==
3211 14:46:43.966474 Dram Type= 6, Freq= 0, CH_1, rank 0
3212 14:46:43.966566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3213 14:46:43.966620 ==
3214 14:46:43.966673 TX Vref=22, minBit 9, minWin=24, winSum=410
3215 14:46:43.966767 TX Vref=24, minBit 3, minWin=24, winSum=414
3216 14:46:43.966849 TX Vref=26, minBit 9, minWin=25, winSum=422
3217 14:46:43.966946 TX Vref=28, minBit 3, minWin=26, winSum=428
3218 14:46:43.967027 TX Vref=30, minBit 3, minWin=26, winSum=428
3219 14:46:43.967129 TX Vref=32, minBit 9, minWin=25, winSum=425
3220 14:46:43.967185 [TxChooseVref] Worse bit 3, Min win 26, Win sum 428, Final Vref 28
3221 14:46:43.967257
3222 14:46:43.967349 Final TX Range 1 Vref 28
3223 14:46:43.967402
3224 14:46:43.967454 ==
3225 14:46:43.967539 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 14:46:43.967592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 14:46:43.967651 ==
3228 14:46:43.967743
3229 14:46:43.967823
3230 14:46:43.967918 TX Vref Scan disable
3231 14:46:43.967999 == TX Byte 0 ==
3232 14:46:43.968093 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3233 14:46:43.968148 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3234 14:46:43.968394 == TX Byte 1 ==
3235 14:46:43.968489 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3236 14:46:43.968547 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3237 14:46:43.968608
3238 14:46:43.968684 [DATLAT]
3239 14:46:43.968737 Freq=1200, CH1 RK0
3240 14:46:43.968789
3241 14:46:43.968873 DATLAT Default: 0xd
3242 14:46:43.968927 0, 0xFFFF, sum = 0
3243 14:46:43.968982 1, 0xFFFF, sum = 0
3244 14:46:43.969066 2, 0xFFFF, sum = 0
3245 14:46:43.969120 3, 0xFFFF, sum = 0
3246 14:46:43.969173 4, 0xFFFF, sum = 0
3247 14:46:43.969294 5, 0xFFFF, sum = 0
3248 14:46:43.969365 6, 0xFFFF, sum = 0
3249 14:46:43.969464 7, 0xFFFF, sum = 0
3250 14:46:43.969547 8, 0xFFFF, sum = 0
3251 14:46:43.969645 9, 0xFFFF, sum = 0
3252 14:46:43.969728 10, 0xFFFF, sum = 0
3253 14:46:43.969823 11, 0xFFFF, sum = 0
3254 14:46:43.969879 12, 0x0, sum = 1
3255 14:46:43.969933 13, 0x0, sum = 2
3256 14:46:43.970024 14, 0x0, sum = 3
3257 14:46:43.970089 15, 0x0, sum = 4
3258 14:46:43.970147 best_step = 13
3259 14:46:43.970227
3260 14:46:43.970280 ==
3261 14:46:43.970343 Dram Type= 6, Freq= 0, CH_1, rank 0
3262 14:46:43.970414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3263 14:46:43.970466 ==
3264 14:46:43.970518 RX Vref Scan: 1
3265 14:46:43.970607
3266 14:46:43.970667 Set Vref Range= 32 -> 127
3267 14:46:43.970751
3268 14:46:43.970835 RX Vref 32 -> 127, step: 1
3269 14:46:43.970917
3270 14:46:43.970996 RX Delay -13 -> 252, step: 4
3271 14:46:43.971049
3272 14:46:43.971102 Set Vref, RX VrefLevel [Byte0]: 32
3273 14:46:43.971200 [Byte1]: 32
3274 14:46:43.971281
3275 14:46:43.971376 Set Vref, RX VrefLevel [Byte0]: 33
3276 14:46:43.971458 [Byte1]: 33
3277 14:46:43.971552
3278 14:46:43.971606 Set Vref, RX VrefLevel [Byte0]: 34
3279 14:46:43.971658 [Byte1]: 34
3280 14:46:43.971743
3281 14:46:43.971796 Set Vref, RX VrefLevel [Byte0]: 35
3282 14:46:43.971847 [Byte1]: 35
3283 14:46:43.971930
3284 14:46:43.971985 Set Vref, RX VrefLevel [Byte0]: 36
3285 14:46:43.972036 [Byte1]: 36
3286 14:46:43.972123
3287 14:46:43.972177 Set Vref, RX VrefLevel [Byte0]: 37
3288 14:46:43.972229 [Byte1]: 37
3289 14:46:43.972308
3290 14:46:43.972368 Set Vref, RX VrefLevel [Byte0]: 38
3291 14:46:43.972500 [Byte1]: 38
3292 14:46:43.972592
3293 14:46:43.972728 Set Vref, RX VrefLevel [Byte0]: 39
3294 14:46:43.972866 [Byte1]: 39
3295 14:46:43.972960
3296 14:46:43.973049 Set Vref, RX VrefLevel [Byte0]: 40
3297 14:46:43.973136 [Byte1]: 40
3298 14:46:43.973217
3299 14:46:43.973347 Set Vref, RX VrefLevel [Byte0]: 41
3300 14:46:43.973444 [Byte1]: 41
3301 14:46:43.973500
3302 14:46:43.973551 Set Vref, RX VrefLevel [Byte0]: 42
3303 14:46:43.973607 [Byte1]: 42
3304 14:46:43.973699
3305 14:46:43.973780 Set Vref, RX VrefLevel [Byte0]: 43
3306 14:46:43.973877 [Byte1]: 43
3307 14:46:43.973956
3308 14:46:43.974052 Set Vref, RX VrefLevel [Byte0]: 44
3309 14:46:43.974134 [Byte1]: 44
3310 14:46:43.974228
3311 14:46:43.974309 Set Vref, RX VrefLevel [Byte0]: 45
3312 14:46:43.974397 [Byte1]: 45
3313 14:46:43.974485
3314 14:46:43.974567 Set Vref, RX VrefLevel [Byte0]: 46
3315 14:46:43.974670 [Byte1]: 46
3316 14:46:43.974765
3317 14:46:43.974852 Set Vref, RX VrefLevel [Byte0]: 47
3318 14:46:43.974932 [Byte1]: 47
3319 14:46:43.975029
3320 14:46:43.975109 Set Vref, RX VrefLevel [Byte0]: 48
3321 14:46:43.975205 [Byte1]: 48
3322 14:46:43.975285
3323 14:46:43.975381 Set Vref, RX VrefLevel [Byte0]: 49
3324 14:46:43.975463 [Byte1]: 49
3325 14:46:43.975557
3326 14:46:43.975640 Set Vref, RX VrefLevel [Byte0]: 50
3327 14:46:43.975725 [Byte1]: 50
3328 14:46:43.975814
3329 14:46:43.975894 Set Vref, RX VrefLevel [Byte0]: 51
3330 14:46:43.975991 [Byte1]: 51
3331 14:46:43.976071
3332 14:46:43.976166 Set Vref, RX VrefLevel [Byte0]: 52
3333 14:46:43.976254 [Byte1]: 52
3334 14:46:43.976423
3335 14:46:43.976520 Set Vref, RX VrefLevel [Byte0]: 53
3336 14:46:43.976604 [Byte1]: 53
3337 14:46:43.976688
3338 14:46:43.976787 Set Vref, RX VrefLevel [Byte0]: 54
3339 14:46:43.976882 [Byte1]: 54
3340 14:46:43.976971
3341 14:46:43.977051 Set Vref, RX VrefLevel [Byte0]: 55
3342 14:46:43.977147 [Byte1]: 55
3343 14:46:43.977226
3344 14:46:43.977361 Set Vref, RX VrefLevel [Byte0]: 56
3345 14:46:43.977445 [Byte1]: 56
3346 14:46:43.977537
3347 14:46:43.977619 Set Vref, RX VrefLevel [Byte0]: 57
3348 14:46:43.977715 [Byte1]: 57
3349 14:46:43.977802
3350 14:46:43.977938 Set Vref, RX VrefLevel [Byte0]: 58
3351 14:46:43.978027 [Byte1]: 58
3352 14:46:43.978116
3353 14:46:43.978198 Set Vref, RX VrefLevel [Byte0]: 59
3354 14:46:43.978294 [Byte1]: 59
3355 14:46:43.978374
3356 14:46:43.978470 Set Vref, RX VrefLevel [Byte0]: 60
3357 14:46:43.978550 [Byte1]: 60
3358 14:46:43.978646
3359 14:46:43.978731 Set Vref, RX VrefLevel [Byte0]: 61
3360 14:46:43.978829 [Byte1]: 61
3361 14:46:43.978909
3362 14:46:43.978994 Set Vref, RX VrefLevel [Byte0]: 62
3363 14:46:43.979086 [Byte1]: 62
3364 14:46:43.979166
3365 14:46:43.979261 Set Vref, RX VrefLevel [Byte0]: 63
3366 14:46:43.979341 [Byte1]: 63
3367 14:46:43.979454
3368 14:46:43.979570 Set Vref, RX VrefLevel [Byte0]: 64
3369 14:46:43.979686 [Byte1]: 64
3370 14:46:43.979800
3371 14:46:43.979915 Final RX Vref Byte 0 = 51 to rank0
3372 14:46:43.980029 Final RX Vref Byte 1 = 54 to rank0
3373 14:46:43.980118 Final RX Vref Byte 0 = 51 to rank1
3374 14:46:43.980205 Final RX Vref Byte 1 = 54 to rank1==
3375 14:46:43.980287 Dram Type= 6, Freq= 0, CH_1, rank 0
3376 14:46:43.980360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3377 14:46:43.980415 ==
3378 14:46:43.980468 DQS Delay:
3379 14:46:43.980527 DQS0 = 0, DQS1 = 0
3380 14:46:43.980581 DQM Delay:
3381 14:46:43.980636 DQM0 = 114, DQM1 = 113
3382 14:46:43.980694 DQ Delay:
3383 14:46:43.980781 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3384 14:46:43.980862 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3385 14:46:43.980950 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3386 14:46:43.981030 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =120
3387 14:46:43.981114
3388 14:46:43.981194
3389 14:46:43.981311 [DQSOSCAuto] RK0, (LSB)MR18= 0xf804, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 413 ps
3390 14:46:43.981382 CH1 RK0: MR19=304, MR18=F804
3391 14:46:43.981433 CH1_RK0: MR19=0x304, MR18=0xF804, DQSOSC=408, MR23=63, INC=39, DEC=26
3392 14:46:43.981493
3393 14:46:43.981546 ----->DramcWriteLeveling(PI) begin...
3394 14:46:43.981599 ==
3395 14:46:43.981650 Dram Type= 6, Freq= 0, CH_1, rank 1
3396 14:46:43.981714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3397 14:46:43.981767 ==
3398 14:46:43.981819 Write leveling (Byte 0): 25 => 25
3399 14:46:43.981878 Write leveling (Byte 1): 27 => 27
3400 14:46:43.982138 DramcWriteLeveling(PI) end<-----
3401 14:46:43.982224
3402 14:46:43.982312 ==
3403 14:46:43.982394 Dram Type= 6, Freq= 0, CH_1, rank 1
3404 14:46:43.982483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3405 14:46:43.982564 ==
3406 14:46:43.982662 [Gating] SW mode calibration
3407 14:46:43.982744 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3408 14:46:43.982830 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3409 14:46:43.982914 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3410 14:46:43.983006 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3411 14:46:43.983089 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3412 14:46:43.983170 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3413 14:46:43.983258 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3414 14:46:43.983349 0 15 20 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
3415 14:46:43.983439 0 15 24 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
3416 14:46:43.983520 0 15 28 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
3417 14:46:43.983606 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3418 14:46:43.983688 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3419 14:46:43.983769 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3420 14:46:43.983856 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3421 14:46:43.983937 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3422 14:46:43.984023 1 0 20 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
3423 14:46:43.984104 1 0 24 | B1->B0 | 2525 4544 | 0 1 | (1 1) (0 0)
3424 14:46:43.984190 1 0 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
3425 14:46:43.984272 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3426 14:46:43.984357 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3427 14:46:43.984439 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3428 14:46:43.984519 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3429 14:46:43.984593 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3430 14:46:43.984656 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3431 14:46:43.984708 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3432 14:46:43.984795 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3433 14:46:43.984876 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3434 14:46:43.984961 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3435 14:46:43.985043 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3436 14:46:43.985128 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3437 14:46:43.985211 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3438 14:46:43.985351 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3439 14:46:43.985406 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3440 14:46:43.985458 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3441 14:46:43.985518 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3442 14:46:43.985573 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3443 14:46:43.985624 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3444 14:46:43.985675 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3445 14:46:43.985742 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3446 14:46:43.985795 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3447 14:46:43.985846 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3448 14:46:43.985907 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3449 14:46:43.985989 Total UI for P1: 0, mck2ui 16
3450 14:46:43.986074 best dqsien dly found for B0: ( 1, 3, 22)
3451 14:46:43.986160 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 14:46:43.986240 Total UI for P1: 0, mck2ui 16
3453 14:46:43.986327 best dqsien dly found for B1: ( 1, 3, 28)
3454 14:46:43.986408 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3455 14:46:43.986496 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3456 14:46:43.986576
3457 14:46:43.986709 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3458 14:46:43.986805 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3459 14:46:43.986894 [Gating] SW calibration Done
3460 14:46:43.986984 ==
3461 14:46:43.987070 Dram Type= 6, Freq= 0, CH_1, rank 1
3462 14:46:43.987151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3463 14:46:43.987232 ==
3464 14:46:43.987319 RX Vref Scan: 0
3465 14:46:43.987399
3466 14:46:43.987484 RX Vref 0 -> 0, step: 1
3467 14:46:43.987564
3468 14:46:43.987651 RX Delay -40 -> 252, step: 8
3469 14:46:43.987732 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3470 14:46:43.987819 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3471 14:46:43.987901 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3472 14:46:43.987981 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3473 14:46:43.988073 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3474 14:46:43.988155 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3475 14:46:43.988243 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3476 14:46:43.988323 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3477 14:46:43.988408 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3478 14:46:43.988489 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3479 14:46:43.988570 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3480 14:46:43.988668 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3481 14:46:43.988749 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3482 14:46:43.988836 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3483 14:46:43.988917 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3484 14:46:43.989005 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3485 14:46:43.989084 ==
3486 14:46:43.989183 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 14:46:43.989289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 14:46:43.989369 ==
3489 14:46:43.989425 DQS Delay:
3490 14:46:43.989476 DQS0 = 0, DQS1 = 0
3491 14:46:43.989533 DQM Delay:
3492 14:46:43.989591 DQM0 = 115, DQM1 = 112
3493 14:46:43.989642 DQ Delay:
3494 14:46:43.989693 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3495 14:46:43.989758 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =115
3496 14:46:43.989810 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3497 14:46:43.989862 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3498 14:46:43.989915
3499 14:46:43.990000
3500 14:46:43.990079 ==
3501 14:46:43.990169 Dram Type= 6, Freq= 0, CH_1, rank 1
3502 14:46:43.990249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 14:46:43.990337 ==
3504 14:46:43.990417
3505 14:46:43.990701
3506 14:46:43.990788 TX Vref Scan disable
3507 14:46:43.990871 == TX Byte 0 ==
3508 14:46:43.990956 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3509 14:46:43.991037 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3510 14:46:43.991127 == TX Byte 1 ==
3511 14:46:43.991208 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3512 14:46:43.991297 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3513 14:46:43.991378 ==
3514 14:46:43.991460 Dram Type= 6, Freq= 0, CH_1, rank 1
3515 14:46:43.991546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3516 14:46:43.991626 ==
3517 14:46:43.991715 TX Vref=22, minBit 9, minWin=25, winSum=424
3518 14:46:43.991796 TX Vref=24, minBit 3, minWin=25, winSum=424
3519 14:46:43.991884 TX Vref=26, minBit 1, minWin=26, winSum=429
3520 14:46:43.991965 TX Vref=28, minBit 1, minWin=26, winSum=432
3521 14:46:43.992053 TX Vref=30, minBit 9, minWin=26, winSum=434
3522 14:46:43.992134 TX Vref=32, minBit 9, minWin=25, winSum=433
3523 14:46:43.992219 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3524 14:46:43.992303
3525 14:46:43.992382 Final TX Range 1 Vref 30
3526 14:46:43.992453
3527 14:46:43.992505 ==
3528 14:46:43.992556 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 14:46:43.992638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 14:46:43.992702 ==
3531 14:46:43.992754
3532 14:46:43.992812
3533 14:46:43.992894 TX Vref Scan disable
3534 14:46:43.992974 == TX Byte 0 ==
3535 14:46:43.993063 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3536 14:46:43.993144 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3537 14:46:43.993231 == TX Byte 1 ==
3538 14:46:43.993302 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3539 14:46:43.993362 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3540 14:46:43.993448
3541 14:46:43.993528 [DATLAT]
3542 14:46:43.993617 Freq=1200, CH1 RK1
3543 14:46:43.993698
3544 14:46:43.993784 DATLAT Default: 0xd
3545 14:46:43.993866 0, 0xFFFF, sum = 0
3546 14:46:43.993953 1, 0xFFFF, sum = 0
3547 14:46:43.994039 2, 0xFFFF, sum = 0
3548 14:46:43.994119 3, 0xFFFF, sum = 0
3549 14:46:43.994208 4, 0xFFFF, sum = 0
3550 14:46:43.994290 5, 0xFFFF, sum = 0
3551 14:46:43.994380 6, 0xFFFF, sum = 0
3552 14:46:43.994462 7, 0xFFFF, sum = 0
3553 14:46:43.994549 8, 0xFFFF, sum = 0
3554 14:46:43.994638 9, 0xFFFF, sum = 0
3555 14:46:43.994733 10, 0xFFFF, sum = 0
3556 14:46:43.994817 11, 0xFFFF, sum = 0
3557 14:46:43.994899 12, 0x0, sum = 1
3558 14:46:43.994987 13, 0x0, sum = 2
3559 14:46:43.995068 14, 0x0, sum = 3
3560 14:46:43.995159 15, 0x0, sum = 4
3561 14:46:43.995241 best_step = 13
3562 14:46:43.995326
3563 14:46:43.995406 ==
3564 14:46:43.995487 Dram Type= 6, Freq= 0, CH_1, rank 1
3565 14:46:43.995576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3566 14:46:43.995656 ==
3567 14:46:43.995744 RX Vref Scan: 0
3568 14:46:43.995824
3569 14:46:43.995913 RX Vref 0 -> 0, step: 1
3570 14:46:43.996006
3571 14:46:43.996096 RX Delay -13 -> 252, step: 4
3572 14:46:43.996178 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3573 14:46:43.996260 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3574 14:46:43.996321 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3575 14:46:43.996374 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3576 14:46:43.996426 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3577 14:46:43.996496 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3578 14:46:43.996549 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3579 14:46:43.996605 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3580 14:46:43.996684 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3581 14:46:43.996767 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3582 14:46:43.996855 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3583 14:46:43.996937 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3584 14:46:43.997019 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3585 14:46:43.997107 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3586 14:46:43.997187 iDelay=195, Bit 14, Center 118 (59 ~ 178) 120
3587 14:46:43.997299 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3588 14:46:43.997367 ==
3589 14:46:43.997438 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 14:46:43.997492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 14:46:43.997543 ==
3592 14:46:43.997594 DQS Delay:
3593 14:46:43.997659 DQS0 = 0, DQS1 = 0
3594 14:46:43.997710 DQM Delay:
3595 14:46:43.997760 DQM0 = 115, DQM1 = 112
3596 14:46:43.997831 DQ Delay:
3597 14:46:43.997883 DQ0 =116, DQ1 =112, DQ2 =106, DQ3 =114
3598 14:46:43.997935 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3599 14:46:43.997990 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3600 14:46:43.998077 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =122
3601 14:46:43.998157
3602 14:46:43.998246
3603 14:46:43.998327 [DQSOSCAuto] RK1, (LSB)MR18= 0xf507, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
3604 14:46:43.998416 CH1 RK1: MR19=304, MR18=F507
3605 14:46:43.998498 CH1_RK1: MR19=0x304, MR18=0xF507, DQSOSC=407, MR23=63, INC=39, DEC=26
3606 14:46:43.998585 [RxdqsGatingPostProcess] freq 1200
3607 14:46:43.998668 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3608 14:46:43.998754 best DQS0 dly(2T, 0.5T) = (0, 11)
3609 14:46:43.998836 best DQS1 dly(2T, 0.5T) = (0, 11)
3610 14:46:43.998923 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3611 14:46:43.999022 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3612 14:46:43.999103 best DQS0 dly(2T, 0.5T) = (0, 11)
3613 14:46:43.999193 best DQS1 dly(2T, 0.5T) = (0, 11)
3614 14:46:43.999274 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3615 14:46:43.999361 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3616 14:46:43.999441 Pre-setting of DQS Precalculation
3617 14:46:43.999527 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3618 14:46:43.999613 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3619 14:46:43.999695 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3620 14:46:43.999783
3621 14:46:43.999863
3622 14:46:43.999951 [Calibration Summary] 2400 Mbps
3623 14:46:44.000032 CH 0, Rank 0
3624 14:46:44.000117 SW Impedance : PASS
3625 14:46:44.000198 DUTY Scan : NO K
3626 14:46:44.000278 ZQ Calibration : PASS
3627 14:46:44.000367 Jitter Meter : NO K
3628 14:46:44.000446 CBT Training : PASS
3629 14:46:44.000522 Write leveling : PASS
3630 14:46:44.000575 RX DQS gating : PASS
3631 14:46:44.000626 RX DQ/DQS(RDDQC) : PASS
3632 14:46:44.000683 TX DQ/DQS : PASS
3633 14:46:44.000767 RX DATLAT : PASS
3634 14:46:44.000847 RX DQ/DQS(Engine): PASS
3635 14:46:44.000937 TX OE : NO K
3636 14:46:44.001017 All Pass.
3637 14:46:44.001105
3638 14:46:44.001185 CH 0, Rank 1
3639 14:46:44.001298 SW Impedance : PASS
3640 14:46:44.001368 DUTY Scan : NO K
3641 14:46:44.001419 ZQ Calibration : PASS
3642 14:46:44.001493 Jitter Meter : NO K
3643 14:46:44.001546 CBT Training : PASS
3644 14:46:44.001597 Write leveling : PASS
3645 14:46:44.001865 RX DQS gating : PASS
3646 14:46:44.001951 RX DQ/DQS(RDDQC) : PASS
3647 14:46:44.002039 TX DQ/DQS : PASS
3648 14:46:44.002096 RX DATLAT : PASS
3649 14:46:44.002148 RX DQ/DQS(Engine): PASS
3650 14:46:44.002205 TX OE : NO K
3651 14:46:44.002292 All Pass.
3652 14:46:44.002357
3653 14:46:44.002415 CH 1, Rank 0
3654 14:46:44.002511 SW Impedance : PASS
3655 14:46:44.002597 DUTY Scan : NO K
3656 14:46:44.002682 ZQ Calibration : PASS
3657 14:46:44.002762 Jitter Meter : NO K
3658 14:46:44.002850 CBT Training : PASS
3659 14:46:44.002930 Write leveling : PASS
3660 14:46:44.003020 RX DQS gating : PASS
3661 14:46:44.003100 RX DQ/DQS(RDDQC) : PASS
3662 14:46:44.003186 TX DQ/DQS : PASS
3663 14:46:44.003268 RX DATLAT : PASS
3664 14:46:44.003348 RX DQ/DQS(Engine): PASS
3665 14:46:44.003437 TX OE : NO K
3666 14:46:44.003517 All Pass.
3667 14:46:44.003606
3668 14:46:44.003686 CH 1, Rank 1
3669 14:46:44.003773 SW Impedance : PASS
3670 14:46:44.003853 DUTY Scan : NO K
3671 14:46:44.003936 ZQ Calibration : PASS
3672 14:46:44.004029 Jitter Meter : NO K
3673 14:46:44.004109 CBT Training : PASS
3674 14:46:44.004197 Write leveling : PASS
3675 14:46:44.004277 RX DQS gating : PASS
3676 14:46:44.004368 RX DQ/DQS(RDDQC) : PASS
3677 14:46:44.004448 TX DQ/DQS : PASS
3678 14:46:44.004534 RX DATLAT : PASS
3679 14:46:44.004615 RX DQ/DQS(Engine): PASS
3680 14:46:44.004694 TX OE : NO K
3681 14:46:44.004783 All Pass.
3682 14:46:44.004862
3683 14:46:44.004951 DramC Write-DBI off
3684 14:46:44.005032 PER_BANK_REFRESH: Hybrid Mode
3685 14:46:44.005120 TX_TRACKING: ON
3686 14:46:44.005204 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3687 14:46:44.005325 [FAST_K] Save calibration result to emmc
3688 14:46:44.005420 dramc_set_vcore_voltage set vcore to 650000
3689 14:46:44.005506 Read voltage for 600, 5
3690 14:46:44.005560 Vio18 = 0
3691 14:46:44.005612 Vcore = 650000
3692 14:46:44.005670 Vdram = 0
3693 14:46:44.005754 Vddq = 0
3694 14:46:44.005844 Vmddr = 0
3695 14:46:44.005934 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3696 14:46:44.006016 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3697 14:46:44.006107 MEM_TYPE=3, freq_sel=19
3698 14:46:44.006188 sv_algorithm_assistance_LP4_1600
3699 14:46:44.006310 ============ PULL DRAM RESETB DOWN ============
3700 14:46:44.006366 ========== PULL DRAM RESETB DOWN end =========
3701 14:46:44.006418 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3702 14:46:44.006493 ===================================
3703 14:46:44.006546 LPDDR4 DRAM CONFIGURATION
3704 14:46:44.006597 ===================================
3705 14:46:44.006670 EX_ROW_EN[0] = 0x0
3706 14:46:44.006722 EX_ROW_EN[1] = 0x0
3707 14:46:44.006773 LP4Y_EN = 0x0
3708 14:46:44.006832 WORK_FSP = 0x0
3709 14:46:44.006892 WL = 0x2
3710 14:46:44.006943 RL = 0x2
3711 14:46:44.006996 BL = 0x2
3712 14:46:44.007063 RPST = 0x0
3713 14:46:44.007114 RD_PRE = 0x0
3714 14:46:44.007165 WR_PRE = 0x1
3715 14:46:44.007230 WR_PST = 0x0
3716 14:46:44.007283 DBI_WR = 0x0
3717 14:46:44.007333 DBI_RD = 0x0
3718 14:46:44.007387 OTF = 0x1
3719 14:46:44.007453 ===================================
3720 14:46:44.007505 ===================================
3721 14:46:44.007556 ANA top config
3722 14:46:44.007626 ===================================
3723 14:46:44.007679 DLL_ASYNC_EN = 0
3724 14:46:44.007730 ALL_SLAVE_EN = 1
3725 14:46:44.007788 NEW_RANK_MODE = 1
3726 14:46:44.007876 DLL_IDLE_MODE = 1
3727 14:46:44.007957 LP45_APHY_COMB_EN = 1
3728 14:46:44.008047 TX_ODT_DIS = 1
3729 14:46:44.008127 NEW_8X_MODE = 1
3730 14:46:44.008217 ===================================
3731 14:46:44.008297 ===================================
3732 14:46:44.008388 data_rate = 1200
3733 14:46:44.008469 CKR = 1
3734 14:46:44.008551 DQ_P2S_RATIO = 8
3735 14:46:44.008637 ===================================
3736 14:46:44.008716 CA_P2S_RATIO = 8
3737 14:46:44.008808 DQ_CA_OPEN = 0
3738 14:46:44.008897 DQ_SEMI_OPEN = 0
3739 14:46:44.008987 CA_SEMI_OPEN = 0
3740 14:46:44.009067 CA_FULL_RATE = 0
3741 14:46:44.009157 DQ_CKDIV4_EN = 1
3742 14:46:44.009237 CA_CKDIV4_EN = 1
3743 14:46:44.009354 CA_PREDIV_EN = 0
3744 14:46:44.009410 PH8_DLY = 0
3745 14:46:44.009467 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3746 14:46:44.009536 DQ_AAMCK_DIV = 4
3747 14:46:44.009590 CA_AAMCK_DIV = 4
3748 14:46:44.009641 CA_ADMCK_DIV = 4
3749 14:46:44.009694 DQ_TRACK_CA_EN = 0
3750 14:46:44.009746 CA_PICK = 600
3751 14:46:44.009796 CA_MCKIO = 600
3752 14:46:44.009846 MCKIO_SEMI = 0
3753 14:46:44.009906 PLL_FREQ = 2288
3754 14:46:44.009966 DQ_UI_PI_RATIO = 32
3755 14:46:44.010017 CA_UI_PI_RATIO = 0
3756 14:46:44.010074 ===================================
3757 14:46:44.010135 ===================================
3758 14:46:44.010186 memory_type:LPDDR4
3759 14:46:44.010237 GP_NUM : 10
3760 14:46:44.010302 SRAM_EN : 1
3761 14:46:44.010357 MD32_EN : 0
3762 14:46:44.010408 ===================================
3763 14:46:44.010464 [ANA_INIT] >>>>>>>>>>>>>>
3764 14:46:44.010528 <<<<<< [CONFIGURE PHASE]: ANA_TX
3765 14:46:44.010581 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3766 14:46:44.010631 ===================================
3767 14:46:44.010707 data_rate = 1200,PCW = 0X5800
3768 14:46:44.010788 ===================================
3769 14:46:44.010877 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3770 14:46:44.010960 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3771 14:46:44.011042 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3772 14:46:44.011131 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3773 14:46:44.011211 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3774 14:46:44.011302 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3775 14:46:44.011383 [ANA_INIT] flow start
3776 14:46:44.011472 [ANA_INIT] PLL >>>>>>>>
3777 14:46:44.011552 [ANA_INIT] PLL <<<<<<<<
3778 14:46:44.011638 [ANA_INIT] MIDPI >>>>>>>>
3779 14:46:44.011721 [ANA_INIT] MIDPI <<<<<<<<
3780 14:46:44.011804 [ANA_INIT] DLL >>>>>>>>
3781 14:46:44.011892 [ANA_INIT] flow end
3782 14:46:44.011972 ============ LP4 DIFF to SE enter ============
3783 14:46:44.012062 ============ LP4 DIFF to SE exit ============
3784 14:46:44.012339 [ANA_INIT] <<<<<<<<<<<<<
3785 14:46:44.012446 [Flow] Enable top DCM control >>>>>
3786 14:46:44.012529 [Flow] Enable top DCM control <<<<<
3787 14:46:44.012621 Enable DLL master slave shuffle
3788 14:46:44.012704 ==============================================================
3789 14:46:44.012793 Gating Mode config
3790 14:46:44.012876 ==============================================================
3791 14:46:44.012957 Config description:
3792 14:46:44.013049 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3793 14:46:44.013132 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3794 14:46:44.013225 SELPH_MODE 0: By rank 1: By Phase
3795 14:46:44.013340 ==============================================================
3796 14:46:44.013443 GAT_TRACK_EN = 1
3797 14:46:44.013528 RX_GATING_MODE = 2
3798 14:46:44.013618 RX_GATING_TRACK_MODE = 2
3799 14:46:44.013698 SELPH_MODE = 1
3800 14:46:44.013790 PICG_EARLY_EN = 1
3801 14:46:44.013871 VALID_LAT_VALUE = 1
3802 14:46:44.013962 ==============================================================
3803 14:46:44.014045 Enter into Gating configuration >>>>
3804 14:46:44.014100 Exit from Gating configuration <<<<
3805 14:46:44.014173 Enter into DVFS_PRE_config >>>>>
3806 14:46:44.014225 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3807 14:46:44.014278 Exit from DVFS_PRE_config <<<<<
3808 14:46:44.014355 Enter into PICG configuration >>>>
3809 14:46:44.014436 Exit from PICG configuration <<<<
3810 14:46:44.014525 [RX_INPUT] configuration >>>>>
3811 14:46:44.014607 [RX_INPUT] configuration <<<<<
3812 14:46:44.014697 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3813 14:46:44.014787 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3814 14:46:44.014871 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3815 14:46:44.014961 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3816 14:46:44.015042 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3817 14:46:44.015133 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3818 14:46:44.015214 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3819 14:46:44.015306 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3820 14:46:44.015402 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3821 14:46:44.015493 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3822 14:46:44.015574 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3823 14:46:44.015657 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3824 14:46:44.015755 ===================================
3825 14:46:44.015857 LPDDR4 DRAM CONFIGURATION
3826 14:46:44.015941 ===================================
3827 14:46:44.016022 EX_ROW_EN[0] = 0x0
3828 14:46:44.020293 EX_ROW_EN[1] = 0x0
3829 14:46:44.020371 LP4Y_EN = 0x0
3830 14:46:44.022748 WORK_FSP = 0x0
3831 14:46:44.026244 WL = 0x2
3832 14:46:44.026351 RL = 0x2
3833 14:46:44.030085 BL = 0x2
3834 14:46:44.030164 RPST = 0x0
3835 14:46:44.032135 RD_PRE = 0x0
3836 14:46:44.032242 WR_PRE = 0x1
3837 14:46:44.035530 WR_PST = 0x0
3838 14:46:44.035601 DBI_WR = 0x0
3839 14:46:44.038989 DBI_RD = 0x0
3840 14:46:44.039089 OTF = 0x1
3841 14:46:44.042146 ===================================
3842 14:46:44.045603 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3843 14:46:44.052503 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3844 14:46:44.055393 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3845 14:46:44.058471 ===================================
3846 14:46:44.062167 LPDDR4 DRAM CONFIGURATION
3847 14:46:44.064975 ===================================
3848 14:46:44.065080 EX_ROW_EN[0] = 0x10
3849 14:46:44.069077 EX_ROW_EN[1] = 0x0
3850 14:46:44.072559 LP4Y_EN = 0x0
3851 14:46:44.072657 WORK_FSP = 0x0
3852 14:46:44.074994 WL = 0x2
3853 14:46:44.075090 RL = 0x2
3854 14:46:44.078529 BL = 0x2
3855 14:46:44.078627 RPST = 0x0
3856 14:46:44.081544 RD_PRE = 0x0
3857 14:46:44.081641 WR_PRE = 0x1
3858 14:46:44.085185 WR_PST = 0x0
3859 14:46:44.085320 DBI_WR = 0x0
3860 14:46:44.089002 DBI_RD = 0x0
3861 14:46:44.089100 OTF = 0x1
3862 14:46:44.091494 ===================================
3863 14:46:44.098167 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3864 14:46:44.102269 nWR fixed to 30
3865 14:46:44.106714 [ModeRegInit_LP4] CH0 RK0
3866 14:46:44.106811 [ModeRegInit_LP4] CH0 RK1
3867 14:46:44.109198 [ModeRegInit_LP4] CH1 RK0
3868 14:46:44.112314 [ModeRegInit_LP4] CH1 RK1
3869 14:46:44.112392 match AC timing 17
3870 14:46:44.118835 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3871 14:46:44.122013 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3872 14:46:44.125414 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3873 14:46:44.132954 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3874 14:46:44.135105 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3875 14:46:44.135181 ==
3876 14:46:44.138476 Dram Type= 6, Freq= 0, CH_0, rank 0
3877 14:46:44.142354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3878 14:46:44.142470 ==
3879 14:46:44.148591 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3880 14:46:44.154943 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3881 14:46:44.158282 [CA 0] Center 36 (6~67) winsize 62
3882 14:46:44.161781 [CA 1] Center 36 (6~67) winsize 62
3883 14:46:44.164970 [CA 2] Center 34 (4~65) winsize 62
3884 14:46:44.168894 [CA 3] Center 34 (4~65) winsize 62
3885 14:46:44.171690 [CA 4] Center 34 (3~65) winsize 63
3886 14:46:44.175060 [CA 5] Center 33 (3~64) winsize 62
3887 14:46:44.175156
3888 14:46:44.178092 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3889 14:46:44.178174
3890 14:46:44.181452 [CATrainingPosCal] consider 1 rank data
3891 14:46:44.184500 u2DelayCellTimex100 = 270/100 ps
3892 14:46:44.187807 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3893 14:46:44.191400 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3894 14:46:44.195253 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3895 14:46:44.201100 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3896 14:46:44.204686 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3897 14:46:44.208081 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3898 14:46:44.208162
3899 14:46:44.211141 CA PerBit enable=1, Macro0, CA PI delay=33
3900 14:46:44.211223
3901 14:46:44.214494 [CBTSetCACLKResult] CA Dly = 33
3902 14:46:44.214576 CS Dly: 5 (0~36)
3903 14:46:44.214640 ==
3904 14:46:44.217770 Dram Type= 6, Freq= 0, CH_0, rank 1
3905 14:46:44.224371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3906 14:46:44.224454 ==
3907 14:46:44.228081 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3908 14:46:44.234479 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3909 14:46:44.237805 [CA 0] Center 36 (6~67) winsize 62
3910 14:46:44.241088 [CA 1] Center 36 (6~67) winsize 62
3911 14:46:44.244240 [CA 2] Center 34 (4~65) winsize 62
3912 14:46:44.247396 [CA 3] Center 35 (4~66) winsize 63
3913 14:46:44.250740 [CA 4] Center 34 (3~65) winsize 63
3914 14:46:44.254905 [CA 5] Center 34 (3~65) winsize 63
3915 14:46:44.254987
3916 14:46:44.257428 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3917 14:46:44.257509
3918 14:46:44.260864 [CATrainingPosCal] consider 2 rank data
3919 14:46:44.263901 u2DelayCellTimex100 = 270/100 ps
3920 14:46:44.267169 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3921 14:46:44.274438 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3922 14:46:44.277091 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3923 14:46:44.281458 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3924 14:46:44.283816 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3925 14:46:44.287112 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3926 14:46:44.287194
3927 14:46:44.290307 CA PerBit enable=1, Macro0, CA PI delay=33
3928 14:46:44.290388
3929 14:46:44.293923 [CBTSetCACLKResult] CA Dly = 33
3930 14:46:44.297049 CS Dly: 5 (0~37)
3931 14:46:44.297130
3932 14:46:44.300563 ----->DramcWriteLeveling(PI) begin...
3933 14:46:44.300648 ==
3934 14:46:44.303411 Dram Type= 6, Freq= 0, CH_0, rank 0
3935 14:46:44.306682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3936 14:46:44.306764 ==
3937 14:46:44.310057 Write leveling (Byte 0): 31 => 31
3938 14:46:44.313323 Write leveling (Byte 1): 30 => 30
3939 14:46:44.318439 DramcWriteLeveling(PI) end<-----
3940 14:46:44.318519
3941 14:46:44.318583 ==
3942 14:46:44.320136 Dram Type= 6, Freq= 0, CH_0, rank 0
3943 14:46:44.324094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3944 14:46:44.324176 ==
3945 14:46:44.326728 [Gating] SW mode calibration
3946 14:46:44.333008 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3947 14:46:44.340398 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3948 14:46:44.343383 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3949 14:46:44.346554 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3950 14:46:44.353556 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3951 14:46:44.356248 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
3952 14:46:44.359561 0 9 16 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
3953 14:46:44.366038 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3954 14:46:44.369171 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3955 14:46:44.372750 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3956 14:46:44.379231 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3957 14:46:44.383130 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3958 14:46:44.389057 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3959 14:46:44.392608 0 10 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
3960 14:46:44.395986 0 10 16 | B1->B0 | 3535 4444 | 0 0 | (1 1) (0 0)
3961 14:46:44.401988 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3962 14:46:44.405767 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3963 14:46:44.409788 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3964 14:46:44.415768 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3965 14:46:44.419099 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3966 14:46:44.422256 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3967 14:46:44.429169 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3968 14:46:44.431984 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3969 14:46:44.435700 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3970 14:46:44.442404 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3971 14:46:44.444943 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3972 14:46:44.448290 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3973 14:46:44.455711 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3974 14:46:44.458036 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3975 14:46:44.461887 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3976 14:46:44.467884 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3977 14:46:44.471371 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3978 14:46:44.474615 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3979 14:46:44.482083 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3980 14:46:44.484511 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3981 14:46:44.487799 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3982 14:46:44.494954 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3983 14:46:44.497741 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 14:46:44.500740 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3985 14:46:44.504707 Total UI for P1: 0, mck2ui 16
3986 14:46:44.508028 best dqsien dly found for B0: ( 0, 13, 14)
3987 14:46:44.514295 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 14:46:44.514382 Total UI for P1: 0, mck2ui 16
3989 14:46:44.517548 best dqsien dly found for B1: ( 0, 13, 16)
3990 14:46:44.524282 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
3991 14:46:44.527936 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
3992 14:46:44.528017
3993 14:46:44.530546 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
3994 14:46:44.534464 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
3995 14:46:44.537197 [Gating] SW calibration Done
3996 14:46:44.537339 ==
3997 14:46:44.540904 Dram Type= 6, Freq= 0, CH_0, rank 0
3998 14:46:44.543950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3999 14:46:44.544033 ==
4000 14:46:44.547157 RX Vref Scan: 0
4001 14:46:44.547238
4002 14:46:44.547301 RX Vref 0 -> 0, step: 1
4003 14:46:44.547361
4004 14:46:44.550899 RX Delay -230 -> 252, step: 16
4005 14:46:44.557018 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4006 14:46:44.560158 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4007 14:46:44.563529 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4008 14:46:44.566840 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4009 14:46:44.572170 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4010 14:46:44.576779 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4011 14:46:44.579856 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4012 14:46:44.583275 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4013 14:46:44.586654 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4014 14:46:44.594215 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4015 14:46:44.596417 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4016 14:46:44.600453 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4017 14:46:44.603164 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4018 14:46:44.609749 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4019 14:46:44.613007 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4020 14:46:44.616373 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4021 14:46:44.616455 ==
4022 14:46:44.619678 Dram Type= 6, Freq= 0, CH_0, rank 0
4023 14:46:44.626043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 14:46:44.626126 ==
4025 14:46:44.626190 DQS Delay:
4026 14:46:44.629458 DQS0 = 0, DQS1 = 0
4027 14:46:44.629539 DQM Delay:
4028 14:46:44.629603 DQM0 = 40, DQM1 = 34
4029 14:46:44.632463 DQ Delay:
4030 14:46:44.636146 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4031 14:46:44.639148 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4032 14:46:44.642681 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4033 14:46:44.645718 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4034 14:46:44.645799
4035 14:46:44.645862
4036 14:46:44.645921 ==
4037 14:46:44.649205 Dram Type= 6, Freq= 0, CH_0, rank 0
4038 14:46:44.652482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4039 14:46:44.652563 ==
4040 14:46:44.652627
4041 14:46:44.652686
4042 14:46:44.655509 TX Vref Scan disable
4043 14:46:44.655590 == TX Byte 0 ==
4044 14:46:44.662760 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4045 14:46:44.665863 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4046 14:46:44.669132 == TX Byte 1 ==
4047 14:46:44.672196 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4048 14:46:44.675481 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4049 14:46:44.675566 ==
4050 14:46:44.678567 Dram Type= 6, Freq= 0, CH_0, rank 0
4051 14:46:44.682022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4052 14:46:44.685985 ==
4053 14:46:44.686066
4054 14:46:44.686129
4055 14:46:44.686187 TX Vref Scan disable
4056 14:46:44.689454 == TX Byte 0 ==
4057 14:46:44.692517 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4058 14:46:44.698741 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4059 14:46:44.698822 == TX Byte 1 ==
4060 14:46:44.701980 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4061 14:46:44.708901 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4062 14:46:44.708983
4063 14:46:44.709045 [DATLAT]
4064 14:46:44.709104 Freq=600, CH0 RK0
4065 14:46:44.709162
4066 14:46:44.712424 DATLAT Default: 0x9
4067 14:46:44.715489 0, 0xFFFF, sum = 0
4068 14:46:44.715570 1, 0xFFFF, sum = 0
4069 14:46:44.718534 2, 0xFFFF, sum = 0
4070 14:46:44.718615 3, 0xFFFF, sum = 0
4071 14:46:44.722169 4, 0xFFFF, sum = 0
4072 14:46:44.722250 5, 0xFFFF, sum = 0
4073 14:46:44.725432 6, 0xFFFF, sum = 0
4074 14:46:44.725513 7, 0xFFFF, sum = 0
4075 14:46:44.728604 8, 0x0, sum = 1
4076 14:46:44.728686 9, 0x0, sum = 2
4077 14:46:44.731794 10, 0x0, sum = 3
4078 14:46:44.731875 11, 0x0, sum = 4
4079 14:46:44.731939 best_step = 9
4080 14:46:44.731997
4081 14:46:44.735168 ==
4082 14:46:44.739091 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 14:46:44.741755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 14:46:44.741836 ==
4085 14:46:44.741899 RX Vref Scan: 1
4086 14:46:44.741956
4087 14:46:44.745393 RX Vref 0 -> 0, step: 1
4088 14:46:44.745472
4089 14:46:44.748281 RX Delay -195 -> 252, step: 8
4090 14:46:44.748361
4091 14:46:44.751775 Set Vref, RX VrefLevel [Byte0]: 57
4092 14:46:44.754552 [Byte1]: 58
4093 14:46:44.758127
4094 14:46:44.758206 Final RX Vref Byte 0 = 57 to rank0
4095 14:46:44.762391 Final RX Vref Byte 1 = 58 to rank0
4096 14:46:44.764633 Final RX Vref Byte 0 = 57 to rank1
4097 14:46:44.767891 Final RX Vref Byte 1 = 58 to rank1==
4098 14:46:44.771324 Dram Type= 6, Freq= 0, CH_0, rank 0
4099 14:46:44.777586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4100 14:46:44.777726 ==
4101 14:46:44.777819 DQS Delay:
4102 14:46:44.777915 DQS0 = 0, DQS1 = 0
4103 14:46:44.781347 DQM Delay:
4104 14:46:44.781440 DQM0 = 40, DQM1 = 32
4105 14:46:44.784759 DQ Delay:
4106 14:46:44.788072 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =36
4107 14:46:44.790859 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44
4108 14:46:44.794351 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4109 14:46:44.797775 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4110 14:46:44.797887
4111 14:46:44.797976
4112 14:46:44.804117 [DQSOSCAuto] RK0, (LSB)MR18= 0x524a, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
4113 14:46:44.807605 CH0 RK0: MR19=808, MR18=524A
4114 14:46:44.814827 CH0_RK0: MR19=0x808, MR18=0x524A, DQSOSC=394, MR23=63, INC=168, DEC=112
4115 14:46:44.814964
4116 14:46:44.818442 ----->DramcWriteLeveling(PI) begin...
4117 14:46:44.818538 ==
4118 14:46:44.821280 Dram Type= 6, Freq= 0, CH_0, rank 1
4119 14:46:44.823868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 14:46:44.823944 ==
4121 14:46:44.827179 Write leveling (Byte 0): 33 => 33
4122 14:46:44.830862 Write leveling (Byte 1): 30 => 30
4123 14:46:44.834049 DramcWriteLeveling(PI) end<-----
4124 14:46:44.834134
4125 14:46:44.834197 ==
4126 14:46:44.837361 Dram Type= 6, Freq= 0, CH_0, rank 1
4127 14:46:44.840633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 14:46:44.840716 ==
4129 14:46:44.843856 [Gating] SW mode calibration
4130 14:46:44.850443 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4131 14:46:44.857077 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4132 14:46:44.860548 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4133 14:46:44.867694 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4134 14:46:44.870375 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4135 14:46:44.873979 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
4136 14:46:44.880269 0 9 16 | B1->B0 | 2e2e 2929 | 0 0 | (0 0) (1 1)
4137 14:46:44.884002 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4138 14:46:44.886796 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4139 14:46:44.894559 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4140 14:46:44.896628 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4141 14:46:44.900417 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4142 14:46:44.907225 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4143 14:46:44.910089 0 10 12 | B1->B0 | 2626 3434 | 0 0 | (0 0) (0 0)
4144 14:46:44.913233 0 10 16 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
4145 14:46:44.920316 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4146 14:46:44.922948 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4147 14:46:44.926614 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4148 14:46:44.933213 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4149 14:46:44.936680 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4150 14:46:44.939579 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4151 14:46:44.946714 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4152 14:46:44.949675 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4153 14:46:44.952824 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4154 14:46:44.959504 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4155 14:46:44.962401 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4156 14:46:44.965707 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4157 14:46:44.972333 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4158 14:46:44.976393 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4159 14:46:44.978836 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4160 14:46:44.985918 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4161 14:46:44.989134 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4162 14:46:44.992357 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4163 14:46:44.999445 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4164 14:46:45.002368 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4165 14:46:45.005687 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4166 14:46:45.011992 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4167 14:46:45.015387 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4168 14:46:45.018857 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4169 14:46:45.021875 Total UI for P1: 0, mck2ui 16
4170 14:46:45.024992 best dqsien dly found for B0: ( 0, 13, 12)
4171 14:46:45.028469 Total UI for P1: 0, mck2ui 16
4172 14:46:45.031796 best dqsien dly found for B1: ( 0, 13, 14)
4173 14:46:45.035365 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4174 14:46:45.038664 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4175 14:46:45.038753
4176 14:46:45.045041 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4177 14:46:45.048039 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4178 14:46:45.051581 [Gating] SW calibration Done
4179 14:46:45.051666 ==
4180 14:46:45.054907 Dram Type= 6, Freq= 0, CH_0, rank 1
4181 14:46:45.058508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4182 14:46:45.058592 ==
4183 14:46:45.058657 RX Vref Scan: 0
4184 14:46:45.061691
4185 14:46:45.061772 RX Vref 0 -> 0, step: 1
4186 14:46:45.061837
4187 14:46:45.064950 RX Delay -230 -> 252, step: 16
4188 14:46:45.067791 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4189 14:46:45.074681 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4190 14:46:45.077937 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4191 14:46:45.081005 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4192 14:46:45.084464 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4193 14:46:45.091014 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4194 14:46:45.094207 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4195 14:46:45.097847 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4196 14:46:45.101505 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4197 14:46:45.103953 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4198 14:46:45.110564 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4199 14:46:45.114053 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4200 14:46:45.117203 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4201 14:46:45.120350 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4202 14:46:45.126996 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4203 14:46:45.130512 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4204 14:46:45.130602 ==
4205 14:46:45.134033 Dram Type= 6, Freq= 0, CH_0, rank 1
4206 14:46:45.137041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 14:46:45.137125 ==
4208 14:46:45.140328 DQS Delay:
4209 14:46:45.140410 DQS0 = 0, DQS1 = 0
4210 14:46:45.143353 DQM Delay:
4211 14:46:45.143435 DQM0 = 42, DQM1 = 36
4212 14:46:45.143499 DQ Delay:
4213 14:46:45.147237 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4214 14:46:45.150501 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4215 14:46:45.153796 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4216 14:46:45.156884 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4217 14:46:45.156968
4218 14:46:45.157033
4219 14:46:45.159813 ==
4220 14:46:45.163383 Dram Type= 6, Freq= 0, CH_0, rank 1
4221 14:46:45.167159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4222 14:46:45.167244 ==
4223 14:46:45.167309
4224 14:46:45.167368
4225 14:46:45.170349 TX Vref Scan disable
4226 14:46:45.170430 == TX Byte 0 ==
4227 14:46:45.176101 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4228 14:46:45.180186 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4229 14:46:45.180270 == TX Byte 1 ==
4230 14:46:45.186741 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4231 14:46:45.190730 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4232 14:46:45.190814 ==
4233 14:46:45.192864 Dram Type= 6, Freq= 0, CH_0, rank 1
4234 14:46:45.195979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 14:46:45.196062 ==
4236 14:46:45.196127
4237 14:46:45.196187
4238 14:46:45.199181 TX Vref Scan disable
4239 14:46:45.203241 == TX Byte 0 ==
4240 14:46:45.205788 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4241 14:46:45.212955 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4242 14:46:45.213039 == TX Byte 1 ==
4243 14:46:45.216246 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4244 14:46:45.222445 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4245 14:46:45.222531
4246 14:46:45.222595 [DATLAT]
4247 14:46:45.222654 Freq=600, CH0 RK1
4248 14:46:45.222752
4249 14:46:45.225919 DATLAT Default: 0x9
4250 14:46:45.226000 0, 0xFFFF, sum = 0
4251 14:46:45.229123 1, 0xFFFF, sum = 0
4252 14:46:45.229206 2, 0xFFFF, sum = 0
4253 14:46:45.232846 3, 0xFFFF, sum = 0
4254 14:46:45.235811 4, 0xFFFF, sum = 0
4255 14:46:45.235894 5, 0xFFFF, sum = 0
4256 14:46:45.239108 6, 0xFFFF, sum = 0
4257 14:46:45.239192 7, 0xFFFF, sum = 0
4258 14:46:45.242946 8, 0x0, sum = 1
4259 14:46:45.243030 9, 0x0, sum = 2
4260 14:46:45.243095 10, 0x0, sum = 3
4261 14:46:45.245658 11, 0x0, sum = 4
4262 14:46:45.245741 best_step = 9
4263 14:46:45.245804
4264 14:46:45.245864 ==
4265 14:46:45.249093 Dram Type= 6, Freq= 0, CH_0, rank 1
4266 14:46:45.255593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4267 14:46:45.255684 ==
4268 14:46:45.255749 RX Vref Scan: 0
4269 14:46:45.255809
4270 14:46:45.259415 RX Vref 0 -> 0, step: 1
4271 14:46:45.259496
4272 14:46:45.262442 RX Delay -179 -> 252, step: 8
4273 14:46:45.265494 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4274 14:46:45.272091 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4275 14:46:45.275622 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4276 14:46:45.278664 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4277 14:46:45.281755 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4278 14:46:45.288968 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4279 14:46:45.292533 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4280 14:46:45.295112 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4281 14:46:45.298560 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4282 14:46:45.305143 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4283 14:46:45.308490 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4284 14:46:45.311736 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4285 14:46:45.315125 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4286 14:46:45.321212 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4287 14:46:45.325082 iDelay=205, Bit 14, Center 44 (-115 ~ 204) 320
4288 14:46:45.328011 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4289 14:46:45.328095 ==
4290 14:46:45.331645 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 14:46:45.335210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 14:46:45.338564 ==
4293 14:46:45.338648 DQS Delay:
4294 14:46:45.338713 DQS0 = 0, DQS1 = 0
4295 14:46:45.341155 DQM Delay:
4296 14:46:45.341238 DQM0 = 40, DQM1 = 33
4297 14:46:45.344346 DQ Delay:
4298 14:46:45.344427 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =36
4299 14:46:45.347792 DQ4 =44, DQ5 =28, DQ6 =52, DQ7 =44
4300 14:46:45.351023 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =24
4301 14:46:45.354764 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4302 14:46:45.357581
4303 14:46:45.357662
4304 14:46:45.364584 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a46, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
4305 14:46:45.367477 CH0 RK1: MR19=808, MR18=4A46
4306 14:46:45.374377 CH0_RK1: MR19=0x808, MR18=0x4A46, DQSOSC=395, MR23=63, INC=168, DEC=112
4307 14:46:45.377912 [RxdqsGatingPostProcess] freq 600
4308 14:46:45.380873 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4309 14:46:45.383858 Pre-setting of DQS Precalculation
4310 14:46:45.390611 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4311 14:46:45.390695 ==
4312 14:46:45.393948 Dram Type= 6, Freq= 0, CH_1, rank 0
4313 14:46:45.397710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4314 14:46:45.397793 ==
4315 14:46:45.404465 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4316 14:46:45.407124 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4317 14:46:45.411542 [CA 0] Center 36 (6~66) winsize 61
4318 14:46:45.415370 [CA 1] Center 35 (5~66) winsize 62
4319 14:46:45.418526 [CA 2] Center 34 (4~65) winsize 62
4320 14:46:45.421436 [CA 3] Center 34 (3~65) winsize 63
4321 14:46:45.424779 [CA 4] Center 34 (4~65) winsize 62
4322 14:46:45.427954 [CA 5] Center 34 (3~65) winsize 63
4323 14:46:45.428037
4324 14:46:45.431567 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4325 14:46:45.431649
4326 14:46:45.434335 [CATrainingPosCal] consider 1 rank data
4327 14:46:45.437840 u2DelayCellTimex100 = 270/100 ps
4328 14:46:45.441094 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4329 14:46:45.447575 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4330 14:46:45.451108 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4331 14:46:45.454426 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4332 14:46:45.457914 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4333 14:46:45.460661 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4334 14:46:45.460744
4335 14:46:45.464945 CA PerBit enable=1, Macro0, CA PI delay=34
4336 14:46:45.465030
4337 14:46:45.467316 [CBTSetCACLKResult] CA Dly = 34
4338 14:46:45.470460 CS Dly: 4 (0~35)
4339 14:46:45.470570 ==
4340 14:46:45.474226 Dram Type= 6, Freq= 0, CH_1, rank 1
4341 14:46:45.477211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 14:46:45.477303 ==
4343 14:46:45.484215 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4344 14:46:45.487051 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4345 14:46:45.491779 [CA 0] Center 35 (5~66) winsize 62
4346 14:46:45.495108 [CA 1] Center 35 (5~66) winsize 62
4347 14:46:45.498075 [CA 2] Center 34 (4~65) winsize 62
4348 14:46:45.501743 [CA 3] Center 34 (3~65) winsize 63
4349 14:46:45.505056 [CA 4] Center 34 (4~65) winsize 62
4350 14:46:45.508562 [CA 5] Center 34 (3~65) winsize 63
4351 14:46:45.508649
4352 14:46:45.511539 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4353 14:46:45.511653
4354 14:46:45.514949 [CATrainingPosCal] consider 2 rank data
4355 14:46:45.517782 u2DelayCellTimex100 = 270/100 ps
4356 14:46:45.521178 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4357 14:46:45.528005 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4358 14:46:45.531346 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4359 14:46:45.534540 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4360 14:46:45.537508 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4361 14:46:45.540861 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4362 14:46:45.540948
4363 14:46:45.544276 CA PerBit enable=1, Macro0, CA PI delay=34
4364 14:46:45.544359
4365 14:46:45.547385 [CBTSetCACLKResult] CA Dly = 34
4366 14:46:45.550694 CS Dly: 4 (0~36)
4367 14:46:45.550776
4368 14:46:45.554258 ----->DramcWriteLeveling(PI) begin...
4369 14:46:45.554342 ==
4370 14:46:45.557687 Dram Type= 6, Freq= 0, CH_1, rank 0
4371 14:46:45.560805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4372 14:46:45.560887 ==
4373 14:46:45.563754 Write leveling (Byte 0): 28 => 28
4374 14:46:45.567572 Write leveling (Byte 1): 28 => 28
4375 14:46:45.570882 DramcWriteLeveling(PI) end<-----
4376 14:46:45.570964
4377 14:46:45.571028 ==
4378 14:46:45.573840 Dram Type= 6, Freq= 0, CH_1, rank 0
4379 14:46:45.577033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4380 14:46:45.577118 ==
4381 14:46:45.580457 [Gating] SW mode calibration
4382 14:46:45.587772 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4383 14:46:45.593596 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4384 14:46:45.596895 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4385 14:46:45.599995 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4386 14:46:45.606389 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4387 14:46:45.610160 0 9 12 | B1->B0 | 2f2f 2f2f | 1 0 | (1 0) (0 0)
4388 14:46:45.613604 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4389 14:46:45.620154 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4390 14:46:45.622911 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4391 14:46:45.629604 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4392 14:46:45.633633 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4393 14:46:45.636047 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4394 14:46:45.642876 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4395 14:46:45.646290 0 10 12 | B1->B0 | 3535 3a3a | 0 0 | (0 0) (0 0)
4396 14:46:45.649513 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4397 14:46:45.656296 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4398 14:46:45.659057 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4399 14:46:45.662420 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4400 14:46:45.669176 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4401 14:46:45.672741 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4402 14:46:45.675497 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4403 14:46:45.681990 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4404 14:46:45.685995 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4405 14:46:45.688455 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4406 14:46:45.695976 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4407 14:46:45.698449 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4408 14:46:45.701525 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4409 14:46:45.708468 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4410 14:46:45.711393 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4411 14:46:45.714610 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4412 14:46:45.721753 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4413 14:46:45.724316 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4414 14:46:45.728364 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4415 14:46:45.734477 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4416 14:46:45.737656 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4417 14:46:45.740927 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 14:46:45.747560 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 14:46:45.750787 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4420 14:46:45.754155 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 14:46:45.757608 Total UI for P1: 0, mck2ui 16
4422 14:46:45.761269 best dqsien dly found for B0: ( 0, 13, 12)
4423 14:46:45.764678 Total UI for P1: 0, mck2ui 16
4424 14:46:45.767332 best dqsien dly found for B1: ( 0, 13, 12)
4425 14:46:45.771370 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4426 14:46:45.774001 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4427 14:46:45.777021
4428 14:46:45.780707 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4429 14:46:45.783892 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4430 14:46:45.787608 [Gating] SW calibration Done
4431 14:46:45.787692 ==
4432 14:46:45.790275 Dram Type= 6, Freq= 0, CH_1, rank 0
4433 14:46:45.793694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4434 14:46:45.793777 ==
4435 14:46:45.797301 RX Vref Scan: 0
4436 14:46:45.797397
4437 14:46:45.797461 RX Vref 0 -> 0, step: 1
4438 14:46:45.797521
4439 14:46:45.800326 RX Delay -230 -> 252, step: 16
4440 14:46:45.803515 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4441 14:46:45.810438 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4442 14:46:45.813770 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4443 14:46:45.816828 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4444 14:46:45.819783 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4445 14:46:45.826510 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4446 14:46:45.829699 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4447 14:46:45.833571 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4448 14:46:45.836623 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4449 14:46:45.842851 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4450 14:46:45.846792 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4451 14:46:45.849433 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4452 14:46:45.852598 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4453 14:46:45.859205 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4454 14:46:45.862822 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4455 14:46:45.865800 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4456 14:46:45.865884 ==
4457 14:46:45.869284 Dram Type= 6, Freq= 0, CH_1, rank 0
4458 14:46:45.872342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4459 14:46:45.875771 ==
4460 14:46:45.875854 DQS Delay:
4461 14:46:45.875918 DQS0 = 0, DQS1 = 0
4462 14:46:45.880248 DQM Delay:
4463 14:46:45.880334 DQM0 = 42, DQM1 = 39
4464 14:46:45.882693 DQ Delay:
4465 14:46:45.882775 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4466 14:46:45.885880 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4467 14:46:45.889683 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4468 14:46:45.892291 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4469 14:46:45.892373
4470 14:46:45.896004
4471 14:46:45.896086 ==
4472 14:46:45.898990 Dram Type= 6, Freq= 0, CH_1, rank 0
4473 14:46:45.902293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4474 14:46:45.902377 ==
4475 14:46:45.902441
4476 14:46:45.902501
4477 14:46:45.905635 TX Vref Scan disable
4478 14:46:45.905716 == TX Byte 0 ==
4479 14:46:45.911967 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4480 14:46:45.915959 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4481 14:46:45.916060 == TX Byte 1 ==
4482 14:46:45.922923 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4483 14:46:45.925425 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4484 14:46:45.925508 ==
4485 14:46:45.928931 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 14:46:45.931728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 14:46:45.931810 ==
4488 14:46:45.931874
4489 14:46:45.931951
4490 14:46:45.934892 TX Vref Scan disable
4491 14:46:45.938365 == TX Byte 0 ==
4492 14:46:45.942071 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4493 14:46:45.948308 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4494 14:46:45.948395 == TX Byte 1 ==
4495 14:46:45.951468 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4496 14:46:45.958764 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4497 14:46:45.958851
4498 14:46:45.958935 [DATLAT]
4499 14:46:45.959115 Freq=600, CH1 RK0
4500 14:46:45.959224
4501 14:46:45.961243 DATLAT Default: 0x9
4502 14:46:45.961363 0, 0xFFFF, sum = 0
4503 14:46:45.964341 1, 0xFFFF, sum = 0
4504 14:46:45.968619 2, 0xFFFF, sum = 0
4505 14:46:45.968702 3, 0xFFFF, sum = 0
4506 14:46:45.971861 4, 0xFFFF, sum = 0
4507 14:46:45.971944 5, 0xFFFF, sum = 0
4508 14:46:45.974516 6, 0xFFFF, sum = 0
4509 14:46:45.974599 7, 0xFFFF, sum = 0
4510 14:46:45.977849 8, 0x0, sum = 1
4511 14:46:45.977934 9, 0x0, sum = 2
4512 14:46:45.981087 10, 0x0, sum = 3
4513 14:46:45.981172 11, 0x0, sum = 4
4514 14:46:45.981238 best_step = 9
4515 14:46:45.981341
4516 14:46:45.984390 ==
4517 14:46:45.987508 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 14:46:45.990960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 14:46:45.991049 ==
4520 14:46:45.991115 RX Vref Scan: 1
4521 14:46:45.991175
4522 14:46:45.994515 RX Vref 0 -> 0, step: 1
4523 14:46:45.994600
4524 14:46:45.997619 RX Delay -179 -> 252, step: 8
4525 14:46:45.997710
4526 14:46:46.000746 Set Vref, RX VrefLevel [Byte0]: 51
4527 14:46:46.004414 [Byte1]: 54
4528 14:46:46.004499
4529 14:46:46.007329 Final RX Vref Byte 0 = 51 to rank0
4530 14:46:46.011123 Final RX Vref Byte 1 = 54 to rank0
4531 14:46:46.014073 Final RX Vref Byte 0 = 51 to rank1
4532 14:46:46.017182 Final RX Vref Byte 1 = 54 to rank1==
4533 14:46:46.020748 Dram Type= 6, Freq= 0, CH_1, rank 0
4534 14:46:46.027220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4535 14:46:46.027318 ==
4536 14:46:46.027386 DQS Delay:
4537 14:46:46.027446 DQS0 = 0, DQS1 = 0
4538 14:46:46.030635 DQM Delay:
4539 14:46:46.030718 DQM0 = 42, DQM1 = 34
4540 14:46:46.034106 DQ Delay:
4541 14:46:46.037446 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4542 14:46:46.040082 DQ4 =36, DQ5 =48, DQ6 =56, DQ7 =36
4543 14:46:46.043375 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4544 14:46:46.046871 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4545 14:46:46.046962
4546 14:46:46.047026
4547 14:46:46.053269 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f49, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 400 ps
4548 14:46:46.056516 CH1 RK0: MR19=808, MR18=2F49
4549 14:46:46.063917 CH1_RK0: MR19=0x808, MR18=0x2F49, DQSOSC=396, MR23=63, INC=167, DEC=111
4550 14:46:46.064008
4551 14:46:46.066624 ----->DramcWriteLeveling(PI) begin...
4552 14:46:46.066707 ==
4553 14:46:46.069980 Dram Type= 6, Freq= 0, CH_1, rank 1
4554 14:46:46.073591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4555 14:46:46.073677 ==
4556 14:46:46.076219 Write leveling (Byte 0): 30 => 30
4557 14:46:46.079363 Write leveling (Byte 1): 29 => 29
4558 14:46:46.082638 DramcWriteLeveling(PI) end<-----
4559 14:46:46.082747
4560 14:46:46.082838 ==
4561 14:46:46.086128 Dram Type= 6, Freq= 0, CH_1, rank 1
4562 14:46:46.092725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 14:46:46.092815 ==
4564 14:46:46.092934 [Gating] SW mode calibration
4565 14:46:46.102960 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4566 14:46:46.106497 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4567 14:46:46.109478 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4568 14:46:46.116343 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4569 14:46:46.119324 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4570 14:46:46.122702 0 9 12 | B1->B0 | 3030 2929 | 1 0 | (1 0) (1 0)
4571 14:46:46.129055 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4572 14:46:46.133811 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4573 14:46:46.135881 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4574 14:46:46.142330 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4575 14:46:46.146016 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4576 14:46:46.148921 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4577 14:46:46.155379 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4578 14:46:46.158891 0 10 12 | B1->B0 | 3131 3e3e | 0 0 | (0 0) (0 0)
4579 14:46:46.162049 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4580 14:46:46.168548 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4581 14:46:46.172071 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4582 14:46:46.174948 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4583 14:46:46.181506 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4584 14:46:46.185035 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4585 14:46:46.188374 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4586 14:46:46.194783 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4587 14:46:46.198159 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4588 14:46:46.201506 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4589 14:46:46.208172 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4590 14:46:46.211303 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4591 14:46:46.214724 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4592 14:46:46.221234 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4593 14:46:46.224943 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4594 14:46:46.227981 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4595 14:46:46.234301 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4596 14:46:46.237862 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4597 14:46:46.240768 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4598 14:46:46.247732 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4599 14:46:46.250968 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4600 14:46:46.254402 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4601 14:46:46.260763 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4602 14:46:46.264096 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 14:46:46.267271 Total UI for P1: 0, mck2ui 16
4604 14:46:46.270570 best dqsien dly found for B0: ( 0, 13, 8)
4605 14:46:46.274052 Total UI for P1: 0, mck2ui 16
4606 14:46:46.277922 best dqsien dly found for B1: ( 0, 13, 10)
4607 14:46:46.280300 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4608 14:46:46.283821 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4609 14:46:46.283897
4610 14:46:46.287110 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4611 14:46:46.294005 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4612 14:46:46.294088 [Gating] SW calibration Done
4613 14:46:46.294163 ==
4614 14:46:46.296592 Dram Type= 6, Freq= 0, CH_1, rank 1
4615 14:46:46.303661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4616 14:46:46.303764 ==
4617 14:46:46.303829 RX Vref Scan: 0
4618 14:46:46.303888
4619 14:46:46.307161 RX Vref 0 -> 0, step: 1
4620 14:46:46.307246
4621 14:46:46.310698 RX Delay -230 -> 252, step: 16
4622 14:46:46.314048 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4623 14:46:46.316741 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4624 14:46:46.323074 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4625 14:46:46.326410 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4626 14:46:46.330690 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4627 14:46:46.332870 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4628 14:46:46.336244 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4629 14:46:46.343327 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4630 14:46:46.346482 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4631 14:46:46.349350 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4632 14:46:46.352853 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4633 14:46:46.359930 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4634 14:46:46.363050 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4635 14:46:46.366379 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4636 14:46:46.369621 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4637 14:46:46.376070 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4638 14:46:46.376162 ==
4639 14:46:46.379960 Dram Type= 6, Freq= 0, CH_1, rank 1
4640 14:46:46.382899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4641 14:46:46.382977 ==
4642 14:46:46.383049 DQS Delay:
4643 14:46:46.386121 DQS0 = 0, DQS1 = 0
4644 14:46:46.386194 DQM Delay:
4645 14:46:46.389441 DQM0 = 42, DQM1 = 38
4646 14:46:46.389512 DQ Delay:
4647 14:46:46.392522 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4648 14:46:46.395949 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4649 14:46:46.399412 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4650 14:46:46.401982 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4651 14:46:46.402089
4652 14:46:46.402178
4653 14:46:46.402269 ==
4654 14:46:46.405285 Dram Type= 6, Freq= 0, CH_1, rank 1
4655 14:46:46.412126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4656 14:46:46.412249 ==
4657 14:46:46.412350
4658 14:46:46.412454
4659 14:46:46.412540 TX Vref Scan disable
4660 14:46:46.415472 == TX Byte 0 ==
4661 14:46:46.418898 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4662 14:46:46.425067 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4663 14:46:46.425190 == TX Byte 1 ==
4664 14:46:46.428377 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4665 14:46:46.435080 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4666 14:46:46.435195 ==
4667 14:46:46.438386 Dram Type= 6, Freq= 0, CH_1, rank 1
4668 14:46:46.441707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4669 14:46:46.441821 ==
4670 14:46:46.441912
4671 14:46:46.442004
4672 14:46:46.445199 TX Vref Scan disable
4673 14:46:46.448524 == TX Byte 0 ==
4674 14:46:46.451467 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4675 14:46:46.454996 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4676 14:46:46.458136 == TX Byte 1 ==
4677 14:46:46.461635 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4678 14:46:46.464698 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4679 14:46:46.464807
4680 14:46:46.467773 [DATLAT]
4681 14:46:46.467853 Freq=600, CH1 RK1
4682 14:46:46.467916
4683 14:46:46.471865 DATLAT Default: 0x9
4684 14:46:46.471945 0, 0xFFFF, sum = 0
4685 14:46:46.474836 1, 0xFFFF, sum = 0
4686 14:46:46.474966 2, 0xFFFF, sum = 0
4687 14:46:46.477992 3, 0xFFFF, sum = 0
4688 14:46:46.478108 4, 0xFFFF, sum = 0
4689 14:46:46.481288 5, 0xFFFF, sum = 0
4690 14:46:46.481384 6, 0xFFFF, sum = 0
4691 14:46:46.484372 7, 0xFFFF, sum = 0
4692 14:46:46.484456 8, 0x0, sum = 1
4693 14:46:46.488220 9, 0x0, sum = 2
4694 14:46:46.488332 10, 0x0, sum = 3
4695 14:46:46.491400 11, 0x0, sum = 4
4696 14:46:46.491481 best_step = 9
4697 14:46:46.491543
4698 14:46:46.491600 ==
4699 14:46:46.494738 Dram Type= 6, Freq= 0, CH_1, rank 1
4700 14:46:46.497909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4701 14:46:46.501524 ==
4702 14:46:46.501638 RX Vref Scan: 0
4703 14:46:46.501729
4704 14:46:46.504428 RX Vref 0 -> 0, step: 1
4705 14:46:46.504508
4706 14:46:46.507778 RX Delay -179 -> 252, step: 8
4707 14:46:46.510738 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4708 14:46:46.514234 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4709 14:46:46.520669 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4710 14:46:46.523933 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4711 14:46:46.526931 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4712 14:46:46.530482 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4713 14:46:46.537171 iDelay=205, Bit 6, Center 40 (-115 ~ 196) 312
4714 14:46:46.540300 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4715 14:46:46.543508 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4716 14:46:46.546951 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4717 14:46:46.553887 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4718 14:46:46.556918 iDelay=205, Bit 11, Center 28 (-131 ~ 188) 320
4719 14:46:46.560840 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4720 14:46:46.563369 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4721 14:46:46.569787 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4722 14:46:46.573450 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4723 14:46:46.573527 ==
4724 14:46:46.576382 Dram Type= 6, Freq= 0, CH_1, rank 1
4725 14:46:46.579858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4726 14:46:46.579974 ==
4727 14:46:46.583231 DQS Delay:
4728 14:46:46.583308 DQS0 = 0, DQS1 = 0
4729 14:46:46.583371 DQM Delay:
4730 14:46:46.586295 DQM0 = 37, DQM1 = 35
4731 14:46:46.586370 DQ Delay:
4732 14:46:46.589751 DQ0 =44, DQ1 =36, DQ2 =24, DQ3 =36
4733 14:46:46.592903 DQ4 =36, DQ5 =48, DQ6 =40, DQ7 =32
4734 14:46:46.596547 DQ8 =20, DQ9 =24, DQ10 =40, DQ11 =28
4735 14:46:46.600021 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4736 14:46:46.600103
4737 14:46:46.600165
4738 14:46:46.609418 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a5f, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
4739 14:46:46.612783 CH1 RK1: MR19=808, MR18=3A5F
4740 14:46:46.619213 CH1_RK1: MR19=0x808, MR18=0x3A5F, DQSOSC=391, MR23=63, INC=171, DEC=114
4741 14:46:46.619302 [RxdqsGatingPostProcess] freq 600
4742 14:46:46.625730 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4743 14:46:46.629266 Pre-setting of DQS Precalculation
4744 14:46:46.632213 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4745 14:46:46.642048 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4746 14:46:46.649399 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4747 14:46:46.649485
4748 14:46:46.649548
4749 14:46:46.651974 [Calibration Summary] 1200 Mbps
4750 14:46:46.652041 CH 0, Rank 0
4751 14:46:46.655488 SW Impedance : PASS
4752 14:46:46.658722 DUTY Scan : NO K
4753 14:46:46.658837 ZQ Calibration : PASS
4754 14:46:46.662031 Jitter Meter : NO K
4755 14:46:46.662109 CBT Training : PASS
4756 14:46:46.665161 Write leveling : PASS
4757 14:46:46.668884 RX DQS gating : PASS
4758 14:46:46.668976 RX DQ/DQS(RDDQC) : PASS
4759 14:46:46.671813 TX DQ/DQS : PASS
4760 14:46:46.675238 RX DATLAT : PASS
4761 14:46:46.675310 RX DQ/DQS(Engine): PASS
4762 14:46:46.678669 TX OE : NO K
4763 14:46:46.678747 All Pass.
4764 14:46:46.678809
4765 14:46:46.681618 CH 0, Rank 1
4766 14:46:46.681728 SW Impedance : PASS
4767 14:46:46.685051 DUTY Scan : NO K
4768 14:46:46.688212 ZQ Calibration : PASS
4769 14:46:46.688295 Jitter Meter : NO K
4770 14:46:46.691667 CBT Training : PASS
4771 14:46:46.695046 Write leveling : PASS
4772 14:46:46.695119 RX DQS gating : PASS
4773 14:46:46.698273 RX DQ/DQS(RDDQC) : PASS
4774 14:46:46.702392 TX DQ/DQS : PASS
4775 14:46:46.702476 RX DATLAT : PASS
4776 14:46:46.704666 RX DQ/DQS(Engine): PASS
4777 14:46:46.708366 TX OE : NO K
4778 14:46:46.708451 All Pass.
4779 14:46:46.708513
4780 14:46:46.708571 CH 1, Rank 0
4781 14:46:46.711345 SW Impedance : PASS
4782 14:46:46.714751 DUTY Scan : NO K
4783 14:46:46.714826 ZQ Calibration : PASS
4784 14:46:46.717660 Jitter Meter : NO K
4785 14:46:46.721235 CBT Training : PASS
4786 14:46:46.721361 Write leveling : PASS
4787 14:46:46.725044 RX DQS gating : PASS
4788 14:46:46.728283 RX DQ/DQS(RDDQC) : PASS
4789 14:46:46.728365 TX DQ/DQS : PASS
4790 14:46:46.730921 RX DATLAT : PASS
4791 14:46:46.734922 RX DQ/DQS(Engine): PASS
4792 14:46:46.734998 TX OE : NO K
4793 14:46:46.735061 All Pass.
4794 14:46:46.738157
4795 14:46:46.738253 CH 1, Rank 1
4796 14:46:46.740980 SW Impedance : PASS
4797 14:46:46.741061 DUTY Scan : NO K
4798 14:46:46.744636 ZQ Calibration : PASS
4799 14:46:46.744717 Jitter Meter : NO K
4800 14:46:46.748182 CBT Training : PASS
4801 14:46:46.750882 Write leveling : PASS
4802 14:46:46.750955 RX DQS gating : PASS
4803 14:46:46.753908 RX DQ/DQS(RDDQC) : PASS
4804 14:46:46.757521 TX DQ/DQS : PASS
4805 14:46:46.757600 RX DATLAT : PASS
4806 14:46:46.760555 RX DQ/DQS(Engine): PASS
4807 14:46:46.764026 TX OE : NO K
4808 14:46:46.764107 All Pass.
4809 14:46:46.764168
4810 14:46:46.767233 DramC Write-DBI off
4811 14:46:46.767303 PER_BANK_REFRESH: Hybrid Mode
4812 14:46:46.770428 TX_TRACKING: ON
4813 14:46:46.780559 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4814 14:46:46.783700 [FAST_K] Save calibration result to emmc
4815 14:46:46.787126 dramc_set_vcore_voltage set vcore to 662500
4816 14:46:46.787202 Read voltage for 933, 3
4817 14:46:46.790124 Vio18 = 0
4818 14:46:46.790230 Vcore = 662500
4819 14:46:46.790319 Vdram = 0
4820 14:46:46.794294 Vddq = 0
4821 14:46:46.794366 Vmddr = 0
4822 14:46:46.800266 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4823 14:46:46.803746 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4824 14:46:46.806437 MEM_TYPE=3, freq_sel=17
4825 14:46:46.809912 sv_algorithm_assistance_LP4_1600
4826 14:46:46.813298 ============ PULL DRAM RESETB DOWN ============
4827 14:46:46.817198 ========== PULL DRAM RESETB DOWN end =========
4828 14:46:46.823826 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4829 14:46:46.826615 ===================================
4830 14:46:46.826703 LPDDR4 DRAM CONFIGURATION
4831 14:46:46.829822 ===================================
4832 14:46:46.833074 EX_ROW_EN[0] = 0x0
4833 14:46:46.836693 EX_ROW_EN[1] = 0x0
4834 14:46:46.836780 LP4Y_EN = 0x0
4835 14:46:46.840115 WORK_FSP = 0x0
4836 14:46:46.840190 WL = 0x3
4837 14:46:46.843528 RL = 0x3
4838 14:46:46.843612 BL = 0x2
4839 14:46:46.846225 RPST = 0x0
4840 14:46:46.846309 RD_PRE = 0x0
4841 14:46:46.849473 WR_PRE = 0x1
4842 14:46:46.849562 WR_PST = 0x0
4843 14:46:46.852715 DBI_WR = 0x0
4844 14:46:46.852824 DBI_RD = 0x0
4845 14:46:46.856552 OTF = 0x1
4846 14:46:46.859899 ===================================
4847 14:46:46.863088 ===================================
4848 14:46:46.863171 ANA top config
4849 14:46:46.866256 ===================================
4850 14:46:46.869110 DLL_ASYNC_EN = 0
4851 14:46:46.872450 ALL_SLAVE_EN = 1
4852 14:46:46.876225 NEW_RANK_MODE = 1
4853 14:46:46.876302 DLL_IDLE_MODE = 1
4854 14:46:46.879169 LP45_APHY_COMB_EN = 1
4855 14:46:46.882194 TX_ODT_DIS = 1
4856 14:46:46.885920 NEW_8X_MODE = 1
4857 14:46:46.888994 ===================================
4858 14:46:46.892464 ===================================
4859 14:46:46.895688 data_rate = 1866
4860 14:46:46.899131 CKR = 1
4861 14:46:46.899215 DQ_P2S_RATIO = 8
4862 14:46:46.902789 ===================================
4863 14:46:46.905716 CA_P2S_RATIO = 8
4864 14:46:46.908773 DQ_CA_OPEN = 0
4865 14:46:46.913425 DQ_SEMI_OPEN = 0
4866 14:46:46.915607 CA_SEMI_OPEN = 0
4867 14:46:46.918565 CA_FULL_RATE = 0
4868 14:46:46.918644 DQ_CKDIV4_EN = 1
4869 14:46:46.921669 CA_CKDIV4_EN = 1
4870 14:46:46.924941 CA_PREDIV_EN = 0
4871 14:46:46.928364 PH8_DLY = 0
4872 14:46:46.931703 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4873 14:46:46.934757 DQ_AAMCK_DIV = 4
4874 14:46:46.934833 CA_AAMCK_DIV = 4
4875 14:46:46.938123 CA_ADMCK_DIV = 4
4876 14:46:46.941864 DQ_TRACK_CA_EN = 0
4877 14:46:46.944833 CA_PICK = 933
4878 14:46:46.947995 CA_MCKIO = 933
4879 14:46:46.951176 MCKIO_SEMI = 0
4880 14:46:46.954632 PLL_FREQ = 3732
4881 14:46:46.957954 DQ_UI_PI_RATIO = 32
4882 14:46:46.958073 CA_UI_PI_RATIO = 0
4883 14:46:46.961937 ===================================
4884 14:46:46.964859 ===================================
4885 14:46:46.967562 memory_type:LPDDR4
4886 14:46:46.971197 GP_NUM : 10
4887 14:46:46.971270 SRAM_EN : 1
4888 14:46:46.974414 MD32_EN : 0
4889 14:46:46.977620 ===================================
4890 14:46:46.981250 [ANA_INIT] >>>>>>>>>>>>>>
4891 14:46:46.984340 <<<<<< [CONFIGURE PHASE]: ANA_TX
4892 14:46:46.988121 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4893 14:46:46.990960 ===================================
4894 14:46:46.991079 data_rate = 1866,PCW = 0X8f00
4895 14:46:46.994247 ===================================
4896 14:46:46.997578 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4897 14:46:47.004344 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4898 14:46:47.011106 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4899 14:46:47.014175 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4900 14:46:47.017140 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4901 14:46:47.020693 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4902 14:46:47.024071 [ANA_INIT] flow start
4903 14:46:47.027238 [ANA_INIT] PLL >>>>>>>>
4904 14:46:47.027321 [ANA_INIT] PLL <<<<<<<<
4905 14:46:47.030702 [ANA_INIT] MIDPI >>>>>>>>
4906 14:46:47.033642 [ANA_INIT] MIDPI <<<<<<<<
4907 14:46:47.033774 [ANA_INIT] DLL >>>>>>>>
4908 14:46:47.037127 [ANA_INIT] flow end
4909 14:46:47.040322 ============ LP4 DIFF to SE enter ============
4910 14:46:47.047134 ============ LP4 DIFF to SE exit ============
4911 14:46:47.047252 [ANA_INIT] <<<<<<<<<<<<<
4912 14:46:47.050278 [Flow] Enable top DCM control >>>>>
4913 14:46:47.053465 [Flow] Enable top DCM control <<<<<
4914 14:46:47.056908 Enable DLL master slave shuffle
4915 14:46:47.063596 ==============================================================
4916 14:46:47.063698 Gating Mode config
4917 14:46:47.070096 ==============================================================
4918 14:46:47.073175 Config description:
4919 14:46:47.083192 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4920 14:46:47.089650 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4921 14:46:47.093601 SELPH_MODE 0: By rank 1: By Phase
4922 14:46:47.099953 ==============================================================
4923 14:46:47.102932 GAT_TRACK_EN = 1
4924 14:46:47.106189 RX_GATING_MODE = 2
4925 14:46:47.106272 RX_GATING_TRACK_MODE = 2
4926 14:46:47.109610 SELPH_MODE = 1
4927 14:46:47.112700 PICG_EARLY_EN = 1
4928 14:46:47.116548 VALID_LAT_VALUE = 1
4929 14:46:47.122617 ==============================================================
4930 14:46:47.125929 Enter into Gating configuration >>>>
4931 14:46:47.128967 Exit from Gating configuration <<<<
4932 14:46:47.132603 Enter into DVFS_PRE_config >>>>>
4933 14:46:47.142308 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4934 14:46:47.145717 Exit from DVFS_PRE_config <<<<<
4935 14:46:47.148918 Enter into PICG configuration >>>>
4936 14:46:47.152623 Exit from PICG configuration <<<<
4937 14:46:47.155743 [RX_INPUT] configuration >>>>>
4938 14:46:47.158763 [RX_INPUT] configuration <<<<<
4939 14:46:47.162236 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4940 14:46:47.168891 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4941 14:46:47.175293 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4942 14:46:47.181654 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4943 14:46:47.188859 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4944 14:46:47.191831 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4945 14:46:47.198029 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4946 14:46:47.202226 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4947 14:46:47.205086 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4948 14:46:47.208391 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4949 14:46:47.214872 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4950 14:46:47.218110 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4951 14:46:47.221190 ===================================
4952 14:46:47.224595 LPDDR4 DRAM CONFIGURATION
4953 14:46:47.227968 ===================================
4954 14:46:47.228068 EX_ROW_EN[0] = 0x0
4955 14:46:47.231527 EX_ROW_EN[1] = 0x0
4956 14:46:47.234467 LP4Y_EN = 0x0
4957 14:46:47.234549 WORK_FSP = 0x0
4958 14:46:47.237873 WL = 0x3
4959 14:46:47.237955 RL = 0x3
4960 14:46:47.241185 BL = 0x2
4961 14:46:47.241295 RPST = 0x0
4962 14:46:47.244383 RD_PRE = 0x0
4963 14:46:47.244498 WR_PRE = 0x1
4964 14:46:47.248070 WR_PST = 0x0
4965 14:46:47.248187 DBI_WR = 0x0
4966 14:46:47.251406 DBI_RD = 0x0
4967 14:46:47.251491 OTF = 0x1
4968 14:46:47.253966 ===================================
4969 14:46:47.257191 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4970 14:46:47.264442 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4971 14:46:47.267733 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4972 14:46:47.270818 ===================================
4973 14:46:47.274071 LPDDR4 DRAM CONFIGURATION
4974 14:46:47.276969 ===================================
4975 14:46:47.277071 EX_ROW_EN[0] = 0x10
4976 14:46:47.280616 EX_ROW_EN[1] = 0x0
4977 14:46:47.284014 LP4Y_EN = 0x0
4978 14:46:47.284117 WORK_FSP = 0x0
4979 14:46:47.287041 WL = 0x3
4980 14:46:47.287126 RL = 0x3
4981 14:46:47.290327 BL = 0x2
4982 14:46:47.290432 RPST = 0x0
4983 14:46:47.293826 RD_PRE = 0x0
4984 14:46:47.293930 WR_PRE = 0x1
4985 14:46:47.296850 WR_PST = 0x0
4986 14:46:47.296952 DBI_WR = 0x0
4987 14:46:47.300679 DBI_RD = 0x0
4988 14:46:47.300787 OTF = 0x1
4989 14:46:47.303464 ===================================
4990 14:46:47.309956 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4991 14:46:47.314718 nWR fixed to 30
4992 14:46:47.318004 [ModeRegInit_LP4] CH0 RK0
4993 14:46:47.318109 [ModeRegInit_LP4] CH0 RK1
4994 14:46:47.321168 [ModeRegInit_LP4] CH1 RK0
4995 14:46:47.324200 [ModeRegInit_LP4] CH1 RK1
4996 14:46:47.324284 match AC timing 9
4997 14:46:47.331167 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
4998 14:46:47.334635 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4999 14:46:47.337975 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5000 14:46:47.344437 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5001 14:46:47.348297 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5002 14:46:47.348388 ==
5003 14:46:47.351198 Dram Type= 6, Freq= 0, CH_0, rank 0
5004 14:46:47.354378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5005 14:46:47.354486 ==
5006 14:46:47.361347 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5007 14:46:47.368795 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5008 14:46:47.370598 [CA 0] Center 37 (7~68) winsize 62
5009 14:46:47.374004 [CA 1] Center 37 (7~68) winsize 62
5010 14:46:47.377100 [CA 2] Center 34 (4~64) winsize 61
5011 14:46:47.380598 [CA 3] Center 34 (4~65) winsize 62
5012 14:46:47.383801 [CA 4] Center 33 (3~64) winsize 62
5013 14:46:47.387700 [CA 5] Center 32 (2~63) winsize 62
5014 14:46:47.387784
5015 14:46:47.390675 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5016 14:46:47.390757
5017 14:46:47.394217 [CATrainingPosCal] consider 1 rank data
5018 14:46:47.396897 u2DelayCellTimex100 = 270/100 ps
5019 14:46:47.400686 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5020 14:46:47.403740 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5021 14:46:47.406937 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5022 14:46:47.413777 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5023 14:46:47.416826 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5024 14:46:47.420697 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5025 14:46:47.420800
5026 14:46:47.423511 CA PerBit enable=1, Macro0, CA PI delay=32
5027 14:46:47.423594
5028 14:46:47.426721 [CBTSetCACLKResult] CA Dly = 32
5029 14:46:47.426848 CS Dly: 5 (0~36)
5030 14:46:47.426949 ==
5031 14:46:47.429746 Dram Type= 6, Freq= 0, CH_0, rank 1
5032 14:46:47.436500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5033 14:46:47.436602 ==
5034 14:46:47.439864 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5035 14:46:47.446528 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5036 14:46:47.449510 [CA 0] Center 37 (7~68) winsize 62
5037 14:46:47.453245 [CA 1] Center 37 (7~68) winsize 62
5038 14:46:47.456506 [CA 2] Center 34 (4~65) winsize 62
5039 14:46:47.460159 [CA 3] Center 34 (4~65) winsize 62
5040 14:46:47.463401 [CA 4] Center 33 (3~64) winsize 62
5041 14:46:47.466558 [CA 5] Center 33 (3~63) winsize 61
5042 14:46:47.466657
5043 14:46:47.469980 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5044 14:46:47.470078
5045 14:46:47.472936 [CATrainingPosCal] consider 2 rank data
5046 14:46:47.476862 u2DelayCellTimex100 = 270/100 ps
5047 14:46:47.479271 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5048 14:46:47.485963 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5049 14:46:47.489884 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5050 14:46:47.492758 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5051 14:46:47.495860 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5052 14:46:47.499361 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5053 14:46:47.499435
5054 14:46:47.503329 CA PerBit enable=1, Macro0, CA PI delay=33
5055 14:46:47.503411
5056 14:46:47.506260 [CBTSetCACLKResult] CA Dly = 33
5057 14:46:47.506335 CS Dly: 6 (0~39)
5058 14:46:47.509781
5059 14:46:47.512609 ----->DramcWriteLeveling(PI) begin...
5060 14:46:47.512689 ==
5061 14:46:47.515730 Dram Type= 6, Freq= 0, CH_0, rank 0
5062 14:46:47.518946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5063 14:46:47.519025 ==
5064 14:46:47.522547 Write leveling (Byte 0): 31 => 31
5065 14:46:47.525741 Write leveling (Byte 1): 28 => 28
5066 14:46:47.528992 DramcWriteLeveling(PI) end<-----
5067 14:46:47.529101
5068 14:46:47.529191 ==
5069 14:46:47.532133 Dram Type= 6, Freq= 0, CH_0, rank 0
5070 14:46:47.535611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5071 14:46:47.535694 ==
5072 14:46:47.538894 [Gating] SW mode calibration
5073 14:46:47.545461 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5074 14:46:47.551995 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5075 14:46:47.555488 0 14 0 | B1->B0 | 2626 3333 | 1 1 | (0 0) (1 1)
5076 14:46:47.559087 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5077 14:46:47.565547 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5078 14:46:47.568291 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5079 14:46:47.571512 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5080 14:46:47.578202 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5081 14:46:47.581833 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5082 14:46:47.585043 0 14 28 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5083 14:46:47.591891 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
5084 14:46:47.594827 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5085 14:46:47.598108 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5086 14:46:47.604841 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5087 14:46:47.608131 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5088 14:46:47.611324 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5089 14:46:47.618583 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5090 14:46:47.620886 0 15 28 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
5091 14:46:47.624825 1 0 0 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
5092 14:46:47.631208 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5093 14:46:47.634125 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5094 14:46:47.637738 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5095 14:46:47.643987 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5096 14:46:47.647944 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5097 14:46:47.650926 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5098 14:46:47.657356 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5099 14:46:47.661057 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5100 14:46:47.664161 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5101 14:46:47.670363 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5102 14:46:47.673987 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5103 14:46:47.676999 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5104 14:46:47.683838 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5105 14:46:47.686752 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5106 14:46:47.690513 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5107 14:46:47.696776 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5108 14:46:47.700102 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5109 14:46:47.703573 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5110 14:46:47.710607 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5111 14:46:47.713077 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5112 14:46:47.716599 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5113 14:46:47.723201 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5114 14:46:47.726727 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5115 14:46:47.733162 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5116 14:46:47.736776 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5117 14:46:47.739981 Total UI for P1: 0, mck2ui 16
5118 14:46:47.743018 best dqsien dly found for B0: ( 1, 2, 28)
5119 14:46:47.746846 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 14:46:47.750481 Total UI for P1: 0, mck2ui 16
5121 14:46:47.753186 best dqsien dly found for B1: ( 1, 3, 4)
5122 14:46:47.756501 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5123 14:46:47.759468 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5124 14:46:47.759550
5125 14:46:47.762964 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5126 14:46:47.769039 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5127 14:46:47.769121 [Gating] SW calibration Done
5128 14:46:47.769187 ==
5129 14:46:47.772878 Dram Type= 6, Freq= 0, CH_0, rank 0
5130 14:46:47.779120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5131 14:46:47.779234 ==
5132 14:46:47.779329 RX Vref Scan: 0
5133 14:46:47.779422
5134 14:46:47.782460 RX Vref 0 -> 0, step: 1
5135 14:46:47.782549
5136 14:46:47.785552 RX Delay -80 -> 252, step: 8
5137 14:46:47.789067 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5138 14:46:47.792516 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5139 14:46:47.795917 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5140 14:46:47.798894 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5141 14:46:47.805710 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5142 14:46:47.809120 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5143 14:46:47.812389 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5144 14:46:47.815641 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5145 14:46:47.818541 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5146 14:46:47.824927 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5147 14:46:47.828248 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5148 14:46:47.832188 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5149 14:46:47.835098 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5150 14:46:47.838317 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5151 14:46:47.845802 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5152 14:46:47.848515 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5153 14:46:47.848618 ==
5154 14:46:47.851611 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 14:46:47.855072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 14:46:47.855174 ==
5157 14:46:47.855272 DQS Delay:
5158 14:46:47.858332 DQS0 = 0, DQS1 = 0
5159 14:46:47.858403 DQM Delay:
5160 14:46:47.862811 DQM0 = 100, DQM1 = 89
5161 14:46:47.862894 DQ Delay:
5162 14:46:47.864848 DQ0 =103, DQ1 =103, DQ2 =95, DQ3 =95
5163 14:46:47.868358 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =107
5164 14:46:47.871361 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5165 14:46:47.874735 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =95
5166 14:46:47.874818
5167 14:46:47.874889
5168 14:46:47.874995 ==
5169 14:46:47.877719 Dram Type= 6, Freq= 0, CH_0, rank 0
5170 14:46:47.884980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5171 14:46:47.885124 ==
5172 14:46:47.885234
5173 14:46:47.885326
5174 14:46:47.885399 TX Vref Scan disable
5175 14:46:47.888436 == TX Byte 0 ==
5176 14:46:47.891951 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5177 14:46:47.898270 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5178 14:46:47.898362 == TX Byte 1 ==
5179 14:46:47.901702 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5180 14:46:47.908348 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5181 14:46:47.908464 ==
5182 14:46:47.911612 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 14:46:47.914485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 14:46:47.914568 ==
5185 14:46:47.914629
5186 14:46:47.914686
5187 14:46:47.917907 TX Vref Scan disable
5188 14:46:47.921006 == TX Byte 0 ==
5189 14:46:47.924243 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5190 14:46:47.927900 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5191 14:46:47.931560 == TX Byte 1 ==
5192 14:46:47.934322 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5193 14:46:47.937399 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5194 14:46:47.937472
5195 14:46:47.937533 [DATLAT]
5196 14:46:47.941153 Freq=933, CH0 RK0
5197 14:46:47.941289
5198 14:46:47.944045 DATLAT Default: 0xd
5199 14:46:47.944125 0, 0xFFFF, sum = 0
5200 14:46:47.947820 1, 0xFFFF, sum = 0
5201 14:46:47.947895 2, 0xFFFF, sum = 0
5202 14:46:47.951148 3, 0xFFFF, sum = 0
5203 14:46:47.951229 4, 0xFFFF, sum = 0
5204 14:46:47.953906 5, 0xFFFF, sum = 0
5205 14:46:47.953978 6, 0xFFFF, sum = 0
5206 14:46:47.957089 7, 0xFFFF, sum = 0
5207 14:46:47.957162 8, 0xFFFF, sum = 0
5208 14:46:47.961204 9, 0xFFFF, sum = 0
5209 14:46:47.961308 10, 0x0, sum = 1
5210 14:46:47.963777 11, 0x0, sum = 2
5211 14:46:47.963901 12, 0x0, sum = 3
5212 14:46:47.967028 13, 0x0, sum = 4
5213 14:46:47.967144 best_step = 11
5214 14:46:47.967207
5215 14:46:47.967266 ==
5216 14:46:47.970758 Dram Type= 6, Freq= 0, CH_0, rank 0
5217 14:46:47.973658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5218 14:46:47.977158 ==
5219 14:46:47.977283 RX Vref Scan: 1
5220 14:46:47.977395
5221 14:46:47.980079 RX Vref 0 -> 0, step: 1
5222 14:46:47.980182
5223 14:46:47.983999 RX Delay -61 -> 252, step: 4
5224 14:46:47.984084
5225 14:46:47.987123 Set Vref, RX VrefLevel [Byte0]: 57
5226 14:46:47.990129 [Byte1]: 58
5227 14:46:47.990212
5228 14:46:47.993808 Final RX Vref Byte 0 = 57 to rank0
5229 14:46:47.996847 Final RX Vref Byte 1 = 58 to rank0
5230 14:46:48.001020 Final RX Vref Byte 0 = 57 to rank1
5231 14:46:48.003314 Final RX Vref Byte 1 = 58 to rank1==
5232 14:46:48.006577 Dram Type= 6, Freq= 0, CH_0, rank 0
5233 14:46:48.009802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5234 14:46:48.009875 ==
5235 14:46:48.013573 DQS Delay:
5236 14:46:48.013655 DQS0 = 0, DQS1 = 0
5237 14:46:48.013746 DQM Delay:
5238 14:46:48.016686 DQM0 = 98, DQM1 = 87
5239 14:46:48.016761 DQ Delay:
5240 14:46:48.019807 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5241 14:46:48.023446 DQ4 =100, DQ5 =90, DQ6 =110, DQ7 =104
5242 14:46:48.026148 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =82
5243 14:46:48.029732 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =94
5244 14:46:48.029811
5245 14:46:48.029872
5246 14:46:48.039713 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e18, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 412 ps
5247 14:46:48.042763 CH0 RK0: MR19=505, MR18=1E18
5248 14:46:48.049405 CH0_RK0: MR19=0x505, MR18=0x1E18, DQSOSC=412, MR23=63, INC=63, DEC=42
5249 14:46:48.049535
5250 14:46:48.052490 ----->DramcWriteLeveling(PI) begin...
5251 14:46:48.052567 ==
5252 14:46:48.056501 Dram Type= 6, Freq= 0, CH_0, rank 1
5253 14:46:48.059971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 14:46:48.060048 ==
5255 14:46:48.062656 Write leveling (Byte 0): 30 => 30
5256 14:46:48.065520 Write leveling (Byte 1): 28 => 28
5257 14:46:48.069067 DramcWriteLeveling(PI) end<-----
5258 14:46:48.069174
5259 14:46:48.069283 ==
5260 14:46:48.071999 Dram Type= 6, Freq= 0, CH_0, rank 1
5261 14:46:48.075551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 14:46:48.075626 ==
5263 14:46:48.078654 [Gating] SW mode calibration
5264 14:46:48.085378 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5265 14:46:48.091981 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5266 14:46:48.095107 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
5267 14:46:48.102248 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5268 14:46:48.104863 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5269 14:46:48.108331 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5270 14:46:48.115214 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5271 14:46:48.118400 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5272 14:46:48.121445 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5273 14:46:48.128459 0 14 28 | B1->B0 | 3333 2e2e | 0 0 | (0 0) (0 0)
5274 14:46:48.131482 0 15 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
5275 14:46:48.135326 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5276 14:46:48.141890 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5277 14:46:48.145330 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5278 14:46:48.147907 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5279 14:46:48.154492 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5280 14:46:48.158218 0 15 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5281 14:46:48.162557 0 15 28 | B1->B0 | 2a2a 3a3a | 0 1 | (0 0) (0 0)
5282 14:46:48.168036 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5283 14:46:48.171092 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5284 14:46:48.174668 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5285 14:46:48.181553 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5286 14:46:48.184137 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5287 14:46:48.188561 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5288 14:46:48.194050 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5289 14:46:48.197229 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5290 14:46:48.200482 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5291 14:46:48.207904 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5292 14:46:48.210578 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5293 14:46:48.213984 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5294 14:46:48.220851 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5295 14:46:48.224199 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5296 14:46:48.227147 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5297 14:46:48.234226 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5298 14:46:48.236860 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5299 14:46:48.240575 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5300 14:46:48.246698 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5301 14:46:48.250203 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5302 14:46:48.253251 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5303 14:46:48.259845 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5304 14:46:48.262987 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5305 14:46:48.267136 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5306 14:46:48.273178 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5307 14:46:48.273325 Total UI for P1: 0, mck2ui 16
5308 14:46:48.279829 best dqsien dly found for B0: ( 1, 2, 26)
5309 14:46:48.279919 Total UI for P1: 0, mck2ui 16
5310 14:46:48.285956 best dqsien dly found for B1: ( 1, 2, 30)
5311 14:46:48.289464 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5312 14:46:48.292587 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5313 14:46:48.292679
5314 14:46:48.296324 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5315 14:46:48.299584 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5316 14:46:48.302701 [Gating] SW calibration Done
5317 14:46:48.302813 ==
5318 14:46:48.305640 Dram Type= 6, Freq= 0, CH_0, rank 1
5319 14:46:48.308980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5320 14:46:48.309081 ==
5321 14:46:48.312377 RX Vref Scan: 0
5322 14:46:48.312457
5323 14:46:48.312517 RX Vref 0 -> 0, step: 1
5324 14:46:48.312580
5325 14:46:48.316392 RX Delay -80 -> 252, step: 8
5326 14:46:48.322465 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5327 14:46:48.325467 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5328 14:46:48.328968 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5329 14:46:48.332382 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5330 14:46:48.336110 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5331 14:46:48.339403 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5332 14:46:48.342220 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5333 14:46:48.348477 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5334 14:46:48.352259 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5335 14:46:48.355397 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5336 14:46:48.358793 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5337 14:46:48.362165 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5338 14:46:48.368813 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5339 14:46:48.371604 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5340 14:46:48.375129 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5341 14:46:48.378849 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5342 14:46:48.378928 ==
5343 14:46:48.381399 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 14:46:48.385298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 14:46:48.388433 ==
5346 14:46:48.388519 DQS Delay:
5347 14:46:48.388602 DQS0 = 0, DQS1 = 0
5348 14:46:48.391514 DQM Delay:
5349 14:46:48.391597 DQM0 = 97, DQM1 = 91
5350 14:46:48.394850 DQ Delay:
5351 14:46:48.394933 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5352 14:46:48.398622 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5353 14:46:48.401225 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5354 14:46:48.408088 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5355 14:46:48.408176
5356 14:46:48.408260
5357 14:46:48.408338 ==
5358 14:46:48.411273 Dram Type= 6, Freq= 0, CH_0, rank 1
5359 14:46:48.414896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5360 14:46:48.414982 ==
5361 14:46:48.415067
5362 14:46:48.415145
5363 14:46:48.417989 TX Vref Scan disable
5364 14:46:48.418072 == TX Byte 0 ==
5365 14:46:48.424507 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5366 14:46:48.427936 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5367 14:46:48.428028 == TX Byte 1 ==
5368 14:46:48.434478 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5369 14:46:48.437740 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5370 14:46:48.437825 ==
5371 14:46:48.441379 Dram Type= 6, Freq= 0, CH_0, rank 1
5372 14:46:48.444192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5373 14:46:48.444291 ==
5374 14:46:48.444352
5375 14:46:48.447670
5376 14:46:48.447754 TX Vref Scan disable
5377 14:46:48.451075 == TX Byte 0 ==
5378 14:46:48.455190 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5379 14:46:48.457320 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5380 14:46:48.461066 == TX Byte 1 ==
5381 14:46:48.464526 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5382 14:46:48.470591 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5383 14:46:48.470706
5384 14:46:48.470806 [DATLAT]
5385 14:46:48.470892 Freq=933, CH0 RK1
5386 14:46:48.470984
5387 14:46:48.474637 DATLAT Default: 0xb
5388 14:46:48.474735 0, 0xFFFF, sum = 0
5389 14:46:48.477421 1, 0xFFFF, sum = 0
5390 14:46:48.477530 2, 0xFFFF, sum = 0
5391 14:46:48.480201 3, 0xFFFF, sum = 0
5392 14:46:48.483522 4, 0xFFFF, sum = 0
5393 14:46:48.483625 5, 0xFFFF, sum = 0
5394 14:46:48.487549 6, 0xFFFF, sum = 0
5395 14:46:48.487662 7, 0xFFFF, sum = 0
5396 14:46:48.490655 8, 0xFFFF, sum = 0
5397 14:46:48.490752 9, 0xFFFF, sum = 0
5398 14:46:48.493784 10, 0x0, sum = 1
5399 14:46:48.493864 11, 0x0, sum = 2
5400 14:46:48.497962 12, 0x0, sum = 3
5401 14:46:48.498041 13, 0x0, sum = 4
5402 14:46:48.498105 best_step = 11
5403 14:46:48.498171
5404 14:46:48.500902 ==
5405 14:46:48.504091 Dram Type= 6, Freq= 0, CH_0, rank 1
5406 14:46:48.507036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5407 14:46:48.507110 ==
5408 14:46:48.507180 RX Vref Scan: 0
5409 14:46:48.507238
5410 14:46:48.510298 RX Vref 0 -> 0, step: 1
5411 14:46:48.510381
5412 14:46:48.513601 RX Delay -53 -> 252, step: 4
5413 14:46:48.520778 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5414 14:46:48.523135 iDelay=199, Bit 1, Center 100 (11 ~ 190) 180
5415 14:46:48.526566 iDelay=199, Bit 2, Center 92 (3 ~ 182) 180
5416 14:46:48.529695 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5417 14:46:48.533753 iDelay=199, Bit 4, Center 100 (11 ~ 190) 180
5418 14:46:48.536628 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5419 14:46:48.542866 iDelay=199, Bit 6, Center 108 (19 ~ 198) 180
5420 14:46:48.546417 iDelay=199, Bit 7, Center 104 (15 ~ 194) 180
5421 14:46:48.549678 iDelay=199, Bit 8, Center 80 (-5 ~ 166) 172
5422 14:46:48.552650 iDelay=199, Bit 9, Center 76 (-9 ~ 162) 172
5423 14:46:48.556522 iDelay=199, Bit 10, Center 92 (3 ~ 182) 180
5424 14:46:48.562518 iDelay=199, Bit 11, Center 82 (-5 ~ 170) 176
5425 14:46:48.565802 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5426 14:46:48.569117 iDelay=199, Bit 13, Center 94 (3 ~ 186) 184
5427 14:46:48.572631 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5428 14:46:48.575750 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5429 14:46:48.575859 ==
5430 14:46:48.579103 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 14:46:48.585602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 14:46:48.585696 ==
5433 14:46:48.585760 DQS Delay:
5434 14:46:48.589267 DQS0 = 0, DQS1 = 0
5435 14:46:48.589363 DQM Delay:
5436 14:46:48.592339 DQM0 = 97, DQM1 = 89
5437 14:46:48.592419 DQ Delay:
5438 14:46:48.595874 DQ0 =96, DQ1 =100, DQ2 =92, DQ3 =94
5439 14:46:48.599274 DQ4 =100, DQ5 =86, DQ6 =108, DQ7 =104
5440 14:46:48.602303 DQ8 =80, DQ9 =76, DQ10 =92, DQ11 =82
5441 14:46:48.605436 DQ12 =94, DQ13 =94, DQ14 =100, DQ15 =94
5442 14:46:48.605539
5443 14:46:48.605646
5444 14:46:48.612576 [DQSOSCAuto] RK1, (LSB)MR18= 0x1613, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 414 ps
5445 14:46:48.615562 CH0 RK1: MR19=505, MR18=1613
5446 14:46:48.621792 CH0_RK1: MR19=0x505, MR18=0x1613, DQSOSC=414, MR23=63, INC=63, DEC=42
5447 14:46:48.625122 [RxdqsGatingPostProcess] freq 933
5448 14:46:48.631897 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5449 14:46:48.634993 best DQS0 dly(2T, 0.5T) = (0, 10)
5450 14:46:48.638728 best DQS1 dly(2T, 0.5T) = (0, 11)
5451 14:46:48.638807 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5452 14:46:48.641929 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5453 14:46:48.645495 best DQS0 dly(2T, 0.5T) = (0, 10)
5454 14:46:48.648167 best DQS1 dly(2T, 0.5T) = (0, 10)
5455 14:46:48.651892 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5456 14:46:48.654913 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5457 14:46:48.657954 Pre-setting of DQS Precalculation
5458 14:46:48.664765 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5459 14:46:48.664843 ==
5460 14:46:48.668790 Dram Type= 6, Freq= 0, CH_1, rank 0
5461 14:46:48.671855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 14:46:48.671932 ==
5463 14:46:48.678007 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5464 14:46:48.684615 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5465 14:46:48.687686 [CA 0] Center 36 (6~67) winsize 62
5466 14:46:48.690946 [CA 1] Center 36 (6~67) winsize 62
5467 14:46:48.694049 [CA 2] Center 34 (4~64) winsize 61
5468 14:46:48.698081 [CA 3] Center 33 (3~64) winsize 62
5469 14:46:48.700617 [CA 4] Center 34 (4~64) winsize 61
5470 14:46:48.704347 [CA 5] Center 33 (3~64) winsize 62
5471 14:46:48.704424
5472 14:46:48.707290 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5473 14:46:48.707370
5474 14:46:48.711344 [CATrainingPosCal] consider 1 rank data
5475 14:46:48.714073 u2DelayCellTimex100 = 270/100 ps
5476 14:46:48.717278 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5477 14:46:48.720577 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5478 14:46:48.724040 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5479 14:46:48.727169 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5480 14:46:48.730791 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5481 14:46:48.733928 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5482 14:46:48.734021
5483 14:46:48.740412 CA PerBit enable=1, Macro0, CA PI delay=33
5484 14:46:48.740519
5485 14:46:48.743483 [CBTSetCACLKResult] CA Dly = 33
5486 14:46:48.743561 CS Dly: 5 (0~36)
5487 14:46:48.743623 ==
5488 14:46:48.747362 Dram Type= 6, Freq= 0, CH_1, rank 1
5489 14:46:48.750374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 14:46:48.750452 ==
5491 14:46:48.756599 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5492 14:46:48.763831 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5493 14:46:48.766999 [CA 0] Center 36 (6~67) winsize 62
5494 14:46:48.770285 [CA 1] Center 36 (6~67) winsize 62
5495 14:46:48.773776 [CA 2] Center 34 (4~65) winsize 62
5496 14:46:48.776967 [CA 3] Center 33 (3~64) winsize 62
5497 14:46:48.780266 [CA 4] Center 33 (3~64) winsize 62
5498 14:46:48.783260 [CA 5] Center 33 (3~63) winsize 61
5499 14:46:48.783345
5500 14:46:48.787133 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5501 14:46:48.787232
5502 14:46:48.790144 [CATrainingPosCal] consider 2 rank data
5503 14:46:48.793449 u2DelayCellTimex100 = 270/100 ps
5504 14:46:48.796667 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5505 14:46:48.800068 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5506 14:46:48.803130 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5507 14:46:48.809415 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5508 14:46:48.812617 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5509 14:46:48.816364 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5510 14:46:48.816445
5511 14:46:48.819213 CA PerBit enable=1, Macro0, CA PI delay=33
5512 14:46:48.819304
5513 14:46:48.822512 [CBTSetCACLKResult] CA Dly = 33
5514 14:46:48.822600 CS Dly: 6 (0~38)
5515 14:46:48.822663
5516 14:46:48.826242 ----->DramcWriteLeveling(PI) begin...
5517 14:46:48.826345 ==
5518 14:46:48.829607 Dram Type= 6, Freq= 0, CH_1, rank 0
5519 14:46:48.835779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 14:46:48.835858 ==
5521 14:46:48.839055 Write leveling (Byte 0): 28 => 28
5522 14:46:48.842479 Write leveling (Byte 1): 30 => 30
5523 14:46:48.846013 DramcWriteLeveling(PI) end<-----
5524 14:46:48.846090
5525 14:46:48.846159 ==
5526 14:46:48.849081 Dram Type= 6, Freq= 0, CH_1, rank 0
5527 14:46:48.852336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5528 14:46:48.852441 ==
5529 14:46:48.855727 [Gating] SW mode calibration
5530 14:46:48.862346 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5531 14:46:48.868690 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5532 14:46:48.872655 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5533 14:46:48.875322 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5534 14:46:48.882613 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5535 14:46:48.885521 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5536 14:46:48.888424 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5537 14:46:48.894926 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5538 14:46:48.898384 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5539 14:46:48.901547 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (1 0) (1 0)
5540 14:46:48.908660 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5541 14:46:48.911968 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5542 14:46:48.915450 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5543 14:46:48.921478 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5544 14:46:48.924989 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5545 14:46:48.927752 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5546 14:46:48.934515 0 15 24 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
5547 14:46:48.938106 0 15 28 | B1->B0 | 3a3a 4141 | 0 0 | (0 0) (0 0)
5548 14:46:48.941794 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5549 14:46:48.947785 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5550 14:46:48.950648 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5551 14:46:48.954917 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5552 14:46:48.961714 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5553 14:46:48.964276 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5554 14:46:48.967721 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5555 14:46:48.974417 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5556 14:46:48.977401 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5557 14:46:48.980912 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5558 14:46:48.987009 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5559 14:46:48.991217 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5560 14:46:48.993923 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5561 14:46:49.000338 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5562 14:46:49.003672 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5563 14:46:49.006947 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 14:46:49.013727 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 14:46:49.016793 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 14:46:49.020169 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 14:46:49.026675 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 14:46:49.030489 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 14:46:49.033137 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 14:46:49.039647 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5571 14:46:49.042907 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5572 14:46:49.046696 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5573 14:46:49.049468 Total UI for P1: 0, mck2ui 16
5574 14:46:49.052805 best dqsien dly found for B0: ( 1, 2, 28)
5575 14:46:49.059840 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 14:46:49.059933 Total UI for P1: 0, mck2ui 16
5577 14:46:49.065779 best dqsien dly found for B1: ( 1, 3, 0)
5578 14:46:49.069141 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5579 14:46:49.072471 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5580 14:46:49.072574
5581 14:46:49.075857 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5582 14:46:49.079558 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5583 14:46:49.082652 [Gating] SW calibration Done
5584 14:46:49.082792 ==
5585 14:46:49.086015 Dram Type= 6, Freq= 0, CH_1, rank 0
5586 14:46:49.089330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5587 14:46:49.089416 ==
5588 14:46:49.092520 RX Vref Scan: 0
5589 14:46:49.092636
5590 14:46:49.092719 RX Vref 0 -> 0, step: 1
5591 14:46:49.092798
5592 14:46:49.095994 RX Delay -80 -> 252, step: 8
5593 14:46:49.102373 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5594 14:46:49.105436 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5595 14:46:49.109455 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5596 14:46:49.112284 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5597 14:46:49.115389 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5598 14:46:49.118775 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5599 14:46:49.125212 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5600 14:46:49.129075 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5601 14:46:49.131932 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5602 14:46:49.135240 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5603 14:46:49.138419 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5604 14:46:49.141684 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5605 14:46:49.148202 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5606 14:46:49.151894 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5607 14:46:49.154555 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5608 14:46:49.158373 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5609 14:46:49.158459 ==
5610 14:46:49.161441 Dram Type= 6, Freq= 0, CH_1, rank 0
5611 14:46:49.168501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5612 14:46:49.168587 ==
5613 14:46:49.168672 DQS Delay:
5614 14:46:49.171432 DQS0 = 0, DQS1 = 0
5615 14:46:49.171516 DQM Delay:
5616 14:46:49.171602 DQM0 = 100, DQM1 = 95
5617 14:46:49.174565 DQ Delay:
5618 14:46:49.178228 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5619 14:46:49.181039 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5620 14:46:49.184300 DQ8 =83, DQ9 =87, DQ10 =91, DQ11 =87
5621 14:46:49.188055 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5622 14:46:49.188140
5623 14:46:49.188224
5624 14:46:49.188303 ==
5625 14:46:49.190757 Dram Type= 6, Freq= 0, CH_1, rank 0
5626 14:46:49.194552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5627 14:46:49.194637 ==
5628 14:46:49.194721
5629 14:46:49.197558
5630 14:46:49.197640 TX Vref Scan disable
5631 14:46:49.201174 == TX Byte 0 ==
5632 14:46:49.204662 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5633 14:46:49.207783 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5634 14:46:49.210868 == TX Byte 1 ==
5635 14:46:49.213924 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5636 14:46:49.217527 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5637 14:46:49.217653 ==
5638 14:46:49.220611 Dram Type= 6, Freq= 0, CH_1, rank 0
5639 14:46:49.227499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5640 14:46:49.227606 ==
5641 14:46:49.227697
5642 14:46:49.227786
5643 14:46:49.230392 TX Vref Scan disable
5644 14:46:49.230491 == TX Byte 0 ==
5645 14:46:49.237037 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5646 14:46:49.240586 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5647 14:46:49.240689 == TX Byte 1 ==
5648 14:46:49.246790 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5649 14:46:49.250111 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5650 14:46:49.250212
5651 14:46:49.250302 [DATLAT]
5652 14:46:49.253205 Freq=933, CH1 RK0
5653 14:46:49.253318
5654 14:46:49.253380 DATLAT Default: 0xd
5655 14:46:49.256968 0, 0xFFFF, sum = 0
5656 14:46:49.257074 1, 0xFFFF, sum = 0
5657 14:46:49.259954 2, 0xFFFF, sum = 0
5658 14:46:49.260055 3, 0xFFFF, sum = 0
5659 14:46:49.263170 4, 0xFFFF, sum = 0
5660 14:46:49.263271 5, 0xFFFF, sum = 0
5661 14:46:49.266933 6, 0xFFFF, sum = 0
5662 14:46:49.270216 7, 0xFFFF, sum = 0
5663 14:46:49.270317 8, 0xFFFF, sum = 0
5664 14:46:49.273165 9, 0xFFFF, sum = 0
5665 14:46:49.273272 10, 0x0, sum = 1
5666 14:46:49.276350 11, 0x0, sum = 2
5667 14:46:49.276439 12, 0x0, sum = 3
5668 14:46:49.276519 13, 0x0, sum = 4
5669 14:46:49.279619 best_step = 11
5670 14:46:49.279702
5671 14:46:49.279786 ==
5672 14:46:49.283582 Dram Type= 6, Freq= 0, CH_1, rank 0
5673 14:46:49.286441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5674 14:46:49.286527 ==
5675 14:46:49.290285 RX Vref Scan: 1
5676 14:46:49.290368
5677 14:46:49.293091 RX Vref 0 -> 0, step: 1
5678 14:46:49.293175
5679 14:46:49.293300 RX Delay -53 -> 252, step: 4
5680 14:46:49.293395
5681 14:46:49.296821 Set Vref, RX VrefLevel [Byte0]: 51
5682 14:46:49.299605 [Byte1]: 54
5683 14:46:49.304113
5684 14:46:49.304196 Final RX Vref Byte 0 = 51 to rank0
5685 14:46:49.307584 Final RX Vref Byte 1 = 54 to rank0
5686 14:46:49.311075 Final RX Vref Byte 0 = 51 to rank1
5687 14:46:49.314125 Final RX Vref Byte 1 = 54 to rank1==
5688 14:46:49.317197 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 14:46:49.324177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 14:46:49.324289 ==
5691 14:46:49.324390 DQS Delay:
5692 14:46:49.326910 DQS0 = 0, DQS1 = 0
5693 14:46:49.327006 DQM Delay:
5694 14:46:49.327097 DQM0 = 99, DQM1 = 94
5695 14:46:49.330454 DQ Delay:
5696 14:46:49.333684 DQ0 =104, DQ1 =94, DQ2 =88, DQ3 =100
5697 14:46:49.337332 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5698 14:46:49.340934 DQ8 =82, DQ9 =84, DQ10 =92, DQ11 =88
5699 14:46:49.343585 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =104
5700 14:46:49.343683
5701 14:46:49.343778
5702 14:46:49.350236 [DQSOSCAuto] RK0, (LSB)MR18= 0xa19, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 418 ps
5703 14:46:49.353817 CH1 RK0: MR19=505, MR18=A19
5704 14:46:49.360563 CH1_RK0: MR19=0x505, MR18=0xA19, DQSOSC=413, MR23=63, INC=63, DEC=42
5705 14:46:49.360665
5706 14:46:49.363239 ----->DramcWriteLeveling(PI) begin...
5707 14:46:49.363337 ==
5708 14:46:49.366863 Dram Type= 6, Freq= 0, CH_1, rank 1
5709 14:46:49.370182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 14:46:49.370253 ==
5711 14:46:49.373515 Write leveling (Byte 0): 25 => 25
5712 14:46:49.377107 Write leveling (Byte 1): 26 => 26
5713 14:46:49.379783 DramcWriteLeveling(PI) end<-----
5714 14:46:49.379882
5715 14:46:49.379978 ==
5716 14:46:49.383141 Dram Type= 6, Freq= 0, CH_1, rank 1
5717 14:46:49.389612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5718 14:46:49.389698 ==
5719 14:46:49.389782 [Gating] SW mode calibration
5720 14:46:49.399424 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5721 14:46:49.403352 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5722 14:46:49.409815 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5723 14:46:49.412825 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5724 14:46:49.416015 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5725 14:46:49.422847 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5726 14:46:49.426098 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5727 14:46:49.429404 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5728 14:46:49.436072 0 14 24 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 1)
5729 14:46:49.439344 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
5730 14:46:49.442644 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5731 14:46:49.448921 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5732 14:46:49.452149 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5733 14:46:49.455493 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5734 14:46:49.458830 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5735 14:46:49.465901 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5736 14:46:49.468730 0 15 24 | B1->B0 | 2424 3535 | 1 0 | (0 0) (1 1)
5737 14:46:49.472268 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
5738 14:46:49.479233 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5739 14:46:49.482538 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5740 14:46:49.485217 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5741 14:46:49.492858 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5742 14:46:49.495228 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5743 14:46:49.501873 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5744 14:46:49.505030 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5745 14:46:49.508857 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5746 14:46:49.511765 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5747 14:46:49.518344 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5748 14:46:49.521975 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5749 14:46:49.525295 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5750 14:46:49.531493 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5751 14:46:49.535306 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5752 14:46:49.538781 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5753 14:46:49.544730 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5754 14:46:49.548338 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5755 14:46:49.551501 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5756 14:46:49.557918 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5757 14:46:49.561372 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5758 14:46:49.564329 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5759 14:46:49.571574 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5760 14:46:49.574182 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5761 14:46:49.577628 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5762 14:46:49.584859 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 14:46:49.588168 Total UI for P1: 0, mck2ui 16
5764 14:46:49.590967 best dqsien dly found for B0: ( 1, 2, 26)
5765 14:46:49.594241 Total UI for P1: 0, mck2ui 16
5766 14:46:49.597655 best dqsien dly found for B1: ( 1, 2, 28)
5767 14:46:49.601230 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5768 14:46:49.604646 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5769 14:46:49.604729
5770 14:46:49.607390 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5771 14:46:49.610849 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5772 14:46:49.614085 [Gating] SW calibration Done
5773 14:46:49.614163 ==
5774 14:46:49.617106 Dram Type= 6, Freq= 0, CH_1, rank 1
5775 14:46:49.620484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 14:46:49.620568 ==
5777 14:46:49.623975 RX Vref Scan: 0
5778 14:46:49.624048
5779 14:46:49.626896 RX Vref 0 -> 0, step: 1
5780 14:46:49.626979
5781 14:46:49.627043 RX Delay -80 -> 252, step: 8
5782 14:46:49.633751 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5783 14:46:49.637269 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5784 14:46:49.640681 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5785 14:46:49.643873 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5786 14:46:49.647050 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5787 14:46:49.653818 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5788 14:46:49.657651 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5789 14:46:49.659970 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5790 14:46:49.663305 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5791 14:46:49.667003 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5792 14:46:49.669927 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5793 14:46:49.676492 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5794 14:46:49.680330 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5795 14:46:49.683565 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5796 14:46:49.687008 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5797 14:46:49.690517 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5798 14:46:49.690612 ==
5799 14:46:49.692960 Dram Type= 6, Freq= 0, CH_1, rank 1
5800 14:46:49.699909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5801 14:46:49.700042 ==
5802 14:46:49.700134 DQS Delay:
5803 14:46:49.703212 DQS0 = 0, DQS1 = 0
5804 14:46:49.703367 DQM Delay:
5805 14:46:49.706302 DQM0 = 97, DQM1 = 94
5806 14:46:49.706423 DQ Delay:
5807 14:46:49.709367 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5808 14:46:49.713049 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5809 14:46:49.716166 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5810 14:46:49.719519 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5811 14:46:49.719621
5812 14:46:49.719688
5813 14:46:49.719749 ==
5814 14:46:49.722534 Dram Type= 6, Freq= 0, CH_1, rank 1
5815 14:46:49.726786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5816 14:46:49.726886 ==
5817 14:46:49.726981
5818 14:46:49.729864
5819 14:46:49.729946 TX Vref Scan disable
5820 14:46:49.732641 == TX Byte 0 ==
5821 14:46:49.735859 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5822 14:46:49.739119 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5823 14:46:49.744315 == TX Byte 1 ==
5824 14:46:49.745848 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5825 14:46:49.749366 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5826 14:46:49.749451 ==
5827 14:46:49.752328 Dram Type= 6, Freq= 0, CH_1, rank 1
5828 14:46:49.759517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 14:46:49.759603 ==
5830 14:46:49.759669
5831 14:46:49.759729
5832 14:46:49.759788 TX Vref Scan disable
5833 14:46:49.763471 == TX Byte 0 ==
5834 14:46:49.766400 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5835 14:46:49.773051 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5836 14:46:49.773138 == TX Byte 1 ==
5837 14:46:49.776397 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5838 14:46:49.783114 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5839 14:46:49.783203
5840 14:46:49.783270 [DATLAT]
5841 14:46:49.783330 Freq=933, CH1 RK1
5842 14:46:49.783388
5843 14:46:49.786438 DATLAT Default: 0xb
5844 14:46:49.786523 0, 0xFFFF, sum = 0
5845 14:46:49.789748 1, 0xFFFF, sum = 0
5846 14:46:49.793127 2, 0xFFFF, sum = 0
5847 14:46:49.793227 3, 0xFFFF, sum = 0
5848 14:46:49.796181 4, 0xFFFF, sum = 0
5849 14:46:49.796266 5, 0xFFFF, sum = 0
5850 14:46:49.799541 6, 0xFFFF, sum = 0
5851 14:46:49.799626 7, 0xFFFF, sum = 0
5852 14:46:49.802918 8, 0xFFFF, sum = 0
5853 14:46:49.803003 9, 0xFFFF, sum = 0
5854 14:46:49.806133 10, 0x0, sum = 1
5855 14:46:49.806218 11, 0x0, sum = 2
5856 14:46:49.809608 12, 0x0, sum = 3
5857 14:46:49.809692 13, 0x0, sum = 4
5858 14:46:49.809758 best_step = 11
5859 14:46:49.812443
5860 14:46:49.812525 ==
5861 14:46:49.816074 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 14:46:49.820012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 14:46:49.820097 ==
5864 14:46:49.820163 RX Vref Scan: 0
5865 14:46:49.820223
5866 14:46:49.822403 RX Vref 0 -> 0, step: 1
5867 14:46:49.822486
5868 14:46:49.826080 RX Delay -53 -> 252, step: 4
5869 14:46:49.832648 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5870 14:46:49.835650 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5871 14:46:49.839012 iDelay=199, Bit 2, Center 88 (-1 ~ 178) 180
5872 14:46:49.842024 iDelay=199, Bit 3, Center 96 (3 ~ 190) 188
5873 14:46:49.845795 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5874 14:46:49.848609 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5875 14:46:49.855475 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5876 14:46:49.858674 iDelay=199, Bit 7, Center 96 (3 ~ 190) 188
5877 14:46:49.861797 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5878 14:46:49.865254 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5879 14:46:49.868862 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5880 14:46:49.875268 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5881 14:46:49.878249 iDelay=199, Bit 12, Center 102 (11 ~ 194) 184
5882 14:46:49.882651 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5883 14:46:49.885626 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5884 14:46:49.888884 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5885 14:46:49.891703 ==
5886 14:46:49.894952 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 14:46:49.898456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 14:46:49.898541 ==
5889 14:46:49.898605 DQS Delay:
5890 14:46:49.901620 DQS0 = 0, DQS1 = 0
5891 14:46:49.901701 DQM Delay:
5892 14:46:49.905617 DQM0 = 98, DQM1 = 93
5893 14:46:49.905689 DQ Delay:
5894 14:46:49.908203 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =96
5895 14:46:49.911528 DQ4 =96, DQ5 =106, DQ6 =106, DQ7 =96
5896 14:46:49.915126 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =86
5897 14:46:49.918127 DQ12 =102, DQ13 =100, DQ14 =98, DQ15 =102
5898 14:46:49.918215
5899 14:46:49.918292
5900 14:46:49.927562 [DQSOSCAuto] RK1, (LSB)MR18= 0xb22, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5901 14:46:49.927652 CH1 RK1: MR19=505, MR18=B22
5902 14:46:49.934992 CH1_RK1: MR19=0x505, MR18=0xB22, DQSOSC=411, MR23=63, INC=64, DEC=42
5903 14:46:49.937443 [RxdqsGatingPostProcess] freq 933
5904 14:46:49.944771 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5905 14:46:49.947426 best DQS0 dly(2T, 0.5T) = (0, 10)
5906 14:46:49.951073 best DQS1 dly(2T, 0.5T) = (0, 11)
5907 14:46:49.954487 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5908 14:46:49.957299 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5909 14:46:49.957396 best DQS0 dly(2T, 0.5T) = (0, 10)
5910 14:46:49.960567 best DQS1 dly(2T, 0.5T) = (0, 10)
5911 14:46:49.964403 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5912 14:46:49.967215 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5913 14:46:49.970685 Pre-setting of DQS Precalculation
5914 14:46:49.977003 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5915 14:46:49.983845 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5916 14:46:49.990401 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5917 14:46:49.990513
5918 14:46:49.990578
5919 14:46:49.993684 [Calibration Summary] 1866 Mbps
5920 14:46:49.996822 CH 0, Rank 0
5921 14:46:49.996910 SW Impedance : PASS
5922 14:46:50.000305 DUTY Scan : NO K
5923 14:46:50.003497 ZQ Calibration : PASS
5924 14:46:50.003596 Jitter Meter : NO K
5925 14:46:50.007264 CBT Training : PASS
5926 14:46:50.007345 Write leveling : PASS
5927 14:46:50.010302 RX DQS gating : PASS
5928 14:46:50.013528 RX DQ/DQS(RDDQC) : PASS
5929 14:46:50.013610 TX DQ/DQS : PASS
5930 14:46:50.016692 RX DATLAT : PASS
5931 14:46:50.021002 RX DQ/DQS(Engine): PASS
5932 14:46:50.021087 TX OE : NO K
5933 14:46:50.023091 All Pass.
5934 14:46:50.023173
5935 14:46:50.023236 CH 0, Rank 1
5936 14:46:50.026746 SW Impedance : PASS
5937 14:46:50.026828 DUTY Scan : NO K
5938 14:46:50.029932 ZQ Calibration : PASS
5939 14:46:50.033210 Jitter Meter : NO K
5940 14:46:50.033313 CBT Training : PASS
5941 14:46:50.037513 Write leveling : PASS
5942 14:46:50.039793 RX DQS gating : PASS
5943 14:46:50.039873 RX DQ/DQS(RDDQC) : PASS
5944 14:46:50.043513 TX DQ/DQS : PASS
5945 14:46:50.046687 RX DATLAT : PASS
5946 14:46:50.046768 RX DQ/DQS(Engine): PASS
5947 14:46:50.050052 TX OE : NO K
5948 14:46:50.050133 All Pass.
5949 14:46:50.050196
5950 14:46:50.052869 CH 1, Rank 0
5951 14:46:50.052949 SW Impedance : PASS
5952 14:46:50.057081 DUTY Scan : NO K
5953 14:46:50.059661 ZQ Calibration : PASS
5954 14:46:50.059742 Jitter Meter : NO K
5955 14:46:50.063069 CBT Training : PASS
5956 14:46:50.066952 Write leveling : PASS
5957 14:46:50.067042 RX DQS gating : PASS
5958 14:46:50.069319 RX DQ/DQS(RDDQC) : PASS
5959 14:46:50.072665 TX DQ/DQS : PASS
5960 14:46:50.072773 RX DATLAT : PASS
5961 14:46:50.075985 RX DQ/DQS(Engine): PASS
5962 14:46:50.076065 TX OE : NO K
5963 14:46:50.079112 All Pass.
5964 14:46:50.079192
5965 14:46:50.079255 CH 1, Rank 1
5966 14:46:50.082957 SW Impedance : PASS
5967 14:46:50.083039 DUTY Scan : NO K
5968 14:46:50.086033 ZQ Calibration : PASS
5969 14:46:50.089176 Jitter Meter : NO K
5970 14:46:50.089267 CBT Training : PASS
5971 14:46:50.092451 Write leveling : PASS
5972 14:46:50.095894 RX DQS gating : PASS
5973 14:46:50.095991 RX DQ/DQS(RDDQC) : PASS
5974 14:46:50.099245 TX DQ/DQS : PASS
5975 14:46:50.102689 RX DATLAT : PASS
5976 14:46:50.102771 RX DQ/DQS(Engine): PASS
5977 14:46:50.105649 TX OE : NO K
5978 14:46:50.105730 All Pass.
5979 14:46:50.105793
5980 14:46:50.109245 DramC Write-DBI off
5981 14:46:50.112374 PER_BANK_REFRESH: Hybrid Mode
5982 14:46:50.112456 TX_TRACKING: ON
5983 14:46:50.121875 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5984 14:46:50.125652 [FAST_K] Save calibration result to emmc
5985 14:46:50.129123 dramc_set_vcore_voltage set vcore to 650000
5986 14:46:50.131943 Read voltage for 400, 6
5987 14:46:50.132027 Vio18 = 0
5988 14:46:50.135491 Vcore = 650000
5989 14:46:50.135572 Vdram = 0
5990 14:46:50.135635 Vddq = 0
5991 14:46:50.135694 Vmddr = 0
5992 14:46:50.142457 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5993 14:46:50.148802 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5994 14:46:50.148894 MEM_TYPE=3, freq_sel=20
5995 14:46:50.151652 sv_algorithm_assistance_LP4_800
5996 14:46:50.155189 ============ PULL DRAM RESETB DOWN ============
5997 14:46:50.161619 ========== PULL DRAM RESETB DOWN end =========
5998 14:46:50.165620 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5999 14:46:50.168781 ===================================
6000 14:46:50.171663 LPDDR4 DRAM CONFIGURATION
6001 14:46:50.174935 ===================================
6002 14:46:50.175018 EX_ROW_EN[0] = 0x0
6003 14:46:50.178077 EX_ROW_EN[1] = 0x0
6004 14:46:50.178159 LP4Y_EN = 0x0
6005 14:46:50.181697 WORK_FSP = 0x0
6006 14:46:50.184488 WL = 0x2
6007 14:46:50.184574 RL = 0x2
6008 14:46:50.188151 BL = 0x2
6009 14:46:50.188264 RPST = 0x0
6010 14:46:50.191397 RD_PRE = 0x0
6011 14:46:50.191496 WR_PRE = 0x1
6012 14:46:50.194727 WR_PST = 0x0
6013 14:46:50.194803 DBI_WR = 0x0
6014 14:46:50.198507 DBI_RD = 0x0
6015 14:46:50.198588 OTF = 0x1
6016 14:46:50.201828 ===================================
6017 14:46:50.205064 ===================================
6018 14:46:50.207547 ANA top config
6019 14:46:50.211489 ===================================
6020 14:46:50.211570 DLL_ASYNC_EN = 0
6021 14:46:50.214512 ALL_SLAVE_EN = 1
6022 14:46:50.217769 NEW_RANK_MODE = 1
6023 14:46:50.220857 DLL_IDLE_MODE = 1
6024 14:46:50.224129 LP45_APHY_COMB_EN = 1
6025 14:46:50.224244 TX_ODT_DIS = 1
6026 14:46:50.227951 NEW_8X_MODE = 1
6027 14:46:50.231360 ===================================
6028 14:46:50.233918 ===================================
6029 14:46:50.237634 data_rate = 800
6030 14:46:50.240948 CKR = 1
6031 14:46:50.243743 DQ_P2S_RATIO = 4
6032 14:46:50.247378 ===================================
6033 14:46:50.250595 CA_P2S_RATIO = 4
6034 14:46:50.250669 DQ_CA_OPEN = 0
6035 14:46:50.253836 DQ_SEMI_OPEN = 1
6036 14:46:50.257763 CA_SEMI_OPEN = 1
6037 14:46:50.260940 CA_FULL_RATE = 0
6038 14:46:50.263555 DQ_CKDIV4_EN = 0
6039 14:46:50.267158 CA_CKDIV4_EN = 1
6040 14:46:50.267231 CA_PREDIV_EN = 0
6041 14:46:50.270067 PH8_DLY = 0
6042 14:46:50.273288 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6043 14:46:50.276805 DQ_AAMCK_DIV = 0
6044 14:46:50.280232 CA_AAMCK_DIV = 0
6045 14:46:50.283493 CA_ADMCK_DIV = 4
6046 14:46:50.283591 DQ_TRACK_CA_EN = 0
6047 14:46:50.287303 CA_PICK = 800
6048 14:46:50.289915 CA_MCKIO = 400
6049 14:46:50.294537 MCKIO_SEMI = 400
6050 14:46:50.296604 PLL_FREQ = 3016
6051 14:46:50.299624 DQ_UI_PI_RATIO = 32
6052 14:46:50.304156 CA_UI_PI_RATIO = 32
6053 14:46:50.306574 ===================================
6054 14:46:50.310429 ===================================
6055 14:46:50.310509 memory_type:LPDDR4
6056 14:46:50.313084 GP_NUM : 10
6057 14:46:50.316040 SRAM_EN : 1
6058 14:46:50.316116 MD32_EN : 0
6059 14:46:50.319804 ===================================
6060 14:46:50.323223 [ANA_INIT] >>>>>>>>>>>>>>
6061 14:46:50.326096 <<<<<< [CONFIGURE PHASE]: ANA_TX
6062 14:46:50.329661 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6063 14:46:50.332595 ===================================
6064 14:46:50.336017 data_rate = 800,PCW = 0X7400
6065 14:46:50.339019 ===================================
6066 14:46:50.342595 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6067 14:46:50.345728 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6068 14:46:50.358903 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6069 14:46:50.362596 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6070 14:46:50.366201 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6071 14:46:50.369306 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6072 14:46:50.372264 [ANA_INIT] flow start
6073 14:46:50.375348 [ANA_INIT] PLL >>>>>>>>
6074 14:46:50.375433 [ANA_INIT] PLL <<<<<<<<
6075 14:46:50.378898 [ANA_INIT] MIDPI >>>>>>>>
6076 14:46:50.381867 [ANA_INIT] MIDPI <<<<<<<<
6077 14:46:50.385540 [ANA_INIT] DLL >>>>>>>>
6078 14:46:50.385627 [ANA_INIT] flow end
6079 14:46:50.388928 ============ LP4 DIFF to SE enter ============
6080 14:46:50.395309 ============ LP4 DIFF to SE exit ============
6081 14:46:50.395400 [ANA_INIT] <<<<<<<<<<<<<
6082 14:46:50.398341 [Flow] Enable top DCM control >>>>>
6083 14:46:50.401979 [Flow] Enable top DCM control <<<<<
6084 14:46:50.404881 Enable DLL master slave shuffle
6085 14:46:50.411945 ==============================================================
6086 14:46:50.412029 Gating Mode config
6087 14:46:50.418370 ==============================================================
6088 14:46:50.421400 Config description:
6089 14:46:50.431361 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6090 14:46:50.437697 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6091 14:46:50.441183 SELPH_MODE 0: By rank 1: By Phase
6092 14:46:50.448454 ==============================================================
6093 14:46:50.450951 GAT_TRACK_EN = 0
6094 14:46:50.454290 RX_GATING_MODE = 2
6095 14:46:50.457777 RX_GATING_TRACK_MODE = 2
6096 14:46:50.457860 SELPH_MODE = 1
6097 14:46:50.461299 PICG_EARLY_EN = 1
6098 14:46:50.464298 VALID_LAT_VALUE = 1
6099 14:46:50.470804 ==============================================================
6100 14:46:50.474025 Enter into Gating configuration >>>>
6101 14:46:50.477186 Exit from Gating configuration <<<<
6102 14:46:50.481039 Enter into DVFS_PRE_config >>>>>
6103 14:46:50.490702 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6104 14:46:50.493702 Exit from DVFS_PRE_config <<<<<
6105 14:46:50.497017 Enter into PICG configuration >>>>
6106 14:46:50.500538 Exit from PICG configuration <<<<
6107 14:46:50.504038 [RX_INPUT] configuration >>>>>
6108 14:46:50.507705 [RX_INPUT] configuration <<<<<
6109 14:46:50.510328 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6110 14:46:50.517345 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6111 14:46:50.523780 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6112 14:46:50.530047 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6113 14:46:50.536902 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6114 14:46:50.543792 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6115 14:46:50.546524 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6116 14:46:50.550188 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6117 14:46:50.553142 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6118 14:46:50.559468 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6119 14:46:50.563155 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6120 14:46:50.566342 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6121 14:46:50.569382 ===================================
6122 14:46:50.572857 LPDDR4 DRAM CONFIGURATION
6123 14:46:50.575972 ===================================
6124 14:46:50.579298 EX_ROW_EN[0] = 0x0
6125 14:46:50.579388 EX_ROW_EN[1] = 0x0
6126 14:46:50.582896 LP4Y_EN = 0x0
6127 14:46:50.582974 WORK_FSP = 0x0
6128 14:46:50.586025 WL = 0x2
6129 14:46:50.586103 RL = 0x2
6130 14:46:50.589239 BL = 0x2
6131 14:46:50.589375 RPST = 0x0
6132 14:46:50.592357 RD_PRE = 0x0
6133 14:46:50.592454 WR_PRE = 0x1
6134 14:46:50.595796 WR_PST = 0x0
6135 14:46:50.595892 DBI_WR = 0x0
6136 14:46:50.599469 DBI_RD = 0x0
6137 14:46:50.599567 OTF = 0x1
6138 14:46:50.602240 ===================================
6139 14:46:50.609064 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6140 14:46:50.612597 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6141 14:46:50.615585 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6142 14:46:50.619083 ===================================
6143 14:46:50.622797 LPDDR4 DRAM CONFIGURATION
6144 14:46:50.625869 ===================================
6145 14:46:50.628730 EX_ROW_EN[0] = 0x10
6146 14:46:50.628804 EX_ROW_EN[1] = 0x0
6147 14:46:50.632590 LP4Y_EN = 0x0
6148 14:46:50.632668 WORK_FSP = 0x0
6149 14:46:50.635262 WL = 0x2
6150 14:46:50.635362 RL = 0x2
6151 14:46:50.638769 BL = 0x2
6152 14:46:50.638844 RPST = 0x0
6153 14:46:50.641925 RD_PRE = 0x0
6154 14:46:50.641999 WR_PRE = 0x1
6155 14:46:50.645086 WR_PST = 0x0
6156 14:46:50.645182 DBI_WR = 0x0
6157 14:46:50.648295 DBI_RD = 0x0
6158 14:46:50.648383 OTF = 0x1
6159 14:46:50.651800 ===================================
6160 14:46:50.658390 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6161 14:46:50.663335 nWR fixed to 30
6162 14:46:50.666705 [ModeRegInit_LP4] CH0 RK0
6163 14:46:50.666776 [ModeRegInit_LP4] CH0 RK1
6164 14:46:50.670208 [ModeRegInit_LP4] CH1 RK0
6165 14:46:50.673090 [ModeRegInit_LP4] CH1 RK1
6166 14:46:50.673189 match AC timing 19
6167 14:46:50.680327 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6168 14:46:50.683688 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6169 14:46:50.686824 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6170 14:46:50.693010 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6171 14:46:50.696079 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6172 14:46:50.696169 ==
6173 14:46:50.699677 Dram Type= 6, Freq= 0, CH_0, rank 0
6174 14:46:50.703150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6175 14:46:50.703234 ==
6176 14:46:50.709467 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6177 14:46:50.715970 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6178 14:46:50.719260 [CA 0] Center 36 (8~64) winsize 57
6179 14:46:50.722429 [CA 1] Center 36 (8~64) winsize 57
6180 14:46:50.725723 [CA 2] Center 36 (8~64) winsize 57
6181 14:46:50.729254 [CA 3] Center 36 (8~64) winsize 57
6182 14:46:50.733419 [CA 4] Center 36 (8~64) winsize 57
6183 14:46:50.736007 [CA 5] Center 36 (8~64) winsize 57
6184 14:46:50.736092
6185 14:46:50.739039 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6186 14:46:50.739121
6187 14:46:50.742297 [CATrainingPosCal] consider 1 rank data
6188 14:46:50.745980 u2DelayCellTimex100 = 270/100 ps
6189 14:46:50.749951 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6190 14:46:50.752298 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6191 14:46:50.755572 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6192 14:46:50.759421 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6193 14:46:50.762148 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6194 14:46:50.765272 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6195 14:46:50.765372
6196 14:46:50.772689 CA PerBit enable=1, Macro0, CA PI delay=36
6197 14:46:50.772840
6198 14:46:50.772907 [CBTSetCACLKResult] CA Dly = 36
6199 14:46:50.775506 CS Dly: 1 (0~32)
6200 14:46:50.775587 ==
6201 14:46:50.778706 Dram Type= 6, Freq= 0, CH_0, rank 1
6202 14:46:50.781595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6203 14:46:50.781679 ==
6204 14:46:50.788767 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6205 14:46:50.794790 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6206 14:46:50.798118 [CA 0] Center 36 (8~64) winsize 57
6207 14:46:50.801779 [CA 1] Center 36 (8~64) winsize 57
6208 14:46:50.804615 [CA 2] Center 36 (8~64) winsize 57
6209 14:46:50.807869 [CA 3] Center 36 (8~64) winsize 57
6210 14:46:50.811639 [CA 4] Center 36 (8~64) winsize 57
6211 14:46:50.814465 [CA 5] Center 36 (8~64) winsize 57
6212 14:46:50.814549
6213 14:46:50.817734 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6214 14:46:50.817920
6215 14:46:50.821180 [CATrainingPosCal] consider 2 rank data
6216 14:46:50.825056 u2DelayCellTimex100 = 270/100 ps
6217 14:46:50.827474 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 14:46:50.831097 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 14:46:50.834523 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 14:46:50.838138 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 14:46:50.840844 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 14:46:50.844226 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 14:46:50.844310
6224 14:46:50.850661 CA PerBit enable=1, Macro0, CA PI delay=36
6225 14:46:50.850766
6226 14:46:50.850833 [CBTSetCACLKResult] CA Dly = 36
6227 14:46:50.854233 CS Dly: 1 (0~32)
6228 14:46:50.854317
6229 14:46:50.857193 ----->DramcWriteLeveling(PI) begin...
6230 14:46:50.857308 ==
6231 14:46:50.860764 Dram Type= 6, Freq= 0, CH_0, rank 0
6232 14:46:50.864032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6233 14:46:50.864120 ==
6234 14:46:50.867174 Write leveling (Byte 0): 40 => 8
6235 14:46:50.870589 Write leveling (Byte 1): 40 => 8
6236 14:46:50.873672 DramcWriteLeveling(PI) end<-----
6237 14:46:50.873761
6238 14:46:50.873827 ==
6239 14:46:50.877770 Dram Type= 6, Freq= 0, CH_0, rank 0
6240 14:46:50.880361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6241 14:46:50.883648 ==
6242 14:46:50.883741 [Gating] SW mode calibration
6243 14:46:50.894281 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6244 14:46:50.896832 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6245 14:46:50.899918 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6246 14:46:50.907151 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6247 14:46:50.910080 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6248 14:46:50.913556 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6249 14:46:50.919840 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6250 14:46:50.923129 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6251 14:46:50.926523 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6252 14:46:50.932955 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6253 14:46:50.936094 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6254 14:46:50.939910 Total UI for P1: 0, mck2ui 16
6255 14:46:50.942910 best dqsien dly found for B0: ( 0, 14, 24)
6256 14:46:50.946162 Total UI for P1: 0, mck2ui 16
6257 14:46:50.949424 best dqsien dly found for B1: ( 0, 14, 24)
6258 14:46:50.952841 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6259 14:46:50.956255 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6260 14:46:50.956326
6261 14:46:50.960416 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6262 14:46:50.966321 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6263 14:46:50.966409 [Gating] SW calibration Done
6264 14:46:50.966471 ==
6265 14:46:50.969416 Dram Type= 6, Freq= 0, CH_0, rank 0
6266 14:46:50.975820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6267 14:46:50.975904 ==
6268 14:46:50.975967 RX Vref Scan: 0
6269 14:46:50.976032
6270 14:46:50.980153 RX Vref 0 -> 0, step: 1
6271 14:46:50.980238
6272 14:46:50.982385 RX Delay -410 -> 252, step: 16
6273 14:46:50.985939 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6274 14:46:50.989029 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6275 14:46:50.995945 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6276 14:46:50.999607 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6277 14:46:51.002612 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6278 14:46:51.006079 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6279 14:46:51.012177 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6280 14:46:51.015340 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6281 14:46:51.018904 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6282 14:46:51.022148 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6283 14:46:51.028625 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6284 14:46:51.032066 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6285 14:46:51.035092 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6286 14:46:51.041665 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6287 14:46:51.045003 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6288 14:46:51.048139 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6289 14:46:51.048222 ==
6290 14:46:51.051896 Dram Type= 6, Freq= 0, CH_0, rank 0
6291 14:46:51.054847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 14:46:51.058756 ==
6293 14:46:51.058840 DQS Delay:
6294 14:46:51.058903 DQS0 = 35, DQS1 = 59
6295 14:46:51.061419 DQM Delay:
6296 14:46:51.061499 DQM0 = 4, DQM1 = 17
6297 14:46:51.064805 DQ Delay:
6298 14:46:51.064888 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6299 14:46:51.068015 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6300 14:46:51.071526 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6301 14:46:51.074378 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6302 14:46:51.074459
6303 14:46:51.074522
6304 14:46:51.077987 ==
6305 14:46:51.081174 Dram Type= 6, Freq= 0, CH_0, rank 0
6306 14:46:51.084687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 14:46:51.084797 ==
6308 14:46:51.084895
6309 14:46:51.084983
6310 14:46:51.087999 TX Vref Scan disable
6311 14:46:51.088082 == TX Byte 0 ==
6312 14:46:51.091180 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6313 14:46:51.097531 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6314 14:46:51.097619 == TX Byte 1 ==
6315 14:46:51.101405 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6316 14:46:51.108133 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6317 14:46:51.108249 ==
6318 14:46:51.110875 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 14:46:51.113939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 14:46:51.114046 ==
6321 14:46:51.114136
6322 14:46:51.114226
6323 14:46:51.117621 TX Vref Scan disable
6324 14:46:51.117702 == TX Byte 0 ==
6325 14:46:51.120762 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6326 14:46:51.127507 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6327 14:46:51.127617 == TX Byte 1 ==
6328 14:46:51.130562 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6329 14:46:51.136902 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6330 14:46:51.137012
6331 14:46:51.137110 [DATLAT]
6332 14:46:51.140744 Freq=400, CH0 RK0
6333 14:46:51.140851
6334 14:46:51.140952 DATLAT Default: 0xf
6335 14:46:51.143858 0, 0xFFFF, sum = 0
6336 14:46:51.143940 1, 0xFFFF, sum = 0
6337 14:46:51.146927 2, 0xFFFF, sum = 0
6338 14:46:51.147067 3, 0xFFFF, sum = 0
6339 14:46:51.150480 4, 0xFFFF, sum = 0
6340 14:46:51.150587 5, 0xFFFF, sum = 0
6341 14:46:51.153534 6, 0xFFFF, sum = 0
6342 14:46:51.153630 7, 0xFFFF, sum = 0
6343 14:46:51.157390 8, 0xFFFF, sum = 0
6344 14:46:51.157556 9, 0xFFFF, sum = 0
6345 14:46:51.159956 10, 0xFFFF, sum = 0
6346 14:46:51.163310 11, 0xFFFF, sum = 0
6347 14:46:51.163420 12, 0xFFFF, sum = 0
6348 14:46:51.166596 13, 0x0, sum = 1
6349 14:46:51.166688 14, 0x0, sum = 2
6350 14:46:51.166749 15, 0x0, sum = 3
6351 14:46:51.169788 16, 0x0, sum = 4
6352 14:46:51.169891 best_step = 14
6353 14:46:51.169984
6354 14:46:51.173110 ==
6355 14:46:51.176369 Dram Type= 6, Freq= 0, CH_0, rank 0
6356 14:46:51.179835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 14:46:51.179917 ==
6358 14:46:51.179980 RX Vref Scan: 1
6359 14:46:51.180039
6360 14:46:51.183047 RX Vref 0 -> 0, step: 1
6361 14:46:51.183127
6362 14:46:51.186354 RX Delay -359 -> 252, step: 8
6363 14:46:51.186449
6364 14:46:51.189424 Set Vref, RX VrefLevel [Byte0]: 57
6365 14:46:51.192925 [Byte1]: 58
6366 14:46:51.196977
6367 14:46:51.197058 Final RX Vref Byte 0 = 57 to rank0
6368 14:46:51.199999 Final RX Vref Byte 1 = 58 to rank0
6369 14:46:51.203475 Final RX Vref Byte 0 = 57 to rank1
6370 14:46:51.206645 Final RX Vref Byte 1 = 58 to rank1==
6371 14:46:51.210335 Dram Type= 6, Freq= 0, CH_0, rank 0
6372 14:46:51.216725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6373 14:46:51.216810 ==
6374 14:46:51.216874 DQS Delay:
6375 14:46:51.220091 DQS0 = 44, DQS1 = 60
6376 14:46:51.220173 DQM Delay:
6377 14:46:51.223135 DQM0 = 11, DQM1 = 16
6378 14:46:51.223216 DQ Delay:
6379 14:46:51.226578 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6380 14:46:51.229593 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6381 14:46:51.233016 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6382 14:46:51.236304 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6383 14:46:51.236424
6384 14:46:51.236503
6385 14:46:51.242835 [DQSOSCAuto] RK0, (LSB)MR18= 0x988d, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
6386 14:46:51.246031 CH0 RK0: MR19=C0C, MR18=988D
6387 14:46:51.253009 CH0_RK0: MR19=0xC0C, MR18=0x988D, DQSOSC=390, MR23=63, INC=388, DEC=258
6388 14:46:51.253114 ==
6389 14:46:51.255941 Dram Type= 6, Freq= 0, CH_0, rank 1
6390 14:46:51.259277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 14:46:51.259388 ==
6392 14:46:51.262676 [Gating] SW mode calibration
6393 14:46:51.269049 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6394 14:46:51.275604 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6395 14:46:51.278863 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6396 14:46:51.282376 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6397 14:46:51.289183 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6398 14:46:51.292811 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6399 14:46:51.295635 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6400 14:46:51.302260 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6401 14:46:51.305542 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6402 14:46:51.308872 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6403 14:46:51.315228 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6404 14:46:51.318997 Total UI for P1: 0, mck2ui 16
6405 14:46:51.321829 best dqsien dly found for B0: ( 0, 14, 24)
6406 14:46:51.325383 Total UI for P1: 0, mck2ui 16
6407 14:46:51.328953 best dqsien dly found for B1: ( 0, 14, 24)
6408 14:46:51.331870 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6409 14:46:51.335149 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6410 14:46:51.335231
6411 14:46:51.338368 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6412 14:46:51.341940 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6413 14:46:51.345195 [Gating] SW calibration Done
6414 14:46:51.345316 ==
6415 14:46:51.348574 Dram Type= 6, Freq= 0, CH_0, rank 1
6416 14:46:51.352108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6417 14:46:51.352219 ==
6418 14:46:51.355086 RX Vref Scan: 0
6419 14:46:51.355167
6420 14:46:51.357975 RX Vref 0 -> 0, step: 1
6421 14:46:51.358078
6422 14:46:51.358211 RX Delay -410 -> 252, step: 16
6423 14:46:51.365301 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6424 14:46:51.367995 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6425 14:46:51.371863 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6426 14:46:51.377975 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6427 14:46:51.381872 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6428 14:46:51.384694 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6429 14:46:51.387844 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6430 14:46:51.394474 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6431 14:46:51.398311 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6432 14:46:51.401183 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6433 14:46:51.404571 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6434 14:46:51.411023 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6435 14:46:51.414345 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6436 14:46:51.417867 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6437 14:46:51.421120 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6438 14:46:51.427591 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6439 14:46:51.427669 ==
6440 14:46:51.430704 Dram Type= 6, Freq= 0, CH_0, rank 1
6441 14:46:51.434123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 14:46:51.434195 ==
6443 14:46:51.434255 DQS Delay:
6444 14:46:51.437350 DQS0 = 35, DQS1 = 59
6445 14:46:51.437420 DQM Delay:
6446 14:46:51.440889 DQM0 = 9, DQM1 = 17
6447 14:46:51.440956 DQ Delay:
6448 14:46:51.444012 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6449 14:46:51.447357 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6450 14:46:51.450792 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6451 14:46:51.454003 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6452 14:46:51.454078
6453 14:46:51.454138
6454 14:46:51.454196 ==
6455 14:46:51.457588 Dram Type= 6, Freq= 0, CH_0, rank 1
6456 14:46:51.460729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 14:46:51.460806 ==
6458 14:46:51.460866
6459 14:46:51.460922
6460 14:46:51.463874 TX Vref Scan disable
6461 14:46:51.467360 == TX Byte 0 ==
6462 14:46:51.470714 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6463 14:46:51.474102 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6464 14:46:51.474173 == TX Byte 1 ==
6465 14:46:51.480609 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6466 14:46:51.483884 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6467 14:46:51.483972 ==
6468 14:46:51.488131 Dram Type= 6, Freq= 0, CH_0, rank 1
6469 14:46:51.490590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 14:46:51.490666 ==
6471 14:46:51.490727
6472 14:46:51.493595
6473 14:46:51.493663 TX Vref Scan disable
6474 14:46:51.497119 == TX Byte 0 ==
6475 14:46:51.500286 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6476 14:46:51.503763 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6477 14:46:51.506721 == TX Byte 1 ==
6478 14:46:51.510039 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6479 14:46:51.513562 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6480 14:46:51.513633
6481 14:46:51.513692 [DATLAT]
6482 14:46:51.516672 Freq=400, CH0 RK1
6483 14:46:51.516741
6484 14:46:51.520439 DATLAT Default: 0xe
6485 14:46:51.520543 0, 0xFFFF, sum = 0
6486 14:46:51.523661 1, 0xFFFF, sum = 0
6487 14:46:51.523744 2, 0xFFFF, sum = 0
6488 14:46:51.526567 3, 0xFFFF, sum = 0
6489 14:46:51.526649 4, 0xFFFF, sum = 0
6490 14:46:51.530383 5, 0xFFFF, sum = 0
6491 14:46:51.530465 6, 0xFFFF, sum = 0
6492 14:46:51.533162 7, 0xFFFF, sum = 0
6493 14:46:51.533245 8, 0xFFFF, sum = 0
6494 14:46:51.536678 9, 0xFFFF, sum = 0
6495 14:46:51.536776 10, 0xFFFF, sum = 0
6496 14:46:51.540259 11, 0xFFFF, sum = 0
6497 14:46:51.540345 12, 0xFFFF, sum = 0
6498 14:46:51.542972 13, 0x0, sum = 1
6499 14:46:51.543054 14, 0x0, sum = 2
6500 14:46:51.546916 15, 0x0, sum = 3
6501 14:46:51.546997 16, 0x0, sum = 4
6502 14:46:51.550009 best_step = 14
6503 14:46:51.550090
6504 14:46:51.550154 ==
6505 14:46:51.552828 Dram Type= 6, Freq= 0, CH_0, rank 1
6506 14:46:51.556274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6507 14:46:51.556356 ==
6508 14:46:51.559606 RX Vref Scan: 0
6509 14:46:51.559703
6510 14:46:51.559780 RX Vref 0 -> 0, step: 1
6511 14:46:51.559841
6512 14:46:51.563010 RX Delay -359 -> 252, step: 8
6513 14:46:51.571527 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6514 14:46:51.574289 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6515 14:46:51.577588 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6516 14:46:51.584105 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6517 14:46:51.587549 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6518 14:46:51.591304 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6519 14:46:51.593992 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6520 14:46:51.600815 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6521 14:46:51.603861 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6522 14:46:51.607602 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6523 14:46:51.610708 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6524 14:46:51.618129 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6525 14:46:51.621214 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6526 14:46:51.623564 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6527 14:46:51.627652 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6528 14:46:51.633671 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6529 14:46:51.633775 ==
6530 14:46:51.637280 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 14:46:51.640469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 14:46:51.640547 ==
6533 14:46:51.640608 DQS Delay:
6534 14:46:51.643461 DQS0 = 44, DQS1 = 60
6535 14:46:51.643554 DQM Delay:
6536 14:46:51.647387 DQM0 = 9, DQM1 = 15
6537 14:46:51.647458 DQ Delay:
6538 14:46:51.650039 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6539 14:46:51.653520 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =12
6540 14:46:51.656633 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6541 14:46:51.659951 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6542 14:46:51.660023
6543 14:46:51.660082
6544 14:46:51.666587 [DQSOSCAuto] RK1, (LSB)MR18= 0x8c85, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6545 14:46:51.669783 CH0 RK1: MR19=C0C, MR18=8C85
6546 14:46:51.676379 CH0_RK1: MR19=0xC0C, MR18=0x8C85, DQSOSC=392, MR23=63, INC=384, DEC=256
6547 14:46:51.679475 [RxdqsGatingPostProcess] freq 400
6548 14:46:51.686293 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6549 14:46:51.689250 best DQS0 dly(2T, 0.5T) = (0, 10)
6550 14:46:51.693498 best DQS1 dly(2T, 0.5T) = (0, 10)
6551 14:46:51.696113 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6552 14:46:51.699678 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6553 14:46:51.702751 best DQS0 dly(2T, 0.5T) = (0, 10)
6554 14:46:51.702830 best DQS1 dly(2T, 0.5T) = (0, 10)
6555 14:46:51.706078 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6556 14:46:51.709283 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6557 14:46:51.712991 Pre-setting of DQS Precalculation
6558 14:46:51.719380 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6559 14:46:51.719467 ==
6560 14:46:51.722361 Dram Type= 6, Freq= 0, CH_1, rank 0
6561 14:46:51.725791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 14:46:51.725874 ==
6563 14:46:51.732289 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6564 14:46:51.739245 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6565 14:46:51.742123 [CA 0] Center 36 (8~64) winsize 57
6566 14:46:51.745560 [CA 1] Center 36 (8~64) winsize 57
6567 14:46:51.748798 [CA 2] Center 36 (8~64) winsize 57
6568 14:46:51.752183 [CA 3] Center 36 (8~64) winsize 57
6569 14:46:51.752253 [CA 4] Center 36 (8~64) winsize 57
6570 14:46:51.755564 [CA 5] Center 36 (8~64) winsize 57
6571 14:46:51.755631
6572 14:46:51.761972 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6573 14:46:51.762048
6574 14:46:51.765326 [CATrainingPosCal] consider 1 rank data
6575 14:46:51.768449 u2DelayCellTimex100 = 270/100 ps
6576 14:46:51.772023 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6577 14:46:51.775628 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6578 14:46:51.778399 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6579 14:46:51.781990 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6580 14:46:51.785196 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6581 14:46:51.788661 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6582 14:46:51.788741
6583 14:46:51.792125 CA PerBit enable=1, Macro0, CA PI delay=36
6584 14:46:51.792201
6585 14:46:51.794855 [CBTSetCACLKResult] CA Dly = 36
6586 14:46:51.798259 CS Dly: 1 (0~32)
6587 14:46:51.798344 ==
6588 14:46:51.801908 Dram Type= 6, Freq= 0, CH_1, rank 1
6589 14:46:51.805513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6590 14:46:51.805600 ==
6591 14:46:51.811662 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6592 14:46:51.818103 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6593 14:46:51.821555 [CA 0] Center 36 (8~64) winsize 57
6594 14:46:51.824951 [CA 1] Center 36 (8~64) winsize 57
6595 14:46:51.825038 [CA 2] Center 36 (8~64) winsize 57
6596 14:46:51.828055 [CA 3] Center 36 (8~64) winsize 57
6597 14:46:51.831512 [CA 4] Center 36 (8~64) winsize 57
6598 14:46:51.834477 [CA 5] Center 36 (8~64) winsize 57
6599 14:46:51.834589
6600 14:46:51.837771 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6601 14:46:51.841167
6602 14:46:51.844298 [CATrainingPosCal] consider 2 rank data
6603 14:46:51.844381 u2DelayCellTimex100 = 270/100 ps
6604 14:46:51.851049 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 14:46:51.855345 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 14:46:51.858100 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 14:46:51.861121 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 14:46:51.864113 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 14:46:51.867389 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 14:46:51.867462
6611 14:46:51.871185 CA PerBit enable=1, Macro0, CA PI delay=36
6612 14:46:51.871289
6613 14:46:51.874151 [CBTSetCACLKResult] CA Dly = 36
6614 14:46:51.877178 CS Dly: 1 (0~32)
6615 14:46:51.877296
6616 14:46:51.880616 ----->DramcWriteLeveling(PI) begin...
6617 14:46:51.880717 ==
6618 14:46:51.884336 Dram Type= 6, Freq= 0, CH_1, rank 0
6619 14:46:51.887960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 14:46:51.888047 ==
6621 14:46:51.890585 Write leveling (Byte 0): 40 => 8
6622 14:46:51.894079 Write leveling (Byte 1): 40 => 8
6623 14:46:51.898071 DramcWriteLeveling(PI) end<-----
6624 14:46:51.898156
6625 14:46:51.898224 ==
6626 14:46:51.901055 Dram Type= 6, Freq= 0, CH_1, rank 0
6627 14:46:51.903802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6628 14:46:51.903888 ==
6629 14:46:51.907151 [Gating] SW mode calibration
6630 14:46:51.913625 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6631 14:46:51.920054 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6632 14:46:51.923649 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6633 14:46:51.927153 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6634 14:46:51.933670 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6635 14:46:51.937095 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6636 14:46:51.939749 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6637 14:46:51.946362 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6638 14:46:51.951137 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6639 14:46:51.957463 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6640 14:46:51.960161 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6641 14:46:51.962711 Total UI for P1: 0, mck2ui 16
6642 14:46:51.966096 best dqsien dly found for B0: ( 0, 14, 24)
6643 14:46:51.969842 Total UI for P1: 0, mck2ui 16
6644 14:46:51.972906 best dqsien dly found for B1: ( 0, 14, 24)
6645 14:46:51.975898 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6646 14:46:51.979404 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6647 14:46:51.979520
6648 14:46:51.982720 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6649 14:46:51.985963 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6650 14:46:51.989552 [Gating] SW calibration Done
6651 14:46:51.989648 ==
6652 14:46:51.992835 Dram Type= 6, Freq= 0, CH_1, rank 0
6653 14:46:51.996132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6654 14:46:51.999366 ==
6655 14:46:51.999475 RX Vref Scan: 0
6656 14:46:51.999575
6657 14:46:52.002581 RX Vref 0 -> 0, step: 1
6658 14:46:52.002687
6659 14:46:52.005910 RX Delay -410 -> 252, step: 16
6660 14:46:52.009410 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6661 14:46:52.012726 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6662 14:46:52.016559 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6663 14:46:52.022251 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6664 14:46:52.025974 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6665 14:46:52.028823 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6666 14:46:52.033090 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6667 14:46:52.038638 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6668 14:46:52.041834 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6669 14:46:52.045423 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6670 14:46:52.048814 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6671 14:46:52.055176 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6672 14:46:52.058325 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6673 14:46:52.061990 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6674 14:46:52.068400 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6675 14:46:52.071431 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6676 14:46:52.071553 ==
6677 14:46:52.075178 Dram Type= 6, Freq= 0, CH_1, rank 0
6678 14:46:52.078209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 14:46:52.078323 ==
6680 14:46:52.081664 DQS Delay:
6681 14:46:52.081778 DQS0 = 35, DQS1 = 51
6682 14:46:52.085086 DQM Delay:
6683 14:46:52.085190 DQM0 = 6, DQM1 = 13
6684 14:46:52.085266 DQ Delay:
6685 14:46:52.088240 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6686 14:46:52.091236 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6687 14:46:52.094793 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6688 14:46:52.097973 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6689 14:46:52.098056
6690 14:46:52.098120
6691 14:46:52.098179 ==
6692 14:46:52.101114 Dram Type= 6, Freq= 0, CH_1, rank 0
6693 14:46:52.107799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 14:46:52.107887 ==
6695 14:46:52.107952
6696 14:46:52.108012
6697 14:46:52.108069 TX Vref Scan disable
6698 14:46:52.111416 == TX Byte 0 ==
6699 14:46:52.114489 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6700 14:46:52.118117 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6701 14:46:52.121161 == TX Byte 1 ==
6702 14:46:52.124778 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6703 14:46:52.127415 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6704 14:46:52.127502 ==
6705 14:46:52.131003 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 14:46:52.138053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 14:46:52.138159 ==
6708 14:46:52.138239
6709 14:46:52.138298
6710 14:46:52.138355 TX Vref Scan disable
6711 14:46:52.140819 == TX Byte 0 ==
6712 14:46:52.144540 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6713 14:46:52.147336 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6714 14:46:52.150577 == TX Byte 1 ==
6715 14:46:52.153878 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6716 14:46:52.157352 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6717 14:46:52.157442
6718 14:46:52.160492 [DATLAT]
6719 14:46:52.160591 Freq=400, CH1 RK0
6720 14:46:52.160672
6721 14:46:52.163894 DATLAT Default: 0xf
6722 14:46:52.164008 0, 0xFFFF, sum = 0
6723 14:46:52.167533 1, 0xFFFF, sum = 0
6724 14:46:52.167633 2, 0xFFFF, sum = 0
6725 14:46:52.170662 3, 0xFFFF, sum = 0
6726 14:46:52.170745 4, 0xFFFF, sum = 0
6727 14:46:52.174153 5, 0xFFFF, sum = 0
6728 14:46:52.177293 6, 0xFFFF, sum = 0
6729 14:46:52.177392 7, 0xFFFF, sum = 0
6730 14:46:52.180366 8, 0xFFFF, sum = 0
6731 14:46:52.180450 9, 0xFFFF, sum = 0
6732 14:46:52.183662 10, 0xFFFF, sum = 0
6733 14:46:52.183745 11, 0xFFFF, sum = 0
6734 14:46:52.187866 12, 0xFFFF, sum = 0
6735 14:46:52.187951 13, 0x0, sum = 1
6736 14:46:52.190145 14, 0x0, sum = 2
6737 14:46:52.190228 15, 0x0, sum = 3
6738 14:46:52.193800 16, 0x0, sum = 4
6739 14:46:52.193888 best_step = 14
6740 14:46:52.193953
6741 14:46:52.194012 ==
6742 14:46:52.197027 Dram Type= 6, Freq= 0, CH_1, rank 0
6743 14:46:52.200128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 14:46:52.203451 ==
6745 14:46:52.203532 RX Vref Scan: 1
6746 14:46:52.203596
6747 14:46:52.207042 RX Vref 0 -> 0, step: 1
6748 14:46:52.207124
6749 14:46:52.209943 RX Delay -343 -> 252, step: 8
6750 14:46:52.210024
6751 14:46:52.213546 Set Vref, RX VrefLevel [Byte0]: 51
6752 14:46:52.217576 [Byte1]: 54
6753 14:46:52.217657
6754 14:46:52.220067 Final RX Vref Byte 0 = 51 to rank0
6755 14:46:52.223500 Final RX Vref Byte 1 = 54 to rank0
6756 14:46:52.226791 Final RX Vref Byte 0 = 51 to rank1
6757 14:46:52.229593 Final RX Vref Byte 1 = 54 to rank1==
6758 14:46:52.233336 Dram Type= 6, Freq= 0, CH_1, rank 0
6759 14:46:52.236532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6760 14:46:52.236617 ==
6761 14:46:52.240142 DQS Delay:
6762 14:46:52.240226 DQS0 = 44, DQS1 = 52
6763 14:46:52.243352 DQM Delay:
6764 14:46:52.243435 DQM0 = 11, DQM1 = 11
6765 14:46:52.246617 DQ Delay:
6766 14:46:52.246701 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6767 14:46:52.249460 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6768 14:46:52.253119 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6769 14:46:52.256268 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6770 14:46:52.256352
6771 14:46:52.256435
6772 14:46:52.266335 [DQSOSCAuto] RK0, (LSB)MR18= 0x6b91, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps
6773 14:46:52.269640 CH1 RK0: MR19=C0C, MR18=6B91
6774 14:46:52.272579 CH1_RK0: MR19=0xC0C, MR18=0x6B91, DQSOSC=391, MR23=63, INC=386, DEC=257
6775 14:46:52.276110 ==
6776 14:46:52.279108 Dram Type= 6, Freq= 0, CH_1, rank 1
6777 14:46:52.282424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 14:46:52.282512 ==
6779 14:46:52.286256 [Gating] SW mode calibration
6780 14:46:52.292947 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6781 14:46:52.296038 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6782 14:46:52.302338 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6783 14:46:52.305613 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6784 14:46:52.308798 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6785 14:46:52.315436 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6786 14:46:52.319092 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6787 14:46:52.322091 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6788 14:46:52.328679 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6789 14:46:52.332399 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6790 14:46:52.335609 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6791 14:46:52.338613 Total UI for P1: 0, mck2ui 16
6792 14:46:52.341909 best dqsien dly found for B0: ( 0, 14, 24)
6793 14:46:52.345153 Total UI for P1: 0, mck2ui 16
6794 14:46:52.348384 best dqsien dly found for B1: ( 0, 14, 24)
6795 14:46:52.355122 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6796 14:46:52.358623 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6797 14:46:52.358705
6798 14:46:52.361949 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6799 14:46:52.364974 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6800 14:46:52.367927 [Gating] SW calibration Done
6801 14:46:52.368008 ==
6802 14:46:52.371784 Dram Type= 6, Freq= 0, CH_1, rank 1
6803 14:46:52.375263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6804 14:46:52.375375 ==
6805 14:46:52.377849 RX Vref Scan: 0
6806 14:46:52.377932
6807 14:46:52.377996 RX Vref 0 -> 0, step: 1
6808 14:46:52.378056
6809 14:46:52.381492 RX Delay -410 -> 252, step: 16
6810 14:46:52.387635 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6811 14:46:52.392125 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6812 14:46:52.394374 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6813 14:46:52.398129 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6814 14:46:52.404188 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6815 14:46:52.407915 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6816 14:46:52.410834 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6817 14:46:52.415031 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6818 14:46:52.421679 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6819 14:46:52.424358 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6820 14:46:52.427440 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6821 14:46:52.430594 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6822 14:46:52.437865 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6823 14:46:52.440475 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6824 14:46:52.443949 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6825 14:46:52.450590 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6826 14:46:52.450672 ==
6827 14:46:52.453645 Dram Type= 6, Freq= 0, CH_1, rank 1
6828 14:46:52.457386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 14:46:52.457468 ==
6830 14:46:52.457532 DQS Delay:
6831 14:46:52.461310 DQS0 = 43, DQS1 = 51
6832 14:46:52.461391 DQM Delay:
6833 14:46:52.463616 DQM0 = 8, DQM1 = 14
6834 14:46:52.463697 DQ Delay:
6835 14:46:52.467199 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6836 14:46:52.470007 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6837 14:46:52.473416 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6838 14:46:52.477399 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6839 14:46:52.477481
6840 14:46:52.477559
6841 14:46:52.477631 ==
6842 14:46:52.480283 Dram Type= 6, Freq= 0, CH_1, rank 1
6843 14:46:52.483300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 14:46:52.483387 ==
6845 14:46:52.483451
6846 14:46:52.483510
6847 14:46:52.486547 TX Vref Scan disable
6848 14:46:52.486629 == TX Byte 0 ==
6849 14:46:52.493406 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6850 14:46:52.496974 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6851 14:46:52.497058 == TX Byte 1 ==
6852 14:46:52.503327 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6853 14:46:52.506519 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6854 14:46:52.506601 ==
6855 14:46:52.509556 Dram Type= 6, Freq= 0, CH_1, rank 1
6856 14:46:52.513917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 14:46:52.513999 ==
6858 14:46:52.514063
6859 14:46:52.514121
6860 14:46:52.516579 TX Vref Scan disable
6861 14:46:52.519776 == TX Byte 0 ==
6862 14:46:52.523055 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6863 14:46:52.526107 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6864 14:46:52.530063 == TX Byte 1 ==
6865 14:46:52.533165 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6866 14:46:52.536396 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6867 14:46:52.536478
6868 14:46:52.536541 [DATLAT]
6869 14:46:52.539490 Freq=400, CH1 RK1
6870 14:46:52.539572
6871 14:46:52.539635 DATLAT Default: 0xe
6872 14:46:52.543159 0, 0xFFFF, sum = 0
6873 14:46:52.543258 1, 0xFFFF, sum = 0
6874 14:46:52.546634 2, 0xFFFF, sum = 0
6875 14:46:52.546716 3, 0xFFFF, sum = 0
6876 14:46:52.549833 4, 0xFFFF, sum = 0
6877 14:46:52.552529 5, 0xFFFF, sum = 0
6878 14:46:52.552612 6, 0xFFFF, sum = 0
6879 14:46:52.556030 7, 0xFFFF, sum = 0
6880 14:46:52.556113 8, 0xFFFF, sum = 0
6881 14:46:52.559505 9, 0xFFFF, sum = 0
6882 14:46:52.559587 10, 0xFFFF, sum = 0
6883 14:46:52.562770 11, 0xFFFF, sum = 0
6884 14:46:52.562852 12, 0xFFFF, sum = 0
6885 14:46:52.566032 13, 0x0, sum = 1
6886 14:46:52.566117 14, 0x0, sum = 2
6887 14:46:52.569180 15, 0x0, sum = 3
6888 14:46:52.569268 16, 0x0, sum = 4
6889 14:46:52.572355 best_step = 14
6890 14:46:52.572437
6891 14:46:52.572501 ==
6892 14:46:52.575782 Dram Type= 6, Freq= 0, CH_1, rank 1
6893 14:46:52.578966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6894 14:46:52.579048 ==
6895 14:46:52.579113 RX Vref Scan: 0
6896 14:46:52.582746
6897 14:46:52.582827 RX Vref 0 -> 0, step: 1
6898 14:46:52.582890
6899 14:46:52.585459 RX Delay -343 -> 252, step: 8
6900 14:46:52.593430 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6901 14:46:52.596699 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6902 14:46:52.599697 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6903 14:46:52.606527 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6904 14:46:52.610021 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6905 14:46:52.612922 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6906 14:46:52.616534 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6907 14:46:52.623384 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6908 14:46:52.626653 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6909 14:46:52.629496 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6910 14:46:52.633145 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6911 14:46:52.639225 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6912 14:46:52.643145 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6913 14:46:52.645870 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6914 14:46:52.649112 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6915 14:46:52.655604 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6916 14:46:52.655689 ==
6917 14:46:52.659740 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 14:46:52.663162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 14:46:52.663248 ==
6920 14:46:52.665502 DQS Delay:
6921 14:46:52.665584 DQS0 = 48, DQS1 = 52
6922 14:46:52.665648 DQM Delay:
6923 14:46:52.668703 DQM0 = 10, DQM1 = 10
6924 14:46:52.668787 DQ Delay:
6925 14:46:52.672193 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6926 14:46:52.675704 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6927 14:46:52.678435 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6928 14:46:52.682112 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6929 14:46:52.682193
6930 14:46:52.682257
6931 14:46:52.691774 [DQSOSCAuto] RK1, (LSB)MR18= 0x76ae, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6932 14:46:52.691864 CH1 RK1: MR19=C0C, MR18=76AE
6933 14:46:52.699096 CH1_RK1: MR19=0xC0C, MR18=0x76AE, DQSOSC=388, MR23=63, INC=392, DEC=261
6934 14:46:52.701455 [RxdqsGatingPostProcess] freq 400
6935 14:46:52.708705 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6936 14:46:52.711243 best DQS0 dly(2T, 0.5T) = (0, 10)
6937 14:46:52.715092 best DQS1 dly(2T, 0.5T) = (0, 10)
6938 14:46:52.718260 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6939 14:46:52.721446 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6940 14:46:52.724809 best DQS0 dly(2T, 0.5T) = (0, 10)
6941 14:46:52.728812 best DQS1 dly(2T, 0.5T) = (0, 10)
6942 14:46:52.731339 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6943 14:46:52.734986 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6944 14:46:52.735070 Pre-setting of DQS Precalculation
6945 14:46:52.741025 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6946 14:46:52.747521 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6947 14:46:52.754096 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6948 14:46:52.754183
6949 14:46:52.754267
6950 14:46:52.757781 [Calibration Summary] 800 Mbps
6951 14:46:52.760572 CH 0, Rank 0
6952 14:46:52.760653 SW Impedance : PASS
6953 14:46:52.764273 DUTY Scan : NO K
6954 14:46:52.767240 ZQ Calibration : PASS
6955 14:46:52.767344 Jitter Meter : NO K
6956 14:46:52.770632 CBT Training : PASS
6957 14:46:52.774090 Write leveling : PASS
6958 14:46:52.774171 RX DQS gating : PASS
6959 14:46:52.777571 RX DQ/DQS(RDDQC) : PASS
6960 14:46:52.780978 TX DQ/DQS : PASS
6961 14:46:52.781060 RX DATLAT : PASS
6962 14:46:52.784083 RX DQ/DQS(Engine): PASS
6963 14:46:52.787968 TX OE : NO K
6964 14:46:52.788074 All Pass.
6965 14:46:52.788153
6966 14:46:52.788237 CH 0, Rank 1
6967 14:46:52.790407 SW Impedance : PASS
6968 14:46:52.793624 DUTY Scan : NO K
6969 14:46:52.793705 ZQ Calibration : PASS
6970 14:46:52.796982 Jitter Meter : NO K
6971 14:46:52.797063 CBT Training : PASS
6972 14:46:52.800505 Write leveling : NO K
6973 14:46:52.804791 RX DQS gating : PASS
6974 14:46:52.804872 RX DQ/DQS(RDDQC) : PASS
6975 14:46:52.807078 TX DQ/DQS : PASS
6976 14:46:52.810530 RX DATLAT : PASS
6977 14:46:52.810610 RX DQ/DQS(Engine): PASS
6978 14:46:52.813441 TX OE : NO K
6979 14:46:52.813588 All Pass.
6980 14:46:52.813672
6981 14:46:52.817132 CH 1, Rank 0
6982 14:46:52.817214 SW Impedance : PASS
6983 14:46:52.820353 DUTY Scan : NO K
6984 14:46:52.823885 ZQ Calibration : PASS
6985 14:46:52.823967 Jitter Meter : NO K
6986 14:46:52.827466 CBT Training : PASS
6987 14:46:52.830421 Write leveling : PASS
6988 14:46:52.830504 RX DQS gating : PASS
6989 14:46:52.833435 RX DQ/DQS(RDDQC) : PASS
6990 14:46:52.836475 TX DQ/DQS : PASS
6991 14:46:52.836560 RX DATLAT : PASS
6992 14:46:52.839917 RX DQ/DQS(Engine): PASS
6993 14:46:52.843197 TX OE : NO K
6994 14:46:52.843281 All Pass.
6995 14:46:52.843365
6996 14:46:52.843445 CH 1, Rank 1
6997 14:46:52.847059 SW Impedance : PASS
6998 14:46:52.849584 DUTY Scan : NO K
6999 14:46:52.849667 ZQ Calibration : PASS
7000 14:46:52.853655 Jitter Meter : NO K
7001 14:46:52.856701 CBT Training : PASS
7002 14:46:52.856784 Write leveling : NO K
7003 14:46:52.859770 RX DQS gating : PASS
7004 14:46:52.862987 RX DQ/DQS(RDDQC) : PASS
7005 14:46:52.863068 TX DQ/DQS : PASS
7006 14:46:52.867088 RX DATLAT : PASS
7007 14:46:52.870157 RX DQ/DQS(Engine): PASS
7008 14:46:52.870238 TX OE : NO K
7009 14:46:52.870302 All Pass.
7010 14:46:52.872767
7011 14:46:52.872881 DramC Write-DBI off
7012 14:46:52.876035 PER_BANK_REFRESH: Hybrid Mode
7013 14:46:52.876109 TX_TRACKING: ON
7014 14:46:52.885982 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7015 14:46:52.889794 [FAST_K] Save calibration result to emmc
7016 14:46:52.892936 dramc_set_vcore_voltage set vcore to 725000
7017 14:46:52.895704 Read voltage for 1600, 0
7018 14:46:52.895775 Vio18 = 0
7019 14:46:52.899580 Vcore = 725000
7020 14:46:52.899659 Vdram = 0
7021 14:46:52.899719 Vddq = 0
7022 14:46:52.902744 Vmddr = 0
7023 14:46:52.906039 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7024 14:46:52.912824 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7025 14:46:52.912907 MEM_TYPE=3, freq_sel=13
7026 14:46:52.915581 sv_algorithm_assistance_LP4_3733
7027 14:46:52.922340 ============ PULL DRAM RESETB DOWN ============
7028 14:46:52.925238 ========== PULL DRAM RESETB DOWN end =========
7029 14:46:52.929008 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7030 14:46:52.931924 ===================================
7031 14:46:52.935333 LPDDR4 DRAM CONFIGURATION
7032 14:46:52.938874 ===================================
7033 14:46:52.941814 EX_ROW_EN[0] = 0x0
7034 14:46:52.941894 EX_ROW_EN[1] = 0x0
7035 14:46:52.945225 LP4Y_EN = 0x0
7036 14:46:52.945348 WORK_FSP = 0x1
7037 14:46:52.948427 WL = 0x5
7038 14:46:52.948495 RL = 0x5
7039 14:46:52.951565 BL = 0x2
7040 14:46:52.951635 RPST = 0x0
7041 14:46:52.955073 RD_PRE = 0x0
7042 14:46:52.955149 WR_PRE = 0x1
7043 14:46:52.958611 WR_PST = 0x1
7044 14:46:52.958679 DBI_WR = 0x0
7045 14:46:52.961997 DBI_RD = 0x0
7046 14:46:52.962079 OTF = 0x1
7047 14:46:52.964744 ===================================
7048 14:46:52.968075 ===================================
7049 14:46:52.971696 ANA top config
7050 14:46:52.975026 ===================================
7051 14:46:52.978279 DLL_ASYNC_EN = 0
7052 14:46:52.978353 ALL_SLAVE_EN = 0
7053 14:46:52.981752 NEW_RANK_MODE = 1
7054 14:46:52.984914 DLL_IDLE_MODE = 1
7055 14:46:52.987869 LP45_APHY_COMB_EN = 1
7056 14:46:52.991104 TX_ODT_DIS = 0
7057 14:46:52.991230 NEW_8X_MODE = 1
7058 14:46:52.994327 ===================================
7059 14:46:52.998180 ===================================
7060 14:46:53.001332 data_rate = 3200
7061 14:46:53.004711 CKR = 1
7062 14:46:53.007734 DQ_P2S_RATIO = 8
7063 14:46:53.010983 ===================================
7064 14:46:53.014241 CA_P2S_RATIO = 8
7065 14:46:53.017513 DQ_CA_OPEN = 0
7066 14:46:53.017593 DQ_SEMI_OPEN = 0
7067 14:46:53.021146 CA_SEMI_OPEN = 0
7068 14:46:53.024759 CA_FULL_RATE = 0
7069 14:46:53.027780 DQ_CKDIV4_EN = 0
7070 14:46:53.031106 CA_CKDIV4_EN = 0
7071 14:46:53.034260 CA_PREDIV_EN = 0
7072 14:46:53.034359 PH8_DLY = 12
7073 14:46:53.037368 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7074 14:46:53.040968 DQ_AAMCK_DIV = 4
7075 14:46:53.044312 CA_AAMCK_DIV = 4
7076 14:46:53.047299 CA_ADMCK_DIV = 4
7077 14:46:53.050557 DQ_TRACK_CA_EN = 0
7078 14:46:53.053669 CA_PICK = 1600
7079 14:46:53.053740 CA_MCKIO = 1600
7080 14:46:53.056981 MCKIO_SEMI = 0
7081 14:46:53.060421 PLL_FREQ = 3068
7082 14:46:53.063845 DQ_UI_PI_RATIO = 32
7083 14:46:53.067026 CA_UI_PI_RATIO = 0
7084 14:46:53.070422 ===================================
7085 14:46:53.073902 ===================================
7086 14:46:53.076744 memory_type:LPDDR4
7087 14:46:53.076847 GP_NUM : 10
7088 14:46:53.080072 SRAM_EN : 1
7089 14:46:53.080153 MD32_EN : 0
7090 14:46:53.083365 ===================================
7091 14:46:53.086661 [ANA_INIT] >>>>>>>>>>>>>>
7092 14:46:53.091050 <<<<<< [CONFIGURE PHASE]: ANA_TX
7093 14:46:53.093638 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7094 14:46:53.096517 ===================================
7095 14:46:53.100051 data_rate = 3200,PCW = 0X7600
7096 14:46:53.103099 ===================================
7097 14:46:53.106285 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7098 14:46:53.113128 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7099 14:46:53.117274 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7100 14:46:53.123222 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7101 14:46:53.126123 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7102 14:46:53.129416 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7103 14:46:53.132969 [ANA_INIT] flow start
7104 14:46:53.133141 [ANA_INIT] PLL >>>>>>>>
7105 14:46:53.136028 [ANA_INIT] PLL <<<<<<<<
7106 14:46:53.139461 [ANA_INIT] MIDPI >>>>>>>>
7107 14:46:53.139534 [ANA_INIT] MIDPI <<<<<<<<
7108 14:46:53.142711 [ANA_INIT] DLL >>>>>>>>
7109 14:46:53.145873 [ANA_INIT] DLL <<<<<<<<
7110 14:46:53.145971 [ANA_INIT] flow end
7111 14:46:53.152501 ============ LP4 DIFF to SE enter ============
7112 14:46:53.155790 ============ LP4 DIFF to SE exit ============
7113 14:46:53.159170 [ANA_INIT] <<<<<<<<<<<<<
7114 14:46:53.159278 [Flow] Enable top DCM control >>>>>
7115 14:46:53.162529 [Flow] Enable top DCM control <<<<<
7116 14:46:53.165466 Enable DLL master slave shuffle
7117 14:46:53.172020 ==============================================================
7118 14:46:53.175665 Gating Mode config
7119 14:46:53.178673 ==============================================================
7120 14:46:53.182387 Config description:
7121 14:46:53.191681 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7122 14:46:53.198353 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7123 14:46:53.201832 SELPH_MODE 0: By rank 1: By Phase
7124 14:46:53.208219 ==============================================================
7125 14:46:53.211890 GAT_TRACK_EN = 1
7126 14:46:53.215302 RX_GATING_MODE = 2
7127 14:46:53.218307 RX_GATING_TRACK_MODE = 2
7128 14:46:53.221634 SELPH_MODE = 1
7129 14:46:53.224983 PICG_EARLY_EN = 1
7130 14:46:53.225130 VALID_LAT_VALUE = 1
7131 14:46:53.231769 ==============================================================
7132 14:46:53.235307 Enter into Gating configuration >>>>
7133 14:46:53.238136 Exit from Gating configuration <<<<
7134 14:46:53.241849 Enter into DVFS_PRE_config >>>>>
7135 14:46:53.251378 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7136 14:46:53.254550 Exit from DVFS_PRE_config <<<<<
7137 14:46:53.257752 Enter into PICG configuration >>>>
7138 14:46:53.260954 Exit from PICG configuration <<<<
7139 14:46:53.264425 [RX_INPUT] configuration >>>>>
7140 14:46:53.267631 [RX_INPUT] configuration <<<<<
7141 14:46:53.274158 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7142 14:46:53.277371 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7143 14:46:53.283920 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7144 14:46:53.290811 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7145 14:46:53.297051 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7146 14:46:53.303616 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7147 14:46:53.306925 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7148 14:46:53.310179 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7149 14:46:53.313806 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7150 14:46:53.320169 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7151 14:46:53.324787 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7152 14:46:53.326944 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7153 14:46:53.330176 ===================================
7154 14:46:53.333914 LPDDR4 DRAM CONFIGURATION
7155 14:46:53.337130 ===================================
7156 14:46:53.340243 EX_ROW_EN[0] = 0x0
7157 14:46:53.340323 EX_ROW_EN[1] = 0x0
7158 14:46:53.343201 LP4Y_EN = 0x0
7159 14:46:53.343279 WORK_FSP = 0x1
7160 14:46:53.346580 WL = 0x5
7161 14:46:53.346686 RL = 0x5
7162 14:46:53.350681 BL = 0x2
7163 14:46:53.350761 RPST = 0x0
7164 14:46:53.353217 RD_PRE = 0x0
7165 14:46:53.353330 WR_PRE = 0x1
7166 14:46:53.356737 WR_PST = 0x1
7167 14:46:53.356892 DBI_WR = 0x0
7168 14:46:53.359819 DBI_RD = 0x0
7169 14:46:53.363288 OTF = 0x1
7170 14:46:53.366232 ===================================
7171 14:46:53.370149 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7172 14:46:53.372850 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7173 14:46:53.376536 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7174 14:46:53.379759 ===================================
7175 14:46:53.383055 LPDDR4 DRAM CONFIGURATION
7176 14:46:53.386421 ===================================
7177 14:46:53.389377 EX_ROW_EN[0] = 0x10
7178 14:46:53.389461 EX_ROW_EN[1] = 0x0
7179 14:46:53.393364 LP4Y_EN = 0x0
7180 14:46:53.393450 WORK_FSP = 0x1
7181 14:46:53.396223 WL = 0x5
7182 14:46:53.396328 RL = 0x5
7183 14:46:53.399190 BL = 0x2
7184 14:46:53.399284 RPST = 0x0
7185 14:46:53.402568 RD_PRE = 0x0
7186 14:46:53.402651 WR_PRE = 0x1
7187 14:46:53.405803 WR_PST = 0x1
7188 14:46:53.405874 DBI_WR = 0x0
7189 14:46:53.408949 DBI_RD = 0x0
7190 14:46:53.412186 OTF = 0x1
7191 14:46:53.415773 ===================================
7192 14:46:53.419228 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7193 14:46:53.419301 ==
7194 14:46:53.422435 Dram Type= 6, Freq= 0, CH_0, rank 0
7195 14:46:53.428927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7196 14:46:53.429021 ==
7197 14:46:53.432304 [Duty_Offset_Calibration]
7198 14:46:53.432402 B0:2 B1:0 CA:4
7199 14:46:53.432498
7200 14:46:53.435590 [DutyScan_Calibration_Flow] k_type=0
7201 14:46:53.444344
7202 14:46:53.444426 ==CLK 0==
7203 14:46:53.447718 Final CLK duty delay cell = -4
7204 14:46:53.451514 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7205 14:46:53.454554 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7206 14:46:53.457947 [-4] AVG Duty = 4922%(X100)
7207 14:46:53.458027
7208 14:46:53.460912 CH0 CLK Duty spec in!! Max-Min= 218%
7209 14:46:53.464297 [DutyScan_Calibration_Flow] ====Done====
7210 14:46:53.464374
7211 14:46:53.467337 [DutyScan_Calibration_Flow] k_type=1
7212 14:46:53.485254
7213 14:46:53.485362 ==DQS 0 ==
7214 14:46:53.488205 Final DQS duty delay cell = 0
7215 14:46:53.492108 [0] MAX Duty = 5218%(X100), DQS PI = 38
7216 14:46:53.494517 [0] MIN Duty = 5093%(X100), DQS PI = 6
7217 14:46:53.497744 [0] AVG Duty = 5155%(X100)
7218 14:46:53.497829
7219 14:46:53.497891 ==DQS 1 ==
7220 14:46:53.502244 Final DQS duty delay cell = 0
7221 14:46:53.504326 [0] MAX Duty = 5156%(X100), DQS PI = 2
7222 14:46:53.507998 [0] MIN Duty = 4969%(X100), DQS PI = 10
7223 14:46:53.511031 [0] AVG Duty = 5062%(X100)
7224 14:46:53.511101
7225 14:46:53.514328 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7226 14:46:53.514405
7227 14:46:53.517478 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7228 14:46:53.521169 [DutyScan_Calibration_Flow] ====Done====
7229 14:46:53.521310
7230 14:46:53.524084 [DutyScan_Calibration_Flow] k_type=3
7231 14:46:53.541598
7232 14:46:53.541678 ==DQM 0 ==
7233 14:46:53.545801 Final DQM duty delay cell = 0
7234 14:46:53.548064 [0] MAX Duty = 5124%(X100), DQS PI = 22
7235 14:46:53.551980 [0] MIN Duty = 4844%(X100), DQS PI = 54
7236 14:46:53.554910 [0] AVG Duty = 4984%(X100)
7237 14:46:53.554993
7238 14:46:53.555054 ==DQM 1 ==
7239 14:46:53.557980 Final DQM duty delay cell = 0
7240 14:46:53.561292 [0] MAX Duty = 4969%(X100), DQS PI = 0
7241 14:46:53.565007 [0] MIN Duty = 4813%(X100), DQS PI = 16
7242 14:46:53.567915 [0] AVG Duty = 4891%(X100)
7243 14:46:53.567989
7244 14:46:53.571315 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7245 14:46:53.571387
7246 14:46:53.574496 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7247 14:46:53.577620 [DutyScan_Calibration_Flow] ====Done====
7248 14:46:53.577704
7249 14:46:53.581104 [DutyScan_Calibration_Flow] k_type=2
7250 14:46:53.598946
7251 14:46:53.599040 ==DQ 0 ==
7252 14:46:53.602313 Final DQ duty delay cell = 0
7253 14:46:53.605546 [0] MAX Duty = 5125%(X100), DQS PI = 28
7254 14:46:53.609546 [0] MIN Duty = 4938%(X100), DQS PI = 12
7255 14:46:53.612406 [0] AVG Duty = 5031%(X100)
7256 14:46:53.612478
7257 14:46:53.612538 ==DQ 1 ==
7258 14:46:53.615720 Final DQ duty delay cell = 0
7259 14:46:53.618406 [0] MAX Duty = 5187%(X100), DQS PI = 2
7260 14:46:53.621698 [0] MIN Duty = 4907%(X100), DQS PI = 34
7261 14:46:53.621769 [0] AVG Duty = 5047%(X100)
7262 14:46:53.625143
7263 14:46:53.628223 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7264 14:46:53.628295
7265 14:46:53.631548 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7266 14:46:53.635348 [DutyScan_Calibration_Flow] ====Done====
7267 14:46:53.635425 ==
7268 14:46:53.638176 Dram Type= 6, Freq= 0, CH_1, rank 0
7269 14:46:53.641675 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7270 14:46:53.641746 ==
7271 14:46:53.645006 [Duty_Offset_Calibration]
7272 14:46:53.645081 B0:0 B1:-1 CA:3
7273 14:46:53.645140
7274 14:46:53.648422 [DutyScan_Calibration_Flow] k_type=0
7275 14:46:53.659176
7276 14:46:53.659258 ==CLK 0==
7277 14:46:53.661499 Final CLK duty delay cell = -4
7278 14:46:53.665705 [-4] MAX Duty = 5062%(X100), DQS PI = 36
7279 14:46:53.668038 [-4] MIN Duty = 4813%(X100), DQS PI = 4
7280 14:46:53.671302 [-4] AVG Duty = 4937%(X100)
7281 14:46:53.671406
7282 14:46:53.675009 CH1 CLK Duty spec in!! Max-Min= 249%
7283 14:46:53.678126 [DutyScan_Calibration_Flow] ====Done====
7284 14:46:53.678221
7285 14:46:53.681101 [DutyScan_Calibration_Flow] k_type=1
7286 14:46:53.697436
7287 14:46:53.697547 ==DQS 0 ==
7288 14:46:53.700854 Final DQS duty delay cell = 0
7289 14:46:53.704940 [0] MAX Duty = 5187%(X100), DQS PI = 60
7290 14:46:53.707546 [0] MIN Duty = 4938%(X100), DQS PI = 8
7291 14:46:53.707642 [0] AVG Duty = 5062%(X100)
7292 14:46:53.711057
7293 14:46:53.711154 ==DQS 1 ==
7294 14:46:53.713914 Final DQS duty delay cell = -4
7295 14:46:53.717546 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7296 14:46:53.720807 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7297 14:46:53.724816 [-4] AVG Duty = 4922%(X100)
7298 14:46:53.724897
7299 14:46:53.726918 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7300 14:46:53.726999
7301 14:46:53.730891 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7302 14:46:53.733972 [DutyScan_Calibration_Flow] ====Done====
7303 14:46:53.734052
7304 14:46:53.737283 [DutyScan_Calibration_Flow] k_type=3
7305 14:46:53.754797
7306 14:46:53.754884 ==DQM 0 ==
7307 14:46:53.758064 Final DQM duty delay cell = 0
7308 14:46:53.761559 [0] MAX Duty = 5031%(X100), DQS PI = 62
7309 14:46:53.764551 [0] MIN Duty = 4750%(X100), DQS PI = 8
7310 14:46:53.767967 [0] AVG Duty = 4890%(X100)
7311 14:46:53.768051
7312 14:46:53.768115 ==DQM 1 ==
7313 14:46:53.771063 Final DQM duty delay cell = 0
7314 14:46:53.774239 [0] MAX Duty = 4969%(X100), DQS PI = 0
7315 14:46:53.777789 [0] MIN Duty = 4844%(X100), DQS PI = 28
7316 14:46:53.781082 [0] AVG Duty = 4906%(X100)
7317 14:46:53.781157
7318 14:46:53.784521 CH1 DQM 0 Duty spec in!! Max-Min= 281%
7319 14:46:53.784594
7320 14:46:53.787463 CH1 DQM 1 Duty spec in!! Max-Min= 125%
7321 14:46:53.790916 [DutyScan_Calibration_Flow] ====Done====
7322 14:46:53.790994
7323 14:46:53.794147 [DutyScan_Calibration_Flow] k_type=2
7324 14:46:53.811494
7325 14:46:53.811640 ==DQ 0 ==
7326 14:46:53.815271 Final DQ duty delay cell = 0
7327 14:46:53.818492 [0] MAX Duty = 5187%(X100), DQS PI = 0
7328 14:46:53.821470 [0] MIN Duty = 5000%(X100), DQS PI = 6
7329 14:46:53.821595 [0] AVG Duty = 5093%(X100)
7330 14:46:53.821685
7331 14:46:53.824582 ==DQ 1 ==
7332 14:46:53.827967 Final DQ duty delay cell = 0
7333 14:46:53.831217 [0] MAX Duty = 5031%(X100), DQS PI = 14
7334 14:46:53.835047 [0] MIN Duty = 4844%(X100), DQS PI = 28
7335 14:46:53.835145 [0] AVG Duty = 4937%(X100)
7336 14:46:53.835220
7337 14:46:53.838001 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7338 14:46:53.841017
7339 14:46:53.844313 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7340 14:46:53.847697 [DutyScan_Calibration_Flow] ====Done====
7341 14:46:53.850821 nWR fixed to 30
7342 14:46:53.850912 [ModeRegInit_LP4] CH0 RK0
7343 14:46:53.854572 [ModeRegInit_LP4] CH0 RK1
7344 14:46:53.857599 [ModeRegInit_LP4] CH1 RK0
7345 14:46:53.861057 [ModeRegInit_LP4] CH1 RK1
7346 14:46:53.861149 match AC timing 5
7347 14:46:53.867649 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7348 14:46:53.870803 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7349 14:46:53.874483 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7350 14:46:53.880428 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7351 14:46:53.884144 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7352 14:46:53.884250 [MiockJmeterHQA]
7353 14:46:53.884312
7354 14:46:53.887041 [DramcMiockJmeter] u1RxGatingPI = 0
7355 14:46:53.890995 0 : 4257, 4029
7356 14:46:53.891095 4 : 4363, 4137
7357 14:46:53.893686 8 : 4252, 4027
7358 14:46:53.893771 12 : 4253, 4027
7359 14:46:53.896913 16 : 4257, 4031
7360 14:46:53.897023 20 : 4257, 4029
7361 14:46:53.897113 24 : 4368, 4137
7362 14:46:53.900420 28 : 4369, 4137
7363 14:46:53.900500 32 : 4253, 4027
7364 14:46:53.903653 36 : 4257, 4029
7365 14:46:53.903725 40 : 4258, 4029
7366 14:46:53.907111 44 : 4363, 4137
7367 14:46:53.907189 48 : 4252, 4027
7368 14:46:53.910611 52 : 4364, 4137
7369 14:46:53.910693 56 : 4253, 4026
7370 14:46:53.910754 60 : 4250, 4027
7371 14:46:53.913678 64 : 4252, 4027
7372 14:46:53.913787 68 : 4253, 4029
7373 14:46:53.916843 72 : 4250, 4027
7374 14:46:53.916939 76 : 4363, 4137
7375 14:46:53.921297 80 : 4361, 4137
7376 14:46:53.921425 84 : 4250, 4026
7377 14:46:53.923476 88 : 4252, 4029
7378 14:46:53.923553 92 : 4250, 4027
7379 14:46:53.923615 96 : 4250, 2633
7380 14:46:53.926895 100 : 4254, 0
7381 14:46:53.926967 104 : 4361, 0
7382 14:46:53.930079 108 : 4253, 0
7383 14:46:53.930162 112 : 4360, 0
7384 14:46:53.930237 116 : 4250, 0
7385 14:46:53.933341 120 : 4250, 0
7386 14:46:53.933412 124 : 4366, 0
7387 14:46:53.937581 128 : 4250, 0
7388 14:46:53.937656 132 : 4250, 0
7389 14:46:53.937718 136 : 4249, 0
7390 14:46:53.939791 140 : 4250, 0
7391 14:46:53.939870 144 : 4250, 0
7392 14:46:53.943307 148 : 4249, 0
7393 14:46:53.943425 152 : 4253, 0
7394 14:46:53.943507 156 : 4363, 0
7395 14:46:53.946447 160 : 4361, 0
7396 14:46:53.946518 164 : 4363, 0
7397 14:46:53.946585 168 : 4250, 0
7398 14:46:53.949612 172 : 4250, 0
7399 14:46:53.949689 176 : 4255, 0
7400 14:46:53.952971 180 : 4250, 0
7401 14:46:53.953061 184 : 4250, 0
7402 14:46:53.953159 188 : 4255, 0
7403 14:46:53.956257 192 : 4255, 0
7404 14:46:53.956333 196 : 4250, 0
7405 14:46:53.960150 200 : 4250, 0
7406 14:46:53.960229 204 : 4250, 0
7407 14:46:53.960289 208 : 4250, 0
7408 14:46:53.963032 212 : 4361, 0
7409 14:46:53.963108 216 : 4360, 0
7410 14:46:53.966335 220 : 4250, 486
7411 14:46:53.966410 224 : 4250, 4014
7412 14:46:53.969657 228 : 4361, 4137
7413 14:46:53.969743 232 : 4365, 4139
7414 14:46:53.972623 236 : 4250, 4027
7415 14:46:53.972694 240 : 4361, 4137
7416 14:46:53.972753 244 : 4360, 4138
7417 14:46:53.976308 248 : 4250, 4026
7418 14:46:53.976379 252 : 4250, 4027
7419 14:46:53.979612 256 : 4250, 4026
7420 14:46:53.979695 260 : 4250, 4026
7421 14:46:53.983060 264 : 4250, 4027
7422 14:46:53.983142 268 : 4250, 4027
7423 14:46:53.986150 272 : 4250, 4026
7424 14:46:53.986236 276 : 4250, 4027
7425 14:46:53.989535 280 : 4361, 4138
7426 14:46:53.989617 284 : 4361, 4137
7427 14:46:53.992539 288 : 4250, 4026
7428 14:46:53.992657 292 : 4365, 4142
7429 14:46:53.996156 296 : 4250, 4027
7430 14:46:53.996357 300 : 4250, 4026
7431 14:46:53.999167 304 : 4250, 4027
7432 14:46:53.999270 308 : 4252, 4029
7433 14:46:53.999371 312 : 4250, 4027
7434 14:46:54.002640 316 : 4250, 4027
7435 14:46:54.002750 320 : 4250, 4027
7436 14:46:54.005414 324 : 4252, 4029
7437 14:46:54.005535 328 : 4250, 4027
7438 14:46:54.008944 332 : 4361, 3992
7439 14:46:54.009050 336 : 4361, 1561
7440 14:46:54.009165
7441 14:46:54.012370 MIOCK jitter meter ch=0
7442 14:46:54.012450
7443 14:46:54.015572 1T = (336-100) = 236 dly cells
7444 14:46:54.022421 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7445 14:46:54.022503 ==
7446 14:46:54.025448 Dram Type= 6, Freq= 0, CH_0, rank 0
7447 14:46:54.028885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7448 14:46:54.028977 ==
7449 14:46:54.035475 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7450 14:46:54.038512 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7451 14:46:54.043069 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7452 14:46:54.048436 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7453 14:46:54.057703 [CA 0] Center 43 (13~73) winsize 61
7454 14:46:54.061120 [CA 1] Center 43 (13~73) winsize 61
7455 14:46:54.064017 [CA 2] Center 38 (9~67) winsize 59
7456 14:46:54.067857 [CA 3] Center 37 (7~67) winsize 61
7457 14:46:54.071008 [CA 4] Center 35 (6~65) winsize 60
7458 14:46:54.074198 [CA 5] Center 35 (5~66) winsize 62
7459 14:46:54.074285
7460 14:46:54.077248 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7461 14:46:54.077359
7462 14:46:54.083818 [CATrainingPosCal] consider 1 rank data
7463 14:46:54.083905 u2DelayCellTimex100 = 275/100 ps
7464 14:46:54.091904 CA0 delay=43 (13~73),Diff = 8 PI (28 cell)
7465 14:46:54.093704 CA1 delay=43 (13~73),Diff = 8 PI (28 cell)
7466 14:46:54.096898 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7467 14:46:54.100436 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7468 14:46:54.103837 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7469 14:46:54.106965 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7470 14:46:54.107044
7471 14:46:54.110269 CA PerBit enable=1, Macro0, CA PI delay=35
7472 14:46:54.110344
7473 14:46:54.114018 [CBTSetCACLKResult] CA Dly = 35
7474 14:46:54.117045 CS Dly: 10 (0~41)
7475 14:46:54.119758 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7476 14:46:54.123418 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7477 14:46:54.123503 ==
7478 14:46:54.126490 Dram Type= 6, Freq= 0, CH_0, rank 1
7479 14:46:54.133213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7480 14:46:54.133330 ==
7481 14:46:54.136457 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7482 14:46:54.143354 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7483 14:46:54.146478 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7484 14:46:54.153109 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7485 14:46:54.161756 [CA 0] Center 44 (14~74) winsize 61
7486 14:46:54.164585 [CA 1] Center 44 (14~74) winsize 61
7487 14:46:54.167656 [CA 2] Center 39 (9~69) winsize 61
7488 14:46:54.171281 [CA 3] Center 38 (9~68) winsize 60
7489 14:46:54.174193 [CA 4] Center 37 (7~67) winsize 61
7490 14:46:54.177902 [CA 5] Center 36 (6~66) winsize 61
7491 14:46:54.177981
7492 14:46:54.180771 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7493 14:46:54.180849
7494 14:46:54.184397 [CATrainingPosCal] consider 2 rank data
7495 14:46:54.187581 u2DelayCellTimex100 = 275/100 ps
7496 14:46:54.191023 CA0 delay=43 (14~73),Diff = 7 PI (24 cell)
7497 14:46:54.197733 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7498 14:46:54.200977 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
7499 14:46:54.203971 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7500 14:46:54.207252 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7501 14:46:54.210604 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7502 14:46:54.210675
7503 14:46:54.213990 CA PerBit enable=1, Macro0, CA PI delay=36
7504 14:46:54.214071
7505 14:46:54.217183 [CBTSetCACLKResult] CA Dly = 36
7506 14:46:54.220219 CS Dly: 11 (0~44)
7507 14:46:54.224304 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7508 14:46:54.227012 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7509 14:46:54.227094
7510 14:46:54.230212 ----->DramcWriteLeveling(PI) begin...
7511 14:46:54.230289 ==
7512 14:46:54.233704 Dram Type= 6, Freq= 0, CH_0, rank 0
7513 14:46:54.240593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7514 14:46:54.240669 ==
7515 14:46:54.243758 Write leveling (Byte 0): 34 => 34
7516 14:46:54.246833 Write leveling (Byte 1): 24 => 24
7517 14:46:54.246913 DramcWriteLeveling(PI) end<-----
7518 14:46:54.249937
7519 14:46:54.250006 ==
7520 14:46:54.253219 Dram Type= 6, Freq= 0, CH_0, rank 0
7521 14:46:54.257100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7522 14:46:54.257187 ==
7523 14:46:54.260391 [Gating] SW mode calibration
7524 14:46:54.266704 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7525 14:46:54.270112 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7526 14:46:54.276408 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7527 14:46:54.279527 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7528 14:46:54.286460 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7529 14:46:54.289676 1 4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
7530 14:46:54.292995 1 4 16 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
7531 14:46:54.300159 1 4 20 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
7532 14:46:54.302852 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7533 14:46:54.306128 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7534 14:46:54.312670 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7535 14:46:54.316011 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7536 14:46:54.320029 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7537 14:46:54.325678 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
7538 14:46:54.328893 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7539 14:46:54.332799 1 5 20 | B1->B0 | 2b2b 2323 | 1 0 | (1 1) (0 0)
7540 14:46:54.338643 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7541 14:46:54.342662 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7542 14:46:54.346207 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7543 14:46:54.352008 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7544 14:46:54.355568 1 6 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7545 14:46:54.358463 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
7546 14:46:54.365079 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7547 14:46:54.368534 1 6 20 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
7548 14:46:54.372178 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7549 14:46:54.378747 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7550 14:46:54.381779 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7551 14:46:54.384878 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7552 14:46:54.391462 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7553 14:46:54.395175 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7554 14:46:54.398642 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7555 14:46:54.405229 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7556 14:46:54.408175 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7557 14:46:54.411638 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7558 14:46:54.417717 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7559 14:46:54.421663 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7560 14:46:54.424444 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7561 14:46:54.431430 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7562 14:46:54.434102 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7563 14:46:54.437451 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7564 14:46:54.444036 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7565 14:46:54.447641 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7566 14:46:54.450724 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7567 14:46:54.457385 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 14:46:54.461458 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 14:46:54.464247 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7570 14:46:54.467189 Total UI for P1: 0, mck2ui 16
7571 14:46:54.471659 best dqsien dly found for B0: ( 1, 9, 10)
7572 14:46:54.477197 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7573 14:46:54.480499 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7574 14:46:54.483740 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 14:46:54.486919 Total UI for P1: 0, mck2ui 16
7576 14:46:54.490707 best dqsien dly found for B1: ( 1, 9, 20)
7577 14:46:54.493522 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7578 14:46:54.496927 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7579 14:46:54.497031
7580 14:46:54.503710 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7581 14:46:54.507361 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7582 14:46:54.507449 [Gating] SW calibration Done
7583 14:46:54.509857 ==
7584 14:46:54.513252 Dram Type= 6, Freq= 0, CH_0, rank 0
7585 14:46:54.517098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7586 14:46:54.517219 ==
7587 14:46:54.517347 RX Vref Scan: 0
7588 14:46:54.517431
7589 14:46:54.520034 RX Vref 0 -> 0, step: 1
7590 14:46:54.520136
7591 14:46:54.523105 RX Delay 0 -> 252, step: 8
7592 14:46:54.526527 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7593 14:46:54.530129 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7594 14:46:54.538254 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7595 14:46:54.539682 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7596 14:46:54.542829 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7597 14:46:54.546355 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7598 14:46:54.549287 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7599 14:46:54.556104 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7600 14:46:54.559503 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7601 14:46:54.562912 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
7602 14:46:54.566024 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7603 14:46:54.569390 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7604 14:46:54.575880 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7605 14:46:54.579260 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7606 14:46:54.582628 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7607 14:46:54.586373 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7608 14:46:54.586458 ==
7609 14:46:54.588698 Dram Type= 6, Freq= 0, CH_0, rank 0
7610 14:46:54.595326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7611 14:46:54.595435 ==
7612 14:46:54.595520 DQS Delay:
7613 14:46:54.598993 DQS0 = 0, DQS1 = 0
7614 14:46:54.599107 DQM Delay:
7615 14:46:54.602165 DQM0 = 131, DQM1 = 127
7616 14:46:54.602250 DQ Delay:
7617 14:46:54.605251 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7618 14:46:54.608488 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7619 14:46:54.611994 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
7620 14:46:54.615055 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7621 14:46:54.615144
7622 14:46:54.615208
7623 14:46:54.615266 ==
7624 14:46:54.618278 Dram Type= 6, Freq= 0, CH_0, rank 0
7625 14:46:54.625102 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7626 14:46:54.625212 ==
7627 14:46:54.625333
7628 14:46:54.625393
7629 14:46:54.625448 TX Vref Scan disable
7630 14:46:54.629279 == TX Byte 0 ==
7631 14:46:54.632227 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7632 14:46:54.638700 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7633 14:46:54.638787 == TX Byte 1 ==
7634 14:46:54.642274 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7635 14:46:54.648689 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7636 14:46:54.648776 ==
7637 14:46:54.651742 Dram Type= 6, Freq= 0, CH_0, rank 0
7638 14:46:54.655046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7639 14:46:54.655130 ==
7640 14:46:54.669519
7641 14:46:54.672461 TX Vref early break, caculate TX vref
7642 14:46:54.675172 TX Vref=16, minBit 10, minWin=21, winSum=367
7643 14:46:54.678394 TX Vref=18, minBit 6, minWin=23, winSum=379
7644 14:46:54.681781 TX Vref=20, minBit 3, minWin=23, winSum=387
7645 14:46:54.685314 TX Vref=22, minBit 1, minWin=24, winSum=399
7646 14:46:54.691704 TX Vref=24, minBit 0, minWin=25, winSum=408
7647 14:46:54.694914 TX Vref=26, minBit 1, minWin=25, winSum=408
7648 14:46:54.698538 TX Vref=28, minBit 2, minWin=25, winSum=417
7649 14:46:54.701283 TX Vref=30, minBit 2, minWin=25, winSum=413
7650 14:46:54.704928 TX Vref=32, minBit 1, minWin=24, winSum=403
7651 14:46:54.708525 TX Vref=34, minBit 0, minWin=24, winSum=393
7652 14:46:54.715081 [TxChooseVref] Worse bit 2, Min win 25, Win sum 417, Final Vref 28
7653 14:46:54.715164
7654 14:46:54.718423 Final TX Range 0 Vref 28
7655 14:46:54.718541
7656 14:46:54.718633 ==
7657 14:46:54.721567 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 14:46:54.724759 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 14:46:54.724866 ==
7660 14:46:54.724955
7661 14:46:54.725047
7662 14:46:54.728234 TX Vref Scan disable
7663 14:46:54.734816 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7664 14:46:54.734909 == TX Byte 0 ==
7665 14:46:54.737850 u2DelayCellOfst[0]=14 cells (4 PI)
7666 14:46:54.740743 u2DelayCellOfst[1]=17 cells (5 PI)
7667 14:46:54.744212 u2DelayCellOfst[2]=10 cells (3 PI)
7668 14:46:54.747581 u2DelayCellOfst[3]=10 cells (3 PI)
7669 14:46:54.751232 u2DelayCellOfst[4]=10 cells (3 PI)
7670 14:46:54.754256 u2DelayCellOfst[5]=0 cells (0 PI)
7671 14:46:54.757832 u2DelayCellOfst[6]=17 cells (5 PI)
7672 14:46:54.760949 u2DelayCellOfst[7]=17 cells (5 PI)
7673 14:46:54.764457 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7674 14:46:54.767272 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7675 14:46:54.770607 == TX Byte 1 ==
7676 14:46:54.775644 u2DelayCellOfst[8]=0 cells (0 PI)
7677 14:46:54.777198 u2DelayCellOfst[9]=0 cells (0 PI)
7678 14:46:54.780639 u2DelayCellOfst[10]=3 cells (1 PI)
7679 14:46:54.784395 u2DelayCellOfst[11]=0 cells (0 PI)
7680 14:46:54.784505 u2DelayCellOfst[12]=7 cells (2 PI)
7681 14:46:54.787056 u2DelayCellOfst[13]=7 cells (2 PI)
7682 14:46:54.791011 u2DelayCellOfst[14]=14 cells (4 PI)
7683 14:46:54.793660 u2DelayCellOfst[15]=7 cells (2 PI)
7684 14:46:54.800206 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7685 14:46:54.803933 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7686 14:46:54.804017 DramC Write-DBI on
7687 14:46:54.806922 ==
7688 14:46:54.807006 Dram Type= 6, Freq= 0, CH_0, rank 0
7689 14:46:54.813533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7690 14:46:54.813631 ==
7691 14:46:54.813707
7692 14:46:54.813777
7693 14:46:54.816666 TX Vref Scan disable
7694 14:46:54.816742 == TX Byte 0 ==
7695 14:46:54.824019 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7696 14:46:54.824151 == TX Byte 1 ==
7697 14:46:54.826498 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7698 14:46:54.829812 DramC Write-DBI off
7699 14:46:54.829907
7700 14:46:54.829971 [DATLAT]
7701 14:46:54.833119 Freq=1600, CH0 RK0
7702 14:46:54.833219
7703 14:46:54.833347 DATLAT Default: 0xf
7704 14:46:54.836672 0, 0xFFFF, sum = 0
7705 14:46:54.836748 1, 0xFFFF, sum = 0
7706 14:46:54.839698 2, 0xFFFF, sum = 0
7707 14:46:54.839771 3, 0xFFFF, sum = 0
7708 14:46:54.843242 4, 0xFFFF, sum = 0
7709 14:46:54.846531 5, 0xFFFF, sum = 0
7710 14:46:54.846618 6, 0xFFFF, sum = 0
7711 14:46:54.849706 7, 0xFFFF, sum = 0
7712 14:46:54.849789 8, 0xFFFF, sum = 0
7713 14:46:54.852851 9, 0xFFFF, sum = 0
7714 14:46:54.852925 10, 0xFFFF, sum = 0
7715 14:46:54.856529 11, 0xFFFF, sum = 0
7716 14:46:54.856607 12, 0xFFFF, sum = 0
7717 14:46:54.859965 13, 0xFFFF, sum = 0
7718 14:46:54.860050 14, 0x0, sum = 1
7719 14:46:54.862821 15, 0x0, sum = 2
7720 14:46:54.862900 16, 0x0, sum = 3
7721 14:46:54.866038 17, 0x0, sum = 4
7722 14:46:54.866107 best_step = 15
7723 14:46:54.866168
7724 14:46:54.866224 ==
7725 14:46:54.869970 Dram Type= 6, Freq= 0, CH_0, rank 0
7726 14:46:54.875966 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7727 14:46:54.876044 ==
7728 14:46:54.876106 RX Vref Scan: 1
7729 14:46:54.876166
7730 14:46:54.879483 Set Vref Range= 24 -> 127
7731 14:46:54.879548
7732 14:46:54.882666 RX Vref 24 -> 127, step: 1
7733 14:46:54.882731
7734 14:46:54.882787 RX Delay 19 -> 252, step: 4
7735 14:46:54.882843
7736 14:46:54.885925 Set Vref, RX VrefLevel [Byte0]: 24
7737 14:46:54.889579 [Byte1]: 24
7738 14:46:54.893579
7739 14:46:54.893671 Set Vref, RX VrefLevel [Byte0]: 25
7740 14:46:54.897068 [Byte1]: 25
7741 14:46:54.901206
7742 14:46:54.901321 Set Vref, RX VrefLevel [Byte0]: 26
7743 14:46:54.904172 [Byte1]: 26
7744 14:46:54.908220
7745 14:46:54.908294 Set Vref, RX VrefLevel [Byte0]: 27
7746 14:46:54.915465 [Byte1]: 27
7747 14:46:54.915549
7748 14:46:54.918054 Set Vref, RX VrefLevel [Byte0]: 28
7749 14:46:54.922033 [Byte1]: 28
7750 14:46:54.922109
7751 14:46:54.925439 Set Vref, RX VrefLevel [Byte0]: 29
7752 14:46:54.928605 [Byte1]: 29
7753 14:46:54.928674
7754 14:46:54.931232 Set Vref, RX VrefLevel [Byte0]: 30
7755 14:46:54.937903 [Byte1]: 30
7756 14:46:54.938764
7757 14:46:54.938829 Set Vref, RX VrefLevel [Byte0]: 31
7758 14:46:54.942271 [Byte1]: 31
7759 14:46:54.946113
7760 14:46:54.946181 Set Vref, RX VrefLevel [Byte0]: 32
7761 14:46:54.949485 [Byte1]: 32
7762 14:46:54.954196
7763 14:46:54.954274 Set Vref, RX VrefLevel [Byte0]: 33
7764 14:46:54.957736 [Byte1]: 33
7765 14:46:54.961600
7766 14:46:54.961671 Set Vref, RX VrefLevel [Byte0]: 34
7767 14:46:54.964397 [Byte1]: 34
7768 14:46:54.969048
7769 14:46:54.969123 Set Vref, RX VrefLevel [Byte0]: 35
7770 14:46:54.972385 [Byte1]: 35
7771 14:46:54.976410
7772 14:46:54.976491 Set Vref, RX VrefLevel [Byte0]: 36
7773 14:46:54.979976 [Byte1]: 36
7774 14:46:54.984025
7775 14:46:54.984098 Set Vref, RX VrefLevel [Byte0]: 37
7776 14:46:54.987284 [Byte1]: 37
7777 14:46:54.991745
7778 14:46:54.991841 Set Vref, RX VrefLevel [Byte0]: 38
7779 14:46:54.994762 [Byte1]: 38
7780 14:46:55.000044
7781 14:46:55.000120 Set Vref, RX VrefLevel [Byte0]: 39
7782 14:46:55.002461 [Byte1]: 39
7783 14:46:55.007191
7784 14:46:55.007262 Set Vref, RX VrefLevel [Byte0]: 40
7785 14:46:55.013470 [Byte1]: 40
7786 14:46:55.013547
7787 14:46:55.016381 Set Vref, RX VrefLevel [Byte0]: 41
7788 14:46:55.020054 [Byte1]: 41
7789 14:46:55.020127
7790 14:46:55.023074 Set Vref, RX VrefLevel [Byte0]: 42
7791 14:46:55.026869 [Byte1]: 42
7792 14:46:55.026943
7793 14:46:55.030547 Set Vref, RX VrefLevel [Byte0]: 43
7794 14:46:55.032833 [Byte1]: 43
7795 14:46:55.037246
7796 14:46:55.037342 Set Vref, RX VrefLevel [Byte0]: 44
7797 14:46:55.040176 [Byte1]: 44
7798 14:46:55.044692
7799 14:46:55.044763 Set Vref, RX VrefLevel [Byte0]: 45
7800 14:46:55.047754 [Byte1]: 45
7801 14:46:55.052167
7802 14:46:55.052244 Set Vref, RX VrefLevel [Byte0]: 46
7803 14:46:55.055257 [Byte1]: 46
7804 14:46:55.059618
7805 14:46:55.059698 Set Vref, RX VrefLevel [Byte0]: 47
7806 14:46:55.063244 [Byte1]: 47
7807 14:46:55.067632
7808 14:46:55.067712 Set Vref, RX VrefLevel [Byte0]: 48
7809 14:46:55.070892 [Byte1]: 48
7810 14:46:55.074934
7811 14:46:55.075022 Set Vref, RX VrefLevel [Byte0]: 49
7812 14:46:55.078676 [Byte1]: 49
7813 14:46:55.082329
7814 14:46:55.082404 Set Vref, RX VrefLevel [Byte0]: 50
7815 14:46:55.086137 [Byte1]: 50
7816 14:46:55.090049
7817 14:46:55.090130 Set Vref, RX VrefLevel [Byte0]: 51
7818 14:46:55.093438 [Byte1]: 51
7819 14:46:55.097850
7820 14:46:55.097934 Set Vref, RX VrefLevel [Byte0]: 52
7821 14:46:55.101266 [Byte1]: 52
7822 14:46:55.105300
7823 14:46:55.105381 Set Vref, RX VrefLevel [Byte0]: 53
7824 14:46:55.108598 [Byte1]: 53
7825 14:46:55.112659
7826 14:46:55.112756 Set Vref, RX VrefLevel [Byte0]: 54
7827 14:46:55.116666 [Byte1]: 54
7828 14:46:55.120251
7829 14:46:55.120354 Set Vref, RX VrefLevel [Byte0]: 55
7830 14:46:55.123851 [Byte1]: 55
7831 14:46:55.128358
7832 14:46:55.128444 Set Vref, RX VrefLevel [Byte0]: 56
7833 14:46:55.131497 [Byte1]: 56
7834 14:46:55.135356
7835 14:46:55.135438 Set Vref, RX VrefLevel [Byte0]: 57
7836 14:46:55.138572 [Byte1]: 57
7837 14:46:55.142993
7838 14:46:55.143073 Set Vref, RX VrefLevel [Byte0]: 58
7839 14:46:55.146616 [Byte1]: 58
7840 14:46:55.150641
7841 14:46:55.150708 Set Vref, RX VrefLevel [Byte0]: 59
7842 14:46:55.153982 [Byte1]: 59
7843 14:46:55.158106
7844 14:46:55.158187 Set Vref, RX VrefLevel [Byte0]: 60
7845 14:46:55.162024 [Byte1]: 60
7846 14:46:55.165969
7847 14:46:55.166063 Set Vref, RX VrefLevel [Byte0]: 61
7848 14:46:55.168966 [Byte1]: 61
7849 14:46:55.173435
7850 14:46:55.173547 Set Vref, RX VrefLevel [Byte0]: 62
7851 14:46:55.176961 [Byte1]: 62
7852 14:46:55.181395
7853 14:46:55.181493 Set Vref, RX VrefLevel [Byte0]: 63
7854 14:46:55.184500 [Byte1]: 63
7855 14:46:55.188618
7856 14:46:55.188699 Set Vref, RX VrefLevel [Byte0]: 64
7857 14:46:55.192164 [Byte1]: 64
7858 14:46:55.196344
7859 14:46:55.196451 Set Vref, RX VrefLevel [Byte0]: 65
7860 14:46:55.199789 [Byte1]: 65
7861 14:46:55.203656
7862 14:46:55.203742 Set Vref, RX VrefLevel [Byte0]: 66
7863 14:46:55.206898 [Byte1]: 66
7864 14:46:55.211441
7865 14:46:55.211550 Set Vref, RX VrefLevel [Byte0]: 67
7866 14:46:55.214603 [Byte1]: 67
7867 14:46:55.219166
7868 14:46:55.219272 Set Vref, RX VrefLevel [Byte0]: 68
7869 14:46:55.222194 [Byte1]: 68
7870 14:46:55.226485
7871 14:46:55.226597 Set Vref, RX VrefLevel [Byte0]: 69
7872 14:46:55.229905 [Byte1]: 69
7873 14:46:55.233832
7874 14:46:55.233943 Set Vref, RX VrefLevel [Byte0]: 70
7875 14:46:55.237117 [Byte1]: 70
7876 14:46:55.241306
7877 14:46:55.241430 Set Vref, RX VrefLevel [Byte0]: 71
7878 14:46:55.244805 [Byte1]: 71
7879 14:46:55.249027
7880 14:46:55.249120 Set Vref, RX VrefLevel [Byte0]: 72
7881 14:46:55.252788 [Byte1]: 72
7882 14:46:55.257112
7883 14:46:55.257255 Set Vref, RX VrefLevel [Byte0]: 73
7884 14:46:55.259898 [Byte1]: 73
7885 14:46:55.264520
7886 14:46:55.264615 Set Vref, RX VrefLevel [Byte0]: 74
7887 14:46:55.267990 [Byte1]: 74
7888 14:46:55.271627
7889 14:46:55.271725 Final RX Vref Byte 0 = 55 to rank0
7890 14:46:55.275520 Final RX Vref Byte 1 = 58 to rank0
7891 14:46:55.278308 Final RX Vref Byte 0 = 55 to rank1
7892 14:46:55.281519 Final RX Vref Byte 1 = 58 to rank1==
7893 14:46:55.285397 Dram Type= 6, Freq= 0, CH_0, rank 0
7894 14:46:55.291350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7895 14:46:55.291463 ==
7896 14:46:55.291533 DQS Delay:
7897 14:46:55.294612 DQS0 = 0, DQS1 = 0
7898 14:46:55.294692 DQM Delay:
7899 14:46:55.298780 DQM0 = 128, DQM1 = 124
7900 14:46:55.298867 DQ Delay:
7901 14:46:55.301130 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7902 14:46:55.304744 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =134
7903 14:46:55.307824 DQ8 =112, DQ9 =110, DQ10 =126, DQ11 =120
7904 14:46:55.311113 DQ12 =130, DQ13 =130, DQ14 =134, DQ15 =132
7905 14:46:55.311214
7906 14:46:55.311288
7907 14:46:55.311346
7908 14:46:55.314315 [DramC_TX_OE_Calibration] TA2
7909 14:46:55.317535 Original DQ_B0 (3 6) =30, OEN = 27
7910 14:46:55.321407 Original DQ_B1 (3 6) =30, OEN = 27
7911 14:46:55.324315 24, 0x0, End_B0=24 End_B1=24
7912 14:46:55.327458 25, 0x0, End_B0=25 End_B1=25
7913 14:46:55.327563 26, 0x0, End_B0=26 End_B1=26
7914 14:46:55.330951 27, 0x0, End_B0=27 End_B1=27
7915 14:46:55.334324 28, 0x0, End_B0=28 End_B1=28
7916 14:46:55.337913 29, 0x0, End_B0=29 End_B1=29
7917 14:46:55.340557 30, 0x0, End_B0=30 End_B1=30
7918 14:46:55.340639 31, 0x4141, End_B0=30 End_B1=30
7919 14:46:55.344158 Byte0 end_step=30 best_step=27
7920 14:46:55.347334 Byte1 end_step=30 best_step=27
7921 14:46:55.351616 Byte0 TX OE(2T, 0.5T) = (3, 3)
7922 14:46:55.353825 Byte1 TX OE(2T, 0.5T) = (3, 3)
7923 14:46:55.353906
7924 14:46:55.353968
7925 14:46:55.360206 [DQSOSCAuto] RK0, (LSB)MR18= 0x1816, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
7926 14:46:55.363532 CH0 RK0: MR19=303, MR18=1816
7927 14:46:55.370321 CH0_RK0: MR19=0x303, MR18=0x1816, DQSOSC=397, MR23=63, INC=23, DEC=15
7928 14:46:55.370407
7929 14:46:55.373726 ----->DramcWriteLeveling(PI) begin...
7930 14:46:55.373804 ==
7931 14:46:55.376893 Dram Type= 6, Freq= 0, CH_0, rank 1
7932 14:46:55.380138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7933 14:46:55.383372 ==
7934 14:46:55.383464 Write leveling (Byte 0): 32 => 32
7935 14:46:55.386648 Write leveling (Byte 1): 25 => 25
7936 14:46:55.390040 DramcWriteLeveling(PI) end<-----
7937 14:46:55.390142
7938 14:46:55.390208 ==
7939 14:46:55.393876 Dram Type= 6, Freq= 0, CH_0, rank 1
7940 14:46:55.399931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7941 14:46:55.400050 ==
7942 14:46:55.400126 [Gating] SW mode calibration
7943 14:46:55.410208 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7944 14:46:55.413083 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7945 14:46:55.419978 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7946 14:46:55.423404 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7947 14:46:55.425977 1 4 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
7948 14:46:55.432725 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7949 14:46:55.436765 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7950 14:46:55.439547 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7951 14:46:55.445867 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7952 14:46:55.449525 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7953 14:46:55.452555 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7954 14:46:55.459671 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7955 14:46:55.462725 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7956 14:46:55.465610 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
7957 14:46:55.472401 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7958 14:46:55.475942 1 5 20 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
7959 14:46:55.478988 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7960 14:46:55.485804 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7961 14:46:55.489007 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7962 14:46:55.492049 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7963 14:46:55.498892 1 6 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7964 14:46:55.502569 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7965 14:46:55.505930 1 6 16 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
7966 14:46:55.512160 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7967 14:46:55.515458 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7968 14:46:55.519076 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7969 14:46:55.525146 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7970 14:46:55.528728 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7971 14:46:55.532068 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7972 14:46:55.538449 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7973 14:46:55.541508 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7974 14:46:55.544958 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7975 14:46:55.551391 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7976 14:46:55.554847 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7977 14:46:55.558940 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7978 14:46:55.565336 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7979 14:46:55.568246 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7980 14:46:55.571741 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7981 14:46:55.578774 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7982 14:46:55.580931 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7983 14:46:55.584523 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7984 14:46:55.591120 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7985 14:46:55.594947 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7986 14:46:55.597449 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7987 14:46:55.604356 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7988 14:46:55.607534 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7989 14:46:55.611329 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7990 14:46:55.614326 Total UI for P1: 0, mck2ui 16
7991 14:46:55.617081 best dqsien dly found for B0: ( 1, 9, 8)
7992 14:46:55.624020 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7993 14:46:55.624120 Total UI for P1: 0, mck2ui 16
7994 14:46:55.630244 best dqsien dly found for B1: ( 1, 9, 16)
7995 14:46:55.633880 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7996 14:46:55.637197 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
7997 14:46:55.637361
7998 14:46:55.640178 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7999 14:46:55.643868 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8000 14:46:55.647317 [Gating] SW calibration Done
8001 14:46:55.647414 ==
8002 14:46:55.650380 Dram Type= 6, Freq= 0, CH_0, rank 1
8003 14:46:55.653469 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8004 14:46:55.653579 ==
8005 14:46:55.656607 RX Vref Scan: 0
8006 14:46:55.656713
8007 14:46:55.656820 RX Vref 0 -> 0, step: 1
8008 14:46:55.656909
8009 14:46:55.660028 RX Delay 0 -> 252, step: 8
8010 14:46:55.663998 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8011 14:46:55.670905 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8012 14:46:55.673398 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8013 14:46:55.676604 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8014 14:46:55.680102 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8015 14:46:55.683168 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8016 14:46:55.690111 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8017 14:46:55.693464 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8018 14:46:55.696640 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8019 14:46:55.699651 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8020 14:46:55.702815 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8021 14:46:55.709746 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8022 14:46:55.713156 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8023 14:46:55.716274 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8024 14:46:55.719406 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8025 14:46:55.726110 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8026 14:46:55.726192 ==
8027 14:46:55.729154 Dram Type= 6, Freq= 0, CH_0, rank 1
8028 14:46:55.732822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8029 14:46:55.732908 ==
8030 14:46:55.732972 DQS Delay:
8031 14:46:55.735959 DQS0 = 0, DQS1 = 0
8032 14:46:55.736030 DQM Delay:
8033 14:46:55.739336 DQM0 = 131, DQM1 = 127
8034 14:46:55.739441 DQ Delay:
8035 14:46:55.743196 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8036 14:46:55.745854 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
8037 14:46:55.749170 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
8038 14:46:55.752712 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8039 14:46:55.755876
8040 14:46:55.755956
8041 14:46:55.756018 ==
8042 14:46:55.758839 Dram Type= 6, Freq= 0, CH_0, rank 1
8043 14:46:55.762313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8044 14:46:55.762414 ==
8045 14:46:55.762499
8046 14:46:55.762558
8047 14:46:55.765487 TX Vref Scan disable
8048 14:46:55.765566 == TX Byte 0 ==
8049 14:46:55.771927 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8050 14:46:55.775591 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8051 14:46:55.775664 == TX Byte 1 ==
8052 14:46:55.782233 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8053 14:46:55.785165 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8054 14:46:55.785293 ==
8055 14:46:55.790214 Dram Type= 6, Freq= 0, CH_0, rank 1
8056 14:46:55.792472 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8057 14:46:55.792548 ==
8058 14:46:55.806207
8059 14:46:55.809931 TX Vref early break, caculate TX vref
8060 14:46:55.813217 TX Vref=16, minBit 0, minWin=23, winSum=382
8061 14:46:55.816107 TX Vref=18, minBit 8, minWin=23, winSum=389
8062 14:46:55.819511 TX Vref=20, minBit 1, minWin=24, winSum=398
8063 14:46:55.823246 TX Vref=22, minBit 13, minWin=24, winSum=405
8064 14:46:55.826107 TX Vref=24, minBit 1, minWin=25, winSum=411
8065 14:46:55.832474 TX Vref=26, minBit 15, minWin=25, winSum=421
8066 14:46:55.835806 TX Vref=28, minBit 1, minWin=25, winSum=415
8067 14:46:55.839341 TX Vref=30, minBit 1, minWin=25, winSum=412
8068 14:46:55.842319 TX Vref=32, minBit 1, minWin=24, winSum=401
8069 14:46:55.846209 TX Vref=34, minBit 0, minWin=24, winSum=397
8070 14:46:55.852461 [TxChooseVref] Worse bit 15, Min win 25, Win sum 421, Final Vref 26
8071 14:46:55.852570
8072 14:46:55.856102 Final TX Range 0 Vref 26
8073 14:46:55.856182
8074 14:46:55.856243 ==
8075 14:46:55.858688 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 14:46:55.862184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 14:46:55.862255 ==
8078 14:46:55.865401
8079 14:46:55.865474
8080 14:46:55.865534 TX Vref Scan disable
8081 14:46:55.872078 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8082 14:46:55.872187 == TX Byte 0 ==
8083 14:46:55.876430 u2DelayCellOfst[0]=14 cells (4 PI)
8084 14:46:55.878713 u2DelayCellOfst[1]=17 cells (5 PI)
8085 14:46:55.882594 u2DelayCellOfst[2]=10 cells (3 PI)
8086 14:46:55.885065 u2DelayCellOfst[3]=14 cells (4 PI)
8087 14:46:55.889158 u2DelayCellOfst[4]=10 cells (3 PI)
8088 14:46:55.892270 u2DelayCellOfst[5]=0 cells (0 PI)
8089 14:46:55.895011 u2DelayCellOfst[6]=17 cells (5 PI)
8090 14:46:55.898397 u2DelayCellOfst[7]=17 cells (5 PI)
8091 14:46:55.901914 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8092 14:46:55.904931 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
8093 14:46:55.908401 == TX Byte 1 ==
8094 14:46:55.911392 u2DelayCellOfst[8]=0 cells (0 PI)
8095 14:46:55.914846 u2DelayCellOfst[9]=0 cells (0 PI)
8096 14:46:55.917766 u2DelayCellOfst[10]=3 cells (1 PI)
8097 14:46:55.921457 u2DelayCellOfst[11]=0 cells (0 PI)
8098 14:46:55.924621 u2DelayCellOfst[12]=7 cells (2 PI)
8099 14:46:55.928111 u2DelayCellOfst[13]=7 cells (2 PI)
8100 14:46:55.931295 u2DelayCellOfst[14]=14 cells (4 PI)
8101 14:46:55.934687 u2DelayCellOfst[15]=10 cells (3 PI)
8102 14:46:55.937881 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8103 14:46:55.941852 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8104 14:46:55.944183 DramC Write-DBI on
8105 14:46:55.944279 ==
8106 14:46:55.947510 Dram Type= 6, Freq= 0, CH_0, rank 1
8107 14:46:55.951150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8108 14:46:55.951225 ==
8109 14:46:55.951284
8110 14:46:55.951341
8111 14:46:55.954044 TX Vref Scan disable
8112 14:46:55.957462 == TX Byte 0 ==
8113 14:46:55.961076 Update DQM dly =731 (2 ,6, 27) DQM OEN =(3 ,3)
8114 14:46:55.961173 == TX Byte 1 ==
8115 14:46:55.968330 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8116 14:46:55.968423 DramC Write-DBI off
8117 14:46:55.968530
8118 14:46:55.968590 [DATLAT]
8119 14:46:55.970755 Freq=1600, CH0 RK1
8120 14:46:55.970826
8121 14:46:55.974272 DATLAT Default: 0xf
8122 14:46:55.974344 0, 0xFFFF, sum = 0
8123 14:46:55.977606 1, 0xFFFF, sum = 0
8124 14:46:55.977935 2, 0xFFFF, sum = 0
8125 14:46:55.981026 3, 0xFFFF, sum = 0
8126 14:46:55.981372 4, 0xFFFF, sum = 0
8127 14:46:55.984827 5, 0xFFFF, sum = 0
8128 14:46:55.985530 6, 0xFFFF, sum = 0
8129 14:46:55.987344 7, 0xFFFF, sum = 0
8130 14:46:55.987699 8, 0xFFFF, sum = 0
8131 14:46:55.990673 9, 0xFFFF, sum = 0
8132 14:46:55.991027 10, 0xFFFF, sum = 0
8133 14:46:55.994742 11, 0xFFFF, sum = 0
8134 14:46:55.995268 12, 0xFFFF, sum = 0
8135 14:46:55.997073 13, 0xFFFF, sum = 0
8136 14:46:55.997578 14, 0x0, sum = 1
8137 14:46:56.001046 15, 0x0, sum = 2
8138 14:46:56.001543 16, 0x0, sum = 3
8139 14:46:56.003635 17, 0x0, sum = 4
8140 14:46:56.004145 best_step = 15
8141 14:46:56.004529
8142 14:46:56.004885 ==
8143 14:46:56.007189 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 14:46:56.014139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 14:46:56.014662 ==
8146 14:46:56.015127 RX Vref Scan: 0
8147 14:46:56.015577
8148 14:46:56.016806 RX Vref 0 -> 0, step: 1
8149 14:46:56.017315
8150 14:46:56.020739 RX Delay 11 -> 252, step: 4
8151 14:46:56.023485 iDelay=191, Bit 0, Center 124 (75 ~ 174) 100
8152 14:46:56.026863 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8153 14:46:56.033154 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8154 14:46:56.036933 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8155 14:46:56.040102 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8156 14:46:56.043249 iDelay=191, Bit 5, Center 118 (63 ~ 174) 112
8157 14:46:56.046266 iDelay=191, Bit 6, Center 136 (87 ~ 186) 100
8158 14:46:56.053759 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8159 14:46:56.056421 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8160 14:46:56.059505 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8161 14:46:56.062904 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8162 14:46:56.069378 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8163 14:46:56.073239 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8164 14:46:56.076094 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8165 14:46:56.079308 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8166 14:46:56.083124 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8167 14:46:56.086026 ==
8168 14:46:56.089250 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 14:46:56.092648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 14:46:56.093134 ==
8171 14:46:56.093568 DQS Delay:
8172 14:46:56.095830 DQS0 = 0, DQS1 = 0
8173 14:46:56.096295 DQM Delay:
8174 14:46:56.099420 DQM0 = 127, DQM1 = 124
8175 14:46:56.099781 DQ Delay:
8176 14:46:56.102411 DQ0 =124, DQ1 =130, DQ2 =122, DQ3 =126
8177 14:46:56.105481 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
8178 14:46:56.109155 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8179 14:46:56.112207 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =130
8180 14:46:56.112563
8181 14:46:56.112841
8182 14:46:56.113104
8183 14:46:56.115900 [DramC_TX_OE_Calibration] TA2
8184 14:46:56.118876 Original DQ_B0 (3 6) =30, OEN = 27
8185 14:46:56.122547 Original DQ_B1 (3 6) =30, OEN = 27
8186 14:46:56.125434 24, 0x0, End_B0=24 End_B1=24
8187 14:46:56.128754 25, 0x0, End_B0=25 End_B1=25
8188 14:46:56.132165 26, 0x0, End_B0=26 End_B1=26
8189 14:46:56.132528 27, 0x0, End_B0=27 End_B1=27
8190 14:46:56.135039 28, 0x0, End_B0=28 End_B1=28
8191 14:46:56.138596 29, 0x0, End_B0=29 End_B1=29
8192 14:46:56.141894 30, 0x0, End_B0=30 End_B1=30
8193 14:46:56.145174 31, 0x4545, End_B0=30 End_B1=30
8194 14:46:56.145554 Byte0 end_step=30 best_step=27
8195 14:46:56.148805 Byte1 end_step=30 best_step=27
8196 14:46:56.151612 Byte0 TX OE(2T, 0.5T) = (3, 3)
8197 14:46:56.155289 Byte1 TX OE(2T, 0.5T) = (3, 3)
8198 14:46:56.155646
8199 14:46:56.155925
8200 14:46:56.164806 [DQSOSCAuto] RK1, (LSB)MR18= 0x1513, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8201 14:46:56.165215 CH0 RK1: MR19=303, MR18=1513
8202 14:46:56.171175 CH0_RK1: MR19=0x303, MR18=0x1513, DQSOSC=399, MR23=63, INC=23, DEC=15
8203 14:46:56.174556 [RxdqsGatingPostProcess] freq 1600
8204 14:46:56.181508 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8205 14:46:56.184591 best DQS0 dly(2T, 0.5T) = (1, 1)
8206 14:46:56.187714 best DQS1 dly(2T, 0.5T) = (1, 1)
8207 14:46:56.191100 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8208 14:46:56.194341 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8209 14:46:56.194558 best DQS0 dly(2T, 0.5T) = (1, 1)
8210 14:46:56.198258 best DQS1 dly(2T, 0.5T) = (1, 1)
8211 14:46:56.200814 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8212 14:46:56.204273 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8213 14:46:56.207584 Pre-setting of DQS Precalculation
8214 14:46:56.214235 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8215 14:46:56.214346 ==
8216 14:46:56.217467 Dram Type= 6, Freq= 0, CH_1, rank 0
8217 14:46:56.221111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8218 14:46:56.221217 ==
8219 14:46:56.227154 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8220 14:46:56.230225 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8221 14:46:56.234326 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8222 14:46:56.240078 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8223 14:46:56.249251 [CA 0] Center 42 (13~72) winsize 60
8224 14:46:56.252561 [CA 1] Center 42 (12~72) winsize 61
8225 14:46:56.256310 [CA 2] Center 39 (9~69) winsize 61
8226 14:46:56.258979 [CA 3] Center 37 (8~67) winsize 60
8227 14:46:56.262829 [CA 4] Center 38 (8~69) winsize 62
8228 14:46:56.265964 [CA 5] Center 37 (8~67) winsize 60
8229 14:46:56.266051
8230 14:46:56.268819 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8231 14:46:56.268911
8232 14:46:56.272760 [CATrainingPosCal] consider 1 rank data
8233 14:46:56.275886 u2DelayCellTimex100 = 275/100 ps
8234 14:46:56.282162 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8235 14:46:56.285374 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8236 14:46:56.289143 CA2 delay=39 (9~69),Diff = 2 PI (7 cell)
8237 14:46:56.292021 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8238 14:46:56.295203 CA4 delay=38 (8~69),Diff = 1 PI (3 cell)
8239 14:46:56.299251 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8240 14:46:56.299351
8241 14:46:56.302157 CA PerBit enable=1, Macro0, CA PI delay=37
8242 14:46:56.302227
8243 14:46:56.304956 [CBTSetCACLKResult] CA Dly = 37
8244 14:46:56.308213 CS Dly: 8 (0~39)
8245 14:46:56.311692 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8246 14:46:56.315588 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8247 14:46:56.315687 ==
8248 14:46:56.318822 Dram Type= 6, Freq= 0, CH_1, rank 1
8249 14:46:56.325024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8250 14:46:56.325138 ==
8251 14:46:56.328120 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8252 14:46:56.334448 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8253 14:46:56.337939 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8254 14:46:56.344648 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8255 14:46:56.352565 [CA 0] Center 42 (12~72) winsize 61
8256 14:46:56.355396 [CA 1] Center 42 (12~72) winsize 61
8257 14:46:56.359215 [CA 2] Center 37 (8~67) winsize 60
8258 14:46:56.362604 [CA 3] Center 37 (7~67) winsize 61
8259 14:46:56.365158 [CA 4] Center 37 (8~67) winsize 60
8260 14:46:56.368726 [CA 5] Center 37 (7~67) winsize 61
8261 14:46:56.368803
8262 14:46:56.373372 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8263 14:46:56.373476
8264 14:46:56.378990 [CATrainingPosCal] consider 2 rank data
8265 14:46:56.379068 u2DelayCellTimex100 = 275/100 ps
8266 14:46:56.385769 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8267 14:46:56.388526 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8268 14:46:56.392027 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8269 14:46:56.395080 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8270 14:46:56.398571 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8271 14:46:56.402138 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8272 14:46:56.402240
8273 14:46:56.404727 CA PerBit enable=1, Macro0, CA PI delay=37
8274 14:46:56.404829
8275 14:46:56.408088 [CBTSetCACLKResult] CA Dly = 37
8276 14:46:56.411293 CS Dly: 9 (0~42)
8277 14:46:56.414536 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8278 14:46:56.417931 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8279 14:46:56.418005
8280 14:46:56.421605 ----->DramcWriteLeveling(PI) begin...
8281 14:46:56.421679 ==
8282 14:46:56.424584 Dram Type= 6, Freq= 0, CH_1, rank 0
8283 14:46:56.431205 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8284 14:46:56.431302 ==
8285 14:46:56.434574 Write leveling (Byte 0): 23 => 23
8286 14:46:56.438172 Write leveling (Byte 1): 26 => 26
8287 14:46:56.440849 DramcWriteLeveling(PI) end<-----
8288 14:46:56.440946
8289 14:46:56.441035 ==
8290 14:46:56.444558 Dram Type= 6, Freq= 0, CH_1, rank 0
8291 14:46:56.447447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8292 14:46:56.447539 ==
8293 14:46:56.450811 [Gating] SW mode calibration
8294 14:46:56.457692 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8295 14:46:56.464306 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8296 14:46:56.467639 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8297 14:46:56.470794 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8298 14:46:56.477835 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
8299 14:46:56.481217 1 4 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8300 14:46:56.484133 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8301 14:46:56.490712 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8302 14:46:56.493715 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8303 14:46:56.497052 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8304 14:46:56.503598 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8305 14:46:56.506690 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8306 14:46:56.510311 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8307 14:46:56.517020 1 5 12 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (1 0)
8308 14:46:56.519891 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8309 14:46:56.523379 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8310 14:46:56.529813 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8311 14:46:56.533704 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8312 14:46:56.536802 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8313 14:46:56.542949 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8314 14:46:56.546097 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8315 14:46:56.549553 1 6 12 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
8316 14:46:56.556138 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8317 14:46:56.559616 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8318 14:46:56.562880 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8319 14:46:56.569219 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8320 14:46:56.572833 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8321 14:46:56.577227 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8322 14:46:56.582375 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8323 14:46:56.585937 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8324 14:46:56.589248 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8325 14:46:56.595841 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8326 14:46:56.599010 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8327 14:46:56.602569 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8328 14:46:56.608798 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8329 14:46:56.611960 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8330 14:46:56.615911 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8331 14:46:56.622121 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8332 14:46:56.625179 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8333 14:46:56.628723 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8334 14:46:56.635212 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8335 14:46:56.638706 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8336 14:46:56.642142 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8337 14:46:56.648489 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8338 14:46:56.651793 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8339 14:46:56.654943 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8340 14:46:56.661600 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8341 14:46:56.661704 Total UI for P1: 0, mck2ui 16
8342 14:46:56.668171 best dqsien dly found for B0: ( 1, 9, 10)
8343 14:46:56.671625 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 14:46:56.674808 Total UI for P1: 0, mck2ui 16
8345 14:46:56.678317 best dqsien dly found for B1: ( 1, 9, 14)
8346 14:46:56.681126 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8347 14:46:56.684916 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8348 14:46:56.685019
8349 14:46:56.687951 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8350 14:46:56.691130 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8351 14:46:56.694600 [Gating] SW calibration Done
8352 14:46:56.694719 ==
8353 14:46:56.697666 Dram Type= 6, Freq= 0, CH_1, rank 0
8354 14:46:56.704511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8355 14:46:56.704596 ==
8356 14:46:56.704702 RX Vref Scan: 0
8357 14:46:56.704791
8358 14:46:56.707911 RX Vref 0 -> 0, step: 1
8359 14:46:56.708018
8360 14:46:56.711397 RX Delay 0 -> 252, step: 8
8361 14:46:56.714175 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8362 14:46:56.717304 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8363 14:46:56.720808 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8364 14:46:56.723946 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8365 14:46:56.730935 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8366 14:46:56.734396 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8367 14:46:56.737409 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8368 14:46:56.740644 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8369 14:46:56.743783 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8370 14:46:56.750447 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8371 14:46:56.753768 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8372 14:46:56.757337 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8373 14:46:56.760622 iDelay=200, Bit 12, Center 143 (96 ~ 191) 96
8374 14:46:56.766895 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8375 14:46:56.770239 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8376 14:46:56.773294 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8377 14:46:56.773456 ==
8378 14:46:56.776755 Dram Type= 6, Freq= 0, CH_1, rank 0
8379 14:46:56.780420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8380 14:46:56.780502 ==
8381 14:46:56.783249 DQS Delay:
8382 14:46:56.783355 DQS0 = 0, DQS1 = 0
8383 14:46:56.787419 DQM Delay:
8384 14:46:56.787499 DQM0 = 135, DQM1 = 132
8385 14:46:56.790454 DQ Delay:
8386 14:46:56.793111 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8387 14:46:56.797046 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =131
8388 14:46:56.799591 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8389 14:46:56.803067 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =139
8390 14:46:56.803153
8391 14:46:56.803217
8392 14:46:56.803276 ==
8393 14:46:56.806326 Dram Type= 6, Freq= 0, CH_1, rank 0
8394 14:46:56.809459 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8395 14:46:56.809566 ==
8396 14:46:56.809657
8397 14:46:56.812743
8398 14:46:56.812815 TX Vref Scan disable
8399 14:46:56.816965 == TX Byte 0 ==
8400 14:46:56.819671 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8401 14:46:56.822824 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8402 14:46:56.826074 == TX Byte 1 ==
8403 14:46:56.829131 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8404 14:46:56.832494 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8405 14:46:56.832594 ==
8406 14:46:56.835966 Dram Type= 6, Freq= 0, CH_1, rank 0
8407 14:46:56.842746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8408 14:46:56.842855 ==
8409 14:46:56.854456
8410 14:46:56.857787 TX Vref early break, caculate TX vref
8411 14:46:56.860732 TX Vref=16, minBit 8, minWin=21, winSum=368
8412 14:46:56.864031 TX Vref=18, minBit 8, minWin=21, winSum=378
8413 14:46:56.867438 TX Vref=20, minBit 5, minWin=23, winSum=386
8414 14:46:56.871086 TX Vref=22, minBit 8, minWin=23, winSum=397
8415 14:46:56.874076 TX Vref=24, minBit 8, minWin=24, winSum=410
8416 14:46:56.880610 TX Vref=26, minBit 8, minWin=25, winSum=416
8417 14:46:56.883879 TX Vref=28, minBit 9, minWin=25, winSum=418
8418 14:46:56.888063 TX Vref=30, minBit 9, minWin=25, winSum=415
8419 14:46:56.890535 TX Vref=32, minBit 6, minWin=24, winSum=404
8420 14:46:56.894422 TX Vref=34, minBit 1, minWin=23, winSum=395
8421 14:46:56.900215 [TxChooseVref] Worse bit 9, Min win 25, Win sum 418, Final Vref 28
8422 14:46:56.900333
8423 14:46:56.903809 Final TX Range 0 Vref 28
8424 14:46:56.903921
8425 14:46:56.904009 ==
8426 14:46:56.908169 Dram Type= 6, Freq= 0, CH_1, rank 0
8427 14:46:56.910051 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8428 14:46:56.910146 ==
8429 14:46:56.910233
8430 14:46:56.910317
8431 14:46:56.913860 TX Vref Scan disable
8432 14:46:56.920941 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8433 14:46:56.921054 == TX Byte 0 ==
8434 14:46:56.923554 u2DelayCellOfst[0]=17 cells (5 PI)
8435 14:46:56.926565 u2DelayCellOfst[1]=10 cells (3 PI)
8436 14:46:56.929778 u2DelayCellOfst[2]=0 cells (0 PI)
8437 14:46:56.933173 u2DelayCellOfst[3]=7 cells (2 PI)
8438 14:46:56.936343 u2DelayCellOfst[4]=7 cells (2 PI)
8439 14:46:56.939897 u2DelayCellOfst[5]=17 cells (5 PI)
8440 14:46:56.942920 u2DelayCellOfst[6]=17 cells (5 PI)
8441 14:46:56.946551 u2DelayCellOfst[7]=7 cells (2 PI)
8442 14:46:56.949633 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8443 14:46:56.953135 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8444 14:46:56.956442 == TX Byte 1 ==
8445 14:46:56.959745 u2DelayCellOfst[8]=0 cells (0 PI)
8446 14:46:56.963284 u2DelayCellOfst[9]=3 cells (1 PI)
8447 14:46:56.966261 u2DelayCellOfst[10]=14 cells (4 PI)
8448 14:46:56.966332 u2DelayCellOfst[11]=3 cells (1 PI)
8449 14:46:56.969479 u2DelayCellOfst[12]=14 cells (4 PI)
8450 14:46:56.972652 u2DelayCellOfst[13]=14 cells (4 PI)
8451 14:46:56.976061 u2DelayCellOfst[14]=17 cells (5 PI)
8452 14:46:56.979445 u2DelayCellOfst[15]=14 cells (4 PI)
8453 14:46:56.986538 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8454 14:46:56.989541 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8455 14:46:56.989613 DramC Write-DBI on
8456 14:46:56.992408 ==
8457 14:46:56.995765 Dram Type= 6, Freq= 0, CH_1, rank 0
8458 14:46:56.998810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8459 14:46:56.998917 ==
8460 14:46:56.999009
8461 14:46:56.999096
8462 14:46:57.002767 TX Vref Scan disable
8463 14:46:57.002838 == TX Byte 0 ==
8464 14:46:57.008848 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8465 14:46:57.008950 == TX Byte 1 ==
8466 14:46:57.012504 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8467 14:46:57.015488 DramC Write-DBI off
8468 14:46:57.015585
8469 14:46:57.015673 [DATLAT]
8470 14:46:57.019282 Freq=1600, CH1 RK0
8471 14:46:57.019362
8472 14:46:57.019425 DATLAT Default: 0xf
8473 14:46:57.022035 0, 0xFFFF, sum = 0
8474 14:46:57.022116 1, 0xFFFF, sum = 0
8475 14:46:57.025695 2, 0xFFFF, sum = 0
8476 14:46:57.025775 3, 0xFFFF, sum = 0
8477 14:46:57.028629 4, 0xFFFF, sum = 0
8478 14:46:57.031843 5, 0xFFFF, sum = 0
8479 14:46:57.031972 6, 0xFFFF, sum = 0
8480 14:46:57.034906 7, 0xFFFF, sum = 0
8481 14:46:57.034984 8, 0xFFFF, sum = 0
8482 14:46:57.038662 9, 0xFFFF, sum = 0
8483 14:46:57.038734 10, 0xFFFF, sum = 0
8484 14:46:57.042171 11, 0xFFFF, sum = 0
8485 14:46:57.042244 12, 0xFFFF, sum = 0
8486 14:46:57.045666 13, 0xFFFF, sum = 0
8487 14:46:57.045756 14, 0x0, sum = 1
8488 14:46:57.049074 15, 0x0, sum = 2
8489 14:46:57.049175 16, 0x0, sum = 3
8490 14:46:57.051604 17, 0x0, sum = 4
8491 14:46:57.051682 best_step = 15
8492 14:46:57.051743
8493 14:46:57.051802 ==
8494 14:46:57.054646 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 14:46:57.061622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8496 14:46:57.061726 ==
8497 14:46:57.061820 RX Vref Scan: 1
8498 14:46:57.061883
8499 14:46:57.064910 Set Vref Range= 24 -> 127
8500 14:46:57.065008
8501 14:46:57.067799 RX Vref 24 -> 127, step: 1
8502 14:46:57.067905
8503 14:46:57.067968 RX Delay 19 -> 252, step: 4
8504 14:46:57.068050
8505 14:46:57.071306 Set Vref, RX VrefLevel [Byte0]: 24
8506 14:46:57.074301 [Byte1]: 24
8507 14:46:57.078500
8508 14:46:57.078573 Set Vref, RX VrefLevel [Byte0]: 25
8509 14:46:57.082114 [Byte1]: 25
8510 14:46:57.085984
8511 14:46:57.086059 Set Vref, RX VrefLevel [Byte0]: 26
8512 14:46:57.089413 [Byte1]: 26
8513 14:46:57.093560
8514 14:46:57.093674 Set Vref, RX VrefLevel [Byte0]: 27
8515 14:46:57.097989 [Byte1]: 27
8516 14:46:57.101522
8517 14:46:57.101607 Set Vref, RX VrefLevel [Byte0]: 28
8518 14:46:57.104617 [Byte1]: 28
8519 14:46:57.108865
8520 14:46:57.108941 Set Vref, RX VrefLevel [Byte0]: 29
8521 14:46:57.112210 [Byte1]: 29
8522 14:46:57.116365
8523 14:46:57.116439 Set Vref, RX VrefLevel [Byte0]: 30
8524 14:46:57.119864 [Byte1]: 30
8525 14:46:57.124509
8526 14:46:57.124584 Set Vref, RX VrefLevel [Byte0]: 31
8527 14:46:57.127298 [Byte1]: 31
8528 14:46:57.131806
8529 14:46:57.131878 Set Vref, RX VrefLevel [Byte0]: 32
8530 14:46:57.135016 [Byte1]: 32
8531 14:46:57.139536
8532 14:46:57.139620 Set Vref, RX VrefLevel [Byte0]: 33
8533 14:46:57.142472 [Byte1]: 33
8534 14:46:57.147004
8535 14:46:57.147081 Set Vref, RX VrefLevel [Byte0]: 34
8536 14:46:57.150175 [Byte1]: 34
8537 14:46:57.155111
8538 14:46:57.155186 Set Vref, RX VrefLevel [Byte0]: 35
8539 14:46:57.157393 [Byte1]: 35
8540 14:46:57.161965
8541 14:46:57.162039 Set Vref, RX VrefLevel [Byte0]: 36
8542 14:46:57.166099 [Byte1]: 36
8543 14:46:57.169912
8544 14:46:57.169987 Set Vref, RX VrefLevel [Byte0]: 37
8545 14:46:57.172847 [Byte1]: 37
8546 14:46:57.177003
8547 14:46:57.177110 Set Vref, RX VrefLevel [Byte0]: 38
8548 14:46:57.180873 [Byte1]: 38
8549 14:46:57.185192
8550 14:46:57.185296 Set Vref, RX VrefLevel [Byte0]: 39
8551 14:46:57.187826 [Byte1]: 39
8552 14:46:57.192667
8553 14:46:57.192739 Set Vref, RX VrefLevel [Byte0]: 40
8554 14:46:57.195513 [Byte1]: 40
8555 14:46:57.200010
8556 14:46:57.200084 Set Vref, RX VrefLevel [Byte0]: 41
8557 14:46:57.202973 [Byte1]: 41
8558 14:46:57.207168
8559 14:46:57.207252 Set Vref, RX VrefLevel [Byte0]: 42
8560 14:46:57.211780 [Byte1]: 42
8561 14:46:57.214935
8562 14:46:57.215011 Set Vref, RX VrefLevel [Byte0]: 43
8563 14:46:57.218388 [Byte1]: 43
8564 14:46:57.222435
8565 14:46:57.222515 Set Vref, RX VrefLevel [Byte0]: 44
8566 14:46:57.225848 [Byte1]: 44
8567 14:46:57.230025
8568 14:46:57.230107 Set Vref, RX VrefLevel [Byte0]: 45
8569 14:46:57.233650 [Byte1]: 45
8570 14:46:57.237445
8571 14:46:57.237522 Set Vref, RX VrefLevel [Byte0]: 46
8572 14:46:57.240866 [Byte1]: 46
8573 14:46:57.245614
8574 14:46:57.245699 Set Vref, RX VrefLevel [Byte0]: 47
8575 14:46:57.248829 [Byte1]: 47
8576 14:46:57.252927
8577 14:46:57.253002 Set Vref, RX VrefLevel [Byte0]: 48
8578 14:46:57.256029 [Byte1]: 48
8579 14:46:57.260523
8580 14:46:57.260599 Set Vref, RX VrefLevel [Byte0]: 49
8581 14:46:57.263694 [Byte1]: 49
8582 14:46:57.268055
8583 14:46:57.268141 Set Vref, RX VrefLevel [Byte0]: 50
8584 14:46:57.271454 [Byte1]: 50
8585 14:46:57.275698
8586 14:46:57.275780 Set Vref, RX VrefLevel [Byte0]: 51
8587 14:46:57.278858 [Byte1]: 51
8588 14:46:57.282928
8589 14:46:57.283010 Set Vref, RX VrefLevel [Byte0]: 52
8590 14:46:57.286470 [Byte1]: 52
8591 14:46:57.290527
8592 14:46:57.290604 Set Vref, RX VrefLevel [Byte0]: 53
8593 14:46:57.293854 [Byte1]: 53
8594 14:46:57.298511
8595 14:46:57.298615 Set Vref, RX VrefLevel [Byte0]: 54
8596 14:46:57.301723 [Byte1]: 54
8597 14:46:57.305583
8598 14:46:57.305661 Set Vref, RX VrefLevel [Byte0]: 55
8599 14:46:57.309426 [Byte1]: 55
8600 14:46:57.313365
8601 14:46:57.313442 Set Vref, RX VrefLevel [Byte0]: 56
8602 14:46:57.316681 [Byte1]: 56
8603 14:46:57.321187
8604 14:46:57.321291 Set Vref, RX VrefLevel [Byte0]: 57
8605 14:46:57.324053 [Byte1]: 57
8606 14:46:57.328621
8607 14:46:57.328722 Set Vref, RX VrefLevel [Byte0]: 58
8608 14:46:57.331652 [Byte1]: 58
8609 14:46:57.336109
8610 14:46:57.336203 Set Vref, RX VrefLevel [Byte0]: 59
8611 14:46:57.339356 [Byte1]: 59
8612 14:46:57.343616
8613 14:46:57.343698 Set Vref, RX VrefLevel [Byte0]: 60
8614 14:46:57.347155 [Byte1]: 60
8615 14:46:57.351136
8616 14:46:57.351247 Set Vref, RX VrefLevel [Byte0]: 61
8617 14:46:57.354485 [Byte1]: 61
8618 14:46:57.358850
8619 14:46:57.358931 Set Vref, RX VrefLevel [Byte0]: 62
8620 14:46:57.362184 [Byte1]: 62
8621 14:46:57.366576
8622 14:46:57.366697 Set Vref, RX VrefLevel [Byte0]: 63
8623 14:46:57.370081 [Byte1]: 63
8624 14:46:57.374346
8625 14:46:57.374427 Set Vref, RX VrefLevel [Byte0]: 64
8626 14:46:57.376979 [Byte1]: 64
8627 14:46:57.381422
8628 14:46:57.381503 Set Vref, RX VrefLevel [Byte0]: 65
8629 14:46:57.384819 [Byte1]: 65
8630 14:46:57.389155
8631 14:46:57.389237 Set Vref, RX VrefLevel [Byte0]: 66
8632 14:46:57.392939 [Byte1]: 66
8633 14:46:57.396721
8634 14:46:57.396836 Set Vref, RX VrefLevel [Byte0]: 67
8635 14:46:57.399865 [Byte1]: 67
8636 14:46:57.404068
8637 14:46:57.404149 Set Vref, RX VrefLevel [Byte0]: 68
8638 14:46:57.408557 [Byte1]: 68
8639 14:46:57.411903
8640 14:46:57.411995 Set Vref, RX VrefLevel [Byte0]: 69
8641 14:46:57.414995 [Byte1]: 69
8642 14:46:57.419666
8643 14:46:57.419748 Set Vref, RX VrefLevel [Byte0]: 70
8644 14:46:57.422513 [Byte1]: 70
8645 14:46:57.426993
8646 14:46:57.427127 Set Vref, RX VrefLevel [Byte0]: 71
8647 14:46:57.430753 [Byte1]: 71
8648 14:46:57.434636
8649 14:46:57.434756 Final RX Vref Byte 0 = 57 to rank0
8650 14:46:57.437738 Final RX Vref Byte 1 = 61 to rank0
8651 14:46:57.441010 Final RX Vref Byte 0 = 57 to rank1
8652 14:46:57.444362 Final RX Vref Byte 1 = 61 to rank1==
8653 14:46:57.447872 Dram Type= 6, Freq= 0, CH_1, rank 0
8654 14:46:57.454082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8655 14:46:57.454165 ==
8656 14:46:57.454239 DQS Delay:
8657 14:46:57.457422 DQS0 = 0, DQS1 = 0
8658 14:46:57.457502 DQM Delay:
8659 14:46:57.457566 DQM0 = 132, DQM1 = 129
8660 14:46:57.460723 DQ Delay:
8661 14:46:57.464227 DQ0 =138, DQ1 =130, DQ2 =118, DQ3 =132
8662 14:46:57.467676 DQ4 =128, DQ5 =144, DQ6 =146, DQ7 =126
8663 14:46:57.471228 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =120
8664 14:46:57.474173 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8665 14:46:57.474252
8666 14:46:57.474313
8667 14:46:57.474370
8668 14:46:57.477458 [DramC_TX_OE_Calibration] TA2
8669 14:46:57.480551 Original DQ_B0 (3 6) =30, OEN = 27
8670 14:46:57.484649 Original DQ_B1 (3 6) =30, OEN = 27
8671 14:46:57.487310 24, 0x0, End_B0=24 End_B1=24
8672 14:46:57.491259 25, 0x0, End_B0=25 End_B1=25
8673 14:46:57.491337 26, 0x0, End_B0=26 End_B1=26
8674 14:46:57.494097 27, 0x0, End_B0=27 End_B1=27
8675 14:46:57.497383 28, 0x0, End_B0=28 End_B1=28
8676 14:46:57.500700 29, 0x0, End_B0=29 End_B1=29
8677 14:46:57.501289 30, 0x0, End_B0=30 End_B1=30
8678 14:46:57.504361 31, 0x4141, End_B0=30 End_B1=30
8679 14:46:57.507555 Byte0 end_step=30 best_step=27
8680 14:46:57.510907 Byte1 end_step=30 best_step=27
8681 14:46:57.513857 Byte0 TX OE(2T, 0.5T) = (3, 3)
8682 14:46:57.517129 Byte1 TX OE(2T, 0.5T) = (3, 3)
8683 14:46:57.517583
8684 14:46:57.517889
8685 14:46:57.523842 [DQSOSCAuto] RK0, (LSB)MR18= 0xc16, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
8686 14:46:57.526941 CH1 RK0: MR19=303, MR18=C16
8687 14:46:57.533401 CH1_RK0: MR19=0x303, MR18=0xC16, DQSOSC=398, MR23=63, INC=23, DEC=15
8688 14:46:57.533502
8689 14:46:57.536785 ----->DramcWriteLeveling(PI) begin...
8690 14:46:57.536889 ==
8691 14:46:57.540372 Dram Type= 6, Freq= 0, CH_1, rank 1
8692 14:46:57.543076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8693 14:46:57.543195 ==
8694 14:46:57.546311 Write leveling (Byte 0): 23 => 23
8695 14:46:57.550202 Write leveling (Byte 1): 25 => 25
8696 14:46:57.553421 DramcWriteLeveling(PI) end<-----
8697 14:46:57.553564
8698 14:46:57.553658 ==
8699 14:46:57.556229 Dram Type= 6, Freq= 0, CH_1, rank 1
8700 14:46:57.559505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8701 14:46:57.562977 ==
8702 14:46:57.563063 [Gating] SW mode calibration
8703 14:46:57.573027 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8704 14:46:57.575846 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8705 14:46:57.580006 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8706 14:46:57.586159 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8707 14:46:57.589188 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8708 14:46:57.592988 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8709 14:46:57.599113 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8710 14:46:57.602645 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8711 14:46:57.606475 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8712 14:46:57.612320 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8713 14:46:57.615773 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8714 14:46:57.618858 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8715 14:46:57.625532 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8716 14:46:57.629047 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8717 14:46:57.632252 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8718 14:46:57.639185 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8719 14:46:57.642296 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8720 14:46:57.645961 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8721 14:46:57.652920 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8722 14:46:57.655719 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8723 14:46:57.658485 1 6 8 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8724 14:46:57.664988 1 6 12 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
8725 14:46:57.668485 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8726 14:46:57.671529 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8727 14:46:57.678804 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8728 14:46:57.681802 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8729 14:46:57.684584 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8730 14:46:57.691456 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8731 14:46:57.695201 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8732 14:46:57.698089 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8733 14:46:57.704838 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8734 14:46:57.708074 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8735 14:46:57.710903 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8736 14:46:57.717450 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8737 14:46:57.721358 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8738 14:46:57.724415 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8739 14:46:57.730955 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8740 14:46:57.734320 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8741 14:46:57.737574 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8742 14:46:57.744390 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8743 14:46:57.747244 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8744 14:46:57.750729 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8745 14:46:57.757535 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8746 14:46:57.760622 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8747 14:46:57.763953 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8748 14:46:57.771109 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8749 14:46:57.774293 Total UI for P1: 0, mck2ui 16
8750 14:46:57.776981 best dqsien dly found for B0: ( 1, 9, 8)
8751 14:46:57.780347 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8752 14:46:57.783436 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8753 14:46:57.787044 Total UI for P1: 0, mck2ui 16
8754 14:46:57.790113 best dqsien dly found for B1: ( 1, 9, 14)
8755 14:46:57.793712 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8756 14:46:57.796955 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8757 14:46:57.800623
8758 14:46:57.803253 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8759 14:46:57.806833 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8760 14:46:57.810312 [Gating] SW calibration Done
8761 14:46:57.810399 ==
8762 14:46:57.813289 Dram Type= 6, Freq= 0, CH_1, rank 1
8763 14:46:57.816436 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8764 14:46:57.816520 ==
8765 14:46:57.820050 RX Vref Scan: 0
8766 14:46:57.820123
8767 14:46:57.820191 RX Vref 0 -> 0, step: 1
8768 14:46:57.820250
8769 14:46:57.823084 RX Delay 0 -> 252, step: 8
8770 14:46:57.826771 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8771 14:46:57.830387 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8772 14:46:57.836836 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8773 14:46:57.839808 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8774 14:46:57.842928 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8775 14:46:57.846275 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8776 14:46:57.849776 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8777 14:46:57.856207 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8778 14:46:57.859679 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8779 14:46:57.863294 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8780 14:46:57.866145 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8781 14:46:57.872608 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8782 14:46:57.876136 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8783 14:46:57.879214 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8784 14:46:57.882620 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8785 14:46:57.885759 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8786 14:46:57.889408 ==
8787 14:46:57.892212 Dram Type= 6, Freq= 0, CH_1, rank 1
8788 14:46:57.896690 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8789 14:46:57.896813 ==
8790 14:46:57.896876 DQS Delay:
8791 14:46:57.899537 DQS0 = 0, DQS1 = 0
8792 14:46:57.899613 DQM Delay:
8793 14:46:57.902582 DQM0 = 136, DQM1 = 129
8794 14:46:57.902724 DQ Delay:
8795 14:46:57.905917 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =135
8796 14:46:57.908831 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =135
8797 14:46:57.911984 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8798 14:46:57.916035 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8799 14:46:57.916129
8800 14:46:57.916207
8801 14:46:57.918903 ==
8802 14:46:57.919024 Dram Type= 6, Freq= 0, CH_1, rank 1
8803 14:46:57.925421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8804 14:46:57.925502 ==
8805 14:46:57.925566
8806 14:46:57.925626
8807 14:46:57.928628 TX Vref Scan disable
8808 14:46:57.928700 == TX Byte 0 ==
8809 14:46:57.932229 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8810 14:46:57.938595 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8811 14:46:57.938675 == TX Byte 1 ==
8812 14:46:57.941733 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8813 14:46:57.948398 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8814 14:46:57.948487 ==
8815 14:46:57.951703 Dram Type= 6, Freq= 0, CH_1, rank 1
8816 14:46:57.954633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8817 14:46:57.954711 ==
8818 14:46:57.967925
8819 14:46:57.971200 TX Vref early break, caculate TX vref
8820 14:46:57.974584 TX Vref=16, minBit 9, minWin=21, winSum=381
8821 14:46:57.977795 TX Vref=18, minBit 9, minWin=22, winSum=388
8822 14:46:57.980891 TX Vref=20, minBit 9, minWin=22, winSum=395
8823 14:46:57.984436 TX Vref=22, minBit 9, minWin=23, winSum=403
8824 14:46:57.987719 TX Vref=24, minBit 9, minWin=24, winSum=415
8825 14:46:57.994172 TX Vref=26, minBit 9, minWin=24, winSum=419
8826 14:46:57.997371 TX Vref=28, minBit 0, minWin=26, winSum=426
8827 14:46:58.000777 TX Vref=30, minBit 9, minWin=24, winSum=414
8828 14:46:58.004145 TX Vref=32, minBit 5, minWin=24, winSum=407
8829 14:46:58.007523 TX Vref=34, minBit 9, minWin=23, winSum=399
8830 14:46:58.014003 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
8831 14:46:58.014084
8832 14:46:58.017602 Final TX Range 0 Vref 28
8833 14:46:58.017702
8834 14:46:58.017765 ==
8835 14:46:58.020484 Dram Type= 6, Freq= 0, CH_1, rank 1
8836 14:46:58.024095 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8837 14:46:58.024170 ==
8838 14:46:58.024233
8839 14:46:58.024291
8840 14:46:58.027178 TX Vref Scan disable
8841 14:46:58.033982 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8842 14:46:58.034104 == TX Byte 0 ==
8843 14:46:58.037581 u2DelayCellOfst[0]=17 cells (5 PI)
8844 14:46:58.040452 u2DelayCellOfst[1]=10 cells (3 PI)
8845 14:46:58.043715 u2DelayCellOfst[2]=0 cells (0 PI)
8846 14:46:58.046820 u2DelayCellOfst[3]=7 cells (2 PI)
8847 14:46:58.050035 u2DelayCellOfst[4]=7 cells (2 PI)
8848 14:46:58.053568 u2DelayCellOfst[5]=17 cells (5 PI)
8849 14:46:58.057110 u2DelayCellOfst[6]=17 cells (5 PI)
8850 14:46:58.060439 u2DelayCellOfst[7]=7 cells (2 PI)
8851 14:46:58.063376 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8852 14:46:58.066842 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8853 14:46:58.069990 == TX Byte 1 ==
8854 14:46:58.073278 u2DelayCellOfst[8]=0 cells (0 PI)
8855 14:46:58.076724 u2DelayCellOfst[9]=3 cells (1 PI)
8856 14:46:58.079787 u2DelayCellOfst[10]=10 cells (3 PI)
8857 14:46:58.079861 u2DelayCellOfst[11]=3 cells (1 PI)
8858 14:46:58.083380 u2DelayCellOfst[12]=10 cells (3 PI)
8859 14:46:58.086882 u2DelayCellOfst[13]=14 cells (4 PI)
8860 14:46:58.089831 u2DelayCellOfst[14]=17 cells (5 PI)
8861 14:46:58.093329 u2DelayCellOfst[15]=17 cells (5 PI)
8862 14:46:58.099999 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8863 14:46:58.103221 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8864 14:46:58.103312 DramC Write-DBI on
8865 14:46:58.103377 ==
8866 14:46:58.106740 Dram Type= 6, Freq= 0, CH_1, rank 1
8867 14:46:58.113166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8868 14:46:58.113285 ==
8869 14:46:58.113354
8870 14:46:58.113414
8871 14:46:58.113488 TX Vref Scan disable
8872 14:46:58.117913 == TX Byte 0 ==
8873 14:46:58.120569 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8874 14:46:58.123764 == TX Byte 1 ==
8875 14:46:58.127691 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8876 14:46:58.130365 DramC Write-DBI off
8877 14:46:58.130444
8878 14:46:58.130533 [DATLAT]
8879 14:46:58.130608 Freq=1600, CH1 RK1
8880 14:46:58.130684
8881 14:46:58.134014 DATLAT Default: 0xf
8882 14:46:58.136882 0, 0xFFFF, sum = 0
8883 14:46:58.136964 1, 0xFFFF, sum = 0
8884 14:46:58.140055 2, 0xFFFF, sum = 0
8885 14:46:58.140129 3, 0xFFFF, sum = 0
8886 14:46:58.143568 4, 0xFFFF, sum = 0
8887 14:46:58.143643 5, 0xFFFF, sum = 0
8888 14:46:58.146899 6, 0xFFFF, sum = 0
8889 14:46:58.146975 7, 0xFFFF, sum = 0
8890 14:46:58.150081 8, 0xFFFF, sum = 0
8891 14:46:58.150154 9, 0xFFFF, sum = 0
8892 14:46:58.153994 10, 0xFFFF, sum = 0
8893 14:46:58.154067 11, 0xFFFF, sum = 0
8894 14:46:58.156809 12, 0xFFFF, sum = 0
8895 14:46:58.156877 13, 0xFFFF, sum = 0
8896 14:46:58.159970 14, 0x0, sum = 1
8897 14:46:58.160043 15, 0x0, sum = 2
8898 14:46:58.163320 16, 0x0, sum = 3
8899 14:46:58.163389 17, 0x0, sum = 4
8900 14:46:58.167059 best_step = 15
8901 14:46:58.167128
8902 14:46:58.167185 ==
8903 14:46:58.169648 Dram Type= 6, Freq= 0, CH_1, rank 1
8904 14:46:58.173439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8905 14:46:58.173554 ==
8906 14:46:58.176640 RX Vref Scan: 0
8907 14:46:58.176718
8908 14:46:58.176780 RX Vref 0 -> 0, step: 1
8909 14:46:58.176838
8910 14:46:58.180049 RX Delay 11 -> 252, step: 4
8911 14:46:58.186399 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8912 14:46:58.189453 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8913 14:46:58.192654 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8914 14:46:58.196698 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8915 14:46:58.199907 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8916 14:46:58.205957 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8917 14:46:58.209542 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8918 14:46:58.212987 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8919 14:46:58.216029 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8920 14:46:58.219237 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8921 14:46:58.225894 iDelay=195, Bit 10, Center 130 (75 ~ 186) 112
8922 14:46:58.229467 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8923 14:46:58.232686 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8924 14:46:58.235860 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8925 14:46:58.242205 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8926 14:46:58.245537 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8927 14:46:58.245634 ==
8928 14:46:58.249093 Dram Type= 6, Freq= 0, CH_1, rank 1
8929 14:46:58.252483 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8930 14:46:58.252562 ==
8931 14:46:58.255383 DQS Delay:
8932 14:46:58.255486 DQS0 = 0, DQS1 = 0
8933 14:46:58.255594 DQM Delay:
8934 14:46:58.258837 DQM0 = 133, DQM1 = 128
8935 14:46:58.258938 DQ Delay:
8936 14:46:58.262062 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =130
8937 14:46:58.265473 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =130
8938 14:46:58.271728 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =120
8939 14:46:58.275167 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
8940 14:46:58.275269
8941 14:46:58.275377
8942 14:46:58.275447
8943 14:46:58.278320 [DramC_TX_OE_Calibration] TA2
8944 14:46:58.281873 Original DQ_B0 (3 6) =30, OEN = 27
8945 14:46:58.284982 Original DQ_B1 (3 6) =30, OEN = 27
8946 14:46:58.285062 24, 0x0, End_B0=24 End_B1=24
8947 14:46:58.288175 25, 0x0, End_B0=25 End_B1=25
8948 14:46:58.291618 26, 0x0, End_B0=26 End_B1=26
8949 14:46:58.295141 27, 0x0, End_B0=27 End_B1=27
8950 14:46:58.295214 28, 0x0, End_B0=28 End_B1=28
8951 14:46:58.298370 29, 0x0, End_B0=29 End_B1=29
8952 14:46:58.301836 30, 0x0, End_B0=30 End_B1=30
8953 14:46:58.305196 31, 0x4141, End_B0=30 End_B1=30
8954 14:46:58.308651 Byte0 end_step=30 best_step=27
8955 14:46:58.311786 Byte1 end_step=30 best_step=27
8956 14:46:58.311858 Byte0 TX OE(2T, 0.5T) = (3, 3)
8957 14:46:58.314753 Byte1 TX OE(2T, 0.5T) = (3, 3)
8958 14:46:58.314826
8959 14:46:58.314889
8960 14:46:58.324908 [DQSOSCAuto] RK1, (LSB)MR18= 0x1120, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 401 ps
8961 14:46:58.328421 CH1 RK1: MR19=303, MR18=1120
8962 14:46:58.331922 CH1_RK1: MR19=0x303, MR18=0x1120, DQSOSC=393, MR23=63, INC=23, DEC=15
8963 14:46:58.334730 [RxdqsGatingPostProcess] freq 1600
8964 14:46:58.341570 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8965 14:46:58.344886 best DQS0 dly(2T, 0.5T) = (1, 1)
8966 14:46:58.347854 best DQS1 dly(2T, 0.5T) = (1, 1)
8967 14:46:58.351099 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8968 14:46:58.354669 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8969 14:46:58.357569 best DQS0 dly(2T, 0.5T) = (1, 1)
8970 14:46:58.360958 best DQS1 dly(2T, 0.5T) = (1, 1)
8971 14:46:58.364585 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8972 14:46:58.364660 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8973 14:46:58.367910 Pre-setting of DQS Precalculation
8974 14:46:58.374281 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8975 14:46:58.381487 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8976 14:46:58.387548 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8977 14:46:58.387621
8978 14:46:58.387686
8979 14:46:58.391009 [Calibration Summary] 3200 Mbps
8980 14:46:58.393877 CH 0, Rank 0
8981 14:46:58.393947 SW Impedance : PASS
8982 14:46:58.397404 DUTY Scan : NO K
8983 14:46:58.400573 ZQ Calibration : PASS
8984 14:46:58.400649 Jitter Meter : NO K
8985 14:46:58.403889 CBT Training : PASS
8986 14:46:58.407670 Write leveling : PASS
8987 14:46:58.407740 RX DQS gating : PASS
8988 14:46:58.410371 RX DQ/DQS(RDDQC) : PASS
8989 14:46:58.413751 TX DQ/DQS : PASS
8990 14:46:58.413822 RX DATLAT : PASS
8991 14:46:58.417329 RX DQ/DQS(Engine): PASS
8992 14:46:58.420230 TX OE : PASS
8993 14:46:58.420307 All Pass.
8994 14:46:58.420368
8995 14:46:58.420425 CH 0, Rank 1
8996 14:46:58.424061 SW Impedance : PASS
8997 14:46:58.427062 DUTY Scan : NO K
8998 14:46:58.427129 ZQ Calibration : PASS
8999 14:46:58.430509 Jitter Meter : NO K
9000 14:46:58.430582 CBT Training : PASS
9001 14:46:58.434196 Write leveling : PASS
9002 14:46:58.437576 RX DQS gating : PASS
9003 14:46:58.437664 RX DQ/DQS(RDDQC) : PASS
9004 14:46:58.440062 TX DQ/DQS : PASS
9005 14:46:58.443330 RX DATLAT : PASS
9006 14:46:58.443403 RX DQ/DQS(Engine): PASS
9007 14:46:58.446555 TX OE : PASS
9008 14:46:58.446635 All Pass.
9009 14:46:58.446696
9010 14:46:58.449891 CH 1, Rank 0
9011 14:46:58.449963 SW Impedance : PASS
9012 14:46:58.453403 DUTY Scan : NO K
9013 14:46:58.456576 ZQ Calibration : PASS
9014 14:46:58.456646 Jitter Meter : NO K
9015 14:46:58.460353 CBT Training : PASS
9016 14:46:58.463665 Write leveling : PASS
9017 14:46:58.463735 RX DQS gating : PASS
9018 14:46:58.466535 RX DQ/DQS(RDDQC) : PASS
9019 14:46:58.469722 TX DQ/DQS : PASS
9020 14:46:58.469791 RX DATLAT : PASS
9021 14:46:58.473270 RX DQ/DQS(Engine): PASS
9022 14:46:58.476145 TX OE : PASS
9023 14:46:58.476215 All Pass.
9024 14:46:58.476281
9025 14:46:58.476339 CH 1, Rank 1
9026 14:46:58.480254 SW Impedance : PASS
9027 14:46:58.482805 DUTY Scan : NO K
9028 14:46:58.482881 ZQ Calibration : PASS
9029 14:46:58.486010 Jitter Meter : NO K
9030 14:46:58.489615 CBT Training : PASS
9031 14:46:58.489683 Write leveling : PASS
9032 14:46:58.492694 RX DQS gating : PASS
9033 14:46:58.496072 RX DQ/DQS(RDDQC) : PASS
9034 14:46:58.496199 TX DQ/DQS : PASS
9035 14:46:58.499234 RX DATLAT : PASS
9036 14:46:58.502655 RX DQ/DQS(Engine): PASS
9037 14:46:58.502757 TX OE : PASS
9038 14:46:58.502865 All Pass.
9039 14:46:58.502954
9040 14:46:58.505905 DramC Write-DBI on
9041 14:46:58.509537 PER_BANK_REFRESH: Hybrid Mode
9042 14:46:58.509653 TX_TRACKING: ON
9043 14:46:58.519100 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9044 14:46:58.526302 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9045 14:46:58.535332 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9046 14:46:58.538701 [FAST_K] Save calibration result to emmc
9047 14:46:58.542594 sync common calibartion params.
9048 14:46:58.542697 sync cbt_mode0:1, 1:1
9049 14:46:58.545403 dram_init: ddr_geometry: 2
9050 14:46:58.548821 dram_init: ddr_geometry: 2
9051 14:46:58.548962 dram_init: ddr_geometry: 2
9052 14:46:58.551936 0:dram_rank_size:100000000
9053 14:46:58.555421 1:dram_rank_size:100000000
9054 14:46:58.562241 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9055 14:46:58.562374 DFS_SHUFFLE_HW_MODE: ON
9056 14:46:58.565340 dramc_set_vcore_voltage set vcore to 725000
9057 14:46:58.568512 Read voltage for 1600, 0
9058 14:46:58.568588 Vio18 = 0
9059 14:46:58.571715 Vcore = 725000
9060 14:46:58.571819 Vdram = 0
9061 14:46:58.571897 Vddq = 0
9062 14:46:58.575060 Vmddr = 0
9063 14:46:58.575132 switch to 3200 Mbps bootup
9064 14:46:58.578235 [DramcRunTimeConfig]
9065 14:46:58.578310 PHYPLL
9066 14:46:58.582276 DPM_CONTROL_AFTERK: ON
9067 14:46:58.582353 PER_BANK_REFRESH: ON
9068 14:46:58.585101 REFRESH_OVERHEAD_REDUCTION: ON
9069 14:46:58.588335 CMD_PICG_NEW_MODE: OFF
9070 14:46:58.588476 XRTWTW_NEW_MODE: ON
9071 14:46:58.592498 XRTRTR_NEW_MODE: ON
9072 14:46:58.592603 TX_TRACKING: ON
9073 14:46:58.594676 RDSEL_TRACKING: OFF
9074 14:46:58.598137 DQS Precalculation for DVFS: ON
9075 14:46:58.598229 RX_TRACKING: OFF
9076 14:46:58.602007 HW_GATING DBG: ON
9077 14:46:58.602083 ZQCS_ENABLE_LP4: ON
9078 14:46:58.604968 RX_PICG_NEW_MODE: ON
9079 14:46:58.605087 TX_PICG_NEW_MODE: ON
9080 14:46:58.608154 ENABLE_RX_DCM_DPHY: ON
9081 14:46:58.611211 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9082 14:46:58.614551 DUMMY_READ_FOR_TRACKING: OFF
9083 14:46:58.618732 !!! SPM_CONTROL_AFTERK: OFF
9084 14:46:58.618809 !!! SPM could not control APHY
9085 14:46:58.621203 IMPEDANCE_TRACKING: ON
9086 14:46:58.621330 TEMP_SENSOR: ON
9087 14:46:58.624546 HW_SAVE_FOR_SR: OFF
9088 14:46:58.628152 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9089 14:46:58.630955 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9090 14:46:58.634338 Read ODT Tracking: ON
9091 14:46:58.634414 Refresh Rate DeBounce: ON
9092 14:46:58.637688 DFS_NO_QUEUE_FLUSH: ON
9093 14:46:58.641047 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9094 14:46:58.644207 ENABLE_DFS_RUNTIME_MRW: OFF
9095 14:46:58.644278 DDR_RESERVE_NEW_MODE: ON
9096 14:46:58.647559 MR_CBT_SWITCH_FREQ: ON
9097 14:46:58.650858 =========================
9098 14:46:58.669004 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9099 14:46:58.672086 dram_init: ddr_geometry: 2
9100 14:46:58.690550 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9101 14:46:58.693706 dram_init: dram init end (result: 0)
9102 14:46:58.700301 DRAM-K: Full calibration passed in 24378 msecs
9103 14:46:58.703992 MRC: failed to locate region type 0.
9104 14:46:58.704106 DRAM rank0 size:0x100000000,
9105 14:46:58.707540 DRAM rank1 size=0x100000000
9106 14:46:58.716649 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9107 14:46:58.723144 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9108 14:46:58.729940 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9109 14:46:58.739639 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9110 14:46:58.739757 DRAM rank0 size:0x100000000,
9111 14:46:58.743029 DRAM rank1 size=0x100000000
9112 14:46:58.743136 CBMEM:
9113 14:46:58.745861 IMD: root @ 0xfffff000 254 entries.
9114 14:46:58.749911 IMD: root @ 0xffffec00 62 entries.
9115 14:46:58.756076 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9116 14:46:58.759811 WARNING: RO_VPD is uninitialized or empty.
9117 14:46:58.762404 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9118 14:46:58.770076 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9119 14:46:58.783301 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9120 14:46:58.794915 BS: romstage times (exec / console): total (unknown) / 23916 ms
9121 14:46:58.795000
9122 14:46:58.795063
9123 14:46:58.804516 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9124 14:46:58.807974 ARM64: Exception handlers installed.
9125 14:46:58.810769 ARM64: Testing exception
9126 14:46:58.814389 ARM64: Done test exception
9127 14:46:58.814468 Enumerating buses...
9128 14:46:58.817459 Show all devs... Before device enumeration.
9129 14:46:58.821602 Root Device: enabled 1
9130 14:46:58.824800 CPU_CLUSTER: 0: enabled 1
9131 14:46:58.824877 CPU: 00: enabled 1
9132 14:46:58.827391 Compare with tree...
9133 14:46:58.827460 Root Device: enabled 1
9134 14:46:58.830567 CPU_CLUSTER: 0: enabled 1
9135 14:46:58.834408 CPU: 00: enabled 1
9136 14:46:58.834488 Root Device scanning...
9137 14:46:58.837589 scan_static_bus for Root Device
9138 14:46:58.840271 CPU_CLUSTER: 0 enabled
9139 14:46:58.844079 scan_static_bus for Root Device done
9140 14:46:58.847991 scan_bus: bus Root Device finished in 8 msecs
9141 14:46:58.848083 done
9142 14:46:58.853608 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9143 14:46:58.857361 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9144 14:46:58.863394 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9145 14:46:58.869904 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9146 14:46:58.869981 Allocating resources...
9147 14:46:58.873181 Reading resources...
9148 14:46:58.876833 Root Device read_resources bus 0 link: 0
9149 14:46:58.879713 DRAM rank0 size:0x100000000,
9150 14:46:58.879785 DRAM rank1 size=0x100000000
9151 14:46:58.886621 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9152 14:46:58.886700 CPU: 00 missing read_resources
9153 14:46:58.892930 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9154 14:46:58.896292 Root Device read_resources bus 0 link: 0 done
9155 14:46:58.899436 Done reading resources.
9156 14:46:58.903164 Show resources in subtree (Root Device)...After reading.
9157 14:46:58.906442 Root Device child on link 0 CPU_CLUSTER: 0
9158 14:46:58.909279 CPU_CLUSTER: 0 child on link 0 CPU: 00
9159 14:46:58.919301 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9160 14:46:58.919387 CPU: 00
9161 14:46:58.925877 Root Device assign_resources, bus 0 link: 0
9162 14:46:58.928931 CPU_CLUSTER: 0 missing set_resources
9163 14:46:58.932171 Root Device assign_resources, bus 0 link: 0 done
9164 14:46:58.935676 Done setting resources.
9165 14:46:58.938893 Show resources in subtree (Root Device)...After assigning values.
9166 14:46:58.945961 Root Device child on link 0 CPU_CLUSTER: 0
9167 14:46:58.949060 CPU_CLUSTER: 0 child on link 0 CPU: 00
9168 14:46:58.955329 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9169 14:46:58.958846 CPU: 00
9170 14:46:58.958944 Done allocating resources.
9171 14:46:58.965147 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9172 14:46:58.968356 Enabling resources...
9173 14:46:58.968430 done.
9174 14:46:58.971583 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9175 14:46:58.975028 Initializing devices...
9176 14:46:58.975115 Root Device init
9177 14:46:58.978395 init hardware done!
9178 14:46:58.981454 0x00000018: ctrlr->caps
9179 14:46:58.981524 52.000 MHz: ctrlr->f_max
9180 14:46:58.985227 0.400 MHz: ctrlr->f_min
9181 14:46:58.989308 0x40ff8080: ctrlr->voltages
9182 14:46:58.989404 sclk: 390625
9183 14:46:58.989508 Bus Width = 1
9184 14:46:58.991460 sclk: 390625
9185 14:46:58.991524 Bus Width = 1
9186 14:46:58.995585 Early init status = 3
9187 14:46:58.998343 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9188 14:46:59.002212 in-header: 03 fc 00 00 01 00 00 00
9189 14:46:59.005651 in-data: 00
9190 14:46:59.009281 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9191 14:46:59.014123 in-header: 03 fd 00 00 00 00 00 00
9192 14:46:59.017744 in-data:
9193 14:46:59.020522 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9194 14:46:59.025125 in-header: 03 fc 00 00 01 00 00 00
9195 14:46:59.028911 in-data: 00
9196 14:46:59.031960 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9197 14:46:59.037154 in-header: 03 fd 00 00 00 00 00 00
9198 14:46:59.040981 in-data:
9199 14:46:59.044028 [SSUSB] Setting up USB HOST controller...
9200 14:46:59.047113 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9201 14:46:59.050880 [SSUSB] phy power-on done.
9202 14:46:59.053784 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9203 14:46:59.060477 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9204 14:46:59.063742 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9205 14:46:59.069899 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9206 14:46:59.076736 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9207 14:46:59.083849 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9208 14:46:59.090181 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9209 14:46:59.097506 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9210 14:46:59.099768 SPM: binary array size = 0x9dc
9211 14:46:59.102986 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9212 14:46:59.109500 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9213 14:46:59.116214 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9214 14:46:59.122902 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9215 14:46:59.125856 configure_display: Starting display init
9216 14:46:59.161025 anx7625_power_on_init: Init interface.
9217 14:46:59.163814 anx7625_disable_pd_protocol: Disabled PD feature.
9218 14:46:59.167072 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9219 14:46:59.194971 anx7625_start_dp_work: Secure OCM version=00
9220 14:46:59.198794 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9221 14:46:59.213732 sp_tx_get_edid_block: EDID Block = 1
9222 14:46:59.316072 Extracted contents:
9223 14:46:59.319460 header: 00 ff ff ff ff ff ff 00
9224 14:46:59.322392 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9225 14:46:59.325766 version: 01 04
9226 14:46:59.329037 basic params: 95 1f 11 78 0a
9227 14:46:59.333454 chroma info: 76 90 94 55 54 90 27 21 50 54
9228 14:46:59.335475 established: 00 00 00
9229 14:46:59.342273 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9230 14:46:59.346237 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9231 14:46:59.352143 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9232 14:46:59.358511 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9233 14:46:59.365524 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9234 14:46:59.369397 extensions: 00
9235 14:46:59.369489 checksum: fb
9236 14:46:59.369553
9237 14:46:59.372129 Manufacturer: IVO Model 57d Serial Number 0
9238 14:46:59.375148 Made week 0 of 2020
9239 14:46:59.378992 EDID version: 1.4
9240 14:46:59.379077 Digital display
9241 14:46:59.381691 6 bits per primary color channel
9242 14:46:59.381773 DisplayPort interface
9243 14:46:59.385149 Maximum image size: 31 cm x 17 cm
9244 14:46:59.389003 Gamma: 220%
9245 14:46:59.389089 Check DPMS levels
9246 14:46:59.391565 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9247 14:46:59.398527 First detailed timing is preferred timing
9248 14:46:59.398619 Established timings supported:
9249 14:46:59.402143 Standard timings supported:
9250 14:46:59.405038 Detailed timings
9251 14:46:59.408811 Hex of detail: 383680a07038204018303c0035ae10000019
9252 14:46:59.414856 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9253 14:46:59.418107 0780 0798 07c8 0820 hborder 0
9254 14:46:59.421533 0438 043b 0447 0458 vborder 0
9255 14:46:59.425157 -hsync -vsync
9256 14:46:59.425247 Did detailed timing
9257 14:46:59.431125 Hex of detail: 000000000000000000000000000000000000
9258 14:46:59.434654 Manufacturer-specified data, tag 0
9259 14:46:59.437926 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9260 14:46:59.441048 ASCII string: InfoVision
9261 14:46:59.444528 Hex of detail: 000000fe00523134304e574635205248200a
9262 14:46:59.448813 ASCII string: R140NWF5 RH
9263 14:46:59.448908 Checksum
9264 14:46:59.450710 Checksum: 0xfb (valid)
9265 14:46:59.454363 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9266 14:46:59.457972 DSI data_rate: 832800000 bps
9267 14:46:59.464168 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9268 14:46:59.467610 anx7625_parse_edid: pixelclock(138800).
9269 14:46:59.470573 hactive(1920), hsync(48), hfp(24), hbp(88)
9270 14:46:59.474561 vactive(1080), vsync(12), vfp(3), vbp(17)
9271 14:46:59.477443 anx7625_dsi_config: config dsi.
9272 14:46:59.483787 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9273 14:46:59.497748 anx7625_dsi_config: success to config DSI
9274 14:46:59.501974 anx7625_dp_start: MIPI phy setup OK.
9275 14:46:59.504674 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9276 14:46:59.508634 mtk_ddp_mode_set invalid vrefresh 60
9277 14:46:59.511238 main_disp_path_setup
9278 14:46:59.511318 ovl_layer_smi_id_en
9279 14:46:59.514244 ovl_layer_smi_id_en
9280 14:46:59.514324 ccorr_config
9281 14:46:59.514387 aal_config
9282 14:46:59.517399 gamma_config
9283 14:46:59.517478 postmask_config
9284 14:46:59.520988 dither_config
9285 14:46:59.524056 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9286 14:46:59.531085 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9287 14:46:59.534080 Root Device init finished in 554 msecs
9288 14:46:59.537545 CPU_CLUSTER: 0 init
9289 14:46:59.543807 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9290 14:46:59.550990 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9291 14:46:59.551071 APU_MBOX 0x190000b0 = 0x10001
9292 14:46:59.553708 APU_MBOX 0x190001b0 = 0x10001
9293 14:46:59.557079 APU_MBOX 0x190005b0 = 0x10001
9294 14:46:59.560207 APU_MBOX 0x190006b0 = 0x10001
9295 14:46:59.567225 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9296 14:46:59.576737 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9297 14:46:59.589507 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9298 14:46:59.595740 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9299 14:46:59.607803 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9300 14:46:59.616567 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9301 14:46:59.619935 CPU_CLUSTER: 0 init finished in 81 msecs
9302 14:46:59.622972 Devices initialized
9303 14:46:59.626244 Show all devs... After init.
9304 14:46:59.626336 Root Device: enabled 1
9305 14:46:59.629927 CPU_CLUSTER: 0: enabled 1
9306 14:46:59.632705 CPU: 00: enabled 1
9307 14:46:59.636233 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9308 14:46:59.639464 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9309 14:46:59.642464 ELOG: NV offset 0x57f000 size 0x1000
9310 14:46:59.649947 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9311 14:46:59.656403 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9312 14:46:59.660190 ELOG: Event(17) added with size 13 at 2024-06-04 14:46:59 UTC
9313 14:46:59.666087 out: cmd=0x121: 03 db 21 01 00 00 00 00
9314 14:46:59.669193 in-header: 03 26 00 00 2c 00 00 00
9315 14:46:59.679769 in-data: 17 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9316 14:46:59.686270 ELOG: Event(A1) added with size 10 at 2024-06-04 14:46:59 UTC
9317 14:46:59.692791 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9318 14:46:59.699145 ELOG: Event(A0) added with size 9 at 2024-06-04 14:46:59 UTC
9319 14:46:59.702177 elog_add_boot_reason: Logged dev mode boot
9320 14:46:59.708770 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9321 14:46:59.708850 Finalize devices...
9322 14:46:59.712061 Devices finalized
9323 14:46:59.715707 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9324 14:46:59.718771 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9325 14:46:59.722670 in-header: 03 07 00 00 08 00 00 00
9326 14:46:59.726190 in-data: aa e4 47 04 13 02 00 00
9327 14:46:59.728932 Chrome EC: UHEPI supported
9328 14:46:59.736209 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9329 14:46:59.739450 in-header: 03 a9 00 00 08 00 00 00
9330 14:46:59.742477 in-data: 84 60 60 08 00 00 00 00
9331 14:46:59.749026 ELOG: Event(91) added with size 10 at 2024-06-04 14:46:59 UTC
9332 14:46:59.751933 Chrome EC: clear events_b mask to 0x0000000020004000
9333 14:46:59.758678 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9334 14:46:59.763243 in-header: 03 fd 00 00 00 00 00 00
9335 14:46:59.766669 in-data:
9336 14:46:59.770261 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9337 14:46:59.773123 Writing coreboot table at 0xffe64000
9338 14:46:59.779765 0. 000000000010a000-0000000000113fff: RAMSTAGE
9339 14:46:59.783031 1. 0000000040000000-00000000400fffff: RAM
9340 14:46:59.786174 2. 0000000040100000-000000004032afff: RAMSTAGE
9341 14:46:59.789489 3. 000000004032b000-00000000545fffff: RAM
9342 14:46:59.792742 4. 0000000054600000-000000005465ffff: BL31
9343 14:46:59.796772 5. 0000000054660000-00000000ffe63fff: RAM
9344 14:46:59.802986 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9345 14:46:59.806263 7. 0000000100000000-000000023fffffff: RAM
9346 14:46:59.809653 Passing 5 GPIOs to payload:
9347 14:46:59.812524 NAME | PORT | POLARITY | VALUE
9348 14:46:59.819307 EC in RW | 0x000000aa | low | undefined
9349 14:46:59.823120 EC interrupt | 0x00000005 | low | undefined
9350 14:46:59.829197 TPM interrupt | 0x000000ab | high | undefined
9351 14:46:59.832152 SD card detect | 0x00000011 | high | undefined
9352 14:46:59.835535 speaker enable | 0x00000093 | high | undefined
9353 14:46:59.842128 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9354 14:46:59.845298 in-header: 03 f9 00 00 02 00 00 00
9355 14:46:59.845393 in-data: 02 00
9356 14:46:59.848607 ADC[4]: Raw value=902955 ID=7
9357 14:46:59.852608 ADC[3]: Raw value=213916 ID=1
9358 14:46:59.852687 RAM Code: 0x71
9359 14:46:59.855191 ADC[6]: Raw value=75000 ID=0
9360 14:46:59.858481 ADC[5]: Raw value=213546 ID=1
9361 14:46:59.858562 SKU Code: 0x1
9362 14:46:59.865417 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum edbb
9363 14:46:59.868391 coreboot table: 964 bytes.
9364 14:46:59.871727 IMD ROOT 0. 0xfffff000 0x00001000
9365 14:46:59.874845 IMD SMALL 1. 0xffffe000 0x00001000
9366 14:46:59.879239 RO MCACHE 2. 0xffffc000 0x00001104
9367 14:46:59.881698 CONSOLE 3. 0xfff7c000 0x00080000
9368 14:46:59.884873 FMAP 4. 0xfff7b000 0x00000452
9369 14:46:59.888220 TIME STAMP 5. 0xfff7a000 0x00000910
9370 14:46:59.891516 VBOOT WORK 6. 0xfff66000 0x00014000
9371 14:46:59.894634 RAMOOPS 7. 0xffe66000 0x00100000
9372 14:46:59.898066 COREBOOT 8. 0xffe64000 0x00002000
9373 14:46:59.898147 IMD small region:
9374 14:46:59.901736 IMD ROOT 0. 0xffffec00 0x00000400
9375 14:46:59.905230 VPD 1. 0xffffeb80 0x0000006c
9376 14:46:59.907777 MMC STATUS 2. 0xffffeb60 0x00000004
9377 14:46:59.915032 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9378 14:46:59.921567 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9379 14:46:59.960162 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9380 14:46:59.963689 Checking segment from ROM address 0x40100000
9381 14:46:59.966818 Checking segment from ROM address 0x4010001c
9382 14:46:59.973055 Loading segment from ROM address 0x40100000
9383 14:46:59.973135 code (compression=0)
9384 14:46:59.983354 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9385 14:46:59.989679 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9386 14:46:59.989760 it's not compressed!
9387 14:46:59.996573 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9388 14:47:00.003204 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9389 14:47:00.020698 Loading segment from ROM address 0x4010001c
9390 14:47:00.020784 Entry Point 0x80000000
9391 14:47:00.024041 Loaded segments
9392 14:47:00.026951 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9393 14:47:00.033929 Jumping to boot code at 0x80000000(0xffe64000)
9394 14:47:00.040100 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9395 14:47:00.046583 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9396 14:47:00.054993 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9397 14:47:00.058200 Checking segment from ROM address 0x40100000
9398 14:47:00.061359 Checking segment from ROM address 0x4010001c
9399 14:47:00.068135 Loading segment from ROM address 0x40100000
9400 14:47:00.068215 code (compression=1)
9401 14:47:00.074693 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9402 14:47:00.084435 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9403 14:47:00.084518 using LZMA
9404 14:47:00.093137 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9405 14:47:00.099695 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9406 14:47:00.103246 Loading segment from ROM address 0x4010001c
9407 14:47:00.106178 Entry Point 0x54601000
9408 14:47:00.106275 Loaded segments
9409 14:47:00.109466 NOTICE: MT8192 bl31_setup
9410 14:47:00.116804 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9411 14:47:00.120588 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9412 14:47:00.123540 WARNING: region 0:
9413 14:47:00.126510 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9414 14:47:00.126589 WARNING: region 1:
9415 14:47:00.133825 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9416 14:47:00.136746 WARNING: region 2:
9417 14:47:00.140085 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9418 14:47:00.143284 WARNING: region 3:
9419 14:47:00.146735 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9420 14:47:00.150079 WARNING: region 4:
9421 14:47:00.156769 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9422 14:47:00.156850 WARNING: region 5:
9423 14:47:00.159722 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9424 14:47:00.163527 WARNING: region 6:
9425 14:47:00.166412 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9426 14:47:00.169610 WARNING: region 7:
9427 14:47:00.173527 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9428 14:47:00.179760 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9429 14:47:00.183005 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9430 14:47:00.189438 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9431 14:47:00.192551 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9432 14:47:00.196349 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9433 14:47:00.202576 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9434 14:47:00.206039 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9435 14:47:00.209222 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9436 14:47:00.215879 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9437 14:47:00.219269 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9438 14:47:00.225468 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9439 14:47:00.229060 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9440 14:47:00.232048 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9441 14:47:00.238695 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9442 14:47:00.241923 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9443 14:47:00.248600 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9444 14:47:00.251662 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9445 14:47:00.255293 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9446 14:47:00.262218 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9447 14:47:00.265178 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9448 14:47:00.271710 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9449 14:47:00.275002 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9450 14:47:00.277909 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9451 14:47:00.284838 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9452 14:47:00.288147 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9453 14:47:00.294566 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9454 14:47:00.297895 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9455 14:47:00.301772 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9456 14:47:00.308127 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9457 14:47:00.311422 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9458 14:47:00.318198 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9459 14:47:00.321021 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9460 14:47:00.324182 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9461 14:47:00.331243 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9462 14:47:00.334233 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9463 14:47:00.337283 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9464 14:47:00.340664 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9465 14:47:00.348029 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9466 14:47:00.350604 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9467 14:47:00.354306 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9468 14:47:00.357028 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9469 14:47:00.363732 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9470 14:47:00.367184 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9471 14:47:00.370659 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9472 14:47:00.373815 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9473 14:47:00.382330 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9474 14:47:00.383900 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9475 14:47:00.387391 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9476 14:47:00.393499 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9477 14:47:00.396802 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9478 14:47:00.403404 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9479 14:47:00.406677 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9480 14:47:00.410233 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9481 14:47:00.417185 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9482 14:47:00.420097 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9483 14:47:00.426573 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9484 14:47:00.430030 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9485 14:47:00.436348 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9486 14:47:00.439715 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9487 14:47:00.446371 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9488 14:47:00.449536 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9489 14:47:00.453096 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9490 14:47:00.459542 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9491 14:47:00.463002 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9492 14:47:00.469734 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9493 14:47:00.472463 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9494 14:47:00.479169 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9495 14:47:00.482650 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9496 14:47:00.489132 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9497 14:47:00.492261 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9498 14:47:00.496216 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9499 14:47:00.502309 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9500 14:47:00.505546 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9501 14:47:00.512761 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9502 14:47:00.515699 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9503 14:47:00.522226 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9504 14:47:00.525463 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9505 14:47:00.531758 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9506 14:47:00.535316 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9507 14:47:00.541866 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9508 14:47:00.544992 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9509 14:47:00.551949 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9510 14:47:00.555512 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9511 14:47:00.558101 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9512 14:47:00.564426 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9513 14:47:00.567904 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9514 14:47:00.574648 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9515 14:47:00.577972 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9516 14:47:00.584609 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9517 14:47:00.588169 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9518 14:47:00.594447 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9519 14:47:00.598057 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9520 14:47:00.601029 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9521 14:47:00.607658 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9522 14:47:00.610829 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9523 14:47:00.617441 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9524 14:47:00.620644 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9525 14:47:00.623892 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9526 14:47:00.630892 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9527 14:47:00.633874 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9528 14:47:00.636947 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9529 14:47:00.643828 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9530 14:47:00.646919 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9531 14:47:00.650397 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9532 14:47:00.657152 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9533 14:47:00.660012 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9534 14:47:00.667180 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9535 14:47:00.670444 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9536 14:47:00.674213 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9537 14:47:00.680390 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9538 14:47:00.683916 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9539 14:47:00.690014 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9540 14:47:00.693253 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9541 14:47:00.700063 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9542 14:47:00.703204 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9543 14:47:00.706570 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9544 14:47:00.710046 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9545 14:47:00.717091 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9546 14:47:00.719636 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9547 14:47:00.722766 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9548 14:47:00.729426 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9549 14:47:00.732667 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9550 14:47:00.736164 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9551 14:47:00.742512 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9552 14:47:00.745889 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9553 14:47:00.749239 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9554 14:47:00.756519 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9555 14:47:00.759448 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9556 14:47:00.765603 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9557 14:47:00.768927 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9558 14:47:00.772089 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9559 14:47:00.778957 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9560 14:47:00.781999 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9561 14:47:00.788892 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9562 14:47:00.792542 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9563 14:47:00.795948 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9564 14:47:00.802062 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9565 14:47:00.805828 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9566 14:47:00.811824 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9567 14:47:00.815173 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9568 14:47:00.818362 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9569 14:47:00.824880 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9570 14:47:00.828601 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9571 14:47:00.835154 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9572 14:47:00.838750 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9573 14:47:00.841960 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9574 14:47:00.848291 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9575 14:47:00.851572 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9576 14:47:00.858255 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9577 14:47:00.861430 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9578 14:47:00.864881 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9579 14:47:00.871289 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9580 14:47:00.874535 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9581 14:47:00.881553 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9582 14:47:00.885265 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9583 14:47:00.887851 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9584 14:47:00.894948 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9585 14:47:00.897618 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9586 14:47:00.904719 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9587 14:47:00.907387 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9588 14:47:00.910536 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9589 14:47:00.917225 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9590 14:47:00.920754 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9591 14:47:00.927565 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9592 14:47:00.930785 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9593 14:47:00.933904 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9594 14:47:00.940521 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9595 14:47:00.944381 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9596 14:47:00.950927 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9597 14:47:00.953509 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9598 14:47:00.957451 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9599 14:47:00.963677 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9600 14:47:00.967051 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9601 14:47:00.973528 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9602 14:47:00.976747 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9603 14:47:00.980382 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9604 14:47:00.986760 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9605 14:47:00.990191 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9606 14:47:00.996462 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9607 14:47:00.999736 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9608 14:47:01.003062 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9609 14:47:01.009663 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9610 14:47:01.012804 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9611 14:47:01.019391 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9612 14:47:01.022799 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9613 14:47:01.026395 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9614 14:47:01.032490 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9615 14:47:01.036001 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9616 14:47:01.043082 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9617 14:47:01.046642 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9618 14:47:01.053088 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9619 14:47:01.056213 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9620 14:47:01.059501 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9621 14:47:01.065711 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9622 14:47:01.069261 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9623 14:47:01.075746 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9624 14:47:01.079141 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9625 14:47:01.085594 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9626 14:47:01.088787 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9627 14:47:01.091680 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9628 14:47:01.098418 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9629 14:47:01.101571 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9630 14:47:01.108363 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9631 14:47:01.111493 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9632 14:47:01.118073 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9633 14:47:01.121679 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9634 14:47:01.124967 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9635 14:47:01.131437 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9636 14:47:01.134704 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9637 14:47:01.141011 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9638 14:47:01.144472 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9639 14:47:01.151155 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9640 14:47:01.154299 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9641 14:47:01.157418 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9642 14:47:01.164262 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9643 14:47:01.167399 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9644 14:47:01.174352 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9645 14:47:01.177706 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9646 14:47:01.184004 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9647 14:47:01.187710 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9648 14:47:01.190563 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9649 14:47:01.197196 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9650 14:47:01.200821 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9651 14:47:01.206975 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9652 14:47:01.210284 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9653 14:47:01.216896 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9654 14:47:01.220609 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9655 14:47:01.223807 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9656 14:47:01.229855 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9657 14:47:01.233548 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9658 14:47:01.236753 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9659 14:47:01.239999 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9660 14:47:01.246655 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9661 14:47:01.249976 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9662 14:47:01.252943 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9663 14:47:01.259692 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9664 14:47:01.263095 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9665 14:47:01.269421 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9666 14:47:01.273220 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9667 14:47:01.276031 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9668 14:47:01.283077 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9669 14:47:01.285786 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9670 14:47:01.289143 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9671 14:47:01.295949 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9672 14:47:01.299035 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9673 14:47:01.305997 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9674 14:47:01.309418 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9675 14:47:01.312307 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9676 14:47:01.318957 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9677 14:47:01.322165 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9678 14:47:01.325383 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9679 14:47:01.331947 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9680 14:47:01.335253 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9681 14:47:01.338744 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9682 14:47:01.345534 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9683 14:47:01.348889 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9684 14:47:01.355444 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9685 14:47:01.358494 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9686 14:47:01.362078 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9687 14:47:01.368367 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9688 14:47:01.372153 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9689 14:47:01.378046 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9690 14:47:01.381626 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9691 14:47:01.384505 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9692 14:47:01.391206 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9693 14:47:01.394850 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9694 14:47:01.401001 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9695 14:47:01.404692 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9696 14:47:01.407852 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9697 14:47:01.410792 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9698 14:47:01.417388 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9699 14:47:01.421235 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9700 14:47:01.424295 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9701 14:47:01.427673 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9702 14:47:01.433958 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9703 14:47:01.437275 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9704 14:47:01.441151 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9705 14:47:01.444299 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9706 14:47:01.451385 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9707 14:47:01.454247 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9708 14:47:01.457244 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9709 14:47:01.460745 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9710 14:47:01.467186 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9711 14:47:01.470779 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9712 14:47:01.476851 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9713 14:47:01.480062 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9714 14:47:01.487507 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9715 14:47:01.490209 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9716 14:47:01.496896 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9717 14:47:01.500553 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9718 14:47:01.503484 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9719 14:47:01.509929 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9720 14:47:01.512936 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9721 14:47:01.520054 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9722 14:47:01.523260 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9723 14:47:01.529263 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9724 14:47:01.532681 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9725 14:47:01.536509 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9726 14:47:01.542501 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9727 14:47:01.546078 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9728 14:47:01.553018 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9729 14:47:01.556044 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9730 14:47:01.559117 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9731 14:47:01.565872 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9732 14:47:01.569095 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9733 14:47:01.575844 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9734 14:47:01.579111 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9735 14:47:01.582485 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9736 14:47:01.588823 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9737 14:47:01.592239 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9738 14:47:01.598837 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9739 14:47:01.602183 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9740 14:47:01.608725 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9741 14:47:01.612023 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9742 14:47:01.615552 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9743 14:47:01.622195 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9744 14:47:01.625411 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9745 14:47:01.631756 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9746 14:47:01.635255 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9747 14:47:01.641923 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9748 14:47:01.645383 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9749 14:47:01.648134 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9750 14:47:01.655381 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9751 14:47:01.657927 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9752 14:47:01.665123 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9753 14:47:01.668399 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9754 14:47:01.671521 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9755 14:47:01.678002 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9756 14:47:01.681565 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9757 14:47:01.687610 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9758 14:47:01.691115 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9759 14:47:01.694491 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9760 14:47:01.701191 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9761 14:47:01.704437 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9762 14:47:01.711144 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9763 14:47:01.714139 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9764 14:47:01.721213 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9765 14:47:01.723842 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9766 14:47:01.727403 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9767 14:47:01.733880 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9768 14:47:01.737154 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9769 14:47:01.743936 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9770 14:47:01.747350 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9771 14:47:01.753873 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9772 14:47:01.756911 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9773 14:47:01.760480 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9774 14:47:01.766776 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9775 14:47:01.769898 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9776 14:47:01.776626 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9777 14:47:01.780388 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9778 14:47:01.783353 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9779 14:47:01.789954 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9780 14:47:01.793788 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9781 14:47:01.800282 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9782 14:47:01.803421 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9783 14:47:01.809751 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9784 14:47:01.812943 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9785 14:47:01.819502 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9786 14:47:01.823334 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9787 14:47:01.825967 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9788 14:47:01.832980 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9789 14:47:01.835620 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9790 14:47:01.842360 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9791 14:47:01.846085 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9792 14:47:01.852201 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9793 14:47:01.856149 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9794 14:47:01.862453 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9795 14:47:01.866053 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9796 14:47:01.869036 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9797 14:47:01.875565 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9798 14:47:01.879935 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9799 14:47:01.885321 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9800 14:47:01.888342 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9801 14:47:01.895137 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9802 14:47:01.898782 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9803 14:47:01.904889 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9804 14:47:01.908326 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9805 14:47:01.911573 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9806 14:47:01.918124 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9807 14:47:01.921605 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9808 14:47:01.928132 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9809 14:47:01.931840 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9810 14:47:01.938564 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9811 14:47:01.941174 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9812 14:47:01.947839 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9813 14:47:01.951751 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9814 14:47:01.954739 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9815 14:47:01.961021 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9816 14:47:01.964274 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9817 14:47:01.971395 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9818 14:47:01.974037 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9819 14:47:01.981139 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9820 14:47:01.984982 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9821 14:47:01.990638 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9822 14:47:01.994294 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9823 14:47:01.997449 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9824 14:47:02.003657 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9825 14:47:02.007554 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9826 14:47:02.013558 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9827 14:47:02.017404 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9828 14:47:02.023912 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9829 14:47:02.026717 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9830 14:47:02.030159 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9831 14:47:02.036543 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9832 14:47:02.040021 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9833 14:47:02.046427 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9834 14:47:02.050097 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9835 14:47:02.056377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9836 14:47:02.059826 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9837 14:47:02.066079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9838 14:47:02.070165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9839 14:47:02.076152 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9840 14:47:02.079676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9841 14:47:02.086480 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9842 14:47:02.089607 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9843 14:47:02.095699 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9844 14:47:02.099286 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9845 14:47:02.105727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9846 14:47:02.110014 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9847 14:47:02.116018 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9848 14:47:02.119205 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9849 14:47:02.125793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9850 14:47:02.129022 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9851 14:47:02.135142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9852 14:47:02.138524 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9853 14:47:02.145181 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9854 14:47:02.148273 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9855 14:47:02.154981 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9856 14:47:02.158191 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9857 14:47:02.165898 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9858 14:47:02.168598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9859 14:47:02.174869 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9860 14:47:02.178269 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9861 14:47:02.184873 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9862 14:47:02.188269 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9863 14:47:02.191516 INFO: [APUAPC] vio 0
9864 14:47:02.194837 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9865 14:47:02.201106 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9866 14:47:02.204594 INFO: [APUAPC] D0_APC_0: 0x400510
9867 14:47:02.207829 INFO: [APUAPC] D0_APC_1: 0x0
9868 14:47:02.211156 INFO: [APUAPC] D0_APC_2: 0x1540
9869 14:47:02.211238 INFO: [APUAPC] D0_APC_3: 0x0
9870 14:47:02.214430 INFO: [APUAPC] D1_APC_0: 0xffffffff
9871 14:47:02.220997 INFO: [APUAPC] D1_APC_1: 0xffffffff
9872 14:47:02.224201 INFO: [APUAPC] D1_APC_2: 0x3fffff
9873 14:47:02.224281 INFO: [APUAPC] D1_APC_3: 0x0
9874 14:47:02.228181 INFO: [APUAPC] D2_APC_0: 0xffffffff
9875 14:47:02.230975 INFO: [APUAPC] D2_APC_1: 0xffffffff
9876 14:47:02.234424 INFO: [APUAPC] D2_APC_2: 0x3fffff
9877 14:47:02.237597 INFO: [APUAPC] D2_APC_3: 0x0
9878 14:47:02.240706 INFO: [APUAPC] D3_APC_0: 0xffffffff
9879 14:47:02.244278 INFO: [APUAPC] D3_APC_1: 0xffffffff
9880 14:47:02.248779 INFO: [APUAPC] D3_APC_2: 0x3fffff
9881 14:47:02.250311 INFO: [APUAPC] D3_APC_3: 0x0
9882 14:47:02.254330 INFO: [APUAPC] D4_APC_0: 0xffffffff
9883 14:47:02.257074 INFO: [APUAPC] D4_APC_1: 0xffffffff
9884 14:47:02.260989 INFO: [APUAPC] D4_APC_2: 0x3fffff
9885 14:47:02.263844 INFO: [APUAPC] D4_APC_3: 0x0
9886 14:47:02.266905 INFO: [APUAPC] D5_APC_0: 0xffffffff
9887 14:47:02.270582 INFO: [APUAPC] D5_APC_1: 0xffffffff
9888 14:47:02.273409 INFO: [APUAPC] D5_APC_2: 0x3fffff
9889 14:47:02.276641 INFO: [APUAPC] D5_APC_3: 0x0
9890 14:47:02.280282 INFO: [APUAPC] D6_APC_0: 0xffffffff
9891 14:47:02.283868 INFO: [APUAPC] D6_APC_1: 0xffffffff
9892 14:47:02.286794 INFO: [APUAPC] D6_APC_2: 0x3fffff
9893 14:47:02.290138 INFO: [APUAPC] D6_APC_3: 0x0
9894 14:47:02.293404 INFO: [APUAPC] D7_APC_0: 0xffffffff
9895 14:47:02.296837 INFO: [APUAPC] D7_APC_1: 0xffffffff
9896 14:47:02.300217 INFO: [APUAPC] D7_APC_2: 0x3fffff
9897 14:47:02.303430 INFO: [APUAPC] D7_APC_3: 0x0
9898 14:47:02.306940 INFO: [APUAPC] D8_APC_0: 0xffffffff
9899 14:47:02.310010 INFO: [APUAPC] D8_APC_1: 0xffffffff
9900 14:47:02.312955 INFO: [APUAPC] D8_APC_2: 0x3fffff
9901 14:47:02.316296 INFO: [APUAPC] D8_APC_3: 0x0
9902 14:47:02.319675 INFO: [APUAPC] D9_APC_0: 0xffffffff
9903 14:47:02.323276 INFO: [APUAPC] D9_APC_1: 0xffffffff
9904 14:47:02.326815 INFO: [APUAPC] D9_APC_2: 0x3fffff
9905 14:47:02.329662 INFO: [APUAPC] D9_APC_3: 0x0
9906 14:47:02.333189 INFO: [APUAPC] D10_APC_0: 0xffffffff
9907 14:47:02.336610 INFO: [APUAPC] D10_APC_1: 0xffffffff
9908 14:47:02.339772 INFO: [APUAPC] D10_APC_2: 0x3fffff
9909 14:47:02.343326 INFO: [APUAPC] D10_APC_3: 0x0
9910 14:47:02.346717 INFO: [APUAPC] D11_APC_0: 0xffffffff
9911 14:47:02.349433 INFO: [APUAPC] D11_APC_1: 0xffffffff
9912 14:47:02.352884 INFO: [APUAPC] D11_APC_2: 0x3fffff
9913 14:47:02.355816 INFO: [APUAPC] D11_APC_3: 0x0
9914 14:47:02.359272 INFO: [APUAPC] D12_APC_0: 0xffffffff
9915 14:47:02.362484 INFO: [APUAPC] D12_APC_1: 0xffffffff
9916 14:47:02.365891 INFO: [APUAPC] D12_APC_2: 0x3fffff
9917 14:47:02.369536 INFO: [APUAPC] D12_APC_3: 0x0
9918 14:47:02.372665 INFO: [APUAPC] D13_APC_0: 0xffffffff
9919 14:47:02.376330 INFO: [APUAPC] D13_APC_1: 0xffffffff
9920 14:47:02.379249 INFO: [APUAPC] D13_APC_2: 0x3fffff
9921 14:47:02.382317 INFO: [APUAPC] D13_APC_3: 0x0
9922 14:47:02.386355 INFO: [APUAPC] D14_APC_0: 0xffffffff
9923 14:47:02.389032 INFO: [APUAPC] D14_APC_1: 0xffffffff
9924 14:47:02.393000 INFO: [APUAPC] D14_APC_2: 0x3fffff
9925 14:47:02.395633 INFO: [APUAPC] D14_APC_3: 0x0
9926 14:47:02.398969 INFO: [APUAPC] D15_APC_0: 0xffffffff
9927 14:47:02.402787 INFO: [APUAPC] D15_APC_1: 0xffffffff
9928 14:47:02.405671 INFO: [APUAPC] D15_APC_2: 0x3fffff
9929 14:47:02.409263 INFO: [APUAPC] D15_APC_3: 0x0
9930 14:47:02.412236 INFO: [APUAPC] APC_CON: 0x4
9931 14:47:02.415929 INFO: [NOCDAPC] D0_APC_0: 0x0
9932 14:47:02.418697 INFO: [NOCDAPC] D0_APC_1: 0x0
9933 14:47:02.422297 INFO: [NOCDAPC] D1_APC_0: 0x0
9934 14:47:02.425233 INFO: [NOCDAPC] D1_APC_1: 0xfff
9935 14:47:02.428698 INFO: [NOCDAPC] D2_APC_0: 0x0
9936 14:47:02.432064 INFO: [NOCDAPC] D2_APC_1: 0xfff
9937 14:47:02.432144 INFO: [NOCDAPC] D3_APC_0: 0x0
9938 14:47:02.435419 INFO: [NOCDAPC] D3_APC_1: 0xfff
9939 14:47:02.438479 INFO: [NOCDAPC] D4_APC_0: 0x0
9940 14:47:02.441619 INFO: [NOCDAPC] D4_APC_1: 0xfff
9941 14:47:02.445219 INFO: [NOCDAPC] D5_APC_0: 0x0
9942 14:47:02.448099 INFO: [NOCDAPC] D5_APC_1: 0xfff
9943 14:47:02.451467 INFO: [NOCDAPC] D6_APC_0: 0x0
9944 14:47:02.455110 INFO: [NOCDAPC] D6_APC_1: 0xfff
9945 14:47:02.458344 INFO: [NOCDAPC] D7_APC_0: 0x0
9946 14:47:02.461933 INFO: [NOCDAPC] D7_APC_1: 0xfff
9947 14:47:02.465086 INFO: [NOCDAPC] D8_APC_0: 0x0
9948 14:47:02.468354 INFO: [NOCDAPC] D8_APC_1: 0xfff
9949 14:47:02.468434 INFO: [NOCDAPC] D9_APC_0: 0x0
9950 14:47:02.471282 INFO: [NOCDAPC] D9_APC_1: 0xfff
9951 14:47:02.474435 INFO: [NOCDAPC] D10_APC_0: 0x0
9952 14:47:02.478473 INFO: [NOCDAPC] D10_APC_1: 0xfff
9953 14:47:02.481029 INFO: [NOCDAPC] D11_APC_0: 0x0
9954 14:47:02.484693 INFO: [NOCDAPC] D11_APC_1: 0xfff
9955 14:47:02.487812 INFO: [NOCDAPC] D12_APC_0: 0x0
9956 14:47:02.492036 INFO: [NOCDAPC] D12_APC_1: 0xfff
9957 14:47:02.494800 INFO: [NOCDAPC] D13_APC_0: 0x0
9958 14:47:02.497870 INFO: [NOCDAPC] D13_APC_1: 0xfff
9959 14:47:02.501320 INFO: [NOCDAPC] D14_APC_0: 0x0
9960 14:47:02.504163 INFO: [NOCDAPC] D14_APC_1: 0xfff
9961 14:47:02.507718 INFO: [NOCDAPC] D15_APC_0: 0x0
9962 14:47:02.510739 INFO: [NOCDAPC] D15_APC_1: 0xfff
9963 14:47:02.514609 INFO: [NOCDAPC] APC_CON: 0x4
9964 14:47:02.517545 INFO: [APUAPC] set_apusys_apc done
9965 14:47:02.520657 INFO: [DEVAPC] devapc_init done
9966 14:47:02.524281 INFO: GICv3 without legacy support detected.
9967 14:47:02.527322 INFO: ARM GICv3 driver initialized in EL3
9968 14:47:02.530941 INFO: Maximum SPI INTID supported: 639
9969 14:47:02.533606 INFO: BL31: Initializing runtime services
9970 14:47:02.540575 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9971 14:47:02.543304 INFO: SPM: enable CPC mode
9972 14:47:02.550285 INFO: mcdi ready for mcusys-off-idle and system suspend
9973 14:47:02.554052 INFO: BL31: Preparing for EL3 exit to normal world
9974 14:47:02.557313 INFO: Entry point address = 0x80000000
9975 14:47:02.560068 INFO: SPSR = 0x8
9976 14:47:02.564923
9977 14:47:02.565005
9978 14:47:02.565069
9979 14:47:02.568592 Starting depthcharge on Spherion...
9980 14:47:02.568672
9981 14:47:02.568734 Wipe memory regions:
9982 14:47:02.568792
9983 14:47:02.569430 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
9984 14:47:02.569528 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
9985 14:47:02.569608 Setting prompt string to ['asurada:']
9986 14:47:02.569684 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
9987 14:47:02.571426 [0x00000040000000, 0x00000054600000)
9988 14:47:02.694080
9989 14:47:02.694216 [0x00000054660000, 0x00000080000000)
9990 14:47:02.954515
9991 14:47:02.954658 [0x000000821a7280, 0x000000ffe64000)
9992 14:47:03.699807
9993 14:47:03.699955 [0x00000100000000, 0x00000240000000)
9994 14:47:05.589654
9995 14:47:05.592594 Initializing XHCI USB controller at 0x11200000.
9996 14:47:06.631255
9997 14:47:06.634224 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9998 14:47:06.634341
9999 14:47:06.634436
10000 14:47:06.634765 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10002 14:47:06.735176 asurada: tftpboot 192.168.201.1 14167035/tftp-deploy-3rgjmpmz/kernel/image.itb 14167035/tftp-deploy-3rgjmpmz/kernel/cmdline
10003 14:47:06.735384 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10004 14:47:06.735507 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10005 14:47:06.739511 tftpboot 192.168.201.1 14167035/tftp-deploy-3rgjmpmz/kernel/image.ittp-deploy-3rgjmpmz/kernel/cmdline
10006 14:47:06.739625
10007 14:47:06.739723 Waiting for link
10008 14:47:06.897693
10009 14:47:06.897912 R8152: Initializing
10010 14:47:06.898012
10011 14:47:06.901098 Version 6 (ocp_data = 5c30)
10012 14:47:06.901209
10013 14:47:06.904833 R8152: Done initializing
10014 14:47:06.904941
10015 14:47:06.905039 Adding net device
10016 14:47:08.872634
10017 14:47:08.872828 done.
10018 14:47:08.872935
10019 14:47:08.873031 MAC: 00:24:32:30:7c:7b
10020 14:47:08.873124
10021 14:47:08.875771 Sending DHCP discover... done.
10022 14:47:08.875882
10023 14:47:08.878808 Waiting for reply... done.
10024 14:47:08.878919
10025 14:47:08.882469 Sending DHCP request... done.
10026 14:47:08.882578
10027 14:47:08.888435 Waiting for reply... done.
10028 14:47:08.888549
10029 14:47:08.888644 My ip is 192.168.201.14
10030 14:47:08.888735
10031 14:47:08.891422 The DHCP server ip is 192.168.201.1
10032 14:47:08.891529
10033 14:47:08.897581 TFTP server IP predefined by user: 192.168.201.1
10034 14:47:08.897694
10035 14:47:08.904285 Bootfile predefined by user: 14167035/tftp-deploy-3rgjmpmz/kernel/image.itb
10036 14:47:08.904398
10037 14:47:08.907274 Sending tftp read request... done.
10038 14:47:08.907383
10039 14:47:08.911491 Waiting for the transfer...
10040 14:47:08.911605
10041 14:47:09.480536 00000000 ################################################################
10042 14:47:09.480672
10043 14:47:10.047939 00080000 ################################################################
10044 14:47:10.048084
10045 14:47:10.615197 00100000 ################################################################
10046 14:47:10.615346
10047 14:47:11.180082 00180000 ################################################################
10048 14:47:11.180228
10049 14:47:11.745423 00200000 ################################################################
10050 14:47:11.745577
10051 14:47:12.306124 00280000 ################################################################
10052 14:47:12.306280
10053 14:47:12.877636 00300000 ################################################################
10054 14:47:12.877797
10055 14:47:13.451867 00380000 ################################################################
10056 14:47:13.452020
10057 14:47:14.019621 00400000 ################################################################
10058 14:47:14.019780
10059 14:47:14.617015 00480000 ################################################################
10060 14:47:14.617174
10061 14:47:15.168362 00500000 ################################################################
10062 14:47:15.168517
10063 14:47:15.733130 00580000 ################################################################
10064 14:47:15.733325
10065 14:47:16.293655 00600000 ################################################################
10066 14:47:16.293814
10067 14:47:16.867004 00680000 ################################################################
10068 14:47:16.867203
10069 14:47:17.411238 00700000 ################################################################
10070 14:47:17.411408
10071 14:47:17.947177 00780000 ################################################################
10072 14:47:17.947336
10073 14:47:18.515197 00800000 ################################################################
10074 14:47:18.515353
10075 14:47:19.088190 00880000 ################################################################
10076 14:47:19.088348
10077 14:47:19.626230 00900000 ################################################################
10078 14:47:19.626386
10079 14:47:20.199130 00980000 ################################################################
10080 14:47:20.199284
10081 14:47:20.761624 00a00000 ################################################################
10082 14:47:20.761782
10083 14:47:21.295258 00a80000 ################################################################
10084 14:47:21.295417
10085 14:47:21.824906 00b00000 ################################################################
10086 14:47:21.825059
10087 14:47:22.360175 00b80000 ################################################################
10088 14:47:22.360329
10089 14:47:22.900497 00c00000 ################################################################
10090 14:47:22.900651
10091 14:47:23.424762 00c80000 ################################################################
10092 14:47:23.424913
10093 14:47:23.947947 00d00000 ################################################################
10094 14:47:23.948154
10095 14:47:24.483472 00d80000 ################################################################
10096 14:47:24.483639
10097 14:47:25.041570 00e00000 ################################################################
10098 14:47:25.041730
10099 14:47:25.638457 00e80000 ################################################################
10100 14:47:25.638611
10101 14:47:26.301071 00f00000 ################################################################
10102 14:47:26.301631
10103 14:47:26.995646 00f80000 ################################################################
10104 14:47:26.996173
10105 14:47:27.633844 01000000 ################################################################
10106 14:47:27.634002
10107 14:47:28.289188 01080000 ################################################################
10108 14:47:28.289917
10109 14:47:28.956278 01100000 ################################################################
10110 14:47:28.956428
10111 14:47:29.651197 01180000 ################################################################
10112 14:47:29.651748
10113 14:47:30.341300 01200000 ################################################################
10114 14:47:30.341884
10115 14:47:31.043944 01280000 ################################################################
10116 14:47:31.044453
10117 14:47:31.750143 01300000 ################################################################
10118 14:47:31.750645
10119 14:47:32.444390 01380000 ################################################################
10120 14:47:32.444900
10121 14:47:33.124192 01400000 ################################################################
10122 14:47:33.124335
10123 14:47:33.805141 01480000 ################################################################
10124 14:47:33.805387
10125 14:47:34.462281 01500000 ################################################################
10126 14:47:34.462787
10127 14:47:35.148085 01580000 ################################################################
10128 14:47:35.148723
10129 14:47:35.823496 01600000 ################################################################
10130 14:47:35.824062
10131 14:47:36.502676 01680000 ################################################################
10132 14:47:36.503312
10133 14:47:37.186757 01700000 ################################################################
10134 14:47:37.187297
10135 14:47:37.828167 01780000 ################################################################
10136 14:47:37.828682
10137 14:47:38.439883 01800000 ################################################################
10138 14:47:38.440069
10139 14:47:39.083691 01880000 ################################################################
10140 14:47:39.084270
10141 14:47:39.771016 01900000 ################################################################
10142 14:47:39.771525
10143 14:47:40.468831 01980000 ################################################################
10144 14:47:40.469372
10145 14:47:41.128088 01a00000 ################################################################
10146 14:47:41.128596
10147 14:47:41.817726 01a80000 ################################################################
10148 14:47:41.818235
10149 14:47:42.471507 01b00000 ################################################################
10150 14:47:42.471716
10151 14:47:42.986206 01b80000 ################################################################
10152 14:47:42.986347
10153 14:47:43.508841 01c00000 ################################################################
10154 14:47:43.508983
10155 14:47:44.022152 01c80000 ################################################################
10156 14:47:44.022301
10157 14:47:44.554699 01d00000 ################################################################
10158 14:47:44.554843
10159 14:47:45.093116 01d80000 ################################################################
10160 14:47:45.093325
10161 14:47:45.607722 01e00000 ################################################################
10162 14:47:45.607868
10163 14:47:46.121822 01e80000 ################################################################
10164 14:47:46.121967
10165 14:47:46.636374 01f00000 ################################################################
10166 14:47:46.636520
10167 14:47:47.153741 01f80000 ################################################################
10168 14:47:47.153925
10169 14:47:47.668455 02000000 ################################################################
10170 14:47:47.668597
10171 14:47:48.186790 02080000 ################################################################
10172 14:47:48.186934
10173 14:47:48.699864 02100000 ################################################################
10174 14:47:48.700009
10175 14:47:49.214594 02180000 ################################################################
10176 14:47:49.214768
10177 14:47:49.729915 02200000 ################################################################
10178 14:47:49.730052
10179 14:47:50.251610 02280000 ################################################################
10180 14:47:50.251741
10181 14:47:50.927117 02300000 ################################################################
10182 14:47:50.927611
10183 14:47:51.623420 02380000 ################################################################
10184 14:47:51.623931
10185 14:47:52.327516 02400000 ################################################################
10186 14:47:52.328065
10187 14:47:53.024687 02480000 ################################################################
10188 14:47:53.025206
10189 14:47:53.705198 02500000 ################################################################
10190 14:47:53.705725
10191 14:47:54.379408 02580000 ################################################################
10192 14:47:54.379895
10193 14:47:55.033113 02600000 ################################################################
10194 14:47:55.033295
10195 14:47:55.643625 02680000 ################################################################
10196 14:47:55.644108
10197 14:47:56.305875 02700000 ################################################################
10198 14:47:56.306011
10199 14:47:56.965848 02780000 ################################################################
10200 14:47:56.966411
10201 14:47:57.644793 02800000 ################################################################
10202 14:47:57.644923
10203 14:47:58.264430 02880000 ################################################################
10204 14:47:58.264577
10205 14:47:58.945133 02900000 ################################################################
10206 14:47:58.945667
10207 14:47:59.576005 02980000 ################################################################
10208 14:47:59.576148
10209 14:48:00.179971 02a00000 ################################################################
10210 14:48:00.180139
10211 14:48:00.720949 02a80000 ################################################################
10212 14:48:00.721114
10213 14:48:01.248788 02b00000 ################################################################
10214 14:48:01.248954
10215 14:48:01.777142 02b80000 ################################################################
10216 14:48:01.777333
10217 14:48:02.322006 02c00000 ################################################################
10218 14:48:02.322165
10219 14:48:02.884557 02c80000 ################################################################
10220 14:48:02.884690
10221 14:48:03.426002 02d00000 ################################################################
10222 14:48:03.426144
10223 14:48:03.965593 02d80000 ################################################################
10224 14:48:03.965765
10225 14:48:04.511232 02e00000 ################################################################
10226 14:48:04.511363
10227 14:48:05.070869 02e80000 ################################################################
10228 14:48:05.071008
10229 14:48:05.614345 02f00000 ################################################################
10230 14:48:05.614494
10231 14:48:06.161730 02f80000 ################################################################
10232 14:48:06.161892
10233 14:48:06.701396 03000000 ################################################################
10234 14:48:06.701537
10235 14:48:07.246809 03080000 ################################################################
10236 14:48:07.246940
10237 14:48:07.822799 03100000 ################################################################
10238 14:48:07.822931
10239 14:48:08.372840 03180000 ################################################################
10240 14:48:08.372974
10241 14:48:08.935826 03200000 ################################################################
10242 14:48:08.935968
10243 14:48:09.508773 03280000 ################################################################
10244 14:48:09.508939
10245 14:48:10.066629 03300000 ################################################################
10246 14:48:10.066796
10247 14:48:10.645081 03380000 ################################################################
10248 14:48:10.645229
10249 14:48:11.197101 03400000 ################################################################
10250 14:48:11.197287
10251 14:48:11.729204 03480000 ################################################################
10252 14:48:11.729341
10253 14:48:12.270955 03500000 ################################################################
10254 14:48:12.271091
10255 14:48:12.829580 03580000 ################################################################
10256 14:48:12.829729
10257 14:48:13.367543 03600000 ################################################################
10258 14:48:13.367695
10259 14:48:13.905529 03680000 ################################################################
10260 14:48:13.905685
10261 14:48:14.455075 03700000 ################################################################
10262 14:48:14.455228
10263 14:48:14.995012 03780000 ################################################################
10264 14:48:14.995169
10265 14:48:15.548675 03800000 ################################################################
10266 14:48:15.548830
10267 14:48:16.115699 03880000 ################################################################
10268 14:48:16.115863
10269 14:48:16.667417 03900000 ################################################################
10270 14:48:16.667566
10271 14:48:17.242181 03980000 ################################################################
10272 14:48:17.242332
10273 14:48:17.805976 03a00000 ################################################################
10274 14:48:17.806128
10275 14:48:18.381628 03a80000 ################################################################
10276 14:48:18.381780
10277 14:48:18.946845 03b00000 ################################################################
10278 14:48:18.946980
10279 14:48:19.504465 03b80000 ################################################################
10280 14:48:19.504602
10281 14:48:20.058124 03c00000 ################################################################
10282 14:48:20.058262
10283 14:48:20.616954 03c80000 ################################################################
10284 14:48:20.617090
10285 14:48:21.199390 03d00000 ################################################################
10286 14:48:21.199528
10287 14:48:21.863778 03d80000 ################################################################
10288 14:48:21.864232
10289 14:48:22.507198 03e00000 ################################################################
10290 14:48:22.507808
10291 14:48:23.211986 03e80000 ################################################################
10292 14:48:23.212482
10293 14:48:23.909203 03f00000 ################################################################
10294 14:48:23.909726
10295 14:48:24.617343 03f80000 ################################################################
10296 14:48:24.617844
10297 14:48:25.325183 04000000 ################################################################
10298 14:48:25.325721
10299 14:48:26.036218 04080000 ################################################################
10300 14:48:26.036726
10301 14:48:26.723969 04100000 ################################################################
10302 14:48:26.724479
10303 14:48:27.385604 04180000 ################################################################
10304 14:48:27.385748
10305 14:48:27.975954 04200000 ################################################################
10306 14:48:27.976103
10307 14:48:28.539567 04280000 ################################################################
10308 14:48:28.539717
10309 14:48:29.172703 04300000 ################################################################
10310 14:48:29.173421
10311 14:48:29.831882 04380000 ################################################################
10312 14:48:29.832385
10313 14:48:30.513475 04400000 ################################################################
10314 14:48:30.513791
10315 14:48:31.164107 04480000 ################################################################
10316 14:48:31.164759
10317 14:48:31.834083 04500000 ################################################################
10318 14:48:31.834566
10319 14:48:32.514179 04580000 ################################################################
10320 14:48:32.514324
10321 14:48:33.247473 04600000 ################################################################
10322 14:48:33.247615
10323 14:48:33.498865 04680000 ###################### done.
10324 14:48:33.499006
10325 14:48:33.502893 The bootfile was 74103818 bytes long.
10326 14:48:33.502972
10327 14:48:33.505980 Sending tftp read request... done.
10328 14:48:33.506061
10329 14:48:33.506125 Waiting for the transfer...
10330 14:48:33.506184
10331 14:48:33.509228 00000000 # done.
10332 14:48:33.509333
10333 14:48:33.515760 Command line loaded dynamically from TFTP file: 14167035/tftp-deploy-3rgjmpmz/kernel/cmdline
10334 14:48:33.515837
10335 14:48:33.529084 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10336 14:48:33.529224
10337 14:48:33.532826 Loading FIT.
10338 14:48:33.533223
10339 14:48:33.535995 Image ramdisk-1 has 60993907 bytes.
10340 14:48:33.536408
10341 14:48:33.536733 Image fdt-1 has 47258 bytes.
10342 14:48:33.537037
10343 14:48:33.539412 Image kernel-1 has 13060619 bytes.
10344 14:48:33.539827
10345 14:48:33.549356 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10346 14:48:33.549834
10347 14:48:33.565817 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10348 14:48:33.566289
10349 14:48:33.573034 Choosing best match conf-1 for compat google,spherion-rev2.
10350 14:48:33.576464
10351 14:48:33.581405 Connected to device vid:did:rid of 1ae0:0028:00
10352 14:48:33.588221
10353 14:48:33.591267 tpm_get_response: command 0x17b, return code 0x0
10354 14:48:33.591681
10355 14:48:33.594671 ec_init: CrosEC protocol v3 supported (256, 248)
10356 14:48:33.598812
10357 14:48:33.602220 tpm_cleanup: add release locality here.
10358 14:48:33.602607
10359 14:48:33.602982 Shutting down all USB controllers.
10360 14:48:33.605853
10361 14:48:33.606393 Removing current net device
10362 14:48:33.606846
10363 14:48:33.612201 Exiting depthcharge with code 4 at timestamp: 120242145
10364 14:48:33.613021
10365 14:48:33.615837 LZMA decompressing kernel-1 to 0x821a6718
10366 14:48:33.616272
10367 14:48:33.618977 LZMA decompressing kernel-1 to 0x40000000
10368 14:48:35.230715
10369 14:48:35.231263 jumping to kernel
10370 14:48:35.233443 end: 2.2.4 bootloader-commands (duration 00:01:33) [common]
10371 14:48:35.234227 start: 2.2.5 auto-login-action (timeout 00:02:54) [common]
10372 14:48:35.234766 Setting prompt string to ['Linux version [0-9]']
10373 14:48:35.235302 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10374 14:48:35.235875 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10375 14:48:35.312175
10376 14:48:35.315780 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10377 14:48:35.319192 start: 2.2.5.1 login-action (timeout 00:02:54) [common]
10378 14:48:35.319674 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10379 14:48:35.320161 Setting prompt string to []
10380 14:48:35.320664 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10381 14:48:35.321038 Using line separator: #'\n'#
10382 14:48:35.321377 No login prompt set.
10383 14:48:35.321712 Parsing kernel messages
10384 14:48:35.321998 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10385 14:48:35.322513 [login-action] Waiting for messages, (timeout 00:02:54)
10386 14:48:35.322842 Waiting using forced prompt support (timeout 00:01:27)
10387 14:48:35.338959 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j216541-arm64-gcc-10-defconfig-arm64-chromebook-f7c97) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024
10388 14:48:35.341540 [ 0.000000] random: crng init done
10389 14:48:35.348611 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10390 14:48:35.351345 [ 0.000000] efi: UEFI not found.
10391 14:48:35.358130 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10392 14:48:35.364894 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10393 14:48:35.374765 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10394 14:48:35.384769 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10395 14:48:35.391840 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10396 14:48:35.398078 [ 0.000000] printk: bootconsole [mtk8250] enabled
10397 14:48:35.404676 [ 0.000000] NUMA: No NUMA configuration found
10398 14:48:35.411212 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10399 14:48:35.414421 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10400 14:48:35.417583 [ 0.000000] Zone ranges:
10401 14:48:35.424174 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10402 14:48:35.429428 [ 0.000000] DMA32 empty
10403 14:48:35.434554 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10404 14:48:35.437759 [ 0.000000] Movable zone start for each node
10405 14:48:35.441444 [ 0.000000] Early memory node ranges
10406 14:48:35.447476 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10407 14:48:35.454057 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10408 14:48:35.461118 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10409 14:48:35.467325 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10410 14:48:35.470758 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10411 14:48:35.480665 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10412 14:48:35.536407 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10413 14:48:35.543342 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10414 14:48:35.549720 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10415 14:48:35.553294 [ 0.000000] psci: probing for conduit method from DT.
10416 14:48:35.559531 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10417 14:48:35.562934 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10418 14:48:35.569792 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10419 14:48:35.573239 [ 0.000000] psci: SMC Calling Convention v1.2
10420 14:48:35.579538 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10421 14:48:35.582795 [ 0.000000] Detected VIPT I-cache on CPU0
10422 14:48:35.589230 [ 0.000000] CPU features: detected: GIC system register CPU interface
10423 14:48:35.595789 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10424 14:48:35.602727 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10425 14:48:35.609213 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10426 14:48:35.618992 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10427 14:48:35.625683 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10428 14:48:35.628600 [ 0.000000] alternatives: applying boot alternatives
10429 14:48:35.635881 [ 0.000000] Fallback order for Node 0: 0
10430 14:48:35.641870 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10431 14:48:35.645381 [ 0.000000] Policy zone: Normal
10432 14:48:35.658798 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10433 14:48:35.668432 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10434 14:48:35.681294 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10435 14:48:35.691499 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10436 14:48:35.697605 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10437 14:48:35.701234 <6>[ 0.000000] software IO TLB: area num 8.
10438 14:48:35.757631 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10439 14:48:35.907137 <6>[ 0.000000] Memory: 7904624K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 448144K reserved, 32768K cma-reserved)
10440 14:48:35.913908 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10441 14:48:35.920224 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10442 14:48:35.923677 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10443 14:48:35.930315 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10444 14:48:35.936637 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10445 14:48:35.940243 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10446 14:48:35.950462 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10447 14:48:35.957126 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10448 14:48:35.963232 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10449 14:48:35.969850 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10450 14:48:35.973510 <6>[ 0.000000] GICv3: 608 SPIs implemented
10451 14:48:35.976795 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10452 14:48:35.983069 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10453 14:48:35.987053 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10454 14:48:35.993353 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10455 14:48:36.006196 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10456 14:48:36.019421 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10457 14:48:36.026028 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10458 14:48:36.033811 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10459 14:48:36.046943 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10460 14:48:36.053847 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10461 14:48:36.060259 <6>[ 0.009182] Console: colour dummy device 80x25
10462 14:48:36.070449 <6>[ 0.013910] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10463 14:48:36.076637 <6>[ 0.024417] pid_max: default: 32768 minimum: 301
10464 14:48:36.079953 <6>[ 0.029289] LSM: Security Framework initializing
10465 14:48:36.086746 <6>[ 0.034225] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10466 14:48:36.097093 <6>[ 0.042038] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10467 14:48:36.103163 <6>[ 0.051517] cblist_init_generic: Setting adjustable number of callback queues.
10468 14:48:36.109880 <6>[ 0.058960] cblist_init_generic: Setting shift to 3 and lim to 1.
10469 14:48:36.120041 <6>[ 0.065300] cblist_init_generic: Setting adjustable number of callback queues.
10470 14:48:36.126564 <6>[ 0.072726] cblist_init_generic: Setting shift to 3 and lim to 1.
10471 14:48:36.129909 <6>[ 0.079127] rcu: Hierarchical SRCU implementation.
10472 14:48:36.136484 <6>[ 0.084142] rcu: Max phase no-delay instances is 1000.
10473 14:48:36.142951 <6>[ 0.091164] EFI services will not be available.
10474 14:48:36.146505 <6>[ 0.096123] smp: Bringing up secondary CPUs ...
10475 14:48:36.154658 <6>[ 0.101168] Detected VIPT I-cache on CPU1
10476 14:48:36.161069 <6>[ 0.101241] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10477 14:48:36.168059 <6>[ 0.101273] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10478 14:48:36.171110 <6>[ 0.101608] Detected VIPT I-cache on CPU2
10479 14:48:36.180949 <6>[ 0.101658] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10480 14:48:36.187539 <6>[ 0.101674] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10481 14:48:36.190828 <6>[ 0.101931] Detected VIPT I-cache on CPU3
10482 14:48:36.197334 <6>[ 0.101978] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10483 14:48:36.203921 <6>[ 0.101992] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10484 14:48:36.207652 <6>[ 0.102297] CPU features: detected: Spectre-v4
10485 14:48:36.214198 <6>[ 0.102303] CPU features: detected: Spectre-BHB
10486 14:48:36.217561 <6>[ 0.102308] Detected PIPT I-cache on CPU4
10487 14:48:36.224319 <6>[ 0.102363] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10488 14:48:36.231560 <6>[ 0.102379] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10489 14:48:36.236923 <6>[ 0.102670] Detected PIPT I-cache on CPU5
10490 14:48:36.243422 <6>[ 0.102733] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10491 14:48:36.250680 <6>[ 0.102749] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10492 14:48:36.253544 <6>[ 0.103028] Detected PIPT I-cache on CPU6
10493 14:48:36.260088 <6>[ 0.103092] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10494 14:48:36.266979 <6>[ 0.103108] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10495 14:48:36.273362 <6>[ 0.103403] Detected PIPT I-cache on CPU7
10496 14:48:36.279748 <6>[ 0.103466] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10497 14:48:36.286770 <6>[ 0.103481] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10498 14:48:36.289865 <6>[ 0.103528] smp: Brought up 1 node, 8 CPUs
10499 14:48:36.296319 <6>[ 0.244839] SMP: Total of 8 processors activated.
10500 14:48:36.300138 <6>[ 0.249759] CPU features: detected: 32-bit EL0 Support
10501 14:48:36.309532 <6>[ 0.255123] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10502 14:48:36.316374 <6>[ 0.263924] CPU features: detected: Common not Private translations
10503 14:48:36.323204 <6>[ 0.270399] CPU features: detected: CRC32 instructions
10504 14:48:36.326333 <6>[ 0.275751] CPU features: detected: RCpc load-acquire (LDAPR)
10505 14:48:36.332926 <6>[ 0.281711] CPU features: detected: LSE atomic instructions
10506 14:48:36.339076 <6>[ 0.287492] CPU features: detected: Privileged Access Never
10507 14:48:36.346046 <6>[ 0.293272] CPU features: detected: RAS Extension Support
10508 14:48:36.353170 <6>[ 0.298881] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10509 14:48:36.355973 <6>[ 0.306103] CPU: All CPU(s) started at EL2
10510 14:48:36.362557 <6>[ 0.310420] alternatives: applying system-wide alternatives
10511 14:48:36.372129 <6>[ 0.321240] devtmpfs: initialized
10512 14:48:36.384909 <6>[ 0.330180] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10513 14:48:36.394848 <6>[ 0.340140] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10514 14:48:36.400898 <6>[ 0.348172] pinctrl core: initialized pinctrl subsystem
10515 14:48:36.404196 <6>[ 0.354818] DMI not present or invalid.
10516 14:48:36.411342 <6>[ 0.359234] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10517 14:48:36.421705 <6>[ 0.366116] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10518 14:48:36.427486 <6>[ 0.373702] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10519 14:48:36.437081 <6>[ 0.381921] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10520 14:48:36.440532 <6>[ 0.390163] audit: initializing netlink subsys (disabled)
10521 14:48:36.450390 <5>[ 0.395855] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10522 14:48:36.457088 <6>[ 0.396559] thermal_sys: Registered thermal governor 'step_wise'
10523 14:48:36.463490 <6>[ 0.403823] thermal_sys: Registered thermal governor 'power_allocator'
10524 14:48:36.467483 <6>[ 0.410078] cpuidle: using governor menu
10525 14:48:36.473092 <6>[ 0.421039] NET: Registered PF_QIPCRTR protocol family
10526 14:48:36.479938 <6>[ 0.426517] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10527 14:48:36.486535 <6>[ 0.433622] ASID allocator initialised with 32768 entries
10528 14:48:36.489524 <6>[ 0.440203] Serial: AMBA PL011 UART driver
10529 14:48:36.499453 <4>[ 0.448953] Trying to register duplicate clock ID: 134
10530 14:48:36.559590 <6>[ 0.511852] KASLR enabled
10531 14:48:36.574092 <6>[ 0.519759] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10532 14:48:36.580806 <6>[ 0.526771] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10533 14:48:36.587357 <6>[ 0.533261] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10534 14:48:36.593697 <6>[ 0.540266] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10535 14:48:36.600152 <6>[ 0.546753] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10536 14:48:36.607652 <6>[ 0.553755] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10537 14:48:36.614094 <6>[ 0.560242] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10538 14:48:36.620863 <6>[ 0.567245] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10539 14:48:36.623970 <6>[ 0.574785] ACPI: Interpreter disabled.
10540 14:48:36.632664 <6>[ 0.581235] iommu: Default domain type: Translated
10541 14:48:36.639092 <6>[ 0.586349] iommu: DMA domain TLB invalidation policy: strict mode
10542 14:48:36.642151 <5>[ 0.593010] SCSI subsystem initialized
10543 14:48:36.649099 <6>[ 0.597176] usbcore: registered new interface driver usbfs
10544 14:48:36.655241 <6>[ 0.602909] usbcore: registered new interface driver hub
10545 14:48:36.658989 <6>[ 0.608463] usbcore: registered new device driver usb
10546 14:48:36.665430 <6>[ 0.614557] pps_core: LinuxPPS API ver. 1 registered
10547 14:48:36.675572 <6>[ 0.619751] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10548 14:48:36.678912 <6>[ 0.629099] PTP clock support registered
10549 14:48:36.681751 <6>[ 0.633340] EDAC MC: Ver: 3.0.0
10550 14:48:36.689283 <6>[ 0.638491] FPGA manager framework
10551 14:48:36.696188 <6>[ 0.642178] Advanced Linux Sound Architecture Driver Initialized.
10552 14:48:36.699551 <6>[ 0.648955] vgaarb: loaded
10553 14:48:36.705515 <6>[ 0.652114] clocksource: Switched to clocksource arch_sys_counter
10554 14:48:36.709181 <5>[ 0.658554] VFS: Disk quotas dquot_6.6.0
10555 14:48:36.716185 <6>[ 0.662738] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10556 14:48:36.719116 <6>[ 0.669929] pnp: PnP ACPI: disabled
10557 14:48:36.727339 <6>[ 0.676590] NET: Registered PF_INET protocol family
10558 14:48:36.737501 <6>[ 0.682181] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10559 14:48:36.748969 <6>[ 0.694496] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10560 14:48:36.758513 <6>[ 0.703309] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10561 14:48:36.765417 <6>[ 0.711278] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10562 14:48:36.775127 <6>[ 0.719980] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10563 14:48:36.781443 <6>[ 0.729732] TCP: Hash tables configured (established 65536 bind 65536)
10564 14:48:36.788256 <6>[ 0.736532] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10565 14:48:36.798270 <6>[ 0.743730] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10566 14:48:36.804670 <6>[ 0.751432] NET: Registered PF_UNIX/PF_LOCAL protocol family
10567 14:48:36.811269 <6>[ 0.757585] RPC: Registered named UNIX socket transport module.
10568 14:48:36.814550 <6>[ 0.763739] RPC: Registered udp transport module.
10569 14:48:36.820883 <6>[ 0.768672] RPC: Registered tcp transport module.
10570 14:48:36.827470 <6>[ 0.773603] RPC: Registered tcp NFSv4.1 backchannel transport module.
10571 14:48:36.830840 <6>[ 0.780270] PCI: CLS 0 bytes, default 64
10572 14:48:36.834232 <6>[ 0.784575] Unpacking initramfs...
10573 14:48:36.855088 <6>[ 0.800719] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10574 14:48:36.864824 <6>[ 0.809352] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10575 14:48:36.868538 <6>[ 0.818168] kvm [1]: IPA Size Limit: 40 bits
10576 14:48:36.875199 <6>[ 0.822694] kvm [1]: GICv3: no GICV resource entry
10577 14:48:36.878267 <6>[ 0.827711] kvm [1]: disabling GICv2 emulation
10578 14:48:36.885070 <6>[ 0.832398] kvm [1]: GIC system register CPU interface enabled
10579 14:48:36.888307 <6>[ 0.838553] kvm [1]: vgic interrupt IRQ18
10580 14:48:36.894753 <6>[ 0.842903] kvm [1]: VHE mode initialized successfully
10581 14:48:36.901341 <5>[ 0.849385] Initialise system trusted keyrings
10582 14:48:36.908266 <6>[ 0.854179] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10583 14:48:36.915727 <6>[ 0.864264] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10584 14:48:36.921944 <5>[ 0.870612] NFS: Registering the id_resolver key type
10585 14:48:36.925328 <5>[ 0.875912] Key type id_resolver registered
10586 14:48:36.932039 <5>[ 0.880327] Key type id_legacy registered
10587 14:48:36.938311 <6>[ 0.884609] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10588 14:48:36.944921 <6>[ 0.891532] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10589 14:48:36.951389 <6>[ 0.899265] 9p: Installing v9fs 9p2000 file system support
10590 14:48:36.988759 <5>[ 0.937451] Key type asymmetric registered
10591 14:48:36.992203 <5>[ 0.941784] Asymmetric key parser 'x509' registered
10592 14:48:37.002303 <6>[ 0.946944] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10593 14:48:37.004680 <6>[ 0.954590] io scheduler mq-deadline registered
10594 14:48:37.008415 <6>[ 0.959361] io scheduler kyber registered
10595 14:48:37.027187 <6>[ 0.976383] EINJ: ACPI disabled.
10596 14:48:37.060188 <4>[ 1.002916] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10597 14:48:37.070241 <4>[ 1.013572] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10598 14:48:37.085531 <6>[ 1.035045] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10599 14:48:37.093611 <6>[ 1.043258] printk: console [ttyS0] disabled
10600 14:48:37.121719 <6>[ 1.067885] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10601 14:48:37.128381 <6>[ 1.077379] printk: console [ttyS0] enabled
10602 14:48:37.132292 <6>[ 1.077379] printk: console [ttyS0] enabled
10603 14:48:37.138350 <6>[ 1.086277] printk: bootconsole [mtk8250] disabled
10604 14:48:37.141632 <6>[ 1.086277] printk: bootconsole [mtk8250] disabled
10605 14:48:37.148017 <6>[ 1.097630] SuperH (H)SCI(F) driver initialized
10606 14:48:37.151377 <6>[ 1.102926] msm_serial: driver initialized
10607 14:48:37.166157 <6>[ 1.111951] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10608 14:48:37.176114 <6>[ 1.120505] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10609 14:48:37.182412 <6>[ 1.129049] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10610 14:48:37.192469 <6>[ 1.137677] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10611 14:48:37.201947 <6>[ 1.146384] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10612 14:48:37.208739 <6>[ 1.155108] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10613 14:48:37.218767 <6>[ 1.163648] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10614 14:48:37.225381 <6>[ 1.172442] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10615 14:48:37.235149 <6>[ 1.180985] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10616 14:48:37.247335 <6>[ 1.196674] loop: module loaded
10617 14:48:37.253753 <6>[ 1.202668] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10618 14:48:37.276625 <4>[ 1.226342] mtk-pmic-keys: Failed to locate of_node [id: -1]
10619 14:48:37.283760 <6>[ 1.233424] megasas: 07.719.03.00-rc1
10620 14:48:37.293810 <6>[ 1.243170] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10621 14:48:37.302342 <6>[ 1.251499] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10622 14:48:37.319089 <6>[ 1.267958] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10623 14:48:37.375216 <6>[ 1.317824] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10624 14:48:39.523970 <6>[ 3.473881] Freeing initrd memory: 59560K
10625 14:48:39.535749 <6>[ 3.485648] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10626 14:48:39.546897 <6>[ 3.496766] tun: Universal TUN/TAP device driver, 1.6
10627 14:48:39.550667 <6>[ 3.502832] thunder_xcv, ver 1.0
10628 14:48:39.554063 <6>[ 3.506343] thunder_bgx, ver 1.0
10629 14:48:39.556592 <6>[ 3.509837] nicpf, ver 1.0
10630 14:48:39.567474 <6>[ 3.513853] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10631 14:48:39.570841 <6>[ 3.521329] hns3: Copyright (c) 2017 Huawei Corporation.
10632 14:48:39.577071 <6>[ 3.526924] hclge is initializing
10633 14:48:39.580896 <6>[ 3.530504] e1000: Intel(R) PRO/1000 Network Driver
10634 14:48:39.587641 <6>[ 3.535633] e1000: Copyright (c) 1999-2006 Intel Corporation.
10635 14:48:39.590480 <6>[ 3.541645] e1000e: Intel(R) PRO/1000 Network Driver
10636 14:48:39.597103 <6>[ 3.546860] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10637 14:48:39.604014 <6>[ 3.553045] igb: Intel(R) Gigabit Ethernet Network Driver
10638 14:48:39.610066 <6>[ 3.558694] igb: Copyright (c) 2007-2014 Intel Corporation.
10639 14:48:39.616789 <6>[ 3.564530] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10640 14:48:39.623733 <6>[ 3.571048] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10641 14:48:39.627288 <6>[ 3.577508] sky2: driver version 1.30
10642 14:48:39.633441 <6>[ 3.582446] usbcore: registered new device driver r8152-cfgselector
10643 14:48:39.640524 <6>[ 3.588981] usbcore: registered new interface driver r8152
10644 14:48:39.646399 <6>[ 3.594802] VFIO - User Level meta-driver version: 0.3
10645 14:48:39.653398 <6>[ 3.603060] usbcore: registered new interface driver usb-storage
10646 14:48:39.660070 <6>[ 3.609511] usbcore: registered new device driver onboard-usb-hub
10647 14:48:39.668817 <6>[ 3.618662] mt6397-rtc mt6359-rtc: registered as rtc0
10648 14:48:39.678674 <6>[ 3.624124] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T14:48:39 UTC (1717512519)
10649 14:48:39.682595 <6>[ 3.633690] i2c_dev: i2c /dev entries driver
10650 14:48:39.699598 <6>[ 3.645643] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10651 14:48:39.705393 <4>[ 3.654365] cpu cpu0: supply cpu not found, using dummy regulator
10652 14:48:39.712210 <4>[ 3.660790] cpu cpu1: supply cpu not found, using dummy regulator
10653 14:48:39.718871 <4>[ 3.667213] cpu cpu2: supply cpu not found, using dummy regulator
10654 14:48:39.725443 <4>[ 3.673611] cpu cpu3: supply cpu not found, using dummy regulator
10655 14:48:39.731958 <4>[ 3.680019] cpu cpu4: supply cpu not found, using dummy regulator
10656 14:48:39.738592 <4>[ 3.686413] cpu cpu5: supply cpu not found, using dummy regulator
10657 14:48:39.745153 <4>[ 3.692812] cpu cpu6: supply cpu not found, using dummy regulator
10658 14:48:39.751748 <4>[ 3.699212] cpu cpu7: supply cpu not found, using dummy regulator
10659 14:48:39.770263 <6>[ 3.719856] cpu cpu0: EM: created perf domain
10660 14:48:39.773051 <6>[ 3.724782] cpu cpu4: EM: created perf domain
10661 14:48:39.780601 <6>[ 3.730428] sdhci: Secure Digital Host Controller Interface driver
10662 14:48:39.787088 <6>[ 3.736861] sdhci: Copyright(c) Pierre Ossman
10663 14:48:39.793524 <6>[ 3.741818] Synopsys Designware Multimedia Card Interface Driver
10664 14:48:39.800699 <6>[ 3.748456] sdhci-pltfm: SDHCI platform and OF driver helper
10665 14:48:39.803370 <6>[ 3.748454] mmc0: CQHCI version 5.10
10666 14:48:39.810441 <6>[ 3.758671] ledtrig-cpu: registered to indicate activity on CPUs
10667 14:48:39.817070 <6>[ 3.765731] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10668 14:48:39.823962 <6>[ 3.772789] usbcore: registered new interface driver usbhid
10669 14:48:39.826559 <6>[ 3.778611] usbhid: USB HID core driver
10670 14:48:39.833867 <6>[ 3.782818] spi_master spi0: will run message pump with realtime priority
10671 14:48:39.879811 <6>[ 3.823151] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10672 14:48:39.898076 <6>[ 3.838256] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10673 14:48:39.901537 <6>[ 3.851852] mmc0: Command Queue Engine enabled
10674 14:48:39.908655 <6>[ 3.856660] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10675 14:48:39.915178 <6>[ 3.863936] mmcblk0: mmc0:0001 DA4128 116 GiB
10676 14:48:39.918672 <6>[ 3.868883] cros-ec-spi spi0.0: Chrome EC device registered
10677 14:48:39.924988 <6>[ 3.872677] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10678 14:48:39.932563 <6>[ 3.882460] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10679 14:48:39.939129 <6>[ 3.888324] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10680 14:48:39.946116 <6>[ 3.894423] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10681 14:48:39.963131 <6>[ 3.909544] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10682 14:48:39.969886 <6>[ 3.919916] NET: Registered PF_PACKET protocol family
10683 14:48:39.973396 <6>[ 3.925298] 9pnet: Installing 9P2000 support
10684 14:48:39.980022 <5>[ 3.929863] Key type dns_resolver registered
10685 14:48:39.983531 <6>[ 3.934860] registered taskstats version 1
10686 14:48:39.989588 <5>[ 3.939240] Loading compiled-in X.509 certificates
10687 14:48:40.021564 <4>[ 3.964539] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10688 14:48:40.031070 <4>[ 3.975291] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10689 14:48:40.046521 <6>[ 3.995382] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10690 14:48:40.052924 <6>[ 4.002254] xhci-mtk 11200000.usb: xHCI Host Controller
10691 14:48:40.058873 <6>[ 4.007785] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10692 14:48:40.069430 <6>[ 4.015626] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10693 14:48:40.076182 <6>[ 4.025049] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10694 14:48:40.082094 <6>[ 4.031154] xhci-mtk 11200000.usb: xHCI Host Controller
10695 14:48:40.088875 <6>[ 4.036632] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10696 14:48:40.095893 <6>[ 4.044279] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10697 14:48:40.102176 <6>[ 4.051891] hub 1-0:1.0: USB hub found
10698 14:48:40.105406 <6>[ 4.055903] hub 1-0:1.0: 1 port detected
10699 14:48:40.115535 <6>[ 4.060192] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10700 14:48:40.118511 <6>[ 4.068720] hub 2-0:1.0: USB hub found
10701 14:48:40.122056 <6>[ 4.072727] hub 2-0:1.0: 1 port detected
10702 14:48:40.129843 <6>[ 4.079824] mtk-msdc 11f70000.mmc: Got CD GPIO
10703 14:48:40.148217 <6>[ 4.094769] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10704 14:48:40.154761 <6>[ 4.102825] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10705 14:48:40.165051 <4>[ 4.110749] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10706 14:48:40.174833 <6>[ 4.120283] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10707 14:48:40.181521 <6>[ 4.128362] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10708 14:48:40.188383 <6>[ 4.136387] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10709 14:48:40.198159 <6>[ 4.144300] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10710 14:48:40.204781 <6>[ 4.152126] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10711 14:48:40.214219 <6>[ 4.159944] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10712 14:48:40.224200 <6>[ 4.170324] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10713 14:48:40.230932 <6>[ 4.178680] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10714 14:48:40.241193 <6>[ 4.187031] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10715 14:48:40.247185 <6>[ 4.195369] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10716 14:48:40.257101 <6>[ 4.203708] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10717 14:48:40.267350 <6>[ 4.212045] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10718 14:48:40.274416 <6>[ 4.220383] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10719 14:48:40.284229 <6>[ 4.228721] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10720 14:48:40.290422 <6>[ 4.237058] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10721 14:48:40.300276 <6>[ 4.245404] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10722 14:48:40.306553 <6>[ 4.253743] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10723 14:48:40.316478 <6>[ 4.262082] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10724 14:48:40.323226 <6>[ 4.270420] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10725 14:48:40.333148 <6>[ 4.278758] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10726 14:48:40.339649 <6>[ 4.287096] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10727 14:48:40.346374 <6>[ 4.295835] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10728 14:48:40.353302 <6>[ 4.303009] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10729 14:48:40.360032 <6>[ 4.309778] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10730 14:48:40.369893 <6>[ 4.316547] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10731 14:48:40.376312 <6>[ 4.323481] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10732 14:48:40.383173 <6>[ 4.330332] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10733 14:48:40.392971 <6>[ 4.339467] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10734 14:48:40.402852 <6>[ 4.348587] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10735 14:48:40.412947 <6>[ 4.357880] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10736 14:48:40.422760 <6>[ 4.367348] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10737 14:48:40.432449 <6>[ 4.376815] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10738 14:48:40.438864 <6>[ 4.385934] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10739 14:48:40.448703 <6>[ 4.395402] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10740 14:48:40.459013 <6>[ 4.404521] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10741 14:48:40.468786 <6>[ 4.413815] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10742 14:48:40.478364 <6>[ 4.423975] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10743 14:48:40.489142 <6>[ 4.435892] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10744 14:48:40.533820 <6>[ 4.480395] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10745 14:48:40.687589 <6>[ 4.637485] hub 1-1:1.0: USB hub found
10746 14:48:40.690717 <6>[ 4.641943] hub 1-1:1.0: 4 ports detected
10747 14:48:40.701685 <6>[ 4.651343] hub 1-1:1.0: USB hub found
10748 14:48:40.704895 <6>[ 4.655734] hub 1-1:1.0: 4 ports detected
10749 14:48:40.814312 <6>[ 4.760731] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10750 14:48:40.840698 <6>[ 4.790103] hub 2-1:1.0: USB hub found
10751 14:48:40.843624 <6>[ 4.794594] hub 2-1:1.0: 3 ports detected
10752 14:48:40.852932 <6>[ 4.802766] hub 2-1:1.0: USB hub found
10753 14:48:40.856140 <6>[ 4.807212] hub 2-1:1.0: 3 ports detected
10754 14:48:41.029871 <6>[ 4.976328] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10755 14:48:41.162558 <6>[ 5.112150] hub 1-1.4:1.0: USB hub found
10756 14:48:41.165604 <6>[ 5.116798] hub 1-1.4:1.0: 2 ports detected
10757 14:48:41.175088 <6>[ 5.125089] hub 1-1.4:1.0: USB hub found
10758 14:48:41.178663 <6>[ 5.129714] hub 1-1.4:1.0: 2 ports detected
10759 14:48:41.246019 <6>[ 5.192531] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10760 14:48:41.354213 <6>[ 5.300914] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10761 14:48:41.390906 <4>[ 5.337440] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10762 14:48:41.400989 <4>[ 5.346531] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10763 14:48:41.436665 <6>[ 5.385993] r8152 2-1.3:1.0 eth0: v1.12.13
10764 14:48:41.478198 <6>[ 5.424437] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10765 14:48:41.669808 <6>[ 5.616245] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10766 14:48:43.048169 <6>[ 6.998366] r8152 2-1.3:1.0 eth0: carrier on
10767 14:48:43.094132 <5>[ 7.028226] Sending DHCP requests ., OK
10768 14:48:43.100981 <6>[ 7.048464] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10769 14:48:43.104020 <6>[ 7.056752] IP-Config: Complete:
10770 14:48:43.117361 <6>[ 7.060253] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10771 14:48:43.124122 <6>[ 7.070974] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10772 14:48:43.130874 <6>[ 7.079593] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10773 14:48:43.137984 <6>[ 7.079602] nameserver0=192.168.201.1
10774 14:48:43.141250 <6>[ 7.091758] clk: Disabling unused clocks
10775 14:48:43.143871 <6>[ 7.097257] ALSA device list:
10776 14:48:43.150743 <6>[ 7.100519] No soundcards found.
10777 14:48:43.158190 <6>[ 7.107790] Freeing unused kernel memory: 8512K
10778 14:48:43.161107 <6>[ 7.112759] Run /init as init process
10779 14:48:43.190439 <6>[ 7.140195] NET: Registered PF_INET6 protocol family
10780 14:48:43.197048 <6>[ 7.146948] Segment Routing with IPv6
10781 14:48:43.200136 <6>[ 7.150900] In-situ OAM (IOAM) with IPv6
10782 14:48:43.243449 <30>[ 7.166711] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10783 14:48:43.249497 <30>[ 7.199769] systemd[1]: Detected architecture arm64.
10784 14:48:43.249582
10785 14:48:43.255965 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10786 14:48:43.256089
10787 14:48:43.270071 <30>[ 7.220457] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10788 14:48:43.393154 <30>[ 7.339801] systemd[1]: Queued start job for default target graphical.target.
10789 14:48:43.443635 <30>[ 7.390120] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10790 14:48:43.450060 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10791 14:48:43.470500 <30>[ 7.417129] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10792 14:48:43.479860 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10793 14:48:43.499126 <30>[ 7.445345] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10794 14:48:43.508469 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10795 14:48:43.527095 <30>[ 7.473762] systemd[1]: Created slice user.slice - User and Session Slice.
10796 14:48:43.533405 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10797 14:48:43.557635 <30>[ 7.501122] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10798 14:48:43.568004 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10799 14:48:43.584686 <30>[ 7.528502] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10800 14:48:43.591718 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10801 14:48:43.620102 <30>[ 7.556932] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10802 14:48:43.629902 <30>[ 7.576798] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10803 14:48:43.636643 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10804 14:48:43.653792 <30>[ 7.600742] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10805 14:48:43.664213 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10806 14:48:43.677900 <30>[ 7.624462] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10807 14:48:43.687413 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10808 14:48:43.702739 <30>[ 7.652877] systemd[1]: Reached target paths.target - Path Units.
10809 14:48:43.712921 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10810 14:48:43.729757 <30>[ 7.676819] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10811 14:48:43.736428 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10812 14:48:43.750057 <30>[ 7.700396] systemd[1]: Reached target slices.target - Slice Units.
10813 14:48:43.760492 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10814 14:48:43.774634 <30>[ 7.724853] systemd[1]: Reached target swap.target - Swaps.
10815 14:48:43.782245 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10816 14:48:43.802155 <30>[ 7.748575] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10817 14:48:43.812365 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10818 14:48:43.830574 <30>[ 7.776991] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10819 14:48:43.840418 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10820 14:48:43.860081 <30>[ 7.806683] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10821 14:48:43.870191 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10822 14:48:43.886565 <30>[ 7.833140] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10823 14:48:43.896287 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10824 14:48:43.914611 <30>[ 7.861044] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10825 14:48:43.921066 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10826 14:48:43.938632 <30>[ 7.885102] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10827 14:48:43.948122 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10828 14:48:43.966727 <30>[ 7.913598] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10829 14:48:43.976790 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10830 14:48:44.025801 <30>[ 7.972651] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10831 14:48:44.032225 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10832 14:48:44.051253 <30>[ 7.998229] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10833 14:48:44.058193 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10834 14:48:44.080243 <30>[ 8.027157] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10835 14:48:44.087197 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10836 14:48:44.112017 <30>[ 8.052595] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10837 14:48:44.125506 <30>[ 8.072599] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10838 14:48:44.135420 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10839 14:48:44.189859 <30>[ 8.136986] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10840 14:48:44.196639 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10841 14:48:44.222401 <30>[ 8.169450] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10842 14:48:44.235630 Starting [0;1;39mmodpr<6>[ 8.180684] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10843 14:48:44.239168 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10844 14:48:44.263130 <30>[ 8.209750] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10845 14:48:44.269191 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10846 14:48:44.334453 <30>[ 8.280921] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10847 14:48:44.343659 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10848 14:48:44.366755 <30>[ 8.313636] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10849 14:48:44.373316 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10850 14:48:44.402276 <30>[ 8.349070] systemd[1]: Starting systemd-journald.service - Journal Service...
10851 14:48:44.409159 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10852 14:48:44.427924 <30>[ 8.375075] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10853 14:48:44.434761 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10854 14:48:44.493759 <30>[ 8.437175] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10855 14:48:44.500076 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10856 14:48:44.522771 <30>[ 8.469421] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10857 14:48:44.532571 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10858 14:48:44.553651 <30>[ 8.499784] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10859 14:48:44.563020 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10860 14:48:44.582464 <30>[ 8.529414] systemd[1]: Started systemd-journald.service - Journal Service.
10861 14:48:44.589051 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10862 14:48:44.607970 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10863 14:48:44.627324 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10864 14:48:44.646473 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10865 14:48:44.670294 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10866 14:48:44.691999 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10867 14:48:44.711455 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10868 14:48:44.731596 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10869 14:48:44.752388 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10870 14:48:44.772963 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10871 14:48:44.792719 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10872 14:48:44.811258 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10873 14:48:44.832814 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10874 14:48:44.846278 See 'systemctl status systemd-remount-fs.service' for details.
10875 14:48:44.856680 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10876 14:48:44.876440 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10877 14:48:44.930120 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10878 14:48:44.950636 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10879 14:48:44.969521 <46>[ 8.916728] systemd-journald[197]: Received client request to flush runtime journal.
10880 14:48:44.976121 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10881 14:48:45.002167 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10882 14:48:45.026751 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10883 14:48:45.051037 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10884 14:48:45.071224 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10885 14:48:45.091124 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10886 14:48:45.110740 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10887 14:48:45.130538 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10888 14:48:45.182678 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10889 14:48:45.214188 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10890 14:48:45.234604 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10891 14:48:45.253555 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10892 14:48:45.297902 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10893 14:48:45.318976 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10894 14:48:45.342075 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10895 14:48:45.359909 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10896 14:48:45.421079 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10897 14:48:45.446749 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10898 14:48:45.486435 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10899 14:48:45.511333 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10900 14:48:45.545690 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10901 14:48:45.633322 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10902 14:48:45.650890 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10903 14:48:45.670468 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10904 14:48:45.691722 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10905 14:48:45.710291 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10906 14:48:45.726411 <6>[ 9.673245] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10907 14:48:45.739820 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message<6>[ 9.686972] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10908 14:48:45.742897 Bus Socket.
10909 14:48:45.749462 <6>[ 9.695928] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10910 14:48:45.759837 <6>[ 9.705867] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10911 14:48:45.765972 <6>[ 9.708345] remoteproc remoteproc0: scp is available
10912 14:48:45.772891 <3>[ 9.716053] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10913 14:48:45.778989 <6>[ 9.719850] remoteproc remoteproc0: powering up scp
10914 14:48:45.785996 <3>[ 9.727879] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10915 14:48:45.795886 <6>[ 9.733110] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10916 14:48:45.802395 <3>[ 9.741482] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10917 14:48:45.809220 <6>[ 9.749829] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10918 14:48:45.815410 <6>[ 9.753600] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10919 14:48:45.825205 <3>[ 9.757781] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10920 14:48:45.831904 <3>[ 9.779090] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10921 14:48:45.839318 <3>[ 9.779098] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10922 14:48:45.849217 <3>[ 9.779107] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10923 14:48:45.859090 [[0;32m OK [<3>[ 9.779115] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10924 14:48:45.862535 0m] Reached targ<6>[ 9.779476] mc: Linux media interface: v0.10
10925 14:48:45.872291 <4>[ 9.781680] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10926 14:48:45.883110 et [0;1;39msock<4>[ 9.781762] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10927 14:48:45.885638 <4>[ 9.781762] Fallback method does not support PEC.
10928 14:48:45.896561 ets.target[0m -<4>[ 9.782139] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10929 14:48:45.896987 Socket Units.
10930 14:48:45.906560 <3>[ 9.797366] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 14:48:45.906960
10932 14:48:45.913702 <3>[ 9.803643] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10933 14:48:45.920280 <6>[ 9.804633] videodev: Linux video capture interface: v2.00
10934 14:48:45.926793 <6>[ 9.833495] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10935 14:48:45.934149 <3>[ 9.841194] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10936 14:48:45.944096 <3>[ 9.849359] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 14:48:45.947385 <6>[ 9.849846] pci_bus 0000:00: root bus resource [bus 00-ff]
10938 14:48:45.957611 <3>[ 9.850185] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10939 14:48:45.964330 <3>[ 9.860002] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10940 14:48:45.974511 <6>[ 9.861216] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10941 14:48:45.984206 <6>[ 9.861514] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10942 14:48:45.990986 <6>[ 9.868166] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10943 14:48:46.000995 <3>[ 9.871895] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 14:48:46.007352 <3>[ 9.873900] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10945 14:48:46.018105 <6>[ 9.880761] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10946 14:48:46.028708 <6>[ 9.888096] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10947 14:48:46.035141 <3>[ 9.888885] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10948 14:48:46.045601 <3>[ 9.892678] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10949 14:48:46.052322 <6>[ 9.897642] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10950 14:48:46.059418 <3>[ 9.903348] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10951 14:48:46.066018 <6>[ 9.905220] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10952 14:48:46.076462 <6>[ 9.912494] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10953 14:48:46.082802 <6>[ 9.913808] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10954 14:48:46.085989 <6>[ 9.913888] pci 0000:00:00.0: supports D1 D2
10955 14:48:46.092675 <6>[ 9.913892] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10956 14:48:46.103120 <6>[ 9.915535] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10957 14:48:46.106778 <6>[ 9.915647] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10958 14:48:46.116316 <6>[ 9.915679] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10959 14:48:46.122929 <6>[ 9.915699] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10960 14:48:46.129706 <6>[ 9.915718] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10961 14:48:46.133540 <6>[ 9.915841] pci 0000:01:00.0: supports D1 D2
10962 14:48:46.140213 <6>[ 9.915844] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10963 14:48:46.150190 <3>[ 9.920542] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10964 14:48:46.157946 <6>[ 9.923362] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10965 14:48:46.167615 <3>[ 9.925720] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 14:48:46.174399 <3>[ 9.926334] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
10967 14:48:46.181836 <6>[ 9.928557] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10968 14:48:46.191107 <6>[ 9.928785] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10969 14:48:46.198025 <6>[ 9.928801] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10970 14:48:46.208103 <6>[ 9.928832] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10971 14:48:46.214135 <6>[ 9.928850] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10972 14:48:46.220809 <6>[ 9.928869] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10973 14:48:46.227399 <6>[ 9.928890] pci 0000:00:00.0: PCI bridge to [bus 01]
10974 14:48:46.236912 <6>[ 9.928912] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10975 14:48:46.240447 <6>[ 9.929299] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10976 14:48:46.246927 <6>[ 9.930644] remoteproc remoteproc0: remote processor scp is now up
10977 14:48:46.253685 <6>[ 9.931457] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10978 14:48:46.260552 <6>[ 9.931693] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10979 14:48:46.267132 <3>[ 9.939681] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10980 14:48:46.273177 <6>[ 9.941653] Bluetooth: Core ver 2.22
10981 14:48:46.276871 <6>[ 9.941717] NET: Registered PF_BLUETOOTH protocol family
10982 14:48:46.283157 <6>[ 9.941720] Bluetooth: HCI device and connection manager initialized
10983 14:48:46.290082 <6>[ 9.941742] Bluetooth: HCI socket layer initialized
10984 14:48:46.293147 <6>[ 9.941752] Bluetooth: L2CAP socket layer initialized
10985 14:48:46.299753 <6>[ 9.941771] Bluetooth: SCO socket layer initialized
10986 14:48:46.306178 <5>[ 9.949226] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10987 14:48:46.316293 <6>[ 9.950186] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10988 14:48:46.322902 <3>[ 9.955576] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10989 14:48:46.332894 <3>[ 9.955639] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10990 14:48:46.339602 <6>[ 9.965763] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10991 14:48:46.349142 <3>[ 9.979761] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10992 14:48:46.352631 <6>[ 9.984732] usbcore: registered new interface driver btusb
10993 14:48:46.359118 <6>[ 9.984800] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10994 14:48:46.372369 <4>[ 9.985658] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10995 14:48:46.375767 <3>[ 9.985692] Bluetooth: hci0: Failed to load firmware file (-2)
10996 14:48:46.382216 <3>[ 9.985698] Bluetooth: hci0: Failed to set up firmware (-2)
10997 14:48:46.392416 <4>[ 9.985708] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10998 14:48:46.405517 <6>[ 9.986954] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10999 14:48:46.411836 <6>[ 9.987147] usbcore: registered new interface driver uvcvideo
11000 14:48:46.418399 <5>[ 9.997018] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11001 14:48:46.428000 <3>[ 9.997319] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11002 14:48:46.434858 <3>[ 10.023236] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11003 14:48:46.444956 <5>[ 10.030284] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11004 14:48:46.451239 <4>[ 10.399599] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11005 14:48:46.458584 <6>[ 10.399607] cfg80211: failed to load regulatory.db
11006 14:48:46.465195 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11007 14:48:46.500351 <6>[ 10.447314] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11008 14:48:46.506675 <6>[ 10.454824] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11009 14:48:46.531246 Starting [0;1;39mdbus.service[0m - D-<6>[ 10.480991] mt7921e 0000:01:00.0: ASIC revision: 79610010
11010 14:48:46.534464 Bus System Message Bus...
11011 14:48:46.562653 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11012 14:48:46.597825 <46>[ 10.531380] systemd-journald[197]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.2 (1539 of 2047 items, 524288 file size, 340 bytes per hash table item), suggesting rotation.
11013 14:48:46.614402 Startin<46>[ 10.552735] systemd-journald[197]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
11014 14:48:46.620949 g [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11015 14:48:46.641164 <6>[ 10.588287] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11016 14:48:46.645282 <6>[ 10.588287]
11017 14:48:46.650983 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11018 14:48:46.685191 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11019 14:48:46.745397 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11020 14:48:46.765360 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11021 14:48:46.781920 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11022 14:48:46.802344 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11023 14:48:46.861212 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11024 14:48:46.912001 <6>[ 10.858845] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11025 14:48:46.921439 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11026 14:48:46.939162 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11027 14:48:46.953961 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11028 14:48:46.974027 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11029 14:48:47.026737 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11030 14:48:47.051276 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11031 14:48:47.079626 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11032 14:48:47.136820 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11033 14:48:47.155410 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11034 14:48:47.179899 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11035 14:48:47.224821
11036 14:48:47.227399 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11037 14:48:47.227482
11038 14:48:47.230696 debian-bookworm-arm64 login: root (automatic login)
11039 14:48:47.230778
11040 14:48:47.244706 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024 aarch64
11041 14:48:47.244790
11042 14:48:47.251163 The programs included with the Debian GNU/Linux system are free software;
11043 14:48:47.257892 the exact distribution terms for each program are described in the
11044 14:48:47.261287 individual files in /usr/share/doc/*/copyright.
11045 14:48:47.261384
11046 14:48:47.267942 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11047 14:48:47.271019 permitted by applicable law.
11048 14:48:47.271442 Matched prompt #10: / #
11050 14:48:47.271781 Setting prompt string to ['/ #']
11051 14:48:47.271931 end: 2.2.5.1 login-action (duration 00:00:12) [common]
11053 14:48:47.272256 end: 2.2.5 auto-login-action (duration 00:00:12) [common]
11054 14:48:47.272367 start: 2.2.6 expect-shell-connection (timeout 00:02:42) [common]
11055 14:48:47.272450 Setting prompt string to ['/ #']
11056 14:48:47.272519 Forcing a shell prompt, looking for ['/ #']
11058 14:48:47.322785 / #
11059 14:48:47.323427 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11060 14:48:47.323925 Waiting using forced prompt support (timeout 00:02:30)
11061 14:48:47.328911
11062 14:48:47.329784 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11063 14:48:47.330378 start: 2.2.7 export-device-env (timeout 00:02:42) [common]
11064 14:48:47.330938 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11065 14:48:47.331497 end: 2.2 depthcharge-retry (duration 00:02:18) [common]
11066 14:48:47.331921 end: 2 depthcharge-action (duration 00:02:18) [common]
11067 14:48:47.332355 start: 3 lava-test-retry (timeout 00:07:17) [common]
11068 14:48:47.332773 start: 3.1 lava-test-shell (timeout 00:07:17) [common]
11069 14:48:47.333212 Using namespace: common
11071 14:48:47.434288 / # #
11072 14:48:47.434429 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11073 14:48:47.439354 #
11074 14:48:47.439619 Using /lava-14167035
11076 14:48:47.540116 / # export SHELL=/bin/sh
11077 14:48:47.546189 export SHELL=/bin/sh
11079 14:48:47.647499 / # . /lava-14167035/environment
11080 14:48:47.653071 . /lava-14167035/environment
11082 14:48:47.754653 / # /lava-14167035/bin/lava-test-runner /lava-14167035/0
11083 14:48:47.755190 Test shell timeout: 10s (minimum of the action and connection timeout)
11084 14:48:47.760270 /lava-14167035/bin/lava-test-runner /lava-14167035/0
11085 14:48:47.778372 <6>[ 11.728456] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11086 14:48:47.788938 + export TESTRUN_ID=0_igt-gpu-pa<8>[ 11.737969] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 14167035_1.5.2.3.1>
11087 14:48:47.789813 Received signal: <STARTRUN> 0_igt-gpu-panfrost 14167035_1.5.2.3.1
11088 14:48:47.790179 Starting test lava.0_igt-gpu-panfrost (14167035_1.5.2.3.1)
11089 14:48:47.790572 Skipping test definition patterns.
11090 14:48:47.792266 nfrost
11091 14:48:47.795319 + cd /lava-14167035/0/tests/0_igt-gpu-panfrost
11092 14:48:47.795946 + cat uuid
11093 14:48:47.798748 + UUID=14167035_1.5.2.3.1
11094 14:48:47.799190 + set +x
11095 14:48:47.809039 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
11096 14:48:47.815994 <8>[ 11.766436] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11097 14:48:47.816702 Received signal: <TESTSET> START panfrost_gem_new
11098 14:48:47.817113 Starting test_set panfrost_gem_new
11099 14:48:47.836199 <14>[ 11.786359] [IGT] panfrost_gem_new: executing
11100 14:48:47.842986 IGT-Version: 1.2<14>[ 11.793944] [IGT] panfrost_gem_new: exiting, ret=77
11101 14:48:47.849795 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11102 14:48:47.856559 Using IGT_SR<8>[ 11.804971] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11103 14:48:47.857367 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11105 14:48:47.860066 ANDOM=1717512527 for randomisation
11106 14:48:47.866418 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11107 14:48:47.869420 Test requirement: !(fd<0)
11108 14:48:47.876335 No known gpu found for chipset flags 0x32 (panfrost)
11109 14:48:47.879288 Last errno: 2, No such file or directory
11110 14:48:47.882783 [1mSubtest gem<14>[ 11.834176] [IGT] panfrost_gem_new: executing
11111 14:48:47.885778 -new-4096: SKIP (0.000s)[0m
11112 14:48:47.892707 IGT-Version: 1.28-<14>[ 11.842922] [IGT] panfrost_gem_new: exiting, ret=77
11113 14:48:47.899135 ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11114 14:48:47.905592 Using IGT_SRAN<8>[ 11.854415] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11115 14:48:47.906396 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11117 14:48:47.908827 DOM=1717512527 for randomisation
11118 14:48:47.915680 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11119 14:48:47.919044 Test requirement: !(fd<0)
11120 14:48:47.925325 No known gpu found for chipset fl<14>[ 11.875440] [IGT] panfrost_gem_new: executing
11121 14:48:47.928503 ags 0x32 (panfrost)
11122 14:48:47.935166 Last errno:<14>[ 11.883608] [IGT] panfrost_gem_new: exiting, ret=77
11123 14:48:47.935722 2, No such file or directory
11124 14:48:47.945809 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11126 14:48:47.948582 [1mSubtest gem-new-0: SKIP (0.00<8>[ 11.893619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11127 14:48:47.949032 0s)[0m
11128 14:48:47.954710 IGT-Version: 1.28-ga44e<8>[ 11.903572] <LAVA_SIGNAL_TESTSET STOP>
11129 14:48:47.954991 Received signal: <TESTSET> STOP
11130 14:48:47.955095 Closing test_set panfrost_gem_new
11131 14:48:47.957771 bfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11132 14:48:47.961500 Using IGT_SRANDOM=1717512527 for randomisation
11133 14:48:47.968021 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11134 14:48:47.974195 Test requirement:<8>[ 11.925448] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11135 14:48:47.974453 Received signal: <TESTSET> START panfrost_get_param
11136 14:48:47.974564 Starting test_set panfrost_get_param
11137 14:48:47.977773 !(fd<0)
11138 14:48:47.981145 No known gpu found for chipset flags 0x32 (panfrost)
11139 14:48:47.984208 Last errno: 2, No such file or directory
11140 14:48:47.987714 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
11141 14:48:47.994165 <14>[ 11.944541] [IGT] panfrost_get_param: executing
11142 14:48:48.000897 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 11.951915] [IGT] panfrost_get_param: exiting, ret=77
11143 14:48:48.003673 h64) (Linux: 6.1.91-cip21 aarch64)
11144 14:48:48.014123 Using IGT_SRANDOM=1717512527<8>[ 11.962626] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11145 14:48:48.014416 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11147 14:48:48.017146 for randomisation
11148 14:48:48.023672 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11149 14:48:48.027041 Test requirement: !(fd<0)
11150 14:48:48.030369 No known gpu found for chipset flags 0x32 (panfrost)
11151 14:48:48.033846 Last errno: 2, No such file or directory
11152 14:48:48.037451 [1mSubtest base-params: SKIP (0.000s)[0m
11153 14:48:48.044343 <14>[ 11.994791] [IGT] panfrost_get_param: executing
11154 14:48:48.054588 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 12.003052] [IGT] panfrost_get_param: exiting, ret=77
11155 14:48:48.055082 .91-cip21 aarch64)
11156 14:48:48.060812 Using IGT_SRANDOM=1717512527 for randomisation
11157 14:48:48.067701 Test require<8>[ 12.015401] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11158 14:48:48.068529 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11160 14:48:48.074076 ment not met in function drm_open_driver, file ../lib/drmtest.c:694:
11161 14:48:48.077590 Test requirement: !(fd<0)
11162 14:48:48.080853 No known gpu found for chipset flags 0x32 (panfrost)
11163 14:48:48.087445 Last errno: 2, No such file or directory
11164 14:48:48.091112 [1mSubtest get-bad-param: SKIP (0.000s)[0m
11165 14:48:48.098650 <14>[ 12.048425] [IGT] panfrost_get_param: executing
11166 14:48:48.108041 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 12.056849] [IGT] panfrost_get_param: exiting, ret=77
11167 14:48:48.111367 .91-cip21 aarch64)
11168 14:48:48.114435 Using IGT_SRANDOM=1717512527 for randomisation
11169 14:48:48.124869 Test requirement not met in <8>[ 12.071199] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11170 14:48:48.125642 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11172 14:48:48.131266 function drm_open_driver, file .<8>[ 12.080647] <LAVA_SIGNAL_TESTSET STOP>
11173 14:48:48.131704 ./lib/drmtest.c:694:
11174 14:48:48.132400 Received signal: <TESTSET> STOP
11175 14:48:48.132769 Closing test_set panfrost_get_param
11176 14:48:48.134527 Test requirement: !(fd<0)
11177 14:48:48.137797 No known gpu found for chipset flags 0x32 (panfrost)
11178 14:48:48.144252 Last errno: 2, No such file or directory
11179 14:48:48.147459 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
11180 14:48:48.161434 <8>[ 12.112265] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11181 14:48:48.161717 Received signal: <TESTSET> START panfrost_prime
11182 14:48:48.161817 Starting test_set panfrost_prime
11183 14:48:48.188793 <14>[ 12.139574] [IGT] panfrost_prime: executing
11184 14:48:48.198879 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 12.147397] [IGT] panfrost_prime: exiting, ret=77
11185 14:48:48.198965 .91-cip21 aarch64)
11186 14:48:48.205766 Using IGT_SRANDOM=1717512528 for randomisation
11187 14:48:48.215666 Test requirement not met in function drm_ope<8>[ 12.162449] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11188 14:48:48.215936 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11190 14:48:48.222500 n_driver, file ../lib/drmtest.c:<8>[ 12.172451] <LAVA_SIGNAL_TESTSET STOP>
11191 14:48:48.223043 694:
11192 14:48:48.223854 Received signal: <TESTSET> STOP
11193 14:48:48.224353 Closing test_set panfrost_prime
11194 14:48:48.225971 Test requirement: !(fd<0)
11195 14:48:48.229196 No known gpu found for chipset flags 0x32 (panfrost)
11196 14:48:48.232253 Last errno: 2, No such file or directory
11197 14:48:48.238783 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
11198 14:48:48.254260 <8>[ 12.204655] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11199 14:48:48.255116 Received signal: <TESTSET> START panfrost_submit
11200 14:48:48.255624 Starting test_set panfrost_submit
11201 14:48:48.290900 <14>[ 12.241182] [IGT] panfrost_submit: executing
11202 14:48:48.300421 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 12.249182] [IGT] panfrost_submit: exiting, ret=77
11203 14:48:48.301066 .91-cip21 aarch64)
11204 14:48:48.307314 Using IGT_SRANDOM=1717512528 for randomisation
11205 14:48:48.313702 Test require<8>[ 12.262273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11206 14:48:48.314483 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11208 14:48:48.320895 ment not met in function drm_open_driver, file ../lib/drmtest.c:694:
11209 14:48:48.324149 Test requirement: !(fd<0)
11210 14:48:48.327322 No known gpu found for chipset flags 0x32 (panfrost)
11211 14:48:48.330680 Last errno: 2, No such file or directory
11212 14:48:48.333733 [1mSubtest pan-submit: SKIP (0.000s)[0m
11213 14:48:48.343906 <14>[ 12.293743] [IGT] panfrost_submit: executing
11214 14:48:48.352997 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 12.301838] [IGT] panfrost_submit: exiting, ret=77
11215 14:48:48.353603 .91-cip21 aarch64)
11216 14:48:48.360348 Using IGT_SRANDOM=1717512528 for randomisation
11217 14:48:48.369750 Test requirement not met in function drm_ope<8>[ 12.317181] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11218 14:48:48.370431 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11220 14:48:48.373176 n_driver, file ../lib/drmtest.c:694:
11221 14:48:48.376616 Test requirement: !(fd<0)
11222 14:48:48.380216 No known gpu found for chipset flags 0x32 (panfrost)
11223 14:48:48.383134 Last errno: 2, No such file or directory
11224 14:48:48.389221 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[0m
11225 14:48:48.399307 <14>[ 12.349815] [IGT] panfrost_submit: executing
11226 14:48:48.409321 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 12.358085] [IGT] panfrost_submit: exiting, ret=77
11227 14:48:48.409764 .91-cip21 aarch64)
11228 14:48:48.415805 Using IGT_SRANDOM=1717512528 for randomisation
11229 14:48:48.425971 Test requirement not met in <8>[ 12.371245] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11230 14:48:48.426908 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11232 14:48:48.429061 function drm_open_driver, file ../lib/drmtest.c:694:
11233 14:48:48.432783 Test requirement: !(fd<0)
11234 14:48:48.435871 No known gpu found for chipset flags 0x32 (panfrost)
11235 14:48:48.445553 Last errno: 2, No such fi<14>[ 12.394826] [IGT] panfrost_submit: executing
11236 14:48:48.445995 le or directory
11237 14:48:48.452671 [1mSubtest pan<14>[ 12.401998] [IGT] panfrost_submit: exiting, ret=77
11238 14:48:48.455368 -submit-error-bad-in-syncs: SKIP (0.000s)[0m
11239 14:48:48.468736 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.<8>[ 12.415030] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11240 14:48:48.469010 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11242 14:48:48.471976 91-cip21 aarch64)
11243 14:48:48.475290 Using IGT_SRANDOM=1717512528 for randomisation
11244 14:48:48.481510 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11245 14:48:48.485222 Test requirement: !(fd<0)
11246 14:48:48.491568 No known gpu fou<14>[ 12.439895] [IGT] panfrost_submit: executing
11247 14:48:48.498232 nd for chipset flags 0x32 (panfr<14>[ 12.448149] [IGT] panfrost_submit: exiting, ret=77
11248 14:48:48.498348 ost)
11249 14:48:48.501324 Last errno: 2, No such file or directory
11250 14:48:48.511505 [1mSubtest pan-<8>[ 12.459231] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11251 14:48:48.511814 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11253 14:48:48.517942 submit-error-bad-bo-handles: SKIP (0.000s)[0m
11254 14:48:48.521391 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11255 14:48:48.527918 Using IGT_SRANDOM=1717512528 for randomisation
11256 14:48:48.534858 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11257 14:48:48.537816 Test requirement: !(fd<0)
11258 14:48:48.541229 No known gpu fo<14>[ 12.491859] [IGT] panfrost_submit: executing
11259 14:48:48.544609 und for chipset flags 0x32 (panfrost)
11260 14:48:48.551097 Last errn<14>[ 12.501477] [IGT] panfrost_submit: exiting, ret=77
11261 14:48:48.554519 o: 2, No such file or directory
11262 14:48:48.567788 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0<8>[ 12.515380] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11263 14:48:48.567919 m
11264 14:48:48.568192 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11266 14:48:48.574190 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11267 14:48:48.577307 Using IGT_SRANDOM=1717512528 for randomisation
11268 14:48:48.587516 Test requirement not met in function drm_open_driver, fil<14>[ 12.539346] [IGT] panfrost_submit: executing
11269 14:48:48.590723 e ../lib/drmtest.c:694:
11270 14:48:48.597510 Test re<14>[ 12.546208] [IGT] panfrost_submit: exiting, ret=77
11271 14:48:48.597602 quirement: !(fd<0)
11272 14:48:48.603771 No known gpu found for chipset flags 0x32 (panfrost)
11273 14:48:48.610960 Last e<8>[ 12.558378] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11274 14:48:48.611301 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11276 14:48:48.614170 rrno: 2, No such file or directory
11277 14:48:48.616922 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
11278 14:48:48.623733 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11279 14:48:48.627074 Using IGT_SRANDOM=1717512528 for randomisation
11280 14:48:48.640149 Test requirement not met in function drm_open_driver, file ../lib/drmtest.<14>[ 12.589364] [IGT] panfrost_submit: executing
11281 14:48:48.640356 c:694:
11282 14:48:48.644208 Test requirement: !(fd<0)
11283 14:48:48.650226 No known gpu <14>[ 12.598695] [IGT] panfrost_submit: exiting, ret=77
11284 14:48:48.654287 found for chipset flags 0x32 (panfrost)
11285 14:48:48.657084 Last errno: 2, No such file or directory
11286 14:48:48.663881 [1mSubtest p<8>[ 12.611897] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11287 14:48:48.664576 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11289 14:48:48.667004 an-reset: SKIP (0.000s)[0m
11290 14:48:48.673908 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11291 14:48:48.676658 Using IGT_SRANDOM=1717512528 for randomisation
11292 14:48:48.683743 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11293 14:48:48.686558 Test requirement: !(fd<0)
11294 14:48:48.693188 No known gpu found for chipset fla<14>[ 12.644984] [IGT] panfrost_submit: executing
11295 14:48:48.696319 gs 0x32 (panfrost)
11296 14:48:48.700181 Last errno: 2, No such file or directory
11297 14:48:48.706727 [<14>[ 12.654692] [IGT] panfrost_submit: exiting, ret=77
11298 14:48:48.709733 1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11299 14:48:48.720014 IGT-Version: 1.28-ga44ebfe (a<8>[ 12.666597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11300 14:48:48.720719 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11302 14:48:48.727031 arch64) (Linux: 6.1.91-cip21 aar<8>[ 12.677420] <LAVA_SIGNAL_TESTSET STOP>
11303 14:48:48.727462 ch64)
11304 14:48:48.728155 Received signal: <TESTSET> STOP
11305 14:48:48.728715 Closing test_set panfrost_submit
11306 14:48:48.736234 Using IGT<8>[ 12.683320] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 14167035_1.5.2.3.1>
11307 14:48:48.737177 Received signal: <ENDRUN> 0_igt-gpu-panfrost 14167035_1.5.2.3.1
11308 14:48:48.737741 Ending use of test pattern.
11309 14:48:48.738144 Ending test lava.0_igt-gpu-panfrost (14167035_1.5.2.3.1), duration 0.95
11311 14:48:48.739865 _SRANDOM=1717512528 for randomisation
11312 14:48:48.746121 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11313 14:48:48.749381 Test requirement: !(fd<0)
11314 14:48:48.753228 No known gpu found for chipset flags 0x32 (panfrost)
11315 14:48:48.755824 Last errno: 2, No such file or directory
11316 14:48:48.762854 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11317 14:48:48.763272 + set +x
11318 14:48:48.765894 <LAVA_TEST_RUNNER EXIT>
11319 14:48:48.766569 ok: lava_test_shell seems to have completed
11320 14:48:48.768140 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11321 14:48:48.768620 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11322 14:48:48.769036 end: 3 lava-test-retry (duration 00:00:01) [common]
11323 14:48:48.769513 start: 4 finalize (timeout 00:07:16) [common]
11324 14:48:48.770026 start: 4.1 power-off (timeout 00:00:30) [common]
11325 14:48:48.770769 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
11326 14:48:49.026254 >> Command sent successfully.
11327 14:48:49.028631 Returned 0 in 0 seconds
11328 14:48:49.129375 end: 4.1 power-off (duration 00:00:00) [common]
11330 14:48:49.130995 start: 4.2 read-feedback (timeout 00:07:15) [common]
11331 14:48:49.132169 Listened to connection for namespace 'common' for up to 1s
11332 14:48:50.132710 Finalising connection for namespace 'common'
11333 14:48:50.132893 Disconnecting from shell: Finalise
11334 14:48:50.132970 / #
11335 14:48:50.233340 end: 4.2 read-feedback (duration 00:00:01) [common]
11336 14:48:50.233512 end: 4 finalize (duration 00:00:01) [common]
11337 14:48:50.233632 Cleaning after the job
11338 14:48:50.233728 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167035/tftp-deploy-3rgjmpmz/ramdisk
11339 14:48:50.240203 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167035/tftp-deploy-3rgjmpmz/kernel
11340 14:48:50.255647 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167035/tftp-deploy-3rgjmpmz/dtb
11341 14:48:50.255864 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167035/tftp-deploy-3rgjmpmz/modules
11342 14:48:50.261605 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14167035
11343 14:48:50.374843 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14167035
11344 14:48:50.375024 Job finished correctly