Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 0
- Kernel Errors: 55
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 91
1 14:42:23.447929 lava-dispatcher, installed at version: 2024.03
2 14:42:23.448155 start: 0 validate
3 14:42:23.448295 Start time: 2024-06-04 14:42:23.448287+00:00 (UTC)
4 14:42:23.448423 Using caching service: 'http://localhost/cache/?uri=%s'
5 14:42:23.448549 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 14:42:23.709858 Using caching service: 'http://localhost/cache/?uri=%s'
7 14:42:23.710635 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 14:43:46.809509 Using caching service: 'http://localhost/cache/?uri=%s'
9 14:43:46.810235 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 14:43:47.071394 Using caching service: 'http://localhost/cache/?uri=%s'
11 14:43:47.071592 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 14:43:47.589361 Using caching service: 'http://localhost/cache/?uri=%s'
13 14:43:47.590099 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 14:43:47.856491 validate duration: 84.41
16 14:43:47.856771 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 14:43:47.856871 start: 1.1 download-retry (timeout 00:10:00) [common]
18 14:43:47.856956 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 14:43:47.857078 Not decompressing ramdisk as can be used compressed.
20 14:43:47.857159 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 14:43:47.857223 saving as /var/lib/lava/dispatcher/tmp/14166990/tftp-deploy-muq91wc3/ramdisk/initrd.cpio.gz
22 14:43:47.857334 total size: 5628169 (5 MB)
23 14:43:48.114666 progress 0 % (0 MB)
24 14:43:48.116302 progress 5 % (0 MB)
25 14:43:48.117936 progress 10 % (0 MB)
26 14:43:48.119331 progress 15 % (0 MB)
27 14:43:48.120889 progress 20 % (1 MB)
28 14:43:48.122327 progress 25 % (1 MB)
29 14:43:48.123881 progress 30 % (1 MB)
30 14:43:48.125447 progress 35 % (1 MB)
31 14:43:48.126804 progress 40 % (2 MB)
32 14:43:48.128327 progress 45 % (2 MB)
33 14:43:48.129733 progress 50 % (2 MB)
34 14:43:48.131245 progress 55 % (2 MB)
35 14:43:48.132757 progress 60 % (3 MB)
36 14:43:48.134177 progress 65 % (3 MB)
37 14:43:48.135702 progress 70 % (3 MB)
38 14:43:48.137053 progress 75 % (4 MB)
39 14:43:48.138597 progress 80 % (4 MB)
40 14:43:48.139963 progress 85 % (4 MB)
41 14:43:48.141503 progress 90 % (4 MB)
42 14:43:48.143013 progress 95 % (5 MB)
43 14:43:48.144425 progress 100 % (5 MB)
44 14:43:48.144644 5 MB downloaded in 0.29 s (18.68 MB/s)
45 14:43:48.144797 end: 1.1.1 http-download (duration 00:00:00) [common]
47 14:43:48.145030 end: 1.1 download-retry (duration 00:00:00) [common]
48 14:43:48.145117 start: 1.2 download-retry (timeout 00:10:00) [common]
49 14:43:48.145199 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 14:43:48.145383 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 14:43:48.145477 saving as /var/lib/lava/dispatcher/tmp/14166990/tftp-deploy-muq91wc3/kernel/Image
52 14:43:48.145553 total size: 54682112 (52 MB)
53 14:43:48.145616 No compression specified
54 14:43:48.146726 progress 0 % (0 MB)
55 14:43:48.160507 progress 5 % (2 MB)
56 14:43:48.174434 progress 10 % (5 MB)
57 14:43:48.188454 progress 15 % (7 MB)
58 14:43:48.202575 progress 20 % (10 MB)
59 14:43:48.216800 progress 25 % (13 MB)
60 14:43:48.230750 progress 30 % (15 MB)
61 14:43:48.245182 progress 35 % (18 MB)
62 14:43:48.260286 progress 40 % (20 MB)
63 14:43:48.274482 progress 45 % (23 MB)
64 14:43:48.288827 progress 50 % (26 MB)
65 14:43:48.303035 progress 55 % (28 MB)
66 14:43:48.317206 progress 60 % (31 MB)
67 14:43:48.332028 progress 65 % (33 MB)
68 14:43:48.346216 progress 70 % (36 MB)
69 14:43:48.360514 progress 75 % (39 MB)
70 14:43:48.374715 progress 80 % (41 MB)
71 14:43:48.388690 progress 85 % (44 MB)
72 14:43:48.402683 progress 90 % (46 MB)
73 14:43:48.416769 progress 95 % (49 MB)
74 14:43:48.430465 progress 100 % (52 MB)
75 14:43:48.430740 52 MB downloaded in 0.29 s (182.86 MB/s)
76 14:43:48.430894 end: 1.2.1 http-download (duration 00:00:00) [common]
78 14:43:48.431134 end: 1.2 download-retry (duration 00:00:00) [common]
79 14:43:48.431221 start: 1.3 download-retry (timeout 00:09:59) [common]
80 14:43:48.431306 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 14:43:48.431441 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
82 14:43:48.431510 saving as /var/lib/lava/dispatcher/tmp/14166990/tftp-deploy-muq91wc3/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
83 14:43:48.431570 total size: 57695 (0 MB)
84 14:43:48.431630 No compression specified
85 14:43:48.432782 progress 56 % (0 MB)
86 14:43:48.433078 progress 100 % (0 MB)
87 14:43:48.433321 0 MB downloaded in 0.00 s (31.48 MB/s)
88 14:43:48.433444 end: 1.3.1 http-download (duration 00:00:00) [common]
90 14:43:48.433664 end: 1.3 download-retry (duration 00:00:00) [common]
91 14:43:48.433746 start: 1.4 download-retry (timeout 00:09:59) [common]
92 14:43:48.433827 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 14:43:48.433940 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 14:43:48.434006 saving as /var/lib/lava/dispatcher/tmp/14166990/tftp-deploy-muq91wc3/nfsrootfs/full.rootfs.tar
95 14:43:48.434065 total size: 120894716 (115 MB)
96 14:43:48.434124 Using unxz to decompress xz
97 14:43:48.438258 progress 0 % (0 MB)
98 14:43:48.790812 progress 5 % (5 MB)
99 14:43:49.161717 progress 10 % (11 MB)
100 14:43:49.518410 progress 15 % (17 MB)
101 14:43:49.848612 progress 20 % (23 MB)
102 14:43:50.141654 progress 25 % (28 MB)
103 14:43:50.500778 progress 30 % (34 MB)
104 14:43:50.843580 progress 35 % (40 MB)
105 14:43:51.015476 progress 40 % (46 MB)
106 14:43:51.197877 progress 45 % (51 MB)
107 14:43:51.510476 progress 50 % (57 MB)
108 14:43:51.888863 progress 55 % (63 MB)
109 14:43:52.237405 progress 60 % (69 MB)
110 14:43:52.595759 progress 65 % (74 MB)
111 14:43:52.948121 progress 70 % (80 MB)
112 14:43:53.313794 progress 75 % (86 MB)
113 14:43:53.672622 progress 80 % (92 MB)
114 14:43:54.024465 progress 85 % (98 MB)
115 14:43:54.392318 progress 90 % (103 MB)
116 14:43:54.730326 progress 95 % (109 MB)
117 14:43:55.094564 progress 100 % (115 MB)
118 14:43:55.099884 115 MB downloaded in 6.67 s (17.30 MB/s)
119 14:43:55.100188 end: 1.4.1 http-download (duration 00:00:07) [common]
121 14:43:55.100477 end: 1.4 download-retry (duration 00:00:07) [common]
122 14:43:55.100583 start: 1.5 download-retry (timeout 00:09:53) [common]
123 14:43:55.100684 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 14:43:55.100879 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 14:43:55.100971 saving as /var/lib/lava/dispatcher/tmp/14166990/tftp-deploy-muq91wc3/modules/modules.tar
126 14:43:55.101035 total size: 8608920 (8 MB)
127 14:43:55.101099 Using unxz to decompress xz
128 14:43:55.105488 progress 0 % (0 MB)
129 14:43:55.125387 progress 5 % (0 MB)
130 14:43:55.154478 progress 10 % (0 MB)
131 14:43:55.185922 progress 15 % (1 MB)
132 14:43:55.210184 progress 20 % (1 MB)
133 14:43:55.235472 progress 25 % (2 MB)
134 14:43:55.260027 progress 30 % (2 MB)
135 14:43:55.284954 progress 35 % (2 MB)
136 14:43:55.312099 progress 40 % (3 MB)
137 14:43:55.335130 progress 45 % (3 MB)
138 14:43:55.359807 progress 50 % (4 MB)
139 14:43:55.385616 progress 55 % (4 MB)
140 14:43:55.410488 progress 60 % (4 MB)
141 14:43:55.435020 progress 65 % (5 MB)
142 14:43:55.460634 progress 70 % (5 MB)
143 14:43:55.487085 progress 75 % (6 MB)
144 14:43:55.514271 progress 80 % (6 MB)
145 14:43:55.539167 progress 85 % (7 MB)
146 14:43:55.565207 progress 90 % (7 MB)
147 14:43:55.591224 progress 95 % (7 MB)
148 14:43:55.617028 progress 100 % (8 MB)
149 14:43:55.622735 8 MB downloaded in 0.52 s (15.74 MB/s)
150 14:43:55.623037 end: 1.5.1 http-download (duration 00:00:01) [common]
152 14:43:55.623310 end: 1.5 download-retry (duration 00:00:01) [common]
153 14:43:55.623405 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 14:43:55.623502 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 14:43:59.192095 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14166990/extract-nfsrootfs-830ytlfh
156 14:43:59.192309 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 14:43:59.192405 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 14:43:59.192585 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy
159 14:43:59.192749 makedir: /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin
160 14:43:59.192865 makedir: /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/tests
161 14:43:59.192965 makedir: /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/results
162 14:43:59.193066 Creating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-add-keys
163 14:43:59.193209 Creating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-add-sources
164 14:43:59.193364 Creating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-background-process-start
165 14:43:59.193488 Creating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-background-process-stop
166 14:43:59.193609 Creating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-common-functions
167 14:43:59.193730 Creating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-echo-ipv4
168 14:43:59.193850 Creating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-install-packages
169 14:43:59.193968 Creating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-installed-packages
170 14:43:59.194087 Creating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-os-build
171 14:43:59.194208 Creating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-probe-channel
172 14:43:59.194328 Creating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-probe-ip
173 14:43:59.194447 Creating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-target-ip
174 14:43:59.194565 Creating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-target-mac
175 14:43:59.194683 Creating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-target-storage
176 14:43:59.194803 Creating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-test-case
177 14:43:59.194921 Creating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-test-event
178 14:43:59.195040 Creating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-test-feedback
179 14:43:59.195157 Creating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-test-raise
180 14:43:59.195278 Creating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-test-reference
181 14:43:59.195397 Creating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-test-runner
182 14:43:59.195515 Creating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-test-set
183 14:43:59.195667 Creating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-test-shell
184 14:43:59.195847 Updating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-add-keys (debian)
185 14:43:59.196006 Updating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-add-sources (debian)
186 14:43:59.196176 Updating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-install-packages (debian)
187 14:43:59.196313 Updating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-installed-packages (debian)
188 14:43:59.196450 Updating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/bin/lava-os-build (debian)
189 14:43:59.196568 Creating /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/environment
190 14:43:59.196664 LAVA metadata
191 14:43:59.196729 - LAVA_JOB_ID=14166990
192 14:43:59.196790 - LAVA_DISPATCHER_IP=192.168.201.1
193 14:43:59.196895 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 14:43:59.196961 skipped lava-vland-overlay
195 14:43:59.197034 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 14:43:59.197111 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 14:43:59.197170 skipped lava-multinode-overlay
198 14:43:59.197240 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 14:43:59.197371 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 14:43:59.197446 Loading test definitions
201 14:43:59.197533 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 14:43:59.197601 Using /lava-14166990 at stage 0
203 14:43:59.197924 uuid=14166990_1.6.2.3.1 testdef=None
204 14:43:59.198045 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 14:43:59.198128 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 14:43:59.198575 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 14:43:59.198790 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 14:43:59.199322 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 14:43:59.199576 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 14:43:59.200222 runner path: /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/0/tests/0_timesync-off test_uuid 14166990_1.6.2.3.1
213 14:43:59.200378 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 14:43:59.200597 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 14:43:59.200670 Using /lava-14166990 at stage 0
217 14:43:59.200764 Fetching tests from https://github.com/kernelci/test-definitions.git
218 14:43:59.200849 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/0/tests/1_kselftest-alsa'
219 14:44:01.652486 Running '/usr/bin/git checkout kernelci.org
220 14:44:01.802500 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 14:44:01.803490 uuid=14166990_1.6.2.3.5 testdef=None
222 14:44:01.803700 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 14:44:01.804096 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 14:44:01.805294 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 14:44:01.805674 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 14:44:01.807184 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 14:44:01.807535 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 14:44:01.808950 runner path: /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/0/tests/1_kselftest-alsa test_uuid 14166990_1.6.2.3.5
232 14:44:01.809076 BOARD='mt8183-kukui-jacuzzi-juniper-sku16'
233 14:44:01.809169 BRANCH='cip'
234 14:44:01.809262 SKIPFILE='/dev/null'
235 14:44:01.809386 SKIP_INSTALL='True'
236 14:44:01.809473 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 14:44:01.809564 TST_CASENAME=''
238 14:44:01.809651 TST_CMDFILES='alsa'
239 14:44:01.809843 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 14:44:01.810160 Creating lava-test-runner.conf files
242 14:44:01.810255 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14166990/lava-overlay-w4vv9nfy/lava-14166990/0 for stage 0
243 14:44:01.810385 - 0_timesync-off
244 14:44:01.810486 - 1_kselftest-alsa
245 14:44:01.810624 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 14:44:01.810748 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 14:44:09.358716 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 14:44:09.358878 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 14:44:09.358971 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 14:44:09.359068 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 14:44:09.359159 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 14:44:09.525017 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 14:44:09.525456 start: 1.6.4 extract-modules (timeout 00:09:38) [common]
254 14:44:09.525573 extracting modules file /var/lib/lava/dispatcher/tmp/14166990/tftp-deploy-muq91wc3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14166990/extract-nfsrootfs-830ytlfh
255 14:44:09.750442 extracting modules file /var/lib/lava/dispatcher/tmp/14166990/tftp-deploy-muq91wc3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14166990/extract-overlay-ramdisk-xxdjmi35/ramdisk
256 14:44:09.972352 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 14:44:09.972533 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 14:44:09.972629 [common] Applying overlay to NFS
259 14:44:09.972700 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14166990/compress-overlay-e_jakdjp/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14166990/extract-nfsrootfs-830ytlfh
260 14:44:10.891194 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 14:44:10.891367 start: 1.6.6 configure-preseed-file (timeout 00:09:37) [common]
262 14:44:10.891481 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 14:44:10.891593 start: 1.6.7 compress-ramdisk (timeout 00:09:37) [common]
264 14:44:10.891675 Building ramdisk /var/lib/lava/dispatcher/tmp/14166990/extract-overlay-ramdisk-xxdjmi35/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14166990/extract-overlay-ramdisk-xxdjmi35/ramdisk
265 14:44:11.230560 >> 130335 blocks
266 14:44:13.266978 rename /var/lib/lava/dispatcher/tmp/14166990/extract-overlay-ramdisk-xxdjmi35/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14166990/tftp-deploy-muq91wc3/ramdisk/ramdisk.cpio.gz
267 14:44:13.267569 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 14:44:13.267764 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 14:44:13.267924 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 14:44:13.268110 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14166990/tftp-deploy-muq91wc3/kernel/Image']
271 14:44:27.151582 Returned 0 in 13 seconds
272 14:44:27.252547 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14166990/tftp-deploy-muq91wc3/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14166990/tftp-deploy-muq91wc3/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14166990/tftp-deploy-muq91wc3/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14166990/tftp-deploy-muq91wc3/kernel/image.itb
273 14:44:27.644604 output: FIT description: Kernel Image image with one or more FDT blobs
274 14:44:27.644964 output: Created: Tue Jun 4 15:44:27 2024
275 14:44:27.645039 output: Image 0 (kernel-1)
276 14:44:27.645104 output: Description:
277 14:44:27.645170 output: Created: Tue Jun 4 15:44:27 2024
278 14:44:27.645234 output: Type: Kernel Image
279 14:44:27.645340 output: Compression: lzma compressed
280 14:44:27.645404 output: Data Size: 13060619 Bytes = 12754.51 KiB = 12.46 MiB
281 14:44:27.645464 output: Architecture: AArch64
282 14:44:27.645522 output: OS: Linux
283 14:44:27.645580 output: Load Address: 0x00000000
284 14:44:27.645633 output: Entry Point: 0x00000000
285 14:44:27.645688 output: Hash algo: crc32
286 14:44:27.645743 output: Hash value: 88dcd836
287 14:44:27.645796 output: Image 1 (fdt-1)
288 14:44:27.645852 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
289 14:44:27.645907 output: Created: Tue Jun 4 15:44:27 2024
290 14:44:27.645961 output: Type: Flat Device Tree
291 14:44:27.646016 output: Compression: uncompressed
292 14:44:27.646068 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
293 14:44:27.646121 output: Architecture: AArch64
294 14:44:27.646174 output: Hash algo: crc32
295 14:44:27.646226 output: Hash value: a9713552
296 14:44:27.646279 output: Image 2 (ramdisk-1)
297 14:44:27.646331 output: Description: unavailable
298 14:44:27.646417 output: Created: Tue Jun 4 15:44:27 2024
299 14:44:27.646497 output: Type: RAMDisk Image
300 14:44:27.646556 output: Compression: Unknown Compression
301 14:44:27.646612 output: Data Size: 18720226 Bytes = 18281.47 KiB = 17.85 MiB
302 14:44:27.646669 output: Architecture: AArch64
303 14:44:27.646724 output: OS: Linux
304 14:44:27.646777 output: Load Address: unavailable
305 14:44:27.646830 output: Entry Point: unavailable
306 14:44:27.646882 output: Hash algo: crc32
307 14:44:27.646935 output: Hash value: e56f7ac2
308 14:44:27.646987 output: Default Configuration: 'conf-1'
309 14:44:27.647040 output: Configuration 0 (conf-1)
310 14:44:27.647092 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
311 14:44:27.647145 output: Kernel: kernel-1
312 14:44:27.647197 output: Init Ramdisk: ramdisk-1
313 14:44:27.647250 output: FDT: fdt-1
314 14:44:27.647303 output: Loadables: kernel-1
315 14:44:27.647355 output:
316 14:44:27.647556 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 14:44:27.647655 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 14:44:27.647760 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 14:44:27.647855 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 14:44:27.647933 No LXC device requested
321 14:44:27.648011 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 14:44:27.648095 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 14:44:27.648169 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 14:44:27.648240 Checking files for TFTP limit of 4294967296 bytes.
325 14:44:27.648752 end: 1 tftp-deploy (duration 00:00:40) [common]
326 14:44:27.648866 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 14:44:27.648962 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 14:44:27.649086 substitutions:
329 14:44:27.649153 - {DTB}: 14166990/tftp-deploy-muq91wc3/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
330 14:44:27.649217 - {INITRD}: 14166990/tftp-deploy-muq91wc3/ramdisk/ramdisk.cpio.gz
331 14:44:27.649321 - {KERNEL}: 14166990/tftp-deploy-muq91wc3/kernel/Image
332 14:44:27.649380 - {LAVA_MAC}: None
333 14:44:27.649437 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14166990/extract-nfsrootfs-830ytlfh
334 14:44:27.649494 - {NFS_SERVER_IP}: 192.168.201.1
335 14:44:27.649548 - {PRESEED_CONFIG}: None
336 14:44:27.649603 - {PRESEED_LOCAL}: None
337 14:44:27.649657 - {RAMDISK}: 14166990/tftp-deploy-muq91wc3/ramdisk/ramdisk.cpio.gz
338 14:44:27.649712 - {ROOT_PART}: None
339 14:44:27.649767 - {ROOT}: None
340 14:44:27.649828 - {SERVER_IP}: 192.168.201.1
341 14:44:27.649883 - {TEE}: None
342 14:44:27.649941 Parsed boot commands:
343 14:44:27.649994 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 14:44:27.650177 Parsed boot commands: tftpboot 192.168.201.1 14166990/tftp-deploy-muq91wc3/kernel/image.itb 14166990/tftp-deploy-muq91wc3/kernel/cmdline
345 14:44:27.650266 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 14:44:27.650347 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 14:44:27.650436 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 14:44:27.650521 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 14:44:27.650592 Not connected, no need to disconnect.
350 14:44:27.650664 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 14:44:27.650744 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 14:44:27.650812 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-3'
353 14:44:27.654557 Setting prompt string to ['lava-test: # ']
354 14:44:27.654925 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 14:44:27.655038 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 14:44:27.655140 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 14:44:27.655235 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 14:44:27.655414 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8183-kukui-jacuzzi-juniper-sku16-cbg-3']
359 14:44:51.368994 Returned 0 in 23 seconds
360 14:44:51.469696 end: 2.2.2.1 pdu-reboot (duration 00:00:24) [common]
362 14:44:51.470132 end: 2.2.2 reset-device (duration 00:00:24) [common]
363 14:44:51.470266 start: 2.2.3 depthcharge-start (timeout 00:04:36) [common]
364 14:44:51.470392 Setting prompt string to 'Starting depthcharge on Juniper...'
365 14:44:51.470489 Changing prompt to 'Starting depthcharge on Juniper...'
366 14:44:51.470591 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
367 14:44:51.471265 [Enter `^Ec?' for help]
368 14:44:51.471424 [DL] 00000000 00000000 010701
369 14:44:51.471563
370 14:44:51.471631
371 14:44:51.471693 F0: 102B 0000
372 14:44:51.471759
373 14:44:51.471819 F3: 1006 0033 [0200]
374 14:44:51.471879
375 14:44:51.471936 F3: 4001 00E0 [0200]
376 14:44:51.471991
377 14:44:51.472060 F3: 0000 0000
378 14:44:51.472128
379 14:44:51.472180 V0: 0000 0000 [0001]
380 14:44:51.472234
381 14:44:51.472287 00: 1027 0002
382 14:44:51.472344
383 14:44:51.472397 01: 0000 0000
384 14:44:51.472451
385 14:44:51.472505 BP: 0C00 0251 [0000]
386 14:44:51.472558
387 14:44:51.472610 G0: 1182 0000
388 14:44:51.472694
389 14:44:51.472747 EC: 0004 0000 [0001]
390 14:44:51.472800
391 14:44:51.472851 S7: 0000 0000 [0000]
392 14:44:51.472904
393 14:44:51.472956 CC: 0000 0000 [0001]
394 14:44:51.473009
395 14:44:51.473060 T0: 0000 00DB [000F]
396 14:44:51.473114
397 14:44:51.473166 Jump to BL
398 14:44:51.473219
399 14:44:51.473294
400 14:44:51.473362
401 14:44:51.473415 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
402 14:44:51.473472 ARM64: Exception handlers installed.
403 14:44:51.473526 ARM64: Testing exception
404 14:44:51.473579 ARM64: Done test exception
405 14:44:51.473633 WDT: Last reset was cold boot
406 14:44:51.473686 SPI0(PAD0) initialized at 992727 Hz
407 14:44:51.473739 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
408 14:44:51.473793 Manufacturer: ef
409 14:44:51.473846 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
410 14:44:51.473899 Probing TPM: . done!
411 14:44:51.473952 TPM ready after 0 ms
412 14:44:51.474005 Connected to device vid:did:rid of 1ae0:0028:00
413 14:44:51.474058 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.5.171/cr50_v2.94_mp.164-2fb1dd676c
414 14:44:51.474112 Initialized TPM device CR50 revision 0
415 14:44:51.474165 tlcl_send_startup: Startup return code is 0
416 14:44:51.474218 TPM: setup succeeded
417 14:44:51.474271 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
418 14:44:51.474324 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
419 14:44:51.474377 in-header: 03 19 00 00 08 00 00 00
420 14:44:51.474430 in-data: a2 e0 47 00 13 00 00 00
421 14:44:51.474483 Chrome EC: UHEPI supported
422 14:44:51.474536 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
423 14:44:51.474590 in-header: 03 a1 00 00 08 00 00 00
424 14:44:51.474684 in-data: 84 60 60 10 00 00 00 00
425 14:44:51.474754 Phase 1
426 14:44:51.474821 FMAP: area GBB found @ 3f5000 (12032 bytes)
427 14:44:51.474874 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
428 14:44:51.474927 VB2:vb2_check_recovery() Recovery was requested manually
429 14:44:51.474980 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
430 14:44:51.475033 Recovery requested (1009000e)
431 14:44:51.475085 tlcl_extend: response is 0
432 14:44:51.475138 tlcl_extend: response is 0
433 14:44:51.475191
434 14:44:51.475243
435 14:44:51.475296 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
436 14:44:51.475349 ARM64: Exception handlers installed.
437 14:44:51.475402 ARM64: Testing exception
438 14:44:51.475454 ARM64: Done test exception
439 14:44:51.475507 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0xea6b, sec=0x2000
440 14:44:51.475560 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
441 14:44:51.475613 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
442 14:44:51.475665 [RTC]rtc_get_frequency_meter,134: input=0xf, output=864
443 14:44:51.475718 [RTC]rtc_get_frequency_meter,134: input=0x7, output=734
444 14:44:51.475771 [RTC]rtc_get_frequency_meter,134: input=0xb, output=800
445 14:44:51.475824 [RTC]rtc_get_frequency_meter,134: input=0x9, output=767
446 14:44:51.475877 [RTC]rtc_get_frequency_meter,134: input=0xa, output=783
447 14:44:51.475930 [RTC]rtc_get_frequency_meter,134: input=0xa, output=783
448 14:44:51.475983 [RTC]rtc_get_frequency_meter,134: input=0xb, output=796
449 14:44:51.476036 [RTC]rtc_osc_init,208: EOSC32 cali val = 0xea6b
450 14:44:51.476089 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
451 14:44:51.476142 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
452 14:44:51.476194 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
453 14:44:51.476247 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
454 14:44:51.476300 in-header: 03 19 00 00 08 00 00 00
455 14:44:51.476352 in-data: a2 e0 47 00 13 00 00 00
456 14:44:51.476405 Chrome EC: UHEPI supported
457 14:44:51.476458 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
458 14:44:51.476512 in-header: 03 a1 00 00 08 00 00 00
459 14:44:51.476565 in-data: 84 60 60 10 00 00 00 00
460 14:44:51.476618 Skip loading cached calibration data
461 14:44:51.476670 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
462 14:44:51.476724 in-header: 03 a1 00 00 08 00 00 00
463 14:44:51.476777 in-data: 84 60 60 10 00 00 00 00
464 14:44:51.476830 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
465 14:44:51.476883 in-header: 03 a1 00 00 08 00 00 00
466 14:44:51.476935 in-data: 84 60 60 10 00 00 00 00
467 14:44:51.476987 ADC[3]: Raw value=1037476 ID=8
468 14:44:51.477039 Manufacturer: ef
469 14:44:51.477091 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
470 14:44:51.477145 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
471 14:44:51.477198 CBFS @ 21000 size 3d4000
472 14:44:51.477251 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
473 14:44:51.477344 CBFS: Locating 'sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB'
474 14:44:51.477396 CBFS: Found @ offset 3c880 size 4b
475 14:44:51.477450 DRAM-K: Full Calibration
476 14:44:51.477502 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
477 14:44:51.477556 CBFS @ 21000 size 3d4000
478 14:44:51.477608 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
479 14:44:51.477660 CBFS: Locating 'fallback/dram'
480 14:44:51.477713 CBFS: Found @ offset 24b00 size 12268
481 14:44:51.477765 read SPI 0x45b44 0x1224c: 22774 us, 3263 KB/s, 26.104 Mbps
482 14:44:51.477818 ddr_geometry: 1, config: 0x0
483 14:44:51.477871 header.status = 0x0
484 14:44:51.477924 header.magic = 0x44524d4b (expected: 0x44524d4b)
485 14:44:51.477977 header.version = 0x5 (expected: 0x5)
486 14:44:51.478219 header.size = 0x8f0 (expected: 0x8f0)
487 14:44:51.478279 header.config = 0x0
488 14:44:51.478333 header.flags = 0x0
489 14:44:51.478386 header.checksum = 0x0
490 14:44:51.478439 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
491 14:44:51.478493 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
492 14:44:51.478547 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
493 14:44:51.478600 ddr_geometry:1
494 14:44:51.478654 [EMI] new MDL number = 1
495 14:44:51.478707 dram_cbt_mode_extern: 0
496 14:44:51.478760 dram_cbt_mode [RK0]: 0, [RK1]: 0
497 14:44:51.478813 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
498 14:44:51.478866
499 14:44:51.478918
500 14:44:51.478970 [Bianco] ETT version 0.0.0.1
501 14:44:51.479023 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
502 14:44:51.479076
503 14:44:51.479128 vSetVcoreByFreq with vcore:762500, freq=1600
504 14:44:51.479183
505 14:44:51.479235 [DramcInit]
506 14:44:51.479288 AutoRefreshCKEOff AutoREF OFF
507 14:44:51.479340 DDRPhyPLLSetting-CKEOFF
508 14:44:51.479393 DDRPhyPLLSetting-CKEON
509 14:44:51.479445
510 14:44:51.479497 Enable WDQS
511 14:44:51.479550 [ModeRegInit_LP4] CH0 RK0
512 14:44:51.479603 Write Rank0 MR13 =0x18
513 14:44:51.479655 Write Rank0 MR12 =0x5d
514 14:44:51.479707 Write Rank0 MR1 =0x56
515 14:44:51.479760 Write Rank0 MR2 =0x1a
516 14:44:51.479812 Write Rank0 MR11 =0x0
517 14:44:51.479865 Write Rank0 MR22 =0x38
518 14:44:51.479917 Write Rank0 MR14 =0x5d
519 14:44:51.479970 Write Rank0 MR3 =0x30
520 14:44:51.480053 Write Rank0 MR13 =0x58
521 14:44:51.480126 Write Rank0 MR12 =0x5d
522 14:44:51.480192 Write Rank0 MR1 =0x56
523 14:44:51.480244 Write Rank0 MR2 =0x2d
524 14:44:51.480296 Write Rank0 MR11 =0x23
525 14:44:51.480350 Write Rank0 MR22 =0x34
526 14:44:51.480402 Write Rank0 MR14 =0x10
527 14:44:51.480455 Write Rank0 MR3 =0x30
528 14:44:51.480507 Write Rank0 MR13 =0xd8
529 14:44:51.480559 [ModeRegInit_LP4] CH0 RK1
530 14:44:51.480612 Write Rank1 MR13 =0x18
531 14:44:51.480664 Write Rank1 MR12 =0x5d
532 14:44:51.480717 Write Rank1 MR1 =0x56
533 14:44:51.480769 Write Rank1 MR2 =0x1a
534 14:44:51.480821 Write Rank1 MR11 =0x0
535 14:44:51.480873 Write Rank1 MR22 =0x38
536 14:44:51.480926 Write Rank1 MR14 =0x5d
537 14:44:51.480977 Write Rank1 MR3 =0x30
538 14:44:51.481029 Write Rank1 MR13 =0x58
539 14:44:51.481081 Write Rank1 MR12 =0x5d
540 14:44:51.481134 Write Rank1 MR1 =0x56
541 14:44:51.481186 Write Rank1 MR2 =0x2d
542 14:44:51.481239 Write Rank1 MR11 =0x23
543 14:44:51.481297 Write Rank1 MR22 =0x34
544 14:44:51.481351 Write Rank1 MR14 =0x10
545 14:44:51.481404 Write Rank1 MR3 =0x30
546 14:44:51.481457 Write Rank1 MR13 =0xd8
547 14:44:51.481509 [ModeRegInit_LP4] CH1 RK0
548 14:44:51.481562 Write Rank0 MR13 =0x18
549 14:44:51.481614 Write Rank0 MR12 =0x5d
550 14:44:51.481666 Write Rank0 MR1 =0x56
551 14:44:51.481719 Write Rank0 MR2 =0x1a
552 14:44:51.481771 Write Rank0 MR11 =0x0
553 14:44:51.481824 Write Rank0 MR22 =0x38
554 14:44:51.481877 Write Rank0 MR14 =0x5d
555 14:44:51.481929 Write Rank0 MR3 =0x30
556 14:44:51.481982 Write Rank0 MR13 =0x58
557 14:44:51.482034 Write Rank0 MR12 =0x5d
558 14:44:51.482087 Write Rank0 MR1 =0x56
559 14:44:51.482139 Write Rank0 MR2 =0x2d
560 14:44:51.482192 Write Rank0 MR11 =0x23
561 14:44:51.482245 Write Rank0 MR22 =0x34
562 14:44:51.482297 Write Rank0 MR14 =0x10
563 14:44:51.482349 Write Rank0 MR3 =0x30
564 14:44:51.482402 Write Rank0 MR13 =0xd8
565 14:44:51.482455 [ModeRegInit_LP4] CH1 RK1
566 14:44:51.482507 Write Rank1 MR13 =0x18
567 14:44:51.482559 Write Rank1 MR12 =0x5d
568 14:44:51.482611 Write Rank1 MR1 =0x56
569 14:44:51.482723 Write Rank1 MR2 =0x1a
570 14:44:51.482814 Write Rank1 MR11 =0x0
571 14:44:51.482872 Write Rank1 MR22 =0x38
572 14:44:51.482926 Write Rank1 MR14 =0x5d
573 14:44:51.482979 Write Rank1 MR3 =0x30
574 14:44:51.483032 Write Rank1 MR13 =0x58
575 14:44:51.483086 Write Rank1 MR12 =0x5d
576 14:44:51.483139 Write Rank1 MR1 =0x56
577 14:44:51.483192 Write Rank1 MR2 =0x2d
578 14:44:51.483244 Write Rank1 MR11 =0x23
579 14:44:51.483297 Write Rank1 MR22 =0x34
580 14:44:51.483349 Write Rank1 MR14 =0x10
581 14:44:51.483402 Write Rank1 MR3 =0x30
582 14:44:51.483455 Write Rank1 MR13 =0xd8
583 14:44:51.483507 match AC timing 3
584 14:44:51.483560 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
585 14:44:51.483614 [MiockJmeterHQA]
586 14:44:51.483667 vSetVcoreByFreq with vcore:762500, freq=1600
587 14:44:51.483720
588 14:44:51.483773 MIOCK jitter meter ch=0
589 14:44:51.483826
590 14:44:51.483878 1T = (100-18) = 82 dly cells
591 14:44:51.483949 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 762/100 ps
592 14:44:51.484017 vSetVcoreByFreq with vcore:725000, freq=1200
593 14:44:51.484070
594 14:44:51.484122 MIOCK jitter meter ch=0
595 14:44:51.484175
596 14:44:51.484228 1T = (95-17) = 78 dly cells
597 14:44:51.484282 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 801/100 ps
598 14:44:51.484335 vSetVcoreByFreq with vcore:725000, freq=800
599 14:44:51.484388
600 14:44:51.484440 MIOCK jitter meter ch=0
601 14:44:51.484493
602 14:44:51.484546 1T = (95-17) = 78 dly cells
603 14:44:51.484600 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 801/100 ps
604 14:44:51.484652 vSetVcoreByFreq with vcore:762500, freq=1600
605 14:44:51.484706 vSetVcoreByFreq with vcore:762500, freq=1600
606 14:44:51.484759
607 14:44:51.484811 K DRVP
608 14:44:51.484864 1. OCD DRVP=0 CALOUT=0
609 14:44:51.484918 1. OCD DRVP=1 CALOUT=0
610 14:44:51.484973 1. OCD DRVP=2 CALOUT=0
611 14:44:51.485027 1. OCD DRVP=3 CALOUT=0
612 14:44:51.485081 1. OCD DRVP=4 CALOUT=0
613 14:44:51.485134 1. OCD DRVP=5 CALOUT=0
614 14:44:51.485188 1. OCD DRVP=6 CALOUT=0
615 14:44:51.485243 1. OCD DRVP=7 CALOUT=0
616 14:44:51.485344 1. OCD DRVP=8 CALOUT=0
617 14:44:51.485399 1. OCD DRVP=9 CALOUT=1
618 14:44:51.485454
619 14:44:51.485507 1. OCD DRVP calibration OK! DRVP=9
620 14:44:51.485561
621 14:44:51.485614
622 14:44:51.485666
623 14:44:51.485719 K ODTN
624 14:44:51.485772 3. OCD ODTN=0 ,CALOUT=1
625 14:44:51.485826 3. OCD ODTN=1 ,CALOUT=1
626 14:44:51.485880 3. OCD ODTN=2 ,CALOUT=1
627 14:44:51.485934 3. OCD ODTN=3 ,CALOUT=1
628 14:44:51.485988 3. OCD ODTN=4 ,CALOUT=1
629 14:44:51.486042 3. OCD ODTN=5 ,CALOUT=1
630 14:44:51.486096 3. OCD ODTN=6 ,CALOUT=1
631 14:44:51.486150 3. OCD ODTN=7 ,CALOUT=0
632 14:44:51.486203
633 14:44:51.486256 3. OCD ODTN calibration OK! ODTN=7
634 14:44:51.486310
635 14:44:51.486362 [SwImpedanceCal] DRVP=9, DRVN=9, ODTN=7
636 14:44:51.486415 term_option=0, Reg: DRVP=9, DRVN=7, ODTN=15
637 14:44:51.486469 term_option=0, Reg: DRVP=9, DRVN=7, ODTN=15 (After Adjust)
638 14:44:51.486521
639 14:44:51.486574 K DRVP
640 14:44:51.486651 1. OCD DRVP=0 CALOUT=0
641 14:44:51.486740 1. OCD DRVP=1 CALOUT=0
642 14:44:51.486809 1. OCD DRVP=2 CALOUT=0
643 14:44:51.486862 1. OCD DRVP=3 CALOUT=0
644 14:44:51.486916 1. OCD DRVP=4 CALOUT=0
645 14:44:51.486970 1. OCD DRVP=5 CALOUT=0
646 14:44:51.487024 1. OCD DRVP=6 CALOUT=0
647 14:44:51.487078 1. OCD DRVP=7 CALOUT=0
648 14:44:51.487132 1. OCD DRVP=8 CALOUT=0
649 14:44:51.487186 1. OCD DRVP=9 CALOUT=0
650 14:44:51.487429 1. OCD DRVP=10 CALOUT=1
651 14:44:51.487581
652 14:44:51.487721 1. OCD DRVP calibration OK! DRVP=10
653 14:44:51.487869
654 14:44:51.488011
655 14:44:51.488138
656 14:44:51.488266 K ODTN
657 14:44:51.488458 3. OCD ODTN=0 ,CALOUT=1
658 14:44:51.488586 3. OCD ODTN=1 ,CALOUT=1
659 14:44:51.488646 3. OCD ODTN=2 ,CALOUT=1
660 14:44:51.488702 3. OCD ODTN=3 ,CALOUT=1
661 14:44:51.488756 3. OCD ODTN=4 ,CALOUT=1
662 14:44:51.488811 3. OCD ODTN=5 ,CALOUT=1
663 14:44:51.488865 3. OCD ODTN=6 ,CALOUT=1
664 14:44:51.488920 3. OCD ODTN=7 ,CALOUT=1
665 14:44:51.488973 3. OCD ODTN=8 ,CALOUT=1
666 14:44:51.489027 3. OCD ODTN=9 ,CALOUT=1
667 14:44:51.489081 3. OCD ODTN=10 ,CALOUT=1
668 14:44:51.489134 3. OCD ODTN=11 ,CALOUT=1
669 14:44:51.489188 3. OCD ODTN=12 ,CALOUT=1
670 14:44:51.489242 3. OCD ODTN=13 ,CALOUT=1
671 14:44:51.489334 3. OCD ODTN=14 ,CALOUT=0
672 14:44:51.489389
673 14:44:51.489442 3. OCD ODTN calibration OK! ODTN=14
674 14:44:51.489496
675 14:44:51.489549 [SwImpedanceCal] DRVP=10, DRVN=9, ODTN=14
676 14:44:51.489602 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=14
677 14:44:51.489655 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=14 (After Adjust)
678 14:44:51.489709
679 14:44:51.489761 [DramcInit]
680 14:44:51.489814 AutoRefreshCKEOff AutoREF OFF
681 14:44:51.489867 DDRPhyPLLSetting-CKEOFF
682 14:44:51.489920 DDRPhyPLLSetting-CKEON
683 14:44:51.489973
684 14:44:51.490025 Enable WDQS
685 14:44:51.490077 ==
686 14:44:51.490131 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
687 14:44:51.490183 fsp= 1, odt_onoff= 1, Byte mode= 0
688 14:44:51.490236 ==
689 14:44:51.490289 [Duty_Offset_Calibration]
690 14:44:51.490342
691 14:44:51.490394 ===========================
692 14:44:51.490446 B0:0 B1:1 CA:1
693 14:44:51.490499 ==
694 14:44:51.490551 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
695 14:44:51.490604 fsp= 1, odt_onoff= 1, Byte mode= 0
696 14:44:51.490656 ==
697 14:44:51.490708 [Duty_Offset_Calibration]
698 14:44:51.490760
699 14:44:51.490812 ===========================
700 14:44:51.490865 B0:1 B1:1 CA:0
701 14:44:51.490917 [ModeRegInit_LP4] CH0 RK0
702 14:44:51.490971 Write Rank0 MR13 =0x18
703 14:44:51.491023 Write Rank0 MR12 =0x5d
704 14:44:51.491075 Write Rank0 MR1 =0x56
705 14:44:51.491128 Write Rank0 MR2 =0x1a
706 14:44:51.491180 Write Rank0 MR11 =0x0
707 14:44:51.491232 Write Rank0 MR22 =0x38
708 14:44:51.491285 Write Rank0 MR14 =0x5d
709 14:44:51.491337 Write Rank0 MR3 =0x30
710 14:44:51.491390 Write Rank0 MR13 =0x58
711 14:44:51.491442 Write Rank0 MR12 =0x5d
712 14:44:51.491494 Write Rank0 MR1 =0x56
713 14:44:51.491546 Write Rank0 MR2 =0x2d
714 14:44:51.491599 Write Rank0 MR11 =0x23
715 14:44:51.491652 Write Rank0 MR22 =0x34
716 14:44:51.491735 Write Rank0 MR14 =0x10
717 14:44:51.491815 Write Rank0 MR3 =0x30
718 14:44:51.491868 Write Rank0 MR13 =0xd8
719 14:44:51.491920 [ModeRegInit_LP4] CH0 RK1
720 14:44:51.491973 Write Rank1 MR13 =0x18
721 14:44:51.492025 Write Rank1 MR12 =0x5d
722 14:44:51.492078 Write Rank1 MR1 =0x56
723 14:44:51.492130 Write Rank1 MR2 =0x1a
724 14:44:51.492183 Write Rank1 MR11 =0x0
725 14:44:51.492234 Write Rank1 MR22 =0x38
726 14:44:51.492287 Write Rank1 MR14 =0x5d
727 14:44:51.492339 Write Rank1 MR3 =0x30
728 14:44:51.492391 Write Rank1 MR13 =0x58
729 14:44:51.492443 Write Rank1 MR12 =0x5d
730 14:44:51.492495 Write Rank1 MR1 =0x56
731 14:44:51.492547 Write Rank1 MR2 =0x2d
732 14:44:51.492599 Write Rank1 MR11 =0x23
733 14:44:51.492651 Write Rank1 MR22 =0x34
734 14:44:51.492703 Write Rank1 MR14 =0x10
735 14:44:51.492756 Write Rank1 MR3 =0x30
736 14:44:51.492808 Write Rank1 MR13 =0xd8
737 14:44:51.492860 [ModeRegInit_LP4] CH1 RK0
738 14:44:51.492912 Write Rank0 MR13 =0x18
739 14:44:51.492964 Write Rank0 MR12 =0x5d
740 14:44:51.493017 Write Rank0 MR1 =0x56
741 14:44:51.493069 Write Rank0 MR2 =0x1a
742 14:44:51.493121 Write Rank0 MR11 =0x0
743 14:44:51.493173 Write Rank0 MR22 =0x38
744 14:44:51.493225 Write Rank0 MR14 =0x5d
745 14:44:51.493313 Write Rank0 MR3 =0x30
746 14:44:51.493366 Write Rank0 MR13 =0x58
747 14:44:51.493418 Write Rank0 MR12 =0x5d
748 14:44:51.493470 Write Rank0 MR1 =0x56
749 14:44:51.493522 Write Rank0 MR2 =0x2d
750 14:44:51.493575 Write Rank0 MR11 =0x23
751 14:44:51.493627 Write Rank0 MR22 =0x34
752 14:44:51.493679 Write Rank0 MR14 =0x10
753 14:44:51.493732 Write Rank0 MR3 =0x30
754 14:44:51.493784 Write Rank0 MR13 =0xd8
755 14:44:51.493836 [ModeRegInit_LP4] CH1 RK1
756 14:44:51.493888 Write Rank1 MR13 =0x18
757 14:44:51.493940 Write Rank1 MR12 =0x5d
758 14:44:51.493992 Write Rank1 MR1 =0x56
759 14:44:51.494044 Write Rank1 MR2 =0x1a
760 14:44:51.494096 Write Rank1 MR11 =0x0
761 14:44:51.494149 Write Rank1 MR22 =0x38
762 14:44:51.494201 Write Rank1 MR14 =0x5d
763 14:44:51.494252 Write Rank1 MR3 =0x30
764 14:44:51.494305 Write Rank1 MR13 =0x58
765 14:44:51.494357 Write Rank1 MR12 =0x5d
766 14:44:51.494410 Write Rank1 MR1 =0x56
767 14:44:51.494462 Write Rank1 MR2 =0x2d
768 14:44:51.494513 Write Rank1 MR11 =0x23
769 14:44:51.494565 Write Rank1 MR22 =0x34
770 14:44:51.494617 Write Rank1 MR14 =0x10
771 14:44:51.494668 Write Rank1 MR3 =0x30
772 14:44:51.494720 Write Rank1 MR13 =0xd8
773 14:44:51.494773 match AC timing 3
774 14:44:51.494825 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
775 14:44:51.494879 DramC Write-DBI off
776 14:44:51.494931 DramC Read-DBI off
777 14:44:51.494983 Write Rank0 MR13 =0x59
778 14:44:51.495035 ==
779 14:44:51.495088 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
780 14:44:51.495141 fsp= 1, odt_onoff= 1, Byte mode= 0
781 14:44:51.495194 ==
782 14:44:51.495246 === u2Vref_new: 0x56 --> 0x2d
783 14:44:51.495298 === u2Vref_new: 0x58 --> 0x38
784 14:44:51.495351 === u2Vref_new: 0x5a --> 0x39
785 14:44:51.495404 === u2Vref_new: 0x5c --> 0x3c
786 14:44:51.495457 === u2Vref_new: 0x5e --> 0x3d
787 14:44:51.495509 === u2Vref_new: 0x60 --> 0xa0
788 14:44:51.495562
789 14:44:51.495614 CBT Vref found, early break!
790 14:44:51.495666 [CA 0] Center 33 (4~63) winsize 60
791 14:44:51.495719 [CA 1] Center 34 (5~63) winsize 59
792 14:44:51.495772 [CA 2] Center 29 (1~57) winsize 57
793 14:44:51.495824 [CA 3] Center 24 (-3~51) winsize 55
794 14:44:51.495877 [CA 4] Center 25 (-2~52) winsize 55
795 14:44:51.495930 [CA 5] Center 30 (2~58) winsize 57
796 14:44:51.495982
797 14:44:51.496034 [CATrainingPosCal] consider 1 rank data
798 14:44:51.496086 u2DelayCellTimex100 = 762/100 ps
799 14:44:51.496139 CA0 delay=33 (4~63),Diff = 9 PI (11 cell)
800 14:44:51.496192 CA1 delay=34 (5~63),Diff = 10 PI (12 cell)
801 14:44:51.496245 CA2 delay=29 (1~57),Diff = 5 PI (6 cell)
802 14:44:51.496298 CA3 delay=24 (-3~51),Diff = 0 PI (0 cell)
803 14:44:51.496350 CA4 delay=25 (-2~52),Diff = 1 PI (1 cell)
804 14:44:51.496403 CA5 delay=30 (2~58),Diff = 6 PI (7 cell)
805 14:44:51.496455
806 14:44:51.496507 CA PerBit enable=1, Macro0, CA PI delay=24
807 14:44:51.496560 === u2Vref_new: 0x56 --> 0x2d
808 14:44:51.496613
809 14:44:51.496665 Vref(ca) range 1: 22
810 14:44:51.496718
811 14:44:51.496770 CS Dly= 10 (41-0-32)
812 14:44:51.496823 Write Rank0 MR13 =0xd8
813 14:44:51.496875 Write Rank0 MR13 =0xd8
814 14:44:51.496927 Write Rank0 MR12 =0x56
815 14:44:51.497190 Write Rank1 MR13 =0x59
816 14:44:51.497251 ==
817 14:44:51.497348 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
818 14:44:51.497402 fsp= 1, odt_onoff= 1, Byte mode= 0
819 14:44:51.497456 ==
820 14:44:51.497510 === u2Vref_new: 0x56 --> 0x2d
821 14:44:51.497563 === u2Vref_new: 0x58 --> 0x38
822 14:44:51.497617 === u2Vref_new: 0x5a --> 0x39
823 14:44:51.497671 === u2Vref_new: 0x5c --> 0x3c
824 14:44:51.497723 === u2Vref_new: 0x5e --> 0x3d
825 14:44:51.497776 === u2Vref_new: 0x60 --> 0xa0
826 14:44:51.497829 [CA 0] Center 34 (5~63) winsize 59
827 14:44:51.497882 [CA 1] Center 34 (6~63) winsize 58
828 14:44:51.497934 [CA 2] Center 29 (1~58) winsize 58
829 14:44:51.497988 [CA 3] Center 23 (-4~51) winsize 56
830 14:44:51.498040 [CA 4] Center 24 (-3~52) winsize 56
831 14:44:51.498094 [CA 5] Center 30 (1~59) winsize 59
832 14:44:51.498146
833 14:44:51.498199 [CATrainingPosCal] consider 2 rank data
834 14:44:51.498252 u2DelayCellTimex100 = 762/100 ps
835 14:44:51.498305 CA0 delay=34 (5~63),Diff = 10 PI (12 cell)
836 14:44:51.498358 CA1 delay=34 (6~63),Diff = 10 PI (12 cell)
837 14:44:51.498412 CA2 delay=29 (1~57),Diff = 5 PI (6 cell)
838 14:44:51.498464 CA3 delay=24 (-3~51),Diff = 0 PI (0 cell)
839 14:44:51.498517 CA4 delay=25 (-2~52),Diff = 1 PI (1 cell)
840 14:44:51.498570 CA5 delay=30 (2~58),Diff = 6 PI (7 cell)
841 14:44:51.498623
842 14:44:51.498676 CA PerBit enable=1, Macro0, CA PI delay=24
843 14:44:51.498728 === u2Vref_new: 0x56 --> 0x2d
844 14:44:51.498782
845 14:44:51.498834 Vref(ca) range 1: 22
846 14:44:51.498887
847 14:44:51.498940 CS Dly= 11 (42-0-32)
848 14:44:51.498993 Write Rank1 MR13 =0xd8
849 14:44:51.499045 Write Rank1 MR13 =0xd8
850 14:44:51.499098 Write Rank1 MR12 =0x56
851 14:44:51.499150 [RankSwap] Rank num 2, (Multi 1), Rank 0
852 14:44:51.499204 Write Rank0 MR2 =0xad
853 14:44:51.499256 [Write Leveling]
854 14:44:51.499308 delay byte0 byte1 byte2 byte3
855 14:44:51.499361
856 14:44:51.499414 10 0 0
857 14:44:51.499468 11 0 0
858 14:44:51.499522 12 0 0
859 14:44:51.499576 13 0 0
860 14:44:51.499629 14 0 0
861 14:44:51.499682 15 0 0
862 14:44:51.499736 16 0 0
863 14:44:51.499790 17 0 0
864 14:44:51.499843 18 0 0
865 14:44:51.499896 19 0 0
866 14:44:51.499949 20 0 0
867 14:44:51.500003 21 0 0
868 14:44:51.500056 22 0 0
869 14:44:51.500110 23 0 0
870 14:44:51.500174 24 0 0
871 14:44:51.500229 25 0 ff
872 14:44:51.500310 26 0 ff
873 14:44:51.500363 27 0 ff
874 14:44:51.500416 28 0 ff
875 14:44:51.500469 29 0 ff
876 14:44:51.500522 30 0 ff
877 14:44:51.500575 31 0 ff
878 14:44:51.500628 32 ff ff
879 14:44:51.500681 33 ff ff
880 14:44:51.500734 34 ff ff
881 14:44:51.500788 35 ff ff
882 14:44:51.500841 36 ff ff
883 14:44:51.500894 37 ff ff
884 14:44:51.500947 38 ff ff
885 14:44:51.501001 pass bytecount = 0xff (0xff: all bytes pass)
886 14:44:51.501054
887 14:44:51.501106 DQS0 dly: 32
888 14:44:51.501158 DQS1 dly: 25
889 14:44:51.501210 Write Rank0 MR2 =0x2d
890 14:44:51.501285 [RankSwap] Rank num 2, (Multi 1), Rank 0
891 14:44:51.501355 Write Rank0 MR1 =0xd6
892 14:44:51.501408 [Gating]
893 14:44:51.501461 ==
894 14:44:51.501513 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
895 14:44:51.501567 fsp= 1, odt_onoff= 1, Byte mode= 0
896 14:44:51.501620 ==
897 14:44:51.501674 3 1 0 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
898 14:44:51.501728 3 1 4 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
899 14:44:51.501783 3 1 8 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
900 14:44:51.501836 3 1 12 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
901 14:44:51.501890 3 1 16 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
902 14:44:51.501944 3 1 20 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
903 14:44:51.501998 3 1 24 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
904 14:44:51.502052 3 1 28 |1716 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
905 14:44:51.502106 3 2 0 |303 2c2b |(11 11)(11 11) |(0 0)(0 0)| 0
906 14:44:51.502160 3 2 4 |3534 201 |(11 11)(11 11) |(0 0)(0 0)| 0
907 14:44:51.502214 3 2 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
908 14:44:51.502268 3 2 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
909 14:44:51.502322 3 2 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
910 14:44:51.502376 3 2 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
911 14:44:51.502430 3 2 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
912 14:44:51.502487 3 2 28 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
913 14:44:51.502541 3 3 0 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
914 14:44:51.502595 3 3 4 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
915 14:44:51.502649 3 3 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
916 14:44:51.502703 3 3 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
917 14:44:51.502757 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
918 14:44:51.502811 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
919 14:44:51.502864 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
920 14:44:51.502918 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
921 14:44:51.502971 3 4 0 |b0a 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
922 14:44:51.503025 3 4 4 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
923 14:44:51.503078 3 4 8 |3d3d 1c1c |(11 11)(11 11) |(1 1)(1 1)| 0
924 14:44:51.503132 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
925 14:44:51.503203 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
926 14:44:51.503269 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
927 14:44:51.503323 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
928 14:44:51.503376 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
929 14:44:51.503430 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
930 14:44:51.503499 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
931 14:44:51.503567 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
932 14:44:51.503620 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
933 14:44:51.503674 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
934 14:44:51.503728 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
935 14:44:51.503781 [Byte 0] Lead/lag falling Transition (3, 5, 20)
936 14:44:51.503835 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
937 14:44:51.503889 [Byte 0] Lead/lag Transition tap number (2)
938 14:44:51.503942 [Byte 1] Lead/lag falling Transition (3, 5, 24)
939 14:44:51.503994 3 5 28 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
940 14:44:51.504246 3 6 0 |404 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
941 14:44:51.504386 [Byte 1] Lead/lag Transition tap number (3)
942 14:44:51.504516 3 6 4 |4646 3e3d |(0 0)(11 11) |(0 0)(0 0)| 0
943 14:44:51.504649 [Byte 0]First pass (3, 6, 4)
944 14:44:51.504779 3 6 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
945 14:44:51.504911 [Byte 1]First pass (3, 6, 8)
946 14:44:51.505041 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
947 14:44:51.505172 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
948 14:44:51.505341 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
949 14:44:51.505428 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
950 14:44:51.505485 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
951 14:44:51.505541 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
952 14:44:51.505596 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
953 14:44:51.505649 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
954 14:44:51.505704 All bytes gating window > 1UI, Early break!
955 14:44:51.505787
956 14:44:51.505840 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 24)
957 14:44:51.505893
958 14:44:51.505945 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 30)
959 14:44:51.505998
960 14:44:51.506050
961 14:44:51.506102
962 14:44:51.506154 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 24)
963 14:44:51.506207
964 14:44:51.506259 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 30)
965 14:44:51.506311
966 14:44:51.506363
967 14:44:51.506415 Write Rank0 MR1 =0x56
968 14:44:51.506468
969 14:44:51.506520 best RODT dly(2T, 0.5T) = (2, 2)
970 14:44:51.506572
971 14:44:51.506624 best RODT dly(2T, 0.5T) = (2, 2)
972 14:44:51.506676 ==
973 14:44:51.506728 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
974 14:44:51.506781 fsp= 1, odt_onoff= 1, Byte mode= 0
975 14:44:51.506834 ==
976 14:44:51.506917 Start DQ dly to find pass range UseTestEngine =0
977 14:44:51.506970 x-axis: bit #, y-axis: DQ dly (-127~63)
978 14:44:51.507023 RX Vref Scan = 0
979 14:44:51.507076 -26, [0] xxxxxxxx xxxxxxxx [MSB]
980 14:44:51.507132 -25, [0] xxxxxxxx xxxxxxxx [MSB]
981 14:44:51.507185 -24, [0] xxxxxxxx xxxxxxxx [MSB]
982 14:44:51.507239 -23, [0] xxxxxxxx xxxxxxxx [MSB]
983 14:44:51.507292 -22, [0] xxxxxxxx xxxxxxxx [MSB]
984 14:44:51.507345 -21, [0] xxxxxxxx xxxxxxxx [MSB]
985 14:44:51.507399 -20, [0] xxxxxxxx xxxxxxxx [MSB]
986 14:44:51.507452 -19, [0] xxxxxxxx xxxxxxxx [MSB]
987 14:44:51.507505 -18, [0] xxxxxxxx xxxxxxxx [MSB]
988 14:44:51.507558 -17, [0] xxxxxxxx xxxxxxxx [MSB]
989 14:44:51.507610 -16, [0] xxxxxxxx xxxxxxxx [MSB]
990 14:44:51.507664 -15, [0] xxxxxxxx xxxxxxxx [MSB]
991 14:44:51.507717 -14, [0] xxxxxxxx xxxxxxxx [MSB]
992 14:44:51.507770 -13, [0] xxxxxxxx xxxxxxxx [MSB]
993 14:44:51.507824 -12, [0] xxxxxxxx xxxxxxxx [MSB]
994 14:44:51.507877 -11, [0] xxxxxxxx xxxxxxxx [MSB]
995 14:44:51.507931 -10, [0] xxxxxxxx xxxxxxxx [MSB]
996 14:44:51.507983 -9, [0] xxxxxxxx xxxxxxxx [MSB]
997 14:44:51.508037 -8, [0] xxxxxxxx xxxxxxxx [MSB]
998 14:44:51.508090 -7, [0] xxxxxxxx xxxxxxxx [MSB]
999 14:44:51.508180 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1000 14:44:51.508268 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1001 14:44:51.508377 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1002 14:44:51.508434 -3, [0] xxxxxxxx xxxxxxxx [MSB]
1003 14:44:51.508488 -2, [0] xxxxxxxx xxxxxxxx [MSB]
1004 14:44:51.508542 -1, [0] xxxxxxxx xxxxxxxx [MSB]
1005 14:44:51.508599 0, [0] xxxoxoxx xxxxxxxx [MSB]
1006 14:44:51.508653 1, [0] xxxoxoxx xxxoxxxx [MSB]
1007 14:44:51.508708 2, [0] xxxoxoxx xxxoxxxx [MSB]
1008 14:44:51.508762 3, [0] xxxoxooo oxxoxoox [MSB]
1009 14:44:51.508815 4, [0] xxxoxooo ooxoxooo [MSB]
1010 14:44:51.508869 5, [0] xxxoxooo ooxooooo [MSB]
1011 14:44:51.508924 6, [0] xxxooooo ooxooooo [MSB]
1012 14:44:51.508979 7, [0] xooooooo ooxooooo [MSB]
1013 14:44:51.509033 8, [0] xooooooo oooooooo [MSB]
1014 14:44:51.509087 9, [0] xooooooo oooooooo [MSB]
1015 14:44:51.509140 10, [0] xooooooo oooooooo [MSB]
1016 14:44:51.509194 32, [0] oooxoooo oooooooo [MSB]
1017 14:44:51.509248 33, [0] oooxoooo oooooxoo [MSB]
1018 14:44:51.509343 34, [0] oooxoxxo oooooxxo [MSB]
1019 14:44:51.509396 35, [0] oooxoxxx xooooxxo [MSB]
1020 14:44:51.509449 36, [0] oooxoxxx xooxoxxo [MSB]
1021 14:44:51.509502 37, [0] oooxoxxx xxoxxxxx [MSB]
1022 14:44:51.509555 38, [0] oooxoxxx xxoxxxxx [MSB]
1023 14:44:51.509610 39, [0] oooxoxxx xxoxxxxx [MSB]
1024 14:44:51.509669 40, [0] oooxxxxx xxoxxxxx [MSB]
1025 14:44:51.509731 41, [0] xoxxxxxx xxoxxxxx [MSB]
1026 14:44:51.509789 42, [0] xxxxxxxx xxxxxxxx [MSB]
1027 14:44:51.509844 iDelay=42, Bit 0, Center 25 (11 ~ 40) 30
1028 14:44:51.509897 iDelay=42, Bit 1, Center 24 (7 ~ 41) 35
1029 14:44:51.509950 iDelay=42, Bit 2, Center 23 (7 ~ 40) 34
1030 14:44:51.510002 iDelay=42, Bit 3, Center 15 (0 ~ 31) 32
1031 14:44:51.510054 iDelay=42, Bit 4, Center 22 (6 ~ 39) 34
1032 14:44:51.510106 iDelay=42, Bit 5, Center 16 (0 ~ 33) 34
1033 14:44:51.510158 iDelay=42, Bit 6, Center 18 (3 ~ 33) 31
1034 14:44:51.510210 iDelay=42, Bit 7, Center 18 (3 ~ 34) 32
1035 14:44:51.510262 iDelay=42, Bit 8, Center 18 (3 ~ 34) 32
1036 14:44:51.510314 iDelay=42, Bit 9, Center 20 (4 ~ 36) 33
1037 14:44:51.510367 iDelay=42, Bit 10, Center 24 (8 ~ 41) 34
1038 14:44:51.510419 iDelay=42, Bit 11, Center 18 (1 ~ 35) 35
1039 14:44:51.510471 iDelay=42, Bit 12, Center 20 (5 ~ 36) 32
1040 14:44:51.510522 iDelay=42, Bit 13, Center 17 (3 ~ 32) 30
1041 14:44:51.510574 iDelay=42, Bit 14, Center 18 (3 ~ 33) 31
1042 14:44:51.510626 iDelay=42, Bit 15, Center 20 (4 ~ 36) 33
1043 14:44:51.510677 ==
1044 14:44:51.510730 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1045 14:44:51.510783 fsp= 1, odt_onoff= 1, Byte mode= 0
1046 14:44:51.510835 ==
1047 14:44:51.510888 DQS Delay:
1048 14:44:51.510939 DQS0 = 0, DQS1 = 0
1049 14:44:51.510991 DQM Delay:
1050 14:44:51.511044 DQM0 = 20, DQM1 = 19
1051 14:44:51.511096 DQ Delay:
1052 14:44:51.511149 DQ0 =25, DQ1 =24, DQ2 =23, DQ3 =15
1053 14:44:51.511201 DQ4 =22, DQ5 =16, DQ6 =18, DQ7 =18
1054 14:44:51.511253 DQ8 =18, DQ9 =20, DQ10 =24, DQ11 =18
1055 14:44:51.511305 DQ12 =20, DQ13 =17, DQ14 =18, DQ15 =20
1056 14:44:51.511357
1057 14:44:51.511409
1058 14:44:51.511461 DramC Write-DBI off
1059 14:44:51.511513 ==
1060 14:44:51.511566 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1061 14:44:51.511647 fsp= 1, odt_onoff= 1, Byte mode= 0
1062 14:44:51.511713 ==
1063 14:44:51.511780 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1064 14:44:51.511832
1065 14:44:51.511884 Begin, DQ Scan Range 921~1177
1066 14:44:51.511936
1067 14:44:51.511987
1068 14:44:51.512039 TX Vref Scan disable
1069 14:44:51.512091 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1070 14:44:51.512145 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1071 14:44:51.512396 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1072 14:44:51.512531 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1073 14:44:51.512716 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1074 14:44:51.512860 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1075 14:44:51.512988 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1076 14:44:51.513047 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1077 14:44:51.513102 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1078 14:44:51.513157 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1079 14:44:51.513210 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1080 14:44:51.513293 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1081 14:44:51.513362 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1082 14:44:51.513415 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1083 14:44:51.513468 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1084 14:44:51.513522 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1085 14:44:51.513575 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1086 14:44:51.513628 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1087 14:44:51.513681 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1088 14:44:51.513734 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1089 14:44:51.513786 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1090 14:44:51.513839 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1091 14:44:51.513893 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1092 14:44:51.513946 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1093 14:44:51.513999 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1094 14:44:51.514052 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1095 14:44:51.514105 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1096 14:44:51.514158 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1097 14:44:51.514211 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1098 14:44:51.514263 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1099 14:44:51.514316 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1100 14:44:51.514370 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1101 14:44:51.514423 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1102 14:44:51.514476 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1103 14:44:51.514529 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1104 14:44:51.514606 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1105 14:44:51.514674 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1106 14:44:51.514727 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1107 14:44:51.514780 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1108 14:44:51.514833 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1109 14:44:51.514886 961 |3 6 1|[0] xxxxxxxx oxxoxxxx [MSB]
1110 14:44:51.514940 962 |3 6 2|[0] xxxxxxxx oxxoooxx [MSB]
1111 14:44:51.514993 963 |3 6 3|[0] xxxxxxxx ooxoooox [MSB]
1112 14:44:51.515046 964 |3 6 4|[0] xxxxxxxx ooxoooox [MSB]
1113 14:44:51.515098 965 |3 6 5|[0] xxxxxxxx ooxoooox [MSB]
1114 14:44:51.515151 966 |3 6 6|[0] xxxxxxxx ooxooooo [MSB]
1115 14:44:51.515203 967 |3 6 7|[0] xxxxxxxx oooooooo [MSB]
1116 14:44:51.515256 968 |3 6 8|[0] xxxoxxxx oooooooo [MSB]
1117 14:44:51.515309 969 |3 6 9|[0] xxxoxoox oooooooo [MSB]
1118 14:44:51.515363 970 |3 6 10|[0] xxxoxoox oooooooo [MSB]
1119 14:44:51.515416 971 |3 6 11|[0] xxxoxoox oooooooo [MSB]
1120 14:44:51.515469 972 |3 6 12|[0] xxxooooo oooooooo [MSB]
1121 14:44:51.515522 973 |3 6 13|[0] xxxooooo oooooooo [MSB]
1122 14:44:51.515576 974 |3 6 14|[0] xxoooooo oooooooo [MSB]
1123 14:44:51.515629 985 |3 6 25|[0] oooooooo oooxoxoo [MSB]
1124 14:44:51.515682 986 |3 6 26|[0] oooooooo xxxxxxxx [MSB]
1125 14:44:51.515735 987 |3 6 27|[0] oooooooo xxxxxxxx [MSB]
1126 14:44:51.515788 988 |3 6 28|[0] oooooooo xxxxxxxx [MSB]
1127 14:44:51.515841 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
1128 14:44:51.515894 990 |3 6 30|[0] oooxoooo xxxxxxxx [MSB]
1129 14:44:51.515948 991 |3 6 31|[0] oooxoxoo xxxxxxxx [MSB]
1130 14:44:51.516001 992 |3 6 32|[0] xxxxxxxx xxxxxxxx [MSB]
1131 14:44:51.516054 Byte0, DQ PI dly=980, DQM PI dly= 980
1132 14:44:51.516106 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
1133 14:44:51.516159
1134 14:44:51.516212 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
1135 14:44:51.516265
1136 14:44:51.516317 Byte1, DQ PI dly=974, DQM PI dly= 974
1137 14:44:51.516370 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 14)
1138 14:44:51.516422
1139 14:44:51.516474 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 14)
1140 14:44:51.516526
1141 14:44:51.516579 ==
1142 14:44:51.516631 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1143 14:44:51.516698 fsp= 1, odt_onoff= 1, Byte mode= 0
1144 14:44:51.516765 ==
1145 14:44:51.516818 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1146 14:44:51.516871
1147 14:44:51.516923 Begin, DQ Scan Range 950~1014
1148 14:44:51.516975 Write Rank0 MR14 =0x0
1149 14:44:51.517027
1150 14:44:51.517080 CH=0, VrefRange= 0, VrefLevel = 0
1151 14:44:51.517133 TX Bit0 (977~993) 17 985, Bit8 (963~982) 20 972,
1152 14:44:51.517186 TX Bit1 (976~992) 17 984, Bit9 (966~982) 17 974,
1153 14:44:51.517238 TX Bit2 (976~992) 17 984, Bit10 (969~987) 19 978,
1154 14:44:51.517327 TX Bit3 (969~985) 17 977, Bit11 (963~982) 20 972,
1155 14:44:51.517380 TX Bit4 (975~992) 18 983, Bit12 (966~982) 17 974,
1156 14:44:51.517433 TX Bit5 (970~986) 17 978, Bit13 (965~982) 18 973,
1157 14:44:51.517485 TX Bit6 (972~986) 15 979, Bit14 (966~983) 18 974,
1158 14:44:51.517538 TX Bit7 (976~988) 13 982, Bit15 (968~983) 16 975,
1159 14:44:51.517590
1160 14:44:51.517643 Write Rank0 MR14 =0x2
1161 14:44:51.517695
1162 14:44:51.517747 CH=0, VrefRange= 0, VrefLevel = 2
1163 14:44:51.517800 TX Bit0 (977~993) 17 985, Bit8 (963~982) 20 972,
1164 14:44:51.517853 TX Bit1 (976~992) 17 984, Bit9 (966~982) 17 974,
1165 14:44:51.517905 TX Bit2 (975~992) 18 983, Bit10 (968~988) 21 978,
1166 14:44:51.517958 TX Bit3 (969~985) 17 977, Bit11 (963~982) 20 972,
1167 14:44:51.518010 TX Bit4 (975~992) 18 983, Bit12 (966~983) 18 974,
1168 14:44:51.518063 TX Bit5 (970~986) 17 978, Bit13 (965~982) 18 973,
1169 14:44:51.518115 TX Bit6 (971~987) 17 979, Bit14 (966~983) 18 974,
1170 14:44:51.518168 TX Bit7 (976~990) 15 983, Bit15 (968~983) 16 975,
1171 14:44:51.518220
1172 14:44:51.518272 Write Rank0 MR14 =0x4
1173 14:44:51.518325
1174 14:44:51.518377 CH=0, VrefRange= 0, VrefLevel = 4
1175 14:44:51.518430 TX Bit0 (976~993) 18 984, Bit8 (962~983) 22 972,
1176 14:44:51.518483 TX Bit1 (976~992) 17 984, Bit9 (965~982) 18 973,
1177 14:44:51.518535 TX Bit2 (975~992) 18 983, Bit10 (968~988) 21 978,
1178 14:44:51.518782 TX Bit3 (969~986) 18 977, Bit11 (963~982) 20 972,
1179 14:44:51.518915 TX Bit4 (974~993) 20 983, Bit12 (965~983) 19 974,
1180 14:44:51.519050 TX Bit5 (970~987) 18 978, Bit13 (964~982) 19 973,
1181 14:44:51.519186 TX Bit6 (971~988) 18 979, Bit14 (966~983) 18 974,
1182 14:44:51.519310 TX Bit7 (975~990) 16 982, Bit15 (968~983) 16 975,
1183 14:44:51.519369
1184 14:44:51.519424 Write Rank0 MR14 =0x6
1185 14:44:51.519477
1186 14:44:51.519531 CH=0, VrefRange= 0, VrefLevel = 6
1187 14:44:51.519585 TX Bit0 (976~994) 19 985, Bit8 (962~983) 22 972,
1188 14:44:51.519638 TX Bit1 (976~992) 17 984, Bit9 (965~983) 19 974,
1189 14:44:51.519692 TX Bit2 (976~992) 17 984, Bit10 (968~989) 22 978,
1190 14:44:51.519744 TX Bit3 (969~986) 18 977, Bit11 (962~982) 21 972,
1191 14:44:51.519797 TX Bit4 (974~993) 20 983, Bit12 (965~983) 19 974,
1192 14:44:51.519886 TX Bit5 (970~987) 18 978, Bit13 (963~982) 20 972,
1193 14:44:51.519939 TX Bit6 (971~989) 19 980, Bit14 (965~983) 19 974,
1194 14:44:51.519992 TX Bit7 (975~991) 17 983, Bit15 (967~984) 18 975,
1195 14:44:51.520044
1196 14:44:51.520097 Write Rank0 MR14 =0x8
1197 14:44:51.520149
1198 14:44:51.520200 CH=0, VrefRange= 0, VrefLevel = 8
1199 14:44:51.520253 TX Bit0 (976~994) 19 985, Bit8 (961~983) 23 972,
1200 14:44:51.520305 TX Bit1 (976~993) 18 984, Bit9 (965~983) 19 974,
1201 14:44:51.520358 TX Bit2 (975~993) 19 984, Bit10 (968~989) 22 978,
1202 14:44:51.520410 TX Bit3 (968~987) 20 977, Bit11 (962~983) 22 972,
1203 14:44:51.520463 TX Bit4 (973~993) 21 983, Bit12 (964~983) 20 973,
1204 14:44:51.520515 TX Bit5 (970~987) 18 978, Bit13 (963~983) 21 973,
1205 14:44:51.520567 TX Bit6 (970~989) 20 979, Bit14 (965~984) 20 974,
1206 14:44:51.520620 TX Bit7 (975~991) 17 983, Bit15 (967~984) 18 975,
1207 14:44:51.520671
1208 14:44:51.520723 Write Rank0 MR14 =0xa
1209 14:44:51.520775
1210 14:44:51.520828 CH=0, VrefRange= 0, VrefLevel = 10
1211 14:44:51.520880 TX Bit0 (976~994) 19 985, Bit8 (962~984) 23 973,
1212 14:44:51.520932 TX Bit1 (975~993) 19 984, Bit9 (965~983) 19 974,
1213 14:44:51.520985 TX Bit2 (974~993) 20 983, Bit10 (968~989) 22 978,
1214 14:44:51.521037 TX Bit3 (969~987) 19 978, Bit11 (962~983) 22 972,
1215 14:44:51.521089 TX Bit4 (973~994) 22 983, Bit12 (963~984) 22 973,
1216 14:44:51.521142 TX Bit5 (969~989) 21 979, Bit13 (963~983) 21 973,
1217 14:44:51.521195 TX Bit6 (970~990) 21 980, Bit14 (964~985) 22 974,
1218 14:44:51.521248 TX Bit7 (974~991) 18 982, Bit15 (967~985) 19 976,
1219 14:44:51.521338
1220 14:44:51.521391 Write Rank0 MR14 =0xc
1221 14:44:51.521444
1222 14:44:51.521496 CH=0, VrefRange= 0, VrefLevel = 12
1223 14:44:51.521548 TX Bit0 (976~995) 20 985, Bit8 (961~984) 24 972,
1224 14:44:51.521600 TX Bit1 (975~993) 19 984, Bit9 (964~984) 21 974,
1225 14:44:51.521653 TX Bit2 (974~993) 20 983, Bit10 (967~990) 24 978,
1226 14:44:51.521706 TX Bit3 (968~988) 21 978, Bit11 (962~983) 22 972,
1227 14:44:51.521758 TX Bit4 (973~994) 22 983, Bit12 (964~984) 21 974,
1228 14:44:51.521811 TX Bit5 (969~989) 21 979, Bit13 (963~983) 21 973,
1229 14:44:51.521864 TX Bit6 (970~990) 21 980, Bit14 (964~985) 22 974,
1230 14:44:51.521916 TX Bit7 (973~991) 19 982, Bit15 (967~985) 19 976,
1231 14:44:51.521969
1232 14:44:51.522020 Write Rank0 MR14 =0xe
1233 14:44:51.522072
1234 14:44:51.522124 CH=0, VrefRange= 0, VrefLevel = 14
1235 14:44:51.522177 TX Bit0 (975~995) 21 985, Bit8 (961~985) 25 973,
1236 14:44:51.522229 TX Bit1 (975~994) 20 984, Bit9 (963~985) 23 974,
1237 14:44:51.522282 TX Bit2 (974~993) 20 983, Bit10 (967~990) 24 978,
1238 14:44:51.522334 TX Bit3 (968~988) 21 978, Bit11 (961~983) 23 972,
1239 14:44:51.522387 TX Bit4 (973~994) 22 983, Bit12 (963~985) 23 974,
1240 14:44:51.522438 TX Bit5 (969~990) 22 979, Bit13 (962~984) 23 973,
1241 14:44:51.522490 TX Bit6 (969~991) 23 980, Bit14 (963~986) 24 974,
1242 14:44:51.522543 TX Bit7 (973~992) 20 982, Bit15 (966~986) 21 976,
1243 14:44:51.522595
1244 14:44:51.522647 Write Rank0 MR14 =0x10
1245 14:44:51.522699
1246 14:44:51.522752 CH=0, VrefRange= 0, VrefLevel = 16
1247 14:44:51.522804 TX Bit0 (975~995) 21 985, Bit8 (961~985) 25 973,
1248 14:44:51.522856 TX Bit1 (974~994) 21 984, Bit9 (962~985) 24 973,
1249 14:44:51.522909 TX Bit2 (974~994) 21 984, Bit10 (967~990) 24 978,
1250 14:44:51.522961 TX Bit3 (968~989) 22 978, Bit11 (961~984) 24 972,
1251 14:44:51.523013 TX Bit4 (971~995) 25 983, Bit12 (963~985) 23 974,
1252 14:44:51.523066 TX Bit5 (969~990) 22 979, Bit13 (962~984) 23 973,
1253 14:44:51.523118 TX Bit6 (969~991) 23 980, Bit14 (963~986) 24 974,
1254 14:44:51.523171 TX Bit7 (972~992) 21 982, Bit15 (967~986) 20 976,
1255 14:44:51.523223
1256 14:44:51.523275 Write Rank0 MR14 =0x12
1257 14:44:51.523327
1258 14:44:51.523378 CH=0, VrefRange= 0, VrefLevel = 18
1259 14:44:51.523430 TX Bit0 (975~996) 22 985, Bit8 (961~985) 25 973,
1260 14:44:51.523483 TX Bit1 (974~994) 21 984, Bit9 (962~986) 25 974,
1261 14:44:51.523535 TX Bit2 (973~994) 22 983, Bit10 (967~990) 24 978,
1262 14:44:51.523587 TX Bit3 (967~990) 24 978, Bit11 (961~984) 24 972,
1263 14:44:51.523640 TX Bit4 (971~995) 25 983, Bit12 (962~985) 24 973,
1264 14:44:51.523692 TX Bit5 (969~991) 23 980, Bit13 (961~984) 24 972,
1265 14:44:51.523745 TX Bit6 (969~991) 23 980, Bit14 (962~987) 26 974,
1266 14:44:51.523797 TX Bit7 (972~993) 22 982, Bit15 (966~987) 22 976,
1267 14:44:51.523849
1268 14:44:51.523901 Write Rank0 MR14 =0x14
1269 14:44:51.523953
1270 14:44:51.524005 CH=0, VrefRange= 0, VrefLevel = 20
1271 14:44:51.524058 TX Bit0 (974~997) 24 985, Bit8 (961~986) 26 973,
1272 14:44:51.524110 TX Bit1 (973~995) 23 984, Bit9 (962~986) 25 974,
1273 14:44:51.524163 TX Bit2 (973~995) 23 984, Bit10 (966~990) 25 978,
1274 14:44:51.524215 TX Bit3 (967~991) 25 979, Bit11 (961~985) 25 973,
1275 14:44:51.524268 TX Bit4 (971~996) 26 983, Bit12 (962~986) 25 974,
1276 14:44:51.524350 TX Bit5 (968~991) 24 979, Bit13 (961~985) 25 973,
1277 14:44:51.524402 TX Bit6 (969~992) 24 980, Bit14 (962~986) 25 974,
1278 14:44:51.524652 TX Bit7 (971~993) 23 982, Bit15 (966~988) 23 977,
1279 14:44:51.524787
1280 14:44:51.524918 Write Rank0 MR14 =0x16
1281 14:44:51.525045
1282 14:44:51.525189 CH=0, VrefRange= 0, VrefLevel = 22
1283 14:44:51.525253 TX Bit0 (974~998) 25 986, Bit8 (960~985) 26 972,
1284 14:44:51.525329 TX Bit1 (973~995) 23 984, Bit9 (962~987) 26 974,
1285 14:44:51.525383 TX Bit2 (972~995) 24 983, Bit10 (966~990) 25 978,
1286 14:44:51.525436 TX Bit3 (967~991) 25 979, Bit11 (961~985) 25 973,
1287 14:44:51.525490 TX Bit4 (971~996) 26 983, Bit12 (962~986) 25 974,
1288 14:44:51.525543 TX Bit5 (968~991) 24 979, Bit13 (961~985) 25 973,
1289 14:44:51.525596 TX Bit6 (969~992) 24 980, Bit14 (962~986) 25 974,
1290 14:44:51.525648 TX Bit7 (971~994) 24 982, Bit15 (965~988) 24 976,
1291 14:44:51.525700
1292 14:44:51.525753 wait MRW command Rank0 MR14 =0x18 fired (1)
1293 14:44:51.525805 Write Rank0 MR14 =0x18
1294 14:44:51.525857
1295 14:44:51.525909 CH=0, VrefRange= 0, VrefLevel = 24
1296 14:44:51.525962 TX Bit0 (974~998) 25 986, Bit8 (961~985) 25 973,
1297 14:44:51.526016 TX Bit1 (972~995) 24 983, Bit9 (962~987) 26 974,
1298 14:44:51.526069 TX Bit2 (972~995) 24 983, Bit10 (966~990) 25 978,
1299 14:44:51.526122 TX Bit3 (967~991) 25 979, Bit11 (961~984) 24 972,
1300 14:44:51.526174 TX Bit4 (972~996) 25 984, Bit12 (961~985) 25 973,
1301 14:44:51.526227 TX Bit5 (968~991) 24 979, Bit13 (961~984) 24 972,
1302 14:44:51.526279 TX Bit6 (969~992) 24 980, Bit14 (962~985) 24 973,
1303 14:44:51.526332 TX Bit7 (970~994) 25 982, Bit15 (965~989) 25 977,
1304 14:44:51.526385
1305 14:44:51.526436 Write Rank0 MR14 =0x1a
1306 14:44:51.526489
1307 14:44:51.526541 CH=0, VrefRange= 0, VrefLevel = 26
1308 14:44:51.526593 TX Bit0 (974~998) 25 986, Bit8 (961~985) 25 973,
1309 14:44:51.526646 TX Bit1 (972~995) 24 983, Bit9 (962~987) 26 974,
1310 14:44:51.526699 TX Bit2 (972~995) 24 983, Bit10 (966~990) 25 978,
1311 14:44:51.526751 TX Bit3 (967~991) 25 979, Bit11 (961~984) 24 972,
1312 14:44:51.526804 TX Bit4 (972~996) 25 984, Bit12 (961~985) 25 973,
1313 14:44:51.526856 TX Bit5 (968~991) 24 979, Bit13 (961~984) 24 972,
1314 14:44:51.526908 TX Bit6 (969~992) 24 980, Bit14 (962~985) 24 973,
1315 14:44:51.526960 TX Bit7 (970~994) 25 982, Bit15 (965~989) 25 977,
1316 14:44:51.527012
1317 14:44:51.527064 Write Rank0 MR14 =0x1c
1318 14:44:51.527117
1319 14:44:51.527169 CH=0, VrefRange= 0, VrefLevel = 28
1320 14:44:51.527222 TX Bit0 (974~998) 25 986, Bit8 (961~985) 25 973,
1321 14:44:51.527275 TX Bit1 (972~995) 24 983, Bit9 (962~987) 26 974,
1322 14:44:51.527327 TX Bit2 (972~995) 24 983, Bit10 (966~990) 25 978,
1323 14:44:51.527380 TX Bit3 (967~991) 25 979, Bit11 (961~984) 24 972,
1324 14:44:51.527432 TX Bit4 (972~996) 25 984, Bit12 (961~985) 25 973,
1325 14:44:51.527484 TX Bit5 (968~991) 24 979, Bit13 (961~984) 24 972,
1326 14:44:51.527537 TX Bit6 (969~992) 24 980, Bit14 (962~985) 24 973,
1327 14:44:51.527589 TX Bit7 (970~994) 25 982, Bit15 (965~989) 25 977,
1328 14:44:51.527671
1329 14:44:51.527723 Write Rank0 MR14 =0x1e
1330 14:44:51.527775
1331 14:44:51.527827 CH=0, VrefRange= 0, VrefLevel = 30
1332 14:44:51.527879 TX Bit0 (974~998) 25 986, Bit8 (961~985) 25 973,
1333 14:44:51.527932 TX Bit1 (972~995) 24 983, Bit9 (962~987) 26 974,
1334 14:44:51.527984 TX Bit2 (972~995) 24 983, Bit10 (966~990) 25 978,
1335 14:44:51.528037 TX Bit3 (967~991) 25 979, Bit11 (961~984) 24 972,
1336 14:44:51.528090 TX Bit4 (972~996) 25 984, Bit12 (961~985) 25 973,
1337 14:44:51.528142 TX Bit5 (968~991) 24 979, Bit13 (961~984) 24 972,
1338 14:44:51.528194 TX Bit6 (969~992) 24 980, Bit14 (962~985) 24 973,
1339 14:44:51.528247 TX Bit7 (970~994) 25 982, Bit15 (965~989) 25 977,
1340 14:44:51.528299
1341 14:44:51.528351
1342 14:44:51.528403 TX Vref found, early break! 372< 374
1343 14:44:51.528456 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =762/100 ps
1344 14:44:51.528508 u1DelayCellOfst[0]=8 cells (7 PI)
1345 14:44:51.528560 u1DelayCellOfst[1]=5 cells (4 PI)
1346 14:44:51.528612 u1DelayCellOfst[2]=5 cells (4 PI)
1347 14:44:51.528664 u1DelayCellOfst[3]=0 cells (0 PI)
1348 14:44:51.528715 u1DelayCellOfst[4]=6 cells (5 PI)
1349 14:44:51.528768 u1DelayCellOfst[5]=0 cells (0 PI)
1350 14:44:51.528820 u1DelayCellOfst[6]=1 cells (1 PI)
1351 14:44:51.528873 u1DelayCellOfst[7]=3 cells (3 PI)
1352 14:44:51.528925 Byte0, DQ PI dly=979, DQM PI dly= 982
1353 14:44:51.528977 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
1354 14:44:51.529029
1355 14:44:51.529082 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
1356 14:44:51.529135
1357 14:44:51.529187 u1DelayCellOfst[8]=1 cells (1 PI)
1358 14:44:51.529239 u1DelayCellOfst[9]=2 cells (2 PI)
1359 14:44:51.529328 u1DelayCellOfst[10]=7 cells (6 PI)
1360 14:44:51.529380 u1DelayCellOfst[11]=0 cells (0 PI)
1361 14:44:51.529432 u1DelayCellOfst[12]=1 cells (1 PI)
1362 14:44:51.529484 u1DelayCellOfst[13]=0 cells (0 PI)
1363 14:44:51.529535 u1DelayCellOfst[14]=1 cells (1 PI)
1364 14:44:51.529587 u1DelayCellOfst[15]=6 cells (5 PI)
1365 14:44:51.529639 Byte1, DQ PI dly=972, DQM PI dly= 975
1366 14:44:51.529690 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 12)
1367 14:44:51.529742
1368 14:44:51.529793 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 12)
1369 14:44:51.529845
1370 14:44:51.529896 Write Rank0 MR14 =0x18
1371 14:44:51.529947
1372 14:44:51.529998 Final TX Range 0 Vref 24
1373 14:44:51.530050
1374 14:44:51.530101 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1375 14:44:51.530155
1376 14:44:51.530207 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1377 14:44:51.530260 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1378 14:44:51.530311 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1379 14:44:51.530363 Write Rank0 MR3 =0xb0
1380 14:44:51.530414 DramC Write-DBI on
1381 14:44:51.530466 ==
1382 14:44:51.530518 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1383 14:44:51.530570 fsp= 1, odt_onoff= 1, Byte mode= 0
1384 14:44:51.530623 ==
1385 14:44:51.530674 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1386 14:44:51.530726
1387 14:44:51.530777 Begin, DQ Scan Range 695~759
1388 14:44:51.530829
1389 14:44:51.530880
1390 14:44:51.530931 TX Vref Scan disable
1391 14:44:51.531177 695 |2 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1392 14:44:51.531253 696 |2 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1393 14:44:51.531310 697 |2 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1394 14:44:51.531364 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1395 14:44:51.531417 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1396 14:44:51.531470 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1397 14:44:51.531524 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1398 14:44:51.531576 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1399 14:44:51.531631 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1400 14:44:51.531685 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1401 14:44:51.531739 705 |2 6 1|[0] xxxxxxxx oooooooo [MSB]
1402 14:44:51.531792 706 |2 6 2|[0] xxxxxxxx oooooooo [MSB]
1403 14:44:51.531845 707 |2 6 3|[0] xxxxxxxx oooooooo [MSB]
1404 14:44:51.531898 708 |2 6 4|[0] xxxxxxxx oooooooo [MSB]
1405 14:44:51.531950 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB]
1406 14:44:51.532003 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
1407 14:44:51.532091 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
1408 14:44:51.532191 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
1409 14:44:51.532257 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1410 14:44:51.532309 732 |2 6 28|[0] oooooooo xxxxxxxx [MSB]
1411 14:44:51.532361 733 |2 6 29|[0] oooooooo xxxxxxxx [MSB]
1412 14:44:51.532414 734 |2 6 30|[0] oooooooo xxxxxxxx [MSB]
1413 14:44:51.532466 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB]
1414 14:44:51.532518 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
1415 14:44:51.532570 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
1416 14:44:51.532623 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
1417 14:44:51.532675 739 |2 6 35|[0] xxxxxxxx xxxxxxxx [MSB]
1418 14:44:51.532727 Byte0, DQ PI dly=726, DQM PI dly= 726
1419 14:44:51.532779 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 22)
1420 14:44:51.532830
1421 14:44:51.532882 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 22)
1422 14:44:51.532934
1423 14:44:51.532985 Byte1, DQ PI dly=718, DQM PI dly= 718
1424 14:44:51.533037 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 14)
1425 14:44:51.533089
1426 14:44:51.533140 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 14)
1427 14:44:51.533192
1428 14:44:51.533243 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1429 14:44:51.533338 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1430 14:44:51.533391 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1431 14:44:51.533443 Write Rank0 MR3 =0x30
1432 14:44:51.533495 DramC Write-DBI off
1433 14:44:51.533546
1434 14:44:51.533598 [DATLAT]
1435 14:44:51.533649 Freq=1600, CH0 RK0, use_rxtx_scan=0
1436 14:44:51.533701
1437 14:44:51.533752 DATLAT Default: 0xf
1438 14:44:51.533805 7, 0xFFFF, sum=0
1439 14:44:51.533858 8, 0xFFFF, sum=0
1440 14:44:51.533910 9, 0xFFFF, sum=0
1441 14:44:51.533963 10, 0xFFFF, sum=0
1442 14:44:51.534016 11, 0xFFFF, sum=0
1443 14:44:51.534068 12, 0xFFFF, sum=0
1444 14:44:51.534120 13, 0xFFFF, sum=0
1445 14:44:51.534172 14, 0x0, sum=1
1446 14:44:51.534225 15, 0x0, sum=2
1447 14:44:51.534276 16, 0x0, sum=3
1448 14:44:51.534329 17, 0x0, sum=4
1449 14:44:51.534381 pattern=2 first_step=14 total pass=5 best_step=16
1450 14:44:51.534433 ==
1451 14:44:51.534484 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1452 14:44:51.534536 fsp= 1, odt_onoff= 1, Byte mode= 0
1453 14:44:51.534588 ==
1454 14:44:51.534640 Start DQ dly to find pass range UseTestEngine =1
1455 14:44:51.534692 x-axis: bit #, y-axis: DQ dly (-127~63)
1456 14:44:51.534744 RX Vref Scan = 1
1457 14:44:51.534795
1458 14:44:51.534846 RX Vref found, early break!
1459 14:44:51.534897
1460 14:44:51.534948 Final RX Vref 12, apply to both rank0 and 1
1461 14:44:51.535000 ==
1462 14:44:51.535052 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1463 14:44:51.535104 fsp= 1, odt_onoff= 1, Byte mode= 0
1464 14:44:51.535155 ==
1465 14:44:51.535206 DQS Delay:
1466 14:44:51.535258 DQS0 = 0, DQS1 = 0
1467 14:44:51.535309 DQM Delay:
1468 14:44:51.535360 DQM0 = 20, DQM1 = 18
1469 14:44:51.535412 DQ Delay:
1470 14:44:51.535463 DQ0 =25, DQ1 =25, DQ2 =24, DQ3 =15
1471 14:44:51.535515 DQ4 =23, DQ5 =16, DQ6 =18, DQ7 =18
1472 14:44:51.535566 DQ8 =18, DQ9 =19, DQ10 =24, DQ11 =16
1473 14:44:51.535617 DQ12 =20, DQ13 =16, DQ14 =18, DQ15 =20
1474 14:44:51.535668
1475 14:44:51.535719
1476 14:44:51.535770
1477 14:44:51.535821 [DramC_TX_OE_Calibration] TA2
1478 14:44:51.535873 Original DQ_B0 (3 6) =30, OEN = 27
1479 14:44:51.535925 Original DQ_B1 (3 6) =30, OEN = 27
1480 14:44:51.536006 23, 0x0, End_B0=23 End_B1=23
1481 14:44:51.536060 24, 0x0, End_B0=24 End_B1=24
1482 14:44:51.536112 25, 0x0, End_B0=25 End_B1=25
1483 14:44:51.536165 26, 0x0, End_B0=26 End_B1=26
1484 14:44:51.536217 27, 0x0, End_B0=27 End_B1=27
1485 14:44:51.536269 28, 0x0, End_B0=28 End_B1=28
1486 14:44:51.536321 29, 0x0, End_B0=29 End_B1=29
1487 14:44:51.536373 30, 0x0, End_B0=30 End_B1=30
1488 14:44:51.536426 31, 0xFFFF, End_B0=30 End_B1=30
1489 14:44:51.536478 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1490 14:44:51.536530 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1491 14:44:51.536582
1492 14:44:51.536634
1493 14:44:51.536685 Write Rank0 MR23 =0x3f
1494 14:44:51.536736 [DQSOSC]
1495 14:44:51.536788 [DQSOSCAuto] RK0, (LSB)MR18= 0xaa, (MSB)MR19= 0x3, tDQSOscB0 = 335 ps tDQSOscB1 = 0 ps
1496 14:44:51.536840 CH0_RK0: MR19=0x3, MR18=0xAA, DQSOSC=335, MR23=63, INC=21, DEC=32
1497 14:44:51.536892 Write Rank0 MR23 =0x3f
1498 14:44:51.536944 [DQSOSC]
1499 14:44:51.536995 [DQSOSCAuto] RK0, (LSB)MR18= 0xa7, (MSB)MR19= 0x3, tDQSOscB0 = 336 ps tDQSOscB1 = 0 ps
1500 14:44:51.537048 CH0 RK0: MR19=3, MR18=A7
1501 14:44:51.537100 [RankSwap] Rank num 2, (Multi 1), Rank 1
1502 14:44:51.537151 Write Rank0 MR2 =0xad
1503 14:44:51.537202 [Write Leveling]
1504 14:44:51.537253 delay byte0 byte1 byte2 byte3
1505 14:44:51.537309
1506 14:44:51.537360 10 0 0
1507 14:44:51.537413 11 0 0
1508 14:44:51.537465 12 0 0
1509 14:44:51.537517 13 0 0
1510 14:44:51.537569 14 0 0
1511 14:44:51.537621 15 0 0
1512 14:44:51.537673 16 0 0
1513 14:44:51.537725 17 0 0
1514 14:44:51.537777 18 0 0
1515 14:44:51.537829 19 0 0
1516 14:44:51.537881 20 0 0
1517 14:44:51.537933 21 0 0
1518 14:44:51.537986 22 0 0
1519 14:44:51.538037 23 0 0
1520 14:44:51.538089 24 0 0
1521 14:44:51.538141 25 0 0
1522 14:44:51.538192 26 0 0
1523 14:44:51.538245 27 0 0
1524 14:44:51.538298 28 0 ff
1525 14:44:51.538349 29 0 ff
1526 14:44:51.538401 30 0 ff
1527 14:44:51.538453 31 0 ff
1528 14:44:51.538505 32 0 ff
1529 14:44:51.538556 33 0 ff
1530 14:44:51.538608 34 ff ff
1531 14:44:51.538662 35 ff ff
1532 14:44:51.538715 36 ff ff
1533 14:44:51.538795 37 ff ff
1534 14:44:51.538848 38 ff ff
1535 14:44:51.538899 39 ff ff
1536 14:44:51.538952 40 ff ff
1537 14:44:51.539202 pass bytecount = 0xff (0xff: all bytes pass)
1538 14:44:51.539332
1539 14:44:51.539459 DQS0 dly: 34
1540 14:44:51.539586 DQS1 dly: 28
1541 14:44:51.539712 Write Rank0 MR2 =0x2d
1542 14:44:51.539839 [RankSwap] Rank num 2, (Multi 1), Rank 0
1543 14:44:51.539964 Write Rank1 MR1 =0xd6
1544 14:44:51.540089 [Gating]
1545 14:44:51.540214 ==
1546 14:44:51.540286 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1547 14:44:51.540342 fsp= 1, odt_onoff= 1, Byte mode= 0
1548 14:44:51.540395 ==
1549 14:44:51.540448 3 1 0 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
1550 14:44:51.540503 3 1 4 |2c2b 2c2b |(11 11)(11 11) |(0 0)(0 0)| 0
1551 14:44:51.540556 3 1 8 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1552 14:44:51.540609 3 1 12 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1553 14:44:51.540662 3 1 16 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1554 14:44:51.540715 3 1 20 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1555 14:44:51.540767 3 1 24 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1556 14:44:51.540820 3 1 28 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1557 14:44:51.540873 3 2 0 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1558 14:44:51.540927 3 2 4 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1559 14:44:51.540979 3 2 8 |706 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1560 14:44:51.541031 3 2 12 |201 2c2c |(11 11)(11 0) |(0 0)(0 0)| 0
1561 14:44:51.541084 3 2 16 |3534 201 |(11 11)(11 11) |(0 0)(0 0)| 0
1562 14:44:51.541137 3 2 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1563 14:44:51.541191 3 2 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1564 14:44:51.541244 3 2 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1565 14:44:51.541333 3 3 0 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1566 14:44:51.541386 3 3 4 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1567 14:44:51.541439 3 3 8 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1568 14:44:51.541491 3 3 12 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1569 14:44:51.541544 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1570 14:44:51.541596 [Byte 1] Lead/lag falling Transition (3, 3, 16)
1571 14:44:51.541648 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1572 14:44:51.541700 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1573 14:44:51.541753 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1574 14:44:51.541805 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1575 14:44:51.541871 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1576 14:44:51.541928 3 4 8 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
1577 14:44:51.541984 3 4 12 |403 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1578 14:44:51.542038 3 4 16 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
1579 14:44:51.542091 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1580 14:44:51.542143 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1581 14:44:51.542196 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1582 14:44:51.542249 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1583 14:44:51.542301 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1584 14:44:51.542353 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1585 14:44:51.542405 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1586 14:44:51.542458 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1587 14:44:51.542510 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1588 14:44:51.542563 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1589 14:44:51.542615 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1590 14:44:51.542668 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1591 14:44:51.542720 [Byte 0] Lead/lag falling Transition (3, 6, 0)
1592 14:44:51.542772 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
1593 14:44:51.542824 [Byte 0] Lead/lag Transition tap number (2)
1594 14:44:51.542876 [Byte 1] Lead/lag falling Transition (3, 6, 4)
1595 14:44:51.542927 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
1596 14:44:51.542980 [Byte 1] Lead/lag Transition tap number (2)
1597 14:44:51.543033 3 6 12 |3434 3e3d |(1 1)(11 11) |(0 0)(0 0)| 0
1598 14:44:51.543086 3 6 16 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
1599 14:44:51.543139 [Byte 0]First pass (3, 6, 16)
1600 14:44:51.543191 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1601 14:44:51.543244 [Byte 1]First pass (3, 6, 20)
1602 14:44:51.543296 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1603 14:44:51.543348 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1604 14:44:51.543401 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1605 14:44:51.543453 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1606 14:44:51.543506 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1607 14:44:51.543558 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1608 14:44:51.543611 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1609 14:44:51.543663 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1610 14:44:51.543715 All bytes gating window > 1UI, Early break!
1611 14:44:51.543767
1612 14:44:51.543819 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 4)
1613 14:44:51.543871
1614 14:44:51.543922 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 8)
1615 14:44:51.543975
1616 14:44:51.544026
1617 14:44:51.544076
1618 14:44:51.544127 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 4)
1619 14:44:51.544179
1620 14:44:51.544231 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 8)
1621 14:44:51.544283
1622 14:44:51.544333
1623 14:44:51.544384 Write Rank1 MR1 =0x56
1624 14:44:51.544436
1625 14:44:51.544488 best RODT dly(2T, 0.5T) = (2, 3)
1626 14:44:51.544539
1627 14:44:51.544590 best RODT dly(2T, 0.5T) = (2, 3)
1628 14:44:51.544642 ==
1629 14:44:51.544693 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1630 14:44:51.544746 fsp= 1, odt_onoff= 1, Byte mode= 0
1631 14:44:51.544798 ==
1632 14:44:51.544850 Start DQ dly to find pass range UseTestEngine =0
1633 14:44:51.544901 x-axis: bit #, y-axis: DQ dly (-127~63)
1634 14:44:51.544953 RX Vref Scan = 0
1635 14:44:51.545005 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1636 14:44:51.545058 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1637 14:44:51.545121 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1638 14:44:51.545182 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1639 14:44:51.545235 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1640 14:44:51.545325 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1641 14:44:51.545378 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1642 14:44:51.545430 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1643 14:44:51.545482 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1644 14:44:51.545727 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1645 14:44:51.545789 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1646 14:44:51.545843 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1647 14:44:51.545896 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1648 14:44:51.545949 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1649 14:44:51.546002 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1650 14:44:51.546055 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1651 14:44:51.546108 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1652 14:44:51.546161 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1653 14:44:51.546213 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1654 14:44:51.546265 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1655 14:44:51.546318 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1656 14:44:51.546370 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1657 14:44:51.546422 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1658 14:44:51.546474 -3, [0] xxxxxxxx xxxxxxxx [MSB]
1659 14:44:51.546526 -2, [0] xxxxxxxx xxxxxxxx [MSB]
1660 14:44:51.546578 -1, [0] xxxxxxxx xxxxxxxx [MSB]
1661 14:44:51.546630 0, [0] xxxoxxxx xxxoxxxx [MSB]
1662 14:44:51.546682 1, [0] xxxoxoxx oxxoxoxx [MSB]
1663 14:44:51.546734 2, [0] xxxoxoxx ooxoooox [MSB]
1664 14:44:51.546787 3, [0] xxxoxooo ooxoooox [MSB]
1665 14:44:51.546838 4, [0] xxxoxooo ooxooooo [MSB]
1666 14:44:51.546891 5, [0] xxxoxooo oooooooo [MSB]
1667 14:44:51.546943 6, [0] xxxoxooo oooooooo [MSB]
1668 14:44:51.546995 7, [0] xoxooooo oooooooo [MSB]
1669 14:44:51.547047 8, [0] xooooooo oooooooo [MSB]
1670 14:44:51.547099 9, [0] xooooooo oooooooo [MSB]
1671 14:44:51.547151 10, [0] xooooooo oooooooo [MSB]
1672 14:44:51.547204 33, [0] oooooooo oooooooo [MSB]
1673 14:44:51.547256 34, [0] oooxoooo oooooooo [MSB]
1674 14:44:51.547309 35, [0] oooxoooo oooooxxo [MSB]
1675 14:44:51.547361 36, [0] oooxooxx xooxoxxo [MSB]
1676 14:44:51.547415 37, [0] oooxoxxx xxoxxxxo [MSB]
1677 14:44:51.547467 38, [0] oooxoxxx xxoxxxxo [MSB]
1678 14:44:51.547519 39, [0] oooxoxxx xxoxxxxx [MSB]
1679 14:44:51.547572 40, [0] oooxoxxx xxoxxxxx [MSB]
1680 14:44:51.547623 41, [0] oooxxxxx xxoxxxxx [MSB]
1681 14:44:51.547676 42, [0] xoxxxxxx xxoxxxxx [MSB]
1682 14:44:51.547728 43, [0] xxxxxxxx xxxxxxxx [MSB]
1683 14:44:51.547781 iDelay=43, Bit 0, Center 26 (11 ~ 41) 31
1684 14:44:51.547832 iDelay=43, Bit 1, Center 24 (7 ~ 42) 36
1685 14:44:51.547883 iDelay=43, Bit 2, Center 24 (8 ~ 41) 34
1686 14:44:51.547935 iDelay=43, Bit 3, Center 16 (0 ~ 33) 34
1687 14:44:51.547986 iDelay=43, Bit 4, Center 23 (7 ~ 40) 34
1688 14:44:51.548037 iDelay=43, Bit 5, Center 18 (1 ~ 36) 36
1689 14:44:51.548088 iDelay=43, Bit 6, Center 19 (3 ~ 35) 33
1690 14:44:51.548139 iDelay=43, Bit 7, Center 19 (3 ~ 35) 33
1691 14:44:51.548191 iDelay=43, Bit 8, Center 18 (1 ~ 35) 35
1692 14:44:51.548242 iDelay=43, Bit 9, Center 19 (2 ~ 36) 35
1693 14:44:51.548293 iDelay=43, Bit 10, Center 23 (5 ~ 42) 38
1694 14:44:51.548344 iDelay=43, Bit 11, Center 17 (0 ~ 35) 36
1695 14:44:51.548396 iDelay=43, Bit 12, Center 19 (2 ~ 36) 35
1696 14:44:51.548447 iDelay=43, Bit 13, Center 17 (1 ~ 34) 34
1697 14:44:51.548498 iDelay=43, Bit 14, Center 18 (2 ~ 34) 33
1698 14:44:51.548549 iDelay=43, Bit 15, Center 21 (4 ~ 38) 35
1699 14:44:51.548622 ==
1700 14:44:51.548676 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1701 14:44:51.548728 fsp= 1, odt_onoff= 1, Byte mode= 0
1702 14:44:51.548780 ==
1703 14:44:51.548832 DQS Delay:
1704 14:44:51.548883 DQS0 = 0, DQS1 = 0
1705 14:44:51.548936 DQM Delay:
1706 14:44:51.548987 DQM0 = 21, DQM1 = 19
1707 14:44:51.549038 DQ Delay:
1708 14:44:51.549090 DQ0 =26, DQ1 =24, DQ2 =24, DQ3 =16
1709 14:44:51.549141 DQ4 =23, DQ5 =18, DQ6 =19, DQ7 =19
1710 14:44:51.549192 DQ8 =18, DQ9 =19, DQ10 =23, DQ11 =17
1711 14:44:51.549244 DQ12 =19, DQ13 =17, DQ14 =18, DQ15 =21
1712 14:44:51.549338
1713 14:44:51.549389
1714 14:44:51.549440 DramC Write-DBI off
1715 14:44:51.549492 ==
1716 14:44:51.549545 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1717 14:44:51.549597 fsp= 1, odt_onoff= 1, Byte mode= 0
1718 14:44:51.549649 ==
1719 14:44:51.549701 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1720 14:44:51.549753
1721 14:44:51.549804 Begin, DQ Scan Range 924~1180
1722 14:44:51.549855
1723 14:44:51.549906
1724 14:44:51.549956 TX Vref Scan disable
1725 14:44:51.550008 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1726 14:44:51.550061 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1727 14:44:51.550114 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1728 14:44:51.550166 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1729 14:44:51.550219 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1730 14:44:51.550272 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1731 14:44:51.550325 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1732 14:44:51.550378 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1733 14:44:51.550430 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1734 14:44:51.550483 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1735 14:44:51.550535 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1736 14:44:51.550588 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1737 14:44:51.550641 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1738 14:44:51.550693 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1739 14:44:51.550745 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1740 14:44:51.550798 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1741 14:44:51.550851 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1742 14:44:51.550903 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1743 14:44:51.550955 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1744 14:44:51.551008 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1745 14:44:51.551060 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1746 14:44:51.551112 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1747 14:44:51.551165 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1748 14:44:51.551217 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1749 14:44:51.551270 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1750 14:44:51.551323 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1751 14:44:51.551376 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1752 14:44:51.551428 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1753 14:44:51.551480 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1754 14:44:51.551533 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1755 14:44:51.551586 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1756 14:44:51.551638 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1757 14:44:51.551690 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1758 14:44:51.551742 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1759 14:44:51.551795 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1760 14:44:51.551847 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1761 14:44:51.551899 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1762 14:44:51.551951 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1763 14:44:51.552196 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1764 14:44:51.552258 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1765 14:44:51.552313 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1766 14:44:51.552366 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1767 14:44:51.552419 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1768 14:44:51.552472 967 |3 6 7|[0] xxxxxxxx oxxoxoxx [MSB]
1769 14:44:51.552525 968 |3 6 8|[0] xxxxxxxx ooxoooox [MSB]
1770 14:44:51.552578 969 |3 6 9|[0] xxxxxxxx ooxooooo [MSB]
1771 14:44:51.552630 970 |3 6 10|[0] xxxxxxxx ooxooooo [MSB]
1772 14:44:51.552683 971 |3 6 11|[0] xxxxxxxx oooooooo [MSB]
1773 14:44:51.552735 972 |3 6 12|[0] xxxoxxxx oooooooo [MSB]
1774 14:44:51.552788 973 |3 6 13|[0] xxxoxoxx oooooooo [MSB]
1775 14:44:51.552840 974 |3 6 14|[0] xxxoxoox oooooooo [MSB]
1776 14:44:51.552893 975 |3 6 15|[0] xxxoxoox oooooooo [MSB]
1777 14:44:51.552946 976 |3 6 16|[0] xxxoxooo oooooooo [MSB]
1778 14:44:51.552998 977 |3 6 17|[0] xooooooo oooooooo [MSB]
1779 14:44:51.553051 988 |3 6 28|[0] oooooooo oooooxoo [MSB]
1780 14:44:51.553104 989 |3 6 29|[0] oooooooo xooxoxoo [MSB]
1781 14:44:51.553156 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1782 14:44:51.553208 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1783 14:44:51.553290 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1784 14:44:51.553358 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1785 14:44:51.553411 994 |3 6 34|[0] oooooxoo xxxxxxxx [MSB]
1786 14:44:51.553464 995 |3 6 35|[0] oooxoxoo xxxxxxxx [MSB]
1787 14:44:51.553516 996 |3 6 36|[0] oooxoxoo xxxxxxxx [MSB]
1788 14:44:51.553569 997 |3 6 37|[0] oooxoxxo xxxxxxxx [MSB]
1789 14:44:51.553621 998 |3 6 38|[0] xxxxxxxx xxxxxxxx [MSB]
1790 14:44:51.553674 Byte0, DQ PI dly=985, DQM PI dly= 985
1791 14:44:51.553726 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 25)
1792 14:44:51.553778
1793 14:44:51.553829 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 25)
1794 14:44:51.553882
1795 14:44:51.553933 Byte1, DQ PI dly=978, DQM PI dly= 978
1796 14:44:51.553985 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
1797 14:44:51.554036
1798 14:44:51.554088 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
1799 14:44:51.554140
1800 14:44:51.554191 ==
1801 14:44:51.554243 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1802 14:44:51.554294 fsp= 1, odt_onoff= 1, Byte mode= 0
1803 14:44:51.554346 ==
1804 14:44:51.554398 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1805 14:44:51.554450
1806 14:44:51.554501 Begin, DQ Scan Range 954~1018
1807 14:44:51.554553 Write Rank1 MR14 =0x0
1808 14:44:51.554605
1809 14:44:51.554656 CH=0, VrefRange= 0, VrefLevel = 0
1810 14:44:51.554708 TX Bit0 (980~998) 19 989, Bit8 (969~984) 16 976,
1811 14:44:51.554760 TX Bit1 (978~996) 19 987, Bit9 (969~985) 17 977,
1812 14:44:51.554812 TX Bit2 (979~996) 18 987, Bit10 (975~989) 15 982,
1813 14:44:51.554864 TX Bit3 (974~991) 18 982, Bit11 (968~984) 17 976,
1814 14:44:51.554916 TX Bit4 (979~997) 19 988, Bit12 (969~984) 16 976,
1815 14:44:51.554967 TX Bit5 (976~990) 15 983, Bit13 (968~983) 16 975,
1816 14:44:51.555019 TX Bit6 (976~992) 17 984, Bit14 (969~984) 16 976,
1817 14:44:51.555071 TX Bit7 (978~993) 16 985, Bit15 (972~988) 17 980,
1818 14:44:51.555123
1819 14:44:51.555173 wait MRW command Rank1 MR14 =0x2 fired (1)
1820 14:44:51.555225 Write Rank1 MR14 =0x2
1821 14:44:51.555277
1822 14:44:51.555347 CH=0, VrefRange= 0, VrefLevel = 2
1823 14:44:51.555400 TX Bit0 (979~999) 21 989, Bit8 (968~985) 18 976,
1824 14:44:51.555452 TX Bit1 (978~997) 20 987, Bit9 (969~985) 17 977,
1825 14:44:51.555504 TX Bit2 (979~996) 18 987, Bit10 (974~990) 17 982,
1826 14:44:51.555556 TX Bit3 (973~991) 19 982, Bit11 (968~984) 17 976,
1827 14:44:51.555607 TX Bit4 (978~997) 20 987, Bit12 (968~985) 18 976,
1828 14:44:51.555659 TX Bit5 (976~990) 15 983, Bit13 (968~984) 17 976,
1829 14:44:51.555712 TX Bit6 (976~992) 17 984, Bit14 (969~984) 16 976,
1830 14:44:51.555763 TX Bit7 (978~993) 16 985, Bit15 (973~988) 16 980,
1831 14:44:51.555815
1832 14:44:51.555866 Write Rank1 MR14 =0x4
1833 14:44:51.555917
1834 14:44:51.555969 CH=0, VrefRange= 0, VrefLevel = 4
1835 14:44:51.556020 TX Bit0 (979~999) 21 989, Bit8 (968~985) 18 976,
1836 14:44:51.556072 TX Bit1 (978~998) 21 988, Bit9 (969~985) 17 977,
1837 14:44:51.556124 TX Bit2 (978~997) 20 987, Bit10 (973~990) 18 981,
1838 14:44:51.556176 TX Bit3 (973~992) 20 982, Bit11 (968~985) 18 976,
1839 14:44:51.556227 TX Bit4 (978~998) 21 988, Bit12 (969~986) 18 977,
1840 14:44:51.556280 TX Bit5 (976~991) 16 983, Bit13 (968~984) 17 976,
1841 14:44:51.556332 TX Bit6 (975~993) 19 984, Bit14 (969~985) 17 977,
1842 14:44:51.556384 TX Bit7 (977~995) 19 986, Bit15 (971~989) 19 980,
1843 14:44:51.556436
1844 14:44:51.556487 wait MRW command Rank1 MR14 =0x6 fired (1)
1845 14:44:51.556538 Write Rank1 MR14 =0x6
1846 14:44:51.556590
1847 14:44:51.556641 CH=0, VrefRange= 0, VrefLevel = 6
1848 14:44:51.556692 TX Bit0 (979~999) 21 989, Bit8 (968~985) 18 976,
1849 14:44:51.556744 TX Bit1 (978~998) 21 988, Bit9 (969~986) 18 977,
1850 14:44:51.556796 TX Bit2 (978~998) 21 988, Bit10 (973~990) 18 981,
1851 14:44:51.556848 TX Bit3 (972~992) 21 982, Bit11 (968~985) 18 976,
1852 14:44:51.556900 TX Bit4 (978~998) 21 988, Bit12 (969~986) 18 977,
1853 14:44:51.556951 TX Bit5 (975~992) 18 983, Bit13 (968~984) 17 976,
1854 14:44:51.557003 TX Bit6 (975~993) 19 984, Bit14 (968~986) 19 977,
1855 14:44:51.557054 TX Bit7 (978~995) 18 986, Bit15 (971~989) 19 980,
1856 14:44:51.557106
1857 14:44:51.557157 Write Rank1 MR14 =0x8
1858 14:44:51.557207
1859 14:44:51.557261 CH=0, VrefRange= 0, VrefLevel = 8
1860 14:44:51.557347 TX Bit0 (979~1000) 22 989, Bit8 (968~986) 19 977,
1861 14:44:51.557399 TX Bit1 (978~998) 21 988, Bit9 (969~986) 18 977,
1862 14:44:51.557451 TX Bit2 (978~998) 21 988, Bit10 (973~990) 18 981,
1863 14:44:51.557502 TX Bit3 (972~992) 21 982, Bit11 (967~986) 20 976,
1864 14:44:51.557555 TX Bit4 (977~999) 23 988, Bit12 (968~987) 20 977,
1865 14:44:51.557606 TX Bit5 (975~991) 17 983, Bit13 (968~985) 18 976,
1866 14:44:51.557659 TX Bit6 (975~994) 20 984, Bit14 (968~986) 19 977,
1867 14:44:51.557711 TX Bit7 (977~996) 20 986, Bit15 (971~989) 19 980,
1868 14:44:51.557763
1869 14:44:51.557814 Write Rank1 MR14 =0xa
1870 14:44:51.557866
1871 14:44:51.558105 CH=0, VrefRange= 0, VrefLevel = 10
1872 14:44:51.558163 TX Bit0 (978~1000) 23 989, Bit8 (968~986) 19 977,
1873 14:44:51.558216 TX Bit1 (978~999) 22 988, Bit9 (968~987) 20 977,
1874 14:44:51.558268 TX Bit2 (978~998) 21 988, Bit10 (971~990) 20 980,
1875 14:44:51.558320 TX Bit3 (971~993) 23 982, Bit11 (967~986) 20 976,
1876 14:44:51.558372 TX Bit4 (977~999) 23 988, Bit12 (968~988) 21 978,
1877 14:44:51.558424 TX Bit5 (974~992) 19 983, Bit13 (967~985) 19 976,
1878 14:44:51.558476 TX Bit6 (974~994) 21 984, Bit14 (968~987) 20 977,
1879 14:44:51.558528 TX Bit7 (977~997) 21 987, Bit15 (970~989) 20 979,
1880 14:44:51.558595
1881 14:44:51.558677 Write Rank1 MR14 =0xc
1882 14:44:51.558733
1883 14:44:51.558785 CH=0, VrefRange= 0, VrefLevel = 12
1884 14:44:51.558837 TX Bit0 (978~1000) 23 989, Bit8 (968~987) 20 977,
1885 14:44:51.558889 TX Bit1 (978~999) 22 988, Bit9 (968~988) 21 978,
1886 14:44:51.558942 TX Bit2 (978~999) 22 988, Bit10 (971~990) 20 980,
1887 14:44:51.558994 TX Bit3 (971~994) 24 982, Bit11 (967~987) 21 977,
1888 14:44:51.559045 TX Bit4 (977~999) 23 988, Bit12 (968~988) 21 978,
1889 14:44:51.559098 TX Bit5 (974~992) 19 983, Bit13 (967~986) 20 976,
1890 14:44:51.559150 TX Bit6 (974~995) 22 984, Bit14 (968~988) 21 978,
1891 14:44:51.559201 TX Bit7 (977~997) 21 987, Bit15 (970~990) 21 980,
1892 14:44:51.559253
1893 14:44:51.559304 Write Rank1 MR14 =0xe
1894 14:44:51.559355
1895 14:44:51.559407 CH=0, VrefRange= 0, VrefLevel = 14
1896 14:44:51.559459 TX Bit0 (978~1000) 23 989, Bit8 (967~988) 22 977,
1897 14:44:51.559511 TX Bit1 (977~999) 23 988, Bit9 (968~989) 22 978,
1898 14:44:51.559562 TX Bit2 (977~999) 23 988, Bit10 (971~991) 21 981,
1899 14:44:51.559614 TX Bit3 (971~994) 24 982, Bit11 (967~988) 22 977,
1900 14:44:51.559666 TX Bit4 (977~999) 23 988, Bit12 (968~989) 22 978,
1901 14:44:51.559717 TX Bit5 (974~993) 20 983, Bit13 (967~986) 20 976,
1902 14:44:51.559770 TX Bit6 (974~995) 22 984, Bit14 (968~988) 21 978,
1903 14:44:51.559822 TX Bit7 (976~998) 23 987, Bit15 (970~990) 21 980,
1904 14:44:51.559873
1905 14:44:51.559925 Write Rank1 MR14 =0x10
1906 14:44:51.559977
1907 14:44:51.560028 CH=0, VrefRange= 0, VrefLevel = 16
1908 14:44:51.560080 TX Bit0 (978~1001) 24 989, Bit8 (968~988) 21 978,
1909 14:44:51.560132 TX Bit1 (977~999) 23 988, Bit9 (968~989) 22 978,
1910 14:44:51.560184 TX Bit2 (977~999) 23 988, Bit10 (971~991) 21 981,
1911 14:44:51.560235 TX Bit3 (970~994) 25 982, Bit11 (967~988) 22 977,
1912 14:44:51.560287 TX Bit4 (977~999) 23 988, Bit12 (968~989) 22 978,
1913 14:44:51.560339 TX Bit5 (973~994) 22 983, Bit13 (967~987) 21 977,
1914 14:44:51.560390 TX Bit6 (973~996) 24 984, Bit14 (968~989) 22 978,
1915 14:44:51.560442 TX Bit7 (976~998) 23 987, Bit15 (969~990) 22 979,
1916 14:44:51.560493
1917 14:44:51.560544 Write Rank1 MR14 =0x12
1918 14:44:51.560595
1919 14:44:51.560647 CH=0, VrefRange= 0, VrefLevel = 18
1920 14:44:51.560698 TX Bit0 (978~1001) 24 989, Bit8 (967~989) 23 978,
1921 14:44:51.560751 TX Bit1 (978~1000) 23 989, Bit9 (968~989) 22 978,
1922 14:44:51.560802 TX Bit2 (977~999) 23 988, Bit10 (970~992) 23 981,
1923 14:44:51.560853 TX Bit3 (970~995) 26 982, Bit11 (966~989) 24 977,
1924 14:44:51.560905 TX Bit4 (977~1000) 24 988, Bit12 (968~989) 22 978,
1925 14:44:51.560957 TX Bit5 (972~994) 23 983, Bit13 (967~988) 22 977,
1926 14:44:51.561008 TX Bit6 (973~996) 24 984, Bit14 (967~989) 23 978,
1927 14:44:51.561060 TX Bit7 (976~998) 23 987, Bit15 (969~990) 22 979,
1928 14:44:51.561111
1929 14:44:51.561163 Write Rank1 MR14 =0x14
1930 14:44:51.561214
1931 14:44:51.561271 CH=0, VrefRange= 0, VrefLevel = 20
1932 14:44:51.561325 TX Bit0 (977~1001) 25 989, Bit8 (967~989) 23 978,
1933 14:44:51.561377 TX Bit1 (977~1000) 24 988, Bit9 (967~989) 23 978,
1934 14:44:51.561429 TX Bit2 (977~999) 23 988, Bit10 (970~992) 23 981,
1935 14:44:51.561480 TX Bit3 (970~995) 26 982, Bit11 (966~989) 24 977,
1936 14:44:51.561532 TX Bit4 (976~1000) 25 988, Bit12 (967~989) 23 978,
1937 14:44:51.561583 TX Bit5 (972~995) 24 983, Bit13 (966~988) 23 977,
1938 14:44:51.561636 TX Bit6 (973~997) 25 985, Bit14 (967~989) 23 978,
1939 14:44:51.561691 TX Bit7 (976~999) 24 987, Bit15 (969~990) 22 979,
1940 14:44:51.561748
1941 14:44:51.561811 Write Rank1 MR14 =0x16
1942 14:44:51.561864
1943 14:44:51.561915 CH=0, VrefRange= 0, VrefLevel = 22
1944 14:44:51.561968 TX Bit0 (977~1002) 26 989, Bit8 (966~989) 24 977,
1945 14:44:51.562020 TX Bit1 (977~1000) 24 988, Bit9 (968~990) 23 979,
1946 14:44:51.562072 TX Bit2 (976~1000) 25 988, Bit10 (970~992) 23 981,
1947 14:44:51.562124 TX Bit3 (969~995) 27 982, Bit11 (966~989) 24 977,
1948 14:44:51.562175 TX Bit4 (976~1001) 26 988, Bit12 (967~989) 23 978,
1949 14:44:51.562227 TX Bit5 (971~995) 25 983, Bit13 (966~987) 22 976,
1950 14:44:51.562279 TX Bit6 (972~998) 27 985, Bit14 (967~989) 23 978,
1951 14:44:51.562331 TX Bit7 (975~999) 25 987, Bit15 (969~990) 22 979,
1952 14:44:51.562382
1953 14:44:51.562434 Write Rank1 MR14 =0x18
1954 14:44:51.562485
1955 14:44:51.562537 CH=0, VrefRange= 0, VrefLevel = 24
1956 14:44:51.562589 TX Bit0 (977~1002) 26 989, Bit8 (966~989) 24 977,
1957 14:44:51.562640 TX Bit1 (977~1000) 24 988, Bit9 (968~990) 23 979,
1958 14:44:51.562692 TX Bit2 (976~1000) 25 988, Bit10 (970~992) 23 981,
1959 14:44:51.562744 TX Bit3 (969~995) 27 982, Bit11 (966~989) 24 977,
1960 14:44:51.562795 TX Bit4 (976~1001) 26 988, Bit12 (967~989) 23 978,
1961 14:44:51.562847 TX Bit5 (971~995) 25 983, Bit13 (966~987) 22 976,
1962 14:44:51.562899 TX Bit6 (972~998) 27 985, Bit14 (967~989) 23 978,
1963 14:44:51.562950 TX Bit7 (975~999) 25 987, Bit15 (969~990) 22 979,
1964 14:44:51.563002
1965 14:44:51.563053 Write Rank1 MR14 =0x1a
1966 14:44:51.563105
1967 14:44:51.563157 CH=0, VrefRange= 0, VrefLevel = 26
1968 14:44:51.563209 TX Bit0 (977~1002) 26 989, Bit8 (966~989) 24 977,
1969 14:44:51.563260 TX Bit1 (977~1000) 24 988, Bit9 (968~990) 23 979,
1970 14:44:51.563508 TX Bit2 (976~1000) 25 988, Bit10 (970~992) 23 981,
1971 14:44:51.563569 TX Bit3 (969~995) 27 982, Bit11 (966~989) 24 977,
1972 14:44:51.563621 TX Bit4 (976~1001) 26 988, Bit12 (967~989) 23 978,
1973 14:44:51.563673 TX Bit5 (971~995) 25 983, Bit13 (966~987) 22 976,
1974 14:44:51.689381 TX Bit6 (972~998) 27 985, Bit14 (967~989) 23 978,
1975 14:44:51.689501 TX Bit7 (975~999) 25 987, Bit15 (969~990) 22 979,
1976 14:44:51.689566
1977 14:44:51.689625 Write Rank1 MR14 =0x1c
1978 14:44:51.689682
1979 14:44:51.689737 CH=0, VrefRange= 0, VrefLevel = 28
1980 14:44:51.689792 TX Bit0 (977~1002) 26 989, Bit8 (966~989) 24 977,
1981 14:44:51.689847 TX Bit1 (977~1000) 24 988, Bit9 (968~990) 23 979,
1982 14:44:51.689901 TX Bit2 (976~1000) 25 988, Bit10 (970~992) 23 981,
1983 14:44:51.689987 TX Bit3 (969~995) 27 982, Bit11 (966~989) 24 977,
1984 14:44:51.690108 TX Bit4 (976~1001) 26 988, Bit12 (967~989) 23 978,
1985 14:44:51.690170 TX Bit5 (971~995) 25 983, Bit13 (966~987) 22 976,
1986 14:44:51.690224 TX Bit6 (972~998) 27 985, Bit14 (967~989) 23 978,
1987 14:44:51.690278 TX Bit7 (975~999) 25 987, Bit15 (969~990) 22 979,
1988 14:44:51.690346
1989 14:44:51.690412 Write Rank1 MR14 =0x1e
1990 14:44:51.690465
1991 14:44:51.690518 CH=0, VrefRange= 0, VrefLevel = 30
1992 14:44:51.690570 TX Bit0 (977~1002) 26 989, Bit8 (966~989) 24 977,
1993 14:44:51.690622 TX Bit1 (977~1000) 24 988, Bit9 (968~990) 23 979,
1994 14:44:51.690674 TX Bit2 (976~1000) 25 988, Bit10 (970~992) 23 981,
1995 14:44:51.690727 TX Bit3 (969~995) 27 982, Bit11 (966~989) 24 977,
1996 14:44:51.690779 TX Bit4 (976~1001) 26 988, Bit12 (967~989) 23 978,
1997 14:44:51.690832 TX Bit5 (971~995) 25 983, Bit13 (966~987) 22 976,
1998 14:44:51.690908 TX Bit6 (972~998) 27 985, Bit14 (967~989) 23 978,
1999 14:44:51.690973 TX Bit7 (975~999) 25 987, Bit15 (969~990) 22 979,
2000 14:44:51.691025
2001 14:44:51.691077
2002 14:44:51.691128 TX Vref found, early break! 367< 369
2003 14:44:51.691179 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =762/100 ps
2004 14:44:51.691232 u1DelayCellOfst[0]=8 cells (7 PI)
2005 14:44:51.691284 u1DelayCellOfst[1]=7 cells (6 PI)
2006 14:44:51.691336 u1DelayCellOfst[2]=7 cells (6 PI)
2007 14:44:51.691387 u1DelayCellOfst[3]=0 cells (0 PI)
2008 14:44:51.691438 u1DelayCellOfst[4]=7 cells (6 PI)
2009 14:44:51.691489 u1DelayCellOfst[5]=1 cells (1 PI)
2010 14:44:51.691540 u1DelayCellOfst[6]=3 cells (3 PI)
2011 14:44:51.691592 u1DelayCellOfst[7]=6 cells (5 PI)
2012 14:44:51.691643 Byte0, DQ PI dly=982, DQM PI dly= 985
2013 14:44:51.691695 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22)
2014 14:44:51.691747
2015 14:44:51.691799 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22)
2016 14:44:51.691851
2017 14:44:51.691902 u1DelayCellOfst[8]=1 cells (1 PI)
2018 14:44:51.691954 u1DelayCellOfst[9]=3 cells (3 PI)
2019 14:44:51.692005 u1DelayCellOfst[10]=6 cells (5 PI)
2020 14:44:51.692056 u1DelayCellOfst[11]=1 cells (1 PI)
2021 14:44:51.692108 u1DelayCellOfst[12]=2 cells (2 PI)
2022 14:44:51.692159 u1DelayCellOfst[13]=0 cells (0 PI)
2023 14:44:51.692210 u1DelayCellOfst[14]=2 cells (2 PI)
2024 14:44:51.692261 u1DelayCellOfst[15]=3 cells (3 PI)
2025 14:44:51.692312 Byte1, DQ PI dly=976, DQM PI dly= 978
2026 14:44:51.692363 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 16)
2027 14:44:51.692415
2028 14:44:51.692467 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 16)
2029 14:44:51.692519
2030 14:44:51.692570 Write Rank1 MR14 =0x16
2031 14:44:51.692622
2032 14:44:51.692672 Final TX Range 0 Vref 22
2033 14:44:51.692724
2034 14:44:51.692775 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2035 14:44:51.692827
2036 14:44:51.692878 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2037 14:44:51.692930 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2038 14:44:51.692982 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2039 14:44:51.693034 Write Rank1 MR3 =0xb0
2040 14:44:51.693102 DramC Write-DBI on
2041 14:44:51.693155 ==
2042 14:44:51.693208 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2043 14:44:51.693267 fsp= 1, odt_onoff= 1, Byte mode= 0
2044 14:44:51.693333 ==
2045 14:44:51.693403 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2046 14:44:51.693459
2047 14:44:51.693511 Begin, DQ Scan Range 698~762
2048 14:44:51.693563
2049 14:44:51.693614
2050 14:44:51.693666 TX Vref Scan disable
2051 14:44:51.693718 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2052 14:44:51.693772 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2053 14:44:51.693824 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2054 14:44:51.693877 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2055 14:44:51.693929 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2056 14:44:51.693982 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2057 14:44:51.694035 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2058 14:44:51.694087 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2059 14:44:51.694140 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2060 14:44:51.694193 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2061 14:44:51.694246 708 |2 6 4|[0] xxxxxxxx oooooooo [MSB]
2062 14:44:51.694298 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB]
2063 14:44:51.694351 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
2064 14:44:51.694403 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
2065 14:44:51.694456 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2066 14:44:51.694508 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2067 14:44:51.694561 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2068 14:44:51.694613 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2069 14:44:51.694666 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2070 14:44:51.694718 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2071 14:44:51.694810 734 |2 6 30|[0] oooooooo xxxxxxxx [MSB]
2072 14:44:51.694864 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB]
2073 14:44:51.694916 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
2074 14:44:51.694969 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2075 14:44:51.695022 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2076 14:44:51.695075 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2077 14:44:51.695128 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2078 14:44:51.695181 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2079 14:44:51.695233 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2080 14:44:51.695287 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2081 14:44:51.695340 744 |2 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
2082 14:44:51.695593 Byte0, DQ PI dly=730, DQM PI dly= 730
2083 14:44:51.695652 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 26)
2084 14:44:51.695707
2085 14:44:51.695760 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 26)
2086 14:44:51.695813
2087 14:44:51.695865 Byte1, DQ PI dly=720, DQM PI dly= 720
2088 14:44:51.695918 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 16)
2089 14:44:51.695971
2090 14:44:51.696024 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 16)
2091 14:44:51.696077
2092 14:44:51.696129 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2093 14:44:51.696182 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2094 14:44:51.696235 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2095 14:44:51.696288 Write Rank1 MR3 =0x30
2096 14:44:51.696340 DramC Write-DBI off
2097 14:44:51.696392
2098 14:44:51.696445 [DATLAT]
2099 14:44:51.696497 Freq=1600, CH0 RK1, use_rxtx_scan=0
2100 14:44:51.696549
2101 14:44:51.696601 DATLAT Default: 0x10
2102 14:44:51.696670 7, 0xFFFF, sum=0
2103 14:44:51.696738 8, 0xFFFF, sum=0
2104 14:44:51.696791 9, 0xFFFF, sum=0
2105 14:44:51.696844 10, 0xFFFF, sum=0
2106 14:44:51.696898 11, 0xFFFF, sum=0
2107 14:44:51.696971 12, 0xFFFF, sum=0
2108 14:44:51.697026 13, 0xFFFF, sum=0
2109 14:44:51.697079 14, 0x0, sum=1
2110 14:44:51.697133 15, 0x0, sum=2
2111 14:44:51.697186 16, 0x0, sum=3
2112 14:44:51.697239 17, 0x0, sum=4
2113 14:44:51.697332 pattern=2 first_step=14 total pass=5 best_step=16
2114 14:44:51.697386 ==
2115 14:44:51.697439 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2116 14:44:51.697491 fsp= 1, odt_onoff= 1, Byte mode= 0
2117 14:44:51.697544 ==
2118 14:44:51.697597 Start DQ dly to find pass range UseTestEngine =1
2119 14:44:51.697650 x-axis: bit #, y-axis: DQ dly (-127~63)
2120 14:44:51.697702 RX Vref Scan = 0
2121 14:44:51.697754 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2122 14:44:51.697808 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2123 14:44:51.697861 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2124 14:44:51.697914 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2125 14:44:51.697967 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2126 14:44:51.698020 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2127 14:44:51.698074 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2128 14:44:51.698126 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2129 14:44:51.698179 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2130 14:44:51.698233 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2131 14:44:51.698286 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2132 14:44:51.698339 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2133 14:44:51.698392 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2134 14:44:51.698445 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2135 14:44:51.698498 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2136 14:44:51.698551 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2137 14:44:51.698604 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2138 14:44:51.698688 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2139 14:44:51.698816 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2140 14:44:51.698923 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2141 14:44:51.698983 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2142 14:44:51.699066 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2143 14:44:51.699120 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2144 14:44:51.699174 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2145 14:44:51.699228 -2, [0] xxxxxxxx xxxxxxxx [MSB]
2146 14:44:51.699281 -1, [0] xxxxxxxx xxxxxxxx [MSB]
2147 14:44:51.699334 0, [0] xxxoxoxx oxxoxoxx [MSB]
2148 14:44:51.699388 1, [0] xxxoxoxx oxxoxoxx [MSB]
2149 14:44:51.699442 2, [0] xxxoxoxx oxxoxoox [MSB]
2150 14:44:51.699495 3, [0] xxxoxooo ooxoooox [MSB]
2151 14:44:51.699549 4, [0] xxxoxooo ooxooooo [MSB]
2152 14:44:51.699602 5, [0] xxxoxooo ooxooooo [MSB]
2153 14:44:51.699655 6, [0] xxxooooo oooooooo [MSB]
2154 14:44:51.699708 7, [0] xoxooooo oooooooo [MSB]
2155 14:44:51.699761 8, [0] xooooooo oooooooo [MSB]
2156 14:44:51.699815 33, [0] oooxoooo oooooooo [MSB]
2157 14:44:51.699868 34, [0] oooxoooo oooooxoo [MSB]
2158 14:44:51.699921 35, [0] oooxoooo oooxoxoo [MSB]
2159 14:44:51.699974 36, [0] oooxoxox oooxoxxo [MSB]
2160 14:44:51.700027 37, [0] oooxoxxx xooxoxxo [MSB]
2161 14:44:51.700079 38, [0] oooxoxxx xxoxxxxx [MSB]
2162 14:44:51.700132 39, [0] oooxoxxx xxoxxxxx [MSB]
2163 14:44:51.700185 40, [0] oooxoxxx xxoxxxxx [MSB]
2164 14:44:51.700238 41, [0] oooxxxxx xxoxxxxx [MSB]
2165 14:44:51.700290 42, [0] oooxxxxx xxoxxxxx [MSB]
2166 14:44:51.700344 43, [0] xxxxxxxx xxxxxxxx [MSB]
2167 14:44:51.700397 iDelay=43, Bit 0, Center 25 (9 ~ 42) 34
2168 14:44:51.700456 iDelay=43, Bit 1, Center 24 (7 ~ 42) 36
2169 14:44:51.700558 iDelay=43, Bit 2, Center 25 (8 ~ 42) 35
2170 14:44:51.700642 iDelay=43, Bit 3, Center 16 (0 ~ 32) 33
2171 14:44:51.700694 iDelay=43, Bit 4, Center 23 (6 ~ 40) 35
2172 14:44:51.700746 iDelay=43, Bit 5, Center 17 (0 ~ 35) 36
2173 14:44:51.700798 iDelay=43, Bit 6, Center 19 (3 ~ 36) 34
2174 14:44:51.700850 iDelay=43, Bit 7, Center 19 (3 ~ 35) 33
2175 14:44:51.700902 iDelay=43, Bit 8, Center 18 (0 ~ 36) 37
2176 14:44:51.700954 iDelay=43, Bit 9, Center 20 (3 ~ 37) 35
2177 14:44:51.701006 iDelay=43, Bit 10, Center 24 (6 ~ 42) 37
2178 14:44:51.701058 iDelay=43, Bit 11, Center 17 (0 ~ 34) 35
2179 14:44:51.701110 iDelay=43, Bit 12, Center 20 (3 ~ 37) 35
2180 14:44:51.701163 iDelay=43, Bit 13, Center 16 (0 ~ 33) 34
2181 14:44:51.701215 iDelay=43, Bit 14, Center 18 (2 ~ 35) 34
2182 14:44:51.701287 iDelay=43, Bit 15, Center 20 (4 ~ 37) 34
2183 14:44:51.701353 ==
2184 14:44:51.701406 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2185 14:44:51.701460 fsp= 1, odt_onoff= 1, Byte mode= 0
2186 14:44:51.701512 ==
2187 14:44:51.701565 DQS Delay:
2188 14:44:51.701617 DQS0 = 0, DQS1 = 0
2189 14:44:51.701670 DQM Delay:
2190 14:44:51.701722 DQM0 = 21, DQM1 = 19
2191 14:44:51.701774 DQ Delay:
2192 14:44:51.701827 DQ0 =25, DQ1 =24, DQ2 =25, DQ3 =16
2193 14:44:51.701880 DQ4 =23, DQ5 =17, DQ6 =19, DQ7 =19
2194 14:44:51.701932 DQ8 =18, DQ9 =20, DQ10 =24, DQ11 =17
2195 14:44:51.701985 DQ12 =20, DQ13 =16, DQ14 =18, DQ15 =20
2196 14:44:51.702037
2197 14:44:51.702089
2198 14:44:51.702140
2199 14:44:51.702192 [DramC_TX_OE_Calibration] TA2
2200 14:44:51.702244 Original DQ_B0 (3 6) =30, OEN = 27
2201 14:44:51.702298 Original DQ_B1 (3 6) =30, OEN = 27
2202 14:44:51.702350 23, 0x0, End_B0=23 End_B1=23
2203 14:44:51.702403 24, 0x0, End_B0=24 End_B1=24
2204 14:44:51.702457 25, 0x0, End_B0=25 End_B1=25
2205 14:44:51.702510 26, 0x0, End_B0=26 End_B1=26
2206 14:44:51.702563 27, 0x0, End_B0=27 End_B1=27
2207 14:44:51.702616 28, 0x0, End_B0=28 End_B1=28
2208 14:44:51.702669 29, 0x0, End_B0=29 End_B1=29
2209 14:44:51.702722 30, 0x0, End_B0=30 End_B1=30
2210 14:44:51.702775 31, 0xFFFF, End_B0=30 End_B1=30
2211 14:44:51.702828 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2212 14:44:51.703070 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2213 14:44:51.703129
2214 14:44:51.703182
2215 14:44:51.703235 Write Rank1 MR23 =0x3f
2216 14:44:51.703288 [DQSOSC]
2217 14:44:51.703341 [DQSOSCAuto] RK1, (LSB)MR18= 0x7d, (MSB)MR19= 0x3, tDQSOscB0 = 352 ps tDQSOscB1 = 0 ps
2218 14:44:51.703395 CH0_RK1: MR19=0x3, MR18=0x7D, DQSOSC=352, MR23=63, INC=19, DEC=29
2219 14:44:51.703467 Write Rank1 MR23 =0x3f
2220 14:44:51.703522 [DQSOSC]
2221 14:44:51.703575 [DQSOSCAuto] RK1, (LSB)MR18= 0x78, (MSB)MR19= 0x3, tDQSOscB0 = 354 ps tDQSOscB1 = 0 ps
2222 14:44:51.703629 CH0 RK1: MR19=3, MR18=78
2223 14:44:51.703681 [RxdqsGatingPostProcess] freq 1600
2224 14:44:51.703734 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2225 14:44:51.703787 Rank: 0
2226 14:44:51.703840 best DQS0 dly(2T, 0.5T) = (2, 5)
2227 14:44:51.703893 best DQS1 dly(2T, 0.5T) = (2, 5)
2228 14:44:51.703945 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
2229 14:44:51.703997 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
2230 14:44:51.704049 Rank: 1
2231 14:44:51.704101 best DQS0 dly(2T, 0.5T) = (2, 6)
2232 14:44:51.704153 best DQS1 dly(2T, 0.5T) = (2, 6)
2233 14:44:51.704205 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2234 14:44:51.704257 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2235 14:44:51.704309 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2236 14:44:51.704362 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2237 14:44:51.704414 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2238 14:44:51.704466 Write Rank0 MR13 =0x59
2239 14:44:51.704519 ==
2240 14:44:51.704570 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2241 14:44:51.704623 fsp= 1, odt_onoff= 1, Byte mode= 0
2242 14:44:51.704676 ==
2243 14:44:51.704728 === u2Vref_new: 0x56 --> 0x3a
2244 14:44:51.704781 === u2Vref_new: 0x58 --> 0x58
2245 14:44:51.704833 === u2Vref_new: 0x5a --> 0x5a
2246 14:44:51.704885 === u2Vref_new: 0x5c --> 0x78
2247 14:44:51.704937 === u2Vref_new: 0x5e --> 0x7a
2248 14:44:51.705001 === u2Vref_new: 0x60 --> 0x90
2249 14:44:51.706906 [CA 0] Center 36 (9~63) winsize 55
2250 14:44:51.710784 [CA 1] Center 35 (7~63) winsize 57
2251 14:44:51.713833 [CA 2] Center 32 (3~62) winsize 60
2252 14:44:51.713913 [CA 3] Center 33 (3~63) winsize 61
2253 14:44:51.717219 [CA 4] Center 33 (3~63) winsize 61
2254 14:44:51.720690 [CA 5] Center 25 (-1~52) winsize 54
2255 14:44:51.720770
2256 14:44:51.724223 [CATrainingPosCal] consider 1 rank data
2257 14:44:51.727600 u2DelayCellTimex100 = 762/100 ps
2258 14:44:51.730598 CA0 delay=36 (9~63),Diff = 11 PI (14 cell)
2259 14:44:51.737190 CA1 delay=35 (7~63),Diff = 10 PI (12 cell)
2260 14:44:51.740694 CA2 delay=32 (3~62),Diff = 7 PI (8 cell)
2261 14:44:51.744451 CA3 delay=33 (3~63),Diff = 8 PI (10 cell)
2262 14:44:51.747340 CA4 delay=33 (3~63),Diff = 8 PI (10 cell)
2263 14:44:51.750464 CA5 delay=25 (-1~52),Diff = 0 PI (0 cell)
2264 14:44:51.750545
2265 14:44:51.753845 CA PerBit enable=1, Macro0, CA PI delay=25
2266 14:44:51.757792 === u2Vref_new: 0x56 --> 0x3a
2267 14:44:51.757873
2268 14:44:51.760793 Vref(ca) range 1: 22
2269 14:44:51.760873
2270 14:44:51.760937 CS Dly= 10 (41-0-32)
2271 14:44:51.764301 Write Rank0 MR13 =0xd8
2272 14:44:51.767732 Write Rank0 MR13 =0xd8
2273 14:44:51.767823 Write Rank0 MR12 =0x56
2274 14:44:51.770581 Write Rank1 MR13 =0x59
2275 14:44:51.770671 ==
2276 14:44:51.773948 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2277 14:44:51.777498 fsp= 1, odt_onoff= 1, Byte mode= 0
2278 14:44:51.777580 ==
2279 14:44:51.780530 === u2Vref_new: 0x56 --> 0x3a
2280 14:44:51.783839 === u2Vref_new: 0x58 --> 0x58
2281 14:44:51.787937 === u2Vref_new: 0x5a --> 0x5a
2282 14:44:51.790751 === u2Vref_new: 0x5c --> 0x78
2283 14:44:51.793835 === u2Vref_new: 0x5e --> 0x7a
2284 14:44:51.797313 === u2Vref_new: 0x60 --> 0x90
2285 14:44:51.800538 [CA 0] Center 36 (9~63) winsize 55
2286 14:44:51.803884 [CA 1] Center 35 (7~63) winsize 57
2287 14:44:51.807261 [CA 2] Center 32 (3~62) winsize 60
2288 14:44:51.810705 [CA 3] Center 33 (3~63) winsize 61
2289 14:44:51.814443 [CA 4] Center 33 (4~63) winsize 60
2290 14:44:51.817709 [CA 5] Center 25 (-2~53) winsize 56
2291 14:44:51.817780
2292 14:44:51.820773 [CATrainingPosCal] consider 2 rank data
2293 14:44:51.824058 u2DelayCellTimex100 = 762/100 ps
2294 14:44:51.827372 CA0 delay=36 (9~63),Diff = 11 PI (14 cell)
2295 14:44:51.830967 CA1 delay=35 (7~63),Diff = 10 PI (12 cell)
2296 14:44:51.834005 CA2 delay=32 (3~62),Diff = 7 PI (8 cell)
2297 14:44:51.837464 CA3 delay=33 (3~63),Diff = 8 PI (10 cell)
2298 14:44:51.840890 CA4 delay=33 (4~63),Diff = 8 PI (10 cell)
2299 14:44:51.844318 CA5 delay=25 (-1~52),Diff = 0 PI (0 cell)
2300 14:44:51.844403
2301 14:44:51.847750 CA PerBit enable=1, Macro0, CA PI delay=25
2302 14:44:51.851177 === u2Vref_new: 0x58 --> 0x58
2303 14:44:51.851272
2304 14:44:51.854163 Vref(ca) range 1: 24
2305 14:44:51.854257
2306 14:44:51.854343 CS Dly= 11 (42-0-32)
2307 14:44:51.857445 Write Rank1 MR13 =0xd8
2308 14:44:51.861063 Write Rank1 MR13 =0xd8
2309 14:44:51.861159 Write Rank1 MR12 =0x58
2310 14:44:51.864292 [RankSwap] Rank num 2, (Multi 1), Rank 0
2311 14:44:51.867525 Write Rank0 MR2 =0xad
2312 14:44:51.867621 [Write Leveling]
2313 14:44:51.871105 delay byte0 byte1 byte2 byte3
2314 14:44:51.871206
2315 14:44:51.874379 10 0 0
2316 14:44:51.874475 11 0 0
2317 14:44:51.877651 12 0 0
2318 14:44:51.877747 13 0 0
2319 14:44:51.877842 14 0 0
2320 14:44:51.881022 15 0 0
2321 14:44:51.881121 16 0 0
2322 14:44:51.884239 17 0 0
2323 14:44:51.884342 18 0 0
2324 14:44:51.884431 19 0 0
2325 14:44:51.887873 20 0 0
2326 14:44:51.887976 21 0 0
2327 14:44:51.890860 22 0 0
2328 14:44:51.890958 23 0 0
2329 14:44:51.894622 24 0 0
2330 14:44:51.894729 25 0 0
2331 14:44:51.894820 26 0 0
2332 14:44:51.897495 27 0 0
2333 14:44:51.897565 28 0 0
2334 14:44:51.900828 29 0 0
2335 14:44:51.900929 30 0 0
2336 14:44:51.901018 31 0 ff
2337 14:44:51.904952 32 0 ff
2338 14:44:51.905055 33 0 ff
2339 14:44:51.908102 34 0 ff
2340 14:44:51.908199 35 ff ff
2341 14:44:51.911324 36 ff ff
2342 14:44:51.911423 37 ff ff
2343 14:44:51.914389 38 ff ff
2344 14:44:51.914485 39 ff ff
2345 14:44:51.914573 40 ff ff
2346 14:44:51.918292 41 ff ff
2347 14:44:51.921336 pass bytecount = 0xff (0xff: all bytes pass)
2348 14:44:51.921420
2349 14:44:51.924662 DQS0 dly: 35
2350 14:44:51.924755 DQS1 dly: 31
2351 14:44:51.928008 Write Rank0 MR2 =0x2d
2352 14:44:51.931387 [RankSwap] Rank num 2, (Multi 1), Rank 0
2353 14:44:51.931482 Write Rank0 MR1 =0xd6
2354 14:44:51.931568 [Gating]
2355 14:44:51.934717 ==
2356 14:44:51.937722 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2357 14:44:51.941321 fsp= 1, odt_onoff= 1, Byte mode= 0
2358 14:44:51.941419 ==
2359 14:44:51.944673 3 1 0 |2d2d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2360 14:44:51.951508 3 1 4 |3130 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2361 14:44:51.954494 3 1 8 |2f2e 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2362 14:44:51.957806 3 1 12 |2f2f 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2363 14:44:51.964525 3 1 16 |908 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2364 14:44:51.968181 3 1 20 |2d2c 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2365 14:44:51.971280 3 1 24 |302f 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2366 14:44:51.974765 3 1 28 |201 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
2367 14:44:51.981535 3 2 0 |3737 403 |(11 11)(11 11) |(0 0)(1 1)| 0
2368 14:44:51.984420 3 2 4 |1c1b 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2369 14:44:51.987932 3 2 8 |3837 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2370 14:44:51.995164 3 2 12 |3736 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2371 14:44:51.998234 3 2 16 |3636 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2372 14:44:52.001474 3 2 20 |3535 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2373 14:44:52.008336 3 2 24 |3535 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2374 14:44:52.011820 3 2 28 |2525 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2375 14:44:52.015201 [Byte 0] Lead/lag falling Transition (3, 2, 28)
2376 14:44:52.018025 3 3 0 |2c2b 3d3d |(11 11)(11 11) |(0 1)(1 1)| 0
2377 14:44:52.024861 3 3 4 |3534 3736 |(11 11)(11 11) |(0 1)(1 1)| 0
2378 14:44:52.028518 3 3 8 |3534 504 |(11 11)(11 11) |(0 1)(1 1)| 0
2379 14:44:52.031683 [Byte 1] Lead/lag falling Transition (3, 3, 8)
2380 14:44:52.034981 3 3 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2381 14:44:52.041671 3 3 16 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2382 14:44:52.045368 3 3 20 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2383 14:44:52.048625 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2384 14:44:52.055126 3 3 28 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2385 14:44:52.058392 3 4 0 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
2386 14:44:52.062009 3 4 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2387 14:44:52.068543 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2388 14:44:52.072352 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2389 14:44:52.075960 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2390 14:44:52.078857 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2391 14:44:52.085607 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2392 14:44:52.088633 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2393 14:44:52.092164 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2394 14:44:52.098642 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2395 14:44:52.102056 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2396 14:44:52.105156 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2397 14:44:52.112121 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2398 14:44:52.115491 [Byte 0] Lead/lag falling Transition (3, 5, 16)
2399 14:44:52.118909 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2400 14:44:52.122091 [Byte 0] Lead/lag Transition tap number (2)
2401 14:44:52.128909 3 5 24 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2402 14:44:52.132290 [Byte 1] Lead/lag falling Transition (3, 5, 24)
2403 14:44:52.135909 3 5 28 |605 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2404 14:44:52.139180 [Byte 1] Lead/lag Transition tap number (2)
2405 14:44:52.142429 3 6 0 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
2406 14:44:52.145756 [Byte 0]First pass (3, 6, 0)
2407 14:44:52.149029 3 6 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2408 14:44:52.152526 [Byte 1]First pass (3, 6, 4)
2409 14:44:52.155991 3 6 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2410 14:44:52.162533 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2411 14:44:52.166066 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2412 14:44:52.169456 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2413 14:44:52.172843 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2414 14:44:52.176119 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2415 14:44:52.182760 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2416 14:44:52.186111 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2417 14:44:52.189566 All bytes gating window > 1UI, Early break!
2418 14:44:52.189665
2419 14:44:52.192575 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 20)
2420 14:44:52.192681
2421 14:44:52.196065 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 28)
2422 14:44:52.196146
2423 14:44:52.196211
2424 14:44:52.196270
2425 14:44:52.203014 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 20)
2426 14:44:52.203103
2427 14:44:52.206359 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 28)
2428 14:44:52.206440
2429 14:44:52.206502
2430 14:44:52.206561 Write Rank0 MR1 =0x56
2431 14:44:52.206618
2432 14:44:52.209976 best RODT dly(2T, 0.5T) = (2, 2)
2433 14:44:52.210056
2434 14:44:52.213104 best RODT dly(2T, 0.5T) = (2, 2)
2435 14:44:52.213184 ==
2436 14:44:52.219977 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2437 14:44:52.222955 fsp= 1, odt_onoff= 1, Byte mode= 0
2438 14:44:52.223037 ==
2439 14:44:52.226268 Start DQ dly to find pass range UseTestEngine =0
2440 14:44:52.229922 x-axis: bit #, y-axis: DQ dly (-127~63)
2441 14:44:52.233154 RX Vref Scan = 0
2442 14:44:52.236478 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2443 14:44:52.236560 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2444 14:44:52.239633 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2445 14:44:52.243034 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2446 14:44:52.246505 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2447 14:44:52.249462 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2448 14:44:52.252809 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2449 14:44:52.256336 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2450 14:44:52.260171 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2451 14:44:52.260255 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2452 14:44:52.263291 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2453 14:44:52.266527 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2454 14:44:52.270120 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2455 14:44:52.273266 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2456 14:44:52.276427 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2457 14:44:52.279729 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2458 14:44:52.283205 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2459 14:44:52.283288 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2460 14:44:52.286669 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2461 14:44:52.289901 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2462 14:44:52.293228 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2463 14:44:52.296757 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2464 14:44:52.300063 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2465 14:44:52.300148 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2466 14:44:52.303590 -2, [0] xxxxxxxx xxxxxxxx [MSB]
2467 14:44:52.306802 -1, [0] xxxxxxxx xxxxxxxx [MSB]
2468 14:44:52.310374 0, [0] xxxoxxxx xxxxxxxx [MSB]
2469 14:44:52.313228 1, [0] xxxoxxxx xxxxxxxo [MSB]
2470 14:44:52.316772 2, [0] xxooxxxo xxxxxxxo [MSB]
2471 14:44:52.316864 3, [0] xxoooxxo xxxxxxxo [MSB]
2472 14:44:52.319916 4, [0] xxoooxxo oooxooxo [MSB]
2473 14:44:52.323610 5, [0] xxoooxxo oooooooo [MSB]
2474 14:44:52.327010 6, [0] xooooxxo oooooooo [MSB]
2475 14:44:52.330002 7, [0] xoooooxo oooooooo [MSB]
2476 14:44:52.333306 8, [0] ooooooxo oooooooo [MSB]
2477 14:44:52.333391 32, [0] ooxxoooo oooooooo [MSB]
2478 14:44:52.337165 33, [0] ooxxoooo ooooooox [MSB]
2479 14:44:52.340405 34, [0] ooxxoooo ooooooox [MSB]
2480 14:44:52.343520 35, [0] ooxxxooo ooxoooox [MSB]
2481 14:44:52.346898 36, [0] ooxxxoox xoxoooox [MSB]
2482 14:44:52.350098 37, [0] ooxxxoox xxxxoxxx [MSB]
2483 14:44:52.353565 38, [0] ooxxxoox xxxxoxxx [MSB]
2484 14:44:52.353648 39, [0] ooxxxoox xxxxxxxx [MSB]
2485 14:44:52.356688 40, [0] oxxxxoox xxxxxxxx [MSB]
2486 14:44:52.360086 41, [0] xxxxxxxx xxxxxxxx [MSB]
2487 14:44:52.363981 iDelay=41, Bit 0, Center 24 (8 ~ 40) 33
2488 14:44:52.367076 iDelay=41, Bit 1, Center 22 (6 ~ 39) 34
2489 14:44:52.370064 iDelay=41, Bit 2, Center 16 (2 ~ 31) 30
2490 14:44:52.373704 iDelay=41, Bit 3, Center 15 (0 ~ 31) 32
2491 14:44:52.376794 iDelay=41, Bit 4, Center 18 (3 ~ 34) 32
2492 14:44:52.380590 iDelay=41, Bit 5, Center 23 (7 ~ 40) 34
2493 14:44:52.383714 iDelay=41, Bit 6, Center 24 (9 ~ 40) 32
2494 14:44:52.390490 iDelay=41, Bit 7, Center 18 (2 ~ 35) 34
2495 14:44:52.393765 iDelay=41, Bit 8, Center 19 (4 ~ 35) 32
2496 14:44:52.396847 iDelay=41, Bit 9, Center 20 (4 ~ 36) 33
2497 14:44:52.400604 iDelay=41, Bit 10, Center 19 (4 ~ 34) 31
2498 14:44:52.403698 iDelay=41, Bit 11, Center 20 (5 ~ 36) 32
2499 14:44:52.406951 iDelay=41, Bit 12, Center 21 (4 ~ 38) 35
2500 14:44:52.410536 iDelay=41, Bit 13, Center 20 (4 ~ 36) 33
2501 14:44:52.413604 iDelay=41, Bit 14, Center 20 (5 ~ 36) 32
2502 14:44:52.417198 iDelay=41, Bit 15, Center 16 (1 ~ 32) 32
2503 14:44:52.417316 ==
2504 14:44:52.423770 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2505 14:44:52.427139 fsp= 1, odt_onoff= 1, Byte mode= 0
2506 14:44:52.427222 ==
2507 14:44:52.427286 DQS Delay:
2508 14:44:52.430173 DQS0 = 0, DQS1 = 0
2509 14:44:52.430253 DQM Delay:
2510 14:44:52.430319 DQM0 = 20, DQM1 = 19
2511 14:44:52.433703 DQ Delay:
2512 14:44:52.436886 DQ0 =24, DQ1 =22, DQ2 =16, DQ3 =15
2513 14:44:52.440228 DQ4 =18, DQ5 =23, DQ6 =24, DQ7 =18
2514 14:44:52.443430 DQ8 =19, DQ9 =20, DQ10 =19, DQ11 =20
2515 14:44:52.446853 DQ12 =21, DQ13 =20, DQ14 =20, DQ15 =16
2516 14:44:52.446934
2517 14:44:52.446997
2518 14:44:52.447056 DramC Write-DBI off
2519 14:44:52.447115 ==
2520 14:44:52.453893 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2521 14:44:52.457007 fsp= 1, odt_onoff= 1, Byte mode= 0
2522 14:44:52.457088 ==
2523 14:44:52.460120 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2524 14:44:52.460204
2525 14:44:52.463746 Begin, DQ Scan Range 927~1183
2526 14:44:52.463827
2527 14:44:52.463891
2528 14:44:52.467074 TX Vref Scan disable
2529 14:44:52.470344 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
2530 14:44:52.473486 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
2531 14:44:52.476608 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2532 14:44:52.480278 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2533 14:44:52.483839 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2534 14:44:52.487006 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2535 14:44:52.490543 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2536 14:44:52.493479 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2537 14:44:52.497044 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2538 14:44:52.500283 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2539 14:44:52.503658 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2540 14:44:52.510019 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2541 14:44:52.513231 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2542 14:44:52.516625 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2543 14:44:52.520414 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2544 14:44:52.523391 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2545 14:44:52.526613 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2546 14:44:52.530671 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2547 14:44:52.533374 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2548 14:44:52.536691 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2549 14:44:52.540105 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2550 14:44:52.543330 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2551 14:44:52.546634 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2552 14:44:52.549900 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2553 14:44:52.553723 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2554 14:44:52.556739 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2555 14:44:52.559835 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2556 14:44:52.563459 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2557 14:44:52.570095 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2558 14:44:52.573272 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2559 14:44:52.576503 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2560 14:44:52.580064 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2561 14:44:52.583640 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2562 14:44:52.586568 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2563 14:44:52.590402 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2564 14:44:52.593446 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2565 14:44:52.596657 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2566 14:44:52.600089 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2567 14:44:52.603621 965 |3 6 5|[0] xxxxxxxx xxxxxxxo [MSB]
2568 14:44:52.606375 966 |3 6 6|[0] xxxxxxxx xxxxxxxo [MSB]
2569 14:44:52.609915 967 |3 6 7|[0] xxxxxxxx ooxxxxxo [MSB]
2570 14:44:52.613397 968 |3 6 8|[0] xxxxxxxx oooxxxxo [MSB]
2571 14:44:52.616607 969 |3 6 9|[0] xxxxxxxx oooooooo [MSB]
2572 14:44:52.619736 970 |3 6 10|[0] xxxxxxxx oooooooo [MSB]
2573 14:44:52.623499 971 |3 6 11|[0] xxxxxxxx oooooooo [MSB]
2574 14:44:52.626305 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB]
2575 14:44:52.629723 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
2576 14:44:52.632990 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
2577 14:44:52.639642 975 |3 6 15|[0] xxoooxxo oooooooo [MSB]
2578 14:44:52.643531 976 |3 6 16|[0] xooooxxo oooooooo [MSB]
2579 14:44:52.646556 977 |3 6 17|[0] xoooooxo oooooooo [MSB]
2580 14:44:52.649779 989 |3 6 29|[0] oooooooo ooooooox [MSB]
2581 14:44:52.652988 990 |3 6 30|[0] oooooooo oxooooox [MSB]
2582 14:44:52.656188 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
2583 14:44:52.659868 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
2584 14:44:52.663183 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
2585 14:44:52.669973 994 |3 6 34|[0] oooxoooo xxxxxxxx [MSB]
2586 14:44:52.673138 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB]
2587 14:44:52.676727 996 |3 6 36|[0] ooxxooox xxxxxxxx [MSB]
2588 14:44:52.679835 997 |3 6 37|[0] ooxxooox xxxxxxxx [MSB]
2589 14:44:52.683048 998 |3 6 38|[0] xxxxxxxx xxxxxxxx [MSB]
2590 14:44:52.686513 Byte0, DQ PI dly=985, DQM PI dly= 985
2591 14:44:52.690267 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 25)
2592 14:44:52.690339
2593 14:44:52.692740 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 25)
2594 14:44:52.696322
2595 14:44:52.699439 Byte1, DQ PI dly=977, DQM PI dly= 977
2596 14:44:52.702887 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
2597 14:44:52.702958
2598 14:44:52.706153 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
2599 14:44:52.706228
2600 14:44:52.706290 ==
2601 14:44:52.713535 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2602 14:44:52.716312 fsp= 1, odt_onoff= 1, Byte mode= 0
2603 14:44:52.716408 ==
2604 14:44:52.719798 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2605 14:44:52.719892
2606 14:44:52.723193 Begin, DQ Scan Range 953~1017
2607 14:44:52.726241 Write Rank0 MR14 =0x0
2608 14:44:52.733691
2609 14:44:52.733776 CH=1, VrefRange= 0, VrefLevel = 0
2610 14:44:52.740230 TX Bit0 (979~997) 19 988, Bit8 (968~985) 18 976,
2611 14:44:52.743495 TX Bit1 (977~995) 19 986, Bit9 (968~985) 18 976,
2612 14:44:52.750024 TX Bit2 (977~991) 15 984, Bit10 (970~985) 16 977,
2613 14:44:52.753381 TX Bit3 (975~990) 16 982, Bit11 (971~988) 18 979,
2614 14:44:52.756726 TX Bit4 (977~992) 16 984, Bit12 (970~988) 19 979,
2615 14:44:52.763569 TX Bit5 (978~997) 20 987, Bit13 (972~987) 16 979,
2616 14:44:52.766642 TX Bit6 (979~997) 19 988, Bit14 (970~986) 17 978,
2617 14:44:52.769946 TX Bit7 (977~991) 15 984, Bit15 (967~985) 19 976,
2618 14:44:52.770052
2619 14:44:52.773223 Write Rank0 MR14 =0x2
2620 14:44:52.782410
2621 14:44:52.782482 CH=1, VrefRange= 0, VrefLevel = 2
2622 14:44:52.789202 TX Bit0 (978~998) 21 988, Bit8 (969~985) 17 977,
2623 14:44:52.792546 TX Bit1 (977~996) 20 986, Bit9 (968~985) 18 976,
2624 14:44:52.799454 TX Bit2 (976~992) 17 984, Bit10 (969~985) 17 977,
2625 14:44:52.802475 TX Bit3 (975~990) 16 982, Bit11 (971~988) 18 979,
2626 14:44:52.806111 TX Bit4 (977~993) 17 985, Bit12 (970~988) 19 979,
2627 14:44:52.812686 TX Bit5 (978~997) 20 987, Bit13 (972~988) 17 980,
2628 14:44:52.815795 TX Bit6 (979~997) 19 988, Bit14 (970~986) 17 978,
2629 14:44:52.819440 TX Bit7 (977~991) 15 984, Bit15 (967~985) 19 976,
2630 14:44:52.819537
2631 14:44:52.822288 Write Rank0 MR14 =0x4
2632 14:44:52.831549
2633 14:44:52.831646 CH=1, VrefRange= 0, VrefLevel = 4
2634 14:44:52.838717 TX Bit0 (978~998) 21 988, Bit8 (968~986) 19 977,
2635 14:44:52.842016 TX Bit1 (977~996) 20 986, Bit9 (968~986) 19 977,
2636 14:44:52.845141 TX Bit2 (976~992) 17 984, Bit10 (969~986) 18 977,
2637 14:44:52.851682 TX Bit3 (974~990) 17 982, Bit11 (970~989) 20 979,
2638 14:44:52.854893 TX Bit4 (977~993) 17 985, Bit12 (970~989) 20 979,
2639 14:44:52.861672 TX Bit5 (977~997) 21 987, Bit13 (971~989) 19 980,
2640 14:44:52.865002 TX Bit6 (979~998) 20 988, Bit14 (970~987) 18 978,
2641 14:44:52.868293 TX Bit7 (976~992) 17 984, Bit15 (966~985) 20 975,
2642 14:44:52.868389
2643 14:44:52.871490 Write Rank0 MR14 =0x6
2644 14:44:52.880637
2645 14:44:52.880739 CH=1, VrefRange= 0, VrefLevel = 6
2646 14:44:52.887298 TX Bit0 (978~998) 21 988, Bit8 (968~986) 19 977,
2647 14:44:52.890943 TX Bit1 (977~996) 20 986, Bit9 (968~986) 19 977,
2648 14:44:52.897275 TX Bit2 (976~992) 17 984, Bit10 (969~986) 18 977,
2649 14:44:52.900856 TX Bit3 (974~990) 17 982, Bit11 (970~989) 20 979,
2650 14:44:52.904182 TX Bit4 (977~993) 17 985, Bit12 (970~989) 20 979,
2651 14:44:52.910750 TX Bit5 (977~997) 21 987, Bit13 (971~989) 19 980,
2652 14:44:52.913799 TX Bit6 (979~998) 20 988, Bit14 (970~987) 18 978,
2653 14:44:52.917412 TX Bit7 (976~992) 17 984, Bit15 (966~985) 20 975,
2654 14:44:52.917484
2655 14:44:52.920721 Write Rank0 MR14 =0x8
2656 14:44:52.929869
2657 14:44:52.929958 CH=1, VrefRange= 0, VrefLevel = 8
2658 14:44:52.936272 TX Bit0 (978~998) 21 988, Bit8 (968~987) 20 977,
2659 14:44:52.939486 TX Bit1 (976~997) 22 986, Bit9 (968~986) 19 977,
2660 14:44:52.946517 TX Bit2 (976~993) 18 984, Bit10 (969~987) 19 978,
2661 14:44:52.949797 TX Bit3 (973~991) 19 982, Bit11 (970~990) 21 980,
2662 14:44:52.953299 TX Bit4 (976~995) 20 985, Bit12 (969~990) 22 979,
2663 14:44:52.959976 TX Bit5 (977~998) 22 987, Bit13 (970~990) 21 980,
2664 14:44:52.963025 TX Bit6 (978~998) 21 988, Bit14 (969~988) 20 978,
2665 14:44:52.966587 TX Bit7 (976~993) 18 984, Bit15 (966~986) 21 976,
2666 14:44:52.966658
2667 14:44:52.969458 Write Rank0 MR14 =0xa
2668 14:44:52.978757
2669 14:44:52.982634 CH=1, VrefRange= 0, VrefLevel = 10
2670 14:44:52.985924 TX Bit0 (978~999) 22 988, Bit8 (968~988) 21 978,
2671 14:44:52.988808 TX Bit1 (976~998) 23 987, Bit9 (967~987) 21 977,
2672 14:44:52.995770 TX Bit2 (975~993) 19 984, Bit10 (969~988) 20 978,
2673 14:44:52.998542 TX Bit3 (972~992) 21 982, Bit11 (970~991) 22 980,
2674 14:44:53.002191 TX Bit4 (976~995) 20 985, Bit12 (969~991) 23 980,
2675 14:44:53.008720 TX Bit5 (977~998) 22 987, Bit13 (970~991) 22 980,
2676 14:44:53.011814 TX Bit6 (978~998) 21 988, Bit14 (970~989) 20 979,
2677 14:44:53.018460 TX Bit7 (976~994) 19 985, Bit15 (966~986) 21 976,
2678 14:44:53.018541
2679 14:44:53.018604 Write Rank0 MR14 =0xc
2680 14:44:53.028317
2681 14:44:53.031752 CH=1, VrefRange= 0, VrefLevel = 12
2682 14:44:53.035049 TX Bit0 (978~999) 22 988, Bit8 (968~988) 21 978,
2683 14:44:53.038261 TX Bit1 (976~998) 23 987, Bit9 (968~988) 21 978,
2684 14:44:53.044762 TX Bit2 (975~994) 20 984, Bit10 (968~989) 22 978,
2685 14:44:53.048355 TX Bit3 (972~992) 21 982, Bit11 (969~991) 23 980,
2686 14:44:53.051840 TX Bit4 (976~996) 21 986, Bit12 (969~991) 23 980,
2687 14:44:53.058606 TX Bit5 (977~999) 23 988, Bit13 (970~991) 22 980,
2688 14:44:53.061478 TX Bit6 (978~999) 22 988, Bit14 (969~990) 22 979,
2689 14:44:53.064809 TX Bit7 (976~994) 19 985, Bit15 (965~987) 23 976,
2690 14:44:53.064891
2691 14:44:53.068055 Write Rank0 MR14 =0xe
2692 14:44:53.077364
2693 14:44:53.081094 CH=1, VrefRange= 0, VrefLevel = 14
2694 14:44:53.083958 TX Bit0 (977~999) 23 988, Bit8 (967~988) 22 977,
2695 14:44:53.087660 TX Bit1 (976~998) 23 987, Bit9 (967~988) 22 977,
2696 14:44:53.093960 TX Bit2 (975~994) 20 984, Bit10 (968~990) 23 979,
2697 14:44:53.097614 TX Bit3 (972~992) 21 982, Bit11 (969~991) 23 980,
2698 14:44:53.100805 TX Bit4 (976~997) 22 986, Bit12 (969~991) 23 980,
2699 14:44:53.107485 TX Bit5 (977~999) 23 988, Bit13 (970~991) 22 980,
2700 14:44:53.110722 TX Bit6 (977~999) 23 988, Bit14 (969~990) 22 979,
2701 14:44:53.113849 TX Bit7 (976~995) 20 985, Bit15 (965~987) 23 976,
2702 14:44:53.113930
2703 14:44:53.117680 Write Rank0 MR14 =0x10
2704 14:44:53.126625
2705 14:44:53.130540 CH=1, VrefRange= 0, VrefLevel = 16
2706 14:44:53.133416 TX Bit0 (977~999) 23 988, Bit8 (967~990) 24 978,
2707 14:44:53.136809 TX Bit1 (976~998) 23 987, Bit9 (967~989) 23 978,
2708 14:44:53.143447 TX Bit2 (974~995) 22 984, Bit10 (968~990) 23 979,
2709 14:44:53.146758 TX Bit3 (971~993) 23 982, Bit11 (969~991) 23 980,
2710 14:44:53.150075 TX Bit4 (975~997) 23 986, Bit12 (969~991) 23 980,
2711 14:44:53.156822 TX Bit5 (976~999) 24 987, Bit13 (969~991) 23 980,
2712 14:44:53.160048 TX Bit6 (978~999) 22 988, Bit14 (969~991) 23 980,
2713 14:44:53.163324 TX Bit7 (975~996) 22 985, Bit15 (965~988) 24 976,
2714 14:44:53.166567
2715 14:44:53.166648 Write Rank0 MR14 =0x12
2716 14:44:53.176596
2717 14:44:53.179581 CH=1, VrefRange= 0, VrefLevel = 18
2718 14:44:53.182893 TX Bit0 (977~1000) 24 988, Bit8 (967~990) 24 978,
2719 14:44:53.186465 TX Bit1 (976~999) 24 987, Bit9 (967~990) 24 978,
2720 14:44:53.193002 TX Bit2 (974~996) 23 985, Bit10 (968~991) 24 979,
2721 14:44:53.196268 TX Bit3 (971~993) 23 982, Bit11 (969~992) 24 980,
2722 14:44:53.200073 TX Bit4 (975~998) 24 986, Bit12 (968~992) 25 980,
2723 14:44:53.206327 TX Bit5 (976~999) 24 987, Bit13 (969~991) 23 980,
2724 14:44:53.209679 TX Bit6 (977~999) 23 988, Bit14 (968~991) 24 979,
2725 14:44:53.212998 TX Bit7 (975~996) 22 985, Bit15 (964~989) 26 976,
2726 14:44:53.213080
2727 14:44:53.216895 Write Rank0 MR14 =0x14
2728 14:44:53.226234
2729 14:44:53.229171 CH=1, VrefRange= 0, VrefLevel = 20
2730 14:44:53.232764 TX Bit0 (977~1000) 24 988, Bit8 (966~991) 26 978,
2731 14:44:53.236127 TX Bit1 (975~999) 25 987, Bit9 (967~990) 24 978,
2732 14:44:53.242853 TX Bit2 (973~996) 24 984, Bit10 (967~991) 25 979,
2733 14:44:53.246070 TX Bit3 (970~994) 25 982, Bit11 (969~992) 24 980,
2734 14:44:53.249795 TX Bit4 (975~998) 24 986, Bit12 (968~992) 25 980,
2735 14:44:53.256446 TX Bit5 (976~1000) 25 988, Bit13 (969~991) 23 980,
2736 14:44:53.259715 TX Bit6 (977~1000) 24 988, Bit14 (968~991) 24 979,
2737 14:44:53.262820 TX Bit7 (975~997) 23 986, Bit15 (964~989) 26 976,
2738 14:44:53.262922
2739 14:44:53.265834 Write Rank0 MR14 =0x16
2740 14:44:53.275947
2741 14:44:53.279173 CH=1, VrefRange= 0, VrefLevel = 22
2742 14:44:53.282498 TX Bit0 (977~1001) 25 989, Bit8 (966~991) 26 978,
2743 14:44:53.285728 TX Bit1 (975~999) 25 987, Bit9 (966~990) 25 978,
2744 14:44:53.292620 TX Bit2 (973~997) 25 985, Bit10 (968~991) 24 979,
2745 14:44:53.295758 TX Bit3 (970~994) 25 982, Bit11 (969~992) 24 980,
2746 14:44:53.298951 TX Bit4 (974~998) 25 986, Bit12 (968~992) 25 980,
2747 14:44:53.305628 TX Bit5 (976~1000) 25 988, Bit13 (969~991) 23 980,
2748 14:44:53.308962 TX Bit6 (977~1000) 24 988, Bit14 (968~991) 24 979,
2749 14:44:53.315945 TX Bit7 (974~997) 24 985, Bit15 (964~988) 25 976,
2750 14:44:53.316027
2751 14:44:53.316091 Write Rank0 MR14 =0x18
2752 14:44:53.326212
2753 14:44:53.329100 CH=1, VrefRange= 0, VrefLevel = 24
2754 14:44:53.332740 TX Bit0 (977~1001) 25 989, Bit8 (966~991) 26 978,
2755 14:44:53.335879 TX Bit1 (975~999) 25 987, Bit9 (966~991) 26 978,
2756 14:44:53.342201 TX Bit2 (973~997) 25 985, Bit10 (967~991) 25 979,
2757 14:44:53.345797 TX Bit3 (970~994) 25 982, Bit11 (968~992) 25 980,
2758 14:44:53.349036 TX Bit4 (974~998) 25 986, Bit12 (968~992) 25 980,
2759 14:44:53.356199 TX Bit5 (976~1000) 25 988, Bit13 (969~991) 23 980,
2760 14:44:53.359331 TX Bit6 (977~1000) 24 988, Bit14 (967~991) 25 979,
2761 14:44:53.365687 TX Bit7 (974~997) 24 985, Bit15 (963~988) 26 975,
2762 14:44:53.365769
2763 14:44:53.365833 Write Rank0 MR14 =0x1a
2764 14:44:53.375820
2765 14:44:53.379572 CH=1, VrefRange= 0, VrefLevel = 26
2766 14:44:53.382971 TX Bit0 (977~1001) 25 989, Bit8 (966~991) 26 978,
2767 14:44:53.386061 TX Bit1 (975~999) 25 987, Bit9 (966~991) 26 978,
2768 14:44:53.392565 TX Bit2 (973~997) 25 985, Bit10 (967~991) 25 979,
2769 14:44:53.395644 TX Bit3 (970~994) 25 982, Bit11 (968~992) 25 980,
2770 14:44:53.399447 TX Bit4 (974~998) 25 986, Bit12 (968~992) 25 980,
2771 14:44:53.405774 TX Bit5 (976~1000) 25 988, Bit13 (969~991) 23 980,
2772 14:44:53.409559 TX Bit6 (977~1000) 24 988, Bit14 (967~991) 25 979,
2773 14:44:53.412703 TX Bit7 (974~997) 24 985, Bit15 (963~988) 26 975,
2774 14:44:53.415744
2775 14:44:53.415825 Write Rank0 MR14 =0x1c
2776 14:44:53.425491
2777 14:44:53.428897 CH=1, VrefRange= 0, VrefLevel = 28
2778 14:44:53.432664 TX Bit0 (977~1001) 25 989, Bit8 (966~991) 26 978,
2779 14:44:53.435559 TX Bit1 (975~999) 25 987, Bit9 (966~991) 26 978,
2780 14:44:53.442311 TX Bit2 (973~997) 25 985, Bit10 (967~991) 25 979,
2781 14:44:53.445550 TX Bit3 (970~994) 25 982, Bit11 (968~992) 25 980,
2782 14:44:53.449186 TX Bit4 (974~998) 25 986, Bit12 (968~992) 25 980,
2783 14:44:53.456228 TX Bit5 (976~1000) 25 988, Bit13 (969~991) 23 980,
2784 14:44:53.458925 TX Bit6 (977~1000) 24 988, Bit14 (967~991) 25 979,
2785 14:44:53.465779 TX Bit7 (974~997) 24 985, Bit15 (963~988) 26 975,
2786 14:44:53.465863
2787 14:44:53.465929 Write Rank0 MR14 =0x1e
2788 14:44:53.475437
2789 14:44:53.478492 CH=1, VrefRange= 0, VrefLevel = 30
2790 14:44:53.482051 TX Bit0 (977~1001) 25 989, Bit8 (966~991) 26 978,
2791 14:44:53.485489 TX Bit1 (975~999) 25 987, Bit9 (966~991) 26 978,
2792 14:44:53.492053 TX Bit2 (973~997) 25 985, Bit10 (967~991) 25 979,
2793 14:44:53.495460 TX Bit3 (970~994) 25 982, Bit11 (968~992) 25 980,
2794 14:44:53.498758 TX Bit4 (974~998) 25 986, Bit12 (968~992) 25 980,
2795 14:44:53.505509 TX Bit5 (976~1000) 25 988, Bit13 (969~991) 23 980,
2796 14:44:53.508483 TX Bit6 (977~1000) 24 988, Bit14 (967~991) 25 979,
2797 14:44:53.512227 TX Bit7 (974~997) 24 985, Bit15 (963~988) 26 975,
2798 14:44:53.515309
2799 14:44:53.515391
2800 14:44:53.518479 TX Vref found, early break! 378< 379
2801 14:44:53.522359 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =762/100 ps
2802 14:44:53.525566 u1DelayCellOfst[0]=8 cells (7 PI)
2803 14:44:53.528902 u1DelayCellOfst[1]=6 cells (5 PI)
2804 14:44:53.532156 u1DelayCellOfst[2]=3 cells (3 PI)
2805 14:44:53.535638 u1DelayCellOfst[3]=0 cells (0 PI)
2806 14:44:53.535720 u1DelayCellOfst[4]=5 cells (4 PI)
2807 14:44:53.538773 u1DelayCellOfst[5]=7 cells (6 PI)
2808 14:44:53.542059 u1DelayCellOfst[6]=7 cells (6 PI)
2809 14:44:53.545720 u1DelayCellOfst[7]=3 cells (3 PI)
2810 14:44:53.549096 Byte0, DQ PI dly=982, DQM PI dly= 985
2811 14:44:53.555933 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22)
2812 14:44:53.556017
2813 14:44:53.558818 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22)
2814 14:44:53.558926
2815 14:44:53.562264 u1DelayCellOfst[8]=3 cells (3 PI)
2816 14:44:53.565827 u1DelayCellOfst[9]=3 cells (3 PI)
2817 14:44:53.568972 u1DelayCellOfst[10]=5 cells (4 PI)
2818 14:44:53.572396 u1DelayCellOfst[11]=6 cells (5 PI)
2819 14:44:53.572478 u1DelayCellOfst[12]=6 cells (5 PI)
2820 14:44:53.575525 u1DelayCellOfst[13]=6 cells (5 PI)
2821 14:44:53.579071 u1DelayCellOfst[14]=5 cells (4 PI)
2822 14:44:53.582455 u1DelayCellOfst[15]=0 cells (0 PI)
2823 14:44:53.585679 Byte1, DQ PI dly=975, DQM PI dly= 977
2824 14:44:53.592343 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 15)
2825 14:44:53.592426
2826 14:44:53.595472 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 15)
2827 14:44:53.595554
2828 14:44:53.598965 Write Rank0 MR14 =0x18
2829 14:44:53.599047
2830 14:44:53.599111 Final TX Range 0 Vref 24
2831 14:44:53.599173
2832 14:44:53.605394 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2833 14:44:53.605476
2834 14:44:53.612361 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2835 14:44:53.618953 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2836 14:44:53.628965 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2837 14:44:53.629048 Write Rank0 MR3 =0xb0
2838 14:44:53.632161 DramC Write-DBI on
2839 14:44:53.632242 ==
2840 14:44:53.635408 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2841 14:44:53.639170 fsp= 1, odt_onoff= 1, Byte mode= 0
2842 14:44:53.639252 ==
2843 14:44:53.645853 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2844 14:44:53.645935
2845 14:44:53.645999 Begin, DQ Scan Range 697~761
2846 14:44:53.646059
2847 14:44:53.646116
2848 14:44:53.648736 TX Vref Scan disable
2849 14:44:53.652308 697 |2 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2850 14:44:53.655437 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2851 14:44:53.658552 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2852 14:44:53.661897 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2853 14:44:53.665289 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2854 14:44:53.668854 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2855 14:44:53.672271 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2856 14:44:53.678938 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2857 14:44:53.681968 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2858 14:44:53.685248 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2859 14:44:53.689116 707 |2 6 3|[0] xxxxxxxx oooooooo [MSB]
2860 14:44:53.691898 708 |2 6 4|[0] xxxxxxxx oooooooo [MSB]
2861 14:44:53.695365 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB]
2862 14:44:53.698986 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
2863 14:44:53.702134 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
2864 14:44:53.705535 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2865 14:44:53.708661 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2866 14:44:53.712148 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2867 14:44:53.715960 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2868 14:44:53.718778 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2869 14:44:53.726841 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
2870 14:44:53.729984 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2871 14:44:53.733284 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2872 14:44:53.736819 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2873 14:44:53.740133 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2874 14:44:53.743258 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2875 14:44:53.746665 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2876 14:44:53.749950 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2877 14:44:53.753047 744 |2 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
2878 14:44:53.757078 Byte0, DQ PI dly=730, DQM PI dly= 730
2879 14:44:53.759974 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 26)
2880 14:44:53.760057
2881 14:44:53.767142 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 26)
2882 14:44:53.767225
2883 14:44:53.770305 Byte1, DQ PI dly=721, DQM PI dly= 721
2884 14:44:53.773173 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 17)
2885 14:44:53.773277
2886 14:44:53.776830 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 17)
2887 14:44:53.776912
2888 14:44:53.783349 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2889 14:44:53.790104 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2890 14:44:53.800249 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2891 14:44:53.800331 Write Rank0 MR3 =0x30
2892 14:44:53.803370 DramC Write-DBI off
2893 14:44:53.803451
2894 14:44:53.803515 [DATLAT]
2895 14:44:53.806536 Freq=1600, CH1 RK0, use_rxtx_scan=0
2896 14:44:53.806618
2897 14:44:53.809914 DATLAT Default: 0xf
2898 14:44:53.809995 7, 0xFFFF, sum=0
2899 14:44:53.813047 8, 0xFFFF, sum=0
2900 14:44:53.813130 9, 0xFFFF, sum=0
2901 14:44:53.816441 10, 0xFFFF, sum=0
2902 14:44:53.816524 11, 0xFFFF, sum=0
2903 14:44:53.816589 12, 0xFFFF, sum=0
2904 14:44:53.819934 13, 0xFFFF, sum=0
2905 14:44:53.820016 14, 0x0, sum=1
2906 14:44:53.823253 15, 0x0, sum=2
2907 14:44:53.823336 16, 0x0, sum=3
2908 14:44:53.826837 17, 0x0, sum=4
2909 14:44:53.830204 pattern=2 first_step=14 total pass=5 best_step=16
2910 14:44:53.830285 ==
2911 14:44:53.836454 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2912 14:44:53.836537 fsp= 1, odt_onoff= 1, Byte mode= 0
2913 14:44:53.840221 ==
2914 14:44:53.843531 Start DQ dly to find pass range UseTestEngine =1
2915 14:44:53.846754 x-axis: bit #, y-axis: DQ dly (-127~63)
2916 14:44:53.846836 RX Vref Scan = 1
2917 14:44:53.962743
2918 14:44:53.962855 RX Vref found, early break!
2919 14:44:53.962921
2920 14:44:53.969519 Final RX Vref 13, apply to both rank0 and 1
2921 14:44:53.969602 ==
2922 14:44:53.972752 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2923 14:44:53.976085 fsp= 1, odt_onoff= 1, Byte mode= 0
2924 14:44:53.976167 ==
2925 14:44:53.976231 DQS Delay:
2926 14:44:53.979395 DQS0 = 0, DQS1 = 0
2927 14:44:53.979476 DQM Delay:
2928 14:44:53.982938 DQM0 = 20, DQM1 = 18
2929 14:44:53.983019 DQ Delay:
2930 14:44:53.986495 DQ0 =24, DQ1 =22, DQ2 =16, DQ3 =15
2931 14:44:53.989492 DQ4 =19, DQ5 =24, DQ6 =25, DQ7 =19
2932 14:44:53.992528 DQ8 =19, DQ9 =19, DQ10 =18, DQ11 =19
2933 14:44:53.996123 DQ12 =20, DQ13 =19, DQ14 =19, DQ15 =17
2934 14:44:53.996204
2935 14:44:53.996268
2936 14:44:53.996327
2937 14:44:53.999413 [DramC_TX_OE_Calibration] TA2
2938 14:44:54.002832 Original DQ_B0 (3 6) =30, OEN = 27
2939 14:44:54.005838 Original DQ_B1 (3 6) =30, OEN = 27
2940 14:44:54.009146 23, 0x0, End_B0=23 End_B1=23
2941 14:44:54.009229 24, 0x0, End_B0=24 End_B1=24
2942 14:44:54.012547 25, 0x0, End_B0=25 End_B1=25
2943 14:44:54.015790 26, 0x0, End_B0=26 End_B1=26
2944 14:44:54.018973 27, 0x0, End_B0=27 End_B1=27
2945 14:44:54.022349 28, 0x0, End_B0=28 End_B1=28
2946 14:44:54.022431 29, 0x0, End_B0=29 End_B1=29
2947 14:44:54.025575 30, 0x0, End_B0=30 End_B1=30
2948 14:44:54.029035 31, 0xFFFF, End_B0=30 End_B1=30
2949 14:44:54.035518 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2950 14:44:54.038890 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2951 14:44:54.038974
2952 14:44:54.039063
2953 14:44:54.042686 Write Rank0 MR23 =0x3f
2954 14:44:54.042767 [DQSOSC]
2955 14:44:54.052411 [DQSOSCAuto] RK0, (LSB)MR18= 0xbe, (MSB)MR19= 0x3, tDQSOscB0 = 328 ps tDQSOscB1 = 0 ps
2956 14:44:54.056067 CH1_RK0: MR19=0x3, MR18=0xBE, DQSOSC=328, MR23=63, INC=22, DEC=34
2957 14:44:54.058752 Write Rank0 MR23 =0x3f
2958 14:44:54.058833 [DQSOSC]
2959 14:44:54.068850 [DQSOSCAuto] RK0, (LSB)MR18= 0xbc, (MSB)MR19= 0x3, tDQSOscB0 = 329 ps tDQSOscB1 = 0 ps
2960 14:44:54.068933 CH1 RK0: MR19=3, MR18=BC
2961 14:44:54.072489 [RankSwap] Rank num 2, (Multi 1), Rank 1
2962 14:44:54.075698 Write Rank0 MR2 =0xad
2963 14:44:54.075779 [Write Leveling]
2964 14:44:54.079012 delay byte0 byte1 byte2 byte3
2965 14:44:54.079093
2966 14:44:54.082293 10 0 0
2967 14:44:54.082376 11 0 0
2968 14:44:54.085374 12 0 0
2969 14:44:54.085457 13 0 0
2970 14:44:54.085522 14 0 0
2971 14:44:54.088990 15 0 0
2972 14:44:54.089073 16 0 0
2973 14:44:54.092406 17 0 0
2974 14:44:54.092488 18 0 0
2975 14:44:54.092554 19 0 0
2976 14:44:54.095585 20 0 0
2977 14:44:54.095667 21 0 0
2978 14:44:54.098765 22 0 0
2979 14:44:54.098848 23 0 0
2980 14:44:54.098914 24 0 0
2981 14:44:54.102208 25 0 0
2982 14:44:54.102290 26 0 0
2983 14:44:54.105342 27 0 0
2984 14:44:54.105423 28 0 0
2985 14:44:54.108716 29 0 0
2986 14:44:54.108799 30 0 0
2987 14:44:54.108863 31 0 0
2988 14:44:54.112221 32 0 ff
2989 14:44:54.112304 33 0 ff
2990 14:44:54.115642 34 0 ff
2991 14:44:54.115725 35 0 ff
2992 14:44:54.118732 36 ff ff
2993 14:44:54.118814 37 ff ff
2994 14:44:54.122044 38 ff ff
2995 14:44:54.122126 39 ff ff
2996 14:44:54.122191 40 ff ff
2997 14:44:54.125355 41 ff ff
2998 14:44:54.125437 42 ff ff
2999 14:44:54.132127 pass bytecount = 0xff (0xff: all bytes pass)
3000 14:44:54.132210
3001 14:44:54.132274 DQS0 dly: 36
3002 14:44:54.132335 DQS1 dly: 32
3003 14:44:54.135687 Write Rank0 MR2 =0x2d
3004 14:44:54.139088 [RankSwap] Rank num 2, (Multi 1), Rank 0
3005 14:44:54.142432 Write Rank1 MR1 =0xd6
3006 14:44:54.142514 [Gating]
3007 14:44:54.142579 ==
3008 14:44:54.145638 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3009 14:44:54.148751 fsp= 1, odt_onoff= 1, Byte mode= 0
3010 14:44:54.152045 ==
3011 14:44:54.155323 3 1 0 |1b1a 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
3012 14:44:54.159010 3 1 4 |3130 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
3013 14:44:54.162234 3 1 8 |2c2c 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
3014 14:44:54.168796 3 1 12 |2f2f 3534 |(0 0)(11 11) |(0 1)(0 1)| 0
3015 14:44:54.172002 3 1 16 |2e2d 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
3016 14:44:54.175569 3 1 20 |1e1d 3534 |(1 1)(11 11) |(1 0)(0 1)| 0
3017 14:44:54.182174 3 1 24 |2e2d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3018 14:44:54.185613 3 1 28 |606 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3019 14:44:54.189085 3 2 0 |3635 201 |(11 11)(11 11) |(0 0)(1 1)| 0
3020 14:44:54.192235 3 2 4 |1919 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
3021 14:44:54.199044 3 2 8 |1f1e 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3022 14:44:54.202570 3 2 12 |3636 3d3d |(0 0)(11 11) |(0 0)(1 1)| 0
3023 14:44:54.205646 3 2 16 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3024 14:44:54.212098 3 2 20 |201 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
3025 14:44:54.215564 3 2 24 |1111 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3026 14:44:54.218773 3 2 28 |b0b 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3027 14:44:54.222526 3 3 0 |1413 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3028 14:44:54.228892 [Byte 0] Lead/lag falling Transition (3, 3, 0)
3029 14:44:54.232253 3 3 4 |3534 909 |(11 11)(11 11) |(0 1)(1 1)| 0
3030 14:44:54.235804 3 3 8 |3534 2928 |(11 11)(11 11) |(0 1)(1 1)| 0
3031 14:44:54.242170 [Byte 1] Lead/lag falling Transition (3, 3, 8)
3032 14:44:54.245302 3 3 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3033 14:44:54.249230 3 3 16 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3034 14:44:54.255277 3 3 20 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3035 14:44:54.258701 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3036 14:44:54.261971 3 3 28 |1c1b 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3037 14:44:54.265322 3 4 0 |3d3d a0a |(11 11)(11 11) |(1 1)(1 1)| 0
3038 14:44:54.272322 3 4 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3039 14:44:54.275454 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3040 14:44:54.279061 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3041 14:44:54.285311 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3042 14:44:54.288864 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3043 14:44:54.292341 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3044 14:44:54.298564 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3045 14:44:54.302001 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3046 14:44:54.305216 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3047 14:44:54.308731 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3048 14:44:54.315748 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3049 14:44:54.318828 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3050 14:44:54.322247 [Byte 0] Lead/lag falling Transition (3, 5, 16)
3051 14:44:54.329099 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3052 14:44:54.332511 [Byte 0] Lead/lag Transition tap number (2)
3053 14:44:54.335731 [Byte 1] Lead/lag falling Transition (3, 5, 20)
3054 14:44:54.338746 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3055 14:44:54.345543 [Byte 1] Lead/lag Transition tap number (2)
3056 14:44:54.348869 3 5 28 |403 3e3d |(11 11)(11 11) |(0 0)(0 0)| 0
3057 14:44:54.352352 3 6 0 |4646 c0b |(0 0)(11 11) |(0 0)(0 0)| 0
3058 14:44:54.355527 [Byte 0]First pass (3, 6, 0)
3059 14:44:54.358743 3 6 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3060 14:44:54.362350 [Byte 1]First pass (3, 6, 4)
3061 14:44:54.365482 3 6 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3062 14:44:54.368848 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3063 14:44:54.372061 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3064 14:44:54.378976 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3065 14:44:54.382282 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3066 14:44:54.385496 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3067 14:44:54.388664 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3068 14:44:54.392226 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3069 14:44:54.398931 All bytes gating window > 1UI, Early break!
3070 14:44:54.399013
3071 14:44:54.402254 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 20)
3072 14:44:54.402335
3073 14:44:54.405549 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 24)
3074 14:44:54.405630
3075 14:44:54.405694
3076 14:44:54.405754
3077 14:44:54.408973 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 20)
3078 14:44:54.409054
3079 14:44:54.412384 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 24)
3080 14:44:54.416006
3081 14:44:54.416085
3082 14:44:54.416148 Write Rank1 MR1 =0x56
3083 14:44:54.416207
3084 14:44:54.419028 best RODT dly(2T, 0.5T) = (2, 2)
3085 14:44:54.419113
3086 14:44:54.422403 best RODT dly(2T, 0.5T) = (2, 2)
3087 14:44:54.422490 ==
3088 14:44:54.428737 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3089 14:44:54.428818 fsp= 1, odt_onoff= 1, Byte mode= 0
3090 14:44:54.432237 ==
3091 14:44:54.435934 Start DQ dly to find pass range UseTestEngine =0
3092 14:44:54.439135 x-axis: bit #, y-axis: DQ dly (-127~63)
3093 14:44:54.439219 RX Vref Scan = 0
3094 14:44:54.442439 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3095 14:44:54.445779 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3096 14:44:54.449316 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3097 14:44:54.452402 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3098 14:44:54.455626 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3099 14:44:54.459070 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3100 14:44:54.462380 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3101 14:44:54.462463 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3102 14:44:54.465786 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3103 14:44:54.469078 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3104 14:44:54.472455 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3105 14:44:54.476054 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3106 14:44:54.479237 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3107 14:44:54.482694 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3108 14:44:54.485865 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3109 14:44:54.485951 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3110 14:44:54.489101 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3111 14:44:54.492353 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3112 14:44:54.495644 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3113 14:44:54.499004 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3114 14:44:54.502697 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3115 14:44:54.505841 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3116 14:44:54.505923 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3117 14:44:54.509031 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3118 14:44:54.512353 -2, [0] xxxoxxxx xxxxxxxx [MSB]
3119 14:44:54.515976 -1, [0] xxxoxxxx xxxxxxxo [MSB]
3120 14:44:54.519166 0, [0] xxooxxxo xxxxxxxo [MSB]
3121 14:44:54.522624 1, [0] xxoooxxo xxxxxxxo [MSB]
3122 14:44:54.522707 2, [0] xxoooxxo oooxxxxo [MSB]
3123 14:44:54.525785 3, [0] xxoooxxo ooooxooo [MSB]
3124 14:44:54.529225 4, [0] xxoooxxo oooooooo [MSB]
3125 14:44:54.532490 5, [0] xoooooxo oooooooo [MSB]
3126 14:44:54.536056 6, [0] xoooooxo oooooooo [MSB]
3127 14:44:54.539419 34, [0] oooxoooo oooooooo [MSB]
3128 14:44:54.539501 35, [0] ooxxoooo ooooooox [MSB]
3129 14:44:54.542360 36, [0] ooxxoooo ooooooox [MSB]
3130 14:44:54.546063 37, [0] ooxxxooo ooxoooox [MSB]
3131 14:44:54.549301 38, [0] ooxxxooo xoxoooox [MSB]
3132 14:44:54.552362 39, [0] ooxxxoox xxxxoxxx [MSB]
3133 14:44:54.556152 40, [0] ooxxxoox xxxxoxxx [MSB]
3134 14:44:54.559501 41, [0] ooxxxoox xxxxxxxx [MSB]
3135 14:44:54.559583 42, [0] xxxxxxxx xxxxxxxx [MSB]
3136 14:44:54.565618 iDelay=42, Bit 0, Center 24 (7 ~ 41) 35
3137 14:44:54.569388 iDelay=42, Bit 1, Center 23 (5 ~ 41) 37
3138 14:44:54.572576 iDelay=42, Bit 2, Center 17 (0 ~ 34) 35
3139 14:44:54.575816 iDelay=42, Bit 3, Center 15 (-2 ~ 33) 36
3140 14:44:54.579249 iDelay=42, Bit 4, Center 18 (1 ~ 36) 36
3141 14:44:54.582869 iDelay=42, Bit 5, Center 23 (5 ~ 41) 37
3142 14:44:54.586098 iDelay=42, Bit 6, Center 24 (7 ~ 41) 35
3143 14:44:54.589253 iDelay=42, Bit 7, Center 19 (0 ~ 38) 39
3144 14:44:54.592329 iDelay=42, Bit 8, Center 19 (2 ~ 37) 36
3145 14:44:54.595724 iDelay=42, Bit 9, Center 20 (2 ~ 38) 37
3146 14:44:54.599120 iDelay=42, Bit 10, Center 19 (2 ~ 36) 35
3147 14:44:54.602410 iDelay=42, Bit 11, Center 20 (3 ~ 38) 36
3148 14:44:54.605697 iDelay=42, Bit 12, Center 22 (4 ~ 40) 37
3149 14:44:54.609342 iDelay=42, Bit 13, Center 20 (3 ~ 38) 36
3150 14:44:54.612384 iDelay=42, Bit 14, Center 20 (3 ~ 38) 36
3151 14:44:54.619689 iDelay=42, Bit 15, Center 16 (-1 ~ 34) 36
3152 14:44:54.619771 ==
3153 14:44:54.622512 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3154 14:44:54.625996 fsp= 1, odt_onoff= 1, Byte mode= 0
3155 14:44:54.626077 ==
3156 14:44:54.629212 DQS Delay:
3157 14:44:54.629333 DQS0 = 0, DQS1 = 0
3158 14:44:54.629397 DQM Delay:
3159 14:44:54.632340 DQM0 = 20, DQM1 = 19
3160 14:44:54.632420 DQ Delay:
3161 14:44:54.635852 DQ0 =24, DQ1 =23, DQ2 =17, DQ3 =15
3162 14:44:54.639382 DQ4 =18, DQ5 =23, DQ6 =24, DQ7 =19
3163 14:44:54.642290 DQ8 =19, DQ9 =20, DQ10 =19, DQ11 =20
3164 14:44:54.646139 DQ12 =22, DQ13 =20, DQ14 =20, DQ15 =16
3165 14:44:54.646219
3166 14:44:54.646283
3167 14:44:54.649206 DramC Write-DBI off
3168 14:44:54.649321 ==
3169 14:44:54.653199 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3170 14:44:54.655551 fsp= 1, odt_onoff= 1, Byte mode= 0
3171 14:44:54.655632 ==
3172 14:44:54.662321 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3173 14:44:54.662403
3174 14:44:54.665498 Begin, DQ Scan Range 928~1184
3175 14:44:54.665579
3176 14:44:54.665641
3177 14:44:54.665700 TX Vref Scan disable
3178 14:44:54.668875 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3179 14:44:54.672403 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3180 14:44:54.675554 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3181 14:44:54.679387 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3182 14:44:54.685717 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3183 14:44:54.689060 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3184 14:44:54.692280 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3185 14:44:54.695763 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3186 14:44:54.698713 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3187 14:44:54.702363 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3188 14:44:54.705487 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3189 14:44:54.708896 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3190 14:44:54.712384 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3191 14:44:54.715909 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3192 14:44:54.718941 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3193 14:44:54.722177 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3194 14:44:54.725452 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3195 14:44:54.729197 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3196 14:44:54.732139 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3197 14:44:54.735536 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3198 14:44:54.742238 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3199 14:44:54.745597 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3200 14:44:54.749099 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3201 14:44:54.752906 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3202 14:44:54.755600 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3203 14:44:54.758886 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3204 14:44:54.762180 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3205 14:44:54.765418 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3206 14:44:54.769116 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3207 14:44:54.772152 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3208 14:44:54.775504 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3209 14:44:54.778724 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3210 14:44:54.782160 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3211 14:44:54.785485 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3212 14:44:54.788948 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3213 14:44:54.791969 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3214 14:44:54.795734 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3215 14:44:54.798650 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3216 14:44:54.802079 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3217 14:44:54.805438 967 |3 6 7|[0] xxxxxxxx xxxxxxxo [MSB]
3218 14:44:54.808739 968 |3 6 8|[0] xxxxxxxx xxxxxxxo [MSB]
3219 14:44:54.815444 969 |3 6 9|[0] xxxxxxxx oooxxxxo [MSB]
3220 14:44:54.818782 970 |3 6 10|[0] xxxxxxxx oooooxoo [MSB]
3221 14:44:54.822472 971 |3 6 11|[0] xxxxxxxx oooooooo [MSB]
3222 14:44:54.825360 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB]
3223 14:44:54.829003 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
3224 14:44:54.831808 974 |3 6 14|[0] xxxoxxxx oooooooo [MSB]
3225 14:44:54.835290 975 |3 6 15|[0] xxoooxxx oooooooo [MSB]
3226 14:44:54.838840 976 |3 6 16|[0] xxoooxxo oooooooo [MSB]
3227 14:44:54.842139 977 |3 6 17|[0] xooooooo oooooooo [MSB]
3228 14:44:54.849127 989 |3 6 29|[0] oooooooo ooooooox [MSB]
3229 14:44:54.852305 990 |3 6 30|[0] oooooooo ooooooox [MSB]
3230 14:44:54.855899 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
3231 14:44:54.858901 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
3232 14:44:54.862275 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
3233 14:44:54.865729 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
3234 14:44:54.868906 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB]
3235 14:44:54.872685 996 |3 6 36|[0] oooxoooo xxxxxxxx [MSB]
3236 14:44:54.875822 997 |3 6 37|[0] ooxxoooo xxxxxxxx [MSB]
3237 14:44:54.878920 998 |3 6 38|[0] ooxxooox xxxxxxxx [MSB]
3238 14:44:54.882217 999 |3 6 39|[0] ooxxxoox xxxxxxxx [MSB]
3239 14:44:54.885817 1000 |3 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
3240 14:44:54.888936 Byte0, DQ PI dly=986, DQM PI dly= 986
3241 14:44:54.895796 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
3242 14:44:54.895878
3243 14:44:54.898889 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
3244 14:44:54.898971
3245 14:44:54.902260 Byte1, DQ PI dly=978, DQM PI dly= 978
3246 14:44:54.905819 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
3247 14:44:54.905907
3248 14:44:54.912327 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
3249 14:44:54.912416
3250 14:44:54.912485 ==
3251 14:44:54.915693 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3252 14:44:54.918782 fsp= 1, odt_onoff= 1, Byte mode= 0
3253 14:44:54.918877 ==
3254 14:44:54.925814 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3255 14:44:54.925925
3256 14:44:54.926012 Begin, DQ Scan Range 954~1018
3257 14:44:54.929107 Write Rank1 MR14 =0x0
3258 14:44:54.937912
3259 14:44:54.938048 CH=1, VrefRange= 0, VrefLevel = 0
3260 14:44:54.944640 TX Bit0 (980~998) 19 989, Bit8 (971~986) 16 978,
3261 14:44:54.947768 TX Bit1 (979~997) 19 988, Bit9 (970~986) 17 978,
3262 14:44:54.954527 TX Bit2 (977~991) 15 984, Bit10 (972~986) 15 979,
3263 14:44:54.957747 TX Bit3 (975~991) 17 983, Bit11 (974~990) 17 982,
3264 14:44:54.961236 TX Bit4 (977~993) 17 985, Bit12 (972~988) 17 980,
3265 14:44:54.967579 TX Bit5 (978~997) 20 987, Bit13 (975~987) 13 981,
3266 14:44:54.971335 TX Bit6 (979~998) 20 988, Bit14 (973~988) 16 980,
3267 14:44:54.974821 TX Bit7 (978~992) 15 985, Bit15 (968~985) 18 976,
3268 14:44:54.975243
3269 14:44:54.977617 Write Rank1 MR14 =0x2
3270 14:44:54.987419
3271 14:44:54.987836 CH=1, VrefRange= 0, VrefLevel = 2
3272 14:44:54.993837 TX Bit0 (979~999) 21 989, Bit8 (971~987) 17 979,
3273 14:44:54.997324 TX Bit1 (978~997) 20 987, Bit9 (970~986) 17 978,
3274 14:44:55.000849 TX Bit2 (976~992) 17 984, Bit10 (971~986) 16 978,
3275 14:44:55.007565 TX Bit3 (975~991) 17 983, Bit11 (973~991) 19 982,
3276 14:44:55.010850 TX Bit4 (977~994) 18 985, Bit12 (972~988) 17 980,
3277 14:44:55.017321 TX Bit5 (979~998) 20 988, Bit13 (974~987) 14 980,
3278 14:44:55.020458 TX Bit6 (979~998) 20 988, Bit14 (972~988) 17 980,
3279 14:44:55.023548 TX Bit7 (978~993) 16 985, Bit15 (968~985) 18 976,
3280 14:44:55.023972
3281 14:44:55.027204 Write Rank1 MR14 =0x4
3282 14:44:55.036435
3283 14:44:55.036852 CH=1, VrefRange= 0, VrefLevel = 4
3284 14:44:55.043083 TX Bit0 (979~999) 21 989, Bit8 (970~987) 18 978,
3285 14:44:55.046201 TX Bit1 (978~997) 20 987, Bit9 (970~987) 18 978,
3286 14:44:55.052875 TX Bit2 (976~992) 17 984, Bit10 (971~987) 17 979,
3287 14:44:55.056971 TX Bit3 (975~992) 18 983, Bit11 (973~991) 19 982,
3288 14:44:55.059447 TX Bit4 (976~994) 19 985, Bit12 (972~989) 18 980,
3289 14:44:55.066011 TX Bit5 (978~998) 21 988, Bit13 (974~987) 14 980,
3290 14:44:55.069573 TX Bit6 (978~999) 22 988, Bit14 (972~988) 17 980,
3291 14:44:55.073007 TX Bit7 (977~993) 17 985, Bit15 (968~985) 18 976,
3292 14:44:55.073545
3293 14:44:55.075801 Write Rank1 MR14 =0x6
3294 14:44:55.085110
3295 14:44:55.085644 CH=1, VrefRange= 0, VrefLevel = 6
3296 14:44:55.091865 TX Bit0 (979~999) 21 989, Bit8 (970~988) 19 979,
3297 14:44:55.095537 TX Bit1 (978~997) 20 987, Bit9 (970~988) 19 979,
3298 14:44:55.101905 TX Bit2 (976~993) 18 984, Bit10 (971~988) 18 979,
3299 14:44:55.105110 TX Bit3 (975~992) 18 983, Bit11 (973~991) 19 982,
3300 14:44:55.108527 TX Bit4 (976~995) 20 985, Bit12 (971~990) 20 980,
3301 14:44:55.114779 TX Bit5 (978~998) 21 988, Bit13 (973~988) 16 980,
3302 14:44:55.118520 TX Bit6 (978~999) 22 988, Bit14 (972~989) 18 980,
3303 14:44:55.121614 TX Bit7 (977~993) 17 985, Bit15 (968~985) 18 976,
3304 14:44:55.121689
3305 14:44:55.124715 Write Rank1 MR14 =0x8
3306 14:44:55.134133
3307 14:44:55.134214 CH=1, VrefRange= 0, VrefLevel = 8
3308 14:44:55.140927 TX Bit0 (978~999) 22 988, Bit8 (970~989) 20 979,
3309 14:44:55.144108 TX Bit1 (978~998) 21 988, Bit9 (969~988) 20 978,
3310 14:44:55.150739 TX Bit2 (976~993) 18 984, Bit10 (970~989) 20 979,
3311 14:44:55.154014 TX Bit3 (974~992) 19 983, Bit11 (972~992) 21 982,
3312 14:44:55.157360 TX Bit4 (976~996) 21 986, Bit12 (971~991) 21 981,
3313 14:44:55.163855 TX Bit5 (978~998) 21 988, Bit13 (973~989) 17 981,
3314 14:44:55.167462 TX Bit6 (978~999) 22 988, Bit14 (970~990) 21 980,
3315 14:44:55.171062 TX Bit7 (977~994) 18 985, Bit15 (967~986) 20 976,
3316 14:44:55.171145
3317 14:44:55.174361 Write Rank1 MR14 =0xa
3318 14:44:55.183657
3319 14:44:55.186969 CH=1, VrefRange= 0, VrefLevel = 10
3320 14:44:55.190286 TX Bit0 (978~1000) 23 989, Bit8 (970~990) 21 980,
3321 14:44:55.193581 TX Bit1 (978~999) 22 988, Bit9 (969~989) 21 979,
3322 14:44:55.199975 TX Bit2 (975~994) 20 984, Bit10 (970~989) 20 979,
3323 14:44:55.203672 TX Bit3 (974~993) 20 983, Bit11 (972~992) 21 982,
3324 14:44:55.207073 TX Bit4 (976~996) 21 986, Bit12 (971~991) 21 981,
3325 14:44:55.213903 TX Bit5 (978~999) 22 988, Bit13 (972~990) 19 981,
3326 14:44:55.216673 TX Bit6 (978~999) 22 988, Bit14 (971~990) 20 980,
3327 14:44:55.219996 TX Bit7 (977~995) 19 986, Bit15 (967~986) 20 976,
3328 14:44:55.220078
3329 14:44:55.223276 Write Rank1 MR14 =0xc
3330 14:44:55.233237
3331 14:44:55.233326 CH=1, VrefRange= 0, VrefLevel = 12
3332 14:44:55.239906 TX Bit0 (978~1000) 23 989, Bit8 (969~990) 22 979,
3333 14:44:55.243061 TX Bit1 (978~999) 22 988, Bit9 (969~989) 21 979,
3334 14:44:55.249540 TX Bit2 (975~994) 20 984, Bit10 (971~990) 20 980,
3335 14:44:55.252797 TX Bit3 (973~993) 21 983, Bit11 (971~992) 22 981,
3336 14:44:55.256561 TX Bit4 (976~997) 22 986, Bit12 (970~991) 22 980,
3337 14:44:55.263097 TX Bit5 (977~999) 23 988, Bit13 (972~991) 20 981,
3338 14:44:55.266350 TX Bit6 (978~999) 22 988, Bit14 (970~991) 22 980,
3339 14:44:55.269872 TX Bit7 (977~996) 20 986, Bit15 (967~987) 21 977,
3340 14:44:55.269954
3341 14:44:55.273048 Write Rank1 MR14 =0xe
3342 14:44:55.282244
3343 14:44:55.285510 CH=1, VrefRange= 0, VrefLevel = 14
3344 14:44:55.288774 TX Bit0 (978~1000) 23 989, Bit8 (969~991) 23 980,
3345 14:44:55.292228 TX Bit1 (978~999) 22 988, Bit9 (969~990) 22 979,
3346 14:44:55.299334 TX Bit2 (975~995) 21 985, Bit10 (969~991) 23 980,
3347 14:44:55.302178 TX Bit3 (973~994) 22 983, Bit11 (970~992) 23 981,
3348 14:44:55.305670 TX Bit4 (976~997) 22 986, Bit12 (970~991) 22 980,
3349 14:44:55.312347 TX Bit5 (977~999) 23 988, Bit13 (971~991) 21 981,
3350 14:44:55.315716 TX Bit6 (977~1000) 24 988, Bit14 (970~991) 22 980,
3351 14:44:55.318981 TX Bit7 (976~996) 21 986, Bit15 (967~987) 21 977,
3352 14:44:55.322103
3353 14:44:55.322183 Write Rank1 MR14 =0x10
3354 14:44:55.332510
3355 14:44:55.335450 CH=1, VrefRange= 0, VrefLevel = 16
3356 14:44:55.338699 TX Bit0 (978~1001) 24 989, Bit8 (969~991) 23 980,
3357 14:44:55.342231 TX Bit1 (977~999) 23 988, Bit9 (969~990) 22 979,
3358 14:44:55.348687 TX Bit2 (974~996) 23 985, Bit10 (969~991) 23 980,
3359 14:44:55.352555 TX Bit3 (972~995) 24 983, Bit11 (970~993) 24 981,
3360 14:44:55.355423 TX Bit4 (976~997) 22 986, Bit12 (970~992) 23 981,
3361 14:44:55.361989 TX Bit5 (977~999) 23 988, Bit13 (971~991) 21 981,
3362 14:44:55.365081 TX Bit6 (977~1000) 24 988, Bit14 (970~991) 22 980,
3363 14:44:55.372193 TX Bit7 (976~997) 22 986, Bit15 (967~987) 21 977,
3364 14:44:55.372304
3365 14:44:55.372396 Write Rank1 MR14 =0x12
3366 14:44:55.381773
3367 14:44:55.385592 CH=1, VrefRange= 0, VrefLevel = 18
3368 14:44:55.388396 TX Bit0 (977~1001) 25 989, Bit8 (969~991) 23 980,
3369 14:44:55.391688 TX Bit1 (977~1000) 24 988, Bit9 (969~991) 23 980,
3370 14:44:55.398529 TX Bit2 (974~996) 23 985, Bit10 (970~991) 22 980,
3371 14:44:55.401771 TX Bit3 (972~995) 24 983, Bit11 (970~993) 24 981,
3372 14:44:55.405168 TX Bit4 (975~998) 24 986, Bit12 (970~992) 23 981,
3373 14:44:55.411668 TX Bit5 (977~1000) 24 988, Bit13 (970~991) 22 980,
3374 14:44:55.415587 TX Bit6 (977~1001) 25 989, Bit14 (970~992) 23 981,
3375 14:44:55.421586 TX Bit7 (976~997) 22 986, Bit15 (966~988) 23 977,
3376 14:44:55.421668
3377 14:44:55.421733 Write Rank1 MR14 =0x14
3378 14:44:55.431714
3379 14:44:55.435780 CH=1, VrefRange= 0, VrefLevel = 20
3380 14:44:55.439137 TX Bit0 (978~1002) 25 990, Bit8 (968~992) 25 980,
3381 14:44:55.441982 TX Bit1 (977~1000) 24 988, Bit9 (968~991) 24 979,
3382 14:44:55.448673 TX Bit2 (974~997) 24 985, Bit10 (969~991) 23 980,
3383 14:44:55.452077 TX Bit3 (972~996) 25 984, Bit11 (969~993) 25 981,
3384 14:44:55.455256 TX Bit4 (975~998) 24 986, Bit12 (969~992) 24 980,
3385 14:44:55.462096 TX Bit5 (977~1000) 24 988, Bit13 (970~992) 23 981,
3386 14:44:55.465171 TX Bit6 (977~1001) 25 989, Bit14 (970~992) 23 981,
3387 14:44:55.471798 TX Bit7 (976~998) 23 987, Bit15 (966~988) 23 977,
3388 14:44:55.471879
3389 14:44:55.471942 Write Rank1 MR14 =0x16
3390 14:44:55.482252
3391 14:44:55.485712 CH=1, VrefRange= 0, VrefLevel = 22
3392 14:44:55.488821 TX Bit0 (977~1002) 26 989, Bit8 (969~991) 23 980,
3393 14:44:55.491915 TX Bit1 (977~1000) 24 988, Bit9 (968~991) 24 979,
3394 14:44:55.499032 TX Bit2 (973~997) 25 985, Bit10 (969~991) 23 980,
3395 14:44:55.501905 TX Bit3 (971~996) 26 983, Bit11 (970~993) 24 981,
3396 14:44:55.505700 TX Bit4 (975~998) 24 986, Bit12 (969~992) 24 980,
3397 14:44:55.512251 TX Bit5 (976~1000) 25 988, Bit13 (970~992) 23 981,
3398 14:44:55.515595 TX Bit6 (977~1001) 25 989, Bit14 (969~992) 24 980,
3399 14:44:55.518858 TX Bit7 (976~998) 23 987, Bit15 (966~989) 24 977,
3400 14:44:55.522134
3401 14:44:55.522223 Write Rank1 MR14 =0x18
3402 14:44:55.532711
3403 14:44:55.535629 CH=1, VrefRange= 0, VrefLevel = 24
3404 14:44:55.539284 TX Bit0 (977~1002) 26 989, Bit8 (969~991) 23 980,
3405 14:44:55.542511 TX Bit1 (977~1000) 24 988, Bit9 (968~991) 24 979,
3406 14:44:55.548855 TX Bit2 (973~997) 25 985, Bit10 (969~991) 23 980,
3407 14:44:55.552544 TX Bit3 (971~996) 26 983, Bit11 (970~993) 24 981,
3408 14:44:55.555626 TX Bit4 (975~998) 24 986, Bit12 (969~992) 24 980,
3409 14:44:55.562077 TX Bit5 (976~1000) 25 988, Bit13 (970~992) 23 981,
3410 14:44:55.565741 TX Bit6 (977~1001) 25 989, Bit14 (969~992) 24 980,
3411 14:44:55.571923 TX Bit7 (976~998) 23 987, Bit15 (966~989) 24 977,
3412 14:44:55.572005
3413 14:44:55.572068 Write Rank1 MR14 =0x1a
3414 14:44:55.582484
3415 14:44:55.585983 CH=1, VrefRange= 0, VrefLevel = 26
3416 14:44:55.588837 TX Bit0 (977~1002) 26 989, Bit8 (969~991) 23 980,
3417 14:44:55.592615 TX Bit1 (977~1000) 24 988, Bit9 (968~991) 24 979,
3418 14:44:55.599236 TX Bit2 (973~997) 25 985, Bit10 (969~991) 23 980,
3419 14:44:55.602435 TX Bit3 (971~996) 26 983, Bit11 (970~993) 24 981,
3420 14:44:55.605786 TX Bit4 (975~998) 24 986, Bit12 (969~992) 24 980,
3421 14:44:55.612193 TX Bit5 (976~1000) 25 988, Bit13 (970~992) 23 981,
3422 14:44:55.615417 TX Bit6 (977~1001) 25 989, Bit14 (969~992) 24 980,
3423 14:44:55.622449 TX Bit7 (976~998) 23 987, Bit15 (966~989) 24 977,
3424 14:44:55.622556
3425 14:44:55.622647 Write Rank1 MR14 =0x1c
3426 14:44:55.632715
3427 14:44:55.635800 CH=1, VrefRange= 0, VrefLevel = 28
3428 14:44:55.639436 TX Bit0 (977~1002) 26 989, Bit8 (969~991) 23 980,
3429 14:44:55.642433 TX Bit1 (977~1000) 24 988, Bit9 (968~991) 24 979,
3430 14:44:55.649314 TX Bit2 (973~997) 25 985, Bit10 (969~991) 23 980,
3431 14:44:55.652496 TX Bit3 (971~996) 26 983, Bit11 (970~993) 24 981,
3432 14:44:55.656491 TX Bit4 (975~998) 24 986, Bit12 (969~992) 24 980,
3433 14:44:55.662686 TX Bit5 (976~1000) 25 988, Bit13 (970~992) 23 981,
3434 14:44:55.665757 TX Bit6 (977~1001) 25 989, Bit14 (969~992) 24 980,
3435 14:44:55.669216 TX Bit7 (976~998) 23 987, Bit15 (966~989) 24 977,
3436 14:44:55.672560
3437 14:44:55.672666 Write Rank1 MR14 =0x1e
3438 14:44:55.682613
3439 14:44:55.685817 CH=1, VrefRange= 0, VrefLevel = 30
3440 14:44:55.689472 TX Bit0 (977~1002) 26 989, Bit8 (969~991) 23 980,
3441 14:44:55.692641 TX Bit1 (977~1000) 24 988, Bit9 (968~991) 24 979,
3442 14:44:55.699479 TX Bit2 (973~997) 25 985, Bit10 (969~991) 23 980,
3443 14:44:55.702568 TX Bit3 (971~996) 26 983, Bit11 (970~993) 24 981,
3444 14:44:55.706163 TX Bit4 (975~998) 24 986, Bit12 (969~992) 24 980,
3445 14:44:55.712380 TX Bit5 (976~1000) 25 988, Bit13 (970~992) 23 981,
3446 14:44:55.715778 TX Bit6 (977~1001) 25 989, Bit14 (969~992) 24 980,
3447 14:44:55.722584 TX Bit7 (976~998) 23 987, Bit15 (966~989) 24 977,
3448 14:44:55.722691
3449 14:44:55.722783 Write Rank1 MR14 =0x20
3450 14:44:55.732595
3451 14:44:55.736013 CH=1, VrefRange= 0, VrefLevel = 32
3452 14:44:55.739411 TX Bit0 (977~1002) 26 989, Bit8 (969~991) 23 980,
3453 14:44:55.742534 TX Bit1 (977~1000) 24 988, Bit9 (968~991) 24 979,
3454 14:44:55.749311 TX Bit2 (973~997) 25 985, Bit10 (969~991) 23 980,
3455 14:44:55.752829 TX Bit3 (971~996) 26 983, Bit11 (970~993) 24 981,
3456 14:44:55.755838 TX Bit4 (975~998) 24 986, Bit12 (969~992) 24 980,
3457 14:44:55.762480 TX Bit5 (976~1000) 25 988, Bit13 (970~992) 23 981,
3458 14:44:55.765928 TX Bit6 (977~1001) 25 989, Bit14 (969~992) 24 980,
3459 14:44:55.772607 TX Bit7 (976~998) 23 987, Bit15 (966~989) 24 977,
3460 14:44:55.772689
3461 14:44:55.772752
3462 14:44:55.775710 TX Vref found, early break! 364< 367
3463 14:44:55.779359 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =762/100 ps
3464 14:44:55.782644 u1DelayCellOfst[0]=7 cells (6 PI)
3465 14:44:55.785964 u1DelayCellOfst[1]=6 cells (5 PI)
3466 14:44:55.789331 u1DelayCellOfst[2]=2 cells (2 PI)
3467 14:44:55.792415 u1DelayCellOfst[3]=0 cells (0 PI)
3468 14:44:55.795587 u1DelayCellOfst[4]=3 cells (3 PI)
3469 14:44:55.799213 u1DelayCellOfst[5]=6 cells (5 PI)
3470 14:44:55.799295 u1DelayCellOfst[6]=7 cells (6 PI)
3471 14:44:55.802217 u1DelayCellOfst[7]=5 cells (4 PI)
3472 14:44:55.805722 Byte0, DQ PI dly=983, DQM PI dly= 986
3473 14:44:55.812284 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
3474 14:44:55.812369
3475 14:44:55.815986 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
3476 14:44:55.816069
3477 14:44:55.818945 u1DelayCellOfst[8]=3 cells (3 PI)
3478 14:44:55.822422 u1DelayCellOfst[9]=2 cells (2 PI)
3479 14:44:55.825447 u1DelayCellOfst[10]=3 cells (3 PI)
3480 14:44:55.829148 u1DelayCellOfst[11]=5 cells (4 PI)
3481 14:44:55.832232 u1DelayCellOfst[12]=3 cells (3 PI)
3482 14:44:55.835818 u1DelayCellOfst[13]=5 cells (4 PI)
3483 14:44:55.835926 u1DelayCellOfst[14]=3 cells (3 PI)
3484 14:44:55.839028 u1DelayCellOfst[15]=0 cells (0 PI)
3485 14:44:55.842761 Byte1, DQ PI dly=977, DQM PI dly= 979
3486 14:44:55.849061 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
3487 14:44:55.849170
3488 14:44:55.852350 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
3489 14:44:55.852433
3490 14:44:55.856024 Write Rank1 MR14 =0x16
3491 14:44:55.856105
3492 14:44:55.856170 Final TX Range 0 Vref 22
3493 14:44:55.856230
3494 14:44:55.862491 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3495 14:44:55.862573
3496 14:44:55.869268 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3497 14:44:55.879052 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3498 14:44:55.885600 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3499 14:44:55.885682 Write Rank1 MR3 =0xb0
3500 14:44:55.889192 DramC Write-DBI on
3501 14:44:55.889315 ==
3502 14:44:55.892157 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3503 14:44:55.895490 fsp= 1, odt_onoff= 1, Byte mode= 0
3504 14:44:55.895597 ==
3505 14:44:55.902184 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3506 14:44:55.902265
3507 14:44:55.902329 Begin, DQ Scan Range 699~763
3508 14:44:55.905713
3509 14:44:55.905793
3510 14:44:55.905856 TX Vref Scan disable
3511 14:44:55.908921 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3512 14:44:55.912162 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3513 14:44:55.915515 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3514 14:44:55.919229 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3515 14:44:55.922587 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3516 14:44:55.928760 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3517 14:44:55.932427 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3518 14:44:55.935610 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3519 14:44:55.938924 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3520 14:44:55.942160 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3521 14:44:55.945736 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3522 14:44:55.949123 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3523 14:44:55.952257 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
3524 14:44:55.955579 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
3525 14:44:55.959116 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
3526 14:44:55.962194 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
3527 14:44:55.965590 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
3528 14:44:55.969083 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3529 14:44:55.972815 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
3530 14:44:55.975898 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3531 14:44:55.979134 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3532 14:44:55.987106 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
3533 14:44:55.990583 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
3534 14:44:55.994326 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
3535 14:44:55.997084 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
3536 14:44:56.000542 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
3537 14:44:56.003673 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
3538 14:44:56.007226 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
3539 14:44:56.010545 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3540 14:44:56.014100 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3541 14:44:56.017113 745 |2 6 41|[0] xxxxxxxx xxxxxxxx [MSB]
3542 14:44:56.020698 Byte0, DQ PI dly=732, DQM PI dly= 732
3543 14:44:56.023857 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 28)
3544 14:44:56.023969
3545 14:44:56.030405 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 28)
3546 14:44:56.030487
3547 14:44:56.034348 Byte1, DQ PI dly=723, DQM PI dly= 723
3548 14:44:56.037136 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 19)
3549 14:44:56.037243
3550 14:44:56.040903 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 19)
3551 14:44:56.040985
3552 14:44:56.047462 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3553 14:44:56.054128 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3554 14:44:56.064125 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3555 14:44:56.064208 Write Rank1 MR3 =0x30
3556 14:44:56.067206 DramC Write-DBI off
3557 14:44:56.067287
3558 14:44:56.067351 [DATLAT]
3559 14:44:56.070845 Freq=1600, CH1 RK1, use_rxtx_scan=0
3560 14:44:56.070935
3561 14:44:56.073731 DATLAT Default: 0x10
3562 14:44:56.073812 7, 0xFFFF, sum=0
3563 14:44:56.077061 8, 0xFFFF, sum=0
3564 14:44:56.077190 9, 0xFFFF, sum=0
3565 14:44:56.080504 10, 0xFFFF, sum=0
3566 14:44:56.080586 11, 0xFFFF, sum=0
3567 14:44:56.080652 12, 0xFFFF, sum=0
3568 14:44:56.083787 13, 0xFFFF, sum=0
3569 14:44:56.083869 14, 0x0, sum=1
3570 14:44:56.087144 15, 0x0, sum=2
3571 14:44:56.087273 16, 0x0, sum=3
3572 14:44:56.090471 17, 0x0, sum=4
3573 14:44:56.093996 pattern=2 first_step=14 total pass=5 best_step=16
3574 14:44:56.094078 ==
3575 14:44:56.100990 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3576 14:44:56.101076 fsp= 1, odt_onoff= 1, Byte mode= 0
3577 14:44:56.103819 ==
3578 14:44:56.107178 Start DQ dly to find pass range UseTestEngine =1
3579 14:44:56.110438 x-axis: bit #, y-axis: DQ dly (-127~63)
3580 14:44:56.110536 RX Vref Scan = 0
3581 14:44:56.113761 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3582 14:44:56.117217 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3583 14:44:56.120352 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3584 14:44:56.123633 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3585 14:44:56.127351 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3586 14:44:56.130469 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3587 14:44:56.133784 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3588 14:44:56.133866 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3589 14:44:56.137540 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3590 14:44:56.140787 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3591 14:44:56.144527 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3592 14:44:56.147734 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3593 14:44:56.150815 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3594 14:44:56.153801 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3595 14:44:56.156988 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3596 14:44:56.160483 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3597 14:44:56.160566 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3598 14:44:56.163720 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3599 14:44:56.167327 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3600 14:44:56.170237 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3601 14:44:56.173835 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3602 14:44:56.177324 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3603 14:44:56.177418 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3604 14:44:56.180549 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3605 14:44:56.183648 -2, [0] xxxoxxxx xxxxxxxx [MSB]
3606 14:44:56.186981 -1, [0] xxxoxxxx xxxxxxxx [MSB]
3607 14:44:56.190495 0, [0] xxooxxxx xxxxxxxo [MSB]
3608 14:44:56.193531 1, [0] xxooxxxo ooxxxxxo [MSB]
3609 14:44:56.197046 2, [0] xxoooxxo oooxxxxo [MSB]
3610 14:44:56.197126 3, [0] xxoooxxo ooooxooo [MSB]
3611 14:44:56.200124 4, [0] xxoooxxo oooooooo [MSB]
3612 14:44:56.203473 5, [0] xoooooxo oooooooo [MSB]
3613 14:44:56.207091 6, [0] ooooooxo oooooooo [MSB]
3614 14:44:56.210261 7, [0] ooooooxo oooooooo [MSB]
3615 14:44:56.213498 34, [0] oooxoooo oooooooo [MSB]
3616 14:44:56.217135 35, [0] oooxoooo ooooooox [MSB]
3617 14:44:56.220380 36, [0] ooxxoooo ooooooox [MSB]
3618 14:44:56.223785 37, [0] ooxxxoox ooxooxxx [MSB]
3619 14:44:56.226653 38, [0] ooxxxoox xxxooxxx [MSB]
3620 14:44:56.226730 39, [0] ooxxxoox xxxxoxxx [MSB]
3621 14:44:56.230128 40, [0] ooxxxoox xxxxxxxx [MSB]
3622 14:44:56.233349 41, [0] oxxxxoox xxxxxxxx [MSB]
3623 14:44:56.236874 42, [0] oxxxxxox xxxxxxxx [MSB]
3624 14:44:56.240281 43, [0] xxxxxxxx xxxxxxxx [MSB]
3625 14:44:56.243861 iDelay=43, Bit 0, Center 24 (6 ~ 42) 37
3626 14:44:56.246809 iDelay=43, Bit 1, Center 22 (5 ~ 40) 36
3627 14:44:56.250469 iDelay=43, Bit 2, Center 17 (0 ~ 35) 36
3628 14:44:56.253514 iDelay=43, Bit 3, Center 15 (-2 ~ 33) 36
3629 14:44:56.256850 iDelay=43, Bit 4, Center 19 (2 ~ 36) 35
3630 14:44:56.260716 iDelay=43, Bit 5, Center 23 (5 ~ 41) 37
3631 14:44:56.263729 iDelay=43, Bit 6, Center 25 (8 ~ 42) 35
3632 14:44:56.267299 iDelay=43, Bit 7, Center 18 (1 ~ 36) 36
3633 14:44:56.270369 iDelay=43, Bit 8, Center 19 (1 ~ 37) 37
3634 14:44:56.276641 iDelay=43, Bit 9, Center 19 (1 ~ 37) 37
3635 14:44:56.280390 iDelay=43, Bit 10, Center 19 (2 ~ 36) 35
3636 14:44:56.283679 iDelay=43, Bit 11, Center 20 (3 ~ 38) 36
3637 14:44:56.286660 iDelay=43, Bit 12, Center 21 (4 ~ 39) 36
3638 14:44:56.290022 iDelay=43, Bit 13, Center 19 (3 ~ 36) 34
3639 14:44:56.293422 iDelay=43, Bit 14, Center 19 (3 ~ 36) 34
3640 14:44:56.296876 iDelay=43, Bit 15, Center 17 (0 ~ 34) 35
3641 14:44:56.296951 ==
3642 14:44:56.303192 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3643 14:44:56.306443 fsp= 1, odt_onoff= 1, Byte mode= 0
3644 14:44:56.306521 ==
3645 14:44:56.306608 DQS Delay:
3646 14:44:56.310151 DQS0 = 0, DQS1 = 0
3647 14:44:56.310231 DQM Delay:
3648 14:44:56.310319 DQM0 = 20, DQM1 = 19
3649 14:44:56.313449 DQ Delay:
3650 14:44:56.316657 DQ0 =24, DQ1 =22, DQ2 =17, DQ3 =15
3651 14:44:56.320181 DQ4 =19, DQ5 =23, DQ6 =25, DQ7 =18
3652 14:44:56.323440 DQ8 =19, DQ9 =19, DQ10 =19, DQ11 =20
3653 14:44:56.326642 DQ12 =21, DQ13 =19, DQ14 =19, DQ15 =17
3654 14:44:56.326725
3655 14:44:56.326806
3656 14:44:56.326881
3657 14:44:56.330130 [DramC_TX_OE_Calibration] TA2
3658 14:44:56.330212 Original DQ_B0 (3 6) =30, OEN = 27
3659 14:44:56.333247 Original DQ_B1 (3 6) =30, OEN = 27
3660 14:44:56.336597 23, 0x0, End_B0=23 End_B1=23
3661 14:44:56.340111 24, 0x0, End_B0=24 End_B1=24
3662 14:44:56.343500 25, 0x0, End_B0=25 End_B1=25
3663 14:44:56.343586 26, 0x0, End_B0=26 End_B1=26
3664 14:44:56.346549 27, 0x0, End_B0=27 End_B1=27
3665 14:44:56.350209 28, 0x0, End_B0=28 End_B1=28
3666 14:44:56.353510 29, 0x0, End_B0=29 End_B1=29
3667 14:44:56.357193 30, 0x0, End_B0=30 End_B1=30
3668 14:44:56.357313 31, 0xFFFF, End_B0=30 End_B1=30
3669 14:44:56.363171 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3670 14:44:56.370185 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3671 14:44:56.370268
3672 14:44:56.370332
3673 14:44:56.370391 Write Rank1 MR23 =0x3f
3674 14:44:56.373914 [DQSOSC]
3675 14:44:56.379785 [DQSOSCAuto] RK1, (LSB)MR18= 0xb2, (MSB)MR19= 0x3, tDQSOscB0 = 332 ps tDQSOscB1 = 0 ps
3676 14:44:56.386948 CH1_RK1: MR19=0x3, MR18=0xB2, DQSOSC=332, MR23=63, INC=22, DEC=33
3677 14:44:56.387030 Write Rank1 MR23 =0x3f
3678 14:44:56.390091 [DQSOSC]
3679 14:44:56.396706 [DQSOSCAuto] RK1, (LSB)MR18= 0xb2, (MSB)MR19= 0x3, tDQSOscB0 = 332 ps tDQSOscB1 = 0 ps
3680 14:44:56.399975 CH1 RK1: MR19=3, MR18=B2
3681 14:44:56.403139 [RxdqsGatingPostProcess] freq 1600
3682 14:44:56.406541 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3683 14:44:56.406621 Rank: 0
3684 14:44:56.410164 best DQS0 dly(2T, 0.5T) = (2, 5)
3685 14:44:56.413284 best DQS1 dly(2T, 0.5T) = (2, 5)
3686 14:44:56.416569 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
3687 14:44:56.419873 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
3688 14:44:56.419954 Rank: 1
3689 14:44:56.423448 best DQS0 dly(2T, 0.5T) = (2, 5)
3690 14:44:56.426685 best DQS1 dly(2T, 0.5T) = (2, 5)
3691 14:44:56.429690 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
3692 14:44:56.433536 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
3693 14:44:56.436746 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3694 14:44:56.439985 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3695 14:44:56.446598 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3696 14:44:56.446679
3697 14:44:56.446745
3698 14:44:56.450344 [Calibration Summary] Freqency 1600
3699 14:44:56.450418 CH 0, Rank 0
3700 14:44:56.453353 All Pass.
3701 14:44:56.453426
3702 14:44:56.453485 CH 0, Rank 1
3703 14:44:56.453541 All Pass.
3704 14:44:56.453599
3705 14:44:56.456441 CH 1, Rank 0
3706 14:44:56.456515 All Pass.
3707 14:44:56.456576
3708 14:44:56.456636 CH 1, Rank 1
3709 14:44:56.459759 All Pass.
3710 14:44:56.459830
3711 14:44:56.466356 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3712 14:44:56.473250 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3713 14:44:56.479605 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3714 14:44:56.483585 Write Rank0 MR3 =0xb0
3715 14:44:56.486434 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3716 14:44:56.496281 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3717 14:44:56.503426 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3718 14:44:56.503505 Write Rank1 MR3 =0xb0
3719 14:44:56.509910 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3720 14:44:56.516496 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3721 14:44:56.523045 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3722 14:44:56.526576 Write Rank0 MR3 =0xb0
3723 14:44:56.533553 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3724 14:44:56.539999 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3725 14:44:56.546355 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3726 14:44:56.550194 Write Rank1 MR3 =0xb0
3727 14:44:56.550275 DramC Write-DBI on
3728 14:44:56.553192 [GetDramInforAfterCalByMRR] Vendor 1.
3729 14:44:56.556487 [GetDramInforAfterCalByMRR] Revision 7.
3730 14:44:56.560125 MR8 12
3731 14:44:56.563402 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3732 14:44:56.563485 MR8 12
3733 14:44:56.569509 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3734 14:44:56.569590 MR8 12
3735 14:44:56.572882 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3736 14:44:56.576236 MR8 12
3737 14:44:56.579885 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3738 14:44:56.589927 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3739 14:44:56.590009 Write Rank0 MR13 =0xd0
3740 14:44:56.592800 Write Rank1 MR13 =0xd0
3741 14:44:56.596539 Write Rank0 MR13 =0xd0
3742 14:44:56.596619 Write Rank1 MR13 =0xd0
3743 14:44:56.599742 Save calibration result to emmc
3744 14:44:56.599822
3745 14:44:56.599885
3746 14:44:56.603245 [DramcModeReg_Check] Freq_1600, FSP_1
3747 14:44:56.606695 FSP_1, CH_0, RK0
3748 14:44:56.606776 Write Rank0 MR13 =0xd8
3749 14:44:56.609947 MR12 = 0x56 (global = 0x56) match
3750 14:44:56.613033 MR14 = 0x18 (global = 0x18) match
3751 14:44:56.616446 FSP_1, CH_0, RK1
3752 14:44:56.616526 Write Rank1 MR13 =0xd8
3753 14:44:56.619539 MR12 = 0x56 (global = 0x56) match
3754 14:44:56.623026 MR14 = 0x16 (global = 0x16) match
3755 14:44:56.626322 FSP_1, CH_1, RK0
3756 14:44:56.626402 Write Rank0 MR13 =0xd8
3757 14:44:56.629961 MR12 = 0x56 (global = 0x56) match
3758 14:44:56.633204 MR14 = 0x18 (global = 0x18) match
3759 14:44:56.636637 FSP_1, CH_1, RK1
3760 14:44:56.636720 Write Rank1 MR13 =0xd8
3761 14:44:56.640068 MR12 = 0x58 (global = 0x58) match
3762 14:44:56.643369 MR14 = 0x16 (global = 0x16) match
3763 14:44:56.643449
3764 14:44:56.646558 [MEM_TEST] 02: After DFS, before run time config
3765 14:44:56.658694 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3766 14:44:56.658781
3767 14:44:56.658844 [TA2_TEST]
3768 14:44:56.658909 === TA2 HW
3769 14:44:56.661980 TA2 PAT: XTALK
3770 14:44:56.665550 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
3771 14:44:56.672096 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
3772 14:44:56.675661 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
3773 14:44:56.678684 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
3774 14:44:56.678765
3775 14:44:56.682447
3776 14:44:56.682526 Settings after calibration
3777 14:44:56.682590
3778 14:44:56.685555 [DramcRunTimeConfig]
3779 14:44:56.688740 TransferPLLToSPMControl - MODE SW PHYPLL
3780 14:44:56.688825 TX_TRACKING: ON
3781 14:44:56.692021 RX_TRACKING: ON
3782 14:44:56.692101 HW_GATING: ON
3783 14:44:56.695588 HW_GATING DBG: OFF
3784 14:44:56.695669 ddr_geometry:1
3785 14:44:56.698803 ddr_geometry:1
3786 14:44:56.698882 ddr_geometry:1
3787 14:44:56.698946 ddr_geometry:1
3788 14:44:56.701748 ddr_geometry:1
3789 14:44:56.701830 ddr_geometry:1
3790 14:44:56.705261 ddr_geometry:1
3791 14:44:56.705410 ddr_geometry:1
3792 14:44:56.708508 High Freq DUMMY_READ_FOR_TRACKING: ON
3793 14:44:56.712005 ZQCS_ENABLE_LP4: OFF
3794 14:44:56.715121 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
3795 14:44:56.718613 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
3796 14:44:56.718692 SPM_CONTROL_AFTERK: ON
3797 14:44:56.721720 IMPEDANCE_TRACKING: ON
3798 14:44:56.721800 TEMP_SENSOR: ON
3799 14:44:56.725069 PER_BANK_REFRESH: ON
3800 14:44:56.725149 HW_SAVE_FOR_SR: ON
3801 14:44:56.728662 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3802 14:44:56.732513 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
3803 14:44:56.734934 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
3804 14:44:56.738396 Read ODT Tracking: ON
3805 14:44:56.741501 =========================
3806 14:44:56.741582
3807 14:44:56.741645 [TA2_TEST]
3808 14:44:56.741704 === TA2 HW
3809 14:44:56.748572 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
3810 14:44:56.752331 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
3811 14:44:56.758459 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
3812 14:44:56.761505 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
3813 14:44:56.761611
3814 14:44:56.764836 [MEM_TEST] 03: After run time config
3815 14:44:56.776882 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3816 14:44:56.780109 [complex_mem_test] start addr:0x40024000, len:131072
3817 14:44:56.984218 1st complex R/W mem test pass
3818 14:44:56.990944 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
3819 14:44:56.994497 sync preloader write leveling
3820 14:44:56.997493 sync preloader cbt_mr12
3821 14:44:56.997623 sync preloader cbt_clk_dly
3822 14:44:57.001068 sync preloader cbt_cmd_dly
3823 14:44:57.004169 sync preloader cbt_cs
3824 14:44:57.007553 sync preloader cbt_ca_perbit_delay
3825 14:44:57.007664 sync preloader clk_delay
3826 14:44:57.010676 sync preloader dqs_delay
3827 14:44:57.014459 sync preloader u1Gating2T_Save
3828 14:44:57.017767 sync preloader u1Gating05T_Save
3829 14:44:57.020988 sync preloader u1Gatingfine_tune_Save
3830 14:44:57.024495 sync preloader u1Gatingucpass_count_Save
3831 14:44:57.027471 sync preloader u1TxWindowPerbitVref_Save
3832 14:44:57.030993 sync preloader u1TxCenter_min_Save
3833 14:44:57.034250 sync preloader u1TxCenter_max_Save
3834 14:44:57.037714 sync preloader u1Txwin_center_Save
3835 14:44:57.041191 sync preloader u1Txfirst_pass_Save
3836 14:44:57.044039 sync preloader u1Txlast_pass_Save
3837 14:44:57.044135 sync preloader u1RxDatlat_Save
3838 14:44:57.047742 sync preloader u1RxWinPerbitVref_Save
3839 14:44:57.054128 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3840 14:44:57.057525 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3841 14:44:57.060870 sync preloader delay_cell_unit
3842 14:44:57.067721 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
3843 14:44:57.067805 sync preloader write leveling
3844 14:44:57.071155 sync preloader cbt_mr12
3845 14:44:57.074516 sync preloader cbt_clk_dly
3846 14:44:57.077794 sync preloader cbt_cmd_dly
3847 14:44:57.077864 sync preloader cbt_cs
3848 14:44:57.081611 sync preloader cbt_ca_perbit_delay
3849 14:44:57.084622 sync preloader clk_delay
3850 14:44:57.084704 sync preloader dqs_delay
3851 14:44:57.088214 sync preloader u1Gating2T_Save
3852 14:44:57.091503 sync preloader u1Gating05T_Save
3853 14:44:57.094570 sync preloader u1Gatingfine_tune_Save
3854 14:44:57.097879 sync preloader u1Gatingucpass_count_Save
3855 14:44:57.101671 sync preloader u1TxWindowPerbitVref_Save
3856 14:44:57.104946 sync preloader u1TxCenter_min_Save
3857 14:44:57.108119 sync preloader u1TxCenter_max_Save
3858 14:44:57.111281 sync preloader u1Txwin_center_Save
3859 14:44:57.114845 sync preloader u1Txfirst_pass_Save
3860 14:44:57.117993 sync preloader u1Txlast_pass_Save
3861 14:44:57.121418 sync preloader u1RxDatlat_Save
3862 14:44:57.124751 sync preloader u1RxWinPerbitVref_Save
3863 14:44:57.127895 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3864 14:44:57.131073 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3865 14:44:57.134985 sync preloader delay_cell_unit
3866 14:44:57.141460 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
3867 14:44:57.144571 sync preloader write leveling
3868 14:44:57.144645 sync preloader cbt_mr12
3869 14:44:57.147907 sync preloader cbt_clk_dly
3870 14:44:57.151365 sync preloader cbt_cmd_dly
3871 14:44:57.154726 sync preloader cbt_cs
3872 14:44:57.154801 sync preloader cbt_ca_perbit_delay
3873 14:44:57.157908 sync preloader clk_delay
3874 14:44:57.161002 sync preloader dqs_delay
3875 14:44:57.164638 sync preloader u1Gating2T_Save
3876 14:44:57.164711 sync preloader u1Gating05T_Save
3877 14:44:57.171060 sync preloader u1Gatingfine_tune_Save
3878 14:44:57.174247 sync preloader u1Gatingucpass_count_Save
3879 14:44:57.177751 sync preloader u1TxWindowPerbitVref_Save
3880 14:44:57.181095 sync preloader u1TxCenter_min_Save
3881 14:44:57.184469 sync preloader u1TxCenter_max_Save
3882 14:44:57.184563 sync preloader u1Txwin_center_Save
3883 14:44:57.187644 sync preloader u1Txfirst_pass_Save
3884 14:44:57.191497 sync preloader u1Txlast_pass_Save
3885 14:44:57.194323 sync preloader u1RxDatlat_Save
3886 14:44:57.198021 sync preloader u1RxWinPerbitVref_Save
3887 14:44:57.201198 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3888 14:44:57.207881 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3889 14:44:57.207955 sync preloader delay_cell_unit
3890 14:44:57.214778 just_for_test_dump_coreboot_params dump all params
3891 14:44:57.214856 dump source = 0x0
3892 14:44:57.217891 dump params frequency:1600
3893 14:44:57.221040 dump params rank number:2
3894 14:44:57.221142
3895 14:44:57.221287 dump params write leveling
3896 14:44:57.224671 write leveling[0][0][0] = 0x20
3897 14:44:57.227943 write leveling[0][0][1] = 0x19
3898 14:44:57.231401 write leveling[0][1][0] = 0x22
3899 14:44:57.234834 write leveling[0][1][1] = 0x1c
3900 14:44:57.237802 write leveling[1][0][0] = 0x23
3901 14:44:57.237876 write leveling[1][0][1] = 0x1f
3902 14:44:57.241235 write leveling[1][1][0] = 0x24
3903 14:44:57.244789 write leveling[1][1][1] = 0x20
3904 14:44:57.248455 dump params cbt_cs
3905 14:44:57.248526 cbt_cs[0][0] = 0xa
3906 14:44:57.251888 cbt_cs[0][1] = 0xa
3907 14:44:57.251968 cbt_cs[1][0] = 0xa
3908 14:44:57.254680 cbt_cs[1][1] = 0xa
3909 14:44:57.254761 dump params cbt_mr12
3910 14:44:57.257886 cbt_mr12[0][0] = 0x16
3911 14:44:57.257992 cbt_mr12[0][1] = 0x16
3912 14:44:57.261613 cbt_mr12[1][0] = 0x16
3913 14:44:57.264651 cbt_mr12[1][1] = 0x18
3914 14:44:57.264732 dump params tx window
3915 14:44:57.268425 tx_center_min[0][0][0] = 979
3916 14:44:57.271448 tx_center_max[0][0][0] = 986
3917 14:44:57.274493 tx_center_min[0][0][1] = 972
3918 14:44:57.274566 tx_center_max[0][0][1] = 978
3919 14:44:57.278469 tx_center_min[0][1][0] = 982
3920 14:44:57.281382 tx_center_max[0][1][0] = 989
3921 14:44:57.284565 tx_center_min[0][1][1] = 976
3922 14:44:57.287878 tx_center_max[0][1][1] = 981
3923 14:44:57.287962 tx_center_min[1][0][0] = 982
3924 14:44:57.291231 tx_center_max[1][0][0] = 989
3925 14:44:57.294589 tx_center_min[1][0][1] = 975
3926 14:44:57.297959 tx_center_max[1][0][1] = 980
3927 14:44:57.298040 tx_center_min[1][1][0] = 983
3928 14:44:57.301449 tx_center_max[1][1][0] = 989
3929 14:44:57.304479 tx_center_min[1][1][1] = 977
3930 14:44:57.308324 tx_center_max[1][1][1] = 981
3931 14:44:57.308404 dump params tx window
3932 14:44:57.311299 tx_win_center[0][0][0] = 986
3933 14:44:57.314364 tx_first_pass[0][0][0] = 974
3934 14:44:57.317787 tx_last_pass[0][0][0] = 998
3935 14:44:57.321025 tx_win_center[0][0][1] = 983
3936 14:44:57.321105 tx_first_pass[0][0][1] = 972
3937 14:44:57.324468 tx_last_pass[0][0][1] = 995
3938 14:44:57.327869 tx_win_center[0][0][2] = 983
3939 14:44:57.331235 tx_first_pass[0][0][2] = 972
3940 14:44:57.331315 tx_last_pass[0][0][2] = 995
3941 14:44:57.334420 tx_win_center[0][0][3] = 979
3942 14:44:57.337647 tx_first_pass[0][0][3] = 967
3943 14:44:57.341583 tx_last_pass[0][0][3] = 991
3944 14:44:57.344574 tx_win_center[0][0][4] = 984
3945 14:44:57.344665 tx_first_pass[0][0][4] = 972
3946 14:44:57.348015 tx_last_pass[0][0][4] = 996
3947 14:44:57.351140 tx_win_center[0][0][5] = 979
3948 14:44:57.354853 tx_first_pass[0][0][5] = 968
3949 14:44:57.354934 tx_last_pass[0][0][5] = 991
3950 14:44:57.358033 tx_win_center[0][0][6] = 980
3951 14:44:57.361290 tx_first_pass[0][0][6] = 969
3952 14:44:57.364609 tx_last_pass[0][0][6] = 992
3953 14:44:57.364727 tx_win_center[0][0][7] = 982
3954 14:44:57.367775 tx_first_pass[0][0][7] = 970
3955 14:44:57.371180 tx_last_pass[0][0][7] = 994
3956 14:44:57.374589 tx_win_center[0][0][8] = 973
3957 14:44:57.377979 tx_first_pass[0][0][8] = 961
3958 14:44:57.378059 tx_last_pass[0][0][8] = 985
3959 14:44:57.381164 tx_win_center[0][0][9] = 974
3960 14:44:57.384602 tx_first_pass[0][0][9] = 962
3961 14:44:57.388189 tx_last_pass[0][0][9] = 987
3962 14:44:57.388270 tx_win_center[0][0][10] = 978
3963 14:44:57.391512 tx_first_pass[0][0][10] = 966
3964 14:44:57.394554 tx_last_pass[0][0][10] = 990
3965 14:44:57.397800 tx_win_center[0][0][11] = 972
3966 14:44:57.401099 tx_first_pass[0][0][11] = 961
3967 14:44:57.404489 tx_last_pass[0][0][11] = 984
3968 14:44:57.404569 tx_win_center[0][0][12] = 973
3969 14:44:57.408041 tx_first_pass[0][0][12] = 961
3970 14:44:57.411437 tx_last_pass[0][0][12] = 985
3971 14:44:57.414512 tx_win_center[0][0][13] = 972
3972 14:44:57.418336 tx_first_pass[0][0][13] = 961
3973 14:44:57.418419 tx_last_pass[0][0][13] = 984
3974 14:44:57.421135 tx_win_center[0][0][14] = 973
3975 14:44:57.424541 tx_first_pass[0][0][14] = 962
3976 14:44:57.427924 tx_last_pass[0][0][14] = 985
3977 14:44:57.431156 tx_win_center[0][0][15] = 977
3978 14:44:57.431239 tx_first_pass[0][0][15] = 965
3979 14:44:57.434345 tx_last_pass[0][0][15] = 989
3980 14:44:57.437623 tx_win_center[0][1][0] = 989
3981 14:44:57.441071 tx_first_pass[0][1][0] = 977
3982 14:44:57.444311 tx_last_pass[0][1][0] = 1002
3983 14:44:57.444392 tx_win_center[0][1][1] = 988
3984 14:44:57.448006 tx_first_pass[0][1][1] = 977
3985 14:44:57.450967 tx_last_pass[0][1][1] = 1000
3986 14:44:57.454290 tx_win_center[0][1][2] = 988
3987 14:44:57.454374 tx_first_pass[0][1][2] = 976
3988 14:44:57.458060 tx_last_pass[0][1][2] = 1000
3989 14:44:57.461145 tx_win_center[0][1][3] = 982
3990 14:44:57.464401 tx_first_pass[0][1][3] = 969
3991 14:44:57.464484 tx_last_pass[0][1][3] = 995
3992 14:44:57.467879 tx_win_center[0][1][4] = 988
3993 14:44:57.471383 tx_first_pass[0][1][4] = 976
3994 14:44:57.474683 tx_last_pass[0][1][4] = 1001
3995 14:44:57.477743 tx_win_center[0][1][5] = 983
3996 14:44:57.477823 tx_first_pass[0][1][5] = 971
3997 14:44:57.481433 tx_last_pass[0][1][5] = 995
3998 14:44:57.484261 tx_win_center[0][1][6] = 985
3999 14:44:57.487817 tx_first_pass[0][1][6] = 972
4000 14:44:57.491458 tx_last_pass[0][1][6] = 998
4001 14:44:57.491538 tx_win_center[0][1][7] = 987
4002 14:44:57.494356 tx_first_pass[0][1][7] = 975
4003 14:44:57.497418 tx_last_pass[0][1][7] = 999
4004 14:44:57.500973 tx_win_center[0][1][8] = 977
4005 14:44:57.501053 tx_first_pass[0][1][8] = 966
4006 14:44:57.504420 tx_last_pass[0][1][8] = 989
4007 14:44:57.507861 tx_win_center[0][1][9] = 979
4008 14:44:57.511170 tx_first_pass[0][1][9] = 968
4009 14:44:57.514387 tx_last_pass[0][1][9] = 990
4010 14:44:57.514473 tx_win_center[0][1][10] = 981
4011 14:44:57.517826 tx_first_pass[0][1][10] = 970
4012 14:44:57.521495 tx_last_pass[0][1][10] = 992
4013 14:44:57.524085 tx_win_center[0][1][11] = 977
4014 14:44:57.527518 tx_first_pass[0][1][11] = 966
4015 14:44:57.527599 tx_last_pass[0][1][11] = 989
4016 14:44:57.530511 tx_win_center[0][1][12] = 978
4017 14:44:57.534266 tx_first_pass[0][1][12] = 967
4018 14:44:57.537491 tx_last_pass[0][1][12] = 989
4019 14:44:57.540683 tx_win_center[0][1][13] = 976
4020 14:44:57.540765 tx_first_pass[0][1][13] = 966
4021 14:44:57.543906 tx_last_pass[0][1][13] = 987
4022 14:44:57.547500 tx_win_center[0][1][14] = 978
4023 14:44:57.551076 tx_first_pass[0][1][14] = 967
4024 14:44:57.553984 tx_last_pass[0][1][14] = 989
4025 14:44:57.554078 tx_win_center[0][1][15] = 979
4026 14:44:57.557699 tx_first_pass[0][1][15] = 969
4027 14:44:57.560780 tx_last_pass[0][1][15] = 990
4028 14:44:57.564160 tx_win_center[1][0][0] = 989
4029 14:44:57.567516 tx_first_pass[1][0][0] = 977
4030 14:44:57.567629 tx_last_pass[1][0][0] = 1001
4031 14:44:57.570310 tx_win_center[1][0][1] = 987
4032 14:44:57.574252 tx_first_pass[1][0][1] = 975
4033 14:44:57.577065 tx_last_pass[1][0][1] = 999
4034 14:44:57.580521 tx_win_center[1][0][2] = 985
4035 14:44:57.580600 tx_first_pass[1][0][2] = 973
4036 14:44:57.584443 tx_last_pass[1][0][2] = 997
4037 14:44:57.587619 tx_win_center[1][0][3] = 982
4038 14:44:57.590528 tx_first_pass[1][0][3] = 970
4039 14:44:57.590601 tx_last_pass[1][0][3] = 994
4040 14:44:57.593681 tx_win_center[1][0][4] = 986
4041 14:44:57.597153 tx_first_pass[1][0][4] = 974
4042 14:44:57.600555 tx_last_pass[1][0][4] = 998
4043 14:44:57.603901 tx_win_center[1][0][5] = 988
4044 14:44:57.603973 tx_first_pass[1][0][5] = 976
4045 14:44:57.606899 tx_last_pass[1][0][5] = 1000
4046 14:44:57.610233 tx_win_center[1][0][6] = 988
4047 14:44:57.613773 tx_first_pass[1][0][6] = 977
4048 14:44:57.616967 tx_last_pass[1][0][6] = 1000
4049 14:44:57.617035 tx_win_center[1][0][7] = 985
4050 14:44:57.620235 tx_first_pass[1][0][7] = 974
4051 14:44:57.623995 tx_last_pass[1][0][7] = 997
4052 14:44:57.627017 tx_win_center[1][0][8] = 978
4053 14:44:57.627085 tx_first_pass[1][0][8] = 966
4054 14:44:57.630290 tx_last_pass[1][0][8] = 991
4055 14:44:57.634215 tx_win_center[1][0][9] = 978
4056 14:44:57.637180 tx_first_pass[1][0][9] = 966
4057 14:44:57.637269 tx_last_pass[1][0][9] = 991
4058 14:44:57.640418 tx_win_center[1][0][10] = 979
4059 14:44:57.644201 tx_first_pass[1][0][10] = 967
4060 14:44:57.647340 tx_last_pass[1][0][10] = 991
4061 14:44:57.650423 tx_win_center[1][0][11] = 980
4062 14:44:57.653914 tx_first_pass[1][0][11] = 968
4063 14:44:57.653988 tx_last_pass[1][0][11] = 992
4064 14:44:57.657244 tx_win_center[1][0][12] = 980
4065 14:44:57.660724 tx_first_pass[1][0][12] = 968
4066 14:44:57.663802 tx_last_pass[1][0][12] = 992
4067 14:44:57.666860 tx_win_center[1][0][13] = 980
4068 14:44:57.666930 tx_first_pass[1][0][13] = 969
4069 14:44:57.670306 tx_last_pass[1][0][13] = 991
4070 14:44:57.673814 tx_win_center[1][0][14] = 979
4071 14:44:57.676954 tx_first_pass[1][0][14] = 967
4072 14:44:57.680172 tx_last_pass[1][0][14] = 991
4073 14:44:57.680247 tx_win_center[1][0][15] = 975
4074 14:44:57.683645 tx_first_pass[1][0][15] = 963
4075 14:44:57.687075 tx_last_pass[1][0][15] = 988
4076 14:44:57.690678 tx_win_center[1][1][0] = 989
4077 14:44:57.690759 tx_first_pass[1][1][0] = 977
4078 14:44:57.693507 tx_last_pass[1][1][0] = 1002
4079 14:44:57.697023 tx_win_center[1][1][1] = 988
4080 14:44:57.700378 tx_first_pass[1][1][1] = 977
4081 14:44:57.703915 tx_last_pass[1][1][1] = 1000
4082 14:44:57.703995 tx_win_center[1][1][2] = 985
4083 14:44:57.707160 tx_first_pass[1][1][2] = 973
4084 14:44:57.710480 tx_last_pass[1][1][2] = 997
4085 14:44:57.714232 tx_win_center[1][1][3] = 983
4086 14:44:57.716859 tx_first_pass[1][1][3] = 971
4087 14:44:57.716940 tx_last_pass[1][1][3] = 996
4088 14:44:57.720615 tx_win_center[1][1][4] = 986
4089 14:44:57.723953 tx_first_pass[1][1][4] = 975
4090 14:44:57.726895 tx_last_pass[1][1][4] = 998
4091 14:44:57.726979 tx_win_center[1][1][5] = 988
4092 14:44:57.730661 tx_first_pass[1][1][5] = 976
4093 14:44:57.733629 tx_last_pass[1][1][5] = 1000
4094 14:44:57.737277 tx_win_center[1][1][6] = 989
4095 14:44:57.740563 tx_first_pass[1][1][6] = 977
4096 14:44:57.740643 tx_last_pass[1][1][6] = 1001
4097 14:44:57.743430 tx_win_center[1][1][7] = 987
4098 14:44:57.746976 tx_first_pass[1][1][7] = 976
4099 14:44:57.750476 tx_last_pass[1][1][7] = 998
4100 14:44:57.750556 tx_win_center[1][1][8] = 980
4101 14:44:57.753699 tx_first_pass[1][1][8] = 969
4102 14:44:57.757555 tx_last_pass[1][1][8] = 991
4103 14:44:57.760339 tx_win_center[1][1][9] = 979
4104 14:44:57.763766 tx_first_pass[1][1][9] = 968
4105 14:44:57.763847 tx_last_pass[1][1][9] = 991
4106 14:44:57.767113 tx_win_center[1][1][10] = 980
4107 14:44:57.770127 tx_first_pass[1][1][10] = 969
4108 14:44:57.773791 tx_last_pass[1][1][10] = 991
4109 14:44:57.776922 tx_win_center[1][1][11] = 981
4110 14:44:57.777028 tx_first_pass[1][1][11] = 970
4111 14:44:57.780175 tx_last_pass[1][1][11] = 993
4112 14:44:57.783718 tx_win_center[1][1][12] = 980
4113 14:44:57.787089 tx_first_pass[1][1][12] = 969
4114 14:44:57.790431 tx_last_pass[1][1][12] = 992
4115 14:44:57.790511 tx_win_center[1][1][13] = 981
4116 14:44:57.793349 tx_first_pass[1][1][13] = 970
4117 14:44:57.797176 tx_last_pass[1][1][13] = 992
4118 14:44:57.800222 tx_win_center[1][1][14] = 980
4119 14:44:57.803373 tx_first_pass[1][1][14] = 969
4120 14:44:57.803453 tx_last_pass[1][1][14] = 992
4121 14:44:57.806822 tx_win_center[1][1][15] = 977
4122 14:44:57.810246 tx_first_pass[1][1][15] = 966
4123 14:44:57.813606 tx_last_pass[1][1][15] = 989
4124 14:44:57.813694 dump params rx window
4125 14:44:57.816870 rx_firspass[0][0][0] = 9
4126 14:44:57.820024 rx_lastpass[0][0][0] = 42
4127 14:44:57.820105 rx_firspass[0][0][1] = 9
4128 14:44:57.823592 rx_lastpass[0][0][1] = 40
4129 14:44:57.826727 rx_firspass[0][0][2] = 9
4130 14:44:57.830515 rx_lastpass[0][0][2] = 39
4131 14:44:57.830595 rx_firspass[0][0][3] = -1
4132 14:44:57.833294 rx_lastpass[0][0][3] = 30
4133 14:44:57.836931 rx_firspass[0][0][4] = 7
4134 14:44:57.837011 rx_lastpass[0][0][4] = 39
4135 14:44:57.840071 rx_firspass[0][0][5] = 3
4136 14:44:57.843624 rx_lastpass[0][0][5] = 29
4137 14:44:57.843705 rx_firspass[0][0][6] = 2
4138 14:44:57.846495 rx_lastpass[0][0][6] = 32
4139 14:44:57.850357 rx_firspass[0][0][7] = 4
4140 14:44:57.853138 rx_lastpass[0][0][7] = 34
4141 14:44:57.853243 rx_firspass[0][0][8] = 2
4142 14:44:57.856690 rx_lastpass[0][0][8] = 34
4143 14:44:57.859767 rx_firspass[0][0][9] = 5
4144 14:44:57.859855 rx_lastpass[0][0][9] = 35
4145 14:44:57.863742 rx_firspass[0][0][10] = 9
4146 14:44:57.866867 rx_lastpass[0][0][10] = 38
4147 14:44:57.869908 rx_firspass[0][0][11] = 3
4148 14:44:57.869989 rx_lastpass[0][0][11] = 30
4149 14:44:57.873389 rx_firspass[0][0][12] = 5
4150 14:44:57.876627 rx_lastpass[0][0][12] = 34
4151 14:44:57.876707 rx_firspass[0][0][13] = 1
4152 14:44:57.880325 rx_lastpass[0][0][13] = 31
4153 14:44:57.883852 rx_firspass[0][0][14] = 3
4154 14:44:57.886952 rx_lastpass[0][0][14] = 33
4155 14:44:57.887033 rx_firspass[0][0][15] = 4
4156 14:44:57.890064 rx_lastpass[0][0][15] = 35
4157 14:44:57.893492 rx_firspass[0][1][0] = 9
4158 14:44:57.893572 rx_lastpass[0][1][0] = 42
4159 14:44:57.896772 rx_firspass[0][1][1] = 7
4160 14:44:57.900105 rx_lastpass[0][1][1] = 42
4161 14:44:57.903608 rx_firspass[0][1][2] = 8
4162 14:44:57.903689 rx_lastpass[0][1][2] = 42
4163 14:44:57.906713 rx_firspass[0][1][3] = 0
4164 14:44:57.909802 rx_lastpass[0][1][3] = 32
4165 14:44:57.909882 rx_firspass[0][1][4] = 6
4166 14:44:57.913483 rx_lastpass[0][1][4] = 40
4167 14:44:57.916456 rx_firspass[0][1][5] = 0
4168 14:44:57.916535 rx_lastpass[0][1][5] = 35
4169 14:44:57.920158 rx_firspass[0][1][6] = 3
4170 14:44:57.923303 rx_lastpass[0][1][6] = 36
4171 14:44:57.926527 rx_firspass[0][1][7] = 3
4172 14:44:57.926607 rx_lastpass[0][1][7] = 35
4173 14:44:57.930758 rx_firspass[0][1][8] = 0
4174 14:44:57.933505 rx_lastpass[0][1][8] = 36
4175 14:44:57.933586 rx_firspass[0][1][9] = 3
4176 14:44:57.936569 rx_lastpass[0][1][9] = 37
4177 14:44:57.940138 rx_firspass[0][1][10] = 6
4178 14:44:57.943066 rx_lastpass[0][1][10] = 42
4179 14:44:57.943146 rx_firspass[0][1][11] = 0
4180 14:44:57.946580 rx_lastpass[0][1][11] = 34
4181 14:44:57.950287 rx_firspass[0][1][12] = 3
4182 14:44:57.950367 rx_lastpass[0][1][12] = 37
4183 14:44:57.953519 rx_firspass[0][1][13] = 0
4184 14:44:57.956740 rx_lastpass[0][1][13] = 33
4185 14:44:57.960045 rx_firspass[0][1][14] = 2
4186 14:44:57.960125 rx_lastpass[0][1][14] = 35
4187 14:44:57.963259 rx_firspass[0][1][15] = 4
4188 14:44:57.967222 rx_lastpass[0][1][15] = 37
4189 14:44:57.967326 rx_firspass[1][0][0] = 7
4190 14:44:57.970138 rx_lastpass[1][0][0] = 42
4191 14:44:57.973786 rx_firspass[1][0][1] = 6
4192 14:44:57.976781 rx_lastpass[1][0][1] = 40
4193 14:44:57.976860 rx_firspass[1][0][2] = 0
4194 14:44:57.980067 rx_lastpass[1][0][2] = 33
4195 14:44:57.983217 rx_firspass[1][0][3] = -1
4196 14:44:57.983297 rx_lastpass[1][0][3] = 32
4197 14:44:57.986511 rx_firspass[1][0][4] = 3
4198 14:44:57.989789 rx_lastpass[1][0][4] = 34
4199 14:44:57.989869 rx_firspass[1][0][5] = 8
4200 14:44:57.993102 rx_lastpass[1][0][5] = 40
4201 14:44:57.996603 rx_firspass[1][0][6] = 9
4202 14:44:58.000107 rx_lastpass[1][0][6] = 41
4203 14:44:58.000212 rx_firspass[1][0][7] = 4
4204 14:44:58.003369 rx_lastpass[1][0][7] = 34
4205 14:44:58.006507 rx_firspass[1][0][8] = 1
4206 14:44:58.006586 rx_lastpass[1][0][8] = 36
4207 14:44:58.009783 rx_firspass[1][0][9] = 3
4208 14:44:58.013301 rx_lastpass[1][0][9] = 36
4209 14:44:58.013382 rx_firspass[1][0][10] = 1
4210 14:44:58.016613 rx_lastpass[1][0][10] = 35
4211 14:44:58.019703 rx_firspass[1][0][11] = 3
4212 14:44:58.023174 rx_lastpass[1][0][11] = 36
4213 14:44:58.023254 rx_firspass[1][0][12] = 5
4214 14:44:58.026776 rx_lastpass[1][0][12] = 36
4215 14:44:58.030093 rx_firspass[1][0][13] = 4
4216 14:44:58.033431 rx_lastpass[1][0][13] = 34
4217 14:44:58.033515 rx_firspass[1][0][14] = 3
4218 14:44:58.036617 rx_lastpass[1][0][14] = 35
4219 14:44:58.039998 rx_firspass[1][0][15] = 0
4220 14:44:58.040078 rx_lastpass[1][0][15] = 33
4221 14:44:58.043172 rx_firspass[1][1][0] = 6
4222 14:44:58.046821 rx_lastpass[1][1][0] = 42
4223 14:44:58.046919 rx_firspass[1][1][1] = 5
4224 14:44:58.049820 rx_lastpass[1][1][1] = 40
4225 14:44:58.053117 rx_firspass[1][1][2] = 0
4226 14:44:58.056505 rx_lastpass[1][1][2] = 35
4227 14:44:58.056585 rx_firspass[1][1][3] = -2
4228 14:44:58.060067 rx_lastpass[1][1][3] = 33
4229 14:44:58.063113 rx_firspass[1][1][4] = 2
4230 14:44:58.063193 rx_lastpass[1][1][4] = 36
4231 14:44:58.066421 rx_firspass[1][1][5] = 5
4232 14:44:58.070060 rx_lastpass[1][1][5] = 41
4233 14:44:58.073069 rx_firspass[1][1][6] = 8
4234 14:44:58.073177 rx_lastpass[1][1][6] = 42
4235 14:44:58.076580 rx_firspass[1][1][7] = 1
4236 14:44:58.080085 rx_lastpass[1][1][7] = 36
4237 14:44:58.080172 rx_firspass[1][1][8] = 1
4238 14:44:58.083474 rx_lastpass[1][1][8] = 37
4239 14:44:58.086772 rx_firspass[1][1][9] = 1
4240 14:44:58.086852 rx_lastpass[1][1][9] = 37
4241 14:44:58.089614 rx_firspass[1][1][10] = 2
4242 14:44:58.092777 rx_lastpass[1][1][10] = 36
4243 14:44:58.096748 rx_firspass[1][1][11] = 3
4244 14:44:58.096828 rx_lastpass[1][1][11] = 38
4245 14:44:58.099625 rx_firspass[1][1][12] = 4
4246 14:44:58.103246 rx_lastpass[1][1][12] = 39
4247 14:44:58.103326 rx_firspass[1][1][13] = 3
4248 14:44:58.106777 rx_lastpass[1][1][13] = 36
4249 14:44:58.109710 rx_firspass[1][1][14] = 3
4250 14:44:58.112943 rx_lastpass[1][1][14] = 36
4251 14:44:58.113029 rx_firspass[1][1][15] = 0
4252 14:44:58.116716 rx_lastpass[1][1][15] = 34
4253 14:44:58.119859 dump params clk_delay
4254 14:44:58.119939 clk_delay[0] = -1
4255 14:44:58.123051 clk_delay[1] = 0
4256 14:44:58.123156 dump params dqs_delay
4257 14:44:58.126492 dqs_delay[0][0] = 0
4258 14:44:58.126571 dqs_delay[0][1] = -1
4259 14:44:58.129667 dqs_delay[1][0] = -1
4260 14:44:58.129748 dqs_delay[1][1] = 0
4261 14:44:58.133248 dump params delay_cell_unit = 762
4262 14:44:58.136449 dump source = 0x0
4263 14:44:58.140054 dump params frequency:1200
4264 14:44:58.140155 dump params rank number:2
4265 14:44:58.140218
4266 14:44:58.143433 dump params write leveling
4267 14:44:58.146332 write leveling[0][0][0] = 0x0
4268 14:44:58.150017 write leveling[0][0][1] = 0x0
4269 14:44:58.150124 write leveling[0][1][0] = 0x0
4270 14:44:58.153045 write leveling[0][1][1] = 0x0
4271 14:44:58.156484 write leveling[1][0][0] = 0x0
4272 14:44:58.159804 write leveling[1][0][1] = 0x0
4273 14:44:58.163160 write leveling[1][1][0] = 0x0
4274 14:44:58.166892 write leveling[1][1][1] = 0x0
4275 14:44:58.167010 dump params cbt_cs
4276 14:44:58.169800 cbt_cs[0][0] = 0x0
4277 14:44:58.169908 cbt_cs[0][1] = 0x0
4278 14:44:58.173409 cbt_cs[1][0] = 0x0
4279 14:44:58.173480 cbt_cs[1][1] = 0x0
4280 14:44:58.176567 dump params cbt_mr12
4281 14:44:58.176633 cbt_mr12[0][0] = 0x0
4282 14:44:58.179931 cbt_mr12[0][1] = 0x0
4283 14:44:58.180011 cbt_mr12[1][0] = 0x0
4284 14:44:58.183134 cbt_mr12[1][1] = 0x0
4285 14:44:58.186427 dump params tx window
4286 14:44:58.186507 tx_center_min[0][0][0] = 0
4287 14:44:58.189664 tx_center_max[0][0][0] = 0
4288 14:44:58.193218 tx_center_min[0][0][1] = 0
4289 14:44:58.196811 tx_center_max[0][0][1] = 0
4290 14:44:58.196908 tx_center_min[0][1][0] = 0
4291 14:44:58.200029 tx_center_max[0][1][0] = 0
4292 14:44:58.203458 tx_center_min[0][1][1] = 0
4293 14:44:58.203538 tx_center_max[0][1][1] = 0
4294 14:44:58.206311 tx_center_min[1][0][0] = 0
4295 14:44:58.209810 tx_center_max[1][0][0] = 0
4296 14:44:58.212872 tx_center_min[1][0][1] = 0
4297 14:44:58.212953 tx_center_max[1][0][1] = 0
4298 14:44:58.216425 tx_center_min[1][1][0] = 0
4299 14:44:58.219878 tx_center_max[1][1][0] = 0
4300 14:44:58.223119 tx_center_min[1][1][1] = 0
4301 14:44:58.223221 tx_center_max[1][1][1] = 0
4302 14:44:58.226529 dump params tx window
4303 14:44:58.229775 tx_win_center[0][0][0] = 0
4304 14:44:58.229878 tx_first_pass[0][0][0] = 0
4305 14:44:58.233329 tx_last_pass[0][0][0] = 0
4306 14:44:58.236580 tx_win_center[0][0][1] = 0
4307 14:44:58.239711 tx_first_pass[0][0][1] = 0
4308 14:44:58.239791 tx_last_pass[0][0][1] = 0
4309 14:44:58.243512 tx_win_center[0][0][2] = 0
4310 14:44:58.246959 tx_first_pass[0][0][2] = 0
4311 14:44:58.247039 tx_last_pass[0][0][2] = 0
4312 14:44:58.249903 tx_win_center[0][0][3] = 0
4313 14:44:58.253522 tx_first_pass[0][0][3] = 0
4314 14:44:58.256669 tx_last_pass[0][0][3] = 0
4315 14:44:58.256749 tx_win_center[0][0][4] = 0
4316 14:44:58.260128 tx_first_pass[0][0][4] = 0
4317 14:44:58.263154 tx_last_pass[0][0][4] = 0
4318 14:44:58.263224 tx_win_center[0][0][5] = 0
4319 14:44:58.266387 tx_first_pass[0][0][5] = 0
4320 14:44:58.269647 tx_last_pass[0][0][5] = 0
4321 14:44:58.273192 tx_win_center[0][0][6] = 0
4322 14:44:58.273311 tx_first_pass[0][0][6] = 0
4323 14:44:58.276294 tx_last_pass[0][0][6] = 0
4324 14:44:58.279612 tx_win_center[0][0][7] = 0
4325 14:44:58.283531 tx_first_pass[0][0][7] = 0
4326 14:44:58.283612 tx_last_pass[0][0][7] = 0
4327 14:44:58.286801 tx_win_center[0][0][8] = 0
4328 14:44:58.290215 tx_first_pass[0][0][8] = 0
4329 14:44:58.290296 tx_last_pass[0][0][8] = 0
4330 14:44:58.293202 tx_win_center[0][0][9] = 0
4331 14:44:58.296492 tx_first_pass[0][0][9] = 0
4332 14:44:58.299822 tx_last_pass[0][0][9] = 0
4333 14:44:58.299903 tx_win_center[0][0][10] = 0
4334 14:44:58.303305 tx_first_pass[0][0][10] = 0
4335 14:44:58.306509 tx_last_pass[0][0][10] = 0
4336 14:44:58.309729 tx_win_center[0][0][11] = 0
4337 14:44:58.309815 tx_first_pass[0][0][11] = 0
4338 14:44:58.313226 tx_last_pass[0][0][11] = 0
4339 14:44:58.316456 tx_win_center[0][0][12] = 0
4340 14:44:58.320343 tx_first_pass[0][0][12] = 0
4341 14:44:58.320448 tx_last_pass[0][0][12] = 0
4342 14:44:58.323158 tx_win_center[0][0][13] = 0
4343 14:44:58.326463 tx_first_pass[0][0][13] = 0
4344 14:44:58.330252 tx_last_pass[0][0][13] = 0
4345 14:44:58.330358 tx_win_center[0][0][14] = 0
4346 14:44:58.333281 tx_first_pass[0][0][14] = 0
4347 14:44:58.336552 tx_last_pass[0][0][14] = 0
4348 14:44:58.339799 tx_win_center[0][0][15] = 0
4349 14:44:58.339895 tx_first_pass[0][0][15] = 0
4350 14:44:58.343448 tx_last_pass[0][0][15] = 0
4351 14:44:58.347126 tx_win_center[0][1][0] = 0
4352 14:44:58.350403 tx_first_pass[0][1][0] = 0
4353 14:44:58.350499 tx_last_pass[0][1][0] = 0
4354 14:44:58.353427 tx_win_center[0][1][1] = 0
4355 14:44:58.356425 tx_first_pass[0][1][1] = 0
4356 14:44:58.356517 tx_last_pass[0][1][1] = 0
4357 14:44:58.359766 tx_win_center[0][1][2] = 0
4358 14:44:58.362921 tx_first_pass[0][1][2] = 0
4359 14:44:58.366461 tx_last_pass[0][1][2] = 0
4360 14:44:58.366625 tx_win_center[0][1][3] = 0
4361 14:44:58.369799 tx_first_pass[0][1][3] = 0
4362 14:44:58.373121 tx_last_pass[0][1][3] = 0
4363 14:44:58.376782 tx_win_center[0][1][4] = 0
4364 14:44:58.376885 tx_first_pass[0][1][4] = 0
4365 14:44:58.379686 tx_last_pass[0][1][4] = 0
4366 14:44:58.383084 tx_win_center[0][1][5] = 0
4367 14:44:58.383191 tx_first_pass[0][1][5] = 0
4368 14:44:58.386229 tx_last_pass[0][1][5] = 0
4369 14:44:58.389560 tx_win_center[0][1][6] = 0
4370 14:44:58.393201 tx_first_pass[0][1][6] = 0
4371 14:44:58.393339 tx_last_pass[0][1][6] = 0
4372 14:44:58.396411 tx_win_center[0][1][7] = 0
4373 14:44:58.400001 tx_first_pass[0][1][7] = 0
4374 14:44:58.400102 tx_last_pass[0][1][7] = 0
4375 14:44:58.402962 tx_win_center[0][1][8] = 0
4376 14:44:58.406592 tx_first_pass[0][1][8] = 0
4377 14:44:58.410255 tx_last_pass[0][1][8] = 0
4378 14:44:58.410354 tx_win_center[0][1][9] = 0
4379 14:44:58.412884 tx_first_pass[0][1][9] = 0
4380 14:44:58.416834 tx_last_pass[0][1][9] = 0
4381 14:44:58.419757 tx_win_center[0][1][10] = 0
4382 14:44:58.419861 tx_first_pass[0][1][10] = 0
4383 14:44:58.422894 tx_last_pass[0][1][10] = 0
4384 14:44:58.426503 tx_win_center[0][1][11] = 0
4385 14:44:58.429687 tx_first_pass[0][1][11] = 0
4386 14:44:58.429783 tx_last_pass[0][1][11] = 0
4387 14:44:58.433865 tx_win_center[0][1][12] = 0
4388 14:44:58.436140 tx_first_pass[0][1][12] = 0
4389 14:44:58.439500 tx_last_pass[0][1][12] = 0
4390 14:44:58.439596 tx_win_center[0][1][13] = 0
4391 14:44:58.442804 tx_first_pass[0][1][13] = 0
4392 14:44:58.446408 tx_last_pass[0][1][13] = 0
4393 14:44:58.449542 tx_win_center[0][1][14] = 0
4394 14:44:58.449613 tx_first_pass[0][1][14] = 0
4395 14:44:58.452533 tx_last_pass[0][1][14] = 0
4396 14:44:58.456355 tx_win_center[0][1][15] = 0
4397 14:44:58.459274 tx_first_pass[0][1][15] = 0
4398 14:44:58.459375 tx_last_pass[0][1][15] = 0
4399 14:44:58.462455 tx_win_center[1][0][0] = 0
4400 14:44:58.465872 tx_first_pass[1][0][0] = 0
4401 14:44:58.469248 tx_last_pass[1][0][0] = 0
4402 14:44:58.469349 tx_win_center[1][0][1] = 0
4403 14:44:58.472855 tx_first_pass[1][0][1] = 0
4404 14:44:58.476322 tx_last_pass[1][0][1] = 0
4405 14:44:58.479397 tx_win_center[1][0][2] = 0
4406 14:44:58.479467 tx_first_pass[1][0][2] = 0
4407 14:44:58.482783 tx_last_pass[1][0][2] = 0
4408 14:44:58.485902 tx_win_center[1][0][3] = 0
4409 14:44:58.489395 tx_first_pass[1][0][3] = 0
4410 14:44:58.489478 tx_last_pass[1][0][3] = 0
4411 14:44:58.492622 tx_win_center[1][0][4] = 0
4412 14:44:58.495778 tx_first_pass[1][0][4] = 0
4413 14:44:58.495847 tx_last_pass[1][0][4] = 0
4414 14:44:58.499114 tx_win_center[1][0][5] = 0
4415 14:44:58.502524 tx_first_pass[1][0][5] = 0
4416 14:44:58.505969 tx_last_pass[1][0][5] = 0
4417 14:44:58.506040 tx_win_center[1][0][6] = 0
4418 14:44:58.509447 tx_first_pass[1][0][6] = 0
4419 14:44:58.512667 tx_last_pass[1][0][6] = 0
4420 14:44:58.512735 tx_win_center[1][0][7] = 0
4421 14:44:58.515902 tx_first_pass[1][0][7] = 0
4422 14:44:58.519500 tx_last_pass[1][0][7] = 0
4423 14:44:58.522346 tx_win_center[1][0][8] = 0
4424 14:44:58.522415 tx_first_pass[1][0][8] = 0
4425 14:44:58.525700 tx_last_pass[1][0][8] = 0
4426 14:44:58.529198 tx_win_center[1][0][9] = 0
4427 14:44:58.532671 tx_first_pass[1][0][9] = 0
4428 14:44:58.532740 tx_last_pass[1][0][9] = 0
4429 14:44:58.535983 tx_win_center[1][0][10] = 0
4430 14:44:58.539159 tx_first_pass[1][0][10] = 0
4431 14:44:58.539226 tx_last_pass[1][0][10] = 0
4432 14:44:58.542745 tx_win_center[1][0][11] = 0
4433 14:44:58.546049 tx_first_pass[1][0][11] = 0
4434 14:44:58.549383 tx_last_pass[1][0][11] = 0
4435 14:44:58.549451 tx_win_center[1][0][12] = 0
4436 14:44:58.552853 tx_first_pass[1][0][12] = 0
4437 14:44:58.556115 tx_last_pass[1][0][12] = 0
4438 14:44:58.559221 tx_win_center[1][0][13] = 0
4439 14:44:58.562661 tx_first_pass[1][0][13] = 0
4440 14:44:58.562731 tx_last_pass[1][0][13] = 0
4441 14:44:58.565985 tx_win_center[1][0][14] = 0
4442 14:44:58.569167 tx_first_pass[1][0][14] = 0
4443 14:44:58.569310 tx_last_pass[1][0][14] = 0
4444 14:44:58.572853 tx_win_center[1][0][15] = 0
4445 14:44:58.576171 tx_first_pass[1][0][15] = 0
4446 14:44:58.579372 tx_last_pass[1][0][15] = 0
4447 14:44:58.579468 tx_win_center[1][1][0] = 0
4448 14:44:58.582650 tx_first_pass[1][1][0] = 0
4449 14:44:58.585911 tx_last_pass[1][1][0] = 0
4450 14:44:58.589159 tx_win_center[1][1][1] = 0
4451 14:44:58.589254 tx_first_pass[1][1][1] = 0
4452 14:44:58.592641 tx_last_pass[1][1][1] = 0
4453 14:44:58.595765 tx_win_center[1][1][2] = 0
4454 14:44:58.598834 tx_first_pass[1][1][2] = 0
4455 14:44:58.598932 tx_last_pass[1][1][2] = 0
4456 14:44:58.602366 tx_win_center[1][1][3] = 0
4457 14:44:58.605829 tx_first_pass[1][1][3] = 0
4458 14:44:58.605901 tx_last_pass[1][1][3] = 0
4459 14:44:58.609135 tx_win_center[1][1][4] = 0
4460 14:44:58.612569 tx_first_pass[1][1][4] = 0
4461 14:44:58.615929 tx_last_pass[1][1][4] = 0
4462 14:44:58.616024 tx_win_center[1][1][5] = 0
4463 14:44:58.619469 tx_first_pass[1][1][5] = 0
4464 14:44:58.622472 tx_last_pass[1][1][5] = 0
4465 14:44:58.622571 tx_win_center[1][1][6] = 0
4466 14:44:58.625796 tx_first_pass[1][1][6] = 0
4467 14:44:58.629287 tx_last_pass[1][1][6] = 0
4468 14:44:58.632789 tx_win_center[1][1][7] = 0
4469 14:44:58.632874 tx_first_pass[1][1][7] = 0
4470 14:44:58.636035 tx_last_pass[1][1][7] = 0
4471 14:44:58.639408 tx_win_center[1][1][8] = 0
4472 14:44:58.642954 tx_first_pass[1][1][8] = 0
4473 14:44:58.643053 tx_last_pass[1][1][8] = 0
4474 14:44:58.646090 tx_win_center[1][1][9] = 0
4475 14:44:58.649504 tx_first_pass[1][1][9] = 0
4476 14:44:58.649574 tx_last_pass[1][1][9] = 0
4477 14:44:58.652394 tx_win_center[1][1][10] = 0
4478 14:44:58.655953 tx_first_pass[1][1][10] = 0
4479 14:44:58.659043 tx_last_pass[1][1][10] = 0
4480 14:44:58.659143 tx_win_center[1][1][11] = 0
4481 14:44:58.662783 tx_first_pass[1][1][11] = 0
4482 14:44:58.666049 tx_last_pass[1][1][11] = 0
4483 14:44:58.669411 tx_win_center[1][1][12] = 0
4484 14:44:58.669498 tx_first_pass[1][1][12] = 0
4485 14:44:58.672308 tx_last_pass[1][1][12] = 0
4486 14:44:58.675941 tx_win_center[1][1][13] = 0
4487 14:44:58.679405 tx_first_pass[1][1][13] = 0
4488 14:44:58.679486 tx_last_pass[1][1][13] = 0
4489 14:44:58.682767 tx_win_center[1][1][14] = 0
4490 14:44:58.685995 tx_first_pass[1][1][14] = 0
4491 14:44:58.689242 tx_last_pass[1][1][14] = 0
4492 14:44:58.689366 tx_win_center[1][1][15] = 0
4493 14:44:58.692659 tx_first_pass[1][1][15] = 0
4494 14:44:58.696101 tx_last_pass[1][1][15] = 0
4495 14:44:58.699405 dump params rx window
4496 14:44:58.699493 rx_firspass[0][0][0] = 0
4497 14:44:58.702724 rx_lastpass[0][0][0] = 0
4498 14:44:58.706189 rx_firspass[0][0][1] = 0
4499 14:44:58.706270 rx_lastpass[0][0][1] = 0
4500 14:44:58.709361 rx_firspass[0][0][2] = 0
4501 14:44:58.712383 rx_lastpass[0][0][2] = 0
4502 14:44:58.712487 rx_firspass[0][0][3] = 0
4503 14:44:58.715837 rx_lastpass[0][0][3] = 0
4504 14:44:58.719117 rx_firspass[0][0][4] = 0
4505 14:44:58.719196 rx_lastpass[0][0][4] = 0
4506 14:44:58.722715 rx_firspass[0][0][5] = 0
4507 14:44:58.726180 rx_lastpass[0][0][5] = 0
4508 14:44:58.726268 rx_firspass[0][0][6] = 0
4509 14:44:58.729180 rx_lastpass[0][0][6] = 0
4510 14:44:58.732826 rx_firspass[0][0][7] = 0
4511 14:44:58.732906 rx_lastpass[0][0][7] = 0
4512 14:44:58.736120 rx_firspass[0][0][8] = 0
4513 14:44:58.739316 rx_lastpass[0][0][8] = 0
4514 14:44:58.742420 rx_firspass[0][0][9] = 0
4515 14:44:58.742508 rx_lastpass[0][0][9] = 0
4516 14:44:58.745713 rx_firspass[0][0][10] = 0
4517 14:44:58.749339 rx_lastpass[0][0][10] = 0
4518 14:44:58.749418 rx_firspass[0][0][11] = 0
4519 14:44:58.752165 rx_lastpass[0][0][11] = 0
4520 14:44:58.755710 rx_firspass[0][0][12] = 0
4521 14:44:58.758957 rx_lastpass[0][0][12] = 0
4522 14:44:58.759037 rx_firspass[0][0][13] = 0
4523 14:44:58.762666 rx_lastpass[0][0][13] = 0
4524 14:44:58.765832 rx_firspass[0][0][14] = 0
4525 14:44:58.765913 rx_lastpass[0][0][14] = 0
4526 14:44:58.769338 rx_firspass[0][0][15] = 0
4527 14:44:58.772580 rx_lastpass[0][0][15] = 0
4528 14:44:58.772659 rx_firspass[0][1][0] = 0
4529 14:44:58.776009 rx_lastpass[0][1][0] = 0
4530 14:44:58.778975 rx_firspass[0][1][1] = 0
4531 14:44:58.782604 rx_lastpass[0][1][1] = 0
4532 14:44:58.782684 rx_firspass[0][1][2] = 0
4533 14:44:58.785864 rx_lastpass[0][1][2] = 0
4534 14:44:58.789171 rx_firspass[0][1][3] = 0
4535 14:44:58.789251 rx_lastpass[0][1][3] = 0
4536 14:44:58.792357 rx_firspass[0][1][4] = 0
4537 14:44:58.795818 rx_lastpass[0][1][4] = 0
4538 14:44:58.795898 rx_firspass[0][1][5] = 0
4539 14:44:58.799012 rx_lastpass[0][1][5] = 0
4540 14:44:58.802489 rx_firspass[0][1][6] = 0
4541 14:44:58.802569 rx_lastpass[0][1][6] = 0
4542 14:44:58.805886 rx_firspass[0][1][7] = 0
4543 14:44:58.809132 rx_lastpass[0][1][7] = 0
4544 14:44:58.809211 rx_firspass[0][1][8] = 0
4545 14:44:58.812517 rx_lastpass[0][1][8] = 0
4546 14:44:58.815692 rx_firspass[0][1][9] = 0
4547 14:44:58.815772 rx_lastpass[0][1][9] = 0
4548 14:44:58.819231 rx_firspass[0][1][10] = 0
4549 14:44:58.822661 rx_lastpass[0][1][10] = 0
4550 14:44:58.825831 rx_firspass[0][1][11] = 0
4551 14:44:58.825911 rx_lastpass[0][1][11] = 0
4552 14:44:58.829223 rx_firspass[0][1][12] = 0
4553 14:44:58.832244 rx_lastpass[0][1][12] = 0
4554 14:44:58.832336 rx_firspass[0][1][13] = 0
4555 14:44:58.836114 rx_lastpass[0][1][13] = 0
4556 14:44:58.838945 rx_firspass[0][1][14] = 0
4557 14:44:58.842727 rx_lastpass[0][1][14] = 0
4558 14:44:58.842806 rx_firspass[0][1][15] = 0
4559 14:44:58.845867 rx_lastpass[0][1][15] = 0
4560 14:44:58.849270 rx_firspass[1][0][0] = 0
4561 14:44:58.849363 rx_lastpass[1][0][0] = 0
4562 14:44:58.852703 rx_firspass[1][0][1] = 0
4563 14:44:58.855604 rx_lastpass[1][0][1] = 0
4564 14:44:58.855691 rx_firspass[1][0][2] = 0
4565 14:44:58.858839 rx_lastpass[1][0][2] = 0
4566 14:44:58.862135 rx_firspass[1][0][3] = 0
4567 14:44:58.866007 rx_lastpass[1][0][3] = 0
4568 14:44:58.866088 rx_firspass[1][0][4] = 0
4569 14:44:58.869056 rx_lastpass[1][0][4] = 0
4570 14:44:58.872180 rx_firspass[1][0][5] = 0
4571 14:44:58.872260 rx_lastpass[1][0][5] = 0
4572 14:44:58.875666 rx_firspass[1][0][6] = 0
4573 14:44:58.879036 rx_lastpass[1][0][6] = 0
4574 14:44:58.879116 rx_firspass[1][0][7] = 0
4575 14:44:58.882188 rx_lastpass[1][0][7] = 0
4576 14:44:58.885523 rx_firspass[1][0][8] = 0
4577 14:44:58.885603 rx_lastpass[1][0][8] = 0
4578 14:44:58.888740 rx_firspass[1][0][9] = 0
4579 14:44:58.892205 rx_lastpass[1][0][9] = 0
4580 14:44:58.892285 rx_firspass[1][0][10] = 0
4581 14:44:58.895798 rx_lastpass[1][0][10] = 0
4582 14:44:58.898715 rx_firspass[1][0][11] = 0
4583 14:44:58.902172 rx_lastpass[1][0][11] = 0
4584 14:44:58.902252 rx_firspass[1][0][12] = 0
4585 14:44:58.905552 rx_lastpass[1][0][12] = 0
4586 14:44:58.909234 rx_firspass[1][0][13] = 0
4587 14:44:58.909330 rx_lastpass[1][0][13] = 0
4588 14:44:58.911912 rx_firspass[1][0][14] = 0
4589 14:44:58.915406 rx_lastpass[1][0][14] = 0
4590 14:44:58.918839 rx_firspass[1][0][15] = 0
4591 14:44:58.918919 rx_lastpass[1][0][15] = 0
4592 14:44:58.921967 rx_firspass[1][1][0] = 0
4593 14:44:58.925323 rx_lastpass[1][1][0] = 0
4594 14:44:58.925402 rx_firspass[1][1][1] = 0
4595 14:44:58.928587 rx_lastpass[1][1][1] = 0
4596 14:44:58.931972 rx_firspass[1][1][2] = 0
4597 14:44:58.932052 rx_lastpass[1][1][2] = 0
4598 14:44:58.935121 rx_firspass[1][1][3] = 0
4599 14:44:58.938668 rx_lastpass[1][1][3] = 0
4600 14:44:58.942003 rx_firspass[1][1][4] = 0
4601 14:44:58.942083 rx_lastpass[1][1][4] = 0
4602 14:44:58.945434 rx_firspass[1][1][5] = 0
4603 14:44:58.948669 rx_lastpass[1][1][5] = 0
4604 14:44:58.948755 rx_firspass[1][1][6] = 0
4605 14:44:58.951834 rx_lastpass[1][1][6] = 0
4606 14:44:58.955635 rx_firspass[1][1][7] = 0
4607 14:44:58.955714 rx_lastpass[1][1][7] = 0
4608 14:44:58.958908 rx_firspass[1][1][8] = 0
4609 14:44:58.961991 rx_lastpass[1][1][8] = 0
4610 14:44:58.962061 rx_firspass[1][1][9] = 0
4611 14:44:58.965316 rx_lastpass[1][1][9] = 0
4612 14:44:58.968491 rx_firspass[1][1][10] = 0
4613 14:44:58.968570 rx_lastpass[1][1][10] = 0
4614 14:44:58.972042 rx_firspass[1][1][11] = 0
4615 14:44:58.975435 rx_lastpass[1][1][11] = 0
4616 14:44:58.978706 rx_firspass[1][1][12] = 0
4617 14:44:58.978786 rx_lastpass[1][1][12] = 0
4618 14:44:58.981822 rx_firspass[1][1][13] = 0
4619 14:44:58.985235 rx_lastpass[1][1][13] = 0
4620 14:44:58.985381 rx_firspass[1][1][14] = 0
4621 14:44:58.988807 rx_lastpass[1][1][14] = 0
4622 14:44:58.992120 rx_firspass[1][1][15] = 0
4623 14:44:58.995487 rx_lastpass[1][1][15] = 0
4624 14:44:58.995567 dump params clk_delay
4625 14:44:58.998969 clk_delay[0] = 0
4626 14:44:58.999049 clk_delay[1] = 0
4627 14:44:59.002075 dump params dqs_delay
4628 14:44:59.002154 dqs_delay[0][0] = 0
4629 14:44:59.005268 dqs_delay[0][1] = 0
4630 14:44:59.005348 dqs_delay[1][0] = 0
4631 14:44:59.008545 dqs_delay[1][1] = 0
4632 14:44:59.012110 dump params delay_cell_unit = 762
4633 14:44:59.012189 dump source = 0x0
4634 14:44:59.015426 dump params frequency:800
4635 14:44:59.018662 dump params rank number:2
4636 14:44:59.018741
4637 14:44:59.018804 dump params write leveling
4638 14:44:59.021901 write leveling[0][0][0] = 0x0
4639 14:44:59.025615 write leveling[0][0][1] = 0x0
4640 14:44:59.028445 write leveling[0][1][0] = 0x0
4641 14:44:59.032092 write leveling[0][1][1] = 0x0
4642 14:44:59.032171 write leveling[1][0][0] = 0x0
4643 14:44:59.035198 write leveling[1][0][1] = 0x0
4644 14:44:59.039002 write leveling[1][1][0] = 0x0
4645 14:44:59.041919 write leveling[1][1][1] = 0x0
4646 14:44:59.041997 dump params cbt_cs
4647 14:44:59.044990 cbt_cs[0][0] = 0x0
4648 14:44:59.045094 cbt_cs[0][1] = 0x0
4649 14:44:59.049094 cbt_cs[1][0] = 0x0
4650 14:44:59.049199 cbt_cs[1][1] = 0x0
4651 14:44:59.051850 dump params cbt_mr12
4652 14:44:59.055334 cbt_mr12[0][0] = 0x0
4653 14:44:59.055414 cbt_mr12[0][1] = 0x0
4654 14:44:59.058438 cbt_mr12[1][0] = 0x0
4655 14:44:59.058517 cbt_mr12[1][1] = 0x0
4656 14:44:59.062138 dump params tx window
4657 14:44:59.065040 tx_center_min[0][0][0] = 0
4658 14:44:59.065119 tx_center_max[0][0][0] = 0
4659 14:44:59.068581 tx_center_min[0][0][1] = 0
4660 14:44:59.072596 tx_center_max[0][0][1] = 0
4661 14:44:59.075570 tx_center_min[0][1][0] = 0
4662 14:44:59.075650 tx_center_max[0][1][0] = 0
4663 14:44:59.078815 tx_center_min[0][1][1] = 0
4664 14:44:59.081892 tx_center_max[0][1][1] = 0
4665 14:44:59.085427 tx_center_min[1][0][0] = 0
4666 14:44:59.085507 tx_center_max[1][0][0] = 0
4667 14:44:59.088504 tx_center_min[1][0][1] = 0
4668 14:44:59.091777 tx_center_max[1][0][1] = 0
4669 14:44:59.091857 tx_center_min[1][1][0] = 0
4670 14:44:59.095513 tx_center_max[1][1][0] = 0
4671 14:44:59.098457 tx_center_min[1][1][1] = 0
4672 14:44:59.102210 tx_center_max[1][1][1] = 0
4673 14:44:59.102290 dump params tx window
4674 14:44:59.105185 tx_win_center[0][0][0] = 0
4675 14:44:59.109038 tx_first_pass[0][0][0] = 0
4676 14:44:59.109118 tx_last_pass[0][0][0] = 0
4677 14:44:59.112332 tx_win_center[0][0][1] = 0
4678 14:44:59.115362 tx_first_pass[0][0][1] = 0
4679 14:44:59.118700 tx_last_pass[0][0][1] = 0
4680 14:44:59.118780 tx_win_center[0][0][2] = 0
4681 14:44:59.121866 tx_first_pass[0][0][2] = 0
4682 14:44:59.125632 tx_last_pass[0][0][2] = 0
4683 14:44:59.125712 tx_win_center[0][0][3] = 0
4684 14:44:59.128682 tx_first_pass[0][0][3] = 0
4685 14:44:59.132381 tx_last_pass[0][0][3] = 0
4686 14:44:59.135617 tx_win_center[0][0][4] = 0
4687 14:44:59.135698 tx_first_pass[0][0][4] = 0
4688 14:44:59.138543 tx_last_pass[0][0][4] = 0
4689 14:44:59.142013 tx_win_center[0][0][5] = 0
4690 14:44:59.145540 tx_first_pass[0][0][5] = 0
4691 14:44:59.145621 tx_last_pass[0][0][5] = 0
4692 14:44:59.148674 tx_win_center[0][0][6] = 0
4693 14:44:59.151951 tx_first_pass[0][0][6] = 0
4694 14:44:59.152039 tx_last_pass[0][0][6] = 0
4695 14:44:59.155412 tx_win_center[0][0][7] = 0
4696 14:44:59.158933 tx_first_pass[0][0][7] = 0
4697 14:44:59.162323 tx_last_pass[0][0][7] = 0
4698 14:44:59.162403 tx_win_center[0][0][8] = 0
4699 14:44:59.165296 tx_first_pass[0][0][8] = 0
4700 14:44:59.168851 tx_last_pass[0][0][8] = 0
4701 14:44:59.172399 tx_win_center[0][0][9] = 0
4702 14:44:59.172481 tx_first_pass[0][0][9] = 0
4703 14:44:59.175623 tx_last_pass[0][0][9] = 0
4704 14:44:59.178665 tx_win_center[0][0][10] = 0
4705 14:44:59.178746 tx_first_pass[0][0][10] = 0
4706 14:44:59.181990 tx_last_pass[0][0][10] = 0
4707 14:44:59.185550 tx_win_center[0][0][11] = 0
4708 14:44:59.188683 tx_first_pass[0][0][11] = 0
4709 14:44:59.188754 tx_last_pass[0][0][11] = 0
4710 14:44:59.192117 tx_win_center[0][0][12] = 0
4711 14:44:59.195460 tx_first_pass[0][0][12] = 0
4712 14:44:59.198771 tx_last_pass[0][0][12] = 0
4713 14:44:59.198839 tx_win_center[0][0][13] = 0
4714 14:44:59.202126 tx_first_pass[0][0][13] = 0
4715 14:44:59.205220 tx_last_pass[0][0][13] = 0
4716 14:44:59.208999 tx_win_center[0][0][14] = 0
4717 14:44:59.209078 tx_first_pass[0][0][14] = 0
4718 14:44:59.212020 tx_last_pass[0][0][14] = 0
4719 14:44:59.215506 tx_win_center[0][0][15] = 0
4720 14:44:59.218944 tx_first_pass[0][0][15] = 0
4721 14:44:59.219024 tx_last_pass[0][0][15] = 0
4722 14:44:59.222623 tx_win_center[0][1][0] = 0
4723 14:44:59.225139 tx_first_pass[0][1][0] = 0
4724 14:44:59.228893 tx_last_pass[0][1][0] = 0
4725 14:44:59.228973 tx_win_center[0][1][1] = 0
4726 14:44:59.232223 tx_first_pass[0][1][1] = 0
4727 14:44:59.235338 tx_last_pass[0][1][1] = 0
4728 14:44:59.238640 tx_win_center[0][1][2] = 0
4729 14:44:59.238719 tx_first_pass[0][1][2] = 0
4730 14:44:59.242077 tx_last_pass[0][1][2] = 0
4731 14:44:59.245634 tx_win_center[0][1][3] = 0
4732 14:44:59.245714 tx_first_pass[0][1][3] = 0
4733 14:44:59.249147 tx_last_pass[0][1][3] = 0
4734 14:44:59.252728 tx_win_center[0][1][4] = 0
4735 14:44:59.256144 tx_first_pass[0][1][4] = 0
4736 14:44:59.256224 tx_last_pass[0][1][4] = 0
4737 14:44:59.259695 tx_win_center[0][1][5] = 0
4738 14:44:59.262536 tx_first_pass[0][1][5] = 0
4739 14:44:59.262621 tx_last_pass[0][1][5] = 0
4740 14:44:59.265606 tx_win_center[0][1][6] = 0
4741 14:44:59.269209 tx_first_pass[0][1][6] = 0
4742 14:44:59.272316 tx_last_pass[0][1][6] = 0
4743 14:44:59.272396 tx_win_center[0][1][7] = 0
4744 14:44:59.275754 tx_first_pass[0][1][7] = 0
4745 14:44:59.278693 tx_last_pass[0][1][7] = 0
4746 14:44:59.282212 tx_win_center[0][1][8] = 0
4747 14:44:59.282292 tx_first_pass[0][1][8] = 0
4748 14:44:59.285209 tx_last_pass[0][1][8] = 0
4749 14:44:59.288706 tx_win_center[0][1][9] = 0
4750 14:44:59.288785 tx_first_pass[0][1][9] = 0
4751 14:44:59.291954 tx_last_pass[0][1][9] = 0
4752 14:44:59.295254 tx_win_center[0][1][10] = 0
4753 14:44:59.298812 tx_first_pass[0][1][10] = 0
4754 14:44:59.298892 tx_last_pass[0][1][10] = 0
4755 14:44:59.302298 tx_win_center[0][1][11] = 0
4756 14:44:59.305758 tx_first_pass[0][1][11] = 0
4757 14:44:59.308432 tx_last_pass[0][1][11] = 0
4758 14:44:59.308511 tx_win_center[0][1][12] = 0
4759 14:44:59.311793 tx_first_pass[0][1][12] = 0
4760 14:44:59.315076 tx_last_pass[0][1][12] = 0
4761 14:44:59.318507 tx_win_center[0][1][13] = 0
4762 14:44:59.321699 tx_first_pass[0][1][13] = 0
4763 14:44:59.321777 tx_last_pass[0][1][13] = 0
4764 14:44:59.324948 tx_win_center[0][1][14] = 0
4765 14:44:59.328291 tx_first_pass[0][1][14] = 0
4766 14:44:59.332012 tx_last_pass[0][1][14] = 0
4767 14:44:59.332091 tx_win_center[0][1][15] = 0
4768 14:44:59.335208 tx_first_pass[0][1][15] = 0
4769 14:44:59.338471 tx_last_pass[0][1][15] = 0
4770 14:44:59.338551 tx_win_center[1][0][0] = 0
4771 14:44:59.341732 tx_first_pass[1][0][0] = 0
4772 14:44:59.345381 tx_last_pass[1][0][0] = 0
4773 14:44:59.348145 tx_win_center[1][0][1] = 0
4774 14:44:59.348224 tx_first_pass[1][0][1] = 0
4775 14:44:59.351377 tx_last_pass[1][0][1] = 0
4776 14:44:59.354917 tx_win_center[1][0][2] = 0
4777 14:44:59.358182 tx_first_pass[1][0][2] = 0
4778 14:44:59.358277 tx_last_pass[1][0][2] = 0
4779 14:44:59.361205 tx_win_center[1][0][3] = 0
4780 14:44:59.364981 tx_first_pass[1][0][3] = 0
4781 14:44:59.368197 tx_last_pass[1][0][3] = 0
4782 14:44:59.368276 tx_win_center[1][0][4] = 0
4783 14:44:59.371645 tx_first_pass[1][0][4] = 0
4784 14:44:59.374845 tx_last_pass[1][0][4] = 0
4785 14:44:59.374925 tx_win_center[1][0][5] = 0
4786 14:44:59.377771 tx_first_pass[1][0][5] = 0
4787 14:44:59.381785 tx_last_pass[1][0][5] = 0
4788 14:44:59.384940 tx_win_center[1][0][6] = 0
4789 14:44:59.385030 tx_first_pass[1][0][6] = 0
4790 14:44:59.388192 tx_last_pass[1][0][6] = 0
4791 14:44:59.391483 tx_win_center[1][0][7] = 0
4792 14:44:59.394500 tx_first_pass[1][0][7] = 0
4793 14:44:59.394579 tx_last_pass[1][0][7] = 0
4794 14:44:59.397943 tx_win_center[1][0][8] = 0
4795 14:44:59.401086 tx_first_pass[1][0][8] = 0
4796 14:44:59.401192 tx_last_pass[1][0][8] = 0
4797 14:44:59.404744 tx_win_center[1][0][9] = 0
4798 14:44:59.408116 tx_first_pass[1][0][9] = 0
4799 14:44:59.411112 tx_last_pass[1][0][9] = 0
4800 14:44:59.411192 tx_win_center[1][0][10] = 0
4801 14:44:59.414547 tx_first_pass[1][0][10] = 0
4802 14:44:59.417737 tx_last_pass[1][0][10] = 0
4803 14:44:59.420815 tx_win_center[1][0][11] = 0
4804 14:44:59.420896 tx_first_pass[1][0][11] = 0
4805 14:44:59.424394 tx_last_pass[1][0][11] = 0
4806 14:44:59.427891 tx_win_center[1][0][12] = 0
4807 14:44:59.430800 tx_first_pass[1][0][12] = 0
4808 14:44:59.430880 tx_last_pass[1][0][12] = 0
4809 14:44:59.434433 tx_win_center[1][0][13] = 0
4810 14:44:59.437826 tx_first_pass[1][0][13] = 0
4811 14:44:59.440974 tx_last_pass[1][0][13] = 0
4812 14:44:59.441054 tx_win_center[1][0][14] = 0
4813 14:44:59.444372 tx_first_pass[1][0][14] = 0
4814 14:44:59.447831 tx_last_pass[1][0][14] = 0
4815 14:44:59.450994 tx_win_center[1][0][15] = 0
4816 14:44:59.454200 tx_first_pass[1][0][15] = 0
4817 14:44:59.454273 tx_last_pass[1][0][15] = 0
4818 14:44:59.457461 tx_win_center[1][1][0] = 0
4819 14:44:59.460819 tx_first_pass[1][1][0] = 0
4820 14:44:59.460888 tx_last_pass[1][1][0] = 0
4821 14:44:59.463863 tx_win_center[1][1][1] = 0
4822 14:44:59.467343 tx_first_pass[1][1][1] = 0
4823 14:44:59.470574 tx_last_pass[1][1][1] = 0
4824 14:44:59.470655 tx_win_center[1][1][2] = 0
4825 14:44:59.473985 tx_first_pass[1][1][2] = 0
4826 14:44:59.477246 tx_last_pass[1][1][2] = 0
4827 14:44:59.480558 tx_win_center[1][1][3] = 0
4828 14:44:59.480629 tx_first_pass[1][1][3] = 0
4829 14:44:59.483927 tx_last_pass[1][1][3] = 0
4830 14:44:59.487404 tx_win_center[1][1][4] = 0
4831 14:44:59.487480 tx_first_pass[1][1][4] = 0
4832 14:44:59.490555 tx_last_pass[1][1][4] = 0
4833 14:44:59.493994 tx_win_center[1][1][5] = 0
4834 14:44:59.497787 tx_first_pass[1][1][5] = 0
4835 14:44:59.497859 tx_last_pass[1][1][5] = 0
4836 14:44:59.500966 tx_win_center[1][1][6] = 0
4837 14:44:59.503737 tx_first_pass[1][1][6] = 0
4838 14:44:59.507085 tx_last_pass[1][1][6] = 0
4839 14:44:59.507173 tx_win_center[1][1][7] = 0
4840 14:44:59.510597 tx_first_pass[1][1][7] = 0
4841 14:44:59.513923 tx_last_pass[1][1][7] = 0
4842 14:44:59.513994 tx_win_center[1][1][8] = 0
4843 14:44:59.516960 tx_first_pass[1][1][8] = 0
4844 14:44:59.520319 tx_last_pass[1][1][8] = 0
4845 14:44:59.523802 tx_win_center[1][1][9] = 0
4846 14:44:59.523871 tx_first_pass[1][1][9] = 0
4847 14:44:59.527220 tx_last_pass[1][1][9] = 0
4848 14:44:59.530339 tx_win_center[1][1][10] = 0
4849 14:44:59.533846 tx_first_pass[1][1][10] = 0
4850 14:44:59.533913 tx_last_pass[1][1][10] = 0
4851 14:44:59.536995 tx_win_center[1][1][11] = 0
4852 14:44:59.540241 tx_first_pass[1][1][11] = 0
4853 14:44:59.543612 tx_last_pass[1][1][11] = 0
4854 14:44:59.543684 tx_win_center[1][1][12] = 0
4855 14:44:59.547092 tx_first_pass[1][1][12] = 0
4856 14:44:59.550508 tx_last_pass[1][1][12] = 0
4857 14:44:59.554183 tx_win_center[1][1][13] = 0
4858 14:44:59.554264 tx_first_pass[1][1][13] = 0
4859 14:44:59.556713 tx_last_pass[1][1][13] = 0
4860 14:44:59.560250 tx_win_center[1][1][14] = 0
4861 14:44:59.563522 tx_first_pass[1][1][14] = 0
4862 14:44:59.563601 tx_last_pass[1][1][14] = 0
4863 14:44:59.567407 tx_win_center[1][1][15] = 0
4864 14:44:59.570294 tx_first_pass[1][1][15] = 0
4865 14:44:59.573397 tx_last_pass[1][1][15] = 0
4866 14:44:59.573476 dump params rx window
4867 14:44:59.576699 rx_firspass[0][0][0] = 0
4868 14:44:59.579813 rx_lastpass[0][0][0] = 0
4869 14:44:59.579893 rx_firspass[0][0][1] = 0
4870 14:44:59.583232 rx_lastpass[0][0][1] = 0
4871 14:44:59.586506 rx_firspass[0][0][2] = 0
4872 14:44:59.586577 rx_lastpass[0][0][2] = 0
4873 14:44:59.590047 rx_firspass[0][0][3] = 0
4874 14:44:59.593203 rx_lastpass[0][0][3] = 0
4875 14:44:59.593336 rx_firspass[0][0][4] = 0
4876 14:44:59.596412 rx_lastpass[0][0][4] = 0
4877 14:44:59.600122 rx_firspass[0][0][5] = 0
4878 14:44:59.603248 rx_lastpass[0][0][5] = 0
4879 14:44:59.603318 rx_firspass[0][0][6] = 0
4880 14:44:59.606454 rx_lastpass[0][0][6] = 0
4881 14:44:59.610124 rx_firspass[0][0][7] = 0
4882 14:44:59.610203 rx_lastpass[0][0][7] = 0
4883 14:44:59.613210 rx_firspass[0][0][8] = 0
4884 14:44:59.616379 rx_lastpass[0][0][8] = 0
4885 14:44:59.616458 rx_firspass[0][0][9] = 0
4886 14:44:59.619561 rx_lastpass[0][0][9] = 0
4887 14:44:59.622941 rx_firspass[0][0][10] = 0
4888 14:44:59.626375 rx_lastpass[0][0][10] = 0
4889 14:44:59.626455 rx_firspass[0][0][11] = 0
4890 14:44:59.629835 rx_lastpass[0][0][11] = 0
4891 14:44:59.633118 rx_firspass[0][0][12] = 0
4892 14:44:59.633223 rx_lastpass[0][0][12] = 0
4893 14:44:59.636705 rx_firspass[0][0][13] = 0
4894 14:44:59.639486 rx_lastpass[0][0][13] = 0
4895 14:44:59.639565 rx_firspass[0][0][14] = 0
4896 14:44:59.643122 rx_lastpass[0][0][14] = 0
4897 14:44:59.646619 rx_firspass[0][0][15] = 0
4898 14:44:59.649829 rx_lastpass[0][0][15] = 0
4899 14:44:59.649901 rx_firspass[0][1][0] = 0
4900 14:44:59.653147 rx_lastpass[0][1][0] = 0
4901 14:44:59.656505 rx_firspass[0][1][1] = 0
4902 14:44:59.656574 rx_lastpass[0][1][1] = 0
4903 14:44:59.659830 rx_firspass[0][1][2] = 0
4904 14:44:59.662886 rx_lastpass[0][1][2] = 0
4905 14:44:59.662957 rx_firspass[0][1][3] = 0
4906 14:44:59.666527 rx_lastpass[0][1][3] = 0
4907 14:44:59.669561 rx_firspass[0][1][4] = 0
4908 14:44:59.669640 rx_lastpass[0][1][4] = 0
4909 14:44:59.673199 rx_firspass[0][1][5] = 0
4910 14:44:59.676196 rx_lastpass[0][1][5] = 0
4911 14:44:59.676275 rx_firspass[0][1][6] = 0
4912 14:44:59.679624 rx_lastpass[0][1][6] = 0
4913 14:44:59.683245 rx_firspass[0][1][7] = 0
4914 14:44:59.686375 rx_lastpass[0][1][7] = 0
4915 14:44:59.686455 rx_firspass[0][1][8] = 0
4916 14:44:59.689832 rx_lastpass[0][1][8] = 0
4917 14:44:59.693052 rx_firspass[0][1][9] = 0
4918 14:44:59.693130 rx_lastpass[0][1][9] = 0
4919 14:44:59.696158 rx_firspass[0][1][10] = 0
4920 14:44:59.699627 rx_lastpass[0][1][10] = 0
4921 14:44:59.699731 rx_firspass[0][1][11] = 0
4922 14:44:59.702882 rx_lastpass[0][1][11] = 0
4923 14:44:59.706488 rx_firspass[0][1][12] = 0
4924 14:44:59.709722 rx_lastpass[0][1][12] = 0
4925 14:44:59.709801 rx_firspass[0][1][13] = 0
4926 14:44:59.712780 rx_lastpass[0][1][13] = 0
4927 14:44:59.716271 rx_firspass[0][1][14] = 0
4928 14:44:59.716349 rx_lastpass[0][1][14] = 0
4929 14:44:59.719810 rx_firspass[0][1][15] = 0
4930 14:44:59.723418 rx_lastpass[0][1][15] = 0
4931 14:44:59.726080 rx_firspass[1][0][0] = 0
4932 14:44:59.726159 rx_lastpass[1][0][0] = 0
4933 14:44:59.729456 rx_firspass[1][0][1] = 0
4934 14:44:59.732853 rx_lastpass[1][0][1] = 0
4935 14:44:59.732934 rx_firspass[1][0][2] = 0
4936 14:44:59.736020 rx_lastpass[1][0][2] = 0
4937 14:44:59.739546 rx_firspass[1][0][3] = 0
4938 14:44:59.739626 rx_lastpass[1][0][3] = 0
4939 14:44:59.742837 rx_firspass[1][0][4] = 0
4940 14:44:59.746158 rx_lastpass[1][0][4] = 0
4941 14:44:59.746238 rx_firspass[1][0][5] = 0
4942 14:44:59.749631 rx_lastpass[1][0][5] = 0
4943 14:44:59.753219 rx_firspass[1][0][6] = 0
4944 14:44:59.753316 rx_lastpass[1][0][6] = 0
4945 14:44:59.756295 rx_firspass[1][0][7] = 0
4946 14:44:59.760079 rx_lastpass[1][0][7] = 0
4947 14:44:59.763179 rx_firspass[1][0][8] = 0
4948 14:44:59.763251 rx_lastpass[1][0][8] = 0
4949 14:44:59.766090 rx_firspass[1][0][9] = 0
4950 14:44:59.769350 rx_lastpass[1][0][9] = 0
4951 14:44:59.769430 rx_firspass[1][0][10] = 0
4952 14:44:59.772642 rx_lastpass[1][0][10] = 0
4953 14:44:59.776252 rx_firspass[1][0][11] = 0
4954 14:44:59.776331 rx_lastpass[1][0][11] = 0
4955 14:44:59.779505 rx_firspass[1][0][12] = 0
4956 14:44:59.782733 rx_lastpass[1][0][12] = 0
4957 14:44:59.785974 rx_firspass[1][0][13] = 0
4958 14:44:59.786053 rx_lastpass[1][0][13] = 0
4959 14:44:59.789397 rx_firspass[1][0][14] = 0
4960 14:44:59.793165 rx_lastpass[1][0][14] = 0
4961 14:44:59.793307 rx_firspass[1][0][15] = 0
4962 14:44:59.795957 rx_lastpass[1][0][15] = 0
4963 14:44:59.799565 rx_firspass[1][1][0] = 0
4964 14:44:59.802885 rx_lastpass[1][1][0] = 0
4965 14:44:59.802965 rx_firspass[1][1][1] = 0
4966 14:44:59.805980 rx_lastpass[1][1][1] = 0
4967 14:44:59.809757 rx_firspass[1][1][2] = 0
4968 14:44:59.809836 rx_lastpass[1][1][2] = 0
4969 14:44:59.813001 rx_firspass[1][1][3] = 0
4970 14:44:59.816138 rx_lastpass[1][1][3] = 0
4971 14:44:59.816217 rx_firspass[1][1][4] = 0
4972 14:44:59.819778 rx_lastpass[1][1][4] = 0
4973 14:44:59.823006 rx_firspass[1][1][5] = 0
4974 14:44:59.823091 rx_lastpass[1][1][5] = 0
4975 14:44:59.826047 rx_firspass[1][1][6] = 0
4976 14:44:59.829341 rx_lastpass[1][1][6] = 0
4977 14:44:59.829420 rx_firspass[1][1][7] = 0
4978 14:44:59.832641 rx_lastpass[1][1][7] = 0
4979 14:44:59.836217 rx_firspass[1][1][8] = 0
4980 14:44:59.836301 rx_lastpass[1][1][8] = 0
4981 14:44:59.839694 rx_firspass[1][1][9] = 0
4982 14:44:59.842672 rx_lastpass[1][1][9] = 0
4983 14:44:59.846185 rx_firspass[1][1][10] = 0
4984 14:44:59.846265 rx_lastpass[1][1][10] = 0
4985 14:44:59.849443 rx_firspass[1][1][11] = 0
4986 14:44:59.852980 rx_lastpass[1][1][11] = 0
4987 14:44:59.853064 rx_firspass[1][1][12] = 0
4988 14:44:59.856033 rx_lastpass[1][1][12] = 0
4989 14:44:59.859512 rx_firspass[1][1][13] = 0
4990 14:44:59.863298 rx_lastpass[1][1][13] = 0
4991 14:44:59.863377 rx_firspass[1][1][14] = 0
4992 14:44:59.866059 rx_lastpass[1][1][14] = 0
4993 14:44:59.869283 rx_firspass[1][1][15] = 0
4994 14:44:59.869377 rx_lastpass[1][1][15] = 0
4995 14:44:59.873071 dump params clk_delay
4996 14:44:59.873151 clk_delay[0] = 0
4997 14:44:59.876116 clk_delay[1] = 0
4998 14:44:59.876195 dump params dqs_delay
4999 14:44:59.879417 dqs_delay[0][0] = 0
5000 14:44:59.882658 dqs_delay[0][1] = 0
5001 14:44:59.882738 dqs_delay[1][0] = 0
5002 14:44:59.886562 dqs_delay[1][1] = 0
5003 14:44:59.889206 dump params delay_cell_unit = 762
5004 14:44:59.889335 mt_set_emi_preloader end
5005 14:44:59.896173 [mt_mem_init] dram size: 0x100000000, rank number: 2
5006 14:44:59.899405 [complex_mem_test] start addr:0x40000000, len:20480
5007 14:44:59.936540 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
5008 14:44:59.943011 [complex_mem_test] start addr:0x80000000, len:20480
5009 14:44:59.978466 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
5010 14:44:59.985094 [complex_mem_test] start addr:0xc0000000, len:20480
5011 14:45:00.021013 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
5012 14:45:00.027265 [complex_mem_test] start addr:0x56000000, len:8192
5013 14:45:00.044144 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
5014 14:45:00.044228 ddr_geometry:1
5015 14:45:00.050745 [complex_mem_test] start addr:0x80000000, len:8192
5016 14:45:00.068043 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
5017 14:45:00.071128 dram_init: dram init end (result: 0)
5018 14:45:00.078188 Successfully loaded DRAM blobs and ran DRAM calibration
5019 14:45:00.087913 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
5020 14:45:00.087995 CBMEM:
5021 14:45:00.090926 IMD: root @ 00000000fffff000 254 entries.
5022 14:45:00.094693 IMD: root @ 00000000ffffec00 62 entries.
5023 14:45:00.101401 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
5024 14:45:00.108300 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
5025 14:45:00.111532 in-header: 03 a1 00 00 08 00 00 00
5026 14:45:00.115039 in-data: 84 60 60 10 00 00 00 00
5027 14:45:00.118318 Chrome EC: clear events_b mask to 0x0000000020004000
5028 14:45:00.125782 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
5029 14:45:00.128667 in-header: 03 fd 00 00 00 00 00 00
5030 14:45:00.128746 in-data:
5031 14:45:00.135687 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5032 14:45:00.135768 CBFS @ 21000 size 3d4000
5033 14:45:00.142405 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5034 14:45:00.145485 CBFS: Locating 'fallback/ramstage'
5035 14:45:00.148699 CBFS: Found @ offset 10d40 size d563
5036 14:45:00.169867 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
5037 14:45:00.181789 Accumulated console time in romstage 12820 ms
5038 14:45:00.181872
5039 14:45:00.181935
5040 14:45:00.191854 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
5041 14:45:00.195399 ARM64: Exception handlers installed.
5042 14:45:00.195479 ARM64: Testing exception
5043 14:45:00.198544 ARM64: Done test exception
5044 14:45:00.201890 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
5045 14:45:00.205077 Manufacturer: ef
5046 14:45:00.208446 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
5047 14:45:00.215075 WARNING: RO_VPD is uninitialized or empty.
5048 14:45:00.218811 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5049 14:45:00.221577 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5050 14:45:00.231335 read SPI 0x550600 0x3a00: 4532 us, 3276 KB/s, 26.208 Mbps
5051 14:45:00.235051 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5052 14:45:00.242050 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5053 14:45:00.242130 Enumerating buses...
5054 14:45:00.248436 Show all devs... Before device enumeration.
5055 14:45:00.248516 Root Device: enabled 1
5056 14:45:00.251534 CPU_CLUSTER: 0: enabled 1
5057 14:45:00.251613 CPU: 00: enabled 1
5058 14:45:00.254956 Compare with tree...
5059 14:45:00.258047 Root Device: enabled 1
5060 14:45:00.258126 CPU_CLUSTER: 0: enabled 1
5061 14:45:00.261680 CPU: 00: enabled 1
5062 14:45:00.264689 Root Device scanning...
5063 14:45:00.264768 root_dev_scan_bus for Root Device
5064 14:45:00.267942 CPU_CLUSTER: 0 enabled
5065 14:45:00.271662 root_dev_scan_bus for Root Device done
5066 14:45:00.277894 scan_bus: scanning of bus Root Device took 10690 usecs
5067 14:45:00.277975 done
5068 14:45:00.281144 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5069 14:45:00.284841 Allocating resources...
5070 14:45:00.284920 Reading resources...
5071 14:45:00.288254 Root Device read_resources bus 0 link: 0
5072 14:45:00.294922 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5073 14:45:00.295003 CPU: 00 missing read_resources
5074 14:45:00.301234 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5075 14:45:00.304390 Root Device read_resources bus 0 link: 0 done
5076 14:45:00.308230 Done reading resources.
5077 14:45:00.311316 Show resources in subtree (Root Device)...After reading.
5078 14:45:00.314712 Root Device child on link 0 CPU_CLUSTER: 0
5079 14:45:00.318384 CPU_CLUSTER: 0 child on link 0 CPU: 00
5080 14:45:00.327982 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5081 14:45:00.328063 CPU: 00
5082 14:45:00.331213 Setting resources...
5083 14:45:00.335159 Root Device assign_resources, bus 0 link: 0
5084 14:45:00.337862 CPU_CLUSTER: 0 missing set_resources
5085 14:45:00.341053 Root Device assign_resources, bus 0 link: 0
5086 14:45:00.345036 Done setting resources.
5087 14:45:00.351305 Show resources in subtree (Root Device)...After assigning values.
5088 14:45:00.354784 Root Device child on link 0 CPU_CLUSTER: 0
5089 14:45:00.358150 CPU_CLUSTER: 0 child on link 0 CPU: 00
5090 14:45:00.364599 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5091 14:45:00.368046 CPU: 00
5092 14:45:00.371465 Done allocating resources.
5093 14:45:00.374834 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5094 14:45:00.378110 Enabling resources...
5095 14:45:00.378189 done.
5096 14:45:00.381574 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5097 14:45:00.384458 Initializing devices...
5098 14:45:00.384538 Root Device init ...
5099 14:45:00.388154 mainboard_init: Starting display init.
5100 14:45:00.391723 ADC[4]: Raw value=76850 ID=0
5101 14:45:00.414305 anx7625_power_on_init: Init interface.
5102 14:45:00.417446 anx7625_disable_pd_protocol: Disabled PD feature.
5103 14:45:00.424219 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5104 14:45:00.470902 anx7625_start_dp_work: Secure OCM version=00
5105 14:45:00.474503 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5106 14:45:00.491147 sp_tx_get_edid_block: EDID Block = 1
5107 14:45:00.608529 Extracted contents:
5108 14:45:00.612026 header: 00 ff ff ff ff ff ff 00
5109 14:45:00.615216 serial number: 06 af 5c 14 00 00 00 00 00 1a
5110 14:45:00.618440 version: 01 04
5111 14:45:00.621744 basic params: 95 1a 0e 78 02
5112 14:45:00.625006 chroma info: 99 85 95 55 56 92 28 22 50 54
5113 14:45:00.628337 established: 00 00 00
5114 14:45:00.635180 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5115 14:45:00.638389 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5116 14:45:00.645183 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5117 14:45:00.651677 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5118 14:45:00.658318 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5119 14:45:00.661739 extensions: 00
5120 14:45:00.661813 checksum: ae
5121 14:45:00.661875
5122 14:45:00.664905 Manufacturer: AUO Model 145c Serial Number 0
5123 14:45:00.668449 Made week 0 of 2016
5124 14:45:00.668522 EDID version: 1.4
5125 14:45:00.672174 Digital display
5126 14:45:00.675264 6 bits per primary color channel
5127 14:45:00.675343 DisplayPort interface
5128 14:45:00.678669 Maximum image size: 26 cm x 14 cm
5129 14:45:00.682006 Gamma: 220%
5130 14:45:00.682077 Check DPMS levels
5131 14:45:00.685102 Supported color formats: RGB 4:4:4
5132 14:45:00.688506 First detailed timing is preferred timing
5133 14:45:00.691937 Established timings supported:
5134 14:45:00.695253 Standard timings supported:
5135 14:45:00.695360 Detailed timings
5136 14:45:00.701827 Hex of detail: ce1d56ea50001a3030204600009010000018
5137 14:45:00.705144 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5138 14:45:00.708415 0556 0586 05a6 0640 hborder 0
5139 14:45:00.711931 0300 0304 030a 031a vborder 0
5140 14:45:00.715050 -hsync -vsync
5141 14:45:00.719045 Did detailed timing
5142 14:45:00.721967 Hex of detail: 0000000f0000000000000000000000000020
5143 14:45:00.724760 Manufacturer-specified data, tag 15
5144 14:45:00.728424 Hex of detail: 000000fe0041554f0a202020202020202020
5145 14:45:00.731923 ASCII string: AUO
5146 14:45:00.735081 Hex of detail: 000000fe004231313658414230312e34200a
5147 14:45:00.738636 ASCII string: B116XAB01.4
5148 14:45:00.738709 Checksum
5149 14:45:00.742380 Checksum: 0xae (valid)
5150 14:45:00.745177 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5151 14:45:00.748436 DSI data_rate: 457800000 bps
5152 14:45:00.755514 anx7625_parse_edid: set default k value to 0x3d for panel
5153 14:45:00.759031 anx7625_parse_edid: pixelclock(76300).
5154 14:45:00.762454 hactive(1366), hsync(32), hfp(48), hbp(154)
5155 14:45:00.765727 vactive(768), vsync(6), vfp(4), vbp(16)
5156 14:45:00.769329 anx7625_dsi_config: config dsi.
5157 14:45:00.777067 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5158 14:45:00.798061 anx7625_dsi_config: success to config DSI
5159 14:45:00.801675 anx7625_dp_start: MIPI phy setup OK.
5160 14:45:00.804476 [SSUSB] Setting up USB HOST controller...
5161 14:45:00.808406 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5162 14:45:00.808485 [SSUSB] phy power-on done.
5163 14:45:00.815132 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5164 14:45:00.818373 in-header: 03 fc 01 00 00 00 00 00
5165 14:45:00.818453 in-data:
5166 14:45:00.821496 handle_proto3_response: EC response with error code: 1
5167 14:45:00.824868 SPM: pcm index = 1
5168 14:45:00.828398 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5169 14:45:00.831725 CBFS @ 21000 size 3d4000
5170 14:45:00.838136 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5171 14:45:00.842046 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5172 14:45:00.844887 CBFS: Found @ offset 1e7c0 size 1026
5173 14:45:00.851834 read SPI 0x3f808 0x1026: 1272 us, 3250 KB/s, 26.000 Mbps
5174 14:45:00.854821 SPM: binary array size = 2988
5175 14:45:00.858140 SPM: version = pcm_allinone_v1.17.2_20180829
5176 14:45:00.861488 SPM binary loaded in 32 msecs
5177 14:45:00.868903 spm_kick_im_to_fetch: ptr = 000000004021eec2
5178 14:45:00.872432 spm_kick_im_to_fetch: len = 2988
5179 14:45:00.872533 SPM: spm_kick_pcm_to_run
5180 14:45:00.875713 SPM: spm_kick_pcm_to_run done
5181 14:45:00.878863 SPM: spm_init done in 52 msecs
5182 14:45:00.882237 Root Device init finished in 494989 usecs
5183 14:45:00.885555 CPU_CLUSTER: 0 init ...
5184 14:45:00.895693 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5185 14:45:00.898942 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5186 14:45:00.902247 CBFS @ 21000 size 3d4000
5187 14:45:00.905761 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5188 14:45:00.908825 CBFS: Locating 'sspm.bin'
5189 14:45:00.912183 CBFS: Found @ offset 208c0 size 41cb
5190 14:45:00.922411 read SPI 0x418f8 0x41cb: 5141 us, 3276 KB/s, 26.208 Mbps
5191 14:45:00.930462 CPU_CLUSTER: 0 init finished in 42803 usecs
5192 14:45:00.930543 Devices initialized
5193 14:45:00.934088 Show all devs... After init.
5194 14:45:00.936766 Root Device: enabled 1
5195 14:45:00.936846 CPU_CLUSTER: 0: enabled 1
5196 14:45:00.940432 CPU: 00: enabled 1
5197 14:45:00.943698 BS: BS_DEV_INIT times (ms): entry 0 run 224 exit 0
5198 14:45:00.946972 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5199 14:45:00.950117 ELOG: NV offset 0x558000 size 0x1000
5200 14:45:00.957811 read SPI 0x558000 0x1000: 1259 us, 3253 KB/s, 26.024 Mbps
5201 14:45:00.964217 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5202 14:45:00.967506 ELOG: Event(17) added with size 13 at 2024-06-04 14:45:00 UTC
5203 14:45:00.970992 out: cmd=0x121: 03 db 21 01 00 00 00 00
5204 14:45:00.974438 in-header: 03 70 00 00 2c 00 00 00
5205 14:45:00.987631 in-data: 13 48 00 00 00 00 00 00 02 10 00 00 06 80 00 00 fd 84 07 00 06 80 00 00 e1 3a 08 00 06 80 00 00 2f 3b 01 00 06 80 00 00 26 98 08 00
5206 14:45:00.991246 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5207 14:45:00.994171 in-header: 03 19 00 00 08 00 00 00
5208 14:45:00.998061 in-data: a2 e0 47 00 13 00 00 00
5209 14:45:01.000810 Chrome EC: UHEPI supported
5210 14:45:01.007454 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5211 14:45:01.011143 in-header: 03 e1 00 00 08 00 00 00
5212 14:45:01.014432 in-data: 84 20 60 10 00 00 00 00
5213 14:45:01.017595 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5214 14:45:01.024239 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5215 14:45:01.027538 in-header: 03 e1 00 00 08 00 00 00
5216 14:45:01.030799 in-data: 84 20 60 10 00 00 00 00
5217 14:45:01.037417 ELOG: Event(A1) added with size 10 at 2024-06-04 14:45:00 UTC
5218 14:45:01.044260 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5219 14:45:01.047515 ELOG: Event(A0) added with size 9 at 2024-06-04 14:45:00 UTC
5220 14:45:01.054120 elog_add_boot_reason: Logged dev mode boot
5221 14:45:01.054200 Finalize devices...
5222 14:45:01.057438 Devices finalized
5223 14:45:01.060852 BS: BS_POST_DEVICE times (ms): entry 3 run 0 exit 0
5224 14:45:01.064169 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5225 14:45:01.070792 ELOG: Event(91) added with size 10 at 2024-06-04 14:45:00 UTC
5226 14:45:01.074347 Writing coreboot table at 0xffeda000
5227 14:45:01.077590 0. 0000000000114000-000000000011efff: RAMSTAGE
5228 14:45:01.085109 1. 0000000040000000-000000004023cfff: RAMSTAGE
5229 14:45:01.088016 2. 000000004023d000-00000000545fffff: RAM
5230 14:45:01.091458 3. 0000000054600000-000000005465ffff: BL31
5231 14:45:01.094457 4. 0000000054660000-00000000ffed9fff: RAM
5232 14:45:01.101130 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5233 14:45:01.104498 6. 0000000100000000-000000013fffffff: RAM
5234 14:45:01.107826 Passing 5 GPIOs to payload:
5235 14:45:01.110853 NAME | PORT | POLARITY | VALUE
5236 14:45:01.114646 write protect | 0x00000096 | low | high
5237 14:45:01.121066 EC in RW | 0x000000b1 | high | undefined
5238 14:45:01.124578 EC interrupt | 0x00000097 | low | undefined
5239 14:45:01.127679 TPM interrupt | 0x00000099 | high | undefined
5240 14:45:01.134152 speaker enable | 0x000000af | high | undefined
5241 14:45:01.137516 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5242 14:45:01.141033 in-header: 03 f7 00 00 02 00 00 00
5243 14:45:01.141113 in-data: 04 00
5244 14:45:01.144209 Board ID: 4
5245 14:45:01.147966 ADC[3]: Raw value=1034985 ID=8
5246 14:45:01.148046 RAM code: 8
5247 14:45:01.148110 SKU ID: 16
5248 14:45:01.150759 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5249 14:45:01.154532 CBFS @ 21000 size 3d4000
5250 14:45:01.160694 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5251 14:45:01.167880 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum 3897
5252 14:45:01.167961 coreboot table: 940 bytes.
5253 14:45:01.170710 IMD ROOT 0. 00000000fffff000 00001000
5254 14:45:01.177536 IMD SMALL 1. 00000000ffffe000 00001000
5255 14:45:01.181019 CONSOLE 2. 00000000fffde000 00020000
5256 14:45:01.184437 FMAP 3. 00000000fffdd000 0000047c
5257 14:45:01.187565 TIME STAMP 4. 00000000fffdc000 00000910
5258 14:45:01.190694 RAMOOPS 5. 00000000ffedc000 00100000
5259 14:45:01.194502 COREBOOT 6. 00000000ffeda000 00002000
5260 14:45:01.194585 IMD small region:
5261 14:45:01.201481 IMD ROOT 0. 00000000ffffec00 00000400
5262 14:45:01.204358 VBOOT WORK 1. 00000000ffffeb00 00000100
5263 14:45:01.207714 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5264 14:45:01.210934 VPD 3. 00000000ffffea60 0000006c
5265 14:45:01.214155 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5266 14:45:01.220679 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5267 14:45:01.224174 in-header: 03 e1 00 00 08 00 00 00
5268 14:45:01.227457 in-data: 84 20 60 10 00 00 00 00
5269 14:45:01.234366 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5270 14:45:01.234448 CBFS @ 21000 size 3d4000
5271 14:45:01.240784 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5272 14:45:01.244530 CBFS: Locating 'fallback/payload'
5273 14:45:01.252064 CBFS: Found @ offset dc040 size 439a0
5274 14:45:01.340115 read SPI 0xfd078 0x439a0: 84379 us, 3281 KB/s, 26.248 Mbps
5275 14:45:01.343120 Checking segment from ROM address 0x0000000040003a00
5276 14:45:01.349793 Checking segment from ROM address 0x0000000040003a1c
5277 14:45:01.353116 Loading segment from ROM address 0x0000000040003a00
5278 14:45:01.356297 code (compression=0)
5279 14:45:01.366400 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5280 14:45:01.373184 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5281 14:45:01.376086 it's not compressed!
5282 14:45:01.379544 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5283 14:45:01.386051 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5284 14:45:01.394734 Loading segment from ROM address 0x0000000040003a1c
5285 14:45:01.397612 Entry Point 0x0000000080000000
5286 14:45:01.397736 Loaded segments
5287 14:45:01.403807 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5288 14:45:01.407583 Jumping to boot code at 0000000080000000(00000000ffeda000)
5289 14:45:01.417400 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5290 14:45:01.420936 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5291 14:45:01.424551 CBFS @ 21000 size 3d4000
5292 14:45:01.431064 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5293 14:45:01.434663 CBFS: Locating 'fallback/bl31'
5294 14:45:01.437671 CBFS: Found @ offset 36dc0 size 5820
5295 14:45:01.448760 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5296 14:45:01.451763 Checking segment from ROM address 0x0000000040003a00
5297 14:45:01.458607 Checking segment from ROM address 0x0000000040003a1c
5298 14:45:01.461635 Loading segment from ROM address 0x0000000040003a00
5299 14:45:01.465148 code (compression=1)
5300 14:45:01.471570 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5301 14:45:01.481506 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5302 14:45:01.481940 using LZMA
5303 14:45:01.490532 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5304 14:45:01.496828 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5305 14:45:01.500280 Loading segment from ROM address 0x0000000040003a1c
5306 14:45:01.503536 Entry Point 0x0000000054601000
5307 14:45:01.503963 Loaded segments
5308 14:45:01.506827 NOTICE: MT8183 bl31_setup
5309 14:45:01.513940 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5310 14:45:01.517079 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5311 14:45:01.520732 INFO: [DEVAPC] dump DEVAPC registers:
5312 14:45:01.530860 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5313 14:45:01.537404 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5314 14:45:01.547421 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5315 14:45:01.553739 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5316 14:45:01.563600 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5317 14:45:01.570217 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5318 14:45:01.580135 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5319 14:45:01.586481 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5320 14:45:01.593573 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5321 14:45:01.603214 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5322 14:45:01.610398 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5323 14:45:01.619737 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5324 14:45:01.626507 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5325 14:45:01.633227 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5326 14:45:01.643668 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5327 14:45:01.650252 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5328 14:45:01.657089 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5329 14:45:01.663672 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5330 14:45:01.670224 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5331 14:45:01.680407 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5332 14:45:01.686895 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5333 14:45:01.693223 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5334 14:45:01.696680 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5335 14:45:01.699904 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5336 14:45:01.703500 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5337 14:45:01.706425 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5338 14:45:01.709776 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5339 14:45:01.716706 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5340 14:45:01.719894 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5341 14:45:01.723123 WARNING: region 0:
5342 14:45:01.726788 WARNING: apc:0x168, sa:0x0, ea:0xfff
5343 14:45:01.729930 WARNING: region 1:
5344 14:45:01.732987 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5345 14:45:01.733067 WARNING: region 2:
5346 14:45:01.736227 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5347 14:45:01.739540 WARNING: region 3:
5348 14:45:01.742856 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5349 14:45:01.742953 WARNING: region 4:
5350 14:45:01.749769 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5351 14:45:01.749850 WARNING: region 5:
5352 14:45:01.752935 WARNING: apc:0x0, sa:0x0, ea:0x0
5353 14:45:01.756569 WARNING: region 6:
5354 14:45:01.756649 WARNING: apc:0x0, sa:0x0, ea:0x0
5355 14:45:01.759671 WARNING: region 7:
5356 14:45:01.763226 WARNING: apc:0x0, sa:0x0, ea:0x0
5357 14:45:01.769471 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5358 14:45:01.773101 INFO: SPM: enable SPMC mode
5359 14:45:01.776082 NOTICE: spm_boot_init() start
5360 14:45:01.779631 NOTICE: spm_boot_init() end
5361 14:45:01.782655 INFO: BL31: Initializing runtime services
5362 14:45:01.786452 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5363 14:45:01.792796 INFO: BL31: Preparing for EL3 exit to normal world
5364 14:45:01.796071 INFO: Entry point address = 0x80000000
5365 14:45:01.799273 INFO: SPSR = 0x8
5366 14:45:01.819971
5367 14:45:01.820049
5368 14:45:01.820111
5369 14:45:01.820552 end: 2.2.3 depthcharge-start (duration 00:00:10) [common]
5370 14:45:01.820648 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
5371 14:45:01.820730 Setting prompt string to ['jacuzzi:']
5372 14:45:01.820813 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:26)
5373 14:45:01.823588 Starting depthcharge on Juniper...
5374 14:45:01.823663
5375 14:45:01.826703 vboot_handoff: creating legacy vboot_handoff structure
5376 14:45:01.826774
5377 14:45:01.829882 ec_init(0): CrosEC protocol v3 supported (544, 544)
5378 14:45:01.829951
5379 14:45:01.833180 Wipe memory regions:
5380 14:45:01.833254
5381 14:45:01.837086 [0x00000040000000, 0x00000054600000)
5382 14:45:01.879693
5383 14:45:01.879794 [0x00000054660000, 0x00000080000000)
5384 14:45:01.970833
5385 14:45:01.970937 [0x000000811994a0, 0x000000ffeda000)
5386 14:45:02.230230
5387 14:45:02.230377 [0x00000100000000, 0x00000140000000)
5388 14:45:02.362756
5389 14:45:02.366060 Initializing XHCI USB controller at 0x11200000.
5390 14:45:02.388628
5391 14:45:02.392101 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5392 14:45:02.392184
5393 14:45:02.392248
5394 14:45:02.392527 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5396 14:45:02.492839 jacuzzi: tftpboot 192.168.201.1 14166990/tftp-deploy-muq91wc3/kernel/image.itb 14166990/tftp-deploy-muq91wc3/kernel/cmdline
5397 14:45:02.492971 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5398 14:45:02.493061 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:25)
5399 14:45:02.497617 tftpboot 192.168.201.1 14166990/tftp-deploy-muq91wc3/kernel/image.ittp-deploy-muq91wc3/kernel/cmdline
5400 14:45:02.497701
5401 14:45:02.497764 Waiting for link
5402 14:45:02.902762
5403 14:45:02.902914 R8152: Initializing
5404 14:45:02.902982
5405 14:45:02.906463 Version 9 (ocp_data = 6010)
5406 14:45:02.906544
5407 14:45:02.909514 R8152: Done initializing
5408 14:45:02.909594
5409 14:45:02.909656 Adding net device
5410 14:45:03.294880
5411 14:45:03.295018 done.
5412 14:45:03.295092
5413 14:45:03.295152 MAC: 00:e0:4c:71:a7:1f
5414 14:45:03.295211
5415 14:45:03.297865 Sending DHCP discover... done.
5416 14:45:03.297945
5417 14:45:03.301225 Waiting for reply... done.
5418 14:45:03.301349
5419 14:45:03.304483 Sending DHCP request... done.
5420 14:45:03.304556
5421 14:45:03.309885 Waiting for reply... done.
5422 14:45:03.309959
5423 14:45:03.310019 My ip is 192.168.201.23
5424 14:45:03.310076
5425 14:45:03.313072 The DHCP server ip is 192.168.201.1
5426 14:45:03.313142
5427 14:45:03.319545 TFTP server IP predefined by user: 192.168.201.1
5428 14:45:03.319625
5429 14:45:03.326153 Bootfile predefined by user: 14166990/tftp-deploy-muq91wc3/kernel/image.itb
5430 14:45:03.326229
5431 14:45:03.326290 Sending tftp read request... done.
5432 14:45:03.329572
5433 14:45:03.333059 Waiting for the transfer...
5434 14:45:03.333141
5435 14:45:03.582313 00000000 ################################################################
5436 14:45:03.582444
5437 14:45:03.832393 00080000 ################################################################
5438 14:45:03.832556
5439 14:45:04.080910 00100000 ################################################################
5440 14:45:04.081044
5441 14:45:04.330668 00180000 ################################################################
5442 14:45:04.330810
5443 14:45:04.581818 00200000 ################################################################
5444 14:45:04.581976
5445 14:45:04.830847 00280000 ################################################################
5446 14:45:04.830998
5447 14:45:05.080186 00300000 ################################################################
5448 14:45:05.080321
5449 14:45:05.328774 00380000 ################################################################
5450 14:45:05.328918
5451 14:45:05.582266 00400000 ################################################################
5452 14:45:05.582428
5453 14:45:05.834966 00480000 ################################################################
5454 14:45:05.835100
5455 14:45:06.087254 00500000 ################################################################
5456 14:45:06.087395
5457 14:45:06.341848 00580000 ################################################################
5458 14:45:06.341981
5459 14:45:06.592511 00600000 ################################################################
5460 14:45:06.592656
5461 14:45:06.839897 00680000 ################################################################
5462 14:45:06.840030
5463 14:45:07.092525 00700000 ################################################################
5464 14:45:07.092665
5465 14:45:07.346261 00780000 ################################################################
5466 14:45:07.346399
5467 14:45:07.601472 00800000 ################################################################
5468 14:45:07.601624
5469 14:45:07.872103 00880000 ################################################################
5470 14:45:07.872244
5471 14:45:08.134220 00900000 ################################################################
5472 14:45:08.134363
5473 14:45:08.388221 00980000 ################################################################
5474 14:45:08.388364
5475 14:45:08.649031 00a00000 ################################################################
5476 14:45:08.649192
5477 14:45:08.907720 00a80000 ################################################################
5478 14:45:08.907857
5479 14:45:09.176578 00b00000 ################################################################
5480 14:45:09.176716
5481 14:45:09.432341 00b80000 ################################################################
5482 14:45:09.432485
5483 14:45:09.683358 00c00000 ################################################################
5484 14:45:09.683487
5485 14:45:09.943106 00c80000 ################################################################
5486 14:45:09.943238
5487 14:45:10.203257 00d00000 ################################################################
5488 14:45:10.203396
5489 14:45:10.472682 00d80000 ################################################################
5490 14:45:10.472817
5491 14:45:10.732363 00e00000 ################################################################
5492 14:45:10.732530
5493 14:45:10.988969 00e80000 ################################################################
5494 14:45:10.989100
5495 14:45:11.245358 00f00000 ################################################################
5496 14:45:11.245492
5497 14:45:11.501242 00f80000 ################################################################
5498 14:45:11.501407
5499 14:45:11.780533 01000000 ################################################################
5500 14:45:11.780685
5501 14:45:12.046063 01080000 ################################################################
5502 14:45:12.046226
5503 14:45:12.302333 01100000 ################################################################
5504 14:45:12.302466
5505 14:45:12.558096 01180000 ################################################################
5506 14:45:12.558236
5507 14:45:12.839725 01200000 ################################################################
5508 14:45:12.839882
5509 14:45:13.100192 01280000 ################################################################
5510 14:45:13.100348
5511 14:45:13.353631 01300000 ################################################################
5512 14:45:13.353755
5513 14:45:13.616901 01380000 ################################################################
5514 14:45:13.617034
5515 14:45:13.869935 01400000 ################################################################
5516 14:45:13.870075
5517 14:45:14.121429 01480000 ################################################################
5518 14:45:14.121571
5519 14:45:14.381460 01500000 ################################################################
5520 14:45:14.381599
5521 14:45:14.640407 01580000 ################################################################
5522 14:45:14.640536
5523 14:45:14.905759 01600000 ################################################################
5524 14:45:14.905906
5525 14:45:15.162726 01680000 ################################################################
5526 14:45:15.162860
5527 14:45:15.417799 01700000 ################################################################
5528 14:45:15.417945
5529 14:45:15.675194 01780000 ################################################################
5530 14:45:15.675360
5531 14:45:15.932522 01800000 ################################################################
5532 14:45:15.932692
5533 14:45:16.187606 01880000 ################################################################
5534 14:45:16.187734
5535 14:45:16.447760 01900000 ################################################################
5536 14:45:16.447906
5537 14:45:16.711390 01980000 ################################################################
5538 14:45:16.711518
5539 14:45:16.981705 01a00000 ################################################################
5540 14:45:16.981835
5541 14:45:17.247628 01a80000 ################################################################
5542 14:45:17.247754
5543 14:45:17.527183 01b00000 ################################################################
5544 14:45:17.527343
5545 14:45:17.801543 01b80000 ################################################################
5546 14:45:17.801670
5547 14:45:18.090255 01c00000 ################################################################
5548 14:45:18.090403
5549 14:45:18.374451 01c80000 ################################################################
5550 14:45:18.374576
5551 14:45:18.654480 01d00000 ################################################################
5552 14:45:18.654626
5553 14:45:18.919613 01d80000 ################################################################
5554 14:45:18.919755
5555 14:45:19.114107 01e00000 ############################################### done.
5556 14:45:19.114246
5557 14:45:19.117011 The bootfile was 31840590 bytes long.
5558 14:45:19.117127
5559 14:45:19.120206 Sending tftp read request... done.
5560 14:45:19.120292
5561 14:45:19.120360 Waiting for the transfer...
5562 14:45:19.120423
5563 14:45:19.123549 00000000 # done.
5564 14:45:19.123643
5565 14:45:19.130277 Command line loaded dynamically from TFTP file: 14166990/tftp-deploy-muq91wc3/kernel/cmdline
5566 14:45:19.130457
5567 14:45:19.156963 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14166990/extract-nfsrootfs-830ytlfh,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5568 14:45:19.157253
5569 14:45:19.157435 Loading FIT.
5570 14:45:19.157583
5571 14:45:19.160289 Image ramdisk-1 has 18720226 bytes.
5572 14:45:19.160625
5573 14:45:19.163989 Image fdt-1 has 57695 bytes.
5574 14:45:19.164242
5575 14:45:19.167417 Image kernel-1 has 13060619 bytes.
5576 14:45:19.167709
5577 14:45:19.177124 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5578 14:45:19.177602
5579 14:45:19.187398 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5580 14:45:19.187988
5581 14:45:19.193801 Choosing best match conf-1 for compat google,juniper-sku16.
5582 14:45:19.197703
5583 14:45:19.202158 Connected to device vid:did:rid of 1ae0:0028:00
5584 14:45:19.210208
5585 14:45:19.213394 tpm_get_response: command 0x17b, return code 0x0
5586 14:45:19.213810
5587 14:45:19.217185 tpm_cleanup: add release locality here.
5588 14:45:19.217636
5589 14:45:19.220387 Shutting down all USB controllers.
5590 14:45:19.220793
5591 14:45:19.223407 Removing current net device
5592 14:45:19.223839
5593 14:45:19.226976 Exiting depthcharge with code 4 at timestamp: 33777037
5594 14:45:19.227485
5595 14:45:19.230202 LZMA decompressing kernel-1 to 0x80193568
5596 14:45:19.230615
5597 14:45:19.233620 LZMA decompressing kernel-1 to 0x40000000
5598 14:45:21.094606
5599 14:45:21.095188 jumping to kernel
5600 14:45:21.097007 end: 2.2.4 bootloader-commands (duration 00:00:19) [common]
5601 14:45:21.097621 start: 2.2.5 auto-login-action (timeout 00:04:07) [common]
5602 14:45:21.098007 Setting prompt string to ['Linux version [0-9]']
5603 14:45:21.098390 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5604 14:45:21.098733 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5605 14:45:21.169834
5606 14:45:21.173371 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5607 14:45:21.177181 start: 2.2.5.1 login-action (timeout 00:04:06) [common]
5608 14:45:21.178064 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5609 14:45:21.178532 Setting prompt string to []
5610 14:45:21.179030 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5611 14:45:21.179444 Using line separator: #'\n'#
5612 14:45:21.179859 No login prompt set.
5613 14:45:21.180280 Parsing kernel messages
5614 14:45:21.180629 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5615 14:45:21.181625 [login-action] Waiting for messages, (timeout 00:04:06)
5616 14:45:21.182055 Waiting using forced prompt support (timeout 00:02:03)
5617 14:45:21.196454 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j216541-arm64-gcc-10-defconfig-arm64-chromebook-f7c97) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024
5618 14:45:21.199650 [ 0.000000] random: crng init done
5619 14:45:21.206841 [ 0.000000] Machine model: Google juniper sku16 board
5620 14:45:21.209982 [ 0.000000] efi: UEFI not found.
5621 14:45:21.216797 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5622 14:45:21.223338 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5623 14:45:21.233183 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5624 14:45:21.236080 [ 0.000000] printk: bootconsole [mtk8250] enabled
5625 14:45:21.244827 [ 0.000000] NUMA: No NUMA configuration found
5626 14:45:21.251659 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5627 14:45:21.258091 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff]
5628 14:45:21.258546 [ 0.000000] Zone ranges:
5629 14:45:21.264813 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5630 14:45:21.268263 [ 0.000000] DMA32 empty
5631 14:45:21.274731 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5632 14:45:21.278110 [ 0.000000] Movable zone start for each node
5633 14:45:21.281560 [ 0.000000] Early memory node ranges
5634 14:45:21.288518 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5635 14:45:21.294400 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5636 14:45:21.301158 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5637 14:45:21.308014 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5638 14:45:21.314867 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5639 14:45:21.321820 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5640 14:45:21.337481 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5641 14:45:21.344121 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5642 14:45:21.350430 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5643 14:45:21.354092 [ 0.000000] psci: probing for conduit method from DT.
5644 14:45:21.360891 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5645 14:45:21.364047 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5646 14:45:21.370965 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5647 14:45:21.374048 [ 0.000000] psci: SMC Calling Convention v1.1
5648 14:45:21.380614 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5649 14:45:21.383981 [ 0.000000] Detected VIPT I-cache on CPU0
5650 14:45:21.390683 [ 0.000000] CPU features: detected: GIC system register CPU interface
5651 14:45:21.397254 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5652 14:45:21.403903 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5653 14:45:21.407325 [ 0.000000] CPU features: detected: ARM erratum 845719
5654 14:45:21.413794 [ 0.000000] alternatives: applying boot alternatives
5655 14:45:21.417639 [ 0.000000] Fallback order for Node 0: 0
5656 14:45:21.423872 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5657 14:45:21.427242 [ 0.000000] Policy zone: Normal
5658 14:45:21.454116 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14166990/extract-nfsrootfs-830ytlfh,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5659 14:45:21.466932 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5660 14:45:21.476945 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5661 14:45:21.484066 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5662 14:45:21.490489 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
5663 14:45:21.494018 <6>[ 0.000000] software IO TLB: area num 8.
5664 14:45:21.520994 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5665 14:45:21.578213 <6>[ 0.000000] Memory: 3896916K/4191232K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 261548K reserved, 32768K cma-reserved)
5666 14:45:21.585124 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5667 14:45:21.591739 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5668 14:45:21.594919 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5669 14:45:21.601852 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5670 14:45:21.608207 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5671 14:45:21.611506 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5672 14:45:21.621778 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5673 14:45:21.628423 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5674 14:45:21.631671 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5675 14:45:21.643645 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5676 14:45:21.650511 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5677 14:45:21.653691 <6>[ 0.000000] GICv3: 640 SPIs implemented
5678 14:45:21.656782 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5679 14:45:21.660174 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5680 14:45:21.667244 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5681 14:45:21.673671 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5682 14:45:21.683621 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5683 14:45:21.696924 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5684 14:45:21.703266 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5685 14:45:21.715673 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5686 14:45:21.728521 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5687 14:45:21.735265 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5688 14:45:21.741988 <6>[ 0.009468] Console: colour dummy device 80x25
5689 14:45:21.745373 <6>[ 0.014528] printk: console [tty1] enabled
5690 14:45:21.755435 <6>[ 0.018918] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5691 14:45:21.762506 <6>[ 0.029382] pid_max: default: 32768 minimum: 301
5692 14:45:21.765518 <6>[ 0.034263] LSM: Security Framework initializing
5693 14:45:21.775264 <6>[ 0.039178] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5694 14:45:21.782122 <6>[ 0.046800] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5695 14:45:21.788752 <4>[ 0.055673] cacheinfo: Unable to detect cache hierarchy for CPU 0
5696 14:45:21.798931 <6>[ 0.062301] cblist_init_generic: Setting adjustable number of callback queues.
5697 14:45:21.802289 <6>[ 0.069747] cblist_init_generic: Setting shift to 3 and lim to 1.
5698 14:45:21.812358 <6>[ 0.076099] cblist_init_generic: Setting adjustable number of callback queues.
5699 14:45:21.819265 <6>[ 0.083543] cblist_init_generic: Setting shift to 3 and lim to 1.
5700 14:45:21.822235 <6>[ 0.089941] rcu: Hierarchical SRCU implementation.
5701 14:45:21.828697 <6>[ 0.094967] rcu: Max phase no-delay instances is 1000.
5702 14:45:21.835765 <6>[ 0.102893] EFI services will not be available.
5703 14:45:21.838589 <6>[ 0.107847] smp: Bringing up secondary CPUs ...
5704 14:45:21.849521 <6>[ 0.113111] Detected VIPT I-cache on CPU1
5705 14:45:21.855858 <4>[ 0.113155] cacheinfo: Unable to detect cache hierarchy for CPU 1
5706 14:45:21.862029 <6>[ 0.113165] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5707 14:45:21.869536 <6>[ 0.113196] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5708 14:45:21.872506 <6>[ 0.113682] Detected VIPT I-cache on CPU2
5709 14:45:21.878719 <4>[ 0.113713] cacheinfo: Unable to detect cache hierarchy for CPU 2
5710 14:45:21.885744 <6>[ 0.113718] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5711 14:45:21.892098 <6>[ 0.113730] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5712 14:45:21.895626 <6>[ 0.114176] Detected VIPT I-cache on CPU3
5713 14:45:21.902282 <4>[ 0.114206] cacheinfo: Unable to detect cache hierarchy for CPU 3
5714 14:45:21.912093 <6>[ 0.114211] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5715 14:45:21.919230 <6>[ 0.114222] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5716 14:45:21.922504 <6>[ 0.114796] CPU features: detected: Spectre-v2
5717 14:45:21.925487 <6>[ 0.114806] CPU features: detected: Spectre-BHB
5718 14:45:21.932421 <6>[ 0.114810] CPU features: detected: ARM erratum 858921
5719 14:45:21.935364 <6>[ 0.114815] Detected VIPT I-cache on CPU4
5720 14:45:21.942470 <4>[ 0.114863] cacheinfo: Unable to detect cache hierarchy for CPU 4
5721 14:45:21.949048 <6>[ 0.114870] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5722 14:45:21.955846 <6>[ 0.114878] arch_timer: Enabling local workaround for ARM erratum 858921
5723 14:45:21.962240 <6>[ 0.114889] arch_timer: CPU4: Trapping CNTVCT access
5724 14:45:21.968974 <6>[ 0.114896] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5725 14:45:21.972127 <6>[ 0.115382] Detected VIPT I-cache on CPU5
5726 14:45:21.978834 <4>[ 0.115423] cacheinfo: Unable to detect cache hierarchy for CPU 5
5727 14:45:21.985666 <6>[ 0.115429] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5728 14:45:21.992290 <6>[ 0.115436] arch_timer: Enabling local workaround for ARM erratum 858921
5729 14:45:21.999282 <6>[ 0.115442] arch_timer: CPU5: Trapping CNTVCT access
5730 14:45:22.005459 <6>[ 0.115447] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5731 14:45:22.008761 <6>[ 0.115883] Detected VIPT I-cache on CPU6
5732 14:45:22.015469 <4>[ 0.115929] cacheinfo: Unable to detect cache hierarchy for CPU 6
5733 14:45:22.021935 <6>[ 0.115935] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5734 14:45:22.028480 <6>[ 0.115942] arch_timer: Enabling local workaround for ARM erratum 858921
5735 14:45:22.035349 <6>[ 0.115949] arch_timer: CPU6: Trapping CNTVCT access
5736 14:45:22.041946 <6>[ 0.115954] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5737 14:45:22.045198 <6>[ 0.116483] Detected VIPT I-cache on CPU7
5738 14:45:22.052152 <4>[ 0.116527] cacheinfo: Unable to detect cache hierarchy for CPU 7
5739 14:45:22.058446 <6>[ 0.116533] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5740 14:45:22.064715 <6>[ 0.116540] arch_timer: Enabling local workaround for ARM erratum 858921
5741 14:45:22.071534 <6>[ 0.116546] arch_timer: CPU7: Trapping CNTVCT access
5742 14:45:22.078512 <6>[ 0.116552] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5743 14:45:22.081968 <6>[ 0.116599] smp: Brought up 1 node, 8 CPUs
5744 14:45:22.088323 <6>[ 0.355514] SMP: Total of 8 processors activated.
5745 14:45:22.091802 <6>[ 0.360449] CPU features: detected: 32-bit EL0 Support
5746 14:45:22.098136 <6>[ 0.365828] CPU features: detected: 32-bit EL1 Support
5747 14:45:22.105060 <6>[ 0.371196] CPU features: detected: CRC32 instructions
5748 14:45:22.108363 <6>[ 0.376622] CPU: All CPU(s) started at EL2
5749 14:45:22.115040 <6>[ 0.380960] alternatives: applying system-wide alternatives
5750 14:45:22.121275 <6>[ 0.389003] devtmpfs: initialized
5751 14:45:22.133813 <6>[ 0.397950] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5752 14:45:22.144090 <6>[ 0.407899] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5753 14:45:22.147273 <6>[ 0.415626] pinctrl core: initialized pinctrl subsystem
5754 14:45:22.155604 <6>[ 0.422721] DMI not present or invalid.
5755 14:45:22.161988 <6>[ 0.427091] NET: Registered PF_NETLINK/PF_ROUTE protocol family
5756 14:45:22.168987 <6>[ 0.433998] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
5757 14:45:22.178633 <6>[ 0.441527] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
5758 14:45:22.185286 <6>[ 0.449779] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
5759 14:45:22.192442 <6>[ 0.457959] audit: initializing netlink subsys (disabled)
5760 14:45:22.198947 <5>[ 0.463662] audit: type=2000 audit(0.332:1): state=initialized audit_enabled=0 res=1
5761 14:45:22.205366 <6>[ 0.464625] thermal_sys: Registered thermal governor 'step_wise'
5762 14:45:22.212102 <6>[ 0.471628] thermal_sys: Registered thermal governor 'power_allocator'
5763 14:45:22.215411 <6>[ 0.477925] cpuidle: using governor menu
5764 14:45:22.222160 <6>[ 0.488884] NET: Registered PF_QIPCRTR protocol family
5765 14:45:22.228490 <6>[ 0.494379] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
5766 14:45:22.235780 <6>[ 0.501474] ASID allocator initialised with 32768 entries
5767 14:45:22.238594 <6>[ 0.508241] Serial: AMBA PL011 UART driver
5768 14:45:22.251227 <4>[ 0.518646] Trying to register duplicate clock ID: 113
5769 14:45:22.311067 <6>[ 0.575193] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5770 14:45:22.325690 <6>[ 0.589522] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5771 14:45:22.328798 <6>[ 0.599268] KASLR enabled
5772 14:45:22.343137 <6>[ 0.607279] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
5773 14:45:22.349905 <6>[ 0.614281] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
5774 14:45:22.356825 <6>[ 0.620759] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
5775 14:45:22.363352 <6>[ 0.627750] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
5776 14:45:22.370041 <6>[ 0.634224] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
5777 14:45:22.376430 <6>[ 0.641214] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
5778 14:45:22.383345 <6>[ 0.647688] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
5779 14:45:22.389866 <6>[ 0.654678] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
5780 14:45:22.393380 <6>[ 0.662241] ACPI: Interpreter disabled.
5781 14:45:22.402669 <6>[ 0.670208] iommu: Default domain type: Translated
5782 14:45:22.408998 <6>[ 0.675315] iommu: DMA domain TLB invalidation policy: strict mode
5783 14:45:22.412474 <5>[ 0.681947] SCSI subsystem initialized
5784 14:45:22.419306 <6>[ 0.686359] usbcore: registered new interface driver usbfs
5785 14:45:22.425811 <6>[ 0.692087] usbcore: registered new interface driver hub
5786 14:45:22.429053 <6>[ 0.697628] usbcore: registered new device driver usb
5787 14:45:22.436221 <6>[ 0.703919] pps_core: LinuxPPS API ver. 1 registered
5788 14:45:22.446190 <6>[ 0.709105] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
5789 14:45:22.449196 <6>[ 0.718429] PTP clock support registered
5790 14:45:22.452682 <6>[ 0.722681] EDAC MC: Ver: 3.0.0
5791 14:45:22.460556 <6>[ 0.728314] FPGA manager framework
5792 14:45:22.464134 <6>[ 0.732003] Advanced Linux Sound Architecture Driver Initialized.
5793 14:45:22.467853 <6>[ 0.738746] vgaarb: loaded
5794 14:45:22.474140 <6>[ 0.741882] clocksource: Switched to clocksource arch_sys_counter
5795 14:45:22.481277 <5>[ 0.748319] VFS: Disk quotas dquot_6.6.0
5796 14:45:22.487862 <6>[ 0.752492] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
5797 14:45:22.490941 <6>[ 0.759665] pnp: PnP ACPI: disabled
5798 14:45:22.498648 <6>[ 0.766508] NET: Registered PF_INET protocol family
5799 14:45:22.505670 <6>[ 0.771741] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
5800 14:45:22.517498 <6>[ 0.781651] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
5801 14:45:22.524083 <6>[ 0.790404] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
5802 14:45:22.533837 <6>[ 0.798355] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
5803 14:45:22.540806 <6>[ 0.806589] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
5804 14:45:22.547406 <6>[ 0.814684] TCP: Hash tables configured (established 32768 bind 32768)
5805 14:45:22.557336 <6>[ 0.821509] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
5806 14:45:22.563655 <6>[ 0.828479] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
5807 14:45:22.570542 <6>[ 0.835958] NET: Registered PF_UNIX/PF_LOCAL protocol family
5808 14:45:22.576860 <6>[ 0.842049] RPC: Registered named UNIX socket transport module.
5809 14:45:22.580988 <6>[ 0.848193] RPC: Registered udp transport module.
5810 14:45:22.584015 <6>[ 0.853117] RPC: Registered tcp transport module.
5811 14:45:22.593822 <6>[ 0.858041] RPC: Registered tcp NFSv4.1 backchannel transport module.
5812 14:45:22.596855 <6>[ 0.864693] PCI: CLS 0 bytes, default 64
5813 14:45:22.600339 <6>[ 0.868943] Unpacking initramfs...
5814 14:45:22.610190 <6>[ 0.872998] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
5815 14:45:22.617013 <6>[ 0.881695] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
5816 14:45:22.623304 <6>[ 0.890585] kvm [1]: IPA Size Limit: 40 bits
5817 14:45:22.626813 <6>[ 0.896912] kvm [1]: vgic-v2@c420000
5818 14:45:22.633466 <6>[ 0.900739] kvm [1]: GIC system register CPU interface enabled
5819 14:45:22.636847 <6>[ 0.906913] kvm [1]: vgic interrupt IRQ18
5820 14:45:22.644261 <6>[ 0.911277] kvm [1]: Hyp mode initialized successfully
5821 14:45:22.650726 <5>[ 0.917571] Initialise system trusted keyrings
5822 14:45:22.657550 <6>[ 0.922343] workingset: timestamp_bits=42 max_order=20 bucket_order=0
5823 14:45:22.664631 <6>[ 0.932291] squashfs: version 4.0 (2009/01/31) Phillip Lougher
5824 14:45:22.671454 <5>[ 0.938709] NFS: Registering the id_resolver key type
5825 14:45:22.674668 <5>[ 0.944011] Key type id_resolver registered
5826 14:45:22.681398 <5>[ 0.948423] Key type id_legacy registered
5827 14:45:22.687735 <6>[ 0.952721] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
5828 14:45:22.695034 <6>[ 0.959637] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
5829 14:45:22.701865 <6>[ 0.967367] 9p: Installing v9fs 9p2000 file system support
5830 14:45:22.728981 <5>[ 0.996192] Key type asymmetric registered
5831 14:45:22.732564 <5>[ 1.000528] Asymmetric key parser 'x509' registered
5832 14:45:22.742157 <6>[ 1.005674] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
5833 14:45:22.745754 <6>[ 1.013282] io scheduler mq-deadline registered
5834 14:45:22.748989 <6>[ 1.018036] io scheduler kyber registered
5835 14:45:22.771525 <6>[ 1.038646] EINJ: ACPI disabled.
5836 14:45:22.778310 <4>[ 1.042397] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
5837 14:45:22.815864 <6>[ 1.082740] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
5838 14:45:22.823806 <6>[ 1.091201] printk: console [ttyS0] disabled
5839 14:45:22.851799 <6>[ 1.115838] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
5840 14:45:22.858679 <6>[ 1.125305] printk: console [ttyS0] enabled
5841 14:45:22.861730 <6>[ 1.125305] printk: console [ttyS0] enabled
5842 14:45:22.868829 <6>[ 1.134221] printk: bootconsole [mtk8250] disabled
5843 14:45:22.871710 <6>[ 1.134221] printk: bootconsole [mtk8250] disabled
5844 14:45:22.882158 <3>[ 1.144741] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
5845 14:45:22.888585 <3>[ 1.153121] mt6577-uart 11003000.serial: Error applying setting, reverse things back
5846 14:45:22.917939 <6>[ 1.181525] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
5847 14:45:22.924120 <6>[ 1.191166] serial serial0: tty port ttyS1 registered
5848 14:45:22.930792 <6>[ 1.197709] SuperH (H)SCI(F) driver initialized
5849 14:45:22.934256 <6>[ 1.203205] msm_serial: driver initialized
5850 14:45:22.949827 <6>[ 1.213466] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
5851 14:45:22.959379 <6>[ 1.222058] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
5852 14:45:22.966010 <6>[ 1.230630] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
5853 14:45:22.976130 <6>[ 1.239196] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
5854 14:45:22.982729 <6>[ 1.247848] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
5855 14:45:22.992520 <6>[ 1.256509] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
5856 14:45:23.002726 <6>[ 1.265249] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
5857 14:45:23.009506 <6>[ 1.273989] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
5858 14:45:23.019313 <6>[ 1.282555] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
5859 14:45:23.029222 <6>[ 1.291354] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
5860 14:45:23.036498 <4>[ 1.303727] cacheinfo: Unable to detect cache hierarchy for CPU 0
5861 14:45:23.045517 <6>[ 1.313043] loop: module loaded
5862 14:45:23.057725 <6>[ 1.324910] vsim1: Bringing 1800000uV into 2700000-2700000uV
5863 14:45:23.075695 <6>[ 1.342810] megasas: 07.719.03.00-rc1
5864 14:45:23.084302 <6>[ 1.351506] spi-nor spi1.0: w25q64dw (8192 Kbytes)
5865 14:45:23.093949 <6>[ 1.361253] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
5866 14:45:23.111138 <6>[ 1.378035] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
5867 14:45:23.167502 <6>[ 1.428224] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.5.171/cr50_v2.94_mp.164-2fb1d
5868 14:45:23.226347 <6>[ 1.493642] Freeing initrd memory: 18280K
5869 14:45:23.241503 <4>[ 1.505442] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
5870 14:45:23.248115 <4>[ 1.514670] CPU: 4 PID: 1 Comm: swapper/0 Not tainted 6.1.91-cip21 #1
5871 14:45:23.254755 <4>[ 1.521368] Hardware name: Google juniper sku16 board (DT)
5872 14:45:23.258101 <4>[ 1.527107] Call trace:
5873 14:45:23.261779 <4>[ 1.529807] dump_backtrace.part.0+0xe0/0xf0
5874 14:45:23.264688 <4>[ 1.534344] show_stack+0x18/0x30
5875 14:45:23.268275 <4>[ 1.537916] dump_stack_lvl+0x68/0x84
5876 14:45:23.271783 <4>[ 1.541837] dump_stack+0x18/0x34
5877 14:45:23.278587 <4>[ 1.545407] sysfs_warn_dup+0x64/0x80
5878 14:45:23.281850 <4>[ 1.549329] sysfs_do_create_link_sd+0xf0/0x100
5879 14:45:23.285178 <4>[ 1.554116] sysfs_create_link+0x20/0x40
5880 14:45:23.291483 <4>[ 1.558295] bus_add_device+0x68/0x10c
5881 14:45:23.294970 <4>[ 1.562302] device_add+0x340/0x7ac
5882 14:45:23.298203 <4>[ 1.566045] of_device_add+0x44/0x60
5883 14:45:23.301757 <4>[ 1.569879] of_platform_device_create_pdata+0x90/0x120
5884 14:45:23.308044 <4>[ 1.575361] of_platform_bus_create+0x170/0x370
5885 14:45:23.311371 <4>[ 1.580147] of_platform_populate+0x50/0xfc
5886 14:45:23.318353 <4>[ 1.584587] parse_mtd_partitions+0x1dc/0x510
5887 14:45:23.321562 <4>[ 1.589200] mtd_device_parse_register+0xf8/0x2e0
5888 14:45:23.324791 <4>[ 1.594158] spi_nor_probe+0x21c/0x2f0
5889 14:45:23.328208 <4>[ 1.598164] spi_mem_probe+0x6c/0xb0
5890 14:45:23.334797 <4>[ 1.601996] spi_probe+0x84/0xe4
5891 14:45:23.338358 <4>[ 1.605479] really_probe+0xbc/0x2e0
5892 14:45:23.341627 <4>[ 1.609309] __driver_probe_device+0x78/0x11c
5893 14:45:23.344752 <4>[ 1.613921] driver_probe_device+0xd8/0x160
5894 14:45:23.351593 <4>[ 1.618359] __device_attach_driver+0xb8/0x134
5895 14:45:23.354619 <4>[ 1.623058] bus_for_each_drv+0x78/0xd0
5896 14:45:23.357780 <4>[ 1.627148] __device_attach+0xa8/0x1c0
5897 14:45:23.364706 <4>[ 1.631239] device_initial_probe+0x14/0x20
5898 14:45:23.367856 <4>[ 1.635677] bus_probe_device+0x9c/0xa4
5899 14:45:23.371261 <4>[ 1.639767] device_add+0x3ac/0x7ac
5900 14:45:23.374457 <4>[ 1.643509] __spi_add_device+0x78/0x120
5901 14:45:23.377784 <4>[ 1.647687] spi_add_device+0x40/0x7c
5902 14:45:23.384486 <4>[ 1.651605] spi_register_controller+0x610/0xad0
5903 14:45:23.387972 <4>[ 1.656477] devm_spi_register_controller+0x4c/0xa4
5904 14:45:23.394893 <4>[ 1.661610] mtk_spi_probe+0x3f8/0x650
5905 14:45:23.398129 <4>[ 1.665614] platform_probe+0x68/0xe0
5906 14:45:23.401674 <4>[ 1.669533] really_probe+0xbc/0x2e0
5907 14:45:23.404637 <4>[ 1.673363] __driver_probe_device+0x78/0x11c
5908 14:45:23.411695 <4>[ 1.677974] driver_probe_device+0xd8/0x160
5909 14:45:23.415107 <4>[ 1.682412] __driver_attach+0x94/0x19c
5910 14:45:23.418031 <4>[ 1.686502] bus_for_each_dev+0x70/0xd0
5911 14:45:23.421492 <4>[ 1.690593] driver_attach+0x24/0x30
5912 14:45:23.424683 <4>[ 1.694422] bus_add_driver+0x154/0x20c
5913 14:45:23.431836 <4>[ 1.698513] driver_register+0x78/0x130
5914 14:45:23.434793 <4>[ 1.702604] __platform_driver_register+0x28/0x34
5915 14:45:23.438183 <4>[ 1.707563] mtk_spi_driver_init+0x1c/0x28
5916 14:45:23.444636 <4>[ 1.711917] do_one_initcall+0x50/0x1d0
5917 14:45:23.448080 <4>[ 1.716008] kernel_init_freeable+0x21c/0x288
5918 14:45:23.451377 <4>[ 1.720621] kernel_init+0x24/0x12c
5919 14:45:23.454855 <4>[ 1.724367] ret_from_fork+0x10/0x20
5920 14:45:23.466109 <6>[ 1.733274] tun: Universal TUN/TAP device driver, 1.6
5921 14:45:23.469794 <6>[ 1.739554] thunder_xcv, ver 1.0
5922 14:45:23.473047 <6>[ 1.743072] thunder_bgx, ver 1.0
5923 14:45:23.476172 <6>[ 1.746574] nicpf, ver 1.0
5924 14:45:23.487102 <6>[ 1.750931] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
5925 14:45:23.490615 <6>[ 1.758415] hns3: Copyright (c) 2017 Huawei Corporation.
5926 14:45:23.493691 <6>[ 1.764016] hclge is initializing
5927 14:45:23.500728 <6>[ 1.767603] e1000: Intel(R) PRO/1000 Network Driver
5928 14:45:23.507104 <6>[ 1.772739] e1000: Copyright (c) 1999-2006 Intel Corporation.
5929 14:45:23.510444 <6>[ 1.778763] e1000e: Intel(R) PRO/1000 Network Driver
5930 14:45:23.517226 <6>[ 1.783984] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
5931 14:45:23.523898 <6>[ 1.790177] igb: Intel(R) Gigabit Ethernet Network Driver
5932 14:45:23.530420 <6>[ 1.795834] igb: Copyright (c) 2007-2014 Intel Corporation.
5933 14:45:23.536771 <6>[ 1.801677] igbvf: Intel(R) Gigabit Virtual Function Network Driver
5934 14:45:23.540345 <6>[ 1.808200] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
5935 14:45:23.547173 <6>[ 1.814753] sky2: driver version 1.30
5936 14:45:23.553739 <6>[ 1.819991] usbcore: registered new device driver r8152-cfgselector
5937 14:45:23.560583 <6>[ 1.826535] usbcore: registered new interface driver r8152
5938 14:45:23.563843 <6>[ 1.832361] VFIO - User Level meta-driver version: 0.3
5939 14:45:23.572595 <6>[ 1.840130] mtu3 11201000.usb: uwk - reg:0x420, version:101
5940 14:45:23.579753 <4>[ 1.846003] mtu3 11201000.usb: supply vbus not found, using dummy regulator
5941 14:45:23.586281 <6>[ 1.853273] mtu3 11201000.usb: dr_mode: 1, drd: auto
5942 14:45:23.592970 <6>[ 1.858497] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
5943 14:45:23.595961 <6>[ 1.864685] mtu3 11201000.usb: usb3-drd: 0
5944 14:45:23.606565 <6>[ 1.870262] mtu3 11201000.usb: xHCI platform device register success...
5945 14:45:23.612820 <4>[ 1.878934] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
5946 14:45:23.619838 <6>[ 1.886876] xhci-mtk 11200000.usb: xHCI Host Controller
5947 14:45:23.626428 <6>[ 1.892386] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
5948 14:45:23.632939 <6>[ 1.900126] xhci-mtk 11200000.usb: USB3 root hub has no ports
5949 14:45:23.642835 <6>[ 1.906135] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
5950 14:45:23.649487 <6>[ 1.915557] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
5951 14:45:23.656159 <6>[ 1.921638] xhci-mtk 11200000.usb: xHCI Host Controller
5952 14:45:23.662778 <6>[ 1.927129] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
5953 14:45:23.669682 <6>[ 1.934787] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
5954 14:45:23.672923 <6>[ 1.941604] hub 1-0:1.0: USB hub found
5955 14:45:23.676054 <6>[ 1.945635] hub 1-0:1.0: 1 port detected
5956 14:45:23.686857 <6>[ 1.950984] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
5957 14:45:23.689950 <6>[ 1.959618] hub 2-0:1.0: USB hub found
5958 14:45:23.699966 <3>[ 1.963666] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
5959 14:45:23.706625 <6>[ 1.971553] usbcore: registered new interface driver usb-storage
5960 14:45:23.713228 <6>[ 1.978168] usbcore: registered new device driver onboard-usb-hub
5961 14:45:23.725731 <4>[ 1.989995] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
5962 14:45:23.734687 <6>[ 2.002216] mt6397-rtc mt6358-rtc: registered as rtc0
5963 14:45:23.744567 <6>[ 2.007700] mt6397-rtc mt6358-rtc: setting system clock to 2024-06-04T14:45:22 UTC (1717512322)
5964 14:45:23.750814 <6>[ 2.017583] i2c_dev: i2c /dev entries driver
5965 14:45:23.761283 <6>[ 2.023990] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5966 14:45:23.767883 <6>[ 2.032313] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5967 14:45:23.774033 <6>[ 2.041218] i2c 4-0058: Fixed dependency cycle(s) with /panel
5968 14:45:23.780922 <6>[ 2.047248] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
5969 14:45:23.790574 <3>[ 2.054693] anx7625 4-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
5970 14:45:23.807632 <6>[ 2.071695] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
5971 14:45:23.815734 <6>[ 2.083159] cpu cpu0: EM: created perf domain
5972 14:45:23.826129 <6>[ 2.088588] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
5973 14:45:23.832554 <6>[ 2.099871] cpu cpu4: EM: created perf domain
5974 14:45:23.839407 <6>[ 2.106820] sdhci: Secure Digital Host Controller Interface driver
5975 14:45:23.845897 <6>[ 2.113276] sdhci: Copyright(c) Pierre Ossman
5976 14:45:23.852680 <6>[ 2.118683] Synopsys Designware Multimedia Card Interface Driver
5977 14:45:23.859519 <6>[ 2.119225] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
5978 14:45:23.863040 <6>[ 2.125742] sdhci-pltfm: SDHCI platform and OF driver helper
5979 14:45:23.871143 <6>[ 2.138372] ledtrig-cpu: registered to indicate activity on CPUs
5980 14:45:23.878961 <6>[ 2.146072] usbcore: registered new interface driver usbhid
5981 14:45:23.882021 <6>[ 2.151911] usbhid: USB HID core driver
5982 14:45:23.892929 <6>[ 2.156172] spi_master spi2: will run message pump with realtime priority
5983 14:45:23.896324 <4>[ 2.156180] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
5984 14:45:23.903551 <4>[ 2.170420] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
5985 14:45:23.917291 <6>[ 2.175906] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
5986 14:45:23.935517 <6>[ 2.193091] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
5987 14:45:23.942522 <4>[ 2.204095] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
5988 14:45:23.945864 <6>[ 2.208045] cros-ec-spi spi2.0: Chrome EC device registered
5989 14:45:23.958149 <4>[ 2.222321] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
5990 14:45:23.969611 <4>[ 2.233586] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
5991 14:45:23.976021 <4>[ 2.242630] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
5992 14:45:23.982689 <6>[ 2.245511] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x11c14
5993 14:45:23.986040 <6>[ 2.254948] mmc0: new HS400 MMC card at address 0001
5994 14:45:23.995991 <6>[ 2.258669] mmc1: new ultra high speed SDR104 SDIO card at address 0001
5995 14:45:23.999715 <6>[ 2.267828] mmcblk0: mmc0:0001 TB2932 29.2 GiB
5996 14:45:24.009526 <6>[ 2.268960] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
5997 14:45:24.016201 <6>[ 2.275540] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
5998 14:45:24.026300 <6>[ 2.284730] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
5999 14:45:24.029250 <6>[ 2.289785] mmcblk0boot0: mmc0:0001 TB2932 4.00 MiB
6000 14:45:24.036228 <6>[ 2.299209] NET: Registered PF_PACKET protocol family
6001 14:45:24.042916 <6>[ 2.304550] mmcblk0boot1: mmc0:0001 TB2932 4.00 MiB
6002 14:45:24.046241 <6>[ 2.308702] 9pnet: Installing 9P2000 support
6003 14:45:24.052705 <6>[ 2.315029] mmcblk0rpmb: mmc0:0001 TB2932 4.00 MiB, chardev (507:0)
6004 14:45:24.056271 <5>[ 2.318425] Key type dns_resolver registered
6005 14:45:24.069466 <6>[ 2.322686] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
6006 14:45:24.079912 <6>[ 2.323432] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
6007 14:45:24.083100 <6>[ 2.352105] registered taskstats version 1
6008 14:45:24.089507 <5>[ 2.356498] Loading compiled-in X.509 certificates
6009 14:45:24.105585 <6>[ 2.369899] usb 1-1: new high-speed USB device number 2 using xhci-mtk
6010 14:45:24.138148 <3>[ 2.402014] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
6011 14:45:24.165517 <4>[ 2.429573] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6012 14:45:24.176281 <6>[ 2.440168] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6013 14:45:24.192463 <6>[ 2.453016] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6014 14:45:24.205762 <3>[ 2.465071] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6015 14:45:24.219686 <3>[ 2.480556] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6016 14:45:24.226536 <3>[ 2.492985] debugfs: File 'Playback' in directory 'dapm' already present!
6017 14:45:24.233351 <3>[ 2.500035] debugfs: File 'Capture' in directory 'dapm' already present!
6018 14:45:24.249476 <6>[ 2.509820] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input4
6019 14:45:24.259260 <6>[ 2.523155] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
6020 14:45:24.269541 <6>[ 2.531764] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
6021 14:45:24.275734 <6>[ 2.540314] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
6022 14:45:24.285818 <6>[ 2.548846] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
6023 14:45:24.292855 <6>[ 2.557381] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
6024 14:45:24.302606 <6>[ 2.565912] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
6025 14:45:24.308914 <6>[ 2.574491] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
6026 14:45:24.316777 <6>[ 2.583806] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
6027 14:45:24.323780 <6>[ 2.590421] hub 1-1:1.0: USB hub found
6028 14:45:24.327096 <6>[ 2.594902] hub 1-1:1.0: 3 ports detected
6029 14:45:24.333197 <6>[ 2.599793] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
6030 14:45:24.340136 <6>[ 2.607177] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
6031 14:45:24.347838 <6>[ 2.614590] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
6032 14:45:24.358375 <6>[ 2.622211] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
6033 14:45:24.364873 <6>[ 2.630528] panfrost 13040000.gpu: clock rate = 511999970
6034 14:45:24.374981 <6>[ 2.636227] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
6035 14:45:24.381681 <6>[ 2.646370] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
6036 14:45:24.392205 <6>[ 2.654383] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
6037 14:45:24.401867 <6>[ 2.662823] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
6038 14:45:24.408624 <6>[ 2.674902] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
6039 14:45:24.422053 <6>[ 2.685776] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6040 14:45:24.432241 <6>[ 2.694581] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6041 14:45:24.441984 <6>[ 2.703724] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6042 14:45:24.448324 <6>[ 2.712854] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6043 14:45:24.458912 <6>[ 2.721984] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6044 14:45:24.468425 <6>[ 2.731284] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6045 14:45:24.478677 <6>[ 2.740583] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6046 14:45:24.488316 <6>[ 2.750058] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6047 14:45:24.494909 <6>[ 2.759531] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6048 14:45:24.504982 <6>[ 2.768658] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6049 14:45:24.577538 <6>[ 2.841220] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6050 14:45:24.587257 <6>[ 2.850132] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6051 14:45:24.597828 <6>[ 2.861779] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6052 14:45:24.645885 <6>[ 2.909920] usb 1-1.2: new high-speed USB device number 3 using xhci-mtk
6053 14:45:25.280216 <6>[ 3.106397] r8152-cfgselector 1-1.2: reset high-speed USB device number 3 using xhci-mtk
6054 14:45:25.290117 <4>[ 3.223120] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6055 14:45:25.296487 <4>[ 3.223138] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6056 14:45:25.303249 <6>[ 3.260030] r8152 1-1.2:1.0 eth0: v1.12.13
6057 14:45:25.309981 <6>[ 3.337912] usb 1-1.3: new high-speed USB device number 4 using xhci-mtk
6058 14:45:25.316824 <6>[ 3.527510] Console: switching to colour frame buffer device 170x48
6059 14:45:25.323288 <6>[ 3.588148] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6060 14:45:25.340508 <6>[ 3.604060] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input5
6061 14:45:25.346771 <6>[ 3.612213] input: volume-buttons as /devices/platform/volume-buttons/input/input6
6062 14:45:26.607588 <6>[ 4.874906] r8152 1-1.2:1.0 eth0: carrier on
6063 14:45:28.782614 <5>[ 4.905916] Sending DHCP requests .., OK
6064 14:45:28.789901 <6>[ 7.054227] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.23
6065 14:45:28.792996 <6>[ 7.062663] IP-Config: Complete:
6066 14:45:28.806354 <6>[ 7.066234] device=eth0, hwaddr=00:e0:4c:71:a7:1f, ipaddr=192.168.201.23, mask=255.255.255.0, gw=192.168.201.1
6067 14:45:28.812670 <6>[ 7.077135] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-3, domain=lava-rack, nis-domain=(none)
6068 14:45:28.822818 <6>[ 7.086616] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6069 14:45:28.825897 <6>[ 7.086626] nameserver0=192.168.201.1
6070 14:45:28.829855 <6>[ 7.098964] clk: Disabling unused clocks
6071 14:45:28.833940 <6>[ 7.104077] ALSA device list:
6072 14:45:28.843522 <6>[ 7.110690] #0: mt8183_mt6358_ts3a227_max98357
6073 14:45:28.854797 <6>[ 7.122384] Freeing unused kernel memory: 8512K
6074 14:45:28.862780 <6>[ 7.130017] Run /init as init process
6075 14:45:28.875163 Loading, please wait...
6076 14:45:28.913381 Starting systemd-udevd version 252.22-1~deb12u1
6077 14:45:29.264474 <3>[ 7.531920] mtk-scp 10500000.scp: invalid resource
6078 14:45:29.271111 <3>[ 7.533724] thermal_sys: Failed to find 'trips' node
6079 14:45:29.277684 <6>[ 7.537366] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6080 14:45:29.288452 <3>[ 7.537372] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6081 14:45:29.294692 <3>[ 7.537380] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6082 14:45:29.304264 <3>[ 7.537385] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6083 14:45:29.311431 <3>[ 7.537390] elan_i2c 2-0015: Error applying setting, reverse things back
6084 14:45:29.321692 <3>[ 7.542252] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6085 14:45:29.328074 <3>[ 7.542265] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6086 14:45:29.335050 <4>[ 7.542269] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6087 14:45:29.341713 <3>[ 7.543498] thermal_sys: Failed to find 'trips' node
6088 14:45:29.345134 <6>[ 7.551116] remoteproc remoteproc0: scp is available
6089 14:45:29.355232 <3>[ 7.560284] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6090 14:45:29.361783 <4>[ 7.562902] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6091 14:45:29.368634 <4>[ 7.563010] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6092 14:45:29.378961 <4>[ 7.567228] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6093 14:45:29.388317 <3>[ 7.568178] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6094 14:45:29.394980 <3>[ 7.568197] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6095 14:45:29.405485 <3>[ 7.568206] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6096 14:45:29.415357 <3>[ 7.568293] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6097 14:45:29.425289 <3>[ 7.568302] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6098 14:45:29.432184 <3>[ 7.568309] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6099 14:45:29.442058 <3>[ 7.568319] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6100 14:45:29.452084 <3>[ 7.568327] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6101 14:45:29.458206 <3>[ 7.568364] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6102 14:45:29.468944 <6>[ 7.576556] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6103 14:45:29.474863 <3>[ 7.577625] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6104 14:45:29.481422 <6>[ 7.577822] mc: Linux media interface: v0.10
6105 14:45:29.485001 <6>[ 7.585112] remoteproc remoteproc0: powering up scp
6106 14:45:29.491283 <4>[ 7.591882] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6107 14:45:29.498746 <3>[ 7.593788] thermal_sys: Failed to find 'trips' node
6108 14:45:29.508721 <4>[ 7.600382] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6109 14:45:29.515597 <3>[ 7.607970] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6110 14:45:29.522053 <3>[ 7.613406] remoteproc remoteproc0: request_firmware failed: -2
6111 14:45:29.525604 <6>[ 7.616713] videodev: Linux video capture interface: v2.00
6112 14:45:29.535610 <3>[ 7.618380] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6113 14:45:29.542315 <4>[ 7.618387] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6114 14:45:29.552179 <5>[ 7.624245] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6115 14:45:29.559296 <6>[ 7.626445] cs_system_cfg: CoreSight Configuration manager initialised
6116 14:45:29.565610 <5>[ 7.647735] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6117 14:45:29.572423 <6>[ 7.703798] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7
6118 14:45:29.581812 <5>[ 7.706055] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6119 14:45:29.592200 <6>[ 7.723723] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6120 14:45:29.598959 <4>[ 7.731669] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6121 14:45:29.608975 <6>[ 7.739492] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6122 14:45:29.616207 <6>[ 7.747981] cfg80211: failed to load regulatory.db
6123 14:45:29.623192 <6>[ 7.752618] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6124 14:45:29.628931 <6>[ 7.767031] Bluetooth: Core ver 2.22
6125 14:45:29.635595 <6>[ 7.771307] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6126 14:45:29.642243 <6>[ 7.771964] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6127 14:45:29.649339 <6>[ 7.772032] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6128 14:45:29.659339 <6>[ 7.772595] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video0 (81,0)
6129 14:45:29.669190 <6>[ 7.773098] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video1
6130 14:45:29.672463 <6>[ 7.779664] NET: Registered PF_BLUETOOTH protocol family
6131 14:45:29.682822 <6>[ 7.781243] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6132 14:45:29.696862 <6>[ 7.787202] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6133 14:45:29.700697 <6>[ 7.793103] Bluetooth: HCI device and connection manager initialized
6134 14:45:29.711396 <6>[ 7.798899] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6135 14:45:29.721899 <6>[ 7.799752] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6136 14:45:29.728636 <6>[ 7.800050] usbcore: registered new interface driver uvcvideo
6137 14:45:29.732035 <6>[ 7.807284] Bluetooth: HCI socket layer initialized
6138 14:45:29.742347 <6>[ 7.815083] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6139 14:45:29.748821 <6>[ 7.822974] Bluetooth: L2CAP socket layer initialized
6140 14:45:29.755557 <6>[ 7.829775] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6141 14:45:29.765998 <6>[ 7.831744] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6142 14:45:29.775412 <6>[ 7.831750] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6143 14:45:29.789007 <6>[ 7.831837] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6144 14:45:29.792060 <6>[ 7.836504] Bluetooth: SCO socket layer initialized
6145 14:45:29.802542 <4>[ 7.936199] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6146 14:45:29.808786 <4>[ 7.936199] Fallback method does not support PEC.
6147 14:45:29.812174 <6>[ 7.960358] Bluetooth: HCI UART driver ver 2.3
6148 14:45:29.822507 <3>[ 7.970279] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6149 14:45:29.828661 <6>[ 7.974533] Bluetooth: HCI UART protocol H4 registered
6150 14:45:29.832128 <6>[ 7.974575] Bluetooth: HCI UART protocol LL registered
6151 14:45:29.842409 <6>[ 7.979599] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6152 14:45:29.849431 <3>[ 7.989134] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6153 14:45:29.855601 <6>[ 7.994280] Bluetooth: HCI UART protocol Three-wire (H5) registered
6154 14:45:29.888530 <6>[ 8.155247] Bluetooth: HCI UART protocol Broadcom registered
6155 14:45:29.894687 <6>[ 8.162002] Bluetooth: HCI UART protocol QCA registered
6156 14:45:29.901573 <6>[ 8.162600] Bluetooth: hci0: setting up ROME/QCA6390
6157 14:45:29.905151 <6>[ 8.167498] Bluetooth: HCI UART protocol Marvell registered
6158 14:45:29.932012 Begin: Loading essential drivers ... done.
6159 14:45:29.935225 Begin: Running /scripts/init-premount ... done.
6160 14:45:29.941421 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
6161 14:45:29.951731 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
6162 14:45:29.954932 Device /sys/class/net/eth0 found
6163 14:45:29.955351 done.
6164 14:45:29.961753 Begin: Waiting up to 180 secs for any network device to become available ... done.
6165 14:45:30.006947 IP-Config: eth0 hardware address 00:e0:4c:71:a7:1f mtu 1500 DHCP
6166 14:45:30.015731 IP-Config: eth0 complete (dhcp from 192.168.201.1):
6167 14:45:30.022213 address: 192.168.201.23 broadcast: 192.168.201.255 netmask: 255.255.255.0
6168 14:45:30.028853 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
6169 14:45:30.035607 host : mt8183-kukui-jacuzzi-juniper-sku16-cbg-3
6170 14:45:30.045130 domain : l<6>[ 8.308649] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6171 14:45:30.056110 ava-rack
6172 14:45:30.059512 rootserver: 192.168.201.1 rootpath:
6173 14:45:30.059933 filename :
6174 14:45:30.117876 <3>[ 8.385448] Bluetooth: hci0: Frame reassembly failed (-84)
6175 14:45:30.131939 <4>[ 8.394113] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6176 14:45:30.150907 <4>[ 8.414746] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6177 14:45:30.165756 <4>[ 8.429828] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6178 14:45:30.175398 <4>[ 8.443029] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6179 14:45:30.202407 done.
6180 14:45:30.210886 Begin: Running /scripts/nfs-bottom ... done.
6181 14:45:30.224303 Begin: Running /scripts/init-bottom ... done.
6182 14:45:30.413424 <6>[ 8.680504] Bluetooth: hci0: QCA Product ID :0x00000008
6183 14:45:30.423745 <6>[ 8.690668] Bluetooth: hci0: QCA SOC Version :0x00000044
6184 14:45:30.433856 <6>[ 8.700662] Bluetooth: hci0: QCA ROM Version :0x00000302
6185 14:45:30.443794 <6>[ 8.710572] Bluetooth: hci0: QCA Patch Version:0x00000111
6186 14:45:30.453222 <6>[ 8.720413] Bluetooth: hci0: QCA controller version 0x00440302
6187 14:45:30.466580 <6>[ 8.730152] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6188 14:45:30.478031 <4>[ 8.741716] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6189 14:45:30.490187 <3>[ 8.754045] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6190 14:45:30.498706 <3>[ 8.765265] Bluetooth: hci0: QCA Failed to download patch (-2)
6191 14:45:31.564374 <6>[ 9.831586] NET: Registered PF_INET6 protocol family
6192 14:45:31.575620 <6>[ 9.842901] Segment Routing with IPv6
6193 14:45:31.582154 <6>[ 9.849443] In-situ OAM (IOAM) with IPv6
6194 14:45:31.751136 <30>[ 9.992029] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6195 14:45:31.770466 <30>[ 10.038081] systemd[1]: Detected architecture arm64.
6196 14:45:31.781958
6197 14:45:31.785289 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6198 14:45:31.785377
6199 14:45:31.811788 <30>[ 10.079462] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6200 14:45:32.837598 <30>[ 11.100939] systemd[1]: Queued start job for default target graphical.target.
6201 14:45:32.875986 <30>[ 11.139468] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6202 14:45:32.888337 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6203 14:45:32.910090 <30>[ 11.173295] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6204 14:45:32.923131 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6205 14:45:32.939893 <30>[ 11.204199] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6206 14:45:32.953648 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6207 14:45:32.971706 <30>[ 11.235468] systemd[1]: Created slice user.slice - User and Session Slice.
6208 14:45:32.983038 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6209 14:45:33.006190 <30>[ 11.266513] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6210 14:45:33.019071 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6211 14:45:33.037750 <30>[ 11.298301] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6212 14:45:33.049881 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6213 14:45:33.076737 <30>[ 11.330244] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6214 14:45:33.094805 <30>[ 11.358572] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6215 14:45:33.101993 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6216 14:45:33.122534 <30>[ 11.386113] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6217 14:45:33.134797 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6218 14:45:33.154673 <30>[ 11.418294] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6219 14:45:33.168566 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6220 14:45:33.183122 <30>[ 11.450194] systemd[1]: Reached target paths.target - Path Units.
6221 14:45:33.197441 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6222 14:45:33.214541 <30>[ 11.478091] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6223 14:45:33.226778 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6224 14:45:33.239256 <30>[ 11.506040] systemd[1]: Reached target slices.target - Slice Units.
6225 14:45:33.252787 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6226 14:45:33.266336 <30>[ 11.534106] systemd[1]: Reached target swap.target - Swaps.
6227 14:45:33.277304 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6228 14:45:33.297823 <30>[ 11.562118] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6229 14:45:33.311087 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6230 14:45:33.330326 <30>[ 11.594464] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6231 14:45:33.344487 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6232 14:45:33.364663 <30>[ 11.628929] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6233 14:45:33.378002 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6234 14:45:33.395425 <30>[ 11.659440] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6235 14:45:33.409598 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6236 14:45:33.426632 <30>[ 11.690776] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6237 14:45:33.438743 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6238 14:45:33.459743 <30>[ 11.723758] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
6239 14:45:33.473200 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
6240 14:45:33.492898 <30>[ 11.756739] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6241 14:45:33.505933 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6242 14:45:33.522584 <30>[ 11.786672] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6243 14:45:33.535273 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6244 14:45:33.578183 <30>[ 11.842250] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6245 14:45:33.590066 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6246 14:45:33.611791 <30>[ 11.876002] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6247 14:45:33.625247 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6248 14:45:33.645213 <30>[ 11.909367] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6249 14:45:33.656079 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6250 14:45:33.681525 <30>[ 11.938744] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6251 14:45:33.705279 <30>[ 11.969185] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6252 14:45:33.718223 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6253 14:45:33.744563 <30>[ 12.008471] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6254 14:45:33.755855 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6255 14:45:33.779946 <30>[ 12.043934] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6256 14:45:33.790907 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6257 14:45:33.809900 <30>[ 12.074154] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6258 14:45:33.824004 Startin<6>[ 12.085602] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6259 14:45:33.827332 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
6260 14:45:33.883493 <30>[ 12.147189] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6261 14:45:33.896264 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6262 14:45:33.920418 <30>[ 12.184566] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
6263 14:45:33.931265 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
6264 14:45:33.955216 <6>[ 12.222579] fuse: init (API version 7.37)
6265 14:45:33.979232 <30>[ 12.243116] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6266 14:45:33.990809 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6267 14:45:34.021672 <30>[ 12.285363] systemd[1]: Starting systemd-journald.service - Journal Service...
6268 14:45:34.031274 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6269 14:45:34.056823 <30>[ 12.320756] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6270 14:45:34.067994 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6271 14:45:34.093550 <30>[ 12.354268] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6272 14:45:34.104211 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6273 14:45:34.126185 <30>[ 12.390188] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6274 14:45:34.138673 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
6275 14:45:34.157040 <30>[ 12.421201] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6276 14:45:34.167024 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
6277 14:45:34.189201 <3>[ 12.452862] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6278 14:45:34.204269 <30>[ 12.468086] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
6279 14:45:34.211022 <3>[ 12.468374] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6280 14:45:34.223363 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
6281 14:45:34.229821 <3>[ 12.493620] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6282 14:45:34.237494 <30>[ 12.503007] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
6283 14:45:34.247691 <3>[ 12.508841] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6284 14:45:34.262402 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSI<3>[ 12.526621] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6285 14:45:34.265991 X Message Queue File System.
6286 14:45:34.278451 <3>[ 12.541830] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6287 14:45:34.286559 <30>[ 12.551089] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
6288 14:45:34.296098 <3>[ 12.557419] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6289 14:45:34.314831 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug <3>[ 12.577683] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6290 14:45:34.314918 File System.
6291 14:45:34.339097 <30>[ 12.603062] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
6292 14:45:34.350081 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
6293 14:45:34.366905 <30>[ 12.631186] systemd[1]: Started systemd-journald.service - Journal Service.
6294 14:45:34.379578 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6295 14:45:34.403862 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
6296 14:45:34.425164 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6297 14:45:34.444755 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6298 14:45:34.465094 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6299 14:45:34.484716 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
6300 14:45:34.504953 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6301 14:45:34.523540 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6302 14:45:34.544088 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6303 14:45:34.563338 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
6304 14:45:34.585234 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6305 14:45:34.644801 <4>[ 12.901625] synth uevent: /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:i2c-tunnel/i2c-12/12-000b/power_supply/sbs-12-000b: failed to send uevent
6306 14:45:34.655208 <3>[ 12.919385] power_supply sbs-12-000b: uevent: failed to send synthetic uevent: -5
6307 14:45:34.668214 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
6308 14:45:34.693324 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
6309 14:45:34.720884 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
6310 14:45:34.746891 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
6311 14:45:34.773239 <46>[ 13.037323] systemd-journald[323]: Received client request to flush runtime journal.
6312 14:45:34.793465 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
6313 14:45:34.821692 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
6314 14:45:35.110048 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6315 14:45:35.129772 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
6316 14:45:35.147220 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6317 14:45:35.169468 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6318 14:45:35.559271 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6319 14:45:36.219817 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
6320 14:45:36.244336 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6321 14:45:36.295361 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6322 14:45:36.388098 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
6323 14:45:36.407606 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6324 14:45:36.426454 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6325 14:45:36.479420 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6326 14:45:36.508690 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6327 14:45:36.756131 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6328 14:45:36.778816 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
6329 14:45:36.842313 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
6330 14:45:36.994198 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
6331 14:45:37.013653 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
6332 14:45:37.032146 <4>[ 15.299096] power_supply_show_property: 4 callbacks suppressed
6333 14:45:37.043202 <3>[ 15.299105] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6334 14:45:37.049523 <3>[ 15.311083] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6335 14:45:37.073469 <3>[ 15.335919] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6336 14:45:37.080310 <3>[ 15.338901] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6337 14:45:37.087950 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
6338 14:45:37.097809 <3>[ 15.360035] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6339 14:45:37.112874 <3>[ 15.376531] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6340 14:45:37.129107 <3>[ 15.392911] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6341 14:45:37.146862 <3>[ 15.410481] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6342 14:45:37.161446 <3>[ 15.425251] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6343 14:45:37.178086 <3>[ 15.440912] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6344 14:45:37.309653 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
6345 14:45:37.330409 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
6346 14:45:37.350847 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
6347 14:45:37.399722 Starting [0;1;39msystemd-backlight…ess of backlight:backlight_lcd0...
6348 14:45:37.535236 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6349 14:45:37.559836 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6350 14:45:37.584732 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6351 14:45:37.619930 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
6352 14:45:37.642048 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
6353 14:45:37.660410 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6354 14:45:37.679578 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
6355 14:45:37.701824 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6356 14:45:37.722522 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6357 14:45:37.742594 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6358 14:45:37.763161 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6359 14:45:37.782729 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6360 14:45:37.800130 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
6361 14:45:37.819566 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
6362 14:45:37.839769 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
6363 14:45:37.866021 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
6364 14:45:37.885108 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
6365 14:45:37.903498 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
6366 14:45:37.926426 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
6367 14:45:37.947681 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6368 14:45:37.967257 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
6369 14:45:37.983039 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6370 14:45:38.003752 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
6371 14:45:38.023194 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
6372 14:45:38.044438 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
6373 14:45:38.084458 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
6374 14:45:38.103723 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
6375 14:45:38.175546 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
6376 14:45:38.273884 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6377 14:45:38.300409 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
6378 14:45:38.328293 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
6379 14:45:38.348423 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
6380 14:45:38.458717 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6381 14:45:38.511225 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6382 14:45:38.543467 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6383 14:45:38.563472 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6384 14:45:38.586467 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6385 14:45:38.617687 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
6386 14:45:38.642102 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6387 14:45:38.661506 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6388 14:45:38.681542 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6389 14:45:38.733419 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6390 14:45:38.796200 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6391 14:45:38.870697
6392 14:45:38.873857 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6393 14:45:38.873940
6394 14:45:38.877000 debian-bookworm-arm64 login: root (automatic login)
6395 14:45:38.877086
6396 14:45:39.166304 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024 aarch64
6397 14:45:39.166782
6398 14:45:39.173123 The programs included with the Debian GNU/Linux system are free software;
6399 14:45:39.179355 the exact distribution terms for each program are described in the
6400 14:45:39.182800 individual files in /usr/share/doc/*/copyright.
6401 14:45:39.183211
6402 14:45:39.189592 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6403 14:45:39.193119 permitted by applicable law.
6404 14:45:40.349924 Matched prompt #10: / #
6406 14:45:40.350221 Setting prompt string to ['/ #']
6407 14:45:40.350315 end: 2.2.5.1 login-action (duration 00:00:19) [common]
6409 14:45:40.350585 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
6410 14:45:40.350676 start: 2.2.6 expect-shell-connection (timeout 00:03:47) [common]
6411 14:45:40.350756 Setting prompt string to ['/ #']
6412 14:45:40.350818 Forcing a shell prompt, looking for ['/ #']
6414 14:45:40.401012 / #
6415 14:45:40.401122 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6416 14:45:40.401200 Waiting using forced prompt support (timeout 00:02:30)
6417 14:45:40.406210
6418 14:45:40.406472 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6419 14:45:40.406561 start: 2.2.7 export-device-env (timeout 00:03:47) [common]
6421 14:45:40.506881 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14166990/extract-nfsrootfs-830ytlfh'
6422 14:45:40.511607 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14166990/extract-nfsrootfs-830ytlfh'
6424 14:45:40.612066 / # export NFS_SERVER_IP='192.168.201.1'
6425 14:45:40.617431 export NFS_SERVER_IP='192.168.201.1'
6426 14:45:40.617705 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6427 14:45:40.617835 end: 2.2 depthcharge-retry (duration 00:01:13) [common]
6428 14:45:40.617938 end: 2 depthcharge-action (duration 00:01:13) [common]
6429 14:45:40.618029 start: 3 lava-test-retry (timeout 00:08:07) [common]
6430 14:45:40.618112 start: 3.1 lava-test-shell (timeout 00:08:07) [common]
6431 14:45:40.618193 Using namespace: common
6433 14:45:40.718470 / # #
6434 14:45:40.718647 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
6435 14:45:40.723616 #
6436 14:45:40.723871 Using /lava-14166990
6438 14:45:40.824168 / # export SHELL=/bin/bash
6439 14:45:40.828871 export SHELL=/bin/bash
6441 14:45:40.929380 / # . /lava-14166990/environment
6442 14:45:40.933897 . /lava-14166990/environment
6444 14:45:41.038516 / # /lava-14166990/bin/lava-test-runner /lava-14166990/0
6445 14:45:41.038673 Test shell timeout: 10s (minimum of the action and connection timeout)
6446 14:45:41.043720 /lava-14166990/bin/lava-test-runner /lava-14166990/0
6447 14:45:41.255008 + export TESTRUN_ID=0_timesync-off
6448 14:45:41.258585 + TESTRUN_ID=0_timesync-off
6449 14:45:41.261725 + cd /lava-14166990/0/tests/0_timesync-off
6450 14:45:41.264883 ++ cat uuid
6451 14:45:41.264957 + UUID=14166990_1.6.2.3.1
6452 14:45:41.268396 + set +x
6453 14:45:41.271548 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14166990_1.6.2.3.1>
6454 14:45:41.271810 Received signal: <STARTRUN> 0_timesync-off 14166990_1.6.2.3.1
6455 14:45:41.271882 Starting test lava.0_timesync-off (14166990_1.6.2.3.1)
6456 14:45:41.272007 Skipping test definition patterns.
6457 14:45:41.274950 + systemctl stop systemd-timesyncd
6458 14:45:41.317029 + set +x
6459 14:45:41.320199 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14166990_1.6.2.3.1>
6460 14:45:41.320450 Received signal: <ENDRUN> 0_timesync-off 14166990_1.6.2.3.1
6461 14:45:41.320535 Ending use of test pattern.
6462 14:45:41.320603 Ending test lava.0_timesync-off (14166990_1.6.2.3.1), duration 0.05
6464 14:45:41.369568 + export TESTRUN_ID=1_kselftest-alsa
6465 14:45:41.372818 + TESTRUN_ID=1_kselftest-alsa
6466 14:45:41.379348 + cd /lava-14166990/0/tests/1_kselftest-alsa
6467 14:45:41.379427 ++ cat uuid
6468 14:45:41.382970 + UUID=14166990_1.6.2.3.5
6469 14:45:41.383046 + set +x
6470 14:45:41.385805 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 14166990_1.6.2.3.5>
6471 14:45:41.386056 Received signal: <STARTRUN> 1_kselftest-alsa 14166990_1.6.2.3.5
6472 14:45:41.386127 Starting test lava.1_kselftest-alsa (14166990_1.6.2.3.5)
6473 14:45:41.386203 Skipping test definition patterns.
6474 14:45:41.389172 + cd ./automated/linux/kselftest/
6475 14:45:41.419291 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8183-kukui-jacuzzi-juniper-sku16 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
6476 14:45:41.442189 INFO: install_deps skipped
6477 14:45:41.931298 --2024-06-04 14:45:40-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
6478 14:45:41.940499 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
6479 14:45:42.072952 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
6480 14:45:42.201651 HTTP request sent, awaiting response... 200 OK
6481 14:45:42.204999 Length: 1647736 (1.6M) [application/octet-stream]
6482 14:45:42.208207 Saving to: 'kselftest_armhf.tar.gz'
6483 14:45:42.208308
6484 14:45:42.208402
6485 14:45:42.458469 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
6486 14:45:42.716310 kselftest_armhf.tar 2%[ ] 46.39K 181KB/s
6487 14:45:42.987210 kselftest_armhf.tar 13%[=> ] 217.50K 423KB/s
6488 14:45:43.259731 kselftest_armhf.tar 32%[=====> ] 518.21K 660KB/s
6489 14:45:43.266368 kselftest_armhf.tar 90%[=================> ] 1.42M 1.35MB/s
6490 14:45:43.272867 kselftest_armhf.tar 100%[===================>] 1.57M 1.48MB/s in 1.1s
6491 14:45:43.272982
6492 14:45:43.412782 2024-06-04 14:45:42 (1.48 MB/s) - 'kselftest_armhf.tar.gz' saved [1647736/1647736]
6493 14:45:43.412953
6494 14:45:47.251485 skiplist:
6495 14:45:47.254522 ========================================
6496 14:45:47.257777 ========================================
6497 14:45:47.293774 alsa:mixer-test
6498 14:45:47.310642 ============== Tests to run ===============
6499 14:45:47.310756 alsa:mixer-test
6500 14:45:47.317403 ===========End Tests to run ===============
6501 14:45:47.317510 shardfile-alsa pass
6502 14:45:47.429167 <12>[ 25.695525] kselftest: Running tests in alsa
6503 14:45:47.439543 TAP version 13
6504 14:45:47.456448 1..1
6505 14:45:47.475653 # selftests: alsa: mixer-test
6506 14:45:47.583289 <6>[ 25.843043] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6507 14:45:47.596348 <6>[ 25.855387] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6508 14:45:47.609457 <6>[ 25.867632] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 1
6509 14:45:47.619351 <6>[ 25.879846] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6510 14:45:47.632737 <6>[ 25.892035] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6511 14:45:47.642781 <6>[ 25.904410] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6512 14:45:47.656272 <6>[ 25.915998] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6513 14:45:47.665783 <6>[ 25.927369] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 1
6514 14:45:47.679297 <6>[ 25.938711] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6515 14:45:47.689152 <6>[ 25.950051] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6516 14:45:47.702566 <6>[ 25.961407] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6517 14:45:47.712520 <6>[ 25.972743] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6518 14:45:47.722039 <6>[ 25.984075] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 1
6519 14:45:47.735377 <6>[ 25.995407] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6520 14:45:47.745612 <6>[ 26.006742] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6521 14:45:47.758674 <6>[ 26.018080] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6522 14:45:47.768989 <6>[ 26.029412] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6523 14:45:47.778651 <6>[ 26.040767] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 1
6524 14:45:47.791849 <6>[ 26.052096] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6525 14:45:47.801996 <6>[ 26.063429] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6526 14:45:47.814999 <6>[ 26.074766] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6527 14:45:47.825313 <6>[ 26.086104] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6528 14:45:47.838695 <6>[ 26.097434] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 1
6529 14:45:47.848606 <6>[ 26.108763] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6530 14:45:47.858484 <6>[ 26.120094] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6531 14:45:47.871408 <6>[ 26.131428] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6532 14:45:47.881654 <6>[ 26.142759] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6533 14:45:47.895058 <6>[ 26.154088] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 1
6534 14:45:47.904810 <6>[ 26.165416] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6535 14:45:47.914514 <6>[ 26.176748] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6536 14:45:47.922899 # TAP version 13
6537 14:45:47.922981 # 1..658
6538 14:45:47.925868 # ok 1 get_value.0.93
6539 14:45:47.925949 # ok 2 name.0.93
6540 14:45:47.929889 # ok 3 write_default.0.93
6541 14:45:47.932700 # ok 4 write_valid.0.93
6542 14:45:47.932781 # ok 5 write_invalid.0.93
6543 14:45:47.936395 # ok 6 event_missing.0.93
6544 14:45:47.939348 # ok 7 event_spurious.0.93
6545 14:45:47.939428 # ok 8 get_value.0.92
6546 14:45:47.943091 # ok 9 name.0.92
6547 14:45:47.946366 # ok 10 write_default.0.92
6548 14:45:47.946446 # ok 11 write_valid.0.92
6549 14:45:47.949337 # ok 12 write_invalid.0.92
6550 14:45:47.952726 # ok 13 event_missing.0.92
6551 14:45:47.955919 # ok 14 event_spurious.0.92
6552 14:45:47.955999 # ok 15 get_value.0.91
6553 14:45:47.959250 # ok 16 name.0.91
6554 14:45:47.959331 # ok 17 write_default.0.91
6555 14:45:47.962494 # ok 18 write_valid.0.91
6556 14:45:47.965794 # ok 19 write_invalid.0.91
6557 14:45:47.969150 # ok 20 event_missing.0.91
6558 14:45:47.969246 # ok 21 event_spurious.0.91
6559 14:45:47.972915 # ok 22 get_value.0.90
6560 14:45:47.973011 # ok 23 name.0.90
6561 14:45:47.975941 # ok 24 write_default.0.90
6562 14:45:47.979164 # ok 25 write_valid.0.90
6563 14:45:47.982631 # ok 26 write_invalid.0.90
6564 14:45:47.982711 # ok 27 event_missing.0.90
6565 14:45:47.985789 # ok 28 event_spurious.0.90
6566 14:45:47.989138 # ok 29 get_value.0.89
6567 14:45:47.989241 # ok 30 name.0.89
6568 14:45:47.992846 # ok 31 write_default.0.89
6569 14:45:47.996109 # ok 32 write_valid.0.89
6570 14:45:47.999029 # ok 33 write_invalid.0.89
6571 14:45:47.999098 # ok 34 event_missing.0.89
6572 14:45:48.002730 # ok 35 event_spurious.0.89
6573 14:45:48.005603 # ok 36 get_value.0.88
6574 14:45:48.005702 # ok 37 name.0.88
6575 14:45:48.009090 # ok 38 write_default.0.88
6576 14:45:48.012297 # # Spurious event generated for AIF Out Mux
6577 14:45:48.019183 # # AIF Out Mux.0 expected 1 but read 0, is_volatile 0
6578 14:45:48.022749 # # Spurious event generated for AIF Out Mux
6579 14:45:48.025627 # not ok 39 write_valid.0.88
6580 14:45:48.028821 # ok 40 write_invalid.0.88
6581 14:45:48.032173 # ok 41 event_missing.0.88
6582 14:45:48.032253 # not ok 42 event_spurious.0.88
6583 14:45:48.035488 # ok 43 get_value.0.87
6584 14:45:48.038764 # ok 44 name.0.87
6585 14:45:48.038845 # ok 45 write_default.0.87
6586 14:45:48.042198 # ok 46 write_valid.0.87
6587 14:45:48.045697 # ok 47 write_invalid.0.87
6588 14:45:48.049154 # ok 48 event_missing.0.87
6589 14:45:48.049234 # ok 49 event_spurious.0.87
6590 14:45:48.052055 # ok 50 get_value.0.86
6591 14:45:48.055385 # ok 51 name.0.86
6592 14:45:48.055465 # ok 52 write_default.0.86
6593 14:45:48.062069 # # HPR Mux.0 expected 5 but read 0, is_volatile 0
6594 14:45:48.065230 # # HPR Mux.0 expected 6 but read 0, is_volatile 0
6595 14:45:48.071804 # # HPR Mux.0 expected 7 but read 0, is_volatile 0
6596 14:45:48.071885 # not ok 53 write_valid.0.86
6597 14:45:48.075365 # ok 54 write_invalid.0.86
6598 14:45:48.078963 # ok 55 event_missing.0.86
6599 14:45:48.082180 # ok 56 event_spurious.0.86
6600 14:45:48.082261 # ok 57 get_value.0.85
6601 14:45:48.085239 # ok 58 name.0.85
6602 14:45:48.088996 # ok 59 write_default.0.85
6603 14:45:48.091969 # # HPL Mux.0 expected 5 but read 0, is_volatile 0
6604 14:45:48.095038 # # HPL Mux.0 expected 6 but read 0, is_volatile 0
6605 14:45:48.101633 # # HPL Mux.0 expected 7 but read 0, is_volatile 0
6606 14:45:48.105175 # not ok 60 write_valid.0.85
6607 14:45:48.105321 # ok 61 write_invalid.0.85
6608 14:45:48.108293 # ok 62 event_missing.0.85
6609 14:45:48.111686 # ok 63 event_spurious.0.85
6610 14:45:48.115022 # ok 64 get_value.0.84
6611 14:45:48.115102 # ok 65 name.0.84
6612 14:45:48.118213 # ok 66 write_default.0.84
6613 14:45:48.121751 # ok 67 write_valid.0.84
6614 14:45:48.121831 # ok 68 write_invalid.0.84
6615 14:45:48.124992 # ok 69 event_missing.0.84
6616 14:45:48.128289 # ok 70 event_spurious.0.84
6617 14:45:48.131823 # ok 71 get_value.0.83
6618 14:45:48.131903 # ok 72 name.0.83
6619 14:45:48.134962 # ok 73 write_default.0.83
6620 14:45:48.138129 # ok 74 write_valid.0.83
6621 14:45:48.138210 # ok 75 write_invalid.0.83
6622 14:45:48.141531 # ok 76 event_missing.0.83
6623 14:45:48.145088 # ok 77 event_spurious.0.83
6624 14:45:48.148407 # ok 78 get_value.0.82
6625 14:45:48.148488 # ok 79 name.0.82
6626 14:45:48.151532 # # Headset Jack is not writeable
6627 14:45:48.154764 # ok 80 # SKIP write_default.0.82
6628 14:45:48.158522 # # Headset Jack is not writeable
6629 14:45:48.161720 # ok 81 # SKIP write_valid.0.82
6630 14:45:48.164706 # # Headset Jack is not writeable
6631 14:45:48.168798 # ok 82 # SKIP write_invalid.0.82
6632 14:45:48.168878 # ok 83 event_missing.0.82
6633 14:45:48.171704 # ok 84 event_spurious.0.82
6634 14:45:48.175117 # ok 85 get_value.0.81
6635 14:45:48.175197 # ok 86 name.0.81
6636 14:45:48.178145 # ok 87 write_default.0.81
6637 14:45:48.184927 # # No event generated for Wake-on-Voice Phase2 Switch
6638 14:45:48.188079 # # No event generated for Wake-on-Voice Phase2 Switch
6639 14:45:48.191590 # ok 88 write_valid.0.81
6640 14:45:48.195043 # # Wake-on-Voice Phase2 Switch.0 Invalid boolean value 2
6641 14:45:48.201247 # # No event generated for Wake-on-Voice Phase2 Switch
6642 14:45:48.204903 # not ok 89 write_invalid.0.81
6643 14:45:48.208213 # not ok 90 event_missing.0.81
6644 14:45:48.208293 # ok 91 event_spurious.0.81
6645 14:45:48.211456 # ok 92 get_value.0.80
6646 14:45:48.215025 # ok 93 name.0.80
6647 14:45:48.215105 # ok 94 write_default.0.80
6648 14:45:48.217818 # ok 95 write_valid.0.80
6649 14:45:48.221551 # ok 96 write_invalid.0.80
6650 14:45:48.224424 # ok 97 event_missing.0.80
6651 14:45:48.224504 # ok 98 event_spurious.0.80
6652 14:45:48.231276 # # Handset Volume.0 value -13 less than minimum 0
6653 14:45:48.231359 # not ok 99 get_value.0.79
6654 14:45:48.234445 # ok 100 name.0.79
6655 14:45:48.237695 # # snd_ctl_elem_write() failed: Invalid argument
6656 14:45:48.240874 # not ok 101 write_default.0.79
6657 14:45:48.248011 # # snd_ctl_elem_write() failed: Invalid argument
6658 14:45:48.248102 # not ok 102 write_valid.0.79
6659 14:45:48.254502 # # snd_ctl_elem_write() failed: Invalid argument
6660 14:45:48.257583 # not ok 103 write_invalid.0.79
6661 14:45:48.257664 # ok 104 event_missing.0.79
6662 14:45:48.260732 # ok 105 event_spurious.0.79
6663 14:45:48.264679 # # Lineout Volume.0 value -13 less than minimum 0
6664 14:45:48.270701 # # Lineout Volume.1 value -13 less than minimum 0
6665 14:45:48.274309 # not ok 106 get_value.0.78
6666 14:45:48.274390 # ok 107 name.0.78
6667 14:45:48.277873 # # snd_ctl_elem_write() failed: Invalid argument
6668 14:45:48.280687 # not ok 108 write_default.0.78
6669 14:45:48.287548 # # snd_ctl_elem_write() failed: Invalid argument
6670 14:45:48.287630 # not ok 109 write_valid.0.78
6671 14:45:48.294075 # # snd_ctl_elem_write() failed: Invalid argument
6672 14:45:48.297510 # not ok 110 write_invalid.0.78
6673 14:45:48.297592 # ok 111 event_missing.0.78
6674 14:45:48.300904 # ok 112 event_spurious.0.78
6675 14:45:48.307240 # # Headphone Volume.0 value -13 less than minimum 0
6676 14:45:48.310642 # # Headphone Volume.1 value -13 less than minimum 0
6677 14:45:48.314503 # not ok 113 get_value.0.77
6678 14:45:48.314585 # ok 114 name.0.77
6679 14:45:48.321021 # # snd_ctl_elem_write() failed: Invalid argument
6680 14:45:48.321103 # not ok 115 write_default.0.77
6681 14:45:48.327342 # # snd_ctl_elem_write() failed: Invalid argument
6682 14:45:48.330616 # not ok 116 write_valid.0.77
6683 14:45:48.333902 # # snd_ctl_elem_write() failed: Invalid argument
6684 14:45:48.337173 # not ok 117 write_invalid.0.77
6685 14:45:48.340519 # ok 118 event_missing.0.77
6686 14:45:48.340600 # ok 119 event_spurious.0.77
6687 14:45:48.344073 # ok 120 get_value.0.76
6688 14:45:48.350737 # # 0.76 ADDA_DL_CH2 PCM_2_CAP_CH2 is a writeable boolean but not a Switch
6689 14:45:48.354089 # not ok 121 name.0.76
6690 14:45:48.354170 # ok 122 write_default.0.76
6691 14:45:48.357513 # ok 123 write_valid.0.76
6692 14:45:48.360728 # ok 124 write_invalid.0.76
6693 14:45:48.364597 # ok 125 event_missing.0.76
6694 14:45:48.364678 # ok 126 event_spurious.0.76
6695 14:45:48.367472 # ok 127 get_value.0.75
6696 14:45:48.373758 # # 0.75 ADDA_DL_CH2 PCM_1_CAP_CH2 is a writeable boolean but not a Switch
6697 14:45:48.377613 # not ok 128 name.0.75
6698 14:45:48.377694 # ok 129 write_default.0.75
6699 14:45:48.380711 # ok 130 write_valid.0.75
6700 14:45:48.383948 # ok 131 write_invalid.0.75
6701 14:45:48.387191 # ok 132 event_missing.0.75
6702 14:45:48.387272 # ok 133 event_spurious.0.75
6703 14:45:48.390404 # ok 134 get_value.0.74
6704 14:45:48.397025 # # 0.74 ADDA_DL_CH2 PCM_2_CAP_CH1 is a writeable boolean but not a Switch
6705 14:45:48.400495 # not ok 135 name.0.74
6706 14:45:48.400577 # ok 136 write_default.0.74
6707 14:45:48.403763 # ok 137 write_valid.0.74
6708 14:45:48.407315 # ok 138 write_invalid.0.74
6709 14:45:48.410590 # ok 139 event_missing.0.74
6710 14:45:48.410672 # ok 140 event_spurious.0.74
6711 14:45:48.413651 # ok 141 get_value.0.73
6712 14:45:48.420179 # # 0.73 ADDA_DL_CH2 PCM_1_CAP_CH1 is a writeable boolean but not a Switch
6713 14:45:48.423638 # not ok 142 name.0.73
6714 14:45:48.423719 # ok 143 write_default.0.73
6715 14:45:48.426947 # ok 144 write_valid.0.73
6716 14:45:48.430175 # ok 145 write_invalid.0.73
6717 14:45:48.433776 # ok 146 event_missing.0.73
6718 14:45:48.433856 # ok 147 event_spurious.0.73
6719 14:45:48.437201 # ok 148 get_value.0.72
6720 14:45:48.443594 # # 0.72 ADDA_DL_CH2 ADDA_UL_CH1 is a writeable boolean but not a Switch
6721 14:45:48.447053 # not ok 149 name.0.72
6722 14:45:48.447134 # ok 150 write_default.0.72
6723 14:45:48.450305 # ok 151 write_valid.0.72
6724 14:45:48.453505 # ok 152 write_invalid.0.72
6725 14:45:48.457484 # ok 153 event_missing.0.72
6726 14:45:48.457566 # ok 154 event_spurious.0.72
6727 14:45:48.460381 # ok 155 get_value.0.71
6728 14:45:48.467022 # # 0.71 ADDA_DL_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
6729 14:45:48.470295 # not ok 156 name.0.71
6730 14:45:48.470376 # ok 157 write_default.0.71
6731 14:45:48.473913 # ok 158 write_valid.0.71
6732 14:45:48.476897 # ok 159 write_invalid.0.71
6733 14:45:48.480210 # ok 160 event_missing.0.71
6734 14:45:48.480292 # ok 161 event_spurious.0.71
6735 14:45:48.483536 # ok 162 get_value.0.70
6736 14:45:48.490085 # # 0.70 ADDA_DL_CH2 DL3_CH2 is a writeable boolean but not a Switch
6737 14:45:48.493828 # not ok 163 name.0.70
6738 14:45:48.493909 # ok 164 write_default.0.70
6739 14:45:48.497076 # ok 165 write_valid.0.70
6740 14:45:48.500525 # ok 166 write_invalid.0.70
6741 14:45:48.503629 # ok 167 event_missing.0.70
6742 14:45:48.506915 # ok 168 event_spurious.0.70
6743 14:45:48.506996 # ok 169 get_value.0.69
6744 14:45:48.513731 # # 0.69 ADDA_DL_CH2 DL3_CH1 is a writeable boolean but not a Switch
6745 14:45:48.516962 # not ok 170 name.0.69
6746 14:45:48.520845 # ok 171 write_default.0.69
6747 14:45:48.523592 # ok 172 write_valid.0.69
6748 14:45:48.523671 # ok 173 write_invalid.0.69
6749 14:45:48.526847 # ok 174 event_missing.0.69
6750 14:45:48.530119 # ok 175 event_spurious.0.69
6751 14:45:48.533705 # ok 176 get_value.0.68
6752 14:45:48.540359 # # 0.68 ADDA_DL_CH2 DL2_CH2 is a writeable boolean but not a Switch
6753 14:45:48.540440 # not ok 177 name.0.68
6754 14:45:48.543835 # ok 178 write_default.0.68
6755 14:45:48.546601 # ok 179 write_valid.0.68
6756 14:45:48.550158 # ok 180 write_invalid.0.68
6757 14:45:48.550239 # ok 181 event_missing.0.68
6758 14:45:48.553249 # ok 182 event_spurious.0.68
6759 14:45:48.556580 # ok 183 get_value.0.67
6760 14:45:48.563651 # # 0.67 ADDA_DL_CH2 DL2_CH1 is a writeable boolean but not a Switch
6761 14:45:48.563733 # not ok 184 name.0.67
6762 14:45:48.566951 # ok 185 write_default.0.67
6763 14:45:48.569738 # ok 186 write_valid.0.67
6764 14:45:48.569819 # ok 187 write_invalid.0.67
6765 14:45:48.573264 # ok 188 event_missing.0.67
6766 14:45:48.576650 # ok 189 event_spurious.0.67
6767 14:45:48.580065 # ok 190 get_value.0.66
6768 14:45:48.586663 # # 0.66 ADDA_DL_CH2 DL1_CH2 is a writeable boolean but not a Switch
6769 14:45:48.586748 # not ok 191 name.0.66
6770 14:45:48.589868 # ok 192 write_default.0.66
6771 14:45:48.593163 # ok 193 write_valid.0.66
6772 14:45:48.593243 # ok 194 write_invalid.0.66
6773 14:45:48.596443 # ok 195 event_missing.0.66
6774 14:45:48.599637 # ok 196 event_spurious.0.66
6775 14:45:48.603496 # ok 197 get_value.0.65
6776 14:45:48.606587 # # 0.65 ADDA_DL_CH2 DL1_CH1 is a writeable boolean but not a Switch
6777 14:45:48.609734 # not ok 198 name.0.65
6778 14:45:48.613196 # ok 199 write_default.0.65
6779 14:45:48.613319 # ok 200 write_valid.0.65
6780 14:45:48.616560 # ok 201 write_invalid.0.65
6781 14:45:48.619510 # ok 202 event_missing.0.65
6782 14:45:48.622944 # ok 203 event_spurious.0.65
6783 14:45:48.623024 # ok 204 get_value.0.64
6784 14:45:48.629419 # # 0.64 ADDA_DL_CH1 PCM_2_CAP_CH1 is a writeable boolean but not a Switch
6785 14:45:48.632975 # not ok 205 name.0.64
6786 14:45:48.636012 # ok 206 write_default.0.64
6787 14:45:48.639332 # ok 207 write_valid.0.64
6788 14:45:48.639412 # ok 208 write_invalid.0.64
6789 14:45:48.642738 # ok 209 event_missing.0.64
6790 14:45:48.646175 # ok 210 event_spurious.0.64
6791 14:45:48.646255 # ok 211 get_value.0.63
6792 14:45:48.652556 # # 0.63 ADDA_DL_CH1 PCM_1_CAP_CH1 is a writeable boolean but not a Switch
6793 14:45:48.656082 # not ok 212 name.0.63
6794 14:45:48.659500 # ok 213 write_default.0.63
6795 14:45:48.662779 # ok 214 write_valid.0.63
6796 14:45:48.662859 # ok 215 write_invalid.0.63
6797 14:45:48.665983 # ok 216 event_missing.0.63
6798 14:45:48.669386 # ok 217 event_spurious.0.63
6799 14:45:48.672766 # ok 218 get_value.0.62
6800 14:45:48.676033 # # 0.62 ADDA_DL_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
6801 14:45:48.679392 # not ok 219 name.0.62
6802 14:45:48.682383 # ok 220 write_default.0.62
6803 14:45:48.685649 # ok 221 write_valid.0.62
6804 14:45:48.685729 # ok 222 write_invalid.0.62
6805 14:45:48.689091 # ok 223 event_missing.0.62
6806 14:45:48.692560 # ok 224 event_spurious.0.62
6807 14:45:48.695780 # ok 225 get_value.0.61
6808 14:45:48.699270 # # 0.61 ADDA_DL_CH1 ADDA_UL_CH2 is a writeable boolean but not a Switch
6809 14:45:48.702588 # not ok 226 name.0.61
6810 14:45:48.705762 # ok 227 write_default.0.61
6811 14:45:48.709221 # ok 228 write_valid.0.61
6812 14:45:48.709347 # ok 229 write_invalid.0.61
6813 14:45:48.712679 # ok 230 event_missing.0.61
6814 14:45:48.715994 # ok 231 event_spurious.0.61
6815 14:45:48.718999 # ok 232 get_value.0.60
6816 14:45:48.722295 # # 0.60 ADDA_DL_CH1 DL3_CH1 is a writeable boolean but not a Switch
6817 14:45:48.725810 # not ok 233 name.0.60
6818 14:45:48.728936 # ok 234 write_default.0.60
6819 14:45:48.732336 # ok 235 write_valid.0.60
6820 14:45:48.732417 # ok 236 write_invalid.0.60
6821 14:45:48.736027 # ok 237 event_missing.0.60
6822 14:45:48.739221 # ok 238 event_spurious.0.60
6823 14:45:48.742099 # ok 239 get_value.0.59
6824 14:45:48.748744 # # 0.59 ADDA_DL_CH1 DL2_CH1 is a writeable boolean but not a Switch
6825 14:45:48.748825 # not ok 240 name.0.59
6826 14:45:48.752426 # ok 241 write_default.0.59
6827 14:45:48.755457 # ok 242 write_valid.0.59
6828 14:45:48.758754 # ok 243 write_invalid.0.59
6829 14:45:48.758834 # ok 244 event_missing.0.59
6830 14:45:48.762133 # ok 245 event_spurious.0.59
6831 14:45:48.765582 # ok 246 get_value.0.58
6832 14:45:48.772484 # # 0.58 ADDA_DL_CH1 DL1_CH1 is a writeable boolean but not a Switch
6833 14:45:48.772566 # not ok 247 name.0.58
6834 14:45:48.775826 # ok 248 write_default.0.58
6835 14:45:48.778921 # ok 249 write_valid.0.58
6836 14:45:48.782431 # ok 250 write_invalid.0.58
6837 14:45:48.782512 # ok 251 event_missing.0.58
6838 14:45:48.785390 # ok 252 event_spurious.0.58
6839 14:45:48.788880 # ok 253 get_value.0.57
6840 14:45:48.795326 # # 0.57 I2S5_CH2 DL3_CH2 is a writeable boolean but not a Switch
6841 14:45:48.795407 # not ok 254 name.0.57
6842 14:45:48.798877 # ok 255 write_default.0.57
6843 14:45:48.802001 # ok 256 write_valid.0.57
6844 14:45:48.805411 # ok 257 write_invalid.0.57
6845 14:45:48.808470 # ok 258 event_missing.0.57
6846 14:45:48.808550 # ok 259 event_spurious.0.57
6847 14:45:48.812006 # ok 260 get_value.0.56
6848 14:45:48.818690 # # 0.56 I2S5_CH2 DL2_CH2 is a writeable boolean but not a Switch
6849 14:45:48.818771 # not ok 261 name.0.56
6850 14:45:48.821750 # ok 262 write_default.0.56
6851 14:45:48.825129 # ok 263 write_valid.0.56
6852 14:45:48.828782 # ok 264 write_invalid.0.56
6853 14:45:48.828862 # ok 265 event_missing.0.56
6854 14:45:48.831705 # ok 266 event_spurious.0.56
6855 14:45:48.835122 # ok 267 get_value.0.55
6856 14:45:48.841677 # # 0.55 I2S5_CH2 DL1_CH2 is a writeable boolean but not a Switch
6857 14:45:48.841758 # not ok 268 name.0.55
6858 14:45:48.844787 # ok 269 write_default.0.55
6859 14:45:48.848033 # ok 270 write_valid.0.55
6860 14:45:48.848113 # ok 271 write_invalid.0.55
6861 14:45:48.851527 # ok 272 event_missing.0.55
6862 14:45:48.855037 # ok 273 event_spurious.0.55
6863 14:45:48.858303 # ok 274 get_value.0.54
6864 14:45:48.862039 # # 0.54 I2S5_CH1 DL3_CH1 is a writeable boolean but not a Switch
6865 14:45:48.865065 # not ok 275 name.0.54
6866 14:45:48.868311 # ok 276 write_default.0.54
6867 14:45:48.868391 # ok 277 write_valid.0.54
6868 14:45:48.871666 # ok 278 write_invalid.0.54
6869 14:45:48.874669 # ok 279 event_missing.0.54
6870 14:45:48.878406 # ok 280 event_spurious.0.54
6871 14:45:48.878486 # ok 281 get_value.0.53
6872 14:45:48.884812 # # 0.53 I2S5_CH1 DL2_CH1 is a writeable boolean but not a Switch
6873 14:45:48.888283 # not ok 282 name.0.53
6874 14:45:48.891580 # ok 283 write_default.0.53
6875 14:45:48.891661 # ok 284 write_valid.0.53
6876 14:45:48.894939 # ok 285 write_invalid.0.53
6877 14:45:48.897981 # ok 286 event_missing.0.53
6878 14:45:48.901603 # ok 287 event_spurious.0.53
6879 14:45:48.901683 # ok 288 get_value.0.52
6880 14:45:48.908203 # # 0.52 I2S5_CH1 DL1_CH1 is a writeable boolean but not a Switch
6881 14:45:48.911415 # not ok 289 name.0.52
6882 14:45:48.911495 # ok 290 write_default.0.52
6883 14:45:48.914735 # ok 291 write_valid.0.52
6884 14:45:48.918159 # ok 292 write_invalid.0.52
6885 14:45:48.921430 # ok 293 event_missing.0.52
6886 14:45:48.921511 # ok 294 event_spurious.0.52
6887 14:45:48.924740 # ok 295 get_value.0.51
6888 14:45:48.931197 # # 0.51 I2S3_CH2 DL3_CH2 is a writeable boolean but not a Switch
6889 14:45:48.931279 # not ok 296 name.0.51
6890 14:45:48.934658 # ok 297 write_default.0.51
6891 14:45:48.938031 # ok 298 write_valid.0.51
6892 14:45:48.941463 # ok 299 write_invalid.0.51
6893 14:45:48.941544 # ok 300 event_missing.0.51
6894 14:45:48.944421 # ok 301 event_spurious.0.51
6895 14:45:48.947666 # ok 302 get_value.0.50
6896 14:45:48.954339 # # 0.50 I2S3_CH2 DL2_CH2 is a writeable boolean but not a Switch
6897 14:45:48.954421 # not ok 303 name.0.50
6898 14:45:48.957668 # ok 304 write_default.0.50
6899 14:45:48.960913 # ok 305 write_valid.0.50
6900 14:45:48.960993 # ok 306 write_invalid.0.50
6901 14:45:48.964261 # ok 307 event_missing.0.50
6902 14:45:48.967474 # ok 308 event_spurious.0.50
6903 14:45:48.971049 # ok 309 get_value.0.49
6904 14:45:48.977622 # # 0.49 I2S3_CH2 DL1_CH2 is a writeable boolean but not a Switch
6905 14:45:48.977703 # not ok 310 name.0.49
6906 14:45:48.980749 # ok 311 write_default.0.49
6907 14:45:48.984334 # ok 312 write_valid.0.49
6908 14:45:48.984414 # ok 313 write_invalid.0.49
6909 14:45:48.987880 # ok 314 event_missing.0.49
6910 14:45:48.991299 # ok 315 event_spurious.0.49
6911 14:45:48.994180 # ok 316 get_value.0.48
6912 14:45:49.000869 # # 0.48 I2S3_CH1 DL3_CH1 is a writeable boolean but not a Switch
6913 14:45:49.000950 # not ok 317 name.0.48
6914 14:45:49.004213 # ok 318 write_default.0.48
6915 14:45:49.007538 # ok 319 write_valid.0.48
6916 14:45:49.007619 # ok 320 write_invalid.0.48
6917 14:45:49.011477 # ok 321 event_missing.0.48
6918 14:45:49.014710 # ok 322 event_spurious.0.48
6919 14:45:49.017558 # ok 323 get_value.0.47
6920 14:45:49.021398 # # 0.47 I2S3_CH1 DL2_CH1 is a writeable boolean but not a Switch
6921 14:45:49.024335 # not ok 324 name.0.47
6922 14:45:49.027712 # ok 325 write_default.0.47
6923 14:45:49.031041 # ok 326 write_valid.0.47
6924 14:45:49.031121 # ok 327 write_invalid.0.47
6925 14:45:49.034686 # ok 328 event_missing.0.47
6926 14:45:49.037982 # ok 329 event_spurious.0.47
6927 14:45:49.038062 # ok 330 get_value.0.46
6928 14:45:49.044396 # # 0.46 I2S3_CH1 DL1_CH1 is a writeable boolean but not a Switch
6929 14:45:49.047707 # not ok 331 name.0.46
6930 14:45:49.050961 # ok 332 write_default.0.46
6931 14:45:49.051042 # ok 333 write_valid.0.46
6932 14:45:49.053975 # ok 334 write_invalid.0.46
6933 14:45:49.057619 # ok 335 event_missing.0.46
6934 14:45:49.060648 # ok 336 event_spurious.0.46
6935 14:45:49.060730 # ok 337 get_value.0.45
6936 14:45:49.067697 # # 0.45 I2S1_CH2 DL3_CH2 is a writeable boolean but not a Switch
6937 14:45:49.070882 # not ok 338 name.0.45
6938 14:45:49.070964 # ok 339 write_default.0.45
6939 14:45:49.073847 # ok 340 write_valid.0.45
6940 14:45:49.077320 # ok 341 write_invalid.0.45
6941 14:45:49.080837 # ok 342 event_missing.0.45
6942 14:45:49.080921 # ok 343 event_spurious.0.45
6943 14:45:49.084283 # ok 344 get_value.0.44
6944 14:45:49.090487 # # 0.44 I2S1_CH2 DL2_CH2 is a writeable boolean but not a Switch
6945 14:45:49.090572 # not ok 345 name.0.44
6946 14:45:49.094045 # ok 346 write_default.0.44
6947 14:45:49.097186 # ok 347 write_valid.0.44
6948 14:45:49.100728 # ok 348 write_invalid.0.44
6949 14:45:49.100813 # ok 349 event_missing.0.44
6950 14:45:49.104411 # ok 350 event_spurious.0.44
6951 14:45:49.107347 # ok 351 get_value.0.43
6952 14:45:49.114202 # # 0.43 I2S1_CH2 DL1_CH2 is a writeable boolean but not a Switch
6953 14:45:49.114287 # not ok 352 name.0.43
6954 14:45:49.117555 # ok 353 write_default.0.43
6955 14:45:49.120762 # ok 354 write_valid.0.43
6956 14:45:49.120845 # ok 355 write_invalid.0.43
6957 14:45:49.124212 # ok 356 event_missing.0.43
6958 14:45:49.127274 # ok 357 event_spurious.0.43
6959 14:45:49.130962 # ok 358 get_value.0.42
6960 14:45:49.134168 # # 0.42 I2S1_CH1 DL3_CH1 is a writeable boolean but not a Switch
6961 14:45:49.137320 # not ok 359 name.0.42
6962 14:45:49.140828 # ok 360 write_default.0.42
6963 14:45:49.140912 # ok 361 write_valid.0.42
6964 14:45:49.144158 # ok 362 write_invalid.0.42
6965 14:45:49.147654 # ok 363 event_missing.0.42
6966 14:45:49.150434 # ok 364 event_spurious.0.42
6967 14:45:49.150518 # ok 365 get_value.0.41
6968 14:45:49.157968 # # 0.41 I2S1_CH1 DL2_CH1 is a writeable boolean but not a Switch
6969 14:45:49.160306 # not ok 366 name.0.41
6970 14:45:49.164159 # ok 367 write_default.0.41
6971 14:45:49.164244 # ok 368 write_valid.0.41
6972 14:45:49.167502 # ok 369 write_invalid.0.41
6973 14:45:49.170330 # ok 370 event_missing.0.41
6974 14:45:49.173733 # ok 371 event_spurious.0.41
6975 14:45:49.173817 # ok 372 get_value.0.40
6976 14:45:49.180490 # # 0.40 I2S1_CH1 DL1_CH1 is a writeable boolean but not a Switch
6977 14:45:49.183640 # not ok 373 name.0.40
6978 14:45:49.183725 # ok 374 write_default.0.40
6979 14:45:49.186876 # ok 375 write_valid.0.40
6980 14:45:49.190148 # ok 376 write_invalid.0.40
6981 14:45:49.193441 # ok 377 event_missing.0.40
6982 14:45:49.193521 # ok 378 event_spurious.0.40
6983 14:45:49.197000 # ok 379 get_value.0.39
6984 14:45:49.203643 # # 0.39 PCM_2_PB_CH4 DL1_CH1 is a writeable boolean but not a Switch
6985 14:45:49.206834 # not ok 380 name.0.39
6986 14:45:49.206917 # ok 381 write_default.0.39
6987 14:45:49.210837 # ok 382 write_valid.0.39
6988 14:45:49.213629 # ok 383 write_invalid.0.39
6989 14:45:49.217134 # ok 384 event_missing.0.39
6990 14:45:49.217215 # ok 385 event_spurious.0.39
6991 14:45:49.220571 # ok 386 get_value.0.38
6992 14:45:49.226907 # # 0.38 PCM_2_PB_CH2 DL2_CH2 is a writeable boolean but not a Switch
6993 14:45:49.226989 # not ok 387 name.0.38
6994 14:45:49.230143 # ok 388 write_default.0.38
6995 14:45:49.233621 # ok 389 write_valid.0.38
6996 14:45:49.236742 # ok 390 write_invalid.0.38
6997 14:45:49.236823 # ok 391 event_missing.0.38
6998 14:45:49.240447 # ok 392 event_spurious.0.38
6999 14:45:49.243300 # ok 393 get_value.0.37
7000 14:45:49.249873 # # 0.37 PCM_2_PB_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7001 14:45:49.249955 # not ok 394 name.0.37
7002 14:45:49.253178 # ok 395 write_default.0.37
7003 14:45:49.256619 # ok 396 write_valid.0.37
7004 14:45:49.260623 # ok 397 write_invalid.0.37
7005 14:45:49.260704 # ok 398 event_missing.0.37
7006 14:45:49.263465 # ok 399 event_spurious.0.37
7007 14:45:49.266886 # ok 400 get_value.0.36
7008 14:45:49.273245 # # 0.36 PCM_2_PB_CH1 DL2_CH1 is a writeable boolean but not a Switch
7009 14:45:49.273332 # not ok 401 name.0.36
7010 14:45:49.276525 # ok 402 write_default.0.36
7011 14:45:49.279861 # ok 403 write_valid.0.36
7012 14:45:49.283026 # ok 404 write_invalid.0.36
7013 14:45:49.283108 # ok 405 event_missing.0.36
7014 14:45:49.286411 # ok 406 event_spurious.0.36
7015 14:45:49.289708 # ok 407 get_value.0.35
7016 14:45:49.296321 # # 0.35 PCM_2_PB_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7017 14:45:49.296405 # not ok 408 name.0.35
7018 14:45:49.299499 # ok 409 write_default.0.35
7019 14:45:49.302959 # ok 410 write_valid.0.35
7020 14:45:49.306284 # ok 411 write_invalid.0.35
7021 14:45:49.306365 # ok 412 event_missing.0.35
7022 14:45:49.309820 # ok 413 event_spurious.0.35
7023 14:45:49.313169 # ok 414 get_value.0.34
7024 14:45:49.319621 # # 0.34 PCM_1_PB_CH4 DL1_CH1 is a writeable boolean but not a Switch
7025 14:45:49.319704 # not ok 415 name.0.34
7026 14:45:49.322717 # ok 416 write_default.0.34
7027 14:45:49.326010 # ok 417 write_valid.0.34
7028 14:45:49.329467 # ok 418 write_invalid.0.34
7029 14:45:49.329574 # ok 419 event_missing.0.34
7030 14:45:49.333215 # ok 420 event_spurious.0.34
7031 14:45:49.336072 # ok 421 get_value.0.33
7032 14:45:49.342705 # # 0.33 PCM_1_PB_CH2 DL2_CH2 is a writeable boolean but not a Switch
7033 14:45:49.342787 # not ok 422 name.0.33
7034 14:45:49.346016 # ok 423 write_default.0.33
7035 14:45:49.349289 # ok 424 write_valid.0.33
7036 14:45:49.349370 # ok 425 write_invalid.0.33
7037 14:45:49.352471 # ok 426 event_missing.0.33
7038 14:45:49.355876 # ok 427 event_spurious.0.33
7039 14:45:49.359122 # ok 428 get_value.0.32
7040 14:45:49.365891 # # 0.32 PCM_1_PB_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7041 14:45:49.365973 # not ok 429 name.0.32
7042 14:45:49.369556 # ok 430 write_default.0.32
7043 14:45:49.372342 # ok 431 write_valid.0.32
7044 14:45:49.372423 # ok 432 write_invalid.0.32
7045 14:45:49.375850 # ok 433 event_missing.0.32
7046 14:45:49.379438 # ok 434 event_spurious.0.32
7047 14:45:49.382313 # ok 435 get_value.0.31
7048 14:45:49.389151 # # 0.31 PCM_1_PB_CH1 DL2_CH1 is a writeable boolean but not a Switch
7049 14:45:49.389234 # not ok 436 name.0.31
7050 14:45:49.392588 # ok 437 write_default.0.31
7051 14:45:49.395645 # ok 438 write_valid.0.31
7052 14:45:49.395726 # ok 439 write_invalid.0.31
7053 14:45:49.398960 # ok 440 event_missing.0.31
7054 14:45:49.402538 # ok 441 event_spurious.0.31
7055 14:45:49.405944 # ok 442 get_value.0.30
7056 14:45:49.412341 # # 0.30 PCM_1_PB_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7057 14:45:49.412423 # not ok 443 name.0.30
7058 14:45:49.415924 # ok 444 write_default.0.30
7059 14:45:49.419253 # ok 445 write_valid.0.30
7060 14:45:49.419334 # ok 446 write_invalid.0.30
7061 14:45:49.422007 # ok 447 event_missing.0.30
7062 14:45:49.425449 # ok 448 event_spurious.0.30
7063 14:45:49.428716 # ok 449 get_value.0.29
7064 14:45:49.428798 # ok 450 name.0.29
7065 14:45:49.432199 # ok 451 write_default.0.29
7066 14:45:49.435550 # ok 452 write_valid.0.29
7067 14:45:49.435632 # ok 453 write_invalid.0.29
7068 14:45:49.438727 # ok 454 event_missing.0.29
7069 14:45:49.442309 # ok 455 event_spurious.0.29
7070 14:45:49.445415 # ok 456 get_value.0.28
7071 14:45:49.445499 # ok 457 name.0.28
7072 14:45:49.448499 # ok 458 write_default.0.28
7073 14:45:49.452110 # ok 459 write_valid.0.28
7074 14:45:49.452195 # ok 460 write_invalid.0.28
7075 14:45:49.455454 # ok 461 event_missing.0.28
7076 14:45:49.459038 # ok 462 event_spurious.0.28
7077 14:45:49.461836 # ok 463 get_value.0.27
7078 14:45:49.461920 # ok 464 name.0.27
7079 14:45:49.465196 # ok 465 write_default.0.27
7080 14:45:49.468574 # ok 466 write_valid.0.27
7081 14:45:49.468658 # ok 467 write_invalid.0.27
7082 14:45:49.472053 # ok 468 event_missing.0.27
7083 14:45:49.475434 # ok 469 event_spurious.0.27
7084 14:45:49.475519 # ok 470 get_value.0.26
7085 14:45:49.478725 # ok 471 name.0.26
7086 14:45:49.481619 # ok 472 write_default.0.26
7087 14:45:49.485237 # ok 473 write_valid.0.26
7088 14:45:49.485343 # ok 474 write_invalid.0.26
7089 14:45:49.488254 # ok 475 event_missing.0.26
7090 14:45:49.491810 # ok 476 event_spurious.0.26
7091 14:45:49.491894 # ok 477 get_value.0.25
7092 14:45:49.495166 # ok 478 name.0.25
7093 14:45:49.498110 # ok 479 write_default.0.25
7094 14:45:49.498194 # ok 480 write_valid.0.25
7095 14:45:49.501662 # ok 481 write_invalid.0.25
7096 14:45:49.505043 # ok 482 event_missing.0.25
7097 14:45:49.508221 # ok 483 event_spurious.0.25
7098 14:45:49.508306 # ok 484 get_value.0.24
7099 14:45:49.511900 # ok 485 name.0.24
7100 14:45:49.514927 # ok 486 write_default.0.24
7101 14:45:49.515025 # ok 487 write_valid.0.24
7102 14:45:49.518387 # ok 488 write_invalid.0.24
7103 14:45:49.522067 # ok 489 event_missing.0.24
7104 14:45:49.524999 # ok 490 event_spurious.0.24
7105 14:45:49.525083 # ok 491 get_value.0.23
7106 14:45:49.528264 # ok 492 name.0.23
7107 14:45:49.531590 # ok 493 write_default.0.23
7108 14:45:49.531674 # ok 494 write_valid.0.23
7109 14:45:49.534804 # ok 495 write_invalid.0.23
7110 14:45:49.538267 # ok 496 event_missing.0.23
7111 14:45:49.541608 # ok 497 event_spurious.0.23
7112 14:45:49.541692 # ok 498 get_value.0.22
7113 14:45:49.545306 # ok 499 name.0.22
7114 14:45:49.549009 # ok 500 write_default.0.22
7115 14:45:49.549093 # ok 501 write_valid.0.22
7116 14:45:49.551416 # ok 502 write_invalid.0.22
7117 14:45:49.554900 # ok 503 event_missing.0.22
7118 14:45:49.558406 # ok 504 event_spurious.0.22
7119 14:45:49.558489 # ok 505 get_value.0.21
7120 14:45:49.564864 # # 0.21 UL_MONO_1_CH1 ADDA_UL_CH2 is a writeable boolean but not a Switch
7121 14:45:49.568414 # not ok 506 name.0.21
7122 14:45:49.571281 # ok 507 write_default.0.21
7123 14:45:49.571366 # ok 508 write_valid.0.21
7124 14:45:49.575110 # ok 509 write_invalid.0.21
7125 14:45:49.577954 # ok 510 event_missing.0.21
7126 14:45:49.581515 # ok 511 event_spurious.0.21
7127 14:45:49.581599 # ok 512 get_value.0.20
7128 14:45:49.587966 # # 0.20 UL_MONO_1_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7129 14:45:49.591185 # not ok 513 name.0.20
7130 14:45:49.594839 # ok 514 write_default.0.20
7131 14:45:49.594919 # ok 515 write_valid.0.20
7132 14:45:49.598145 # ok 516 write_invalid.0.20
7133 14:45:49.601724 # ok 517 event_missing.0.20
7134 14:45:49.604599 # ok 518 event_spurious.0.20
7135 14:45:49.604683 # ok 519 get_value.0.19
7136 14:45:49.611364 # # 0.19 UL4_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7137 14:45:49.614957 # not ok 520 name.0.19
7138 14:45:49.617943 # ok 521 write_default.0.19
7139 14:45:49.618026 # ok 522 write_valid.0.19
7140 14:45:49.621450 # ok 523 write_invalid.0.19
7141 14:45:49.624422 # ok 524 event_missing.0.19
7142 14:45:49.628093 # ok 525 event_spurious.0.19
7143 14:45:49.628177 # ok 526 get_value.0.18
7144 14:45:49.634736 # # 0.18 UL4_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7145 14:45:49.638308 # not ok 527 name.0.18
7146 14:45:49.638392 # ok 528 write_default.0.18
7147 14:45:49.641146 # ok 529 write_valid.0.18
7148 14:45:49.644627 # ok 530 write_invalid.0.18
7149 14:45:49.647938 # ok 531 event_missing.0.18
7150 14:45:49.648021 # ok 532 event_spurious.0.18
7151 14:45:49.651020 # ok 533 get_value.0.17
7152 14:45:49.657927 # # 0.17 UL3_CH2 I2S2_CH2 is a writeable boolean but not a Switch
7153 14:45:49.658012 # not ok 534 name.0.17
7154 14:45:49.661098 # ok 535 write_default.0.17
7155 14:45:49.664382 # ok 536 write_valid.0.17
7156 14:45:49.667586 # ok 537 write_invalid.0.17
7157 14:45:49.667670 # ok 538 event_missing.0.17
7158 14:45:49.671127 # ok 539 event_spurious.0.17
7159 14:45:49.674353 # ok 540 get_value.0.16
7160 14:45:49.680803 # # 0.16 UL3_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7161 14:45:49.680888 # not ok 541 name.0.16
7162 14:45:49.684124 # ok 542 write_default.0.16
7163 14:45:49.687841 # ok 543 write_valid.0.16
7164 14:45:49.691184 # ok 544 write_invalid.0.16
7165 14:45:49.691268 # ok 545 event_missing.0.16
7166 14:45:49.694118 # ok 546 event_spurious.0.16
7167 14:45:49.697587 # ok 547 get_value.0.15
7168 14:45:49.704108 # # 0.15 UL3_CH1 I2S2_CH1 is a writeable boolean but not a Switch
7169 14:45:49.704192 # not ok 548 name.0.15
7170 14:45:49.707551 # ok 549 write_default.0.15
7171 14:45:49.710686 # ok 550 write_valid.0.15
7172 14:45:49.710771 # ok 551 write_invalid.0.15
7173 14:45:49.714270 # ok 552 event_missing.0.15
7174 14:45:49.717580 # ok 553 event_spurious.0.15
7175 14:45:49.720724 # ok 554 get_value.0.14
7176 14:45:49.723686 # # 0.14 UL3_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7177 14:45:49.727265 # not ok 555 name.0.14
7178 14:45:49.730523 # ok 556 write_default.0.14
7179 14:45:49.733948 # ok 557 write_valid.0.14
7180 14:45:49.734032 # ok 558 write_invalid.0.14
7181 14:45:49.737277 # ok 559 event_missing.0.14
7182 14:45:49.740298 # ok 560 event_spurious.0.14
7183 14:45:49.743593 # ok 561 get_value.0.13
7184 14:45:49.747009 # # 0.13 UL2_CH2 I2S2_CH2 is a writeable boolean but not a Switch
7185 14:45:49.750279 # not ok 562 name.0.13
7186 14:45:49.753736 # ok 563 write_default.0.13
7187 14:45:49.753820 # ok 564 write_valid.0.13
7188 14:45:49.757203 # ok 565 write_invalid.0.13
7189 14:45:49.760243 # ok 566 event_missing.0.13
7190 14:45:49.763715 # ok 567 event_spurious.0.13
7191 14:45:49.763799 # ok 568 get_value.0.12
7192 14:45:49.770058 # # 0.12 UL2_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7193 14:45:49.773396 # not ok 569 name.0.12
7194 14:45:49.776718 # ok 570 write_default.0.12
7195 14:45:49.776802 # ok 571 write_valid.0.12
7196 14:45:49.780071 # ok 572 write_invalid.0.12
7197 14:45:49.783469 # ok 573 event_missing.0.12
7198 14:45:49.786867 # ok 574 event_spurious.0.12
7199 14:45:49.786951 # ok 575 get_value.0.11
7200 14:45:49.793547 # # 0.11 UL2_CH1 I2S2_CH1 is a writeable boolean but not a Switch
7201 14:45:49.796632 # not ok 576 name.0.11
7202 14:45:49.796716 # ok 577 write_default.0.11
7203 14:45:49.800407 # ok 578 write_valid.0.11
7204 14:45:49.803890 # ok 579 write_invalid.0.11
7205 14:45:49.806914 # ok 580 event_missing.0.11
7206 14:45:49.806998 # ok 581 event_spurious.0.11
7207 14:45:49.810253 # ok 582 get_value.0.10
7208 14:45:49.816662 # # 0.10 UL2_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7209 14:45:49.816747 # not ok 583 name.0.10
7210 14:45:49.820375 # ok 584 write_default.0.10
7211 14:45:49.823246 # ok 585 write_valid.0.10
7212 14:45:49.826541 # ok 586 write_invalid.0.10
7213 14:45:49.826625 # ok 587 event_missing.0.10
7214 14:45:49.829857 # ok 588 event_spurious.0.10
7215 14:45:49.833543 # ok 589 get_value.0.9
7216 14:45:49.839745 # # 0.9 UL1_CH2 I2S0_CH2 is a writeable boolean but not a Switch
7217 14:45:49.839830 # not ok 590 name.0.9
7218 14:45:49.843202 # ok 591 write_default.0.9
7219 14:45:49.846948 # ok 592 write_valid.0.9
7220 14:45:49.847032 # ok 593 write_invalid.0.9
7221 14:45:49.849960 # ok 594 event_missing.0.9
7222 14:45:49.853472 # ok 595 event_spurious.0.9
7223 14:45:49.856526 # ok 596 get_value.0.8
7224 14:45:49.859852 # # 0.8 UL1_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7225 14:45:49.862870 # not ok 597 name.0.8
7226 14:45:49.866313 # ok 598 write_default.0.8
7227 14:45:49.866397 # ok 599 write_valid.0.8
7228 14:45:49.869719 # ok 600 write_invalid.0.8
7229 14:45:49.872964 # ok 601 event_missing.0.8
7230 14:45:49.876377 # ok 602 event_spurious.0.8
7231 14:45:49.876461 # ok 603 get_value.0.7
7232 14:45:49.883849 # # 0.7 UL1_CH1 I2S0_CH1 is a writeable boolean but not a Switch
7233 14:45:49.886206 # not ok 604 name.0.7
7234 14:45:49.886290 # ok 605 write_default.0.7
7235 14:45:49.889254 # ok 606 write_valid.0.7
7236 14:45:49.893187 # ok 607 write_invalid.0.7
7237 14:45:49.893308 # ok 608 event_missing.0.7
7238 14:45:49.896432 # ok 609 event_spurious.0.7
7239 14:45:49.899349 # ok 610 get_value.0.6
7240 14:45:49.906175 # # 0.6 UL1_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7241 14:45:49.906260 # not ok 611 name.0.6
7242 14:45:49.909060 # ok 612 write_default.0.6
7243 14:45:49.912478 # ok 613 write_valid.0.6
7244 14:45:49.912562 # ok 614 write_invalid.0.6
7245 14:45:49.915720 # ok 615 event_missing.0.6
7246 14:45:49.919044 # ok 616 event_spurious.0.6
7247 14:45:49.922367 # ok 617 get_value.0.5
7248 14:45:49.922451 # ok 618 name.0.5
7249 14:45:49.926207 # ok 619 write_default.0.5
7250 14:45:49.929059 # # No event generated for MTKAIF_DMIC
7251 14:45:49.932254 # # No event generated for MTKAIF_DMIC
7252 14:45:49.935992 # ok 620 write_valid.0.5
7253 14:45:49.936076 # ok 621 write_invalid.0.5
7254 14:45:49.939278 # not ok 622 event_missing.0.5
7255 14:45:49.942276 # ok 623 event_spurious.0.5
7256 14:45:49.942361 # ok 624 get_value.0.4
7257 14:45:49.945849 # ok 625 name.0.4
7258 14:45:49.949228 # ok 626 write_default.0.4
7259 14:45:49.952315 # # No event generated for I2S5_HD_Mux
7260 14:45:49.955674 # # No event generated for I2S5_HD_Mux
7261 14:45:49.959292 # ok 627 write_valid.0.4
7262 14:45:49.959376 # ok 628 write_invalid.0.4
7263 14:45:49.962312 # not ok 629 event_missing.0.4
7264 14:45:49.965575 # ok 630 event_spurious.0.4
7265 14:45:49.965659 # ok 631 get_value.0.3
7266 14:45:49.969110 # ok 632 name.0.3
7267 14:45:49.972342 # ok 633 write_default.0.3
7268 14:45:49.975607 # # No event generated for I2S3_HD_Mux
7269 14:45:49.978634 # # No event generated for I2S3_HD_Mux
7270 14:45:49.978718 # ok 634 write_valid.0.3
7271 14:45:49.982150 # ok 635 write_invalid.0.3
7272 14:45:49.985266 # not ok 636 event_missing.0.3
7273 14:45:49.989035 # ok 637 event_spurious.0.3
7274 14:45:49.989119 # ok 638 get_value.0.2
7275 14:45:49.991944 # ok 639 name.0.2
7276 14:45:49.995452 # ok 640 write_default.0.2
7277 14:45:49.999025 # # No event generated for I2S2_HD_Mux
7278 14:45:50.001987 # # No event generated for I2S2_HD_Mux
7279 14:45:50.002071 # ok 641 write_valid.0.2
7280 14:45:50.005685 # ok 642 write_invalid.0.2
7281 14:45:50.009203 # not ok 643 event_missing.0.2
7282 14:45:50.012388 # ok 644 event_spurious.0.2
7283 14:45:50.012473 # ok 645 get_value.0.1
7284 14:45:50.015672 # ok 646 name.0.1
7285 14:45:50.018883 # ok 647 write_default.0.1
7286 14:45:50.022458 # # No event generated for I2S1_HD_Mux
7287 14:45:50.025590 # # No event generated for I2S1_HD_Mux
7288 14:45:50.025674 # ok 648 write_valid.0.1
7289 14:45:50.029195 # ok 649 write_invalid.0.1
7290 14:45:50.032434 # not ok 650 event_missing.0.1
7291 14:45:50.035703 # ok 651 event_spurious.0.1
7292 14:45:50.035787 # ok 652 get_value.0.0
7293 14:45:50.039046 # ok 653 name.0.0
7294 14:45:50.039130 # ok 654 write_default.0.0
7295 14:45:50.042276 # # No event generated for I2S0_HD_Mux
7296 14:45:50.049175 # # No event generated for I2S0_HD_Mux
7297 14:45:50.049288 # ok 655 write_valid.0.0
7298 14:45:50.052037 # ok 656 write_invalid.0.0
7299 14:45:50.055464 # not ok 657 event_missing.0.0
7300 14:45:50.058766 # ok 658 event_spurious.0.0
7301 14:45:50.062168 # # Totals: pass:568 fail:87 xfail:0 xpass:0 skip:3 error:0
7302 14:45:50.065511 ok 1 selftests: alsa: mixer-test
7303 14:45:51.603149 alsa_mixer-test_get_value_0_93 pass
7304 14:45:51.606108 alsa_mixer-test_name_0_93 pass
7305 14:45:51.609765 alsa_mixer-test_write_default_0_93 pass
7306 14:45:51.613398 alsa_mixer-test_write_valid_0_93 pass
7307 14:45:51.619631 alsa_mixer-test_write_invalid_0_93 pass
7308 14:45:51.622947 alsa_mixer-test_event_missing_0_93 pass
7309 14:45:51.626201 alsa_mixer-test_event_spurious_0_93 pass
7310 14:45:51.629518 alsa_mixer-test_get_value_0_92 pass
7311 14:45:51.633120 alsa_mixer-test_name_0_92 pass
7312 14:45:51.637118 alsa_mixer-test_write_default_0_92 pass
7313 14:45:51.639596 alsa_mixer-test_write_valid_0_92 pass
7314 14:45:51.642624 alsa_mixer-test_write_invalid_0_92 pass
7315 14:45:51.646178 alsa_mixer-test_event_missing_0_92 pass
7316 14:45:51.649620 alsa_mixer-test_event_spurious_0_92 pass
7317 14:45:51.653092 alsa_mixer-test_get_value_0_91 pass
7318 14:45:51.656130 alsa_mixer-test_name_0_91 pass
7319 14:45:51.659662 alsa_mixer-test_write_default_0_91 pass
7320 14:45:51.662764 alsa_mixer-test_write_valid_0_91 pass
7321 14:45:51.665796 alsa_mixer-test_write_invalid_0_91 pass
7322 14:45:51.669633 alsa_mixer-test_event_missing_0_91 pass
7323 14:45:51.672343 alsa_mixer-test_event_spurious_0_91 pass
7324 14:45:51.675917 alsa_mixer-test_get_value_0_90 pass
7325 14:45:51.679227 alsa_mixer-test_name_0_90 pass
7326 14:45:51.682187 alsa_mixer-test_write_default_0_90 pass
7327 14:45:51.685744 alsa_mixer-test_write_valid_0_90 pass
7328 14:45:51.692773 alsa_mixer-test_write_invalid_0_90 pass
7329 14:45:51.695814 alsa_mixer-test_event_missing_0_90 pass
7330 14:45:51.699285 alsa_mixer-test_event_spurious_0_90 pass
7331 14:45:51.702580 alsa_mixer-test_get_value_0_89 pass
7332 14:45:51.705778 alsa_mixer-test_name_0_89 pass
7333 14:45:51.709239 alsa_mixer-test_write_default_0_89 pass
7334 14:45:51.712744 alsa_mixer-test_write_valid_0_89 pass
7335 14:45:51.715968 alsa_mixer-test_write_invalid_0_89 pass
7336 14:45:51.719202 alsa_mixer-test_event_missing_0_89 pass
7337 14:45:51.722271 alsa_mixer-test_event_spurious_0_89 pass
7338 14:45:51.728685 alsa_mixer-test_get_value_0_88 pass
7339 14:45:51.728860 alsa_mixer-test_name_0_88 pass
7340 14:45:51.735496 alsa_mixer-test_write_default_0_88 pass
7341 14:45:51.738517 alsa_mixer-test_write_valid_0_88 fail
7342 14:45:51.742268 alsa_mixer-test_write_invalid_0_88 pass
7343 14:45:51.745544 alsa_mixer-test_event_missing_0_88 pass
7344 14:45:51.748602 alsa_mixer-test_event_spurious_0_88 fail
7345 14:45:51.751731 alsa_mixer-test_get_value_0_87 pass
7346 14:45:51.755209 alsa_mixer-test_name_0_87 pass
7347 14:45:51.758537 alsa_mixer-test_write_default_0_87 pass
7348 14:45:51.765546 alsa_mixer-test_write_valid_0_87 pass
7349 14:45:51.768580 alsa_mixer-test_write_invalid_0_87 pass
7350 14:45:51.772156 alsa_mixer-test_event_missing_0_87 pass
7351 14:45:51.775272 alsa_mixer-test_event_spurious_0_87 pass
7352 14:45:51.778704 alsa_mixer-test_get_value_0_86 pass
7353 14:45:51.782454 alsa_mixer-test_name_0_86 pass
7354 14:45:51.785401 alsa_mixer-test_write_default_0_86 pass
7355 14:45:51.788406 alsa_mixer-test_write_valid_0_86 fail
7356 14:45:51.795185 alsa_mixer-test_write_invalid_0_86 pass
7357 14:45:51.798689 alsa_mixer-test_event_missing_0_86 pass
7358 14:45:51.801600 alsa_mixer-test_event_spurious_0_86 pass
7359 14:45:51.805052 alsa_mixer-test_get_value_0_85 pass
7360 14:45:51.808443 alsa_mixer-test_name_0_85 pass
7361 14:45:51.811926 alsa_mixer-test_write_default_0_85 pass
7362 14:45:51.814989 alsa_mixer-test_write_valid_0_85 fail
7363 14:45:51.818206 alsa_mixer-test_write_invalid_0_85 pass
7364 14:45:51.825350 alsa_mixer-test_event_missing_0_85 pass
7365 14:45:51.828576 alsa_mixer-test_event_spurious_0_85 pass
7366 14:45:51.831612 alsa_mixer-test_get_value_0_84 pass
7367 14:45:51.835537 alsa_mixer-test_name_0_84 pass
7368 14:45:51.838502 alsa_mixer-test_write_default_0_84 pass
7369 14:45:51.841800 alsa_mixer-test_write_valid_0_84 pass
7370 14:45:51.845204 alsa_mixer-test_write_invalid_0_84 pass
7371 14:45:51.848280 alsa_mixer-test_event_missing_0_84 pass
7372 14:45:51.854856 alsa_mixer-test_event_spurious_0_84 pass
7373 14:45:51.858448 alsa_mixer-test_get_value_0_83 pass
7374 14:45:51.861817 alsa_mixer-test_name_0_83 pass
7375 14:45:51.864996 alsa_mixer-test_write_default_0_83 pass
7376 14:45:51.868332 alsa_mixer-test_write_valid_0_83 pass
7377 14:45:51.871570 alsa_mixer-test_write_invalid_0_83 pass
7378 14:45:51.875322 alsa_mixer-test_event_missing_0_83 pass
7379 14:45:51.878315 alsa_mixer-test_event_spurious_0_83 pass
7380 14:45:51.881789 alsa_mixer-test_get_value_0_82 pass
7381 14:45:51.885313 alsa_mixer-test_name_0_82 pass
7382 14:45:51.891569 alsa_mixer-test_write_default_0_82 skip
7383 14:45:51.895182 alsa_mixer-test_write_valid_0_82 skip
7384 14:45:51.898162 alsa_mixer-test_write_invalid_0_82 skip
7385 14:45:51.901629 alsa_mixer-test_event_missing_0_82 pass
7386 14:45:51.904855 alsa_mixer-test_event_spurious_0_82 pass
7387 14:45:51.908172 alsa_mixer-test_get_value_0_81 pass
7388 14:45:51.911924 alsa_mixer-test_name_0_81 pass
7389 14:45:51.914624 alsa_mixer-test_write_default_0_81 pass
7390 14:45:51.921366 alsa_mixer-test_write_valid_0_81 pass
7391 14:45:51.924969 alsa_mixer-test_write_invalid_0_81 fail
7392 14:45:51.928522 alsa_mixer-test_event_missing_0_81 fail
7393 14:45:51.931280 alsa_mixer-test_event_spurious_0_81 pass
7394 14:45:51.934999 alsa_mixer-test_get_value_0_80 pass
7395 14:45:51.938235 alsa_mixer-test_name_0_80 pass
7396 14:45:51.941336 alsa_mixer-test_write_default_0_80 pass
7397 14:45:51.944790 alsa_mixer-test_write_valid_0_80 pass
7398 14:45:51.948276 alsa_mixer-test_write_invalid_0_80 pass
7399 14:45:51.954836 alsa_mixer-test_event_missing_0_80 pass
7400 14:45:51.958269 alsa_mixer-test_event_spurious_0_80 pass
7401 14:45:51.961727 alsa_mixer-test_get_value_0_79 fail
7402 14:45:51.965123 alsa_mixer-test_name_0_79 pass
7403 14:45:51.968462 alsa_mixer-test_write_default_0_79 fail
7404 14:45:51.971800 alsa_mixer-test_write_valid_0_79 fail
7405 14:45:51.975072 alsa_mixer-test_write_invalid_0_79 fail
7406 14:45:51.978278 alsa_mixer-test_event_missing_0_79 pass
7407 14:45:51.984549 alsa_mixer-test_event_spurious_0_79 pass
7408 14:45:51.988424 alsa_mixer-test_get_value_0_78 fail
7409 14:45:51.991725 alsa_mixer-test_name_0_78 pass
7410 14:45:51.994776 alsa_mixer-test_write_default_0_78 fail
7411 14:45:51.998066 alsa_mixer-test_write_valid_0_78 fail
7412 14:45:52.001433 alsa_mixer-test_write_invalid_0_78 fail
7413 14:45:52.004704 alsa_mixer-test_event_missing_0_78 pass
7414 14:45:52.008114 alsa_mixer-test_event_spurious_0_78 pass
7415 14:45:52.011569 alsa_mixer-test_get_value_0_77 fail
7416 14:45:52.014540 alsa_mixer-test_name_0_77 pass
7417 14:45:52.020815 alsa_mixer-test_write_default_0_77 fail
7418 14:45:52.024005 alsa_mixer-test_write_valid_0_77 fail
7419 14:45:52.027497 alsa_mixer-test_write_invalid_0_77 fail
7420 14:45:52.030718 alsa_mixer-test_event_missing_0_77 pass
7421 14:45:52.034056 alsa_mixer-test_event_spurious_0_77 pass
7422 14:45:52.037349 alsa_mixer-test_get_value_0_76 pass
7423 14:45:52.041068 alsa_mixer-test_name_0_76 fail
7424 14:45:52.044153 alsa_mixer-test_write_default_0_76 pass
7425 14:45:52.047441 alsa_mixer-test_write_valid_0_76 pass
7426 14:45:52.054218 alsa_mixer-test_write_invalid_0_76 pass
7427 14:45:52.057685 alsa_mixer-test_event_missing_0_76 pass
7428 14:45:52.060557 alsa_mixer-test_event_spurious_0_76 pass
7429 14:45:52.064333 alsa_mixer-test_get_value_0_75 pass
7430 14:45:52.067062 alsa_mixer-test_name_0_75 fail
7431 14:45:52.070259 alsa_mixer-test_write_default_0_75 pass
7432 14:45:52.073860 alsa_mixer-test_write_valid_0_75 pass
7433 14:45:52.077046 alsa_mixer-test_write_invalid_0_75 pass
7434 14:45:52.083699 alsa_mixer-test_event_missing_0_75 pass
7435 14:45:52.086728 alsa_mixer-test_event_spurious_0_75 pass
7436 14:45:52.090374 alsa_mixer-test_get_value_0_74 pass
7437 14:45:52.093587 alsa_mixer-test_name_0_74 fail
7438 14:45:52.097032 alsa_mixer-test_write_default_0_74 pass
7439 14:45:52.100229 alsa_mixer-test_write_valid_0_74 pass
7440 14:45:52.103602 alsa_mixer-test_write_invalid_0_74 pass
7441 14:45:52.106964 alsa_mixer-test_event_missing_0_74 pass
7442 14:45:52.113163 alsa_mixer-test_event_spurious_0_74 pass
7443 14:45:52.116645 alsa_mixer-test_get_value_0_73 pass
7444 14:45:52.120043 alsa_mixer-test_name_0_73 fail
7445 14:45:52.123227 alsa_mixer-test_write_default_0_73 pass
7446 14:45:52.126555 alsa_mixer-test_write_valid_0_73 pass
7447 14:45:52.130118 alsa_mixer-test_write_invalid_0_73 pass
7448 14:45:52.133584 alsa_mixer-test_event_missing_0_73 pass
7449 14:45:52.136741 alsa_mixer-test_event_spurious_0_73 pass
7450 14:45:52.140036 alsa_mixer-test_get_value_0_72 pass
7451 14:45:52.143387 alsa_mixer-test_name_0_72 fail
7452 14:45:52.146601 alsa_mixer-test_write_default_0_72 pass
7453 14:45:52.153364 alsa_mixer-test_write_valid_0_72 pass
7454 14:45:52.156699 alsa_mixer-test_write_invalid_0_72 pass
7455 14:45:52.160475 alsa_mixer-test_event_missing_0_72 pass
7456 14:45:52.163420 alsa_mixer-test_event_spurious_0_72 pass
7457 14:45:52.167128 alsa_mixer-test_get_value_0_71 pass
7458 14:45:52.170078 alsa_mixer-test_name_0_71 fail
7459 14:45:52.173598 alsa_mixer-test_write_default_0_71 pass
7460 14:45:52.176836 alsa_mixer-test_write_valid_0_71 pass
7461 14:45:52.180499 alsa_mixer-test_write_invalid_0_71 pass
7462 14:45:52.186790 alsa_mixer-test_event_missing_0_71 pass
7463 14:45:52.190077 alsa_mixer-test_event_spurious_0_71 pass
7464 14:45:52.193613 alsa_mixer-test_get_value_0_70 pass
7465 14:45:52.196759 alsa_mixer-test_name_0_70 fail
7466 14:45:52.200325 alsa_mixer-test_write_default_0_70 pass
7467 14:45:52.203489 alsa_mixer-test_write_valid_0_70 pass
7468 14:45:52.207259 alsa_mixer-test_write_invalid_0_70 pass
7469 14:45:52.210138 alsa_mixer-test_event_missing_0_70 pass
7470 14:45:52.217590 alsa_mixer-test_event_spurious_0_70 pass
7471 14:45:52.220321 alsa_mixer-test_get_value_0_69 pass
7472 14:45:52.224028 alsa_mixer-test_name_0_69 fail
7473 14:45:52.226997 alsa_mixer-test_write_default_0_69 pass
7474 14:45:52.230425 alsa_mixer-test_write_valid_0_69 pass
7475 14:45:52.233804 alsa_mixer-test_write_invalid_0_69 pass
7476 14:45:52.237045 alsa_mixer-test_event_missing_0_69 pass
7477 14:45:52.240353 alsa_mixer-test_event_spurious_0_69 pass
7478 14:45:52.243751 alsa_mixer-test_get_value_0_68 pass
7479 14:45:52.247056 alsa_mixer-test_name_0_68 fail
7480 14:45:52.253415 alsa_mixer-test_write_default_0_68 pass
7481 14:45:52.256785 alsa_mixer-test_write_valid_0_68 pass
7482 14:45:52.260284 alsa_mixer-test_write_invalid_0_68 pass
7483 14:45:52.263131 alsa_mixer-test_event_missing_0_68 pass
7484 14:45:52.266663 alsa_mixer-test_event_spurious_0_68 pass
7485 14:45:52.269767 alsa_mixer-test_get_value_0_67 pass
7486 14:45:52.273162 alsa_mixer-test_name_0_67 fail
7487 14:45:52.276709 alsa_mixer-test_write_default_0_67 pass
7488 14:45:52.283016 alsa_mixer-test_write_valid_0_67 pass
7489 14:45:52.286485 alsa_mixer-test_write_invalid_0_67 pass
7490 14:45:52.289886 alsa_mixer-test_event_missing_0_67 pass
7491 14:45:52.293077 alsa_mixer-test_event_spurious_0_67 pass
7492 14:45:52.296826 alsa_mixer-test_get_value_0_66 pass
7493 14:45:52.299922 alsa_mixer-test_name_0_66 fail
7494 14:45:52.303322 alsa_mixer-test_write_default_0_66 pass
7495 14:45:52.306756 alsa_mixer-test_write_valid_0_66 pass
7496 14:45:52.313000 alsa_mixer-test_write_invalid_0_66 pass
7497 14:45:52.316436 alsa_mixer-test_event_missing_0_66 pass
7498 14:45:52.319754 alsa_mixer-test_event_spurious_0_66 pass
7499 14:45:52.323273 alsa_mixer-test_get_value_0_65 pass
7500 14:45:52.326323 alsa_mixer-test_name_0_65 fail
7501 14:45:52.329728 alsa_mixer-test_write_default_0_65 pass
7502 14:45:52.333160 alsa_mixer-test_write_valid_0_65 pass
7503 14:45:52.336502 alsa_mixer-test_write_invalid_0_65 pass
7504 14:45:52.339687 alsa_mixer-test_event_missing_0_65 pass
7505 14:45:52.346280 alsa_mixer-test_event_spurious_0_65 pass
7506 14:45:52.349311 alsa_mixer-test_get_value_0_64 pass
7507 14:45:52.353011 alsa_mixer-test_name_0_64 fail
7508 14:45:52.356300 alsa_mixer-test_write_default_0_64 pass
7509 14:45:52.359533 alsa_mixer-test_write_valid_0_64 pass
7510 14:45:52.362627 alsa_mixer-test_write_invalid_0_64 pass
7511 14:45:52.366115 alsa_mixer-test_event_missing_0_64 pass
7512 14:45:52.372912 alsa_mixer-test_event_spurious_0_64 pass
7513 14:45:52.376101 alsa_mixer-test_get_value_0_63 pass
7514 14:45:52.379116 alsa_mixer-test_name_0_63 fail
7515 14:45:52.382485 alsa_mixer-test_write_default_0_63 pass
7516 14:45:52.385903 alsa_mixer-test_write_valid_0_63 pass
7517 14:45:52.389197 alsa_mixer-test_write_invalid_0_63 pass
7518 14:45:52.392168 alsa_mixer-test_event_missing_0_63 pass
7519 14:45:52.395751 alsa_mixer-test_event_spurious_0_63 pass
7520 14:45:52.398926 alsa_mixer-test_get_value_0_62 pass
7521 14:45:52.402348 alsa_mixer-test_name_0_62 fail
7522 14:45:52.405821 alsa_mixer-test_write_default_0_62 pass
7523 14:45:52.408812 alsa_mixer-test_write_valid_0_62 pass
7524 14:45:52.412268 alsa_mixer-test_write_invalid_0_62 pass
7525 14:45:52.415631 alsa_mixer-test_event_missing_0_62 pass
7526 14:45:52.418926 alsa_mixer-test_event_spurious_0_62 pass
7527 14:45:52.422245 alsa_mixer-test_get_value_0_61 pass
7528 14:45:52.425462 alsa_mixer-test_name_0_61 fail
7529 14:45:52.428717 alsa_mixer-test_write_default_0_61 pass
7530 14:45:52.432044 alsa_mixer-test_write_valid_0_61 pass
7531 14:45:52.435385 alsa_mixer-test_write_invalid_0_61 pass
7532 14:45:52.442178 alsa_mixer-test_event_missing_0_61 pass
7533 14:45:52.445447 alsa_mixer-test_event_spurious_0_61 pass
7534 14:45:52.448503 alsa_mixer-test_get_value_0_60 pass
7535 14:45:52.448584 alsa_mixer-test_name_0_60 fail
7536 14:45:52.456237 alsa_mixer-test_write_default_0_60 pass
7537 14:45:52.459227 alsa_mixer-test_write_valid_0_60 pass
7538 14:45:52.462298 alsa_mixer-test_write_invalid_0_60 pass
7539 14:45:52.465449 alsa_mixer-test_event_missing_0_60 pass
7540 14:45:52.468966 alsa_mixer-test_event_spurious_0_60 pass
7541 14:45:52.472411 alsa_mixer-test_get_value_0_59 pass
7542 14:45:52.475805 alsa_mixer-test_name_0_59 fail
7543 14:45:52.478974 alsa_mixer-test_write_default_0_59 pass
7544 14:45:52.482364 alsa_mixer-test_write_valid_0_59 pass
7545 14:45:52.485585 alsa_mixer-test_write_invalid_0_59 pass
7546 14:45:52.488946 alsa_mixer-test_event_missing_0_59 pass
7547 14:45:52.492046 alsa_mixer-test_event_spurious_0_59 pass
7548 14:45:52.495483 alsa_mixer-test_get_value_0_58 pass
7549 14:45:52.498870 alsa_mixer-test_name_0_58 fail
7550 14:45:52.501919 alsa_mixer-test_write_default_0_58 pass
7551 14:45:52.505583 alsa_mixer-test_write_valid_0_58 pass
7552 14:45:52.508648 alsa_mixer-test_write_invalid_0_58 pass
7553 14:45:52.511927 alsa_mixer-test_event_missing_0_58 pass
7554 14:45:52.515073 alsa_mixer-test_event_spurious_0_58 pass
7555 14:45:52.518753 alsa_mixer-test_get_value_0_57 pass
7556 14:45:52.521834 alsa_mixer-test_name_0_57 fail
7557 14:45:52.525178 alsa_mixer-test_write_default_0_57 pass
7558 14:45:52.528633 alsa_mixer-test_write_valid_0_57 pass
7559 14:45:52.534987 alsa_mixer-test_write_invalid_0_57 pass
7560 14:45:52.538294 alsa_mixer-test_event_missing_0_57 pass
7561 14:45:52.541707 alsa_mixer-test_event_spurious_0_57 pass
7562 14:45:52.544941 alsa_mixer-test_get_value_0_56 pass
7563 14:45:52.548384 alsa_mixer-test_name_0_56 fail
7564 14:45:52.551568 alsa_mixer-test_write_default_0_56 pass
7565 14:45:52.554875 alsa_mixer-test_write_valid_0_56 pass
7566 14:45:52.558031 alsa_mixer-test_write_invalid_0_56 pass
7567 14:45:52.561687 alsa_mixer-test_event_missing_0_56 pass
7568 14:45:52.564547 alsa_mixer-test_event_spurious_0_56 pass
7569 14:45:52.568169 alsa_mixer-test_get_value_0_55 pass
7570 14:45:52.571065 alsa_mixer-test_name_0_55 fail
7571 14:45:52.574501 alsa_mixer-test_write_default_0_55 pass
7572 14:45:52.577743 alsa_mixer-test_write_valid_0_55 pass
7573 14:45:52.581201 alsa_mixer-test_write_invalid_0_55 pass
7574 14:45:52.584419 alsa_mixer-test_event_missing_0_55 pass
7575 14:45:52.590894 alsa_mixer-test_event_spurious_0_55 pass
7576 14:45:52.594504 alsa_mixer-test_get_value_0_54 pass
7577 14:45:52.594729 alsa_mixer-test_name_0_54 fail
7578 14:45:52.600983 alsa_mixer-test_write_default_0_54 pass
7579 14:45:52.604127 alsa_mixer-test_write_valid_0_54 pass
7580 14:45:52.607385 alsa_mixer-test_write_invalid_0_54 pass
7581 14:45:52.611098 alsa_mixer-test_event_missing_0_54 pass
7582 14:45:52.614036 alsa_mixer-test_event_spurious_0_54 pass
7583 14:45:52.617456 alsa_mixer-test_get_value_0_53 pass
7584 14:45:52.620730 alsa_mixer-test_name_0_53 fail
7585 14:45:52.624016 alsa_mixer-test_write_default_0_53 pass
7586 14:45:52.627505 alsa_mixer-test_write_valid_0_53 pass
7587 14:45:52.630549 alsa_mixer-test_write_invalid_0_53 pass
7588 14:45:52.633999 alsa_mixer-test_event_missing_0_53 pass
7589 14:45:52.637484 alsa_mixer-test_event_spurious_0_53 pass
7590 14:45:52.640569 alsa_mixer-test_get_value_0_52 pass
7591 14:45:52.643826 alsa_mixer-test_name_0_52 fail
7592 14:45:52.646829 alsa_mixer-test_write_default_0_52 pass
7593 14:45:52.653745 alsa_mixer-test_write_valid_0_52 pass
7594 14:45:52.657203 alsa_mixer-test_write_invalid_0_52 pass
7595 14:45:52.660106 alsa_mixer-test_event_missing_0_52 pass
7596 14:45:52.663689 alsa_mixer-test_event_spurious_0_52 pass
7597 14:45:52.666764 alsa_mixer-test_get_value_0_51 pass
7598 14:45:52.670131 alsa_mixer-test_name_0_51 fail
7599 14:45:52.673755 alsa_mixer-test_write_default_0_51 pass
7600 14:45:52.677282 alsa_mixer-test_write_valid_0_51 pass
7601 14:45:52.679928 alsa_mixer-test_write_invalid_0_51 pass
7602 14:45:52.683571 alsa_mixer-test_event_missing_0_51 pass
7603 14:45:52.686850 alsa_mixer-test_event_spurious_0_51 pass
7604 14:45:52.690216 alsa_mixer-test_get_value_0_50 pass
7605 14:45:52.693354 alsa_mixer-test_name_0_50 fail
7606 14:45:52.696742 alsa_mixer-test_write_default_0_50 pass
7607 14:45:52.700096 alsa_mixer-test_write_valid_0_50 pass
7608 14:45:52.703625 alsa_mixer-test_write_invalid_0_50 pass
7609 14:45:52.709849 alsa_mixer-test_event_missing_0_50 pass
7610 14:45:52.713153 alsa_mixer-test_event_spurious_0_50 pass
7611 14:45:52.716657 alsa_mixer-test_get_value_0_49 pass
7612 14:45:52.720042 alsa_mixer-test_name_0_49 fail
7613 14:45:52.723032 alsa_mixer-test_write_default_0_49 pass
7614 14:45:52.726378 alsa_mixer-test_write_valid_0_49 pass
7615 14:45:52.729507 alsa_mixer-test_write_invalid_0_49 pass
7616 14:45:52.732932 alsa_mixer-test_event_missing_0_49 pass
7617 14:45:52.736609 alsa_mixer-test_event_spurious_0_49 pass
7618 14:45:52.739808 alsa_mixer-test_get_value_0_48 pass
7619 14:45:52.742806 alsa_mixer-test_name_0_48 fail
7620 14:45:52.746262 alsa_mixer-test_write_default_0_48 pass
7621 14:45:52.749490 alsa_mixer-test_write_valid_0_48 pass
7622 14:45:52.752781 alsa_mixer-test_write_invalid_0_48 pass
7623 14:45:52.756050 alsa_mixer-test_event_missing_0_48 pass
7624 14:45:52.762865 alsa_mixer-test_event_spurious_0_48 pass
7625 14:45:52.766277 alsa_mixer-test_get_value_0_47 pass
7626 14:45:52.766358 alsa_mixer-test_name_0_47 fail
7627 14:45:52.772891 alsa_mixer-test_write_default_0_47 pass
7628 14:45:52.776363 alsa_mixer-test_write_valid_0_47 pass
7629 14:45:52.779129 alsa_mixer-test_write_invalid_0_47 pass
7630 14:45:52.782793 alsa_mixer-test_event_missing_0_47 pass
7631 14:45:52.786200 alsa_mixer-test_event_spurious_0_47 pass
7632 14:45:52.789220 alsa_mixer-test_get_value_0_46 pass
7633 14:45:52.792838 alsa_mixer-test_name_0_46 fail
7634 14:45:52.795871 alsa_mixer-test_write_default_0_46 pass
7635 14:45:52.799182 alsa_mixer-test_write_valid_0_46 pass
7636 14:45:52.802684 alsa_mixer-test_write_invalid_0_46 pass
7637 14:45:52.805667 alsa_mixer-test_event_missing_0_46 pass
7638 14:45:52.809190 alsa_mixer-test_event_spurious_0_46 pass
7639 14:45:52.812784 alsa_mixer-test_get_value_0_45 pass
7640 14:45:52.815794 alsa_mixer-test_name_0_45 fail
7641 14:45:52.819259 alsa_mixer-test_write_default_0_45 pass
7642 14:45:52.822108 alsa_mixer-test_write_valid_0_45 pass
7643 14:45:52.825662 alsa_mixer-test_write_invalid_0_45 pass
7644 14:45:52.828754 alsa_mixer-test_event_missing_0_45 pass
7645 14:45:52.835434 alsa_mixer-test_event_spurious_0_45 pass
7646 14:45:52.839011 alsa_mixer-test_get_value_0_44 pass
7647 14:45:52.839092 alsa_mixer-test_name_0_44 fail
7648 14:45:52.842206 alsa_mixer-test_write_default_0_44 pass
7649 14:45:52.848959 alsa_mixer-test_write_valid_0_44 pass
7650 14:45:52.851844 alsa_mixer-test_write_invalid_0_44 pass
7651 14:45:52.855342 alsa_mixer-test_event_missing_0_44 pass
7652 14:45:52.858793 alsa_mixer-test_event_spurious_0_44 pass
7653 14:45:52.861863 alsa_mixer-test_get_value_0_43 pass
7654 14:45:52.865642 alsa_mixer-test_name_0_43 fail
7655 14:45:52.868651 alsa_mixer-test_write_default_0_43 pass
7656 14:45:52.871890 alsa_mixer-test_write_valid_0_43 pass
7657 14:45:52.875249 alsa_mixer-test_write_invalid_0_43 pass
7658 14:45:52.878287 alsa_mixer-test_event_missing_0_43 pass
7659 14:45:52.881526 alsa_mixer-test_event_spurious_0_43 pass
7660 14:45:52.885634 alsa_mixer-test_get_value_0_42 pass
7661 14:45:52.888432 alsa_mixer-test_name_0_42 fail
7662 14:45:52.891860 alsa_mixer-test_write_default_0_42 pass
7663 14:45:52.895161 alsa_mixer-test_write_valid_0_42 pass
7664 14:45:52.898266 alsa_mixer-test_write_invalid_0_42 pass
7665 14:45:52.901705 alsa_mixer-test_event_missing_0_42 pass
7666 14:45:52.904952 alsa_mixer-test_event_spurious_0_42 pass
7667 14:45:52.908463 alsa_mixer-test_get_value_0_41 pass
7668 14:45:52.911745 alsa_mixer-test_name_0_41 fail
7669 14:45:52.915351 alsa_mixer-test_write_default_0_41 pass
7670 14:45:52.918242 alsa_mixer-test_write_valid_0_41 pass
7671 14:45:52.921666 alsa_mixer-test_write_invalid_0_41 pass
7672 14:45:52.924948 alsa_mixer-test_event_missing_0_41 pass
7673 14:45:52.928128 alsa_mixer-test_event_spurious_0_41 pass
7674 14:45:52.931587 alsa_mixer-test_get_value_0_40 pass
7675 14:45:52.935137 alsa_mixer-test_name_0_40 fail
7676 14:45:52.938641 alsa_mixer-test_write_default_0_40 pass
7677 14:45:52.941573 alsa_mixer-test_write_valid_0_40 pass
7678 14:45:52.944728 alsa_mixer-test_write_invalid_0_40 pass
7679 14:45:52.948461 alsa_mixer-test_event_missing_0_40 pass
7680 14:45:52.951720 alsa_mixer-test_event_spurious_0_40 pass
7681 14:45:52.955247 alsa_mixer-test_get_value_0_39 pass
7682 14:45:52.958224 alsa_mixer-test_name_0_39 fail
7683 14:45:52.961423 alsa_mixer-test_write_default_0_39 pass
7684 14:45:52.965027 alsa_mixer-test_write_valid_0_39 pass
7685 14:45:52.968063 alsa_mixer-test_write_invalid_0_39 pass
7686 14:45:52.971451 alsa_mixer-test_event_missing_0_39 pass
7687 14:45:52.975099 alsa_mixer-test_event_spurious_0_39 pass
7688 14:45:52.978076 alsa_mixer-test_get_value_0_38 pass
7689 14:45:52.981249 alsa_mixer-test_name_0_38 fail
7690 14:45:52.984651 alsa_mixer-test_write_default_0_38 pass
7691 14:45:52.988234 alsa_mixer-test_write_valid_0_38 pass
7692 14:45:52.991352 alsa_mixer-test_write_invalid_0_38 pass
7693 14:45:52.998107 alsa_mixer-test_event_missing_0_38 pass
7694 14:45:53.001822 alsa_mixer-test_event_spurious_0_38 pass
7695 14:45:53.005061 alsa_mixer-test_get_value_0_37 pass
7696 14:45:53.005591 alsa_mixer-test_name_0_37 fail
7697 14:45:53.008068 alsa_mixer-test_write_default_0_37 pass
7698 14:45:53.014930 alsa_mixer-test_write_valid_0_37 pass
7699 14:45:53.018255 alsa_mixer-test_write_invalid_0_37 pass
7700 14:45:53.021713 alsa_mixer-test_event_missing_0_37 pass
7701 14:45:53.024847 alsa_mixer-test_event_spurious_0_37 pass
7702 14:45:53.028407 alsa_mixer-test_get_value_0_36 pass
7703 14:45:53.031504 alsa_mixer-test_name_0_36 fail
7704 14:45:53.035181 alsa_mixer-test_write_default_0_36 pass
7705 14:45:53.038197 alsa_mixer-test_write_valid_0_36 pass
7706 14:45:53.041400 alsa_mixer-test_write_invalid_0_36 pass
7707 14:45:53.045201 alsa_mixer-test_event_missing_0_36 pass
7708 14:45:53.047889 alsa_mixer-test_event_spurious_0_36 pass
7709 14:45:53.051570 alsa_mixer-test_get_value_0_35 pass
7710 14:45:53.054804 alsa_mixer-test_name_0_35 fail
7711 14:45:53.058281 alsa_mixer-test_write_default_0_35 pass
7712 14:45:53.061049 alsa_mixer-test_write_valid_0_35 pass
7713 14:45:53.064301 alsa_mixer-test_write_invalid_0_35 pass
7714 14:45:53.068283 alsa_mixer-test_event_missing_0_35 pass
7715 14:45:53.071578 alsa_mixer-test_event_spurious_0_35 pass
7716 14:45:53.074226 alsa_mixer-test_get_value_0_34 pass
7717 14:45:53.077761 alsa_mixer-test_name_0_34 fail
7718 14:45:53.080749 alsa_mixer-test_write_default_0_34 pass
7719 14:45:53.084663 alsa_mixer-test_write_valid_0_34 pass
7720 14:45:53.087401 alsa_mixer-test_write_invalid_0_34 pass
7721 14:45:53.091092 alsa_mixer-test_event_missing_0_34 pass
7722 14:45:53.097678 alsa_mixer-test_event_spurious_0_34 pass
7723 14:45:53.100939 alsa_mixer-test_get_value_0_33 pass
7724 14:45:53.101020 alsa_mixer-test_name_0_33 fail
7725 14:45:53.103876 alsa_mixer-test_write_default_0_33 pass
7726 14:45:53.107519 alsa_mixer-test_write_valid_0_33 pass
7727 14:45:53.114405 alsa_mixer-test_write_invalid_0_33 pass
7728 14:45:53.117389 alsa_mixer-test_event_missing_0_33 pass
7729 14:45:53.120806 alsa_mixer-test_event_spurious_0_33 pass
7730 14:45:53.123928 alsa_mixer-test_get_value_0_32 pass
7731 14:45:53.127526 alsa_mixer-test_name_0_32 fail
7732 14:45:53.130579 alsa_mixer-test_write_default_0_32 pass
7733 14:45:53.134825 alsa_mixer-test_write_valid_0_32 pass
7734 14:45:53.137194 alsa_mixer-test_write_invalid_0_32 pass
7735 14:45:53.140808 alsa_mixer-test_event_missing_0_32 pass
7736 14:45:53.143987 alsa_mixer-test_event_spurious_0_32 pass
7737 14:45:53.147009 alsa_mixer-test_get_value_0_31 pass
7738 14:45:53.150414 alsa_mixer-test_name_0_31 fail
7739 14:45:53.154007 alsa_mixer-test_write_default_0_31 pass
7740 14:45:53.157295 alsa_mixer-test_write_valid_0_31 pass
7741 14:45:53.160672 alsa_mixer-test_write_invalid_0_31 pass
7742 14:45:53.163680 alsa_mixer-test_event_missing_0_31 pass
7743 14:45:53.167176 alsa_mixer-test_event_spurious_0_31 pass
7744 14:45:53.170314 alsa_mixer-test_get_value_0_30 pass
7745 14:45:53.173821 alsa_mixer-test_name_0_30 fail
7746 14:45:53.177365 alsa_mixer-test_write_default_0_30 pass
7747 14:45:53.180418 alsa_mixer-test_write_valid_0_30 pass
7748 14:45:53.183502 alsa_mixer-test_write_invalid_0_30 pass
7749 14:45:53.186969 alsa_mixer-test_event_missing_0_30 pass
7750 14:45:53.190776 alsa_mixer-test_event_spurious_0_30 pass
7751 14:45:53.193725 alsa_mixer-test_get_value_0_29 pass
7752 14:45:53.197013 alsa_mixer-test_name_0_29 pass
7753 14:45:53.200223 alsa_mixer-test_write_default_0_29 pass
7754 14:45:53.203685 alsa_mixer-test_write_valid_0_29 pass
7755 14:45:53.206923 alsa_mixer-test_write_invalid_0_29 pass
7756 14:45:53.210091 alsa_mixer-test_event_missing_0_29 pass
7757 14:45:53.213563 alsa_mixer-test_event_spurious_0_29 pass
7758 14:45:53.216965 alsa_mixer-test_get_value_0_28 pass
7759 14:45:53.220441 alsa_mixer-test_name_0_28 pass
7760 14:45:53.223847 alsa_mixer-test_write_default_0_28 pass
7761 14:45:53.226912 alsa_mixer-test_write_valid_0_28 pass
7762 14:45:53.230331 alsa_mixer-test_write_invalid_0_28 pass
7763 14:45:53.236855 alsa_mixer-test_event_missing_0_28 pass
7764 14:45:53.240373 alsa_mixer-test_event_spurious_0_28 pass
7765 14:45:53.243383 alsa_mixer-test_get_value_0_27 pass
7766 14:45:53.246650 alsa_mixer-test_name_0_27 pass
7767 14:45:53.249999 alsa_mixer-test_write_default_0_27 pass
7768 14:45:53.253200 alsa_mixer-test_write_valid_0_27 pass
7769 14:45:53.257164 alsa_mixer-test_write_invalid_0_27 pass
7770 14:45:53.260267 alsa_mixer-test_event_missing_0_27 pass
7771 14:45:53.263269 alsa_mixer-test_event_spurious_0_27 pass
7772 14:45:53.266728 alsa_mixer-test_get_value_0_26 pass
7773 14:45:53.270270 alsa_mixer-test_name_0_26 pass
7774 14:45:53.273372 alsa_mixer-test_write_default_0_26 pass
7775 14:45:53.276681 alsa_mixer-test_write_valid_0_26 pass
7776 14:45:53.279967 alsa_mixer-test_write_invalid_0_26 pass
7777 14:45:53.283839 alsa_mixer-test_event_missing_0_26 pass
7778 14:45:53.286357 alsa_mixer-test_event_spurious_0_26 pass
7779 14:45:53.289917 alsa_mixer-test_get_value_0_25 pass
7780 14:45:53.293027 alsa_mixer-test_name_0_25 pass
7781 14:45:53.296574 alsa_mixer-test_write_default_0_25 pass
7782 14:45:53.300425 alsa_mixer-test_write_valid_0_25 pass
7783 14:45:53.306202 alsa_mixer-test_write_invalid_0_25 pass
7784 14:45:53.309608 alsa_mixer-test_event_missing_0_25 pass
7785 14:45:53.313133 alsa_mixer-test_event_spurious_0_25 pass
7786 14:45:53.316369 alsa_mixer-test_get_value_0_24 pass
7787 14:45:53.319610 alsa_mixer-test_name_0_24 pass
7788 14:45:53.323169 alsa_mixer-test_write_default_0_24 pass
7789 14:45:53.326319 alsa_mixer-test_write_valid_0_24 pass
7790 14:45:53.329609 alsa_mixer-test_write_invalid_0_24 pass
7791 14:45:53.332848 alsa_mixer-test_event_missing_0_24 pass
7792 14:45:53.336520 alsa_mixer-test_event_spurious_0_24 pass
7793 14:45:53.339594 alsa_mixer-test_get_value_0_23 pass
7794 14:45:53.342722 alsa_mixer-test_name_0_23 pass
7795 14:45:53.346008 alsa_mixer-test_write_default_0_23 pass
7796 14:45:53.349201 alsa_mixer-test_write_valid_0_23 pass
7797 14:45:53.353098 alsa_mixer-test_write_invalid_0_23 pass
7798 14:45:53.359520 alsa_mixer-test_event_missing_0_23 pass
7799 14:45:53.362691 alsa_mixer-test_event_spurious_0_23 pass
7800 14:45:53.366139 alsa_mixer-test_get_value_0_22 pass
7801 14:45:53.369438 alsa_mixer-test_name_0_22 pass
7802 14:45:53.372588 alsa_mixer-test_write_default_0_22 pass
7803 14:45:53.376030 alsa_mixer-test_write_valid_0_22 pass
7804 14:45:53.379247 alsa_mixer-test_write_invalid_0_22 pass
7805 14:45:53.382397 alsa_mixer-test_event_missing_0_22 pass
7806 14:45:53.386136 alsa_mixer-test_event_spurious_0_22 pass
7807 14:45:53.389537 alsa_mixer-test_get_value_0_21 pass
7808 14:45:53.392531 alsa_mixer-test_name_0_21 fail
7809 14:45:53.395689 alsa_mixer-test_write_default_0_21 pass
7810 14:45:53.399186 alsa_mixer-test_write_valid_0_21 pass
7811 14:45:53.402484 alsa_mixer-test_write_invalid_0_21 pass
7812 14:45:53.405842 alsa_mixer-test_event_missing_0_21 pass
7813 14:45:53.409056 alsa_mixer-test_event_spurious_0_21 pass
7814 14:45:53.412493 alsa_mixer-test_get_value_0_20 pass
7815 14:45:53.415961 alsa_mixer-test_name_0_20 fail
7816 14:45:53.419038 alsa_mixer-test_write_default_0_20 pass
7817 14:45:53.422341 alsa_mixer-test_write_valid_0_20 pass
7818 14:45:53.425840 alsa_mixer-test_write_invalid_0_20 pass
7819 14:45:53.428963 alsa_mixer-test_event_missing_0_20 pass
7820 14:45:53.436151 alsa_mixer-test_event_spurious_0_20 pass
7821 14:45:53.438999 alsa_mixer-test_get_value_0_19 pass
7822 14:45:53.439079 alsa_mixer-test_name_0_19 fail
7823 14:45:53.442576 alsa_mixer-test_write_default_0_19 pass
7824 14:45:53.445945 alsa_mixer-test_write_valid_0_19 pass
7825 14:45:53.452581 alsa_mixer-test_write_invalid_0_19 pass
7826 14:45:53.455396 alsa_mixer-test_event_missing_0_19 pass
7827 14:45:53.459058 alsa_mixer-test_event_spurious_0_19 pass
7828 14:45:53.462050 alsa_mixer-test_get_value_0_18 pass
7829 14:45:53.465753 alsa_mixer-test_name_0_18 fail
7830 14:45:53.468649 alsa_mixer-test_write_default_0_18 pass
7831 14:45:53.471957 alsa_mixer-test_write_valid_0_18 pass
7832 14:45:53.475750 alsa_mixer-test_write_invalid_0_18 pass
7833 14:45:53.478649 alsa_mixer-test_event_missing_0_18 pass
7834 14:45:53.481787 alsa_mixer-test_event_spurious_0_18 pass
7835 14:45:53.485487 alsa_mixer-test_get_value_0_17 pass
7836 14:45:53.488926 alsa_mixer-test_name_0_17 fail
7837 14:45:53.491982 alsa_mixer-test_write_default_0_17 pass
7838 14:45:53.495377 alsa_mixer-test_write_valid_0_17 pass
7839 14:45:53.498943 alsa_mixer-test_write_invalid_0_17 pass
7840 14:45:53.502035 alsa_mixer-test_event_missing_0_17 pass
7841 14:45:53.505609 alsa_mixer-test_event_spurious_0_17 pass
7842 14:45:53.508898 alsa_mixer-test_get_value_0_16 pass
7843 14:45:53.512404 alsa_mixer-test_name_0_16 fail
7844 14:45:53.515298 alsa_mixer-test_write_default_0_16 pass
7845 14:45:53.519116 alsa_mixer-test_write_valid_0_16 pass
7846 14:45:53.521915 alsa_mixer-test_write_invalid_0_16 pass
7847 14:45:53.525442 alsa_mixer-test_event_missing_0_16 pass
7848 14:45:53.528580 alsa_mixer-test_event_spurious_0_16 pass
7849 14:45:53.531875 alsa_mixer-test_get_value_0_15 pass
7850 14:45:53.535264 alsa_mixer-test_name_0_15 fail
7851 14:45:53.538344 alsa_mixer-test_write_default_0_15 pass
7852 14:45:53.542246 alsa_mixer-test_write_valid_0_15 pass
7853 14:45:53.545425 alsa_mixer-test_write_invalid_0_15 pass
7854 14:45:53.548719 alsa_mixer-test_event_missing_0_15 pass
7855 14:45:53.555146 alsa_mixer-test_event_spurious_0_15 pass
7856 14:45:53.555228 alsa_mixer-test_get_value_0_14 pass
7857 14:45:53.558393 alsa_mixer-test_name_0_14 fail
7858 14:45:53.561638 alsa_mixer-test_write_default_0_14 pass
7859 14:45:53.564963 alsa_mixer-test_write_valid_0_14 pass
7860 14:45:53.568670 alsa_mixer-test_write_invalid_0_14 pass
7861 14:45:53.575139 alsa_mixer-test_event_missing_0_14 pass
7862 14:45:53.578353 alsa_mixer-test_event_spurious_0_14 pass
7863 14:45:53.581577 alsa_mixer-test_get_value_0_13 pass
7864 14:45:53.581659 alsa_mixer-test_name_0_13 fail
7865 14:45:53.588138 alsa_mixer-test_write_default_0_13 pass
7866 14:45:53.591409 alsa_mixer-test_write_valid_0_13 pass
7867 14:45:53.595031 alsa_mixer-test_write_invalid_0_13 pass
7868 14:45:53.597942 alsa_mixer-test_event_missing_0_13 pass
7869 14:45:53.601486 alsa_mixer-test_event_spurious_0_13 pass
7870 14:45:53.605000 alsa_mixer-test_get_value_0_12 pass
7871 14:45:53.608380 alsa_mixer-test_name_0_12 fail
7872 14:45:53.611212 alsa_mixer-test_write_default_0_12 pass
7873 14:45:53.614648 alsa_mixer-test_write_valid_0_12 pass
7874 14:45:53.618175 alsa_mixer-test_write_invalid_0_12 pass
7875 14:45:53.621600 alsa_mixer-test_event_missing_0_12 pass
7876 14:45:53.624422 alsa_mixer-test_event_spurious_0_12 pass
7877 14:45:53.627807 alsa_mixer-test_get_value_0_11 pass
7878 14:45:53.631075 alsa_mixer-test_name_0_11 fail
7879 14:45:53.634343 alsa_mixer-test_write_default_0_11 pass
7880 14:45:53.637930 alsa_mixer-test_write_valid_0_11 pass
7881 14:45:53.641192 alsa_mixer-test_write_invalid_0_11 pass
7882 14:45:53.644651 alsa_mixer-test_event_missing_0_11 pass
7883 14:45:53.648017 alsa_mixer-test_event_spurious_0_11 pass
7884 14:45:53.651266 alsa_mixer-test_get_value_0_10 pass
7885 14:45:53.654332 alsa_mixer-test_name_0_10 fail
7886 14:45:53.657873 alsa_mixer-test_write_default_0_10 pass
7887 14:45:53.661154 alsa_mixer-test_write_valid_0_10 pass
7888 14:45:53.664675 alsa_mixer-test_write_invalid_0_10 pass
7889 14:45:53.668018 alsa_mixer-test_event_missing_0_10 pass
7890 14:45:53.671337 alsa_mixer-test_event_spurious_0_10 pass
7891 14:45:53.674435 alsa_mixer-test_get_value_0_9 pass
7892 14:45:53.677653 alsa_mixer-test_name_0_9 fail
7893 14:45:53.680974 alsa_mixer-test_write_default_0_9 pass
7894 14:45:53.684065 alsa_mixer-test_write_valid_0_9 pass
7895 14:45:53.687642 alsa_mixer-test_write_invalid_0_9 pass
7896 14:45:53.690919 alsa_mixer-test_event_missing_0_9 pass
7897 14:45:53.694303 alsa_mixer-test_event_spurious_0_9 pass
7898 14:45:53.697130 alsa_mixer-test_get_value_0_8 pass
7899 14:45:53.701169 alsa_mixer-test_name_0_8 fail
7900 14:45:53.704074 alsa_mixer-test_write_default_0_8 pass
7901 14:45:53.707223 alsa_mixer-test_write_valid_0_8 pass
7902 14:45:53.710414 alsa_mixer-test_write_invalid_0_8 pass
7903 14:45:53.713769 alsa_mixer-test_event_missing_0_8 pass
7904 14:45:53.717367 alsa_mixer-test_event_spurious_0_8 pass
7905 14:45:53.720524 alsa_mixer-test_get_value_0_7 pass
7906 14:45:53.724093 alsa_mixer-test_name_0_7 fail
7907 14:45:53.727388 alsa_mixer-test_write_default_0_7 pass
7908 14:45:53.730769 alsa_mixer-test_write_valid_0_7 pass
7909 14:45:53.733830 alsa_mixer-test_write_invalid_0_7 pass
7910 14:45:53.737377 alsa_mixer-test_event_missing_0_7 pass
7911 14:45:53.740680 alsa_mixer-test_event_spurious_0_7 pass
7912 14:45:53.743785 alsa_mixer-test_get_value_0_6 pass
7913 14:45:53.747184 alsa_mixer-test_name_0_6 fail
7914 14:45:53.750458 alsa_mixer-test_write_default_0_6 pass
7915 14:45:53.754003 alsa_mixer-test_write_valid_0_6 pass
7916 14:45:53.757029 alsa_mixer-test_write_invalid_0_6 pass
7917 14:45:53.760539 alsa_mixer-test_event_missing_0_6 pass
7918 14:45:53.763883 alsa_mixer-test_event_spurious_0_6 pass
7919 14:45:53.766982 alsa_mixer-test_get_value_0_5 pass
7920 14:45:53.770254 alsa_mixer-test_name_0_5 pass
7921 14:45:53.773719 alsa_mixer-test_write_default_0_5 pass
7922 14:45:53.777438 alsa_mixer-test_write_valid_0_5 pass
7923 14:45:53.780639 alsa_mixer-test_write_invalid_0_5 pass
7924 14:45:53.783873 alsa_mixer-test_event_missing_0_5 fail
7925 14:45:53.787018 alsa_mixer-test_event_spurious_0_5 pass
7926 14:45:53.790518 alsa_mixer-test_get_value_0_4 pass
7927 14:45:53.794091 alsa_mixer-test_name_0_4 pass
7928 14:45:53.797130 alsa_mixer-test_write_default_0_4 pass
7929 14:45:53.800164 alsa_mixer-test_write_valid_0_4 pass
7930 14:45:53.803722 alsa_mixer-test_write_invalid_0_4 pass
7931 14:45:53.806831 alsa_mixer-test_event_missing_0_4 fail
7932 14:45:53.810697 alsa_mixer-test_event_spurious_0_4 pass
7933 14:45:53.813456 alsa_mixer-test_get_value_0_3 pass
7934 14:45:53.816799 alsa_mixer-test_name_0_3 pass
7935 14:45:53.820148 alsa_mixer-test_write_default_0_3 pass
7936 14:45:53.823667 alsa_mixer-test_write_valid_0_3 pass
7937 14:45:53.826673 alsa_mixer-test_write_invalid_0_3 pass
7938 14:45:53.830192 alsa_mixer-test_event_missing_0_3 fail
7939 14:45:53.833357 alsa_mixer-test_event_spurious_0_3 pass
7940 14:45:53.836752 alsa_mixer-test_get_value_0_2 pass
7941 14:45:53.840174 alsa_mixer-test_name_0_2 pass
7942 14:45:53.843102 alsa_mixer-test_write_default_0_2 pass
7943 14:45:53.846945 alsa_mixer-test_write_valid_0_2 pass
7944 14:45:53.850432 alsa_mixer-test_write_invalid_0_2 pass
7945 14:45:53.853244 alsa_mixer-test_event_missing_0_2 fail
7946 14:45:53.856455 alsa_mixer-test_event_spurious_0_2 pass
7947 14:45:53.860025 alsa_mixer-test_get_value_0_1 pass
7948 14:45:53.863322 alsa_mixer-test_name_0_1 pass
7949 14:45:53.866817 alsa_mixer-test_write_default_0_1 pass
7950 14:45:53.869647 alsa_mixer-test_write_valid_0_1 pass
7951 14:45:53.873230 alsa_mixer-test_write_invalid_0_1 pass
7952 14:45:53.876689 alsa_mixer-test_event_missing_0_1 fail
7953 14:45:53.882931 alsa_mixer-test_event_spurious_0_1 pass
7954 14:45:53.883010 alsa_mixer-test_get_value_0_0 pass
7955 14:45:53.886606 alsa_mixer-test_name_0_0 pass
7956 14:45:53.889550 alsa_mixer-test_write_default_0_0 pass
7957 14:45:53.892788 alsa_mixer-test_write_valid_0_0 pass
7958 14:45:53.896400 alsa_mixer-test_write_invalid_0_0 pass
7959 14:45:53.899544 alsa_mixer-test_event_missing_0_0 fail
7960 14:45:53.906264 alsa_mixer-test_event_spurious_0_0 pass
7961 14:45:53.906343 alsa_mixer-test pass
7962 14:45:53.909145 + ../../utils/send-to-lava.sh ./output/result.txt
7963 14:45:53.916158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
7964 14:45:53.916493 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
7966 14:45:53.922341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_93 RESULT=pass>
7967 14:45:53.922588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_93 RESULT=pass
7969 14:45:53.929210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_93 RESULT=pass>
7970 14:45:53.929541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_93 RESULT=pass
7972 14:45:53.935658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_93 RESULT=pass>
7973 14:45:53.935930 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_93 RESULT=pass
7975 14:45:53.945855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_93 RESULT=pass>
7976 14:45:53.946111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_93 RESULT=pass
7978 14:45:53.952659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_93 RESULT=pass>
7979 14:45:53.952909 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_93 RESULT=pass
7981 14:45:53.982084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_93 RESULT=pass>
7982 14:45:53.982340 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_93 RESULT=pass
7984 14:45:54.020397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_93 RESULT=pass>
7985 14:45:54.020686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_93 RESULT=pass
7987 14:45:54.058072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_92 RESULT=pass>
7988 14:45:54.058337 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_92 RESULT=pass
7990 14:45:54.091634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_92 RESULT=pass>
7991 14:45:54.091895 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_92 RESULT=pass
7993 14:45:54.132455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_92 RESULT=pass>
7994 14:45:54.132748 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_92 RESULT=pass
7996 14:45:54.169274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_92 RESULT=pass>
7997 14:45:54.169534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_92 RESULT=pass
7999 14:45:54.206710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_92 RESULT=pass>
8000 14:45:54.206988 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_92 RESULT=pass
8002 14:45:54.242855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_92 RESULT=pass>
8003 14:45:54.243120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_92 RESULT=pass
8005 14:45:54.280014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_92 RESULT=pass>
8006 14:45:54.280284 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_92 RESULT=pass
8008 14:45:54.316512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_91 RESULT=pass>
8009 14:45:54.316800 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_91 RESULT=pass
8011 14:45:54.354425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_91 RESULT=pass>
8012 14:45:54.354704 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_91 RESULT=pass
8014 14:45:54.396567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_91 RESULT=pass>
8015 14:45:54.396852 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_91 RESULT=pass
8017 14:45:54.433911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_91 RESULT=pass>
8018 14:45:54.434193 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_91 RESULT=pass
8020 14:45:54.472583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_91 RESULT=pass>
8021 14:45:54.472851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_91 RESULT=pass
8023 14:45:54.511650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_91 RESULT=pass>
8024 14:45:54.511919 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_91 RESULT=pass
8026 14:45:54.552298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_91 RESULT=pass>
8027 14:45:54.552574 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_91 RESULT=pass
8029 14:45:54.588070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_90 RESULT=pass>
8030 14:45:54.588326 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_90 RESULT=pass
8032 14:45:54.623065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_90 RESULT=pass>
8033 14:45:54.623352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_90 RESULT=pass
8035 14:45:54.662864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_90 RESULT=pass>
8036 14:45:54.663136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_90 RESULT=pass
8038 14:45:54.701234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_90 RESULT=pass>
8039 14:45:54.701555 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_90 RESULT=pass
8041 14:45:54.740373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_90 RESULT=pass>
8042 14:45:54.740676 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_90 RESULT=pass
8044 14:45:54.778087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_90 RESULT=pass>
8045 14:45:54.778369 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_90 RESULT=pass
8047 14:45:54.812378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_90 RESULT=pass>
8048 14:45:54.812647 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_90 RESULT=pass
8050 14:45:54.844879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_89 RESULT=pass>
8051 14:45:54.845148 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_89 RESULT=pass
8053 14:45:54.881772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_89 RESULT=pass>
8054 14:45:54.882041 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_89 RESULT=pass
8056 14:45:54.921173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_89 RESULT=pass>
8057 14:45:54.921503 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_89 RESULT=pass
8059 14:45:54.956951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_89 RESULT=pass>
8060 14:45:54.957211 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_89 RESULT=pass
8062 14:45:54.993283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_89 RESULT=pass>
8063 14:45:54.993561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_89 RESULT=pass
8065 14:45:55.034938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_89 RESULT=pass>
8066 14:45:55.035207 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_89 RESULT=pass
8068 14:45:55.073551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_89 RESULT=pass>
8069 14:45:55.073839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_89 RESULT=pass
8071 14:45:55.111702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_88 RESULT=pass>
8072 14:45:55.111974 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_88 RESULT=pass
8074 14:45:55.148060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_88 RESULT=pass>
8075 14:45:55.148321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_88 RESULT=pass
8077 14:45:55.189023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_88 RESULT=pass>
8078 14:45:55.189297 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_88 RESULT=pass
8080 14:45:55.227039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_88 RESULT=fail>
8081 14:45:55.227303 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_88 RESULT=fail
8083 14:45:55.263130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_88 RESULT=pass>
8084 14:45:55.263391 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_88 RESULT=pass
8086 14:45:55.298652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_88 RESULT=pass>
8087 14:45:55.298917 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_88 RESULT=pass
8089 14:45:55.332650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_88 RESULT=fail>
8090 14:45:55.332920 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_88 RESULT=fail
8092 14:45:55.369899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_87 RESULT=pass>
8093 14:45:55.370161 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_87 RESULT=pass
8095 14:45:55.405965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_87 RESULT=pass>
8096 14:45:55.406247 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_87 RESULT=pass
8098 14:45:55.449674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_87 RESULT=pass>
8099 14:45:55.449940 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_87 RESULT=pass
8101 14:45:55.486128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_87 RESULT=pass>
8102 14:45:55.486417 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_87 RESULT=pass
8104 14:45:55.521103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_87 RESULT=pass>
8105 14:45:55.521405 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_87 RESULT=pass
8107 14:45:55.560254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_87 RESULT=pass>
8108 14:45:55.560529 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_87 RESULT=pass
8110 14:45:55.594430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_87 RESULT=pass>
8111 14:45:55.594732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_87 RESULT=pass
8113 14:45:55.628337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_86 RESULT=pass>
8114 14:45:55.628606 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_86 RESULT=pass
8116 14:45:55.662997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_86 RESULT=pass>
8117 14:45:55.663272 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_86 RESULT=pass
8119 14:45:55.707728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_86 RESULT=pass>
8120 14:45:55.708003 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_86 RESULT=pass
8122 14:45:55.744853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_86 RESULT=fail>
8123 14:45:55.745121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_86 RESULT=fail
8125 14:45:55.780400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_86 RESULT=pass>
8126 14:45:55.780667 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_86 RESULT=pass
8128 14:45:55.816453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_86 RESULT=pass>
8129 14:45:55.816714 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_86 RESULT=pass
8131 14:45:55.852218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_86 RESULT=pass>
8132 14:45:55.852486 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_86 RESULT=pass
8134 14:45:55.891172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_85 RESULT=pass>
8135 14:45:55.891433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_85 RESULT=pass
8137 14:45:55.926127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_85 RESULT=pass>
8138 14:45:55.926394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_85 RESULT=pass
8140 14:45:55.968218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_85 RESULT=pass>
8141 14:45:55.968494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_85 RESULT=pass
8143 14:45:56.005891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_85 RESULT=fail>
8144 14:45:56.006164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_85 RESULT=fail
8146 14:45:56.042071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_85 RESULT=pass>
8147 14:45:56.042336 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_85 RESULT=pass
8149 14:45:56.077091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_85 RESULT=pass>
8150 14:45:56.077349 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_85 RESULT=pass
8152 14:45:56.117189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_85 RESULT=pass>
8153 14:45:56.117522 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_85 RESULT=pass
8155 14:45:56.161783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_84 RESULT=pass>
8156 14:45:56.162043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_84 RESULT=pass
8158 14:45:56.194072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_84 RESULT=pass>
8159 14:45:56.194330 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_84 RESULT=pass
8161 14:45:56.236828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_84 RESULT=pass>
8162 14:45:56.237103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_84 RESULT=pass
8164 14:45:56.278043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_84 RESULT=pass>
8165 14:45:56.278299 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_84 RESULT=pass
8167 14:45:56.313554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_84 RESULT=pass>
8168 14:45:56.313838 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_84 RESULT=pass
8170 14:45:56.352825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_84 RESULT=pass>
8171 14:45:56.353088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_84 RESULT=pass
8173 14:45:56.395288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_84 RESULT=pass>
8174 14:45:56.395548 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_84 RESULT=pass
8176 14:45:56.430663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_83 RESULT=pass>
8177 14:45:56.430935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_83 RESULT=pass
8179 14:45:56.465495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_83 RESULT=pass>
8180 14:45:56.465752 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_83 RESULT=pass
8182 14:45:56.508255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_83 RESULT=pass>
8183 14:45:56.508524 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_83 RESULT=pass
8185 14:45:56.543792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_83 RESULT=pass>
8186 14:45:56.544054 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_83 RESULT=pass
8188 14:45:56.582236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_83 RESULT=pass>
8189 14:45:56.582494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_83 RESULT=pass
8191 14:45:56.618741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_83 RESULT=pass>
8192 14:45:56.619015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_83 RESULT=pass
8194 14:45:56.658226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_83 RESULT=pass>
8195 14:45:56.658506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_83 RESULT=pass
8197 14:45:56.694142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_82 RESULT=pass>
8198 14:45:56.694475 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_82 RESULT=pass
8200 14:45:56.729981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_82 RESULT=pass>
8201 14:45:56.730276 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_82 RESULT=pass
8203 14:45:56.773744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_82 RESULT=skip>
8204 14:45:56.774017 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_82 RESULT=skip
8206 14:45:56.810625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_82 RESULT=skip>
8207 14:45:56.810902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_82 RESULT=skip
8209 14:45:56.852916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_82 RESULT=skip>
8210 14:45:56.853179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_82 RESULT=skip
8212 14:45:56.895853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_82 RESULT=pass>
8213 14:45:56.896132 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_82 RESULT=pass
8215 14:45:56.934284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_82 RESULT=pass>
8216 14:45:56.934589 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_82 RESULT=pass
8218 14:45:56.975568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_81 RESULT=pass>
8219 14:45:56.975855 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_81 RESULT=pass
8221 14:45:57.009617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_81 RESULT=pass>
8222 14:45:57.009930 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_81 RESULT=pass
8224 14:45:57.053277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_81 RESULT=pass>
8225 14:45:57.053544 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_81 RESULT=pass
8227 14:45:57.093987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_81 RESULT=pass>
8228 14:45:57.094261 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_81 RESULT=pass
8230 14:45:57.133441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_81 RESULT=fail>
8231 14:45:57.133710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_81 RESULT=fail
8233 14:45:57.171712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_81 RESULT=fail>
8234 14:45:57.171992 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_81 RESULT=fail
8236 14:45:57.209589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_81 RESULT=pass>
8237 14:45:57.209861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_81 RESULT=pass
8239 14:45:57.243603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_80 RESULT=pass>
8240 14:45:57.243873 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_80 RESULT=pass
8242 14:45:57.278043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_80 RESULT=pass>
8243 14:45:57.278310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_80 RESULT=pass
8245 14:45:57.320370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_80 RESULT=pass>
8246 14:45:57.320658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_80 RESULT=pass
8248 14:45:57.359295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_80 RESULT=pass>
8249 14:45:57.359572 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_80 RESULT=pass
8251 14:45:57.395351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_80 RESULT=pass>
8252 14:45:57.395614 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_80 RESULT=pass
8254 14:45:57.433961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_80 RESULT=pass>
8255 14:45:57.434224 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_80 RESULT=pass
8257 14:45:57.470057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_80 RESULT=pass>
8258 14:45:57.470318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_80 RESULT=pass
8260 14:45:57.509195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_79 RESULT=fail>
8261 14:45:57.509503 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_79 RESULT=fail
8263 14:45:57.545025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_79 RESULT=pass>
8264 14:45:57.545313 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_79 RESULT=pass
8266 14:45:57.583928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_79 RESULT=fail>
8267 14:45:57.584186 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_79 RESULT=fail
8269 14:45:57.618467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_79 RESULT=fail>
8270 14:45:57.618741 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_79 RESULT=fail
8272 14:45:57.653490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_79 RESULT=fail>
8273 14:45:57.653752 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_79 RESULT=fail
8275 14:45:57.691013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_79 RESULT=pass>
8276 14:45:57.691267 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_79 RESULT=pass
8278 14:45:57.728482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_79 RESULT=pass>
8279 14:45:57.728767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_79 RESULT=pass
8281 14:45:57.767303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_78 RESULT=fail>
8282 14:45:57.767600 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_78 RESULT=fail
8284 14:45:57.802795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_78 RESULT=pass>
8285 14:45:57.803080 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_78 RESULT=pass
8287 14:45:57.844613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_78 RESULT=fail>
8288 14:45:57.844926 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_78 RESULT=fail
8290 14:45:57.881223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_78 RESULT=fail>
8291 14:45:57.881508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_78 RESULT=fail
8293 14:45:57.920934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_78 RESULT=fail>
8294 14:45:57.921214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_78 RESULT=fail
8296 14:45:57.961244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_78 RESULT=pass>
8297 14:45:57.961523 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_78 RESULT=pass
8299 14:45:58.000972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_78 RESULT=pass>
8300 14:45:58.001316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_78 RESULT=pass
8302 14:45:58.037047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_77 RESULT=fail>
8303 14:45:58.037333 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_77 RESULT=fail
8305 14:45:58.074185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_77 RESULT=pass>
8306 14:45:58.074451 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_77 RESULT=pass
8308 14:45:58.118994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_77 RESULT=fail>
8309 14:45:58.119288 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_77 RESULT=fail
8311 14:45:58.160412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_77 RESULT=fail>
8312 14:45:58.160678 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_77 RESULT=fail
8314 14:45:58.200276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_77 RESULT=fail>
8315 14:45:58.200574 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_77 RESULT=fail
8317 14:45:58.240739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_77 RESULT=pass>
8318 14:45:58.241035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_77 RESULT=pass
8320 14:45:58.275994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_77 RESULT=pass>
8321 14:45:58.276256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_77 RESULT=pass
8323 14:45:58.309887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_76 RESULT=pass>
8324 14:45:58.310174 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_76 RESULT=pass
8326 14:45:58.345490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_76 RESULT=fail>
8327 14:45:58.345748 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_76 RESULT=fail
8329 14:45:58.386773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_76 RESULT=pass>
8330 14:45:58.387041 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_76 RESULT=pass
8332 14:45:58.422144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_76 RESULT=pass>
8333 14:45:58.422417 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_76 RESULT=pass
8335 14:45:58.456814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_76 RESULT=pass>
8336 14:45:58.457074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_76 RESULT=pass
8338 14:45:58.492984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_76 RESULT=pass>
8339 14:45:58.493242 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_76 RESULT=pass
8341 14:45:58.527266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_76 RESULT=pass>
8342 14:45:58.527564 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_76 RESULT=pass
8344 14:45:58.565507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_75 RESULT=pass>
8345 14:45:58.565771 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_75 RESULT=pass
8347 14:45:58.600208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_75 RESULT=fail>
8348 14:45:58.600496 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_75 RESULT=fail
8350 14:45:58.638780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_75 RESULT=pass>
8351 14:45:58.639065 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_75 RESULT=pass
8353 14:45:58.672211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_75 RESULT=pass>
8354 14:45:58.672471 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_75 RESULT=pass
8356 14:45:58.706310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_75 RESULT=pass>
8357 14:45:58.706580 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_75 RESULT=pass
8359 14:45:58.741778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_75 RESULT=pass>
8360 14:45:58.742053 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_75 RESULT=pass
8362 14:45:58.776879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_75 RESULT=pass>
8363 14:45:58.777169 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_75 RESULT=pass
8365 14:45:58.810701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_74 RESULT=pass>
8366 14:45:58.810994 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_74 RESULT=pass
8368 14:45:58.841358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_74 RESULT=fail>
8369 14:45:58.841694 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_74 RESULT=fail
8371 14:45:58.878755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_74 RESULT=pass>
8372 14:45:58.879041 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_74 RESULT=pass
8374 14:45:58.912725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_74 RESULT=pass>
8375 14:45:58.913019 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_74 RESULT=pass
8377 14:45:58.948958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_74 RESULT=pass>
8378 14:45:58.949270 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_74 RESULT=pass
8380 14:45:58.984812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_74 RESULT=pass>
8381 14:45:58.985097 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_74 RESULT=pass
8383 14:45:59.024084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_74 RESULT=pass>
8384 14:45:59.024446 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_74 RESULT=pass
8386 14:45:59.067102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_73 RESULT=pass>
8387 14:45:59.067360 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_73 RESULT=pass
8389 14:45:59.102711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_73 RESULT=fail>
8390 14:45:59.103006 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_73 RESULT=fail
8392 14:45:59.143288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_73 RESULT=pass>
8393 14:45:59.143558 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_73 RESULT=pass
8395 14:45:59.180300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_73 RESULT=pass>
8396 14:45:59.180587 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_73 RESULT=pass
8398 14:45:59.217416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_73 RESULT=pass>
8399 14:45:59.217712 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_73 RESULT=pass
8401 14:45:59.253397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_73 RESULT=pass>
8402 14:45:59.253672 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_73 RESULT=pass
8404 14:45:59.289570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_73 RESULT=pass>
8405 14:45:59.289848 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_73 RESULT=pass
8407 14:45:59.326436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_72 RESULT=pass>
8408 14:45:59.326729 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_72 RESULT=pass
8410 14:45:59.360466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_72 RESULT=fail>
8411 14:45:59.360727 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_72 RESULT=fail
8413 14:45:59.404717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_72 RESULT=pass>
8414 14:45:59.405031 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_72 RESULT=pass
8416 14:45:59.443059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_72 RESULT=pass>
8417 14:45:59.443362 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_72 RESULT=pass
8419 14:45:59.479421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_72 RESULT=pass>
8420 14:45:59.479688 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_72 RESULT=pass
8422 14:45:59.513108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_72 RESULT=pass>
8423 14:45:59.513412 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_72 RESULT=pass
8425 14:45:59.549183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_72 RESULT=pass>
8426 14:45:59.549517 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_72 RESULT=pass
8428 14:45:59.584944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_71 RESULT=pass>
8429 14:45:59.585207 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_71 RESULT=pass
8431 14:45:59.617864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_71 RESULT=fail>
8432 14:45:59.618164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_71 RESULT=fail
8434 14:45:59.658979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_71 RESULT=pass>
8435 14:45:59.659246 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_71 RESULT=pass
8437 14:45:59.698721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_71 RESULT=pass>
8438 14:45:59.699014 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_71 RESULT=pass
8440 14:45:59.720021 <6>[ 37.990195] vaux18: disabling
8441 14:45:59.723287 <6>[ 37.993599] vio28: disabling
8442 14:45:59.736155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_71 RESULT=pass>
8443 14:45:59.736437 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_71 RESULT=pass
8445 14:45:59.774187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_71 RESULT=pass>
8446 14:45:59.774444 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_71 RESULT=pass
8448 14:45:59.810102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_71 RESULT=pass>
8449 14:45:59.810373 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_71 RESULT=pass
8451 14:45:59.846151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_70 RESULT=pass>
8452 14:45:59.846452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_70 RESULT=pass
8454 14:45:59.877138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_70 RESULT=fail>
8455 14:45:59.877421 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_70 RESULT=fail
8457 14:45:59.914338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_70 RESULT=pass>
8458 14:45:59.914616 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_70 RESULT=pass
8460 14:45:59.953160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_70 RESULT=pass>
8461 14:45:59.953425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_70 RESULT=pass
8463 14:45:59.988519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_70 RESULT=pass>
8464 14:45:59.988833 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_70 RESULT=pass
8466 14:46:00.027891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_70 RESULT=pass>
8467 14:46:00.028191 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_70 RESULT=pass
8469 14:46:00.066103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_70 RESULT=pass>
8470 14:46:00.066383 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_70 RESULT=pass
8472 14:46:00.096853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_69 RESULT=pass
8474 14:46:00.099773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_69 RESULT=pass>
8475 14:46:00.131266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_69 RESULT=fail>
8476 14:46:00.131565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_69 RESULT=fail
8478 14:46:00.168079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_69 RESULT=pass>
8479 14:46:00.168384 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_69 RESULT=pass
8481 14:46:00.203149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_69 RESULT=pass>
8482 14:46:00.203442 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_69 RESULT=pass
8484 14:46:00.246538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_69 RESULT=pass>
8485 14:46:00.246816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_69 RESULT=pass
8487 14:46:00.282402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_69 RESULT=pass>
8488 14:46:00.282693 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_69 RESULT=pass
8490 14:46:00.320021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_69 RESULT=pass>
8491 14:46:00.320331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_69 RESULT=pass
8493 14:46:00.357134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_68 RESULT=pass>
8494 14:46:00.357418 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_68 RESULT=pass
8496 14:46:00.394217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_68 RESULT=fail>
8497 14:46:00.394507 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_68 RESULT=fail
8499 14:46:00.434838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_68 RESULT=pass>
8500 14:46:00.435112 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_68 RESULT=pass
8502 14:46:00.468195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_68 RESULT=pass>
8503 14:46:00.468475 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_68 RESULT=pass
8505 14:46:00.501574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_68 RESULT=pass>
8506 14:46:00.501833 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_68 RESULT=pass
8508 14:46:00.537724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_68 RESULT=pass>
8509 14:46:00.537992 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_68 RESULT=pass
8511 14:46:00.574786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_68 RESULT=pass>
8512 14:46:00.575040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_68 RESULT=pass
8514 14:46:00.611837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_67 RESULT=pass>
8515 14:46:00.612136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_67 RESULT=pass
8517 14:46:00.654532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_67 RESULT=fail>
8518 14:46:00.654906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_67 RESULT=fail
8520 14:46:00.699983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_67 RESULT=pass>
8521 14:46:00.700277 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_67 RESULT=pass
8523 14:46:00.737509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_67 RESULT=pass>
8524 14:46:00.737784 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_67 RESULT=pass
8526 14:46:00.773372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_67 RESULT=pass>
8527 14:46:00.773662 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_67 RESULT=pass
8529 14:46:00.809396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_67 RESULT=pass>
8530 14:46:00.809685 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_67 RESULT=pass
8532 14:46:00.846545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_67 RESULT=pass>
8533 14:46:00.846821 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_67 RESULT=pass
8535 14:46:00.883352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_66 RESULT=pass>
8536 14:46:00.883608 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_66 RESULT=pass
8538 14:46:00.917557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_66 RESULT=fail>
8539 14:46:00.917835 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_66 RESULT=fail
8541 14:46:00.962711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_66 RESULT=pass>
8542 14:46:00.962976 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_66 RESULT=pass
8544 14:46:01.000038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_66 RESULT=pass>
8545 14:46:01.000310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_66 RESULT=pass
8547 14:46:01.036609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_66 RESULT=pass>
8548 14:46:01.036899 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_66 RESULT=pass
8550 14:46:01.073032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_66 RESULT=pass>
8551 14:46:01.073312 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_66 RESULT=pass
8553 14:46:01.110669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_66 RESULT=pass>
8554 14:46:01.110942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_66 RESULT=pass
8556 14:46:01.145384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_65 RESULT=pass>
8557 14:46:01.145670 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_65 RESULT=pass
8559 14:46:01.176745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_65 RESULT=fail>
8560 14:46:01.177013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_65 RESULT=fail
8562 14:46:01.219768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_65 RESULT=pass>
8563 14:46:01.220062 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_65 RESULT=pass
8565 14:46:01.257139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_65 RESULT=pass>
8566 14:46:01.257450 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_65 RESULT=pass
8568 14:46:01.295336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_65 RESULT=pass>
8569 14:46:01.295634 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_65 RESULT=pass
8571 14:46:01.334728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_65 RESULT=pass>
8572 14:46:01.335031 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_65 RESULT=pass
8574 14:46:01.374850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_65 RESULT=pass>
8575 14:46:01.375126 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_65 RESULT=pass
8577 14:46:01.411986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_64 RESULT=pass>
8578 14:46:01.412281 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_64 RESULT=pass
8580 14:46:01.445669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_64 RESULT=fail>
8581 14:46:01.445965 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_64 RESULT=fail
8583 14:46:01.488731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_64 RESULT=pass>
8584 14:46:01.489030 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_64 RESULT=pass
8586 14:46:01.528817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_64 RESULT=pass>
8587 14:46:01.529119 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_64 RESULT=pass
8589 14:46:01.565570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_64 RESULT=pass>
8590 14:46:01.565836 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_64 RESULT=pass
8592 14:46:01.603073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_64 RESULT=pass>
8593 14:46:01.603331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_64 RESULT=pass
8595 14:46:01.639961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_64 RESULT=pass>
8596 14:46:01.640256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_64 RESULT=pass
8598 14:46:01.677938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_63 RESULT=pass>
8599 14:46:01.678206 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_63 RESULT=pass
8601 14:46:01.711847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_63 RESULT=fail>
8602 14:46:01.712133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_63 RESULT=fail
8604 14:46:01.749609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_63 RESULT=pass>
8605 14:46:01.749878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_63 RESULT=pass
8607 14:46:01.785205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_63 RESULT=pass>
8608 14:46:01.785503 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_63 RESULT=pass
8610 14:46:01.820560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_63 RESULT=pass>
8611 14:46:01.820861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_63 RESULT=pass
8613 14:46:01.866688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_63 RESULT=pass>
8614 14:46:01.867407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_63 RESULT=pass
8616 14:46:01.905803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_63 RESULT=pass>
8617 14:46:01.906080 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_63 RESULT=pass
8619 14:46:01.943509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_62 RESULT=pass>
8620 14:46:01.943799 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_62 RESULT=pass
8622 14:46:01.977389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_62 RESULT=fail>
8623 14:46:01.977681 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_62 RESULT=fail
8625 14:46:02.020696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_62 RESULT=pass>
8626 14:46:02.020999 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_62 RESULT=pass
8628 14:46:02.057149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_62 RESULT=pass>
8629 14:46:02.057458 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_62 RESULT=pass
8631 14:46:02.095457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_62 RESULT=pass>
8632 14:46:02.095709 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_62 RESULT=pass
8634 14:46:02.135039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_62 RESULT=pass>
8635 14:46:02.135345 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_62 RESULT=pass
8637 14:46:02.170291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_62 RESULT=pass>
8638 14:46:02.170550 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_62 RESULT=pass
8640 14:46:02.207914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_61 RESULT=pass>
8641 14:46:02.208216 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_61 RESULT=pass
8643 14:46:02.240893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_61 RESULT=fail>
8644 14:46:02.241154 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_61 RESULT=fail
8646 14:46:02.285333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_61 RESULT=pass>
8647 14:46:02.285599 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_61 RESULT=pass
8649 14:46:02.324687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_61 RESULT=pass>
8650 14:46:02.324997 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_61 RESULT=pass
8652 14:46:02.363080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_61 RESULT=pass>
8653 14:46:02.363340 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_61 RESULT=pass
8655 14:46:02.400218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_61 RESULT=pass>
8656 14:46:02.400508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_61 RESULT=pass
8658 14:46:02.437826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_61 RESULT=pass>
8659 14:46:02.438088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_61 RESULT=pass
8661 14:46:02.474907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_60 RESULT=pass>
8662 14:46:02.475167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_60 RESULT=pass
8664 14:46:02.509933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_60 RESULT=fail>
8665 14:46:02.510250 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_60 RESULT=fail
8667 14:46:02.551237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_60 RESULT=pass>
8668 14:46:02.551532 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_60 RESULT=pass
8670 14:46:02.588832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_60 RESULT=pass>
8671 14:46:02.589124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_60 RESULT=pass
8673 14:46:02.623136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_60 RESULT=pass>
8674 14:46:02.623416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_60 RESULT=pass
8676 14:46:02.657139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_60 RESULT=pass>
8677 14:46:02.657463 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_60 RESULT=pass
8679 14:46:02.694716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_60 RESULT=pass>
8680 14:46:02.694982 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_60 RESULT=pass
8682 14:46:02.728402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_59 RESULT=pass>
8683 14:46:02.728720 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_59 RESULT=pass
8685 14:46:02.758708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_59 RESULT=fail>
8686 14:46:02.759007 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_59 RESULT=fail
8688 14:46:02.801034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_59 RESULT=pass>
8689 14:46:02.801304 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_59 RESULT=pass
8691 14:46:02.840129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_59 RESULT=pass>
8692 14:46:02.840423 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_59 RESULT=pass
8694 14:46:02.873357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_59 RESULT=pass>
8695 14:46:02.873610 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_59 RESULT=pass
8697 14:46:02.912117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_59 RESULT=pass>
8698 14:46:02.912431 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_59 RESULT=pass
8700 14:46:02.951096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_59 RESULT=pass>
8701 14:46:02.951397 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_59 RESULT=pass
8703 14:46:02.989468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_58 RESULT=pass>
8704 14:46:02.989749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_58 RESULT=pass
8706 14:46:03.032726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_58 RESULT=fail>
8707 14:46:03.033753 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_58 RESULT=fail
8709 14:46:03.086904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_58 RESULT=pass>
8710 14:46:03.087436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_58 RESULT=pass
8712 14:46:03.126210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_58 RESULT=pass>
8713 14:46:03.126506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_58 RESULT=pass
8715 14:46:03.162325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_58 RESULT=pass>
8716 14:46:03.162598 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_58 RESULT=pass
8718 14:46:03.197997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_58 RESULT=pass>
8719 14:46:03.198281 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_58 RESULT=pass
8721 14:46:03.233406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_58 RESULT=pass>
8722 14:46:03.233702 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_58 RESULT=pass
8724 14:46:03.271013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_57 RESULT=pass>
8725 14:46:03.271323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_57 RESULT=pass
8727 14:46:03.307286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_57 RESULT=fail>
8728 14:46:03.307606 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_57 RESULT=fail
8730 14:46:03.345476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_57 RESULT=pass>
8731 14:46:03.345792 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_57 RESULT=pass
8733 14:46:03.383086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_57 RESULT=pass>
8734 14:46:03.383409 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_57 RESULT=pass
8736 14:46:03.418416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_57 RESULT=pass>
8737 14:46:03.418712 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_57 RESULT=pass
8739 14:46:03.457189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_57 RESULT=pass>
8740 14:46:03.457570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_57 RESULT=pass
8742 14:46:03.494202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_57 RESULT=pass>
8743 14:46:03.494532 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_57 RESULT=pass
8745 14:46:03.531159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_56 RESULT=pass>
8746 14:46:03.531455 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_56 RESULT=pass
8748 14:46:03.565662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_56 RESULT=fail>
8749 14:46:03.565944 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_56 RESULT=fail
8751 14:46:03.606189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_56 RESULT=pass>
8752 14:46:03.606489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_56 RESULT=pass
8754 14:46:03.645631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_56 RESULT=pass>
8755 14:46:03.645948 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_56 RESULT=pass
8757 14:46:03.683344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_56 RESULT=pass>
8758 14:46:03.683642 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_56 RESULT=pass
8760 14:46:03.719973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_56 RESULT=pass>
8761 14:46:03.720281 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_56 RESULT=pass
8763 14:46:03.755119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_56 RESULT=pass>
8764 14:46:03.755393 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_56 RESULT=pass
8766 14:46:03.793286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_55 RESULT=pass>
8767 14:46:03.793572 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_55 RESULT=pass
8769 14:46:03.826157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_55 RESULT=fail>
8770 14:46:03.826432 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_55 RESULT=fail
8772 14:46:03.869158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_55 RESULT=pass>
8773 14:46:03.869517 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_55 RESULT=pass
8775 14:46:03.911777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_55 RESULT=pass>
8776 14:46:03.912084 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_55 RESULT=pass
8778 14:46:03.946358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_55 RESULT=pass>
8779 14:46:03.946666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_55 RESULT=pass
8781 14:46:03.982929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_55 RESULT=pass>
8782 14:46:03.983201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_55 RESULT=pass
8784 14:46:04.021065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_55 RESULT=pass>
8785 14:46:04.021390 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_55 RESULT=pass
8787 14:46:04.060975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_54 RESULT=pass>
8788 14:46:04.061311 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_54 RESULT=pass
8790 14:46:04.097397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_54 RESULT=fail>
8791 14:46:04.097699 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_54 RESULT=fail
8793 14:46:04.140440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_54 RESULT=pass>
8794 14:46:04.140716 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_54 RESULT=pass
8796 14:46:04.175443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_54 RESULT=pass>
8797 14:46:04.175743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_54 RESULT=pass
8799 14:46:04.212476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_54 RESULT=pass>
8800 14:46:04.212768 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_54 RESULT=pass
8802 14:46:04.251120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_54 RESULT=pass>
8803 14:46:04.251429 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_54 RESULT=pass
8805 14:46:04.290627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_54 RESULT=pass>
8806 14:46:04.290928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_54 RESULT=pass
8808 14:46:04.326059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_53 RESULT=pass>
8809 14:46:04.326344 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_53 RESULT=pass
8811 14:46:04.359591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_53 RESULT=fail>
8812 14:46:04.359900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_53 RESULT=fail
8814 14:46:04.399138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_53 RESULT=pass>
8815 14:46:04.399432 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_53 RESULT=pass
8817 14:46:04.440085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_53 RESULT=pass>
8818 14:46:04.441009 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_53 RESULT=pass
8820 14:46:04.482164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_53 RESULT=pass>
8821 14:46:04.482462 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_53 RESULT=pass
8823 14:46:04.517599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_53 RESULT=pass>
8824 14:46:04.517905 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_53 RESULT=pass
8826 14:46:04.552819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_53 RESULT=pass>
8827 14:46:04.553143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_53 RESULT=pass
8829 14:46:04.588731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_52 RESULT=pass>
8830 14:46:04.589061 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_52 RESULT=pass
8832 14:46:04.619624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_52 RESULT=fail>
8833 14:46:04.619950 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_52 RESULT=fail
8835 14:46:04.658840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_52 RESULT=pass>
8836 14:46:04.659174 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_52 RESULT=pass
8838 14:46:04.691056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_52 RESULT=pass>
8839 14:46:04.691363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_52 RESULT=pass
8841 14:46:04.725643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_52 RESULT=pass>
8842 14:46:04.725977 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_52 RESULT=pass
8844 14:46:04.758530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_52 RESULT=pass>
8845 14:46:04.758831 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_52 RESULT=pass
8847 14:46:04.792739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_52 RESULT=pass>
8848 14:46:04.793039 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_52 RESULT=pass
8850 14:46:04.826706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_51 RESULT=pass>
8851 14:46:04.827041 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_51 RESULT=pass
8853 14:46:04.859479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_51 RESULT=fail>
8854 14:46:04.859793 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_51 RESULT=fail
8856 14:46:04.897445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_51 RESULT=pass>
8857 14:46:04.897767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_51 RESULT=pass
8859 14:46:04.931046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_51 RESULT=pass>
8860 14:46:04.931368 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_51 RESULT=pass
8862 14:46:04.966849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_51 RESULT=pass>
8863 14:46:04.967189 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_51 RESULT=pass
8865 14:46:04.998257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_51 RESULT=pass>
8866 14:46:04.998558 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_51 RESULT=pass
8868 14:46:05.034596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_51 RESULT=pass>
8869 14:46:05.034902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_51 RESULT=pass
8871 14:46:05.071288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_50 RESULT=pass>
8872 14:46:05.071655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_50 RESULT=pass
8874 14:46:05.102594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_50 RESULT=fail>
8875 14:46:05.102910 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_50 RESULT=fail
8877 14:46:05.139383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_50 RESULT=pass>
8878 14:46:05.139707 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_50 RESULT=pass
8880 14:46:05.174971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_50 RESULT=pass>
8881 14:46:05.175290 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_50 RESULT=pass
8883 14:46:05.209561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_50 RESULT=pass>
8884 14:46:05.209865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_50 RESULT=pass
8886 14:46:05.245152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_50 RESULT=pass>
8887 14:46:05.245490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_50 RESULT=pass
8889 14:46:05.281852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_50 RESULT=pass>
8890 14:46:05.282152 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_50 RESULT=pass
8892 14:46:05.319106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_49 RESULT=pass>
8893 14:46:05.319425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_49 RESULT=pass
8895 14:46:05.354105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_49 RESULT=fail>
8896 14:46:05.354406 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_49 RESULT=fail
8898 14:46:05.392240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_49 RESULT=pass>
8899 14:46:05.392550 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_49 RESULT=pass
8901 14:46:05.429471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_49 RESULT=pass>
8902 14:46:05.429780 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_49 RESULT=pass
8904 14:46:05.465794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_49 RESULT=pass>
8905 14:46:05.466089 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_49 RESULT=pass
8907 14:46:05.501553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_49 RESULT=pass>
8908 14:46:05.501852 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_49 RESULT=pass
8910 14:46:05.538767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_49 RESULT=pass>
8911 14:46:05.539108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_49 RESULT=pass
8913 14:46:05.572989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_48 RESULT=pass>
8914 14:46:05.573285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_48 RESULT=pass
8916 14:46:05.604134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_48 RESULT=fail>
8917 14:46:05.604473 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_48 RESULT=fail
8919 14:46:05.646680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_48 RESULT=pass>
8920 14:46:05.647022 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_48 RESULT=pass
8922 14:46:05.682690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_48 RESULT=pass>
8923 14:46:05.683016 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_48 RESULT=pass
8925 14:46:05.719453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_48 RESULT=pass>
8926 14:46:05.719794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_48 RESULT=pass
8928 14:46:05.754073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_48 RESULT=pass>
8929 14:46:05.754380 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_48 RESULT=pass
8931 14:46:05.788195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_48 RESULT=pass>
8932 14:46:05.788522 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_48 RESULT=pass
8934 14:46:05.823197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_47 RESULT=pass>
8935 14:46:05.823509 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_47 RESULT=pass
8937 14:46:05.854127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_47 RESULT=fail>
8938 14:46:05.854416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_47 RESULT=fail
8940 14:46:05.894758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_47 RESULT=pass>
8941 14:46:05.895092 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_47 RESULT=pass
8943 14:46:05.931163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_47 RESULT=pass>
8944 14:46:05.931501 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_47 RESULT=pass
8946 14:46:05.969917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_47 RESULT=pass>
8947 14:46:05.970248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_47 RESULT=pass
8949 14:46:06.007022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_47 RESULT=pass>
8950 14:46:06.007350 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_47 RESULT=pass
8952 14:46:06.042640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_47 RESULT=pass>
8953 14:46:06.042992 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_47 RESULT=pass
8955 14:46:06.076445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_46 RESULT=pass>
8956 14:46:06.076765 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_46 RESULT=pass
8958 14:46:06.112642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_46 RESULT=fail>
8959 14:46:06.113029 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_46 RESULT=fail
8961 14:46:06.152558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_46 RESULT=pass>
8962 14:46:06.152913 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_46 RESULT=pass
8964 14:46:06.191045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_46 RESULT=pass>
8965 14:46:06.191408 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_46 RESULT=pass
8967 14:46:06.229651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_46 RESULT=pass>
8968 14:46:06.230006 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_46 RESULT=pass
8970 14:46:06.266010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_46 RESULT=pass>
8971 14:46:06.266350 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_46 RESULT=pass
8973 14:46:06.300896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_46 RESULT=pass>
8974 14:46:06.301231 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_46 RESULT=pass
8976 14:46:06.334503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_45 RESULT=pass>
8977 14:46:06.334837 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_45 RESULT=pass
8979 14:46:06.370244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_45 RESULT=fail>
8980 14:46:06.370571 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_45 RESULT=fail
8982 14:46:06.412042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_45 RESULT=pass>
8983 14:46:06.412340 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_45 RESULT=pass
8985 14:46:06.449669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_45 RESULT=pass>
8986 14:46:06.449993 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_45 RESULT=pass
8988 14:46:06.487753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_45 RESULT=pass>
8989 14:46:06.488100 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_45 RESULT=pass
8991 14:46:06.530124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_45 RESULT=pass>
8992 14:46:06.530468 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_45 RESULT=pass
8994 14:46:06.566571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_45 RESULT=pass>
8995 14:46:06.566952 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_45 RESULT=pass
8997 14:46:06.604078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_44 RESULT=pass>
8998 14:46:06.604423 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_44 RESULT=pass
9000 14:46:06.640821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_44 RESULT=fail>
9001 14:46:06.641175 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_44 RESULT=fail
9003 14:46:06.680437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_44 RESULT=pass>
9004 14:46:06.680786 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_44 RESULT=pass
9006 14:46:06.715642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_44 RESULT=pass>
9007 14:46:06.715979 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_44 RESULT=pass
9009 14:46:06.754461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_44 RESULT=pass>
9010 14:46:06.754807 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_44 RESULT=pass
9012 14:46:06.792274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_44 RESULT=pass>
9013 14:46:06.792611 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_44 RESULT=pass
9015 14:46:06.829550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_44 RESULT=pass>
9016 14:46:06.829914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_44 RESULT=pass
9018 14:46:06.866007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_43 RESULT=pass>
9019 14:46:06.866342 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_43 RESULT=pass
9021 14:46:06.896416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_43 RESULT=fail>
9022 14:46:06.896729 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_43 RESULT=fail
9024 14:46:06.936856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_43 RESULT=pass>
9025 14:46:06.937230 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_43 RESULT=pass
9027 14:46:06.970714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_43 RESULT=pass>
9028 14:46:06.971046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_43 RESULT=pass
9030 14:46:07.006155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_43 RESULT=pass>
9031 14:46:07.006482 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_43 RESULT=pass
9033 14:46:07.041729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_43 RESULT=pass>
9034 14:46:07.042040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_43 RESULT=pass
9036 14:46:07.077782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_43 RESULT=pass>
9037 14:46:07.078098 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_43 RESULT=pass
9039 14:46:07.114304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_42 RESULT=pass>
9040 14:46:07.114645 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_42 RESULT=pass
9042 14:46:07.146663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_42 RESULT=fail>
9043 14:46:07.147014 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_42 RESULT=fail
9045 14:46:07.185669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_42 RESULT=pass>
9046 14:46:07.186000 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_42 RESULT=pass
9048 14:46:07.223704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_42 RESULT=pass>
9049 14:46:07.224038 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_42 RESULT=pass
9051 14:46:07.260888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_42 RESULT=pass>
9052 14:46:07.261235 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_42 RESULT=pass
9054 14:46:07.296387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_42 RESULT=pass>
9055 14:46:07.296737 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_42 RESULT=pass
9057 14:46:07.330746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_42 RESULT=pass>
9058 14:46:07.331103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_42 RESULT=pass
9060 14:46:07.366684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_41 RESULT=pass>
9061 14:46:07.367064 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_41 RESULT=pass
9063 14:46:07.399220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_41 RESULT=fail>
9064 14:46:07.399558 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_41 RESULT=fail
9066 14:46:07.438671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_41 RESULT=pass>
9067 14:46:07.439005 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_41 RESULT=pass
9069 14:46:07.477032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_41 RESULT=pass>
9070 14:46:07.477360 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_41 RESULT=pass
9072 14:46:07.513243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_41 RESULT=pass>
9073 14:46:07.513551 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_41 RESULT=pass
9075 14:46:07.546812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_41 RESULT=pass>
9076 14:46:07.547136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_41 RESULT=pass
9078 14:46:07.584004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_41 RESULT=pass>
9079 14:46:07.584322 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_41 RESULT=pass
9081 14:46:07.623286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_40 RESULT=pass>
9082 14:46:07.623597 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_40 RESULT=pass
9084 14:46:07.655055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_40 RESULT=fail>
9085 14:46:07.655370 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_40 RESULT=fail
9087 14:46:07.697364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_40 RESULT=pass>
9088 14:46:07.697679 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_40 RESULT=pass
9090 14:46:07.733586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_40 RESULT=pass>
9091 14:46:07.733898 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_40 RESULT=pass
9093 14:46:07.768088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_40 RESULT=pass>
9094 14:46:07.768406 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_40 RESULT=pass
9096 14:46:07.808169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_40 RESULT=pass>
9097 14:46:07.808488 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_40 RESULT=pass
9099 14:46:07.841521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_40 RESULT=pass>
9100 14:46:07.841829 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_40 RESULT=pass
9102 14:46:07.877532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_39 RESULT=pass>
9103 14:46:07.877843 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_39 RESULT=pass
9105 14:46:07.912248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_39 RESULT=fail>
9106 14:46:07.912588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_39 RESULT=fail
9108 14:46:07.951699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_39 RESULT=pass>
9109 14:46:07.951998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_39 RESULT=pass
9111 14:46:07.989960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_39 RESULT=pass>
9112 14:46:07.990292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_39 RESULT=pass
9114 14:46:08.029434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_39 RESULT=pass>
9115 14:46:08.029755 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_39 RESULT=pass
9117 14:46:08.067662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_39 RESULT=pass>
9118 14:46:08.067973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_39 RESULT=pass
9120 14:46:08.102317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_39 RESULT=pass>
9121 14:46:08.102626 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_39 RESULT=pass
9123 14:46:08.138868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_38 RESULT=pass>
9124 14:46:08.139207 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_38 RESULT=pass
9126 14:46:08.172818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_38 RESULT=fail>
9127 14:46:08.173120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_38 RESULT=fail
9129 14:46:08.214878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_38 RESULT=pass>
9130 14:46:08.215214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_38 RESULT=pass
9132 14:46:08.257866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_38 RESULT=pass>
9133 14:46:08.258183 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_38 RESULT=pass
9135 14:46:08.294397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_38 RESULT=pass>
9136 14:46:08.294756 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_38 RESULT=pass
9138 14:46:08.331516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_38 RESULT=pass>
9139 14:46:08.331833 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_38 RESULT=pass
9141 14:46:08.369597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_38 RESULT=pass>
9142 14:46:08.369904 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_38 RESULT=pass
9144 14:46:08.407848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_37 RESULT=pass>
9145 14:46:08.408196 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_37 RESULT=pass
9147 14:46:08.440381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_37 RESULT=fail>
9148 14:46:08.440714 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_37 RESULT=fail
9150 14:46:08.480662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_37 RESULT=pass>
9151 14:46:08.480976 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_37 RESULT=pass
9153 14:46:08.518880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_37 RESULT=pass>
9154 14:46:08.519227 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_37 RESULT=pass
9156 14:46:08.557147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_37 RESULT=pass>
9157 14:46:08.557535 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_37 RESULT=pass
9159 14:46:08.594674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_37 RESULT=pass>
9160 14:46:08.595025 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_37 RESULT=pass
9162 14:46:08.630045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_37 RESULT=pass>
9163 14:46:08.630403 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_37 RESULT=pass
9165 14:46:08.665598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_36 RESULT=pass>
9166 14:46:08.665908 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_36 RESULT=pass
9168 14:46:08.698731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_36 RESULT=fail>
9169 14:46:08.699037 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_36 RESULT=fail
9171 14:46:08.740700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_36 RESULT=pass>
9172 14:46:08.741013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_36 RESULT=pass
9174 14:46:08.774476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_36 RESULT=pass>
9175 14:46:08.774763 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_36 RESULT=pass
9177 14:46:08.808948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_36 RESULT=pass>
9178 14:46:08.809230 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_36 RESULT=pass
9180 14:46:08.841190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_36 RESULT=pass>
9181 14:46:08.841548 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_36 RESULT=pass
9183 14:46:08.873685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_36 RESULT=pass>
9184 14:46:08.873989 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_36 RESULT=pass
9186 14:46:08.905881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_35 RESULT=pass>
9187 14:46:08.906187 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_35 RESULT=pass
9189 14:46:08.939001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_35 RESULT=fail>
9190 14:46:08.939288 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_35 RESULT=fail
9192 14:46:08.981211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_35 RESULT=pass>
9193 14:46:08.981538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_35 RESULT=pass
9195 14:46:09.017448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_35 RESULT=pass>
9196 14:46:09.017714 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_35 RESULT=pass
9198 14:46:09.056413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_35 RESULT=pass>
9199 14:46:09.056693 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_35 RESULT=pass
9201 14:46:09.093108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_35 RESULT=pass>
9202 14:46:09.093400 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_35 RESULT=pass
9204 14:46:09.134757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_35 RESULT=pass>
9205 14:46:09.135036 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_35 RESULT=pass
9207 14:46:09.175660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_34 RESULT=pass>
9208 14:46:09.175955 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_34 RESULT=pass
9210 14:46:09.213811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_34 RESULT=fail>
9211 14:46:09.214121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_34 RESULT=fail
9213 14:46:09.256035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_34 RESULT=pass>
9214 14:46:09.256334 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_34 RESULT=pass
9216 14:46:09.293596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_34 RESULT=pass>
9217 14:46:09.293900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_34 RESULT=pass
9219 14:46:09.329553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_34 RESULT=pass>
9220 14:46:09.329832 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_34 RESULT=pass
9222 14:46:09.365892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_34 RESULT=pass>
9223 14:46:09.366160 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_34 RESULT=pass
9225 14:46:09.401299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_34 RESULT=pass>
9226 14:46:09.401567 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_34 RESULT=pass
9228 14:46:09.439814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_33 RESULT=pass>
9229 14:46:09.440092 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_33 RESULT=pass
9231 14:46:09.472914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_33 RESULT=fail>
9232 14:46:09.473173 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_33 RESULT=fail
9234 14:46:09.513494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_33 RESULT=pass>
9235 14:46:09.513783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_33 RESULT=pass
9237 14:46:09.548657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_33 RESULT=pass>
9238 14:46:09.548973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_33 RESULT=pass
9240 14:46:09.583466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_33 RESULT=pass>
9241 14:46:09.583729 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_33 RESULT=pass
9243 14:46:09.616904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_33 RESULT=pass>
9244 14:46:09.617211 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_33 RESULT=pass
9246 14:46:09.651508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_33 RESULT=pass>
9247 14:46:09.651784 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_33 RESULT=pass
9249 14:46:09.690658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_32 RESULT=pass>
9250 14:46:09.690968 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_32 RESULT=pass
9252 14:46:09.724032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_32 RESULT=fail>
9253 14:46:09.724314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_32 RESULT=fail
9255 14:46:09.761329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_32 RESULT=pass>
9256 14:46:09.761620 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_32 RESULT=pass
9258 14:46:09.797016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_32 RESULT=pass>
9259 14:46:09.797295 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_32 RESULT=pass
9261 14:46:09.833177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_32 RESULT=pass>
9262 14:46:09.833539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_32 RESULT=pass
9264 14:46:09.868466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_32 RESULT=pass>
9265 14:46:09.868741 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_32 RESULT=pass
9267 14:46:09.901999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_32 RESULT=pass>
9268 14:46:09.902290 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_32 RESULT=pass
9270 14:46:09.943117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_31 RESULT=pass>
9271 14:46:09.943400 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_31 RESULT=pass
9273 14:46:09.974563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_31 RESULT=fail>
9274 14:46:09.974834 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_31 RESULT=fail
9276 14:46:10.011342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_31 RESULT=pass>
9277 14:46:10.011615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_31 RESULT=pass
9279 14:46:10.047495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_31 RESULT=pass>
9280 14:46:10.047826 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_31 RESULT=pass
9282 14:46:10.085574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_31 RESULT=pass>
9283 14:46:10.085856 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_31 RESULT=pass
9285 14:46:10.119088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_31 RESULT=pass>
9286 14:46:10.119407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_31 RESULT=pass
9288 14:46:10.152593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_31 RESULT=pass>
9289 14:46:10.152859 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_31 RESULT=pass
9291 14:46:10.186681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_30 RESULT=pass>
9292 14:46:10.186945 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_30 RESULT=pass
9294 14:46:10.218158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_30 RESULT=fail>
9295 14:46:10.218469 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_30 RESULT=fail
9297 14:46:10.257060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_30 RESULT=pass>
9298 14:46:10.257414 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_30 RESULT=pass
9300 14:46:10.290457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_30 RESULT=pass>
9301 14:46:10.290755 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_30 RESULT=pass
9303 14:46:10.326345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_30 RESULT=pass>
9304 14:46:10.326680 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_30 RESULT=pass
9306 14:46:10.364836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_30 RESULT=pass>
9307 14:46:10.365109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_30 RESULT=pass
9309 14:46:10.399632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_30 RESULT=pass>
9310 14:46:10.399913 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_30 RESULT=pass
9312 14:46:10.432919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_29 RESULT=pass>
9313 14:46:10.433189 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_29 RESULT=pass
9315 14:46:10.470416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_29 RESULT=pass>
9316 14:46:10.470687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_29 RESULT=pass
9318 14:46:10.513501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_29 RESULT=pass>
9319 14:46:10.513873 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_29 RESULT=pass
9321 14:46:10.549766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_29 RESULT=pass>
9322 14:46:10.550047 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_29 RESULT=pass
9324 14:46:10.585881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_29 RESULT=pass>
9325 14:46:10.586152 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_29 RESULT=pass
9327 14:46:10.621464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_29 RESULT=pass>
9328 14:46:10.621732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_29 RESULT=pass
9330 14:46:10.661931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_29 RESULT=pass>
9331 14:46:10.662217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_29 RESULT=pass
9333 14:46:10.702610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_28 RESULT=pass>
9334 14:46:10.702875 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_28 RESULT=pass
9336 14:46:10.738568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_28 RESULT=pass>
9337 14:46:10.738848 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_28 RESULT=pass
9339 14:46:10.777663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_28 RESULT=pass>
9340 14:46:10.777934 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_28 RESULT=pass
9342 14:46:10.816974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_28 RESULT=pass>
9343 14:46:10.817304 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_28 RESULT=pass
9345 14:46:10.857598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_28 RESULT=pass>
9346 14:46:10.857905 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_28 RESULT=pass
9348 14:46:10.898518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_28 RESULT=pass>
9349 14:46:10.898840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_28 RESULT=pass
9351 14:46:10.938204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_28 RESULT=pass>
9352 14:46:10.938521 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_28 RESULT=pass
9354 14:46:10.981699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_27 RESULT=pass>
9355 14:46:10.982000 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_27 RESULT=pass
9357 14:46:11.019151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_27 RESULT=pass>
9358 14:46:11.019454 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_27 RESULT=pass
9360 14:46:11.060250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_27 RESULT=pass>
9361 14:46:11.060563 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_27 RESULT=pass
9363 14:46:11.100487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_27 RESULT=pass>
9364 14:46:11.100794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_27 RESULT=pass
9366 14:46:11.141996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_27 RESULT=pass>
9367 14:46:11.142276 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_27 RESULT=pass
9369 14:46:11.179198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_27 RESULT=pass>
9370 14:46:11.179506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_27 RESULT=pass
9372 14:46:11.216530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_27 RESULT=pass>
9373 14:46:11.216833 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_27 RESULT=pass
9375 14:46:11.256288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_26 RESULT=pass>
9376 14:46:11.256598 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_26 RESULT=pass
9378 14:46:11.291762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_26 RESULT=pass>
9379 14:46:11.292046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_26 RESULT=pass
9381 14:46:11.338036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_26 RESULT=pass>
9382 14:46:11.338310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_26 RESULT=pass
9384 14:46:11.372890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_26 RESULT=pass>
9385 14:46:11.373181 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_26 RESULT=pass
9387 14:46:11.406037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_26 RESULT=pass>
9388 14:46:11.406305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_26 RESULT=pass
9390 14:46:11.441855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_26 RESULT=pass>
9391 14:46:11.442143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_26 RESULT=pass
9393 14:46:11.482713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_26 RESULT=pass>
9394 14:46:11.482987 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_26 RESULT=pass
9396 14:46:11.521131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_25 RESULT=pass>
9397 14:46:11.521441 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_25 RESULT=pass
9399 14:46:11.555535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_25 RESULT=pass>
9400 14:46:11.555816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_25 RESULT=pass
9402 14:46:11.595107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_25 RESULT=pass>
9403 14:46:11.595366 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_25 RESULT=pass
9405 14:46:11.631267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_25 RESULT=pass>
9406 14:46:11.631570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_25 RESULT=pass
9408 14:46:11.671870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_25 RESULT=pass>
9409 14:46:11.672174 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_25 RESULT=pass
9411 14:46:11.709536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_25 RESULT=pass>
9412 14:46:11.709800 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_25 RESULT=pass
9414 14:46:11.744927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_25 RESULT=pass>
9415 14:46:11.745216 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_25 RESULT=pass
9417 14:46:11.782227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_24 RESULT=pass>
9418 14:46:11.782500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_24 RESULT=pass
9420 14:46:11.817101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_24 RESULT=pass>
9421 14:46:11.817448 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_24 RESULT=pass
9423 14:46:11.858252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_24 RESULT=pass>
9424 14:46:11.858551 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_24 RESULT=pass
9426 14:46:11.894250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_24 RESULT=pass>
9427 14:46:11.894528 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_24 RESULT=pass
9429 14:46:11.938861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_24 RESULT=pass>
9430 14:46:11.939169 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_24 RESULT=pass
9432 14:46:11.977466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_24 RESULT=pass>
9433 14:46:11.977733 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_24 RESULT=pass
9435 14:46:12.014553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_24 RESULT=pass>
9436 14:46:12.014823 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_24 RESULT=pass
9438 14:46:12.051081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_23 RESULT=pass>
9439 14:46:12.051357 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_23 RESULT=pass
9441 14:46:12.083061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_23 RESULT=pass>
9442 14:46:12.083335 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_23 RESULT=pass
9444 14:46:12.124676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_23 RESULT=pass>
9445 14:46:12.124955 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_23 RESULT=pass
9447 14:46:12.161185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_23 RESULT=pass>
9448 14:46:12.161508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_23 RESULT=pass
9450 14:46:12.198848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_23 RESULT=pass>
9451 14:46:12.199120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_23 RESULT=pass
9453 14:46:12.235767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_23 RESULT=pass>
9454 14:46:12.236044 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_23 RESULT=pass
9456 14:46:12.272606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_23 RESULT=pass>
9457 14:46:12.272893 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_23 RESULT=pass
9459 14:46:12.309412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_22 RESULT=pass>
9460 14:46:12.309721 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_22 RESULT=pass
9462 14:46:12.343344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_22 RESULT=pass>
9463 14:46:12.343651 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_22 RESULT=pass
9465 14:46:12.380652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_22 RESULT=pass>
9466 14:46:12.380962 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_22 RESULT=pass
9468 14:46:12.415059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_22 RESULT=pass>
9469 14:46:12.415329 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_22 RESULT=pass
9471 14:46:12.452598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_22 RESULT=pass>
9472 14:46:12.452891 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_22 RESULT=pass
9474 14:46:12.488384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_22 RESULT=pass>
9475 14:46:12.488645 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_22 RESULT=pass
9477 14:46:12.525450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_22 RESULT=pass>
9478 14:46:12.525721 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_22 RESULT=pass
9480 14:46:12.566429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_21 RESULT=pass>
9481 14:46:12.566706 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_21 RESULT=pass
9483 14:46:12.598750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_21 RESULT=fail>
9484 14:46:12.599016 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_21 RESULT=fail
9486 14:46:12.638721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_21 RESULT=pass>
9487 14:46:12.639014 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_21 RESULT=pass
9489 14:46:12.675782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_21 RESULT=pass>
9490 14:46:12.676054 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_21 RESULT=pass
9492 14:46:12.709156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_21 RESULT=pass>
9493 14:46:12.709417 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_21 RESULT=pass
9495 14:46:12.746095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_21 RESULT=pass>
9496 14:46:12.746384 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_21 RESULT=pass
9498 14:46:12.785005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_21 RESULT=pass>
9499 14:46:12.785296 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_21 RESULT=pass
9501 14:46:12.820637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_20 RESULT=pass>
9502 14:46:12.820912 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_20 RESULT=pass
9504 14:46:12.857139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_20 RESULT=fail>
9505 14:46:12.857473 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_20 RESULT=fail
9507 14:46:12.895083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_20 RESULT=pass>
9508 14:46:12.895349 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_20 RESULT=pass
9510 14:46:12.927471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_20 RESULT=pass>
9511 14:46:12.927749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_20 RESULT=pass
9513 14:46:12.965220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_20 RESULT=pass>
9514 14:46:12.965527 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_20 RESULT=pass
9516 14:46:13.002808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_20 RESULT=pass>
9517 14:46:13.003067 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_20 RESULT=pass
9519 14:46:13.037894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_20 RESULT=pass>
9520 14:46:13.038195 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_20 RESULT=pass
9522 14:46:13.076282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_19 RESULT=pass>
9523 14:46:13.076561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_19 RESULT=pass
9525 14:46:13.107704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_19 RESULT=fail>
9526 14:46:13.107966 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_19 RESULT=fail
9528 14:46:13.150476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_19 RESULT=pass>
9529 14:46:13.150793 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_19 RESULT=pass
9531 14:46:13.186154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_19 RESULT=pass>
9532 14:46:13.186488 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_19 RESULT=pass
9534 14:46:13.223135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_19 RESULT=pass>
9535 14:46:13.223446 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_19 RESULT=pass
9537 14:46:13.260056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_19 RESULT=pass>
9538 14:46:13.260364 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_19 RESULT=pass
9540 14:46:13.296482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_19 RESULT=pass>
9541 14:46:13.296778 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_19 RESULT=pass
9543 14:46:13.331362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_18 RESULT=pass>
9544 14:46:13.331665 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_18 RESULT=pass
9546 14:46:13.366282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_18 RESULT=fail>
9547 14:46:13.366562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_18 RESULT=fail
9549 14:46:13.407202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_18 RESULT=pass>
9550 14:46:13.407510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_18 RESULT=pass
9552 14:46:13.445568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_18 RESULT=pass>
9553 14:46:13.445922 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_18 RESULT=pass
9555 14:46:13.480034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_18 RESULT=pass>
9556 14:46:13.480348 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_18 RESULT=pass
9558 14:46:13.516434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_18 RESULT=pass>
9559 14:46:13.516724 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_18 RESULT=pass
9561 14:46:13.553903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_18 RESULT=pass>
9562 14:46:13.554208 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_18 RESULT=pass
9564 14:46:13.590969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_17 RESULT=pass>
9565 14:46:13.591244 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_17 RESULT=pass
9567 14:46:13.624955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_17 RESULT=fail>
9568 14:46:13.625253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_17 RESULT=fail
9570 14:46:13.665457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_17 RESULT=pass>
9571 14:46:13.665739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_17 RESULT=pass
9573 14:46:13.705074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_17 RESULT=pass>
9574 14:46:13.705351 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_17 RESULT=pass
9576 14:46:13.739868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_17 RESULT=pass>
9577 14:46:13.740142 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_17 RESULT=pass
9579 14:46:13.775574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_17 RESULT=pass>
9580 14:46:13.775854 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_17 RESULT=pass
9582 14:46:13.814192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_17 RESULT=pass>
9583 14:46:13.814496 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_17 RESULT=pass
9585 14:46:13.848173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_16 RESULT=pass>
9586 14:46:13.848459 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_16 RESULT=pass
9588 14:46:13.880619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_16 RESULT=fail>
9589 14:46:13.880929 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_16 RESULT=fail
9591 14:46:13.921648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_16 RESULT=pass>
9592 14:46:13.921937 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_16 RESULT=pass
9594 14:46:13.957630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_16 RESULT=pass>
9595 14:46:13.957901 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_16 RESULT=pass
9597 14:46:13.995203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_16 RESULT=pass>
9598 14:46:13.995479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_16 RESULT=pass
9600 14:46:14.031119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_16 RESULT=pass>
9601 14:46:14.031400 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_16 RESULT=pass
9603 14:46:14.070019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_16 RESULT=pass>
9604 14:46:14.070318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_16 RESULT=pass
9606 14:46:14.108333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_15 RESULT=pass>
9607 14:46:14.108612 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_15 RESULT=pass
9609 14:46:14.143471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_15 RESULT=fail>
9610 14:46:14.143763 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_15 RESULT=fail
9612 14:46:14.186413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_15 RESULT=pass>
9613 14:46:14.186676 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_15 RESULT=pass
9615 14:46:14.225523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_15 RESULT=pass>
9616 14:46:14.225825 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_15 RESULT=pass
9618 14:46:14.265175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_15 RESULT=pass>
9619 14:46:14.265494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_15 RESULT=pass
9621 14:46:14.301982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_15 RESULT=pass>
9622 14:46:14.302256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_15 RESULT=pass
9624 14:46:14.339770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_15 RESULT=pass>
9625 14:46:14.340050 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_15 RESULT=pass
9627 14:46:14.379319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_14 RESULT=pass>
9628 14:46:14.379632 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_14 RESULT=pass
9630 14:46:14.417255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_14 RESULT=fail>
9631 14:46:14.417534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_14 RESULT=fail
9633 14:46:14.457386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_14 RESULT=pass>
9634 14:46:14.457664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_14 RESULT=pass
9636 14:46:14.494625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_14 RESULT=pass>
9637 14:46:14.494906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_14 RESULT=pass
9639 14:46:14.528441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_14 RESULT=pass>
9640 14:46:14.528715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_14 RESULT=pass
9642 14:46:14.565816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_14 RESULT=pass>
9643 14:46:14.566101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_14 RESULT=pass
9645 14:46:14.601813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_14 RESULT=pass>
9646 14:46:14.602137 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_14 RESULT=pass
9648 14:46:14.638608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_13 RESULT=pass>
9649 14:46:14.638932 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_13 RESULT=pass
9651 14:46:14.670206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_13 RESULT=fail>
9652 14:46:14.670488 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_13 RESULT=fail
9654 14:46:14.710107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_13 RESULT=pass>
9655 14:46:14.710400 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_13 RESULT=pass
9657 14:46:14.746227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_13 RESULT=pass>
9658 14:46:14.746555 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_13 RESULT=pass
9660 14:46:14.786699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_13 RESULT=pass>
9661 14:46:14.786977 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_13 RESULT=pass
9663 14:46:14.827150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_13 RESULT=pass>
9664 14:46:14.827423 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_13 RESULT=pass
9666 14:46:14.866947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_13 RESULT=pass>
9667 14:46:14.867267 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_13 RESULT=pass
9669 14:46:14.904736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_12 RESULT=pass>
9670 14:46:14.905006 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_12 RESULT=pass
9672 14:46:14.937867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_12 RESULT=fail>
9673 14:46:14.938155 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_12 RESULT=fail
9675 14:46:14.979786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_12 RESULT=pass>
9676 14:46:14.980071 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_12 RESULT=pass
9678 14:46:15.018566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_12 RESULT=pass>
9679 14:46:15.018839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_12 RESULT=pass
9681 14:46:15.055622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_12 RESULT=pass>
9682 14:46:15.055913 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_12 RESULT=pass
9684 14:46:15.091894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_12 RESULT=pass>
9685 14:46:15.092164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_12 RESULT=pass
9687 14:46:15.130472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_12 RESULT=pass>
9688 14:46:15.130758 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_12 RESULT=pass
9690 14:46:15.169465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_11 RESULT=pass>
9691 14:46:15.169738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_11 RESULT=pass
9693 14:46:15.203918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_11 RESULT=fail>
9694 14:46:15.204245 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_11 RESULT=fail
9696 14:46:15.243197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_11 RESULT=pass>
9697 14:46:15.243517 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_11 RESULT=pass
9699 14:46:15.280975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_11 RESULT=pass>
9700 14:46:15.281372 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_11 RESULT=pass
9702 14:46:15.319132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_11 RESULT=pass>
9703 14:46:15.319485 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_11 RESULT=pass
9705 14:46:15.353505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_11 RESULT=pass>
9706 14:46:15.353824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_11 RESULT=pass
9708 14:46:15.389828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_11 RESULT=pass>
9709 14:46:15.390166 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_11 RESULT=pass
9711 14:46:15.424616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_10 RESULT=pass>
9712 14:46:15.424967 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_10 RESULT=pass
9714 14:46:15.459383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_10 RESULT=fail>
9715 14:46:15.459733 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_10 RESULT=fail
9717 14:46:15.498686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_10 RESULT=pass>
9718 14:46:15.499007 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_10 RESULT=pass
9720 14:46:15.535835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_10 RESULT=pass>
9721 14:46:15.536186 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_10 RESULT=pass
9723 14:46:15.575208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_10 RESULT=pass>
9724 14:46:15.575559 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_10 RESULT=pass
9726 14:46:15.612587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_10 RESULT=pass>
9727 14:46:15.612906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_10 RESULT=pass
9729 14:46:15.648925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_10 RESULT=pass>
9730 14:46:15.649289 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_10 RESULT=pass
9732 14:46:15.687762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_9 RESULT=pass>
9733 14:46:15.688110 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_9 RESULT=pass
9735 14:46:15.719136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_9 RESULT=fail>
9736 14:46:15.719502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_9 RESULT=fail
9738 14:46:15.758112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_9 RESULT=pass>
9739 14:46:15.758479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_9 RESULT=pass
9741 14:46:15.795754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_9 RESULT=pass>
9742 14:46:15.796099 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_9 RESULT=pass
9744 14:46:15.830482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_9 RESULT=pass>
9745 14:46:15.830850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_9 RESULT=pass
9747 14:46:15.869148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_9 RESULT=pass>
9748 14:46:15.869539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_9 RESULT=pass
9750 14:46:15.911010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_9 RESULT=pass>
9751 14:46:15.911316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_9 RESULT=pass
9753 14:46:15.942482 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_8 RESULT=pass
9755 14:46:15.945701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_8 RESULT=pass>
9756 14:46:15.978084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_8 RESULT=fail>
9757 14:46:15.978417 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_8 RESULT=fail
9759 14:46:16.021021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_8 RESULT=pass>
9760 14:46:16.021352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_8 RESULT=pass
9762 14:46:16.061047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_8 RESULT=pass>
9763 14:46:16.061391 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_8 RESULT=pass
9765 14:46:16.096132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_8 RESULT=pass>
9766 14:46:16.096504 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_8 RESULT=pass
9768 14:46:16.132319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_8 RESULT=pass>
9769 14:46:16.132664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_8 RESULT=pass
9771 14:46:16.171264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_8 RESULT=pass>
9772 14:46:16.171593 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_8 RESULT=pass
9774 14:46:16.213316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_7 RESULT=pass>
9775 14:46:16.213636 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_7 RESULT=pass
9777 14:46:16.253227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_7 RESULT=fail>
9778 14:46:16.253597 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_7 RESULT=fail
9780 14:46:16.292385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_7 RESULT=pass>
9781 14:46:16.292700 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_7 RESULT=pass
9783 14:46:16.328129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_7 RESULT=pass>
9784 14:46:16.328461 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_7 RESULT=pass
9786 14:46:16.362880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_7 RESULT=pass>
9787 14:46:16.363239 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_7 RESULT=pass
9789 14:46:16.396903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_7 RESULT=pass>
9790 14:46:16.397232 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_7 RESULT=pass
9792 14:46:16.432378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_7 RESULT=pass>
9793 14:46:16.432704 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_7 RESULT=pass
9795 14:46:16.468915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_6 RESULT=pass>
9796 14:46:16.469281 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_6 RESULT=pass
9798 14:46:16.501247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_6 RESULT=fail>
9799 14:46:16.501614 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_6 RESULT=fail
9801 14:46:16.541116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_6 RESULT=pass>
9802 14:46:16.541474 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_6 RESULT=pass
9804 14:46:16.578057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_6 RESULT=pass>
9805 14:46:16.578404 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_6 RESULT=pass
9807 14:46:16.617566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_6 RESULT=pass>
9808 14:46:16.617890 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_6 RESULT=pass
9810 14:46:16.652883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_6 RESULT=pass>
9811 14:46:16.653226 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_6 RESULT=pass
9813 14:46:16.690395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_6 RESULT=pass>
9814 14:46:16.690723 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_6 RESULT=pass
9816 14:46:16.726869 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_5 RESULT=pass
9818 14:46:16.729931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_5 RESULT=pass>
9819 14:46:16.762556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_5 RESULT=pass>
9820 14:46:16.762897 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_5 RESULT=pass
9822 14:46:16.802134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_5 RESULT=pass>
9823 14:46:16.802477 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_5 RESULT=pass
9825 14:46:16.841695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_5 RESULT=pass>
9826 14:46:16.842022 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_5 RESULT=pass
9828 14:46:16.877047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_5 RESULT=pass>
9829 14:46:16.877373 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_5 RESULT=pass
9831 14:46:16.912342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_5 RESULT=fail>
9832 14:46:16.912690 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_5 RESULT=fail
9834 14:46:16.948979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_5 RESULT=pass>
9835 14:46:16.949295 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_5 RESULT=pass
9837 14:46:16.984694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_4 RESULT=pass>
9838 14:46:16.985022 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_4 RESULT=pass
9840 14:46:17.020416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_4 RESULT=pass>
9841 14:46:17.020771 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_4 RESULT=pass
9843 14:46:17.060015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_4 RESULT=pass>
9844 14:46:17.060340 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_4 RESULT=pass
9846 14:46:17.094755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_4 RESULT=pass>
9847 14:46:17.095078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_4 RESULT=pass
9849 14:46:17.130187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_4 RESULT=pass>
9850 14:46:17.130519 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_4 RESULT=pass
9852 14:46:17.163977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_4 RESULT=fail>
9853 14:46:17.164354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_4 RESULT=fail
9855 14:46:17.202241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_4 RESULT=pass>
9856 14:46:17.202570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_4 RESULT=pass
9858 14:46:17.234839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_3 RESULT=pass
9860 14:46:17.237842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_3 RESULT=pass>
9861 14:46:17.272750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_3 RESULT=pass>
9862 14:46:17.273078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_3 RESULT=pass
9864 14:46:17.316041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_3 RESULT=pass>
9865 14:46:17.316371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_3 RESULT=pass
9867 14:46:17.356712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_3 RESULT=pass>
9868 14:46:17.357040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_3 RESULT=pass
9870 14:46:17.393045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_3 RESULT=pass>
9871 14:46:17.393375 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_3 RESULT=pass
9873 14:46:17.428529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_3 RESULT=fail>
9874 14:46:17.428860 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_3 RESULT=fail
9876 14:46:17.465853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_3 RESULT=pass>
9877 14:46:17.466181 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_3 RESULT=pass
9879 14:46:17.501931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_2 RESULT=pass>
9880 14:46:17.502261 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_2 RESULT=pass
9882 14:46:17.536202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_2 RESULT=pass>
9883 14:46:17.536529 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_2 RESULT=pass
9885 14:46:17.574793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_2 RESULT=pass>
9886 14:46:17.575149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_2 RESULT=pass
9888 14:46:17.615687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_2 RESULT=pass>
9889 14:46:17.616013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_2 RESULT=pass
9891 14:46:17.651266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_2 RESULT=pass>
9892 14:46:17.651595 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_2 RESULT=pass
9894 14:46:17.686515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_2 RESULT=fail>
9895 14:46:17.686841 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_2 RESULT=fail
9897 14:46:17.723247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_2 RESULT=pass>
9898 14:46:17.723574 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_2 RESULT=pass
9900 14:46:17.760454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_1 RESULT=pass>
9901 14:46:17.760780 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_1 RESULT=pass
9903 14:46:17.796718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_1 RESULT=pass>
9904 14:46:17.797042 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_1 RESULT=pass
9906 14:46:17.838979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_1 RESULT=pass>
9907 14:46:17.839339 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_1 RESULT=pass
9909 14:46:17.876030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_1 RESULT=pass>
9910 14:46:17.876372 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_1 RESULT=pass
9912 14:46:17.912822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_1 RESULT=pass>
9913 14:46:17.913164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_1 RESULT=pass
9915 14:46:17.949950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_1 RESULT=fail>
9916 14:46:17.950315 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_1 RESULT=fail
9918 14:46:17.986583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_1 RESULT=pass>
9919 14:46:17.986927 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_1 RESULT=pass
9921 14:46:18.022912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_0 RESULT=pass>
9922 14:46:18.023255 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_0 RESULT=pass
9924 14:46:18.055980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_0 RESULT=pass>
9925 14:46:18.056353 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_0 RESULT=pass
9927 14:46:18.093254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_0 RESULT=pass>
9928 14:46:18.093639 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_0 RESULT=pass
9930 14:46:18.127371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_0 RESULT=pass>
9931 14:46:18.127712 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_0 RESULT=pass
9933 14:46:18.166055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_0 RESULT=pass>
9934 14:46:18.166378 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_0 RESULT=pass
9936 14:46:18.201395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_0 RESULT=fail>
9937 14:46:18.201719 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_0 RESULT=fail
9939 14:46:18.240321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_0 RESULT=pass>
9940 14:46:18.240652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_0 RESULT=pass
9942 14:46:18.273277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
9943 14:46:18.273456 + set +x
9944 14:46:18.273716 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
9946 14:46:18.280269 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 14166990_1.6.2.3.5>
9947 14:46:18.280579 Received signal: <ENDRUN> 1_kselftest-alsa 14166990_1.6.2.3.5
9948 14:46:18.280659 Ending use of test pattern.
9949 14:46:18.280722 Ending test lava.1_kselftest-alsa (14166990_1.6.2.3.5), duration 36.89
9951 14:46:18.283276 <LAVA_TEST_RUNNER EXIT>
9952 14:46:18.283533 ok: lava_test_shell seems to have completed
9953 14:46:18.286888 alsa_mixer-test: pass
alsa_mixer-test_event_missing_0_0: fail
alsa_mixer-test_event_missing_0_1: fail
alsa_mixer-test_event_missing_0_10: pass
alsa_mixer-test_event_missing_0_11: pass
alsa_mixer-test_event_missing_0_12: pass
alsa_mixer-test_event_missing_0_13: pass
alsa_mixer-test_event_missing_0_14: pass
alsa_mixer-test_event_missing_0_15: pass
alsa_mixer-test_event_missing_0_16: pass
alsa_mixer-test_event_missing_0_17: pass
alsa_mixer-test_event_missing_0_18: pass
alsa_mixer-test_event_missing_0_19: pass
alsa_mixer-test_event_missing_0_2: fail
alsa_mixer-test_event_missing_0_20: pass
alsa_mixer-test_event_missing_0_21: pass
alsa_mixer-test_event_missing_0_22: pass
alsa_mixer-test_event_missing_0_23: pass
alsa_mixer-test_event_missing_0_24: pass
alsa_mixer-test_event_missing_0_25: pass
alsa_mixer-test_event_missing_0_26: pass
alsa_mixer-test_event_missing_0_27: pass
alsa_mixer-test_event_missing_0_28: pass
alsa_mixer-test_event_missing_0_29: pass
alsa_mixer-test_event_missing_0_3: fail
alsa_mixer-test_event_missing_0_30: pass
alsa_mixer-test_event_missing_0_31: pass
alsa_mixer-test_event_missing_0_32: pass
alsa_mixer-test_event_missing_0_33: pass
alsa_mixer-test_event_missing_0_34: pass
alsa_mixer-test_event_missing_0_35: pass
alsa_mixer-test_event_missing_0_36: pass
alsa_mixer-test_event_missing_0_37: pass
alsa_mixer-test_event_missing_0_38: pass
alsa_mixer-test_event_missing_0_39: pass
alsa_mixer-test_event_missing_0_4: fail
alsa_mixer-test_event_missing_0_40: pass
alsa_mixer-test_event_missing_0_41: pass
alsa_mixer-test_event_missing_0_42: pass
alsa_mixer-test_event_missing_0_43: pass
alsa_mixer-test_event_missing_0_44: pass
alsa_mixer-test_event_missing_0_45: pass
alsa_mixer-test_event_missing_0_46: pass
alsa_mixer-test_event_missing_0_47: pass
alsa_mixer-test_event_missing_0_48: pass
alsa_mixer-test_event_missing_0_49: pass
alsa_mixer-test_event_missing_0_5: fail
alsa_mixer-test_event_missing_0_50: pass
alsa_mixer-test_event_missing_0_51: pass
alsa_mixer-test_event_missing_0_52: pass
alsa_mixer-test_event_missing_0_53: pass
alsa_mixer-test_event_missing_0_54: pass
alsa_mixer-test_event_missing_0_55: pass
alsa_mixer-test_event_missing_0_56: pass
alsa_mixer-test_event_missing_0_57: pass
alsa_mixer-test_event_missing_0_58: pass
alsa_mixer-test_event_missing_0_59: pass
alsa_mixer-test_event_missing_0_6: pass
alsa_mixer-test_event_missing_0_60: pass
alsa_mixer-test_event_missing_0_61: pass
alsa_mixer-test_event_missing_0_62: pass
alsa_mixer-test_event_missing_0_63: pass
alsa_mixer-test_event_missing_0_64: pass
alsa_mixer-test_event_missing_0_65: pass
alsa_mixer-test_event_missing_0_66: pass
alsa_mixer-test_event_missing_0_67: pass
alsa_mixer-test_event_missing_0_68: pass
alsa_mixer-test_event_missing_0_69: pass
alsa_mixer-test_event_missing_0_7: pass
alsa_mixer-test_event_missing_0_70: pass
alsa_mixer-test_event_missing_0_71: pass
alsa_mixer-test_event_missing_0_72: pass
alsa_mixer-test_event_missing_0_73: pass
alsa_mixer-test_event_missing_0_74: pass
alsa_mixer-test_event_missing_0_75: pass
alsa_mixer-test_event_missing_0_76: pass
alsa_mixer-test_event_missing_0_77: pass
alsa_mixer-test_event_missing_0_78: pass
alsa_mixer-test_event_missing_0_79: pass
alsa_mixer-test_event_missing_0_8: pass
alsa_mixer-test_event_missing_0_80: pass
alsa_mixer-test_event_missing_0_81: fail
alsa_mixer-test_event_missing_0_82: pass
alsa_mixer-test_event_missing_0_83: pass
alsa_mixer-test_event_missing_0_84: pass
alsa_mixer-test_event_missing_0_85: pass
alsa_mixer-test_event_missing_0_86: pass
alsa_mixer-test_event_missing_0_87: pass
alsa_mixer-test_event_missing_0_88: pass
alsa_mixer-test_event_missing_0_89: pass
alsa_mixer-test_event_missing_0_9: pass
alsa_mixer-test_event_missing_0_90: pass
alsa_mixer-test_event_missing_0_91: pass
alsa_mixer-test_event_missing_0_92: pass
alsa_mixer-test_event_missing_0_93: pass
alsa_mixer-test_event_spurious_0_0: pass
alsa_mixer-test_event_spurious_0_1: pass
alsa_mixer-test_event_spurious_0_10: pass
alsa_mixer-test_event_spurious_0_11: pass
alsa_mixer-test_event_spurious_0_12: pass
alsa_mixer-test_event_spurious_0_13: pass
alsa_mixer-test_event_spurious_0_14: pass
alsa_mixer-test_event_spurious_0_15: pass
alsa_mixer-test_event_spurious_0_16: pass
alsa_mixer-test_event_spurious_0_17: pass
alsa_mixer-test_event_spurious_0_18: pass
alsa_mixer-test_event_spurious_0_19: pass
alsa_mixer-test_event_spurious_0_2: pass
alsa_mixer-test_event_spurious_0_20: pass
alsa_mixer-test_event_spurious_0_21: pass
alsa_mixer-test_event_spurious_0_22: pass
alsa_mixer-test_event_spurious_0_23: pass
alsa_mixer-test_event_spurious_0_24: pass
alsa_mixer-test_event_spurious_0_25: pass
alsa_mixer-test_event_spurious_0_26: pass
alsa_mixer-test_event_spurious_0_27: pass
alsa_mixer-test_event_spurious_0_28: pass
alsa_mixer-test_event_spurious_0_29: pass
alsa_mixer-test_event_spurious_0_3: pass
alsa_mixer-test_event_spurious_0_30: pass
alsa_mixer-test_event_spurious_0_31: pass
alsa_mixer-test_event_spurious_0_32: pass
alsa_mixer-test_event_spurious_0_33: pass
alsa_mixer-test_event_spurious_0_34: pass
alsa_mixer-test_event_spurious_0_35: pass
alsa_mixer-test_event_spurious_0_36: pass
alsa_mixer-test_event_spurious_0_37: pass
alsa_mixer-test_event_spurious_0_38: pass
alsa_mixer-test_event_spurious_0_39: pass
alsa_mixer-test_event_spurious_0_4: pass
alsa_mixer-test_event_spurious_0_40: pass
alsa_mixer-test_event_spurious_0_41: pass
alsa_mixer-test_event_spurious_0_42: pass
alsa_mixer-test_event_spurious_0_43: pass
alsa_mixer-test_event_spurious_0_44: pass
alsa_mixer-test_event_spurious_0_45: pass
alsa_mixer-test_event_spurious_0_46: pass
alsa_mixer-test_event_spurious_0_47: pass
alsa_mixer-test_event_spurious_0_48: pass
alsa_mixer-test_event_spurious_0_49: pass
alsa_mixer-test_event_spurious_0_5: pass
alsa_mixer-test_event_spurious_0_50: pass
alsa_mixer-test_event_spurious_0_51: pass
alsa_mixer-test_event_spurious_0_52: pass
alsa_mixer-test_event_spurious_0_53: pass
alsa_mixer-test_event_spurious_0_54: pass
alsa_mixer-test_event_spurious_0_55: pass
alsa_mixer-test_event_spurious_0_56: pass
alsa_mixer-test_event_spurious_0_57: pass
alsa_mixer-test_event_spurious_0_58: pass
alsa_mixer-test_event_spurious_0_59: pass
alsa_mixer-test_event_spurious_0_6: pass
alsa_mixer-test_event_spurious_0_60: pass
alsa_mixer-test_event_spurious_0_61: pass
alsa_mixer-test_event_spurious_0_62: pass
alsa_mixer-test_event_spurious_0_63: pass
alsa_mixer-test_event_spurious_0_64: pass
alsa_mixer-test_event_spurious_0_65: pass
alsa_mixer-test_event_spurious_0_66: pass
alsa_mixer-test_event_spurious_0_67: pass
alsa_mixer-test_event_spurious_0_68: pass
alsa_mixer-test_event_spurious_0_69: pass
alsa_mixer-test_event_spurious_0_7: pass
alsa_mixer-test_event_spurious_0_70: pass
alsa_mixer-test_event_spurious_0_71: pass
alsa_mixer-test_event_spurious_0_72: pass
alsa_mixer-test_event_spurious_0_73: pass
alsa_mixer-test_event_spurious_0_74: pass
alsa_mixer-test_event_spurious_0_75: pass
alsa_mixer-test_event_spurious_0_76: pass
alsa_mixer-test_event_spurious_0_77: pass
alsa_mixer-test_event_spurious_0_78: pass
alsa_mixer-test_event_spurious_0_79: pass
alsa_mixer-test_event_spurious_0_8: pass
alsa_mixer-test_event_spurious_0_80: pass
alsa_mixer-test_event_spurious_0_81: pass
alsa_mixer-test_event_spurious_0_82: pass
alsa_mixer-test_event_spurious_0_83: pass
alsa_mixer-test_event_spurious_0_84: pass
alsa_mixer-test_event_spurious_0_85: pass
alsa_mixer-test_event_spurious_0_86: pass
alsa_mixer-test_event_spurious_0_87: pass
alsa_mixer-test_event_spurious_0_88: fail
alsa_mixer-test_event_spurious_0_89: pass
alsa_mixer-test_event_spurious_0_9: pass
alsa_mixer-test_event_spurious_0_90: pass
alsa_mixer-test_event_spurious_0_91: pass
alsa_mixer-test_event_spurious_0_92: pass
alsa_mixer-test_event_spurious_0_93: pass
alsa_mixer-test_get_value_0_0: pass
alsa_mixer-test_get_value_0_1: pass
alsa_mixer-test_get_value_0_10: pass
alsa_mixer-test_get_value_0_11: pass
alsa_mixer-test_get_value_0_12: pass
alsa_mixer-test_get_value_0_13: pass
alsa_mixer-test_get_value_0_14: pass
alsa_mixer-test_get_value_0_15: pass
alsa_mixer-test_get_value_0_16: pass
alsa_mixer-test_get_value_0_17: pass
alsa_mixer-test_get_value_0_18: pass
alsa_mixer-test_get_value_0_19: pass
alsa_mixer-test_get_value_0_2: pass
alsa_mixer-test_get_value_0_20: pass
alsa_mixer-test_get_value_0_21: pass
alsa_mixer-test_get_value_0_22: pass
alsa_mixer-test_get_value_0_23: pass
alsa_mixer-test_get_value_0_24: pass
alsa_mixer-test_get_value_0_25: pass
alsa_mixer-test_get_value_0_26: pass
alsa_mixer-test_get_value_0_27: pass
alsa_mixer-test_get_value_0_28: pass
alsa_mixer-test_get_value_0_29: pass
alsa_mixer-test_get_value_0_3: pass
alsa_mixer-test_get_value_0_30: pass
alsa_mixer-test_get_value_0_31: pass
alsa_mixer-test_get_value_0_32: pass
alsa_mixer-test_get_value_0_33: pass
alsa_mixer-test_get_value_0_34: pass
alsa_mixer-test_get_value_0_35: pass
alsa_mixer-test_get_value_0_36: pass
alsa_mixer-test_get_value_0_37: pass
alsa_mixer-test_get_value_0_38: pass
alsa_mixer-test_get_value_0_39: pass
alsa_mixer-test_get_value_0_4: pass
alsa_mixer-test_get_value_0_40: pass
alsa_mixer-test_get_value_0_41: pass
alsa_mixer-test_get_value_0_42: pass
alsa_mixer-test_get_value_0_43: pass
alsa_mixer-test_get_value_0_44: pass
alsa_mixer-test_get_value_0_45: pass
alsa_mixer-test_get_value_0_46: pass
alsa_mixer-test_get_value_0_47: pass
alsa_mixer-test_get_value_0_48: pass
alsa_mixer-test_get_value_0_49: pass
alsa_mixer-test_get_value_0_5: pass
alsa_mixer-test_get_value_0_50: pass
alsa_mixer-test_get_value_0_51: pass
alsa_mixer-test_get_value_0_52: pass
alsa_mixer-test_get_value_0_53: pass
alsa_mixer-test_get_value_0_54: pass
alsa_mixer-test_get_value_0_55: pass
alsa_mixer-test_get_value_0_56: pass
alsa_mixer-test_get_value_0_57: pass
alsa_mixer-test_get_value_0_58: pass
alsa_mixer-test_get_value_0_59: pass
alsa_mixer-test_get_value_0_6: pass
alsa_mixer-test_get_value_0_60: pass
alsa_mixer-test_get_value_0_61: pass
alsa_mixer-test_get_value_0_62: pass
alsa_mixer-test_get_value_0_63: pass
alsa_mixer-test_get_value_0_64: pass
alsa_mixer-test_get_value_0_65: pass
alsa_mixer-test_get_value_0_66: pass
alsa_mixer-test_get_value_0_67: pass
alsa_mixer-test_get_value_0_68: pass
alsa_mixer-test_get_value_0_69: pass
alsa_mixer-test_get_value_0_7: pass
alsa_mixer-test_get_value_0_70: pass
alsa_mixer-test_get_value_0_71: pass
alsa_mixer-test_get_value_0_72: pass
alsa_mixer-test_get_value_0_73: pass
alsa_mixer-test_get_value_0_74: pass
alsa_mixer-test_get_value_0_75: pass
alsa_mixer-test_get_value_0_76: pass
alsa_mixer-test_get_value_0_77: fail
alsa_mixer-test_get_value_0_78: fail
alsa_mixer-test_get_value_0_79: fail
alsa_mixer-test_get_value_0_8: pass
alsa_mixer-test_get_value_0_80: pass
alsa_mixer-test_get_value_0_81: pass
alsa_mixer-test_get_value_0_82: pass
alsa_mixer-test_get_value_0_83: pass
alsa_mixer-test_get_value_0_84: pass
alsa_mixer-test_get_value_0_85: pass
alsa_mixer-test_get_value_0_86: pass
alsa_mixer-test_get_value_0_87: pass
alsa_mixer-test_get_value_0_88: pass
alsa_mixer-test_get_value_0_89: pass
alsa_mixer-test_get_value_0_9: pass
alsa_mixer-test_get_value_0_90: pass
alsa_mixer-test_get_value_0_91: pass
alsa_mixer-test_get_value_0_92: pass
alsa_mixer-test_get_value_0_93: pass
alsa_mixer-test_name_0_0: pass
alsa_mixer-test_name_0_1: pass
alsa_mixer-test_name_0_10: fail
alsa_mixer-test_name_0_11: fail
alsa_mixer-test_name_0_12: fail
alsa_mixer-test_name_0_13: fail
alsa_mixer-test_name_0_14: fail
alsa_mixer-test_name_0_15: fail
alsa_mixer-test_name_0_16: fail
alsa_mixer-test_name_0_17: fail
alsa_mixer-test_name_0_18: fail
alsa_mixer-test_name_0_19: fail
alsa_mixer-test_name_0_2: pass
alsa_mixer-test_name_0_20: fail
alsa_mixer-test_name_0_21: fail
alsa_mixer-test_name_0_22: pass
alsa_mixer-test_name_0_23: pass
alsa_mixer-test_name_0_24: pass
alsa_mixer-test_name_0_25: pass
alsa_mixer-test_name_0_26: pass
alsa_mixer-test_name_0_27: pass
alsa_mixer-test_name_0_28: pass
alsa_mixer-test_name_0_29: pass
alsa_mixer-test_name_0_3: pass
alsa_mixer-test_name_0_30: fail
alsa_mixer-test_name_0_31: fail
alsa_mixer-test_name_0_32: fail
alsa_mixer-test_name_0_33: fail
alsa_mixer-test_name_0_34: fail
alsa_mixer-test_name_0_35: fail
alsa_mixer-test_name_0_36: fail
alsa_mixer-test_name_0_37: fail
alsa_mixer-test_name_0_38: fail
alsa_mixer-test_name_0_39: fail
alsa_mixer-test_name_0_4: pass
alsa_mixer-test_name_0_40: fail
alsa_mixer-test_name_0_41: fail
alsa_mixer-test_name_0_42: fail
alsa_mixer-test_name_0_43: fail
alsa_mixer-test_name_0_44: fail
alsa_mixer-test_name_0_45: fail
alsa_mixer-test_name_0_46: fail
alsa_mixer-test_name_0_47: fail
alsa_mixer-test_name_0_48: fail
alsa_mixer-test_name_0_49: fail
alsa_mixer-test_name_0_5: pass
alsa_mixer-test_name_0_50: fail
alsa_mixer-test_name_0_51: fail
alsa_mixer-test_name_0_52: fail
alsa_mixer-test_name_0_53: fail
alsa_mixer-test_name_0_54: fail
alsa_mixer-test_name_0_55: fail
alsa_mixer-test_name_0_56: fail
alsa_mixer-test_name_0_57: fail
alsa_mixer-test_name_0_58: fail
alsa_mixer-test_name_0_59: fail
alsa_mixer-test_name_0_6: fail
alsa_mixer-test_name_0_60: fail
alsa_mixer-test_name_0_61: fail
alsa_mixer-test_name_0_62: fail
alsa_mixer-test_name_0_63: fail
alsa_mixer-test_name_0_64: fail
alsa_mixer-test_name_0_65: fail
alsa_mixer-test_name_0_66: fail
alsa_mixer-test_name_0_67: fail
alsa_mixer-test_name_0_68: fail
alsa_mixer-test_name_0_69: fail
alsa_mixer-test_name_0_7: fail
alsa_mixer-test_name_0_70: fail
alsa_mixer-test_name_0_71: fail
alsa_mixer-test_name_0_72: fail
alsa_mixer-test_name_0_73: fail
alsa_mixer-test_name_0_74: fail
alsa_mixer-test_name_0_75: fail
alsa_mixer-test_name_0_76: fail
alsa_mixer-test_name_0_77: pass
alsa_mixer-test_name_0_78: pass
alsa_mixer-test_name_0_79: pass
alsa_mixer-test_name_0_8: fail
alsa_mixer-test_name_0_80: pass
alsa_mixer-test_name_0_81: pass
alsa_mixer-test_name_0_82: pass
alsa_mixer-test_name_0_83: pass
alsa_mixer-test_name_0_84: pass
alsa_mixer-test_name_0_85: pass
alsa_mixer-test_name_0_86: pass
alsa_mixer-test_name_0_87: pass
alsa_mixer-test_name_0_88: pass
alsa_mixer-test_name_0_89: pass
alsa_mixer-test_name_0_9: fail
alsa_mixer-test_name_0_90: pass
alsa_mixer-test_name_0_91: pass
alsa_mixer-test_name_0_92: pass
alsa_mixer-test_name_0_93: pass
alsa_mixer-test_write_default_0_0: pass
alsa_mixer-test_write_default_0_1: pass
alsa_mixer-test_write_default_0_10: pass
alsa_mixer-test_write_default_0_11: pass
alsa_mixer-test_write_default_0_12: pass
alsa_mixer-test_write_default_0_13: pass
alsa_mixer-test_write_default_0_14: pass
alsa_mixer-test_write_default_0_15: pass
alsa_mixer-test_write_default_0_16: pass
alsa_mixer-test_write_default_0_17: pass
alsa_mixer-test_write_default_0_18: pass
alsa_mixer-test_write_default_0_19: pass
alsa_mixer-test_write_default_0_2: pass
alsa_mixer-test_write_default_0_20: pass
alsa_mixer-test_write_default_0_21: pass
alsa_mixer-test_write_default_0_22: pass
alsa_mixer-test_write_default_0_23: pass
alsa_mixer-test_write_default_0_24: pass
alsa_mixer-test_write_default_0_25: pass
alsa_mixer-test_write_default_0_26: pass
alsa_mixer-test_write_default_0_27: pass
alsa_mixer-test_write_default_0_28: pass
alsa_mixer-test_write_default_0_29: pass
alsa_mixer-test_write_default_0_3: pass
alsa_mixer-test_write_default_0_30: pass
alsa_mixer-test_write_default_0_31: pass
alsa_mixer-test_write_default_0_32: pass
alsa_mixer-test_write_default_0_33: pass
alsa_mixer-test_write_default_0_34: pass
alsa_mixer-test_write_default_0_35: pass
alsa_mixer-test_write_default_0_36: pass
alsa_mixer-test_write_default_0_37: pass
alsa_mixer-test_write_default_0_38: pass
alsa_mixer-test_write_default_0_39: pass
alsa_mixer-test_write_default_0_4: pass
alsa_mixer-test_write_default_0_40: pass
alsa_mixer-test_write_default_0_41: pass
alsa_mixer-test_write_default_0_42: pass
alsa_mixer-test_write_default_0_43: pass
alsa_mixer-test_write_default_0_44: pass
alsa_mixer-test_write_default_0_45: pass
alsa_mixer-test_write_default_0_46: pass
alsa_mixer-test_write_default_0_47: pass
alsa_mixer-test_write_default_0_48: pass
alsa_mixer-test_write_default_0_49: pass
alsa_mixer-test_write_default_0_5: pass
alsa_mixer-test_write_default_0_50: pass
alsa_mixer-test_write_default_0_51: pass
alsa_mixer-test_write_default_0_52: pass
alsa_mixer-test_write_default_0_53: pass
alsa_mixer-test_write_default_0_54: pass
alsa_mixer-test_write_default_0_55: pass
alsa_mixer-test_write_default_0_56: pass
alsa_mixer-test_write_default_0_57: pass
alsa_mixer-test_write_default_0_58: pass
alsa_mixer-test_write_default_0_59: pass
alsa_mixer-test_write_default_0_6: pass
alsa_mixer-test_write_default_0_60: pass
alsa_mixer-test_write_default_0_61: pass
alsa_mixer-test_write_default_0_62: pass
alsa_mixer-test_write_default_0_63: pass
alsa_mixer-test_write_default_0_64: pass
alsa_mixer-test_write_default_0_65: pass
alsa_mixer-test_write_default_0_66: pass
alsa_mixer-test_write_default_0_67: pass
alsa_mixer-test_write_default_0_68: pass
alsa_mixer-test_write_default_0_69: pass
alsa_mixer-test_write_default_0_7: pass
alsa_mixer-test_write_default_0_70: pass
alsa_mixer-test_write_default_0_71: pass
alsa_mixer-test_write_default_0_72: pass
alsa_mixer-test_write_default_0_73: pass
alsa_mixer-test_write_default_0_74: pass
alsa_mixer-test_write_default_0_75: pass
alsa_mixer-test_write_default_0_76: pass
alsa_mixer-test_write_default_0_77: fail
alsa_mixer-test_write_default_0_78: fail
alsa_mixer-test_write_default_0_79: fail
alsa_mixer-test_write_default_0_8: pass
alsa_mixer-test_write_default_0_80: pass
alsa_mixer-test_write_default_0_81: pass
alsa_mixer-test_write_default_0_82: skip
alsa_mixer-test_write_default_0_83: pass
alsa_mixer-test_write_default_0_84: pass
alsa_mixer-test_write_default_0_85: pass
alsa_mixer-test_write_default_0_86: pass
alsa_mixer-test_write_default_0_87: pass
alsa_mixer-test_write_default_0_88: pass
alsa_mixer-test_write_default_0_89: pass
alsa_mixer-test_write_default_0_9: pass
alsa_mixer-test_write_default_0_90: pass
alsa_mixer-test_write_default_0_91: pass
alsa_mixer-test_write_default_0_92: pass
alsa_mixer-test_write_default_0_93: pass
alsa_mixer-test_write_invalid_0_0: pass
alsa_mixer-test_write_invalid_0_1: pass
alsa_mixer-test_write_invalid_0_10: pass
alsa_mixer-test_write_invalid_0_11: pass
alsa_mixer-test_write_invalid_0_12: pass
alsa_mixer-test_write_invalid_0_13: pass
alsa_mixer-test_write_invalid_0_14: pass
alsa_mixer-test_write_invalid_0_15: pass
alsa_mixer-test_write_invalid_0_16: pass
alsa_mixer-test_write_invalid_0_17: pass
alsa_mixer-test_write_invalid_0_18: pass
alsa_mixer-test_write_invalid_0_19: pass
alsa_mixer-test_write_invalid_0_2: pass
alsa_mixer-test_write_invalid_0_20: pass
alsa_mixer-test_write_invalid_0_21: pass
alsa_mixer-test_write_invalid_0_22: pass
alsa_mixer-test_write_invalid_0_23: pass
alsa_mixer-test_write_invalid_0_24: pass
alsa_mixer-test_write_invalid_0_25: pass
alsa_mixer-test_write_invalid_0_26: pass
alsa_mixer-test_write_invalid_0_27: pass
alsa_mixer-test_write_invalid_0_28: pass
alsa_mixer-test_write_invalid_0_29: pass
alsa_mixer-test_write_invalid_0_3: pass
alsa_mixer-test_write_invalid_0_30: pass
alsa_mixer-test_write_invalid_0_31: pass
alsa_mixer-test_write_invalid_0_32: pass
alsa_mixer-test_write_invalid_0_33: pass
alsa_mixer-test_write_invalid_0_34: pass
alsa_mixer-test_write_invalid_0_35: pass
alsa_mixer-test_write_invalid_0_36: pass
alsa_mixer-test_write_invalid_0_37: pass
alsa_mixer-test_write_invalid_0_38: pass
alsa_mixer-test_write_invalid_0_39: pass
alsa_mixer-test_write_invalid_0_4: pass
alsa_mixer-test_write_invalid_0_40: pass
alsa_mixer-test_write_invalid_0_41: pass
alsa_mixer-test_write_invalid_0_42: pass
alsa_mixer-test_write_invalid_0_43: pass
alsa_mixer-test_write_invalid_0_44: pass
alsa_mixer-test_write_invalid_0_45: pass
alsa_mixer-test_write_invalid_0_46: pass
alsa_mixer-test_write_invalid_0_47: pass
alsa_mixer-test_write_invalid_0_48: pass
alsa_mixer-test_write_invalid_0_49: pass
alsa_mixer-test_write_invalid_0_5: pass
alsa_mixer-test_write_invalid_0_50: pass
alsa_mixer-test_write_invalid_0_51: pass
alsa_mixer-test_write_invalid_0_52: pass
alsa_mixer-test_write_invalid_0_53: pass
alsa_mixer-test_write_invalid_0_54: pass
alsa_mixer-test_write_invalid_0_55: pass
alsa_mixer-test_write_invalid_0_56: pass
alsa_mixer-test_write_invalid_0_57: pass
alsa_mixer-test_write_invalid_0_58: pass
alsa_mixer-test_write_invalid_0_59: pass
alsa_mixer-test_write_invalid_0_6: pass
alsa_mixer-test_write_invalid_0_60: pass
alsa_mixer-test_write_invalid_0_61: pass
alsa_mixer-test_write_invalid_0_62: pass
alsa_mixer-test_write_invalid_0_63: pass
alsa_mixer-test_write_invalid_0_64: pass
alsa_mixer-test_write_invalid_0_65: pass
alsa_mixer-test_write_invalid_0_66: pass
alsa_mixer-test_write_invalid_0_67: pass
alsa_mixer-test_write_invalid_0_68: pass
alsa_mixer-test_write_invalid_0_69: pass
alsa_mixer-test_write_invalid_0_7: pass
alsa_mixer-test_write_invalid_0_70: pass
alsa_mixer-test_write_invalid_0_71: pass
alsa_mixer-test_write_invalid_0_72: pass
alsa_mixer-test_write_invalid_0_73: pass
alsa_mixer-test_write_invalid_0_74: pass
alsa_mixer-test_write_invalid_0_75: pass
alsa_mixer-test_write_invalid_0_76: pass
alsa_mixer-test_write_invalid_0_77: fail
alsa_mixer-test_write_invalid_0_78: fail
alsa_mixer-test_write_invalid_0_79: fail
alsa_mixer-test_write_invalid_0_8: pass
alsa_mixer-test_write_invalid_0_80: pass
alsa_mixer-test_write_invalid_0_81: fail
alsa_mixer-test_write_invalid_0_82: skip
alsa_mixer-test_write_invalid_0_83: pass
alsa_mixer-test_write_invalid_0_84: pass
alsa_mixer-test_write_invalid_0_85: pass
alsa_mixer-test_write_invalid_0_86: pass
alsa_mixer-test_write_invalid_0_87: pass
alsa_mixer-test_write_invalid_0_88: pass
alsa_mixer-test_write_invalid_0_89: pass
alsa_mixer-test_write_invalid_0_9: pass
alsa_mixer-test_write_invalid_0_90: pass
alsa_mixer-test_write_invalid_0_91: pass
alsa_mixer-test_write_invalid_0_92: pass
alsa_mixer-test_write_invalid_0_93: pass
alsa_mixer-test_write_valid_0_0: pass
alsa_mixer-test_write_valid_0_1: pass
alsa_mixer-test_write_valid_0_10: pass
alsa_mixer-test_write_valid_0_11: pass
alsa_mixer-test_write_valid_0_12: pass
alsa_mixer-test_write_valid_0_13: pass
alsa_mixer-test_write_valid_0_14: pass
alsa_mixer-test_write_valid_0_15: pass
alsa_mixer-test_write_valid_0_16: pass
alsa_mixer-test_write_valid_0_17: pass
alsa_mixer-test_write_valid_0_18: pass
alsa_mixer-test_write_valid_0_19: pass
alsa_mixer-test_write_valid_0_2: pass
alsa_mixer-test_write_valid_0_20: pass
alsa_mixer-test_write_valid_0_21: pass
alsa_mixer-test_write_valid_0_22: pass
alsa_mixer-test_write_valid_0_23: pass
alsa_mixer-test_write_valid_0_24: pass
alsa_mixer-test_write_valid_0_25: pass
alsa_mixer-test_write_valid_0_26: pass
alsa_mixer-test_write_valid_0_27: pass
alsa_mixer-test_write_valid_0_28: pass
alsa_mixer-test_write_valid_0_29: pass
alsa_mixer-test_write_valid_0_3: pass
alsa_mixer-test_write_valid_0_30: pass
alsa_mixer-test_write_valid_0_31: pass
alsa_mixer-test_write_valid_0_32: pass
alsa_mixer-test_write_valid_0_33: pass
alsa_mixer-test_write_valid_0_34: pass
alsa_mixer-test_write_valid_0_35: pass
alsa_mixer-test_write_valid_0_36: pass
alsa_mixer-test_write_valid_0_37: pass
alsa_mixer-test_write_valid_0_38: pass
alsa_mixer-test_write_valid_0_39: pass
alsa_mixer-test_write_valid_0_4: pass
alsa_mixer-test_write_valid_0_40: pass
alsa_mixer-test_write_valid_0_41: pass
alsa_mixer-test_write_valid_0_42: pass
alsa_mixer-test_write_valid_0_43: pass
alsa_mixer-test_write_valid_0_44: pass
alsa_mixer-test_write_valid_0_45: pass
alsa_mixer-test_write_valid_0_46: pass
alsa_mixer-test_write_valid_0_47: pass
alsa_mixer-test_write_valid_0_48: pass
alsa_mixer-test_write_valid_0_49: pass
alsa_mixer-test_write_valid_0_5: pass
alsa_mixer-test_write_valid_0_50: pass
alsa_mixer-test_write_valid_0_51: pass
alsa_mixer-test_write_valid_0_52: pass
alsa_mixer-test_write_valid_0_53: pass
alsa_mixer-test_write_valid_0_54: pass
alsa_mixer-test_write_valid_0_55: pass
alsa_mixer-test_write_valid_0_56: pass
alsa_mixer-test_write_valid_0_57: pass
alsa_mixer-test_write_valid_0_58: pass
alsa_mixer-test_write_valid_0_59: pass
alsa_mixer-test_write_valid_0_6: pass
alsa_mixer-test_write_valid_0_60: pass
alsa_mixer-test_write_valid_0_61: pass
alsa_mixer-test_write_valid_0_62: pass
alsa_mixer-test_write_valid_0_63: pass
alsa_mixer-test_write_valid_0_64: pass
alsa_mixer-test_write_valid_0_65: pass
alsa_mixer-test_write_valid_0_66: pass
alsa_mixer-test_write_valid_0_67: pass
alsa_mixer-test_write_valid_0_68: pass
alsa_mixer-test_write_valid_0_69: pass
alsa_mixer-test_write_valid_0_7: pass
alsa_mixer-test_write_valid_0_70: pass
alsa_mixer-test_write_valid_0_71: pass
alsa_mixer-test_write_valid_0_72: pass
alsa_mixer-test_write_valid_0_73: pass
alsa_mixer-test_write_valid_0_74: pass
alsa_mixer-test_write_valid_0_75: pass
alsa_mixer-test_write_valid_0_76: pass
alsa_mixer-test_write_valid_0_77: fail
alsa_mixer-test_write_valid_0_78: fail
alsa_mixer-test_write_valid_0_79: fail
alsa_mixer-test_write_valid_0_8: pass
alsa_mixer-test_write_valid_0_80: pass
alsa_mixer-test_write_valid_0_81: pass
alsa_mixer-test_write_valid_0_82: skip
alsa_mixer-test_write_valid_0_83: pass
alsa_mixer-test_write_valid_0_84: pass
alsa_mixer-test_write_valid_0_85: fail
alsa_mixer-test_write_valid_0_86: fail
alsa_mixer-test_write_valid_0_87: pass
alsa_mixer-test_write_valid_0_88: fail
alsa_mixer-test_write_valid_0_89: pass
alsa_mixer-test_write_valid_0_9: pass
alsa_mixer-test_write_valid_0_90: pass
alsa_mixer-test_write_valid_0_91: pass
alsa_mixer-test_write_valid_0_92: pass
alsa_mixer-test_write_valid_0_93: pass
shardfile-alsa: pass
9954 14:46:18.287217 end: 3.1 lava-test-shell (duration 00:00:38) [common]
9955 14:46:18.287308 end: 3 lava-test-retry (duration 00:00:38) [common]
9956 14:46:18.287399 start: 4 finalize (timeout 00:07:30) [common]
9957 14:46:18.287488 start: 4.1 power-off (timeout 00:00:30) [common]
9958 14:46:18.287646 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-3', '--port=1', '--command=off']
9959 14:46:19.745109 >> Command sent successfully.
9960 14:46:19.747476 Returned 0 in 1 seconds
9961 14:46:19.847924 end: 4.1 power-off (duration 00:00:02) [common]
9963 14:46:19.848266 start: 4.2 read-feedback (timeout 00:07:28) [common]
9964 14:46:19.848571 Listened to connection for namespace 'common' for up to 1s
9965 14:46:20.849380 Finalising connection for namespace 'common'
9966 14:46:20.849561 Disconnecting from shell: Finalise
9967 14:46:20.849636 / #
9968 14:46:20.949981 end: 4.2 read-feedback (duration 00:00:01) [common]
9969 14:46:20.950163 end: 4 finalize (duration 00:00:03) [common]
9970 14:46:20.950284 Cleaning after the job
9971 14:46:20.950387 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166990/tftp-deploy-muq91wc3/ramdisk
9972 14:46:20.952589 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166990/tftp-deploy-muq91wc3/kernel
9973 14:46:20.963637 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166990/tftp-deploy-muq91wc3/dtb
9974 14:46:20.963879 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166990/tftp-deploy-muq91wc3/nfsrootfs
9975 14:46:21.027514 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166990/tftp-deploy-muq91wc3/modules
9976 14:46:21.033414 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14166990
9977 14:46:21.653594 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14166990
9978 14:46:21.653785 Job finished correctly