Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 35
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 14:46:14.680316 lava-dispatcher, installed at version: 2024.03
2 14:46:14.680524 start: 0 validate
3 14:46:14.680664 Start time: 2024-06-04 14:46:14.680657+00:00 (UTC)
4 14:46:14.680785 Using caching service: 'http://localhost/cache/?uri=%s'
5 14:46:14.680915 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 14:46:14.945249 Using caching service: 'http://localhost/cache/?uri=%s'
7 14:46:14.946076 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 14:46:15.207771 Using caching service: 'http://localhost/cache/?uri=%s'
9 14:46:15.208731 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 14:46:15.469972 Using caching service: 'http://localhost/cache/?uri=%s'
11 14:46:15.470643 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 14:46:15.734392 Using caching service: 'http://localhost/cache/?uri=%s'
13 14:46:15.735184 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 14:46:16.002209 validate duration: 1.32
16 14:46:16.002490 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 14:46:16.002594 start: 1.1 download-retry (timeout 00:10:00) [common]
18 14:46:16.002678 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 14:46:16.002807 Not decompressing ramdisk as can be used compressed.
20 14:46:16.002890 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 14:46:16.002952 saving as /var/lib/lava/dispatcher/tmp/14167017/tftp-deploy-lmyx8m5s/ramdisk/initrd.cpio.gz
22 14:46:16.003014 total size: 5628169 (5 MB)
23 14:46:16.004196 progress 0 % (0 MB)
24 14:46:16.005795 progress 5 % (0 MB)
25 14:46:16.007353 progress 10 % (0 MB)
26 14:46:16.008769 progress 15 % (0 MB)
27 14:46:16.010362 progress 20 % (1 MB)
28 14:46:16.011745 progress 25 % (1 MB)
29 14:46:16.013276 progress 30 % (1 MB)
30 14:46:16.014827 progress 35 % (1 MB)
31 14:46:16.016208 progress 40 % (2 MB)
32 14:46:16.017783 progress 45 % (2 MB)
33 14:46:16.019129 progress 50 % (2 MB)
34 14:46:16.020628 progress 55 % (2 MB)
35 14:46:16.022210 progress 60 % (3 MB)
36 14:46:16.023596 progress 65 % (3 MB)
37 14:46:16.025112 progress 70 % (3 MB)
38 14:46:16.026507 progress 75 % (4 MB)
39 14:46:16.028011 progress 80 % (4 MB)
40 14:46:16.029374 progress 85 % (4 MB)
41 14:46:16.030937 progress 90 % (4 MB)
42 14:46:16.032444 progress 95 % (5 MB)
43 14:46:16.033884 progress 100 % (5 MB)
44 14:46:16.034090 5 MB downloaded in 0.03 s (172.72 MB/s)
45 14:46:16.034242 end: 1.1.1 http-download (duration 00:00:00) [common]
47 14:46:16.034481 end: 1.1 download-retry (duration 00:00:00) [common]
48 14:46:16.034566 start: 1.2 download-retry (timeout 00:10:00) [common]
49 14:46:16.034647 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 14:46:16.034785 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 14:46:16.034857 saving as /var/lib/lava/dispatcher/tmp/14167017/tftp-deploy-lmyx8m5s/kernel/Image
52 14:46:16.034917 total size: 54682112 (52 MB)
53 14:46:16.034977 No compression specified
54 14:46:16.036091 progress 0 % (0 MB)
55 14:46:16.049865 progress 5 % (2 MB)
56 14:46:16.063666 progress 10 % (5 MB)
57 14:46:16.077733 progress 15 % (7 MB)
58 14:46:16.091389 progress 20 % (10 MB)
59 14:46:16.105188 progress 25 % (13 MB)
60 14:46:16.118973 progress 30 % (15 MB)
61 14:46:16.132784 progress 35 % (18 MB)
62 14:46:16.146654 progress 40 % (20 MB)
63 14:46:16.160664 progress 45 % (23 MB)
64 14:46:16.174592 progress 50 % (26 MB)
65 14:46:16.188422 progress 55 % (28 MB)
66 14:46:16.202237 progress 60 % (31 MB)
67 14:46:16.215749 progress 65 % (33 MB)
68 14:46:16.229727 progress 70 % (36 MB)
69 14:46:16.243379 progress 75 % (39 MB)
70 14:46:16.257284 progress 80 % (41 MB)
71 14:46:16.271184 progress 85 % (44 MB)
72 14:46:16.284837 progress 90 % (46 MB)
73 14:46:16.298656 progress 95 % (49 MB)
74 14:46:16.312068 progress 100 % (52 MB)
75 14:46:16.312318 52 MB downloaded in 0.28 s (187.99 MB/s)
76 14:46:16.312476 end: 1.2.1 http-download (duration 00:00:00) [common]
78 14:46:16.312706 end: 1.2 download-retry (duration 00:00:00) [common]
79 14:46:16.312792 start: 1.3 download-retry (timeout 00:10:00) [common]
80 14:46:16.312875 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 14:46:16.313009 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 14:46:16.313077 saving as /var/lib/lava/dispatcher/tmp/14167017/tftp-deploy-lmyx8m5s/dtb/mt8192-asurada-spherion-r0.dtb
83 14:46:16.313136 total size: 47258 (0 MB)
84 14:46:16.313196 No compression specified
85 14:46:16.314326 progress 69 % (0 MB)
86 14:46:16.314607 progress 100 % (0 MB)
87 14:46:16.314761 0 MB downloaded in 0.00 s (27.79 MB/s)
88 14:46:16.314881 end: 1.3.1 http-download (duration 00:00:00) [common]
90 14:46:16.315103 end: 1.3 download-retry (duration 00:00:00) [common]
91 14:46:16.315185 start: 1.4 download-retry (timeout 00:10:00) [common]
92 14:46:16.315264 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 14:46:16.315374 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 14:46:16.315441 saving as /var/lib/lava/dispatcher/tmp/14167017/tftp-deploy-lmyx8m5s/nfsrootfs/full.rootfs.tar
95 14:46:16.315500 total size: 120894716 (115 MB)
96 14:46:16.315558 Using unxz to decompress xz
97 14:46:16.319573 progress 0 % (0 MB)
98 14:46:16.669091 progress 5 % (5 MB)
99 14:46:17.039065 progress 10 % (11 MB)
100 14:46:17.401566 progress 15 % (17 MB)
101 14:46:17.740872 progress 20 % (23 MB)
102 14:46:18.040062 progress 25 % (28 MB)
103 14:46:18.395804 progress 30 % (34 MB)
104 14:46:18.730167 progress 35 % (40 MB)
105 14:46:18.894020 progress 40 % (46 MB)
106 14:46:19.070243 progress 45 % (51 MB)
107 14:46:19.376806 progress 50 % (57 MB)
108 14:46:19.748184 progress 55 % (63 MB)
109 14:46:20.087170 progress 60 % (69 MB)
110 14:46:20.422647 progress 65 % (74 MB)
111 14:46:20.764633 progress 70 % (80 MB)
112 14:46:21.117085 progress 75 % (86 MB)
113 14:46:21.453246 progress 80 % (92 MB)
114 14:46:21.790357 progress 85 % (98 MB)
115 14:46:22.147340 progress 90 % (103 MB)
116 14:46:22.469738 progress 95 % (109 MB)
117 14:46:22.820409 progress 100 % (115 MB)
118 14:46:22.825778 115 MB downloaded in 6.51 s (17.71 MB/s)
119 14:46:22.826062 end: 1.4.1 http-download (duration 00:00:07) [common]
121 14:46:22.826359 end: 1.4 download-retry (duration 00:00:07) [common]
122 14:46:22.826467 start: 1.5 download-retry (timeout 00:09:53) [common]
123 14:46:22.826570 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 14:46:22.826738 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 14:46:22.826814 saving as /var/lib/lava/dispatcher/tmp/14167017/tftp-deploy-lmyx8m5s/modules/modules.tar
126 14:46:22.826896 total size: 8608920 (8 MB)
127 14:46:22.827000 Using unxz to decompress xz
128 14:46:22.831507 progress 0 % (0 MB)
129 14:46:22.850365 progress 5 % (0 MB)
130 14:46:22.877278 progress 10 % (0 MB)
131 14:46:22.906746 progress 15 % (1 MB)
132 14:46:22.930489 progress 20 % (1 MB)
133 14:46:22.954167 progress 25 % (2 MB)
134 14:46:22.977856 progress 30 % (2 MB)
135 14:46:23.003627 progress 35 % (2 MB)
136 14:46:23.031235 progress 40 % (3 MB)
137 14:46:23.054864 progress 45 % (3 MB)
138 14:46:23.080184 progress 50 % (4 MB)
139 14:46:23.106734 progress 55 % (4 MB)
140 14:46:23.131778 progress 60 % (4 MB)
141 14:46:23.156487 progress 65 % (5 MB)
142 14:46:23.182023 progress 70 % (5 MB)
143 14:46:23.208079 progress 75 % (6 MB)
144 14:46:23.234602 progress 80 % (6 MB)
145 14:46:23.258919 progress 85 % (7 MB)
146 14:46:23.284276 progress 90 % (7 MB)
147 14:46:23.309527 progress 95 % (7 MB)
148 14:46:23.334294 progress 100 % (8 MB)
149 14:46:23.339749 8 MB downloaded in 0.51 s (16.01 MB/s)
150 14:46:23.340070 end: 1.5.1 http-download (duration 00:00:01) [common]
152 14:46:23.340467 end: 1.5 download-retry (duration 00:00:01) [common]
153 14:46:23.340598 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 14:46:23.340734 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 14:46:26.826761 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14167017/extract-nfsrootfs-oz49gv4g
156 14:46:26.826985 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 14:46:26.827129 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 14:46:26.827365 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0
159 14:46:26.827552 makedir: /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin
160 14:46:26.827699 makedir: /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/tests
161 14:46:26.827838 makedir: /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/results
162 14:46:26.827985 Creating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-add-keys
163 14:46:26.828191 Creating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-add-sources
164 14:46:26.828379 Creating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-background-process-start
165 14:46:26.828563 Creating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-background-process-stop
166 14:46:26.828697 Creating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-common-functions
167 14:46:26.828824 Creating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-echo-ipv4
168 14:46:26.828949 Creating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-install-packages
169 14:46:26.829073 Creating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-installed-packages
170 14:46:26.829195 Creating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-os-build
171 14:46:26.829455 Creating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-probe-channel
172 14:46:26.829583 Creating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-probe-ip
173 14:46:26.829706 Creating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-target-ip
174 14:46:26.829830 Creating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-target-mac
175 14:46:26.829953 Creating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-target-storage
176 14:46:26.830078 Creating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-test-case
177 14:46:26.830204 Creating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-test-event
178 14:46:26.830327 Creating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-test-feedback
179 14:46:26.830449 Creating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-test-raise
180 14:46:26.830571 Creating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-test-reference
181 14:46:26.830694 Creating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-test-runner
182 14:46:26.830815 Creating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-test-set
183 14:46:26.830938 Creating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-test-shell
184 14:46:26.831062 Updating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-add-keys (debian)
185 14:46:26.831211 Updating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-add-sources (debian)
186 14:46:26.831348 Updating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-install-packages (debian)
187 14:46:26.831483 Updating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-installed-packages (debian)
188 14:46:26.831617 Updating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/bin/lava-os-build (debian)
189 14:46:26.831734 Creating /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/environment
190 14:46:26.831828 LAVA metadata
191 14:46:26.831894 - LAVA_JOB_ID=14167017
192 14:46:26.831955 - LAVA_DISPATCHER_IP=192.168.201.1
193 14:46:26.832059 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 14:46:26.832125 skipped lava-vland-overlay
195 14:46:26.832199 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 14:46:26.832278 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 14:46:26.832338 skipped lava-multinode-overlay
198 14:46:26.832408 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 14:46:26.832483 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 14:46:26.832556 Loading test definitions
201 14:46:26.832644 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 14:46:26.832713 Using /lava-14167017 at stage 0
203 14:46:26.832990 uuid=14167017_1.6.2.3.1 testdef=None
204 14:46:26.833078 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 14:46:26.833160 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 14:46:26.833625 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 14:46:26.833841 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 14:46:26.834373 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 14:46:26.834598 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 14:46:26.835148 runner path: /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/0/tests/0_timesync-off test_uuid 14167017_1.6.2.3.1
213 14:46:26.835308 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 14:46:26.835534 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 14:46:26.835605 Using /lava-14167017 at stage 0
217 14:46:26.835700 Fetching tests from https://github.com/kernelci/test-definitions.git
218 14:46:26.835786 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/0/tests/1_kselftest-arm64'
219 14:46:29.456177 Running '/usr/bin/git checkout kernelci.org
220 14:46:29.603462 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 14:46:29.604204 uuid=14167017_1.6.2.3.5 testdef=None
222 14:46:29.604369 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 14:46:29.604615 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 14:46:29.605469 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 14:46:29.605704 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 14:46:29.606756 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 14:46:29.606995 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 14:46:29.607910 runner path: /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/0/tests/1_kselftest-arm64 test_uuid 14167017_1.6.2.3.5
232 14:46:29.608003 BOARD='mt8192-asurada-spherion-r0'
233 14:46:29.608066 BRANCH='cip'
234 14:46:29.608122 SKIPFILE='/dev/null'
235 14:46:29.608178 SKIP_INSTALL='True'
236 14:46:29.608282 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 14:46:29.608356 TST_CASENAME=''
238 14:46:29.608411 TST_CMDFILES='arm64'
239 14:46:29.608551 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 14:46:29.608758 Creating lava-test-runner.conf files
242 14:46:29.608822 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14167017/lava-overlay-2u_0pmt0/lava-14167017/0 for stage 0
243 14:46:29.608914 - 0_timesync-off
244 14:46:29.608983 - 1_kselftest-arm64
245 14:46:29.609076 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 14:46:29.609163 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 14:46:37.139976 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 14:46:37.140136 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 14:46:37.140225 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 14:46:37.140321 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 14:46:37.140411 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 14:46:37.303841 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 14:46:37.304234 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 14:46:37.304344 extracting modules file /var/lib/lava/dispatcher/tmp/14167017/tftp-deploy-lmyx8m5s/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14167017/extract-nfsrootfs-oz49gv4g
255 14:46:37.518565 extracting modules file /var/lib/lava/dispatcher/tmp/14167017/tftp-deploy-lmyx8m5s/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14167017/extract-overlay-ramdisk-f6g80rex/ramdisk
256 14:46:37.747884 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 14:46:37.748071 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 14:46:37.748168 [common] Applying overlay to NFS
259 14:46:37.748240 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14167017/compress-overlay-rdujlrth/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14167017/extract-nfsrootfs-oz49gv4g
260 14:46:38.655254 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 14:46:38.655421 start: 1.6.6 configure-preseed-file (timeout 00:09:37) [common]
262 14:46:38.655515 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 14:46:38.655599 start: 1.6.7 compress-ramdisk (timeout 00:09:37) [common]
264 14:46:38.655679 Building ramdisk /var/lib/lava/dispatcher/tmp/14167017/extract-overlay-ramdisk-f6g80rex/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14167017/extract-overlay-ramdisk-f6g80rex/ramdisk
265 14:46:39.008079 >> 130335 blocks
266 14:46:40.978639 rename /var/lib/lava/dispatcher/tmp/14167017/extract-overlay-ramdisk-f6g80rex/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14167017/tftp-deploy-lmyx8m5s/ramdisk/ramdisk.cpio.gz
267 14:46:40.979113 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 14:46:40.979285 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 14:46:40.979429 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 14:46:40.979581 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14167017/tftp-deploy-lmyx8m5s/kernel/Image']
271 14:46:53.947655 Returned 0 in 12 seconds
272 14:46:54.048321 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14167017/tftp-deploy-lmyx8m5s/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14167017/tftp-deploy-lmyx8m5s/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14167017/tftp-deploy-lmyx8m5s/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14167017/tftp-deploy-lmyx8m5s/kernel/image.itb
273 14:46:54.402752 output: FIT description: Kernel Image image with one or more FDT blobs
274 14:46:54.403145 output: Created: Tue Jun 4 15:46:54 2024
275 14:46:54.403228 output: Image 0 (kernel-1)
276 14:46:54.403297 output: Description:
277 14:46:54.403459 output: Created: Tue Jun 4 15:46:54 2024
278 14:46:54.403593 output: Type: Kernel Image
279 14:46:54.403690 output: Compression: lzma compressed
280 14:46:54.403779 output: Data Size: 13060619 Bytes = 12754.51 KiB = 12.46 MiB
281 14:46:54.403867 output: Architecture: AArch64
282 14:46:54.403954 output: OS: Linux
283 14:46:54.404047 output: Load Address: 0x00000000
284 14:46:54.404155 output: Entry Point: 0x00000000
285 14:46:54.404317 output: Hash algo: crc32
286 14:46:54.404416 output: Hash value: 88dcd836
287 14:46:54.404480 output: Image 1 (fdt-1)
288 14:46:54.404543 output: Description: mt8192-asurada-spherion-r0
289 14:46:54.404599 output: Created: Tue Jun 4 15:46:54 2024
290 14:46:54.404656 output: Type: Flat Device Tree
291 14:46:54.404711 output: Compression: uncompressed
292 14:46:54.404776 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 14:46:54.404851 output: Architecture: AArch64
294 14:46:54.404918 output: Hash algo: crc32
295 14:46:54.404969 output: Hash value: 0f8e4d2e
296 14:46:54.405021 output: Image 2 (ramdisk-1)
297 14:46:54.405073 output: Description: unavailable
298 14:46:54.405125 output: Created: Tue Jun 4 15:46:54 2024
299 14:46:54.405177 output: Type: RAMDisk Image
300 14:46:54.405229 output: Compression: Unknown Compression
301 14:46:54.405280 output: Data Size: 18730005 Bytes = 18291.02 KiB = 17.86 MiB
302 14:46:54.405344 output: Architecture: AArch64
303 14:46:54.405396 output: OS: Linux
304 14:46:54.405447 output: Load Address: unavailable
305 14:46:54.405499 output: Entry Point: unavailable
306 14:46:54.405550 output: Hash algo: crc32
307 14:46:54.405601 output: Hash value: ad9841ad
308 14:46:54.405652 output: Default Configuration: 'conf-1'
309 14:46:54.405703 output: Configuration 0 (conf-1)
310 14:46:54.405754 output: Description: mt8192-asurada-spherion-r0
311 14:46:54.405806 output: Kernel: kernel-1
312 14:46:54.405857 output: Init Ramdisk: ramdisk-1
313 14:46:54.405909 output: FDT: fdt-1
314 14:46:54.405961 output: Loadables: kernel-1
315 14:46:54.406012 output:
316 14:46:54.406212 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 14:46:54.406307 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 14:46:54.406412 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 14:46:54.406502 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:22) [common]
320 14:46:54.406577 No LXC device requested
321 14:46:54.406655 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 14:46:54.406741 start: 1.8 deploy-device-env (timeout 00:09:22) [common]
323 14:46:54.406817 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 14:46:54.406883 Checking files for TFTP limit of 4294967296 bytes.
325 14:46:54.407375 end: 1 tftp-deploy (duration 00:00:38) [common]
326 14:46:54.407482 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 14:46:54.407572 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 14:46:54.407690 substitutions:
329 14:46:54.407757 - {DTB}: 14167017/tftp-deploy-lmyx8m5s/dtb/mt8192-asurada-spherion-r0.dtb
330 14:46:54.407819 - {INITRD}: 14167017/tftp-deploy-lmyx8m5s/ramdisk/ramdisk.cpio.gz
331 14:46:54.407877 - {KERNEL}: 14167017/tftp-deploy-lmyx8m5s/kernel/Image
332 14:46:54.407933 - {LAVA_MAC}: None
333 14:46:54.407987 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14167017/extract-nfsrootfs-oz49gv4g
334 14:46:54.408042 - {NFS_SERVER_IP}: 192.168.201.1
335 14:46:54.408096 - {PRESEED_CONFIG}: None
336 14:46:54.408149 - {PRESEED_LOCAL}: None
337 14:46:54.408202 - {RAMDISK}: 14167017/tftp-deploy-lmyx8m5s/ramdisk/ramdisk.cpio.gz
338 14:46:54.408254 - {ROOT_PART}: None
339 14:46:54.408307 - {ROOT}: None
340 14:46:54.408359 - {SERVER_IP}: 192.168.201.1
341 14:46:54.408412 - {TEE}: None
342 14:46:54.408464 Parsed boot commands:
343 14:46:54.408523 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 14:46:54.408803 Parsed boot commands: tftpboot 192.168.201.1 14167017/tftp-deploy-lmyx8m5s/kernel/image.itb 14167017/tftp-deploy-lmyx8m5s/kernel/cmdline
345 14:46:54.408894 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 14:46:54.408979 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 14:46:54.409071 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 14:46:54.409160 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 14:46:54.409233 Not connected, no need to disconnect.
350 14:46:54.409315 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 14:46:54.409396 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 14:46:54.409462 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 14:46:54.413413 Setting prompt string to ['lava-test: # ']
354 14:46:54.413791 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 14:46:54.413901 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 14:46:54.413995 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 14:46:54.414083 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 14:46:54.414310 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=reboot']
359 14:46:59.547370 >> Command sent successfully.
360 14:46:59.549772 Returned 0 in 5 seconds
361 14:46:59.650166 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 14:46:59.650483 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 14:46:59.650585 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 14:46:59.650680 Setting prompt string to 'Starting depthcharge on Spherion...'
366 14:46:59.650748 Changing prompt to 'Starting depthcharge on Spherion...'
367 14:46:59.650813 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 14:46:59.651201 [Enter `^Ec?' for help]
369 14:46:59.831034
370 14:46:59.831194
371 14:46:59.831300 F0: 102B 0000
372 14:46:59.831394
373 14:46:59.831485 F3: 1001 0000 [0200]
374 14:46:59.831583
375 14:46:59.834654 F3: 1001 0000
376 14:46:59.834736
377 14:46:59.834801 F7: 102D 0000
378 14:46:59.834861
379 14:46:59.834920 F1: 0000 0000
380 14:46:59.838300
381 14:46:59.838384 V0: 0000 0000 [0001]
382 14:46:59.838450
383 14:46:59.838511 00: 0007 8000
384 14:46:59.838613
385 14:46:59.841508 01: 0000 0000
386 14:46:59.841594
387 14:46:59.841658 BP: 0C00 0209 [0000]
388 14:46:59.841718
389 14:46:59.845317 G0: 1182 0000
390 14:46:59.845399
391 14:46:59.845463 EC: 0000 0021 [4000]
392 14:46:59.845522
393 14:46:59.848922 S7: 0000 0000 [0000]
394 14:46:59.849003
395 14:46:59.849067 CC: 0000 0000 [0001]
396 14:46:59.849126
397 14:46:59.852285 T0: 0000 0040 [010F]
398 14:46:59.852367
399 14:46:59.852462 Jump to BL
400 14:46:59.852529
401 14:46:59.877729
402 14:46:59.877810
403 14:46:59.885079 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 14:46:59.888428 ARM64: Exception handlers installed.
405 14:46:59.891942 ARM64: Testing exception
406 14:46:59.895692 ARM64: Done test exception
407 14:46:59.903131 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 14:46:59.910223 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 14:46:59.917584 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 14:46:59.928262 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 14:46:59.934862 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 14:46:59.945081 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 14:46:59.955762 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 14:46:59.962387 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 14:46:59.980357 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 14:46:59.983908 WDT: Last reset was cold boot
417 14:46:59.987118 SPI1(PAD0) initialized at 2873684 Hz
418 14:46:59.990364 SPI5(PAD0) initialized at 992727 Hz
419 14:46:59.993526 VBOOT: Loading verstage.
420 14:47:00.000296 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 14:47:00.003686 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 14:47:00.007174 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 14:47:00.010269 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 14:47:00.018073 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 14:47:00.024368 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 14:47:00.035128 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
427 14:47:00.035235
428 14:47:00.035339
429 14:47:00.045250 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 14:47:00.048447 ARM64: Exception handlers installed.
431 14:47:00.052161 ARM64: Testing exception
432 14:47:00.052266 ARM64: Done test exception
433 14:47:00.058522 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 14:47:00.062036 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 14:47:00.076390 Probing TPM: . done!
436 14:47:00.076468 TPM ready after 0 ms
437 14:47:00.083604 Connected to device vid:did:rid of 1ae0:0028:00
438 14:47:00.090205 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
439 14:47:00.138804 Initialized TPM device CR50 revision 0
440 14:47:00.154425 tlcl_send_startup: Startup return code is 0
441 14:47:00.154514 TPM: setup succeeded
442 14:47:00.165007 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 14:47:00.174231 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 14:47:00.183538 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 14:47:00.192575 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 14:47:00.195994 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 14:47:00.199210 in-header: 03 07 00 00 08 00 00 00
448 14:47:00.202672 in-data: aa e4 47 04 13 02 00 00
449 14:47:00.205940 Chrome EC: UHEPI supported
450 14:47:00.212452 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 14:47:00.216349 in-header: 03 95 00 00 08 00 00 00
452 14:47:00.220017 in-data: 18 20 20 08 00 00 00 00
453 14:47:00.220096 Phase 1
454 14:47:00.223517 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 14:47:00.231025 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 14:47:00.234804 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
457 14:47:00.237995 Recovery requested (1009000e)
458 14:47:00.247206 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 14:47:00.253132 tlcl_extend: response is 0
460 14:47:00.262030 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 14:47:00.267372 tlcl_extend: response is 0
462 14:47:00.274868 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 14:47:00.295172 read SPI 0x210d4 0x2173b: 15144 us, 9047 KB/s, 72.376 Mbps
464 14:47:00.302544 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 14:47:00.302652
466 14:47:00.302760
467 14:47:00.313517 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 14:47:00.313607 ARM64: Exception handlers installed.
469 14:47:00.316806 ARM64: Testing exception
470 14:47:00.320470 ARM64: Done test exception
471 14:47:00.340475 pmic_efuse_setting: Set efuses in 11 msecs
472 14:47:00.343690 pmwrap_interface_init: Select PMIF_VLD_RDY
473 14:47:00.350228 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 14:47:00.353442 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 14:47:00.360018 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 14:47:00.363893 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 14:47:00.370388 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 14:47:00.373564 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 14:47:00.377144 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 14:47:00.383698 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 14:47:00.386846 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 14:47:00.393666 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 14:47:00.396892 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 14:47:00.400224 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 14:47:00.406646 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 14:47:00.413513 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 14:47:00.417208 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 14:47:00.424876 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 14:47:00.428518 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 14:47:00.435289 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 14:47:00.442575 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 14:47:00.446360 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 14:47:00.453750 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 14:47:00.456993 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 14:47:00.464390 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 14:47:00.468103 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 14:47:00.475415 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 14:47:00.479134 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 14:47:00.486171 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 14:47:00.490358 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 14:47:00.493478 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 14:47:00.500917 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 14:47:00.504747 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 14:47:00.507897 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 14:47:00.515398 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 14:47:00.518878 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 14:47:00.522877 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 14:47:00.530040 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 14:47:00.533997 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 14:47:00.541786 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 14:47:00.544986 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 14:47:00.548678 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 14:47:00.552377 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 14:47:00.555532 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 14:47:00.562718 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 14:47:00.566572 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 14:47:00.569869 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 14:47:00.573425 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 14:47:00.577582 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 14:47:00.584515 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 14:47:00.588228 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 14:47:00.591952 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 14:47:00.595576 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 14:47:00.602635 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
525 14:47:00.613467 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 14:47:00.617857 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 14:47:00.624857 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 14:47:00.632059 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 14:47:00.636040 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 14:47:00.643214 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 14:47:00.646570 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 14:47:00.653615 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x18
533 14:47:00.657260 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 14:47:00.664798 [RTC]rtc_osc_init,62: osc32con val = 0xde70
535 14:47:00.668028 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 14:47:00.678360 [RTC]rtc_get_frequency_meter,154: input=15, output=764
537 14:47:00.687911 [RTC]rtc_get_frequency_meter,154: input=23, output=948
538 14:47:00.696707 [RTC]rtc_get_frequency_meter,154: input=19, output=857
539 14:47:00.706570 [RTC]rtc_get_frequency_meter,154: input=17, output=811
540 14:47:00.715907 [RTC]rtc_get_frequency_meter,154: input=16, output=787
541 14:47:00.725233 [RTC]rtc_get_frequency_meter,154: input=16, output=786
542 14:47:00.735442 [RTC]rtc_get_frequency_meter,154: input=17, output=811
543 14:47:00.738697 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
544 14:47:00.742764 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
545 14:47:00.746287 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 14:47:00.753532 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
547 14:47:00.757255 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 14:47:00.760808 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
549 14:47:00.764583 ADC[4]: Raw value=670432 ID=5
550 14:47:00.768178 ADC[3]: Raw value=212917 ID=1
551 14:47:00.768281 RAM Code: 0x51
552 14:47:00.772101 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 14:47:00.779422 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 14:47:00.786925 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
555 14:47:00.791024 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
556 14:47:00.794721 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 14:47:00.798416 in-header: 03 07 00 00 08 00 00 00
558 14:47:00.802031 in-data: aa e4 47 04 13 02 00 00
559 14:47:00.802136 Chrome EC: UHEPI supported
560 14:47:00.809205 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 14:47:00.814478 in-header: 03 95 00 00 08 00 00 00
562 14:47:00.818070 in-data: 18 20 20 08 00 00 00 00
563 14:47:00.821878 MRC: failed to locate region type 0.
564 14:47:00.829222 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 14:47:00.833142 DRAM-K: Running full calibration
566 14:47:00.836393 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
567 14:47:00.839943 header.status = 0x0
568 14:47:00.843499 header.version = 0x6 (expected: 0x6)
569 14:47:00.847469 header.size = 0xd00 (expected: 0xd00)
570 14:47:00.847574 header.flags = 0x0
571 14:47:00.854086 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 14:47:00.872065 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
573 14:47:00.879388 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 14:47:00.879471 dram_init: ddr_geometry: 0
575 14:47:00.882981 [EMI] MDL number = 0
576 14:47:00.886842 [EMI] Get MDL freq = 0
577 14:47:00.886921 dram_init: ddr_type: 0
578 14:47:00.890987 is_discrete_lpddr4: 1
579 14:47:00.894331 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 14:47:00.894409
581 14:47:00.894492
582 14:47:00.894585 [Bian_co] ETT version 0.0.0.1
583 14:47:00.901691 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
584 14:47:00.901774
585 14:47:00.905430 dramc_set_vcore_voltage set vcore to 650000
586 14:47:00.905540 Read voltage for 800, 4
587 14:47:00.905642 Vio18 = 0
588 14:47:00.909169 Vcore = 650000
589 14:47:00.909245 Vdram = 0
590 14:47:00.909371 Vddq = 0
591 14:47:00.913015 Vmddr = 0
592 14:47:00.913113 dram_init: config_dvfs: 1
593 14:47:00.920026 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 14:47:00.923586 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 14:47:00.927358 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
596 14:47:00.930962 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
597 14:47:00.934656 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
598 14:47:00.938212 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
599 14:47:00.941734 MEM_TYPE=3, freq_sel=18
600 14:47:00.945860 sv_algorithm_assistance_LP4_1600
601 14:47:00.948922 ============ PULL DRAM RESETB DOWN ============
602 14:47:00.952433 ========== PULL DRAM RESETB DOWN end =========
603 14:47:00.955894 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 14:47:00.959427 ===================================
605 14:47:00.963328 LPDDR4 DRAM CONFIGURATION
606 14:47:00.967100 ===================================
607 14:47:00.967178 EX_ROW_EN[0] = 0x0
608 14:47:00.970425 EX_ROW_EN[1] = 0x0
609 14:47:00.970499 LP4Y_EN = 0x0
610 14:47:00.974295 WORK_FSP = 0x0
611 14:47:00.974395 WL = 0x2
612 14:47:00.978300 RL = 0x2
613 14:47:00.978376 BL = 0x2
614 14:47:00.981922 RPST = 0x0
615 14:47:00.981996 RD_PRE = 0x0
616 14:47:00.985792 WR_PRE = 0x1
617 14:47:00.985895 WR_PST = 0x0
618 14:47:00.985996 DBI_WR = 0x0
619 14:47:00.989212 DBI_RD = 0x0
620 14:47:00.989346 OTF = 0x1
621 14:47:00.993076 ===================================
622 14:47:00.996282 ===================================
623 14:47:01.000140 ANA top config
624 14:47:01.004140 ===================================
625 14:47:01.004243 DLL_ASYNC_EN = 0
626 14:47:01.008114 ALL_SLAVE_EN = 1
627 14:47:01.011616 NEW_RANK_MODE = 1
628 14:47:01.011724 DLL_IDLE_MODE = 1
629 14:47:01.015052 LP45_APHY_COMB_EN = 1
630 14:47:01.018552 TX_ODT_DIS = 1
631 14:47:01.018652 NEW_8X_MODE = 1
632 14:47:01.022101 ===================================
633 14:47:01.025272 ===================================
634 14:47:01.028537 data_rate = 1600
635 14:47:01.031997 CKR = 1
636 14:47:01.035351 DQ_P2S_RATIO = 8
637 14:47:01.038777 ===================================
638 14:47:01.042582 CA_P2S_RATIO = 8
639 14:47:01.042689 DQ_CA_OPEN = 0
640 14:47:01.046073 DQ_SEMI_OPEN = 0
641 14:47:01.049981 CA_SEMI_OPEN = 0
642 14:47:01.053569 CA_FULL_RATE = 0
643 14:47:01.053652 DQ_CKDIV4_EN = 1
644 14:47:01.057227 CA_CKDIV4_EN = 1
645 14:47:01.060944 CA_PREDIV_EN = 0
646 14:47:01.064343 PH8_DLY = 0
647 14:47:01.067641 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 14:47:01.067720 DQ_AAMCK_DIV = 4
649 14:47:01.071184 CA_AAMCK_DIV = 4
650 14:47:01.074246 CA_ADMCK_DIV = 4
651 14:47:01.077895 DQ_TRACK_CA_EN = 0
652 14:47:01.081695 CA_PICK = 800
653 14:47:01.081772 CA_MCKIO = 800
654 14:47:01.085010 MCKIO_SEMI = 0
655 14:47:01.088748 PLL_FREQ = 3068
656 14:47:01.092051 DQ_UI_PI_RATIO = 32
657 14:47:01.095209 CA_UI_PI_RATIO = 0
658 14:47:01.098893 ===================================
659 14:47:01.102380 ===================================
660 14:47:01.102459 memory_type:LPDDR4
661 14:47:01.106073 GP_NUM : 10
662 14:47:01.106178 SRAM_EN : 1
663 14:47:01.109948 MD32_EN : 0
664 14:47:01.113608 ===================================
665 14:47:01.113686 [ANA_INIT] >>>>>>>>>>>>>>
666 14:47:01.117254 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 14:47:01.120750 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 14:47:01.124236 ===================================
669 14:47:01.128296 data_rate = 1600,PCW = 0X7600
670 14:47:01.131981 ===================================
671 14:47:01.135454 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 14:47:01.138716 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 14:47:01.145276 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 14:47:01.149092 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 14:47:01.151998 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 14:47:01.155608 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 14:47:01.158648 [ANA_INIT] flow start
678 14:47:01.162208 [ANA_INIT] PLL >>>>>>>>
679 14:47:01.162284 [ANA_INIT] PLL <<<<<<<<
680 14:47:01.165234 [ANA_INIT] MIDPI >>>>>>>>
681 14:47:01.168476 [ANA_INIT] MIDPI <<<<<<<<
682 14:47:01.168575 [ANA_INIT] DLL >>>>>>>>
683 14:47:01.171838 [ANA_INIT] flow end
684 14:47:01.175308 ============ LP4 DIFF to SE enter ============
685 14:47:01.182386 ============ LP4 DIFF to SE exit ============
686 14:47:01.182471 [ANA_INIT] <<<<<<<<<<<<<
687 14:47:01.185241 [Flow] Enable top DCM control >>>>>
688 14:47:01.188662 [Flow] Enable top DCM control <<<<<
689 14:47:01.191917 Enable DLL master slave shuffle
690 14:47:01.198552 ==============================================================
691 14:47:01.198640 Gating Mode config
692 14:47:01.205371 ==============================================================
693 14:47:01.205478 Config description:
694 14:47:01.215576 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 14:47:01.222450 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 14:47:01.228751 SELPH_MODE 0: By rank 1: By Phase
697 14:47:01.232108 ==============================================================
698 14:47:01.235398 GAT_TRACK_EN = 1
699 14:47:01.238732 RX_GATING_MODE = 2
700 14:47:01.242244 RX_GATING_TRACK_MODE = 2
701 14:47:01.245361 SELPH_MODE = 1
702 14:47:01.248487 PICG_EARLY_EN = 1
703 14:47:01.251927 VALID_LAT_VALUE = 1
704 14:47:01.258491 ==============================================================
705 14:47:01.262073 Enter into Gating configuration >>>>
706 14:47:01.265159 Exit from Gating configuration <<<<
707 14:47:01.265264 Enter into DVFS_PRE_config >>>>>
708 14:47:01.278380 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 14:47:01.281831 Exit from DVFS_PRE_config <<<<<
710 14:47:01.285285 Enter into PICG configuration >>>>
711 14:47:01.288282 Exit from PICG configuration <<<<
712 14:47:01.288386 [RX_INPUT] configuration >>>>>
713 14:47:01.291671 [RX_INPUT] configuration <<<<<
714 14:47:01.298332 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 14:47:01.301763 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 14:47:01.308372 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 14:47:01.315015 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 14:47:01.321700 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 14:47:01.328714 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 14:47:01.331946 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 14:47:01.334965 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 14:47:01.341750 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 14:47:01.344933 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 14:47:01.348358 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 14:47:01.351638 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 14:47:01.354910 ===================================
727 14:47:01.358852 LPDDR4 DRAM CONFIGURATION
728 14:47:01.361794 ===================================
729 14:47:01.365170 EX_ROW_EN[0] = 0x0
730 14:47:01.365270 EX_ROW_EN[1] = 0x0
731 14:47:01.368411 LP4Y_EN = 0x0
732 14:47:01.368492 WORK_FSP = 0x0
733 14:47:01.371830 WL = 0x2
734 14:47:01.371912 RL = 0x2
735 14:47:01.374878 BL = 0x2
736 14:47:01.374960 RPST = 0x0
737 14:47:01.378236 RD_PRE = 0x0
738 14:47:01.378319 WR_PRE = 0x1
739 14:47:01.381692 WR_PST = 0x0
740 14:47:01.381774 DBI_WR = 0x0
741 14:47:01.384783 DBI_RD = 0x0
742 14:47:01.388422 OTF = 0x1
743 14:47:01.388507 ===================================
744 14:47:01.395034 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 14:47:01.398279 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 14:47:01.401630 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 14:47:01.405001 ===================================
748 14:47:01.408396 LPDDR4 DRAM CONFIGURATION
749 14:47:01.411592 ===================================
750 14:47:01.414698 EX_ROW_EN[0] = 0x10
751 14:47:01.414802 EX_ROW_EN[1] = 0x0
752 14:47:01.418210 LP4Y_EN = 0x0
753 14:47:01.418330 WORK_FSP = 0x0
754 14:47:01.421675 WL = 0x2
755 14:47:01.421748 RL = 0x2
756 14:47:01.424662 BL = 0x2
757 14:47:01.424733 RPST = 0x0
758 14:47:01.428538 RD_PRE = 0x0
759 14:47:01.428613 WR_PRE = 0x1
760 14:47:01.431638 WR_PST = 0x0
761 14:47:01.431717 DBI_WR = 0x0
762 14:47:01.434939 DBI_RD = 0x0
763 14:47:01.435015 OTF = 0x1
764 14:47:01.438279 ===================================
765 14:47:01.444750 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 14:47:01.449360 nWR fixed to 40
767 14:47:01.452878 [ModeRegInit_LP4] CH0 RK0
768 14:47:01.453035 [ModeRegInit_LP4] CH0 RK1
769 14:47:01.455984 [ModeRegInit_LP4] CH1 RK0
770 14:47:01.459646 [ModeRegInit_LP4] CH1 RK1
771 14:47:01.459793 match AC timing 12
772 14:47:01.465945 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
773 14:47:01.469348 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 14:47:01.472647 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 14:47:01.479496 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 14:47:01.482593 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 14:47:01.482678 [EMI DOE] emi_dcm 0
778 14:47:01.489678 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 14:47:01.489800 ==
780 14:47:01.492851 Dram Type= 6, Freq= 0, CH_0, rank 0
781 14:47:01.496215 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 14:47:01.496301 ==
783 14:47:01.502584 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 14:47:01.509348 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 14:47:01.516750 [CA 0] Center 37 (7~68) winsize 62
786 14:47:01.520215 [CA 1] Center 37 (7~68) winsize 62
787 14:47:01.523335 [CA 2] Center 35 (5~66) winsize 62
788 14:47:01.526575 [CA 3] Center 35 (4~66) winsize 63
789 14:47:01.530121 [CA 4] Center 34 (4~65) winsize 62
790 14:47:01.533251 [CA 5] Center 34 (4~64) winsize 61
791 14:47:01.533361
792 14:47:01.536832 [CmdBusTrainingLP45] Vref(ca) range 1: 32
793 14:47:01.536935
794 14:47:01.540274 [CATrainingPosCal] consider 1 rank data
795 14:47:01.543434 u2DelayCellTimex100 = 270/100 ps
796 14:47:01.547118 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
797 14:47:01.550042 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
798 14:47:01.556734 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
799 14:47:01.559932 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
800 14:47:01.563322 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
801 14:47:01.566637 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
802 14:47:01.566720
803 14:47:01.570136 CA PerBit enable=1, Macro0, CA PI delay=34
804 14:47:01.570266
805 14:47:01.573223 [CBTSetCACLKResult] CA Dly = 34
806 14:47:01.573347 CS Dly: 5 (0~36)
807 14:47:01.577088 ==
808 14:47:01.577196 Dram Type= 6, Freq= 0, CH_0, rank 1
809 14:47:01.583150 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
810 14:47:01.583233 ==
811 14:47:01.586663 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 14:47:01.593185 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 14:47:01.602639 [CA 0] Center 37 (7~68) winsize 62
814 14:47:01.606057 [CA 1] Center 37 (6~68) winsize 63
815 14:47:01.609225 [CA 2] Center 35 (4~66) winsize 63
816 14:47:01.612638 [CA 3] Center 34 (4~65) winsize 62
817 14:47:01.616256 [CA 4] Center 33 (3~64) winsize 62
818 14:47:01.619504 [CA 5] Center 33 (3~64) winsize 62
819 14:47:01.619577
820 14:47:01.622422 [CmdBusTrainingLP45] Vref(ca) range 1: 32
821 14:47:01.622497
822 14:47:01.625796 [CATrainingPosCal] consider 2 rank data
823 14:47:01.629353 u2DelayCellTimex100 = 270/100 ps
824 14:47:01.632495 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
825 14:47:01.635980 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
826 14:47:01.642475 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
827 14:47:01.646017 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
828 14:47:01.649320 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
829 14:47:01.652336 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
830 14:47:01.652450
831 14:47:01.655673 CA PerBit enable=1, Macro0, CA PI delay=34
832 14:47:01.655746
833 14:47:01.658961 [CBTSetCACLKResult] CA Dly = 34
834 14:47:01.659032 CS Dly: 6 (0~38)
835 14:47:01.659095
836 14:47:01.662609 ----->DramcWriteLeveling(PI) begin...
837 14:47:01.665854 ==
838 14:47:01.669029 Dram Type= 6, Freq= 0, CH_0, rank 0
839 14:47:01.672426 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
840 14:47:01.672509 ==
841 14:47:01.675589 Write leveling (Byte 0): 27 => 27
842 14:47:01.679724 Write leveling (Byte 1): 27 => 27
843 14:47:01.679805 DramcWriteLeveling(PI) end<-----
844 14:47:01.682896
845 14:47:01.683009 ==
846 14:47:01.686776 Dram Type= 6, Freq= 0, CH_0, rank 0
847 14:47:01.690030 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
848 14:47:01.690113 ==
849 14:47:01.693751 [Gating] SW mode calibration
850 14:47:01.697846 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 14:47:01.704769 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 14:47:01.708129 0 6 0 | B1->B0 | 3434 3333 | 1 1 | (0 0) (1 0)
853 14:47:01.711784 0 6 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
854 14:47:01.718195 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 14:47:01.721503 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 14:47:01.724739 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 14:47:01.731503 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 14:47:01.734752 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 14:47:01.738163 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 14:47:01.745126 0 7 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
861 14:47:01.748202 0 7 4 | B1->B0 | 3b3b 4242 | 0 0 | (0 0) (0 0)
862 14:47:01.751420 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 14:47:01.757980 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 14:47:01.761432 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 14:47:01.764656 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 14:47:01.771190 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 14:47:01.774690 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 14:47:01.778018 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
869 14:47:01.784460 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
870 14:47:01.787694 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 14:47:01.791111 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 14:47:01.798020 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 14:47:01.801175 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 14:47:01.804418 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 14:47:01.810962 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 14:47:01.814276 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 14:47:01.817795 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 14:47:01.821154 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 14:47:01.827892 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 14:47:01.831217 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 14:47:01.834424 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 14:47:01.840930 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 14:47:01.844419 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 14:47:01.847735 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
885 14:47:01.854474 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
886 14:47:01.857881 Total UI for P1: 0, mck2ui 16
887 14:47:01.861090 best dqsien dly found for B1: ( 0, 10, 0)
888 14:47:01.864207 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
889 14:47:01.867589 Total UI for P1: 0, mck2ui 16
890 14:47:01.871089 best dqsien dly found for B0: ( 0, 10, 2)
891 14:47:01.874528 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
892 14:47:01.877580 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
893 14:47:01.877662
894 14:47:01.881136 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
895 14:47:01.884299 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
896 14:47:01.887696 [Gating] SW calibration Done
897 14:47:01.887802 ==
898 14:47:01.890955 Dram Type= 6, Freq= 0, CH_0, rank 0
899 14:47:01.894153 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 14:47:01.897949 ==
901 14:47:01.898030 RX Vref Scan: 0
902 14:47:01.898094
903 14:47:01.900919 RX Vref 0 -> 0, step: 1
904 14:47:01.901026
905 14:47:01.904145 RX Delay -130 -> 252, step: 16
906 14:47:01.907588 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
907 14:47:01.910944 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
908 14:47:01.914365 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
909 14:47:01.918347 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
910 14:47:01.924521 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
911 14:47:01.927756 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
912 14:47:01.931252 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
913 14:47:01.934412 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
914 14:47:01.937448 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
915 14:47:01.944146 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
916 14:47:01.947499 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
917 14:47:01.951334 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
918 14:47:01.954318 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
919 14:47:01.957715 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
920 14:47:01.964136 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
921 14:47:01.967488 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
922 14:47:01.967569 ==
923 14:47:01.970977 Dram Type= 6, Freq= 0, CH_0, rank 0
924 14:47:01.974355 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
925 14:47:01.974437 ==
926 14:47:01.977636 DQS Delay:
927 14:47:01.977717 DQS0 = 0, DQS1 = 0
928 14:47:01.977782 DQM Delay:
929 14:47:01.980951 DQM0 = 82, DQM1 = 74
930 14:47:01.981033 DQ Delay:
931 14:47:01.984621 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
932 14:47:01.988121 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
933 14:47:01.990835 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
934 14:47:01.994190 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
935 14:47:01.994272
936 14:47:01.994335
937 14:47:01.994395 ==
938 14:47:01.997405 Dram Type= 6, Freq= 0, CH_0, rank 0
939 14:47:02.000833 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
940 14:47:02.004081 ==
941 14:47:02.004162
942 14:47:02.004225
943 14:47:02.004283 TX Vref Scan disable
944 14:47:02.007632 == TX Byte 0 ==
945 14:47:02.010778 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
946 14:47:02.014566 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
947 14:47:02.017715 == TX Byte 1 ==
948 14:47:02.020976 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
949 14:47:02.024486 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
950 14:47:02.027637 ==
951 14:47:02.027718 Dram Type= 6, Freq= 0, CH_0, rank 0
952 14:47:02.034587 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
953 14:47:02.034695 ==
954 14:47:02.046313 TX Vref=22, minBit 0, minWin=27, winSum=439
955 14:47:02.049381 TX Vref=24, minBit 2, minWin=27, winSum=445
956 14:47:02.052890 TX Vref=26, minBit 4, minWin=27, winSum=449
957 14:47:02.056019 TX Vref=28, minBit 3, minWin=28, winSum=453
958 14:47:02.059710 TX Vref=30, minBit 11, minWin=27, winSum=451
959 14:47:02.066150 TX Vref=32, minBit 0, minWin=28, winSum=450
960 14:47:02.069683 [TxChooseVref] Worse bit 3, Min win 28, Win sum 453, Final Vref 28
961 14:47:02.069765
962 14:47:02.073186 Final TX Range 1 Vref 28
963 14:47:02.073274
964 14:47:02.073350 ==
965 14:47:02.076207 Dram Type= 6, Freq= 0, CH_0, rank 0
966 14:47:02.079648 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
967 14:47:02.079728 ==
968 14:47:02.079793
969 14:47:02.079854
970 14:47:02.082815 TX Vref Scan disable
971 14:47:02.086290 == TX Byte 0 ==
972 14:47:02.089614 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
973 14:47:02.093055 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
974 14:47:02.096475 == TX Byte 1 ==
975 14:47:02.099400 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
976 14:47:02.102972 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
977 14:47:02.103076
978 14:47:02.106025 [DATLAT]
979 14:47:02.106106 Freq=800, CH0 RK0
980 14:47:02.106170
981 14:47:02.109685 DATLAT Default: 0xa
982 14:47:02.109766 0, 0xFFFF, sum = 0
983 14:47:02.113433 1, 0xFFFF, sum = 0
984 14:47:02.113516 2, 0xFFFF, sum = 0
985 14:47:02.116241 3, 0xFFFF, sum = 0
986 14:47:02.116324 4, 0xFFFF, sum = 0
987 14:47:02.119623 5, 0xFFFF, sum = 0
988 14:47:02.119706 6, 0xFFFF, sum = 0
989 14:47:02.123012 7, 0xFFFF, sum = 0
990 14:47:02.123095 8, 0x0, sum = 1
991 14:47:02.126264 9, 0x0, sum = 2
992 14:47:02.126347 10, 0x0, sum = 3
993 14:47:02.129602 11, 0x0, sum = 4
994 14:47:02.129711 best_step = 9
995 14:47:02.129803
996 14:47:02.129891 ==
997 14:47:02.132859 Dram Type= 6, Freq= 0, CH_0, rank 0
998 14:47:02.139986 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
999 14:47:02.140069 ==
1000 14:47:02.140133 RX Vref Scan: 1
1001 14:47:02.140193
1002 14:47:02.142889 Set Vref Range= 32 -> 127
1003 14:47:02.142993
1004 14:47:02.146189 RX Vref 32 -> 127, step: 1
1005 14:47:02.146271
1006 14:47:02.146335 RX Delay -111 -> 252, step: 8
1007 14:47:02.149623
1008 14:47:02.149704 Set Vref, RX VrefLevel [Byte0]: 32
1009 14:47:02.152770 [Byte1]: 32
1010 14:47:02.157015
1011 14:47:02.157122 Set Vref, RX VrefLevel [Byte0]: 33
1012 14:47:02.160347 [Byte1]: 33
1013 14:47:02.164714
1014 14:47:02.164795 Set Vref, RX VrefLevel [Byte0]: 34
1015 14:47:02.167887 [Byte1]: 34
1016 14:47:02.172884
1017 14:47:02.172965 Set Vref, RX VrefLevel [Byte0]: 35
1018 14:47:02.175890 [Byte1]: 35
1019 14:47:02.179943
1020 14:47:02.180031 Set Vref, RX VrefLevel [Byte0]: 36
1021 14:47:02.183454 [Byte1]: 36
1022 14:47:02.187693
1023 14:47:02.187774 Set Vref, RX VrefLevel [Byte0]: 37
1024 14:47:02.191022 [Byte1]: 37
1025 14:47:02.195321
1026 14:47:02.195400 Set Vref, RX VrefLevel [Byte0]: 38
1027 14:47:02.198531 [Byte1]: 38
1028 14:47:02.202976
1029 14:47:02.203084 Set Vref, RX VrefLevel [Byte0]: 39
1030 14:47:02.206318 [Byte1]: 39
1031 14:47:02.210427
1032 14:47:02.210508 Set Vref, RX VrefLevel [Byte0]: 40
1033 14:47:02.213794 [Byte1]: 40
1034 14:47:02.218552
1035 14:47:02.218631 Set Vref, RX VrefLevel [Byte0]: 41
1036 14:47:02.221697 [Byte1]: 41
1037 14:47:02.226147
1038 14:47:02.229122 Set Vref, RX VrefLevel [Byte0]: 42
1039 14:47:02.229228 [Byte1]: 42
1040 14:47:02.233616
1041 14:47:02.233721 Set Vref, RX VrefLevel [Byte0]: 43
1042 14:47:02.236731 [Byte1]: 43
1043 14:47:02.241468
1044 14:47:02.241592 Set Vref, RX VrefLevel [Byte0]: 44
1045 14:47:02.244758 [Byte1]: 44
1046 14:47:02.248716
1047 14:47:02.248795 Set Vref, RX VrefLevel [Byte0]: 45
1048 14:47:02.252270 [Byte1]: 45
1049 14:47:02.256809
1050 14:47:02.256889 Set Vref, RX VrefLevel [Byte0]: 46
1051 14:47:02.260162 [Byte1]: 46
1052 14:47:02.264192
1053 14:47:02.264272 Set Vref, RX VrefLevel [Byte0]: 47
1054 14:47:02.267159 [Byte1]: 47
1055 14:47:02.271884
1056 14:47:02.271965 Set Vref, RX VrefLevel [Byte0]: 48
1057 14:47:02.274839 [Byte1]: 48
1058 14:47:02.279260
1059 14:47:02.279339 Set Vref, RX VrefLevel [Byte0]: 49
1060 14:47:02.282793 [Byte1]: 49
1061 14:47:02.286987
1062 14:47:02.287067 Set Vref, RX VrefLevel [Byte0]: 50
1063 14:47:02.290485 [Byte1]: 50
1064 14:47:02.294763
1065 14:47:02.294842 Set Vref, RX VrefLevel [Byte0]: 51
1066 14:47:02.298066 [Byte1]: 51
1067 14:47:02.302702
1068 14:47:02.302781 Set Vref, RX VrefLevel [Byte0]: 52
1069 14:47:02.305627 [Byte1]: 52
1070 14:47:02.309970
1071 14:47:02.310049 Set Vref, RX VrefLevel [Byte0]: 53
1072 14:47:02.313199 [Byte1]: 53
1073 14:47:02.317389
1074 14:47:02.317468 Set Vref, RX VrefLevel [Byte0]: 54
1075 14:47:02.321092 [Byte1]: 54
1076 14:47:02.325266
1077 14:47:02.328489 Set Vref, RX VrefLevel [Byte0]: 55
1078 14:47:02.328562 [Byte1]: 55
1079 14:47:02.332903
1080 14:47:02.332976 Set Vref, RX VrefLevel [Byte0]: 56
1081 14:47:02.336012 [Byte1]: 56
1082 14:47:02.340587
1083 14:47:02.340664 Set Vref, RX VrefLevel [Byte0]: 57
1084 14:47:02.343814 [Byte1]: 57
1085 14:47:02.348452
1086 14:47:02.348526 Set Vref, RX VrefLevel [Byte0]: 58
1087 14:47:02.351897 [Byte1]: 58
1088 14:47:02.356212
1089 14:47:02.356284 Set Vref, RX VrefLevel [Byte0]: 59
1090 14:47:02.359398 [Byte1]: 59
1091 14:47:02.363813
1092 14:47:02.363885 Set Vref, RX VrefLevel [Byte0]: 60
1093 14:47:02.367326 [Byte1]: 60
1094 14:47:02.371379
1095 14:47:02.371450 Set Vref, RX VrefLevel [Byte0]: 61
1096 14:47:02.374508 [Byte1]: 61
1097 14:47:02.378803
1098 14:47:02.378884 Set Vref, RX VrefLevel [Byte0]: 62
1099 14:47:02.382271 [Byte1]: 62
1100 14:47:02.386440
1101 14:47:02.386521 Set Vref, RX VrefLevel [Byte0]: 63
1102 14:47:02.389490 [Byte1]: 63
1103 14:47:02.394285
1104 14:47:02.394365 Set Vref, RX VrefLevel [Byte0]: 64
1105 14:47:02.397424 [Byte1]: 64
1106 14:47:02.401764
1107 14:47:02.401844 Set Vref, RX VrefLevel [Byte0]: 65
1108 14:47:02.404918 [Byte1]: 65
1109 14:47:02.409623
1110 14:47:02.409703 Set Vref, RX VrefLevel [Byte0]: 66
1111 14:47:02.412635 [Byte1]: 66
1112 14:47:02.416906
1113 14:47:02.416985 Set Vref, RX VrefLevel [Byte0]: 67
1114 14:47:02.420438 [Byte1]: 67
1115 14:47:02.424494
1116 14:47:02.424573 Set Vref, RX VrefLevel [Byte0]: 68
1117 14:47:02.427987 [Byte1]: 68
1118 14:47:02.432324
1119 14:47:02.432402 Set Vref, RX VrefLevel [Byte0]: 69
1120 14:47:02.435561 [Byte1]: 69
1121 14:47:02.440114
1122 14:47:02.440193 Set Vref, RX VrefLevel [Byte0]: 70
1123 14:47:02.443127 [Byte1]: 70
1124 14:47:02.447428
1125 14:47:02.447507 Set Vref, RX VrefLevel [Byte0]: 71
1126 14:47:02.451103 [Byte1]: 71
1127 14:47:02.455294
1128 14:47:02.455391 Set Vref, RX VrefLevel [Byte0]: 72
1129 14:47:02.458412 [Byte1]: 72
1130 14:47:02.462984
1131 14:47:02.463063 Set Vref, RX VrefLevel [Byte0]: 73
1132 14:47:02.466162 [Byte1]: 73
1133 14:47:02.470584
1134 14:47:02.470664 Set Vref, RX VrefLevel [Byte0]: 74
1135 14:47:02.473821 [Byte1]: 74
1136 14:47:02.478086
1137 14:47:02.478165 Set Vref, RX VrefLevel [Byte0]: 75
1138 14:47:02.481660 [Byte1]: 75
1139 14:47:02.485743
1140 14:47:02.485822 Final RX Vref Byte 0 = 49 to rank0
1141 14:47:02.489305 Final RX Vref Byte 1 = 55 to rank0
1142 14:47:02.492528 Final RX Vref Byte 0 = 49 to rank1
1143 14:47:02.496114 Final RX Vref Byte 1 = 55 to rank1==
1144 14:47:02.499168 Dram Type= 6, Freq= 0, CH_0, rank 0
1145 14:47:02.505805 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1146 14:47:02.505886 ==
1147 14:47:02.505948 DQS Delay:
1148 14:47:02.506007 DQS0 = 0, DQS1 = 0
1149 14:47:02.509251 DQM Delay:
1150 14:47:02.509353 DQM0 = 84, DQM1 = 74
1151 14:47:02.512506 DQ Delay:
1152 14:47:02.515672 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1153 14:47:02.515752 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1154 14:47:02.519131 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1155 14:47:02.522348 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1156 14:47:02.525983
1157 14:47:02.526063
1158 14:47:02.532421 [DQSOSCAuto] RK0, (LSB)MR18= 0x3434, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1159 14:47:02.535689 CH0 RK0: MR19=606, MR18=3434
1160 14:47:02.542204 CH0_RK0: MR19=0x606, MR18=0x3434, DQSOSC=396, MR23=63, INC=94, DEC=62
1161 14:47:02.542285
1162 14:47:02.545647 ----->DramcWriteLeveling(PI) begin...
1163 14:47:02.545728 ==
1164 14:47:02.549019 Dram Type= 6, Freq= 0, CH_0, rank 1
1165 14:47:02.552142 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1166 14:47:02.552223 ==
1167 14:47:02.555677 Write leveling (Byte 0): 31 => 31
1168 14:47:02.559098 Write leveling (Byte 1): 28 => 28
1169 14:47:02.562609 DramcWriteLeveling(PI) end<-----
1170 14:47:02.562688
1171 14:47:02.562750 ==
1172 14:47:02.565739 Dram Type= 6, Freq= 0, CH_0, rank 1
1173 14:47:02.569225 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1174 14:47:02.569327 ==
1175 14:47:02.572681 [Gating] SW mode calibration
1176 14:47:02.578968 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1177 14:47:02.585584 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1178 14:47:02.589020 0 6 0 | B1->B0 | 3131 3030 | 0 0 | (1 0) (1 0)
1179 14:47:02.592388 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1180 14:47:02.599181 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 14:47:02.602376 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 14:47:02.605928 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 14:47:02.612409 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 14:47:02.615530 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 14:47:02.619275 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 14:47:02.625664 0 7 0 | B1->B0 | 2828 3030 | 1 0 | (0 0) (0 0)
1187 14:47:02.628813 0 7 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1188 14:47:02.632297 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 14:47:02.635581 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 14:47:02.642609 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 14:47:02.645976 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 14:47:02.649187 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 14:47:02.655642 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 14:47:02.659027 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 14:47:02.662864 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 14:47:02.668974 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 14:47:02.672358 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 14:47:02.675853 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 14:47:02.682414 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 14:47:02.685962 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 14:47:02.689208 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 14:47:02.696205 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 14:47:02.699647 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 14:47:02.702559 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 14:47:02.709340 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 14:47:02.712541 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 14:47:02.716198 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 14:47:02.719427 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 14:47:02.726214 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 14:47:02.729336 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1211 14:47:02.732539 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 14:47:02.736212 Total UI for P1: 0, mck2ui 16
1213 14:47:02.739300 best dqsien dly found for B0: ( 0, 10, 0)
1214 14:47:02.742588 Total UI for P1: 0, mck2ui 16
1215 14:47:02.745896 best dqsien dly found for B1: ( 0, 10, 0)
1216 14:47:02.749218 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1217 14:47:02.752476 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1218 14:47:02.752558
1219 14:47:02.799967 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1220 14:47:02.800055 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1221 14:47:02.800334 [Gating] SW calibration Done
1222 14:47:02.800421 ==
1223 14:47:02.800486 Dram Type= 6, Freq= 0, CH_0, rank 1
1224 14:47:02.800546 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1225 14:47:02.800603 ==
1226 14:47:02.800659 RX Vref Scan: 0
1227 14:47:02.800714
1228 14:47:02.800798 RX Vref 0 -> 0, step: 1
1229 14:47:02.800860
1230 14:47:02.800914 RX Delay -130 -> 252, step: 16
1231 14:47:02.800992 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1232 14:47:02.801064 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1233 14:47:02.801175 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1234 14:47:02.801272 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1235 14:47:02.801382 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1236 14:47:02.814085 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1237 14:47:02.814189 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1238 14:47:02.814449 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1239 14:47:02.817266 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1240 14:47:02.820910 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1241 14:47:02.824041 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1242 14:47:02.827542 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1243 14:47:02.830643 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1244 14:47:02.834111 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1245 14:47:02.840534 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1246 14:47:02.843831 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1247 14:47:02.843914 ==
1248 14:47:02.847256 Dram Type= 6, Freq= 0, CH_0, rank 1
1249 14:47:02.850778 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1250 14:47:02.850860 ==
1251 14:47:02.850924 DQS Delay:
1252 14:47:02.854024 DQS0 = 0, DQS1 = 0
1253 14:47:02.854105 DQM Delay:
1254 14:47:02.857711 DQM0 = 82, DQM1 = 74
1255 14:47:02.857792 DQ Delay:
1256 14:47:02.860651 DQ0 =77, DQ1 =85, DQ2 =85, DQ3 =77
1257 14:47:02.863769 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
1258 14:47:02.867184 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1259 14:47:02.870731 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1260 14:47:02.870812
1261 14:47:02.870875
1262 14:47:02.870933 ==
1263 14:47:02.874092 Dram Type= 6, Freq= 0, CH_0, rank 1
1264 14:47:02.877204 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1265 14:47:02.880642 ==
1266 14:47:02.880724
1267 14:47:02.880787
1268 14:47:02.880846 TX Vref Scan disable
1269 14:47:02.884167 == TX Byte 0 ==
1270 14:47:02.887321 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1271 14:47:02.890808 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1272 14:47:02.893783 == TX Byte 1 ==
1273 14:47:02.897183 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1274 14:47:02.900386 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1275 14:47:02.903728 ==
1276 14:47:02.907396 Dram Type= 6, Freq= 0, CH_0, rank 1
1277 14:47:02.910436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1278 14:47:02.910517 ==
1279 14:47:02.923301 TX Vref=22, minBit 12, minWin=27, winSum=447
1280 14:47:02.926559 TX Vref=24, minBit 0, minWin=28, winSum=453
1281 14:47:02.930492 TX Vref=26, minBit 14, minWin=27, winSum=450
1282 14:47:02.933883 TX Vref=28, minBit 2, minWin=28, winSum=457
1283 14:47:02.937536 TX Vref=30, minBit 2, minWin=28, winSum=459
1284 14:47:02.941413 TX Vref=32, minBit 0, minWin=28, winSum=458
1285 14:47:02.948104 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 30
1286 14:47:02.948188
1287 14:47:02.951358 Final TX Range 1 Vref 30
1288 14:47:02.951440
1289 14:47:02.951503 ==
1290 14:47:02.954924 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 14:47:02.958517 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1292 14:47:02.958600 ==
1293 14:47:02.958663
1294 14:47:02.958722
1295 14:47:02.961666 TX Vref Scan disable
1296 14:47:02.961751 == TX Byte 0 ==
1297 14:47:02.968572 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1298 14:47:02.971890 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1299 14:47:02.971972 == TX Byte 1 ==
1300 14:47:02.978513 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1301 14:47:02.982278 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1302 14:47:02.982360
1303 14:47:02.982423 [DATLAT]
1304 14:47:02.985391 Freq=800, CH0 RK1
1305 14:47:02.985472
1306 14:47:02.985535 DATLAT Default: 0x9
1307 14:47:02.988373 0, 0xFFFF, sum = 0
1308 14:47:02.988456 1, 0xFFFF, sum = 0
1309 14:47:02.991966 2, 0xFFFF, sum = 0
1310 14:47:02.992048 3, 0xFFFF, sum = 0
1311 14:47:02.995099 4, 0xFFFF, sum = 0
1312 14:47:02.995182 5, 0xFFFF, sum = 0
1313 14:47:02.998509 6, 0xFFFF, sum = 0
1314 14:47:02.998592 7, 0xFFFF, sum = 0
1315 14:47:03.001922 8, 0x0, sum = 1
1316 14:47:03.002004 9, 0x0, sum = 2
1317 14:47:03.004978 10, 0x0, sum = 3
1318 14:47:03.005060 11, 0x0, sum = 4
1319 14:47:03.008335 best_step = 9
1320 14:47:03.008416
1321 14:47:03.008479 ==
1322 14:47:03.011601 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 14:47:03.014969 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1324 14:47:03.015051 ==
1325 14:47:03.018547 RX Vref Scan: 0
1326 14:47:03.018628
1327 14:47:03.018691 RX Vref 0 -> 0, step: 1
1328 14:47:03.018750
1329 14:47:03.021483 RX Delay -111 -> 252, step: 8
1330 14:47:03.028474 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1331 14:47:03.031677 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1332 14:47:03.035063 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1333 14:47:03.038270 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1334 14:47:03.041711 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1335 14:47:03.048340 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1336 14:47:03.051718 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1337 14:47:03.054976 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1338 14:47:03.058098 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1339 14:47:03.061285 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1340 14:47:03.068080 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1341 14:47:03.071897 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1342 14:47:03.074808 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1343 14:47:03.078052 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1344 14:47:03.081513 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1345 14:47:03.087956 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1346 14:47:03.088038 ==
1347 14:47:03.091277 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 14:47:03.094565 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1349 14:47:03.094647 ==
1350 14:47:03.094711 DQS Delay:
1351 14:47:03.098294 DQS0 = 0, DQS1 = 0
1352 14:47:03.098375 DQM Delay:
1353 14:47:03.101408 DQM0 = 86, DQM1 = 74
1354 14:47:03.101489 DQ Delay:
1355 14:47:03.104546 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =84
1356 14:47:03.108421 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1357 14:47:03.111392 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1358 14:47:03.114729 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
1359 14:47:03.114811
1360 14:47:03.114874
1361 14:47:03.121619 [DQSOSCAuto] RK1, (LSB)MR18= 0x4848, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
1362 14:47:03.124747 CH0 RK1: MR19=606, MR18=4848
1363 14:47:03.131283 CH0_RK1: MR19=0x606, MR18=0x4848, DQSOSC=391, MR23=63, INC=96, DEC=64
1364 14:47:03.134598 [RxdqsGatingPostProcess] freq 800
1365 14:47:03.141197 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1366 14:47:03.144501 Pre-setting of DQS Precalculation
1367 14:47:03.147989 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1368 14:47:03.148070 ==
1369 14:47:03.151445 Dram Type= 6, Freq= 0, CH_1, rank 0
1370 14:47:03.154863 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1371 14:47:03.154945 ==
1372 14:47:03.161462 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1373 14:47:03.167728 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1374 14:47:03.175634 [CA 0] Center 37 (6~68) winsize 63
1375 14:47:03.179143 [CA 1] Center 37 (6~68) winsize 63
1376 14:47:03.182439 [CA 2] Center 34 (4~65) winsize 62
1377 14:47:03.185841 [CA 3] Center 34 (4~65) winsize 62
1378 14:47:03.189285 [CA 4] Center 33 (3~64) winsize 62
1379 14:47:03.192389 [CA 5] Center 33 (3~64) winsize 62
1380 14:47:03.192469
1381 14:47:03.196040 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1382 14:47:03.196120
1383 14:47:03.198952 [CATrainingPosCal] consider 1 rank data
1384 14:47:03.202164 u2DelayCellTimex100 = 270/100 ps
1385 14:47:03.205836 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1386 14:47:03.208904 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1387 14:47:03.215831 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1388 14:47:03.219128 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1389 14:47:03.222457 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1390 14:47:03.225563 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1391 14:47:03.225644
1392 14:47:03.228980 CA PerBit enable=1, Macro0, CA PI delay=33
1393 14:47:03.229061
1394 14:47:03.232346 [CBTSetCACLKResult] CA Dly = 33
1395 14:47:03.232427 CS Dly: 5 (0~36)
1396 14:47:03.235557 ==
1397 14:47:03.235638 Dram Type= 6, Freq= 0, CH_1, rank 1
1398 14:47:03.242415 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1399 14:47:03.242498 ==
1400 14:47:03.245654 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1401 14:47:03.252770 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1402 14:47:03.261691 [CA 0] Center 36 (6~67) winsize 62
1403 14:47:03.264966 [CA 1] Center 37 (6~68) winsize 63
1404 14:47:03.268472 [CA 2] Center 34 (4~65) winsize 62
1405 14:47:03.271672 [CA 3] Center 34 (4~65) winsize 62
1406 14:47:03.274947 [CA 4] Center 33 (3~64) winsize 62
1407 14:47:03.278572 [CA 5] Center 33 (3~64) winsize 62
1408 14:47:03.278652
1409 14:47:03.281752 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1410 14:47:03.281833
1411 14:47:03.285173 [CATrainingPosCal] consider 2 rank data
1412 14:47:03.288347 u2DelayCellTimex100 = 270/100 ps
1413 14:47:03.291876 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1414 14:47:03.295209 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1415 14:47:03.298511 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1416 14:47:03.305038 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1417 14:47:03.308443 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1418 14:47:03.311621 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1419 14:47:03.311703
1420 14:47:03.318394 CA PerBit enable=1, Macro0, CA PI delay=33
1421 14:47:03.318476
1422 14:47:03.318725 [CBTSetCACLKResult] CA Dly = 33
1423 14:47:03.318794 CS Dly: 5 (0~36)
1424 14:47:03.318853
1425 14:47:03.321752 ----->DramcWriteLeveling(PI) begin...
1426 14:47:03.321835 ==
1427 14:47:03.325022 Dram Type= 6, Freq= 0, CH_1, rank 0
1428 14:47:03.331522 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1429 14:47:03.331604 ==
1430 14:47:03.334910 Write leveling (Byte 0): 24 => 24
1431 14:47:03.338352 Write leveling (Byte 1): 27 => 27
1432 14:47:03.341510 DramcWriteLeveling(PI) end<-----
1433 14:47:03.341600
1434 14:47:03.341664 ==
1435 14:47:03.345134 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 14:47:03.348468 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1437 14:47:03.348550 ==
1438 14:47:03.351558 [Gating] SW mode calibration
1439 14:47:03.358474 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1440 14:47:03.361662 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1441 14:47:03.368288 0 6 0 | B1->B0 | 3030 2525 | 0 0 | (0 1) (0 0)
1442 14:47:03.371551 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 14:47:03.374914 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 14:47:03.381487 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 14:47:03.384814 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 14:47:03.388376 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 14:47:03.395339 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 14:47:03.398593 0 6 28 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
1449 14:47:03.401567 0 7 0 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
1450 14:47:03.408113 0 7 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1451 14:47:03.411557 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1452 14:47:03.414715 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1453 14:47:03.421956 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1454 14:47:03.424719 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1455 14:47:03.428046 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1456 14:47:03.435215 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1457 14:47:03.438061 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1458 14:47:03.441689 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1459 14:47:03.444891 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 14:47:03.451847 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 14:47:03.454745 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 14:47:03.458118 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 14:47:03.464716 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1464 14:47:03.468739 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1465 14:47:03.471707 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1466 14:47:03.478236 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1467 14:47:03.481234 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1468 14:47:03.484582 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1469 14:47:03.491433 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1470 14:47:03.494949 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1471 14:47:03.498169 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1472 14:47:03.504771 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1473 14:47:03.508111 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1474 14:47:03.511338 Total UI for P1: 0, mck2ui 16
1475 14:47:03.515246 best dqsien dly found for B1: ( 0, 9, 30)
1476 14:47:03.517896 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1477 14:47:03.521320 Total UI for P1: 0, mck2ui 16
1478 14:47:03.524666 best dqsien dly found for B0: ( 0, 10, 0)
1479 14:47:03.528076 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1480 14:47:03.531439 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1481 14:47:03.531535
1482 14:47:03.537989 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1483 14:47:03.541922 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1484 14:47:03.542023 [Gating] SW calibration Done
1485 14:47:03.544473 ==
1486 14:47:03.544549 Dram Type= 6, Freq= 0, CH_1, rank 0
1487 14:47:03.551392 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1488 14:47:03.551494 ==
1489 14:47:03.551584 RX Vref Scan: 0
1490 14:47:03.551666
1491 14:47:03.554763 RX Vref 0 -> 0, step: 1
1492 14:47:03.554833
1493 14:47:03.557906 RX Delay -130 -> 252, step: 16
1494 14:47:03.561206 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1495 14:47:03.564472 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1496 14:47:03.567929 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1497 14:47:03.574911 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1498 14:47:03.578050 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1499 14:47:03.581111 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1500 14:47:03.584825 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1501 14:47:03.588107 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1502 14:47:03.591912 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1503 14:47:03.598999 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1504 14:47:03.603067 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1505 14:47:03.606014 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1506 14:47:03.609844 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1507 14:47:03.613349 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1508 14:47:03.616552 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1509 14:47:03.620295 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1510 14:47:03.624186 ==
1511 14:47:03.624267 Dram Type= 6, Freq= 0, CH_1, rank 0
1512 14:47:03.630533 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1513 14:47:03.630615 ==
1514 14:47:03.630678 DQS Delay:
1515 14:47:03.633917 DQS0 = 0, DQS1 = 0
1516 14:47:03.633998 DQM Delay:
1517 14:47:03.634060 DQM0 = 81, DQM1 = 72
1518 14:47:03.637148 DQ Delay:
1519 14:47:03.640554 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1520 14:47:03.643936 DQ4 =77, DQ5 =101, DQ6 =85, DQ7 =77
1521 14:47:03.647158 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1522 14:47:03.650920 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =85
1523 14:47:03.651001
1524 14:47:03.651065
1525 14:47:03.651124 ==
1526 14:47:03.653820 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 14:47:03.657350 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1528 14:47:03.657432 ==
1529 14:47:03.657496
1530 14:47:03.657554
1531 14:47:03.660524 TX Vref Scan disable
1532 14:47:03.660605 == TX Byte 0 ==
1533 14:47:03.667193 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1534 14:47:03.670379 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1535 14:47:03.670460 == TX Byte 1 ==
1536 14:47:03.677598 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1537 14:47:03.680686 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1538 14:47:03.680767 ==
1539 14:47:03.684020 Dram Type= 6, Freq= 0, CH_1, rank 0
1540 14:47:03.687103 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1541 14:47:03.687184 ==
1542 14:47:03.701767 TX Vref=22, minBit 3, minWin=27, winSum=444
1543 14:47:03.704738 TX Vref=24, minBit 9, minWin=27, winSum=448
1544 14:47:03.708323 TX Vref=26, minBit 0, minWin=28, winSum=452
1545 14:47:03.711374 TX Vref=28, minBit 0, minWin=28, winSum=455
1546 14:47:03.715062 TX Vref=30, minBit 0, minWin=28, winSum=459
1547 14:47:03.718293 TX Vref=32, minBit 9, minWin=27, winSum=458
1548 14:47:03.724770 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 30
1549 14:47:03.724876
1550 14:47:03.728069 Final TX Range 1 Vref 30
1551 14:47:03.728145
1552 14:47:03.728211 ==
1553 14:47:03.731512 Dram Type= 6, Freq= 0, CH_1, rank 0
1554 14:47:03.734973 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1555 14:47:03.735072 ==
1556 14:47:03.735162
1557 14:47:03.738116
1558 14:47:03.738217 TX Vref Scan disable
1559 14:47:03.741245 == TX Byte 0 ==
1560 14:47:03.744864 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1561 14:47:03.748119 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1562 14:47:03.751611 == TX Byte 1 ==
1563 14:47:03.754656 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1564 14:47:03.761259 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1565 14:47:03.761377
1566 14:47:03.761441 [DATLAT]
1567 14:47:03.761500 Freq=800, CH1 RK0
1568 14:47:03.761557
1569 14:47:03.764540 DATLAT Default: 0xa
1570 14:47:03.764621 0, 0xFFFF, sum = 0
1571 14:47:03.768011 1, 0xFFFF, sum = 0
1572 14:47:03.768094 2, 0xFFFF, sum = 0
1573 14:47:03.771314 3, 0xFFFF, sum = 0
1574 14:47:03.771396 4, 0xFFFF, sum = 0
1575 14:47:03.774538 5, 0xFFFF, sum = 0
1576 14:47:03.777835 6, 0xFFFF, sum = 0
1577 14:47:03.777918 7, 0xFFFF, sum = 0
1578 14:47:03.777982 8, 0x0, sum = 1
1579 14:47:03.781583 9, 0x0, sum = 2
1580 14:47:03.781666 10, 0x0, sum = 3
1581 14:47:03.784802 11, 0x0, sum = 4
1582 14:47:03.784885 best_step = 9
1583 14:47:03.784948
1584 14:47:03.785008 ==
1585 14:47:03.788132 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 14:47:03.794411 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1587 14:47:03.794492 ==
1588 14:47:03.794556 RX Vref Scan: 1
1589 14:47:03.794615
1590 14:47:03.797964 Set Vref Range= 32 -> 127
1591 14:47:03.798045
1592 14:47:03.801148 RX Vref 32 -> 127, step: 1
1593 14:47:03.801228
1594 14:47:03.804823 RX Delay -111 -> 252, step: 8
1595 14:47:03.804904
1596 14:47:03.804967 Set Vref, RX VrefLevel [Byte0]: 32
1597 14:47:03.807939 [Byte1]: 32
1598 14:47:03.812295
1599 14:47:03.812376 Set Vref, RX VrefLevel [Byte0]: 33
1600 14:47:03.816050 [Byte1]: 33
1601 14:47:03.819909
1602 14:47:03.819989 Set Vref, RX VrefLevel [Byte0]: 34
1603 14:47:03.823561 [Byte1]: 34
1604 14:47:03.828067
1605 14:47:03.828148 Set Vref, RX VrefLevel [Byte0]: 35
1606 14:47:03.831053 [Byte1]: 35
1607 14:47:03.835311
1608 14:47:03.835391 Set Vref, RX VrefLevel [Byte0]: 36
1609 14:47:03.838676 [Byte1]: 36
1610 14:47:03.843052
1611 14:47:03.843132 Set Vref, RX VrefLevel [Byte0]: 37
1612 14:47:03.846285 [Byte1]: 37
1613 14:47:03.850612
1614 14:47:03.850692 Set Vref, RX VrefLevel [Byte0]: 38
1615 14:47:03.854073 [Byte1]: 38
1616 14:47:03.858252
1617 14:47:03.858332 Set Vref, RX VrefLevel [Byte0]: 39
1618 14:47:03.861330 [Byte1]: 39
1619 14:47:03.866417
1620 14:47:03.866498 Set Vref, RX VrefLevel [Byte0]: 40
1621 14:47:03.869508 [Byte1]: 40
1622 14:47:03.873564
1623 14:47:03.873645 Set Vref, RX VrefLevel [Byte0]: 41
1624 14:47:03.877018 [Byte1]: 41
1625 14:47:03.881195
1626 14:47:03.881276 Set Vref, RX VrefLevel [Byte0]: 42
1627 14:47:03.884506 [Byte1]: 42
1628 14:47:03.888921
1629 14:47:03.889010 Set Vref, RX VrefLevel [Byte0]: 43
1630 14:47:03.892124 [Byte1]: 43
1631 14:47:03.896851
1632 14:47:03.896950 Set Vref, RX VrefLevel [Byte0]: 44
1633 14:47:03.899658 [Byte1]: 44
1634 14:47:03.904209
1635 14:47:03.904289 Set Vref, RX VrefLevel [Byte0]: 45
1636 14:47:03.907213 [Byte1]: 45
1637 14:47:03.911580
1638 14:47:03.911660 Set Vref, RX VrefLevel [Byte0]: 46
1639 14:47:03.915076 [Byte1]: 46
1640 14:47:03.919260
1641 14:47:03.919340 Set Vref, RX VrefLevel [Byte0]: 47
1642 14:47:03.922605 [Byte1]: 47
1643 14:47:03.927128
1644 14:47:03.927209 Set Vref, RX VrefLevel [Byte0]: 48
1645 14:47:03.930331 [Byte1]: 48
1646 14:47:03.934642
1647 14:47:03.934722 Set Vref, RX VrefLevel [Byte0]: 49
1648 14:47:03.938248 [Byte1]: 49
1649 14:47:03.942276
1650 14:47:03.942377 Set Vref, RX VrefLevel [Byte0]: 50
1651 14:47:03.945775 [Byte1]: 50
1652 14:47:03.951066
1653 14:47:03.951171 Set Vref, RX VrefLevel [Byte0]: 51
1654 14:47:03.953213 [Byte1]: 51
1655 14:47:03.957782
1656 14:47:03.957884 Set Vref, RX VrefLevel [Byte0]: 52
1657 14:47:03.960913 [Byte1]: 52
1658 14:47:03.965344
1659 14:47:03.965413 Set Vref, RX VrefLevel [Byte0]: 53
1660 14:47:03.968617 [Byte1]: 53
1661 14:47:03.973057
1662 14:47:03.973153 Set Vref, RX VrefLevel [Byte0]: 54
1663 14:47:03.976571 [Byte1]: 54
1664 14:47:03.980856
1665 14:47:03.980954 Set Vref, RX VrefLevel [Byte0]: 55
1666 14:47:03.983790 [Byte1]: 55
1667 14:47:03.988227
1668 14:47:03.988324 Set Vref, RX VrefLevel [Byte0]: 56
1669 14:47:03.991758 [Byte1]: 56
1670 14:47:03.996061
1671 14:47:03.996160 Set Vref, RX VrefLevel [Byte0]: 57
1672 14:47:03.999183 [Byte1]: 57
1673 14:47:04.003725
1674 14:47:04.003828 Set Vref, RX VrefLevel [Byte0]: 58
1675 14:47:04.006732 [Byte1]: 58
1676 14:47:04.011442
1677 14:47:04.011540 Set Vref, RX VrefLevel [Byte0]: 59
1678 14:47:04.014781 [Byte1]: 59
1679 14:47:04.018936
1680 14:47:04.019008 Set Vref, RX VrefLevel [Byte0]: 60
1681 14:47:04.022480 [Byte1]: 60
1682 14:47:04.026350
1683 14:47:04.026450 Set Vref, RX VrefLevel [Byte0]: 61
1684 14:47:04.029788 [Byte1]: 61
1685 14:47:04.034167
1686 14:47:04.034242 Set Vref, RX VrefLevel [Byte0]: 62
1687 14:47:04.037408 [Byte1]: 62
1688 14:47:04.041661
1689 14:47:04.041758 Set Vref, RX VrefLevel [Byte0]: 63
1690 14:47:04.045065 [Byte1]: 63
1691 14:47:04.049270
1692 14:47:04.049410 Set Vref, RX VrefLevel [Byte0]: 64
1693 14:47:04.052669 [Byte1]: 64
1694 14:47:04.056855
1695 14:47:04.056954 Set Vref, RX VrefLevel [Byte0]: 65
1696 14:47:04.060369 [Byte1]: 65
1697 14:47:04.064622
1698 14:47:04.064721 Set Vref, RX VrefLevel [Byte0]: 66
1699 14:47:04.068200 [Byte1]: 66
1700 14:47:04.072415
1701 14:47:04.072498 Set Vref, RX VrefLevel [Byte0]: 67
1702 14:47:04.075946 [Byte1]: 67
1703 14:47:04.080057
1704 14:47:04.080155 Set Vref, RX VrefLevel [Byte0]: 68
1705 14:47:04.083410 [Byte1]: 68
1706 14:47:04.087938
1707 14:47:04.088038 Set Vref, RX VrefLevel [Byte0]: 69
1708 14:47:04.090852 [Byte1]: 69
1709 14:47:04.095358
1710 14:47:04.095431 Set Vref, RX VrefLevel [Byte0]: 70
1711 14:47:04.098920 [Byte1]: 70
1712 14:47:04.103060
1713 14:47:04.103159 Set Vref, RX VrefLevel [Byte0]: 71
1714 14:47:04.106182 [Byte1]: 71
1715 14:47:04.110712
1716 14:47:04.110808 Set Vref, RX VrefLevel [Byte0]: 72
1717 14:47:04.113923 [Byte1]: 72
1718 14:47:04.118535
1719 14:47:04.118609 Set Vref, RX VrefLevel [Byte0]: 73
1720 14:47:04.121409 [Byte1]: 73
1721 14:47:04.125765
1722 14:47:04.125837 Set Vref, RX VrefLevel [Byte0]: 74
1723 14:47:04.129138 [Byte1]: 74
1724 14:47:04.133460
1725 14:47:04.133531 Set Vref, RX VrefLevel [Byte0]: 75
1726 14:47:04.136748 [Byte1]: 75
1727 14:47:04.141110
1728 14:47:04.141193 Set Vref, RX VrefLevel [Byte0]: 76
1729 14:47:04.144597 [Byte1]: 76
1730 14:47:04.148920
1731 14:47:04.149002 Final RX Vref Byte 0 = 59 to rank0
1732 14:47:04.152087 Final RX Vref Byte 1 = 56 to rank0
1733 14:47:04.155514 Final RX Vref Byte 0 = 59 to rank1
1734 14:47:04.158778 Final RX Vref Byte 1 = 56 to rank1==
1735 14:47:04.162059 Dram Type= 6, Freq= 0, CH_1, rank 0
1736 14:47:04.169437 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1737 14:47:04.169519 ==
1738 14:47:04.169583 DQS Delay:
1739 14:47:04.169707 DQS0 = 0, DQS1 = 0
1740 14:47:04.172731 DQM Delay:
1741 14:47:04.172811 DQM0 = 81, DQM1 = 75
1742 14:47:04.172875 DQ Delay:
1743 14:47:04.176154 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1744 14:47:04.179573 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1745 14:47:04.182827 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1746 14:47:04.186272 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1747 14:47:04.186353
1748 14:47:04.186415
1749 14:47:04.196210 [DQSOSCAuto] RK0, (LSB)MR18= 0x5454, (MSB)MR19= 0x606, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
1750 14:47:04.199415 CH1 RK0: MR19=606, MR18=5454
1751 14:47:04.202702 CH1_RK0: MR19=0x606, MR18=0x5454, DQSOSC=388, MR23=63, INC=98, DEC=65
1752 14:47:04.206085
1753 14:47:04.209254 ----->DramcWriteLeveling(PI) begin...
1754 14:47:04.209372 ==
1755 14:47:04.212978 Dram Type= 6, Freq= 0, CH_1, rank 1
1756 14:47:04.216054 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1757 14:47:04.216136 ==
1758 14:47:04.219207 Write leveling (Byte 0): 24 => 24
1759 14:47:04.222887 Write leveling (Byte 1): 23 => 23
1760 14:47:04.225985 DramcWriteLeveling(PI) end<-----
1761 14:47:04.226066
1762 14:47:04.226132 ==
1763 14:47:04.229557 Dram Type= 6, Freq= 0, CH_1, rank 1
1764 14:47:04.232517 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1765 14:47:04.232598 ==
1766 14:47:04.236499 [Gating] SW mode calibration
1767 14:47:04.242683 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1768 14:47:04.249193 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1769 14:47:04.252564 0 6 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
1770 14:47:04.255969 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1771 14:47:04.263036 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1772 14:47:04.266053 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1773 14:47:04.269605 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1774 14:47:04.272769 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1775 14:47:04.279369 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1776 14:47:04.282780 0 6 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1777 14:47:04.286006 0 7 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
1778 14:47:04.292622 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1779 14:47:04.295981 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1780 14:47:04.299340 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1781 14:47:04.306101 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1782 14:47:04.309266 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1783 14:47:04.312457 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1784 14:47:04.319425 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1785 14:47:04.322743 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1786 14:47:04.326002 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1787 14:47:04.332541 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1788 14:47:04.336102 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1789 14:47:04.339583 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1790 14:47:04.346094 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1791 14:47:04.349154 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1792 14:47:04.352410 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1793 14:47:04.359256 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1794 14:47:04.362666 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1795 14:47:04.365842 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1796 14:47:04.372716 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1797 14:47:04.375798 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1798 14:47:04.379143 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1799 14:47:04.382776 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1800 14:47:04.388988 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1801 14:47:04.392480 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1802 14:47:04.395895 Total UI for P1: 0, mck2ui 16
1803 14:47:04.399088 best dqsien dly found for B0: ( 0, 9, 28)
1804 14:47:04.402474 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1805 14:47:04.409175 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1806 14:47:04.412667 Total UI for P1: 0, mck2ui 16
1807 14:47:04.416227 best dqsien dly found for B1: ( 0, 10, 2)
1808 14:47:04.419054 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1809 14:47:04.422267 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1810 14:47:04.422348
1811 14:47:04.425526 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1812 14:47:04.428903 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1813 14:47:04.432658 [Gating] SW calibration Done
1814 14:47:04.432738 ==
1815 14:47:04.436117 Dram Type= 6, Freq= 0, CH_1, rank 1
1816 14:47:04.439276 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1817 14:47:04.439358 ==
1818 14:47:04.442660 RX Vref Scan: 0
1819 14:47:04.442741
1820 14:47:04.442805 RX Vref 0 -> 0, step: 1
1821 14:47:04.442864
1822 14:47:04.445678 RX Delay -130 -> 252, step: 16
1823 14:47:04.452812 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1824 14:47:04.455895 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1825 14:47:04.459045 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1826 14:47:04.462606 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1827 14:47:04.465520 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1828 14:47:04.471967 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1829 14:47:04.475619 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1830 14:47:04.478971 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1831 14:47:04.482175 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1832 14:47:04.485586 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1833 14:47:04.492073 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1834 14:47:04.495562 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1835 14:47:04.498778 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1836 14:47:04.501968 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1837 14:47:04.505462 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1838 14:47:04.512103 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1839 14:47:04.512205 ==
1840 14:47:04.515232 Dram Type= 6, Freq= 0, CH_1, rank 1
1841 14:47:04.518582 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1842 14:47:04.518681 ==
1843 14:47:04.518770 DQS Delay:
1844 14:47:04.522028 DQS0 = 0, DQS1 = 0
1845 14:47:04.522123 DQM Delay:
1846 14:47:04.525228 DQM0 = 84, DQM1 = 72
1847 14:47:04.525325 DQ Delay:
1848 14:47:04.528776 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1849 14:47:04.531940 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1850 14:47:04.534972 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =61
1851 14:47:04.538478 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1852 14:47:04.538566
1853 14:47:04.538627
1854 14:47:04.538684 ==
1855 14:47:04.541762 Dram Type= 6, Freq= 0, CH_1, rank 1
1856 14:47:04.545214 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1857 14:47:04.545352 ==
1858 14:47:04.548448
1859 14:47:04.548529
1860 14:47:04.548593 TX Vref Scan disable
1861 14:47:04.552074 == TX Byte 0 ==
1862 14:47:04.555131 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1863 14:47:04.558866 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1864 14:47:04.561826 == TX Byte 1 ==
1865 14:47:04.565246 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1866 14:47:04.568721 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1867 14:47:04.568802 ==
1868 14:47:04.572097 Dram Type= 6, Freq= 0, CH_1, rank 1
1869 14:47:04.578667 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1870 14:47:04.578753 ==
1871 14:47:04.590248 TX Vref=22, minBit 0, minWin=28, winSum=452
1872 14:47:04.593866 TX Vref=24, minBit 0, minWin=28, winSum=453
1873 14:47:04.596810 TX Vref=26, minBit 0, minWin=28, winSum=457
1874 14:47:04.600078 TX Vref=28, minBit 0, minWin=28, winSum=457
1875 14:47:04.603516 TX Vref=30, minBit 0, minWin=28, winSum=458
1876 14:47:04.610576 TX Vref=32, minBit 0, minWin=28, winSum=456
1877 14:47:04.613716 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 30
1878 14:47:04.613798
1879 14:47:04.616655 Final TX Range 1 Vref 30
1880 14:47:04.616736
1881 14:47:04.616799 ==
1882 14:47:04.620048 Dram Type= 6, Freq= 0, CH_1, rank 1
1883 14:47:04.623311 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1884 14:47:04.623393 ==
1885 14:47:04.626743
1886 14:47:04.626824
1887 14:47:04.626887 TX Vref Scan disable
1888 14:47:04.630152 == TX Byte 0 ==
1889 14:47:04.633506 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1890 14:47:04.637046 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1891 14:47:04.640690 == TX Byte 1 ==
1892 14:47:04.643610 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1893 14:47:04.647088 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1894 14:47:04.650421
1895 14:47:04.650521 [DATLAT]
1896 14:47:04.650611 Freq=800, CH1 RK1
1897 14:47:04.650698
1898 14:47:04.653653 DATLAT Default: 0x9
1899 14:47:04.653752 0, 0xFFFF, sum = 0
1900 14:47:04.656751 1, 0xFFFF, sum = 0
1901 14:47:04.656855 2, 0xFFFF, sum = 0
1902 14:47:04.660485 3, 0xFFFF, sum = 0
1903 14:47:04.660565 4, 0xFFFF, sum = 0
1904 14:47:04.663272 5, 0xFFFF, sum = 0
1905 14:47:04.666917 6, 0xFFFF, sum = 0
1906 14:47:04.667020 7, 0xFFFF, sum = 0
1907 14:47:04.667112 8, 0x0, sum = 1
1908 14:47:04.670098 9, 0x0, sum = 2
1909 14:47:04.670170 10, 0x0, sum = 3
1910 14:47:04.673278 11, 0x0, sum = 4
1911 14:47:04.673357 best_step = 9
1912 14:47:04.673416
1913 14:47:04.673476 ==
1914 14:47:04.676479 Dram Type= 6, Freq= 0, CH_1, rank 1
1915 14:47:04.683649 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1916 14:47:04.683749 ==
1917 14:47:04.683841 RX Vref Scan: 0
1918 14:47:04.683927
1919 14:47:04.686755 RX Vref 0 -> 0, step: 1
1920 14:47:04.686851
1921 14:47:04.690033 RX Delay -111 -> 252, step: 8
1922 14:47:04.693600 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1923 14:47:04.696558 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1924 14:47:04.703488 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1925 14:47:04.707157 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1926 14:47:04.710208 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1927 14:47:04.713393 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1928 14:47:04.716905 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1929 14:47:04.723300 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1930 14:47:04.726735 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1931 14:47:04.730240 iDelay=217, Bit 9, Center 64 (-55 ~ 184) 240
1932 14:47:04.733350 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1933 14:47:04.736740 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1934 14:47:04.743602 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1935 14:47:04.746496 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1936 14:47:04.750016 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1937 14:47:04.753482 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1938 14:47:04.753572 ==
1939 14:47:04.756781 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 14:47:04.760115 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1941 14:47:04.763275 ==
1942 14:47:04.763349 DQS Delay:
1943 14:47:04.763410 DQS0 = 0, DQS1 = 0
1944 14:47:04.766885 DQM Delay:
1945 14:47:04.766958 DQM0 = 83, DQM1 = 74
1946 14:47:04.770124 DQ Delay:
1947 14:47:04.773199 DQ0 =84, DQ1 =76, DQ2 =76, DQ3 =80
1948 14:47:04.773318 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =80
1949 14:47:04.776619 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1950 14:47:04.779930 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1951 14:47:04.783292
1952 14:47:04.783366
1953 14:47:04.790041 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1954 14:47:04.793321 CH1 RK1: MR19=606, MR18=3A3A
1955 14:47:04.799942 CH1_RK1: MR19=0x606, MR18=0x3A3A, DQSOSC=395, MR23=63, INC=94, DEC=63
1956 14:47:04.803592 [RxdqsGatingPostProcess] freq 800
1957 14:47:04.806632 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1958 14:47:04.810225 Pre-setting of DQS Precalculation
1959 14:47:04.816575 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1960 14:47:04.823510 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1961 14:47:04.830232 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1962 14:47:04.830307
1963 14:47:04.830370
1964 14:47:04.833137 [Calibration Summary] 1600 Mbps
1965 14:47:04.833232 CH 0, Rank 0
1966 14:47:04.836788 SW Impedance : PASS
1967 14:47:04.836883 DUTY Scan : NO K
1968 14:47:04.840090 ZQ Calibration : PASS
1969 14:47:04.843076 Jitter Meter : NO K
1970 14:47:04.843173 CBT Training : PASS
1971 14:47:04.846431 Write leveling : PASS
1972 14:47:04.850055 RX DQS gating : PASS
1973 14:47:04.850154 RX DQ/DQS(RDDQC) : PASS
1974 14:47:04.853208 TX DQ/DQS : PASS
1975 14:47:04.856684 RX DATLAT : PASS
1976 14:47:04.856783 RX DQ/DQS(Engine): PASS
1977 14:47:04.859629 TX OE : NO K
1978 14:47:04.859729 All Pass.
1979 14:47:04.859816
1980 14:47:04.863443 CH 0, Rank 1
1981 14:47:04.863542 SW Impedance : PASS
1982 14:47:04.866207 DUTY Scan : NO K
1983 14:47:04.869584 ZQ Calibration : PASS
1984 14:47:04.869657 Jitter Meter : NO K
1985 14:47:04.873005 CBT Training : PASS
1986 14:47:04.876212 Write leveling : PASS
1987 14:47:04.876310 RX DQS gating : PASS
1988 14:47:04.879572 RX DQ/DQS(RDDQC) : PASS
1989 14:47:04.879669 TX DQ/DQS : PASS
1990 14:47:04.883133 RX DATLAT : PASS
1991 14:47:04.886151 RX DQ/DQS(Engine): PASS
1992 14:47:04.886225 TX OE : NO K
1993 14:47:04.889889 All Pass.
1994 14:47:04.889960
1995 14:47:04.890020 CH 1, Rank 0
1996 14:47:04.892875 SW Impedance : PASS
1997 14:47:04.892972 DUTY Scan : NO K
1998 14:47:04.896158 ZQ Calibration : PASS
1999 14:47:04.899373 Jitter Meter : NO K
2000 14:47:04.899445 CBT Training : PASS
2001 14:47:04.903054 Write leveling : PASS
2002 14:47:04.906396 RX DQS gating : PASS
2003 14:47:04.906494 RX DQ/DQS(RDDQC) : PASS
2004 14:47:04.909582 TX DQ/DQS : PASS
2005 14:47:04.912797 RX DATLAT : PASS
2006 14:47:04.912895 RX DQ/DQS(Engine): PASS
2007 14:47:04.916164 TX OE : NO K
2008 14:47:04.916260 All Pass.
2009 14:47:04.916350
2010 14:47:04.920002 CH 1, Rank 1
2011 14:47:04.920097 SW Impedance : PASS
2012 14:47:04.923000 DUTY Scan : NO K
2013 14:47:04.926050 ZQ Calibration : PASS
2014 14:47:04.926147 Jitter Meter : NO K
2015 14:47:04.929479 CBT Training : PASS
2016 14:47:04.932808 Write leveling : PASS
2017 14:47:04.932905 RX DQS gating : PASS
2018 14:47:04.936062 RX DQ/DQS(RDDQC) : PASS
2019 14:47:04.936157 TX DQ/DQS : PASS
2020 14:47:04.939382 RX DATLAT : PASS
2021 14:47:04.942639 RX DQ/DQS(Engine): PASS
2022 14:47:04.942735 TX OE : NO K
2023 14:47:04.946292 All Pass.
2024 14:47:04.946393
2025 14:47:04.946482 DramC Write-DBI off
2026 14:47:04.949472 PER_BANK_REFRESH: Hybrid Mode
2027 14:47:04.952772 TX_TRACKING: ON
2028 14:47:04.956250 [GetDramInforAfterCalByMRR] Vendor 6.
2029 14:47:04.959304 [GetDramInforAfterCalByMRR] Revision 606.
2030 14:47:04.962769 [GetDramInforAfterCalByMRR] Revision 2 0.
2031 14:47:04.962842 MR0 0x3939
2032 14:47:04.962933 MR8 0x1111
2033 14:47:04.966092 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2034 14:47:04.969412
2035 14:47:04.969512 MR0 0x3939
2036 14:47:04.969604 MR8 0x1111
2037 14:47:04.973021 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2038 14:47:04.973115
2039 14:47:04.982806 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2040 14:47:04.986251 [FAST_K] Save calibration result to emmc
2041 14:47:04.989695 [FAST_K] Save calibration result to emmc
2042 14:47:04.992923 dram_init: config_dvfs: 1
2043 14:47:04.996203 dramc_set_vcore_voltage set vcore to 662500
2044 14:47:04.999802 Read voltage for 1200, 2
2045 14:47:04.999902 Vio18 = 0
2046 14:47:04.999994 Vcore = 662500
2047 14:47:05.002667 Vdram = 0
2048 14:47:05.002753 Vddq = 0
2049 14:47:05.002815 Vmddr = 0
2050 14:47:05.009580 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2051 14:47:05.012959 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2052 14:47:05.016299 MEM_TYPE=3, freq_sel=15
2053 14:47:05.019435 sv_algorithm_assistance_LP4_1600
2054 14:47:05.022811 ============ PULL DRAM RESETB DOWN ============
2055 14:47:05.026081 ========== PULL DRAM RESETB DOWN end =========
2056 14:47:05.033018 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2057 14:47:05.035947 ===================================
2058 14:47:05.036043 LPDDR4 DRAM CONFIGURATION
2059 14:47:05.039401 ===================================
2060 14:47:05.042626 EX_ROW_EN[0] = 0x0
2061 14:47:05.046040 EX_ROW_EN[1] = 0x0
2062 14:47:05.046114 LP4Y_EN = 0x0
2063 14:47:05.049433 WORK_FSP = 0x0
2064 14:47:05.049504 WL = 0x4
2065 14:47:05.052533 RL = 0x4
2066 14:47:05.052605 BL = 0x2
2067 14:47:05.055976 RPST = 0x0
2068 14:47:05.056072 RD_PRE = 0x0
2069 14:47:05.059806 WR_PRE = 0x1
2070 14:47:05.059914 WR_PST = 0x0
2071 14:47:05.063447 DBI_WR = 0x0
2072 14:47:05.063548 DBI_RD = 0x0
2073 14:47:05.066225 OTF = 0x1
2074 14:47:05.069818 ===================================
2075 14:47:05.073099 ===================================
2076 14:47:05.073199 ANA top config
2077 14:47:05.076229 ===================================
2078 14:47:05.079768 DLL_ASYNC_EN = 0
2079 14:47:05.082866 ALL_SLAVE_EN = 0
2080 14:47:05.083008 NEW_RANK_MODE = 1
2081 14:47:05.086225 DLL_IDLE_MODE = 1
2082 14:47:05.089441 LP45_APHY_COMB_EN = 1
2083 14:47:05.093196 TX_ODT_DIS = 1
2084 14:47:05.096181 NEW_8X_MODE = 1
2085 14:47:05.099406 ===================================
2086 14:47:05.103115 ===================================
2087 14:47:05.103217 data_rate = 2400
2088 14:47:05.106170 CKR = 1
2089 14:47:05.109499 DQ_P2S_RATIO = 8
2090 14:47:05.112752 ===================================
2091 14:47:05.116317 CA_P2S_RATIO = 8
2092 14:47:05.119517 DQ_CA_OPEN = 0
2093 14:47:05.122636 DQ_SEMI_OPEN = 0
2094 14:47:05.122739 CA_SEMI_OPEN = 0
2095 14:47:05.126000 CA_FULL_RATE = 0
2096 14:47:05.129108 DQ_CKDIV4_EN = 0
2097 14:47:05.132706 CA_CKDIV4_EN = 0
2098 14:47:05.135798 CA_PREDIV_EN = 0
2099 14:47:05.139424 PH8_DLY = 17
2100 14:47:05.139527 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2101 14:47:05.142719 DQ_AAMCK_DIV = 4
2102 14:47:05.146174 CA_AAMCK_DIV = 4
2103 14:47:05.149374 CA_ADMCK_DIV = 4
2104 14:47:05.152914 DQ_TRACK_CA_EN = 0
2105 14:47:05.155897 CA_PICK = 1200
2106 14:47:05.159097 CA_MCKIO = 1200
2107 14:47:05.159201 MCKIO_SEMI = 0
2108 14:47:05.162528 PLL_FREQ = 2366
2109 14:47:05.166003 DQ_UI_PI_RATIO = 32
2110 14:47:05.169298 CA_UI_PI_RATIO = 0
2111 14:47:05.172576 ===================================
2112 14:47:05.175668 ===================================
2113 14:47:05.179361 memory_type:LPDDR4
2114 14:47:05.179464 GP_NUM : 10
2115 14:47:05.182492 SRAM_EN : 1
2116 14:47:05.185966 MD32_EN : 0
2117 14:47:05.189448 ===================================
2118 14:47:05.189522 [ANA_INIT] >>>>>>>>>>>>>>
2119 14:47:05.192266 <<<<<< [CONFIGURE PHASE]: ANA_TX
2120 14:47:05.196037 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2121 14:47:05.199332 ===================================
2122 14:47:05.202427 data_rate = 2400,PCW = 0X5b00
2123 14:47:05.205812 ===================================
2124 14:47:05.209091 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2125 14:47:05.215636 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2126 14:47:05.218963 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2127 14:47:05.225654 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2128 14:47:05.228999 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2129 14:47:05.232333 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2130 14:47:05.232433 [ANA_INIT] flow start
2131 14:47:05.235603 [ANA_INIT] PLL >>>>>>>>
2132 14:47:05.238845 [ANA_INIT] PLL <<<<<<<<
2133 14:47:05.242402 [ANA_INIT] MIDPI >>>>>>>>
2134 14:47:05.242488 [ANA_INIT] MIDPI <<<<<<<<
2135 14:47:05.245689 [ANA_INIT] DLL >>>>>>>>
2136 14:47:05.248769 [ANA_INIT] DLL <<<<<<<<
2137 14:47:05.248855 [ANA_INIT] flow end
2138 14:47:05.252109 ============ LP4 DIFF to SE enter ============
2139 14:47:05.258761 ============ LP4 DIFF to SE exit ============
2140 14:47:05.258844 [ANA_INIT] <<<<<<<<<<<<<
2141 14:47:05.262090 [Flow] Enable top DCM control >>>>>
2142 14:47:05.265583 [Flow] Enable top DCM control <<<<<
2143 14:47:05.268608 Enable DLL master slave shuffle
2144 14:47:05.275303 ==============================================================
2145 14:47:05.275409 Gating Mode config
2146 14:47:05.282184 ==============================================================
2147 14:47:05.285805 Config description:
2148 14:47:05.295492 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2149 14:47:05.301905 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2150 14:47:05.305240 SELPH_MODE 0: By rank 1: By Phase
2151 14:47:05.312164 ==============================================================
2152 14:47:05.315223 GAT_TRACK_EN = 1
2153 14:47:05.315323 RX_GATING_MODE = 2
2154 14:47:05.318521 RX_GATING_TRACK_MODE = 2
2155 14:47:05.321941 SELPH_MODE = 1
2156 14:47:05.325076 PICG_EARLY_EN = 1
2157 14:47:05.328524 VALID_LAT_VALUE = 1
2158 14:47:05.335427 ==============================================================
2159 14:47:05.338435 Enter into Gating configuration >>>>
2160 14:47:05.342187 Exit from Gating configuration <<<<
2161 14:47:05.345035 Enter into DVFS_PRE_config >>>>>
2162 14:47:05.355439 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2163 14:47:05.358335 Exit from DVFS_PRE_config <<<<<
2164 14:47:05.361829 Enter into PICG configuration >>>>
2165 14:47:05.364940 Exit from PICG configuration <<<<
2166 14:47:05.368412 [RX_INPUT] configuration >>>>>
2167 14:47:05.371809 [RX_INPUT] configuration <<<<<
2168 14:47:05.375278 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2169 14:47:05.381642 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2170 14:47:05.388704 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2171 14:47:05.391775 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2172 14:47:05.398297 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2173 14:47:05.405135 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2174 14:47:05.408784 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2175 14:47:05.411771 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2176 14:47:05.418363 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2177 14:47:05.421812 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2178 14:47:05.425026 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2179 14:47:05.431625 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2180 14:47:05.435007 ===================================
2181 14:47:05.435108 LPDDR4 DRAM CONFIGURATION
2182 14:47:05.438265 ===================================
2183 14:47:05.441595 EX_ROW_EN[0] = 0x0
2184 14:47:05.444964 EX_ROW_EN[1] = 0x0
2185 14:47:05.445058 LP4Y_EN = 0x0
2186 14:47:05.448240 WORK_FSP = 0x0
2187 14:47:05.448341 WL = 0x4
2188 14:47:05.451479 RL = 0x4
2189 14:47:05.451575 BL = 0x2
2190 14:47:05.454961 RPST = 0x0
2191 14:47:05.455059 RD_PRE = 0x0
2192 14:47:05.458648 WR_PRE = 0x1
2193 14:47:05.458747 WR_PST = 0x0
2194 14:47:05.461424 DBI_WR = 0x0
2195 14:47:05.461499 DBI_RD = 0x0
2196 14:47:05.464797 OTF = 0x1
2197 14:47:05.468102 ===================================
2198 14:47:05.471625 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2199 14:47:05.474827 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2200 14:47:05.478296 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2201 14:47:05.481611 ===================================
2202 14:47:05.484915 LPDDR4 DRAM CONFIGURATION
2203 14:47:05.488326 ===================================
2204 14:47:05.491603 EX_ROW_EN[0] = 0x10
2205 14:47:05.491701 EX_ROW_EN[1] = 0x0
2206 14:47:05.495017 LP4Y_EN = 0x0
2207 14:47:05.495090 WORK_FSP = 0x0
2208 14:47:05.498126 WL = 0x4
2209 14:47:05.498199 RL = 0x4
2210 14:47:05.501442 BL = 0x2
2211 14:47:05.501515 RPST = 0x0
2212 14:47:05.505023 RD_PRE = 0x0
2213 14:47:05.508280 WR_PRE = 0x1
2214 14:47:05.508379 WR_PST = 0x0
2215 14:47:05.511580 DBI_WR = 0x0
2216 14:47:05.511675 DBI_RD = 0x0
2217 14:47:05.514885 OTF = 0x1
2218 14:47:05.518534 ===================================
2219 14:47:05.522120 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2220 14:47:05.524891 ==
2221 14:47:05.524962 Dram Type= 6, Freq= 0, CH_0, rank 0
2222 14:47:05.531483 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2223 14:47:05.531558 ==
2224 14:47:05.534746 [Duty_Offset_Calibration]
2225 14:47:05.534843 B0:0 B1:2 CA:1
2226 14:47:05.534931
2227 14:47:05.537984 [DutyScan_Calibration_Flow] k_type=0
2228 14:47:05.547565
2229 14:47:05.547668 ==CLK 0==
2230 14:47:05.550718 Final CLK duty delay cell = 0
2231 14:47:05.554262 [0] MAX Duty = 5093%(X100), DQS PI = 12
2232 14:47:05.557597 [0] MIN Duty = 4938%(X100), DQS PI = 52
2233 14:47:05.557696 [0] AVG Duty = 5015%(X100)
2234 14:47:05.560622
2235 14:47:05.564018 CH0 CLK Duty spec in!! Max-Min= 155%
2236 14:47:05.567472 [DutyScan_Calibration_Flow] ====Done====
2237 14:47:05.567568
2238 14:47:05.570653 [DutyScan_Calibration_Flow] k_type=1
2239 14:47:05.586718
2240 14:47:05.586817 ==DQS 0 ==
2241 14:47:05.590196 Final DQS duty delay cell = 0
2242 14:47:05.593322 [0] MAX Duty = 5125%(X100), DQS PI = 30
2243 14:47:05.596821 [0] MIN Duty = 5031%(X100), DQS PI = 4
2244 14:47:05.596917 [0] AVG Duty = 5078%(X100)
2245 14:47:05.600346
2246 14:47:05.600444 ==DQS 1 ==
2247 14:47:05.603409 Final DQS duty delay cell = 0
2248 14:47:05.606634 [0] MAX Duty = 5031%(X100), DQS PI = 52
2249 14:47:05.610058 [0] MIN Duty = 4906%(X100), DQS PI = 14
2250 14:47:05.613211 [0] AVG Duty = 4968%(X100)
2251 14:47:05.613286
2252 14:47:05.616888 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2253 14:47:05.616992
2254 14:47:05.619827 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2255 14:47:05.623384 [DutyScan_Calibration_Flow] ====Done====
2256 14:47:05.623470
2257 14:47:05.626495 [DutyScan_Calibration_Flow] k_type=3
2258 14:47:05.644052
2259 14:47:05.644150 ==DQM 0 ==
2260 14:47:05.647359 Final DQM duty delay cell = 0
2261 14:47:05.650744 [0] MAX Duty = 5124%(X100), DQS PI = 20
2262 14:47:05.653855 [0] MIN Duty = 4969%(X100), DQS PI = 40
2263 14:47:05.657270 [0] AVG Duty = 5046%(X100)
2264 14:47:05.657393
2265 14:47:05.657453 ==DQM 1 ==
2266 14:47:05.660478 Final DQM duty delay cell = 4
2267 14:47:05.663919 [4] MAX Duty = 5187%(X100), DQS PI = 54
2268 14:47:05.667378 [4] MIN Duty = 5000%(X100), DQS PI = 18
2269 14:47:05.670564 [4] AVG Duty = 5093%(X100)
2270 14:47:05.670649
2271 14:47:05.673850 CH0 DQM 0 Duty spec in!! Max-Min= 155%
2272 14:47:05.673957
2273 14:47:05.677429 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2274 14:47:05.680588 [DutyScan_Calibration_Flow] ====Done====
2275 14:47:05.680687
2276 14:47:05.683893 [DutyScan_Calibration_Flow] k_type=2
2277 14:47:05.699040
2278 14:47:05.699139 ==DQ 0 ==
2279 14:47:05.702243 Final DQ duty delay cell = -4
2280 14:47:05.705681 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2281 14:47:05.709088 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2282 14:47:05.712084 [-4] AVG Duty = 4937%(X100)
2283 14:47:05.712155
2284 14:47:05.712235 ==DQ 1 ==
2285 14:47:05.715815 Final DQ duty delay cell = -4
2286 14:47:05.718793 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2287 14:47:05.722551 [-4] MIN Duty = 4876%(X100), DQS PI = 38
2288 14:47:05.725667 [-4] AVG Duty = 4969%(X100)
2289 14:47:05.725739
2290 14:47:05.729043 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2291 14:47:05.729113
2292 14:47:05.732290 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2293 14:47:05.735652 [DutyScan_Calibration_Flow] ====Done====
2294 14:47:05.735731 ==
2295 14:47:05.738845 Dram Type= 6, Freq= 0, CH_1, rank 0
2296 14:47:05.742346 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2297 14:47:05.742419 ==
2298 14:47:05.745747 [Duty_Offset_Calibration]
2299 14:47:05.745817 B0:0 B1:5 CA:-5
2300 14:47:05.745878
2301 14:47:05.749047 [DutyScan_Calibration_Flow] k_type=0
2302 14:47:05.759413
2303 14:47:05.759487 ==CLK 0==
2304 14:47:05.762813 Final CLK duty delay cell = 0
2305 14:47:05.766024 [0] MAX Duty = 5094%(X100), DQS PI = 24
2306 14:47:05.769572 [0] MIN Duty = 4876%(X100), DQS PI = 52
2307 14:47:05.769646 [0] AVG Duty = 4985%(X100)
2308 14:47:05.773159
2309 14:47:05.776138 CH1 CLK Duty spec in!! Max-Min= 218%
2310 14:47:05.779300 [DutyScan_Calibration_Flow] ====Done====
2311 14:47:05.779371
2312 14:47:05.782689 [DutyScan_Calibration_Flow] k_type=1
2313 14:47:05.797816
2314 14:47:05.797891 ==DQS 0 ==
2315 14:47:05.801089 Final DQS duty delay cell = 0
2316 14:47:05.804606 [0] MAX Duty = 5125%(X100), DQS PI = 16
2317 14:47:05.807800 [0] MIN Duty = 4875%(X100), DQS PI = 40
2318 14:47:05.811290 [0] AVG Duty = 5000%(X100)
2319 14:47:05.811383
2320 14:47:05.811473 ==DQS 1 ==
2321 14:47:05.814488 Final DQS duty delay cell = -4
2322 14:47:05.818095 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2323 14:47:05.821191 [-4] MIN Duty = 4907%(X100), DQS PI = 56
2324 14:47:05.824656 [-4] AVG Duty = 4953%(X100)
2325 14:47:05.824732
2326 14:47:05.827798 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2327 14:47:05.827866
2328 14:47:05.831230 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2329 14:47:05.834371 [DutyScan_Calibration_Flow] ====Done====
2330 14:47:05.834442
2331 14:47:05.837999 [DutyScan_Calibration_Flow] k_type=3
2332 14:47:05.853092
2333 14:47:05.853197 ==DQM 0 ==
2334 14:47:05.856468 Final DQM duty delay cell = -4
2335 14:47:05.860034 [-4] MAX Duty = 5093%(X100), DQS PI = 32
2336 14:47:05.863020 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2337 14:47:05.866473 [-4] AVG Duty = 4968%(X100)
2338 14:47:05.866543
2339 14:47:05.866603 ==DQM 1 ==
2340 14:47:05.869783 Final DQM duty delay cell = -4
2341 14:47:05.873062 [-4] MAX Duty = 5094%(X100), DQS PI = 20
2342 14:47:05.876672 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2343 14:47:05.879818 [-4] AVG Duty = 5000%(X100)
2344 14:47:05.879888
2345 14:47:05.883108 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2346 14:47:05.883176
2347 14:47:05.886656 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2348 14:47:05.890079 [DutyScan_Calibration_Flow] ====Done====
2349 14:47:05.890148
2350 14:47:05.893125 [DutyScan_Calibration_Flow] k_type=2
2351 14:47:05.910452
2352 14:47:05.910550 ==DQ 0 ==
2353 14:47:05.913860 Final DQ duty delay cell = 0
2354 14:47:05.916953 [0] MAX Duty = 5062%(X100), DQS PI = 0
2355 14:47:05.920184 [0] MIN Duty = 4969%(X100), DQS PI = 42
2356 14:47:05.920280 [0] AVG Duty = 5015%(X100)
2357 14:47:05.920366
2358 14:47:05.923899 ==DQ 1 ==
2359 14:47:05.926761 Final DQ duty delay cell = 0
2360 14:47:05.930643 [0] MAX Duty = 5000%(X100), DQS PI = 6
2361 14:47:05.933604 [0] MIN Duty = 4876%(X100), DQS PI = 16
2362 14:47:05.933672 [0] AVG Duty = 4938%(X100)
2363 14:47:05.933729
2364 14:47:05.936852 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2365 14:47:05.936919
2366 14:47:05.940232 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2367 14:47:05.946757 [DutyScan_Calibration_Flow] ====Done====
2368 14:47:05.950239 nWR fixed to 30
2369 14:47:05.950316 [ModeRegInit_LP4] CH0 RK0
2370 14:47:05.953609 [ModeRegInit_LP4] CH0 RK1
2371 14:47:05.957040 [ModeRegInit_LP4] CH1 RK0
2372 14:47:05.957135 [ModeRegInit_LP4] CH1 RK1
2373 14:47:05.960137 match AC timing 6
2374 14:47:05.963575 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2375 14:47:05.966983 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2376 14:47:05.974005 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2377 14:47:05.976898 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2378 14:47:05.983618 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2379 14:47:05.983716 ==
2380 14:47:05.987173 Dram Type= 6, Freq= 0, CH_0, rank 0
2381 14:47:05.990733 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2382 14:47:05.990824 ==
2383 14:47:05.997074 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2384 14:47:06.000282 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2385 14:47:06.010044 [CA 0] Center 39 (9~70) winsize 62
2386 14:47:06.013267 [CA 1] Center 39 (9~70) winsize 62
2387 14:47:06.016695 [CA 2] Center 36 (5~67) winsize 63
2388 14:47:06.020031 [CA 3] Center 35 (4~66) winsize 63
2389 14:47:06.023245 [CA 4] Center 34 (3~65) winsize 63
2390 14:47:06.026673 [CA 5] Center 33 (3~64) winsize 62
2391 14:47:06.026752
2392 14:47:06.029848 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2393 14:47:06.029927
2394 14:47:06.033231 [CATrainingPosCal] consider 1 rank data
2395 14:47:06.036548 u2DelayCellTimex100 = 270/100 ps
2396 14:47:06.039803 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2397 14:47:06.046326 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2398 14:47:06.049799 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2399 14:47:06.052863 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2400 14:47:06.056849 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2401 14:47:06.059901 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2402 14:47:06.060005
2403 14:47:06.063377 CA PerBit enable=1, Macro0, CA PI delay=33
2404 14:47:06.063473
2405 14:47:06.066296 [CBTSetCACLKResult] CA Dly = 33
2406 14:47:06.066365 CS Dly: 7 (0~38)
2407 14:47:06.069406 ==
2408 14:47:06.072953 Dram Type= 6, Freq= 0, CH_0, rank 1
2409 14:47:06.076250 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2410 14:47:06.076330 ==
2411 14:47:06.079754 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2412 14:47:06.086315 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2413 14:47:06.095254 [CA 0] Center 39 (8~70) winsize 63
2414 14:47:06.098868 [CA 1] Center 39 (8~70) winsize 63
2415 14:47:06.102035 [CA 2] Center 35 (5~66) winsize 62
2416 14:47:06.105738 [CA 3] Center 35 (4~66) winsize 63
2417 14:47:06.109109 [CA 4] Center 33 (3~64) winsize 62
2418 14:47:06.112214 [CA 5] Center 33 (3~64) winsize 62
2419 14:47:06.112293
2420 14:47:06.115865 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2421 14:47:06.115944
2422 14:47:06.118687 [CATrainingPosCal] consider 2 rank data
2423 14:47:06.122127 u2DelayCellTimex100 = 270/100 ps
2424 14:47:06.125253 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2425 14:47:06.132010 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2426 14:47:06.135209 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2427 14:47:06.139283 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2428 14:47:06.142306 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2429 14:47:06.145238 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2430 14:47:06.145359
2431 14:47:06.148369 CA PerBit enable=1, Macro0, CA PI delay=33
2432 14:47:06.148462
2433 14:47:06.151824 [CBTSetCACLKResult] CA Dly = 33
2434 14:47:06.151924 CS Dly: 7 (0~39)
2435 14:47:06.152009
2436 14:47:06.155125 ----->DramcWriteLeveling(PI) begin...
2437 14:47:06.158756 ==
2438 14:47:06.162059 Dram Type= 6, Freq= 0, CH_0, rank 0
2439 14:47:06.165124 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2440 14:47:06.165195 ==
2441 14:47:06.168549 Write leveling (Byte 0): 28 => 28
2442 14:47:06.172132 Write leveling (Byte 1): 25 => 25
2443 14:47:06.175106 DramcWriteLeveling(PI) end<-----
2444 14:47:06.175184
2445 14:47:06.175244 ==
2446 14:47:06.178581 Dram Type= 6, Freq= 0, CH_0, rank 0
2447 14:47:06.182019 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2448 14:47:06.182093 ==
2449 14:47:06.185268 [Gating] SW mode calibration
2450 14:47:06.191703 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2451 14:47:06.198452 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2452 14:47:06.201591 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2453 14:47:06.205039 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2454 14:47:06.211847 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2455 14:47:06.215154 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2456 14:47:06.218547 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2457 14:47:06.221932 0 11 20 | B1->B0 | 2e2e 2b2b | 0 0 | (1 0) (1 0)
2458 14:47:06.228566 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2459 14:47:06.231785 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2460 14:47:06.235203 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2461 14:47:06.241542 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2462 14:47:06.245271 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2463 14:47:06.248403 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2464 14:47:06.255054 0 12 16 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2465 14:47:06.258414 0 12 20 | B1->B0 | 3434 3b3b | 0 0 | (0 0) (0 0)
2466 14:47:06.262132 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2467 14:47:06.268691 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2468 14:47:06.271694 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2469 14:47:06.275148 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2470 14:47:06.282014 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2471 14:47:06.285135 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2472 14:47:06.288630 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2473 14:47:06.295130 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2474 14:47:06.298674 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2475 14:47:06.301847 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2476 14:47:06.305175 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2477 14:47:06.311748 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2478 14:47:06.315265 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2479 14:47:06.318542 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2480 14:47:06.324918 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2481 14:47:06.328493 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2482 14:47:06.331655 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2483 14:47:06.338406 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2484 14:47:06.341554 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2485 14:47:06.345196 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2486 14:47:06.351757 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2487 14:47:06.355528 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2488 14:47:06.358435 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2489 14:47:06.365002 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2490 14:47:06.365080 Total UI for P1: 0, mck2ui 16
2491 14:47:06.371599 best dqsien dly found for B0: ( 0, 15, 16)
2492 14:47:06.371700 Total UI for P1: 0, mck2ui 16
2493 14:47:06.378576 best dqsien dly found for B1: ( 0, 15, 18)
2494 14:47:06.381811 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2495 14:47:06.384754 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2496 14:47:06.384859
2497 14:47:06.388154 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2498 14:47:06.391734 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2499 14:47:06.394869 [Gating] SW calibration Done
2500 14:47:06.394941 ==
2501 14:47:06.398165 Dram Type= 6, Freq= 0, CH_0, rank 0
2502 14:47:06.401904 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2503 14:47:06.402009 ==
2504 14:47:06.404961 RX Vref Scan: 0
2505 14:47:06.405056
2506 14:47:06.405142 RX Vref 0 -> 0, step: 1
2507 14:47:06.405234
2508 14:47:06.408436 RX Delay -40 -> 252, step: 8
2509 14:47:06.411639 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2510 14:47:06.418519 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2511 14:47:06.421433 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2512 14:47:06.424812 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2513 14:47:06.428252 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2514 14:47:06.431694 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2515 14:47:06.438191 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2516 14:47:06.441466 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2517 14:47:06.444803 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2518 14:47:06.448236 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2519 14:47:06.451577 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2520 14:47:06.458304 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2521 14:47:06.461540 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2522 14:47:06.465132 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2523 14:47:06.468053 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2524 14:47:06.471654 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2525 14:47:06.474956 ==
2526 14:47:06.475024 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 14:47:06.481577 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2528 14:47:06.481651 ==
2529 14:47:06.481718 DQS Delay:
2530 14:47:06.485043 DQS0 = 0, DQS1 = 0
2531 14:47:06.485107 DQM Delay:
2532 14:47:06.488286 DQM0 = 115, DQM1 = 106
2533 14:47:06.488380 DQ Delay:
2534 14:47:06.491380 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2535 14:47:06.494907 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2536 14:47:06.497954 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2537 14:47:06.501766 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2538 14:47:06.501854
2539 14:47:06.501914
2540 14:47:06.501971 ==
2541 14:47:06.504930 Dram Type= 6, Freq= 0, CH_0, rank 0
2542 14:47:06.511570 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2543 14:47:06.511663 ==
2544 14:47:06.511749
2545 14:47:06.511835
2546 14:47:06.511918 TX Vref Scan disable
2547 14:47:06.515047 == TX Byte 0 ==
2548 14:47:06.518113 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2549 14:47:06.521892 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2550 14:47:06.525075 == TX Byte 1 ==
2551 14:47:06.528105 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2552 14:47:06.531437 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2553 14:47:06.534927 ==
2554 14:47:06.538356 Dram Type= 6, Freq= 0, CH_0, rank 0
2555 14:47:06.541610 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2556 14:47:06.541680 ==
2557 14:47:06.552601 TX Vref=22, minBit 8, minWin=25, winSum=415
2558 14:47:06.555676 TX Vref=24, minBit 9, minWin=25, winSum=421
2559 14:47:06.559393 TX Vref=26, minBit 8, minWin=25, winSum=426
2560 14:47:06.562468 TX Vref=28, minBit 8, minWin=26, winSum=434
2561 14:47:06.566112 TX Vref=30, minBit 8, minWin=26, winSum=432
2562 14:47:06.572357 TX Vref=32, minBit 10, minWin=26, winSum=434
2563 14:47:06.575821 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 28
2564 14:47:06.575916
2565 14:47:06.579470 Final TX Range 1 Vref 28
2566 14:47:06.579566
2567 14:47:06.579651 ==
2568 14:47:06.582374 Dram Type= 6, Freq= 0, CH_0, rank 0
2569 14:47:06.585765 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2570 14:47:06.585831 ==
2571 14:47:06.589125
2572 14:47:06.589216
2573 14:47:06.589308 TX Vref Scan disable
2574 14:47:06.592458 == TX Byte 0 ==
2575 14:47:06.595835 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2576 14:47:06.599190 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2577 14:47:06.602489 == TX Byte 1 ==
2578 14:47:06.605877 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2579 14:47:06.609524 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2580 14:47:06.609590
2581 14:47:06.612471 [DATLAT]
2582 14:47:06.612561 Freq=1200, CH0 RK0
2583 14:47:06.612646
2584 14:47:06.615879 DATLAT Default: 0xd
2585 14:47:06.615986 0, 0xFFFF, sum = 0
2586 14:47:06.619566 1, 0xFFFF, sum = 0
2587 14:47:06.619665 2, 0xFFFF, sum = 0
2588 14:47:06.622879 3, 0xFFFF, sum = 0
2589 14:47:06.622949 4, 0xFFFF, sum = 0
2590 14:47:06.626039 5, 0xFFFF, sum = 0
2591 14:47:06.626104 6, 0xFFFF, sum = 0
2592 14:47:06.629412 7, 0xFFFF, sum = 0
2593 14:47:06.633092 8, 0xFFFF, sum = 0
2594 14:47:06.633184 9, 0xFFFF, sum = 0
2595 14:47:06.635970 10, 0xFFFF, sum = 0
2596 14:47:06.636065 11, 0x0, sum = 1
2597 14:47:06.639192 12, 0x0, sum = 2
2598 14:47:06.639286 13, 0x0, sum = 3
2599 14:47:06.639373 14, 0x0, sum = 4
2600 14:47:06.642360 best_step = 12
2601 14:47:06.642449
2602 14:47:06.642535 ==
2603 14:47:06.646238 Dram Type= 6, Freq= 0, CH_0, rank 0
2604 14:47:06.649448 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2605 14:47:06.649524 ==
2606 14:47:06.652709 RX Vref Scan: 1
2607 14:47:06.652803
2608 14:47:06.652889 Set Vref Range= 32 -> 127
2609 14:47:06.655855
2610 14:47:06.655955 RX Vref 32 -> 127, step: 1
2611 14:47:06.656056
2612 14:47:06.659229 RX Delay -21 -> 252, step: 4
2613 14:47:06.659295
2614 14:47:06.662540 Set Vref, RX VrefLevel [Byte0]: 32
2615 14:47:06.665701 [Byte1]: 32
2616 14:47:06.669207
2617 14:47:06.669272 Set Vref, RX VrefLevel [Byte0]: 33
2618 14:47:06.672459 [Byte1]: 33
2619 14:47:06.676913
2620 14:47:06.680140 Set Vref, RX VrefLevel [Byte0]: 34
2621 14:47:06.680235 [Byte1]: 34
2622 14:47:06.684845
2623 14:47:06.684936 Set Vref, RX VrefLevel [Byte0]: 35
2624 14:47:06.688430 [Byte1]: 35
2625 14:47:06.692799
2626 14:47:06.692867 Set Vref, RX VrefLevel [Byte0]: 36
2627 14:47:06.695941 [Byte1]: 36
2628 14:47:06.700680
2629 14:47:06.700774 Set Vref, RX VrefLevel [Byte0]: 37
2630 14:47:06.704216 [Byte1]: 37
2631 14:47:06.708658
2632 14:47:06.708752 Set Vref, RX VrefLevel [Byte0]: 38
2633 14:47:06.712080 [Byte1]: 38
2634 14:47:06.716538
2635 14:47:06.716634 Set Vref, RX VrefLevel [Byte0]: 39
2636 14:47:06.720035 [Byte1]: 39
2637 14:47:06.724580
2638 14:47:06.724682 Set Vref, RX VrefLevel [Byte0]: 40
2639 14:47:06.728221 [Byte1]: 40
2640 14:47:06.732876
2641 14:47:06.732975 Set Vref, RX VrefLevel [Byte0]: 41
2642 14:47:06.735927 [Byte1]: 41
2643 14:47:06.740457
2644 14:47:06.740554 Set Vref, RX VrefLevel [Byte0]: 42
2645 14:47:06.743650 [Byte1]: 42
2646 14:47:06.748293
2647 14:47:06.748368 Set Vref, RX VrefLevel [Byte0]: 43
2648 14:47:06.751646 [Byte1]: 43
2649 14:47:06.756254
2650 14:47:06.756327 Set Vref, RX VrefLevel [Byte0]: 44
2651 14:47:06.759876 [Byte1]: 44
2652 14:47:06.764336
2653 14:47:06.764436 Set Vref, RX VrefLevel [Byte0]: 45
2654 14:47:06.767333 [Byte1]: 45
2655 14:47:06.772383
2656 14:47:06.772484 Set Vref, RX VrefLevel [Byte0]: 46
2657 14:47:06.775354 [Byte1]: 46
2658 14:47:06.780091
2659 14:47:06.780166 Set Vref, RX VrefLevel [Byte0]: 47
2660 14:47:06.783406 [Byte1]: 47
2661 14:47:06.787990
2662 14:47:06.788061 Set Vref, RX VrefLevel [Byte0]: 48
2663 14:47:06.791130 [Byte1]: 48
2664 14:47:06.795931
2665 14:47:06.796029 Set Vref, RX VrefLevel [Byte0]: 49
2666 14:47:06.799367 [Byte1]: 49
2667 14:47:06.803811
2668 14:47:06.803883 Set Vref, RX VrefLevel [Byte0]: 50
2669 14:47:06.807095 [Byte1]: 50
2670 14:47:06.811910
2671 14:47:06.812008 Set Vref, RX VrefLevel [Byte0]: 51
2672 14:47:06.815285 [Byte1]: 51
2673 14:47:06.819877
2674 14:47:06.819978 Set Vref, RX VrefLevel [Byte0]: 52
2675 14:47:06.822881 [Byte1]: 52
2676 14:47:06.827705
2677 14:47:06.827775 Set Vref, RX VrefLevel [Byte0]: 53
2678 14:47:06.831056 [Byte1]: 53
2679 14:47:06.835654
2680 14:47:06.835725 Set Vref, RX VrefLevel [Byte0]: 54
2681 14:47:06.838964 [Byte1]: 54
2682 14:47:06.843629
2683 14:47:06.843704 Set Vref, RX VrefLevel [Byte0]: 55
2684 14:47:06.846861 [Byte1]: 55
2685 14:47:06.851705
2686 14:47:06.851781 Set Vref, RX VrefLevel [Byte0]: 56
2687 14:47:06.854542 [Byte1]: 56
2688 14:47:06.859271
2689 14:47:06.859343 Set Vref, RX VrefLevel [Byte0]: 57
2690 14:47:06.862679 [Byte1]: 57
2691 14:47:06.867619
2692 14:47:06.867691 Set Vref, RX VrefLevel [Byte0]: 58
2693 14:47:06.870546 [Byte1]: 58
2694 14:47:06.875406
2695 14:47:06.875503 Set Vref, RX VrefLevel [Byte0]: 59
2696 14:47:06.878641 [Byte1]: 59
2697 14:47:06.883098
2698 14:47:06.883171 Set Vref, RX VrefLevel [Byte0]: 60
2699 14:47:06.886601 [Byte1]: 60
2700 14:47:06.891101
2701 14:47:06.891176 Set Vref, RX VrefLevel [Byte0]: 61
2702 14:47:06.894167 [Byte1]: 61
2703 14:47:06.898802
2704 14:47:06.898901 Set Vref, RX VrefLevel [Byte0]: 62
2705 14:47:06.902108 [Byte1]: 62
2706 14:47:06.906977
2707 14:47:06.907051 Set Vref, RX VrefLevel [Byte0]: 63
2708 14:47:06.910422 [Byte1]: 63
2709 14:47:06.914766
2710 14:47:06.914841 Set Vref, RX VrefLevel [Byte0]: 64
2711 14:47:06.917889 [Byte1]: 64
2712 14:47:06.922514
2713 14:47:06.922585 Set Vref, RX VrefLevel [Byte0]: 65
2714 14:47:06.925806 [Byte1]: 65
2715 14:47:06.930469
2716 14:47:06.930539 Set Vref, RX VrefLevel [Byte0]: 66
2717 14:47:06.933899 [Byte1]: 66
2718 14:47:06.938526
2719 14:47:06.938602 Set Vref, RX VrefLevel [Byte0]: 67
2720 14:47:06.941792 [Byte1]: 67
2721 14:47:06.946296
2722 14:47:06.946392 Final RX Vref Byte 0 = 49 to rank0
2723 14:47:06.949695 Final RX Vref Byte 1 = 51 to rank0
2724 14:47:06.952963 Final RX Vref Byte 0 = 49 to rank1
2725 14:47:06.956602 Final RX Vref Byte 1 = 51 to rank1==
2726 14:47:06.959669 Dram Type= 6, Freq= 0, CH_0, rank 0
2727 14:47:06.966501 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2728 14:47:06.966577 ==
2729 14:47:06.966639 DQS Delay:
2730 14:47:06.966714 DQS0 = 0, DQS1 = 0
2731 14:47:06.970039 DQM Delay:
2732 14:47:06.970107 DQM0 = 114, DQM1 = 105
2733 14:47:06.973131 DQ Delay:
2734 14:47:06.976421 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =110
2735 14:47:06.979751 DQ4 =118, DQ5 =104, DQ6 =124, DQ7 =122
2736 14:47:06.983291 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =98
2737 14:47:06.986458 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2738 14:47:06.986559
2739 14:47:06.986645
2740 14:47:06.993308 [DQSOSCAuto] RK0, (LSB)MR18= 0x606, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
2741 14:47:06.996628 CH0 RK0: MR19=404, MR18=606
2742 14:47:07.003120 CH0_RK0: MR19=0x404, MR18=0x606, DQSOSC=407, MR23=63, INC=39, DEC=26
2743 14:47:07.003196
2744 14:47:07.007001 ----->DramcWriteLeveling(PI) begin...
2745 14:47:07.007076 ==
2746 14:47:07.010066 Dram Type= 6, Freq= 0, CH_0, rank 1
2747 14:47:07.013678 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2748 14:47:07.013753 ==
2749 14:47:07.016878 Write leveling (Byte 0): 28 => 28
2750 14:47:07.020013 Write leveling (Byte 1): 26 => 26
2751 14:47:07.023219 DramcWriteLeveling(PI) end<-----
2752 14:47:07.023317
2753 14:47:07.023404 ==
2754 14:47:07.026473 Dram Type= 6, Freq= 0, CH_0, rank 1
2755 14:47:07.029857 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2756 14:47:07.033172 ==
2757 14:47:07.033270 [Gating] SW mode calibration
2758 14:47:07.039950 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2759 14:47:07.046448 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2760 14:47:07.049771 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2761 14:47:07.056295 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2762 14:47:07.060009 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2763 14:47:07.063034 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2764 14:47:07.069629 0 11 16 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
2765 14:47:07.073239 0 11 20 | B1->B0 | 3131 2828 | 1 0 | (1 0) (0 0)
2766 14:47:07.076207 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2767 14:47:07.082835 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2768 14:47:07.086230 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2769 14:47:07.089511 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2770 14:47:07.095978 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2771 14:47:07.099313 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2772 14:47:07.103113 0 12 16 | B1->B0 | 2424 2f2f | 0 1 | (0 0) (0 0)
2773 14:47:07.109670 0 12 20 | B1->B0 | 3b3b 4545 | 1 0 | (0 0) (0 0)
2774 14:47:07.112624 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2775 14:47:07.115812 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2776 14:47:07.122473 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2777 14:47:07.125874 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2778 14:47:07.129065 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2779 14:47:07.135991 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2780 14:47:07.139042 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2781 14:47:07.142704 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2782 14:47:07.149270 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2783 14:47:07.152600 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2784 14:47:07.155992 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2785 14:47:07.159224 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2786 14:47:07.165819 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2787 14:47:07.169021 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2788 14:47:07.172508 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2789 14:47:07.178793 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2790 14:47:07.182374 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2791 14:47:07.185511 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2792 14:47:07.192321 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2793 14:47:07.196027 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2794 14:47:07.199048 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2795 14:47:07.205823 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2796 14:47:07.208888 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2797 14:47:07.212329 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2798 14:47:07.215753 Total UI for P1: 0, mck2ui 16
2799 14:47:07.218953 best dqsien dly found for B0: ( 0, 15, 16)
2800 14:47:07.225478 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2801 14:47:07.228839 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2802 14:47:07.232400 Total UI for P1: 0, mck2ui 16
2803 14:47:07.235916 best dqsien dly found for B1: ( 0, 15, 22)
2804 14:47:07.238795 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2805 14:47:07.242508 best DQS1 dly(MCK, UI, PI) = (0, 15, 22)
2806 14:47:07.242581
2807 14:47:07.245520 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2808 14:47:07.248819 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 22)
2809 14:47:07.252191 [Gating] SW calibration Done
2810 14:47:07.252291 ==
2811 14:47:07.255647 Dram Type= 6, Freq= 0, CH_0, rank 1
2812 14:47:07.258977 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2813 14:47:07.262337 ==
2814 14:47:07.262416 RX Vref Scan: 0
2815 14:47:07.262479
2816 14:47:07.265367 RX Vref 0 -> 0, step: 1
2817 14:47:07.265439
2818 14:47:07.268846 RX Delay -40 -> 252, step: 8
2819 14:47:07.272320 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2820 14:47:07.275404 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2821 14:47:07.278940 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2822 14:47:07.282170 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2823 14:47:07.288779 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2824 14:47:07.292085 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2825 14:47:07.295501 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2826 14:47:07.298597 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2827 14:47:07.302212 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2828 14:47:07.305270 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2829 14:47:07.312497 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2830 14:47:07.315318 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2831 14:47:07.318681 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2832 14:47:07.322022 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2833 14:47:07.328859 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2834 14:47:07.331850 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2835 14:47:07.331953 ==
2836 14:47:07.335424 Dram Type= 6, Freq= 0, CH_0, rank 1
2837 14:47:07.338647 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2838 14:47:07.338741 ==
2839 14:47:07.338836 DQS Delay:
2840 14:47:07.342131 DQS0 = 0, DQS1 = 0
2841 14:47:07.342223 DQM Delay:
2842 14:47:07.345334 DQM0 = 116, DQM1 = 106
2843 14:47:07.345426 DQ Delay:
2844 14:47:07.348543 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =107
2845 14:47:07.352217 DQ4 =119, DQ5 =107, DQ6 =123, DQ7 =123
2846 14:47:07.355302 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2847 14:47:07.358627 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2848 14:47:07.358726
2849 14:47:07.361927
2850 14:47:07.362001 ==
2851 14:47:07.365269 Dram Type= 6, Freq= 0, CH_0, rank 1
2852 14:47:07.368448 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2853 14:47:07.368519 ==
2854 14:47:07.368579
2855 14:47:07.368636
2856 14:47:07.371752 TX Vref Scan disable
2857 14:47:07.371823 == TX Byte 0 ==
2858 14:47:07.378644 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2859 14:47:07.381681 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2860 14:47:07.381755 == TX Byte 1 ==
2861 14:47:07.388471 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2862 14:47:07.391927 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2863 14:47:07.392002 ==
2864 14:47:07.395249 Dram Type= 6, Freq= 0, CH_0, rank 1
2865 14:47:07.398486 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2866 14:47:07.398584 ==
2867 14:47:07.410852 TX Vref=22, minBit 8, minWin=25, winSum=417
2868 14:47:07.413946 TX Vref=24, minBit 1, minWin=26, winSum=427
2869 14:47:07.417416 TX Vref=26, minBit 8, minWin=26, winSum=429
2870 14:47:07.420921 TX Vref=28, minBit 10, minWin=25, winSum=434
2871 14:47:07.424174 TX Vref=30, minBit 12, minWin=26, winSum=436
2872 14:47:07.430825 TX Vref=32, minBit 8, minWin=26, winSum=437
2873 14:47:07.433830 [TxChooseVref] Worse bit 8, Min win 26, Win sum 437, Final Vref 32
2874 14:47:07.433903
2875 14:47:07.437257 Final TX Range 1 Vref 32
2876 14:47:07.437367
2877 14:47:07.437427 ==
2878 14:47:07.440642 Dram Type= 6, Freq= 0, CH_0, rank 1
2879 14:47:07.444313 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2880 14:47:07.447292 ==
2881 14:47:07.447390
2882 14:47:07.447476
2883 14:47:07.447561 TX Vref Scan disable
2884 14:47:07.451179 == TX Byte 0 ==
2885 14:47:07.453868 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2886 14:47:07.457230 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2887 14:47:07.460675 == TX Byte 1 ==
2888 14:47:07.463766 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2889 14:47:07.470623 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2890 14:47:07.470722
2891 14:47:07.470809 [DATLAT]
2892 14:47:07.470894 Freq=1200, CH0 RK1
2893 14:47:07.470981
2894 14:47:07.473758 DATLAT Default: 0xc
2895 14:47:07.473849 0, 0xFFFF, sum = 0
2896 14:47:07.477177 1, 0xFFFF, sum = 0
2897 14:47:07.477274 2, 0xFFFF, sum = 0
2898 14:47:07.480557 3, 0xFFFF, sum = 0
2899 14:47:07.484011 4, 0xFFFF, sum = 0
2900 14:47:07.484085 5, 0xFFFF, sum = 0
2901 14:47:07.487044 6, 0xFFFF, sum = 0
2902 14:47:07.487167 7, 0xFFFF, sum = 0
2903 14:47:07.490316 8, 0xFFFF, sum = 0
2904 14:47:07.490415 9, 0xFFFF, sum = 0
2905 14:47:07.493624 10, 0xFFFF, sum = 0
2906 14:47:07.493726 11, 0x0, sum = 1
2907 14:47:07.497139 12, 0x0, sum = 2
2908 14:47:07.497285 13, 0x0, sum = 3
2909 14:47:07.500418 14, 0x0, sum = 4
2910 14:47:07.500516 best_step = 12
2911 14:47:07.500616
2912 14:47:07.500708 ==
2913 14:47:07.503791 Dram Type= 6, Freq= 0, CH_0, rank 1
2914 14:47:07.506898 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2915 14:47:07.506990 ==
2916 14:47:07.510465 RX Vref Scan: 0
2917 14:47:07.510556
2918 14:47:07.513617 RX Vref 0 -> 0, step: 1
2919 14:47:07.513716
2920 14:47:07.513795 RX Delay -21 -> 252, step: 4
2921 14:47:07.521164 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2922 14:47:07.524508 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2923 14:47:07.528017 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2924 14:47:07.531403 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2925 14:47:07.534586 iDelay=199, Bit 4, Center 116 (43 ~ 190) 148
2926 14:47:07.541416 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2927 14:47:07.544595 iDelay=199, Bit 6, Center 124 (55 ~ 194) 140
2928 14:47:07.547874 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2929 14:47:07.551459 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2930 14:47:07.554717 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2931 14:47:07.561567 iDelay=199, Bit 10, Center 108 (43 ~ 174) 132
2932 14:47:07.564715 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2933 14:47:07.568691 iDelay=199, Bit 12, Center 114 (51 ~ 178) 128
2934 14:47:07.571551 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128
2935 14:47:07.575173 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2936 14:47:07.581579 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
2937 14:47:07.581988 ==
2938 14:47:07.584961 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 14:47:07.588155 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2940 14:47:07.588803 ==
2941 14:47:07.589436 DQS Delay:
2942 14:47:07.591491 DQS0 = 0, DQS1 = 0
2943 14:47:07.591992 DQM Delay:
2944 14:47:07.595014 DQM0 = 115, DQM1 = 106
2945 14:47:07.595558 DQ Delay:
2946 14:47:07.598481 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2947 14:47:07.601669 DQ4 =116, DQ5 =108, DQ6 =124, DQ7 =124
2948 14:47:07.604718 DQ8 =94, DQ9 =90, DQ10 =108, DQ11 =96
2949 14:47:07.608244 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =116
2950 14:47:07.608656
2951 14:47:07.608998
2952 14:47:07.618262 [DQSOSCAuto] RK1, (LSB)MR18= 0x1111, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
2953 14:47:07.621283 CH0 RK1: MR19=404, MR18=1111
2954 14:47:07.624859 CH0_RK1: MR19=0x404, MR18=0x1111, DQSOSC=403, MR23=63, INC=40, DEC=26
2955 14:47:07.628168 [RxdqsGatingPostProcess] freq 1200
2956 14:47:07.634954 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2957 14:47:07.638196 Pre-setting of DQS Precalculation
2958 14:47:07.641375 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2959 14:47:07.641787 ==
2960 14:47:07.644549 Dram Type= 6, Freq= 0, CH_1, rank 0
2961 14:47:07.651258 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2962 14:47:07.651678 ==
2963 14:47:07.654674 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2964 14:47:07.661215 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2965 14:47:07.670210 [CA 0] Center 37 (7~68) winsize 62
2966 14:47:07.673435 [CA 1] Center 37 (7~68) winsize 62
2967 14:47:07.676875 [CA 2] Center 34 (4~65) winsize 62
2968 14:47:07.680130 [CA 3] Center 33 (3~64) winsize 62
2969 14:47:07.683634 [CA 4] Center 32 (2~63) winsize 62
2970 14:47:07.686781 [CA 5] Center 32 (1~63) winsize 63
2971 14:47:07.687191
2972 14:47:07.689979 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2973 14:47:07.690393
2974 14:47:07.693580 [CATrainingPosCal] consider 1 rank data
2975 14:47:07.696772 u2DelayCellTimex100 = 270/100 ps
2976 14:47:07.700261 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2977 14:47:07.703765 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2978 14:47:07.710555 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2979 14:47:07.713688 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2980 14:47:07.717409 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2981 14:47:07.719942 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2982 14:47:07.720377
2983 14:47:07.723605 CA PerBit enable=1, Macro0, CA PI delay=32
2984 14:47:07.724017
2985 14:47:07.726776 [CBTSetCACLKResult] CA Dly = 32
2986 14:47:07.727188 CS Dly: 5 (0~36)
2987 14:47:07.727508 ==
2988 14:47:07.730253 Dram Type= 6, Freq= 0, CH_1, rank 1
2989 14:47:07.736841 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2990 14:47:07.737257 ==
2991 14:47:07.739949 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2992 14:47:07.746694 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2993 14:47:07.755552 [CA 0] Center 37 (7~68) winsize 62
2994 14:47:07.758942 [CA 1] Center 37 (7~68) winsize 62
2995 14:47:07.761927 [CA 2] Center 34 (3~65) winsize 63
2996 14:47:07.765330 [CA 3] Center 33 (3~64) winsize 62
2997 14:47:07.768863 [CA 4] Center 32 (2~63) winsize 62
2998 14:47:07.772373 [CA 5] Center 31 (1~62) winsize 62
2999 14:47:07.772890
3000 14:47:07.775360 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3001 14:47:07.775820
3002 14:47:07.778707 [CATrainingPosCal] consider 2 rank data
3003 14:47:07.782321 u2DelayCellTimex100 = 270/100 ps
3004 14:47:07.785251 CA0 delay=37 (7~68),Diff = 6 PI (28 cell)
3005 14:47:07.788709 CA1 delay=37 (7~68),Diff = 6 PI (28 cell)
3006 14:47:07.795792 CA2 delay=34 (4~65),Diff = 3 PI (14 cell)
3007 14:47:07.798953 CA3 delay=33 (3~64),Diff = 2 PI (9 cell)
3008 14:47:07.801900 CA4 delay=32 (2~63),Diff = 1 PI (4 cell)
3009 14:47:07.805864 CA5 delay=31 (1~62),Diff = 0 PI (0 cell)
3010 14:47:07.806419
3011 14:47:07.809148 CA PerBit enable=1, Macro0, CA PI delay=31
3012 14:47:07.809700
3013 14:47:07.811879 [CBTSetCACLKResult] CA Dly = 31
3014 14:47:07.812482 CS Dly: 6 (0~38)
3015 14:47:07.812992
3016 14:47:07.815199 ----->DramcWriteLeveling(PI) begin...
3017 14:47:07.818690 ==
3018 14:47:07.821908 Dram Type= 6, Freq= 0, CH_1, rank 0
3019 14:47:07.825094 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3020 14:47:07.825604 ==
3021 14:47:07.828415 Write leveling (Byte 0): 21 => 21
3022 14:47:07.832107 Write leveling (Byte 1): 21 => 21
3023 14:47:07.835287 DramcWriteLeveling(PI) end<-----
3024 14:47:07.835686
3025 14:47:07.836036 ==
3026 14:47:07.838702 Dram Type= 6, Freq= 0, CH_1, rank 0
3027 14:47:07.842151 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3028 14:47:07.842737 ==
3029 14:47:07.845221 [Gating] SW mode calibration
3030 14:47:07.852079 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3031 14:47:07.858490 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3032 14:47:07.861840 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3033 14:47:07.865272 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3034 14:47:07.868448 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3035 14:47:07.875261 0 11 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3036 14:47:07.878563 0 11 16 | B1->B0 | 2e2e 2626 | 0 0 | (1 0) (1 0)
3037 14:47:07.881773 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3038 14:47:07.888464 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3039 14:47:07.891640 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3040 14:47:07.894994 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3041 14:47:07.901671 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3042 14:47:07.904990 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3043 14:47:07.908283 0 12 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3044 14:47:07.915012 0 12 16 | B1->B0 | 3131 4242 | 0 0 | (0 0) (0 0)
3045 14:47:07.918213 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3046 14:47:07.921701 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3047 14:47:07.928354 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3048 14:47:07.931589 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3049 14:47:07.934696 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3050 14:47:07.941663 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3051 14:47:07.945013 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3052 14:47:07.948148 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3053 14:47:07.954913 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3054 14:47:07.957860 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3055 14:47:07.961387 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3056 14:47:07.967984 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3057 14:47:07.970927 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3058 14:47:07.974467 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3059 14:47:07.981045 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3060 14:47:07.984868 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3061 14:47:07.987653 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3062 14:47:07.994329 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3063 14:47:07.997605 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3064 14:47:08.000787 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3065 14:47:08.007373 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3066 14:47:08.011151 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3067 14:47:08.014172 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3068 14:47:08.020728 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
3069 14:47:08.021203 Total UI for P1: 0, mck2ui 16
3070 14:47:08.027472 best dqsien dly found for B0: ( 0, 15, 14)
3071 14:47:08.030702 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3072 14:47:08.034305 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3073 14:47:08.037324 Total UI for P1: 0, mck2ui 16
3074 14:47:08.040769 best dqsien dly found for B1: ( 0, 15, 20)
3075 14:47:08.044240 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3076 14:47:08.047608 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
3077 14:47:08.048018
3078 14:47:08.054269 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3079 14:47:08.057274 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
3080 14:47:08.057724 [Gating] SW calibration Done
3081 14:47:08.060726 ==
3082 14:47:08.061135 Dram Type= 6, Freq= 0, CH_1, rank 0
3083 14:47:08.067312 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3084 14:47:08.067727 ==
3085 14:47:08.068047 RX Vref Scan: 0
3086 14:47:08.068342
3087 14:47:08.070800 RX Vref 0 -> 0, step: 1
3088 14:47:08.071211
3089 14:47:08.073928 RX Delay -40 -> 252, step: 8
3090 14:47:08.077198 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3091 14:47:08.080380 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3092 14:47:08.087183 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3093 14:47:08.090744 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3094 14:47:08.093806 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3095 14:47:08.096650 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3096 14:47:08.100564 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3097 14:47:08.106891 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3098 14:47:08.110207 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3099 14:47:08.113395 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3100 14:47:08.116991 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3101 14:47:08.120087 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3102 14:47:08.123548 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3103 14:47:08.129829 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3104 14:47:08.133341 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3105 14:47:08.137015 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3106 14:47:08.137616 ==
3107 14:47:08.140408 Dram Type= 6, Freq= 0, CH_1, rank 0
3108 14:47:08.143231 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3109 14:47:08.146732 ==
3110 14:47:08.147143 DQS Delay:
3111 14:47:08.147461 DQS0 = 0, DQS1 = 0
3112 14:47:08.150097 DQM Delay:
3113 14:47:08.150506 DQM0 = 116, DQM1 = 107
3114 14:47:08.153185 DQ Delay:
3115 14:47:08.156616 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3116 14:47:08.160053 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3117 14:47:08.163348 DQ8 =87, DQ9 =95, DQ10 =107, DQ11 =99
3118 14:47:08.166666 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3119 14:47:08.167126
3120 14:47:08.167529
3121 14:47:08.167949 ==
3122 14:47:08.170115 Dram Type= 6, Freq= 0, CH_1, rank 0
3123 14:47:08.173455 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3124 14:47:08.173946 ==
3125 14:47:08.174356
3126 14:47:08.174729
3127 14:47:08.176845 TX Vref Scan disable
3128 14:47:08.180129 == TX Byte 0 ==
3129 14:47:08.183239 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3130 14:47:08.186750 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3131 14:47:08.189832 == TX Byte 1 ==
3132 14:47:08.193061 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3133 14:47:08.196445 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3134 14:47:08.196939 ==
3135 14:47:08.200187 Dram Type= 6, Freq= 0, CH_1, rank 0
3136 14:47:08.203357 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3137 14:47:08.206451 ==
3138 14:47:08.216413 TX Vref=22, minBit 7, minWin=25, winSum=413
3139 14:47:08.219657 TX Vref=24, minBit 8, minWin=25, winSum=420
3140 14:47:08.222982 TX Vref=26, minBit 0, minWin=26, winSum=423
3141 14:47:08.226683 TX Vref=28, minBit 0, minWin=26, winSum=427
3142 14:47:08.229853 TX Vref=30, minBit 0, minWin=26, winSum=428
3143 14:47:08.236065 TX Vref=32, minBit 10, minWin=25, winSum=427
3144 14:47:08.239468 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 30
3145 14:47:08.240037
3146 14:47:08.242943 Final TX Range 1 Vref 30
3147 14:47:08.243354
3148 14:47:08.243675 ==
3149 14:47:08.246602 Dram Type= 6, Freq= 0, CH_1, rank 0
3150 14:47:08.249866 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3151 14:47:08.252767 ==
3152 14:47:08.253191
3153 14:47:08.253562
3154 14:47:08.253866 TX Vref Scan disable
3155 14:47:08.256136 == TX Byte 0 ==
3156 14:47:08.259608 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3157 14:47:08.262885 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3158 14:47:08.265987 == TX Byte 1 ==
3159 14:47:08.269538 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3160 14:47:08.276167 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3161 14:47:08.276578
3162 14:47:08.276896 [DATLAT]
3163 14:47:08.277193 Freq=1200, CH1 RK0
3164 14:47:08.277606
3165 14:47:08.279600 DATLAT Default: 0xd
3166 14:47:08.280006 0, 0xFFFF, sum = 0
3167 14:47:08.282693 1, 0xFFFF, sum = 0
3168 14:47:08.283107 2, 0xFFFF, sum = 0
3169 14:47:08.286258 3, 0xFFFF, sum = 0
3170 14:47:08.289496 4, 0xFFFF, sum = 0
3171 14:47:08.290057 5, 0xFFFF, sum = 0
3172 14:47:08.292581 6, 0xFFFF, sum = 0
3173 14:47:08.292995 7, 0xFFFF, sum = 0
3174 14:47:08.295997 8, 0xFFFF, sum = 0
3175 14:47:08.296539 9, 0xFFFF, sum = 0
3176 14:47:08.299365 10, 0xFFFF, sum = 0
3177 14:47:08.299776 11, 0x0, sum = 1
3178 14:47:08.302557 12, 0x0, sum = 2
3179 14:47:08.302971 13, 0x0, sum = 3
3180 14:47:08.306255 14, 0x0, sum = 4
3181 14:47:08.306667 best_step = 12
3182 14:47:08.306990
3183 14:47:08.307288 ==
3184 14:47:08.309538 Dram Type= 6, Freq= 0, CH_1, rank 0
3185 14:47:08.312795 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3186 14:47:08.313206 ==
3187 14:47:08.318829 RX Vref Scan: 1
3188 14:47:08.319317
3189 14:47:08.319974 Set Vref Range= 32 -> 127
3190 14:47:08.320335
3191 14:47:08.320645 RX Vref 32 -> 127, step: 1
3192 14:47:08.320931
3193 14:47:08.322694 RX Delay -29 -> 252, step: 4
3194 14:47:08.323105
3195 14:47:08.326081 Set Vref, RX VrefLevel [Byte0]: 32
3196 14:47:08.329512 [Byte1]: 32
3197 14:47:08.333226
3198 14:47:08.333654 Set Vref, RX VrefLevel [Byte0]: 33
3199 14:47:08.336269 [Byte1]: 33
3200 14:47:08.340933
3201 14:47:08.341447 Set Vref, RX VrefLevel [Byte0]: 34
3202 14:47:08.344344 [Byte1]: 34
3203 14:47:08.348998
3204 14:47:08.349566 Set Vref, RX VrefLevel [Byte0]: 35
3205 14:47:08.351846 [Byte1]: 35
3206 14:47:08.356992
3207 14:47:08.357539 Set Vref, RX VrefLevel [Byte0]: 36
3208 14:47:08.360157 [Byte1]: 36
3209 14:47:08.364599
3210 14:47:08.365175 Set Vref, RX VrefLevel [Byte0]: 37
3211 14:47:08.368456 [Byte1]: 37
3212 14:47:08.372760
3213 14:47:08.373280 Set Vref, RX VrefLevel [Byte0]: 38
3214 14:47:08.376028 [Byte1]: 38
3215 14:47:08.380547
3216 14:47:08.380980 Set Vref, RX VrefLevel [Byte0]: 39
3217 14:47:08.384021 [Byte1]: 39
3218 14:47:08.388722
3219 14:47:08.389172 Set Vref, RX VrefLevel [Byte0]: 40
3220 14:47:08.392186 [Byte1]: 40
3221 14:47:08.396756
3222 14:47:08.397322 Set Vref, RX VrefLevel [Byte0]: 41
3223 14:47:08.400004 [Byte1]: 41
3224 14:47:08.404637
3225 14:47:08.405080 Set Vref, RX VrefLevel [Byte0]: 42
3226 14:47:08.407663 [Byte1]: 42
3227 14:47:08.412638
3228 14:47:08.413075 Set Vref, RX VrefLevel [Byte0]: 43
3229 14:47:08.415718 [Byte1]: 43
3230 14:47:08.420918
3231 14:47:08.421377 Set Vref, RX VrefLevel [Byte0]: 44
3232 14:47:08.423682 [Byte1]: 44
3233 14:47:08.428259
3234 14:47:08.428687 Set Vref, RX VrefLevel [Byte0]: 45
3235 14:47:08.431712 [Byte1]: 45
3236 14:47:08.436694
3237 14:47:08.437128 Set Vref, RX VrefLevel [Byte0]: 46
3238 14:47:08.439626 [Byte1]: 46
3239 14:47:08.444347
3240 14:47:08.444776 Set Vref, RX VrefLevel [Byte0]: 47
3241 14:47:08.447476 [Byte1]: 47
3242 14:47:08.452407
3243 14:47:08.452857 Set Vref, RX VrefLevel [Byte0]: 48
3244 14:47:08.455399 [Byte1]: 48
3245 14:47:08.460379
3246 14:47:08.460926 Set Vref, RX VrefLevel [Byte0]: 49
3247 14:47:08.463584 [Byte1]: 49
3248 14:47:08.468656
3249 14:47:08.469063 Set Vref, RX VrefLevel [Byte0]: 50
3250 14:47:08.471506 [Byte1]: 50
3251 14:47:08.476456
3252 14:47:08.476866 Set Vref, RX VrefLevel [Byte0]: 51
3253 14:47:08.479398 [Byte1]: 51
3254 14:47:08.484071
3255 14:47:08.484479 Set Vref, RX VrefLevel [Byte0]: 52
3256 14:47:08.487344 [Byte1]: 52
3257 14:47:08.492188
3258 14:47:08.492629 Set Vref, RX VrefLevel [Byte0]: 53
3259 14:47:08.495285 [Byte1]: 53
3260 14:47:08.500152
3261 14:47:08.500592 Set Vref, RX VrefLevel [Byte0]: 54
3262 14:47:08.503428 [Byte1]: 54
3263 14:47:08.508131
3264 14:47:08.508650 Set Vref, RX VrefLevel [Byte0]: 55
3265 14:47:08.511334 [Byte1]: 55
3266 14:47:08.515973
3267 14:47:08.516459 Set Vref, RX VrefLevel [Byte0]: 56
3268 14:47:08.519256 [Byte1]: 56
3269 14:47:08.524066
3270 14:47:08.524511 Set Vref, RX VrefLevel [Byte0]: 57
3271 14:47:08.527658 [Byte1]: 57
3272 14:47:08.532344
3273 14:47:08.532834 Set Vref, RX VrefLevel [Byte0]: 58
3274 14:47:08.535046 [Byte1]: 58
3275 14:47:08.540047
3276 14:47:08.540482 Set Vref, RX VrefLevel [Byte0]: 59
3277 14:47:08.543208 [Byte1]: 59
3278 14:47:08.547608
3279 14:47:08.548032 Set Vref, RX VrefLevel [Byte0]: 60
3280 14:47:08.551078 [Byte1]: 60
3281 14:47:08.555872
3282 14:47:08.556300 Set Vref, RX VrefLevel [Byte0]: 61
3283 14:47:08.559076 [Byte1]: 61
3284 14:47:08.563676
3285 14:47:08.564088 Set Vref, RX VrefLevel [Byte0]: 62
3286 14:47:08.566711 [Byte1]: 62
3287 14:47:08.571643
3288 14:47:08.572053 Set Vref, RX VrefLevel [Byte0]: 63
3289 14:47:08.575009 [Byte1]: 63
3290 14:47:08.579698
3291 14:47:08.580157 Set Vref, RX VrefLevel [Byte0]: 64
3292 14:47:08.583192 [Byte1]: 64
3293 14:47:08.587721
3294 14:47:08.588127 Set Vref, RX VrefLevel [Byte0]: 65
3295 14:47:08.590963 [Byte1]: 65
3296 14:47:08.595252
3297 14:47:08.595661 Set Vref, RX VrefLevel [Byte0]: 66
3298 14:47:08.598705 [Byte1]: 66
3299 14:47:08.603232
3300 14:47:08.603669 Final RX Vref Byte 0 = 52 to rank0
3301 14:47:08.606612 Final RX Vref Byte 1 = 49 to rank0
3302 14:47:08.610033 Final RX Vref Byte 0 = 52 to rank1
3303 14:47:08.613762 Final RX Vref Byte 1 = 49 to rank1==
3304 14:47:08.617167 Dram Type= 6, Freq= 0, CH_1, rank 0
3305 14:47:08.623433 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3306 14:47:08.623883 ==
3307 14:47:08.624358 DQS Delay:
3308 14:47:08.624671 DQS0 = 0, DQS1 = 0
3309 14:47:08.626724 DQM Delay:
3310 14:47:08.627154 DQM0 = 115, DQM1 = 105
3311 14:47:08.630054 DQ Delay:
3312 14:47:08.633562 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3313 14:47:08.636573 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =114
3314 14:47:08.640018 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3315 14:47:08.643197 DQ12 =112, DQ13 =116, DQ14 =116, DQ15 =114
3316 14:47:08.643636
3317 14:47:08.644120
3318 14:47:08.649839 [DQSOSCAuto] RK0, (LSB)MR18= 0x1313, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
3319 14:47:08.653639 CH1 RK0: MR19=404, MR18=1313
3320 14:47:08.660021 CH1_RK0: MR19=0x404, MR18=0x1313, DQSOSC=402, MR23=63, INC=40, DEC=27
3321 14:47:08.660469
3322 14:47:08.663299 ----->DramcWriteLeveling(PI) begin...
3323 14:47:08.663702 ==
3324 14:47:08.666820 Dram Type= 6, Freq= 0, CH_1, rank 1
3325 14:47:08.669941 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3326 14:47:08.673434 ==
3327 14:47:08.673912 Write leveling (Byte 0): 22 => 22
3328 14:47:08.676711 Write leveling (Byte 1): 22 => 22
3329 14:47:08.680597 DramcWriteLeveling(PI) end<-----
3330 14:47:08.681078
3331 14:47:08.681591 ==
3332 14:47:08.683283 Dram Type= 6, Freq= 0, CH_1, rank 1
3333 14:47:08.689939 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3334 14:47:08.690437 ==
3335 14:47:08.690847 [Gating] SW mode calibration
3336 14:47:08.700018 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3337 14:47:08.703129 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3338 14:47:08.706560 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3339 14:47:08.713422 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3340 14:47:08.716610 0 11 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3341 14:47:08.719826 0 11 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
3342 14:47:08.726804 0 11 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
3343 14:47:08.729868 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3344 14:47:08.732957 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3345 14:47:08.739701 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3346 14:47:08.742990 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3347 14:47:08.746252 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3348 14:47:08.753113 0 12 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
3349 14:47:08.756820 0 12 12 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
3350 14:47:08.760189 0 12 16 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
3351 14:47:08.766879 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3352 14:47:08.770060 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3353 14:47:08.773284 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3354 14:47:08.779793 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3355 14:47:08.783091 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3356 14:47:08.786512 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3357 14:47:08.792843 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3358 14:47:08.796240 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3359 14:47:08.799647 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3360 14:47:08.806316 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3361 14:47:08.809585 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3362 14:47:08.813078 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3363 14:47:08.819846 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3364 14:47:08.823009 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3365 14:47:08.826658 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3366 14:47:08.829594 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3367 14:47:08.836293 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3368 14:47:08.839680 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3369 14:47:08.843040 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3370 14:47:08.849604 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3371 14:47:08.852794 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3372 14:47:08.856320 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3373 14:47:08.862911 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3374 14:47:08.866054 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3375 14:47:08.869637 Total UI for P1: 0, mck2ui 16
3376 14:47:08.872993 best dqsien dly found for B0: ( 0, 15, 12)
3377 14:47:08.876477 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3378 14:47:08.879615 Total UI for P1: 0, mck2ui 16
3379 14:47:08.882918 best dqsien dly found for B1: ( 0, 15, 14)
3380 14:47:08.886612 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3381 14:47:08.889738 best DQS1 dly(MCK, UI, PI) = (0, 15, 14)
3382 14:47:08.890180
3383 14:47:08.896379 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3384 14:47:08.899607 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 14)
3385 14:47:08.903029 [Gating] SW calibration Done
3386 14:47:08.903470 ==
3387 14:47:08.906340 Dram Type= 6, Freq= 0, CH_1, rank 1
3388 14:47:08.909198 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3389 14:47:08.909279 ==
3390 14:47:08.909353 RX Vref Scan: 0
3391 14:47:08.909412
3392 14:47:08.912535 RX Vref 0 -> 0, step: 1
3393 14:47:08.912621
3394 14:47:08.915775 RX Delay -40 -> 252, step: 8
3395 14:47:08.918973 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3396 14:47:08.922421 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3397 14:47:08.928919 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3398 14:47:08.932418 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3399 14:47:08.935671 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3400 14:47:08.939197 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3401 14:47:08.942498 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3402 14:47:08.949110 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3403 14:47:08.952173 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3404 14:47:08.955644 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3405 14:47:08.959063 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3406 14:47:08.962704 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3407 14:47:08.965563 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3408 14:47:08.972785 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3409 14:47:08.975490 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3410 14:47:08.979074 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3411 14:47:08.979149 ==
3412 14:47:08.982402 Dram Type= 6, Freq= 0, CH_1, rank 1
3413 14:47:08.985431 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3414 14:47:08.989064 ==
3415 14:47:08.989132 DQS Delay:
3416 14:47:08.989190 DQS0 = 0, DQS1 = 0
3417 14:47:08.992232 DQM Delay:
3418 14:47:08.992298 DQM0 = 117, DQM1 = 105
3419 14:47:08.995790 DQ Delay:
3420 14:47:08.999080 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3421 14:47:09.002493 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3422 14:47:09.005469 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
3423 14:47:09.009062 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3424 14:47:09.009130
3425 14:47:09.009187
3426 14:47:09.009241 ==
3427 14:47:09.012060 Dram Type= 6, Freq= 0, CH_1, rank 1
3428 14:47:09.015527 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3429 14:47:09.015599 ==
3430 14:47:09.015656
3431 14:47:09.015710
3432 14:47:09.018740 TX Vref Scan disable
3433 14:47:09.022071 == TX Byte 0 ==
3434 14:47:09.025540 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3435 14:47:09.028978 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3436 14:47:09.032109 == TX Byte 1 ==
3437 14:47:09.035399 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3438 14:47:09.038796 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3439 14:47:09.038876 ==
3440 14:47:09.041999 Dram Type= 6, Freq= 0, CH_1, rank 1
3441 14:47:09.045614 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3442 14:47:09.048778 ==
3443 14:47:09.058841 TX Vref=22, minBit 3, minWin=25, winSum=419
3444 14:47:09.062014 TX Vref=24, minBit 9, minWin=25, winSum=427
3445 14:47:09.065116 TX Vref=26, minBit 3, minWin=26, winSum=431
3446 14:47:09.068440 TX Vref=28, minBit 8, minWin=26, winSum=431
3447 14:47:09.071678 TX Vref=30, minBit 9, minWin=26, winSum=431
3448 14:47:09.075480 TX Vref=32, minBit 0, minWin=26, winSum=430
3449 14:47:09.082251 [TxChooseVref] Worse bit 3, Min win 26, Win sum 431, Final Vref 26
3450 14:47:09.082324
3451 14:47:09.085133 Final TX Range 1 Vref 26
3452 14:47:09.085202
3453 14:47:09.085266 ==
3454 14:47:09.088491 Dram Type= 6, Freq= 0, CH_1, rank 1
3455 14:47:09.092047 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3456 14:47:09.092116 ==
3457 14:47:09.092173
3458 14:47:09.095484
3459 14:47:09.095549 TX Vref Scan disable
3460 14:47:09.098829 == TX Byte 0 ==
3461 14:47:09.101908 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3462 14:47:09.105582 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3463 14:47:09.108670 == TX Byte 1 ==
3464 14:47:09.111708 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3465 14:47:09.115259 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3466 14:47:09.115333
3467 14:47:09.118551 [DATLAT]
3468 14:47:09.118620 Freq=1200, CH1 RK1
3469 14:47:09.118679
3470 14:47:09.122378 DATLAT Default: 0xc
3471 14:47:09.122464 0, 0xFFFF, sum = 0
3472 14:47:09.125470 1, 0xFFFF, sum = 0
3473 14:47:09.125552 2, 0xFFFF, sum = 0
3474 14:47:09.128508 3, 0xFFFF, sum = 0
3475 14:47:09.128590 4, 0xFFFF, sum = 0
3476 14:47:09.132167 5, 0xFFFF, sum = 0
3477 14:47:09.132249 6, 0xFFFF, sum = 0
3478 14:47:09.135308 7, 0xFFFF, sum = 0
3479 14:47:09.135390 8, 0xFFFF, sum = 0
3480 14:47:09.138464 9, 0xFFFF, sum = 0
3481 14:47:09.141884 10, 0xFFFF, sum = 0
3482 14:47:09.141966 11, 0x0, sum = 1
3483 14:47:09.142031 12, 0x0, sum = 2
3484 14:47:09.145254 13, 0x0, sum = 3
3485 14:47:09.145402 14, 0x0, sum = 4
3486 14:47:09.148434 best_step = 12
3487 14:47:09.148515
3488 14:47:09.148578 ==
3489 14:47:09.151886 Dram Type= 6, Freq= 0, CH_1, rank 1
3490 14:47:09.155050 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3491 14:47:09.155155 ==
3492 14:47:09.158429 RX Vref Scan: 0
3493 14:47:09.158520
3494 14:47:09.158584 RX Vref 0 -> 0, step: 1
3495 14:47:09.158644
3496 14:47:09.161669 RX Delay -29 -> 252, step: 4
3497 14:47:09.168933 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3498 14:47:09.172108 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3499 14:47:09.175548 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3500 14:47:09.178778 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3501 14:47:09.182299 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3502 14:47:09.188731 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3503 14:47:09.192164 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3504 14:47:09.195472 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3505 14:47:09.198824 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3506 14:47:09.202268 iDelay=199, Bit 9, Center 90 (23 ~ 158) 136
3507 14:47:09.208731 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3508 14:47:09.212238 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3509 14:47:09.215740 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3510 14:47:09.218684 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3511 14:47:09.221908 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3512 14:47:09.228799 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3513 14:47:09.228880 ==
3514 14:47:09.231859 Dram Type= 6, Freq= 0, CH_1, rank 1
3515 14:47:09.235433 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3516 14:47:09.235514 ==
3517 14:47:09.235582 DQS Delay:
3518 14:47:09.238584 DQS0 = 0, DQS1 = 0
3519 14:47:09.238665 DQM Delay:
3520 14:47:09.241755 DQM0 = 114, DQM1 = 103
3521 14:47:09.241836 DQ Delay:
3522 14:47:09.245080 DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =112
3523 14:47:09.248631 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3524 14:47:09.251823 DQ8 =86, DQ9 =90, DQ10 =106, DQ11 =98
3525 14:47:09.255107 DQ12 =112, DQ13 =112, DQ14 =112, DQ15 =110
3526 14:47:09.255201
3527 14:47:09.255296
3528 14:47:09.265049 [DQSOSCAuto] RK1, (LSB)MR18= 0x808, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
3529 14:47:09.268331 CH1 RK1: MR19=404, MR18=808
3530 14:47:09.271793 CH1_RK1: MR19=0x404, MR18=0x808, DQSOSC=406, MR23=63, INC=39, DEC=26
3531 14:47:09.275138 [RxdqsGatingPostProcess] freq 1200
3532 14:47:09.281757 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3533 14:47:09.285469 Pre-setting of DQS Precalculation
3534 14:47:09.288460 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3535 14:47:09.298182 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3536 14:47:09.305057 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3537 14:47:09.305160
3538 14:47:09.305224
3539 14:47:09.308368 [Calibration Summary] 2400 Mbps
3540 14:47:09.308450 CH 0, Rank 0
3541 14:47:09.311787 SW Impedance : PASS
3542 14:47:09.311868 DUTY Scan : NO K
3543 14:47:09.315084 ZQ Calibration : PASS
3544 14:47:09.318619 Jitter Meter : NO K
3545 14:47:09.318700 CBT Training : PASS
3546 14:47:09.321554 Write leveling : PASS
3547 14:47:09.325275 RX DQS gating : PASS
3548 14:47:09.325396 RX DQ/DQS(RDDQC) : PASS
3549 14:47:09.328294 TX DQ/DQS : PASS
3550 14:47:09.331956 RX DATLAT : PASS
3551 14:47:09.332037 RX DQ/DQS(Engine): PASS
3552 14:47:09.335291 TX OE : NO K
3553 14:47:09.335372 All Pass.
3554 14:47:09.335436
3555 14:47:09.338168 CH 0, Rank 1
3556 14:47:09.338248 SW Impedance : PASS
3557 14:47:09.341605 DUTY Scan : NO K
3558 14:47:09.341686 ZQ Calibration : PASS
3559 14:47:09.344958 Jitter Meter : NO K
3560 14:47:09.348342 CBT Training : PASS
3561 14:47:09.348423 Write leveling : PASS
3562 14:47:09.351596 RX DQS gating : PASS
3563 14:47:09.354905 RX DQ/DQS(RDDQC) : PASS
3564 14:47:09.354986 TX DQ/DQS : PASS
3565 14:47:09.358455 RX DATLAT : PASS
3566 14:47:09.361515 RX DQ/DQS(Engine): PASS
3567 14:47:09.361596 TX OE : NO K
3568 14:47:09.364956 All Pass.
3569 14:47:09.365036
3570 14:47:09.365100 CH 1, Rank 0
3571 14:47:09.368364 SW Impedance : PASS
3572 14:47:09.368446 DUTY Scan : NO K
3573 14:47:09.371852 ZQ Calibration : PASS
3574 14:47:09.375087 Jitter Meter : NO K
3575 14:47:09.375168 CBT Training : PASS
3576 14:47:09.378212 Write leveling : PASS
3577 14:47:09.381545 RX DQS gating : PASS
3578 14:47:09.381625 RX DQ/DQS(RDDQC) : PASS
3579 14:47:09.384969 TX DQ/DQS : PASS
3580 14:47:09.388245 RX DATLAT : PASS
3581 14:47:09.388326 RX DQ/DQS(Engine): PASS
3582 14:47:09.391513 TX OE : NO K
3583 14:47:09.391594 All Pass.
3584 14:47:09.391657
3585 14:47:09.394842 CH 1, Rank 1
3586 14:47:09.394923 SW Impedance : PASS
3587 14:47:09.398420 DUTY Scan : NO K
3588 14:47:09.398500 ZQ Calibration : PASS
3589 14:47:09.401867 Jitter Meter : NO K
3590 14:47:09.405035 CBT Training : PASS
3591 14:47:09.405116 Write leveling : PASS
3592 14:47:09.408135 RX DQS gating : PASS
3593 14:47:09.411423 RX DQ/DQS(RDDQC) : PASS
3594 14:47:09.411504 TX DQ/DQS : PASS
3595 14:47:09.414951 RX DATLAT : PASS
3596 14:47:09.418229 RX DQ/DQS(Engine): PASS
3597 14:47:09.418311 TX OE : NO K
3598 14:47:09.421668 All Pass.
3599 14:47:09.421748
3600 14:47:09.421811 DramC Write-DBI off
3601 14:47:09.425159 PER_BANK_REFRESH: Hybrid Mode
3602 14:47:09.425240 TX_TRACKING: ON
3603 14:47:09.434816 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3604 14:47:09.438698 [FAST_K] Save calibration result to emmc
3605 14:47:09.441487 dramc_set_vcore_voltage set vcore to 650000
3606 14:47:09.445138 Read voltage for 600, 5
3607 14:47:09.445219 Vio18 = 0
3608 14:47:09.448030 Vcore = 650000
3609 14:47:09.448110 Vdram = 0
3610 14:47:09.448206 Vddq = 0
3611 14:47:09.448264 Vmddr = 0
3612 14:47:09.454598 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3613 14:47:09.461267 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3614 14:47:09.461387 MEM_TYPE=3, freq_sel=19
3615 14:47:09.464537 sv_algorithm_assistance_LP4_1600
3616 14:47:09.467901 ============ PULL DRAM RESETB DOWN ============
3617 14:47:09.474522 ========== PULL DRAM RESETB DOWN end =========
3618 14:47:09.477925 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3619 14:47:09.481451 ===================================
3620 14:47:09.484411 LPDDR4 DRAM CONFIGURATION
3621 14:47:09.487819 ===================================
3622 14:47:09.487901 EX_ROW_EN[0] = 0x0
3623 14:47:09.490927 EX_ROW_EN[1] = 0x0
3624 14:47:09.494417 LP4Y_EN = 0x0
3625 14:47:09.494498 WORK_FSP = 0x0
3626 14:47:09.497578 WL = 0x2
3627 14:47:09.497658 RL = 0x2
3628 14:47:09.500983 BL = 0x2
3629 14:47:09.501081 RPST = 0x0
3630 14:47:09.503951 RD_PRE = 0x0
3631 14:47:09.504043 WR_PRE = 0x1
3632 14:47:09.507396 WR_PST = 0x0
3633 14:47:09.507490 DBI_WR = 0x0
3634 14:47:09.510821 DBI_RD = 0x0
3635 14:47:09.510902 OTF = 0x1
3636 14:47:09.514059 ===================================
3637 14:47:09.517230 ===================================
3638 14:47:09.520588 ANA top config
3639 14:47:09.524268 ===================================
3640 14:47:09.524349 DLL_ASYNC_EN = 0
3641 14:47:09.527357 ALL_SLAVE_EN = 1
3642 14:47:09.530742 NEW_RANK_MODE = 1
3643 14:47:09.534047 DLL_IDLE_MODE = 1
3644 14:47:09.537257 LP45_APHY_COMB_EN = 1
3645 14:47:09.537344 TX_ODT_DIS = 1
3646 14:47:09.540755 NEW_8X_MODE = 1
3647 14:47:09.543760 ===================================
3648 14:47:09.547031 ===================================
3649 14:47:09.550306 data_rate = 1200
3650 14:47:09.553973 CKR = 1
3651 14:47:09.557169 DQ_P2S_RATIO = 8
3652 14:47:09.560241 ===================================
3653 14:47:09.563609 CA_P2S_RATIO = 8
3654 14:47:09.563691 DQ_CA_OPEN = 0
3655 14:47:09.566823 DQ_SEMI_OPEN = 0
3656 14:47:09.570363 CA_SEMI_OPEN = 0
3657 14:47:09.573441 CA_FULL_RATE = 0
3658 14:47:09.576711 DQ_CKDIV4_EN = 1
3659 14:47:09.580536 CA_CKDIV4_EN = 1
3660 14:47:09.580609 CA_PREDIV_EN = 0
3661 14:47:09.583504 PH8_DLY = 0
3662 14:47:09.587128 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3663 14:47:09.590587 DQ_AAMCK_DIV = 4
3664 14:47:09.593536 CA_AAMCK_DIV = 4
3665 14:47:09.596733 CA_ADMCK_DIV = 4
3666 14:47:09.596803 DQ_TRACK_CA_EN = 0
3667 14:47:09.600096 CA_PICK = 600
3668 14:47:09.603655 CA_MCKIO = 600
3669 14:47:09.606993 MCKIO_SEMI = 0
3670 14:47:09.610419 PLL_FREQ = 2288
3671 14:47:09.613390 DQ_UI_PI_RATIO = 32
3672 14:47:09.616822 CA_UI_PI_RATIO = 0
3673 14:47:09.620087 ===================================
3674 14:47:09.623262 ===================================
3675 14:47:09.623344 memory_type:LPDDR4
3676 14:47:09.626805 GP_NUM : 10
3677 14:47:09.629882 SRAM_EN : 1
3678 14:47:09.629963 MD32_EN : 0
3679 14:47:09.633224 ===================================
3680 14:47:09.636822 [ANA_INIT] >>>>>>>>>>>>>>
3681 14:47:09.640197 <<<<<< [CONFIGURE PHASE]: ANA_TX
3682 14:47:09.643228 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3683 14:47:09.646510 ===================================
3684 14:47:09.649644 data_rate = 1200,PCW = 0X5800
3685 14:47:09.653135 ===================================
3686 14:47:09.656501 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3687 14:47:09.659722 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3688 14:47:09.666452 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3689 14:47:09.669798 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3690 14:47:09.673222 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3691 14:47:09.676517 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3692 14:47:09.679952 [ANA_INIT] flow start
3693 14:47:09.682923 [ANA_INIT] PLL >>>>>>>>
3694 14:47:09.683004 [ANA_INIT] PLL <<<<<<<<
3695 14:47:09.686593 [ANA_INIT] MIDPI >>>>>>>>
3696 14:47:09.689587 [ANA_INIT] MIDPI <<<<<<<<
3697 14:47:09.689668 [ANA_INIT] DLL >>>>>>>>
3698 14:47:09.692969 [ANA_INIT] flow end
3699 14:47:09.696274 ============ LP4 DIFF to SE enter ============
3700 14:47:09.703278 ============ LP4 DIFF to SE exit ============
3701 14:47:09.703360 [ANA_INIT] <<<<<<<<<<<<<
3702 14:47:09.706243 [Flow] Enable top DCM control >>>>>
3703 14:47:09.709648 [Flow] Enable top DCM control <<<<<
3704 14:47:09.713004 Enable DLL master slave shuffle
3705 14:47:09.719677 ==============================================================
3706 14:47:09.719759 Gating Mode config
3707 14:47:09.725991 ==============================================================
3708 14:47:09.729338 Config description:
3709 14:47:09.736041 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3710 14:47:09.742972 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3711 14:47:09.749333 SELPH_MODE 0: By rank 1: By Phase
3712 14:47:09.755868 ==============================================================
3713 14:47:09.755953 GAT_TRACK_EN = 1
3714 14:47:09.759347 RX_GATING_MODE = 2
3715 14:47:09.762794 RX_GATING_TRACK_MODE = 2
3716 14:47:09.766149 SELPH_MODE = 1
3717 14:47:09.769236 PICG_EARLY_EN = 1
3718 14:47:09.772500 VALID_LAT_VALUE = 1
3719 14:47:09.779273 ==============================================================
3720 14:47:09.782301 Enter into Gating configuration >>>>
3721 14:47:09.786012 Exit from Gating configuration <<<<
3722 14:47:09.788830 Enter into DVFS_PRE_config >>>>>
3723 14:47:09.799067 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3724 14:47:09.802185 Exit from DVFS_PRE_config <<<<<
3725 14:47:09.805834 Enter into PICG configuration >>>>
3726 14:47:09.808800 Exit from PICG configuration <<<<
3727 14:47:09.812576 [RX_INPUT] configuration >>>>>
3728 14:47:09.812643 [RX_INPUT] configuration <<<<<
3729 14:47:09.819084 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3730 14:47:09.825876 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3731 14:47:09.832185 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3732 14:47:09.835538 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3733 14:47:09.842028 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3734 14:47:09.848768 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3735 14:47:09.852063 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3736 14:47:09.855293 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3737 14:47:09.862197 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3738 14:47:09.865369 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3739 14:47:09.868684 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3740 14:47:09.875399 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3741 14:47:09.878501 ===================================
3742 14:47:09.878671 LPDDR4 DRAM CONFIGURATION
3743 14:47:09.881903 ===================================
3744 14:47:09.885006 EX_ROW_EN[0] = 0x0
3745 14:47:09.888508 EX_ROW_EN[1] = 0x0
3746 14:47:09.888582 LP4Y_EN = 0x0
3747 14:47:09.891636 WORK_FSP = 0x0
3748 14:47:09.891710 WL = 0x2
3749 14:47:09.895017 RL = 0x2
3750 14:47:09.895089 BL = 0x2
3751 14:47:09.898384 RPST = 0x0
3752 14:47:09.898456 RD_PRE = 0x0
3753 14:47:09.901665 WR_PRE = 0x1
3754 14:47:09.901731 WR_PST = 0x0
3755 14:47:09.905115 DBI_WR = 0x0
3756 14:47:09.905254 DBI_RD = 0x0
3757 14:47:09.908257 OTF = 0x1
3758 14:47:09.911467 ===================================
3759 14:47:09.915053 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3760 14:47:09.918106 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3761 14:47:09.924950 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3762 14:47:09.928016 ===================================
3763 14:47:09.928115 LPDDR4 DRAM CONFIGURATION
3764 14:47:09.931482 ===================================
3765 14:47:09.934792 EX_ROW_EN[0] = 0x10
3766 14:47:09.938112 EX_ROW_EN[1] = 0x0
3767 14:47:09.938192 LP4Y_EN = 0x0
3768 14:47:09.941198 WORK_FSP = 0x0
3769 14:47:09.941340 WL = 0x2
3770 14:47:09.944625 RL = 0x2
3771 14:47:09.944735 BL = 0x2
3772 14:47:09.948223 RPST = 0x0
3773 14:47:09.948304 RD_PRE = 0x0
3774 14:47:09.951469 WR_PRE = 0x1
3775 14:47:09.951551 WR_PST = 0x0
3776 14:47:09.954517 DBI_WR = 0x0
3777 14:47:09.954599 DBI_RD = 0x0
3778 14:47:09.957730 OTF = 0x1
3779 14:47:09.961439 ===================================
3780 14:47:09.967719 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3781 14:47:09.971045 nWR fixed to 30
3782 14:47:09.971127 [ModeRegInit_LP4] CH0 RK0
3783 14:47:09.974290 [ModeRegInit_LP4] CH0 RK1
3784 14:47:09.977828 [ModeRegInit_LP4] CH1 RK0
3785 14:47:09.981134 [ModeRegInit_LP4] CH1 RK1
3786 14:47:09.981241 match AC timing 16
3787 14:47:09.987738 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3788 14:47:09.991036 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3789 14:47:09.994348 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3790 14:47:10.000982 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3791 14:47:10.004396 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3792 14:47:10.004478 ==
3793 14:47:10.007460 Dram Type= 6, Freq= 0, CH_0, rank 0
3794 14:47:10.010761 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3795 14:47:10.010844 ==
3796 14:47:10.017579 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3797 14:47:10.024097 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3798 14:47:10.027475 [CA 0] Center 35 (5~66) winsize 62
3799 14:47:10.030743 [CA 1] Center 35 (5~66) winsize 62
3800 14:47:10.033749 [CA 2] Center 34 (4~65) winsize 62
3801 14:47:10.037194 [CA 3] Center 34 (4~65) winsize 62
3802 14:47:10.040529 [CA 4] Center 33 (3~64) winsize 62
3803 14:47:10.043755 [CA 5] Center 33 (3~64) winsize 62
3804 14:47:10.043837
3805 14:47:10.047543 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3806 14:47:10.047625
3807 14:47:10.050769 [CATrainingPosCal] consider 1 rank data
3808 14:47:10.053831 u2DelayCellTimex100 = 270/100 ps
3809 14:47:10.056966 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3810 14:47:10.060522 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3811 14:47:10.063342 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3812 14:47:10.067135 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3813 14:47:10.070366 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3814 14:47:10.073232 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3815 14:47:10.076767
3816 14:47:10.079941 CA PerBit enable=1, Macro0, CA PI delay=33
3817 14:47:10.080021
3818 14:47:10.083481 [CBTSetCACLKResult] CA Dly = 33
3819 14:47:10.083562 CS Dly: 5 (0~36)
3820 14:47:10.083625 ==
3821 14:47:10.086658 Dram Type= 6, Freq= 0, CH_0, rank 1
3822 14:47:10.089988 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3823 14:47:10.090069 ==
3824 14:47:10.096839 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3825 14:47:10.103217 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3826 14:47:10.106457 [CA 0] Center 36 (6~66) winsize 61
3827 14:47:10.109723 [CA 1] Center 35 (5~66) winsize 62
3828 14:47:10.113070 [CA 2] Center 34 (4~65) winsize 62
3829 14:47:10.116407 [CA 3] Center 34 (4~65) winsize 62
3830 14:47:10.120104 [CA 4] Center 33 (3~64) winsize 62
3831 14:47:10.123074 [CA 5] Center 33 (3~64) winsize 62
3832 14:47:10.123155
3833 14:47:10.126260 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3834 14:47:10.126342
3835 14:47:10.129820 [CATrainingPosCal] consider 2 rank data
3836 14:47:10.133242 u2DelayCellTimex100 = 270/100 ps
3837 14:47:10.136477 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3838 14:47:10.139672 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3839 14:47:10.142916 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3840 14:47:10.146356 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3841 14:47:10.152950 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3842 14:47:10.156254 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3843 14:47:10.156335
3844 14:47:10.159712 CA PerBit enable=1, Macro0, CA PI delay=33
3845 14:47:10.159794
3846 14:47:10.162832 [CBTSetCACLKResult] CA Dly = 33
3847 14:47:10.162913 CS Dly: 5 (0~36)
3848 14:47:10.162976
3849 14:47:10.166286 ----->DramcWriteLeveling(PI) begin...
3850 14:47:10.166368 ==
3851 14:47:10.169419 Dram Type= 6, Freq= 0, CH_0, rank 0
3852 14:47:10.175864 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3853 14:47:10.175945 ==
3854 14:47:10.179405 Write leveling (Byte 0): 31 => 31
3855 14:47:10.182796 Write leveling (Byte 1): 30 => 30
3856 14:47:10.182878 DramcWriteLeveling(PI) end<-----
3857 14:47:10.186014
3858 14:47:10.186094 ==
3859 14:47:10.189146 Dram Type= 6, Freq= 0, CH_0, rank 0
3860 14:47:10.192691 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3861 14:47:10.192772 ==
3862 14:47:10.196084 [Gating] SW mode calibration
3863 14:47:10.202362 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3864 14:47:10.205786 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3865 14:47:10.212215 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3866 14:47:10.215824 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3867 14:47:10.218772 0 5 8 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 0)
3868 14:47:10.225515 0 5 12 | B1->B0 | 2828 2323 | 0 0 | (1 0) (1 0)
3869 14:47:10.228798 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3870 14:47:10.232154 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3871 14:47:10.239093 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3872 14:47:10.242396 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3873 14:47:10.245518 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3874 14:47:10.252227 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3875 14:47:10.255401 0 6 8 | B1->B0 | 2929 3333 | 0 0 | (0 0) (1 1)
3876 14:47:10.258919 0 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3877 14:47:10.265493 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3878 14:47:10.268774 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3879 14:47:10.272367 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3880 14:47:10.278566 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3881 14:47:10.282069 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3882 14:47:10.285272 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3883 14:47:10.292558 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3884 14:47:10.295364 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3885 14:47:10.298559 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3886 14:47:10.305474 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3887 14:47:10.309076 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3888 14:47:10.311968 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3889 14:47:10.318737 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3890 14:47:10.321898 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3891 14:47:10.325075 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3892 14:47:10.331815 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3893 14:47:10.335121 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3894 14:47:10.338531 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3895 14:47:10.344977 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3896 14:47:10.348246 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3897 14:47:10.351548 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3898 14:47:10.358093 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3899 14:47:10.361668 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3900 14:47:10.364958 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3901 14:47:10.371521 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3902 14:47:10.371597 Total UI for P1: 0, mck2ui 16
3903 14:47:10.374833 best dqsien dly found for B0: ( 0, 9, 10)
3904 14:47:10.378427 Total UI for P1: 0, mck2ui 16
3905 14:47:10.381155 best dqsien dly found for B1: ( 0, 9, 12)
3906 14:47:10.387749 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
3907 14:47:10.391171 best DQS1 dly(MCK, UI, PI) = (0, 9, 12)
3908 14:47:10.391247
3909 14:47:10.394660 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
3910 14:47:10.397806 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 12)
3911 14:47:10.401195 [Gating] SW calibration Done
3912 14:47:10.401269 ==
3913 14:47:10.404321 Dram Type= 6, Freq= 0, CH_0, rank 0
3914 14:47:10.407591 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3915 14:47:10.407659 ==
3916 14:47:10.411010 RX Vref Scan: 0
3917 14:47:10.411097
3918 14:47:10.411168 RX Vref 0 -> 0, step: 1
3919 14:47:10.411222
3920 14:47:10.414239 RX Delay -230 -> 252, step: 16
3921 14:47:10.417467 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3922 14:47:10.424362 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
3923 14:47:10.427406 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3924 14:47:10.430729 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3925 14:47:10.434021 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3926 14:47:10.440564 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3927 14:47:10.443956 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3928 14:47:10.447102 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3929 14:47:10.450615 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3930 14:47:10.457472 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3931 14:47:10.460721 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3932 14:47:10.463578 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3933 14:47:10.467139 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3934 14:47:10.473858 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3935 14:47:10.476987 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3936 14:47:10.480366 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3937 14:47:10.480442 ==
3938 14:47:10.483717 Dram Type= 6, Freq= 0, CH_0, rank 0
3939 14:47:10.486982 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3940 14:47:10.487059 ==
3941 14:47:10.490481 DQS Delay:
3942 14:47:10.490554 DQS0 = 0, DQS1 = 0
3943 14:47:10.493882 DQM Delay:
3944 14:47:10.493951 DQM0 = 39, DQM1 = 33
3945 14:47:10.494010 DQ Delay:
3946 14:47:10.497203 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
3947 14:47:10.500319 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3948 14:47:10.503842 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3949 14:47:10.506840 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3950 14:47:10.506911
3951 14:47:10.506969
3952 14:47:10.510071 ==
3953 14:47:10.513457 Dram Type= 6, Freq= 0, CH_0, rank 0
3954 14:47:10.516846 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3955 14:47:10.516928 ==
3956 14:47:10.516991
3957 14:47:10.517050
3958 14:47:10.520214 TX Vref Scan disable
3959 14:47:10.520295 == TX Byte 0 ==
3960 14:47:10.526708 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3961 14:47:10.530058 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3962 14:47:10.530140 == TX Byte 1 ==
3963 14:47:10.536553 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3964 14:47:10.539878 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3965 14:47:10.539960 ==
3966 14:47:10.543068 Dram Type= 6, Freq= 0, CH_0, rank 0
3967 14:47:10.546244 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3968 14:47:10.546325 ==
3969 14:47:10.546388
3970 14:47:10.546447
3971 14:47:10.549793 TX Vref Scan disable
3972 14:47:10.553097 == TX Byte 0 ==
3973 14:47:10.556175 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3974 14:47:10.559454 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3975 14:47:10.563051 == TX Byte 1 ==
3976 14:47:10.566287 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3977 14:47:10.569442 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3978 14:47:10.569524
3979 14:47:10.573027 [DATLAT]
3980 14:47:10.573107 Freq=600, CH0 RK0
3981 14:47:10.573170
3982 14:47:10.576020 DATLAT Default: 0x9
3983 14:47:10.576101 0, 0xFFFF, sum = 0
3984 14:47:10.579759 1, 0xFFFF, sum = 0
3985 14:47:10.579842 2, 0xFFFF, sum = 0
3986 14:47:10.582937 3, 0xFFFF, sum = 0
3987 14:47:10.583019 4, 0xFFFF, sum = 0
3988 14:47:10.586107 5, 0xFFFF, sum = 0
3989 14:47:10.586190 6, 0xFFFF, sum = 0
3990 14:47:10.589709 7, 0x0, sum = 1
3991 14:47:10.589792 8, 0x0, sum = 2
3992 14:47:10.592885 9, 0x0, sum = 3
3993 14:47:10.592967 10, 0x0, sum = 4
3994 14:47:10.596236 best_step = 8
3995 14:47:10.596316
3996 14:47:10.596379 ==
3997 14:47:10.599629 Dram Type= 6, Freq= 0, CH_0, rank 0
3998 14:47:10.602785 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3999 14:47:10.602866 ==
4000 14:47:10.606022 RX Vref Scan: 1
4001 14:47:10.606103
4002 14:47:10.606166 RX Vref 0 -> 0, step: 1
4003 14:47:10.606225
4004 14:47:10.609502 RX Delay -195 -> 252, step: 8
4005 14:47:10.609583
4006 14:47:10.612627 Set Vref, RX VrefLevel [Byte0]: 49
4007 14:47:10.615867 [Byte1]: 51
4008 14:47:10.619779
4009 14:47:10.619859 Final RX Vref Byte 0 = 49 to rank0
4010 14:47:10.622825 Final RX Vref Byte 1 = 51 to rank0
4011 14:47:10.626166 Final RX Vref Byte 0 = 49 to rank1
4012 14:47:10.629745 Final RX Vref Byte 1 = 51 to rank1==
4013 14:47:10.632865 Dram Type= 6, Freq= 0, CH_0, rank 0
4014 14:47:10.639517 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4015 14:47:10.639626 ==
4016 14:47:10.639718 DQS Delay:
4017 14:47:10.642740 DQS0 = 0, DQS1 = 0
4018 14:47:10.642838 DQM Delay:
4019 14:47:10.642928 DQM0 = 39, DQM1 = 30
4020 14:47:10.645985 DQ Delay:
4021 14:47:10.649303 DQ0 =32, DQ1 =40, DQ2 =40, DQ3 =36
4022 14:47:10.652740 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =48
4023 14:47:10.656064 DQ8 =20, DQ9 =12, DQ10 =32, DQ11 =20
4024 14:47:10.659212 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4025 14:47:10.659315
4026 14:47:10.659408
4027 14:47:10.665720 [DQSOSCAuto] RK0, (LSB)MR18= 0x5050, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
4028 14:47:10.669237 CH0 RK0: MR19=808, MR18=5050
4029 14:47:10.675684 CH0_RK0: MR19=0x808, MR18=0x5050, DQSOSC=394, MR23=63, INC=168, DEC=112
4030 14:47:10.675782
4031 14:47:10.679442 ----->DramcWriteLeveling(PI) begin...
4032 14:47:10.679538 ==
4033 14:47:10.682227 Dram Type= 6, Freq= 0, CH_0, rank 1
4034 14:47:10.685704 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4035 14:47:10.685781 ==
4036 14:47:10.688947 Write leveling (Byte 0): 32 => 32
4037 14:47:10.692662 Write leveling (Byte 1): 28 => 28
4038 14:47:10.695789 DramcWriteLeveling(PI) end<-----
4039 14:47:10.695889
4040 14:47:10.695976 ==
4041 14:47:10.698840 Dram Type= 6, Freq= 0, CH_0, rank 1
4042 14:47:10.702322 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4043 14:47:10.705922 ==
4044 14:47:10.705992 [Gating] SW mode calibration
4045 14:47:10.715454 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4046 14:47:10.718895 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4047 14:47:10.722136 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4048 14:47:10.728844 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4049 14:47:10.731972 0 5 8 | B1->B0 | 3333 3131 | 1 0 | (1 0) (1 1)
4050 14:47:10.735244 0 5 12 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4051 14:47:10.742225 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 14:47:10.745127 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 14:47:10.748923 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 14:47:10.755199 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 14:47:10.758445 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 14:47:10.761957 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 14:47:10.768335 0 6 8 | B1->B0 | 2a2a 3434 | 1 0 | (0 0) (0 0)
4058 14:47:10.771783 0 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4059 14:47:10.775137 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 14:47:10.781729 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 14:47:10.785082 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 14:47:10.788248 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 14:47:10.795094 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 14:47:10.798004 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4065 14:47:10.801357 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4066 14:47:10.808164 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 14:47:10.811529 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 14:47:10.814918 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 14:47:10.821495 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 14:47:10.824994 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 14:47:10.828149 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 14:47:10.834809 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 14:47:10.838337 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 14:47:10.841353 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 14:47:10.847857 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 14:47:10.850922 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 14:47:10.854161 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 14:47:10.860765 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 14:47:10.864546 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 14:47:10.867464 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4081 14:47:10.874031 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4082 14:47:10.877352 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4083 14:47:10.880756 Total UI for P1: 0, mck2ui 16
4084 14:47:10.884236 best dqsien dly found for B0: ( 0, 9, 10)
4085 14:47:10.887545 Total UI for P1: 0, mck2ui 16
4086 14:47:10.890715 best dqsien dly found for B1: ( 0, 9, 6)
4087 14:47:10.893977 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
4088 14:47:10.897530 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4089 14:47:10.897625
4090 14:47:10.900657 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
4091 14:47:10.903966 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4092 14:47:10.907161 [Gating] SW calibration Done
4093 14:47:10.907261 ==
4094 14:47:10.910592 Dram Type= 6, Freq= 0, CH_0, rank 1
4095 14:47:10.913931 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4096 14:47:10.914002 ==
4097 14:47:10.917239 RX Vref Scan: 0
4098 14:47:10.917352
4099 14:47:10.920347 RX Vref 0 -> 0, step: 1
4100 14:47:10.920446
4101 14:47:10.920534 RX Delay -230 -> 252, step: 16
4102 14:47:10.927142 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4103 14:47:10.931086 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4104 14:47:10.933868 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4105 14:47:10.937019 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4106 14:47:10.944005 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4107 14:47:10.946974 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4108 14:47:10.950577 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4109 14:47:10.953501 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4110 14:47:10.960209 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4111 14:47:10.963499 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4112 14:47:10.966901 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4113 14:47:10.970115 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4114 14:47:10.976844 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4115 14:47:10.980046 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4116 14:47:10.983868 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4117 14:47:10.986687 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4118 14:47:10.986784 ==
4119 14:47:10.989817 Dram Type= 6, Freq= 0, CH_0, rank 1
4120 14:47:10.996561 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4121 14:47:10.996661 ==
4122 14:47:10.996750 DQS Delay:
4123 14:47:10.999747 DQS0 = 0, DQS1 = 0
4124 14:47:10.999842 DQM Delay:
4125 14:47:10.999928 DQM0 = 41, DQM1 = 33
4126 14:47:11.003416 DQ Delay:
4127 14:47:11.006633 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4128 14:47:11.010077 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4129 14:47:11.013317 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4130 14:47:11.016347 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4131 14:47:11.016413
4132 14:47:11.016472
4133 14:47:11.016528 ==
4134 14:47:11.019849 Dram Type= 6, Freq= 0, CH_0, rank 1
4135 14:47:11.023089 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4136 14:47:11.023160 ==
4137 14:47:11.023220
4138 14:47:11.023282
4139 14:47:11.026301 TX Vref Scan disable
4140 14:47:11.026368 == TX Byte 0 ==
4141 14:47:11.032900 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4142 14:47:11.036127 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4143 14:47:11.039844 == TX Byte 1 ==
4144 14:47:11.043276 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4145 14:47:11.046202 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4146 14:47:11.046296 ==
4147 14:47:11.049376 Dram Type= 6, Freq= 0, CH_0, rank 1
4148 14:47:11.052645 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4149 14:47:11.052736 ==
4150 14:47:11.056234
4151 14:47:11.056326
4152 14:47:11.056414 TX Vref Scan disable
4153 14:47:11.059868 == TX Byte 0 ==
4154 14:47:11.063106 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4155 14:47:11.069848 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4156 14:47:11.069951 == TX Byte 1 ==
4157 14:47:11.073147 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4158 14:47:11.079735 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4159 14:47:11.079833
4160 14:47:11.079922 [DATLAT]
4161 14:47:11.080010 Freq=600, CH0 RK1
4162 14:47:11.080094
4163 14:47:11.083375 DATLAT Default: 0x8
4164 14:47:11.083480 0, 0xFFFF, sum = 0
4165 14:47:11.086369 1, 0xFFFF, sum = 0
4166 14:47:11.089501 2, 0xFFFF, sum = 0
4167 14:47:11.089583 3, 0xFFFF, sum = 0
4168 14:47:11.093104 4, 0xFFFF, sum = 0
4169 14:47:11.093187 5, 0xFFFF, sum = 0
4170 14:47:11.096241 6, 0xFFFF, sum = 0
4171 14:47:11.096323 7, 0x0, sum = 1
4172 14:47:11.096389 8, 0x0, sum = 2
4173 14:47:11.099470 9, 0x0, sum = 3
4174 14:47:11.099555 10, 0x0, sum = 4
4175 14:47:11.102986 best_step = 8
4176 14:47:11.103067
4177 14:47:11.103130 ==
4178 14:47:11.106275 Dram Type= 6, Freq= 0, CH_0, rank 1
4179 14:47:11.109666 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4180 14:47:11.109752 ==
4181 14:47:11.112841 RX Vref Scan: 0
4182 14:47:11.112922
4183 14:47:11.112984 RX Vref 0 -> 0, step: 1
4184 14:47:11.113043
4185 14:47:11.116081 RX Delay -195 -> 252, step: 8
4186 14:47:11.123398 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4187 14:47:11.126846 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4188 14:47:11.130224 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4189 14:47:11.133642 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4190 14:47:11.140192 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4191 14:47:11.143690 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4192 14:47:11.146732 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4193 14:47:11.150007 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4194 14:47:11.153187 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4195 14:47:11.160147 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4196 14:47:11.163195 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4197 14:47:11.166800 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4198 14:47:11.170128 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4199 14:47:11.176863 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4200 14:47:11.180194 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4201 14:47:11.183686 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4202 14:47:11.183761 ==
4203 14:47:11.186638 Dram Type= 6, Freq= 0, CH_0, rank 1
4204 14:47:11.189855 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4205 14:47:11.193421 ==
4206 14:47:11.193501 DQS Delay:
4207 14:47:11.193564 DQS0 = 0, DQS1 = 0
4208 14:47:11.196652 DQM Delay:
4209 14:47:11.196753 DQM0 = 42, DQM1 = 31
4210 14:47:11.199965 DQ Delay:
4211 14:47:11.203768 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =36
4212 14:47:11.203870 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4213 14:47:11.206465 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4214 14:47:11.209694 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4215 14:47:11.212911
4216 14:47:11.212984
4217 14:47:11.219564 [DQSOSCAuto] RK1, (LSB)MR18= 0x6262, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4218 14:47:11.222931 CH0 RK1: MR19=808, MR18=6262
4219 14:47:11.229220 CH0_RK1: MR19=0x808, MR18=0x6262, DQSOSC=391, MR23=63, INC=171, DEC=114
4220 14:47:11.232677 [RxdqsGatingPostProcess] freq 600
4221 14:47:11.235946 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4222 14:47:11.239711 Pre-setting of DQS Precalculation
4223 14:47:11.245740 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4224 14:47:11.245815 ==
4225 14:47:11.249260 Dram Type= 6, Freq= 0, CH_1, rank 0
4226 14:47:11.252700 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4227 14:47:11.252798 ==
4228 14:47:11.259444 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4229 14:47:11.265853 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4230 14:47:11.269478 [CA 0] Center 35 (5~66) winsize 62
4231 14:47:11.272505 [CA 1] Center 35 (5~66) winsize 62
4232 14:47:11.275547 [CA 2] Center 33 (3~64) winsize 62
4233 14:47:11.279209 [CA 3] Center 33 (3~64) winsize 62
4234 14:47:11.282655 [CA 4] Center 33 (2~64) winsize 63
4235 14:47:11.282729 [CA 5] Center 33 (2~64) winsize 63
4236 14:47:11.285425
4237 14:47:11.288725 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4238 14:47:11.288793
4239 14:47:11.292182 [CATrainingPosCal] consider 1 rank data
4240 14:47:11.295375 u2DelayCellTimex100 = 270/100 ps
4241 14:47:11.298853 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4242 14:47:11.302330 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4243 14:47:11.305466 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4244 14:47:11.309115 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4245 14:47:11.312104 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4246 14:47:11.315344 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4247 14:47:11.315414
4248 14:47:11.318466 CA PerBit enable=1, Macro0, CA PI delay=33
4249 14:47:11.321838
4250 14:47:11.321916 [CBTSetCACLKResult] CA Dly = 33
4251 14:47:11.325210 CS Dly: 4 (0~35)
4252 14:47:11.325346 ==
4253 14:47:11.328701 Dram Type= 6, Freq= 0, CH_1, rank 1
4254 14:47:11.331739 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4255 14:47:11.331833 ==
4256 14:47:11.338343 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4257 14:47:11.345173 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4258 14:47:11.348694 [CA 0] Center 35 (5~66) winsize 62
4259 14:47:11.351961 [CA 1] Center 34 (4~65) winsize 62
4260 14:47:11.355168 [CA 2] Center 33 (3~64) winsize 62
4261 14:47:11.358550 [CA 3] Center 33 (3~64) winsize 62
4262 14:47:11.361579 [CA 4] Center 32 (2~63) winsize 62
4263 14:47:11.364746 [CA 5] Center 32 (2~63) winsize 62
4264 14:47:11.364814
4265 14:47:11.368246 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4266 14:47:11.368338
4267 14:47:11.371392 [CATrainingPosCal] consider 2 rank data
4268 14:47:11.374713 u2DelayCellTimex100 = 270/100 ps
4269 14:47:11.377968 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4270 14:47:11.381601 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4271 14:47:11.384753 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4272 14:47:11.388070 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4273 14:47:11.391612 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4274 14:47:11.397777 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4275 14:47:11.397852
4276 14:47:11.401115 CA PerBit enable=1, Macro0, CA PI delay=32
4277 14:47:11.401184
4278 14:47:11.404414 [CBTSetCACLKResult] CA Dly = 32
4279 14:47:11.404508 CS Dly: 4 (0~35)
4280 14:47:11.404570
4281 14:47:11.407854 ----->DramcWriteLeveling(PI) begin...
4282 14:47:11.407922 ==
4283 14:47:11.411315 Dram Type= 6, Freq= 0, CH_1, rank 0
4284 14:47:11.417567 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4285 14:47:11.417641 ==
4286 14:47:11.421102 Write leveling (Byte 0): 27 => 27
4287 14:47:11.421206 Write leveling (Byte 1): 27 => 27
4288 14:47:11.424217 DramcWriteLeveling(PI) end<-----
4289 14:47:11.424310
4290 14:47:11.427958 ==
4291 14:47:11.428056 Dram Type= 6, Freq= 0, CH_1, rank 0
4292 14:47:11.434121 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4293 14:47:11.434196 ==
4294 14:47:11.437468 [Gating] SW mode calibration
4295 14:47:11.444277 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4296 14:47:11.447435 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4297 14:47:11.454200 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4298 14:47:11.457627 0 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4299 14:47:11.460614 0 5 8 | B1->B0 | 2f2f 2727 | 1 0 | (1 0) (1 0)
4300 14:47:11.467238 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4301 14:47:11.470576 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4302 14:47:11.474234 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4303 14:47:11.480369 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4304 14:47:11.483817 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4305 14:47:11.487306 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4306 14:47:11.493873 0 6 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
4307 14:47:11.496974 0 6 8 | B1->B0 | 3535 4343 | 0 1 | (1 1) (0 0)
4308 14:47:11.500230 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4309 14:47:11.506932 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4310 14:47:11.510361 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4311 14:47:11.513549 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4312 14:47:11.520242 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4313 14:47:11.523402 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4314 14:47:11.526895 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4315 14:47:11.533505 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4316 14:47:11.536644 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4317 14:47:11.539933 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4318 14:47:11.546800 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4319 14:47:11.549889 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4320 14:47:11.553246 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4321 14:47:11.559889 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4322 14:47:11.563094 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4323 14:47:11.566899 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4324 14:47:11.573066 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4325 14:47:11.576278 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4326 14:47:11.579663 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4327 14:47:11.583056 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4328 14:47:11.589360 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4329 14:47:11.593277 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4330 14:47:11.596457 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4331 14:47:11.602980 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4332 14:47:11.605914 Total UI for P1: 0, mck2ui 16
4333 14:47:11.609374 best dqsien dly found for B0: ( 0, 9, 4)
4334 14:47:11.612646 Total UI for P1: 0, mck2ui 16
4335 14:47:11.616106 best dqsien dly found for B1: ( 0, 9, 6)
4336 14:47:11.619186 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4337 14:47:11.622417 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4338 14:47:11.622492
4339 14:47:11.626185 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4340 14:47:11.629237 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4341 14:47:11.632347 [Gating] SW calibration Done
4342 14:47:11.632440 ==
4343 14:47:11.635832 Dram Type= 6, Freq= 0, CH_1, rank 0
4344 14:47:11.639017 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4345 14:47:11.639084 ==
4346 14:47:11.642687 RX Vref Scan: 0
4347 14:47:11.642751
4348 14:47:11.645981 RX Vref 0 -> 0, step: 1
4349 14:47:11.646074
4350 14:47:11.646138 RX Delay -230 -> 252, step: 16
4351 14:47:11.652255 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4352 14:47:11.655878 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4353 14:47:11.658966 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4354 14:47:11.662357 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4355 14:47:11.668880 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4356 14:47:11.672099 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4357 14:47:11.675350 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4358 14:47:11.678821 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4359 14:47:11.681977 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4360 14:47:11.688644 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4361 14:47:11.692154 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4362 14:47:11.695788 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4363 14:47:11.698562 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4364 14:47:11.705554 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4365 14:47:11.708442 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4366 14:47:11.711781 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4367 14:47:11.711878 ==
4368 14:47:11.715288 Dram Type= 6, Freq= 0, CH_1, rank 0
4369 14:47:11.721819 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4370 14:47:11.721934 ==
4371 14:47:11.722032 DQS Delay:
4372 14:47:11.722123 DQS0 = 0, DQS1 = 0
4373 14:47:11.725169 DQM Delay:
4374 14:47:11.725266 DQM0 = 39, DQM1 = 31
4375 14:47:11.728195 DQ Delay:
4376 14:47:11.731594 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4377 14:47:11.734965 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4378 14:47:11.735055 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4379 14:47:11.742056 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =49
4380 14:47:11.742152
4381 14:47:11.742239
4382 14:47:11.742326 ==
4383 14:47:11.744796 Dram Type= 6, Freq= 0, CH_1, rank 0
4384 14:47:11.748062 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4385 14:47:11.748148 ==
4386 14:47:11.748206
4387 14:47:11.748262
4388 14:47:11.751295 TX Vref Scan disable
4389 14:47:11.751387 == TX Byte 0 ==
4390 14:47:11.758349 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4391 14:47:11.761220 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4392 14:47:11.761344 == TX Byte 1 ==
4393 14:47:11.767997 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4394 14:47:11.771234 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4395 14:47:11.771328 ==
4396 14:47:11.774524 Dram Type= 6, Freq= 0, CH_1, rank 0
4397 14:47:11.777860 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4398 14:47:11.777931 ==
4399 14:47:11.781376
4400 14:47:11.781470
4401 14:47:11.781556 TX Vref Scan disable
4402 14:47:11.784618 == TX Byte 0 ==
4403 14:47:11.787921 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4404 14:47:11.794519 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4405 14:47:11.794621 == TX Byte 1 ==
4406 14:47:11.797787 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4407 14:47:11.804653 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4408 14:47:11.804755
4409 14:47:11.804844 [DATLAT]
4410 14:47:11.804931 Freq=600, CH1 RK0
4411 14:47:11.805016
4412 14:47:11.807924 DATLAT Default: 0x9
4413 14:47:11.808016 0, 0xFFFF, sum = 0
4414 14:47:11.811114 1, 0xFFFF, sum = 0
4415 14:47:11.814418 2, 0xFFFF, sum = 0
4416 14:47:11.814486 3, 0xFFFF, sum = 0
4417 14:47:11.817504 4, 0xFFFF, sum = 0
4418 14:47:11.817599 5, 0xFFFF, sum = 0
4419 14:47:11.821134 6, 0xFFFF, sum = 0
4420 14:47:11.821214 7, 0x0, sum = 1
4421 14:47:11.821340 8, 0x0, sum = 2
4422 14:47:11.824824 9, 0x0, sum = 3
4423 14:47:11.824919 10, 0x0, sum = 4
4424 14:47:11.827813 best_step = 8
4425 14:47:11.827907
4426 14:47:11.827992 ==
4427 14:47:11.831165 Dram Type= 6, Freq= 0, CH_1, rank 0
4428 14:47:11.834206 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4429 14:47:11.834279 ==
4430 14:47:11.837613 RX Vref Scan: 1
4431 14:47:11.837681
4432 14:47:11.837740 RX Vref 0 -> 0, step: 1
4433 14:47:11.837796
4434 14:47:11.841497 RX Delay -195 -> 252, step: 8
4435 14:47:11.841565
4436 14:47:11.844303 Set Vref, RX VrefLevel [Byte0]: 52
4437 14:47:11.847575 [Byte1]: 49
4438 14:47:11.851971
4439 14:47:11.852064 Final RX Vref Byte 0 = 52 to rank0
4440 14:47:11.855178 Final RX Vref Byte 1 = 49 to rank0
4441 14:47:11.858462 Final RX Vref Byte 0 = 52 to rank1
4442 14:47:11.861739 Final RX Vref Byte 1 = 49 to rank1==
4443 14:47:11.864854 Dram Type= 6, Freq= 0, CH_1, rank 0
4444 14:47:11.871985 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4445 14:47:11.872086 ==
4446 14:47:11.872178 DQS Delay:
4447 14:47:11.872267 DQS0 = 0, DQS1 = 0
4448 14:47:11.874891 DQM Delay:
4449 14:47:11.874986 DQM0 = 38, DQM1 = 30
4450 14:47:11.878131 DQ Delay:
4451 14:47:11.881524 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4452 14:47:11.884959 DQ4 =36, DQ5 =52, DQ6 =44, DQ7 =36
4453 14:47:11.888243 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4454 14:47:11.891550 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4455 14:47:11.891638
4456 14:47:11.891705
4457 14:47:11.898178 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f6f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4458 14:47:11.901533 CH1 RK0: MR19=808, MR18=6F6F
4459 14:47:11.908364 CH1_RK0: MR19=0x808, MR18=0x6F6F, DQSOSC=389, MR23=63, INC=173, DEC=115
4460 14:47:11.908472
4461 14:47:11.911659 ----->DramcWriteLeveling(PI) begin...
4462 14:47:11.911734 ==
4463 14:47:11.914866 Dram Type= 6, Freq= 0, CH_1, rank 1
4464 14:47:11.918326 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4465 14:47:11.918422 ==
4466 14:47:11.921216 Write leveling (Byte 0): 28 => 28
4467 14:47:11.924751 Write leveling (Byte 1): 27 => 27
4468 14:47:11.927918 DramcWriteLeveling(PI) end<-----
4469 14:47:11.927988
4470 14:47:11.928048 ==
4471 14:47:11.931882 Dram Type= 6, Freq= 0, CH_1, rank 1
4472 14:47:11.934622 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4473 14:47:11.934694 ==
4474 14:47:11.937946 [Gating] SW mode calibration
4475 14:47:11.944575 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4476 14:47:11.951238 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4477 14:47:11.954289 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4478 14:47:11.961217 0 5 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
4479 14:47:11.964288 0 5 8 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (0 0)
4480 14:47:11.967542 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 14:47:11.974458 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 14:47:11.977769 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 14:47:11.981055 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 14:47:11.987584 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 14:47:11.990896 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 14:47:11.994494 0 6 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
4487 14:47:11.997685 0 6 8 | B1->B0 | 3636 4545 | 1 0 | (0 0) (0 0)
4488 14:47:12.004239 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 14:47:12.007663 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 14:47:12.010625 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 14:47:12.017485 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 14:47:12.020454 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 14:47:12.023812 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 14:47:12.030627 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4495 14:47:12.034162 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4496 14:47:12.037075 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 14:47:12.043698 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 14:47:12.047168 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 14:47:12.050487 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 14:47:12.056824 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 14:47:12.060544 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 14:47:12.063524 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 14:47:12.070201 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 14:47:12.073542 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 14:47:12.076665 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 14:47:12.083648 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 14:47:12.086867 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 14:47:12.090139 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 14:47:12.096629 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4510 14:47:12.099976 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4511 14:47:12.103111 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4512 14:47:12.106480 Total UI for P1: 0, mck2ui 16
4513 14:47:12.109893 best dqsien dly found for B0: ( 0, 9, 2)
4514 14:47:12.116383 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4515 14:47:12.119930 Total UI for P1: 0, mck2ui 16
4516 14:47:12.123231 best dqsien dly found for B1: ( 0, 9, 8)
4517 14:47:12.126377 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4518 14:47:12.129591 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4519 14:47:12.129662
4520 14:47:12.132967 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4521 14:47:12.136442 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4522 14:47:12.139800 [Gating] SW calibration Done
4523 14:47:12.139896 ==
4524 14:47:12.143188 Dram Type= 6, Freq= 0, CH_1, rank 1
4525 14:47:12.146411 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4526 14:47:12.146509 ==
4527 14:47:12.149790 RX Vref Scan: 0
4528 14:47:12.149857
4529 14:47:12.149919 RX Vref 0 -> 0, step: 1
4530 14:47:12.149977
4531 14:47:12.153282 RX Delay -230 -> 252, step: 16
4532 14:47:12.159469 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4533 14:47:12.162785 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4534 14:47:12.166751 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4535 14:47:12.169539 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4536 14:47:12.172866 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4537 14:47:12.179533 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4538 14:47:12.183507 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4539 14:47:12.186158 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4540 14:47:12.189378 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4541 14:47:12.195865 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4542 14:47:12.199284 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4543 14:47:12.202548 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4544 14:47:12.205855 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4545 14:47:12.212603 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4546 14:47:12.215754 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4547 14:47:12.219178 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4548 14:47:12.219276 ==
4549 14:47:12.222444 Dram Type= 6, Freq= 0, CH_1, rank 1
4550 14:47:12.226005 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4551 14:47:12.226092 ==
4552 14:47:12.229379 DQS Delay:
4553 14:47:12.229462 DQS0 = 0, DQS1 = 0
4554 14:47:12.232511 DQM Delay:
4555 14:47:12.232608 DQM0 = 39, DQM1 = 33
4556 14:47:12.232705 DQ Delay:
4557 14:47:12.235979 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4558 14:47:12.239145 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4559 14:47:12.242436 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4560 14:47:12.245771 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4561 14:47:12.245869
4562 14:47:12.245955
4563 14:47:12.249023 ==
4564 14:47:12.252263 Dram Type= 6, Freq= 0, CH_1, rank 1
4565 14:47:12.255798 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4566 14:47:12.255868 ==
4567 14:47:12.255942
4568 14:47:12.255999
4569 14:47:12.258844 TX Vref Scan disable
4570 14:47:12.258915 == TX Byte 0 ==
4571 14:47:12.265695 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4572 14:47:12.268975 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4573 14:47:12.269073 == TX Byte 1 ==
4574 14:47:12.275332 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4575 14:47:12.279371 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4576 14:47:12.279467 ==
4577 14:47:12.282250 Dram Type= 6, Freq= 0, CH_1, rank 1
4578 14:47:12.285466 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4579 14:47:12.285537 ==
4580 14:47:12.285597
4581 14:47:12.285666
4582 14:47:12.288661 TX Vref Scan disable
4583 14:47:12.292214 == TX Byte 0 ==
4584 14:47:12.295617 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4585 14:47:12.298680 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4586 14:47:12.301928 == TX Byte 1 ==
4587 14:47:12.305922 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4588 14:47:12.308963 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4589 14:47:12.309038
4590 14:47:12.311739 [DATLAT]
4591 14:47:12.311814 Freq=600, CH1 RK1
4592 14:47:12.311881
4593 14:47:12.315273 DATLAT Default: 0x8
4594 14:47:12.315342 0, 0xFFFF, sum = 0
4595 14:47:12.318382 1, 0xFFFF, sum = 0
4596 14:47:12.318452 2, 0xFFFF, sum = 0
4597 14:47:12.321850 3, 0xFFFF, sum = 0
4598 14:47:12.321921 4, 0xFFFF, sum = 0
4599 14:47:12.325446 5, 0xFFFF, sum = 0
4600 14:47:12.325531 6, 0xFFFF, sum = 0
4601 14:47:12.328780 7, 0x0, sum = 1
4602 14:47:12.328875 8, 0x0, sum = 2
4603 14:47:12.331743 9, 0x0, sum = 3
4604 14:47:12.331838 10, 0x0, sum = 4
4605 14:47:12.335367 best_step = 8
4606 14:47:12.335467
4607 14:47:12.335552 ==
4608 14:47:12.338521 Dram Type= 6, Freq= 0, CH_1, rank 1
4609 14:47:12.341850 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4610 14:47:12.341944 ==
4611 14:47:12.345070 RX Vref Scan: 0
4612 14:47:12.345162
4613 14:47:12.345247 RX Vref 0 -> 0, step: 1
4614 14:47:12.345376
4615 14:47:12.348257 RX Delay -195 -> 252, step: 8
4616 14:47:12.355429 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4617 14:47:12.358494 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4618 14:47:12.361570 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4619 14:47:12.364799 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4620 14:47:12.371620 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4621 14:47:12.374842 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4622 14:47:12.378197 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4623 14:47:12.381485 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4624 14:47:12.387966 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4625 14:47:12.391338 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4626 14:47:12.394714 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4627 14:47:12.398226 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4628 14:47:12.404575 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4629 14:47:12.407659 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4630 14:47:12.411146 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4631 14:47:12.414567 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4632 14:47:12.414640 ==
4633 14:47:12.417659 Dram Type= 6, Freq= 0, CH_1, rank 1
4634 14:47:12.424691 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4635 14:47:12.424769 ==
4636 14:47:12.424831 DQS Delay:
4637 14:47:12.427960 DQS0 = 0, DQS1 = 0
4638 14:47:12.428034 DQM Delay:
4639 14:47:12.428094 DQM0 = 37, DQM1 = 29
4640 14:47:12.430837 DQ Delay:
4641 14:47:12.434425 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4642 14:47:12.437616 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =32
4643 14:47:12.440940 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4644 14:47:12.444177 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4645 14:47:12.444259
4646 14:47:12.444322
4647 14:47:12.450975 [DQSOSCAuto] RK1, (LSB)MR18= 0x5454, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4648 14:47:12.454117 CH1 RK1: MR19=808, MR18=5454
4649 14:47:12.460517 CH1_RK1: MR19=0x808, MR18=0x5454, DQSOSC=393, MR23=63, INC=169, DEC=113
4650 14:47:12.463969 [RxdqsGatingPostProcess] freq 600
4651 14:47:12.470456 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4652 14:47:12.470557 Pre-setting of DQS Precalculation
4653 14:47:12.477030 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4654 14:47:12.483720 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4655 14:47:12.490505 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4656 14:47:12.490579
4657 14:47:12.490645
4658 14:47:12.493561 [Calibration Summary] 1200 Mbps
4659 14:47:12.496802 CH 0, Rank 0
4660 14:47:12.496872 SW Impedance : PASS
4661 14:47:12.500342 DUTY Scan : NO K
4662 14:47:12.500411 ZQ Calibration : PASS
4663 14:47:12.503911 Jitter Meter : NO K
4664 14:47:12.507015 CBT Training : PASS
4665 14:47:12.507084 Write leveling : PASS
4666 14:47:12.510585 RX DQS gating : PASS
4667 14:47:12.513581 RX DQ/DQS(RDDQC) : PASS
4668 14:47:12.513678 TX DQ/DQS : PASS
4669 14:47:12.516758 RX DATLAT : PASS
4670 14:47:12.520180 RX DQ/DQS(Engine): PASS
4671 14:47:12.520275 TX OE : NO K
4672 14:47:12.523687 All Pass.
4673 14:47:12.523781
4674 14:47:12.523867 CH 0, Rank 1
4675 14:47:12.526854 SW Impedance : PASS
4676 14:47:12.526929 DUTY Scan : NO K
4677 14:47:12.530308 ZQ Calibration : PASS
4678 14:47:12.533561 Jitter Meter : NO K
4679 14:47:12.533636 CBT Training : PASS
4680 14:47:12.536763 Write leveling : PASS
4681 14:47:12.539947 RX DQS gating : PASS
4682 14:47:12.540041 RX DQ/DQS(RDDQC) : PASS
4683 14:47:12.543329 TX DQ/DQS : PASS
4684 14:47:12.546699 RX DATLAT : PASS
4685 14:47:12.546767 RX DQ/DQS(Engine): PASS
4686 14:47:12.550222 TX OE : NO K
4687 14:47:12.550290 All Pass.
4688 14:47:12.550353
4689 14:47:12.553260 CH 1, Rank 0
4690 14:47:12.553358 SW Impedance : PASS
4691 14:47:12.556407 DUTY Scan : NO K
4692 14:47:12.559969 ZQ Calibration : PASS
4693 14:47:12.560069 Jitter Meter : NO K
4694 14:47:12.563122 CBT Training : PASS
4695 14:47:12.563219 Write leveling : PASS
4696 14:47:12.566286 RX DQS gating : PASS
4697 14:47:12.569674 RX DQ/DQS(RDDQC) : PASS
4698 14:47:12.569752 TX DQ/DQS : PASS
4699 14:47:12.572848 RX DATLAT : PASS
4700 14:47:12.576166 RX DQ/DQS(Engine): PASS
4701 14:47:12.576262 TX OE : NO K
4702 14:47:12.579453 All Pass.
4703 14:47:12.579546
4704 14:47:12.579632 CH 1, Rank 1
4705 14:47:12.582865 SW Impedance : PASS
4706 14:47:12.582965 DUTY Scan : NO K
4707 14:47:12.586077 ZQ Calibration : PASS
4708 14:47:12.589526 Jitter Meter : NO K
4709 14:47:12.589597 CBT Training : PASS
4710 14:47:12.592694 Write leveling : PASS
4711 14:47:12.596920 RX DQS gating : PASS
4712 14:47:12.596990 RX DQ/DQS(RDDQC) : PASS
4713 14:47:12.599469 TX DQ/DQS : PASS
4714 14:47:12.602710 RX DATLAT : PASS
4715 14:47:12.602814 RX DQ/DQS(Engine): PASS
4716 14:47:12.606388 TX OE : NO K
4717 14:47:12.606481 All Pass.
4718 14:47:12.606576
4719 14:47:12.609201 DramC Write-DBI off
4720 14:47:12.612713 PER_BANK_REFRESH: Hybrid Mode
4721 14:47:12.612814 TX_TRACKING: ON
4722 14:47:12.622512 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4723 14:47:12.625998 [FAST_K] Save calibration result to emmc
4724 14:47:12.629229 dramc_set_vcore_voltage set vcore to 662500
4725 14:47:12.632575 Read voltage for 933, 3
4726 14:47:12.632654 Vio18 = 0
4727 14:47:12.632717 Vcore = 662500
4728 14:47:12.635813 Vdram = 0
4729 14:47:12.635912 Vddq = 0
4730 14:47:12.635998 Vmddr = 0
4731 14:47:12.642514 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4732 14:47:12.645760 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4733 14:47:12.648896 MEM_TYPE=3, freq_sel=17
4734 14:47:12.652500 sv_algorithm_assistance_LP4_1600
4735 14:47:12.655938 ============ PULL DRAM RESETB DOWN ============
4736 14:47:12.659178 ========== PULL DRAM RESETB DOWN end =========
4737 14:47:12.665790 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4738 14:47:12.668900 ===================================
4739 14:47:12.672204 LPDDR4 DRAM CONFIGURATION
4740 14:47:12.672303 ===================================
4741 14:47:12.675758 EX_ROW_EN[0] = 0x0
4742 14:47:12.678935 EX_ROW_EN[1] = 0x0
4743 14:47:12.679005 LP4Y_EN = 0x0
4744 14:47:12.682202 WORK_FSP = 0x0
4745 14:47:12.682271 WL = 0x3
4746 14:47:12.685427 RL = 0x3
4747 14:47:12.685496 BL = 0x2
4748 14:47:12.688865 RPST = 0x0
4749 14:47:12.688934 RD_PRE = 0x0
4750 14:47:12.692342 WR_PRE = 0x1
4751 14:47:12.692413 WR_PST = 0x0
4752 14:47:12.695329 DBI_WR = 0x0
4753 14:47:12.695425 DBI_RD = 0x0
4754 14:47:12.698753 OTF = 0x1
4755 14:47:12.702609 ===================================
4756 14:47:12.705592 ===================================
4757 14:47:12.705663 ANA top config
4758 14:47:12.708851 ===================================
4759 14:47:12.711986 DLL_ASYNC_EN = 0
4760 14:47:12.715437 ALL_SLAVE_EN = 1
4761 14:47:12.719238 NEW_RANK_MODE = 1
4762 14:47:12.719309 DLL_IDLE_MODE = 1
4763 14:47:12.721836 LP45_APHY_COMB_EN = 1
4764 14:47:12.725347 TX_ODT_DIS = 1
4765 14:47:12.728802 NEW_8X_MODE = 1
4766 14:47:12.731820 ===================================
4767 14:47:12.735425 ===================================
4768 14:47:12.738447 data_rate = 1866
4769 14:47:12.738517 CKR = 1
4770 14:47:12.741800 DQ_P2S_RATIO = 8
4771 14:47:12.745262 ===================================
4772 14:47:12.748796 CA_P2S_RATIO = 8
4773 14:47:12.751873 DQ_CA_OPEN = 0
4774 14:47:12.754937 DQ_SEMI_OPEN = 0
4775 14:47:12.758287 CA_SEMI_OPEN = 0
4776 14:47:12.758389 CA_FULL_RATE = 0
4777 14:47:12.761618 DQ_CKDIV4_EN = 1
4778 14:47:12.765124 CA_CKDIV4_EN = 1
4779 14:47:12.768223 CA_PREDIV_EN = 0
4780 14:47:12.771448 PH8_DLY = 0
4781 14:47:12.774921 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4782 14:47:12.775021 DQ_AAMCK_DIV = 4
4783 14:47:12.778021 CA_AAMCK_DIV = 4
4784 14:47:12.781327 CA_ADMCK_DIV = 4
4785 14:47:12.784712 DQ_TRACK_CA_EN = 0
4786 14:47:12.787861 CA_PICK = 933
4787 14:47:12.791254 CA_MCKIO = 933
4788 14:47:12.794749 MCKIO_SEMI = 0
4789 14:47:12.797967 PLL_FREQ = 3732
4790 14:47:12.798050 DQ_UI_PI_RATIO = 32
4791 14:47:12.801145 CA_UI_PI_RATIO = 0
4792 14:47:12.804549 ===================================
4793 14:47:12.808050 ===================================
4794 14:47:12.811091 memory_type:LPDDR4
4795 14:47:12.814269 GP_NUM : 10
4796 14:47:12.814345 SRAM_EN : 1
4797 14:47:12.818008 MD32_EN : 0
4798 14:47:12.821015 ===================================
4799 14:47:12.824375 [ANA_INIT] >>>>>>>>>>>>>>
4800 14:47:12.824471 <<<<<< [CONFIGURE PHASE]: ANA_TX
4801 14:47:12.827635 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4802 14:47:12.830901 ===================================
4803 14:47:12.834198 data_rate = 1866,PCW = 0X8f00
4804 14:47:12.837813 ===================================
4805 14:47:12.840935 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4806 14:47:12.847726 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4807 14:47:12.854284 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4808 14:47:12.858320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4809 14:47:12.860946 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4810 14:47:12.864319 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4811 14:47:12.867459 [ANA_INIT] flow start
4812 14:47:12.867560 [ANA_INIT] PLL >>>>>>>>
4813 14:47:12.870632 [ANA_INIT] PLL <<<<<<<<
4814 14:47:12.874257 [ANA_INIT] MIDPI >>>>>>>>
4815 14:47:12.874329 [ANA_INIT] MIDPI <<<<<<<<
4816 14:47:12.877525 [ANA_INIT] DLL >>>>>>>>
4817 14:47:12.880672 [ANA_INIT] flow end
4818 14:47:12.883925 ============ LP4 DIFF to SE enter ============
4819 14:47:12.887252 ============ LP4 DIFF to SE exit ============
4820 14:47:12.890625 [ANA_INIT] <<<<<<<<<<<<<
4821 14:47:12.894000 [Flow] Enable top DCM control >>>>>
4822 14:47:12.897387 [Flow] Enable top DCM control <<<<<
4823 14:47:12.900306 Enable DLL master slave shuffle
4824 14:47:12.906925 ==============================================================
4825 14:47:12.907000 Gating Mode config
4826 14:47:12.913562 ==============================================================
4827 14:47:12.913634 Config description:
4828 14:47:12.923532 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4829 14:47:12.930102 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4830 14:47:12.936750 SELPH_MODE 0: By rank 1: By Phase
4831 14:47:12.940244 ==============================================================
4832 14:47:12.943311 GAT_TRACK_EN = 1
4833 14:47:12.946875 RX_GATING_MODE = 2
4834 14:47:12.949996 RX_GATING_TRACK_MODE = 2
4835 14:47:12.953276 SELPH_MODE = 1
4836 14:47:12.956883 PICG_EARLY_EN = 1
4837 14:47:12.959944 VALID_LAT_VALUE = 1
4838 14:47:12.963738 ==============================================================
4839 14:47:12.966716 Enter into Gating configuration >>>>
4840 14:47:12.969923 Exit from Gating configuration <<<<
4841 14:47:12.973863 Enter into DVFS_PRE_config >>>>>
4842 14:47:12.986738 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4843 14:47:12.989980 Exit from DVFS_PRE_config <<<<<
4844 14:47:12.993336 Enter into PICG configuration >>>>
4845 14:47:12.996399 Exit from PICG configuration <<<<
4846 14:47:12.996469 [RX_INPUT] configuration >>>>>
4847 14:47:12.999733 [RX_INPUT] configuration <<<<<
4848 14:47:13.006350 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4849 14:47:13.009588 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4850 14:47:13.016362 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4851 14:47:13.023139 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4852 14:47:13.029885 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4853 14:47:13.036085 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4854 14:47:13.039505 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4855 14:47:13.042742 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4856 14:47:13.049378 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4857 14:47:13.052707 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4858 14:47:13.056133 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4859 14:47:13.059431 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4860 14:47:13.062619 ===================================
4861 14:47:13.065950 LPDDR4 DRAM CONFIGURATION
4862 14:47:13.069389 ===================================
4863 14:47:13.072363 EX_ROW_EN[0] = 0x0
4864 14:47:13.072459 EX_ROW_EN[1] = 0x0
4865 14:47:13.076033 LP4Y_EN = 0x0
4866 14:47:13.076104 WORK_FSP = 0x0
4867 14:47:13.079329 WL = 0x3
4868 14:47:13.079400 RL = 0x3
4869 14:47:13.082598 BL = 0x2
4870 14:47:13.082673 RPST = 0x0
4871 14:47:13.085693 RD_PRE = 0x0
4872 14:47:13.089077 WR_PRE = 0x1
4873 14:47:13.089152 WR_PST = 0x0
4874 14:47:13.092743 DBI_WR = 0x0
4875 14:47:13.092812 DBI_RD = 0x0
4876 14:47:13.095542 OTF = 0x1
4877 14:47:13.099043 ===================================
4878 14:47:13.102375 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4879 14:47:13.105676 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4880 14:47:13.109078 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4881 14:47:13.112756 ===================================
4882 14:47:13.115563 LPDDR4 DRAM CONFIGURATION
4883 14:47:13.118887 ===================================
4884 14:47:13.122345 EX_ROW_EN[0] = 0x10
4885 14:47:13.122416 EX_ROW_EN[1] = 0x0
4886 14:47:13.125481 LP4Y_EN = 0x0
4887 14:47:13.125555 WORK_FSP = 0x0
4888 14:47:13.128852 WL = 0x3
4889 14:47:13.128948 RL = 0x3
4890 14:47:13.131964 BL = 0x2
4891 14:47:13.132036 RPST = 0x0
4892 14:47:13.135321 RD_PRE = 0x0
4893 14:47:13.135388 WR_PRE = 0x1
4894 14:47:13.139072 WR_PST = 0x0
4895 14:47:13.142106 DBI_WR = 0x0
4896 14:47:13.142177 DBI_RD = 0x0
4897 14:47:13.145136 OTF = 0x1
4898 14:47:13.148612 ===================================
4899 14:47:13.152204 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4900 14:47:13.157033 nWR fixed to 30
4901 14:47:13.160459 [ModeRegInit_LP4] CH0 RK0
4902 14:47:13.160548 [ModeRegInit_LP4] CH0 RK1
4903 14:47:13.163813 [ModeRegInit_LP4] CH1 RK0
4904 14:47:13.167257 [ModeRegInit_LP4] CH1 RK1
4905 14:47:13.167332 match AC timing 8
4906 14:47:13.173808 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4907 14:47:13.176947 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4908 14:47:13.180509 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4909 14:47:13.187754 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4910 14:47:13.190296 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4911 14:47:13.190383 ==
4912 14:47:13.193829 Dram Type= 6, Freq= 0, CH_0, rank 0
4913 14:47:13.197249 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4914 14:47:13.197367 ==
4915 14:47:13.203596 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4916 14:47:13.210275 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4917 14:47:13.213667 [CA 0] Center 38 (8~69) winsize 62
4918 14:47:13.217273 [CA 1] Center 38 (7~69) winsize 63
4919 14:47:13.220194 [CA 2] Center 36 (6~67) winsize 62
4920 14:47:13.224064 [CA 3] Center 36 (6~66) winsize 61
4921 14:47:13.227577 [CA 4] Center 34 (4~65) winsize 62
4922 14:47:13.230308 [CA 5] Center 34 (4~65) winsize 62
4923 14:47:13.230507
4924 14:47:13.233912 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4925 14:47:13.234152
4926 14:47:13.236931 [CATrainingPosCal] consider 1 rank data
4927 14:47:13.240016 u2DelayCellTimex100 = 270/100 ps
4928 14:47:13.243628 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4929 14:47:13.246939 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
4930 14:47:13.250322 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4931 14:47:13.253768 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4932 14:47:13.259980 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4933 14:47:13.263353 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4934 14:47:13.263766
4935 14:47:13.266671 CA PerBit enable=1, Macro0, CA PI delay=34
4936 14:47:13.267082
4937 14:47:13.269835 [CBTSetCACLKResult] CA Dly = 34
4938 14:47:13.270261 CS Dly: 7 (0~38)
4939 14:47:13.270584 ==
4940 14:47:13.273233 Dram Type= 6, Freq= 0, CH_0, rank 1
4941 14:47:13.279894 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4942 14:47:13.280308 ==
4943 14:47:13.283595 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4944 14:47:13.289906 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4945 14:47:13.293713 [CA 0] Center 38 (8~69) winsize 62
4946 14:47:13.296713 [CA 1] Center 38 (7~69) winsize 63
4947 14:47:13.299933 [CA 2] Center 36 (6~67) winsize 62
4948 14:47:13.303062 [CA 3] Center 35 (5~66) winsize 62
4949 14:47:13.306257 [CA 4] Center 34 (4~65) winsize 62
4950 14:47:13.309764 [CA 5] Center 34 (4~65) winsize 62
4951 14:47:13.310190
4952 14:47:13.312989 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4953 14:47:13.313433
4954 14:47:13.316463 [CATrainingPosCal] consider 2 rank data
4955 14:47:13.320161 u2DelayCellTimex100 = 270/100 ps
4956 14:47:13.323098 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4957 14:47:13.326538 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
4958 14:47:13.329858 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4959 14:47:13.336273 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4960 14:47:13.339819 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4961 14:47:13.343102 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4962 14:47:13.343518
4963 14:47:13.346259 CA PerBit enable=1, Macro0, CA PI delay=34
4964 14:47:13.346711
4965 14:47:13.349919 [CBTSetCACLKResult] CA Dly = 34
4966 14:47:13.350395 CS Dly: 7 (0~39)
4967 14:47:13.350895
4968 14:47:13.352918 ----->DramcWriteLeveling(PI) begin...
4969 14:47:13.353527 ==
4970 14:47:13.356474 Dram Type= 6, Freq= 0, CH_0, rank 0
4971 14:47:13.362811 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4972 14:47:13.363222 ==
4973 14:47:13.366207 Write leveling (Byte 0): 29 => 29
4974 14:47:13.369515 Write leveling (Byte 1): 29 => 29
4975 14:47:13.372647 DramcWriteLeveling(PI) end<-----
4976 14:47:13.373058
4977 14:47:13.373422 ==
4978 14:47:13.375904 Dram Type= 6, Freq= 0, CH_0, rank 0
4979 14:47:13.379248 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4980 14:47:13.379666 ==
4981 14:47:13.382878 [Gating] SW mode calibration
4982 14:47:13.389110 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4983 14:47:13.395744 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4984 14:47:13.398965 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4985 14:47:13.402358 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4986 14:47:13.408941 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4987 14:47:13.412549 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4988 14:47:13.415664 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4989 14:47:13.422467 0 10 20 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
4990 14:47:13.425370 0 10 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4991 14:47:13.428724 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4992 14:47:13.435450 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4993 14:47:13.438757 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4994 14:47:13.441816 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4995 14:47:13.448600 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4996 14:47:13.452080 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4997 14:47:13.455089 0 11 20 | B1->B0 | 2525 2d2d | 0 0 | (0 0) (0 0)
4998 14:47:13.461959 0 11 24 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4999 14:47:13.465073 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5000 14:47:13.468874 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5001 14:47:13.474929 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5002 14:47:13.478083 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5003 14:47:13.481618 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5004 14:47:13.487930 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5005 14:47:13.491447 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5006 14:47:13.494853 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5007 14:47:13.501397 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5008 14:47:13.504679 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5009 14:47:13.508123 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5010 14:47:13.514722 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5011 14:47:13.517791 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5012 14:47:13.520758 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5013 14:47:13.527527 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5014 14:47:13.530752 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5015 14:47:13.534217 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5016 14:47:13.537381 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5017 14:47:13.544287 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5018 14:47:13.547574 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5019 14:47:13.550530 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5020 14:47:13.557222 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5021 14:47:13.561113 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5022 14:47:13.564396 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5023 14:47:13.567581 Total UI for P1: 0, mck2ui 16
5024 14:47:13.570461 best dqsien dly found for B0: ( 0, 14, 22)
5025 14:47:13.573932 Total UI for P1: 0, mck2ui 16
5026 14:47:13.577209 best dqsien dly found for B1: ( 0, 14, 22)
5027 14:47:13.580590 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5028 14:47:13.586925 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5029 14:47:13.587005
5030 14:47:13.590431 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5031 14:47:13.593532 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5032 14:47:13.596968 [Gating] SW calibration Done
5033 14:47:13.597049 ==
5034 14:47:13.600299 Dram Type= 6, Freq= 0, CH_0, rank 0
5035 14:47:13.603915 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5036 14:47:13.603997 ==
5037 14:47:13.606966 RX Vref Scan: 0
5038 14:47:13.607047
5039 14:47:13.607110 RX Vref 0 -> 0, step: 1
5040 14:47:13.607170
5041 14:47:13.610010 RX Delay -80 -> 252, step: 8
5042 14:47:13.613468 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5043 14:47:13.616601 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5044 14:47:13.623375 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5045 14:47:13.626611 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5046 14:47:13.630053 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5047 14:47:13.633223 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5048 14:47:13.636950 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5049 14:47:13.643267 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5050 14:47:13.646526 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5051 14:47:13.649879 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5052 14:47:13.653176 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5053 14:47:13.656582 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5054 14:47:13.663013 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5055 14:47:13.666170 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5056 14:47:13.669326 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5057 14:47:13.673245 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5058 14:47:13.673415 ==
5059 14:47:13.676462 Dram Type= 6, Freq= 0, CH_0, rank 0
5060 14:47:13.679606 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5061 14:47:13.683075 ==
5062 14:47:13.683296 DQS Delay:
5063 14:47:13.683480 DQS0 = 0, DQS1 = 0
5064 14:47:13.686195 DQM Delay:
5065 14:47:13.686393 DQM0 = 96, DQM1 = 86
5066 14:47:13.689336 DQ Delay:
5067 14:47:13.689588 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5068 14:47:13.692689 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5069 14:47:13.696193 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5070 14:47:13.699662 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =91
5071 14:47:13.702826
5072 14:47:13.703245
5073 14:47:13.703569 ==
5074 14:47:13.706362 Dram Type= 6, Freq= 0, CH_0, rank 0
5075 14:47:13.709538 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5076 14:47:13.709959 ==
5077 14:47:13.710286
5078 14:47:13.710587
5079 14:47:13.712821 TX Vref Scan disable
5080 14:47:13.713239 == TX Byte 0 ==
5081 14:47:13.719672 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5082 14:47:13.722890 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5083 14:47:13.723370 == TX Byte 1 ==
5084 14:47:13.729533 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5085 14:47:13.732730 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5086 14:47:13.733235 ==
5087 14:47:13.736161 Dram Type= 6, Freq= 0, CH_0, rank 0
5088 14:47:13.739443 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5089 14:47:13.739915 ==
5090 14:47:13.740337
5091 14:47:13.740728
5092 14:47:13.742848 TX Vref Scan disable
5093 14:47:13.746033 == TX Byte 0 ==
5094 14:47:13.749131 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5095 14:47:13.752263 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5096 14:47:13.755683 == TX Byte 1 ==
5097 14:47:13.759370 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5098 14:47:13.762228 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5099 14:47:13.762834
5100 14:47:13.765709 [DATLAT]
5101 14:47:13.766196 Freq=933, CH0 RK0
5102 14:47:13.766797
5103 14:47:13.768687 DATLAT Default: 0xd
5104 14:47:13.769056 0, 0xFFFF, sum = 0
5105 14:47:13.772183 1, 0xFFFF, sum = 0
5106 14:47:13.772609 2, 0xFFFF, sum = 0
5107 14:47:13.775444 3, 0xFFFF, sum = 0
5108 14:47:13.775925 4, 0xFFFF, sum = 0
5109 14:47:13.778879 5, 0xFFFF, sum = 0
5110 14:47:13.779381 6, 0xFFFF, sum = 0
5111 14:47:13.782321 7, 0xFFFF, sum = 0
5112 14:47:13.785480 8, 0xFFFF, sum = 0
5113 14:47:13.786003 9, 0xFFFF, sum = 0
5114 14:47:13.788642 10, 0x0, sum = 1
5115 14:47:13.789149 11, 0x0, sum = 2
5116 14:47:13.789609 12, 0x0, sum = 3
5117 14:47:13.792283 13, 0x0, sum = 4
5118 14:47:13.792834 best_step = 11
5119 14:47:13.793400
5120 14:47:13.795512 ==
5121 14:47:13.796127 Dram Type= 6, Freq= 0, CH_0, rank 0
5122 14:47:13.801958 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5123 14:47:13.802429 ==
5124 14:47:13.802851 RX Vref Scan: 1
5125 14:47:13.803317
5126 14:47:13.805421 RX Vref 0 -> 0, step: 1
5127 14:47:13.805953
5128 14:47:13.808890 RX Delay -69 -> 252, step: 4
5129 14:47:13.809539
5130 14:47:13.811899 Set Vref, RX VrefLevel [Byte0]: 49
5131 14:47:13.814969 [Byte1]: 51
5132 14:47:13.815521
5133 14:47:13.818207 Final RX Vref Byte 0 = 49 to rank0
5134 14:47:13.821790 Final RX Vref Byte 1 = 51 to rank0
5135 14:47:13.825352 Final RX Vref Byte 0 = 49 to rank1
5136 14:47:13.828435 Final RX Vref Byte 1 = 51 to rank1==
5137 14:47:13.831757 Dram Type= 6, Freq= 0, CH_0, rank 0
5138 14:47:13.835190 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5139 14:47:13.838289 ==
5140 14:47:13.838759 DQS Delay:
5141 14:47:13.839116 DQS0 = 0, DQS1 = 0
5142 14:47:13.841552 DQM Delay:
5143 14:47:13.841926 DQM0 = 96, DQM1 = 87
5144 14:47:13.844695 DQ Delay:
5145 14:47:13.848338 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =92
5146 14:47:13.851345 DQ4 =100, DQ5 =86, DQ6 =104, DQ7 =102
5147 14:47:13.854953 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =80
5148 14:47:13.858048 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =96
5149 14:47:13.858643
5150 14:47:13.859118
5151 14:47:13.864486 [DQSOSCAuto] RK0, (LSB)MR18= 0x2424, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5152 14:47:13.868232 CH0 RK0: MR19=505, MR18=2424
5153 14:47:13.874481 CH0_RK0: MR19=0x505, MR18=0x2424, DQSOSC=410, MR23=63, INC=64, DEC=42
5154 14:47:13.874972
5155 14:47:13.877920 ----->DramcWriteLeveling(PI) begin...
5156 14:47:13.878403 ==
5157 14:47:13.881496 Dram Type= 6, Freq= 0, CH_0, rank 1
5158 14:47:13.884605 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5159 14:47:13.885096 ==
5160 14:47:13.887829 Write leveling (Byte 0): 26 => 26
5161 14:47:13.890992 Write leveling (Byte 1): 25 => 25
5162 14:47:13.894307 DramcWriteLeveling(PI) end<-----
5163 14:47:13.894774
5164 14:47:13.895167 ==
5165 14:47:13.897826 Dram Type= 6, Freq= 0, CH_0, rank 1
5166 14:47:13.901107 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5167 14:47:13.901787 ==
5168 14:47:13.904557 [Gating] SW mode calibration
5169 14:47:13.910937 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5170 14:47:13.917416 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5171 14:47:13.920898 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5172 14:47:13.927448 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5173 14:47:13.930820 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 14:47:13.933985 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5175 14:47:13.940673 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5176 14:47:13.943967 0 10 20 | B1->B0 | 3333 3030 | 0 1 | (0 0) (1 1)
5177 14:47:13.947477 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5178 14:47:13.953777 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 14:47:13.956678 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 14:47:13.960081 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 14:47:13.966849 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 14:47:13.970393 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 14:47:13.973223 0 11 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5184 14:47:13.980022 0 11 20 | B1->B0 | 2c2c 3636 | 1 0 | (0 0) (0 0)
5185 14:47:13.983429 0 11 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5186 14:47:13.986938 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 14:47:13.993310 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 14:47:13.996425 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 14:47:13.999966 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 14:47:14.006538 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 14:47:14.009785 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5192 14:47:14.012893 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5193 14:47:14.019641 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5194 14:47:14.022991 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 14:47:14.026076 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 14:47:14.032992 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 14:47:14.036102 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 14:47:14.039724 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 14:47:14.046104 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 14:47:14.049195 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 14:47:14.052759 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 14:47:14.059133 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 14:47:14.062562 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 14:47:14.065637 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 14:47:14.069042 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 14:47:14.075921 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 14:47:14.078821 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 14:47:14.085709 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 14:47:14.089008 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5210 14:47:14.092251 Total UI for P1: 0, mck2ui 16
5211 14:47:14.095563 best dqsien dly found for B0: ( 0, 14, 22)
5212 14:47:14.099372 Total UI for P1: 0, mck2ui 16
5213 14:47:14.101977 best dqsien dly found for B1: ( 0, 14, 22)
5214 14:47:14.105357 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5215 14:47:14.108802 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5216 14:47:14.108872
5217 14:47:14.111873 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5218 14:47:14.115375 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5219 14:47:14.118705 [Gating] SW calibration Done
5220 14:47:14.118783 ==
5221 14:47:14.121978 Dram Type= 6, Freq= 0, CH_0, rank 1
5222 14:47:14.125368 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5223 14:47:14.125440 ==
5224 14:47:14.128345 RX Vref Scan: 0
5225 14:47:14.128418
5226 14:47:14.131589 RX Vref 0 -> 0, step: 1
5227 14:47:14.131663
5228 14:47:14.131723 RX Delay -80 -> 252, step: 8
5229 14:47:14.138661 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5230 14:47:14.142089 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5231 14:47:14.145183 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5232 14:47:14.148585 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5233 14:47:14.152061 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5234 14:47:14.155009 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5235 14:47:14.161804 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5236 14:47:14.165151 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5237 14:47:14.168348 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5238 14:47:14.171712 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5239 14:47:14.174715 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5240 14:47:14.181363 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5241 14:47:14.184994 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5242 14:47:14.187877 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5243 14:47:14.191636 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5244 14:47:14.194723 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5245 14:47:14.197971 ==
5246 14:47:14.201394 Dram Type= 6, Freq= 0, CH_0, rank 1
5247 14:47:14.204843 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5248 14:47:14.204914 ==
5249 14:47:14.204977 DQS Delay:
5250 14:47:14.207723 DQS0 = 0, DQS1 = 0
5251 14:47:14.207795 DQM Delay:
5252 14:47:14.211013 DQM0 = 96, DQM1 = 84
5253 14:47:14.211085 DQ Delay:
5254 14:47:14.214513 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =87
5255 14:47:14.218102 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5256 14:47:14.220880 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79
5257 14:47:14.224664 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5258 14:47:14.224734
5259 14:47:14.224792
5260 14:47:14.224848 ==
5261 14:47:14.227855 Dram Type= 6, Freq= 0, CH_0, rank 1
5262 14:47:14.231169 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5263 14:47:14.231241 ==
5264 14:47:14.231302
5265 14:47:14.231360
5266 14:47:14.234354 TX Vref Scan disable
5267 14:47:14.237591 == TX Byte 0 ==
5268 14:47:14.240750 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5269 14:47:14.244364 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5270 14:47:14.247636 == TX Byte 1 ==
5271 14:47:14.250971 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5272 14:47:14.254237 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5273 14:47:14.254306 ==
5274 14:47:14.257144 Dram Type= 6, Freq= 0, CH_0, rank 1
5275 14:47:14.263867 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5276 14:47:14.263949 ==
5277 14:47:14.264012
5278 14:47:14.264071
5279 14:47:14.264127 TX Vref Scan disable
5280 14:47:14.268362 == TX Byte 0 ==
5281 14:47:14.271572 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5282 14:47:14.278424 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5283 14:47:14.278499 == TX Byte 1 ==
5284 14:47:14.281292 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5285 14:47:14.288224 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5286 14:47:14.288313
5287 14:47:14.288376 [DATLAT]
5288 14:47:14.288435 Freq=933, CH0 RK1
5289 14:47:14.288511
5290 14:47:14.291159 DATLAT Default: 0xb
5291 14:47:14.294600 0, 0xFFFF, sum = 0
5292 14:47:14.294694 1, 0xFFFF, sum = 0
5293 14:47:14.297780 2, 0xFFFF, sum = 0
5294 14:47:14.297859 3, 0xFFFF, sum = 0
5295 14:47:14.301590 4, 0xFFFF, sum = 0
5296 14:47:14.301660 5, 0xFFFF, sum = 0
5297 14:47:14.304232 6, 0xFFFF, sum = 0
5298 14:47:14.304303 7, 0xFFFF, sum = 0
5299 14:47:14.307780 8, 0xFFFF, sum = 0
5300 14:47:14.307853 9, 0xFFFF, sum = 0
5301 14:47:14.311114 10, 0x0, sum = 1
5302 14:47:14.311184 11, 0x0, sum = 2
5303 14:47:14.314361 12, 0x0, sum = 3
5304 14:47:14.314482 13, 0x0, sum = 4
5305 14:47:14.314567 best_step = 11
5306 14:47:14.317528
5307 14:47:14.317635 ==
5308 14:47:14.321145 Dram Type= 6, Freq= 0, CH_0, rank 1
5309 14:47:14.324661 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5310 14:47:14.324744 ==
5311 14:47:14.324827 RX Vref Scan: 0
5312 14:47:14.324905
5313 14:47:14.327757 RX Vref 0 -> 0, step: 1
5314 14:47:14.327839
5315 14:47:14.330706 RX Delay -69 -> 252, step: 4
5316 14:47:14.337632 iDelay=203, Bit 0, Center 94 (3 ~ 186) 184
5317 14:47:14.340687 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5318 14:47:14.344445 iDelay=203, Bit 2, Center 96 (3 ~ 190) 188
5319 14:47:14.347476 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5320 14:47:14.350783 iDelay=203, Bit 4, Center 102 (11 ~ 194) 184
5321 14:47:14.354307 iDelay=203, Bit 5, Center 88 (-5 ~ 182) 188
5322 14:47:14.360459 iDelay=203, Bit 6, Center 106 (15 ~ 198) 184
5323 14:47:14.363886 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188
5324 14:47:14.367101 iDelay=203, Bit 8, Center 76 (-13 ~ 166) 180
5325 14:47:14.370646 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5326 14:47:14.373974 iDelay=203, Bit 10, Center 86 (-5 ~ 178) 184
5327 14:47:14.380687 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5328 14:47:14.383744 iDelay=203, Bit 12, Center 92 (3 ~ 182) 180
5329 14:47:14.387206 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5330 14:47:14.390197 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5331 14:47:14.393542 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5332 14:47:14.393623 ==
5333 14:47:14.397102 Dram Type= 6, Freq= 0, CH_0, rank 1
5334 14:47:14.403832 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5335 14:47:14.403913 ==
5336 14:47:14.403975 DQS Delay:
5337 14:47:14.406805 DQS0 = 0, DQS1 = 0
5338 14:47:14.406885 DQM Delay:
5339 14:47:14.406947 DQM0 = 98, DQM1 = 86
5340 14:47:14.410120 DQ Delay:
5341 14:47:14.413341 DQ0 =94, DQ1 =98, DQ2 =96, DQ3 =92
5342 14:47:14.417120 DQ4 =102, DQ5 =88, DQ6 =106, DQ7 =108
5343 14:47:14.420205 DQ8 =76, DQ9 =72, DQ10 =86, DQ11 =78
5344 14:47:14.423336 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =94
5345 14:47:14.423416
5346 14:47:14.423478
5347 14:47:14.430159 [DQSOSCAuto] RK1, (LSB)MR18= 0x2929, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5348 14:47:14.433398 CH0 RK1: MR19=505, MR18=2929
5349 14:47:14.440013 CH0_RK1: MR19=0x505, MR18=0x2929, DQSOSC=408, MR23=63, INC=65, DEC=43
5350 14:47:14.443266 [RxdqsGatingPostProcess] freq 933
5351 14:47:14.446600 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5352 14:47:14.449692 Pre-setting of DQS Precalculation
5353 14:47:14.456362 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5354 14:47:14.456442 ==
5355 14:47:14.459579 Dram Type= 6, Freq= 0, CH_1, rank 0
5356 14:47:14.463050 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5357 14:47:14.463130 ==
5358 14:47:14.469703 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5359 14:47:14.476163 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5360 14:47:14.479321 [CA 0] Center 37 (7~68) winsize 62
5361 14:47:14.483097 [CA 1] Center 37 (6~68) winsize 63
5362 14:47:14.486166 [CA 2] Center 35 (5~65) winsize 61
5363 14:47:14.489424 [CA 3] Center 34 (4~65) winsize 62
5364 14:47:14.492694 [CA 4] Center 33 (2~64) winsize 63
5365 14:47:14.496144 [CA 5] Center 33 (2~64) winsize 63
5366 14:47:14.496223
5367 14:47:14.499303 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5368 14:47:14.499383
5369 14:47:14.502616 [CATrainingPosCal] consider 1 rank data
5370 14:47:14.505911 u2DelayCellTimex100 = 270/100 ps
5371 14:47:14.509205 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5372 14:47:14.512562 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5373 14:47:14.515880 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5374 14:47:14.519463 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5375 14:47:14.522575 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5376 14:47:14.525973 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5377 14:47:14.529395
5378 14:47:14.532571 CA PerBit enable=1, Macro0, CA PI delay=33
5379 14:47:14.532650
5380 14:47:14.535896 [CBTSetCACLKResult] CA Dly = 33
5381 14:47:14.535974 CS Dly: 5 (0~36)
5382 14:47:14.536037 ==
5383 14:47:14.539039 Dram Type= 6, Freq= 0, CH_1, rank 1
5384 14:47:14.542489 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5385 14:47:14.542572 ==
5386 14:47:14.548865 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5387 14:47:14.555474 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5388 14:47:14.558880 [CA 0] Center 37 (7~68) winsize 62
5389 14:47:14.562337 [CA 1] Center 37 (6~68) winsize 63
5390 14:47:14.565456 [CA 2] Center 34 (4~65) winsize 62
5391 14:47:14.568936 [CA 3] Center 34 (4~64) winsize 61
5392 14:47:14.572292 [CA 4] Center 33 (2~64) winsize 63
5393 14:47:14.575777 [CA 5] Center 33 (2~64) winsize 63
5394 14:47:14.575856
5395 14:47:14.578942 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5396 14:47:14.579021
5397 14:47:14.582103 [CATrainingPosCal] consider 2 rank data
5398 14:47:14.585850 u2DelayCellTimex100 = 270/100 ps
5399 14:47:14.589120 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5400 14:47:14.592366 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5401 14:47:14.595195 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5402 14:47:14.598992 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5403 14:47:14.605199 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5404 14:47:14.608491 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5405 14:47:14.608570
5406 14:47:14.612014 CA PerBit enable=1, Macro0, CA PI delay=33
5407 14:47:14.612093
5408 14:47:14.615300 [CBTSetCACLKResult] CA Dly = 33
5409 14:47:14.615381 CS Dly: 5 (0~37)
5410 14:47:14.615451
5411 14:47:14.618364 ----->DramcWriteLeveling(PI) begin...
5412 14:47:14.618445 ==
5413 14:47:14.622179 Dram Type= 6, Freq= 0, CH_1, rank 0
5414 14:47:14.628290 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5415 14:47:14.628370 ==
5416 14:47:14.631793 Write leveling (Byte 0): 24 => 24
5417 14:47:14.635292 Write leveling (Byte 1): 24 => 24
5418 14:47:14.635371 DramcWriteLeveling(PI) end<-----
5419 14:47:14.635433
5420 14:47:14.638497 ==
5421 14:47:14.641626 Dram Type= 6, Freq= 0, CH_1, rank 0
5422 14:47:14.645112 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5423 14:47:14.645192 ==
5424 14:47:14.648480 [Gating] SW mode calibration
5425 14:47:14.655029 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5426 14:47:14.658063 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5427 14:47:14.664590 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5428 14:47:14.668099 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5429 14:47:14.671326 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5430 14:47:14.677825 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5431 14:47:14.681418 0 10 16 | B1->B0 | 3434 3131 | 1 0 | (1 0) (1 0)
5432 14:47:14.684458 0 10 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
5433 14:47:14.691322 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
5434 14:47:14.694621 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5435 14:47:14.698130 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5436 14:47:14.704526 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5437 14:47:14.707964 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5438 14:47:14.710974 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5439 14:47:14.717652 0 11 16 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
5440 14:47:14.721317 0 11 20 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
5441 14:47:14.724364 0 11 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5442 14:47:14.731220 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5443 14:47:14.734173 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5444 14:47:14.737468 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5445 14:47:14.744095 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5446 14:47:14.747428 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5447 14:47:14.750614 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5448 14:47:14.757642 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5449 14:47:14.760647 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 14:47:14.764070 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 14:47:14.770537 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 14:47:14.773886 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5453 14:47:14.777072 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5454 14:47:14.783833 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5455 14:47:14.786997 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5456 14:47:14.790233 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5457 14:47:14.796817 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5458 14:47:14.800062 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5459 14:47:14.803417 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5460 14:47:14.810194 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5461 14:47:14.813456 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5462 14:47:14.816845 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5463 14:47:14.823422 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5464 14:47:14.826502 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5465 14:47:14.830439 Total UI for P1: 0, mck2ui 16
5466 14:47:14.833452 best dqsien dly found for B0: ( 0, 14, 18)
5467 14:47:14.836611 Total UI for P1: 0, mck2ui 16
5468 14:47:14.840328 best dqsien dly found for B1: ( 0, 14, 18)
5469 14:47:14.843299 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5470 14:47:14.846448 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5471 14:47:14.846529
5472 14:47:14.849914 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5473 14:47:14.853264 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5474 14:47:14.856503 [Gating] SW calibration Done
5475 14:47:14.856585 ==
5476 14:47:14.859901 Dram Type= 6, Freq= 0, CH_1, rank 0
5477 14:47:14.863189 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5478 14:47:14.866373 ==
5479 14:47:14.866455 RX Vref Scan: 0
5480 14:47:14.866538
5481 14:47:14.869791 RX Vref 0 -> 0, step: 1
5482 14:47:14.869874
5483 14:47:14.873031 RX Delay -80 -> 252, step: 8
5484 14:47:14.876257 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5485 14:47:14.879673 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5486 14:47:14.883364 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5487 14:47:14.886388 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5488 14:47:14.889897 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5489 14:47:14.896515 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5490 14:47:14.899441 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5491 14:47:14.902837 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5492 14:47:14.906305 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5493 14:47:14.909411 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5494 14:47:14.916152 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5495 14:47:14.919385 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5496 14:47:14.922839 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5497 14:47:14.925916 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5498 14:47:14.929303 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5499 14:47:14.936039 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5500 14:47:14.936119 ==
5501 14:47:14.939290 Dram Type= 6, Freq= 0, CH_1, rank 0
5502 14:47:14.942687 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5503 14:47:14.942766 ==
5504 14:47:14.942829 DQS Delay:
5505 14:47:14.945732 DQS0 = 0, DQS1 = 0
5506 14:47:14.945811 DQM Delay:
5507 14:47:14.948983 DQM0 = 95, DQM1 = 87
5508 14:47:14.949062 DQ Delay:
5509 14:47:14.952525 DQ0 =103, DQ1 =87, DQ2 =87, DQ3 =91
5510 14:47:14.955763 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91
5511 14:47:14.958921 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =79
5512 14:47:14.962218 DQ12 =91, DQ13 =103, DQ14 =91, DQ15 =99
5513 14:47:14.962298
5514 14:47:14.962360
5515 14:47:14.962417 ==
5516 14:47:14.965538 Dram Type= 6, Freq= 0, CH_1, rank 0
5517 14:47:14.968950 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5518 14:47:14.972873 ==
5519 14:47:14.972952
5520 14:47:14.973014
5521 14:47:14.973072 TX Vref Scan disable
5522 14:47:14.975553 == TX Byte 0 ==
5523 14:47:14.978758 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5524 14:47:14.982276 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5525 14:47:14.985555 == TX Byte 1 ==
5526 14:47:14.988775 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5527 14:47:14.992088 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5528 14:47:14.995618 ==
5529 14:47:14.998566 Dram Type= 6, Freq= 0, CH_1, rank 0
5530 14:47:15.001965 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5531 14:47:15.002045 ==
5532 14:47:15.002107
5533 14:47:15.002163
5534 14:47:15.005489 TX Vref Scan disable
5535 14:47:15.005568 == TX Byte 0 ==
5536 14:47:15.011817 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5537 14:47:15.015347 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5538 14:47:15.015426 == TX Byte 1 ==
5539 14:47:15.021864 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5540 14:47:15.025046 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5541 14:47:15.025126
5542 14:47:15.025188 [DATLAT]
5543 14:47:15.028277 Freq=933, CH1 RK0
5544 14:47:15.028356
5545 14:47:15.028418 DATLAT Default: 0xd
5546 14:47:15.031702 0, 0xFFFF, sum = 0
5547 14:47:15.031824 1, 0xFFFF, sum = 0
5548 14:47:15.035118 2, 0xFFFF, sum = 0
5549 14:47:15.035198 3, 0xFFFF, sum = 0
5550 14:47:15.038661 4, 0xFFFF, sum = 0
5551 14:47:15.041466 5, 0xFFFF, sum = 0
5552 14:47:15.041547 6, 0xFFFF, sum = 0
5553 14:47:15.044777 7, 0xFFFF, sum = 0
5554 14:47:15.044857 8, 0xFFFF, sum = 0
5555 14:47:15.048206 9, 0xFFFF, sum = 0
5556 14:47:15.048286 10, 0x0, sum = 1
5557 14:47:15.051582 11, 0x0, sum = 2
5558 14:47:15.051679 12, 0x0, sum = 3
5559 14:47:15.051781 13, 0x0, sum = 4
5560 14:47:15.054741 best_step = 11
5561 14:47:15.054820
5562 14:47:15.054882 ==
5563 14:47:15.057978 Dram Type= 6, Freq= 0, CH_1, rank 0
5564 14:47:15.061468 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5565 14:47:15.061548 ==
5566 14:47:15.064633 RX Vref Scan: 1
5567 14:47:15.064712
5568 14:47:15.067918 RX Vref 0 -> 0, step: 1
5569 14:47:15.067997
5570 14:47:15.068089 RX Delay -69 -> 252, step: 4
5571 14:47:15.068148
5572 14:47:15.071142 Set Vref, RX VrefLevel [Byte0]: 52
5573 14:47:15.074642 [Byte1]: 49
5574 14:47:15.079337
5575 14:47:15.079417 Final RX Vref Byte 0 = 52 to rank0
5576 14:47:15.082407 Final RX Vref Byte 1 = 49 to rank0
5577 14:47:15.086327 Final RX Vref Byte 0 = 52 to rank1
5578 14:47:15.089484 Final RX Vref Byte 1 = 49 to rank1==
5579 14:47:15.092319 Dram Type= 6, Freq= 0, CH_1, rank 0
5580 14:47:15.099099 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5581 14:47:15.099179 ==
5582 14:47:15.099242 DQS Delay:
5583 14:47:15.102388 DQS0 = 0, DQS1 = 0
5584 14:47:15.102467 DQM Delay:
5585 14:47:15.102530 DQM0 = 94, DQM1 = 88
5586 14:47:15.105602 DQ Delay:
5587 14:47:15.108967 DQ0 =98, DQ1 =88, DQ2 =86, DQ3 =90
5588 14:47:15.112245 DQ4 =94, DQ5 =106, DQ6 =102, DQ7 =92
5589 14:47:15.115547 DQ8 =70, DQ9 =76, DQ10 =90, DQ11 =80
5590 14:47:15.118702 DQ12 =96, DQ13 =100, DQ14 =98, DQ15 =98
5591 14:47:15.118782
5592 14:47:15.118844
5593 14:47:15.125285 [DQSOSCAuto] RK0, (LSB)MR18= 0x3131, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5594 14:47:15.128738 CH1 RK0: MR19=505, MR18=3131
5595 14:47:15.135402 CH1_RK0: MR19=0x505, MR18=0x3131, DQSOSC=406, MR23=63, INC=65, DEC=43
5596 14:47:15.135482
5597 14:47:15.138831 ----->DramcWriteLeveling(PI) begin...
5598 14:47:15.138912 ==
5599 14:47:15.142091 Dram Type= 6, Freq= 0, CH_1, rank 1
5600 14:47:15.145178 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5601 14:47:15.145283 ==
5602 14:47:15.148603 Write leveling (Byte 0): 26 => 26
5603 14:47:15.151750 Write leveling (Byte 1): 25 => 25
5604 14:47:15.155212 DramcWriteLeveling(PI) end<-----
5605 14:47:15.155291
5606 14:47:15.155352 ==
5607 14:47:15.158402 Dram Type= 6, Freq= 0, CH_1, rank 1
5608 14:47:15.162008 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5609 14:47:15.165177 ==
5610 14:47:15.165301 [Gating] SW mode calibration
5611 14:47:15.175433 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5612 14:47:15.178196 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5613 14:47:15.181730 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 14:47:15.188276 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 14:47:15.191677 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 14:47:15.195079 0 10 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5617 14:47:15.201552 0 10 16 | B1->B0 | 3434 2323 | 0 0 | (0 1) (1 0)
5618 14:47:15.205160 0 10 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5619 14:47:15.208069 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 14:47:15.214688 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 14:47:15.218196 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 14:47:15.221806 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 14:47:15.227842 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 14:47:15.231121 0 11 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5625 14:47:15.234392 0 11 16 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
5626 14:47:15.241012 0 11 20 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
5627 14:47:15.244395 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 14:47:15.247665 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 14:47:15.254685 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 14:47:15.257804 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 14:47:15.260865 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 14:47:15.267760 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 14:47:15.270996 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5634 14:47:15.274033 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5635 14:47:15.280760 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 14:47:15.284050 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 14:47:15.287508 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 14:47:15.293771 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 14:47:15.297166 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 14:47:15.300360 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 14:47:15.306845 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 14:47:15.310416 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 14:47:15.313757 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 14:47:15.320067 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 14:47:15.323468 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 14:47:15.326734 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 14:47:15.333383 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 14:47:15.336807 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 14:47:15.340304 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5650 14:47:15.346910 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 14:47:15.346992 Total UI for P1: 0, mck2ui 16
5652 14:47:15.353182 best dqsien dly found for B0: ( 0, 14, 16)
5653 14:47:15.353295 Total UI for P1: 0, mck2ui 16
5654 14:47:15.360217 best dqsien dly found for B1: ( 0, 14, 16)
5655 14:47:15.363064 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5656 14:47:15.366481 best DQS1 dly(MCK, UI, PI) = (0, 14, 16)
5657 14:47:15.366564
5658 14:47:15.369788 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5659 14:47:15.373083 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 16)
5660 14:47:15.376463 [Gating] SW calibration Done
5661 14:47:15.376545 ==
5662 14:47:15.379782 Dram Type= 6, Freq= 0, CH_1, rank 1
5663 14:47:15.383074 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5664 14:47:15.383157 ==
5665 14:47:15.386312 RX Vref Scan: 0
5666 14:47:15.386393
5667 14:47:15.386476 RX Vref 0 -> 0, step: 1
5668 14:47:15.389491
5669 14:47:15.389573 RX Delay -80 -> 252, step: 8
5670 14:47:15.396269 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5671 14:47:15.399624 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5672 14:47:15.402849 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5673 14:47:15.406250 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5674 14:47:15.410162 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5675 14:47:15.412900 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5676 14:47:15.419189 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5677 14:47:15.422611 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5678 14:47:15.425810 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5679 14:47:15.429393 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5680 14:47:15.432509 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5681 14:47:15.439177 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5682 14:47:15.442699 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5683 14:47:15.445719 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5684 14:47:15.448961 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5685 14:47:15.452435 iDelay=208, Bit 15, Center 91 (0 ~ 183) 184
5686 14:47:15.452518 ==
5687 14:47:15.455551 Dram Type= 6, Freq= 0, CH_1, rank 1
5688 14:47:15.462431 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5689 14:47:15.462513 ==
5690 14:47:15.462596 DQS Delay:
5691 14:47:15.465576 DQS0 = 0, DQS1 = 0
5692 14:47:15.465693 DQM Delay:
5693 14:47:15.465770 DQM0 = 95, DQM1 = 87
5694 14:47:15.468721 DQ Delay:
5695 14:47:15.472314 DQ0 =99, DQ1 =87, DQ2 =87, DQ3 =91
5696 14:47:15.475263 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5697 14:47:15.478609 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5698 14:47:15.481929 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =91
5699 14:47:15.482011
5700 14:47:15.482093
5701 14:47:15.482171 ==
5702 14:47:15.485309 Dram Type= 6, Freq= 0, CH_1, rank 1
5703 14:47:15.488699 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5704 14:47:15.488783 ==
5705 14:47:15.488865
5706 14:47:15.488942
5707 14:47:15.492229 TX Vref Scan disable
5708 14:47:15.495270 == TX Byte 0 ==
5709 14:47:15.498653 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5710 14:47:15.501836 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5711 14:47:15.505227 == TX Byte 1 ==
5712 14:47:15.508503 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5713 14:47:15.511798 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5714 14:47:15.511881 ==
5715 14:47:15.515023 Dram Type= 6, Freq= 0, CH_1, rank 1
5716 14:47:15.518250 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5717 14:47:15.521754 ==
5718 14:47:15.521836
5719 14:47:15.521918
5720 14:47:15.521997 TX Vref Scan disable
5721 14:47:15.524928 == TX Byte 0 ==
5722 14:47:15.528467 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5723 14:47:15.534906 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5724 14:47:15.534988 == TX Byte 1 ==
5725 14:47:15.538440 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5726 14:47:15.544875 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5727 14:47:15.544958
5728 14:47:15.545040 [DATLAT]
5729 14:47:15.545117 Freq=933, CH1 RK1
5730 14:47:15.545213
5731 14:47:15.548132 DATLAT Default: 0xb
5732 14:47:15.548214 0, 0xFFFF, sum = 0
5733 14:47:15.551386 1, 0xFFFF, sum = 0
5734 14:47:15.554867 2, 0xFFFF, sum = 0
5735 14:47:15.554950 3, 0xFFFF, sum = 0
5736 14:47:15.558046 4, 0xFFFF, sum = 0
5737 14:47:15.558129 5, 0xFFFF, sum = 0
5738 14:47:15.561239 6, 0xFFFF, sum = 0
5739 14:47:15.561357 7, 0xFFFF, sum = 0
5740 14:47:15.564843 8, 0xFFFF, sum = 0
5741 14:47:15.564927 9, 0xFFFF, sum = 0
5742 14:47:15.568280 10, 0x0, sum = 1
5743 14:47:15.568363 11, 0x0, sum = 2
5744 14:47:15.570992 12, 0x0, sum = 3
5745 14:47:15.571075 13, 0x0, sum = 4
5746 14:47:15.571158 best_step = 11
5747 14:47:15.574464
5748 14:47:15.574546 ==
5749 14:47:15.577771 Dram Type= 6, Freq= 0, CH_1, rank 1
5750 14:47:15.581500 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5751 14:47:15.581582 ==
5752 14:47:15.581665 RX Vref Scan: 0
5753 14:47:15.581742
5754 14:47:15.584498 RX Vref 0 -> 0, step: 1
5755 14:47:15.584594
5756 14:47:15.587715 RX Delay -69 -> 252, step: 4
5757 14:47:15.594568 iDelay=203, Bit 0, Center 96 (7 ~ 186) 180
5758 14:47:15.597747 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5759 14:47:15.601143 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5760 14:47:15.604344 iDelay=203, Bit 3, Center 94 (3 ~ 186) 184
5761 14:47:15.607429 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5762 14:47:15.610817 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5763 14:47:15.617484 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5764 14:47:15.620649 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5765 14:47:15.623904 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5766 14:47:15.627637 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5767 14:47:15.630505 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5768 14:47:15.637249 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5769 14:47:15.640425 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5770 14:47:15.644030 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5771 14:47:15.647535 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5772 14:47:15.650725 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5773 14:47:15.650805 ==
5774 14:47:15.654031 Dram Type= 6, Freq= 0, CH_1, rank 1
5775 14:47:15.660781 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5776 14:47:15.660861 ==
5777 14:47:15.660924 DQS Delay:
5778 14:47:15.663655 DQS0 = 0, DQS1 = 0
5779 14:47:15.663735 DQM Delay:
5780 14:47:15.663798 DQM0 = 96, DQM1 = 87
5781 14:47:15.666970 DQ Delay:
5782 14:47:15.670225 DQ0 =96, DQ1 =90, DQ2 =88, DQ3 =94
5783 14:47:15.673337 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5784 14:47:15.676635 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5785 14:47:15.680284 DQ12 =98, DQ13 =96, DQ14 =94, DQ15 =96
5786 14:47:15.680363
5787 14:47:15.680425
5788 14:47:15.686843 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5789 14:47:15.690429 CH1 RK1: MR19=505, MR18=1F1F
5790 14:47:15.696844 CH1_RK1: MR19=0x505, MR18=0x1F1F, DQSOSC=412, MR23=63, INC=63, DEC=42
5791 14:47:15.699984 [RxdqsGatingPostProcess] freq 933
5792 14:47:15.706577 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5793 14:47:15.706665 Pre-setting of DQS Precalculation
5794 14:47:15.713068 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5795 14:47:15.719681 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5796 14:47:15.726435 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5797 14:47:15.726515
5798 14:47:15.726577
5799 14:47:15.729680 [Calibration Summary] 1866 Mbps
5800 14:47:15.733203 CH 0, Rank 0
5801 14:47:15.733343 SW Impedance : PASS
5802 14:47:15.736120 DUTY Scan : NO K
5803 14:47:15.739712 ZQ Calibration : PASS
5804 14:47:15.739791 Jitter Meter : NO K
5805 14:47:15.742802 CBT Training : PASS
5806 14:47:15.746142 Write leveling : PASS
5807 14:47:15.746246 RX DQS gating : PASS
5808 14:47:15.749643 RX DQ/DQS(RDDQC) : PASS
5809 14:47:15.749724 TX DQ/DQS : PASS
5810 14:47:15.753217 RX DATLAT : PASS
5811 14:47:15.755964 RX DQ/DQS(Engine): PASS
5812 14:47:15.756044 TX OE : NO K
5813 14:47:15.759233 All Pass.
5814 14:47:15.759338
5815 14:47:15.759427 CH 0, Rank 1
5816 14:47:15.762544 SW Impedance : PASS
5817 14:47:15.762624 DUTY Scan : NO K
5818 14:47:15.765844 ZQ Calibration : PASS
5819 14:47:15.769226 Jitter Meter : NO K
5820 14:47:15.769371 CBT Training : PASS
5821 14:47:15.772548 Write leveling : PASS
5822 14:47:15.775704 RX DQS gating : PASS
5823 14:47:15.775809 RX DQ/DQS(RDDQC) : PASS
5824 14:47:15.779536 TX DQ/DQS : PASS
5825 14:47:15.782303 RX DATLAT : PASS
5826 14:47:15.782407 RX DQ/DQS(Engine): PASS
5827 14:47:15.785751 TX OE : NO K
5828 14:47:15.785830 All Pass.
5829 14:47:15.785892
5830 14:47:15.789294 CH 1, Rank 0
5831 14:47:15.789406 SW Impedance : PASS
5832 14:47:15.792072 DUTY Scan : NO K
5833 14:47:15.795488 ZQ Calibration : PASS
5834 14:47:15.795568 Jitter Meter : NO K
5835 14:47:15.798958 CBT Training : PASS
5836 14:47:15.802359 Write leveling : PASS
5837 14:47:15.802438 RX DQS gating : PASS
5838 14:47:15.805365 RX DQ/DQS(RDDQC) : PASS
5839 14:47:15.808455 TX DQ/DQS : PASS
5840 14:47:15.808526 RX DATLAT : PASS
5841 14:47:15.812046 RX DQ/DQS(Engine): PASS
5842 14:47:15.815207 TX OE : NO K
5843 14:47:15.815286 All Pass.
5844 14:47:15.815349
5845 14:47:15.815407 CH 1, Rank 1
5846 14:47:15.818916 SW Impedance : PASS
5847 14:47:15.822023 DUTY Scan : NO K
5848 14:47:15.822102 ZQ Calibration : PASS
5849 14:47:15.825138 Jitter Meter : NO K
5850 14:47:15.828528 CBT Training : PASS
5851 14:47:15.828607 Write leveling : PASS
5852 14:47:15.831924 RX DQS gating : PASS
5853 14:47:15.835172 RX DQ/DQS(RDDQC) : PASS
5854 14:47:15.835254 TX DQ/DQS : PASS
5855 14:47:15.838539 RX DATLAT : PASS
5856 14:47:15.838621 RX DQ/DQS(Engine): PASS
5857 14:47:15.842108 TX OE : NO K
5858 14:47:15.842190 All Pass.
5859 14:47:15.842273
5860 14:47:15.845378 DramC Write-DBI off
5861 14:47:15.848314 PER_BANK_REFRESH: Hybrid Mode
5862 14:47:15.848396 TX_TRACKING: ON
5863 14:47:15.858589 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5864 14:47:15.861905 [FAST_K] Save calibration result to emmc
5865 14:47:15.865254 dramc_set_vcore_voltage set vcore to 650000
5866 14:47:15.868102 Read voltage for 400, 6
5867 14:47:15.868184 Vio18 = 0
5868 14:47:15.871549 Vcore = 650000
5869 14:47:15.871631 Vdram = 0
5870 14:47:15.871713 Vddq = 0
5871 14:47:15.871791 Vmddr = 0
5872 14:47:15.878225 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5873 14:47:15.884811 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5874 14:47:15.884893 MEM_TYPE=3, freq_sel=20
5875 14:47:15.888055 sv_algorithm_assistance_LP4_800
5876 14:47:15.891512 ============ PULL DRAM RESETB DOWN ============
5877 14:47:15.898096 ========== PULL DRAM RESETB DOWN end =========
5878 14:47:15.901484 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5879 14:47:15.904560 ===================================
5880 14:47:15.908001 LPDDR4 DRAM CONFIGURATION
5881 14:47:15.911255 ===================================
5882 14:47:15.911338 EX_ROW_EN[0] = 0x0
5883 14:47:15.914651 EX_ROW_EN[1] = 0x0
5884 14:47:15.914733 LP4Y_EN = 0x0
5885 14:47:15.917799 WORK_FSP = 0x0
5886 14:47:15.917881 WL = 0x2
5887 14:47:15.920825 RL = 0x2
5888 14:47:15.920907 BL = 0x2
5889 14:47:15.924333 RPST = 0x0
5890 14:47:15.927664 RD_PRE = 0x0
5891 14:47:15.927746 WR_PRE = 0x1
5892 14:47:15.930864 WR_PST = 0x0
5893 14:47:15.930946 DBI_WR = 0x0
5894 14:47:15.934273 DBI_RD = 0x0
5895 14:47:15.934355 OTF = 0x1
5896 14:47:15.937494 ===================================
5897 14:47:15.940917 ===================================
5898 14:47:15.944255 ANA top config
5899 14:47:15.947339 ===================================
5900 14:47:15.947421 DLL_ASYNC_EN = 0
5901 14:47:15.950586 ALL_SLAVE_EN = 1
5902 14:47:15.954031 NEW_RANK_MODE = 1
5903 14:47:15.957384 DLL_IDLE_MODE = 1
5904 14:47:15.957463 LP45_APHY_COMB_EN = 1
5905 14:47:15.960821 TX_ODT_DIS = 1
5906 14:47:15.963934 NEW_8X_MODE = 1
5907 14:47:15.967275 ===================================
5908 14:47:15.970609 ===================================
5909 14:47:15.973694 data_rate = 800
5910 14:47:15.977257 CKR = 1
5911 14:47:15.980418 DQ_P2S_RATIO = 4
5912 14:47:15.983848 ===================================
5913 14:47:15.983928 CA_P2S_RATIO = 4
5914 14:47:15.987039 DQ_CA_OPEN = 0
5915 14:47:15.990406 DQ_SEMI_OPEN = 1
5916 14:47:15.993523 CA_SEMI_OPEN = 1
5917 14:47:15.997134 CA_FULL_RATE = 0
5918 14:47:16.000170 DQ_CKDIV4_EN = 0
5919 14:47:16.000249 CA_CKDIV4_EN = 1
5920 14:47:16.003612 CA_PREDIV_EN = 0
5921 14:47:16.006656 PH8_DLY = 0
5922 14:47:16.010057 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5923 14:47:16.013690 DQ_AAMCK_DIV = 0
5924 14:47:16.016751 CA_AAMCK_DIV = 0
5925 14:47:16.016831 CA_ADMCK_DIV = 4
5926 14:47:16.020184 DQ_TRACK_CA_EN = 0
5927 14:47:16.023343 CA_PICK = 800
5928 14:47:16.026473 CA_MCKIO = 400
5929 14:47:16.029867 MCKIO_SEMI = 400
5930 14:47:16.033296 PLL_FREQ = 3016
5931 14:47:16.036511 DQ_UI_PI_RATIO = 32
5932 14:47:16.039934 CA_UI_PI_RATIO = 32
5933 14:47:16.043247 ===================================
5934 14:47:16.046453 ===================================
5935 14:47:16.046540 memory_type:LPDDR4
5936 14:47:16.049628 GP_NUM : 10
5937 14:47:16.053041 SRAM_EN : 1
5938 14:47:16.053120 MD32_EN : 0
5939 14:47:16.056360 ===================================
5940 14:47:16.059555 [ANA_INIT] >>>>>>>>>>>>>>
5941 14:47:16.062718 <<<<<< [CONFIGURE PHASE]: ANA_TX
5942 14:47:16.066348 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5943 14:47:16.069625 ===================================
5944 14:47:16.072899 data_rate = 800,PCW = 0X7400
5945 14:47:16.076180 ===================================
5946 14:47:16.079442 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5947 14:47:16.082742 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5948 14:47:16.096021 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5949 14:47:16.099435 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5950 14:47:16.102546 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5951 14:47:16.106245 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5952 14:47:16.109776 [ANA_INIT] flow start
5953 14:47:16.109855 [ANA_INIT] PLL >>>>>>>>
5954 14:47:16.112858 [ANA_INIT] PLL <<<<<<<<
5955 14:47:16.116299 [ANA_INIT] MIDPI >>>>>>>>
5956 14:47:16.119088 [ANA_INIT] MIDPI <<<<<<<<
5957 14:47:16.119167 [ANA_INIT] DLL >>>>>>>>
5958 14:47:16.122747 [ANA_INIT] flow end
5959 14:47:16.125811 ============ LP4 DIFF to SE enter ============
5960 14:47:16.129098 ============ LP4 DIFF to SE exit ============
5961 14:47:16.132332 [ANA_INIT] <<<<<<<<<<<<<
5962 14:47:16.135797 [Flow] Enable top DCM control >>>>>
5963 14:47:16.138949 [Flow] Enable top DCM control <<<<<
5964 14:47:16.142344 Enable DLL master slave shuffle
5965 14:47:16.149121 ==============================================================
5966 14:47:16.149202 Gating Mode config
5967 14:47:16.155423 ==============================================================
5968 14:47:16.155503 Config description:
5969 14:47:16.165510 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5970 14:47:16.171878 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5971 14:47:16.178793 SELPH_MODE 0: By rank 1: By Phase
5972 14:47:16.182018 ==============================================================
5973 14:47:16.185489 GAT_TRACK_EN = 0
5974 14:47:16.188692 RX_GATING_MODE = 2
5975 14:47:16.191853 RX_GATING_TRACK_MODE = 2
5976 14:47:16.195372 SELPH_MODE = 1
5977 14:47:16.198966 PICG_EARLY_EN = 1
5978 14:47:16.201989 VALID_LAT_VALUE = 1
5979 14:47:16.208525 ==============================================================
5980 14:47:16.211760 Enter into Gating configuration >>>>
5981 14:47:16.215087 Exit from Gating configuration <<<<
5982 14:47:16.218421 Enter into DVFS_PRE_config >>>>>
5983 14:47:16.228520 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5984 14:47:16.231693 Exit from DVFS_PRE_config <<<<<
5985 14:47:16.234931 Enter into PICG configuration >>>>
5986 14:47:16.238802 Exit from PICG configuration <<<<
5987 14:47:16.242186 [RX_INPUT] configuration >>>>>
5988 14:47:16.242266 [RX_INPUT] configuration <<<<<
5989 14:47:16.248077 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5990 14:47:16.254916 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5991 14:47:16.261168 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5992 14:47:16.264949 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5993 14:47:16.271186 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5994 14:47:16.277575 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5995 14:47:16.280889 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5996 14:47:16.287515 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5997 14:47:16.290907 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5998 14:47:16.294051 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5999 14:47:16.297669 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6000 14:47:16.303996 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6001 14:47:16.307500 ===================================
6002 14:47:16.307580 LPDDR4 DRAM CONFIGURATION
6003 14:47:16.310607 ===================================
6004 14:47:16.314359 EX_ROW_EN[0] = 0x0
6005 14:47:16.317515 EX_ROW_EN[1] = 0x0
6006 14:47:16.317594 LP4Y_EN = 0x0
6007 14:47:16.320520 WORK_FSP = 0x0
6008 14:47:16.320629 WL = 0x2
6009 14:47:16.323982 RL = 0x2
6010 14:47:16.324062 BL = 0x2
6011 14:47:16.327419 RPST = 0x0
6012 14:47:16.327499 RD_PRE = 0x0
6013 14:47:16.330764 WR_PRE = 0x1
6014 14:47:16.330843 WR_PST = 0x0
6015 14:47:16.333863 DBI_WR = 0x0
6016 14:47:16.333942 DBI_RD = 0x0
6017 14:47:16.337096 OTF = 0x1
6018 14:47:16.340364 ===================================
6019 14:47:16.343719 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6020 14:47:16.346965 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6021 14:47:16.354044 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6022 14:47:16.357137 ===================================
6023 14:47:16.357243 LPDDR4 DRAM CONFIGURATION
6024 14:47:16.360307 ===================================
6025 14:47:16.363542 EX_ROW_EN[0] = 0x10
6026 14:47:16.366753 EX_ROW_EN[1] = 0x0
6027 14:47:16.366833 LP4Y_EN = 0x0
6028 14:47:16.370112 WORK_FSP = 0x0
6029 14:47:16.370192 WL = 0x2
6030 14:47:16.373205 RL = 0x2
6031 14:47:16.373331 BL = 0x2
6032 14:47:16.376510 RPST = 0x0
6033 14:47:16.376589 RD_PRE = 0x0
6034 14:47:16.379847 WR_PRE = 0x1
6035 14:47:16.379926 WR_PST = 0x0
6036 14:47:16.383322 DBI_WR = 0x0
6037 14:47:16.383401 DBI_RD = 0x0
6038 14:47:16.386839 OTF = 0x1
6039 14:47:16.390005 ===================================
6040 14:47:16.396308 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6041 14:47:16.399855 nWR fixed to 30
6042 14:47:16.403001 [ModeRegInit_LP4] CH0 RK0
6043 14:47:16.403080 [ModeRegInit_LP4] CH0 RK1
6044 14:47:16.406372 [ModeRegInit_LP4] CH1 RK0
6045 14:47:16.409643 [ModeRegInit_LP4] CH1 RK1
6046 14:47:16.409722 match AC timing 18
6047 14:47:16.416482 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6048 14:47:16.419627 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6049 14:47:16.423131 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6050 14:47:16.429529 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6051 14:47:16.432926 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6052 14:47:16.433006 ==
6053 14:47:16.436088 Dram Type= 6, Freq= 0, CH_0, rank 0
6054 14:47:16.439320 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6055 14:47:16.439401 ==
6056 14:47:16.446082 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6057 14:47:16.452728 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6058 14:47:16.456149 [CA 0] Center 36 (8~64) winsize 57
6059 14:47:16.459646 [CA 1] Center 36 (8~64) winsize 57
6060 14:47:16.462871 [CA 2] Center 36 (8~64) winsize 57
6061 14:47:16.462951 [CA 3] Center 36 (8~64) winsize 57
6062 14:47:16.466035 [CA 4] Center 36 (8~64) winsize 57
6063 14:47:16.469250 [CA 5] Center 36 (8~64) winsize 57
6064 14:47:16.469378
6065 14:47:16.475994 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6066 14:47:16.476074
6067 14:47:16.479349 [CATrainingPosCal] consider 1 rank data
6068 14:47:16.482435 u2DelayCellTimex100 = 270/100 ps
6069 14:47:16.486025 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6070 14:47:16.489225 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6071 14:47:16.492260 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6072 14:47:16.495555 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6073 14:47:16.499026 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6074 14:47:16.502432 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6075 14:47:16.502512
6076 14:47:16.505420 CA PerBit enable=1, Macro0, CA PI delay=36
6077 14:47:16.505499
6078 14:47:16.508821 [CBTSetCACLKResult] CA Dly = 36
6079 14:47:16.512131 CS Dly: 1 (0~32)
6080 14:47:16.512210 ==
6081 14:47:16.515301 Dram Type= 6, Freq= 0, CH_0, rank 1
6082 14:47:16.518742 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6083 14:47:16.518823 ==
6084 14:47:16.525414 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6085 14:47:16.531934 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6086 14:47:16.535525 [CA 0] Center 36 (8~64) winsize 57
6087 14:47:16.535605 [CA 1] Center 36 (8~64) winsize 57
6088 14:47:16.538434 [CA 2] Center 36 (8~64) winsize 57
6089 14:47:16.541739 [CA 3] Center 36 (8~64) winsize 57
6090 14:47:16.545208 [CA 4] Center 36 (8~64) winsize 57
6091 14:47:16.548248 [CA 5] Center 36 (8~64) winsize 57
6092 14:47:16.548327
6093 14:47:16.551860 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6094 14:47:16.551940
6095 14:47:16.558440 [CATrainingPosCal] consider 2 rank data
6096 14:47:16.558520 u2DelayCellTimex100 = 270/100 ps
6097 14:47:16.565122 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6098 14:47:16.568393 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6099 14:47:16.571377 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6100 14:47:16.574811 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6101 14:47:16.577942 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6102 14:47:16.581267 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6103 14:47:16.581386
6104 14:47:16.585163 CA PerBit enable=1, Macro0, CA PI delay=36
6105 14:47:16.585267
6106 14:47:16.587867 [CBTSetCACLKResult] CA Dly = 36
6107 14:47:16.591372 CS Dly: 1 (0~32)
6108 14:47:16.591451
6109 14:47:16.594668 ----->DramcWriteLeveling(PI) begin...
6110 14:47:16.594748 ==
6111 14:47:16.597951 Dram Type= 6, Freq= 0, CH_0, rank 0
6112 14:47:16.601697 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6113 14:47:16.601780 ==
6114 14:47:16.604406 Write leveling (Byte 0): 32 => 0
6115 14:47:16.607626 Write leveling (Byte 1): 32 => 0
6116 14:47:16.611211 DramcWriteLeveling(PI) end<-----
6117 14:47:16.611293
6118 14:47:16.611375 ==
6119 14:47:16.614758 Dram Type= 6, Freq= 0, CH_0, rank 0
6120 14:47:16.617887 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6121 14:47:16.617970 ==
6122 14:47:16.621077 [Gating] SW mode calibration
6123 14:47:16.627675 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6124 14:47:16.634651 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6125 14:47:16.637800 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6126 14:47:16.640908 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6127 14:47:16.647514 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6128 14:47:16.650626 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6129 14:47:16.654120 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6130 14:47:16.660596 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6131 14:47:16.664279 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6132 14:47:16.667355 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6133 14:47:16.673611 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6134 14:47:16.676958 Total UI for P1: 0, mck2ui 16
6135 14:47:16.680576 best dqsien dly found for B0: ( 0, 10, 16)
6136 14:47:16.680658 Total UI for P1: 0, mck2ui 16
6137 14:47:16.687015 best dqsien dly found for B1: ( 0, 10, 16)
6138 14:47:16.690504 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6139 14:47:16.693847 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6140 14:47:16.693927
6141 14:47:16.697153 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6142 14:47:16.700947 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6143 14:47:16.703542 [Gating] SW calibration Done
6144 14:47:16.703622 ==
6145 14:47:16.707350 Dram Type= 6, Freq= 0, CH_0, rank 0
6146 14:47:16.710251 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6147 14:47:16.710331 ==
6148 14:47:16.713305 RX Vref Scan: 0
6149 14:47:16.713395
6150 14:47:16.716703 RX Vref 0 -> 0, step: 1
6151 14:47:16.716807
6152 14:47:16.716896 RX Delay -410 -> 252, step: 16
6153 14:47:16.723699 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6154 14:47:16.727012 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6155 14:47:16.729970 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6156 14:47:16.733591 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6157 14:47:16.740032 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6158 14:47:16.743229 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6159 14:47:16.746609 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6160 14:47:16.753189 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6161 14:47:16.756416 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6162 14:47:16.759536 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6163 14:47:16.762991 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6164 14:47:16.769641 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6165 14:47:16.772759 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6166 14:47:16.776105 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6167 14:47:16.779696 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6168 14:47:16.786404 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6169 14:47:16.786483 ==
6170 14:47:16.789670 Dram Type= 6, Freq= 0, CH_0, rank 0
6171 14:47:16.792993 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6172 14:47:16.793074 ==
6173 14:47:16.793136 DQS Delay:
6174 14:47:16.796213 DQS0 = 51, DQS1 = 59
6175 14:47:16.796292 DQM Delay:
6176 14:47:16.799100 DQM0 = 12, DQM1 = 13
6177 14:47:16.799180 DQ Delay:
6178 14:47:16.802594 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6179 14:47:16.806106 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6180 14:47:16.809302 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6181 14:47:16.812463 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6182 14:47:16.812543
6183 14:47:16.812605
6184 14:47:16.812662 ==
6185 14:47:16.815882 Dram Type= 6, Freq= 0, CH_0, rank 0
6186 14:47:16.819358 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6187 14:47:16.819439 ==
6188 14:47:16.822501
6189 14:47:16.822580
6190 14:47:16.822642 TX Vref Scan disable
6191 14:47:16.825742 == TX Byte 0 ==
6192 14:47:16.829010 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6193 14:47:16.832251 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6194 14:47:16.835497 == TX Byte 1 ==
6195 14:47:16.838960 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6196 14:47:16.842243 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6197 14:47:16.842323 ==
6198 14:47:16.845509 Dram Type= 6, Freq= 0, CH_0, rank 0
6199 14:47:16.852308 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6200 14:47:16.852388 ==
6201 14:47:16.852451
6202 14:47:16.852508
6203 14:47:16.852563 TX Vref Scan disable
6204 14:47:16.855456 == TX Byte 0 ==
6205 14:47:16.858695 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6206 14:47:16.861929 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6207 14:47:16.865190 == TX Byte 1 ==
6208 14:47:16.868702 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6209 14:47:16.871918 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6210 14:47:16.872002
6211 14:47:16.875299 [DATLAT]
6212 14:47:16.875379 Freq=400, CH0 RK0
6213 14:47:16.875441
6214 14:47:16.878475 DATLAT Default: 0xf
6215 14:47:16.878554 0, 0xFFFF, sum = 0
6216 14:47:16.881733 1, 0xFFFF, sum = 0
6217 14:47:16.881815 2, 0xFFFF, sum = 0
6218 14:47:16.885431 3, 0xFFFF, sum = 0
6219 14:47:16.885512 4, 0xFFFF, sum = 0
6220 14:47:16.888836 5, 0xFFFF, sum = 0
6221 14:47:16.891859 6, 0xFFFF, sum = 0
6222 14:47:16.891964 7, 0xFFFF, sum = 0
6223 14:47:16.895082 8, 0xFFFF, sum = 0
6224 14:47:16.895163 9, 0xFFFF, sum = 0
6225 14:47:16.898407 10, 0xFFFF, sum = 0
6226 14:47:16.898487 11, 0xFFFF, sum = 0
6227 14:47:16.901575 12, 0x0, sum = 1
6228 14:47:16.901656 13, 0x0, sum = 2
6229 14:47:16.905017 14, 0x0, sum = 3
6230 14:47:16.905115 15, 0x0, sum = 4
6231 14:47:16.905208 best_step = 13
6232 14:47:16.908001
6233 14:47:16.908090 ==
6234 14:47:16.911614 Dram Type= 6, Freq= 0, CH_0, rank 0
6235 14:47:16.914822 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6236 14:47:16.914927 ==
6237 14:47:16.915017 RX Vref Scan: 1
6238 14:47:16.915102
6239 14:47:16.918187 RX Vref 0 -> 0, step: 1
6240 14:47:16.918267
6241 14:47:16.921469 RX Delay -359 -> 252, step: 8
6242 14:47:16.921548
6243 14:47:16.924982 Set Vref, RX VrefLevel [Byte0]: 49
6244 14:47:16.928121 [Byte1]: 51
6245 14:47:16.931783
6246 14:47:16.931862 Final RX Vref Byte 0 = 49 to rank0
6247 14:47:16.935468 Final RX Vref Byte 1 = 51 to rank0
6248 14:47:16.938699 Final RX Vref Byte 0 = 49 to rank1
6249 14:47:16.941841 Final RX Vref Byte 1 = 51 to rank1==
6250 14:47:16.945194 Dram Type= 6, Freq= 0, CH_0, rank 0
6251 14:47:16.951611 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6252 14:47:16.951691 ==
6253 14:47:16.951753 DQS Delay:
6254 14:47:16.955117 DQS0 = 52, DQS1 = 68
6255 14:47:16.955197 DQM Delay:
6256 14:47:16.955274 DQM0 = 9, DQM1 = 18
6257 14:47:16.958241 DQ Delay:
6258 14:47:16.961632 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =4
6259 14:47:16.961711 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6260 14:47:16.964922 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6261 14:47:16.968280 DQ12 =28, DQ13 =24, DQ14 =28, DQ15 =28
6262 14:47:16.968360
6263 14:47:16.971396
6264 14:47:16.978151 [DQSOSCAuto] RK0, (LSB)MR18= 0xadad, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6265 14:47:16.981750 CH0 RK0: MR19=C0C, MR18=ADAD
6266 14:47:16.987929 CH0_RK0: MR19=0xC0C, MR18=0xADAD, DQSOSC=388, MR23=63, INC=392, DEC=261
6267 14:47:16.988009 ==
6268 14:47:16.991242 Dram Type= 6, Freq= 0, CH_0, rank 1
6269 14:47:16.994492 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6270 14:47:16.994572 ==
6271 14:47:16.997936 [Gating] SW mode calibration
6272 14:47:17.004691 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6273 14:47:17.011285 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6274 14:47:17.014520 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6275 14:47:17.017752 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6276 14:47:17.024822 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6277 14:47:17.027819 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6278 14:47:17.031084 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 14:47:17.037320 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 14:47:17.041045 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 14:47:17.044088 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6282 14:47:17.050748 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6283 14:47:17.050828 Total UI for P1: 0, mck2ui 16
6284 14:47:17.057256 best dqsien dly found for B0: ( 0, 10, 16)
6285 14:47:17.057382 Total UI for P1: 0, mck2ui 16
6286 14:47:17.063926 best dqsien dly found for B1: ( 0, 10, 24)
6287 14:47:17.067125 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6288 14:47:17.070603 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6289 14:47:17.070682
6290 14:47:17.073673 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6291 14:47:17.077223 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6292 14:47:17.080121 [Gating] SW calibration Done
6293 14:47:17.080200 ==
6294 14:47:17.083932 Dram Type= 6, Freq= 0, CH_0, rank 1
6295 14:47:17.086967 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6296 14:47:17.087047 ==
6297 14:47:17.090463 RX Vref Scan: 0
6298 14:47:17.090543
6299 14:47:17.090605 RX Vref 0 -> 0, step: 1
6300 14:47:17.093282
6301 14:47:17.093400 RX Delay -410 -> 252, step: 16
6302 14:47:17.100246 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6303 14:47:17.103410 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6304 14:47:17.106695 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6305 14:47:17.109881 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6306 14:47:17.116468 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6307 14:47:17.120176 iDelay=230, Bit 5, Center -51 (-314 ~ 213) 528
6308 14:47:17.123207 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6309 14:47:17.126523 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6310 14:47:17.133112 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6311 14:47:17.136408 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6312 14:47:17.139710 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6313 14:47:17.146320 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6314 14:47:17.149571 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6315 14:47:17.152925 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6316 14:47:17.156504 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6317 14:47:17.162642 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6318 14:47:17.162722 ==
6319 14:47:17.166108 Dram Type= 6, Freq= 0, CH_0, rank 1
6320 14:47:17.169354 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6321 14:47:17.169438 ==
6322 14:47:17.169537 DQS Delay:
6323 14:47:17.172860 DQS0 = 51, DQS1 = 59
6324 14:47:17.172939 DQM Delay:
6325 14:47:17.175882 DQM0 = 14, DQM1 = 14
6326 14:47:17.175970 DQ Delay:
6327 14:47:17.179357 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6328 14:47:17.182688 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6329 14:47:17.185967 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =0
6330 14:47:17.189215 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6331 14:47:17.189356
6332 14:47:17.189421
6333 14:47:17.189479 ==
6334 14:47:17.192603 Dram Type= 6, Freq= 0, CH_0, rank 1
6335 14:47:17.196032 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6336 14:47:17.196116 ==
6337 14:47:17.196198
6338 14:47:17.199228
6339 14:47:17.199310 TX Vref Scan disable
6340 14:47:17.202455 == TX Byte 0 ==
6341 14:47:17.205893 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6342 14:47:17.209199 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6343 14:47:17.212417 == TX Byte 1 ==
6344 14:47:17.215720 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6345 14:47:17.219157 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6346 14:47:17.219239 ==
6347 14:47:17.222283 Dram Type= 6, Freq= 0, CH_0, rank 1
6348 14:47:17.225852 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6349 14:47:17.225934 ==
6350 14:47:17.229184
6351 14:47:17.229265
6352 14:47:17.229355 TX Vref Scan disable
6353 14:47:17.232444 == TX Byte 0 ==
6354 14:47:17.235810 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6355 14:47:17.239104 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6356 14:47:17.242237 == TX Byte 1 ==
6357 14:47:17.245723 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6358 14:47:17.248952 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6359 14:47:17.249035
6360 14:47:17.249130 [DATLAT]
6361 14:47:17.252560 Freq=400, CH0 RK1
6362 14:47:17.252662
6363 14:47:17.252748 DATLAT Default: 0xd
6364 14:47:17.255634 0, 0xFFFF, sum = 0
6365 14:47:17.258926 1, 0xFFFF, sum = 0
6366 14:47:17.259006 2, 0xFFFF, sum = 0
6367 14:47:17.262297 3, 0xFFFF, sum = 0
6368 14:47:17.262378 4, 0xFFFF, sum = 0
6369 14:47:17.265475 5, 0xFFFF, sum = 0
6370 14:47:17.265555 6, 0xFFFF, sum = 0
6371 14:47:17.269017 7, 0xFFFF, sum = 0
6372 14:47:17.269098 8, 0xFFFF, sum = 0
6373 14:47:17.272104 9, 0xFFFF, sum = 0
6374 14:47:17.272184 10, 0xFFFF, sum = 0
6375 14:47:17.275302 11, 0xFFFF, sum = 0
6376 14:47:17.275382 12, 0x0, sum = 1
6377 14:47:17.278563 13, 0x0, sum = 2
6378 14:47:17.278643 14, 0x0, sum = 3
6379 14:47:17.282011 15, 0x0, sum = 4
6380 14:47:17.282091 best_step = 13
6381 14:47:17.282153
6382 14:47:17.282210 ==
6383 14:47:17.285331 Dram Type= 6, Freq= 0, CH_0, rank 1
6384 14:47:17.288987 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6385 14:47:17.291740 ==
6386 14:47:17.291819 RX Vref Scan: 0
6387 14:47:17.291881
6388 14:47:17.295236 RX Vref 0 -> 0, step: 1
6389 14:47:17.295315
6390 14:47:17.298370 RX Delay -359 -> 252, step: 8
6391 14:47:17.304908 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6392 14:47:17.308326 iDelay=217, Bit 1, Center -36 (-287 ~ 216) 504
6393 14:47:17.311656 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6394 14:47:17.315146 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6395 14:47:17.321850 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6396 14:47:17.325255 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6397 14:47:17.328599 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6398 14:47:17.331963 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6399 14:47:17.335109 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6400 14:47:17.341505 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6401 14:47:17.344845 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6402 14:47:17.348285 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6403 14:47:17.354825 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6404 14:47:17.358121 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6405 14:47:17.361665 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6406 14:47:17.364859 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6407 14:47:17.368230 ==
6408 14:47:17.368309 Dram Type= 6, Freq= 0, CH_0, rank 1
6409 14:47:17.374843 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6410 14:47:17.374923 ==
6411 14:47:17.374985 DQS Delay:
6412 14:47:17.378038 DQS0 = 52, DQS1 = 64
6413 14:47:17.378117 DQM Delay:
6414 14:47:17.381625 DQM0 = 11, DQM1 = 14
6415 14:47:17.381703 DQ Delay:
6416 14:47:17.384705 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =4
6417 14:47:17.388008 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =20
6418 14:47:17.391194 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6419 14:47:17.395416 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6420 14:47:17.395496
6421 14:47:17.395557
6422 14:47:17.401447 [DQSOSCAuto] RK1, (LSB)MR18= 0xcccc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6423 14:47:17.404434 CH0 RK1: MR19=C0C, MR18=CCCC
6424 14:47:17.411435 CH0_RK1: MR19=0xC0C, MR18=0xCCCC, DQSOSC=384, MR23=63, INC=400, DEC=267
6425 14:47:17.414436 [RxdqsGatingPostProcess] freq 400
6426 14:47:17.417945 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6427 14:47:17.421068 Pre-setting of DQS Precalculation
6428 14:47:17.427840 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6429 14:47:17.427920 ==
6430 14:47:17.430897 Dram Type= 6, Freq= 0, CH_1, rank 0
6431 14:47:17.434421 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6432 14:47:17.434505 ==
6433 14:47:17.441166 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6434 14:47:17.447921 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6435 14:47:17.451119 [CA 0] Center 36 (8~64) winsize 57
6436 14:47:17.451198 [CA 1] Center 36 (8~64) winsize 57
6437 14:47:17.454215 [CA 2] Center 36 (8~64) winsize 57
6438 14:47:17.457558 [CA 3] Center 36 (8~64) winsize 57
6439 14:47:17.460801 [CA 4] Center 36 (8~64) winsize 57
6440 14:47:17.464027 [CA 5] Center 36 (8~64) winsize 57
6441 14:47:17.464107
6442 14:47:17.467451 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6443 14:47:17.467556
6444 14:47:17.474007 [CATrainingPosCal] consider 1 rank data
6445 14:47:17.474086 u2DelayCellTimex100 = 270/100 ps
6446 14:47:17.480824 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6447 14:47:17.483764 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6448 14:47:17.487111 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6449 14:47:17.490477 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6450 14:47:17.494157 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6451 14:47:17.497214 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6452 14:47:17.497321
6453 14:47:17.500532 CA PerBit enable=1, Macro0, CA PI delay=36
6454 14:47:17.500612
6455 14:47:17.503917 [CBTSetCACLKResult] CA Dly = 36
6456 14:47:17.507103 CS Dly: 1 (0~32)
6457 14:47:17.507183 ==
6458 14:47:17.510704 Dram Type= 6, Freq= 0, CH_1, rank 1
6459 14:47:17.513722 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6460 14:47:17.513802 ==
6461 14:47:17.520503 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6462 14:47:17.523890 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6463 14:47:17.526858 [CA 0] Center 36 (8~64) winsize 57
6464 14:47:17.530472 [CA 1] Center 36 (8~64) winsize 57
6465 14:47:17.533777 [CA 2] Center 36 (8~64) winsize 57
6466 14:47:17.537057 [CA 3] Center 36 (8~64) winsize 57
6467 14:47:17.540439 [CA 4] Center 36 (8~64) winsize 57
6468 14:47:17.543838 [CA 5] Center 36 (8~64) winsize 57
6469 14:47:17.543926
6470 14:47:17.546787 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6471 14:47:17.546866
6472 14:47:17.550141 [CATrainingPosCal] consider 2 rank data
6473 14:47:17.553584 u2DelayCellTimex100 = 270/100 ps
6474 14:47:17.556884 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6475 14:47:17.559965 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6476 14:47:17.563715 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6477 14:47:17.570202 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6478 14:47:17.573315 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6479 14:47:17.576597 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6480 14:47:17.576677
6481 14:47:17.580037 CA PerBit enable=1, Macro0, CA PI delay=36
6482 14:47:17.580116
6483 14:47:17.583431 [CBTSetCACLKResult] CA Dly = 36
6484 14:47:17.583510 CS Dly: 1 (0~32)
6485 14:47:17.583573
6486 14:47:17.586699 ----->DramcWriteLeveling(PI) begin...
6487 14:47:17.586779 ==
6488 14:47:17.590381 Dram Type= 6, Freq= 0, CH_1, rank 0
6489 14:47:17.596653 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6490 14:47:17.596733 ==
6491 14:47:17.599880 Write leveling (Byte 0): 32 => 0
6492 14:47:17.603465 Write leveling (Byte 1): 32 => 0
6493 14:47:17.603544 DramcWriteLeveling(PI) end<-----
6494 14:47:17.606696
6495 14:47:17.606775 ==
6496 14:47:17.609749 Dram Type= 6, Freq= 0, CH_1, rank 0
6497 14:47:17.613080 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6498 14:47:17.613159 ==
6499 14:47:17.616314 [Gating] SW mode calibration
6500 14:47:17.623071 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6501 14:47:17.626163 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6502 14:47:17.632896 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6503 14:47:17.636081 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6504 14:47:17.639647 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6505 14:47:17.646082 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6506 14:47:17.649622 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6507 14:47:17.652819 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6508 14:47:17.659430 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6509 14:47:17.662904 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6510 14:47:17.666514 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6511 14:47:17.669866 Total UI for P1: 0, mck2ui 16
6512 14:47:17.672842 best dqsien dly found for B0: ( 0, 10, 16)
6513 14:47:17.676046 Total UI for P1: 0, mck2ui 16
6514 14:47:17.679690 best dqsien dly found for B1: ( 0, 10, 16)
6515 14:47:17.682793 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6516 14:47:17.686008 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6517 14:47:17.686087
6518 14:47:17.692572 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6519 14:47:17.695963 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6520 14:47:17.699437 [Gating] SW calibration Done
6521 14:47:17.699516 ==
6522 14:47:17.702790 Dram Type= 6, Freq= 0, CH_1, rank 0
6523 14:47:17.705967 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6524 14:47:17.706047 ==
6525 14:47:17.709156 RX Vref Scan: 0
6526 14:47:17.709260
6527 14:47:17.709340 RX Vref 0 -> 0, step: 1
6528 14:47:17.709399
6529 14:47:17.712361 RX Delay -410 -> 252, step: 16
6530 14:47:17.715820 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6531 14:47:17.722322 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6532 14:47:17.725486 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6533 14:47:17.728874 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6534 14:47:17.732397 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6535 14:47:17.738933 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6536 14:47:17.742018 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6537 14:47:17.745528 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6538 14:47:17.748917 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6539 14:47:17.755388 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6540 14:47:17.758761 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6541 14:47:17.762337 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6542 14:47:17.768887 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6543 14:47:17.771926 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6544 14:47:17.775177 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6545 14:47:17.778765 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6546 14:47:17.778845 ==
6547 14:47:17.781982 Dram Type= 6, Freq= 0, CH_1, rank 0
6548 14:47:17.788584 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6549 14:47:17.788663 ==
6550 14:47:17.788728 DQS Delay:
6551 14:47:17.791816 DQS0 = 43, DQS1 = 59
6552 14:47:17.791896 DQM Delay:
6553 14:47:17.795208 DQM0 = 6, DQM1 = 15
6554 14:47:17.795288 DQ Delay:
6555 14:47:17.798465 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6556 14:47:17.801775 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6557 14:47:17.801854 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6558 14:47:17.805106 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6559 14:47:17.808568
6560 14:47:17.808647
6561 14:47:17.808709 ==
6562 14:47:17.811646 Dram Type= 6, Freq= 0, CH_1, rank 0
6563 14:47:17.815027 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6564 14:47:17.815107 ==
6565 14:47:17.815170
6566 14:47:17.815227
6567 14:47:17.818633 TX Vref Scan disable
6568 14:47:17.818712 == TX Byte 0 ==
6569 14:47:17.821612 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6570 14:47:17.828229 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6571 14:47:17.828318 == TX Byte 1 ==
6572 14:47:17.834654 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6573 14:47:17.837974 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6574 14:47:17.838053 ==
6575 14:47:17.841564 Dram Type= 6, Freq= 0, CH_1, rank 0
6576 14:47:17.844967 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6577 14:47:17.845046 ==
6578 14:47:17.845108
6579 14:47:17.845165
6580 14:47:17.848295 TX Vref Scan disable
6581 14:47:17.848377 == TX Byte 0 ==
6582 14:47:17.854693 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6583 14:47:17.857963 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6584 14:47:17.858043 == TX Byte 1 ==
6585 14:47:17.864570 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6586 14:47:17.867925 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6587 14:47:17.868004
6588 14:47:17.868065 [DATLAT]
6589 14:47:17.871798 Freq=400, CH1 RK0
6590 14:47:17.871878
6591 14:47:17.871939 DATLAT Default: 0xf
6592 14:47:17.874676 0, 0xFFFF, sum = 0
6593 14:47:17.874759 1, 0xFFFF, sum = 0
6594 14:47:17.877927 2, 0xFFFF, sum = 0
6595 14:47:17.878007 3, 0xFFFF, sum = 0
6596 14:47:17.881521 4, 0xFFFF, sum = 0
6597 14:47:17.881601 5, 0xFFFF, sum = 0
6598 14:47:17.884720 6, 0xFFFF, sum = 0
6599 14:47:17.884801 7, 0xFFFF, sum = 0
6600 14:47:17.887882 8, 0xFFFF, sum = 0
6601 14:47:17.891383 9, 0xFFFF, sum = 0
6602 14:47:17.891464 10, 0xFFFF, sum = 0
6603 14:47:17.894510 11, 0xFFFF, sum = 0
6604 14:47:17.894591 12, 0x0, sum = 1
6605 14:47:17.898070 13, 0x0, sum = 2
6606 14:47:17.898150 14, 0x0, sum = 3
6607 14:47:17.901425 15, 0x0, sum = 4
6608 14:47:17.901505 best_step = 13
6609 14:47:17.901566
6610 14:47:17.901623 ==
6611 14:47:17.904805 Dram Type= 6, Freq= 0, CH_1, rank 0
6612 14:47:17.907920 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6613 14:47:17.908000 ==
6614 14:47:17.911178 RX Vref Scan: 1
6615 14:47:17.911257
6616 14:47:17.914268 RX Vref 0 -> 0, step: 1
6617 14:47:17.914348
6618 14:47:17.914409 RX Delay -359 -> 252, step: 8
6619 14:47:17.914467
6620 14:47:17.917641 Set Vref, RX VrefLevel [Byte0]: 52
6621 14:47:17.921146 [Byte1]: 49
6622 14:47:17.926462
6623 14:47:17.926541 Final RX Vref Byte 0 = 52 to rank0
6624 14:47:17.929661 Final RX Vref Byte 1 = 49 to rank0
6625 14:47:17.933312 Final RX Vref Byte 0 = 52 to rank1
6626 14:47:17.936343 Final RX Vref Byte 1 = 49 to rank1==
6627 14:47:17.939578 Dram Type= 6, Freq= 0, CH_1, rank 0
6628 14:47:17.946490 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6629 14:47:17.946569 ==
6630 14:47:17.946632 DQS Delay:
6631 14:47:17.949742 DQS0 = 48, DQS1 = 64
6632 14:47:17.949822 DQM Delay:
6633 14:47:17.949884 DQM0 = 8, DQM1 = 16
6634 14:47:17.953021 DQ Delay:
6635 14:47:17.956098 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6636 14:47:17.956177 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6637 14:47:17.959788 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6638 14:47:17.962786 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6639 14:47:17.962865
6640 14:47:17.962927
6641 14:47:17.972675 [DQSOSCAuto] RK0, (LSB)MR18= 0xd4d4, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 383 ps
6642 14:47:17.975906 CH1 RK0: MR19=C0C, MR18=D4D4
6643 14:47:17.982624 CH1_RK0: MR19=0xC0C, MR18=0xD4D4, DQSOSC=383, MR23=63, INC=402, DEC=268
6644 14:47:17.982714 ==
6645 14:47:17.986156 Dram Type= 6, Freq= 0, CH_1, rank 1
6646 14:47:17.989185 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6647 14:47:17.989299 ==
6648 14:47:17.992643 [Gating] SW mode calibration
6649 14:47:17.999316 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6650 14:47:18.002703 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6651 14:47:18.009088 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6652 14:47:18.012489 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6653 14:47:18.015601 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6654 14:47:18.022452 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6655 14:47:18.025833 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6656 14:47:18.029439 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6657 14:47:18.035502 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6658 14:47:18.039107 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6659 14:47:18.042709 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6660 14:47:18.045603 Total UI for P1: 0, mck2ui 16
6661 14:47:18.049020 best dqsien dly found for B0: ( 0, 10, 16)
6662 14:47:18.052270 Total UI for P1: 0, mck2ui 16
6663 14:47:18.055620 best dqsien dly found for B1: ( 0, 10, 16)
6664 14:47:18.059106 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6665 14:47:18.065442 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6666 14:47:18.065522
6667 14:47:18.069170 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6668 14:47:18.072269 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6669 14:47:18.075695 [Gating] SW calibration Done
6670 14:47:18.075775 ==
6671 14:47:18.078676 Dram Type= 6, Freq= 0, CH_1, rank 1
6672 14:47:18.081895 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6673 14:47:18.081975 ==
6674 14:47:18.085519 RX Vref Scan: 0
6675 14:47:18.085599
6676 14:47:18.085661 RX Vref 0 -> 0, step: 1
6677 14:47:18.085719
6678 14:47:18.088596 RX Delay -410 -> 252, step: 16
6679 14:47:18.095376 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6680 14:47:18.098501 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6681 14:47:18.101709 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6682 14:47:18.105206 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6683 14:47:18.111769 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6684 14:47:18.115325 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6685 14:47:18.118592 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6686 14:47:18.121802 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6687 14:47:18.128165 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6688 14:47:18.131580 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6689 14:47:18.134708 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6690 14:47:18.138095 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6691 14:47:18.144717 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6692 14:47:18.148273 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6693 14:47:18.151398 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6694 14:47:18.154920 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6695 14:47:18.158311 ==
6696 14:47:18.158391 Dram Type= 6, Freq= 0, CH_1, rank 1
6697 14:47:18.164930 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6698 14:47:18.165036 ==
6699 14:47:18.165128 DQS Delay:
6700 14:47:18.168031 DQS0 = 43, DQS1 = 59
6701 14:47:18.168106 DQM Delay:
6702 14:47:18.171399 DQM0 = 10, DQM1 = 18
6703 14:47:18.171501 DQ Delay:
6704 14:47:18.175194 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6705 14:47:18.178174 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6706 14:47:18.181087 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6707 14:47:18.184689 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6708 14:47:18.184790
6709 14:47:18.184949
6710 14:47:18.185036 ==
6711 14:47:18.188177 Dram Type= 6, Freq= 0, CH_1, rank 1
6712 14:47:18.191077 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6713 14:47:18.191178 ==
6714 14:47:18.191267
6715 14:47:18.191354
6716 14:47:18.194383 TX Vref Scan disable
6717 14:47:18.194458 == TX Byte 0 ==
6718 14:47:18.201025 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6719 14:47:18.204472 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6720 14:47:18.204579 == TX Byte 1 ==
6721 14:47:18.211002 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6722 14:47:18.214481 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6723 14:47:18.214564 ==
6724 14:47:18.217606 Dram Type= 6, Freq= 0, CH_1, rank 1
6725 14:47:18.221039 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6726 14:47:18.221122 ==
6727 14:47:18.221205
6728 14:47:18.221327
6729 14:47:18.224308 TX Vref Scan disable
6730 14:47:18.224391 == TX Byte 0 ==
6731 14:47:18.230666 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6732 14:47:18.234162 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6733 14:47:18.234245 == TX Byte 1 ==
6734 14:47:18.240804 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6735 14:47:18.244218 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6736 14:47:18.244301
6737 14:47:18.244414 [DATLAT]
6738 14:47:18.247319 Freq=400, CH1 RK1
6739 14:47:18.247402
6740 14:47:18.247486 DATLAT Default: 0xd
6741 14:47:18.250729 0, 0xFFFF, sum = 0
6742 14:47:18.250814 1, 0xFFFF, sum = 0
6743 14:47:18.254014 2, 0xFFFF, sum = 0
6744 14:47:18.254098 3, 0xFFFF, sum = 0
6745 14:47:18.257259 4, 0xFFFF, sum = 0
6746 14:47:18.257378 5, 0xFFFF, sum = 0
6747 14:47:18.260662 6, 0xFFFF, sum = 0
6748 14:47:18.260788 7, 0xFFFF, sum = 0
6749 14:47:18.263737 8, 0xFFFF, sum = 0
6750 14:47:18.263821 9, 0xFFFF, sum = 0
6751 14:47:18.267151 10, 0xFFFF, sum = 0
6752 14:47:18.270555 11, 0xFFFF, sum = 0
6753 14:47:18.270639 12, 0x0, sum = 1
6754 14:47:18.270760 13, 0x0, sum = 2
6755 14:47:18.273885 14, 0x0, sum = 3
6756 14:47:18.273969 15, 0x0, sum = 4
6757 14:47:18.277123 best_step = 13
6758 14:47:18.277230
6759 14:47:18.277361 ==
6760 14:47:18.280522 Dram Type= 6, Freq= 0, CH_1, rank 1
6761 14:47:18.283542 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6762 14:47:18.283626 ==
6763 14:47:18.286958 RX Vref Scan: 0
6764 14:47:18.287044
6765 14:47:18.287128 RX Vref 0 -> 0, step: 1
6766 14:47:18.287207
6767 14:47:18.290276 RX Delay -359 -> 252, step: 8
6768 14:47:18.298554 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6769 14:47:18.301786 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6770 14:47:18.305236 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6771 14:47:18.308644 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6772 14:47:18.315467 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6773 14:47:18.321978 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6774 14:47:18.322062 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6775 14:47:18.325170 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6776 14:47:18.332000 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6777 14:47:18.335337 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6778 14:47:18.338734 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6779 14:47:18.345282 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6780 14:47:18.348425 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6781 14:47:18.351926 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6782 14:47:18.355307 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6783 14:47:18.362020 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6784 14:47:18.362103 ==
6785 14:47:18.365100 Dram Type= 6, Freq= 0, CH_1, rank 1
6786 14:47:18.368430 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6787 14:47:18.368538 ==
6788 14:47:18.368638 DQS Delay:
6789 14:47:18.371885 DQS0 = 48, DQS1 = 64
6790 14:47:18.371968 DQM Delay:
6791 14:47:18.375369 DQM0 = 9, DQM1 = 15
6792 14:47:18.375452 DQ Delay:
6793 14:47:18.378188 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6794 14:47:18.382139 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6795 14:47:18.385081 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6796 14:47:18.388316 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6797 14:47:18.388399
6798 14:47:18.388498
6799 14:47:18.394863 [DQSOSCAuto] RK1, (LSB)MR18= 0xa3a3, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6800 14:47:18.398389 CH1 RK1: MR19=C0C, MR18=A3A3
6801 14:47:18.404702 CH1_RK1: MR19=0xC0C, MR18=0xA3A3, DQSOSC=389, MR23=63, INC=390, DEC=260
6802 14:47:18.408323 [RxdqsGatingPostProcess] freq 400
6803 14:47:18.414794 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6804 14:47:18.414899 Pre-setting of DQS Precalculation
6805 14:47:18.421623 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6806 14:47:18.428554 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6807 14:47:18.434540 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6808 14:47:18.434625
6809 14:47:18.434708
6810 14:47:18.437761 [Calibration Summary] 800 Mbps
6811 14:47:18.441551 CH 0, Rank 0
6812 14:47:18.441658 SW Impedance : PASS
6813 14:47:18.444514 DUTY Scan : NO K
6814 14:47:18.447667 ZQ Calibration : PASS
6815 14:47:18.447750 Jitter Meter : NO K
6816 14:47:18.451140 CBT Training : PASS
6817 14:47:18.454580 Write leveling : PASS
6818 14:47:18.454663 RX DQS gating : PASS
6819 14:47:18.458037 RX DQ/DQS(RDDQC) : PASS
6820 14:47:18.458119 TX DQ/DQS : PASS
6821 14:47:18.461117 RX DATLAT : PASS
6822 14:47:18.464520 RX DQ/DQS(Engine): PASS
6823 14:47:18.464602 TX OE : NO K
6824 14:47:18.467710 All Pass.
6825 14:47:18.467793
6826 14:47:18.467875 CH 0, Rank 1
6827 14:47:18.470899 SW Impedance : PASS
6828 14:47:18.470982 DUTY Scan : NO K
6829 14:47:18.474163 ZQ Calibration : PASS
6830 14:47:18.477726 Jitter Meter : NO K
6831 14:47:18.477809 CBT Training : PASS
6832 14:47:18.481217 Write leveling : NO K
6833 14:47:18.484390 RX DQS gating : PASS
6834 14:47:18.484497 RX DQ/DQS(RDDQC) : PASS
6835 14:47:18.487421 TX DQ/DQS : PASS
6836 14:47:18.490609 RX DATLAT : PASS
6837 14:47:18.490691 RX DQ/DQS(Engine): PASS
6838 14:47:18.494045 TX OE : NO K
6839 14:47:18.494128 All Pass.
6840 14:47:18.494211
6841 14:47:18.497400 CH 1, Rank 0
6842 14:47:18.497484 SW Impedance : PASS
6843 14:47:18.500660 DUTY Scan : NO K
6844 14:47:18.503890 ZQ Calibration : PASS
6845 14:47:18.503972 Jitter Meter : NO K
6846 14:47:18.507220 CBT Training : PASS
6847 14:47:18.510650 Write leveling : PASS
6848 14:47:18.510733 RX DQS gating : PASS
6849 14:47:18.514031 RX DQ/DQS(RDDQC) : PASS
6850 14:47:18.517534 TX DQ/DQS : PASS
6851 14:47:18.517616 RX DATLAT : PASS
6852 14:47:18.520819 RX DQ/DQS(Engine): PASS
6853 14:47:18.520917 TX OE : NO K
6854 14:47:18.523922 All Pass.
6855 14:47:18.524001
6856 14:47:18.524065 CH 1, Rank 1
6857 14:47:18.527064 SW Impedance : PASS
6858 14:47:18.527166 DUTY Scan : NO K
6859 14:47:18.530678 ZQ Calibration : PASS
6860 14:47:18.533601 Jitter Meter : NO K
6861 14:47:18.533676 CBT Training : PASS
6862 14:47:18.537178 Write leveling : NO K
6863 14:47:18.540381 RX DQS gating : PASS
6864 14:47:18.540457 RX DQ/DQS(RDDQC) : PASS
6865 14:47:18.543709 TX DQ/DQS : PASS
6866 14:47:18.546909 RX DATLAT : PASS
6867 14:47:18.546997 RX DQ/DQS(Engine): PASS
6868 14:47:18.550564 TX OE : NO K
6869 14:47:18.550664 All Pass.
6870 14:47:18.550752
6871 14:47:18.553582 DramC Write-DBI off
6872 14:47:18.556785 PER_BANK_REFRESH: Hybrid Mode
6873 14:47:18.556881 TX_TRACKING: ON
6874 14:47:18.566614 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6875 14:47:18.570028 [FAST_K] Save calibration result to emmc
6876 14:47:18.573536 dramc_set_vcore_voltage set vcore to 725000
6877 14:47:18.576901 Read voltage for 1600, 0
6878 14:47:18.577001 Vio18 = 0
6879 14:47:18.577091 Vcore = 725000
6880 14:47:18.580057 Vdram = 0
6881 14:47:18.580152 Vddq = 0
6882 14:47:18.580241 Vmddr = 0
6883 14:47:18.586885 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6884 14:47:18.589880 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6885 14:47:18.592917 MEM_TYPE=3, freq_sel=13
6886 14:47:18.596582 sv_algorithm_assistance_LP4_3733
6887 14:47:18.599534 ============ PULL DRAM RESETB DOWN ============
6888 14:47:18.606176 ========== PULL DRAM RESETB DOWN end =========
6889 14:47:18.609801 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6890 14:47:18.613022 ===================================
6891 14:47:18.616621 LPDDR4 DRAM CONFIGURATION
6892 14:47:18.619965 ===================================
6893 14:47:18.620038 EX_ROW_EN[0] = 0x0
6894 14:47:18.622958 EX_ROW_EN[1] = 0x0
6895 14:47:18.623057 LP4Y_EN = 0x0
6896 14:47:18.626036 WORK_FSP = 0x1
6897 14:47:18.626133 WL = 0x5
6898 14:47:18.629635 RL = 0x5
6899 14:47:18.629708 BL = 0x2
6900 14:47:18.632847 RPST = 0x0
6901 14:47:18.635932 RD_PRE = 0x0
6902 14:47:18.636036 WR_PRE = 0x1
6903 14:47:18.639554 WR_PST = 0x1
6904 14:47:18.639632 DBI_WR = 0x0
6905 14:47:18.642792 DBI_RD = 0x0
6906 14:47:18.642868 OTF = 0x1
6907 14:47:18.645870 ===================================
6908 14:47:18.649409 ===================================
6909 14:47:18.652634 ANA top config
6910 14:47:18.655928 ===================================
6911 14:47:18.656029 DLL_ASYNC_EN = 0
6912 14:47:18.659519 ALL_SLAVE_EN = 0
6913 14:47:18.662563 NEW_RANK_MODE = 1
6914 14:47:18.665758 DLL_IDLE_MODE = 1
6915 14:47:18.665860 LP45_APHY_COMB_EN = 1
6916 14:47:18.669039 TX_ODT_DIS = 0
6917 14:47:18.672609 NEW_8X_MODE = 1
6918 14:47:18.675743 ===================================
6919 14:47:18.679114 ===================================
6920 14:47:18.682516 data_rate = 3200
6921 14:47:18.685712 CKR = 1
6922 14:47:18.689188 DQ_P2S_RATIO = 8
6923 14:47:18.692165 ===================================
6924 14:47:18.692266 CA_P2S_RATIO = 8
6925 14:47:18.695457 DQ_CA_OPEN = 0
6926 14:47:18.698828 DQ_SEMI_OPEN = 0
6927 14:47:18.702163 CA_SEMI_OPEN = 0
6928 14:47:18.705816 CA_FULL_RATE = 0
6929 14:47:18.708747 DQ_CKDIV4_EN = 0
6930 14:47:18.708831 CA_CKDIV4_EN = 0
6931 14:47:18.711984 CA_PREDIV_EN = 0
6932 14:47:18.715209 PH8_DLY = 12
6933 14:47:18.718893 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6934 14:47:18.721924 DQ_AAMCK_DIV = 4
6935 14:47:18.725571 CA_AAMCK_DIV = 4
6936 14:47:18.725655 CA_ADMCK_DIV = 4
6937 14:47:18.728637 DQ_TRACK_CA_EN = 0
6938 14:47:18.731863 CA_PICK = 1600
6939 14:47:18.735042 CA_MCKIO = 1600
6940 14:47:18.738564 MCKIO_SEMI = 0
6941 14:47:18.741841 PLL_FREQ = 3068
6942 14:47:18.745204 DQ_UI_PI_RATIO = 32
6943 14:47:18.748461 CA_UI_PI_RATIO = 0
6944 14:47:18.752016 ===================================
6945 14:47:18.755067 ===================================
6946 14:47:18.755150 memory_type:LPDDR4
6947 14:47:18.758266 GP_NUM : 10
6948 14:47:18.758349 SRAM_EN : 1
6949 14:47:18.761665 MD32_EN : 0
6950 14:47:18.765054 ===================================
6951 14:47:18.768209 [ANA_INIT] >>>>>>>>>>>>>>
6952 14:47:18.771435 <<<<<< [CONFIGURE PHASE]: ANA_TX
6953 14:47:18.775145 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6954 14:47:18.778255 ===================================
6955 14:47:18.781470 data_rate = 3200,PCW = 0X7600
6956 14:47:18.784748 ===================================
6957 14:47:18.787981 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6958 14:47:18.791238 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6959 14:47:18.797844 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6960 14:47:18.801455 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6961 14:47:18.804659 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6962 14:47:18.807897 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6963 14:47:18.811060 [ANA_INIT] flow start
6964 14:47:18.814477 [ANA_INIT] PLL >>>>>>>>
6965 14:47:18.814561 [ANA_INIT] PLL <<<<<<<<
6966 14:47:18.817791 [ANA_INIT] MIDPI >>>>>>>>
6967 14:47:18.820939 [ANA_INIT] MIDPI <<<<<<<<
6968 14:47:18.824223 [ANA_INIT] DLL >>>>>>>>
6969 14:47:18.824306 [ANA_INIT] DLL <<<<<<<<
6970 14:47:18.827619 [ANA_INIT] flow end
6971 14:47:18.831054 ============ LP4 DIFF to SE enter ============
6972 14:47:18.834312 ============ LP4 DIFF to SE exit ============
6973 14:47:18.837499 [ANA_INIT] <<<<<<<<<<<<<
6974 14:47:18.840808 [Flow] Enable top DCM control >>>>>
6975 14:47:18.844130 [Flow] Enable top DCM control <<<<<
6976 14:47:18.847335 Enable DLL master slave shuffle
6977 14:47:18.854026 ==============================================================
6978 14:47:18.854107 Gating Mode config
6979 14:47:18.860765 ==============================================================
6980 14:47:18.860846 Config description:
6981 14:47:18.870449 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6982 14:47:18.877111 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6983 14:47:18.883973 SELPH_MODE 0: By rank 1: By Phase
6984 14:47:18.887174 ==============================================================
6985 14:47:18.890331 GAT_TRACK_EN = 1
6986 14:47:18.894126 RX_GATING_MODE = 2
6987 14:47:18.897309 RX_GATING_TRACK_MODE = 2
6988 14:47:18.900263 SELPH_MODE = 1
6989 14:47:18.903551 PICG_EARLY_EN = 1
6990 14:47:18.906948 VALID_LAT_VALUE = 1
6991 14:47:18.914019 ==============================================================
6992 14:47:18.916722 Enter into Gating configuration >>>>
6993 14:47:18.920593 Exit from Gating configuration <<<<
6994 14:47:18.920677 Enter into DVFS_PRE_config >>>>>
6995 14:47:18.933538 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6996 14:47:18.936960 Exit from DVFS_PRE_config <<<<<
6997 14:47:18.940038 Enter into PICG configuration >>>>
6998 14:47:18.943446 Exit from PICG configuration <<<<
6999 14:47:18.943561 [RX_INPUT] configuration >>>>>
7000 14:47:18.946693 [RX_INPUT] configuration <<<<<
7001 14:47:18.953574 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7002 14:47:18.960243 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7003 14:47:18.963271 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7004 14:47:18.969755 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7005 14:47:18.976408 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7006 14:47:18.982828 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7007 14:47:18.986425 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7008 14:47:18.989488 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7009 14:47:18.996165 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7010 14:47:18.999423 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7011 14:47:19.002901 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7012 14:47:19.009320 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7013 14:47:19.012896 ===================================
7014 14:47:19.012979 LPDDR4 DRAM CONFIGURATION
7015 14:47:19.016032 ===================================
7016 14:47:19.019284 EX_ROW_EN[0] = 0x0
7017 14:47:19.019367 EX_ROW_EN[1] = 0x0
7018 14:47:19.022550 LP4Y_EN = 0x0
7019 14:47:19.022633 WORK_FSP = 0x1
7020 14:47:19.026110 WL = 0x5
7021 14:47:19.029240 RL = 0x5
7022 14:47:19.029329 BL = 0x2
7023 14:47:19.032349 RPST = 0x0
7024 14:47:19.032432 RD_PRE = 0x0
7025 14:47:19.035756 WR_PRE = 0x1
7026 14:47:19.035839 WR_PST = 0x1
7027 14:47:19.039236 DBI_WR = 0x0
7028 14:47:19.039319 DBI_RD = 0x0
7029 14:47:19.042200 OTF = 0x1
7030 14:47:19.045715 ===================================
7031 14:47:19.049129 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7032 14:47:19.052197 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7033 14:47:19.059201 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7034 14:47:19.062335 ===================================
7035 14:47:19.062419 LPDDR4 DRAM CONFIGURATION
7036 14:47:19.066112 ===================================
7037 14:47:19.069071 EX_ROW_EN[0] = 0x10
7038 14:47:19.069154 EX_ROW_EN[1] = 0x0
7039 14:47:19.072635 LP4Y_EN = 0x0
7040 14:47:19.072718 WORK_FSP = 0x1
7041 14:47:19.075538 WL = 0x5
7042 14:47:19.075643 RL = 0x5
7043 14:47:19.079105 BL = 0x2
7044 14:47:19.082162 RPST = 0x0
7045 14:47:19.082261 RD_PRE = 0x0
7046 14:47:19.085418 WR_PRE = 0x1
7047 14:47:19.085490 WR_PST = 0x1
7048 14:47:19.088809 DBI_WR = 0x0
7049 14:47:19.088907 DBI_RD = 0x0
7050 14:47:19.092016 OTF = 0x1
7051 14:47:19.095452 ===================================
7052 14:47:19.098632 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7053 14:47:19.102242 ==
7054 14:47:19.105742 Dram Type= 6, Freq= 0, CH_0, rank 0
7055 14:47:19.108750 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7056 14:47:19.108848 ==
7057 14:47:19.112304 [Duty_Offset_Calibration]
7058 14:47:19.112404 B0:0 B1:2 CA:1
7059 14:47:19.112492
7060 14:47:19.115431 [DutyScan_Calibration_Flow] k_type=0
7061 14:47:19.125416
7062 14:47:19.125494 ==CLK 0==
7063 14:47:19.128734 Final CLK duty delay cell = 0
7064 14:47:19.132068 [0] MAX Duty = 5187%(X100), DQS PI = 24
7065 14:47:19.135394 [0] MIN Duty = 4938%(X100), DQS PI = 54
7066 14:47:19.138610 [0] AVG Duty = 5062%(X100)
7067 14:47:19.138711
7068 14:47:19.142166 CH0 CLK Duty spec in!! Max-Min= 249%
7069 14:47:19.145149 [DutyScan_Calibration_Flow] ====Done====
7070 14:47:19.145245
7071 14:47:19.148355 [DutyScan_Calibration_Flow] k_type=1
7072 14:47:19.165491
7073 14:47:19.165567 ==DQS 0 ==
7074 14:47:19.168528 Final DQS duty delay cell = 0
7075 14:47:19.171938 [0] MAX Duty = 5156%(X100), DQS PI = 34
7076 14:47:19.175322 [0] MIN Duty = 5000%(X100), DQS PI = 8
7077 14:47:19.178703 [0] AVG Duty = 5078%(X100)
7078 14:47:19.178804
7079 14:47:19.178893 ==DQS 1 ==
7080 14:47:19.182083 Final DQS duty delay cell = 0
7081 14:47:19.185239 [0] MAX Duty = 5031%(X100), DQS PI = 6
7082 14:47:19.188660 [0] MIN Duty = 4876%(X100), DQS PI = 18
7083 14:47:19.191763 [0] AVG Duty = 4953%(X100)
7084 14:47:19.191846
7085 14:47:19.195174 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7086 14:47:19.195257
7087 14:47:19.198495 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7088 14:47:19.201811 [DutyScan_Calibration_Flow] ====Done====
7089 14:47:19.201894
7090 14:47:19.205050 [DutyScan_Calibration_Flow] k_type=3
7091 14:47:19.222769
7092 14:47:19.222852 ==DQM 0 ==
7093 14:47:19.225810 Final DQM duty delay cell = 0
7094 14:47:19.229247 [0] MAX Duty = 5187%(X100), DQS PI = 22
7095 14:47:19.232265 [0] MIN Duty = 4907%(X100), DQS PI = 42
7096 14:47:19.235661 [0] AVG Duty = 5047%(X100)
7097 14:47:19.235743
7098 14:47:19.235827 ==DQM 1 ==
7099 14:47:19.239321 Final DQM duty delay cell = 0
7100 14:47:19.242195 [0] MAX Duty = 5031%(X100), DQS PI = 50
7101 14:47:19.245920 [0] MIN Duty = 4782%(X100), DQS PI = 16
7102 14:47:19.248830 [0] AVG Duty = 4906%(X100)
7103 14:47:19.248912
7104 14:47:19.252481 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7105 14:47:19.252564
7106 14:47:19.255512 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7107 14:47:19.258714 [DutyScan_Calibration_Flow] ====Done====
7108 14:47:19.258797
7109 14:47:19.262044 [DutyScan_Calibration_Flow] k_type=2
7110 14:47:19.278830
7111 14:47:19.278914 ==DQ 0 ==
7112 14:47:19.282293 Final DQ duty delay cell = 0
7113 14:47:19.285468 [0] MAX Duty = 5218%(X100), DQS PI = 18
7114 14:47:19.288634 [0] MIN Duty = 4938%(X100), DQS PI = 54
7115 14:47:19.291982 [0] AVG Duty = 5078%(X100)
7116 14:47:19.292064
7117 14:47:19.292147 ==DQ 1 ==
7118 14:47:19.295251 Final DQ duty delay cell = -4
7119 14:47:19.298931 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7120 14:47:19.301735 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7121 14:47:19.305461 [-4] AVG Duty = 4953%(X100)
7122 14:47:19.305545
7123 14:47:19.308580 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7124 14:47:19.308663
7125 14:47:19.312138 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7126 14:47:19.315069 [DutyScan_Calibration_Flow] ====Done====
7127 14:47:19.315152 ==
7128 14:47:19.318351 Dram Type= 6, Freq= 0, CH_1, rank 0
7129 14:47:19.321882 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7130 14:47:19.321968 ==
7131 14:47:19.324994 [Duty_Offset_Calibration]
7132 14:47:19.325077 B0:0 B1:4 CA:-5
7133 14:47:19.325175
7134 14:47:19.328197 [DutyScan_Calibration_Flow] k_type=0
7135 14:47:19.339391
7136 14:47:19.339473 ==CLK 0==
7137 14:47:19.342715 Final CLK duty delay cell = 0
7138 14:47:19.346404 [0] MAX Duty = 5156%(X100), DQS PI = 20
7139 14:47:19.349551 [0] MIN Duty = 4906%(X100), DQS PI = 50
7140 14:47:19.352696 [0] AVG Duty = 5031%(X100)
7141 14:47:19.352779
7142 14:47:19.355990 CH1 CLK Duty spec in!! Max-Min= 250%
7143 14:47:19.359338 [DutyScan_Calibration_Flow] ====Done====
7144 14:47:19.359421
7145 14:47:19.362818 [DutyScan_Calibration_Flow] k_type=1
7146 14:47:19.378565
7147 14:47:19.378649 ==DQS 0 ==
7148 14:47:19.381899 Final DQS duty delay cell = 0
7149 14:47:19.384939 [0] MAX Duty = 5187%(X100), DQS PI = 20
7150 14:47:19.388321 [0] MIN Duty = 4876%(X100), DQS PI = 44
7151 14:47:19.391848 [0] AVG Duty = 5031%(X100)
7152 14:47:19.391948
7153 14:47:19.392031 ==DQS 1 ==
7154 14:47:19.394878 Final DQS duty delay cell = -4
7155 14:47:19.398361 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7156 14:47:19.401562 [-4] MIN Duty = 4875%(X100), DQS PI = 38
7157 14:47:19.404651 [-4] AVG Duty = 4937%(X100)
7158 14:47:19.404735
7159 14:47:19.408159 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7160 14:47:19.408242
7161 14:47:19.411415 CH1 DQS 1 Duty spec in!! Max-Min= 125%
7162 14:47:19.414876 [DutyScan_Calibration_Flow] ====Done====
7163 14:47:19.414959
7164 14:47:19.418071 [DutyScan_Calibration_Flow] k_type=3
7165 14:47:19.434066
7166 14:47:19.434149 ==DQM 0 ==
7167 14:47:19.437117 Final DQM duty delay cell = -4
7168 14:47:19.440705 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7169 14:47:19.444257 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7170 14:47:19.447440 [-4] AVG Duty = 4922%(X100)
7171 14:47:19.447523
7172 14:47:19.447606 ==DQM 1 ==
7173 14:47:19.450868 Final DQM duty delay cell = -4
7174 14:47:19.454140 [-4] MAX Duty = 5093%(X100), DQS PI = 16
7175 14:47:19.457211 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7176 14:47:19.460760 [-4] AVG Duty = 5000%(X100)
7177 14:47:19.460843
7178 14:47:19.464055 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7179 14:47:19.464138
7180 14:47:19.467677 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7181 14:47:19.470657 [DutyScan_Calibration_Flow] ====Done====
7182 14:47:19.470741
7183 14:47:19.473786 [DutyScan_Calibration_Flow] k_type=2
7184 14:47:19.491662
7185 14:47:19.491745 ==DQ 0 ==
7186 14:47:19.494928 Final DQ duty delay cell = 0
7187 14:47:19.498144 [0] MAX Duty = 5093%(X100), DQS PI = 18
7188 14:47:19.501649 [0] MIN Duty = 4938%(X100), DQS PI = 46
7189 14:47:19.501731 [0] AVG Duty = 5015%(X100)
7190 14:47:19.504958
7191 14:47:19.505040 ==DQ 1 ==
7192 14:47:19.508365 Final DQ duty delay cell = 0
7193 14:47:19.511597 [0] MAX Duty = 5031%(X100), DQS PI = 4
7194 14:47:19.514614 [0] MIN Duty = 4876%(X100), DQS PI = 28
7195 14:47:19.514697 [0] AVG Duty = 4953%(X100)
7196 14:47:19.517970
7197 14:47:19.521226 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7198 14:47:19.521369
7199 14:47:19.524774 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7200 14:47:19.527892 [DutyScan_Calibration_Flow] ====Done====
7201 14:47:19.531325 nWR fixed to 30
7202 14:47:19.531435 [ModeRegInit_LP4] CH0 RK0
7203 14:47:19.534461 [ModeRegInit_LP4] CH0 RK1
7204 14:47:19.538195 [ModeRegInit_LP4] CH1 RK0
7205 14:47:19.541435 [ModeRegInit_LP4] CH1 RK1
7206 14:47:19.541518 match AC timing 4
7207 14:47:19.547635 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7208 14:47:19.551165 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7209 14:47:19.554519 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7210 14:47:19.561188 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7211 14:47:19.564539 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7212 14:47:19.564623 [MiockJmeterHQA]
7213 14:47:19.564706
7214 14:47:19.567745 [DramcMiockJmeter] u1RxGatingPI = 0
7215 14:47:19.570846 0 : 4363, 4138
7216 14:47:19.570932 4 : 4257, 4030
7217 14:47:19.574396 8 : 4253, 4026
7218 14:47:19.574481 12 : 4253, 4027
7219 14:47:19.574566 16 : 4253, 4026
7220 14:47:19.577437 20 : 4362, 4137
7221 14:47:19.577521 24 : 4252, 4026
7222 14:47:19.580747 28 : 4366, 4140
7223 14:47:19.580831 32 : 4363, 4137
7224 14:47:19.584272 36 : 4250, 4025
7225 14:47:19.584357 40 : 4253, 4027
7226 14:47:19.587318 44 : 4253, 4027
7227 14:47:19.587402 48 : 4252, 4026
7228 14:47:19.587486 52 : 4253, 4027
7229 14:47:19.590884 56 : 4252, 4027
7230 14:47:19.590968 60 : 4252, 4027
7231 14:47:19.594307 64 : 4253, 4026
7232 14:47:19.594391 68 : 4252, 4027
7233 14:47:19.597488 72 : 4255, 4030
7234 14:47:19.597572 76 : 4252, 4027
7235 14:47:19.600839 80 : 4252, 4027
7236 14:47:19.600922 84 : 4249, 4027
7237 14:47:19.601007 88 : 4258, 4031
7238 14:47:19.604268 92 : 4253, 4029
7239 14:47:19.604377 96 : 4250, 4026
7240 14:47:19.607247 100 : 4253, 1628
7241 14:47:19.607350 104 : 4360, 0
7242 14:47:19.610505 108 : 4253, 0
7243 14:47:19.610607 112 : 4250, 0
7244 14:47:19.610701 116 : 4250, 0
7245 14:47:19.613978 120 : 4258, 0
7246 14:47:19.614052 124 : 4255, 0
7247 14:47:19.617246 128 : 4250, 0
7248 14:47:19.617376 132 : 4360, 0
7249 14:47:19.617440 136 : 4250, 0
7250 14:47:19.620793 140 : 4250, 0
7251 14:47:19.620895 144 : 4360, 0
7252 14:47:19.620987 148 : 4250, 0
7253 14:47:19.623855 152 : 4360, 0
7254 14:47:19.623966 156 : 4250, 0
7255 14:47:19.627015 160 : 4250, 0
7256 14:47:19.627099 164 : 4361, 0
7257 14:47:19.627183 168 : 4249, 0
7258 14:47:19.630880 172 : 4250, 0
7259 14:47:19.630965 176 : 4252, 0
7260 14:47:19.633830 180 : 4249, 0
7261 14:47:19.633914 184 : 4365, 0
7262 14:47:19.633998 188 : 4250, 0
7263 14:47:19.637214 192 : 4252, 0
7264 14:47:19.637334 196 : 4249, 0
7265 14:47:19.640313 200 : 4255, 0
7266 14:47:19.640397 204 : 4250, 0
7267 14:47:19.640481 208 : 4361, 0
7268 14:47:19.643617 212 : 4253, 0
7269 14:47:19.643700 216 : 4250, 0
7270 14:47:19.647182 220 : 4360, 818
7271 14:47:19.647266 224 : 4250, 4008
7272 14:47:19.647352 228 : 4250, 4026
7273 14:47:19.650372 232 : 4250, 4027
7274 14:47:19.650456 236 : 4249, 4027
7275 14:47:19.653814 240 : 4250, 4027
7276 14:47:19.653899 244 : 4253, 4029
7277 14:47:19.657014 248 : 4250, 4027
7278 14:47:19.657098 252 : 4360, 4138
7279 14:47:19.660475 256 : 4365, 4139
7280 14:47:19.660559 260 : 4248, 4024
7281 14:47:19.663570 264 : 4250, 4027
7282 14:47:19.663653 268 : 4252, 4030
7283 14:47:19.666911 272 : 4250, 4026
7284 14:47:19.666994 276 : 4250, 4026
7285 14:47:19.670233 280 : 4250, 4027
7286 14:47:19.670318 284 : 4360, 4138
7287 14:47:19.670402 288 : 4360, 4137
7288 14:47:19.673424 292 : 4250, 4027
7289 14:47:19.673508 296 : 4250, 4027
7290 14:47:19.677325 300 : 4360, 4138
7291 14:47:19.677409 304 : 4363, 4139
7292 14:47:19.680164 308 : 4250, 4026
7293 14:47:19.680248 312 : 4253, 4029
7294 14:47:19.683286 316 : 4363, 4140
7295 14:47:19.683371 320 : 4250, 4027
7296 14:47:19.686984 324 : 4254, 4029
7297 14:47:19.687068 328 : 4250, 4027
7298 14:47:19.690264 332 : 4253, 4029
7299 14:47:19.690348 336 : 4360, 3807
7300 14:47:19.693435 340 : 4360, 1881
7301 14:47:19.693519
7302 14:47:19.693602 MIOCK jitter meter ch=0
7303 14:47:19.693680
7304 14:47:19.696638 1T = (340-100) = 240 dly cells
7305 14:47:19.703273 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7306 14:47:19.703357 ==
7307 14:47:19.706584 Dram Type= 6, Freq= 0, CH_0, rank 0
7308 14:47:19.709833 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7309 14:47:19.709917 ==
7310 14:47:19.716590 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7311 14:47:19.719678 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7312 14:47:19.723456 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7313 14:47:19.729688 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7314 14:47:19.738873 [CA 0] Center 41 (11~72) winsize 62
7315 14:47:19.742848 [CA 1] Center 41 (11~72) winsize 62
7316 14:47:19.745314 [CA 2] Center 37 (7~68) winsize 62
7317 14:47:19.749192 [CA 3] Center 37 (7~67) winsize 61
7318 14:47:19.752118 [CA 4] Center 35 (5~66) winsize 62
7319 14:47:19.755597 [CA 5] Center 35 (5~65) winsize 61
7320 14:47:19.755680
7321 14:47:19.758669 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7322 14:47:19.758752
7323 14:47:19.762049 [CATrainingPosCal] consider 1 rank data
7324 14:47:19.765581 u2DelayCellTimex100 = 271/100 ps
7325 14:47:19.768872 CA0 delay=41 (11~72),Diff = 6 PI (21 cell)
7326 14:47:19.775205 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7327 14:47:19.778765 CA2 delay=37 (7~68),Diff = 2 PI (7 cell)
7328 14:47:19.782180 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7329 14:47:19.785161 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7330 14:47:19.788473 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7331 14:47:19.788555
7332 14:47:19.791680 CA PerBit enable=1, Macro0, CA PI delay=35
7333 14:47:19.791763
7334 14:47:19.795296 [CBTSetCACLKResult] CA Dly = 35
7335 14:47:19.798323 CS Dly: 11 (0~42)
7336 14:47:19.801758 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7337 14:47:19.804968 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7338 14:47:19.805051 ==
7339 14:47:19.808417 Dram Type= 6, Freq= 0, CH_0, rank 1
7340 14:47:19.811547 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7341 14:47:19.814890 ==
7342 14:47:19.818466 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7343 14:47:19.821612 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7344 14:47:19.828500 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7345 14:47:19.834613 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7346 14:47:19.841494 [CA 0] Center 42 (12~73) winsize 62
7347 14:47:19.845074 [CA 1] Center 42 (12~73) winsize 62
7348 14:47:19.848157 [CA 2] Center 38 (9~68) winsize 60
7349 14:47:19.851333 [CA 3] Center 38 (8~68) winsize 61
7350 14:47:19.854742 [CA 4] Center 36 (6~66) winsize 61
7351 14:47:19.858151 [CA 5] Center 36 (6~66) winsize 61
7352 14:47:19.858234
7353 14:47:19.861348 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7354 14:47:19.861431
7355 14:47:19.864436 [CATrainingPosCal] consider 2 rank data
7356 14:47:19.868008 u2DelayCellTimex100 = 271/100 ps
7357 14:47:19.871421 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7358 14:47:19.877903 CA1 delay=42 (12~72),Diff = 7 PI (25 cell)
7359 14:47:19.881007 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7360 14:47:19.884472 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7361 14:47:19.887889 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7362 14:47:19.891421 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7363 14:47:19.891500
7364 14:47:19.894323 CA PerBit enable=1, Macro0, CA PI delay=35
7365 14:47:19.894403
7366 14:47:19.898011 [CBTSetCACLKResult] CA Dly = 35
7367 14:47:19.901044 CS Dly: 11 (0~42)
7368 14:47:19.904189 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7369 14:47:19.907605 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7370 14:47:19.907686
7371 14:47:19.910941 ----->DramcWriteLeveling(PI) begin...
7372 14:47:19.911023 ==
7373 14:47:19.914631 Dram Type= 6, Freq= 0, CH_0, rank 0
7374 14:47:19.920707 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7375 14:47:19.920788 ==
7376 14:47:19.924032 Write leveling (Byte 0): 28 => 28
7377 14:47:19.927344 Write leveling (Byte 1): 25 => 25
7378 14:47:19.927424 DramcWriteLeveling(PI) end<-----
7379 14:47:19.927487
7380 14:47:19.930770 ==
7381 14:47:19.934039 Dram Type= 6, Freq= 0, CH_0, rank 0
7382 14:47:19.937310 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7383 14:47:19.937390 ==
7384 14:47:19.940765 [Gating] SW mode calibration
7385 14:47:19.947322 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7386 14:47:19.950638 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7387 14:47:19.957453 0 12 0 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
7388 14:47:19.960547 0 12 4 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7389 14:47:19.963971 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7390 14:47:19.970376 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7391 14:47:19.973565 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7392 14:47:19.977070 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7393 14:47:19.983688 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7394 14:47:19.986834 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7395 14:47:19.990132 0 13 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7396 14:47:19.997231 0 13 4 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
7397 14:47:20.000194 0 13 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7398 14:47:20.003332 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7399 14:47:20.010577 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7400 14:47:20.013322 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7401 14:47:20.016633 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7402 14:47:20.023240 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7403 14:47:20.026900 0 14 0 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
7404 14:47:20.030023 0 14 4 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
7405 14:47:20.036382 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7406 14:47:20.039778 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7407 14:47:20.043333 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7408 14:47:20.050169 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7409 14:47:20.053000 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7410 14:47:20.056488 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7411 14:47:20.062771 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7412 14:47:20.066467 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7413 14:47:20.069470 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7414 14:47:20.076059 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7415 14:47:20.079635 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7416 14:47:20.082924 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7417 14:47:20.089477 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7418 14:47:20.092573 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7419 14:47:20.095925 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7420 14:47:20.102627 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7421 14:47:20.105740 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7422 14:47:20.109423 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7423 14:47:20.115595 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7424 14:47:20.118852 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7425 14:47:20.122128 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7426 14:47:20.129073 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7427 14:47:20.132222 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7428 14:47:20.135484 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7429 14:47:20.138691 Total UI for P1: 0, mck2ui 16
7430 14:47:20.141946 best dqsien dly found for B0: ( 1, 1, 0)
7431 14:47:20.148840 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7432 14:47:20.148923 Total UI for P1: 0, mck2ui 16
7433 14:47:20.155392 best dqsien dly found for B1: ( 1, 1, 4)
7434 14:47:20.158607 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7435 14:47:20.162436 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7436 14:47:20.162518
7437 14:47:20.165502 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7438 14:47:20.168514 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7439 14:47:20.171916 [Gating] SW calibration Done
7440 14:47:20.172000 ==
7441 14:47:20.175078 Dram Type= 6, Freq= 0, CH_0, rank 0
7442 14:47:20.178417 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7443 14:47:20.178500 ==
7444 14:47:20.181741 RX Vref Scan: 0
7445 14:47:20.181824
7446 14:47:20.181907 RX Vref 0 -> 0, step: 1
7447 14:47:20.181985
7448 14:47:20.185037 RX Delay 0 -> 252, step: 8
7449 14:47:20.188200 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7450 14:47:20.191711 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7451 14:47:20.198430 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7452 14:47:20.201793 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7453 14:47:20.204967 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7454 14:47:20.208385 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7455 14:47:20.211547 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7456 14:47:20.218312 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7457 14:47:20.221466 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7458 14:47:20.225353 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7459 14:47:20.228107 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7460 14:47:20.231351 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7461 14:47:20.238009 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7462 14:47:20.241189 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7463 14:47:20.244617 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7464 14:47:20.247980 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7465 14:47:20.248064 ==
7466 14:47:20.251287 Dram Type= 6, Freq= 0, CH_0, rank 0
7467 14:47:20.257771 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7468 14:47:20.257854 ==
7469 14:47:20.257938 DQS Delay:
7470 14:47:20.261028 DQS0 = 0, DQS1 = 0
7471 14:47:20.261111 DQM Delay:
7472 14:47:20.264568 DQM0 = 130, DQM1 = 123
7473 14:47:20.264650 DQ Delay:
7474 14:47:20.268107 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7475 14:47:20.271101 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7476 14:47:20.274358 DQ8 =111, DQ9 =107, DQ10 =119, DQ11 =115
7477 14:47:20.277772 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7478 14:47:20.277856
7479 14:47:20.277977
7480 14:47:20.278056 ==
7481 14:47:20.281149 Dram Type= 6, Freq= 0, CH_0, rank 0
7482 14:47:20.287566 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7483 14:47:20.287650 ==
7484 14:47:20.287734
7485 14:47:20.287812
7486 14:47:20.287887 TX Vref Scan disable
7487 14:47:20.291373 == TX Byte 0 ==
7488 14:47:20.294355 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7489 14:47:20.300884 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7490 14:47:20.300968 == TX Byte 1 ==
7491 14:47:20.304413 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7492 14:47:20.311224 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7493 14:47:20.311307 ==
7494 14:47:20.314323 Dram Type= 6, Freq= 0, CH_0, rank 0
7495 14:47:20.317658 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7496 14:47:20.317742 ==
7497 14:47:20.330215
7498 14:47:20.333312 TX Vref early break, caculate TX vref
7499 14:47:20.336638 TX Vref=16, minBit 8, minWin=22, winSum=372
7500 14:47:20.340094 TX Vref=18, minBit 9, minWin=22, winSum=377
7501 14:47:20.343126 TX Vref=20, minBit 8, minWin=23, winSum=390
7502 14:47:20.346595 TX Vref=22, minBit 8, minWin=23, winSum=395
7503 14:47:20.350116 TX Vref=24, minBit 8, minWin=24, winSum=411
7504 14:47:20.356401 TX Vref=26, minBit 8, minWin=24, winSum=413
7505 14:47:20.359931 TX Vref=28, minBit 8, minWin=25, winSum=417
7506 14:47:20.363006 TX Vref=30, minBit 0, minWin=25, winSum=412
7507 14:47:20.366369 TX Vref=32, minBit 1, minWin=24, winSum=403
7508 14:47:20.369671 TX Vref=34, minBit 8, minWin=23, winSum=388
7509 14:47:20.376644 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 28
7510 14:47:20.376726
7511 14:47:20.379770 Final TX Range 0 Vref 28
7512 14:47:20.379850
7513 14:47:20.379911 ==
7514 14:47:20.382755 Dram Type= 6, Freq= 0, CH_0, rank 0
7515 14:47:20.386138 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7516 14:47:20.386218 ==
7517 14:47:20.386280
7518 14:47:20.386337
7519 14:47:20.389589 TX Vref Scan disable
7520 14:47:20.396347 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7521 14:47:20.396427 == TX Byte 0 ==
7522 14:47:20.399430 u2DelayCellOfst[0]=14 cells (4 PI)
7523 14:47:20.402564 u2DelayCellOfst[1]=18 cells (5 PI)
7524 14:47:20.406064 u2DelayCellOfst[2]=14 cells (4 PI)
7525 14:47:20.409183 u2DelayCellOfst[3]=10 cells (3 PI)
7526 14:47:20.412565 u2DelayCellOfst[4]=7 cells (2 PI)
7527 14:47:20.415629 u2DelayCellOfst[5]=0 cells (0 PI)
7528 14:47:20.419230 u2DelayCellOfst[6]=18 cells (5 PI)
7529 14:47:20.422514 u2DelayCellOfst[7]=18 cells (5 PI)
7530 14:47:20.425792 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7531 14:47:20.428974 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7532 14:47:20.432521 == TX Byte 1 ==
7533 14:47:20.435602 u2DelayCellOfst[8]=3 cells (1 PI)
7534 14:47:20.438746 u2DelayCellOfst[9]=0 cells (0 PI)
7535 14:47:20.441997 u2DelayCellOfst[10]=10 cells (3 PI)
7536 14:47:20.442077 u2DelayCellOfst[11]=7 cells (2 PI)
7537 14:47:20.445559 u2DelayCellOfst[12]=18 cells (5 PI)
7538 14:47:20.448716 u2DelayCellOfst[13]=18 cells (5 PI)
7539 14:47:20.452004 u2DelayCellOfst[14]=18 cells (5 PI)
7540 14:47:20.455252 u2DelayCellOfst[15]=14 cells (4 PI)
7541 14:47:20.461741 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7542 14:47:20.465257 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7543 14:47:20.465374 DramC Write-DBI on
7544 14:47:20.468725 ==
7545 14:47:20.468805 Dram Type= 6, Freq= 0, CH_0, rank 0
7546 14:47:20.475126 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7547 14:47:20.475206 ==
7548 14:47:20.475268
7549 14:47:20.475326
7550 14:47:20.478301 TX Vref Scan disable
7551 14:47:20.478381 == TX Byte 0 ==
7552 14:47:20.485316 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7553 14:47:20.485410 == TX Byte 1 ==
7554 14:47:20.488412 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7555 14:47:20.491581 DramC Write-DBI off
7556 14:47:20.491660
7557 14:47:20.491723 [DATLAT]
7558 14:47:20.495063 Freq=1600, CH0 RK0
7559 14:47:20.495143
7560 14:47:20.495205 DATLAT Default: 0xf
7561 14:47:20.498229 0, 0xFFFF, sum = 0
7562 14:47:20.498310 1, 0xFFFF, sum = 0
7563 14:47:20.501617 2, 0xFFFF, sum = 0
7564 14:47:20.501698 3, 0xFFFF, sum = 0
7565 14:47:20.504871 4, 0xFFFF, sum = 0
7566 14:47:20.504952 5, 0xFFFF, sum = 0
7567 14:47:20.508138 6, 0xFFFF, sum = 0
7568 14:47:20.508232 7, 0xFFFF, sum = 0
7569 14:47:20.511445 8, 0xFFFF, sum = 0
7570 14:47:20.514731 9, 0xFFFF, sum = 0
7571 14:47:20.514812 10, 0xFFFF, sum = 0
7572 14:47:20.518017 11, 0xFFFF, sum = 0
7573 14:47:20.518097 12, 0xFFF, sum = 0
7574 14:47:20.521374 13, 0x0, sum = 1
7575 14:47:20.521455 14, 0x0, sum = 2
7576 14:47:20.524665 15, 0x0, sum = 3
7577 14:47:20.524745 16, 0x0, sum = 4
7578 14:47:20.524809 best_step = 14
7579 14:47:20.528009
7580 14:47:20.528088 ==
7581 14:47:20.531647 Dram Type= 6, Freq= 0, CH_0, rank 0
7582 14:47:20.534671 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7583 14:47:20.534751 ==
7584 14:47:20.534813 RX Vref Scan: 1
7585 14:47:20.534871
7586 14:47:20.537992 Set Vref Range= 24 -> 127
7587 14:47:20.538072
7588 14:47:20.541186 RX Vref 24 -> 127, step: 1
7589 14:47:20.541266
7590 14:47:20.544479 RX Delay 11 -> 252, step: 4
7591 14:47:20.544561
7592 14:47:20.547727 Set Vref, RX VrefLevel [Byte0]: 24
7593 14:47:20.550880 [Byte1]: 24
7594 14:47:20.550963
7595 14:47:20.554386 Set Vref, RX VrefLevel [Byte0]: 25
7596 14:47:20.557702 [Byte1]: 25
7597 14:47:20.557785
7598 14:47:20.561050 Set Vref, RX VrefLevel [Byte0]: 26
7599 14:47:20.564771 [Byte1]: 26
7600 14:47:20.568020
7601 14:47:20.568103 Set Vref, RX VrefLevel [Byte0]: 27
7602 14:47:20.571197 [Byte1]: 27
7603 14:47:20.575548
7604 14:47:20.575633 Set Vref, RX VrefLevel [Byte0]: 28
7605 14:47:20.578908 [Byte1]: 28
7606 14:47:20.583913
7607 14:47:20.584002 Set Vref, RX VrefLevel [Byte0]: 29
7608 14:47:20.586399 [Byte1]: 29
7609 14:47:20.591236
7610 14:47:20.591316 Set Vref, RX VrefLevel [Byte0]: 30
7611 14:47:20.594108 [Byte1]: 30
7612 14:47:20.598398
7613 14:47:20.598477 Set Vref, RX VrefLevel [Byte0]: 31
7614 14:47:20.601828 [Byte1]: 31
7615 14:47:20.606126
7616 14:47:20.606205 Set Vref, RX VrefLevel [Byte0]: 32
7617 14:47:20.609930 [Byte1]: 32
7618 14:47:20.613787
7619 14:47:20.613867 Set Vref, RX VrefLevel [Byte0]: 33
7620 14:47:20.617183 [Byte1]: 33
7621 14:47:20.621237
7622 14:47:20.621324 Set Vref, RX VrefLevel [Byte0]: 34
7623 14:47:20.624611 [Byte1]: 34
7624 14:47:20.629036
7625 14:47:20.629115 Set Vref, RX VrefLevel [Byte0]: 35
7626 14:47:20.632167 [Byte1]: 35
7627 14:47:20.636533
7628 14:47:20.636613 Set Vref, RX VrefLevel [Byte0]: 36
7629 14:47:20.639922 [Byte1]: 36
7630 14:47:20.644251
7631 14:47:20.644332 Set Vref, RX VrefLevel [Byte0]: 37
7632 14:47:20.647468 [Byte1]: 37
7633 14:47:20.651957
7634 14:47:20.652037 Set Vref, RX VrefLevel [Byte0]: 38
7635 14:47:20.655356 [Byte1]: 38
7636 14:47:20.659376
7637 14:47:20.659470 Set Vref, RX VrefLevel [Byte0]: 39
7638 14:47:20.662481 [Byte1]: 39
7639 14:47:20.666981
7640 14:47:20.667078 Set Vref, RX VrefLevel [Byte0]: 40
7641 14:47:20.670140 [Byte1]: 40
7642 14:47:20.674965
7643 14:47:20.675050 Set Vref, RX VrefLevel [Byte0]: 41
7644 14:47:20.677847 [Byte1]: 41
7645 14:47:20.682256
7646 14:47:20.682339 Set Vref, RX VrefLevel [Byte0]: 42
7647 14:47:20.685534 [Byte1]: 42
7648 14:47:20.689665
7649 14:47:20.689748 Set Vref, RX VrefLevel [Byte0]: 43
7650 14:47:20.693128 [Byte1]: 43
7651 14:47:20.697459
7652 14:47:20.697542 Set Vref, RX VrefLevel [Byte0]: 44
7653 14:47:20.700727 [Byte1]: 44
7654 14:47:20.705091
7655 14:47:20.705170 Set Vref, RX VrefLevel [Byte0]: 45
7656 14:47:20.711699 [Byte1]: 45
7657 14:47:20.711778
7658 14:47:20.714825 Set Vref, RX VrefLevel [Byte0]: 46
7659 14:47:20.718359 [Byte1]: 46
7660 14:47:20.718439
7661 14:47:20.721374 Set Vref, RX VrefLevel [Byte0]: 47
7662 14:47:20.724732 [Byte1]: 47
7663 14:47:20.728331
7664 14:47:20.728410 Set Vref, RX VrefLevel [Byte0]: 48
7665 14:47:20.731365 [Byte1]: 48
7666 14:47:20.735583
7667 14:47:20.735662 Set Vref, RX VrefLevel [Byte0]: 49
7668 14:47:20.738811 [Byte1]: 49
7669 14:47:20.743096
7670 14:47:20.743189 Set Vref, RX VrefLevel [Byte0]: 50
7671 14:47:20.746437 [Byte1]: 50
7672 14:47:20.750785
7673 14:47:20.750865 Set Vref, RX VrefLevel [Byte0]: 51
7674 14:47:20.753813 [Byte1]: 51
7675 14:47:20.758236
7676 14:47:20.758315 Set Vref, RX VrefLevel [Byte0]: 52
7677 14:47:20.761751 [Byte1]: 52
7678 14:47:20.765909
7679 14:47:20.765989 Set Vref, RX VrefLevel [Byte0]: 53
7680 14:47:20.769378 [Byte1]: 53
7681 14:47:20.773556
7682 14:47:20.773636 Set Vref, RX VrefLevel [Byte0]: 54
7683 14:47:20.776884 [Byte1]: 54
7684 14:47:20.780941
7685 14:47:20.781021 Set Vref, RX VrefLevel [Byte0]: 55
7686 14:47:20.784556 [Byte1]: 55
7687 14:47:20.788797
7688 14:47:20.788877 Set Vref, RX VrefLevel [Byte0]: 56
7689 14:47:20.792102 [Byte1]: 56
7690 14:47:20.796389
7691 14:47:20.796468 Set Vref, RX VrefLevel [Byte0]: 57
7692 14:47:20.799523 [Byte1]: 57
7693 14:47:20.803901
7694 14:47:20.803984 Set Vref, RX VrefLevel [Byte0]: 58
7695 14:47:20.807359 [Byte1]: 58
7696 14:47:20.811633
7697 14:47:20.811716 Set Vref, RX VrefLevel [Byte0]: 59
7698 14:47:20.814914 [Byte1]: 59
7699 14:47:20.819306
7700 14:47:20.819406 Set Vref, RX VrefLevel [Byte0]: 60
7701 14:47:20.822796 [Byte1]: 60
7702 14:47:20.826665
7703 14:47:20.826748 Set Vref, RX VrefLevel [Byte0]: 61
7704 14:47:20.830387 [Byte1]: 61
7705 14:47:20.834413
7706 14:47:20.834496 Set Vref, RX VrefLevel [Byte0]: 62
7707 14:47:20.837791 [Byte1]: 62
7708 14:47:20.842272
7709 14:47:20.842354 Set Vref, RX VrefLevel [Byte0]: 63
7710 14:47:20.845230 [Byte1]: 63
7711 14:47:20.849725
7712 14:47:20.849808 Set Vref, RX VrefLevel [Byte0]: 64
7713 14:47:20.852808 [Byte1]: 64
7714 14:47:20.857218
7715 14:47:20.857326 Set Vref, RX VrefLevel [Byte0]: 65
7716 14:47:20.860697 [Byte1]: 65
7717 14:47:20.864801
7718 14:47:20.864884 Set Vref, RX VrefLevel [Byte0]: 66
7719 14:47:20.868119 [Byte1]: 66
7720 14:47:20.872476
7721 14:47:20.872558 Set Vref, RX VrefLevel [Byte0]: 67
7722 14:47:20.875722 [Byte1]: 67
7723 14:47:20.880121
7724 14:47:20.880204 Set Vref, RX VrefLevel [Byte0]: 68
7725 14:47:20.883657 [Byte1]: 68
7726 14:47:20.887961
7727 14:47:20.888044 Set Vref, RX VrefLevel [Byte0]: 69
7728 14:47:20.891002 [Byte1]: 69
7729 14:47:20.895244
7730 14:47:20.895326 Set Vref, RX VrefLevel [Byte0]: 70
7731 14:47:20.898876 [Byte1]: 70
7732 14:47:20.902871
7733 14:47:20.902954 Final RX Vref Byte 0 = 55 to rank0
7734 14:47:20.906512 Final RX Vref Byte 1 = 56 to rank0
7735 14:47:20.909641 Final RX Vref Byte 0 = 55 to rank1
7736 14:47:20.913061 Final RX Vref Byte 1 = 56 to rank1==
7737 14:47:20.916281 Dram Type= 6, Freq= 0, CH_0, rank 0
7738 14:47:20.923133 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7739 14:47:20.923217 ==
7740 14:47:20.923302 DQS Delay:
7741 14:47:20.923382 DQS0 = 0, DQS1 = 0
7742 14:47:20.926223 DQM Delay:
7743 14:47:20.926305 DQM0 = 126, DQM1 = 120
7744 14:47:20.929529 DQ Delay:
7745 14:47:20.932690 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7746 14:47:20.936137 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7747 14:47:20.939143 DQ8 =110, DQ9 =104, DQ10 =122, DQ11 =112
7748 14:47:20.942521 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7749 14:47:20.942603
7750 14:47:20.942687
7751 14:47:20.942765
7752 14:47:20.945839 [DramC_TX_OE_Calibration] TA2
7753 14:47:20.949359 Original DQ_B0 (3 6) =30, OEN = 27
7754 14:47:20.952429 Original DQ_B1 (3 6) =30, OEN = 27
7755 14:47:20.955753 24, 0x0, End_B0=24 End_B1=24
7756 14:47:20.955837 25, 0x0, End_B0=25 End_B1=25
7757 14:47:20.959024 26, 0x0, End_B0=26 End_B1=26
7758 14:47:20.962456 27, 0x0, End_B0=27 End_B1=27
7759 14:47:20.965691 28, 0x0, End_B0=28 End_B1=28
7760 14:47:20.968848 29, 0x0, End_B0=29 End_B1=29
7761 14:47:20.968932 30, 0x0, End_B0=30 End_B1=30
7762 14:47:20.972504 31, 0x4141, End_B0=30 End_B1=30
7763 14:47:20.975656 Byte0 end_step=30 best_step=27
7764 14:47:20.979085 Byte1 end_step=30 best_step=27
7765 14:47:20.982295 Byte0 TX OE(2T, 0.5T) = (3, 3)
7766 14:47:20.985314 Byte1 TX OE(2T, 0.5T) = (3, 3)
7767 14:47:20.985407
7768 14:47:20.985470
7769 14:47:20.991925 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
7770 14:47:20.995163 CH0 RK0: MR19=303, MR18=1E1E
7771 14:47:21.002074 CH0_RK0: MR19=0x303, MR18=0x1E1E, DQSOSC=394, MR23=63, INC=23, DEC=15
7772 14:47:21.002155
7773 14:47:21.005119 ----->DramcWriteLeveling(PI) begin...
7774 14:47:21.005199 ==
7775 14:47:21.008643 Dram Type= 6, Freq= 0, CH_0, rank 1
7776 14:47:21.012045 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7777 14:47:21.012125 ==
7778 14:47:21.015159 Write leveling (Byte 0): 29 => 29
7779 14:47:21.018285 Write leveling (Byte 1): 26 => 26
7780 14:47:21.021859 DramcWriteLeveling(PI) end<-----
7781 14:47:21.021938
7782 14:47:21.022000 ==
7783 14:47:21.025119 Dram Type= 6, Freq= 0, CH_0, rank 1
7784 14:47:21.028568 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7785 14:47:21.031845 ==
7786 14:47:21.031925 [Gating] SW mode calibration
7787 14:47:21.038267 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7788 14:47:21.045242 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7789 14:47:21.048164 0 12 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7790 14:47:21.054779 0 12 4 | B1->B0 | 2b2b 3434 | 0 1 | (1 1) (1 1)
7791 14:47:21.058242 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7792 14:47:21.061676 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7793 14:47:21.067844 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7794 14:47:21.071628 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7795 14:47:21.074688 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7796 14:47:21.081589 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7797 14:47:21.084547 0 13 0 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 0)
7798 14:47:21.088081 0 13 4 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
7799 14:47:21.094783 0 13 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7800 14:47:21.097962 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7801 14:47:21.101145 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7802 14:47:21.107634 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7803 14:47:21.110970 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7804 14:47:21.114541 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7805 14:47:21.120868 0 14 0 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7806 14:47:21.124287 0 14 4 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
7807 14:47:21.127556 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7808 14:47:21.134224 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7809 14:47:21.137431 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7810 14:47:21.140803 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7811 14:47:21.147218 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7812 14:47:21.150463 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7813 14:47:21.153669 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7814 14:47:21.160388 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7815 14:47:21.163833 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7816 14:47:21.167073 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7817 14:47:21.173919 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7818 14:47:21.177103 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7819 14:47:21.180283 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7820 14:47:21.187226 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7821 14:47:21.190407 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7822 14:47:21.193640 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7823 14:47:21.200144 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7824 14:47:21.203593 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7825 14:47:21.206890 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7826 14:47:21.213517 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7827 14:47:21.216663 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7828 14:47:21.219907 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7829 14:47:21.226453 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7830 14:47:21.230225 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7831 14:47:21.233230 Total UI for P1: 0, mck2ui 16
7832 14:47:21.236512 best dqsien dly found for B0: ( 1, 0, 30)
7833 14:47:21.240043 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7834 14:47:21.243049 Total UI for P1: 0, mck2ui 16
7835 14:47:21.246642 best dqsien dly found for B1: ( 1, 1, 2)
7836 14:47:21.249890 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7837 14:47:21.253094 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7838 14:47:21.253177
7839 14:47:21.256637 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7840 14:47:21.262803 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7841 14:47:21.262887 [Gating] SW calibration Done
7842 14:47:21.262971 ==
7843 14:47:21.266508 Dram Type= 6, Freq= 0, CH_0, rank 1
7844 14:47:21.272883 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7845 14:47:21.272970 ==
7846 14:47:21.273053 RX Vref Scan: 0
7847 14:47:21.273132
7848 14:47:21.276381 RX Vref 0 -> 0, step: 1
7849 14:47:21.276464
7850 14:47:21.279635 RX Delay 0 -> 252, step: 8
7851 14:47:21.282594 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7852 14:47:21.286523 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7853 14:47:21.289258 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7854 14:47:21.296227 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7855 14:47:21.299308 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7856 14:47:21.302743 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7857 14:47:21.305813 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7858 14:47:21.309171 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7859 14:47:21.315803 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7860 14:47:21.319215 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7861 14:47:21.322658 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7862 14:47:21.325634 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7863 14:47:21.329068 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7864 14:47:21.335536 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7865 14:47:21.338733 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7866 14:47:21.342324 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7867 14:47:21.342408 ==
7868 14:47:21.345586 Dram Type= 6, Freq= 0, CH_0, rank 1
7869 14:47:21.348835 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7870 14:47:21.352126 ==
7871 14:47:21.352209 DQS Delay:
7872 14:47:21.352292 DQS0 = 0, DQS1 = 0
7873 14:47:21.355570 DQM Delay:
7874 14:47:21.355652 DQM0 = 130, DQM1 = 124
7875 14:47:21.358885 DQ Delay:
7876 14:47:21.361848 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =123
7877 14:47:21.365266 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7878 14:47:21.368547 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7879 14:47:21.372125 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7880 14:47:21.372208
7881 14:47:21.372291
7882 14:47:21.372369 ==
7883 14:47:21.375318 Dram Type= 6, Freq= 0, CH_0, rank 1
7884 14:47:21.378422 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7885 14:47:21.378505 ==
7886 14:47:21.381779
7887 14:47:21.381861
7888 14:47:21.381944 TX Vref Scan disable
7889 14:47:21.385037 == TX Byte 0 ==
7890 14:47:21.388196 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7891 14:47:21.391756 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7892 14:47:21.395292 == TX Byte 1 ==
7893 14:47:21.398393 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7894 14:47:21.401472 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7895 14:47:21.401555 ==
7896 14:47:21.404867 Dram Type= 6, Freq= 0, CH_0, rank 1
7897 14:47:21.411552 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7898 14:47:21.411635 ==
7899 14:47:21.423568
7900 14:47:21.427065 TX Vref early break, caculate TX vref
7901 14:47:21.430320 TX Vref=16, minBit 1, minWin=22, winSum=380
7902 14:47:21.433590 TX Vref=18, minBit 11, minWin=22, winSum=385
7903 14:47:21.436652 TX Vref=20, minBit 9, minWin=23, winSum=391
7904 14:47:21.439966 TX Vref=22, minBit 8, minWin=23, winSum=398
7905 14:47:21.443081 TX Vref=24, minBit 8, minWin=24, winSum=407
7906 14:47:21.449886 TX Vref=26, minBit 1, minWin=24, winSum=413
7907 14:47:21.453504 TX Vref=28, minBit 8, minWin=24, winSum=413
7908 14:47:21.456449 TX Vref=30, minBit 8, minWin=24, winSum=406
7909 14:47:21.459696 TX Vref=32, minBit 1, minWin=24, winSum=400
7910 14:47:21.463566 TX Vref=34, minBit 8, minWin=23, winSum=390
7911 14:47:21.469527 [TxChooseVref] Worse bit 1, Min win 24, Win sum 413, Final Vref 26
7912 14:47:21.469609
7913 14:47:21.472881 Final TX Range 0 Vref 26
7914 14:47:21.472960
7915 14:47:21.473021 ==
7916 14:47:21.476177 Dram Type= 6, Freq= 0, CH_0, rank 1
7917 14:47:21.480027 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7918 14:47:21.480107 ==
7919 14:47:21.480170
7920 14:47:21.480228
7921 14:47:21.483073 TX Vref Scan disable
7922 14:47:21.489555 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7923 14:47:21.489636 == TX Byte 0 ==
7924 14:47:21.492945 u2DelayCellOfst[0]=14 cells (4 PI)
7925 14:47:21.496185 u2DelayCellOfst[1]=18 cells (5 PI)
7926 14:47:21.499449 u2DelayCellOfst[2]=10 cells (3 PI)
7927 14:47:21.502763 u2DelayCellOfst[3]=14 cells (4 PI)
7928 14:47:21.505933 u2DelayCellOfst[4]=7 cells (2 PI)
7929 14:47:21.509247 u2DelayCellOfst[5]=0 cells (0 PI)
7930 14:47:21.512809 u2DelayCellOfst[6]=18 cells (5 PI)
7931 14:47:21.516078 u2DelayCellOfst[7]=18 cells (5 PI)
7932 14:47:21.519275 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7933 14:47:21.522861 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7934 14:47:21.525865 == TX Byte 1 ==
7935 14:47:21.529392 u2DelayCellOfst[8]=0 cells (0 PI)
7936 14:47:21.532451 u2DelayCellOfst[9]=0 cells (0 PI)
7937 14:47:21.532531 u2DelayCellOfst[10]=10 cells (3 PI)
7938 14:47:21.535876 u2DelayCellOfst[11]=7 cells (2 PI)
7939 14:47:21.539109 u2DelayCellOfst[12]=14 cells (4 PI)
7940 14:47:21.542376 u2DelayCellOfst[13]=14 cells (4 PI)
7941 14:47:21.545837 u2DelayCellOfst[14]=18 cells (5 PI)
7942 14:47:21.549227 u2DelayCellOfst[15]=14 cells (4 PI)
7943 14:47:21.555623 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7944 14:47:21.558889 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7945 14:47:21.558968 DramC Write-DBI on
7946 14:47:21.559029 ==
7947 14:47:21.562239 Dram Type= 6, Freq= 0, CH_0, rank 1
7948 14:47:21.568975 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7949 14:47:21.569055 ==
7950 14:47:21.569117
7951 14:47:21.569175
7952 14:47:21.569230 TX Vref Scan disable
7953 14:47:21.573427 == TX Byte 0 ==
7954 14:47:21.576577 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7955 14:47:21.579934 == TX Byte 1 ==
7956 14:47:21.583012 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7957 14:47:21.586241 DramC Write-DBI off
7958 14:47:21.586320
7959 14:47:21.586381 [DATLAT]
7960 14:47:21.586439 Freq=1600, CH0 RK1
7961 14:47:21.586494
7962 14:47:21.589834 DATLAT Default: 0xe
7963 14:47:21.589913 0, 0xFFFF, sum = 0
7964 14:47:21.592847 1, 0xFFFF, sum = 0
7965 14:47:21.596322 2, 0xFFFF, sum = 0
7966 14:47:21.596403 3, 0xFFFF, sum = 0
7967 14:47:21.599827 4, 0xFFFF, sum = 0
7968 14:47:21.599908 5, 0xFFFF, sum = 0
7969 14:47:21.602952 6, 0xFFFF, sum = 0
7970 14:47:21.603033 7, 0xFFFF, sum = 0
7971 14:47:21.606245 8, 0xFFFF, sum = 0
7972 14:47:21.606325 9, 0xFFFF, sum = 0
7973 14:47:21.609619 10, 0xFFFF, sum = 0
7974 14:47:21.609699 11, 0xFFFF, sum = 0
7975 14:47:21.612856 12, 0x8FFF, sum = 0
7976 14:47:21.612937 13, 0x0, sum = 1
7977 14:47:21.616128 14, 0x0, sum = 2
7978 14:47:21.616208 15, 0x0, sum = 3
7979 14:47:21.619933 16, 0x0, sum = 4
7980 14:47:21.620014 best_step = 14
7981 14:47:21.620076
7982 14:47:21.620134 ==
7983 14:47:21.622848 Dram Type= 6, Freq= 0, CH_0, rank 1
7984 14:47:21.626424 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7985 14:47:21.629507 ==
7986 14:47:21.629586 RX Vref Scan: 0
7987 14:47:21.629648
7988 14:47:21.632678 RX Vref 0 -> 0, step: 1
7989 14:47:21.632757
7990 14:47:21.632818 RX Delay 11 -> 252, step: 4
7991 14:47:21.640100 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7992 14:47:21.643337 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
7993 14:47:21.646603 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7994 14:47:21.650333 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7995 14:47:21.656504 iDelay=195, Bit 4, Center 132 (75 ~ 190) 116
7996 14:47:21.659975 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7997 14:47:21.663180 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7998 14:47:21.666459 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7999 14:47:21.669852 iDelay=195, Bit 8, Center 106 (51 ~ 162) 112
8000 14:47:21.676623 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
8001 14:47:21.679713 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8002 14:47:21.682997 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
8003 14:47:21.686674 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
8004 14:47:21.689519 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
8005 14:47:21.696669 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8006 14:47:21.699364 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8007 14:47:21.699448 ==
8008 14:47:21.703025 Dram Type= 6, Freq= 0, CH_0, rank 1
8009 14:47:21.706037 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8010 14:47:21.706120 ==
8011 14:47:21.709465 DQS Delay:
8012 14:47:21.709548 DQS0 = 0, DQS1 = 0
8013 14:47:21.709647 DQM Delay:
8014 14:47:21.712974 DQM0 = 128, DQM1 = 120
8015 14:47:21.713071 DQ Delay:
8016 14:47:21.716101 DQ0 =124, DQ1 =130, DQ2 =126, DQ3 =122
8017 14:47:21.719680 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =138
8018 14:47:21.723041 DQ8 =106, DQ9 =106, DQ10 =122, DQ11 =112
8019 14:47:21.729368 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =130
8020 14:47:21.729451
8021 14:47:21.729534
8022 14:47:21.729613
8023 14:47:21.732720 [DramC_TX_OE_Calibration] TA2
8024 14:47:21.736066 Original DQ_B0 (3 6) =30, OEN = 27
8025 14:47:21.736150 Original DQ_B1 (3 6) =30, OEN = 27
8026 14:47:21.739240 24, 0x0, End_B0=24 End_B1=24
8027 14:47:21.742674 25, 0x0, End_B0=25 End_B1=25
8028 14:47:21.746004 26, 0x0, End_B0=26 End_B1=26
8029 14:47:21.749042 27, 0x0, End_B0=27 End_B1=27
8030 14:47:21.749127 28, 0x0, End_B0=28 End_B1=28
8031 14:47:21.752545 29, 0x0, End_B0=29 End_B1=29
8032 14:47:21.755871 30, 0x0, End_B0=30 End_B1=30
8033 14:47:21.759253 31, 0x4141, End_B0=30 End_B1=30
8034 14:47:21.762857 Byte0 end_step=30 best_step=27
8035 14:47:21.762939 Byte1 end_step=30 best_step=27
8036 14:47:21.765791 Byte0 TX OE(2T, 0.5T) = (3, 3)
8037 14:47:21.769133 Byte1 TX OE(2T, 0.5T) = (3, 3)
8038 14:47:21.769240
8039 14:47:21.769335
8040 14:47:21.779251 [DQSOSCAuto] RK1, (LSB)MR18= 0x2020, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
8041 14:47:21.779359 CH0 RK1: MR19=303, MR18=2020
8042 14:47:21.785517 CH0_RK1: MR19=0x303, MR18=0x2020, DQSOSC=393, MR23=63, INC=23, DEC=15
8043 14:47:21.789183 [RxdqsGatingPostProcess] freq 1600
8044 14:47:21.795657 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8045 14:47:21.799126 Pre-setting of DQS Precalculation
8046 14:47:21.802544 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8047 14:47:21.802624 ==
8048 14:47:21.805851 Dram Type= 6, Freq= 0, CH_1, rank 0
8049 14:47:21.812632 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8050 14:47:21.812709 ==
8051 14:47:21.815805 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8052 14:47:21.822247 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8053 14:47:21.825993 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8054 14:47:21.832458 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8055 14:47:21.839140 [CA 0] Center 41 (12~71) winsize 60
8056 14:47:21.842640 [CA 1] Center 41 (11~72) winsize 62
8057 14:47:21.845659 [CA 2] Center 37 (8~67) winsize 60
8058 14:47:21.849023 [CA 3] Center 36 (7~66) winsize 60
8059 14:47:21.853002 [CA 4] Center 34 (5~64) winsize 60
8060 14:47:21.855565 [CA 5] Center 34 (5~64) winsize 60
8061 14:47:21.855645
8062 14:47:21.858999 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8063 14:47:21.859079
8064 14:47:21.862323 [CATrainingPosCal] consider 1 rank data
8065 14:47:21.865484 u2DelayCellTimex100 = 271/100 ps
8066 14:47:21.872123 CA0 delay=41 (12~71),Diff = 7 PI (25 cell)
8067 14:47:21.875415 CA1 delay=41 (11~72),Diff = 7 PI (25 cell)
8068 14:47:21.879004 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
8069 14:47:21.881973 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8070 14:47:21.885625 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
8071 14:47:21.888733 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8072 14:47:21.888814
8073 14:47:21.892326 CA PerBit enable=1, Macro0, CA PI delay=34
8074 14:47:21.892407
8075 14:47:21.895393 [CBTSetCACLKResult] CA Dly = 34
8076 14:47:21.898517 CS Dly: 8 (0~39)
8077 14:47:21.901788 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8078 14:47:21.905187 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8079 14:47:21.905285 ==
8080 14:47:21.908617 Dram Type= 6, Freq= 0, CH_1, rank 1
8081 14:47:21.915180 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8082 14:47:21.915261 ==
8083 14:47:21.918656 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8084 14:47:21.921834 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8085 14:47:21.928302 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8086 14:47:21.935173 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8087 14:47:21.941749 [CA 0] Center 41 (11~71) winsize 61
8088 14:47:21.944975 [CA 1] Center 41 (11~71) winsize 61
8089 14:47:21.948356 [CA 2] Center 36 (7~66) winsize 60
8090 14:47:21.951490 [CA 3] Center 35 (6~65) winsize 60
8091 14:47:21.955039 [CA 4] Center 34 (5~64) winsize 60
8092 14:47:21.958136 [CA 5] Center 33 (4~63) winsize 60
8093 14:47:21.958217
8094 14:47:21.961742 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8095 14:47:21.961823
8096 14:47:21.964817 [CATrainingPosCal] consider 2 rank data
8097 14:47:21.968198 u2DelayCellTimex100 = 271/100 ps
8098 14:47:21.971326 CA0 delay=41 (12~71),Diff = 7 PI (25 cell)
8099 14:47:21.977974 CA1 delay=41 (11~71),Diff = 7 PI (25 cell)
8100 14:47:21.981186 CA2 delay=37 (8~66),Diff = 3 PI (10 cell)
8101 14:47:21.984584 CA3 delay=36 (7~65),Diff = 2 PI (7 cell)
8102 14:47:21.988095 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
8103 14:47:21.991297 CA5 delay=34 (5~63),Diff = 0 PI (0 cell)
8104 14:47:21.991378
8105 14:47:21.994451 CA PerBit enable=1, Macro0, CA PI delay=34
8106 14:47:21.994531
8107 14:47:21.997830 [CBTSetCACLKResult] CA Dly = 34
8108 14:47:22.001386 CS Dly: 8 (0~40)
8109 14:47:22.004439 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8110 14:47:22.007541 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8111 14:47:22.007621
8112 14:47:22.011500 ----->DramcWriteLeveling(PI) begin...
8113 14:47:22.011582 ==
8114 14:47:22.014495 Dram Type= 6, Freq= 0, CH_1, rank 0
8115 14:47:22.021223 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8116 14:47:22.021308 ==
8117 14:47:22.024513 Write leveling (Byte 0): 21 => 21
8118 14:47:22.024594 Write leveling (Byte 1): 21 => 21
8119 14:47:22.027836 DramcWriteLeveling(PI) end<-----
8120 14:47:22.027916
8121 14:47:22.027978 ==
8122 14:47:22.031105 Dram Type= 6, Freq= 0, CH_1, rank 0
8123 14:47:22.038027 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8124 14:47:22.038108 ==
8125 14:47:22.041118 [Gating] SW mode calibration
8126 14:47:22.047838 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8127 14:47:22.051019 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8128 14:47:22.057862 0 12 0 | B1->B0 | 2423 3434 | 1 0 | (0 0) (0 0)
8129 14:47:22.060888 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8130 14:47:22.064189 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8131 14:47:22.070709 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8132 14:47:22.074150 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8133 14:47:22.077535 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8134 14:47:22.084314 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8135 14:47:22.087416 0 12 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
8136 14:47:22.090738 0 13 0 | B1->B0 | 3333 2424 | 1 0 | (1 1) (1 0)
8137 14:47:22.097475 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8138 14:47:22.100574 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8139 14:47:22.103929 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8140 14:47:22.110769 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8141 14:47:22.114005 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8142 14:47:22.117233 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8143 14:47:22.123784 0 13 28 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8144 14:47:22.127359 0 14 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
8145 14:47:22.130668 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8146 14:47:22.137125 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8147 14:47:22.140625 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8148 14:47:22.143705 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8149 14:47:22.147132 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8150 14:47:22.153744 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8151 14:47:22.156845 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8152 14:47:22.160341 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8153 14:47:22.166885 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8154 14:47:22.170551 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8155 14:47:22.173573 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8156 14:47:22.180147 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8157 14:47:22.183661 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8158 14:47:22.186611 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8159 14:47:22.193204 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8160 14:47:22.196511 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8161 14:47:22.199759 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8162 14:47:22.206522 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8163 14:47:22.209679 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8164 14:47:22.213059 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8165 14:47:22.219678 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8166 14:47:22.222814 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8167 14:47:22.226216 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8168 14:47:22.232797 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8169 14:47:22.236183 Total UI for P1: 0, mck2ui 16
8170 14:47:22.239528 best dqsien dly found for B0: ( 1, 0, 26)
8171 14:47:22.242912 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8172 14:47:22.246076 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8173 14:47:22.249813 Total UI for P1: 0, mck2ui 16
8174 14:47:22.252535 best dqsien dly found for B1: ( 1, 1, 2)
8175 14:47:22.256311 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8176 14:47:22.259500 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8177 14:47:22.259580
8178 14:47:22.266080 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8179 14:47:22.269407 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8180 14:47:22.272614 [Gating] SW calibration Done
8181 14:47:22.272694 ==
8182 14:47:22.276316 Dram Type= 6, Freq= 0, CH_1, rank 0
8183 14:47:22.279466 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8184 14:47:22.279547 ==
8185 14:47:22.279612 RX Vref Scan: 0
8186 14:47:22.279670
8187 14:47:22.282610 RX Vref 0 -> 0, step: 1
8188 14:47:22.282690
8189 14:47:22.285702 RX Delay 0 -> 252, step: 8
8190 14:47:22.289088 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8191 14:47:22.292346 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8192 14:47:22.299077 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8193 14:47:22.302736 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8194 14:47:22.305651 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8195 14:47:22.308975 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8196 14:47:22.312673 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8197 14:47:22.315758 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8198 14:47:22.322454 iDelay=200, Bit 8, Center 103 (48 ~ 159) 112
8199 14:47:22.325499 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8200 14:47:22.328876 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8201 14:47:22.332380 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8202 14:47:22.338699 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8203 14:47:22.342041 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8204 14:47:22.345452 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8205 14:47:22.349092 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8206 14:47:22.349172 ==
8207 14:47:22.352005 Dram Type= 6, Freq= 0, CH_1, rank 0
8208 14:47:22.358874 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8209 14:47:22.358955 ==
8210 14:47:22.359019 DQS Delay:
8211 14:47:22.361926 DQS0 = 0, DQS1 = 0
8212 14:47:22.362006 DQM Delay:
8213 14:47:22.362068 DQM0 = 129, DQM1 = 125
8214 14:47:22.365242 DQ Delay:
8215 14:47:22.368570 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8216 14:47:22.371992 DQ4 =127, DQ5 =143, DQ6 =135, DQ7 =127
8217 14:47:22.375089 DQ8 =103, DQ9 =115, DQ10 =127, DQ11 =115
8218 14:47:22.378510 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8219 14:47:22.378590
8220 14:47:22.378653
8221 14:47:22.378712 ==
8222 14:47:22.381696 Dram Type= 6, Freq= 0, CH_1, rank 0
8223 14:47:22.384963 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8224 14:47:22.388450 ==
8225 14:47:22.388530
8226 14:47:22.388592
8227 14:47:22.388648 TX Vref Scan disable
8228 14:47:22.391557 == TX Byte 0 ==
8229 14:47:22.395283 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8230 14:47:22.398133 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8231 14:47:22.401507 == TX Byte 1 ==
8232 14:47:22.405116 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8233 14:47:22.408073 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8234 14:47:22.411306 ==
8235 14:47:22.414900 Dram Type= 6, Freq= 0, CH_1, rank 0
8236 14:47:22.417883 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8237 14:47:22.417963 ==
8238 14:47:22.431030
8239 14:47:22.434063 TX Vref early break, caculate TX vref
8240 14:47:22.437463 TX Vref=16, minBit 3, minWin=21, winSum=369
8241 14:47:22.440496 TX Vref=18, minBit 3, minWin=22, winSum=378
8242 14:47:22.444138 TX Vref=20, minBit 3, minWin=22, winSum=384
8243 14:47:22.447300 TX Vref=22, minBit 1, minWin=23, winSum=393
8244 14:47:22.450676 TX Vref=24, minBit 4, minWin=23, winSum=404
8245 14:47:22.457336 TX Vref=26, minBit 1, minWin=24, winSum=413
8246 14:47:22.460909 TX Vref=28, minBit 3, minWin=24, winSum=413
8247 14:47:22.463924 TX Vref=30, minBit 7, minWin=24, winSum=407
8248 14:47:22.467570 TX Vref=32, minBit 3, minWin=23, winSum=398
8249 14:47:22.470550 TX Vref=34, minBit 3, minWin=23, winSum=394
8250 14:47:22.473963 TX Vref=36, minBit 3, minWin=21, winSum=379
8251 14:47:22.480599 [TxChooseVref] Worse bit 1, Min win 24, Win sum 413, Final Vref 26
8252 14:47:22.480684
8253 14:47:22.483790 Final TX Range 0 Vref 26
8254 14:47:22.483861
8255 14:47:22.483920 ==
8256 14:47:22.487197 Dram Type= 6, Freq= 0, CH_1, rank 0
8257 14:47:22.490511 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8258 14:47:22.490592 ==
8259 14:47:22.490654
8260 14:47:22.490713
8261 14:47:22.494075 TX Vref Scan disable
8262 14:47:22.500483 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8263 14:47:22.500563 == TX Byte 0 ==
8264 14:47:22.503978 u2DelayCellOfst[0]=14 cells (4 PI)
8265 14:47:22.507168 u2DelayCellOfst[1]=10 cells (3 PI)
8266 14:47:22.510451 u2DelayCellOfst[2]=0 cells (0 PI)
8267 14:47:22.513718 u2DelayCellOfst[3]=3 cells (1 PI)
8268 14:47:22.517019 u2DelayCellOfst[4]=7 cells (2 PI)
8269 14:47:22.520372 u2DelayCellOfst[5]=18 cells (5 PI)
8270 14:47:22.523605 u2DelayCellOfst[6]=14 cells (4 PI)
8271 14:47:22.526779 u2DelayCellOfst[7]=3 cells (1 PI)
8272 14:47:22.530466 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8273 14:47:22.533574 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8274 14:47:22.536874 == TX Byte 1 ==
8275 14:47:22.540132 u2DelayCellOfst[8]=0 cells (0 PI)
8276 14:47:22.540213 u2DelayCellOfst[9]=3 cells (1 PI)
8277 14:47:22.543566 u2DelayCellOfst[10]=7 cells (2 PI)
8278 14:47:22.546760 u2DelayCellOfst[11]=3 cells (1 PI)
8279 14:47:22.550053 u2DelayCellOfst[12]=14 cells (4 PI)
8280 14:47:22.553269 u2DelayCellOfst[13]=18 cells (5 PI)
8281 14:47:22.556507 u2DelayCellOfst[14]=18 cells (5 PI)
8282 14:47:22.559810 u2DelayCellOfst[15]=18 cells (5 PI)
8283 14:47:22.566986 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8284 14:47:22.569839 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8285 14:47:22.569923 DramC Write-DBI on
8286 14:47:22.569986 ==
8287 14:47:22.573097 Dram Type= 6, Freq= 0, CH_1, rank 0
8288 14:47:22.579747 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8289 14:47:22.579828 ==
8290 14:47:22.579891
8291 14:47:22.579949
8292 14:47:22.580005 TX Vref Scan disable
8293 14:47:22.583787 == TX Byte 0 ==
8294 14:47:22.586939 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8295 14:47:22.590112 == TX Byte 1 ==
8296 14:47:22.593457 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8297 14:47:22.596800 DramC Write-DBI off
8298 14:47:22.596879
8299 14:47:22.596940 [DATLAT]
8300 14:47:22.596998 Freq=1600, CH1 RK0
8301 14:47:22.597054
8302 14:47:22.599914 DATLAT Default: 0xf
8303 14:47:22.603389 0, 0xFFFF, sum = 0
8304 14:47:22.603470 1, 0xFFFF, sum = 0
8305 14:47:22.606718 2, 0xFFFF, sum = 0
8306 14:47:22.606799 3, 0xFFFF, sum = 0
8307 14:47:22.610045 4, 0xFFFF, sum = 0
8308 14:47:22.610127 5, 0xFFFF, sum = 0
8309 14:47:22.613472 6, 0xFFFF, sum = 0
8310 14:47:22.613553 7, 0xFFFF, sum = 0
8311 14:47:22.616530 8, 0xFFFF, sum = 0
8312 14:47:22.616611 9, 0xFFFF, sum = 0
8313 14:47:22.619972 10, 0xFFFF, sum = 0
8314 14:47:22.620053 11, 0xFFFF, sum = 0
8315 14:47:22.623314 12, 0x8FFF, sum = 0
8316 14:47:22.623394 13, 0x0, sum = 1
8317 14:47:22.626808 14, 0x0, sum = 2
8318 14:47:22.626888 15, 0x0, sum = 3
8319 14:47:22.630226 16, 0x0, sum = 4
8320 14:47:22.630307 best_step = 14
8321 14:47:22.630369
8322 14:47:22.630427 ==
8323 14:47:22.633208 Dram Type= 6, Freq= 0, CH_1, rank 0
8324 14:47:22.636388 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8325 14:47:22.639791 ==
8326 14:47:22.639870 RX Vref Scan: 1
8327 14:47:22.639932
8328 14:47:22.643042 Set Vref Range= 24 -> 127
8329 14:47:22.643122
8330 14:47:22.646596 RX Vref 24 -> 127, step: 1
8331 14:47:22.646675
8332 14:47:22.646738 RX Delay 3 -> 252, step: 4
8333 14:47:22.646795
8334 14:47:22.649713 Set Vref, RX VrefLevel [Byte0]: 24
8335 14:47:22.653098 [Byte1]: 24
8336 14:47:22.657114
8337 14:47:22.657193 Set Vref, RX VrefLevel [Byte0]: 25
8338 14:47:22.660480 [Byte1]: 25
8339 14:47:22.664782
8340 14:47:22.664861 Set Vref, RX VrefLevel [Byte0]: 26
8341 14:47:22.667998 [Byte1]: 26
8342 14:47:22.672409
8343 14:47:22.672488 Set Vref, RX VrefLevel [Byte0]: 27
8344 14:47:22.675454 [Byte1]: 27
8345 14:47:22.680050
8346 14:47:22.680129 Set Vref, RX VrefLevel [Byte0]: 28
8347 14:47:22.683129 [Byte1]: 28
8348 14:47:22.687611
8349 14:47:22.687690 Set Vref, RX VrefLevel [Byte0]: 29
8350 14:47:22.690807 [Byte1]: 29
8351 14:47:22.695565
8352 14:47:22.695645 Set Vref, RX VrefLevel [Byte0]: 30
8353 14:47:22.698512 [Byte1]: 30
8354 14:47:22.702900
8355 14:47:22.702986 Set Vref, RX VrefLevel [Byte0]: 31
8356 14:47:22.706026 [Byte1]: 31
8357 14:47:22.710456
8358 14:47:22.710540 Set Vref, RX VrefLevel [Byte0]: 32
8359 14:47:22.713851 [Byte1]: 32
8360 14:47:22.718432
8361 14:47:22.718512 Set Vref, RX VrefLevel [Byte0]: 33
8362 14:47:22.721448 [Byte1]: 33
8363 14:47:22.725689
8364 14:47:22.725768 Set Vref, RX VrefLevel [Byte0]: 34
8365 14:47:22.729600 [Byte1]: 34
8366 14:47:22.733485
8367 14:47:22.733564 Set Vref, RX VrefLevel [Byte0]: 35
8368 14:47:22.736898 [Byte1]: 35
8369 14:47:22.741134
8370 14:47:22.741213 Set Vref, RX VrefLevel [Byte0]: 36
8371 14:47:22.744547 [Byte1]: 36
8372 14:47:22.748839
8373 14:47:22.748918 Set Vref, RX VrefLevel [Byte0]: 37
8374 14:47:22.752199 [Byte1]: 37
8375 14:47:22.756321
8376 14:47:22.756400 Set Vref, RX VrefLevel [Byte0]: 38
8377 14:47:22.759727 [Byte1]: 38
8378 14:47:22.764142
8379 14:47:22.764221 Set Vref, RX VrefLevel [Byte0]: 39
8380 14:47:22.767312 [Byte1]: 39
8381 14:47:22.771822
8382 14:47:22.771902 Set Vref, RX VrefLevel [Byte0]: 40
8383 14:47:22.775226 [Byte1]: 40
8384 14:47:22.779408
8385 14:47:22.779487 Set Vref, RX VrefLevel [Byte0]: 41
8386 14:47:22.782527 [Byte1]: 41
8387 14:47:22.787052
8388 14:47:22.787131 Set Vref, RX VrefLevel [Byte0]: 42
8389 14:47:22.790220 [Byte1]: 42
8390 14:47:22.794992
8391 14:47:22.795071 Set Vref, RX VrefLevel [Byte0]: 43
8392 14:47:22.798277 [Byte1]: 43
8393 14:47:22.802309
8394 14:47:22.802388 Set Vref, RX VrefLevel [Byte0]: 44
8395 14:47:22.805668 [Byte1]: 44
8396 14:47:22.809961
8397 14:47:22.810040 Set Vref, RX VrefLevel [Byte0]: 45
8398 14:47:22.813256 [Byte1]: 45
8399 14:47:22.817906
8400 14:47:22.817986 Set Vref, RX VrefLevel [Byte0]: 46
8401 14:47:22.821035 [Byte1]: 46
8402 14:47:22.825236
8403 14:47:22.825351 Set Vref, RX VrefLevel [Byte0]: 47
8404 14:47:22.828463 [Byte1]: 47
8405 14:47:22.833401
8406 14:47:22.833506 Set Vref, RX VrefLevel [Byte0]: 48
8407 14:47:22.836129 [Byte1]: 48
8408 14:47:22.840562
8409 14:47:22.840640 Set Vref, RX VrefLevel [Byte0]: 49
8410 14:47:22.843979 [Byte1]: 49
8411 14:47:22.848129
8412 14:47:22.848208 Set Vref, RX VrefLevel [Byte0]: 50
8413 14:47:22.851453 [Byte1]: 50
8414 14:47:22.855977
8415 14:47:22.856057 Set Vref, RX VrefLevel [Byte0]: 51
8416 14:47:22.859285 [Byte1]: 51
8417 14:47:22.863508
8418 14:47:22.863587 Set Vref, RX VrefLevel [Byte0]: 52
8419 14:47:22.867085 [Byte1]: 52
8420 14:47:22.871126
8421 14:47:22.871205 Set Vref, RX VrefLevel [Byte0]: 53
8422 14:47:22.874503 [Byte1]: 53
8423 14:47:22.878730
8424 14:47:22.878813 Set Vref, RX VrefLevel [Byte0]: 54
8425 14:47:22.882213 [Byte1]: 54
8426 14:47:22.886991
8427 14:47:22.887073 Set Vref, RX VrefLevel [Byte0]: 55
8428 14:47:22.889987 [Byte1]: 55
8429 14:47:22.893944
8430 14:47:22.894026 Set Vref, RX VrefLevel [Byte0]: 56
8431 14:47:22.897529 [Byte1]: 56
8432 14:47:22.901787
8433 14:47:22.901869 Set Vref, RX VrefLevel [Byte0]: 57
8434 14:47:22.905137 [Byte1]: 57
8435 14:47:22.909663
8436 14:47:22.909745 Set Vref, RX VrefLevel [Byte0]: 58
8437 14:47:22.912702 [Byte1]: 58
8438 14:47:22.917037
8439 14:47:22.917120 Set Vref, RX VrefLevel [Byte0]: 59
8440 14:47:22.920489 [Byte1]: 59
8441 14:47:22.924675
8442 14:47:22.924758 Set Vref, RX VrefLevel [Byte0]: 60
8443 14:47:22.928182 [Byte1]: 60
8444 14:47:22.932400
8445 14:47:22.932482 Set Vref, RX VrefLevel [Byte0]: 61
8446 14:47:22.935634 [Byte1]: 61
8447 14:47:22.940220
8448 14:47:22.940302 Set Vref, RX VrefLevel [Byte0]: 62
8449 14:47:22.943312 [Byte1]: 62
8450 14:47:22.947711
8451 14:47:22.947793 Set Vref, RX VrefLevel [Byte0]: 63
8452 14:47:22.950879 [Byte1]: 63
8453 14:47:22.955492
8454 14:47:22.955574 Set Vref, RX VrefLevel [Byte0]: 64
8455 14:47:22.958682 [Byte1]: 64
8456 14:47:22.963180
8457 14:47:22.963262 Set Vref, RX VrefLevel [Byte0]: 65
8458 14:47:22.966307 [Byte1]: 65
8459 14:47:22.970804
8460 14:47:22.970884 Set Vref, RX VrefLevel [Byte0]: 66
8461 14:47:22.973892 [Byte1]: 66
8462 14:47:22.978295
8463 14:47:22.978374 Set Vref, RX VrefLevel [Byte0]: 67
8464 14:47:22.981787 [Byte1]: 67
8465 14:47:22.986104
8466 14:47:22.986183 Set Vref, RX VrefLevel [Byte0]: 68
8467 14:47:22.989632 [Byte1]: 68
8468 14:47:22.993813
8469 14:47:22.993892 Set Vref, RX VrefLevel [Byte0]: 69
8470 14:47:22.996744 [Byte1]: 69
8471 14:47:23.001253
8472 14:47:23.001379 Set Vref, RX VrefLevel [Byte0]: 70
8473 14:47:23.004584 [Byte1]: 70
8474 14:47:23.009042
8475 14:47:23.009152 Set Vref, RX VrefLevel [Byte0]: 71
8476 14:47:23.012270 [Byte1]: 71
8477 14:47:23.016957
8478 14:47:23.017036 Set Vref, RX VrefLevel [Byte0]: 72
8479 14:47:23.020143 [Byte1]: 72
8480 14:47:23.024189
8481 14:47:23.024268 Set Vref, RX VrefLevel [Byte0]: 73
8482 14:47:23.027591 [Byte1]: 73
8483 14:47:23.032038
8484 14:47:23.032135 Set Vref, RX VrefLevel [Byte0]: 74
8485 14:47:23.035315 [Byte1]: 74
8486 14:47:23.039589
8487 14:47:23.039668 Set Vref, RX VrefLevel [Byte0]: 75
8488 14:47:23.042709 [Byte1]: 75
8489 14:47:23.047490
8490 14:47:23.047570 Final RX Vref Byte 0 = 62 to rank0
8491 14:47:23.050757 Final RX Vref Byte 1 = 55 to rank0
8492 14:47:23.053853 Final RX Vref Byte 0 = 62 to rank1
8493 14:47:23.057005 Final RX Vref Byte 1 = 55 to rank1==
8494 14:47:23.060428 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 14:47:23.067004 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8496 14:47:23.067084 ==
8497 14:47:23.067146 DQS Delay:
8498 14:47:23.070349 DQS0 = 0, DQS1 = 0
8499 14:47:23.070432 DQM Delay:
8500 14:47:23.070515 DQM0 = 128, DQM1 = 124
8501 14:47:23.073786 DQ Delay:
8502 14:47:23.077051 DQ0 =132, DQ1 =124, DQ2 =116, DQ3 =126
8503 14:47:23.080209 DQ4 =130, DQ5 =138, DQ6 =138, DQ7 =126
8504 14:47:23.083842 DQ8 =106, DQ9 =114, DQ10 =128, DQ11 =114
8505 14:47:23.087032 DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =134
8506 14:47:23.087114
8507 14:47:23.087212
8508 14:47:23.087292
8509 14:47:23.090276 [DramC_TX_OE_Calibration] TA2
8510 14:47:23.093574 Original DQ_B0 (3 6) =30, OEN = 27
8511 14:47:23.096964 Original DQ_B1 (3 6) =30, OEN = 27
8512 14:47:23.100515 24, 0x0, End_B0=24 End_B1=24
8513 14:47:23.100601 25, 0x0, End_B0=25 End_B1=25
8514 14:47:23.103709 26, 0x0, End_B0=26 End_B1=26
8515 14:47:23.107212 27, 0x0, End_B0=27 End_B1=27
8516 14:47:23.110331 28, 0x0, End_B0=28 End_B1=28
8517 14:47:23.113367 29, 0x0, End_B0=29 End_B1=29
8518 14:47:23.113452 30, 0x0, End_B0=30 End_B1=30
8519 14:47:23.116815 31, 0x4141, End_B0=30 End_B1=30
8520 14:47:23.119880 Byte0 end_step=30 best_step=27
8521 14:47:23.123353 Byte1 end_step=30 best_step=27
8522 14:47:23.126624 Byte0 TX OE(2T, 0.5T) = (3, 3)
8523 14:47:23.129873 Byte1 TX OE(2T, 0.5T) = (3, 3)
8524 14:47:23.129953
8525 14:47:23.130015
8526 14:47:23.136543 [DQSOSCAuto] RK0, (LSB)MR18= 0x2828, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
8527 14:47:23.139805 CH1 RK0: MR19=303, MR18=2828
8528 14:47:23.146357 CH1_RK0: MR19=0x303, MR18=0x2828, DQSOSC=389, MR23=63, INC=24, DEC=16
8529 14:47:23.146439
8530 14:47:23.149832 ----->DramcWriteLeveling(PI) begin...
8531 14:47:23.149918 ==
8532 14:47:23.152940 Dram Type= 6, Freq= 0, CH_1, rank 1
8533 14:47:23.156308 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8534 14:47:23.156391 ==
8535 14:47:23.159684 Write leveling (Byte 0): 22 => 22
8536 14:47:23.162872 Write leveling (Byte 1): 22 => 22
8537 14:47:23.166112 DramcWriteLeveling(PI) end<-----
8538 14:47:23.166195
8539 14:47:23.166277 ==
8540 14:47:23.169775 Dram Type= 6, Freq= 0, CH_1, rank 1
8541 14:47:23.173362 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8542 14:47:23.173446 ==
8543 14:47:23.176195 [Gating] SW mode calibration
8544 14:47:23.182756 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8545 14:47:23.189654 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8546 14:47:23.192940 0 12 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8547 14:47:23.199500 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8548 14:47:23.203150 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8549 14:47:23.206097 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8550 14:47:23.212714 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8551 14:47:23.215763 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8552 14:47:23.219410 0 12 24 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
8553 14:47:23.225793 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8554 14:47:23.229195 0 13 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8555 14:47:23.232491 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8556 14:47:23.239002 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8557 14:47:23.242740 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8558 14:47:23.245802 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8559 14:47:23.249186 0 13 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8560 14:47:23.255865 0 13 24 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
8561 14:47:23.258958 0 13 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8562 14:47:23.262415 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8563 14:47:23.269025 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8564 14:47:23.272270 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8565 14:47:23.275726 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8566 14:47:23.282102 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8567 14:47:23.285524 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8568 14:47:23.288763 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8569 14:47:23.295471 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8570 14:47:23.299000 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8571 14:47:23.302153 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8572 14:47:23.308807 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8573 14:47:23.311890 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8574 14:47:23.315255 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8575 14:47:23.321955 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8576 14:47:23.325655 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8577 14:47:23.328662 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8578 14:47:23.335381 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8579 14:47:23.338681 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8580 14:47:23.342068 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8581 14:47:23.348617 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8582 14:47:23.351962 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8583 14:47:23.355377 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8584 14:47:23.362032 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8585 14:47:23.365201 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8586 14:47:23.368390 Total UI for P1: 0, mck2ui 16
8587 14:47:23.372142 best dqsien dly found for B0: ( 1, 0, 24)
8588 14:47:23.375101 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8589 14:47:23.381807 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8590 14:47:23.381915 Total UI for P1: 0, mck2ui 16
8591 14:47:23.388420 best dqsien dly found for B1: ( 1, 0, 30)
8592 14:47:23.391493 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8593 14:47:23.395289 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8594 14:47:23.395369
8595 14:47:23.398365 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8596 14:47:23.401660 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8597 14:47:23.405084 [Gating] SW calibration Done
8598 14:47:23.405190 ==
8599 14:47:23.408357 Dram Type= 6, Freq= 0, CH_1, rank 1
8600 14:47:23.411438 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8601 14:47:23.411519 ==
8602 14:47:23.414827 RX Vref Scan: 0
8603 14:47:23.414906
8604 14:47:23.414969 RX Vref 0 -> 0, step: 1
8605 14:47:23.415027
8606 14:47:23.418143 RX Delay 0 -> 252, step: 8
8607 14:47:23.421671 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8608 14:47:23.428123 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8609 14:47:23.431657 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8610 14:47:23.434793 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8611 14:47:23.437846 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8612 14:47:23.441279 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8613 14:47:23.447618 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8614 14:47:23.451028 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8615 14:47:23.454586 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8616 14:47:23.457626 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8617 14:47:23.461001 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8618 14:47:23.467974 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8619 14:47:23.470902 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8620 14:47:23.474410 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8621 14:47:23.477614 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8622 14:47:23.484205 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8623 14:47:23.484285 ==
8624 14:47:23.487416 Dram Type= 6, Freq= 0, CH_1, rank 1
8625 14:47:23.490656 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8626 14:47:23.490737 ==
8627 14:47:23.490800 DQS Delay:
8628 14:47:23.494192 DQS0 = 0, DQS1 = 0
8629 14:47:23.494272 DQM Delay:
8630 14:47:23.497462 DQM0 = 131, DQM1 = 125
8631 14:47:23.497542 DQ Delay:
8632 14:47:23.501067 DQ0 =131, DQ1 =123, DQ2 =119, DQ3 =131
8633 14:47:23.503859 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8634 14:47:23.507469 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8635 14:47:23.510421 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8636 14:47:23.510501
8637 14:47:23.510564
8638 14:47:23.513795 ==
8639 14:47:23.516983 Dram Type= 6, Freq= 0, CH_1, rank 1
8640 14:47:23.520263 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8641 14:47:23.520343 ==
8642 14:47:23.520406
8643 14:47:23.520464
8644 14:47:23.523645 TX Vref Scan disable
8645 14:47:23.523725 == TX Byte 0 ==
8646 14:47:23.530252 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8647 14:47:23.534127 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8648 14:47:23.534208 == TX Byte 1 ==
8649 14:47:23.540285 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8650 14:47:23.543823 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8651 14:47:23.543903 ==
8652 14:47:23.546934 Dram Type= 6, Freq= 0, CH_1, rank 1
8653 14:47:23.550332 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8654 14:47:23.550414 ==
8655 14:47:23.562814
8656 14:47:23.566492 TX Vref early break, caculate TX vref
8657 14:47:23.569709 TX Vref=16, minBit 4, minWin=22, winSum=374
8658 14:47:23.572747 TX Vref=18, minBit 5, minWin=22, winSum=385
8659 14:47:23.576211 TX Vref=20, minBit 3, minWin=23, winSum=393
8660 14:47:23.579382 TX Vref=22, minBit 1, minWin=24, winSum=400
8661 14:47:23.582843 TX Vref=24, minBit 2, minWin=24, winSum=410
8662 14:47:23.589231 TX Vref=26, minBit 0, minWin=25, winSum=417
8663 14:47:23.592616 TX Vref=28, minBit 0, minWin=25, winSum=421
8664 14:47:23.595974 TX Vref=30, minBit 0, minWin=24, winSum=414
8665 14:47:23.599202 TX Vref=32, minBit 0, minWin=24, winSum=408
8666 14:47:23.602511 TX Vref=34, minBit 0, minWin=23, winSum=398
8667 14:47:23.609542 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 28
8668 14:47:23.609623
8669 14:47:23.612472 Final TX Range 0 Vref 28
8670 14:47:23.612553
8671 14:47:23.612615 ==
8672 14:47:23.615666 Dram Type= 6, Freq= 0, CH_1, rank 1
8673 14:47:23.618929 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8674 14:47:23.619010 ==
8675 14:47:23.619073
8676 14:47:23.619131
8677 14:47:23.622101 TX Vref Scan disable
8678 14:47:23.628928 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8679 14:47:23.629008 == TX Byte 0 ==
8680 14:47:23.632367 u2DelayCellOfst[0]=18 cells (5 PI)
8681 14:47:23.635558 u2DelayCellOfst[1]=10 cells (3 PI)
8682 14:47:23.638920 u2DelayCellOfst[2]=0 cells (0 PI)
8683 14:47:23.642292 u2DelayCellOfst[3]=7 cells (2 PI)
8684 14:47:23.645530 u2DelayCellOfst[4]=10 cells (3 PI)
8685 14:47:23.648905 u2DelayCellOfst[5]=18 cells (5 PI)
8686 14:47:23.652229 u2DelayCellOfst[6]=18 cells (5 PI)
8687 14:47:23.655486 u2DelayCellOfst[7]=7 cells (2 PI)
8688 14:47:23.658623 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8689 14:47:23.662403 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8690 14:47:23.665521 == TX Byte 1 ==
8691 14:47:23.668680 u2DelayCellOfst[8]=0 cells (0 PI)
8692 14:47:23.668761 u2DelayCellOfst[9]=7 cells (2 PI)
8693 14:47:23.672132 u2DelayCellOfst[10]=14 cells (4 PI)
8694 14:47:23.675141 u2DelayCellOfst[11]=7 cells (2 PI)
8695 14:47:23.678610 u2DelayCellOfst[12]=18 cells (5 PI)
8696 14:47:23.681887 u2DelayCellOfst[13]=21 cells (6 PI)
8697 14:47:23.685439 u2DelayCellOfst[14]=21 cells (6 PI)
8698 14:47:23.688426 u2DelayCellOfst[15]=21 cells (6 PI)
8699 14:47:23.691955 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8700 14:47:23.698403 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8701 14:47:23.698483 DramC Write-DBI on
8702 14:47:23.698546 ==
8703 14:47:23.701715 Dram Type= 6, Freq= 0, CH_1, rank 1
8704 14:47:23.708225 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8705 14:47:23.708305 ==
8706 14:47:23.708368
8707 14:47:23.708439
8708 14:47:23.708535 TX Vref Scan disable
8709 14:47:23.712002 == TX Byte 0 ==
8710 14:47:23.715315 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8711 14:47:23.718998 == TX Byte 1 ==
8712 14:47:23.721977 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8713 14:47:23.725367 DramC Write-DBI off
8714 14:47:23.725447
8715 14:47:23.725510 [DATLAT]
8716 14:47:23.725569 Freq=1600, CH1 RK1
8717 14:47:23.725625
8718 14:47:23.728613 DATLAT Default: 0xe
8719 14:47:23.728693 0, 0xFFFF, sum = 0
8720 14:47:23.731895 1, 0xFFFF, sum = 0
8721 14:47:23.735153 2, 0xFFFF, sum = 0
8722 14:47:23.735235 3, 0xFFFF, sum = 0
8723 14:47:23.738594 4, 0xFFFF, sum = 0
8724 14:47:23.738676 5, 0xFFFF, sum = 0
8725 14:47:23.742075 6, 0xFFFF, sum = 0
8726 14:47:23.742157 7, 0xFFFF, sum = 0
8727 14:47:23.745252 8, 0xFFFF, sum = 0
8728 14:47:23.745383 9, 0xFFFF, sum = 0
8729 14:47:23.748638 10, 0xFFFF, sum = 0
8730 14:47:23.748720 11, 0xFFFF, sum = 0
8731 14:47:23.751933 12, 0xF7F, sum = 0
8732 14:47:23.752015 13, 0x0, sum = 1
8733 14:47:23.755356 14, 0x0, sum = 2
8734 14:47:23.755438 15, 0x0, sum = 3
8735 14:47:23.758584 16, 0x0, sum = 4
8736 14:47:23.758665 best_step = 14
8737 14:47:23.758728
8738 14:47:23.758787 ==
8739 14:47:23.761660 Dram Type= 6, Freq= 0, CH_1, rank 1
8740 14:47:23.765175 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8741 14:47:23.768544 ==
8742 14:47:23.768623 RX Vref Scan: 0
8743 14:47:23.768686
8744 14:47:23.771755 RX Vref 0 -> 0, step: 1
8745 14:47:23.771836
8746 14:47:23.771898 RX Delay 3 -> 252, step: 4
8747 14:47:23.778950 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8748 14:47:23.782147 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8749 14:47:23.785449 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8750 14:47:23.788771 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8751 14:47:23.792194 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8752 14:47:23.798980 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8753 14:47:23.802190 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8754 14:47:23.805595 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8755 14:47:23.808834 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8756 14:47:23.812813 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8757 14:47:23.818821 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8758 14:47:23.822122 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8759 14:47:23.825544 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8760 14:47:23.828847 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8761 14:47:23.835197 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8762 14:47:23.838632 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8763 14:47:23.838712 ==
8764 14:47:23.842109 Dram Type= 6, Freq= 0, CH_1, rank 1
8765 14:47:23.845617 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8766 14:47:23.845697 ==
8767 14:47:23.848627 DQS Delay:
8768 14:47:23.848707 DQS0 = 0, DQS1 = 0
8769 14:47:23.848770 DQM Delay:
8770 14:47:23.852048 DQM0 = 127, DQM1 = 123
8771 14:47:23.852127 DQ Delay:
8772 14:47:23.855193 DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =124
8773 14:47:23.858499 DQ4 =126, DQ5 =138, DQ6 =134, DQ7 =126
8774 14:47:23.865070 DQ8 =106, DQ9 =112, DQ10 =124, DQ11 =114
8775 14:47:23.868506 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132
8776 14:47:23.868586
8777 14:47:23.868651
8778 14:47:23.868732
8779 14:47:23.871644 [DramC_TX_OE_Calibration] TA2
8780 14:47:23.875047 Original DQ_B0 (3 6) =30, OEN = 27
8781 14:47:23.875131 Original DQ_B1 (3 6) =30, OEN = 27
8782 14:47:23.878106 24, 0x0, End_B0=24 End_B1=24
8783 14:47:23.881793 25, 0x0, End_B0=25 End_B1=25
8784 14:47:23.884970 26, 0x0, End_B0=26 End_B1=26
8785 14:47:23.888396 27, 0x0, End_B0=27 End_B1=27
8786 14:47:23.888481 28, 0x0, End_B0=28 End_B1=28
8787 14:47:23.891896 29, 0x0, End_B0=29 End_B1=29
8788 14:47:23.894887 30, 0x0, End_B0=30 End_B1=30
8789 14:47:23.898328 31, 0x4141, End_B0=30 End_B1=30
8790 14:47:23.901530 Byte0 end_step=30 best_step=27
8791 14:47:23.905072 Byte1 end_step=30 best_step=27
8792 14:47:23.905172 Byte0 TX OE(2T, 0.5T) = (3, 3)
8793 14:47:23.907939 Byte1 TX OE(2T, 0.5T) = (3, 3)
8794 14:47:23.908036
8795 14:47:23.908132
8796 14:47:23.918157 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8797 14:47:23.918240 CH1 RK1: MR19=303, MR18=1F1F
8798 14:47:23.924790 CH1_RK1: MR19=0x303, MR18=0x1F1F, DQSOSC=394, MR23=63, INC=23, DEC=15
8799 14:47:23.927986 [RxdqsGatingPostProcess] freq 1600
8800 14:47:23.934683 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8801 14:47:23.938049 Pre-setting of DQS Precalculation
8802 14:47:23.941747 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8803 14:47:23.951167 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8804 14:47:23.957894 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8805 14:47:23.957978
8806 14:47:23.958060
8807 14:47:23.961016 [Calibration Summary] 3200 Mbps
8808 14:47:23.961099 CH 0, Rank 0
8809 14:47:23.964476 SW Impedance : PASS
8810 14:47:23.964559 DUTY Scan : NO K
8811 14:47:23.967746 ZQ Calibration : PASS
8812 14:47:23.971319 Jitter Meter : NO K
8813 14:47:23.971403 CBT Training : PASS
8814 14:47:23.975048 Write leveling : PASS
8815 14:47:23.978005 RX DQS gating : PASS
8816 14:47:23.978087 RX DQ/DQS(RDDQC) : PASS
8817 14:47:23.981251 TX DQ/DQS : PASS
8818 14:47:23.984493 RX DATLAT : PASS
8819 14:47:23.984575 RX DQ/DQS(Engine): PASS
8820 14:47:23.987967 TX OE : PASS
8821 14:47:23.988050 All Pass.
8822 14:47:23.988133
8823 14:47:23.991210 CH 0, Rank 1
8824 14:47:23.991315 SW Impedance : PASS
8825 14:47:23.994403 DUTY Scan : NO K
8826 14:47:23.994486 ZQ Calibration : PASS
8827 14:47:23.997857 Jitter Meter : NO K
8828 14:47:24.001084 CBT Training : PASS
8829 14:47:24.001191 Write leveling : PASS
8830 14:47:24.004636 RX DQS gating : PASS
8831 14:47:24.007837 RX DQ/DQS(RDDQC) : PASS
8832 14:47:24.007920 TX DQ/DQS : PASS
8833 14:47:24.011466 RX DATLAT : PASS
8834 14:47:24.014158 RX DQ/DQS(Engine): PASS
8835 14:47:24.014241 TX OE : PASS
8836 14:47:24.017813 All Pass.
8837 14:47:24.017919
8838 14:47:24.018002 CH 1, Rank 0
8839 14:47:24.020964 SW Impedance : PASS
8840 14:47:24.021047 DUTY Scan : NO K
8841 14:47:24.024491 ZQ Calibration : PASS
8842 14:47:24.027562 Jitter Meter : NO K
8843 14:47:24.027644 CBT Training : PASS
8844 14:47:24.030974 Write leveling : PASS
8845 14:47:24.034450 RX DQS gating : PASS
8846 14:47:24.034533 RX DQ/DQS(RDDQC) : PASS
8847 14:47:24.037322 TX DQ/DQS : PASS
8848 14:47:24.040895 RX DATLAT : PASS
8849 14:47:24.040995 RX DQ/DQS(Engine): PASS
8850 14:47:24.043944 TX OE : PASS
8851 14:47:24.044028 All Pass.
8852 14:47:24.044111
8853 14:47:24.047298 CH 1, Rank 1
8854 14:47:24.047380 SW Impedance : PASS
8855 14:47:24.050771 DUTY Scan : NO K
8856 14:47:24.054018 ZQ Calibration : PASS
8857 14:47:24.054101 Jitter Meter : NO K
8858 14:47:24.057242 CBT Training : PASS
8859 14:47:24.057355 Write leveling : PASS
8860 14:47:24.060457 RX DQS gating : PASS
8861 14:47:24.063860 RX DQ/DQS(RDDQC) : PASS
8862 14:47:24.063943 TX DQ/DQS : PASS
8863 14:47:24.067297 RX DATLAT : PASS
8864 14:47:24.070574 RX DQ/DQS(Engine): PASS
8865 14:47:24.070657 TX OE : PASS
8866 14:47:24.073840 All Pass.
8867 14:47:24.073923
8868 14:47:24.074006 DramC Write-DBI on
8869 14:47:24.077111 PER_BANK_REFRESH: Hybrid Mode
8870 14:47:24.080488 TX_TRACKING: ON
8871 14:47:24.087135 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8872 14:47:24.097141 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8873 14:47:24.103487 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8874 14:47:24.107001 [FAST_K] Save calibration result to emmc
8875 14:47:24.110166 sync common calibartion params.
8876 14:47:24.110248 sync cbt_mode0:0, 1:0
8877 14:47:24.113274 dram_init: ddr_geometry: 0
8878 14:47:24.117299 dram_init: ddr_geometry: 0
8879 14:47:24.120098 dram_init: ddr_geometry: 0
8880 14:47:24.120181 0:dram_rank_size:80000000
8881 14:47:24.123385 1:dram_rank_size:80000000
8882 14:47:24.129945 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8883 14:47:24.130029 DFS_SHUFFLE_HW_MODE: ON
8884 14:47:24.133178 dramc_set_vcore_voltage set vcore to 725000
8885 14:47:24.136697 Read voltage for 1600, 0
8886 14:47:24.136779 Vio18 = 0
8887 14:47:24.139912 Vcore = 725000
8888 14:47:24.140019 Vdram = 0
8889 14:47:24.140118 Vddq = 0
8890 14:47:24.143279 Vmddr = 0
8891 14:47:24.143361 switch to 3200 Mbps bootup
8892 14:47:24.146715 [DramcRunTimeConfig]
8893 14:47:24.146798 PHYPLL
8894 14:47:24.150267 DPM_CONTROL_AFTERK: ON
8895 14:47:24.150350 PER_BANK_REFRESH: ON
8896 14:47:24.153284 REFRESH_OVERHEAD_REDUCTION: ON
8897 14:47:24.156669 CMD_PICG_NEW_MODE: OFF
8898 14:47:24.156752 XRTWTW_NEW_MODE: ON
8899 14:47:24.159962 XRTRTR_NEW_MODE: ON
8900 14:47:24.160046 TX_TRACKING: ON
8901 14:47:24.163127 RDSEL_TRACKING: OFF
8902 14:47:24.166341 DQS Precalculation for DVFS: ON
8903 14:47:24.166424 RX_TRACKING: OFF
8904 14:47:24.169718 HW_GATING DBG: ON
8905 14:47:24.169801 ZQCS_ENABLE_LP4: ON
8906 14:47:24.173141 RX_PICG_NEW_MODE: ON
8907 14:47:24.173247 TX_PICG_NEW_MODE: ON
8908 14:47:24.176543 ENABLE_RX_DCM_DPHY: ON
8909 14:47:24.179800 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8910 14:47:24.183401 DUMMY_READ_FOR_TRACKING: OFF
8911 14:47:24.183484 !!! SPM_CONTROL_AFTERK: OFF
8912 14:47:24.186601 !!! SPM could not control APHY
8913 14:47:24.189941 IMPEDANCE_TRACKING: ON
8914 14:47:24.190023 TEMP_SENSOR: ON
8915 14:47:24.193043 HW_SAVE_FOR_SR: OFF
8916 14:47:24.196458 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8917 14:47:24.199785 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8918 14:47:24.199868 Read ODT Tracking: ON
8919 14:47:24.203073 Refresh Rate DeBounce: ON
8920 14:47:24.206380 DFS_NO_QUEUE_FLUSH: ON
8921 14:47:24.209749 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8922 14:47:24.213237 ENABLE_DFS_RUNTIME_MRW: OFF
8923 14:47:24.213341 DDR_RESERVE_NEW_MODE: ON
8924 14:47:24.216412 MR_CBT_SWITCH_FREQ: ON
8925 14:47:24.219778 =========================
8926 14:47:24.236705 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8927 14:47:24.240055 dram_init: ddr_geometry: 0
8928 14:47:24.258296 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8929 14:47:24.261664 dram_init: dram init end (result: 0)
8930 14:47:24.268122 DRAM-K: Full calibration passed in 23425 msecs
8931 14:47:24.271396 MRC: failed to locate region type 0.
8932 14:47:24.271480 DRAM rank0 size:0x80000000,
8933 14:47:24.274772 DRAM rank1 size=0x80000000
8934 14:47:24.284544 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8935 14:47:24.291238 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8936 14:47:24.298144 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8937 14:47:24.304464 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8938 14:47:24.308224 DRAM rank0 size:0x80000000,
8939 14:47:24.311137 DRAM rank1 size=0x80000000
8940 14:47:24.311220 CBMEM:
8941 14:47:24.314817 IMD: root @ 0xfffff000 254 entries.
8942 14:47:24.317877 IMD: root @ 0xffffec00 62 entries.
8943 14:47:24.321070 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8944 14:47:24.324500 WARNING: RO_VPD is uninitialized or empty.
8945 14:47:24.331115 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8946 14:47:24.337968 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8947 14:47:24.350351 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
8948 14:47:24.361721 BS: romstage times (exec / console): total (unknown) / 22962 ms
8949 14:47:24.361806
8950 14:47:24.361890
8951 14:47:24.371643 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8952 14:47:24.375191 ARM64: Exception handlers installed.
8953 14:47:24.378590 ARM64: Testing exception
8954 14:47:24.381946 ARM64: Done test exception
8955 14:47:24.382030 Enumerating buses...
8956 14:47:24.385136 Show all devs... Before device enumeration.
8957 14:47:24.388630 Root Device: enabled 1
8958 14:47:24.391670 CPU_CLUSTER: 0: enabled 1
8959 14:47:24.391753 CPU: 00: enabled 1
8960 14:47:24.395223 Compare with tree...
8961 14:47:24.395306 Root Device: enabled 1
8962 14:47:24.398051 CPU_CLUSTER: 0: enabled 1
8963 14:47:24.401882 CPU: 00: enabled 1
8964 14:47:24.401965 Root Device scanning...
8965 14:47:24.405082 scan_static_bus for Root Device
8966 14:47:24.407965 CPU_CLUSTER: 0 enabled
8967 14:47:24.411643 scan_static_bus for Root Device done
8968 14:47:24.414737 scan_bus: bus Root Device finished in 8 msecs
8969 14:47:24.414820 done
8970 14:47:24.421324 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8971 14:47:24.424436 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8972 14:47:24.431239 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8973 14:47:24.434450 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8974 14:47:24.437760 Allocating resources...
8975 14:47:24.440901 Reading resources...
8976 14:47:24.444298 Root Device read_resources bus 0 link: 0
8977 14:47:24.444381 DRAM rank0 size:0x80000000,
8978 14:47:24.447900 DRAM rank1 size=0x80000000
8979 14:47:24.450972 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8980 14:47:24.454627 CPU: 00 missing read_resources
8981 14:47:24.460909 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8982 14:47:24.464326 Root Device read_resources bus 0 link: 0 done
8983 14:47:24.464409 Done reading resources.
8984 14:47:24.471150 Show resources in subtree (Root Device)...After reading.
8985 14:47:24.474434 Root Device child on link 0 CPU_CLUSTER: 0
8986 14:47:24.477459 CPU_CLUSTER: 0 child on link 0 CPU: 00
8987 14:47:24.487440 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8988 14:47:24.487529 CPU: 00
8989 14:47:24.490590 Root Device assign_resources, bus 0 link: 0
8990 14:47:24.493849 CPU_CLUSTER: 0 missing set_resources
8991 14:47:24.500688 Root Device assign_resources, bus 0 link: 0 done
8992 14:47:24.500772 Done setting resources.
8993 14:47:24.507229 Show resources in subtree (Root Device)...After assigning values.
8994 14:47:24.510322 Root Device child on link 0 CPU_CLUSTER: 0
8995 14:47:24.513653 CPU_CLUSTER: 0 child on link 0 CPU: 00
8996 14:47:24.523726 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8997 14:47:24.523810 CPU: 00
8998 14:47:24.527153 Done allocating resources.
8999 14:47:24.533648 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9000 14:47:24.533731 Enabling resources...
9001 14:47:24.533815 done.
9002 14:47:24.540084 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9003 14:47:24.540168 Initializing devices...
9004 14:47:24.543619 Root Device init
9005 14:47:24.546699 init hardware done!
9006 14:47:24.546782 0x00000018: ctrlr->caps
9007 14:47:24.550001 52.000 MHz: ctrlr->f_max
9008 14:47:24.550086 0.400 MHz: ctrlr->f_min
9009 14:47:24.553434 0x40ff8080: ctrlr->voltages
9010 14:47:24.556810 sclk: 390625
9011 14:47:24.556893 Bus Width = 1
9012 14:47:24.556977 sclk: 390625
9013 14:47:24.560223 Bus Width = 1
9014 14:47:24.560306 Early init status = 3
9015 14:47:24.566503 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9016 14:47:24.569813 in-header: 03 fc 00 00 01 00 00 00
9017 14:47:24.573211 in-data: 00
9018 14:47:24.576195 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9019 14:47:24.580332 in-header: 03 fd 00 00 00 00 00 00
9020 14:47:24.583474 in-data:
9021 14:47:24.587444 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9022 14:47:24.590446 in-header: 03 fc 00 00 01 00 00 00
9023 14:47:24.593909 in-data: 00
9024 14:47:24.597093 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9025 14:47:24.601899 in-header: 03 fd 00 00 00 00 00 00
9026 14:47:24.605618 in-data:
9027 14:47:24.608300 [SSUSB] Setting up USB HOST controller...
9028 14:47:24.611937 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9029 14:47:24.615068 [SSUSB] phy power-on done.
9030 14:47:24.618330 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9031 14:47:24.625612 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9032 14:47:24.628156 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9033 14:47:24.635058 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9034 14:47:24.641938 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9035 14:47:24.648129 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9036 14:47:24.654984 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9037 14:47:24.662148 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9038 14:47:24.664939 SPM: binary array size = 0x9dc
9039 14:47:24.668542 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9040 14:47:24.675081 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9041 14:47:24.681638 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9042 14:47:24.685098 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9043 14:47:24.691277 configure_display: Starting display init
9044 14:47:24.725272 anx7625_power_on_init: Init interface.
9045 14:47:24.728907 anx7625_disable_pd_protocol: Disabled PD feature.
9046 14:47:24.732012 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9047 14:47:24.759761 anx7625_start_dp_work: Secure OCM version=00
9048 14:47:24.763097 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9049 14:47:24.778076 sp_tx_get_edid_block: EDID Block = 1
9050 14:47:24.881274 Extracted contents:
9051 14:47:24.884204 header: 00 ff ff ff ff ff ff 00
9052 14:47:24.887584 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9053 14:47:24.890459 version: 01 04
9054 14:47:24.893840 basic params: 95 1f 11 78 0a
9055 14:47:24.897646 chroma info: 76 90 94 55 54 90 27 21 50 54
9056 14:47:24.900784 established: 00 00 00
9057 14:47:24.907073 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9058 14:47:24.910281 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9059 14:47:24.917041 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9060 14:47:24.923678 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9061 14:47:24.930483 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9062 14:47:24.933602 extensions: 00
9063 14:47:24.934154 checksum: fb
9064 14:47:24.934510
9065 14:47:24.936702 Manufacturer: IVO Model 57d Serial Number 0
9066 14:47:24.940023 Made week 0 of 2020
9067 14:47:24.943434 EDID version: 1.4
9068 14:47:24.943987 Digital display
9069 14:47:24.946676 6 bits per primary color channel
9070 14:47:24.947141 DisplayPort interface
9071 14:47:24.950020 Maximum image size: 31 cm x 17 cm
9072 14:47:24.953348 Gamma: 220%
9073 14:47:24.953918 Check DPMS levels
9074 14:47:24.957264 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9075 14:47:24.963598 First detailed timing is preferred timing
9076 14:47:24.964170 Established timings supported:
9077 14:47:24.966242 Standard timings supported:
9078 14:47:24.969675 Detailed timings
9079 14:47:24.973094 Hex of detail: 383680a07038204018303c0035ae10000019
9080 14:47:24.979456 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9081 14:47:24.982851 0780 0798 07c8 0820 hborder 0
9082 14:47:24.986263 0438 043b 0447 0458 vborder 0
9083 14:47:24.989902 -hsync -vsync
9084 14:47:24.990463 Did detailed timing
9085 14:47:24.996227 Hex of detail: 000000000000000000000000000000000000
9086 14:47:24.999452 Manufacturer-specified data, tag 0
9087 14:47:25.002716 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9088 14:47:25.005866 ASCII string: InfoVision
9089 14:47:25.009205 Hex of detail: 000000fe00523134304e574635205248200a
9090 14:47:25.012912 ASCII string: R140NWF5 RH
9091 14:47:25.013544 Checksum
9092 14:47:25.015690 Checksum: 0xfb (valid)
9093 14:47:25.019086 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9094 14:47:25.022498 DSI data_rate: 832800000 bps
9095 14:47:25.029155 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9096 14:47:25.032401 anx7625_parse_edid: pixelclock(138800).
9097 14:47:25.035538 hactive(1920), hsync(48), hfp(24), hbp(88)
9098 14:47:25.038780 vactive(1080), vsync(12), vfp(3), vbp(17)
9099 14:47:25.042391 anx7625_dsi_config: config dsi.
9100 14:47:25.049156 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9101 14:47:25.062927 anx7625_dsi_config: success to config DSI
9102 14:47:25.066037 anx7625_dp_start: MIPI phy setup OK.
9103 14:47:25.069565 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9104 14:47:25.072733 mtk_ddp_mode_set invalid vrefresh 60
9105 14:47:25.075797 main_disp_path_setup
9106 14:47:25.076246 ovl_layer_smi_id_en
9107 14:47:25.079221 ovl_layer_smi_id_en
9108 14:47:25.079694 ccorr_config
9109 14:47:25.080273 aal_config
9110 14:47:25.082678 gamma_config
9111 14:47:25.083127 postmask_config
9112 14:47:25.085847 dither_config
9113 14:47:25.089118 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9114 14:47:25.096009 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9115 14:47:25.099115 Root Device init finished in 551 msecs
9116 14:47:25.102502 CPU_CLUSTER: 0 init
9117 14:47:25.109240 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9118 14:47:25.115379 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9119 14:47:25.115918 APU_MBOX 0x190000b0 = 0x10001
9120 14:47:25.118977 APU_MBOX 0x190001b0 = 0x10001
9121 14:47:25.122456 APU_MBOX 0x190005b0 = 0x10001
9122 14:47:25.125549 APU_MBOX 0x190006b0 = 0x10001
9123 14:47:25.132099 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9124 14:47:25.141973 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9125 14:47:25.154269 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9126 14:47:25.160638 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9127 14:47:25.172433 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9128 14:47:25.181423 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9129 14:47:25.184872 CPU_CLUSTER: 0 init finished in 81 msecs
9130 14:47:25.188100 Devices initialized
9131 14:47:25.191180 Show all devs... After init.
9132 14:47:25.191636 Root Device: enabled 1
9133 14:47:25.194860 CPU_CLUSTER: 0: enabled 1
9134 14:47:25.198020 CPU: 00: enabled 1
9135 14:47:25.201540 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9136 14:47:25.204566 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9137 14:47:25.207915 ELOG: NV offset 0x57f000 size 0x1000
9138 14:47:25.214668 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9139 14:47:25.221319 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9140 14:47:25.224824 ELOG: Event(17) added with size 13 at 2024-06-04 14:47:25 UTC
9141 14:47:25.228198 out: cmd=0x121: 03 db 21 01 00 00 00 00
9142 14:47:25.232718 in-header: 03 f0 00 00 2c 00 00 00
9143 14:47:25.245680 in-data: 73 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9144 14:47:25.252277 ELOG: Event(A1) added with size 10 at 2024-06-04 14:47:25 UTC
9145 14:47:25.258708 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9146 14:47:25.265588 ELOG: Event(A0) added with size 9 at 2024-06-04 14:47:25 UTC
9147 14:47:25.268653 elog_add_boot_reason: Logged dev mode boot
9148 14:47:25.272252 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9149 14:47:25.275284 Finalize devices...
9150 14:47:25.275840 Devices finalized
9151 14:47:25.281825 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9152 14:47:25.285171 Writing coreboot table at 0xffe64000
9153 14:47:25.288562 0. 000000000010a000-0000000000113fff: RAMSTAGE
9154 14:47:25.291662 1. 0000000040000000-00000000400fffff: RAM
9155 14:47:25.295453 2. 0000000040100000-000000004032afff: RAMSTAGE
9156 14:47:25.302538 3. 000000004032b000-00000000545fffff: RAM
9157 14:47:25.305260 4. 0000000054600000-000000005465ffff: BL31
9158 14:47:25.308565 5. 0000000054660000-00000000ffe63fff: RAM
9159 14:47:25.311987 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9160 14:47:25.318460 7. 0000000100000000-000000013fffffff: RAM
9161 14:47:25.318934 Passing 5 GPIOs to payload:
9162 14:47:25.325435 NAME | PORT | POLARITY | VALUE
9163 14:47:25.328506 EC in RW | 0x000000aa | low | undefined
9164 14:47:25.335447 EC interrupt | 0x00000005 | low | undefined
9165 14:47:25.338145 TPM interrupt | 0x000000ab | high | undefined
9166 14:47:25.341692 SD card detect | 0x00000011 | high | undefined
9167 14:47:25.348513 speaker enable | 0x00000093 | high | undefined
9168 14:47:25.351433 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9169 14:47:25.354959 in-header: 03 f8 00 00 02 00 00 00
9170 14:47:25.355538 in-data: 03 00
9171 14:47:25.358295 ADC[4]: Raw value=668958 ID=5
9172 14:47:25.362180 ADC[3]: Raw value=212917 ID=1
9173 14:47:25.362743 RAM Code: 0x51
9174 14:47:25.365087 ADC[6]: Raw value=74778 ID=0
9175 14:47:25.368264 ADC[5]: Raw value=211444 ID=1
9176 14:47:25.368827 SKU Code: 0x1
9177 14:47:25.374974 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 15c8
9178 14:47:25.378258 coreboot table: 964 bytes.
9179 14:47:25.381654 IMD ROOT 0. 0xfffff000 0x00001000
9180 14:47:25.384514 IMD SMALL 1. 0xffffe000 0x00001000
9181 14:47:25.388284 RO MCACHE 2. 0xffffc000 0x00001104
9182 14:47:25.391285 CONSOLE 3. 0xfff7c000 0x00080000
9183 14:47:25.394615 FMAP 4. 0xfff7b000 0x00000452
9184 14:47:25.397471 TIME STAMP 5. 0xfff7a000 0x00000910
9185 14:47:25.401370 VBOOT WORK 6. 0xfff66000 0x00014000
9186 14:47:25.404299 RAMOOPS 7. 0xffe66000 0x00100000
9187 14:47:25.408064 COREBOOT 8. 0xffe64000 0x00002000
9188 14:47:25.408622 IMD small region:
9189 14:47:25.411022 IMD ROOT 0. 0xffffec00 0x00000400
9190 14:47:25.413932 VPD 1. 0xffffeb80 0x0000006c
9191 14:47:25.417528 MMC STATUS 2. 0xffffeb60 0x00000004
9192 14:47:25.424342 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9193 14:47:25.427669 Probing TPM: done!
9194 14:47:25.430883 Connected to device vid:did:rid of 1ae0:0028:00
9195 14:47:25.440851 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9196 14:47:25.444069 Initialized TPM device CR50 revision 0
9197 14:47:25.448092 Checking cr50 for pending updates
9198 14:47:25.451045 Reading cr50 TPM mode
9199 14:47:25.460575 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9200 14:47:25.466795 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9201 14:47:25.506833 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9202 14:47:25.510278 Checking segment from ROM address 0x40100000
9203 14:47:25.513544 Checking segment from ROM address 0x4010001c
9204 14:47:25.519903 Loading segment from ROM address 0x40100000
9205 14:47:25.520359 code (compression=0)
9206 14:47:25.529749 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9207 14:47:25.536580 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9208 14:47:25.537069 it's not compressed!
9209 14:47:25.543021 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9210 14:47:25.549470 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9211 14:47:25.566822 Loading segment from ROM address 0x4010001c
9212 14:47:25.567363 Entry Point 0x80000000
9213 14:47:25.570258 Loaded segments
9214 14:47:25.573672 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9215 14:47:25.580820 Jumping to boot code at 0x80000000(0xffe64000)
9216 14:47:25.587143 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9217 14:47:25.593412 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9218 14:47:25.601377 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9219 14:47:25.604599 Checking segment from ROM address 0x40100000
9220 14:47:25.608282 Checking segment from ROM address 0x4010001c
9221 14:47:25.614999 Loading segment from ROM address 0x40100000
9222 14:47:25.615604 code (compression=1)
9223 14:47:25.621538 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9224 14:47:25.631227 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9225 14:47:25.631767 using LZMA
9226 14:47:25.639645 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9227 14:47:25.646503 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9228 14:47:25.649984 Loading segment from ROM address 0x4010001c
9229 14:47:25.650451 Entry Point 0x54601000
9230 14:47:25.653130 Loaded segments
9231 14:47:25.656270 NOTICE: MT8192 bl31_setup
9232 14:47:25.663695 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9233 14:47:25.666898 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9234 14:47:25.670177 WARNING: region 0:
9235 14:47:25.673571 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9236 14:47:25.674030 WARNING: region 1:
9237 14:47:25.680005 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9238 14:47:25.683418 WARNING: region 2:
9239 14:47:25.686625 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9240 14:47:25.690192 WARNING: region 3:
9241 14:47:25.693230 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9242 14:47:25.696808 WARNING: region 4:
9243 14:47:25.703353 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9244 14:47:25.703810 WARNING: region 5:
9245 14:47:25.706725 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9246 14:47:25.710221 WARNING: region 6:
9247 14:47:25.713772 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9248 14:47:25.716702 WARNING: region 7:
9249 14:47:25.720170 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9250 14:47:25.726684 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9251 14:47:25.729914 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9252 14:47:25.733492 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9253 14:47:25.740301 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9254 14:47:25.743247 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9255 14:47:25.747010 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9256 14:47:25.753276 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9257 14:47:25.756619 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9258 14:47:25.763231 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9259 14:47:25.766427 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9260 14:47:25.769838 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9261 14:47:25.776599 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9262 14:47:25.780336 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9263 14:47:25.783376 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9264 14:47:25.789610 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9265 14:47:25.793191 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9266 14:47:25.799834 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9267 14:47:25.803354 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9268 14:47:25.806626 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9269 14:47:25.812963 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9270 14:47:25.816171 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9271 14:47:25.820161 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9272 14:47:25.826810 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9273 14:47:25.829921 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9274 14:47:25.836456 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9275 14:47:25.839662 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9276 14:47:25.842975 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9277 14:47:25.850059 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9278 14:47:25.853027 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9279 14:47:25.859723 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9280 14:47:25.863176 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9281 14:47:25.866602 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9282 14:47:25.873545 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9283 14:47:25.876212 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9284 14:47:25.879792 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9285 14:47:25.883149 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9286 14:47:25.889583 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9287 14:47:25.893279 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9288 14:47:25.896351 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9289 14:47:25.899614 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9290 14:47:25.906498 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9291 14:47:25.909500 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9292 14:47:25.913017 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9293 14:47:25.916478 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9294 14:47:25.923047 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9295 14:47:25.926389 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9296 14:47:25.929742 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9297 14:47:25.933406 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9298 14:47:25.939670 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9299 14:47:25.943111 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9300 14:47:25.949896 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9301 14:47:25.953438 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9302 14:47:25.960255 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9303 14:47:25.963149 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9304 14:47:25.966715 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9305 14:47:25.973228 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9306 14:47:25.976570 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9307 14:47:25.983250 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9308 14:47:25.986177 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9309 14:47:25.992918 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9310 14:47:25.996462 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9311 14:47:25.999514 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9312 14:47:26.006630 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9313 14:47:26.009644 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9314 14:47:26.016170 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9315 14:47:26.019875 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9316 14:47:26.025800 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9317 14:47:26.029521 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9318 14:47:26.035759 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9319 14:47:26.039524 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9320 14:47:26.042703 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9321 14:47:26.049324 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9322 14:47:26.052623 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9323 14:47:26.059433 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9324 14:47:26.062627 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9325 14:47:26.069200 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9326 14:47:26.072593 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9327 14:47:26.076162 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9328 14:47:26.082701 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9329 14:47:26.085898 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9330 14:47:26.092215 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9331 14:47:26.095878 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9332 14:47:26.102089 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9333 14:47:26.105691 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9334 14:47:26.111956 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9335 14:47:26.115769 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9336 14:47:26.118874 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9337 14:47:26.125959 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9338 14:47:26.129099 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9339 14:47:26.136104 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9340 14:47:26.138838 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9341 14:47:26.145839 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9342 14:47:26.148709 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9343 14:47:26.155507 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9344 14:47:26.158840 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9345 14:47:26.161952 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9346 14:47:26.168853 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9347 14:47:26.172302 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9348 14:47:26.175652 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9349 14:47:26.178480 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9350 14:47:26.185045 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9351 14:47:26.188579 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9352 14:47:26.195641 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9353 14:47:26.198204 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9354 14:47:26.201648 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9355 14:47:26.208408 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9356 14:47:26.211624 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9357 14:47:26.218745 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9358 14:47:26.221664 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9359 14:47:26.224917 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9360 14:47:26.231545 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9361 14:47:26.234861 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9362 14:47:26.241598 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9363 14:47:26.244725 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9364 14:47:26.248213 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9365 14:47:26.254844 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9366 14:47:26.257999 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9367 14:47:26.261379 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9368 14:47:26.268171 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9369 14:47:26.270985 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9370 14:47:26.275089 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9371 14:47:26.277878 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9372 14:47:26.284525 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9373 14:47:26.288037 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9374 14:47:26.291077 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9375 14:47:26.297950 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9376 14:47:26.301445 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9377 14:47:26.304684 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9378 14:47:26.311166 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9379 14:47:26.314624 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9380 14:47:26.321441 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9381 14:47:26.324823 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9382 14:47:26.328137 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9383 14:47:26.334673 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9384 14:47:26.338505 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9385 14:47:26.344802 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9386 14:47:26.348166 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9387 14:47:26.351356 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9388 14:47:26.357960 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9389 14:47:26.361121 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9390 14:47:26.368108 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9391 14:47:26.371114 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9392 14:47:26.374361 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9393 14:47:26.381161 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9394 14:47:26.384292 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9395 14:47:26.390703 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9396 14:47:26.394016 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9397 14:47:26.397811 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9398 14:47:26.404309 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9399 14:47:26.407155 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9400 14:47:26.414160 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9401 14:47:26.417442 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9402 14:47:26.420725 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9403 14:47:26.427749 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9404 14:47:26.430794 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9405 14:47:26.433882 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9406 14:47:26.440869 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9407 14:47:26.444493 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9408 14:47:26.450916 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9409 14:47:26.453978 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9410 14:47:26.457458 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9411 14:47:26.464148 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9412 14:47:26.467373 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9413 14:47:26.473809 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9414 14:47:26.477198 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9415 14:47:26.480706 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9416 14:47:26.486900 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9417 14:47:26.490089 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9418 14:47:26.497018 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9419 14:47:26.500709 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9420 14:47:26.503690 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9421 14:47:26.509964 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9422 14:47:26.513362 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9423 14:47:26.520260 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9424 14:47:26.523078 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9425 14:47:26.526735 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9426 14:47:26.533165 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9427 14:47:26.537350 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9428 14:47:26.542953 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9429 14:47:26.546787 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9430 14:47:26.549964 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9431 14:47:26.556696 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9432 14:47:26.559686 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9433 14:47:26.566349 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9434 14:47:26.569680 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9435 14:47:26.573265 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9436 14:47:26.579641 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9437 14:47:26.583473 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9438 14:47:26.589311 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9439 14:47:26.592976 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9440 14:47:26.596018 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9441 14:47:26.602381 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9442 14:47:26.605821 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9443 14:47:26.612719 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9444 14:47:26.615967 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9445 14:47:26.619139 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9446 14:47:26.625873 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9447 14:47:26.629340 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9448 14:47:26.635663 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9449 14:47:26.639277 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9450 14:47:26.645650 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9451 14:47:26.649185 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9452 14:47:26.652270 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9453 14:47:26.659099 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9454 14:47:26.662003 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9455 14:47:26.668888 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9456 14:47:26.672230 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9457 14:47:26.678640 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9458 14:47:26.681946 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9459 14:47:26.685382 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9460 14:47:26.691949 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9461 14:47:26.695379 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9462 14:47:26.701684 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9463 14:47:26.704782 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9464 14:47:26.712055 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9465 14:47:26.714932 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9466 14:47:26.718218 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9467 14:47:26.724712 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9468 14:47:26.728261 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9469 14:47:26.734999 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9470 14:47:26.738338 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9471 14:47:26.744488 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9472 14:47:26.748097 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9473 14:47:26.750926 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9474 14:47:26.757570 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9475 14:47:26.760787 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9476 14:47:26.767834 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9477 14:47:26.770770 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9478 14:47:26.774483 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9479 14:47:26.780965 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9480 14:47:26.784395 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9481 14:47:26.787307 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9482 14:47:26.790858 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9483 14:47:26.797256 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9484 14:47:26.800725 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9485 14:47:26.803729 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9486 14:47:26.810476 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9487 14:47:26.813611 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9488 14:47:26.817001 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9489 14:47:26.823842 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9490 14:47:26.827272 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9491 14:47:26.833658 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9492 14:47:26.836863 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9493 14:47:26.840036 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9494 14:47:26.846748 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9495 14:47:26.850225 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9496 14:47:26.856726 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9497 14:47:26.860176 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9498 14:47:26.863466 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9499 14:47:26.870008 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9500 14:47:26.873283 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9501 14:47:26.876535 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9502 14:47:26.883197 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9503 14:47:26.886283 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9504 14:47:26.892900 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9505 14:47:26.896627 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9506 14:47:26.899553 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9507 14:47:26.906059 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9508 14:47:26.909463 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9509 14:47:26.912721 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9510 14:47:26.919123 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9511 14:47:26.922733 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9512 14:47:26.929342 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9513 14:47:26.932463 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9514 14:47:26.935688 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9515 14:47:26.942423 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9516 14:47:26.945894 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9517 14:47:26.949159 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9518 14:47:26.955822 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9519 14:47:26.959546 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9520 14:47:26.962361 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9521 14:47:26.965641 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9522 14:47:26.972281 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9523 14:47:26.975354 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9524 14:47:26.979055 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9525 14:47:26.982055 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9526 14:47:26.988677 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9527 14:47:26.991906 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9528 14:47:26.995291 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9529 14:47:26.998638 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9530 14:47:27.005369 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9531 14:47:27.008472 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9532 14:47:27.012119 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9533 14:47:27.018204 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9534 14:47:27.021687 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9535 14:47:27.028207 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9536 14:47:27.031280 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9537 14:47:27.038101 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9538 14:47:27.041206 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9539 14:47:27.044562 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9540 14:47:27.051291 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9541 14:47:27.054545 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9542 14:47:27.061352 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9543 14:47:27.064210 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9544 14:47:27.071105 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9545 14:47:27.074730 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9546 14:47:27.077843 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9547 14:47:27.084275 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9548 14:47:27.087921 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9549 14:47:27.094336 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9550 14:47:27.097737 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9551 14:47:27.101017 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9552 14:47:27.107754 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9553 14:47:27.110660 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9554 14:47:27.117446 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9555 14:47:27.121064 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9556 14:47:27.124336 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9557 14:47:27.130639 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9558 14:47:27.134307 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9559 14:47:27.140582 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9560 14:47:27.143941 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9561 14:47:27.150282 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9562 14:47:27.153652 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9563 14:47:27.156924 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9564 14:47:27.163502 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9565 14:47:27.166758 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9566 14:47:27.173836 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9567 14:47:27.176727 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9568 14:47:27.183100 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9569 14:47:27.186653 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9570 14:47:27.190058 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9571 14:47:27.196555 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9572 14:47:27.200346 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9573 14:47:27.203268 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9574 14:47:27.210400 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9575 14:47:27.213171 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9576 14:47:27.219840 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9577 14:47:27.223481 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9578 14:47:27.230012 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9579 14:47:27.233207 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9580 14:47:27.236192 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9581 14:47:27.242995 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9582 14:47:27.246445 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9583 14:47:27.253097 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9584 14:47:27.256507 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9585 14:47:27.262544 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9586 14:47:27.265936 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9587 14:47:27.269384 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9588 14:47:27.275914 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9589 14:47:27.279221 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9590 14:47:27.285867 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9591 14:47:27.289349 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9592 14:47:27.292652 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9593 14:47:27.299223 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9594 14:47:27.302419 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9595 14:47:27.308844 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9596 14:47:27.312037 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9597 14:47:27.315493 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9598 14:47:27.322130 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9599 14:47:27.325492 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9600 14:47:27.332346 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9601 14:47:27.335922 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9602 14:47:27.341904 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9603 14:47:27.345384 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9604 14:47:27.348711 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9605 14:47:27.355126 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9606 14:47:27.358326 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9607 14:47:27.364955 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9608 14:47:27.368274 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9609 14:47:27.375288 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9610 14:47:27.378659 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9611 14:47:27.381926 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9612 14:47:27.388737 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9613 14:47:27.391753 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9614 14:47:27.398684 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9615 14:47:27.401400 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9616 14:47:27.408092 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9617 14:47:27.411295 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9618 14:47:27.417812 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9619 14:47:27.421253 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9620 14:47:27.424578 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9621 14:47:27.431091 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9622 14:47:27.434885 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9623 14:47:27.441247 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9624 14:47:27.444478 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9625 14:47:27.451117 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9626 14:47:27.454296 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9627 14:47:27.460779 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9628 14:47:27.464416 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9629 14:47:27.467793 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9630 14:47:27.474142 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9631 14:47:27.477110 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9632 14:47:27.484310 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9633 14:47:27.487318 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9634 14:47:27.493744 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9635 14:47:27.497115 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9636 14:47:27.503817 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9637 14:47:27.506984 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9638 14:47:27.510313 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9639 14:47:27.517088 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9640 14:47:27.520294 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9641 14:47:27.527157 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9642 14:47:27.529989 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9643 14:47:27.537208 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9644 14:47:27.539875 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9645 14:47:27.546734 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9646 14:47:27.550165 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9647 14:47:27.553533 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9648 14:47:27.560216 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9649 14:47:27.563613 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9650 14:47:27.569823 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9651 14:47:27.573228 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9652 14:47:27.579782 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9653 14:47:27.582744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9654 14:47:27.586106 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9655 14:47:27.592746 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9656 14:47:27.595898 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9657 14:47:27.602738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9658 14:47:27.605944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9659 14:47:27.612406 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9660 14:47:27.616000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9661 14:47:27.622282 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9662 14:47:27.625579 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9663 14:47:27.632194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9664 14:47:27.635570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9665 14:47:27.642209 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9666 14:47:27.645260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9667 14:47:27.652068 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9668 14:47:27.655577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9669 14:47:27.661884 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9670 14:47:27.664982 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9671 14:47:27.671708 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9672 14:47:27.675311 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9673 14:47:27.681646 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9674 14:47:27.685025 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9675 14:47:27.691825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9676 14:47:27.694715 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9677 14:47:27.701430 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9678 14:47:27.704784 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9679 14:47:27.711396 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9680 14:47:27.715098 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9681 14:47:27.721148 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9682 14:47:27.724815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9683 14:47:27.731531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9684 14:47:27.735564 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9685 14:47:27.737750 INFO: [APUAPC] vio 0
9686 14:47:27.740941 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9687 14:47:27.747545 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9688 14:47:27.750941 INFO: [APUAPC] D0_APC_0: 0x400510
9689 14:47:27.754333 INFO: [APUAPC] D0_APC_1: 0x0
9690 14:47:27.757342 INFO: [APUAPC] D0_APC_2: 0x1540
9691 14:47:27.758018 INFO: [APUAPC] D0_APC_3: 0x0
9692 14:47:27.763985 INFO: [APUAPC] D1_APC_0: 0xffffffff
9693 14:47:27.767423 INFO: [APUAPC] D1_APC_1: 0xffffffff
9694 14:47:27.770638 INFO: [APUAPC] D1_APC_2: 0x3fffff
9695 14:47:27.771304 INFO: [APUAPC] D1_APC_3: 0x0
9696 14:47:27.773888 INFO: [APUAPC] D2_APC_0: 0xffffffff
9697 14:47:27.780853 INFO: [APUAPC] D2_APC_1: 0xffffffff
9698 14:47:27.783775 INFO: [APUAPC] D2_APC_2: 0x3fffff
9699 14:47:27.784328 INFO: [APUAPC] D2_APC_3: 0x0
9700 14:47:27.787016 INFO: [APUAPC] D3_APC_0: 0xffffffff
9701 14:47:27.793547 INFO: [APUAPC] D3_APC_1: 0xffffffff
9702 14:47:27.796852 INFO: [APUAPC] D3_APC_2: 0x3fffff
9703 14:47:27.797284 INFO: [APUAPC] D3_APC_3: 0x0
9704 14:47:27.799863 INFO: [APUAPC] D4_APC_0: 0xffffffff
9705 14:47:27.803363 INFO: [APUAPC] D4_APC_1: 0xffffffff
9706 14:47:27.806971 INFO: [APUAPC] D4_APC_2: 0x3fffff
9707 14:47:27.809901 INFO: [APUAPC] D4_APC_3: 0x0
9708 14:47:27.813219 INFO: [APUAPC] D5_APC_0: 0xffffffff
9709 14:47:27.816693 INFO: [APUAPC] D5_APC_1: 0xffffffff
9710 14:47:27.820138 INFO: [APUAPC] D5_APC_2: 0x3fffff
9711 14:47:27.823214 INFO: [APUAPC] D5_APC_3: 0x0
9712 14:47:27.826351 INFO: [APUAPC] D6_APC_0: 0xffffffff
9713 14:47:27.829684 INFO: [APUAPC] D6_APC_1: 0xffffffff
9714 14:47:27.833694 INFO: [APUAPC] D6_APC_2: 0x3fffff
9715 14:47:27.836459 INFO: [APUAPC] D6_APC_3: 0x0
9716 14:47:27.839623 INFO: [APUAPC] D7_APC_0: 0xffffffff
9717 14:47:27.843273 INFO: [APUAPC] D7_APC_1: 0xffffffff
9718 14:47:27.846802 INFO: [APUAPC] D7_APC_2: 0x3fffff
9719 14:47:27.849665 INFO: [APUAPC] D7_APC_3: 0x0
9720 14:47:27.853043 INFO: [APUAPC] D8_APC_0: 0xffffffff
9721 14:47:27.856696 INFO: [APUAPC] D8_APC_1: 0xffffffff
9722 14:47:27.859843 INFO: [APUAPC] D8_APC_2: 0x3fffff
9723 14:47:27.862763 INFO: [APUAPC] D8_APC_3: 0x0
9724 14:47:27.866997 INFO: [APUAPC] D9_APC_0: 0xffffffff
9725 14:47:27.869616 INFO: [APUAPC] D9_APC_1: 0xffffffff
9726 14:47:27.873674 INFO: [APUAPC] D9_APC_2: 0x3fffff
9727 14:47:27.876423 INFO: [APUAPC] D9_APC_3: 0x0
9728 14:47:27.879913 INFO: [APUAPC] D10_APC_0: 0xffffffff
9729 14:47:27.883271 INFO: [APUAPC] D10_APC_1: 0xffffffff
9730 14:47:27.886009 INFO: [APUAPC] D10_APC_2: 0x3fffff
9731 14:47:27.889628 INFO: [APUAPC] D10_APC_3: 0x0
9732 14:47:27.893039 INFO: [APUAPC] D11_APC_0: 0xffffffff
9733 14:47:27.896134 INFO: [APUAPC] D11_APC_1: 0xffffffff
9734 14:47:27.899498 INFO: [APUAPC] D11_APC_2: 0x3fffff
9735 14:47:27.902902 INFO: [APUAPC] D11_APC_3: 0x0
9736 14:47:27.906032 INFO: [APUAPC] D12_APC_0: 0xffffffff
9737 14:47:27.909094 INFO: [APUAPC] D12_APC_1: 0xffffffff
9738 14:47:27.912401 INFO: [APUAPC] D12_APC_2: 0x3fffff
9739 14:47:27.915860 INFO: [APUAPC] D12_APC_3: 0x0
9740 14:47:27.919158 INFO: [APUAPC] D13_APC_0: 0xffffffff
9741 14:47:27.922219 INFO: [APUAPC] D13_APC_1: 0xffffffff
9742 14:47:27.925754 INFO: [APUAPC] D13_APC_2: 0x3fffff
9743 14:47:27.928758 INFO: [APUAPC] D13_APC_3: 0x0
9744 14:47:27.932096 INFO: [APUAPC] D14_APC_0: 0xffffffff
9745 14:47:27.935430 INFO: [APUAPC] D14_APC_1: 0xffffffff
9746 14:47:27.938718 INFO: [APUAPC] D14_APC_2: 0x3fffff
9747 14:47:27.941980 INFO: [APUAPC] D14_APC_3: 0x0
9748 14:47:27.945459 INFO: [APUAPC] D15_APC_0: 0xffffffff
9749 14:47:27.948699 INFO: [APUAPC] D15_APC_1: 0xffffffff
9750 14:47:27.951986 INFO: [APUAPC] D15_APC_2: 0x3fffff
9751 14:47:27.955195 INFO: [APUAPC] D15_APC_3: 0x0
9752 14:47:27.958539 INFO: [APUAPC] APC_CON: 0x4
9753 14:47:27.961897 INFO: [NOCDAPC] D0_APC_0: 0x0
9754 14:47:27.965179 INFO: [NOCDAPC] D0_APC_1: 0x0
9755 14:47:27.968440 INFO: [NOCDAPC] D1_APC_0: 0x0
9756 14:47:27.971752 INFO: [NOCDAPC] D1_APC_1: 0xfff
9757 14:47:27.975482 INFO: [NOCDAPC] D2_APC_0: 0x0
9758 14:47:27.978428 INFO: [NOCDAPC] D2_APC_1: 0xfff
9759 14:47:27.978963 INFO: [NOCDAPC] D3_APC_0: 0x0
9760 14:47:27.981582 INFO: [NOCDAPC] D3_APC_1: 0xfff
9761 14:47:27.985099 INFO: [NOCDAPC] D4_APC_0: 0x0
9762 14:47:27.988482 INFO: [NOCDAPC] D4_APC_1: 0xfff
9763 14:47:27.991296 INFO: [NOCDAPC] D5_APC_0: 0x0
9764 14:47:27.994851 INFO: [NOCDAPC] D5_APC_1: 0xfff
9765 14:47:27.997949 INFO: [NOCDAPC] D6_APC_0: 0x0
9766 14:47:28.001458 INFO: [NOCDAPC] D6_APC_1: 0xfff
9767 14:47:28.004571 INFO: [NOCDAPC] D7_APC_0: 0x0
9768 14:47:28.007993 INFO: [NOCDAPC] D7_APC_1: 0xfff
9769 14:47:28.011361 INFO: [NOCDAPC] D8_APC_0: 0x0
9770 14:47:28.015128 INFO: [NOCDAPC] D8_APC_1: 0xfff
9771 14:47:28.015663 INFO: [NOCDAPC] D9_APC_0: 0x0
9772 14:47:28.017893 INFO: [NOCDAPC] D9_APC_1: 0xfff
9773 14:47:28.021237 INFO: [NOCDAPC] D10_APC_0: 0x0
9774 14:47:28.024641 INFO: [NOCDAPC] D10_APC_1: 0xfff
9775 14:47:28.027790 INFO: [NOCDAPC] D11_APC_0: 0x0
9776 14:47:28.031217 INFO: [NOCDAPC] D11_APC_1: 0xfff
9777 14:47:28.034410 INFO: [NOCDAPC] D12_APC_0: 0x0
9778 14:47:28.037824 INFO: [NOCDAPC] D12_APC_1: 0xfff
9779 14:47:28.041126 INFO: [NOCDAPC] D13_APC_0: 0x0
9780 14:47:28.044395 INFO: [NOCDAPC] D13_APC_1: 0xfff
9781 14:47:28.047848 INFO: [NOCDAPC] D14_APC_0: 0x0
9782 14:47:28.050834 INFO: [NOCDAPC] D14_APC_1: 0xfff
9783 14:47:28.054426 INFO: [NOCDAPC] D15_APC_0: 0x0
9784 14:47:28.057478 INFO: [NOCDAPC] D15_APC_1: 0xfff
9785 14:47:28.057898 INFO: [NOCDAPC] APC_CON: 0x4
9786 14:47:28.063972 INFO: [APUAPC] set_apusys_apc done
9787 14:47:28.064385 INFO: [DEVAPC] devapc_init done
9788 14:47:28.070726 INFO: GICv3 without legacy support detected.
9789 14:47:28.073992 INFO: ARM GICv3 driver initialized in EL3
9790 14:47:28.077047 INFO: Maximum SPI INTID supported: 639
9791 14:47:28.080315 INFO: BL31: Initializing runtime services
9792 14:47:28.087254 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9793 14:47:28.090716 INFO: SPM: enable CPC mode
9794 14:47:28.094067 INFO: mcdi ready for mcusys-off-idle and system suspend
9795 14:47:28.100785 INFO: BL31: Preparing for EL3 exit to normal world
9796 14:47:28.103836 INFO: Entry point address = 0x80000000
9797 14:47:28.106899 INFO: SPSR = 0x8
9798 14:47:28.111239
9799 14:47:28.111746
9800 14:47:28.112077
9801 14:47:28.114600 Starting depthcharge on Spherion...
9802 14:47:28.115014
9803 14:47:28.115337 Wipe memory regions:
9804 14:47:28.115787
9805 14:47:28.118233 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9806 14:47:28.118726 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9807 14:47:28.119267 Setting prompt string to ['asurada:']
9808 14:47:28.119695 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9809 14:47:28.120342 [0x00000040000000, 0x00000054600000)
9810 14:47:28.240426
9811 14:47:28.241156 [0x00000054660000, 0x00000080000000)
9812 14:47:28.500584
9813 14:47:28.501131 [0x000000821a7280, 0x000000ffe64000)
9814 14:47:29.245820
9815 14:47:29.246372 [0x00000100000000, 0x00000140000000)
9816 14:47:29.627103
9817 14:47:29.630163 Initializing XHCI USB controller at 0x11200000.
9818 14:47:30.667861
9819 14:47:30.671821 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9820 14:47:30.672338
9821 14:47:30.672668
9822 14:47:30.673440 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9824 14:47:30.774676 asurada: tftpboot 192.168.201.1 14167017/tftp-deploy-lmyx8m5s/kernel/image.itb 14167017/tftp-deploy-lmyx8m5s/kernel/cmdline
9825 14:47:30.775320 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9826 14:47:30.775994 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9827 14:47:30.780628 tftpboot 192.168.201.1 14167017/tftp-deploy-lmyx8m5s/kernel/image.ittp-deploy-lmyx8m5s/kernel/cmdline
9828 14:47:30.781196
9829 14:47:30.781623 Waiting for link
9830 14:47:30.940707
9831 14:47:30.941229 R8152: Initializing
9832 14:47:30.941623
9833 14:47:30.943811 Version 9 (ocp_data = 6010)
9834 14:47:30.944271
9835 14:47:30.947332 R8152: Done initializing
9836 14:47:30.948049
9837 14:47:30.948427 Adding net device
9838 14:47:32.913721
9839 14:47:32.914267 done.
9840 14:47:32.914641
9841 14:47:32.914987 MAC: 00:e0:4c:68:03:bd
9842 14:47:32.915307
9843 14:47:32.916824 Sending DHCP discover... done.
9844 14:47:32.917430
9845 14:47:32.919850 Waiting for reply... done.
9846 14:47:32.919943
9847 14:47:32.923102 Sending DHCP request... done.
9848 14:47:32.923185
9849 14:47:32.929148 Waiting for reply... done.
9850 14:47:32.929233
9851 14:47:32.929306 My ip is 192.168.201.16
9852 14:47:32.929370
9853 14:47:32.931752 The DHCP server ip is 192.168.201.1
9854 14:47:32.931843
9855 14:47:32.938316 TFTP server IP predefined by user: 192.168.201.1
9856 14:47:32.938446
9857 14:47:32.945002 Bootfile predefined by user: 14167017/tftp-deploy-lmyx8m5s/kernel/image.itb
9858 14:47:32.945155
9859 14:47:32.948045 Sending tftp read request... done.
9860 14:47:32.948161
9861 14:47:32.952113 Waiting for the transfer...
9862 14:47:32.952242
9863 14:47:33.299125 00000000 ################################################################
9864 14:47:33.299275
9865 14:47:33.594651 00080000 ################################################################
9866 14:47:33.594842
9867 14:47:33.983242 00100000 ################################################################
9868 14:47:33.983804
9869 14:47:34.373593 00180000 ################################################################
9870 14:47:34.374124
9871 14:47:34.754197 00200000 ################################################################
9872 14:47:34.754730
9873 14:47:35.151544 00280000 ################################################################
9874 14:47:35.152050
9875 14:47:35.553504 00300000 ################################################################
9876 14:47:35.554085
9877 14:47:35.936921 00380000 ################################################################
9878 14:47:35.937483
9879 14:47:36.254586 00400000 ################################################################
9880 14:47:36.254721
9881 14:47:36.552670 00480000 ################################################################
9882 14:47:36.552804
9883 14:47:36.844128 00500000 ################################################################
9884 14:47:36.844261
9885 14:47:37.133607 00580000 ################################################################
9886 14:47:37.133739
9887 14:47:37.420904 00600000 ################################################################
9888 14:47:37.421035
9889 14:47:37.694896 00680000 ################################################################
9890 14:47:37.695027
9891 14:47:38.060314 00700000 ################################################################
9892 14:47:38.060795
9893 14:47:38.441626 00780000 ################################################################
9894 14:47:38.442185
9895 14:47:38.844070 00800000 ################################################################
9896 14:47:38.844686
9897 14:47:39.251582 00880000 ################################################################
9898 14:47:39.252142
9899 14:47:39.636646 00900000 ################################################################
9900 14:47:39.637137
9901 14:47:39.963271 00980000 ################################################################
9902 14:47:39.963408
9903 14:47:40.229458 00a00000 ################################################################
9904 14:47:40.229587
9905 14:47:40.525714 00a80000 ################################################################
9906 14:47:40.525850
9907 14:47:40.794922 00b00000 ################################################################
9908 14:47:40.795055
9909 14:47:41.132432 00b80000 ################################################################
9910 14:47:41.132560
9911 14:47:41.403181 00c00000 ################################################################
9912 14:47:41.403321
9913 14:47:41.698440 00c80000 ################################################################
9914 14:47:41.698605
9915 14:47:41.960168 00d00000 ################################################################
9916 14:47:41.960297
9917 14:47:42.235604 00d80000 ################################################################
9918 14:47:42.235739
9919 14:47:42.519476 00e00000 ################################################################
9920 14:47:42.519618
9921 14:47:42.811269 00e80000 ################################################################
9922 14:47:42.811409
9923 14:47:43.095430 00f00000 ################################################################
9924 14:47:43.095578
9925 14:47:43.380022 00f80000 ################################################################
9926 14:47:43.380169
9927 14:47:43.681264 01000000 ################################################################
9928 14:47:43.681418
9929 14:47:43.970153 01080000 ################################################################
9930 14:47:43.970305
9931 14:47:44.253583 01100000 ################################################################
9932 14:47:44.253724
9933 14:47:44.533690 01180000 ################################################################
9934 14:47:44.533833
9935 14:47:44.816527 01200000 ################################################################
9936 14:47:44.816663
9937 14:47:45.100815 01280000 ################################################################
9938 14:47:45.100952
9939 14:47:45.394761 01300000 ################################################################
9940 14:47:45.394902
9941 14:47:45.681681 01380000 ################################################################
9942 14:47:45.681828
9943 14:47:45.980028 01400000 ################################################################
9944 14:47:45.980170
9945 14:47:46.280544 01480000 ################################################################
9946 14:47:46.280688
9947 14:47:46.574437 01500000 ################################################################
9948 14:47:46.574592
9949 14:47:46.855517 01580000 ################################################################
9950 14:47:46.855661
9951 14:47:47.244791 01600000 ################################################################
9952 14:47:47.245317
9953 14:47:47.643575 01680000 ################################################################
9954 14:47:47.644093
9955 14:47:47.945879 01700000 ################################################################
9956 14:47:47.946051
9957 14:47:48.243853 01780000 ################################################################
9958 14:47:48.243991
9959 14:47:48.537484 01800000 ################################################################
9960 14:47:48.537652
9961 14:47:48.835956 01880000 ################################################################
9962 14:47:48.836094
9963 14:47:49.125103 01900000 ################################################################
9964 14:47:49.125268
9965 14:47:49.393036 01980000 ################################################################
9966 14:47:49.393178
9967 14:47:49.685223 01a00000 ################################################################
9968 14:47:49.685403
9969 14:47:49.972362 01a80000 ################################################################
9970 14:47:49.972499
9971 14:47:50.269587 01b00000 ################################################################
9972 14:47:50.269724
9973 14:47:50.533795 01b80000 ################################################################
9974 14:47:50.533946
9975 14:47:50.792862 01c00000 ################################################################
9976 14:47:50.792999
9977 14:47:51.134788 01c80000 ################################################################
9978 14:47:51.134934
9979 14:47:51.527724 01d00000 ################################################################
9980 14:47:51.528288
9981 14:47:51.884292 01d80000 ################################################################
9982 14:47:51.884440
9983 14:47:52.102204 01e00000 ############################################### done.
9984 14:47:52.102337
9985 14:47:52.105360 The bootfile was 31839918 bytes long.
9986 14:47:52.105451
9987 14:47:52.108851 Sending tftp read request... done.
9988 14:47:52.108997
9989 14:47:52.109099 Waiting for the transfer...
9990 14:47:52.109193
9991 14:47:52.112079 00000000 # done.
9992 14:47:52.112255
9993 14:47:52.119017 Command line loaded dynamically from TFTP file: 14167017/tftp-deploy-lmyx8m5s/kernel/cmdline
9994 14:47:52.119197
9995 14:47:52.141776 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14167017/extract-nfsrootfs-oz49gv4g,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
9996 14:47:52.142042
9997 14:47:52.142190 Loading FIT.
9998 14:47:52.142329
9999 14:47:52.145383 Image ramdisk-1 has 18730005 bytes.
10000 14:47:52.145666
10001 14:47:52.148673 Image fdt-1 has 47258 bytes.
10002 14:47:52.148967
10003 14:47:52.152034 Image kernel-1 has 13060619 bytes.
10004 14:47:52.152363
10005 14:47:52.161907 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10006 14:47:52.162300
10007 14:47:52.178435 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10008 14:47:52.179009
10009 14:47:52.185333 Choosing best match conf-1 for compat google,spherion-rev3.
10010 14:47:52.188308
10011 14:47:52.193070 Connected to device vid:did:rid of 1ae0:0028:00
10012 14:47:52.199981
10013 14:47:52.203564 tpm_get_response: command 0x17b, return code 0x0
10014 14:47:52.204125
10015 14:47:52.206742 ec_init: CrosEC protocol v3 supported (256, 248)
10016 14:47:52.209900
10017 14:47:52.212938 tpm_cleanup: add release locality here.
10018 14:47:52.213447
10019 14:47:52.216422 Shutting down all USB controllers.
10020 14:47:52.216885
10021 14:47:52.220554 Removing current net device
10022 14:47:52.221114
10023 14:47:52.223128 Exiting depthcharge with code 4 at timestamp: 52343763
10024 14:47:52.223593
10025 14:47:52.226610 LZMA decompressing kernel-1 to 0x821a6718
10026 14:47:52.227091
10027 14:47:52.233226 LZMA decompressing kernel-1 to 0x40000000
10028 14:47:53.842679
10029 14:47:53.843235 jumping to kernel
10030 14:47:53.844982 end: 2.2.4 bootloader-commands (duration 00:00:26) [common]
10031 14:47:53.845580 start: 2.2.5 auto-login-action (timeout 00:04:01) [common]
10032 14:47:53.846077 Setting prompt string to ['Linux version [0-9]']
10033 14:47:53.846457 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10034 14:47:53.846828 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10035 14:47:53.894116
10036 14:47:53.897423 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10037 14:47:53.900890 start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10038 14:47:53.901451 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10039 14:47:53.901861 Setting prompt string to []
10040 14:47:53.902274 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10041 14:47:53.902666 Using line separator: #'\n'#
10042 14:47:53.902998 No login prompt set.
10043 14:47:53.903333 Parsing kernel messages
10044 14:47:53.903835 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10045 14:47:53.904430 [login-action] Waiting for messages, (timeout 00:04:01)
10046 14:47:53.904802 Waiting using forced prompt support (timeout 00:02:00)
10047 14:47:53.920208 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j216541-arm64-gcc-10-defconfig-arm64-chromebook-f7c97) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024
10048 14:47:53.923749 [ 0.000000] random: crng init done
10049 14:47:53.930520 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10050 14:47:53.933524 [ 0.000000] efi: UEFI not found.
10051 14:47:53.939916 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10052 14:47:53.949857 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10053 14:47:53.959973 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10054 14:47:53.966357 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10055 14:47:53.972831 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10056 14:47:53.979659 [ 0.000000] printk: bootconsole [mtk8250] enabled
10057 14:47:53.986193 [ 0.000000] NUMA: No NUMA configuration found
10058 14:47:53.992536 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10059 14:47:53.999248 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10060 14:47:53.999802 [ 0.000000] Zone ranges:
10061 14:47:54.006078 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10062 14:47:54.009504 [ 0.000000] DMA32 empty
10063 14:47:54.015683 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10064 14:47:54.019056 [ 0.000000] Movable zone start for each node
10065 14:47:54.022374 [ 0.000000] Early memory node ranges
10066 14:47:54.029130 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10067 14:47:54.035622 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10068 14:47:54.042071 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10069 14:47:54.048792 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10070 14:47:54.055555 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10071 14:47:54.062075 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10072 14:47:54.092336 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10073 14:47:54.098681 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10074 14:47:54.105688 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10075 14:47:54.109273 [ 0.000000] psci: probing for conduit method from DT.
10076 14:47:54.115437 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10077 14:47:54.118751 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10078 14:47:54.125573 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10079 14:47:54.128896 [ 0.000000] psci: SMC Calling Convention v1.2
10080 14:47:54.135562 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10081 14:47:54.139427 [ 0.000000] Detected VIPT I-cache on CPU0
10082 14:47:54.145234 [ 0.000000] CPU features: detected: GIC system register CPU interface
10083 14:47:54.151834 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10084 14:47:54.158288 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10085 14:47:54.164662 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10086 14:47:54.174639 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10087 14:47:54.181202 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10088 14:47:54.184324 [ 0.000000] alternatives: applying boot alternatives
10089 14:47:54.190913 [ 0.000000] Fallback order for Node 0: 0
10090 14:47:54.198192 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10091 14:47:54.200988 [ 0.000000] Policy zone: Normal
10092 14:47:54.224358 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14167017/extract-nfsrootfs-oz49gv4g,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10093 14:47:54.234231 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10094 14:47:54.244298 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10095 14:47:54.254146 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10096 14:47:54.257755 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10097 14:47:54.263784 <6>[ 0.000000] software IO TLB: area num 8.
10098 14:47:54.319630 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10099 14:47:54.399539 <6>[ 0.000000] Memory: 3831484K/4191232K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 326980K reserved, 32768K cma-reserved)
10100 14:47:54.406349 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10101 14:47:54.413112 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10102 14:47:54.416186 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10103 14:47:54.422822 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10104 14:47:54.429508 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10105 14:47:54.432737 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10106 14:47:54.442786 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10107 14:47:54.449009 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10108 14:47:54.455834 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10109 14:47:54.462450 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10110 14:47:54.465843 <6>[ 0.000000] GICv3: 608 SPIs implemented
10111 14:47:54.468877 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10112 14:47:54.475645 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10113 14:47:54.479112 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10114 14:47:54.485436 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10115 14:47:54.498705 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10116 14:47:54.511770 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10117 14:47:54.518519 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10118 14:47:54.526227 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10119 14:47:54.539664 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10120 14:47:54.546006 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10121 14:47:54.552975 <6>[ 0.009225] Console: colour dummy device 80x25
10122 14:47:54.562553 <6>[ 0.013952] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10123 14:47:54.569801 <6>[ 0.024394] pid_max: default: 32768 minimum: 301
10124 14:47:54.572776 <6>[ 0.029264] LSM: Security Framework initializing
10125 14:47:54.578962 <6>[ 0.034175] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10126 14:47:54.589235 <6>[ 0.041782] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10127 14:47:54.595788 <6>[ 0.051019] cblist_init_generic: Setting adjustable number of callback queues.
10128 14:47:54.602326 <6>[ 0.058509] cblist_init_generic: Setting shift to 3 and lim to 1.
10129 14:47:54.612139 <6>[ 0.064848] cblist_init_generic: Setting adjustable number of callback queues.
10130 14:47:54.618775 <6>[ 0.072321] cblist_init_generic: Setting shift to 3 and lim to 1.
10131 14:47:54.621870 <6>[ 0.078721] rcu: Hierarchical SRCU implementation.
10132 14:47:54.628742 <6>[ 0.083768] rcu: Max phase no-delay instances is 1000.
10133 14:47:54.635673 <6>[ 0.090834] EFI services will not be available.
10134 14:47:54.638809 <6>[ 0.095821] smp: Bringing up secondary CPUs ...
10135 14:47:54.646815 <6>[ 0.100869] Detected VIPT I-cache on CPU1
10136 14:47:54.653539 <6>[ 0.100936] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10137 14:47:54.660171 <6>[ 0.100967] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10138 14:47:54.663089 <6>[ 0.101299] Detected VIPT I-cache on CPU2
10139 14:47:54.673476 <6>[ 0.101346] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10140 14:47:54.679634 <6>[ 0.101363] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10141 14:47:54.683285 <6>[ 0.101619] Detected VIPT I-cache on CPU3
10142 14:47:54.689566 <6>[ 0.101666] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10143 14:47:54.697001 <6>[ 0.101680] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10144 14:47:54.699860 <6>[ 0.101983] CPU features: detected: Spectre-v4
10145 14:47:54.706336 <6>[ 0.101989] CPU features: detected: Spectre-BHB
10146 14:47:54.709524 <6>[ 0.101995] Detected PIPT I-cache on CPU4
10147 14:47:54.716161 <6>[ 0.102051] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10148 14:47:54.722853 <6>[ 0.102067] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10149 14:47:54.729757 <6>[ 0.102358] Detected PIPT I-cache on CPU5
10150 14:47:54.736203 <6>[ 0.102420] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10151 14:47:54.742560 <6>[ 0.102436] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10152 14:47:54.745999 <6>[ 0.102715] Detected PIPT I-cache on CPU6
10153 14:47:54.752551 <6>[ 0.102775] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10154 14:47:54.759034 <6>[ 0.102791] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10155 14:47:54.765667 <6>[ 0.103091] Detected PIPT I-cache on CPU7
10156 14:47:54.772517 <6>[ 0.103155] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10157 14:47:54.778857 <6>[ 0.103171] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10158 14:47:54.781886 <6>[ 0.103219] smp: Brought up 1 node, 8 CPUs
10159 14:47:54.788760 <6>[ 0.244631] SMP: Total of 8 processors activated.
10160 14:47:54.792119 <6>[ 0.249552] CPU features: detected: 32-bit EL0 Support
10161 14:47:54.801885 <6>[ 0.254915] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10162 14:47:54.808550 <6>[ 0.263715] CPU features: detected: Common not Private translations
10163 14:47:54.815201 <6>[ 0.270231] CPU features: detected: CRC32 instructions
10164 14:47:54.821602 <6>[ 0.275583] CPU features: detected: RCpc load-acquire (LDAPR)
10165 14:47:54.824936 <6>[ 0.281580] CPU features: detected: LSE atomic instructions
10166 14:47:54.831657 <6>[ 0.287397] CPU features: detected: Privileged Access Never
10167 14:47:54.838274 <6>[ 0.293212] CPU features: detected: RAS Extension Support
10168 14:47:54.844738 <6>[ 0.298821] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10169 14:47:54.848207 <6>[ 0.306083] CPU: All CPU(s) started at EL2
10170 14:47:54.854521 <6>[ 0.310400] alternatives: applying system-wide alternatives
10171 14:47:54.863691 <6>[ 0.320393] devtmpfs: initialized
10172 14:47:54.878996 <6>[ 0.328613] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10173 14:47:54.885267 <6>[ 0.338574] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10174 14:47:54.892007 <6>[ 0.346492] pinctrl core: initialized pinctrl subsystem
10175 14:47:54.894866 <6>[ 0.353146] DMI not present or invalid.
10176 14:47:54.901555 <6>[ 0.357546] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10177 14:47:54.911422 <6>[ 0.364382] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10178 14:47:54.917937 <6>[ 0.371831] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10179 14:47:54.927564 <6>[ 0.379923] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10180 14:47:54.931088 <6>[ 0.388078] audit: initializing netlink subsys (disabled)
10181 14:47:54.941221 <5>[ 0.393774] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10182 14:47:54.947692 <6>[ 0.394470] thermal_sys: Registered thermal governor 'step_wise'
10183 14:47:54.954262 <6>[ 0.401741] thermal_sys: Registered thermal governor 'power_allocator'
10184 14:47:54.957460 <6>[ 0.407997] cpuidle: using governor menu
10185 14:47:54.963929 <6>[ 0.418951] NET: Registered PF_QIPCRTR protocol family
10186 14:47:54.970856 <6>[ 0.424436] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10187 14:47:54.977244 <6>[ 0.431538] ASID allocator initialised with 32768 entries
10188 14:47:54.980723 <6>[ 0.438089] Serial: AMBA PL011 UART driver
10189 14:47:54.990133 <4>[ 0.446822] Trying to register duplicate clock ID: 134
10190 14:47:55.048639 <6>[ 0.508355] KASLR enabled
10191 14:47:55.062992 <6>[ 0.516054] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10192 14:47:55.069157 <6>[ 0.523068] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10193 14:47:55.076288 <6>[ 0.529558] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10194 14:47:55.082725 <6>[ 0.536564] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10195 14:47:55.088963 <6>[ 0.543050] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10196 14:47:55.095746 <6>[ 0.550053] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10197 14:47:55.102269 <6>[ 0.556539] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10198 14:47:55.108822 <6>[ 0.563543] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10199 14:47:55.112025 <6>[ 0.571052] ACPI: Interpreter disabled.
10200 14:47:55.120747 <6>[ 0.577468] iommu: Default domain type: Translated
10201 14:47:55.127755 <6>[ 0.582581] iommu: DMA domain TLB invalidation policy: strict mode
10202 14:47:55.130724 <5>[ 0.589237] SCSI subsystem initialized
10203 14:47:55.137472 <6>[ 0.593401] usbcore: registered new interface driver usbfs
10204 14:47:55.144014 <6>[ 0.599131] usbcore: registered new interface driver hub
10205 14:47:55.147220 <6>[ 0.604683] usbcore: registered new device driver usb
10206 14:47:55.154258 <6>[ 0.610773] pps_core: LinuxPPS API ver. 1 registered
10207 14:47:55.164155 <6>[ 0.615966] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10208 14:47:55.167171 <6>[ 0.625310] PTP clock support registered
10209 14:47:55.170728 <6>[ 0.629551] EDAC MC: Ver: 3.0.0
10210 14:47:55.178240 <6>[ 0.634701] FPGA manager framework
10211 14:47:55.184557 <6>[ 0.638386] Advanced Linux Sound Architecture Driver Initialized.
10212 14:47:55.187780 <6>[ 0.645154] vgaarb: loaded
10213 14:47:55.194548 <6>[ 0.648308] clocksource: Switched to clocksource arch_sys_counter
10214 14:47:55.197791 <5>[ 0.654748] VFS: Disk quotas dquot_6.6.0
10215 14:47:55.204859 <6>[ 0.658931] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10216 14:47:55.207622 <6>[ 0.666119] pnp: PnP ACPI: disabled
10217 14:47:55.216355 <6>[ 0.672756] NET: Registered PF_INET protocol family
10218 14:47:55.222547 <6>[ 0.678137] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10219 14:47:55.234824 <6>[ 0.688150] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10220 14:47:55.245034 <6>[ 0.696933] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10221 14:47:55.251328 <6>[ 0.704898] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10222 14:47:55.258176 <6>[ 0.713302] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10223 14:47:55.268719 <6>[ 0.721958] TCP: Hash tables configured (established 32768 bind 32768)
10224 14:47:55.275310 <6>[ 0.728814] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10225 14:47:55.281798 <6>[ 0.735834] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10226 14:47:55.288634 <6>[ 0.743354] NET: Registered PF_UNIX/PF_LOCAL protocol family
10227 14:47:55.294805 <6>[ 0.749495] RPC: Registered named UNIX socket transport module.
10228 14:47:55.298222 <6>[ 0.755647] RPC: Registered udp transport module.
10229 14:47:55.304903 <6>[ 0.760579] RPC: Registered tcp transport module.
10230 14:47:55.311864 <6>[ 0.765509] RPC: Registered tcp NFSv4.1 backchannel transport module.
10231 14:47:55.314944 <6>[ 0.772178] PCI: CLS 0 bytes, default 64
10232 14:47:55.318491 <6>[ 0.776467] Unpacking initramfs...
10233 14:47:55.328012 <6>[ 0.780520] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10234 14:47:55.334457 <6>[ 0.789139] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10235 14:47:55.341176 <6>[ 0.797910] kvm [1]: IPA Size Limit: 40 bits
10236 14:47:55.344561 <6>[ 0.802436] kvm [1]: GICv3: no GICV resource entry
10237 14:47:55.351350 <6>[ 0.807456] kvm [1]: disabling GICv2 emulation
10238 14:47:55.357979 <6>[ 0.812141] kvm [1]: GIC system register CPU interface enabled
10239 14:47:55.361169 <6>[ 0.818292] kvm [1]: vgic interrupt IRQ18
10240 14:47:55.367582 <6>[ 0.822665] kvm [1]: VHE mode initialized successfully
10241 14:47:55.370961 <5>[ 0.829151] Initialise system trusted keyrings
10242 14:47:55.377408 <6>[ 0.833975] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10243 14:47:55.387428 <6>[ 0.843960] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10244 14:47:55.393883 <5>[ 0.850332] NFS: Registering the id_resolver key type
10245 14:47:55.397124 <5>[ 0.855634] Key type id_resolver registered
10246 14:47:55.403696 <5>[ 0.860046] Key type id_legacy registered
10247 14:47:55.410334 <6>[ 0.864332] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10248 14:47:55.417120 <6>[ 0.871254] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10249 14:47:55.423816 <6>[ 0.878973] 9p: Installing v9fs 9p2000 file system support
10250 14:47:55.460882 <5>[ 0.917065] Key type asymmetric registered
10251 14:47:55.463563 <5>[ 0.921396] Asymmetric key parser 'x509' registered
10252 14:47:55.473854 <6>[ 0.926536] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10253 14:47:55.477201 <6>[ 0.934149] io scheduler mq-deadline registered
10254 14:47:55.480319 <6>[ 0.938908] io scheduler kyber registered
10255 14:47:55.499421 <6>[ 0.955917] EINJ: ACPI disabled.
10256 14:47:55.531901 <4>[ 0.981870] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10257 14:47:55.541921 <4>[ 0.992509] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10258 14:47:55.556979 <6>[ 1.013364] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10259 14:47:55.564974 <6>[ 1.021327] printk: console [ttyS0] disabled
10260 14:47:55.593137 <6>[ 1.045968] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10261 14:47:55.599491 <6>[ 1.055449] printk: console [ttyS0] enabled
10262 14:47:55.602763 <6>[ 1.055449] printk: console [ttyS0] enabled
10263 14:47:55.609251 <6>[ 1.064347] printk: bootconsole [mtk8250] disabled
10264 14:47:55.612374 <6>[ 1.064347] printk: bootconsole [mtk8250] disabled
10265 14:47:55.619420 <6>[ 1.075418] SuperH (H)SCI(F) driver initialized
10266 14:47:55.622510 <6>[ 1.080704] msm_serial: driver initialized
10267 14:47:55.636163 <6>[ 1.089602] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10268 14:47:55.646831 <6>[ 1.098150] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10269 14:47:55.653324 <6>[ 1.106692] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10270 14:47:55.663315 <6>[ 1.115319] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10271 14:47:55.669958 <6>[ 1.124026] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10272 14:47:55.679599 <6>[ 1.132748] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10273 14:47:55.689509 <6>[ 1.141291] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10274 14:47:55.695996 <6>[ 1.150084] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10275 14:47:55.706006 <6>[ 1.158627] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10276 14:47:55.717545 <6>[ 1.174128] loop: module loaded
10277 14:47:55.724172 <6>[ 1.180022] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10278 14:47:55.746857 <4>[ 1.203262] mtk-pmic-keys: Failed to locate of_node [id: -1]
10279 14:47:55.753437 <6>[ 1.210062] megasas: 07.719.03.00-rc1
10280 14:47:55.763010 <6>[ 1.219408] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10281 14:47:55.771629 <6>[ 1.227693] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10282 14:47:55.787683 <6>[ 1.244287] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10283 14:47:55.843994 <6>[ 1.293682] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10284 14:47:56.149448 <6>[ 1.605848] Freeing initrd memory: 18288K
10285 14:47:56.160956 <6>[ 1.617494] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10286 14:47:56.171757 <6>[ 1.628639] tun: Universal TUN/TAP device driver, 1.6
10287 14:47:56.175385 <6>[ 1.634713] thunder_xcv, ver 1.0
10288 14:47:56.178412 <6>[ 1.638220] thunder_bgx, ver 1.0
10289 14:47:56.181868 <6>[ 1.641714] nicpf, ver 1.0
10290 14:47:56.192611 <6>[ 1.645733] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10291 14:47:56.196019 <6>[ 1.653213] hns3: Copyright (c) 2017 Huawei Corporation.
10292 14:47:56.202517 <6>[ 1.658804] hclge is initializing
10293 14:47:56.205419 <6>[ 1.662386] e1000: Intel(R) PRO/1000 Network Driver
10294 14:47:56.212078 <6>[ 1.667515] e1000: Copyright (c) 1999-2006 Intel Corporation.
10295 14:47:56.215592 <6>[ 1.673526] e1000e: Intel(R) PRO/1000 Network Driver
10296 14:47:56.222052 <6>[ 1.678741] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10297 14:47:56.228942 <6>[ 1.684927] igb: Intel(R) Gigabit Ethernet Network Driver
10298 14:47:56.235302 <6>[ 1.690576] igb: Copyright (c) 2007-2014 Intel Corporation.
10299 14:47:56.241989 <6>[ 1.696416] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10300 14:47:56.248776 <6>[ 1.702934] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10301 14:47:56.251992 <6>[ 1.709394] sky2: driver version 1.30
10302 14:47:56.258716 <6>[ 1.714326] usbcore: registered new device driver r8152-cfgselector
10303 14:47:56.265357 <6>[ 1.720861] usbcore: registered new interface driver r8152
10304 14:47:56.271666 <6>[ 1.726678] VFIO - User Level meta-driver version: 0.3
10305 14:47:56.278396 <6>[ 1.734894] usbcore: registered new interface driver usb-storage
10306 14:47:56.285027 <6>[ 1.741339] usbcore: registered new device driver onboard-usb-hub
10307 14:47:56.293887 <6>[ 1.750487] mt6397-rtc mt6359-rtc: registered as rtc0
10308 14:47:56.303670 <6>[ 1.755948] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T14:47:56 UTC (1717512476)
10309 14:47:56.306832 <6>[ 1.765511] i2c_dev: i2c /dev entries driver
10310 14:47:56.324184 <6>[ 1.777254] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10311 14:47:56.330611 <4>[ 1.785975] cpu cpu0: supply cpu not found, using dummy regulator
10312 14:47:56.336982 <4>[ 1.792396] cpu cpu1: supply cpu not found, using dummy regulator
10313 14:47:56.344267 <4>[ 1.798800] cpu cpu2: supply cpu not found, using dummy regulator
10314 14:47:56.350330 <4>[ 1.805201] cpu cpu3: supply cpu not found, using dummy regulator
10315 14:47:56.357218 <4>[ 1.811615] cpu cpu4: supply cpu not found, using dummy regulator
10316 14:47:56.364044 <4>[ 1.818013] cpu cpu5: supply cpu not found, using dummy regulator
10317 14:47:56.370684 <4>[ 1.824408] cpu cpu6: supply cpu not found, using dummy regulator
10318 14:47:56.373724 <4>[ 1.830803] cpu cpu7: supply cpu not found, using dummy regulator
10319 14:47:56.395115 <6>[ 1.851427] cpu cpu0: EM: created perf domain
10320 14:47:56.397843 <6>[ 1.856341] cpu cpu4: EM: created perf domain
10321 14:47:56.405097 <6>[ 1.861904] sdhci: Secure Digital Host Controller Interface driver
10322 14:47:56.411923 <6>[ 1.868338] sdhci: Copyright(c) Pierre Ossman
10323 14:47:56.418532 <6>[ 1.873255] Synopsys Designware Multimedia Card Interface Driver
10324 14:47:56.425170 <6>[ 1.879851] sdhci-pltfm: SDHCI platform and OF driver helper
10325 14:47:56.428534 <6>[ 1.879906] mmc0: CQHCI version 5.10
10326 14:47:56.434969 <6>[ 1.890199] ledtrig-cpu: registered to indicate activity on CPUs
10327 14:47:56.441758 <6>[ 1.897195] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10328 14:47:56.448420 <6>[ 1.904189] usbcore: registered new interface driver usbhid
10329 14:47:56.451790 <6>[ 1.910011] usbhid: USB HID core driver
10330 14:47:56.458105 <6>[ 1.914210] spi_master spi0: will run message pump with realtime priority
10331 14:47:56.501263 <6>[ 1.951334] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10332 14:47:56.519762 <6>[ 1.966439] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10333 14:47:56.527016 <6>[ 1.981406] cros-ec-spi spi0.0: Chrome EC device registered
10334 14:47:56.530210 <6>[ 1.987442] mmc0: Command Queue Engine enabled
10335 14:47:56.536683 <6>[ 1.992193] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10336 14:47:56.546749 <6>[ 1.999406] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10337 14:47:56.553309 <6>[ 1.999498] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10338 14:47:56.556590 <6>[ 2.009641] NET: Registered PF_PACKET protocol family
10339 14:47:56.562983 <6>[ 2.018197] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10340 14:47:56.566445 <6>[ 2.018886] 9pnet: Installing 9P2000 support
10341 14:47:56.573201 <6>[ 2.026071] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10342 14:47:56.576841 <5>[ 2.029277] Key type dns_resolver registered
10343 14:47:56.583544 <6>[ 2.035095] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10344 14:47:56.586237 <6>[ 2.039420] registered taskstats version 1
10345 14:47:56.592815 <6>[ 2.044872] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10346 14:47:56.599315 <5>[ 2.048584] Loading compiled-in X.509 certificates
10347 14:47:56.626512 <4>[ 2.076734] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10348 14:47:56.636253 <4>[ 2.087430] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10349 14:47:56.650805 <6>[ 2.107064] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10350 14:47:56.657135 <6>[ 2.113803] xhci-mtk 11200000.usb: xHCI Host Controller
10351 14:47:56.663816 <6>[ 2.119303] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10352 14:47:56.673907 <6>[ 2.127160] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10353 14:47:56.680562 <6>[ 2.136587] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10354 14:47:56.686884 <6>[ 2.142743] xhci-mtk 11200000.usb: xHCI Host Controller
10355 14:47:56.693588 <6>[ 2.148234] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10356 14:47:56.700124 <6>[ 2.155909] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10357 14:47:56.706879 <6>[ 2.163738] hub 1-0:1.0: USB hub found
10358 14:47:56.710585 <6>[ 2.167767] hub 1-0:1.0: 1 port detected
10359 14:47:56.717349 <6>[ 2.172067] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10360 14:47:56.724124 <6>[ 2.180876] hub 2-0:1.0: USB hub found
10361 14:47:56.727478 <6>[ 2.184903] hub 2-0:1.0: 1 port detected
10362 14:47:56.735727 <6>[ 2.192699] mtk-msdc 11f70000.mmc: Got CD GPIO
10363 14:47:56.748541 <6>[ 2.201962] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10364 14:47:56.755073 <6>[ 2.209987] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10365 14:47:56.765163 <4>[ 2.217931] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10366 14:47:56.774884 <6>[ 2.227504] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10367 14:47:56.782036 <6>[ 2.235585] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10368 14:47:56.788327 <6>[ 2.243605] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10369 14:47:56.797960 <6>[ 2.251523] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10370 14:47:56.804606 <6>[ 2.259342] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10371 14:47:56.814857 <6>[ 2.267159] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10372 14:47:56.825013 <6>[ 2.277570] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10373 14:47:56.831563 <6>[ 2.285933] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10374 14:47:56.841204 <6>[ 2.294280] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10375 14:47:56.848070 <6>[ 2.302618] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10376 14:47:56.858011 <6>[ 2.310955] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10377 14:47:56.864453 <6>[ 2.319293] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10378 14:47:56.874509 <6>[ 2.327631] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10379 14:47:56.881325 <6>[ 2.335968] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10380 14:47:56.891022 <6>[ 2.344306] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10381 14:47:56.900499 <6>[ 2.352644] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10382 14:47:56.907483 <6>[ 2.360981] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10383 14:47:56.917173 <6>[ 2.369319] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10384 14:47:56.924057 <6>[ 2.377657] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10385 14:47:56.933893 <6>[ 2.385995] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10386 14:47:56.940554 <6>[ 2.394332] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10387 14:47:56.946934 <6>[ 2.403064] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10388 14:47:56.953583 <6>[ 2.410201] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10389 14:47:56.960317 <6>[ 2.416957] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10390 14:47:56.970586 <6>[ 2.423678] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10391 14:47:56.977018 <6>[ 2.430601] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10392 14:47:56.983363 <6>[ 2.437441] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10393 14:47:56.993468 <6>[ 2.446571] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10394 14:47:57.003600 <6>[ 2.455691] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10395 14:47:57.013166 <6>[ 2.464984] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10396 14:47:57.023335 <6>[ 2.474451] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10397 14:47:57.029745 <6>[ 2.483917] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10398 14:47:57.039616 <6>[ 2.493036] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10399 14:47:57.049457 <6>[ 2.502503] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10400 14:47:57.059329 <6>[ 2.511622] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10401 14:47:57.069050 <6>[ 2.520916] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10402 14:47:57.079385 <6>[ 2.531076] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10403 14:47:57.089659 <6>[ 2.542939] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10404 14:47:57.096283 <6>[ 2.552656] Trying to probe devices needed for running init ...
10405 14:47:57.135098 <6>[ 2.588580] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10406 14:47:57.289734 <6>[ 2.746365] hub 1-1:1.0: USB hub found
10407 14:47:57.293018 <6>[ 2.750747] hub 1-1:1.0: 4 ports detected
10408 14:47:57.301768 <6>[ 2.758702] hub 1-1:1.0: USB hub found
10409 14:47:57.305257 <6>[ 2.763125] hub 1-1:1.0: 4 ports detected
10410 14:47:57.415309 <6>[ 2.868929] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10411 14:47:57.441816 <6>[ 2.898469] hub 2-1:1.0: USB hub found
10412 14:47:57.445119 <6>[ 2.903002] hub 2-1:1.0: 3 ports detected
10413 14:47:57.454139 <6>[ 2.911101] hub 2-1:1.0: USB hub found
10414 14:47:57.457564 <6>[ 2.915547] hub 2-1:1.0: 3 ports detected
10415 14:47:57.631011 <6>[ 3.084607] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10416 14:47:57.763290 <6>[ 3.220090] hub 1-1.4:1.0: USB hub found
10417 14:47:57.766919 <6>[ 3.224668] hub 1-1.4:1.0: 2 ports detected
10418 14:47:57.774669 <6>[ 3.231337] hub 1-1.4:1.0: USB hub found
10419 14:47:57.777794 <6>[ 3.235820] hub 1-1.4:1.0: 2 ports detected
10420 14:47:57.846805 <6>[ 3.300713] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10421 14:47:57.955221 <6>[ 3.409201] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10422 14:47:57.991432 <4>[ 3.444817] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10423 14:47:58.001208 <4>[ 3.453928] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10424 14:47:58.041376 <6>[ 3.498134] r8152 2-1.3:1.0 eth0: v1.12.13
10425 14:47:58.078996 <6>[ 3.532624] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10426 14:47:58.271149 <6>[ 3.724463] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10427 14:47:59.655336 <6>[ 5.112249] r8152 2-1.3:1.0 eth0: carrier on
10428 14:47:59.691516 <5>[ 5.132360] Sending DHCP requests ., OK
10429 14:47:59.698007 <6>[ 5.152744] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10430 14:47:59.701233 <6>[ 5.161014] IP-Config: Complete:
10431 14:47:59.714315 <6>[ 5.164497] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10432 14:47:59.721492 <6>[ 5.175190] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10433 14:47:59.727754 <6>[ 5.183796] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10434 14:47:59.734391 <6>[ 5.183801] nameserver0=192.168.201.1
10435 14:47:59.737524 <6>[ 5.195872] clk: Disabling unused clocks
10436 14:47:59.741037 <6>[ 5.200966] ALSA device list:
10437 14:47:59.744266 <6>[ 5.204242] No soundcards found.
10438 14:47:59.754396 <6>[ 5.211461] Freeing unused kernel memory: 8512K
10439 14:47:59.757426 <6>[ 5.216654] Run /init as init process
10440 14:47:59.768461 Loading, please wait...
10441 14:47:59.791065 Starting systemd-udevd version 252.22-1~deb12u1
10442 14:47:59.998230 <6>[ 5.451999] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10443 14:48:00.010118 <6>[ 5.463862] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10444 14:48:00.019893 <6>[ 5.473795] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10445 14:48:00.044715 <6>[ 5.498632] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10446 14:48:00.051727 <6>[ 5.501456] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10447 14:48:00.058395 <3>[ 5.502889] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10448 14:48:00.068085 <3>[ 5.502897] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10449 14:48:00.074932 <3>[ 5.502901] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10450 14:48:00.085106 <3>[ 5.502938] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10451 14:48:00.091279 <3>[ 5.502941] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10452 14:48:00.101144 <3>[ 5.502943] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10453 14:48:00.107675 <3>[ 5.502947] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10454 14:48:00.117664 <3>[ 5.502949] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10455 14:48:00.124359 <3>[ 5.502981] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10456 14:48:00.134432 <3>[ 5.503003] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10457 14:48:00.141007 <3>[ 5.503005] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10458 14:48:00.150849 <3>[ 5.503007] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10459 14:48:00.157943 <3>[ 5.503020] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10460 14:48:00.167671 <3>[ 5.503022] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10461 14:48:00.174365 <3>[ 5.503024] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10462 14:48:00.181189 <3>[ 5.503026] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10463 14:48:00.191363 <3>[ 5.503028] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10464 14:48:00.198146 <3>[ 5.503040] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10465 14:48:00.205408 <6>[ 5.522389] mc: Linux media interface: v0.10
10466 14:48:00.208424 <6>[ 5.523670] remoteproc remoteproc0: scp is available
10467 14:48:00.215060 <6>[ 5.523757] remoteproc remoteproc0: powering up scp
10468 14:48:00.221664 <6>[ 5.523762] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10469 14:48:00.228542 <6>[ 5.523793] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10470 14:48:00.235006 <4>[ 5.540777] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10471 14:48:00.241404 <6>[ 5.555005] videodev: Linux video capture interface: v2.00
10472 14:48:00.248364 <4>[ 5.564685] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10473 14:48:00.258068 <4>[ 5.573857] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10474 14:48:00.261373 <4>[ 5.573857] Fallback method does not support PEC.
10475 14:48:00.267654 <6>[ 5.601694] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10476 14:48:00.277439 <3>[ 5.620810] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10477 14:48:00.284434 <6>[ 5.628648] pci_bus 0000:00: root bus resource [bus 00-ff]
10478 14:48:00.294466 <6>[ 5.637306] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10479 14:48:00.300865 <6>[ 5.644859] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10480 14:48:00.310847 <6>[ 5.644862] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10481 14:48:00.317671 <6>[ 5.644903] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10482 14:48:00.323795 <6>[ 5.649533] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10483 14:48:00.334006 <6>[ 5.653612] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10484 14:48:00.340598 <3>[ 5.656554] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10485 14:48:00.350631 <6>[ 5.661047] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10486 14:48:00.357232 <6>[ 5.661055] remoteproc remoteproc0: remote processor scp is now up
10487 14:48:00.364160 <6>[ 5.661291] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10488 14:48:00.373556 <6>[ 5.717105] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10489 14:48:00.376712 <6>[ 5.724095] pci 0000:00:00.0: supports D1 D2
10490 14:48:00.386556 <6>[ 5.747613] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10491 14:48:00.393047 <6>[ 5.755545] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10492 14:48:00.396521 <6>[ 5.756392] Bluetooth: Core ver 2.22
10493 14:48:00.406653 <6>[ 5.756491] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10494 14:48:00.409629 <6>[ 5.756631] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10495 14:48:00.419562 <6>[ 5.756664] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10496 14:48:00.426276 <6>[ 5.756682] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10497 14:48:00.432902 <6>[ 5.756699] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10498 14:48:00.439315 <6>[ 5.756810] pci 0000:01:00.0: supports D1 D2
10499 14:48:00.446197 <6>[ 5.756811] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10500 14:48:00.452949 <6>[ 5.764611] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10501 14:48:00.459215 <6>[ 5.772651] NET: Registered PF_BLUETOOTH protocol family
10502 14:48:00.466100 <6>[ 5.779065] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10503 14:48:00.473119 <6>[ 5.785895] Bluetooth: HCI device and connection manager initialized
10504 14:48:00.475828 <6>[ 5.785923] Bluetooth: HCI socket layer initialized
10505 14:48:00.485602 <6>[ 5.787180] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10506 14:48:00.495650 <6>[ 5.788185] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10507 14:48:00.502264 <6>[ 5.788284] usbcore: registered new interface driver uvcvideo
10508 14:48:00.512371 <6>[ 5.794980] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10509 14:48:00.515598 <6>[ 5.803710] Bluetooth: L2CAP socket layer initialized
10510 14:48:00.525369 <6>[ 5.812217] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10511 14:48:00.528703 <6>[ 5.818654] Bluetooth: SCO socket layer initialized
10512 14:48:00.538824 <6>[ 5.826123] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10513 14:48:00.544997 <6>[ 5.836242] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10514 14:48:00.551847 <6>[ 5.839935] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10515 14:48:00.558448 <6>[ 5.881386] usbcore: registered new interface driver btusb
10516 14:48:00.568295 <4>[ 5.882356] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10517 14:48:00.575113 <3>[ 5.882370] Bluetooth: hci0: Failed to load firmware file (-2)
10518 14:48:00.581520 <3>[ 5.882376] Bluetooth: hci0: Failed to set up firmware (-2)
10519 14:48:00.591491 <4>[ 5.882383] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10520 14:48:00.598093 <6>[ 5.888320] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10521 14:48:00.604787 <6>[ 6.060503] pci 0000:00:00.0: PCI bridge to [bus 01]
10522 14:48:00.611641 <6>[ 6.065727] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10523 14:48:00.617955 <6>[ 6.073853] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10524 14:48:00.624365 <6>[ 6.080800] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10525 14:48:00.631258 <6>[ 6.087211] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10526 14:48:00.646492 <5>[ 6.100287] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10527 14:48:00.671940 <5>[ 6.125559] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10528 14:48:00.678297 <5>[ 6.132652] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10529 14:48:00.688382 <4>[ 6.141059] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10530 14:48:00.691637 <6>[ 6.149929] cfg80211: failed to load regulatory.db
10531 14:48:00.740554 <6>[ 6.194173] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10532 14:48:00.747214 <6>[ 6.201676] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10533 14:48:00.771079 <6>[ 6.228356] mt7921e 0000:01:00.0: ASIC revision: 79610010
10534 14:48:00.874240 <6>[ 6.327982] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10535 14:48:00.877560 <6>[ 6.327982]
10536 14:48:00.888403 Begin: Loading essential drivers ... done.
10537 14:48:00.891908 Begin: Running /scripts/init-premount ... done.
10538 14:48:00.898266 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10539 14:48:00.908154 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10540 14:48:00.911121 Device /sys/class/net/eth0 found
10541 14:48:00.911579 done.
10542 14:48:00.917721 Begin: Waiting up to 180 secs for any network device to become available ... done.
10543 14:48:00.959363 IP-Config: eth0 hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10544 14:48:00.965960 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10545 14:48:00.972916 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10546 14:48:00.979349 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10547 14:48:00.985822 host : mt8192-asurada-spherion-r0-cbg-4
10548 14:48:00.992185 domain : lava-rack
10549 14:48:00.995365 rootserver: 192.168.201.1 rootpath:
10550 14:48:00.995825 filename :
10551 14:48:01.100567 done.
10552 14:48:01.107833 Begin: Running /scripts/nfs-bottom ... done.
10553 14:48:01.122258 Begin: Running /scripts/init-bottom ... done.
10554 14:48:01.144467 <6>[ 6.598164] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10555 14:48:02.487184 <6>[ 7.944504] NET: Registered PF_INET6 protocol family
10556 14:48:02.494822 <6>[ 7.952145] Segment Routing with IPv6
10557 14:48:02.497738 <6>[ 7.956099] In-situ OAM (IOAM) with IPv6
10558 14:48:02.666016 <30>[ 8.093856] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10559 14:48:02.669180 <30>[ 8.126992] systemd[1]: Detected architecture arm64.
10560 14:48:02.678792
10561 14:48:02.681729 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10562 14:48:02.682439
10563 14:48:02.708294 <30>[ 8.166057] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10564 14:48:03.828415 <30>[ 9.282911] systemd[1]: Queued start job for default target graphical.target.
10565 14:48:03.875025 <30>[ 9.329556] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10566 14:48:03.881817 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10567 14:48:03.903801 <30>[ 9.358326] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10568 14:48:03.914104 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10569 14:48:03.931950 <30>[ 9.386317] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10570 14:48:03.941836 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10571 14:48:03.959870 <30>[ 9.414045] systemd[1]: Created slice user.slice - User and Session Slice.
10572 14:48:03.966140 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10573 14:48:03.989990 <30>[ 9.440892] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10574 14:48:03.996230 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10575 14:48:04.018037 <30>[ 9.468829] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10576 14:48:04.024234 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10577 14:48:04.052378 <30>[ 9.496750] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10578 14:48:04.062026 <30>[ 9.516561] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10579 14:48:04.068636 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10580 14:48:04.086179 <30>[ 9.540632] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10581 14:48:04.092838 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10582 14:48:04.110288 <30>[ 9.564658] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10583 14:48:04.119929 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10584 14:48:04.135129 <30>[ 9.592697] systemd[1]: Reached target paths.target - Path Units.
10585 14:48:04.144711 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10586 14:48:04.162885 <30>[ 9.617104] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10587 14:48:04.169102 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10588 14:48:04.182765 <30>[ 9.640594] systemd[1]: Reached target slices.target - Slice Units.
10589 14:48:04.192690 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10590 14:48:04.207617 <30>[ 9.665120] systemd[1]: Reached target swap.target - Swaps.
10591 14:48:04.214040 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10592 14:48:04.234250 <30>[ 9.688676] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10593 14:48:04.244315 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10594 14:48:04.263314 <30>[ 9.717518] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10595 14:48:04.272990 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10596 14:48:04.293124 <30>[ 9.747425] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10597 14:48:04.303088 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10598 14:48:04.320038 <30>[ 9.774152] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10599 14:48:04.329882 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10600 14:48:04.347859 <30>[ 9.801952] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10601 14:48:04.354411 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10602 14:48:04.376346 <30>[ 9.830599] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10603 14:48:04.386146 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10604 14:48:04.406755 <30>[ 9.861179] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10605 14:48:04.416933 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10606 14:48:04.434884 <30>[ 9.889106] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10607 14:48:04.444859 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10608 14:48:04.502579 <30>[ 9.956775] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10609 14:48:04.509044 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10610 14:48:04.530754 <30>[ 9.985344] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10611 14:48:04.537488 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10612 14:48:04.562965 <30>[ 10.017342] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10613 14:48:04.569834 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10614 14:48:04.597502 <30>[ 10.045163] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10615 14:48:04.612689 <30>[ 10.067024] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10616 14:48:04.622344 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10617 14:48:04.644322 <30>[ 10.098432] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10618 14:48:04.650566 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10619 14:48:04.675888 <30>[ 10.130254] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10620 14:48:04.682411 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10621 14:48:04.707836 <30>[ 10.162386] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10622 14:48:04.717694 Starting [0;1;39mmodpr<6>[ 10.172787] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10623 14:48:04.724545 obe@drm.service[0m - Load Kernel Module drm...
10624 14:48:04.747955 <30>[ 10.202430] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10625 14:48:04.757613 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10626 14:48:04.779527 <30>[ 10.234114] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10627 14:48:04.785868 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10628 14:48:04.811797 <30>[ 10.266266] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10629 14:48:04.818291 Startin<6>[ 10.274998] fuse: init (API version 7.37)
10630 14:48:04.824466 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10631 14:48:04.887395 <30>[ 10.341448] systemd[1]: Starting systemd-journald.service - Journal Service...
10632 14:48:04.893730 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10633 14:48:04.926852 <30>[ 10.381720] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10634 14:48:04.933181 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10635 14:48:04.960587 <30>[ 10.411960] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10636 14:48:04.966988 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10637 14:48:05.027236 <30>[ 10.481682] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10638 14:48:05.037096 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10639 14:48:05.055350 <3>[ 10.509668] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10640 14:48:05.065191 <30>[ 10.512808] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10641 14:48:05.071905 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10642 14:48:05.087519 <3>[ 10.541833] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10643 14:48:05.104154 <30>[ 10.558630] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10644 14:48:05.110638 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10645 14:48:05.130502 <30>[ 10.585097] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10646 14:48:05.140660 <3>[ 10.585507] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10647 14:48:05.146878 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10648 14:48:05.167158 <30>[ 10.621404] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10649 14:48:05.173650 <3>[ 10.622594] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10650 14:48:05.183624 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10651 14:48:05.203690 <30>[ 10.657628] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10652 14:48:05.213406 <3>[ 10.659325] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10653 14:48:05.220107 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10654 14:48:05.239565 <30>[ 10.693547] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10655 14:48:05.245944 <3>[ 10.698130] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10656 14:48:05.255869 <30>[ 10.701322] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10657 14:48:05.262337 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10658 14:48:05.278190 <3>[ 10.732702] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10659 14:48:05.288484 <30>[ 10.743042] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10660 14:48:05.295168 <30>[ 10.750888] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10661 14:48:05.308736 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 10.763554] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10662 14:48:05.315495 m_mod.s…e[0m - Load Kernel Module dm_mod.
10663 14:48:05.328340 <30>[ 10.785680] systemd[1]: modprobe@drm.service: Deactivated successfully.
10664 14:48:05.339086 <3>[ 10.793051] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10665 14:48:05.345325 <30>[ 10.793155] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10666 14:48:05.355557 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10667 14:48:05.367592 <3>[ 10.822297] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10668 14:48:05.378222 <30>[ 10.832853] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10669 14:48:05.389007 <30>[ 10.841296] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10670 14:48:05.399006 [[0;32m OK [0m] Finished [0<3>[ 10.851873] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10671 14:48:05.405318 ;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10672 14:48:05.426729 <3>[ 10.881373] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10673 14:48:05.433370 <30>[ 10.881890] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10674 14:48:05.443460 <30>[ 10.897893] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10675 14:48:05.449955 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10676 14:48:05.466729 <3>[ 10.920951] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10677 14:48:05.476515 <3>[ 10.921749] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
10678 14:48:05.490339 <4>[ 10.938036] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10679 14:48:05.496786 <30>[ 10.939027] systemd[1]: modprobe@loop.service: Deactivated successfully.
10680 14:48:05.504371 <3>[ 10.953675] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10681 14:48:05.515381 <30>[ 10.969264] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10682 14:48:05.521824 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10683 14:48:05.543228 <30>[ 10.997617] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10684 14:48:05.549921 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10685 14:48:05.570308 <30>[ 11.025016] systemd[1]: Started systemd-journald.service - Journal Service.
10686 14:48:05.577447 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10687 14:48:05.601402 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10688 14:48:05.619773 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10689 14:48:05.640013 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10690 14:48:05.661240 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10691 14:48:05.698828 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10692 14:48:05.723432 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10693 14:48:05.747713 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10694 14:48:05.771648 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10695 14:48:05.802165 <46>[ 11.257151] systemd-journald[298]: Received client request to flush runtime journal.
10696 14:48:05.823348 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10697 14:48:05.849133 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10698 14:48:06.119290 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10699 14:48:06.138116 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10700 14:48:06.158712 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10701 14:48:06.920091 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10702 14:48:07.223867 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10703 14:48:07.242727 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10704 14:48:07.294582 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10705 14:48:07.398470 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10706 14:48:07.414963 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10707 14:48:07.430268 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10708 14:48:07.474747 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10709 14:48:07.501230 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10710 14:48:07.688857 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10711 14:48:07.745210 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10712 14:48:07.815648 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10713 14:48:08.031580 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10714 14:48:08.134128 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization..<6>[ 13.592646] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10715 14:48:08.134277 .
10716 14:48:08.168582 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10717 14:48:08.271702 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10718 14:48:08.290128 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10719 14:48:08.310054 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10720 14:48:08.358853 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10721 14:48:08.379817 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10722 14:48:08.399365 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10723 14:48:08.449655 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10724 14:48:08.464635 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10725 14:48:08.490428 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10726 14:48:08.534948 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10727 14:48:08.556166 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10728 14:48:08.580107 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10729 14:48:08.612695 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10730 14:48:08.633668 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10731 14:48:08.650233 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10732 14:48:08.669732 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10733 14:48:08.689936 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10734 14:48:08.706266 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10735 14:48:08.721911 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10736 14:48:08.739949 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10737 14:48:08.757693 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10738 14:48:08.774213 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10739 14:48:08.819718 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10740 14:48:08.852859 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10741 14:48:08.914086 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10742 14:48:08.939459 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10743 14:48:08.958662 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10744 14:48:08.983486 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10745 14:48:09.030872 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10746 14:48:09.049899 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10747 14:48:09.067785 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10748 14:48:09.097835 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10749 14:48:09.198724 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10750 14:48:09.288850 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10751 14:48:09.308801 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10752 14:48:09.329276 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10753 14:48:09.373114 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10754 14:48:09.424097 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10755 14:48:09.498376
10756 14:48:09.501546 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10757 14:48:09.502019
10758 14:48:09.505054 debian-bookworm-arm64 login: root (automatic login)
10759 14:48:09.505705
10760 14:48:09.803088 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024 aarch64
10761 14:48:09.803947
10762 14:48:09.809474 The programs included with the Debian GNU/Linux system are free software;
10763 14:48:09.816074 the exact distribution terms for each program are described in the
10764 14:48:09.819476 individual files in /usr/share/doc/*/copyright.
10765 14:48:09.820065
10766 14:48:09.825918 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10767 14:48:09.829262 permitted by applicable law.
10768 14:48:10.835754 Matched prompt #10: / #
10770 14:48:10.836900 Setting prompt string to ['/ #']
10771 14:48:10.837395 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10773 14:48:10.838378 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10774 14:48:10.838837 start: 2.2.6 expect-shell-connection (timeout 00:03:44) [common]
10775 14:48:10.839238 Setting prompt string to ['/ #']
10776 14:48:10.839551 Forcing a shell prompt, looking for ['/ #']
10778 14:48:10.890329 / #
10779 14:48:10.891098 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10780 14:48:10.891536 Waiting using forced prompt support (timeout 00:02:30)
10781 14:48:10.896786
10782 14:48:10.897776 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10783 14:48:10.898312 start: 2.2.7 export-device-env (timeout 00:03:44) [common]
10785 14:48:10.999600 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14167017/extract-nfsrootfs-oz49gv4g'
10786 14:48:11.006242 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14167017/extract-nfsrootfs-oz49gv4g'
10788 14:48:11.108013 / # export NFS_SERVER_IP='192.168.201.1'
10789 14:48:11.114753 export NFS_SERVER_IP='192.168.201.1'
10790 14:48:11.115689 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10791 14:48:11.116224 end: 2.2 depthcharge-retry (duration 00:01:17) [common]
10792 14:48:11.116717 end: 2 depthcharge-action (duration 00:01:17) [common]
10793 14:48:11.117198 start: 3 lava-test-retry (timeout 00:08:05) [common]
10794 14:48:11.117721 start: 3.1 lava-test-shell (timeout 00:08:05) [common]
10795 14:48:11.118145 Using namespace: common
10797 14:48:11.219384 / # #
10798 14:48:11.220032 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10799 14:48:11.226014 #
10800 14:48:11.226892 Using /lava-14167017
10802 14:48:11.328027 / # export SHELL=/bin/bash
10803 14:48:11.334645 export SHELL=/bin/bash
10805 14:48:11.436191 / # . /lava-14167017/environment
10806 14:48:11.442721 . /lava-14167017/environment
10808 14:48:11.550428 / # /lava-14167017/bin/lava-test-runner /lava-14167017/0
10809 14:48:11.551055 Test shell timeout: 10s (minimum of the action and connection timeout)
10810 14:48:11.556698 /lava-14167017/bin/lava-test-runner /lava-14167017/0
10811 14:48:11.799997 + export TESTRUN_ID=0_timesync-off
10812 14:48:11.802984 + TESTRUN_ID=0_timesync-off
10813 14:48:11.806305 + cd /lava-14167017/0/tests/0_timesync-off
10814 14:48:11.809635 ++ cat uuid
10815 14:48:11.813897 + UUID=14167017_1.6.2.3.1
10816 14:48:11.814315 + set +x
10817 14:48:11.820528 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14167017_1.6.2.3.1>
10818 14:48:11.821422 Received signal: <STARTRUN> 0_timesync-off 14167017_1.6.2.3.1
10819 14:48:11.821829 Starting test lava.0_timesync-off (14167017_1.6.2.3.1)
10820 14:48:11.822313 Skipping test definition patterns.
10821 14:48:11.823716 + systemctl stop systemd-timesyncd
10822 14:48:11.922789 + set +x
10823 14:48:11.925977 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14167017_1.6.2.3.1>
10824 14:48:11.926730 Received signal: <ENDRUN> 0_timesync-off 14167017_1.6.2.3.1
10825 14:48:11.927194 Ending use of test pattern.
10826 14:48:11.927545 Ending test lava.0_timesync-off (14167017_1.6.2.3.1), duration 0.11
10828 14:48:12.008488 + export TESTRUN_ID=1_kselftest-arm64
10829 14:48:12.008953 + TESTRUN_ID=1_kselftest-arm64
10830 14:48:12.015497 + cd /lava-14167017/0/tests/1_kselftest-arm64
10831 14:48:12.015969 ++ cat uuid
10832 14:48:12.018308 + UUID=14167017_1.6.2.3.5
10833 14:48:12.018741 + set +x
10834 14:48:12.024958 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 14167017_1.6.2.3.5>
10835 14:48:12.025734 Received signal: <STARTRUN> 1_kselftest-arm64 14167017_1.6.2.3.5
10836 14:48:12.026111 Starting test lava.1_kselftest-arm64 (14167017_1.6.2.3.5)
10837 14:48:12.026525 Skipping test definition patterns.
10838 14:48:12.028102 + cd ./automated/linux/kselftest/
10839 14:48:12.054673 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10840 14:48:12.091256 INFO: install_deps skipped
10841 14:48:12.598810 --2024-06-04 14:48:12-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10842 14:48:12.613144 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10843 14:48:12.742955 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10844 14:48:12.873512 HTTP request sent, awaiting response... 200 OK
10845 14:48:12.876712 Length: 1647736 (1.6M) [application/octet-stream]
10846 14:48:12.880589 Saving to: 'kselftest_armhf.tar.gz'
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10852 14:48:13.931836 kselftest_armhf.tar 51%[=========> ] 825.54K 960KB/s
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10854 14:48:13.938499
10855 14:48:14.082229 2024-06-04 14:48:14 (1.49 MB/s) - 'kselftest_armhf.tar.gz' saved [1647736/1647736]
10856 14:48:14.082381
10857 14:48:18.612851 skiplist:
10858 14:48:18.616236 ========================================
10859 14:48:18.619246 ========================================
10860 14:48:18.667128 arm64:tags_test
10861 14:48:18.670370 arm64:run_tags_test.sh
10862 14:48:18.670731 arm64:fake_sigreturn_bad_magic
10863 14:48:18.673789 arm64:fake_sigreturn_bad_size
10864 14:48:18.677028 arm64:fake_sigreturn_bad_size_for_magic0
10865 14:48:18.680317 arm64:fake_sigreturn_duplicated_fpsimd
10866 14:48:18.683714 arm64:fake_sigreturn_misaligned_sp
10867 14:48:18.686957 arm64:fake_sigreturn_missing_fpsimd
10868 14:48:18.690329 arm64:fake_sigreturn_sme_change_vl
10869 14:48:18.693620 arm64:fake_sigreturn_sve_change_vl
10870 14:48:18.697118 arm64:mangle_pstate_invalid_compat_toggle
10871 14:48:18.700545 arm64:mangle_pstate_invalid_daif_bits
10872 14:48:18.703565 arm64:mangle_pstate_invalid_mode_el1h
10873 14:48:18.706709 arm64:mangle_pstate_invalid_mode_el1t
10874 14:48:18.710034 arm64:mangle_pstate_invalid_mode_el2h
10875 14:48:18.713423 arm64:mangle_pstate_invalid_mode_el2t
10876 14:48:18.716699 arm64:mangle_pstate_invalid_mode_el3h
10877 14:48:18.723274 arm64:mangle_pstate_invalid_mode_el3t
10878 14:48:18.723689 arm64:sme_trap_no_sm
10879 14:48:18.726607 arm64:sme_trap_non_streaming
10880 14:48:18.727022 arm64:sme_trap_za
10881 14:48:18.730142 arm64:sme_vl
10882 14:48:18.730555 arm64:ssve_regs
10883 14:48:18.733390 arm64:sve_regs
10884 14:48:18.733802 arm64:sve_vl
10885 14:48:18.734133 arm64:za_no_regs
10886 14:48:18.736488 arm64:za_regs
10887 14:48:18.736905 arm64:pac
10888 14:48:18.739721 arm64:fp-stress
10889 14:48:18.740134 arm64:sve-ptrace
10890 14:48:18.743052 arm64:sve-probe-vls
10891 14:48:18.743467 arm64:vec-syscfg
10892 14:48:18.743793 arm64:za-fork
10893 14:48:18.746426 arm64:za-ptrace
10894 14:48:18.749708 arm64:check_buffer_fill
10895 14:48:18.750136 arm64:check_child_memory
10896 14:48:18.752939 arm64:check_gcr_el1_cswitch
10897 14:48:18.756332 arm64:check_ksm_options
10898 14:48:18.756792 arm64:check_mmap_options
10899 14:48:18.759642 arm64:check_prctl
10900 14:48:18.762724 arm64:check_tags_inclusion
10901 14:48:18.763139 arm64:check_user_mem
10902 14:48:18.766441 arm64:btitest
10903 14:48:18.766853 arm64:nobtitest
10904 14:48:18.767179 arm64:hwcap
10905 14:48:18.769457 arm64:ptrace
10906 14:48:18.769869 arm64:syscall-abi
10907 14:48:18.773022 arm64:tpidr2
10908 14:48:18.775990 ============== Tests to run ===============
10909 14:48:18.776408 arm64:tags_test
10910 14:48:18.779289 arm64:run_tags_test.sh
10911 14:48:18.782510 arm64:fake_sigreturn_bad_magic
10912 14:48:18.785967 arm64:fake_sigreturn_bad_size
10913 14:48:18.789175 arm64:fake_sigreturn_bad_size_for_magic0
10914 14:48:18.792732 arm64:fake_sigreturn_duplicated_fpsimd
10915 14:48:18.795916 arm64:fake_sigreturn_misaligned_sp
10916 14:48:18.799071 arm64:fake_sigreturn_missing_fpsimd
10917 14:48:18.802322 arm64:fake_sigreturn_sme_change_vl
10918 14:48:18.805553 arm64:fake_sigreturn_sve_change_vl
10919 14:48:18.808998 arm64:mangle_pstate_invalid_compat_toggle
10920 14:48:18.812287 arm64:mangle_pstate_invalid_daif_bits
10921 14:48:18.815529 arm64:mangle_pstate_invalid_mode_el1h
10922 14:48:18.819040 arm64:mangle_pstate_invalid_mode_el1t
10923 14:48:18.822570 arm64:mangle_pstate_invalid_mode_el2h
10924 14:48:18.825552 arm64:mangle_pstate_invalid_mode_el2t
10925 14:48:18.829103 arm64:mangle_pstate_invalid_mode_el3h
10926 14:48:18.832265 arm64:mangle_pstate_invalid_mode_el3t
10927 14:48:18.832740 arm64:sme_trap_no_sm
10928 14:48:18.835909 arm64:sme_trap_non_streaming
10929 14:48:18.839292 arm64:sme_trap_za
10930 14:48:18.839857 arm64:sme_vl
10931 14:48:18.841922 arm64:ssve_regs
10932 14:48:18.842380 arm64:sve_regs
10933 14:48:18.842741 arm64:sve_vl
10934 14:48:18.845348 arm64:za_no_regs
10935 14:48:18.845805 arm64:za_regs
10936 14:48:18.846165 arm64:pac
10937 14:48:18.848758 arm64:fp-stress
10938 14:48:18.849217 arm64:sve-ptrace
10939 14:48:18.851739 arm64:sve-probe-vls
10940 14:48:18.852273 arm64:vec-syscfg
10941 14:48:18.855298 arm64:za-fork
10942 14:48:18.855768 arm64:za-ptrace
10943 14:48:18.858505 arm64:check_buffer_fill
10944 14:48:18.861812 arm64:check_child_memory
10945 14:48:18.862287 arm64:check_gcr_el1_cswitch
10946 14:48:18.865036 arm64:check_ksm_options
10947 14:48:18.868319 arm64:check_mmap_options
10948 14:48:18.868793 arm64:check_prctl
10949 14:48:18.871756 arm64:check_tags_inclusion
10950 14:48:18.875102 arm64:check_user_mem
10951 14:48:18.875621 arm64:btitest
10952 14:48:18.876185 arm64:nobtitest
10953 14:48:18.878245 arm64:hwcap
10954 14:48:18.878713 arm64:ptrace
10955 14:48:18.881457 arm64:syscall-abi
10956 14:48:18.881889 arm64:tpidr2
10957 14:48:18.885239 ===========End Tests to run ===============
10958 14:48:18.888453 shardfile-arm64 pass
10959 14:48:19.086372 <12>[ 24.545963] kselftest: Running tests in arm64
10960 14:48:19.097062 TAP version 13
10961 14:48:19.111887 1..48
10962 14:48:19.128901 # selftests: arm64: tags_test
10963 14:48:19.587639 ok 1 selftests: arm64: tags_test
10964 14:48:19.604552 # selftests: arm64: run_tags_test.sh
10965 14:48:19.658165 # --------------------
10966 14:48:19.661184 # running tags test
10967 14:48:19.661455 # --------------------
10968 14:48:19.664472 # [PASS]
10969 14:48:19.667736 ok 2 selftests: arm64: run_tags_test.sh
10970 14:48:19.679651 # selftests: arm64: fake_sigreturn_bad_magic
10971 14:48:19.735810 # Registered handlers for all signals.
10972 14:48:19.736477 # Detected MINSTKSIGSZ:4720
10973 14:48:19.738957 # Testcase initialized.
10974 14:48:19.741988 # uc context validated.
10975 14:48:19.745647 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
10976 14:48:19.748737 # Handled SIG_COPYCTX
10977 14:48:19.749362 # Available space:3568
10978 14:48:19.755418 # Using badly built context - ERR: BAD MAGIC !
10979 14:48:19.761365 # SIG_OK -- SP:0xFFFFE96144A0 si_addr@:0xffffe96144a0 si_code:2 token@:0xffffe9613240 offset:-4704
10980 14:48:19.764781 # ==>> completed. PASS(1)
10981 14:48:19.771365 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
10982 14:48:19.778008 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE9613240
10983 14:48:19.784828 ok 3 selftests: arm64: fake_sigreturn_bad_magic
10984 14:48:19.788160 # selftests: arm64: fake_sigreturn_bad_size
10985 14:48:19.814296 # Registered handlers for all signals.
10986 14:48:19.814931 # Detected MINSTKSIGSZ:4720
10987 14:48:19.817261 # Testcase initialized.
10988 14:48:19.820486 # uc context validated.
10989 14:48:19.823628 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
10990 14:48:19.826990 # Handled SIG_COPYCTX
10991 14:48:19.827547 # Available space:3568
10992 14:48:19.830399 # uc context validated.
10993 14:48:19.836799 # Using badly built context - ERR: Bad size for esr_context
10994 14:48:19.843724 # SIG_OK -- SP:0xFFFFC04E3840 si_addr@:0xffffc04e3840 si_code:2 token@:0xffffc04e25e0 offset:-4704
10995 14:48:19.847011 # ==>> completed. PASS(1)
10996 14:48:19.853473 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
10997 14:48:19.860049 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC04E25E0
10998 14:48:19.863328 ok 4 selftests: arm64: fake_sigreturn_bad_size
10999 14:48:19.869778 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11000 14:48:19.885043 # Registered handlers for all signals.
11001 14:48:19.885728 # Detected MINSTKSIGSZ:4720
11002 14:48:19.888449 # Testcase initialized.
11003 14:48:19.891635 # uc context validated.
11004 14:48:19.894766 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11005 14:48:19.898170 # Handled SIG_COPYCTX
11006 14:48:19.898733 # Available space:3568
11007 14:48:19.904606 # Using badly built context - ERR: Bad size for terminator
11008 14:48:19.914620 # SIG_OK -- SP:0xFFFFED768300 si_addr@:0xffffed768300 si_code:2 token@:0xffffed7670a0 offset:-4704
11009 14:48:19.915120 # ==>> completed. PASS(1)
11010 14:48:19.924580 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11011 14:48:19.931168 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFED7670A0
11012 14:48:19.934700 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11013 14:48:19.941025 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11014 14:48:19.951200 # Registered handlers for all signals.
11015 14:48:19.951701 # Detected MINSTKSIGSZ:4720
11016 14:48:19.954338 # Testcase initialized.
11017 14:48:19.957352 # uc context validated.
11018 14:48:19.960736 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11019 14:48:19.964113 # Handled SIG_COPYCTX
11020 14:48:19.964569 # Available space:3568
11021 14:48:19.970759 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11022 14:48:19.980446 # SIG_OK -- SP:0xFFFFE0D7F2B0 si_addr@:0xffffe0d7f2b0 si_code:2 token@:0xffffe0d7e050 offset:-4704
11023 14:48:19.980911 # ==>> completed. PASS(1)
11024 14:48:19.990226 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11025 14:48:19.996853 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE0D7E050
11026 14:48:20.000567 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11027 14:48:20.006991 # selftests: arm64: fake_sigreturn_misaligned_sp
11028 14:48:20.030024 # Registered handlers for all signals.
11029 14:48:20.030589 # Detected MINSTKSIGSZ:4720
11030 14:48:20.033184 # Testcase initialized.
11031 14:48:20.036475 # uc context validated.
11032 14:48:20.039732 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11033 14:48:20.043057 # Handled SIG_COPYCTX
11034 14:48:20.049651 # SIG_OK -- SP:0xFFFFECC5B393 si_addr@:0xffffecc5b393 si_code:2 token@:0xffffecc5b393 offset:0
11035 14:48:20.053023 # ==>> completed. PASS(1)
11036 14:48:20.059846 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11037 14:48:20.066104 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFECC5B393
11038 14:48:20.072744 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11039 14:48:20.075698 # selftests: arm64: fake_sigreturn_missing_fpsimd
11040 14:48:20.117694 # Registered handlers for all signals.
11041 14:48:20.118247 # Detected MINSTKSIGSZ:4720
11042 14:48:20.120992 # Testcase initialized.
11043 14:48:20.124090 # uc context validated.
11044 14:48:20.127351 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11045 14:48:20.130825 # Handled SIG_COPYCTX
11046 14:48:20.133990 # Mangling template header. Spare space:4096
11047 14:48:20.137657 # Using badly built context - ERR: Missing FPSIMD
11048 14:48:20.147129 # SIG_OK -- SP:0xFFFFF7E79A10 si_addr@:0xfffff7e79a10 si_code:2 token@:0xfffff7e787b0 offset:-4704
11049 14:48:20.150328 # ==>> completed. PASS(1)
11050 14:48:20.157121 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11051 14:48:20.163714 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF7E787B0
11052 14:48:20.167092 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11053 14:48:20.173929 # selftests: arm64: fake_sigreturn_sme_change_vl
11054 14:48:20.194444 # Registered handlers for all signals.
11055 14:48:20.194982 # Detected MINSTKSIGSZ:4720
11056 14:48:20.197750 # ==>> completed. SKIP.
11057 14:48:20.204114 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11058 14:48:20.207645 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11059 14:48:20.214565 # selftests: arm64: fake_sigreturn_sve_change_vl
11060 14:48:20.266595 # Registered handlers for all signals.
11061 14:48:20.267174 # Detected MINSTKSIGSZ:4720
11062 14:48:20.269863 # ==>> completed. SKIP.
11063 14:48:20.273392 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11064 14:48:20.279781 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11065 14:48:20.287117 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11066 14:48:20.348248 # Registered handlers for all signals.
11067 14:48:20.348800 # Detected MINSTKSIGSZ:4720
11068 14:48:20.351130 # Testcase initialized.
11069 14:48:20.354581 # uc context validated.
11070 14:48:20.355241 # Handled SIG_TRIG
11071 14:48:20.364441 # SIG_OK -- SP:0xFFFFEE3FF050 si_addr@:0xffffee3ff050 si_code:2 token@:(nil) offset:-281474678911056
11072 14:48:20.367765 # ==>> completed. PASS(1)
11073 14:48:20.374330 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11074 14:48:20.380900 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11075 14:48:20.384565 # selftests: arm64: mangle_pstate_invalid_daif_bits
11076 14:48:20.416498 # Registered handlers for all signals.
11077 14:48:20.417063 # Detected MINSTKSIGSZ:4720
11078 14:48:20.419792 # Testcase initialized.
11079 14:48:20.423295 # uc context validated.
11080 14:48:20.423862 # Handled SIG_TRIG
11081 14:48:20.432955 # SIG_OK -- SP:0xFFFFD7096AA0 si_addr@:0xffffd7096aa0 si_code:2 token@:(nil) offset:-281474289461920
11082 14:48:20.436376 # ==>> completed. PASS(1)
11083 14:48:20.442874 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11084 14:48:20.446087 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11085 14:48:20.452642 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11086 14:48:20.496833 # Registered handlers for all signals.
11087 14:48:20.496981 # Detected MINSTKSIGSZ:4720
11088 14:48:20.499971 # Testcase initialized.
11089 14:48:20.503216 # uc context validated.
11090 14:48:20.503297 # Handled SIG_TRIG
11091 14:48:20.513153 # SIG_OK -- SP:0xFFFFD6C2F4F0 si_addr@:0xffffd6c2f4f0 si_code:2 token@:(nil) offset:-281474284844272
11092 14:48:20.516910 # ==>> completed. PASS(1)
11093 14:48:20.523220 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11094 14:48:20.526417 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11095 14:48:20.532935 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11096 14:48:20.566493 # Registered handlers for all signals.
11097 14:48:20.566754 # Detected MINSTKSIGSZ:4720
11098 14:48:20.569862 # Testcase initialized.
11099 14:48:20.573183 # uc context validated.
11100 14:48:20.573490 # Handled SIG_TRIG
11101 14:48:20.583212 # SIG_OK -- SP:0xFFFFEBC5C240 si_addr@:0xffffebc5c240 si_code:2 token@:(nil) offset:-281474637349440
11102 14:48:20.586350 # ==>> completed. PASS(1)
11103 14:48:20.592979 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11104 14:48:20.596489 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11105 14:48:20.602688 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11106 14:48:20.638767 # Registered handlers for all signals.
11107 14:48:20.639358 # Detected MINSTKSIGSZ:4720
11108 14:48:20.642150 # Testcase initialized.
11109 14:48:20.645336 # uc context validated.
11110 14:48:20.645899 # Handled SIG_TRIG
11111 14:48:20.655095 # SIG_OK -- SP:0xFFFFC53B7250 si_addr@:0xffffc53b7250 si_code:2 token@:(nil) offset:-281473990750800
11112 14:48:20.658545 # ==>> completed. PASS(1)
11113 14:48:20.664985 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11114 14:48:20.668126 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11115 14:48:20.674712 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11116 14:48:20.722531 # Registered handlers for all signals.
11117 14:48:20.723093 # Detected MINSTKSIGSZ:4720
11118 14:48:20.725493 # Testcase initialized.
11119 14:48:20.728704 # uc context validated.
11120 14:48:20.729219 # Handled SIG_TRIG
11121 14:48:20.739199 # SIG_OK -- SP:0xFFFFCCA494C0 si_addr@:0xffffcca494c0 si_code:2 token@:(nil) offset:-281474115081408
11122 14:48:20.741872 # ==>> completed. PASS(1)
11123 14:48:20.748580 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11124 14:48:20.751991 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11125 14:48:20.758392 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11126 14:48:20.803536 # Registered handlers for all signals.
11127 14:48:20.804111 # Detected MINSTKSIGSZ:4720
11128 14:48:20.807159 # Testcase initialized.
11129 14:48:20.810426 # uc context validated.
11130 14:48:20.810882 # Handled SIG_TRIG
11131 14:48:20.820497 # SIG_OK -- SP:0xFFFFD2668290 si_addr@:0xffffd2668290 si_code:2 token@:(nil) offset:-281474211676816
11132 14:48:20.823670 # ==>> completed. PASS(1)
11133 14:48:20.830253 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11134 14:48:20.833398 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11135 14:48:20.839859 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11136 14:48:20.886871 # Registered handlers for all signals.
11137 14:48:20.887550 # Detected MINSTKSIGSZ:4720
11138 14:48:20.890571 # Testcase initialized.
11139 14:48:20.893798 # uc context validated.
11140 14:48:20.894251 # Handled SIG_TRIG
11141 14:48:20.903588 # SIG_OK -- SP:0xFFFFD27FCAA0 si_addr@:0xffffd27fcaa0 si_code:2 token@:(nil) offset:-281474213333664
11142 14:48:20.906694 # ==>> completed. PASS(1)
11143 14:48:20.913733 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11144 14:48:20.917190 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11145 14:48:20.919891 # selftests: arm64: sme_trap_no_sm
11146 14:48:20.968706 # Registered handlers for all signals.
11147 14:48:20.969261 # Detected MINSTKSIGSZ:4720
11148 14:48:20.971881 # ==>> completed. SKIP.
11149 14:48:20.981766 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11150 14:48:20.985081 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11151 14:48:20.995639 # selftests: arm64: sme_trap_non_streaming
11152 14:48:21.044579 # Registered handlers for all signals.
11153 14:48:21.045166 # Detected MINSTKSIGSZ:4720
11154 14:48:21.047850 # ==>> completed. SKIP.
11155 14:48:21.057635 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11156 14:48:21.064184 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11157 14:48:21.067570 # selftests: arm64: sme_trap_za
11158 14:48:21.126136 # Registered handlers for all signals.
11159 14:48:21.126807 # Detected MINSTKSIGSZ:4720
11160 14:48:21.127900 # Testcase initialized.
11161 14:48:21.137970 # SIG_OK -- SP:0xFFFFC253D750 si_addr@:0xaaaab8bf2510 si_code:1 token@:(nil) offset:-187650220696848
11162 14:48:21.138430 # ==>> completed. PASS(1)
11163 14:48:21.147809 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11164 14:48:21.150961 ok 21 selftests: arm64: sme_trap_za
11165 14:48:21.151571 # selftests: arm64: sme_vl
11166 14:48:21.199597 # Registered handlers for all signals.
11167 14:48:21.200242 # Detected MINSTKSIGSZ:4720
11168 14:48:21.203024 # ==>> completed. SKIP.
11169 14:48:21.209279 # # SME VL :: Check that we get the right SME VL reported
11170 14:48:21.212570 ok 22 selftests: arm64: sme_vl # SKIP
11171 14:48:21.217037 # selftests: arm64: ssve_regs
11172 14:48:21.272155 # Registered handlers for all signals.
11173 14:48:21.272754 # Detected MINSTKSIGSZ:4720
11174 14:48:21.275744 # ==>> completed. SKIP.
11175 14:48:21.282457 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11176 14:48:21.285202 ok 23 selftests: arm64: ssve_regs # SKIP
11177 14:48:21.288640 # selftests: arm64: sve_regs
11178 14:48:21.339334 # Registered handlers for all signals.
11179 14:48:21.339927 # Detected MINSTKSIGSZ:4720
11180 14:48:21.342647 # ==>> completed. SKIP.
11181 14:48:21.349038 # # SVE registers :: Check that we get the right SVE registers reported
11182 14:48:21.352276 ok 24 selftests: arm64: sve_regs # SKIP
11183 14:48:21.356674 # selftests: arm64: sve_vl
11184 14:48:21.419114 # Registered handlers for all signals.
11185 14:48:21.419655 # Detected MINSTKSIGSZ:4720
11186 14:48:21.422121 # ==>> completed. SKIP.
11187 14:48:21.428777 # # SVE VL :: Check that we get the right SVE VL reported
11188 14:48:21.431871 ok 25 selftests: arm64: sve_vl # SKIP
11189 14:48:21.439764 # selftests: arm64: za_no_regs
11190 14:48:21.522204 # Registered handlers for all signals.
11191 14:48:21.522777 # Detected MINSTKSIGSZ:4720
11192 14:48:21.525345 # ==>> completed. SKIP.
11193 14:48:21.532233 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11194 14:48:21.535488 ok 26 selftests: arm64: za_no_regs # SKIP
11195 14:48:21.538651 # selftests: arm64: za_regs
11196 14:48:21.582012 # Registered handlers for all signals.
11197 14:48:21.582549 # Detected MINSTKSIGSZ:4720
11198 14:48:21.585420 # ==>> completed. SKIP.
11199 14:48:21.591671 # # ZA register :: Check that we get the right ZA registers reported
11200 14:48:21.594839 ok 27 selftests: arm64: za_regs # SKIP
11201 14:48:21.597816 # selftests: arm64: pac
11202 14:48:21.650019 # TAP version 13
11203 14:48:21.650631 # 1..7
11204 14:48:21.653363 # # Starting 7 tests from 1 test cases.
11205 14:48:21.656594 # # RUN global.corrupt_pac ...
11206 14:48:21.659801 # # SKIP PAUTH not enabled
11207 14:48:21.663784 # # OK global.corrupt_pac
11208 14:48:21.666507 # ok 1 # SKIP PAUTH not enabled
11209 14:48:21.673188 # # RUN global.pac_instructions_not_nop ...
11210 14:48:21.676501 # # SKIP PAUTH not enabled
11211 14:48:21.679705 # # OK global.pac_instructions_not_nop
11212 14:48:21.683084 # ok 2 # SKIP PAUTH not enabled
11213 14:48:21.689628 # # RUN global.pac_instructions_not_nop_generic ...
11214 14:48:21.692831 # # SKIP Generic PAUTH not enabled
11215 14:48:21.696126 # # OK global.pac_instructions_not_nop_generic
11216 14:48:21.702784 # ok 3 # SKIP Generic PAUTH not enabled
11217 14:48:21.705967 # # RUN global.single_thread_different_keys ...
11218 14:48:21.709186 # # SKIP PAUTH not enabled
11219 14:48:21.715909 # # OK global.single_thread_different_keys
11220 14:48:21.716363 # ok 4 # SKIP PAUTH not enabled
11221 14:48:21.722421 # # RUN global.exec_changed_keys ...
11222 14:48:21.725729 # # SKIP PAUTH not enabled
11223 14:48:21.729212 # # OK global.exec_changed_keys
11224 14:48:21.732523 # ok 5 # SKIP PAUTH not enabled
11225 14:48:21.735836 # # RUN global.context_switch_keep_keys ...
11226 14:48:21.738974 # # SKIP PAUTH not enabled
11227 14:48:21.745452 # # OK global.context_switch_keep_keys
11228 14:48:21.749451 # ok 6 # SKIP PAUTH not enabled
11229 14:48:21.752520 # # RUN global.context_switch_keep_keys_generic ...
11230 14:48:21.755637 # # SKIP Generic PAUTH not enabled
11231 14:48:21.762315 # # OK global.context_switch_keep_keys_generic
11232 14:48:21.765447 # ok 7 # SKIP Generic PAUTH not enabled
11233 14:48:21.768945 # # PASSED: 7 / 7 tests passed.
11234 14:48:21.772387 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11235 14:48:21.775606 ok 28 selftests: arm64: pac
11236 14:48:21.778716 # selftests: arm64: fp-stress
11237 14:48:30.460415 <6>[ 35.924400] vpu: disabling
11238 14:48:30.463613 <6>[ 35.927453] vproc2: disabling
11239 14:48:30.466988 <6>[ 35.931018] vproc1: disabling
11240 14:48:30.470379 <6>[ 35.934299] vaud18: disabling
11241 14:48:30.477062 <6>[ 35.937732] vsram_others: disabling
11242 14:48:30.480452 <6>[ 35.941625] va09: disabling
11243 14:48:30.483739 <6>[ 35.944742] vsram_md: disabling
11244 14:48:30.487085 <6>[ 35.948241] Vgpu: disabling
11245 14:48:31.721617 # TAP version 13
11246 14:48:31.722170 # 1..16
11247 14:48:31.725270 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11248 14:48:31.728182 # # Will run for 10s
11249 14:48:31.728737 # # Started FPSIMD-0-0
11250 14:48:31.731492 # # Started FPSIMD-0-1
11251 14:48:31.734728 # # Started FPSIMD-1-0
11252 14:48:31.735328 # # Started FPSIMD-1-1
11253 14:48:31.737985 # # Started FPSIMD-2-0
11254 14:48:31.738469 # # Started FPSIMD-2-1
11255 14:48:31.741584 # # Started FPSIMD-3-0
11256 14:48:31.744547 # # Started FPSIMD-3-1
11257 14:48:31.745001 # # Started FPSIMD-4-0
11258 14:48:31.747820 # # Started FPSIMD-4-1
11259 14:48:31.751098 # # Started FPSIMD-5-0
11260 14:48:31.751635 # # Started FPSIMD-5-1
11261 14:48:31.754261 # # Started FPSIMD-6-0
11262 14:48:31.757737 # # Started FPSIMD-6-1
11263 14:48:31.758396 # # Started FPSIMD-7-0
11264 14:48:31.760768 # # Started FPSIMD-7-1
11265 14:48:31.764274 # # FPSIMD-0-0: Vector length: 128 bits
11266 14:48:31.767482 # # FPSIMD-0-0: PID: 1155
11267 14:48:31.770780 # # FPSIMD-0-1: Vector length: 128 bits
11268 14:48:31.771235 # # FPSIMD-0-1: PID: 1156
11269 14:48:31.774293 # # FPSIMD-2-1: Vector length: 128 bits
11270 14:48:31.777445 # # FPSIMD-2-1: PID: 1160
11271 14:48:31.780875 # # FPSIMD-1-0: Vector length: 128 bits
11272 14:48:31.784310 # # FPSIMD-1-0: PID: 1157
11273 14:48:31.787461 # # FPSIMD-1-1: Vector length: 128 bits
11274 14:48:31.791290 # # FPSIMD-1-1: PID: 1158
11275 14:48:31.794096 # # FPSIMD-2-0: Vector length: 128 bits
11276 14:48:31.794550 # # FPSIMD-2-0: PID: 1159
11277 14:48:31.800708 # # FPSIMD-5-0: Vector length: 128 bits
11278 14:48:31.801196 # # FPSIMD-5-0: PID: 1165
11279 14:48:31.803994 # # FPSIMD-7-1: Vector length: 128 bits
11280 14:48:31.807810 # # FPSIMD-7-1: PID: 1170
11281 14:48:31.810767 # # FPSIMD-6-1: Vector length: 128 bits
11282 14:48:31.814111 # # FPSIMD-6-1: PID: 1168
11283 14:48:31.817414 # # FPSIMD-6-0: Vector length: 128 bits
11284 14:48:31.821213 # # FPSIMD-6-0: PID: 1167
11285 14:48:31.824139 # # FPSIMD-4-1: Vector length: 128 bits
11286 14:48:31.824695 # # FPSIMD-4-1: PID: 1164
11287 14:48:31.827357 # # FPSIMD-3-0: Vector length: 128 bits
11288 14:48:31.830846 # # FPSIMD-3-0: PID: 1161
11289 14:48:31.833912 # # FPSIMD-7-0: Vector length: 128 bits
11290 14:48:31.837226 # # FPSIMD-7-0: PID: 1169
11291 14:48:31.840692 # # FPSIMD-3-1: Vector length: 128 bits
11292 14:48:31.843815 # # FPSIMD-3-1: PID: 1162
11293 14:48:31.847387 # # FPSIMD-5-1: Vector length: 128 bits
11294 14:48:31.850641 # # FPSIMD-5-1: PID: 1166
11295 14:48:31.853816 # # FPSIMD-4-0: Vector length: 128 bits
11296 14:48:31.854383 # # FPSIMD-4-0: PID: 1163
11297 14:48:31.856870 # # Finishing up...
11298 14:48:31.863613 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=986033, signals=10
11299 14:48:31.870335 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1047647, signals=10
11300 14:48:31.877131 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=2128684, signals=10
11301 14:48:31.886564 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=989823, signals=10
11302 14:48:31.893252 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=2180869, signals=10
11303 14:48:31.899821 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=2127926, signals=10
11304 14:48:31.906449 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=2186374, signals=10
11305 14:48:31.909639 # ok 1 FPSIMD-0-0
11306 14:48:31.910050 # ok 2 FPSIMD-0-1
11307 14:48:31.912998 # ok 3 FPSIMD-1-0
11308 14:48:31.913449 # ok 4 FPSIMD-1-1
11309 14:48:31.916533 # ok 5 FPSIMD-2-0
11310 14:48:31.916985 # ok 6 FPSIMD-2-1
11311 14:48:31.919688 # ok 7 FPSIMD-3-0
11312 14:48:31.920098 # ok 8 FPSIMD-3-1
11313 14:48:31.922905 # ok 9 FPSIMD-4-0
11314 14:48:31.923314 # ok 10 FPSIMD-4-1
11315 14:48:31.926381 # ok 11 FPSIMD-5-0
11316 14:48:31.926793 # ok 12 FPSIMD-5-1
11317 14:48:31.929637 # ok 13 FPSIMD-6-0
11318 14:48:31.930046 # ok 14 FPSIMD-6-1
11319 14:48:31.933117 # ok 15 FPSIMD-7-0
11320 14:48:31.933697 # ok 16 FPSIMD-7-1
11321 14:48:31.939945 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1117721, signals=9
11322 14:48:31.949570 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1048005, signals=10
11323 14:48:31.956315 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=978442, signals=10
11324 14:48:31.962540 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=988338, signals=10
11325 14:48:31.968994 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=986425, signals=9
11326 14:48:31.975651 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1052952, signals=10
11327 14:48:31.982202 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=985127, signals=10
11328 14:48:31.992602 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=976124, signals=10
11329 14:48:31.999171 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=1160768, signals=9
11330 14:48:32.002038 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11331 14:48:32.005345 ok 29 selftests: arm64: fp-stress
11332 14:48:32.008964 # selftests: arm64: sve-ptrace
11333 14:48:32.009587 # TAP version 13
11334 14:48:32.012070 # 1..4104
11335 14:48:32.015530 # ok 2 # SKIP SVE not available
11336 14:48:32.018716 # # Planned tests != run tests (4104 != 1)
11337 14:48:32.021840 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11338 14:48:32.025689 ok 30 selftests: arm64: sve-ptrace # SKIP
11339 14:48:32.028648 # selftests: arm64: sve-probe-vls
11340 14:48:32.032120 # TAP version 13
11341 14:48:32.032753 # 1..2
11342 14:48:32.035342 # ok 2 # SKIP SVE not available
11343 14:48:32.038715 # # Planned tests != run tests (2 != 1)
11344 14:48:32.041913 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11345 14:48:32.048392 ok 31 selftests: arm64: sve-probe-vls # SKIP
11346 14:48:32.051821 # selftests: arm64: vec-syscfg
11347 14:48:32.052315 # TAP version 13
11348 14:48:32.052731 # 1..20
11349 14:48:32.055170 # ok 1 # SKIP SVE not supported
11350 14:48:32.058230 # ok 2 # SKIP SVE not supported
11351 14:48:32.061544 # ok 3 # SKIP SVE not supported
11352 14:48:32.065336 # ok 4 # SKIP SVE not supported
11353 14:48:32.068277 # ok 5 # SKIP SVE not supported
11354 14:48:32.068733 # ok 6 # SKIP SVE not supported
11355 14:48:32.071534 # ok 7 # SKIP SVE not supported
11356 14:48:32.074910 # ok 8 # SKIP SVE not supported
11357 14:48:32.078414 # ok 9 # SKIP SVE not supported
11358 14:48:32.081737 # ok 10 # SKIP SVE not supported
11359 14:48:32.085103 # ok 11 # SKIP SME not supported
11360 14:48:32.088535 # ok 12 # SKIP SME not supported
11361 14:48:32.091570 # ok 13 # SKIP SME not supported
11362 14:48:32.092188 # ok 14 # SKIP SME not supported
11363 14:48:32.094915 # ok 15 # SKIP SME not supported
11364 14:48:32.098255 # ok 16 # SKIP SME not supported
11365 14:48:32.101622 # ok 17 # SKIP SME not supported
11366 14:48:32.104765 # ok 18 # SKIP SME not supported
11367 14:48:32.108104 # ok 19 # SKIP SME not supported
11368 14:48:32.111174 # ok 20 # SKIP SME not supported
11369 14:48:32.114769 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11370 14:48:32.118013 ok 32 selftests: arm64: vec-syscfg
11371 14:48:32.121126 # selftests: arm64: za-fork
11372 14:48:32.124621 # TAP version 13
11373 14:48:32.125071 # 1..1
11374 14:48:32.125502 # # PID: 1247
11375 14:48:32.127942 # # SME support not present
11376 14:48:32.128415 # ok 0 skipped
11377 14:48:32.134636 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11378 14:48:32.137733 ok 33 selftests: arm64: za-fork
11379 14:48:32.140851 # selftests: arm64: za-ptrace
11380 14:48:32.141346 # TAP version 13
11381 14:48:32.141718 # 1..1
11382 14:48:32.144224 # ok 2 # SKIP SME not available
11383 14:48:32.150887 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11384 14:48:32.154298 ok 34 selftests: arm64: za-ptrace # SKIP
11385 14:48:32.157699 # selftests: arm64: check_buffer_fill
11386 14:48:32.191176 # # SKIP: MTE features unavailable
11387 14:48:32.198353 ok 35 selftests: arm64: check_buffer_fill # SKIP
11388 14:48:32.215214 # selftests: arm64: check_child_memory
11389 14:48:32.276131 # # SKIP: MTE features unavailable
11390 14:48:32.282723 ok 36 selftests: arm64: check_child_memory # SKIP
11391 14:48:32.297793 # selftests: arm64: check_gcr_el1_cswitch
11392 14:48:32.355026 # # SKIP: MTE features unavailable
11393 14:48:32.361670 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11394 14:48:32.376994 # selftests: arm64: check_ksm_options
11395 14:48:32.432448 # # SKIP: MTE features unavailable
11396 14:48:32.439957 ok 38 selftests: arm64: check_ksm_options # SKIP
11397 14:48:32.457103 # selftests: arm64: check_mmap_options
11398 14:48:32.489178 # # SKIP: MTE features unavailable
11399 14:48:32.495826 ok 39 selftests: arm64: check_mmap_options # SKIP
11400 14:48:32.505842 # selftests: arm64: check_prctl
11401 14:48:32.571134 # TAP version 13
11402 14:48:32.571703 # 1..5
11403 14:48:32.573877 # ok 1 check_basic_read
11404 14:48:32.574349 # ok 2 NONE
11405 14:48:32.577186 # ok 3 # SKIP SYNC
11406 14:48:32.577966 # ok 4 # SKIP ASYNC
11407 14:48:32.580784 # ok 5 # SKIP SYNC+ASYNC
11408 14:48:32.584000 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11409 14:48:32.587370 ok 40 selftests: arm64: check_prctl
11410 14:48:32.593764 # selftests: arm64: check_tags_inclusion
11411 14:48:32.661123 # # SKIP: MTE features unavailable
11412 14:48:32.668239 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11413 14:48:32.680911 # selftests: arm64: check_user_mem
11414 14:48:32.743017 # # SKIP: MTE features unavailable
11415 14:48:32.750817 ok 42 selftests: arm64: check_user_mem # SKIP
11416 14:48:32.764540 # selftests: arm64: btitest
11417 14:48:32.822849 # TAP version 13
11418 14:48:32.823429 # 1..18
11419 14:48:32.825885 # # HWCAP_PACA not present
11420 14:48:32.829358 # # HWCAP2_BTI not present
11421 14:48:32.829856 # # Test binary built for BTI
11422 14:48:32.835747 # ok 1 nohint_func/call_using_br_x0 # SKIP
11423 14:48:32.839178 # ok 1 nohint_func/call_using_br_x16 # SKIP
11424 14:48:32.842597 # ok 1 nohint_func/call_using_blr # SKIP
11425 14:48:32.845736 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11426 14:48:32.849009 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11427 14:48:32.855503 # ok 1 bti_none_func/call_using_blr # SKIP
11428 14:48:32.858843 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11429 14:48:32.862630 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11430 14:48:32.865544 # ok 1 bti_c_func/call_using_blr # SKIP
11431 14:48:32.868936 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11432 14:48:32.872047 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11433 14:48:32.875322 # ok 1 bti_j_func/call_using_blr # SKIP
11434 14:48:32.878684 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11435 14:48:32.885451 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11436 14:48:32.888889 # ok 1 bti_jc_func/call_using_blr # SKIP
11437 14:48:32.891926 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11438 14:48:32.895201 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11439 14:48:32.898395 # ok 1 paciasp_func/call_using_blr # SKIP
11440 14:48:32.904954 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11441 14:48:32.908411 # # WARNING - EXPECTED TEST COUNT WRONG
11442 14:48:32.911550 ok 43 selftests: arm64: btitest
11443 14:48:32.914900 # selftests: arm64: nobtitest
11444 14:48:32.915374 # TAP version 13
11445 14:48:32.915877 # 1..18
11446 14:48:32.918346 # # HWCAP_PACA not present
11447 14:48:32.921425 # # HWCAP2_BTI not present
11448 14:48:32.924924 # # Test binary not built for BTI
11449 14:48:32.928241 # ok 1 nohint_func/call_using_br_x0 # SKIP
11450 14:48:32.931465 # ok 1 nohint_func/call_using_br_x16 # SKIP
11451 14:48:32.934840 # ok 1 nohint_func/call_using_blr # SKIP
11452 14:48:32.938293 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11453 14:48:32.944497 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11454 14:48:32.948107 # ok 1 bti_none_func/call_using_blr # SKIP
11455 14:48:32.951310 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11456 14:48:32.954801 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11457 14:48:32.958285 # ok 1 bti_c_func/call_using_blr # SKIP
11458 14:48:32.961444 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11459 14:48:32.964919 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11460 14:48:32.967660 # ok 1 bti_j_func/call_using_blr # SKIP
11461 14:48:32.974420 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11462 14:48:32.977603 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11463 14:48:32.981029 # ok 1 bti_jc_func/call_using_blr # SKIP
11464 14:48:32.984014 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11465 14:48:32.987307 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11466 14:48:32.990783 # ok 1 paciasp_func/call_using_blr # SKIP
11467 14:48:32.997191 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11468 14:48:33.000790 # # WARNING - EXPECTED TEST COUNT WRONG
11469 14:48:33.003766 ok 44 selftests: arm64: nobtitest
11470 14:48:33.007284 # selftests: arm64: hwcap
11471 14:48:33.007743 # TAP version 13
11472 14:48:33.008102 # 1..28
11473 14:48:33.010770 # ok 1 cpuinfo_match_RNG
11474 14:48:33.013956 # # SIGILL reported for RNG
11475 14:48:33.017541 # ok 2 # SKIP sigill_RNG
11476 14:48:33.018095 # ok 3 cpuinfo_match_SME
11477 14:48:33.020772 # ok 4 sigill_SME
11478 14:48:33.021359 # ok 5 cpuinfo_match_SVE
11479 14:48:33.023607 # ok 6 sigill_SVE
11480 14:48:33.027119 # ok 7 cpuinfo_match_SVE 2
11481 14:48:33.027678 # # SIGILL reported for SVE 2
11482 14:48:33.030371 # ok 8 # SKIP sigill_SVE 2
11483 14:48:33.033638 # ok 9 cpuinfo_match_SVE AES
11484 14:48:33.036759 # # SIGILL reported for SVE AES
11485 14:48:33.040381 # ok 10 # SKIP sigill_SVE AES
11486 14:48:33.043370 # ok 11 cpuinfo_match_SVE2 PMULL
11487 14:48:33.046995 # # SIGILL reported for SVE2 PMULL
11488 14:48:33.047560 # ok 12 # SKIP sigill_SVE2 PMULL
11489 14:48:33.050180 # ok 13 cpuinfo_match_SVE2 BITPERM
11490 14:48:33.053798 # # SIGILL reported for SVE2 BITPERM
11491 14:48:33.056584 # ok 14 # SKIP sigill_SVE2 BITPERM
11492 14:48:33.059807 # ok 15 cpuinfo_match_SVE2 SHA3
11493 14:48:33.063316 # # SIGILL reported for SVE2 SHA3
11494 14:48:33.066635 # ok 16 # SKIP sigill_SVE2 SHA3
11495 14:48:33.069756 # ok 17 cpuinfo_match_SVE2 SM4
11496 14:48:33.073782 # # SIGILL reported for SVE2 SM4
11497 14:48:33.076284 # ok 18 # SKIP sigill_SVE2 SM4
11498 14:48:33.076741 # ok 19 cpuinfo_match_SVE2 I8MM
11499 14:48:33.079621 # # SIGILL reported for SVE2 I8MM
11500 14:48:33.083025 # ok 20 # SKIP sigill_SVE2 I8MM
11501 14:48:33.086834 # ok 21 cpuinfo_match_SVE2 F32MM
11502 14:48:33.089902 # # SIGILL reported for SVE2 F32MM
11503 14:48:33.093030 # ok 22 # SKIP sigill_SVE2 F32MM
11504 14:48:33.096413 # ok 23 cpuinfo_match_SVE2 F64MM
11505 14:48:33.099731 # # SIGILL reported for SVE2 F64MM
11506 14:48:33.102876 # ok 24 # SKIP sigill_SVE2 F64MM
11507 14:48:33.106014 # ok 25 cpuinfo_match_SVE2 BF16
11508 14:48:33.109058 # # SIGILL reported for SVE2 BF16
11509 14:48:33.109644 # ok 26 # SKIP sigill_SVE2 BF16
11510 14:48:33.112834 # ok 27 cpuinfo_match_SVE2 EBF16
11511 14:48:33.116034 # ok 28 # SKIP sigill_SVE2 EBF16
11512 14:48:33.122485 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11513 14:48:33.125682 ok 45 selftests: arm64: hwcap
11514 14:48:33.126144 # selftests: arm64: ptrace
11515 14:48:33.129000 # TAP version 13
11516 14:48:33.129674 # 1..7
11517 14:48:33.132317 # # Parent is 1489, child is 1490
11518 14:48:33.135614 # ok 1 read_tpidr_one
11519 14:48:33.136070 # ok 2 write_tpidr_one
11520 14:48:33.138856 # ok 3 verify_tpidr_one
11521 14:48:33.139319 # ok 4 count_tpidrs
11522 14:48:33.142196 # ok 5 tpidr2_write
11523 14:48:33.142654 # ok 6 tpidr2_read
11524 14:48:33.145509 # ok 7 write_tpidr_only
11525 14:48:33.152071 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11526 14:48:33.152533 ok 46 selftests: arm64: ptrace
11527 14:48:33.155761 # selftests: arm64: syscall-abi
11528 14:48:33.158726 # TAP version 13
11529 14:48:33.159181 # 1..2
11530 14:48:33.161919 # ok 1 getpid() FPSIMD
11531 14:48:33.162378 # ok 2 sched_yield() FPSIMD
11532 14:48:33.168561 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11533 14:48:33.171941 ok 47 selftests: arm64: syscall-abi
11534 14:48:33.175290 # selftests: arm64: tpidr2
11535 14:48:33.189932 # TAP version 13
11536 14:48:33.190518 # 1..5
11537 14:48:33.192869 # # PID: 1526
11538 14:48:33.193508 # # SME support not present
11539 14:48:33.196044 # ok 0 skipped, TPIDR2 not supported
11540 14:48:33.199494 # ok 1 skipped, TPIDR2 not supported
11541 14:48:33.202844 # ok 2 skipped, TPIDR2 not supported
11542 14:48:33.206305 # ok 3 skipped, TPIDR2 not supported
11543 14:48:33.209341 # ok 4 skipped, TPIDR2 not supported
11544 14:48:33.215891 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11545 14:48:33.219297 ok 48 selftests: arm64: tpidr2
11546 14:48:34.751070 arm64_tags_test pass
11547 14:48:34.754518 arm64_run_tags_test_sh pass
11548 14:48:34.757985 arm64_fake_sigreturn_bad_magic pass
11549 14:48:34.760857 arm64_fake_sigreturn_bad_size pass
11550 14:48:34.764318 arm64_fake_sigreturn_bad_size_for_magic0 pass
11551 14:48:34.767442 arm64_fake_sigreturn_duplicated_fpsimd pass
11552 14:48:34.770661 arm64_fake_sigreturn_misaligned_sp pass
11553 14:48:34.773839 arm64_fake_sigreturn_missing_fpsimd pass
11554 14:48:34.777269 arm64_fake_sigreturn_sme_change_vl skip
11555 14:48:34.783518 arm64_fake_sigreturn_sve_change_vl skip
11556 14:48:34.787015 arm64_mangle_pstate_invalid_compat_toggle pass
11557 14:48:34.790267 arm64_mangle_pstate_invalid_daif_bits pass
11558 14:48:34.793591 arm64_mangle_pstate_invalid_mode_el1h pass
11559 14:48:34.796875 arm64_mangle_pstate_invalid_mode_el1t pass
11560 14:48:34.799874 arm64_mangle_pstate_invalid_mode_el2h pass
11561 14:48:34.806859 arm64_mangle_pstate_invalid_mode_el2t pass
11562 14:48:34.809917 arm64_mangle_pstate_invalid_mode_el3h pass
11563 14:48:34.813163 arm64_mangle_pstate_invalid_mode_el3t pass
11564 14:48:34.816535 arm64_sme_trap_no_sm skip
11565 14:48:34.819997 arm64_sme_trap_non_streaming skip
11566 14:48:34.820079 arm64_sme_trap_za pass
11567 14:48:34.823279 arm64_sme_vl skip
11568 14:48:34.823363 arm64_ssve_regs skip
11569 14:48:34.826357 arm64_sve_regs skip
11570 14:48:34.826440 arm64_sve_vl skip
11571 14:48:34.829807 arm64_za_no_regs skip
11572 14:48:34.829893 arm64_za_regs skip
11573 14:48:34.833188 arm64_pac_PAUTH_not_enabled skip
11574 14:48:34.836453 arm64_pac_PAUTH_not_enabled_dup2 skip
11575 14:48:34.840049 arm64_pac_Generic_PAUTH_not_enabled skip
11576 14:48:34.842975 arm64_pac_PAUTH_not_enabled_dup3 skip
11577 14:48:34.849759 arm64_pac_PAUTH_not_enabled_dup4 skip
11578 14:48:34.852943 arm64_pac_PAUTH_not_enabled_dup5 skip
11579 14:48:34.856522 arm64_pac_Generic_PAUTH_not_enabled_dup2 skip
11580 14:48:34.856607 arm64_pac pass
11581 14:48:34.859938 arm64_fp-stress_FPSIMD-0-0 pass
11582 14:48:34.863284 arm64_fp-stress_FPSIMD-0-1 pass
11583 14:48:34.866274 arm64_fp-stress_FPSIMD-1-0 pass
11584 14:48:34.869965 arm64_fp-stress_FPSIMD-1-1 pass
11585 14:48:34.873082 arm64_fp-stress_FPSIMD-2-0 pass
11586 14:48:34.873201 arm64_fp-stress_FPSIMD-2-1 pass
11587 14:48:34.876101 arm64_fp-stress_FPSIMD-3-0 pass
11588 14:48:34.879587 arm64_fp-stress_FPSIMD-3-1 pass
11589 14:48:34.882883 arm64_fp-stress_FPSIMD-4-0 pass
11590 14:48:34.886142 arm64_fp-stress_FPSIMD-4-1 pass
11591 14:48:34.889213 arm64_fp-stress_FPSIMD-5-0 pass
11592 14:48:34.892508 arm64_fp-stress_FPSIMD-5-1 pass
11593 14:48:34.895879 arm64_fp-stress_FPSIMD-6-0 pass
11594 14:48:34.896072 arm64_fp-stress_FPSIMD-6-1 pass
11595 14:48:34.899207 arm64_fp-stress_FPSIMD-7-0 pass
11596 14:48:34.902638 arm64_fp-stress_FPSIMD-7-1 pass
11597 14:48:34.905673 arm64_fp-stress pass
11598 14:48:34.908914 arm64_sve-ptrace_SVE_not_available skip
11599 14:48:34.908998 arm64_sve-ptrace skip
11600 14:48:34.915606 arm64_sve-probe-vls_SVE_not_available skip
11601 14:48:34.915723 arm64_sve-probe-vls skip
11602 14:48:34.918940 arm64_vec-syscfg_SVE_not_supported skip
11603 14:48:34.922443 arm64_vec-syscfg_SVE_not_supported_dup2 skip
11604 14:48:34.928959 arm64_vec-syscfg_SVE_not_supported_dup3 skip
11605 14:48:34.932185 arm64_vec-syscfg_SVE_not_supported_dup4 skip
11606 14:48:34.935601 arm64_vec-syscfg_SVE_not_supported_dup5 skip
11607 14:48:34.938774 arm64_vec-syscfg_SVE_not_supported_dup6 skip
11608 14:48:34.945637 arm64_vec-syscfg_SVE_not_supported_dup7 skip
11609 14:48:34.948880 arm64_vec-syscfg_SVE_not_supported_dup8 skip
11610 14:48:34.952075 arm64_vec-syscfg_SVE_not_supported_dup9 skip
11611 14:48:34.955413 arm64_vec-syscfg_SVE_not_supported_dup10 skip
11612 14:48:34.958538 arm64_vec-syscfg_SME_not_supported skip
11613 14:48:34.962211 arm64_vec-syscfg_SME_not_supported_dup2 skip
11614 14:48:34.968573 arm64_vec-syscfg_SME_not_supported_dup3 skip
11615 14:48:34.971669 arm64_vec-syscfg_SME_not_supported_dup4 skip
11616 14:48:34.975071 arm64_vec-syscfg_SME_not_supported_dup5 skip
11617 14:48:34.978559 arm64_vec-syscfg_SME_not_supported_dup6 skip
11618 14:48:34.985010 arm64_vec-syscfg_SME_not_supported_dup7 skip
11619 14:48:34.988335 arm64_vec-syscfg_SME_not_supported_dup8 skip
11620 14:48:34.991486 arm64_vec-syscfg_SME_not_supported_dup9 skip
11621 14:48:34.994911 arm64_vec-syscfg_SME_not_supported_dup10 skip
11622 14:48:34.998714 arm64_vec-syscfg pass
11623 14:48:35.001516 arm64_za-fork_skipped pass
11624 14:48:35.001683 arm64_za-fork pass
11625 14:48:35.004835 arm64_za-ptrace_SME_not_available skip
11626 14:48:35.008037 arm64_za-ptrace skip
11627 14:48:35.008119 arm64_check_buffer_fill skip
11628 14:48:35.011773 arm64_check_child_memory skip
11629 14:48:35.015122 arm64_check_gcr_el1_cswitch skip
11630 14:48:35.018511 arm64_check_ksm_options skip
11631 14:48:35.021908 arm64_check_mmap_options skip
11632 14:48:35.024937 arm64_check_prctl_check_basic_read pass
11633 14:48:35.028086 arm64_check_prctl_NONE pass
11634 14:48:35.028262 arm64_check_prctl_SYNC skip
11635 14:48:35.031620 arm64_check_prctl_ASYNC skip
11636 14:48:35.034651 arm64_check_prctl_SYNC_ASYNC skip
11637 14:48:35.038248 arm64_check_prctl pass
11638 14:48:35.041317 arm64_check_tags_inclusion skip
11639 14:48:35.041510 arm64_check_user_mem skip
11640 14:48:35.047813 arm64_btitest_nohint_func_call_using_br_x0 skip
11641 14:48:35.051160 arm64_btitest_nohint_func_call_using_br_x16 skip
11642 14:48:35.054605 arm64_btitest_nohint_func_call_using_blr skip
11643 14:48:35.057570 arm64_btitest_bti_none_func_call_using_br_x0 skip
11644 14:48:35.064667 arm64_btitest_bti_none_func_call_using_br_x16 skip
11645 14:48:35.067953 arm64_btitest_bti_none_func_call_using_blr skip
11646 14:48:35.070999 arm64_btitest_bti_c_func_call_using_br_x0 skip
11647 14:48:35.077763 arm64_btitest_bti_c_func_call_using_br_x16 skip
11648 14:48:35.080767 arm64_btitest_bti_c_func_call_using_blr skip
11649 14:48:35.084351 arm64_btitest_bti_j_func_call_using_br_x0 skip
11650 14:48:35.087924 arm64_btitest_bti_j_func_call_using_br_x16 skip
11651 14:48:35.094201 arm64_btitest_bti_j_func_call_using_blr skip
11652 14:48:35.097385 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11653 14:48:35.100667 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11654 14:48:35.107270 arm64_btitest_bti_jc_func_call_using_blr skip
11655 14:48:35.110980 arm64_btitest_paciasp_func_call_using_br_x0 skip
11656 14:48:35.113914 arm64_btitest_paciasp_func_call_using_br_x16 skip
11657 14:48:35.117161 arm64_btitest_paciasp_func_call_using_blr skip
11658 14:48:35.120452 arm64_btitest pass
11659 14:48:35.123602 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11660 14:48:35.130308 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11661 14:48:35.133965 arm64_nobtitest_nohint_func_call_using_blr skip
11662 14:48:35.136906 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11663 14:48:35.143678 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11664 14:48:35.146854 arm64_nobtitest_bti_none_func_call_using_blr skip
11665 14:48:35.149995 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11666 14:48:35.156627 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11667 14:48:35.159903 arm64_nobtitest_bti_c_func_call_using_blr skip
11668 14:48:35.163266 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11669 14:48:35.169917 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11670 14:48:35.173618 arm64_nobtitest_bti_j_func_call_using_blr skip
11671 14:48:35.176448 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11672 14:48:35.183191 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11673 14:48:35.186503 arm64_nobtitest_bti_jc_func_call_using_blr skip
11674 14:48:35.189907 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11675 14:48:35.196530 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11676 14:48:35.199539 arm64_nobtitest_paciasp_func_call_using_blr skip
11677 14:48:35.203114 arm64_nobtitest pass
11678 14:48:35.206387 arm64_hwcap_cpuinfo_match_RNG pass
11679 14:48:35.206799 arm64_hwcap_sigill_RNG skip
11680 14:48:35.209666 arm64_hwcap_cpuinfo_match_SME pass
11681 14:48:35.212826 arm64_hwcap_sigill_SME pass
11682 14:48:35.216146 arm64_hwcap_cpuinfo_match_SVE pass
11683 14:48:35.219587 arm64_hwcap_sigill_SVE pass
11684 14:48:35.223092 arm64_hwcap_cpuinfo_match_SVE_2 pass
11685 14:48:35.226091 arm64_hwcap_sigill_SVE_2 skip
11686 14:48:35.229550 arm64_hwcap_cpuinfo_match_SVE_AES pass
11687 14:48:35.229964 arm64_hwcap_sigill_SVE_AES skip
11688 14:48:35.235907 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11689 14:48:35.239429 arm64_hwcap_sigill_SVE2_PMULL skip
11690 14:48:35.242906 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11691 14:48:35.245893 arm64_hwcap_sigill_SVE2_BITPERM skip
11692 14:48:35.249195 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11693 14:48:35.252756 arm64_hwcap_sigill_SVE2_SHA3 skip
11694 14:48:35.255999 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11695 14:48:35.259198 arm64_hwcap_sigill_SVE2_SM4 skip
11696 14:48:35.262598 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11697 14:48:35.265715 arm64_hwcap_sigill_SVE2_I8MM skip
11698 14:48:35.268970 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11699 14:48:35.272202 arm64_hwcap_sigill_SVE2_F32MM skip
11700 14:48:35.275534 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11701 14:48:35.279174 arm64_hwcap_sigill_SVE2_F64MM skip
11702 14:48:35.282115 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11703 14:48:35.285517 arm64_hwcap_sigill_SVE2_BF16 skip
11704 14:48:35.288790 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11705 14:48:35.292365 arm64_hwcap_sigill_SVE2_EBF16 skip
11706 14:48:35.292779 arm64_hwcap pass
11707 14:48:35.295380 arm64_ptrace_read_tpidr_one pass
11708 14:48:35.298640 arm64_ptrace_write_tpidr_one pass
11709 14:48:35.302144 arm64_ptrace_verify_tpidr_one pass
11710 14:48:35.305433 arm64_ptrace_count_tpidrs pass
11711 14:48:35.308772 arm64_ptrace_tpidr2_write pass
11712 14:48:35.312153 arm64_ptrace_tpidr2_read pass
11713 14:48:35.315226 arm64_ptrace_write_tpidr_only pass
11714 14:48:35.315639 arm64_ptrace pass
11715 14:48:35.318456 arm64_syscall-abi_getpid_FPSIMD pass
11716 14:48:35.321918 arm64_syscall-abi_sched_yield_FPSIMD pass
11717 14:48:35.325171 arm64_syscall-abi pass
11718 14:48:35.328242 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11719 14:48:35.335009 arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 pass
11720 14:48:35.338276 arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 pass
11721 14:48:35.341391 arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 pass
11722 14:48:35.348249 arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 pass
11723 14:48:35.348663 arm64_tpidr2 pass
11724 14:48:35.355094 + ../../utils/send-to-lava.sh ./output/result.txt
11725 14:48:35.358200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
11726 14:48:35.358970 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
11728 14:48:35.364636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11729 14:48:35.365342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11731 14:48:35.371293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11732 14:48:35.372003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
11734 14:48:35.377895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
11735 14:48:35.378631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
11737 14:48:35.384413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
11738 14:48:35.385122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
11740 14:48:35.408848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
11741 14:48:35.409376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
11743 14:48:35.452577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
11744 14:48:35.453270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
11746 14:48:35.496050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
11747 14:48:35.496412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
11749 14:48:35.537622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
11750 14:48:35.537900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
11752 14:48:35.585941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
11753 14:48:35.586518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
11755 14:48:35.629178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
11756 14:48:35.629934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
11758 14:48:35.683649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
11759 14:48:35.684371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
11761 14:48:35.735526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
11762 14:48:35.735796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
11764 14:48:35.779499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
11765 14:48:35.780228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
11767 14:48:35.826407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
11768 14:48:35.826678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
11770 14:48:35.874523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
11771 14:48:35.875159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
11773 14:48:35.923442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
11774 14:48:35.924122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
11776 14:48:35.974998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
11777 14:48:35.975697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
11779 14:48:36.017449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
11780 14:48:36.018200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
11782 14:48:36.065675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
11783 14:48:36.066455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
11785 14:48:36.111666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
11787 14:48:36.114563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
11788 14:48:36.161111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
11789 14:48:36.161958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
11791 14:48:36.214955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
11792 14:48:36.215755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
11794 14:48:36.263156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
11795 14:48:36.264042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
11797 14:48:36.312416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
11798 14:48:36.313391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
11800 14:48:36.352938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
11801 14:48:36.353227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
11803 14:48:36.391570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
11804 14:48:36.391875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
11806 14:48:36.424571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
11807 14:48:36.424865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
11809 14:48:36.466306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
11811 14:48:36.469454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
11812 14:48:36.509265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip>
11813 14:48:36.509577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip
11815 14:48:36.548427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
11816 14:48:36.548728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
11818 14:48:36.585132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip>
11819 14:48:36.585434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip
11821 14:48:36.629243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip>
11822 14:48:36.629557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip
11824 14:48:36.668849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip>
11825 14:48:36.669163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip
11827 14:48:36.705086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip>
11828 14:48:36.705416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip
11830 14:48:36.740699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
11831 14:48:36.740988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
11833 14:48:36.778969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
11834 14:48:36.779259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
11836 14:48:36.821091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
11837 14:48:36.821401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
11839 14:48:36.859053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
11840 14:48:36.859391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
11842 14:48:36.893632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
11843 14:48:36.893923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
11845 14:48:36.930089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
11846 14:48:36.930375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
11848 14:48:36.969651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
11849 14:48:36.969941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
11851 14:48:37.005514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
11852 14:48:37.005808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
11854 14:48:37.046930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
11855 14:48:37.047231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
11857 14:48:37.083648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
11858 14:48:37.084016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
11860 14:48:37.121216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
11861 14:48:37.121574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
11863 14:48:37.153853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
11864 14:48:37.154191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
11866 14:48:37.194534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
11867 14:48:37.194892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
11869 14:48:37.234268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
11870 14:48:37.234678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
11872 14:48:37.268293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
11873 14:48:37.268658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
11875 14:48:37.302901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
11876 14:48:37.303203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
11878 14:48:37.338718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
11879 14:48:37.339024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
11881 14:48:37.375557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
11882 14:48:37.375853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
11884 14:48:37.410070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
11885 14:48:37.410406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
11887 14:48:37.443702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
11888 14:48:37.444012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
11890 14:48:37.480034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
11891 14:48:37.480321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
11893 14:48:37.510701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
11894 14:48:37.510997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
11896 14:48:37.546545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
11897 14:48:37.546821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
11899 14:48:37.584253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip>
11900 14:48:37.584631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip
11902 14:48:37.621743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip>
11903 14:48:37.622106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip
11905 14:48:37.660036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip>
11906 14:48:37.660335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip
11908 14:48:37.694610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip>
11909 14:48:37.694918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip
11911 14:48:37.733485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip>
11912 14:48:37.733784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip
11914 14:48:37.773198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip>
11915 14:48:37.773504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip
11917 14:48:37.814533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip>
11918 14:48:37.814870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip
11920 14:48:37.856337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip>
11921 14:48:37.856661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip
11923 14:48:37.898151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip>
11924 14:48:37.898506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip
11926 14:48:37.932235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
11927 14:48:37.932576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
11929 14:48:37.965390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip>
11930 14:48:37.965729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip
11932 14:48:37.999220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip>
11933 14:48:37.999568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip
11935 14:48:38.035736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip>
11936 14:48:38.036082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip
11938 14:48:38.077341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip>
11939 14:48:38.077656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip
11941 14:48:38.115280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip>
11942 14:48:38.115588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip
11944 14:48:38.155709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip>
11945 14:48:38.156004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip
11947 14:48:38.189063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip>
11948 14:48:38.189365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip
11950 14:48:38.227762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip>
11951 14:48:38.228059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip
11953 14:48:38.262955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip>
11954 14:48:38.263246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip
11956 14:48:38.297472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
11957 14:48:38.297774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
11959 14:48:38.338175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
11960 14:48:38.338469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
11962 14:48:38.376800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
11963 14:48:38.377098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
11965 14:48:38.418933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
11966 14:48:38.419282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
11968 14:48:38.455027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
11969 14:48:38.455369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
11971 14:48:38.491869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
11972 14:48:38.492222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
11974 14:48:38.528673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
11975 14:48:38.529020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
11977 14:48:38.563629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
11979 14:48:38.566937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
11980 14:48:38.596702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
11981 14:48:38.597045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
11983 14:48:38.639242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
11984 14:48:38.639596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
11986 14:48:38.680514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
11987 14:48:38.680868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
11989 14:48:38.717394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
11990 14:48:38.717746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
11992 14:48:38.752909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
11993 14:48:38.753253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
11995 14:48:38.794374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
11996 14:48:38.794734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
11998 14:48:38.829718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12000 14:48:38.832682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12001 14:48:38.864074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12002 14:48:38.864415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12004 14:48:38.898759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12005 14:48:38.899121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12007 14:48:38.933926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12008 14:48:38.934272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12010 14:48:38.979011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12011 14:48:38.979376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12013 14:48:39.025416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12014 14:48:39.025771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12016 14:48:39.068353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12017 14:48:39.068668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12019 14:48:39.113138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12020 14:48:39.113496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12022 14:48:39.147803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12023 14:48:39.148112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12025 14:48:39.184401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12026 14:48:39.184701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12028 14:48:39.221079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12029 14:48:39.221408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12031 14:48:39.257854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12032 14:48:39.258167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12034 14:48:39.295749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12035 14:48:39.296061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12037 14:48:39.330565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12038 14:48:39.330859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12040 14:48:39.372043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12041 14:48:39.372332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12043 14:48:39.412956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12044 14:48:39.413276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12046 14:48:39.457947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12047 14:48:39.458259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12049 14:48:39.499886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12050 14:48:39.500240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12052 14:48:39.540212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12053 14:48:39.540567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12055 14:48:39.576981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12056 14:48:39.577354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12058 14:48:39.617685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12059 14:48:39.618037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12061 14:48:39.660540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12062 14:48:39.660895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12064 14:48:39.695555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12065 14:48:39.695893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12067 14:48:39.740342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12068 14:48:39.740703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12070 14:48:39.780036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12071 14:48:39.780393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12073 14:48:39.818457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12074 14:48:39.818806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12076 14:48:39.861385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12077 14:48:39.861750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12079 14:48:39.896541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12080 14:48:39.896897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12082 14:48:39.938452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12083 14:48:39.938803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12085 14:48:39.980059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12086 14:48:39.980402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12088 14:48:40.021081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12089 14:48:40.021428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12091 14:48:40.058635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12092 14:48:40.058963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12094 14:48:40.090551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12095 14:48:40.090878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12097 14:48:40.126449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12098 14:48:40.126803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12100 14:48:40.162275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12101 14:48:40.162595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12103 14:48:40.198061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12104 14:48:40.198409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12106 14:48:40.237553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12107 14:48:40.237897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12109 14:48:40.273384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12110 14:48:40.273714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12112 14:48:40.310282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12113 14:48:40.310616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12115 14:48:40.343266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12116 14:48:40.343592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12118 14:48:40.381492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12119 14:48:40.381822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12121 14:48:40.415119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12122 14:48:40.415441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12124 14:48:40.450141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12125 14:48:40.450476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12127 14:48:40.482620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12128 14:48:40.482936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12130 14:48:40.520881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12131 14:48:40.521196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12133 14:48:40.555021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12134 14:48:40.555321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12136 14:48:40.592830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12137 14:48:40.593158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12139 14:48:40.622357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12140 14:48:40.622679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12142 14:48:40.665400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12143 14:48:40.665731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12145 14:48:40.708585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12146 14:48:40.708935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12148 14:48:40.752354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12149 14:48:40.752687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12151 14:48:40.790482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12152 14:48:40.790806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12154 14:48:40.837426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12155 14:48:40.837752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12157 14:48:40.877862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12159 14:48:40.881066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12160 14:48:40.921719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12161 14:48:40.922020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12163 14:48:40.966174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12164 14:48:40.966474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12166 14:48:41.011372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12167 14:48:41.011687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12169 14:48:41.047434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12171 14:48:41.050197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12172 14:48:41.095205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12173 14:48:41.095518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12175 14:48:41.135430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12177 14:48:41.138304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12178 14:48:41.176860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12179 14:48:41.177164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12181 14:48:41.213690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12183 14:48:41.216501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12184 14:48:41.254653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12185 14:48:41.254943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12187 14:48:41.293199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12188 14:48:41.293554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12190 14:48:41.337589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12191 14:48:41.337928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12193 14:48:41.378616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12194 14:48:41.378909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12196 14:48:41.421350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12197 14:48:41.421658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12199 14:48:41.461249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12201 14:48:41.464057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12202 14:48:41.507440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12203 14:48:41.507737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12205 14:48:41.550458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12206 14:48:41.550756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12208 14:48:41.594603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12209 14:48:41.594943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12211 14:48:41.638373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12213 14:48:41.641285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12214 14:48:41.686698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12216 14:48:41.689581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12217 14:48:41.732720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12219 14:48:41.735809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12220 14:48:41.776581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12221 14:48:41.776872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12223 14:48:41.821702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12224 14:48:41.822011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12226 14:48:41.862255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12227 14:48:41.862551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12229 14:48:41.913248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12230 14:48:41.913590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12232 14:48:41.956402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12233 14:48:41.956706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12235 14:48:42.004205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12236 14:48:42.004511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12238 14:48:42.045078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12239 14:48:42.045366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12241 14:48:42.086168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12242 14:48:42.086487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12244 14:48:42.136786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12245 14:48:42.137106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12247 14:48:42.179235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass>
12248 14:48:42.179533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass
12250 14:48:42.222486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass>
12251 14:48:42.222798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass
12253 14:48:42.265276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass>
12254 14:48:42.265582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass
12256 14:48:42.304826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass>
12257 14:48:42.305147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass
12259 14:48:42.339866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12260 14:48:42.340001 + set +x
12261 14:48:42.340246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12263 14:48:42.346374 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 14167017_1.6.2.3.5>
12264 14:48:42.346649 Received signal: <ENDRUN> 1_kselftest-arm64 14167017_1.6.2.3.5
12265 14:48:42.346722 Ending use of test pattern.
12266 14:48:42.346784 Ending test lava.1_kselftest-arm64 (14167017_1.6.2.3.5), duration 30.32
12268 14:48:42.349977 <LAVA_TEST_RUNNER EXIT>
12269 14:48:42.350220 ok: lava_test_shell seems to have completed
12270 14:48:42.351442 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_Generic_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled_dup3: skip
arm64_pac_PAUTH_not_enabled_dup4: skip
arm64_pac_PAUTH_not_enabled_dup5: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup3: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup4: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup5: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SME_not_supported_dup10: skip
arm64_vec-syscfg_SME_not_supported_dup2: skip
arm64_vec-syscfg_SME_not_supported_dup3: skip
arm64_vec-syscfg_SME_not_supported_dup4: skip
arm64_vec-syscfg_SME_not_supported_dup5: skip
arm64_vec-syscfg_SME_not_supported_dup6: skip
arm64_vec-syscfg_SME_not_supported_dup7: skip
arm64_vec-syscfg_SME_not_supported_dup8: skip
arm64_vec-syscfg_SME_not_supported_dup9: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_vec-syscfg_SVE_not_supported_dup10: skip
arm64_vec-syscfg_SVE_not_supported_dup2: skip
arm64_vec-syscfg_SVE_not_supported_dup3: skip
arm64_vec-syscfg_SVE_not_supported_dup4: skip
arm64_vec-syscfg_SVE_not_supported_dup5: skip
arm64_vec-syscfg_SVE_not_supported_dup6: skip
arm64_vec-syscfg_SVE_not_supported_dup7: skip
arm64_vec-syscfg_SVE_not_supported_dup8: skip
arm64_vec-syscfg_SVE_not_supported_dup9: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12271 14:48:42.351602 end: 3.1 lava-test-shell (duration 00:00:31) [common]
12272 14:48:42.351694 end: 3 lava-test-retry (duration 00:00:31) [common]
12273 14:48:42.351778 start: 4 finalize (timeout 00:07:34) [common]
12274 14:48:42.351864 start: 4.1 power-off (timeout 00:00:30) [common]
12275 14:48:42.352014 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
12276 14:48:42.427117 >> Command sent successfully.
12277 14:48:42.429697 Returned 0 in 0 seconds
12278 14:48:42.530110 end: 4.1 power-off (duration 00:00:00) [common]
12280 14:48:42.530447 start: 4.2 read-feedback (timeout 00:07:33) [common]
12281 14:48:42.530713 Listened to connection for namespace 'common' for up to 1s
12282 14:48:43.531667 Finalising connection for namespace 'common'
12283 14:48:43.531839 Disconnecting from shell: Finalise
12284 14:48:43.531922 / #
12285 14:48:43.632214 end: 4.2 read-feedback (duration 00:00:01) [common]
12286 14:48:43.632387 end: 4 finalize (duration 00:00:01) [common]
12287 14:48:43.632502 Cleaning after the job
12288 14:48:43.632598 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167017/tftp-deploy-lmyx8m5s/ramdisk
12289 14:48:43.634779 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167017/tftp-deploy-lmyx8m5s/kernel
12290 14:48:43.645576 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167017/tftp-deploy-lmyx8m5s/dtb
12291 14:48:43.645774 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167017/tftp-deploy-lmyx8m5s/nfsrootfs
12292 14:48:43.710283 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167017/tftp-deploy-lmyx8m5s/modules
12293 14:48:43.715951 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14167017
12294 14:48:44.267553 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14167017
12295 14:48:44.267729 Job finished correctly