Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 34
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 14:42:34.556635 lava-dispatcher, installed at version: 2024.03
2 14:42:34.556831 start: 0 validate
3 14:42:34.556960 Start time: 2024-06-04 14:42:34.556953+00:00 (UTC)
4 14:42:34.557078 Using caching service: 'http://localhost/cache/?uri=%s'
5 14:42:34.557201 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 14:42:34.819748 Using caching service: 'http://localhost/cache/?uri=%s'
7 14:42:34.820623 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 14:42:35.084295 Using caching service: 'http://localhost/cache/?uri=%s'
9 14:42:35.085043 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 14:43:19.013905 Using caching service: 'http://localhost/cache/?uri=%s'
11 14:43:19.014575 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 14:43:19.528696 Using caching service: 'http://localhost/cache/?uri=%s'
13 14:43:19.529400 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 14:43:19.800845 validate duration: 45.24
16 14:43:19.802216 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 14:43:19.802779 start: 1.1 download-retry (timeout 00:10:00) [common]
18 14:43:19.803256 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 14:43:19.803864 Not decompressing ramdisk as can be used compressed.
20 14:43:19.804327 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 14:43:19.804682 saving as /var/lib/lava/dispatcher/tmp/14166991/tftp-deploy-4m917e0t/ramdisk/initrd.cpio.gz
22 14:43:19.805042 total size: 5628169 (5 MB)
23 14:43:26.979427 progress 0 % (0 MB)
24 14:43:26.989327 progress 5 % (0 MB)
25 14:43:26.998285 progress 10 % (0 MB)
26 14:43:27.006226 progress 15 % (0 MB)
27 14:43:27.011963 progress 20 % (1 MB)
28 14:43:27.015992 progress 25 % (1 MB)
29 14:43:27.019533 progress 30 % (1 MB)
30 14:43:27.022799 progress 35 % (1 MB)
31 14:43:27.025418 progress 40 % (2 MB)
32 14:43:27.028038 progress 45 % (2 MB)
33 14:43:27.030269 progress 50 % (2 MB)
34 14:43:27.032569 progress 55 % (2 MB)
35 14:43:27.034755 progress 60 % (3 MB)
36 14:43:27.036664 progress 65 % (3 MB)
37 14:43:27.038616 progress 70 % (3 MB)
38 14:43:27.040349 progress 75 % (4 MB)
39 14:43:27.042194 progress 80 % (4 MB)
40 14:43:27.043742 progress 85 % (4 MB)
41 14:43:27.045522 progress 90 % (4 MB)
42 14:43:27.047214 progress 95 % (5 MB)
43 14:43:27.048661 progress 100 % (5 MB)
44 14:43:27.048874 5 MB downloaded in 7.24 s (0.74 MB/s)
45 14:43:27.049026 end: 1.1.1 http-download (duration 00:00:07) [common]
47 14:43:27.049273 end: 1.1 download-retry (duration 00:00:07) [common]
48 14:43:27.049374 start: 1.2 download-retry (timeout 00:09:53) [common]
49 14:43:27.049460 start: 1.2.1 http-download (timeout 00:09:53) [common]
50 14:43:27.049603 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 14:43:27.049677 saving as /var/lib/lava/dispatcher/tmp/14166991/tftp-deploy-4m917e0t/kernel/Image
52 14:43:27.049740 total size: 54682112 (52 MB)
53 14:43:27.049804 No compression specified
54 14:43:27.310132 progress 0 % (0 MB)
55 14:43:27.361164 progress 5 % (2 MB)
56 14:43:27.379328 progress 10 % (5 MB)
57 14:43:27.393696 progress 15 % (7 MB)
58 14:43:27.407834 progress 20 % (10 MB)
59 14:43:27.422083 progress 25 % (13 MB)
60 14:43:27.435898 progress 30 % (15 MB)
61 14:43:27.449614 progress 35 % (18 MB)
62 14:43:27.463474 progress 40 % (20 MB)
63 14:43:27.477196 progress 45 % (23 MB)
64 14:43:27.491074 progress 50 % (26 MB)
65 14:43:27.504838 progress 55 % (28 MB)
66 14:43:27.518732 progress 60 % (31 MB)
67 14:43:27.536613 progress 65 % (33 MB)
68 14:43:27.550544 progress 70 % (36 MB)
69 14:43:27.564428 progress 75 % (39 MB)
70 14:43:27.578308 progress 80 % (41 MB)
71 14:43:27.591643 progress 85 % (44 MB)
72 14:43:27.605059 progress 90 % (46 MB)
73 14:43:27.618661 progress 95 % (49 MB)
74 14:43:27.632006 progress 100 % (52 MB)
75 14:43:27.632224 52 MB downloaded in 0.58 s (89.53 MB/s)
76 14:43:27.632372 end: 1.2.1 http-download (duration 00:00:01) [common]
78 14:43:27.632595 end: 1.2 download-retry (duration 00:00:01) [common]
79 14:43:27.632679 start: 1.3 download-retry (timeout 00:09:52) [common]
80 14:43:27.632760 start: 1.3.1 http-download (timeout 00:09:52) [common]
81 14:43:27.632898 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 14:43:27.632967 saving as /var/lib/lava/dispatcher/tmp/14166991/tftp-deploy-4m917e0t/dtb/mt8192-asurada-spherion-r0.dtb
83 14:43:27.633027 total size: 47258 (0 MB)
84 14:43:27.633087 No compression specified
85 14:43:27.634183 progress 69 % (0 MB)
86 14:43:27.634464 progress 100 % (0 MB)
87 14:43:27.634613 0 MB downloaded in 0.00 s (28.46 MB/s)
88 14:43:27.634730 end: 1.3.1 http-download (duration 00:00:00) [common]
90 14:43:27.634947 end: 1.3 download-retry (duration 00:00:00) [common]
91 14:43:27.635030 start: 1.4 download-retry (timeout 00:09:52) [common]
92 14:43:27.635109 start: 1.4.1 http-download (timeout 00:09:52) [common]
93 14:43:27.635215 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 14:43:27.635280 saving as /var/lib/lava/dispatcher/tmp/14166991/tftp-deploy-4m917e0t/nfsrootfs/full.rootfs.tar
95 14:43:27.635337 total size: 120894716 (115 MB)
96 14:43:27.635397 Using unxz to decompress xz
97 14:43:27.639437 progress 0 % (0 MB)
98 14:43:27.980252 progress 5 % (5 MB)
99 14:43:28.326103 progress 10 % (11 MB)
100 14:43:28.668005 progress 15 % (17 MB)
101 14:43:28.990220 progress 20 % (23 MB)
102 14:43:29.279371 progress 25 % (28 MB)
103 14:43:29.630841 progress 30 % (34 MB)
104 14:43:29.974229 progress 35 % (40 MB)
105 14:43:30.143512 progress 40 % (46 MB)
106 14:43:30.324568 progress 45 % (51 MB)
107 14:43:30.630097 progress 50 % (57 MB)
108 14:43:30.992876 progress 55 % (63 MB)
109 14:43:31.326532 progress 60 % (69 MB)
110 14:43:31.665583 progress 65 % (74 MB)
111 14:43:32.001171 progress 70 % (80 MB)
112 14:43:32.347206 progress 75 % (86 MB)
113 14:43:32.684204 progress 80 % (92 MB)
114 14:43:33.021275 progress 85 % (98 MB)
115 14:43:33.368884 progress 90 % (103 MB)
116 14:43:33.685573 progress 95 % (109 MB)
117 14:43:34.035924 progress 100 % (115 MB)
118 14:43:34.041190 115 MB downloaded in 6.41 s (18.00 MB/s)
119 14:43:34.041436 end: 1.4.1 http-download (duration 00:00:06) [common]
121 14:43:34.041701 end: 1.4 download-retry (duration 00:00:06) [common]
122 14:43:34.041791 start: 1.5 download-retry (timeout 00:09:46) [common]
123 14:43:34.041876 start: 1.5.1 http-download (timeout 00:09:46) [common]
124 14:43:34.042024 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 14:43:34.042094 saving as /var/lib/lava/dispatcher/tmp/14166991/tftp-deploy-4m917e0t/modules/modules.tar
126 14:43:34.042155 total size: 8608920 (8 MB)
127 14:43:34.042216 Using unxz to decompress xz
128 14:43:34.305376 progress 0 % (0 MB)
129 14:43:34.327872 progress 5 % (0 MB)
130 14:43:34.355275 progress 10 % (0 MB)
131 14:43:34.384684 progress 15 % (1 MB)
132 14:43:34.408134 progress 20 % (1 MB)
133 14:43:34.431320 progress 25 % (2 MB)
134 14:43:34.454611 progress 30 % (2 MB)
135 14:43:34.478778 progress 35 % (2 MB)
136 14:43:34.505116 progress 40 % (3 MB)
137 14:43:34.527396 progress 45 % (3 MB)
138 14:43:34.550948 progress 50 % (4 MB)
139 14:43:34.575834 progress 55 % (4 MB)
140 14:43:34.599913 progress 60 % (4 MB)
141 14:43:34.623780 progress 65 % (5 MB)
142 14:43:34.648212 progress 70 % (5 MB)
143 14:43:34.673744 progress 75 % (6 MB)
144 14:43:34.699057 progress 80 % (6 MB)
145 14:43:34.722757 progress 85 % (7 MB)
146 14:43:34.747887 progress 90 % (7 MB)
147 14:43:34.772709 progress 95 % (7 MB)
148 14:43:34.797589 progress 100 % (8 MB)
149 14:43:34.803031 8 MB downloaded in 0.76 s (10.79 MB/s)
150 14:43:34.803270 end: 1.5.1 http-download (duration 00:00:01) [common]
152 14:43:34.803536 end: 1.5 download-retry (duration 00:00:01) [common]
153 14:43:34.803629 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
154 14:43:34.803722 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
155 14:43:38.265505 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14166991/extract-nfsrootfs-__ac4z7s
156 14:43:38.265703 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 14:43:38.265802 start: 1.6.2 lava-overlay (timeout 00:09:42) [common]
158 14:43:38.265964 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b
159 14:43:38.266087 makedir: /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin
160 14:43:38.266184 makedir: /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/tests
161 14:43:38.266278 makedir: /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/results
162 14:43:38.266374 Creating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-add-keys
163 14:43:38.266513 Creating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-add-sources
164 14:43:38.266635 Creating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-background-process-start
165 14:43:38.266758 Creating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-background-process-stop
166 14:43:38.266878 Creating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-common-functions
167 14:43:38.266995 Creating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-echo-ipv4
168 14:43:38.267115 Creating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-install-packages
169 14:43:38.267283 Creating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-installed-packages
170 14:43:38.267472 Creating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-os-build
171 14:43:38.267616 Creating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-probe-channel
172 14:43:38.267737 Creating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-probe-ip
173 14:43:38.267857 Creating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-target-ip
174 14:43:38.267976 Creating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-target-mac
175 14:43:38.268095 Creating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-target-storage
176 14:43:38.268215 Creating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-test-case
177 14:43:38.268338 Creating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-test-event
178 14:43:38.268457 Creating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-test-feedback
179 14:43:38.268575 Creating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-test-raise
180 14:43:38.268692 Creating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-test-reference
181 14:43:38.268846 Creating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-test-runner
182 14:43:38.268964 Creating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-test-set
183 14:43:38.269084 Creating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-test-shell
184 14:43:38.269207 Updating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-add-keys (debian)
185 14:43:38.269419 Updating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-add-sources (debian)
186 14:43:38.269555 Updating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-install-packages (debian)
187 14:43:38.269689 Updating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-installed-packages (debian)
188 14:43:38.269821 Updating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/bin/lava-os-build (debian)
189 14:43:38.269935 Creating /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/environment
190 14:43:38.270026 LAVA metadata
191 14:43:38.270089 - LAVA_JOB_ID=14166991
192 14:43:38.270149 - LAVA_DISPATCHER_IP=192.168.201.1
193 14:43:38.270241 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:42) [common]
194 14:43:38.270305 skipped lava-vland-overlay
195 14:43:38.270376 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 14:43:38.270452 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:42) [common]
197 14:43:38.270509 skipped lava-multinode-overlay
198 14:43:38.270576 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 14:43:38.270649 start: 1.6.2.3 test-definition (timeout 00:09:42) [common]
200 14:43:38.270717 Loading test definitions
201 14:43:38.270800 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:42) [common]
202 14:43:38.270869 Using /lava-14166991 at stage 0
203 14:43:38.271132 uuid=14166991_1.6.2.3.1 testdef=None
204 14:43:38.271214 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 14:43:38.271293 start: 1.6.2.3.2 test-overlay (timeout 00:09:42) [common]
206 14:43:38.271727 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 14:43:38.271936 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:42) [common]
209 14:43:38.272456 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 14:43:38.272675 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:42) [common]
212 14:43:38.273196 runner path: /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/0/tests/0_timesync-off test_uuid 14166991_1.6.2.3.1
213 14:43:38.273580 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 14:43:38.273797 start: 1.6.2.3.5 git-repo-action (timeout 00:09:42) [common]
216 14:43:38.273866 Using /lava-14166991 at stage 0
217 14:43:38.273958 Fetching tests from https://github.com/kernelci/test-definitions.git
218 14:43:38.274040 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/0/tests/1_kselftest-dt'
219 14:43:41.348318 Running '/usr/bin/git checkout kernelci.org
220 14:43:41.493157 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 14:43:41.493937 uuid=14166991_1.6.2.3.5 testdef=None
222 14:43:41.494097 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 14:43:41.494353 start: 1.6.2.3.6 test-overlay (timeout 00:09:38) [common]
225 14:43:41.495075 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 14:43:41.495299 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:38) [common]
228 14:43:41.496259 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 14:43:41.496495 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:38) [common]
231 14:43:41.497445 runner path: /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/0/tests/1_kselftest-dt test_uuid 14166991_1.6.2.3.5
232 14:43:41.497533 BOARD='mt8192-asurada-spherion-r0'
233 14:43:41.497595 BRANCH='cip'
234 14:43:41.497653 SKIPFILE='/dev/null'
235 14:43:41.497708 SKIP_INSTALL='True'
236 14:43:41.497762 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 14:43:41.497817 TST_CASENAME=''
238 14:43:41.497871 TST_CMDFILES='dt'
239 14:43:41.498005 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 14:43:41.498203 Creating lava-test-runner.conf files
242 14:43:41.498264 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14166991/lava-overlay-3vkv2y_b/lava-14166991/0 for stage 0
243 14:43:41.498352 - 0_timesync-off
244 14:43:41.498418 - 1_kselftest-dt
245 14:43:41.498511 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 14:43:41.498596 start: 1.6.2.4 compress-overlay (timeout 00:09:38) [common]
247 14:43:49.091825 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 14:43:49.091976 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:31) [common]
249 14:43:49.092067 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 14:43:49.092160 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 14:43:49.092248 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:31) [common]
252 14:43:49.255133 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 14:43:49.255520 start: 1.6.4 extract-modules (timeout 00:09:31) [common]
254 14:43:49.255628 extracting modules file /var/lib/lava/dispatcher/tmp/14166991/tftp-deploy-4m917e0t/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14166991/extract-nfsrootfs-__ac4z7s
255 14:43:49.473848 extracting modules file /var/lib/lava/dispatcher/tmp/14166991/tftp-deploy-4m917e0t/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14166991/extract-overlay-ramdisk-wwtjdckp/ramdisk
256 14:43:49.695226 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 14:43:49.695395 start: 1.6.5 apply-overlay-tftp (timeout 00:09:30) [common]
258 14:43:49.695484 [common] Applying overlay to NFS
259 14:43:49.695553 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14166991/compress-overlay-hols32a4/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14166991/extract-nfsrootfs-__ac4z7s
260 14:43:50.597602 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 14:43:50.597775 start: 1.6.6 configure-preseed-file (timeout 00:09:29) [common]
262 14:43:50.597867 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 14:43:50.597963 start: 1.6.7 compress-ramdisk (timeout 00:09:29) [common]
264 14:43:50.598045 Building ramdisk /var/lib/lava/dispatcher/tmp/14166991/extract-overlay-ramdisk-wwtjdckp/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14166991/extract-overlay-ramdisk-wwtjdckp/ramdisk
265 14:43:50.946871 >> 130335 blocks
266 14:43:52.931560 rename /var/lib/lava/dispatcher/tmp/14166991/extract-overlay-ramdisk-wwtjdckp/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14166991/tftp-deploy-4m917e0t/ramdisk/ramdisk.cpio.gz
267 14:43:52.932026 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 14:43:52.932151 start: 1.6.8 prepare-kernel (timeout 00:09:27) [common]
269 14:43:52.932256 start: 1.6.8.1 prepare-fit (timeout 00:09:27) [common]
270 14:43:52.932364 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14166991/tftp-deploy-4m917e0t/kernel/Image']
271 14:44:05.729702 Returned 0 in 12 seconds
272 14:44:05.830375 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14166991/tftp-deploy-4m917e0t/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14166991/tftp-deploy-4m917e0t/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14166991/tftp-deploy-4m917e0t/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14166991/tftp-deploy-4m917e0t/kernel/image.itb
273 14:44:06.207690 output: FIT description: Kernel Image image with one or more FDT blobs
274 14:44:06.208064 output: Created: Tue Jun 4 15:44:06 2024
275 14:44:06.208140 output: Image 0 (kernel-1)
276 14:44:06.208207 output: Description:
277 14:44:06.208268 output: Created: Tue Jun 4 15:44:06 2024
278 14:44:06.208327 output: Type: Kernel Image
279 14:44:06.208390 output: Compression: lzma compressed
280 14:44:06.208452 output: Data Size: 13060619 Bytes = 12754.51 KiB = 12.46 MiB
281 14:44:06.208509 output: Architecture: AArch64
282 14:44:06.208567 output: OS: Linux
283 14:44:06.208622 output: Load Address: 0x00000000
284 14:44:06.208676 output: Entry Point: 0x00000000
285 14:44:06.208729 output: Hash algo: crc32
286 14:44:06.208784 output: Hash value: 88dcd836
287 14:44:06.208836 output: Image 1 (fdt-1)
288 14:44:06.208891 output: Description: mt8192-asurada-spherion-r0
289 14:44:06.208946 output: Created: Tue Jun 4 15:44:06 2024
290 14:44:06.209001 output: Type: Flat Device Tree
291 14:44:06.209054 output: Compression: uncompressed
292 14:44:06.209105 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 14:44:06.209157 output: Architecture: AArch64
294 14:44:06.209209 output: Hash algo: crc32
295 14:44:06.209260 output: Hash value: 0f8e4d2e
296 14:44:06.209318 output: Image 2 (ramdisk-1)
297 14:44:06.209371 output: Description: unavailable
298 14:44:06.209422 output: Created: Tue Jun 4 15:44:06 2024
299 14:44:06.209474 output: Type: RAMDisk Image
300 14:44:06.209525 output: Compression: Unknown Compression
301 14:44:06.209576 output: Data Size: 18730931 Bytes = 18291.92 KiB = 17.86 MiB
302 14:44:06.209628 output: Architecture: AArch64
303 14:44:06.209680 output: OS: Linux
304 14:44:06.209731 output: Load Address: unavailable
305 14:44:06.209783 output: Entry Point: unavailable
306 14:44:06.209834 output: Hash algo: crc32
307 14:44:06.209885 output: Hash value: c89b1367
308 14:44:06.209936 output: Default Configuration: 'conf-1'
309 14:44:06.209988 output: Configuration 0 (conf-1)
310 14:44:06.210039 output: Description: mt8192-asurada-spherion-r0
311 14:44:06.210090 output: Kernel: kernel-1
312 14:44:06.210141 output: Init Ramdisk: ramdisk-1
313 14:44:06.210192 output: FDT: fdt-1
314 14:44:06.210243 output: Loadables: kernel-1
315 14:44:06.210294 output:
316 14:44:06.210494 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 14:44:06.210588 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 14:44:06.210695 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 14:44:06.210786 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:14) [common]
320 14:44:06.210865 No LXC device requested
321 14:44:06.210942 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 14:44:06.211029 start: 1.8 deploy-device-env (timeout 00:09:14) [common]
323 14:44:06.211105 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 14:44:06.211171 Checking files for TFTP limit of 4294967296 bytes.
325 14:44:06.211667 end: 1 tftp-deploy (duration 00:00:46) [common]
326 14:44:06.211774 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 14:44:06.211863 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 14:44:06.211987 substitutions:
329 14:44:06.212053 - {DTB}: 14166991/tftp-deploy-4m917e0t/dtb/mt8192-asurada-spherion-r0.dtb
330 14:44:06.212115 - {INITRD}: 14166991/tftp-deploy-4m917e0t/ramdisk/ramdisk.cpio.gz
331 14:44:06.212173 - {KERNEL}: 14166991/tftp-deploy-4m917e0t/kernel/Image
332 14:44:06.212242 - {LAVA_MAC}: None
333 14:44:06.212301 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14166991/extract-nfsrootfs-__ac4z7s
334 14:44:06.212357 - {NFS_SERVER_IP}: 192.168.201.1
335 14:44:06.212410 - {PRESEED_CONFIG}: None
336 14:44:06.212464 - {PRESEED_LOCAL}: None
337 14:44:06.212517 - {RAMDISK}: 14166991/tftp-deploy-4m917e0t/ramdisk/ramdisk.cpio.gz
338 14:44:06.212570 - {ROOT_PART}: None
339 14:44:06.212623 - {ROOT}: None
340 14:44:06.212675 - {SERVER_IP}: 192.168.201.1
341 14:44:06.212727 - {TEE}: None
342 14:44:06.212779 Parsed boot commands:
343 14:44:06.212831 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 14:44:06.213015 Parsed boot commands: tftpboot 192.168.201.1 14166991/tftp-deploy-4m917e0t/kernel/image.itb 14166991/tftp-deploy-4m917e0t/kernel/cmdline
345 14:44:06.213101 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 14:44:06.213183 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 14:44:06.213271 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 14:44:06.213358 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 14:44:06.213429 Not connected, no need to disconnect.
350 14:44:06.213501 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 14:44:06.213584 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 14:44:06.213649 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 14:44:06.217339 Setting prompt string to ['lava-test: # ']
354 14:44:06.217694 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 14:44:06.217801 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 14:44:06.217896 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 14:44:06.217995 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 14:44:06.218253 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=reboot']
359 14:44:11.359655 >> Command sent successfully.
360 14:44:11.371018 Returned 0 in 5 seconds
361 14:44:11.472111 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 14:44:11.472930 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 14:44:11.473220 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 14:44:11.473495 Setting prompt string to 'Starting depthcharge on Spherion...'
366 14:44:11.473694 Changing prompt to 'Starting depthcharge on Spherion...'
367 14:44:11.473882 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 14:44:11.474950 [Enter `^Ec?' for help]
369 14:44:11.640986
370 14:44:11.641175
371 14:44:11.641276 F0: 102B 0000
372 14:44:11.641388
373 14:44:11.641452 F3: 1001 0000 [0200]
374 14:44:11.641511
375 14:44:11.644737 F3: 1001 0000
376 14:44:11.644848
377 14:44:11.644942 F7: 102D 0000
378 14:44:11.645032
379 14:44:11.645118 F1: 0000 0000
380 14:44:11.645203
381 14:44:11.648728 V0: 0000 0000 [0001]
382 14:44:11.648823
383 14:44:11.648909 00: 0007 8000
384 14:44:11.649000
385 14:44:11.652039 01: 0000 0000
386 14:44:11.652126
387 14:44:11.652192 BP: 0C00 0209 [0000]
388 14:44:11.652253
389 14:44:11.655705 G0: 1182 0000
390 14:44:11.655797
391 14:44:11.655863 EC: 0000 0021 [4000]
392 14:44:11.655924
393 14:44:11.659382 S7: 0000 0000 [0000]
394 14:44:11.659466
395 14:44:11.659531 CC: 0000 0000 [0001]
396 14:44:11.659592
397 14:44:11.662703 T0: 0000 0040 [010F]
398 14:44:11.662786
399 14:44:11.662852 Jump to BL
400 14:44:11.662912
401 14:44:11.687741
402 14:44:11.687917
403 14:44:11.694541 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 14:44:11.697798 ARM64: Exception handlers installed.
405 14:44:11.701673 ARM64: Testing exception
406 14:44:11.704888 ARM64: Done test exception
407 14:44:11.712385 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 14:44:11.722834 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 14:44:11.730032 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 14:44:11.739768 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 14:44:11.746576 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 14:44:11.753159 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 14:44:11.764377 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 14:44:11.771115 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 14:44:11.790356 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 14:44:11.793710 WDT: Last reset was cold boot
417 14:44:11.797321 SPI1(PAD0) initialized at 2873684 Hz
418 14:44:11.800591 SPI5(PAD0) initialized at 992727 Hz
419 14:44:11.803838 VBOOT: Loading verstage.
420 14:44:11.810852 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 14:44:11.813742 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 14:44:11.816895 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 14:44:11.820365 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 14:44:11.828024 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 14:44:11.834495 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 14:44:11.845762 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
427 14:44:11.846194
428 14:44:11.846528
429 14:44:11.855743 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 14:44:11.859294 ARM64: Exception handlers installed.
431 14:44:11.862424 ARM64: Testing exception
432 14:44:11.862725 ARM64: Done test exception
433 14:44:11.868667 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 14:44:11.872075 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 14:44:11.886404 Probing TPM: . done!
436 14:44:11.886542 TPM ready after 0 ms
437 14:44:11.893647 Connected to device vid:did:rid of 1ae0:0028:00
438 14:44:11.900231 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
439 14:44:11.949395 Initialized TPM device CR50 revision 0
440 14:44:11.965228 tlcl_send_startup: Startup return code is 0
441 14:44:11.965727 TPM: setup succeeded
442 14:44:11.975765 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 14:44:11.984890 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 14:44:11.994111 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 14:44:12.003079 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 14:44:12.006334 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 14:44:12.009813 in-header: 03 07 00 00 08 00 00 00
448 14:44:12.013103 in-data: aa e4 47 04 13 02 00 00
449 14:44:12.016374 Chrome EC: UHEPI supported
450 14:44:12.023196 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 14:44:12.026344 in-header: 03 95 00 00 08 00 00 00
452 14:44:12.030214 in-data: 18 20 20 08 00 00 00 00
453 14:44:12.030317 Phase 1
454 14:44:12.033813 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 14:44:12.040906 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 14:44:12.044594 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
457 14:44:12.048353 Recovery requested (1009000e)
458 14:44:12.058060 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 14:44:12.063543 tlcl_extend: response is 0
460 14:44:12.073128 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 14:44:12.078664 tlcl_extend: response is 0
462 14:44:12.086173 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 14:44:12.106318 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
464 14:44:12.113534 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 14:44:12.114134
466 14:44:12.114505
467 14:44:12.124137 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 14:44:12.124744 ARM64: Exception handlers installed.
469 14:44:12.127592 ARM64: Testing exception
470 14:44:12.130883 ARM64: Done test exception
471 14:44:12.151345 pmic_efuse_setting: Set efuses in 11 msecs
472 14:44:12.154664 pmwrap_interface_init: Select PMIF_VLD_RDY
473 14:44:12.161310 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 14:44:12.164757 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 14:44:12.170984 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 14:44:12.174638 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 14:44:12.181100 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 14:44:12.184724 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 14:44:12.188018 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 14:44:12.194598 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 14:44:12.197712 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 14:44:12.204906 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 14:44:12.207856 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 14:44:12.211122 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 14:44:12.218005 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 14:44:12.224999 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 14:44:12.228749 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 14:44:12.235655 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 14:44:12.239237 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 14:44:12.246692 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 14:44:12.253740 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 14:44:12.257674 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 14:44:12.264981 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 14:44:12.268330 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 14:44:12.275708 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 14:44:12.279229 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 14:44:12.286180 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 14:44:12.289614 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 14:44:12.297271 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 14:44:12.300799 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 14:44:12.304227 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 14:44:12.311484 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 14:44:12.315037 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 14:44:12.322118 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 14:44:12.325886 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 14:44:12.329403 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 14:44:12.336643 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 14:44:12.340121 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 14:44:12.343906 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 14:44:12.351343 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 14:44:12.354781 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 14:44:12.358353 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 14:44:12.362467 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 14:44:12.369432 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 14:44:12.372902 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 14:44:12.376595 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 14:44:12.380310 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 14:44:12.384106 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 14:44:12.391323 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 14:44:12.394827 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 14:44:12.398443 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 14:44:12.402006 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 14:44:12.406001 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 14:44:12.413118 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
525 14:44:12.423834 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 14:44:12.427423 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 14:44:12.434947 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 14:44:12.445464 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 14:44:12.449199 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 14:44:12.452842 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 14:44:12.456317 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 14:44:12.464447 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x18
533 14:44:12.468495 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 14:44:12.476535 [RTC]rtc_osc_init,62: osc32con val = 0xde70
535 14:44:12.479642 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 14:44:12.488646 [RTC]rtc_get_frequency_meter,154: input=15, output=764
537 14:44:12.498156 [RTC]rtc_get_frequency_meter,154: input=23, output=948
538 14:44:12.507833 [RTC]rtc_get_frequency_meter,154: input=19, output=855
539 14:44:12.516962 [RTC]rtc_get_frequency_meter,154: input=17, output=811
540 14:44:12.526953 [RTC]rtc_get_frequency_meter,154: input=16, output=788
541 14:44:12.536712 [RTC]rtc_get_frequency_meter,154: input=16, output=787
542 14:44:12.546941 [RTC]rtc_get_frequency_meter,154: input=17, output=809
543 14:44:12.550331 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
544 14:44:12.554358 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
545 14:44:12.557913 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 14:44:12.565070 [RTC]rtc_boot_common,220: irqsta=1, bbpu=81, con=486
547 14:44:12.569047 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 14:44:12.572241 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
549 14:44:12.576403 ADC[4]: Raw value=671168 ID=5
550 14:44:12.576982 ADC[3]: Raw value=212549 ID=1
551 14:44:12.580160 RAM Code: 0x51
552 14:44:12.584017 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 14:44:12.587713 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 14:44:12.595297 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
555 14:44:12.602164 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
556 14:44:12.605981 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 14:44:12.609560 in-header: 03 07 00 00 08 00 00 00
558 14:44:12.613535 in-data: aa e4 47 04 13 02 00 00
559 14:44:12.614017 Chrome EC: UHEPI supported
560 14:44:12.620421 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 14:44:12.624585 in-header: 03 95 00 00 08 00 00 00
562 14:44:12.628028 in-data: 18 20 20 08 00 00 00 00
563 14:44:12.631663 MRC: failed to locate region type 0.
564 14:44:12.639159 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 14:44:12.643214 DRAM-K: Running full calibration
566 14:44:12.647205 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
567 14:44:12.650540 header.status = 0x0
568 14:44:12.654269 header.version = 0x6 (expected: 0x6)
569 14:44:12.654750 header.size = 0xd00 (expected: 0xd00)
570 14:44:12.657897 header.flags = 0x0
571 14:44:12.664786 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 14:44:12.682506 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
573 14:44:12.689776 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 14:44:12.690261 dram_init: ddr_geometry: 0
575 14:44:12.693444 [EMI] MDL number = 0
576 14:44:12.697538 [EMI] Get MDL freq = 0
577 14:44:12.698129 dram_init: ddr_type: 0
578 14:44:12.700999 is_discrete_lpddr4: 1
579 14:44:12.704501 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 14:44:12.705083
581 14:44:12.705559
582 14:44:12.705921 [Bian_co] ETT version 0.0.0.1
583 14:44:12.712047 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
584 14:44:12.712637
585 14:44:12.715322 dramc_set_vcore_voltage set vcore to 650000
586 14:44:12.715985 Read voltage for 800, 4
587 14:44:12.719113 Vio18 = 0
588 14:44:12.719587 Vcore = 650000
589 14:44:12.719957 Vdram = 0
590 14:44:12.720299 Vddq = 0
591 14:44:12.723260 Vmddr = 0
592 14:44:12.723836 dram_init: config_dvfs: 1
593 14:44:12.730159 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 14:44:12.734178 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 14:44:12.737551 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
596 14:44:12.741373 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
597 14:44:12.745040 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
598 14:44:12.748799 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
599 14:44:12.752426 MEM_TYPE=3, freq_sel=18
600 14:44:12.756255 sv_algorithm_assistance_LP4_1600
601 14:44:12.759548 ============ PULL DRAM RESETB DOWN ============
602 14:44:12.762979 ========== PULL DRAM RESETB DOWN end =========
603 14:44:12.766964 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 14:44:12.770358 ===================================
605 14:44:12.773925 LPDDR4 DRAM CONFIGURATION
606 14:44:12.777738 ===================================
607 14:44:12.778217 EX_ROW_EN[0] = 0x0
608 14:44:12.781896 EX_ROW_EN[1] = 0x0
609 14:44:12.782366 LP4Y_EN = 0x0
610 14:44:12.785223 WORK_FSP = 0x0
611 14:44:12.785733 WL = 0x2
612 14:44:12.788844 RL = 0x2
613 14:44:12.789357 BL = 0x2
614 14:44:12.792260 RPST = 0x0
615 14:44:12.792736 RD_PRE = 0x0
616 14:44:12.795986 WR_PRE = 0x1
617 14:44:12.796462 WR_PST = 0x0
618 14:44:12.796836 DBI_WR = 0x0
619 14:44:12.799774 DBI_RD = 0x0
620 14:44:12.800391 OTF = 0x1
621 14:44:12.803284 ===================================
622 14:44:12.806789 ===================================
623 14:44:12.810370 ANA top config
624 14:44:12.814106 ===================================
625 14:44:12.814587 DLL_ASYNC_EN = 0
626 14:44:12.817479 ALL_SLAVE_EN = 1
627 14:44:12.821461 NEW_RANK_MODE = 1
628 14:44:12.821951 DLL_IDLE_MODE = 1
629 14:44:12.824713 LP45_APHY_COMB_EN = 1
630 14:44:12.828795 TX_ODT_DIS = 1
631 14:44:12.831762 NEW_8X_MODE = 1
632 14:44:12.835323 ===================================
633 14:44:12.838623 ===================================
634 14:44:12.839219 data_rate = 1600
635 14:44:12.842091 CKR = 1
636 14:44:12.845692 DQ_P2S_RATIO = 8
637 14:44:12.849200 ===================================
638 14:44:12.852669 CA_P2S_RATIO = 8
639 14:44:12.853141 DQ_CA_OPEN = 0
640 14:44:12.856435 DQ_SEMI_OPEN = 0
641 14:44:12.859807 CA_SEMI_OPEN = 0
642 14:44:12.863765 CA_FULL_RATE = 0
643 14:44:12.864360 DQ_CKDIV4_EN = 1
644 14:44:12.866834 CA_CKDIV4_EN = 1
645 14:44:12.870684 CA_PREDIV_EN = 0
646 14:44:12.873521 PH8_DLY = 0
647 14:44:12.877043 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 14:44:12.880195 DQ_AAMCK_DIV = 4
649 14:44:12.880691 CA_AAMCK_DIV = 4
650 14:44:12.883849 CA_ADMCK_DIV = 4
651 14:44:12.887604 DQ_TRACK_CA_EN = 0
652 14:44:12.890738 CA_PICK = 800
653 14:44:12.893972 CA_MCKIO = 800
654 14:44:12.897408 MCKIO_SEMI = 0
655 14:44:12.897877 PLL_FREQ = 3068
656 14:44:12.900719 DQ_UI_PI_RATIO = 32
657 14:44:12.904498 CA_UI_PI_RATIO = 0
658 14:44:12.907390 ===================================
659 14:44:12.911562 ===================================
660 14:44:12.915084 memory_type:LPDDR4
661 14:44:12.915560 GP_NUM : 10
662 14:44:12.918849 SRAM_EN : 1
663 14:44:12.919534 MD32_EN : 0
664 14:44:12.922394 ===================================
665 14:44:12.926315 [ANA_INIT] >>>>>>>>>>>>>>
666 14:44:12.929987 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 14:44:12.933774 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 14:44:12.934344 ===================================
669 14:44:12.937064 data_rate = 1600,PCW = 0X7600
670 14:44:12.940822 ===================================
671 14:44:12.944507 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 14:44:12.951190 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 14:44:12.954439 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 14:44:12.961043 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 14:44:12.964287 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 14:44:12.968159 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 14:44:12.968727 [ANA_INIT] flow start
678 14:44:12.970923 [ANA_INIT] PLL >>>>>>>>
679 14:44:12.974339 [ANA_INIT] PLL <<<<<<<<
680 14:44:12.974825 [ANA_INIT] MIDPI >>>>>>>>
681 14:44:12.977636 [ANA_INIT] MIDPI <<<<<<<<
682 14:44:12.981240 [ANA_INIT] DLL >>>>>>>>
683 14:44:12.981841 [ANA_INIT] flow end
684 14:44:12.987800 ============ LP4 DIFF to SE enter ============
685 14:44:12.991295 ============ LP4 DIFF to SE exit ============
686 14:44:12.994835 [ANA_INIT] <<<<<<<<<<<<<
687 14:44:12.997815 [Flow] Enable top DCM control >>>>>
688 14:44:13.001514 [Flow] Enable top DCM control <<<<<
689 14:44:13.002005 Enable DLL master slave shuffle
690 14:44:13.007624 ==============================================================
691 14:44:13.011169 Gating Mode config
692 14:44:13.014582 ==============================================================
693 14:44:13.017844 Config description:
694 14:44:13.027806 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 14:44:13.034476 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 14:44:13.037769 SELPH_MODE 0: By rank 1: By Phase
697 14:44:13.044570 ==============================================================
698 14:44:13.047933 GAT_TRACK_EN = 1
699 14:44:13.051145 RX_GATING_MODE = 2
700 14:44:13.054854 RX_GATING_TRACK_MODE = 2
701 14:44:13.055425 SELPH_MODE = 1
702 14:44:13.057595 PICG_EARLY_EN = 1
703 14:44:13.061286 VALID_LAT_VALUE = 1
704 14:44:13.068040 ==============================================================
705 14:44:13.071121 Enter into Gating configuration >>>>
706 14:44:13.074289 Exit from Gating configuration <<<<
707 14:44:13.077689 Enter into DVFS_PRE_config >>>>>
708 14:44:13.087694 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 14:44:13.091049 Exit from DVFS_PRE_config <<<<<
710 14:44:13.094365 Enter into PICG configuration >>>>
711 14:44:13.097626 Exit from PICG configuration <<<<
712 14:44:13.100972 [RX_INPUT] configuration >>>>>
713 14:44:13.104322 [RX_INPUT] configuration <<<<<
714 14:44:13.107714 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 14:44:13.114280 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 14:44:13.121058 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 14:44:13.127893 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 14:44:13.130882 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 14:44:13.137561 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 14:44:13.141005 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 14:44:13.147180 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 14:44:13.150965 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 14:44:13.154096 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 14:44:13.157072 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 14:44:13.164183 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 14:44:13.167339 ===================================
727 14:44:13.170656 LPDDR4 DRAM CONFIGURATION
728 14:44:13.173805 ===================================
729 14:44:13.174273 EX_ROW_EN[0] = 0x0
730 14:44:13.177017 EX_ROW_EN[1] = 0x0
731 14:44:13.177558 LP4Y_EN = 0x0
732 14:44:13.180704 WORK_FSP = 0x0
733 14:44:13.181276 WL = 0x2
734 14:44:13.183825 RL = 0x2
735 14:44:13.184400 BL = 0x2
736 14:44:13.187333 RPST = 0x0
737 14:44:13.187802 RD_PRE = 0x0
738 14:44:13.190862 WR_PRE = 0x1
739 14:44:13.191431 WR_PST = 0x0
740 14:44:13.193859 DBI_WR = 0x0
741 14:44:13.194431 DBI_RD = 0x0
742 14:44:13.197046 OTF = 0x1
743 14:44:13.200463 ===================================
744 14:44:13.203657 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 14:44:13.206883 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 14:44:13.213506 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 14:44:13.217041 ===================================
748 14:44:13.217545 LPDDR4 DRAM CONFIGURATION
749 14:44:13.220444 ===================================
750 14:44:13.223833 EX_ROW_EN[0] = 0x10
751 14:44:13.227020 EX_ROW_EN[1] = 0x0
752 14:44:13.227492 LP4Y_EN = 0x0
753 14:44:13.230136 WORK_FSP = 0x0
754 14:44:13.230628 WL = 0x2
755 14:44:13.233577 RL = 0x2
756 14:44:13.234146 BL = 0x2
757 14:44:13.237083 RPST = 0x0
758 14:44:13.237625 RD_PRE = 0x0
759 14:44:13.240457 WR_PRE = 0x1
760 14:44:13.241020 WR_PST = 0x0
761 14:44:13.243902 DBI_WR = 0x0
762 14:44:13.244466 DBI_RD = 0x0
763 14:44:13.247129 OTF = 0x1
764 14:44:13.250086 ===================================
765 14:44:13.257330 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 14:44:13.260283 nWR fixed to 40
767 14:44:13.263721 [ModeRegInit_LP4] CH0 RK0
768 14:44:13.264296 [ModeRegInit_LP4] CH0 RK1
769 14:44:13.267019 [ModeRegInit_LP4] CH1 RK0
770 14:44:13.270216 [ModeRegInit_LP4] CH1 RK1
771 14:44:13.270787 match AC timing 12
772 14:44:13.276853 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
773 14:44:13.280387 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 14:44:13.283896 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 14:44:13.290431 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 14:44:13.293417 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 14:44:13.293897 [EMI DOE] emi_dcm 0
778 14:44:13.300482 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 14:44:13.301093 ==
780 14:44:13.303941 Dram Type= 6, Freq= 0, CH_0, rank 0
781 14:44:13.307000 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 14:44:13.307475 ==
783 14:44:13.313518 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 14:44:13.317097 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 14:44:13.327348 [CA 0] Center 37 (7~68) winsize 62
786 14:44:13.330539 [CA 1] Center 37 (7~68) winsize 62
787 14:44:13.333942 [CA 2] Center 35 (5~66) winsize 62
788 14:44:13.337567 [CA 3] Center 35 (4~66) winsize 63
789 14:44:13.340797 [CA 4] Center 34 (4~65) winsize 62
790 14:44:13.343923 [CA 5] Center 34 (4~64) winsize 61
791 14:44:13.344489
792 14:44:13.347232 [CmdBusTrainingLP45] Vref(ca) range 1: 34
793 14:44:13.347711
794 14:44:13.350602 [CATrainingPosCal] consider 1 rank data
795 14:44:13.354035 u2DelayCellTimex100 = 270/100 ps
796 14:44:13.357433 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
797 14:44:13.360732 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
798 14:44:13.367636 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
799 14:44:13.370705 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
800 14:44:13.374094 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
801 14:44:13.376946 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
802 14:44:13.377456
803 14:44:13.380895 CA PerBit enable=1, Macro0, CA PI delay=34
804 14:44:13.381521
805 14:44:13.384000 [CBTSetCACLKResult] CA Dly = 34
806 14:44:13.384463 CS Dly: 5 (0~36)
807 14:44:13.384831 ==
808 14:44:13.387539 Dram Type= 6, Freq= 0, CH_0, rank 1
809 14:44:13.394023 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
810 14:44:13.394580 ==
811 14:44:13.397026 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 14:44:13.404119 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 14:44:13.413120 [CA 0] Center 37 (7~68) winsize 62
814 14:44:13.416500 [CA 1] Center 37 (6~68) winsize 63
815 14:44:13.419778 [CA 2] Center 35 (4~66) winsize 63
816 14:44:13.423003 [CA 3] Center 34 (4~65) winsize 62
817 14:44:13.426490 [CA 4] Center 33 (3~64) winsize 62
818 14:44:13.429700 [CA 5] Center 33 (3~64) winsize 62
819 14:44:13.430262
820 14:44:13.432984 [CmdBusTrainingLP45] Vref(ca) range 1: 32
821 14:44:13.433550
822 14:44:13.436260 [CATrainingPosCal] consider 2 rank data
823 14:44:13.440235 u2DelayCellTimex100 = 270/100 ps
824 14:44:13.443213 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
825 14:44:13.446769 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
826 14:44:13.452987 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
827 14:44:13.456506 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
828 14:44:13.459821 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
829 14:44:13.463568 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
830 14:44:13.464173
831 14:44:13.466282 CA PerBit enable=1, Macro0, CA PI delay=34
832 14:44:13.466789
833 14:44:13.469968 [CBTSetCACLKResult] CA Dly = 34
834 14:44:13.470538 CS Dly: 6 (0~38)
835 14:44:13.470934
836 14:44:13.473104 ----->DramcWriteLeveling(PI) begin...
837 14:44:13.473681 ==
838 14:44:13.476217 Dram Type= 6, Freq= 0, CH_0, rank 0
839 14:44:13.483039 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
840 14:44:13.483518 ==
841 14:44:13.486529 Write leveling (Byte 0): 31 => 31
842 14:44:13.489935 Write leveling (Byte 1): 30 => 30
843 14:44:13.490413 DramcWriteLeveling(PI) end<-----
844 14:44:13.490785
845 14:44:13.493610 ==
846 14:44:13.494083 Dram Type= 6, Freq= 0, CH_0, rank 0
847 14:44:13.497518 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
848 14:44:13.500928 ==
849 14:44:13.501471 [Gating] SW mode calibration
850 14:44:13.508036 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 14:44:13.515274 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 14:44:13.518343 0 6 0 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
853 14:44:13.522043 0 6 4 | B1->B0 | 2828 2424 | 0 0 | (1 1) (0 0)
854 14:44:13.528681 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 14:44:13.532124 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 14:44:13.535288 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 14:44:13.542213 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 14:44:13.545209 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 14:44:13.548703 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 14:44:13.555410 0 7 0 | B1->B0 | 2424 2626 | 1 0 | (0 0) (0 0)
861 14:44:13.558650 0 7 4 | B1->B0 | 3939 4343 | 0 0 | (0 0) (0 0)
862 14:44:13.561913 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 14:44:13.568919 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 14:44:13.572010 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 14:44:13.575323 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 14:44:13.582000 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 14:44:13.585171 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 14:44:13.588862 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
869 14:44:13.592295 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
870 14:44:13.598736 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 14:44:13.601735 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 14:44:13.605509 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 14:44:13.611755 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 14:44:13.615141 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 14:44:13.618656 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 14:44:13.625212 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 14:44:13.628742 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 14:44:13.632184 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 14:44:13.638751 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 14:44:13.642149 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 14:44:13.645481 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 14:44:13.652188 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 14:44:13.655377 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 14:44:13.658809 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
885 14:44:13.665068 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 14:44:13.665622 Total UI for P1: 0, mck2ui 16
887 14:44:13.668665 best dqsien dly found for B0: ( 0, 10, 0)
888 14:44:13.671903 Total UI for P1: 0, mck2ui 16
889 14:44:13.675750 best dqsien dly found for B1: ( 0, 10, 0)
890 14:44:13.678636 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
891 14:44:13.685522 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
892 14:44:13.686126
893 14:44:13.688488 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
894 14:44:13.691692 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
895 14:44:13.695079 [Gating] SW calibration Done
896 14:44:13.695564 ==
897 14:44:13.698685 Dram Type= 6, Freq= 0, CH_0, rank 0
898 14:44:13.701789 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
899 14:44:13.702352 ==
900 14:44:13.702739 RX Vref Scan: 0
901 14:44:13.705007
902 14:44:13.705504 RX Vref 0 -> 0, step: 1
903 14:44:13.705883
904 14:44:13.708718 RX Delay -130 -> 252, step: 16
905 14:44:13.711718 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
906 14:44:13.715110 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
907 14:44:13.721626 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
908 14:44:13.724927 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
909 14:44:13.728812 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
910 14:44:13.731633 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
911 14:44:13.735014 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
912 14:44:13.742008 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
913 14:44:13.744821 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
914 14:44:13.748283 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
915 14:44:13.751687 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
916 14:44:13.755123 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
917 14:44:13.761561 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
918 14:44:13.765219 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
919 14:44:13.768291 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
920 14:44:13.771765 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
921 14:44:13.772239 ==
922 14:44:13.774729 Dram Type= 6, Freq= 0, CH_0, rank 0
923 14:44:13.781909 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
924 14:44:13.782464 ==
925 14:44:13.782851 DQS Delay:
926 14:44:13.785002 DQS0 = 0, DQS1 = 0
927 14:44:13.785509 DQM Delay:
928 14:44:13.785887 DQM0 = 82, DQM1 = 73
929 14:44:13.788196 DQ Delay:
930 14:44:13.791980 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
931 14:44:13.795193 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
932 14:44:13.798064 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
933 14:44:13.801599 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
934 14:44:13.802224
935 14:44:13.802621
936 14:44:13.803022 ==
937 14:44:13.804950 Dram Type= 6, Freq= 0, CH_0, rank 0
938 14:44:13.808215 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
939 14:44:13.808690 ==
940 14:44:13.809064
941 14:44:13.809470
942 14:44:13.811689 TX Vref Scan disable
943 14:44:13.812257 == TX Byte 0 ==
944 14:44:13.818257 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
945 14:44:13.821760 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
946 14:44:13.822233 == TX Byte 1 ==
947 14:44:13.828110 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
948 14:44:13.831521 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
949 14:44:13.831993 ==
950 14:44:13.834969 Dram Type= 6, Freq= 0, CH_0, rank 0
951 14:44:13.838272 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
952 14:44:13.838839 ==
953 14:44:13.852361 TX Vref=22, minBit 0, minWin=27, winSum=445
954 14:44:13.855628 TX Vref=24, minBit 4, minWin=27, winSum=454
955 14:44:13.859233 TX Vref=26, minBit 4, minWin=27, winSum=455
956 14:44:13.862255 TX Vref=28, minBit 2, minWin=28, winSum=457
957 14:44:13.865449 TX Vref=30, minBit 2, minWin=28, winSum=458
958 14:44:13.872155 TX Vref=32, minBit 0, minWin=28, winSum=456
959 14:44:13.875551 [TxChooseVref] Worse bit 2, Min win 28, Win sum 458, Final Vref 30
960 14:44:13.876026
961 14:44:13.878723 Final TX Range 1 Vref 30
962 14:44:13.879438
963 14:44:13.879831 ==
964 14:44:13.882135 Dram Type= 6, Freq= 0, CH_0, rank 0
965 14:44:13.885933 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
966 14:44:13.886412 ==
967 14:44:13.886812
968 14:44:13.887324
969 14:44:13.889261 TX Vref Scan disable
970 14:44:13.892921 == TX Byte 0 ==
971 14:44:13.896381 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
972 14:44:13.900014 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
973 14:44:13.903020 == TX Byte 1 ==
974 14:44:13.906441 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
975 14:44:13.909852 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
976 14:44:13.910420
977 14:44:13.913099 [DATLAT]
978 14:44:13.913712 Freq=800, CH0 RK0
979 14:44:13.914097
980 14:44:13.916606 DATLAT Default: 0xa
981 14:44:13.917174 0, 0xFFFF, sum = 0
982 14:44:13.919625 1, 0xFFFF, sum = 0
983 14:44:13.920261 2, 0xFFFF, sum = 0
984 14:44:13.922700 3, 0xFFFF, sum = 0
985 14:44:13.923182 4, 0xFFFF, sum = 0
986 14:44:13.926280 5, 0xFFFF, sum = 0
987 14:44:13.926856 6, 0xFFFF, sum = 0
988 14:44:13.929741 7, 0xFFFF, sum = 0
989 14:44:13.930311 8, 0x0, sum = 1
990 14:44:13.933226 9, 0x0, sum = 2
991 14:44:13.933860 10, 0x0, sum = 3
992 14:44:13.936144 11, 0x0, sum = 4
993 14:44:13.936718 best_step = 9
994 14:44:13.937094
995 14:44:13.937490 ==
996 14:44:13.939444 Dram Type= 6, Freq= 0, CH_0, rank 0
997 14:44:13.942928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
998 14:44:13.943497 ==
999 14:44:13.946191 RX Vref Scan: 1
1000 14:44:13.946761
1001 14:44:13.949337 Set Vref Range= 32 -> 127
1002 14:44:13.949811
1003 14:44:13.950184 RX Vref 32 -> 127, step: 1
1004 14:44:13.950532
1005 14:44:13.953164 RX Delay -111 -> 252, step: 8
1006 14:44:13.953780
1007 14:44:13.956443 Set Vref, RX VrefLevel [Byte0]: 32
1008 14:44:13.959489 [Byte1]: 32
1009 14:44:13.963199
1010 14:44:13.963755 Set Vref, RX VrefLevel [Byte0]: 33
1011 14:44:13.966455 [Byte1]: 33
1012 14:44:13.970624
1013 14:44:13.971093 Set Vref, RX VrefLevel [Byte0]: 34
1014 14:44:13.973785 [Byte1]: 34
1015 14:44:13.978530
1016 14:44:13.979119 Set Vref, RX VrefLevel [Byte0]: 35
1017 14:44:13.981593 [Byte1]: 35
1018 14:44:13.986219
1019 14:44:13.986690 Set Vref, RX VrefLevel [Byte0]: 36
1020 14:44:13.989697 [Byte1]: 36
1021 14:44:13.993767
1022 14:44:13.994337 Set Vref, RX VrefLevel [Byte0]: 37
1023 14:44:13.996996 [Byte1]: 37
1024 14:44:14.001265
1025 14:44:14.001930 Set Vref, RX VrefLevel [Byte0]: 38
1026 14:44:14.004698 [Byte1]: 38
1027 14:44:14.009097
1028 14:44:14.009723 Set Vref, RX VrefLevel [Byte0]: 39
1029 14:44:14.012301 [Byte1]: 39
1030 14:44:14.016718
1031 14:44:14.017277 Set Vref, RX VrefLevel [Byte0]: 40
1032 14:44:14.020202 [Byte1]: 40
1033 14:44:14.024429
1034 14:44:14.024987 Set Vref, RX VrefLevel [Byte0]: 41
1035 14:44:14.027738 [Byte1]: 41
1036 14:44:14.032375
1037 14:44:14.032934 Set Vref, RX VrefLevel [Byte0]: 42
1038 14:44:14.035195 [Byte1]: 42
1039 14:44:14.039808
1040 14:44:14.040365 Set Vref, RX VrefLevel [Byte0]: 43
1041 14:44:14.042834 [Byte1]: 43
1042 14:44:14.047407
1043 14:44:14.047965 Set Vref, RX VrefLevel [Byte0]: 44
1044 14:44:14.050547 [Byte1]: 44
1045 14:44:14.054867
1046 14:44:14.055427 Set Vref, RX VrefLevel [Byte0]: 45
1047 14:44:14.058408 [Byte1]: 45
1048 14:44:14.062510
1049 14:44:14.063073 Set Vref, RX VrefLevel [Byte0]: 46
1050 14:44:14.065744 [Byte1]: 46
1051 14:44:14.070107
1052 14:44:14.070563 Set Vref, RX VrefLevel [Byte0]: 47
1053 14:44:14.073598 [Byte1]: 47
1054 14:44:14.078132
1055 14:44:14.078686 Set Vref, RX VrefLevel [Byte0]: 48
1056 14:44:14.080812 [Byte1]: 48
1057 14:44:14.085809
1058 14:44:14.086360 Set Vref, RX VrefLevel [Byte0]: 49
1059 14:44:14.088714 [Byte1]: 49
1060 14:44:14.092925
1061 14:44:14.093514 Set Vref, RX VrefLevel [Byte0]: 50
1062 14:44:14.096426 [Byte1]: 50
1063 14:44:14.100882
1064 14:44:14.101487 Set Vref, RX VrefLevel [Byte0]: 51
1065 14:44:14.103987 [Byte1]: 51
1066 14:44:14.108761
1067 14:44:14.109344 Set Vref, RX VrefLevel [Byte0]: 52
1068 14:44:14.111875 [Byte1]: 52
1069 14:44:14.116284
1070 14:44:14.116850 Set Vref, RX VrefLevel [Byte0]: 53
1071 14:44:14.119440 [Byte1]: 53
1072 14:44:14.123749
1073 14:44:14.124308 Set Vref, RX VrefLevel [Byte0]: 54
1074 14:44:14.127217 [Byte1]: 54
1075 14:44:14.131527
1076 14:44:14.132102 Set Vref, RX VrefLevel [Byte0]: 55
1077 14:44:14.134528 [Byte1]: 55
1078 14:44:14.139003
1079 14:44:14.139558 Set Vref, RX VrefLevel [Byte0]: 56
1080 14:44:14.142190 [Byte1]: 56
1081 14:44:14.146741
1082 14:44:14.147303 Set Vref, RX VrefLevel [Byte0]: 57
1083 14:44:14.149668 [Byte1]: 57
1084 14:44:14.154666
1085 14:44:14.155226 Set Vref, RX VrefLevel [Byte0]: 58
1086 14:44:14.157949 [Byte1]: 58
1087 14:44:14.162202
1088 14:44:14.162769 Set Vref, RX VrefLevel [Byte0]: 59
1089 14:44:14.165519 [Byte1]: 59
1090 14:44:14.169958
1091 14:44:14.170416 Set Vref, RX VrefLevel [Byte0]: 60
1092 14:44:14.173184 [Byte1]: 60
1093 14:44:14.177637
1094 14:44:14.178232 Set Vref, RX VrefLevel [Byte0]: 61
1095 14:44:14.180954 [Byte1]: 61
1096 14:44:14.184842
1097 14:44:14.185338 Set Vref, RX VrefLevel [Byte0]: 62
1098 14:44:14.188371 [Byte1]: 62
1099 14:44:14.192475
1100 14:44:14.193031 Set Vref, RX VrefLevel [Byte0]: 63
1101 14:44:14.196119 [Byte1]: 63
1102 14:44:14.200013
1103 14:44:14.203223 Set Vref, RX VrefLevel [Byte0]: 64
1104 14:44:14.203755 [Byte1]: 64
1105 14:44:14.207851
1106 14:44:14.208310 Set Vref, RX VrefLevel [Byte0]: 65
1107 14:44:14.211133 [Byte1]: 65
1108 14:44:14.215299
1109 14:44:14.215757 Set Vref, RX VrefLevel [Byte0]: 66
1110 14:44:14.218745 [Byte1]: 66
1111 14:44:14.223175
1112 14:44:14.223760 Set Vref, RX VrefLevel [Byte0]: 67
1113 14:44:14.226430 [Byte1]: 67
1114 14:44:14.230762
1115 14:44:14.231322 Set Vref, RX VrefLevel [Byte0]: 68
1116 14:44:14.234077 [Byte1]: 68
1117 14:44:14.238340
1118 14:44:14.238901 Set Vref, RX VrefLevel [Byte0]: 69
1119 14:44:14.242045 [Byte1]: 69
1120 14:44:14.246068
1121 14:44:14.246635 Set Vref, RX VrefLevel [Byte0]: 70
1122 14:44:14.249446 [Byte1]: 70
1123 14:44:14.254004
1124 14:44:14.254570 Set Vref, RX VrefLevel [Byte0]: 71
1125 14:44:14.257136 [Byte1]: 71
1126 14:44:14.261484
1127 14:44:14.262045 Set Vref, RX VrefLevel [Byte0]: 72
1128 14:44:14.264537 [Byte1]: 72
1129 14:44:14.268670
1130 14:44:14.269128 Set Vref, RX VrefLevel [Byte0]: 73
1131 14:44:14.272316 [Byte1]: 73
1132 14:44:14.276688
1133 14:44:14.277264 Set Vref, RX VrefLevel [Byte0]: 74
1134 14:44:14.279818 [Byte1]: 74
1135 14:44:14.283958
1136 14:44:14.284417 Set Vref, RX VrefLevel [Byte0]: 75
1137 14:44:14.287426 [Byte1]: 75
1138 14:44:14.292073
1139 14:44:14.292687 Final RX Vref Byte 0 = 49 to rank0
1140 14:44:14.294981 Final RX Vref Byte 1 = 51 to rank0
1141 14:44:14.298385 Final RX Vref Byte 0 = 49 to rank1
1142 14:44:14.301615 Final RX Vref Byte 1 = 51 to rank1==
1143 14:44:14.305067 Dram Type= 6, Freq= 0, CH_0, rank 0
1144 14:44:14.311687 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1145 14:44:14.312238 ==
1146 14:44:14.312603 DQS Delay:
1147 14:44:14.312941 DQS0 = 0, DQS1 = 0
1148 14:44:14.314923 DQM Delay:
1149 14:44:14.315386 DQM0 = 84, DQM1 = 72
1150 14:44:14.318523 DQ Delay:
1151 14:44:14.322039 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1152 14:44:14.322602 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1153 14:44:14.325264 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1154 14:44:14.328712 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1155 14:44:14.332206
1156 14:44:14.332751
1157 14:44:14.338688 [DQSOSCAuto] RK0, (LSB)MR18= 0x3535, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1158 14:44:14.341999 CH0 RK0: MR19=606, MR18=3535
1159 14:44:14.348319 CH0_RK0: MR19=0x606, MR18=0x3535, DQSOSC=396, MR23=63, INC=94, DEC=62
1160 14:44:14.348878
1161 14:44:14.351956 ----->DramcWriteLeveling(PI) begin...
1162 14:44:14.352541 ==
1163 14:44:14.355327 Dram Type= 6, Freq= 0, CH_0, rank 1
1164 14:44:14.358217 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1165 14:44:14.358683 ==
1166 14:44:14.361862 Write leveling (Byte 0): 31 => 31
1167 14:44:14.365008 Write leveling (Byte 1): 30 => 30
1168 14:44:14.368129 DramcWriteLeveling(PI) end<-----
1169 14:44:14.368592
1170 14:44:14.368972 ==
1171 14:44:14.371843 Dram Type= 6, Freq= 0, CH_0, rank 1
1172 14:44:14.375204 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1173 14:44:14.375771 ==
1174 14:44:14.378061 [Gating] SW mode calibration
1175 14:44:14.384933 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1176 14:44:14.391872 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1177 14:44:14.395004 0 6 0 | B1->B0 | 3131 3030 | 0 0 | (0 0) (0 1)
1178 14:44:14.398034 0 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1179 14:44:14.404681 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 14:44:14.408214 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 14:44:14.411251 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 14:44:14.418237 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 14:44:14.421576 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 14:44:14.424694 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 14:44:14.431303 0 7 0 | B1->B0 | 2f2f 3232 | 0 0 | (0 0) (0 0)
1186 14:44:14.434962 0 7 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1187 14:44:14.437939 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 14:44:14.445909 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 14:44:14.448101 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 14:44:14.451268 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 14:44:14.457989 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 14:44:14.461097 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 14:44:14.464516 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 14:44:14.471135 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1195 14:44:14.474345 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 14:44:14.477765 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 14:44:14.484344 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 14:44:14.487509 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 14:44:14.490810 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 14:44:14.494281 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 14:44:14.501190 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 14:44:14.504033 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 14:44:14.507416 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 14:44:14.514276 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 14:44:14.517516 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 14:44:14.520901 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 14:44:14.527709 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 14:44:14.530725 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 14:44:14.534291 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1210 14:44:14.540957 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 14:44:14.541057 Total UI for P1: 0, mck2ui 16
1212 14:44:14.547414 best dqsien dly found for B0: ( 0, 10, 0)
1213 14:44:14.547503 Total UI for P1: 0, mck2ui 16
1214 14:44:14.554175 best dqsien dly found for B1: ( 0, 10, 0)
1215 14:44:14.557687 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1216 14:44:14.560966 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1217 14:44:14.561061
1218 14:44:14.564149 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1219 14:44:14.608249 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1220 14:44:14.608402 [Gating] SW calibration Done
1221 14:44:14.608476 ==
1222 14:44:14.608737 Dram Type= 6, Freq= 0, CH_0, rank 1
1223 14:44:14.608833 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1224 14:44:14.608922 ==
1225 14:44:14.609011 RX Vref Scan: 0
1226 14:44:14.609090
1227 14:44:14.609147 RX Vref 0 -> 0, step: 1
1228 14:44:14.609232
1229 14:44:14.609370 RX Delay -130 -> 252, step: 16
1230 14:44:14.609480 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1231 14:44:14.609574 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1232 14:44:14.609660 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1233 14:44:14.609743 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1234 14:44:14.609839 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1235 14:44:14.609925 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1236 14:44:14.624432 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1237 14:44:14.624767 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1238 14:44:14.624841 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1239 14:44:14.627640 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1240 14:44:14.630908 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1241 14:44:14.634092 iDelay=222, Bit 11, Center 61 (-50 ~ 173) 224
1242 14:44:14.637567 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1243 14:44:14.640803 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1244 14:44:14.644255 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1245 14:44:14.647495 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1246 14:44:14.651027 ==
1247 14:44:14.651119 Dram Type= 6, Freq= 0, CH_0, rank 1
1248 14:44:14.657557 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1249 14:44:14.657643 ==
1250 14:44:14.657708 DQS Delay:
1251 14:44:14.660761 DQS0 = 0, DQS1 = 0
1252 14:44:14.660843 DQM Delay:
1253 14:44:14.664030 DQM0 = 81, DQM1 = 72
1254 14:44:14.664112 DQ Delay:
1255 14:44:14.667715 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1256 14:44:14.670578 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
1257 14:44:14.674010 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1258 14:44:14.677570 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1259 14:44:14.677652
1260 14:44:14.677718
1261 14:44:14.677778 ==
1262 14:44:14.680573 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 14:44:14.684102 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1264 14:44:14.684186 ==
1265 14:44:14.684251
1266 14:44:14.684310
1267 14:44:14.687750 TX Vref Scan disable
1268 14:44:14.690940 == TX Byte 0 ==
1269 14:44:14.694222 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1270 14:44:14.697061 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1271 14:44:14.700434 == TX Byte 1 ==
1272 14:44:14.704225 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1273 14:44:14.707384 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1274 14:44:14.707550 ==
1275 14:44:14.710618 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 14:44:14.714024 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1277 14:44:14.717456 ==
1278 14:44:14.728551 TX Vref=22, minBit 7, minWin=27, winSum=447
1279 14:44:14.731917 TX Vref=24, minBit 0, minWin=28, winSum=452
1280 14:44:14.735559 TX Vref=26, minBit 0, minWin=28, winSum=453
1281 14:44:14.739022 TX Vref=28, minBit 2, minWin=28, winSum=459
1282 14:44:14.742668 TX Vref=30, minBit 0, minWin=28, winSum=459
1283 14:44:14.746107 TX Vref=32, minBit 1, minWin=28, winSum=457
1284 14:44:14.753396 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 28
1285 14:44:14.753694
1286 14:44:14.756553 Final TX Range 1 Vref 28
1287 14:44:14.756809
1288 14:44:14.757009 ==
1289 14:44:14.760102 Dram Type= 6, Freq= 0, CH_0, rank 1
1290 14:44:14.763880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1291 14:44:14.764398 ==
1292 14:44:14.764691
1293 14:44:14.764934
1294 14:44:14.767353 TX Vref Scan disable
1295 14:44:14.767798 == TX Byte 0 ==
1296 14:44:14.773764 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1297 14:44:14.777494 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1298 14:44:14.778058 == TX Byte 1 ==
1299 14:44:14.783873 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1300 14:44:14.787866 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1301 14:44:14.788431
1302 14:44:14.788797 [DATLAT]
1303 14:44:14.791039 Freq=800, CH0 RK1
1304 14:44:14.791744
1305 14:44:14.792121 DATLAT Default: 0x9
1306 14:44:14.793987 0, 0xFFFF, sum = 0
1307 14:44:14.794455 1, 0xFFFF, sum = 0
1308 14:44:14.797184 2, 0xFFFF, sum = 0
1309 14:44:14.797681 3, 0xFFFF, sum = 0
1310 14:44:14.800476 4, 0xFFFF, sum = 0
1311 14:44:14.800945 5, 0xFFFF, sum = 0
1312 14:44:14.804120 6, 0xFFFF, sum = 0
1313 14:44:14.804698 7, 0xFFFF, sum = 0
1314 14:44:14.807102 8, 0x0, sum = 1
1315 14:44:14.807574 9, 0x0, sum = 2
1316 14:44:14.810537 10, 0x0, sum = 3
1317 14:44:14.811067 11, 0x0, sum = 4
1318 14:44:14.814220 best_step = 9
1319 14:44:14.814784
1320 14:44:14.815155 ==
1321 14:44:14.817041 Dram Type= 6, Freq= 0, CH_0, rank 1
1322 14:44:14.820823 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1323 14:44:14.821447 ==
1324 14:44:14.823836 RX Vref Scan: 0
1325 14:44:14.824297
1326 14:44:14.824660 RX Vref 0 -> 0, step: 1
1327 14:44:14.824999
1328 14:44:14.826922 RX Delay -111 -> 252, step: 8
1329 14:44:14.833714 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1330 14:44:14.837186 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1331 14:44:14.840409 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1332 14:44:14.843730 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1333 14:44:14.847432 iDelay=217, Bit 4, Center 92 (-23 ~ 208) 232
1334 14:44:14.853632 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1335 14:44:14.856843 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1336 14:44:14.860486 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1337 14:44:14.863580 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1338 14:44:14.867083 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1339 14:44:14.873883 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1340 14:44:14.876898 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1341 14:44:14.880396 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1342 14:44:14.883468 iDelay=217, Bit 13, Center 80 (-31 ~ 192) 224
1343 14:44:14.887196 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1344 14:44:14.893650 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1345 14:44:14.894113 ==
1346 14:44:14.897181 Dram Type= 6, Freq= 0, CH_0, rank 1
1347 14:44:14.900439 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1348 14:44:14.900859 ==
1349 14:44:14.901185 DQS Delay:
1350 14:44:14.903735 DQS0 = 0, DQS1 = 0
1351 14:44:14.904194 DQM Delay:
1352 14:44:14.906893 DQM0 = 87, DQM1 = 74
1353 14:44:14.907311 DQ Delay:
1354 14:44:14.910209 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1355 14:44:14.913638 DQ4 =92, DQ5 =76, DQ6 =92, DQ7 =96
1356 14:44:14.916795 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1357 14:44:14.920424 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1358 14:44:14.920944
1359 14:44:14.921275
1360 14:44:14.926556 [DQSOSCAuto] RK1, (LSB)MR18= 0x4747, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
1361 14:44:14.929933 CH0 RK1: MR19=606, MR18=4747
1362 14:44:14.936456 CH0_RK1: MR19=0x606, MR18=0x4747, DQSOSC=392, MR23=63, INC=96, DEC=64
1363 14:44:14.940034 [RxdqsGatingPostProcess] freq 800
1364 14:44:14.946410 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1365 14:44:14.949800 Pre-setting of DQS Precalculation
1366 14:44:14.953059 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1367 14:44:14.953284 ==
1368 14:44:14.957283 Dram Type= 6, Freq= 0, CH_1, rank 0
1369 14:44:14.960403 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1370 14:44:14.960637 ==
1371 14:44:14.966185 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1372 14:44:14.973051 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1373 14:44:14.980888 [CA 0] Center 37 (6~68) winsize 63
1374 14:44:14.984217 [CA 1] Center 37 (6~68) winsize 63
1375 14:44:14.987823 [CA 2] Center 34 (4~65) winsize 62
1376 14:44:14.991429 [CA 3] Center 34 (4~65) winsize 62
1377 14:44:14.994486 [CA 4] Center 33 (2~64) winsize 63
1378 14:44:14.998014 [CA 5] Center 33 (3~64) winsize 62
1379 14:44:14.998471
1380 14:44:15.001243 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1381 14:44:15.001735
1382 14:44:15.004678 [CATrainingPosCal] consider 1 rank data
1383 14:44:15.008257 u2DelayCellTimex100 = 270/100 ps
1384 14:44:15.011360 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1385 14:44:15.014642 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1386 14:44:15.021361 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1387 14:44:15.024834 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1388 14:44:15.028018 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
1389 14:44:15.031336 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1390 14:44:15.031901
1391 14:44:15.034702 CA PerBit enable=1, Macro0, CA PI delay=33
1392 14:44:15.035262
1393 14:44:15.038207 [CBTSetCACLKResult] CA Dly = 33
1394 14:44:15.038769 CS Dly: 4 (0~35)
1395 14:44:15.039129 ==
1396 14:44:15.041678 Dram Type= 6, Freq= 0, CH_1, rank 1
1397 14:44:15.048130 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1398 14:44:15.048702 ==
1399 14:44:15.051337 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1400 14:44:15.057928 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1401 14:44:15.067490 [CA 0] Center 36 (6~67) winsize 62
1402 14:44:15.070708 [CA 1] Center 37 (6~68) winsize 63
1403 14:44:15.074100 [CA 2] Center 34 (4~65) winsize 62
1404 14:44:15.077144 [CA 3] Center 34 (4~65) winsize 62
1405 14:44:15.080612 [CA 4] Center 33 (3~64) winsize 62
1406 14:44:15.083848 [CA 5] Center 33 (3~64) winsize 62
1407 14:44:15.084511
1408 14:44:15.086729 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1409 14:44:15.087187
1410 14:44:15.090078 [CATrainingPosCal] consider 2 rank data
1411 14:44:15.093756 u2DelayCellTimex100 = 270/100 ps
1412 14:44:15.096875 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1413 14:44:15.103748 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1414 14:44:15.106901 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1415 14:44:15.110595 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1416 14:44:15.113543 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1417 14:44:15.117234 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1418 14:44:15.117837
1419 14:44:15.120105 CA PerBit enable=1, Macro0, CA PI delay=33
1420 14:44:15.120636
1421 14:44:15.123422 [CBTSetCACLKResult] CA Dly = 33
1422 14:44:15.123882 CS Dly: 4 (0~36)
1423 14:44:15.124243
1424 14:44:15.130143 ----->DramcWriteLeveling(PI) begin...
1425 14:44:15.130713 ==
1426 14:44:15.133498 Dram Type= 6, Freq= 0, CH_1, rank 0
1427 14:44:15.136849 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1428 14:44:15.137517 ==
1429 14:44:15.140027 Write leveling (Byte 0): 24 => 24
1430 14:44:15.143396 Write leveling (Byte 1): 23 => 23
1431 14:44:15.146834 DramcWriteLeveling(PI) end<-----
1432 14:44:15.147396
1433 14:44:15.147759 ==
1434 14:44:15.150209 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 14:44:15.153641 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1436 14:44:15.154206 ==
1437 14:44:15.156921 [Gating] SW mode calibration
1438 14:44:15.163605 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1439 14:44:15.170875 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1440 14:44:15.173310 0 6 0 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
1441 14:44:15.176881 0 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1442 14:44:15.183635 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 14:44:15.186530 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 14:44:15.190077 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 14:44:15.193335 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 14:44:15.200127 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 14:44:15.203303 0 6 28 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
1448 14:44:15.206587 0 7 0 | B1->B0 | 2f2e 4040 | 1 0 | (0 0) (0 0)
1449 14:44:15.213354 0 7 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1450 14:44:15.216478 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1451 14:44:15.219780 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1452 14:44:15.226498 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1453 14:44:15.229891 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1454 14:44:15.233544 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1455 14:44:15.240104 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1456 14:44:15.243389 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1457 14:44:15.246712 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1458 14:44:15.253571 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1459 14:44:15.256469 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 14:44:15.259820 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 14:44:15.266891 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 14:44:15.270102 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 14:44:15.273560 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1464 14:44:15.280306 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1465 14:44:15.283591 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1466 14:44:15.286536 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1467 14:44:15.289765 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1468 14:44:15.296909 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1469 14:44:15.299941 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1470 14:44:15.303072 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1471 14:44:15.309840 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1472 14:44:15.313114 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1473 14:44:15.316731 Total UI for P1: 0, mck2ui 16
1474 14:44:15.319681 best dqsien dly found for B1: ( 0, 9, 30)
1475 14:44:15.323288 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1476 14:44:15.326516 Total UI for P1: 0, mck2ui 16
1477 14:44:15.330089 best dqsien dly found for B0: ( 0, 9, 28)
1478 14:44:15.333190 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1479 14:44:15.336432 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1480 14:44:15.336914
1481 14:44:15.343221 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1482 14:44:15.346756 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1483 14:44:15.349851 [Gating] SW calibration Done
1484 14:44:15.350400 ==
1485 14:44:15.353349 Dram Type= 6, Freq= 0, CH_1, rank 0
1486 14:44:15.356317 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1487 14:44:15.356788 ==
1488 14:44:15.357155 RX Vref Scan: 0
1489 14:44:15.357558
1490 14:44:15.359927 RX Vref 0 -> 0, step: 1
1491 14:44:15.360483
1492 14:44:15.363207 RX Delay -130 -> 252, step: 16
1493 14:44:15.366620 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1494 14:44:15.369824 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1495 14:44:15.376427 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1496 14:44:15.379835 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1497 14:44:15.383088 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1498 14:44:15.386243 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1499 14:44:15.389438 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1500 14:44:15.396486 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1501 14:44:15.399957 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1502 14:44:15.403373 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1503 14:44:15.407259 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1504 14:44:15.411109 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1505 14:44:15.414145 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1506 14:44:15.417474 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1507 14:44:15.424900 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1508 14:44:15.428705 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1509 14:44:15.429187 ==
1510 14:44:15.432439 Dram Type= 6, Freq= 0, CH_1, rank 0
1511 14:44:15.436042 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1512 14:44:15.436534 ==
1513 14:44:15.437041 DQS Delay:
1514 14:44:15.439363 DQS0 = 0, DQS1 = 0
1515 14:44:15.439833 DQM Delay:
1516 14:44:15.440197 DQM0 = 81, DQM1 = 74
1517 14:44:15.443073 DQ Delay:
1518 14:44:15.446230 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1519 14:44:15.449670 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1520 14:44:15.452752 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1521 14:44:15.456028 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =77
1522 14:44:15.456492
1523 14:44:15.456854
1524 14:44:15.457191 ==
1525 14:44:15.459171 Dram Type= 6, Freq= 0, CH_1, rank 0
1526 14:44:15.462805 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1527 14:44:15.463378 ==
1528 14:44:15.463743
1529 14:44:15.464080
1530 14:44:15.465974 TX Vref Scan disable
1531 14:44:15.466436 == TX Byte 0 ==
1532 14:44:15.473005 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1533 14:44:15.476516 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1534 14:44:15.477078 == TX Byte 1 ==
1535 14:44:15.482552 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1536 14:44:15.485985 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1537 14:44:15.486472 ==
1538 14:44:15.489185 Dram Type= 6, Freq= 0, CH_1, rank 0
1539 14:44:15.492613 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1540 14:44:15.493127 ==
1541 14:44:15.506558 TX Vref=22, minBit 0, minWin=28, winSum=450
1542 14:44:15.509896 TX Vref=24, minBit 9, minWin=27, winSum=449
1543 14:44:15.513372 TX Vref=26, minBit 0, minWin=28, winSum=453
1544 14:44:15.516840 TX Vref=28, minBit 0, minWin=28, winSum=458
1545 14:44:15.519880 TX Vref=30, minBit 0, minWin=28, winSum=458
1546 14:44:15.523425 TX Vref=32, minBit 0, minWin=28, winSum=458
1547 14:44:15.529841 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
1548 14:44:15.530307
1549 14:44:15.533078 Final TX Range 1 Vref 28
1550 14:44:15.533576
1551 14:44:15.533939 ==
1552 14:44:15.536794 Dram Type= 6, Freq= 0, CH_1, rank 0
1553 14:44:15.539735 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1554 14:44:15.540200 ==
1555 14:44:15.543173
1556 14:44:15.543731
1557 14:44:15.544100 TX Vref Scan disable
1558 14:44:15.546571 == TX Byte 0 ==
1559 14:44:15.549641 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1560 14:44:15.556097 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1561 14:44:15.556653 == TX Byte 1 ==
1562 14:44:15.559657 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1563 14:44:15.566311 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1564 14:44:15.566874
1565 14:44:15.567244 [DATLAT]
1566 14:44:15.567586 Freq=800, CH1 RK0
1567 14:44:15.567916
1568 14:44:15.569568 DATLAT Default: 0xa
1569 14:44:15.570031 0, 0xFFFF, sum = 0
1570 14:44:15.573056 1, 0xFFFF, sum = 0
1571 14:44:15.573664 2, 0xFFFF, sum = 0
1572 14:44:15.576700 3, 0xFFFF, sum = 0
1573 14:44:15.577266 4, 0xFFFF, sum = 0
1574 14:44:15.579791 5, 0xFFFF, sum = 0
1575 14:44:15.582684 6, 0xFFFF, sum = 0
1576 14:44:15.583186 7, 0xFFFF, sum = 0
1577 14:44:15.586095 8, 0x0, sum = 1
1578 14:44:15.586571 9, 0x0, sum = 2
1579 14:44:15.586939 10, 0x0, sum = 3
1580 14:44:15.589387 11, 0x0, sum = 4
1581 14:44:15.589814 best_step = 9
1582 14:44:15.590157
1583 14:44:15.590477 ==
1584 14:44:15.592825 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 14:44:15.599785 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1586 14:44:15.600354 ==
1587 14:44:15.600724 RX Vref Scan: 1
1588 14:44:15.601135
1589 14:44:15.603075 Set Vref Range= 32 -> 127
1590 14:44:15.603640
1591 14:44:15.606166 RX Vref 32 -> 127, step: 1
1592 14:44:15.606629
1593 14:44:15.609549 RX Delay -95 -> 252, step: 8
1594 14:44:15.610119
1595 14:44:15.612852 Set Vref, RX VrefLevel [Byte0]: 32
1596 14:44:15.615951 [Byte1]: 32
1597 14:44:15.616413
1598 14:44:15.619868 Set Vref, RX VrefLevel [Byte0]: 33
1599 14:44:15.622983 [Byte1]: 33
1600 14:44:15.623552
1601 14:44:15.626185 Set Vref, RX VrefLevel [Byte0]: 34
1602 14:44:15.629519 [Byte1]: 34
1603 14:44:15.629983
1604 14:44:15.633056 Set Vref, RX VrefLevel [Byte0]: 35
1605 14:44:15.636026 [Byte1]: 35
1606 14:44:15.640380
1607 14:44:15.640941 Set Vref, RX VrefLevel [Byte0]: 36
1608 14:44:15.643679 [Byte1]: 36
1609 14:44:15.647820
1610 14:44:15.648388 Set Vref, RX VrefLevel [Byte0]: 37
1611 14:44:15.651186 [Byte1]: 37
1612 14:44:15.655061
1613 14:44:15.655521 Set Vref, RX VrefLevel [Byte0]: 38
1614 14:44:15.658855 [Byte1]: 38
1615 14:44:15.662766
1616 14:44:15.663305 Set Vref, RX VrefLevel [Byte0]: 39
1617 14:44:15.666223 [Byte1]: 39
1618 14:44:15.670479
1619 14:44:15.671046 Set Vref, RX VrefLevel [Byte0]: 40
1620 14:44:15.673756 [Byte1]: 40
1621 14:44:15.678333
1622 14:44:15.678897 Set Vref, RX VrefLevel [Byte0]: 41
1623 14:44:15.681270 [Byte1]: 41
1624 14:44:15.685597
1625 14:44:15.686056 Set Vref, RX VrefLevel [Byte0]: 42
1626 14:44:15.688668 [Byte1]: 42
1627 14:44:15.693403
1628 14:44:15.693956 Set Vref, RX VrefLevel [Byte0]: 43
1629 14:44:15.696627 [Byte1]: 43
1630 14:44:15.700953
1631 14:44:15.701586 Set Vref, RX VrefLevel [Byte0]: 44
1632 14:44:15.704240 [Byte1]: 44
1633 14:44:15.708366
1634 14:44:15.708824 Set Vref, RX VrefLevel [Byte0]: 45
1635 14:44:15.711986 [Byte1]: 45
1636 14:44:15.715862
1637 14:44:15.716319 Set Vref, RX VrefLevel [Byte0]: 46
1638 14:44:15.719799 [Byte1]: 46
1639 14:44:15.723949
1640 14:44:15.724504 Set Vref, RX VrefLevel [Byte0]: 47
1641 14:44:15.727029 [Byte1]: 47
1642 14:44:15.731042
1643 14:44:15.731501 Set Vref, RX VrefLevel [Byte0]: 48
1644 14:44:15.734631 [Byte1]: 48
1645 14:44:15.739315
1646 14:44:15.739870 Set Vref, RX VrefLevel [Byte0]: 49
1647 14:44:15.741954 [Byte1]: 49
1648 14:44:15.746449
1649 14:44:15.746903 Set Vref, RX VrefLevel [Byte0]: 50
1650 14:44:15.749759 [Byte1]: 50
1651 14:44:15.754228
1652 14:44:15.754796 Set Vref, RX VrefLevel [Byte0]: 51
1653 14:44:15.757422 [Byte1]: 51
1654 14:44:15.761662
1655 14:44:15.762335 Set Vref, RX VrefLevel [Byte0]: 52
1656 14:44:15.764928 [Byte1]: 52
1657 14:44:15.769410
1658 14:44:15.769954 Set Vref, RX VrefLevel [Byte0]: 53
1659 14:44:15.772520 [Byte1]: 53
1660 14:44:15.777008
1661 14:44:15.777628 Set Vref, RX VrefLevel [Byte0]: 54
1662 14:44:15.780189 [Byte1]: 54
1663 14:44:15.784155
1664 14:44:15.784610 Set Vref, RX VrefLevel [Byte0]: 55
1665 14:44:15.787650 [Byte1]: 55
1666 14:44:15.792422
1667 14:44:15.792984 Set Vref, RX VrefLevel [Byte0]: 56
1668 14:44:15.795429 [Byte1]: 56
1669 14:44:15.799916
1670 14:44:15.800478 Set Vref, RX VrefLevel [Byte0]: 57
1671 14:44:15.802908 [Byte1]: 57
1672 14:44:15.807160
1673 14:44:15.807620 Set Vref, RX VrefLevel [Byte0]: 58
1674 14:44:15.810730 [Byte1]: 58
1675 14:44:15.815449
1676 14:44:15.816011 Set Vref, RX VrefLevel [Byte0]: 59
1677 14:44:15.818159 [Byte1]: 59
1678 14:44:15.822457
1679 14:44:15.823019 Set Vref, RX VrefLevel [Byte0]: 60
1680 14:44:15.825483 [Byte1]: 60
1681 14:44:15.830111
1682 14:44:15.830673 Set Vref, RX VrefLevel [Byte0]: 61
1683 14:44:15.833116 [Byte1]: 61
1684 14:44:15.837561
1685 14:44:15.838139 Set Vref, RX VrefLevel [Byte0]: 62
1686 14:44:15.840762 [Byte1]: 62
1687 14:44:15.845145
1688 14:44:15.845756 Set Vref, RX VrefLevel [Byte0]: 63
1689 14:44:15.848463 [Byte1]: 63
1690 14:44:15.852916
1691 14:44:15.853529 Set Vref, RX VrefLevel [Byte0]: 64
1692 14:44:15.855966 [Byte1]: 64
1693 14:44:15.860380
1694 14:44:15.860835 Set Vref, RX VrefLevel [Byte0]: 65
1695 14:44:15.863543 [Byte1]: 65
1696 14:44:15.868126
1697 14:44:15.868712 Set Vref, RX VrefLevel [Byte0]: 66
1698 14:44:15.871186 [Byte1]: 66
1699 14:44:15.875590
1700 14:44:15.876149 Set Vref, RX VrefLevel [Byte0]: 67
1701 14:44:15.878912 [Byte1]: 67
1702 14:44:15.883097
1703 14:44:15.883555 Set Vref, RX VrefLevel [Byte0]: 68
1704 14:44:15.886593 [Byte1]: 68
1705 14:44:15.890921
1706 14:44:15.891500 Set Vref, RX VrefLevel [Byte0]: 69
1707 14:44:15.893967 [Byte1]: 69
1708 14:44:15.898469
1709 14:44:15.899036 Set Vref, RX VrefLevel [Byte0]: 70
1710 14:44:15.901471 [Byte1]: 70
1711 14:44:15.905910
1712 14:44:15.906474 Set Vref, RX VrefLevel [Byte0]: 71
1713 14:44:15.909239 [Byte1]: 71
1714 14:44:15.913402
1715 14:44:15.913863 Set Vref, RX VrefLevel [Byte0]: 72
1716 14:44:15.916964 [Byte1]: 72
1717 14:44:15.921370
1718 14:44:15.921938 Set Vref, RX VrefLevel [Byte0]: 73
1719 14:44:15.924490 [Byte1]: 73
1720 14:44:15.928687
1721 14:44:15.929258 Set Vref, RX VrefLevel [Byte0]: 74
1722 14:44:15.931866 [Byte1]: 74
1723 14:44:15.936495
1724 14:44:15.937058 Set Vref, RX VrefLevel [Byte0]: 75
1725 14:44:15.939966 [Byte1]: 75
1726 14:44:15.944135
1727 14:44:15.944700 Final RX Vref Byte 0 = 60 to rank0
1728 14:44:15.947453 Final RX Vref Byte 1 = 59 to rank0
1729 14:44:15.950527 Final RX Vref Byte 0 = 60 to rank1
1730 14:44:15.954045 Final RX Vref Byte 1 = 59 to rank1==
1731 14:44:15.957312 Dram Type= 6, Freq= 0, CH_1, rank 0
1732 14:44:15.964127 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1733 14:44:15.964735 ==
1734 14:44:15.965108 DQS Delay:
1735 14:44:15.965518 DQS0 = 0, DQS1 = 0
1736 14:44:15.967181 DQM Delay:
1737 14:44:15.967644 DQM0 = 81, DQM1 = 74
1738 14:44:15.970687 DQ Delay:
1739 14:44:15.973988 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1740 14:44:15.974553 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1741 14:44:15.977520 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1742 14:44:15.980987 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1743 14:44:15.981472
1744 14:44:15.981831
1745 14:44:15.991007 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
1746 14:44:15.994961 CH1 RK0: MR19=606, MR18=4B4B
1747 14:44:15.997744 CH1_RK0: MR19=0x606, MR18=0x4B4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1748 14:44:16.001144
1749 14:44:16.004281 ----->DramcWriteLeveling(PI) begin...
1750 14:44:16.004756 ==
1751 14:44:16.007939 Dram Type= 6, Freq= 0, CH_1, rank 1
1752 14:44:16.011114 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1753 14:44:16.011581 ==
1754 14:44:16.014579 Write leveling (Byte 0): 24 => 24
1755 14:44:16.017818 Write leveling (Byte 1): 23 => 23
1756 14:44:16.021397 DramcWriteLeveling(PI) end<-----
1757 14:44:16.021955
1758 14:44:16.022319 ==
1759 14:44:16.024421 Dram Type= 6, Freq= 0, CH_1, rank 1
1760 14:44:16.027778 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1761 14:44:16.028248 ==
1762 14:44:16.031112 [Gating] SW mode calibration
1763 14:44:16.038157 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1764 14:44:16.041214 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1765 14:44:16.048162 0 6 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (1 0)
1766 14:44:16.051612 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1767 14:44:16.054531 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1768 14:44:16.061323 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1769 14:44:16.064542 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1770 14:44:16.068338 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1771 14:44:16.074720 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1772 14:44:16.078153 0 6 28 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1773 14:44:16.081321 0 7 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1774 14:44:16.087957 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1775 14:44:16.091404 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1776 14:44:16.094383 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1777 14:44:16.101342 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1778 14:44:16.104414 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1779 14:44:16.107963 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1780 14:44:16.114747 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1781 14:44:16.117793 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1782 14:44:16.121183 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1783 14:44:16.127833 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1784 14:44:16.131106 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1785 14:44:16.134773 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1786 14:44:16.137837 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1787 14:44:16.144513 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1788 14:44:16.147810 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1789 14:44:16.151282 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1790 14:44:16.157965 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1791 14:44:16.161450 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1792 14:44:16.164805 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1793 14:44:16.170913 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1794 14:44:16.174469 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1795 14:44:16.177840 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1796 14:44:16.184367 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1797 14:44:16.184831 Total UI for P1: 0, mck2ui 16
1798 14:44:16.191182 best dqsien dly found for B0: ( 0, 9, 26)
1799 14:44:16.194505 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1800 14:44:16.197773 Total UI for P1: 0, mck2ui 16
1801 14:44:16.201194 best dqsien dly found for B1: ( 0, 9, 28)
1802 14:44:16.204434 best DQS0 dly(MCK, UI, PI) = (0, 9, 26)
1803 14:44:16.207698 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
1804 14:44:16.208157
1805 14:44:16.211445 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26)
1806 14:44:16.214772 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
1807 14:44:16.217760 [Gating] SW calibration Done
1808 14:44:16.218222 ==
1809 14:44:16.221241 Dram Type= 6, Freq= 0, CH_1, rank 1
1810 14:44:16.224556 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1811 14:44:16.227756 ==
1812 14:44:16.228216 RX Vref Scan: 0
1813 14:44:16.228581
1814 14:44:16.231279 RX Vref 0 -> 0, step: 1
1815 14:44:16.231889
1816 14:44:16.234432 RX Delay -130 -> 252, step: 16
1817 14:44:16.237631 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1818 14:44:16.241443 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1819 14:44:16.244488 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1820 14:44:16.247845 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1821 14:44:16.254099 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1822 14:44:16.257588 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1823 14:44:16.260944 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1824 14:44:16.264302 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1825 14:44:16.267828 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1826 14:44:16.274394 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1827 14:44:16.277590 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1828 14:44:16.280630 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1829 14:44:16.284051 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1830 14:44:16.287288 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1831 14:44:16.293996 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1832 14:44:16.297298 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1833 14:44:16.297551 ==
1834 14:44:16.300470 Dram Type= 6, Freq= 0, CH_1, rank 1
1835 14:44:16.303546 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1836 14:44:16.303740 ==
1837 14:44:16.307171 DQS Delay:
1838 14:44:16.307332 DQS0 = 0, DQS1 = 0
1839 14:44:16.307480 DQM Delay:
1840 14:44:16.310357 DQM0 = 85, DQM1 = 73
1841 14:44:16.310516 DQ Delay:
1842 14:44:16.313417 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1843 14:44:16.316839 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1844 14:44:16.320299 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =69
1845 14:44:16.323876 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1846 14:44:16.323981
1847 14:44:16.324064
1848 14:44:16.324142 ==
1849 14:44:16.326899 Dram Type= 6, Freq= 0, CH_1, rank 1
1850 14:44:16.333597 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1851 14:44:16.333684 ==
1852 14:44:16.333752
1853 14:44:16.333814
1854 14:44:16.333874 TX Vref Scan disable
1855 14:44:16.337192 == TX Byte 0 ==
1856 14:44:16.340668 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1857 14:44:16.347262 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1858 14:44:16.347346 == TX Byte 1 ==
1859 14:44:16.350424 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1860 14:44:16.357162 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1861 14:44:16.357247 ==
1862 14:44:16.360635 Dram Type= 6, Freq= 0, CH_1, rank 1
1863 14:44:16.364212 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1864 14:44:16.364295 ==
1865 14:44:16.376395 TX Vref=22, minBit 0, minWin=28, winSum=451
1866 14:44:16.379761 TX Vref=24, minBit 0, minWin=28, winSum=452
1867 14:44:16.382952 TX Vref=26, minBit 1, minWin=28, winSum=457
1868 14:44:16.386193 TX Vref=28, minBit 9, minWin=27, winSum=455
1869 14:44:16.389520 TX Vref=30, minBit 9, minWin=27, winSum=455
1870 14:44:16.392848 TX Vref=32, minBit 0, minWin=27, winSum=452
1871 14:44:16.399425 [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 26
1872 14:44:16.399510
1873 14:44:16.402787 Final TX Range 1 Vref 26
1874 14:44:16.402870
1875 14:44:16.402935 ==
1876 14:44:16.406143 Dram Type= 6, Freq= 0, CH_1, rank 1
1877 14:44:16.409523 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1878 14:44:16.409626 ==
1879 14:44:16.412725
1880 14:44:16.412806
1881 14:44:16.412870 TX Vref Scan disable
1882 14:44:16.416092 == TX Byte 0 ==
1883 14:44:16.419521 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1884 14:44:16.422726 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1885 14:44:16.426033 == TX Byte 1 ==
1886 14:44:16.429346 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1887 14:44:16.432633 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1888 14:44:16.436100
1889 14:44:16.436182 [DATLAT]
1890 14:44:16.436247 Freq=800, CH1 RK1
1891 14:44:16.436307
1892 14:44:16.439386 DATLAT Default: 0x9
1893 14:44:16.439468 0, 0xFFFF, sum = 0
1894 14:44:16.443121 1, 0xFFFF, sum = 0
1895 14:44:16.443205 2, 0xFFFF, sum = 0
1896 14:44:16.446316 3, 0xFFFF, sum = 0
1897 14:44:16.446400 4, 0xFFFF, sum = 0
1898 14:44:16.449538 5, 0xFFFF, sum = 0
1899 14:44:16.449621 6, 0xFFFF, sum = 0
1900 14:44:16.453212 7, 0xFFFF, sum = 0
1901 14:44:16.453357 8, 0x0, sum = 1
1902 14:44:16.456357 9, 0x0, sum = 2
1903 14:44:16.456440 10, 0x0, sum = 3
1904 14:44:16.459621 11, 0x0, sum = 4
1905 14:44:16.459705 best_step = 9
1906 14:44:16.459768
1907 14:44:16.459827 ==
1908 14:44:16.462939 Dram Type= 6, Freq= 0, CH_1, rank 1
1909 14:44:16.469535 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1910 14:44:16.469620 ==
1911 14:44:16.469685 RX Vref Scan: 0
1912 14:44:16.469744
1913 14:44:16.472665 RX Vref 0 -> 0, step: 1
1914 14:44:16.472745
1915 14:44:16.476027 RX Delay -111 -> 252, step: 8
1916 14:44:16.479522 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1917 14:44:16.482641 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1918 14:44:16.489404 iDelay=209, Bit 2, Center 72 (-47 ~ 192) 240
1919 14:44:16.492781 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1920 14:44:16.496150 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1921 14:44:16.499468 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
1922 14:44:16.502689 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1923 14:44:16.509365 iDelay=209, Bit 7, Center 80 (-39 ~ 200) 240
1924 14:44:16.512665 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1925 14:44:16.515831 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1926 14:44:16.519355 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1927 14:44:16.522872 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1928 14:44:16.529319 iDelay=209, Bit 12, Center 88 (-31 ~ 208) 240
1929 14:44:16.532620 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1930 14:44:16.536049 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1931 14:44:16.539301 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1932 14:44:16.539409 ==
1933 14:44:16.542525 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 14:44:16.545911 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1935 14:44:16.549223 ==
1936 14:44:16.549310 DQS Delay:
1937 14:44:16.549373 DQS0 = 0, DQS1 = 0
1938 14:44:16.552479 DQM Delay:
1939 14:44:16.552560 DQM0 = 84, DQM1 = 74
1940 14:44:16.556166 DQ Delay:
1941 14:44:16.556247 DQ0 =88, DQ1 =80, DQ2 =72, DQ3 =84
1942 14:44:16.559340 DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =80
1943 14:44:16.562713 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =68
1944 14:44:16.566059 DQ12 =88, DQ13 =84, DQ14 =80, DQ15 =84
1945 14:44:16.569617
1946 14:44:16.569697
1947 14:44:16.575717 [DQSOSCAuto] RK1, (LSB)MR18= 0x4040, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1948 14:44:16.579276 CH1 RK1: MR19=606, MR18=4040
1949 14:44:16.585724 CH1_RK1: MR19=0x606, MR18=0x4040, DQSOSC=393, MR23=63, INC=95, DEC=63
1950 14:44:16.589083 [RxdqsGatingPostProcess] freq 800
1951 14:44:16.592794 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1952 14:44:16.595906 Pre-setting of DQS Precalculation
1953 14:44:16.599302 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1954 14:44:16.609095 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1955 14:44:16.615701 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1956 14:44:16.615788
1957 14:44:16.615852
1958 14:44:16.619082 [Calibration Summary] 1600 Mbps
1959 14:44:16.619169 CH 0, Rank 0
1960 14:44:16.622296 SW Impedance : PASS
1961 14:44:16.622383 DUTY Scan : NO K
1962 14:44:16.626073 ZQ Calibration : PASS
1963 14:44:16.629093 Jitter Meter : NO K
1964 14:44:16.629179 CBT Training : PASS
1965 14:44:16.632455 Write leveling : PASS
1966 14:44:16.635894 RX DQS gating : PASS
1967 14:44:16.635974 RX DQ/DQS(RDDQC) : PASS
1968 14:44:16.639179 TX DQ/DQS : PASS
1969 14:44:16.642530 RX DATLAT : PASS
1970 14:44:16.642612 RX DQ/DQS(Engine): PASS
1971 14:44:16.645942 TX OE : NO K
1972 14:44:16.646023 All Pass.
1973 14:44:16.646086
1974 14:44:16.649106 CH 0, Rank 1
1975 14:44:16.649185 SW Impedance : PASS
1976 14:44:16.652554 DUTY Scan : NO K
1977 14:44:16.655960 ZQ Calibration : PASS
1978 14:44:16.656040 Jitter Meter : NO K
1979 14:44:16.659309 CBT Training : PASS
1980 14:44:16.659389 Write leveling : PASS
1981 14:44:16.662400 RX DQS gating : PASS
1982 14:44:16.665798 RX DQ/DQS(RDDQC) : PASS
1983 14:44:16.665879 TX DQ/DQS : PASS
1984 14:44:16.669228 RX DATLAT : PASS
1985 14:44:16.672562 RX DQ/DQS(Engine): PASS
1986 14:44:16.672643 TX OE : NO K
1987 14:44:16.675979 All Pass.
1988 14:44:16.676059
1989 14:44:16.676122 CH 1, Rank 0
1990 14:44:16.679142 SW Impedance : PASS
1991 14:44:16.679223 DUTY Scan : NO K
1992 14:44:16.682418 ZQ Calibration : PASS
1993 14:44:16.686099 Jitter Meter : NO K
1994 14:44:16.686180 CBT Training : PASS
1995 14:44:16.689243 Write leveling : PASS
1996 14:44:16.692351 RX DQS gating : PASS
1997 14:44:16.692434 RX DQ/DQS(RDDQC) : PASS
1998 14:44:16.695806 TX DQ/DQS : PASS
1999 14:44:16.699407 RX DATLAT : PASS
2000 14:44:16.699490 RX DQ/DQS(Engine): PASS
2001 14:44:16.702545 TX OE : NO K
2002 14:44:16.702625 All Pass.
2003 14:44:16.702688
2004 14:44:16.705921 CH 1, Rank 1
2005 14:44:16.706001 SW Impedance : PASS
2006 14:44:16.709195 DUTY Scan : NO K
2007 14:44:16.709276 ZQ Calibration : PASS
2008 14:44:16.712275 Jitter Meter : NO K
2009 14:44:16.715927 CBT Training : PASS
2010 14:44:16.716007 Write leveling : PASS
2011 14:44:16.719258 RX DQS gating : PASS
2012 14:44:16.722399 RX DQ/DQS(RDDQC) : PASS
2013 14:44:16.722479 TX DQ/DQS : PASS
2014 14:44:16.725640 RX DATLAT : PASS
2015 14:44:16.729036 RX DQ/DQS(Engine): PASS
2016 14:44:16.729116 TX OE : NO K
2017 14:44:16.732345 All Pass.
2018 14:44:16.732425
2019 14:44:16.732487 DramC Write-DBI off
2020 14:44:16.735638 PER_BANK_REFRESH: Hybrid Mode
2021 14:44:16.735719 TX_TRACKING: ON
2022 14:44:16.738922 [GetDramInforAfterCalByMRR] Vendor 6.
2023 14:44:16.745666 [GetDramInforAfterCalByMRR] Revision 606.
2024 14:44:16.749030 [GetDramInforAfterCalByMRR] Revision 2 0.
2025 14:44:16.749110 MR0 0x3939
2026 14:44:16.749173 MR8 0x1111
2027 14:44:16.752405 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2028 14:44:16.752486
2029 14:44:16.755444 MR0 0x3939
2030 14:44:16.755524 MR8 0x1111
2031 14:44:16.759008 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2032 14:44:16.759088
2033 14:44:16.769141 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2034 14:44:16.772363 [FAST_K] Save calibration result to emmc
2035 14:44:16.775534 [FAST_K] Save calibration result to emmc
2036 14:44:16.779033 dram_init: config_dvfs: 1
2037 14:44:16.782328 dramc_set_vcore_voltage set vcore to 662500
2038 14:44:16.785635 Read voltage for 1200, 2
2039 14:44:16.785715 Vio18 = 0
2040 14:44:16.785778 Vcore = 662500
2041 14:44:16.789433 Vdram = 0
2042 14:44:16.789513 Vddq = 0
2043 14:44:16.789576 Vmddr = 0
2044 14:44:16.795730 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2045 14:44:16.799081 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2046 14:44:16.802312 MEM_TYPE=3, freq_sel=15
2047 14:44:16.805661 sv_algorithm_assistance_LP4_1600
2048 14:44:16.809049 ============ PULL DRAM RESETB DOWN ============
2049 14:44:16.812222 ========== PULL DRAM RESETB DOWN end =========
2050 14:44:16.818855 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2051 14:44:16.822177 ===================================
2052 14:44:16.822257 LPDDR4 DRAM CONFIGURATION
2053 14:44:16.825500 ===================================
2054 14:44:16.828894 EX_ROW_EN[0] = 0x0
2055 14:44:16.832397 EX_ROW_EN[1] = 0x0
2056 14:44:16.832478 LP4Y_EN = 0x0
2057 14:44:16.835565 WORK_FSP = 0x0
2058 14:44:16.835646 WL = 0x4
2059 14:44:16.839028 RL = 0x4
2060 14:44:16.839108 BL = 0x2
2061 14:44:16.842210 RPST = 0x0
2062 14:44:16.842290 RD_PRE = 0x0
2063 14:44:16.845649 WR_PRE = 0x1
2064 14:44:16.845729 WR_PST = 0x0
2065 14:44:16.848828 DBI_WR = 0x0
2066 14:44:16.848907 DBI_RD = 0x0
2067 14:44:16.852544 OTF = 0x1
2068 14:44:16.855718 ===================================
2069 14:44:16.858874 ===================================
2070 14:44:16.858955 ANA top config
2071 14:44:16.862123 ===================================
2072 14:44:16.865542 DLL_ASYNC_EN = 0
2073 14:44:16.868863 ALL_SLAVE_EN = 0
2074 14:44:16.868942 NEW_RANK_MODE = 1
2075 14:44:16.872174 DLL_IDLE_MODE = 1
2076 14:44:16.875418 LP45_APHY_COMB_EN = 1
2077 14:44:16.878827 TX_ODT_DIS = 1
2078 14:44:16.882084 NEW_8X_MODE = 1
2079 14:44:16.885412 ===================================
2080 14:44:16.888722 ===================================
2081 14:44:16.888802 data_rate = 2400
2082 14:44:16.892163 CKR = 1
2083 14:44:16.895463 DQ_P2S_RATIO = 8
2084 14:44:16.898765 ===================================
2085 14:44:16.902366 CA_P2S_RATIO = 8
2086 14:44:16.905895 DQ_CA_OPEN = 0
2087 14:44:16.908869 DQ_SEMI_OPEN = 0
2088 14:44:16.908949 CA_SEMI_OPEN = 0
2089 14:44:16.912464 CA_FULL_RATE = 0
2090 14:44:16.916255 DQ_CKDIV4_EN = 0
2091 14:44:16.919027 CA_CKDIV4_EN = 0
2092 14:44:16.922194 CA_PREDIV_EN = 0
2093 14:44:16.925649 PH8_DLY = 17
2094 14:44:16.925731 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2095 14:44:16.928788 DQ_AAMCK_DIV = 4
2096 14:44:16.932101 CA_AAMCK_DIV = 4
2097 14:44:16.935412 CA_ADMCK_DIV = 4
2098 14:44:16.938805 DQ_TRACK_CA_EN = 0
2099 14:44:16.941991 CA_PICK = 1200
2100 14:44:16.945349 CA_MCKIO = 1200
2101 14:44:16.945432 MCKIO_SEMI = 0
2102 14:44:16.948644 PLL_FREQ = 2366
2103 14:44:16.952072 DQ_UI_PI_RATIO = 32
2104 14:44:16.955319 CA_UI_PI_RATIO = 0
2105 14:44:16.958721 ===================================
2106 14:44:16.961997 ===================================
2107 14:44:16.965279 memory_type:LPDDR4
2108 14:44:16.965365 GP_NUM : 10
2109 14:44:16.968494 SRAM_EN : 1
2110 14:44:16.971968 MD32_EN : 0
2111 14:44:16.972049 ===================================
2112 14:44:16.975224 [ANA_INIT] >>>>>>>>>>>>>>
2113 14:44:16.978777 <<<<<< [CONFIGURE PHASE]: ANA_TX
2114 14:44:16.981924 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2115 14:44:16.985499 ===================================
2116 14:44:16.988500 data_rate = 2400,PCW = 0X5b00
2117 14:44:16.991885 ===================================
2118 14:44:16.995225 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2119 14:44:17.001967 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2120 14:44:17.005179 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2121 14:44:17.011860 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2122 14:44:17.015274 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2123 14:44:17.018498 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2124 14:44:17.018615 [ANA_INIT] flow start
2125 14:44:17.022001 [ANA_INIT] PLL >>>>>>>>
2126 14:44:17.025147 [ANA_INIT] PLL <<<<<<<<
2127 14:44:17.025229 [ANA_INIT] MIDPI >>>>>>>>
2128 14:44:17.028582 [ANA_INIT] MIDPI <<<<<<<<
2129 14:44:17.031854 [ANA_INIT] DLL >>>>>>>>
2130 14:44:17.031935 [ANA_INIT] DLL <<<<<<<<
2131 14:44:17.035290 [ANA_INIT] flow end
2132 14:44:17.038501 ============ LP4 DIFF to SE enter ============
2133 14:44:17.045260 ============ LP4 DIFF to SE exit ============
2134 14:44:17.045347 [ANA_INIT] <<<<<<<<<<<<<
2135 14:44:17.048589 [Flow] Enable top DCM control >>>>>
2136 14:44:17.051891 [Flow] Enable top DCM control <<<<<
2137 14:44:17.055087 Enable DLL master slave shuffle
2138 14:44:17.061770 ==============================================================
2139 14:44:17.061851 Gating Mode config
2140 14:44:17.068474 ==============================================================
2141 14:44:17.071817 Config description:
2142 14:44:17.078417 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2143 14:44:17.085017 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2144 14:44:17.091628 SELPH_MODE 0: By rank 1: By Phase
2145 14:44:17.098426 ==============================================================
2146 14:44:17.098511 GAT_TRACK_EN = 1
2147 14:44:17.101553 RX_GATING_MODE = 2
2148 14:44:17.105125 RX_GATING_TRACK_MODE = 2
2149 14:44:17.108278 SELPH_MODE = 1
2150 14:44:17.111931 PICG_EARLY_EN = 1
2151 14:44:17.115102 VALID_LAT_VALUE = 1
2152 14:44:17.121555 ==============================================================
2153 14:44:17.124841 Enter into Gating configuration >>>>
2154 14:44:17.128430 Exit from Gating configuration <<<<
2155 14:44:17.131717 Enter into DVFS_PRE_config >>>>>
2156 14:44:17.141794 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2157 14:44:17.144844 Exit from DVFS_PRE_config <<<<<
2158 14:44:17.148503 Enter into PICG configuration >>>>
2159 14:44:17.151657 Exit from PICG configuration <<<<
2160 14:44:17.155026 [RX_INPUT] configuration >>>>>
2161 14:44:17.155106 [RX_INPUT] configuration <<<<<
2162 14:44:17.161483 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2163 14:44:17.168241 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2164 14:44:17.171718 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2165 14:44:17.178293 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2166 14:44:17.184696 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2167 14:44:17.191483 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2168 14:44:17.194635 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2169 14:44:17.198246 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2170 14:44:17.204677 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2171 14:44:17.208133 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2172 14:44:17.211468 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2173 14:44:17.214817 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2174 14:44:17.218232 ===================================
2175 14:44:17.221389 LPDDR4 DRAM CONFIGURATION
2176 14:44:17.224720 ===================================
2177 14:44:17.228078 EX_ROW_EN[0] = 0x0
2178 14:44:17.228160 EX_ROW_EN[1] = 0x0
2179 14:44:17.231257 LP4Y_EN = 0x0
2180 14:44:17.231338 WORK_FSP = 0x0
2181 14:44:17.234700 WL = 0x4
2182 14:44:17.234781 RL = 0x4
2183 14:44:17.238070 BL = 0x2
2184 14:44:17.238151 RPST = 0x0
2185 14:44:17.241268 RD_PRE = 0x0
2186 14:44:17.241356 WR_PRE = 0x1
2187 14:44:17.244719 WR_PST = 0x0
2188 14:44:17.248179 DBI_WR = 0x0
2189 14:44:17.248260 DBI_RD = 0x0
2190 14:44:17.251331 OTF = 0x1
2191 14:44:17.254533 ===================================
2192 14:44:17.258079 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2193 14:44:17.261263 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2194 14:44:17.264670 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2195 14:44:17.267918 ===================================
2196 14:44:17.271567 LPDDR4 DRAM CONFIGURATION
2197 14:44:17.274567 ===================================
2198 14:44:17.278046 EX_ROW_EN[0] = 0x10
2199 14:44:17.278128 EX_ROW_EN[1] = 0x0
2200 14:44:17.281120 LP4Y_EN = 0x0
2201 14:44:17.281200 WORK_FSP = 0x0
2202 14:44:17.284560 WL = 0x4
2203 14:44:17.284642 RL = 0x4
2204 14:44:17.288206 BL = 0x2
2205 14:44:17.288287 RPST = 0x0
2206 14:44:17.291530 RD_PRE = 0x0
2207 14:44:17.291611 WR_PRE = 0x1
2208 14:44:17.294709 WR_PST = 0x0
2209 14:44:17.294790 DBI_WR = 0x0
2210 14:44:17.298242 DBI_RD = 0x0
2211 14:44:17.298323 OTF = 0x1
2212 14:44:17.301548 ===================================
2213 14:44:17.308514 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2214 14:44:17.308596 ==
2215 14:44:17.311357 Dram Type= 6, Freq= 0, CH_0, rank 0
2216 14:44:17.317836 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2217 14:44:17.317918 ==
2218 14:44:17.317982 [Duty_Offset_Calibration]
2219 14:44:17.321441 B0:0 B1:2 CA:1
2220 14:44:17.321549
2221 14:44:17.324337 [DutyScan_Calibration_Flow] k_type=0
2222 14:44:17.333193
2223 14:44:17.333340 ==CLK 0==
2224 14:44:17.336844 Final CLK duty delay cell = 0
2225 14:44:17.340309 [0] MAX Duty = 5093%(X100), DQS PI = 12
2226 14:44:17.343746 [0] MIN Duty = 4938%(X100), DQS PI = 52
2227 14:44:17.346749 [0] AVG Duty = 5015%(X100)
2228 14:44:17.346829
2229 14:44:17.349984 CH0 CLK Duty spec in!! Max-Min= 155%
2230 14:44:17.353128 [DutyScan_Calibration_Flow] ====Done====
2231 14:44:17.353235
2232 14:44:17.356735 [DutyScan_Calibration_Flow] k_type=1
2233 14:44:17.372955
2234 14:44:17.373074 ==DQS 0 ==
2235 14:44:17.376125 Final DQS duty delay cell = 0
2236 14:44:17.379421 [0] MAX Duty = 5124%(X100), DQS PI = 50
2237 14:44:17.382856 [0] MIN Duty = 5000%(X100), DQS PI = 6
2238 14:44:17.382971 [0] AVG Duty = 5062%(X100)
2239 14:44:17.386162
2240 14:44:17.386242 ==DQS 1 ==
2241 14:44:17.389199 Final DQS duty delay cell = 0
2242 14:44:17.392856 [0] MAX Duty = 5062%(X100), DQS PI = 56
2243 14:44:17.395921 [0] MIN Duty = 4906%(X100), DQS PI = 16
2244 14:44:17.396024 [0] AVG Duty = 4984%(X100)
2245 14:44:17.399680
2246 14:44:17.402552 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2247 14:44:17.402635
2248 14:44:17.406071 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2249 14:44:17.409242 [DutyScan_Calibration_Flow] ====Done====
2250 14:44:17.409442
2251 14:44:17.412456 [DutyScan_Calibration_Flow] k_type=3
2252 14:44:17.430282
2253 14:44:17.430370 ==DQM 0 ==
2254 14:44:17.433248 Final DQM duty delay cell = 0
2255 14:44:17.436554 [0] MAX Duty = 5124%(X100), DQS PI = 18
2256 14:44:17.440096 [0] MIN Duty = 4969%(X100), DQS PI = 40
2257 14:44:17.443348 [0] AVG Duty = 5046%(X100)
2258 14:44:17.443428
2259 14:44:17.443490 ==DQM 1 ==
2260 14:44:17.446484 Final DQM duty delay cell = 4
2261 14:44:17.450229 [4] MAX Duty = 5187%(X100), DQS PI = 54
2262 14:44:17.453150 [4] MIN Duty = 5000%(X100), DQS PI = 18
2263 14:44:17.456570 [4] AVG Duty = 5093%(X100)
2264 14:44:17.456650
2265 14:44:17.459881 CH0 DQM 0 Duty spec in!! Max-Min= 155%
2266 14:44:17.459961
2267 14:44:17.463126 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2268 14:44:17.466669 [DutyScan_Calibration_Flow] ====Done====
2269 14:44:17.466749
2270 14:44:17.470523 [DutyScan_Calibration_Flow] k_type=2
2271 14:44:17.485016
2272 14:44:17.485118 ==DQ 0 ==
2273 14:44:17.488285 Final DQ duty delay cell = -4
2274 14:44:17.491751 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2275 14:44:17.495099 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2276 14:44:17.498237 [-4] AVG Duty = 4937%(X100)
2277 14:44:17.498318
2278 14:44:17.498381 ==DQ 1 ==
2279 14:44:17.501797 Final DQ duty delay cell = -4
2280 14:44:17.504976 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2281 14:44:17.508357 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2282 14:44:17.511475 [-4] AVG Duty = 4969%(X100)
2283 14:44:17.511555
2284 14:44:17.515140 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2285 14:44:17.515257
2286 14:44:17.518220 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2287 14:44:17.521538 [DutyScan_Calibration_Flow] ====Done====
2288 14:44:17.521618 ==
2289 14:44:17.524993 Dram Type= 6, Freq= 0, CH_1, rank 0
2290 14:44:17.528143 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2291 14:44:17.528224 ==
2292 14:44:17.531597 [Duty_Offset_Calibration]
2293 14:44:17.531678 B0:0 B1:5 CA:-5
2294 14:44:17.531740
2295 14:44:17.534859 [DutyScan_Calibration_Flow] k_type=0
2296 14:44:17.545508
2297 14:44:17.545591 ==CLK 0==
2298 14:44:17.548760 Final CLK duty delay cell = 0
2299 14:44:17.552062 [0] MAX Duty = 5094%(X100), DQS PI = 24
2300 14:44:17.555673 [0] MIN Duty = 4876%(X100), DQS PI = 52
2301 14:44:17.555754 [0] AVG Duty = 4985%(X100)
2302 14:44:17.558681
2303 14:44:17.561998 CH1 CLK Duty spec in!! Max-Min= 218%
2304 14:44:17.565237 [DutyScan_Calibration_Flow] ====Done====
2305 14:44:17.565370
2306 14:44:17.568695 [DutyScan_Calibration_Flow] k_type=1
2307 14:44:17.583949
2308 14:44:17.584044 ==DQS 0 ==
2309 14:44:17.587347 Final DQS duty delay cell = 0
2310 14:44:17.590525 [0] MAX Duty = 5125%(X100), DQS PI = 16
2311 14:44:17.593843 [0] MIN Duty = 4875%(X100), DQS PI = 42
2312 14:44:17.597465 [0] AVG Duty = 5000%(X100)
2313 14:44:17.597550
2314 14:44:17.597634 ==DQS 1 ==
2315 14:44:17.600823 Final DQS duty delay cell = -4
2316 14:44:17.603965 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2317 14:44:17.607722 [-4] MIN Duty = 4907%(X100), DQS PI = 56
2318 14:44:17.610645 [-4] AVG Duty = 4969%(X100)
2319 14:44:17.610728
2320 14:44:17.613886 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2321 14:44:17.613972
2322 14:44:17.617181 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2323 14:44:17.620828 [DutyScan_Calibration_Flow] ====Done====
2324 14:44:17.620913
2325 14:44:17.623842 [DutyScan_Calibration_Flow] k_type=3
2326 14:44:17.639234
2327 14:44:17.639320 ==DQM 0 ==
2328 14:44:17.642538 Final DQM duty delay cell = -4
2329 14:44:17.645973 [-4] MAX Duty = 5094%(X100), DQS PI = 32
2330 14:44:17.649217 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2331 14:44:17.652443 [-4] AVG Duty = 4969%(X100)
2332 14:44:17.652527
2333 14:44:17.652611 ==DQM 1 ==
2334 14:44:17.655995 Final DQM duty delay cell = -4
2335 14:44:17.659294 [-4] MAX Duty = 5094%(X100), DQS PI = 20
2336 14:44:17.662493 [-4] MIN Duty = 4906%(X100), DQS PI = 56
2337 14:44:17.665812 [-4] AVG Duty = 5000%(X100)
2338 14:44:17.665897
2339 14:44:17.669253 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2340 14:44:17.669378
2341 14:44:17.672477 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2342 14:44:17.675892 [DutyScan_Calibration_Flow] ====Done====
2343 14:44:17.675977
2344 14:44:17.679105 [DutyScan_Calibration_Flow] k_type=2
2345 14:44:17.696602
2346 14:44:17.696712 ==DQ 0 ==
2347 14:44:17.699717 Final DQ duty delay cell = 0
2348 14:44:17.703240 [0] MAX Duty = 5062%(X100), DQS PI = 0
2349 14:44:17.706590 [0] MIN Duty = 4969%(X100), DQS PI = 42
2350 14:44:17.706676 [0] AVG Duty = 5015%(X100)
2351 14:44:17.706760
2352 14:44:17.709766 ==DQ 1 ==
2353 14:44:17.713214 Final DQ duty delay cell = 0
2354 14:44:17.716652 [0] MAX Duty = 5031%(X100), DQS PI = 8
2355 14:44:17.720027 [0] MIN Duty = 4907%(X100), DQS PI = 0
2356 14:44:17.720112 [0] AVG Duty = 4969%(X100)
2357 14:44:17.720197
2358 14:44:17.723098 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2359 14:44:17.723183
2360 14:44:17.726494 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2361 14:44:17.733192 [DutyScan_Calibration_Flow] ====Done====
2362 14:44:17.736750 nWR fixed to 30
2363 14:44:17.736832 [ModeRegInit_LP4] CH0 RK0
2364 14:44:17.739713 [ModeRegInit_LP4] CH0 RK1
2365 14:44:17.743536 [ModeRegInit_LP4] CH1 RK0
2366 14:44:17.743617 [ModeRegInit_LP4] CH1 RK1
2367 14:44:17.746236 match AC timing 6
2368 14:44:17.749618 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2369 14:44:17.753277 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2370 14:44:17.759784 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2371 14:44:17.763283 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2372 14:44:17.769810 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2373 14:44:17.769892 ==
2374 14:44:17.773073 Dram Type= 6, Freq= 0, CH_0, rank 0
2375 14:44:17.776651 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2376 14:44:17.776732 ==
2377 14:44:17.783578 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2378 14:44:17.786276 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2379 14:44:17.796080 [CA 0] Center 39 (9~70) winsize 62
2380 14:44:17.799315 [CA 1] Center 39 (8~70) winsize 63
2381 14:44:17.802656 [CA 2] Center 36 (5~67) winsize 63
2382 14:44:17.805780 [CA 3] Center 35 (4~66) winsize 63
2383 14:44:17.809284 [CA 4] Center 34 (3~65) winsize 63
2384 14:44:17.812706 [CA 5] Center 33 (3~64) winsize 62
2385 14:44:17.812787
2386 14:44:17.816225 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2387 14:44:17.816307
2388 14:44:17.819358 [CATrainingPosCal] consider 1 rank data
2389 14:44:17.822623 u2DelayCellTimex100 = 270/100 ps
2390 14:44:17.825981 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2391 14:44:17.829156 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2392 14:44:17.836193 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2393 14:44:17.839245 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2394 14:44:17.842730 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2395 14:44:17.846086 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2396 14:44:17.846167
2397 14:44:17.849192 CA PerBit enable=1, Macro0, CA PI delay=33
2398 14:44:17.849274
2399 14:44:17.852518 [CBTSetCACLKResult] CA Dly = 33
2400 14:44:17.852599 CS Dly: 7 (0~38)
2401 14:44:17.855981 ==
2402 14:44:17.856063 Dram Type= 6, Freq= 0, CH_0, rank 1
2403 14:44:17.862571 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2404 14:44:17.862654 ==
2405 14:44:17.865835 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2406 14:44:17.872547 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2407 14:44:17.881922 [CA 0] Center 39 (9~70) winsize 62
2408 14:44:17.884754 [CA 1] Center 38 (8~69) winsize 62
2409 14:44:17.888059 [CA 2] Center 35 (5~66) winsize 62
2410 14:44:17.891333 [CA 3] Center 35 (4~66) winsize 63
2411 14:44:17.894615 [CA 4] Center 33 (3~64) winsize 62
2412 14:44:17.898218 [CA 5] Center 34 (3~65) winsize 63
2413 14:44:17.898301
2414 14:44:17.901507 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2415 14:44:17.901589
2416 14:44:17.904659 [CATrainingPosCal] consider 2 rank data
2417 14:44:17.908222 u2DelayCellTimex100 = 270/100 ps
2418 14:44:17.911748 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2419 14:44:17.914870 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2420 14:44:17.921530 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2421 14:44:17.924863 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2422 14:44:17.928096 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2423 14:44:17.931362 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2424 14:44:17.931442
2425 14:44:17.934723 CA PerBit enable=1, Macro0, CA PI delay=33
2426 14:44:17.934805
2427 14:44:17.938003 [CBTSetCACLKResult] CA Dly = 33
2428 14:44:17.938084 CS Dly: 7 (0~39)
2429 14:44:17.938147
2430 14:44:17.941396 ----->DramcWriteLeveling(PI) begin...
2431 14:44:17.944880 ==
2432 14:44:17.944961 Dram Type= 6, Freq= 0, CH_0, rank 0
2433 14:44:17.951704 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2434 14:44:17.951790 ==
2435 14:44:17.954962 Write leveling (Byte 0): 27 => 27
2436 14:44:17.958208 Write leveling (Byte 1): 27 => 27
2437 14:44:17.961617 DramcWriteLeveling(PI) end<-----
2438 14:44:17.961698
2439 14:44:17.961761 ==
2440 14:44:17.964884 Dram Type= 6, Freq= 0, CH_0, rank 0
2441 14:44:17.968593 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2442 14:44:17.968674 ==
2443 14:44:17.971533 [Gating] SW mode calibration
2444 14:44:17.978503 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2445 14:44:17.981630 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2446 14:44:17.988142 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2447 14:44:17.991481 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2448 14:44:17.994970 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2449 14:44:18.001523 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2450 14:44:18.005156 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2451 14:44:18.008267 0 11 20 | B1->B0 | 2e2e 2525 | 0 0 | (0 1) (0 0)
2452 14:44:18.014975 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2453 14:44:18.018070 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2454 14:44:18.021557 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2455 14:44:18.028071 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2456 14:44:18.031552 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2457 14:44:18.034870 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2458 14:44:18.041381 0 12 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2459 14:44:18.044746 0 12 20 | B1->B0 | 3535 3e3e | 0 0 | (0 0) (0 0)
2460 14:44:18.048092 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2461 14:44:18.054671 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2462 14:44:18.057814 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2463 14:44:18.061312 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2464 14:44:18.068158 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2465 14:44:18.071281 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2466 14:44:18.074827 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2467 14:44:18.078021 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2468 14:44:18.084668 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2469 14:44:18.088078 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2470 14:44:18.091539 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2471 14:44:18.098107 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2472 14:44:18.101515 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2473 14:44:18.104614 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2474 14:44:18.111232 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2475 14:44:18.114610 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2476 14:44:18.118113 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2477 14:44:18.124685 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2478 14:44:18.128109 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2479 14:44:18.131236 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2480 14:44:18.138068 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2481 14:44:18.141569 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2482 14:44:18.144656 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2483 14:44:18.151277 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2484 14:44:18.151361 Total UI for P1: 0, mck2ui 16
2485 14:44:18.157951 best dqsien dly found for B0: ( 0, 15, 18)
2486 14:44:18.161170 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2487 14:44:18.165023 Total UI for P1: 0, mck2ui 16
2488 14:44:18.167937 best dqsien dly found for B1: ( 0, 15, 20)
2489 14:44:18.171651 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2490 14:44:18.174744 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2491 14:44:18.174828
2492 14:44:18.178153 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2493 14:44:18.181573 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2494 14:44:18.184874 [Gating] SW calibration Done
2495 14:44:18.184958 ==
2496 14:44:18.187893 Dram Type= 6, Freq= 0, CH_0, rank 0
2497 14:44:18.191354 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2498 14:44:18.191435 ==
2499 14:44:18.194492 RX Vref Scan: 0
2500 14:44:18.194573
2501 14:44:18.197766 RX Vref 0 -> 0, step: 1
2502 14:44:18.197845
2503 14:44:18.197908 RX Delay -40 -> 252, step: 8
2504 14:44:18.204590 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2505 14:44:18.207904 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2506 14:44:18.211805 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2507 14:44:18.214669 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2508 14:44:18.217919 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2509 14:44:18.224662 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2510 14:44:18.227949 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2511 14:44:18.231590 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2512 14:44:18.234531 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2513 14:44:18.238193 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2514 14:44:18.244520 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2515 14:44:18.248266 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2516 14:44:18.251405 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2517 14:44:18.254609 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2518 14:44:18.257934 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2519 14:44:18.264852 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2520 14:44:18.264933 ==
2521 14:44:18.268289 Dram Type= 6, Freq= 0, CH_0, rank 0
2522 14:44:18.271260 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2523 14:44:18.271342 ==
2524 14:44:18.271405 DQS Delay:
2525 14:44:18.274781 DQS0 = 0, DQS1 = 0
2526 14:44:18.274862 DQM Delay:
2527 14:44:18.277975 DQM0 = 115, DQM1 = 105
2528 14:44:18.278056 DQ Delay:
2529 14:44:18.281187 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2530 14:44:18.284561 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2531 14:44:18.288153 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =99
2532 14:44:18.291436 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2533 14:44:18.291516
2534 14:44:18.291578
2535 14:44:18.291636 ==
2536 14:44:18.294673 Dram Type= 6, Freq= 0, CH_0, rank 0
2537 14:44:18.301181 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2538 14:44:18.301266 ==
2539 14:44:18.301368
2540 14:44:18.301428
2541 14:44:18.301486 TX Vref Scan disable
2542 14:44:18.304774 == TX Byte 0 ==
2543 14:44:18.308319 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2544 14:44:18.314902 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2545 14:44:18.314984 == TX Byte 1 ==
2546 14:44:18.318151 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2547 14:44:18.324906 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2548 14:44:18.324989 ==
2549 14:44:18.328151 Dram Type= 6, Freq= 0, CH_0, rank 0
2550 14:44:18.331236 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2551 14:44:18.331317 ==
2552 14:44:18.342696 TX Vref=22, minBit 8, minWin=25, winSum=423
2553 14:44:18.345951 TX Vref=24, minBit 13, minWin=25, winSum=425
2554 14:44:18.349335 TX Vref=26, minBit 10, minWin=25, winSum=429
2555 14:44:18.352592 TX Vref=28, minBit 9, minWin=26, winSum=430
2556 14:44:18.355979 TX Vref=30, minBit 12, minWin=26, winSum=439
2557 14:44:18.362971 TX Vref=32, minBit 10, minWin=26, winSum=431
2558 14:44:18.366095 [TxChooseVref] Worse bit 12, Min win 26, Win sum 439, Final Vref 30
2559 14:44:18.366177
2560 14:44:18.369212 Final TX Range 1 Vref 30
2561 14:44:18.369300
2562 14:44:18.369365 ==
2563 14:44:18.372572 Dram Type= 6, Freq= 0, CH_0, rank 0
2564 14:44:18.376070 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2565 14:44:18.376152 ==
2566 14:44:18.379313
2567 14:44:18.379394
2568 14:44:18.379458 TX Vref Scan disable
2569 14:44:18.382646 == TX Byte 0 ==
2570 14:44:18.385931 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2571 14:44:18.392712 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2572 14:44:18.392795 == TX Byte 1 ==
2573 14:44:18.396317 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2574 14:44:18.402542 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2575 14:44:18.402628
2576 14:44:18.402692 [DATLAT]
2577 14:44:18.402752 Freq=1200, CH0 RK0
2578 14:44:18.402811
2579 14:44:18.405860 DATLAT Default: 0xd
2580 14:44:18.405942 0, 0xFFFF, sum = 0
2581 14:44:18.409173 1, 0xFFFF, sum = 0
2582 14:44:18.409255 2, 0xFFFF, sum = 0
2583 14:44:18.412538 3, 0xFFFF, sum = 0
2584 14:44:18.415765 4, 0xFFFF, sum = 0
2585 14:44:18.415847 5, 0xFFFF, sum = 0
2586 14:44:18.419291 6, 0xFFFF, sum = 0
2587 14:44:18.419374 7, 0xFFFF, sum = 0
2588 14:44:18.422399 8, 0xFFFF, sum = 0
2589 14:44:18.422487 9, 0xFFFF, sum = 0
2590 14:44:18.425818 10, 0xFFFF, sum = 0
2591 14:44:18.425900 11, 0x0, sum = 1
2592 14:44:18.429066 12, 0x0, sum = 2
2593 14:44:18.429148 13, 0x0, sum = 3
2594 14:44:18.432558 14, 0x0, sum = 4
2595 14:44:18.432640 best_step = 12
2596 14:44:18.432703
2597 14:44:18.432762 ==
2598 14:44:18.435934 Dram Type= 6, Freq= 0, CH_0, rank 0
2599 14:44:18.439036 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2600 14:44:18.439119 ==
2601 14:44:18.442426 RX Vref Scan: 1
2602 14:44:18.442507
2603 14:44:18.445762 Set Vref Range= 32 -> 127
2604 14:44:18.445843
2605 14:44:18.445906 RX Vref 32 -> 127, step: 1
2606 14:44:18.445966
2607 14:44:18.449224 RX Delay -21 -> 252, step: 4
2608 14:44:18.449339
2609 14:44:18.452465 Set Vref, RX VrefLevel [Byte0]: 32
2610 14:44:18.455567 [Byte1]: 32
2611 14:44:18.459159
2612 14:44:18.459240 Set Vref, RX VrefLevel [Byte0]: 33
2613 14:44:18.462555 [Byte1]: 33
2614 14:44:18.467183
2615 14:44:18.467265 Set Vref, RX VrefLevel [Byte0]: 34
2616 14:44:18.470603 [Byte1]: 34
2617 14:44:18.475146
2618 14:44:18.475228 Set Vref, RX VrefLevel [Byte0]: 35
2619 14:44:18.478409 [Byte1]: 35
2620 14:44:18.483033
2621 14:44:18.483114 Set Vref, RX VrefLevel [Byte0]: 36
2622 14:44:18.486368 [Byte1]: 36
2623 14:44:18.491002
2624 14:44:18.491083 Set Vref, RX VrefLevel [Byte0]: 37
2625 14:44:18.494561 [Byte1]: 37
2626 14:44:18.498981
2627 14:44:18.499063 Set Vref, RX VrefLevel [Byte0]: 38
2628 14:44:18.502377 [Byte1]: 38
2629 14:44:18.506848
2630 14:44:18.506929 Set Vref, RX VrefLevel [Byte0]: 39
2631 14:44:18.510091 [Byte1]: 39
2632 14:44:18.514811
2633 14:44:18.514893 Set Vref, RX VrefLevel [Byte0]: 40
2634 14:44:18.518123 [Byte1]: 40
2635 14:44:18.522829
2636 14:44:18.522910 Set Vref, RX VrefLevel [Byte0]: 41
2637 14:44:18.526170 [Byte1]: 41
2638 14:44:18.530558
2639 14:44:18.530696 Set Vref, RX VrefLevel [Byte0]: 42
2640 14:44:18.533837 [Byte1]: 42
2641 14:44:18.538598
2642 14:44:18.538682 Set Vref, RX VrefLevel [Byte0]: 43
2643 14:44:18.541959 [Byte1]: 43
2644 14:44:18.546879
2645 14:44:18.546986 Set Vref, RX VrefLevel [Byte0]: 44
2646 14:44:18.549984 [Byte1]: 44
2647 14:44:18.554471
2648 14:44:18.554555 Set Vref, RX VrefLevel [Byte0]: 45
2649 14:44:18.557593 [Byte1]: 45
2650 14:44:18.562512
2651 14:44:18.562672 Set Vref, RX VrefLevel [Byte0]: 46
2652 14:44:18.565716 [Byte1]: 46
2653 14:44:18.570385
2654 14:44:18.570519 Set Vref, RX VrefLevel [Byte0]: 47
2655 14:44:18.573487 [Byte1]: 47
2656 14:44:18.578164
2657 14:44:18.578245 Set Vref, RX VrefLevel [Byte0]: 48
2658 14:44:18.581554 [Byte1]: 48
2659 14:44:18.586154
2660 14:44:18.586234 Set Vref, RX VrefLevel [Byte0]: 49
2661 14:44:18.589391 [Byte1]: 49
2662 14:44:18.593994
2663 14:44:18.594074 Set Vref, RX VrefLevel [Byte0]: 50
2664 14:44:18.597552 [Byte1]: 50
2665 14:44:18.601924
2666 14:44:18.602005 Set Vref, RX VrefLevel [Byte0]: 51
2667 14:44:18.605256 [Byte1]: 51
2668 14:44:18.609873
2669 14:44:18.609953 Set Vref, RX VrefLevel [Byte0]: 52
2670 14:44:18.613067 [Byte1]: 52
2671 14:44:18.617775
2672 14:44:18.617855 Set Vref, RX VrefLevel [Byte0]: 53
2673 14:44:18.621071 [Byte1]: 53
2674 14:44:18.625723
2675 14:44:18.625803 Set Vref, RX VrefLevel [Byte0]: 54
2676 14:44:18.629267 [Byte1]: 54
2677 14:44:18.633645
2678 14:44:18.633724 Set Vref, RX VrefLevel [Byte0]: 55
2679 14:44:18.636846 [Byte1]: 55
2680 14:44:18.641465
2681 14:44:18.641546 Set Vref, RX VrefLevel [Byte0]: 56
2682 14:44:18.644825 [Byte1]: 56
2683 14:44:18.649401
2684 14:44:18.649480 Set Vref, RX VrefLevel [Byte0]: 57
2685 14:44:18.652810 [Byte1]: 57
2686 14:44:18.657284
2687 14:44:18.657402 Set Vref, RX VrefLevel [Byte0]: 58
2688 14:44:18.660827 [Byte1]: 58
2689 14:44:18.665408
2690 14:44:18.665488 Set Vref, RX VrefLevel [Byte0]: 59
2691 14:44:18.668626 [Byte1]: 59
2692 14:44:18.673476
2693 14:44:18.673555 Set Vref, RX VrefLevel [Byte0]: 60
2694 14:44:18.676722 [Byte1]: 60
2695 14:44:18.681066
2696 14:44:18.681145 Set Vref, RX VrefLevel [Byte0]: 61
2697 14:44:18.684517 [Byte1]: 61
2698 14:44:18.689055
2699 14:44:18.689135 Set Vref, RX VrefLevel [Byte0]: 62
2700 14:44:18.692587 [Byte1]: 62
2701 14:44:18.696924
2702 14:44:18.697005 Set Vref, RX VrefLevel [Byte0]: 63
2703 14:44:18.700386 [Byte1]: 63
2704 14:44:18.705203
2705 14:44:18.705309 Set Vref, RX VrefLevel [Byte0]: 64
2706 14:44:18.708319 [Byte1]: 64
2707 14:44:18.712792
2708 14:44:18.712872 Set Vref, RX VrefLevel [Byte0]: 65
2709 14:44:18.716147 [Byte1]: 65
2710 14:44:18.720823
2711 14:44:18.720903 Set Vref, RX VrefLevel [Byte0]: 66
2712 14:44:18.724101 [Byte1]: 66
2713 14:44:18.728632
2714 14:44:18.728712 Final RX Vref Byte 0 = 47 to rank0
2715 14:44:18.732196 Final RX Vref Byte 1 = 49 to rank0
2716 14:44:18.735367 Final RX Vref Byte 0 = 47 to rank1
2717 14:44:18.738708 Final RX Vref Byte 1 = 49 to rank1==
2718 14:44:18.742109 Dram Type= 6, Freq= 0, CH_0, rank 0
2719 14:44:18.748897 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2720 14:44:18.748978 ==
2721 14:44:18.749042 DQS Delay:
2722 14:44:18.749100 DQS0 = 0, DQS1 = 0
2723 14:44:18.752106 DQM Delay:
2724 14:44:18.752185 DQM0 = 113, DQM1 = 105
2725 14:44:18.755247 DQ Delay:
2726 14:44:18.758685 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2727 14:44:18.762350 DQ4 =118, DQ5 =104, DQ6 =124, DQ7 =120
2728 14:44:18.765308 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2729 14:44:18.768539 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2730 14:44:18.768619
2731 14:44:18.768697
2732 14:44:18.775256 [DQSOSCAuto] RK0, (LSB)MR18= 0xb0b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2733 14:44:18.778604 CH0 RK0: MR19=404, MR18=B0B
2734 14:44:18.785253 CH0_RK0: MR19=0x404, MR18=0xB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
2735 14:44:18.785380
2736 14:44:18.788625 ----->DramcWriteLeveling(PI) begin...
2737 14:44:18.788707 ==
2738 14:44:18.791851 Dram Type= 6, Freq= 0, CH_0, rank 1
2739 14:44:18.795017 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2740 14:44:18.795099 ==
2741 14:44:18.798528 Write leveling (Byte 0): 28 => 28
2742 14:44:18.801789 Write leveling (Byte 1): 25 => 25
2743 14:44:18.805490 DramcWriteLeveling(PI) end<-----
2744 14:44:18.805571
2745 14:44:18.805633 ==
2746 14:44:18.808436 Dram Type= 6, Freq= 0, CH_0, rank 1
2747 14:44:18.815043 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2748 14:44:18.815125 ==
2749 14:44:18.815188 [Gating] SW mode calibration
2750 14:44:18.825091 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2751 14:44:18.828494 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2752 14:44:18.831854 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2753 14:44:18.838459 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2754 14:44:18.841714 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2755 14:44:18.845074 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2756 14:44:18.851767 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2757 14:44:18.854914 0 11 20 | B1->B0 | 3131 2828 | 0 0 | (1 0) (1 0)
2758 14:44:18.858314 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2759 14:44:18.864887 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2760 14:44:18.868494 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2761 14:44:18.871526 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2762 14:44:18.878477 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2763 14:44:18.881641 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2764 14:44:18.884963 0 12 16 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2765 14:44:18.891618 0 12 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2766 14:44:18.895000 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2767 14:44:18.898332 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2768 14:44:18.904868 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2769 14:44:18.908292 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2770 14:44:18.911616 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2771 14:44:18.915135 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2772 14:44:18.922061 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2773 14:44:18.925045 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2774 14:44:18.928595 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2775 14:44:18.935082 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2776 14:44:18.938296 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2777 14:44:18.941692 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2778 14:44:18.948359 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2779 14:44:18.951579 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2780 14:44:18.955025 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2781 14:44:18.961763 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2782 14:44:18.965114 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2783 14:44:18.968387 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2784 14:44:18.974990 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2785 14:44:18.978203 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2786 14:44:18.981787 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2787 14:44:18.988161 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2788 14:44:18.991745 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2789 14:44:18.994919 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2790 14:44:18.998310 Total UI for P1: 0, mck2ui 16
2791 14:44:19.001522 best dqsien dly found for B0: ( 0, 15, 16)
2792 14:44:19.004969 Total UI for P1: 0, mck2ui 16
2793 14:44:19.008298 best dqsien dly found for B1: ( 0, 15, 18)
2794 14:44:19.011428 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2795 14:44:19.015287 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2796 14:44:19.015368
2797 14:44:19.018290 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2798 14:44:19.025043 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2799 14:44:19.025124 [Gating] SW calibration Done
2800 14:44:19.028183 ==
2801 14:44:19.028263 Dram Type= 6, Freq= 0, CH_0, rank 1
2802 14:44:19.035054 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2803 14:44:19.035166 ==
2804 14:44:19.035268 RX Vref Scan: 0
2805 14:44:19.035368
2806 14:44:19.038133 RX Vref 0 -> 0, step: 1
2807 14:44:19.038215
2808 14:44:19.041439 RX Delay -40 -> 252, step: 8
2809 14:44:19.044771 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2810 14:44:19.048385 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2811 14:44:19.051816 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2812 14:44:19.058411 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2813 14:44:19.061557 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2814 14:44:19.065274 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2815 14:44:19.068310 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2816 14:44:19.071665 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2817 14:44:19.075068 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2818 14:44:19.081551 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2819 14:44:19.084913 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2820 14:44:19.088169 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2821 14:44:19.091601 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2822 14:44:19.094986 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2823 14:44:19.101557 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2824 14:44:19.105124 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2825 14:44:19.105209 ==
2826 14:44:19.108264 Dram Type= 6, Freq= 0, CH_0, rank 1
2827 14:44:19.111694 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2828 14:44:19.111777 ==
2829 14:44:19.115227 DQS Delay:
2830 14:44:19.115309 DQS0 = 0, DQS1 = 0
2831 14:44:19.115374 DQM Delay:
2832 14:44:19.118345 DQM0 = 115, DQM1 = 107
2833 14:44:19.118426 DQ Delay:
2834 14:44:19.121758 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =111
2835 14:44:19.125089 DQ4 =119, DQ5 =107, DQ6 =123, DQ7 =123
2836 14:44:19.128541 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2837 14:44:19.135140 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
2838 14:44:19.135221
2839 14:44:19.135285
2840 14:44:19.135344 ==
2841 14:44:19.138571 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 14:44:19.141994 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2843 14:44:19.142074 ==
2844 14:44:19.142138
2845 14:44:19.142196
2846 14:44:19.145038 TX Vref Scan disable
2847 14:44:19.145141 == TX Byte 0 ==
2848 14:44:19.151834 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2849 14:44:19.155027 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2850 14:44:19.155121 == TX Byte 1 ==
2851 14:44:19.161555 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2852 14:44:19.165094 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2853 14:44:19.165174 ==
2854 14:44:19.168350 Dram Type= 6, Freq= 0, CH_0, rank 1
2855 14:44:19.171694 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2856 14:44:19.171775 ==
2857 14:44:19.184488 TX Vref=22, minBit 10, minWin=24, winSum=419
2858 14:44:19.187667 TX Vref=24, minBit 10, minWin=25, winSum=427
2859 14:44:19.191058 TX Vref=26, minBit 11, minWin=25, winSum=430
2860 14:44:19.194408 TX Vref=28, minBit 8, minWin=26, winSum=431
2861 14:44:19.197818 TX Vref=30, minBit 9, minWin=26, winSum=436
2862 14:44:19.204536 TX Vref=32, minBit 12, minWin=26, winSum=434
2863 14:44:19.207721 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 30
2864 14:44:19.207802
2865 14:44:19.211361 Final TX Range 1 Vref 30
2866 14:44:19.211441
2867 14:44:19.211504 ==
2868 14:44:19.214269 Dram Type= 6, Freq= 0, CH_0, rank 1
2869 14:44:19.217832 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2870 14:44:19.221173 ==
2871 14:44:19.221253
2872 14:44:19.221354
2873 14:44:19.221414 TX Vref Scan disable
2874 14:44:19.224329 == TX Byte 0 ==
2875 14:44:19.227669 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2876 14:44:19.234360 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2877 14:44:19.234441 == TX Byte 1 ==
2878 14:44:19.237811 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2879 14:44:19.244449 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2880 14:44:19.244531
2881 14:44:19.244594 [DATLAT]
2882 14:44:19.244653 Freq=1200, CH0 RK1
2883 14:44:19.244709
2884 14:44:19.247697 DATLAT Default: 0xc
2885 14:44:19.247778 0, 0xFFFF, sum = 0
2886 14:44:19.251048 1, 0xFFFF, sum = 0
2887 14:44:19.251129 2, 0xFFFF, sum = 0
2888 14:44:19.254456 3, 0xFFFF, sum = 0
2889 14:44:19.257554 4, 0xFFFF, sum = 0
2890 14:44:19.257635 5, 0xFFFF, sum = 0
2891 14:44:19.261041 6, 0xFFFF, sum = 0
2892 14:44:19.261122 7, 0xFFFF, sum = 0
2893 14:44:19.264170 8, 0xFFFF, sum = 0
2894 14:44:19.264251 9, 0xFFFF, sum = 0
2895 14:44:19.267517 10, 0xFFFF, sum = 0
2896 14:44:19.267598 11, 0x0, sum = 1
2897 14:44:19.270975 12, 0x0, sum = 2
2898 14:44:19.271057 13, 0x0, sum = 3
2899 14:44:19.274319 14, 0x0, sum = 4
2900 14:44:19.274401 best_step = 12
2901 14:44:19.274464
2902 14:44:19.274522 ==
2903 14:44:19.277623 Dram Type= 6, Freq= 0, CH_0, rank 1
2904 14:44:19.280760 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2905 14:44:19.280841 ==
2906 14:44:19.284407 RX Vref Scan: 0
2907 14:44:19.284487
2908 14:44:19.287321 RX Vref 0 -> 0, step: 1
2909 14:44:19.287420
2910 14:44:19.287500 RX Delay -21 -> 252, step: 4
2911 14:44:19.295022 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2912 14:44:19.298195 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2913 14:44:19.301423 iDelay=195, Bit 2, Center 114 (43 ~ 186) 144
2914 14:44:19.304834 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2915 14:44:19.308019 iDelay=195, Bit 4, Center 116 (43 ~ 190) 148
2916 14:44:19.314939 iDelay=195, Bit 5, Center 108 (39 ~ 178) 140
2917 14:44:19.318066 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2918 14:44:19.321614 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
2919 14:44:19.324718 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
2920 14:44:19.328043 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2921 14:44:19.334713 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
2922 14:44:19.338275 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2923 14:44:19.341512 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
2924 14:44:19.344694 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2925 14:44:19.347952 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
2926 14:44:19.354778 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2927 14:44:19.354860 ==
2928 14:44:19.358087 Dram Type= 6, Freq= 0, CH_0, rank 1
2929 14:44:19.361430 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2930 14:44:19.361512 ==
2931 14:44:19.361575 DQS Delay:
2932 14:44:19.364688 DQS0 = 0, DQS1 = 0
2933 14:44:19.364768 DQM Delay:
2934 14:44:19.368118 DQM0 = 114, DQM1 = 105
2935 14:44:19.368199 DQ Delay:
2936 14:44:19.371677 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2937 14:44:19.374682 DQ4 =116, DQ5 =108, DQ6 =124, DQ7 =122
2938 14:44:19.378592 DQ8 =94, DQ9 =90, DQ10 =108, DQ11 =96
2939 14:44:19.381528 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2940 14:44:19.381609
2941 14:44:19.381672
2942 14:44:19.391238 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2943 14:44:19.394549 CH0 RK1: MR19=404, MR18=E0E
2944 14:44:19.398024 CH0_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
2945 14:44:19.401347 [RxdqsGatingPostProcess] freq 1200
2946 14:44:19.407890 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2947 14:44:19.411216 Pre-setting of DQS Precalculation
2948 14:44:19.414591 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2949 14:44:19.414673 ==
2950 14:44:19.418157 Dram Type= 6, Freq= 0, CH_1, rank 0
2951 14:44:19.424909 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2952 14:44:19.424991 ==
2953 14:44:19.427875 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2954 14:44:19.434619 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2955 14:44:19.443136 [CA 0] Center 37 (7~68) winsize 62
2956 14:44:19.446573 [CA 1] Center 37 (7~68) winsize 62
2957 14:44:19.450077 [CA 2] Center 34 (4~65) winsize 62
2958 14:44:19.453117 [CA 3] Center 33 (3~64) winsize 62
2959 14:44:19.456441 [CA 4] Center 32 (1~63) winsize 63
2960 14:44:19.460178 [CA 5] Center 32 (1~63) winsize 63
2961 14:44:19.460258
2962 14:44:19.465495 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2963 14:44:19.465575
2964 14:44:19.466460 [CATrainingPosCal] consider 1 rank data
2965 14:44:19.469904 u2DelayCellTimex100 = 270/100 ps
2966 14:44:19.473436 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2967 14:44:19.476811 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2968 14:44:19.483683 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2969 14:44:19.486762 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2970 14:44:19.489913 CA4 delay=32 (1~63),Diff = 0 PI (0 cell)
2971 14:44:19.493342 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2972 14:44:19.493422
2973 14:44:19.496727 CA PerBit enable=1, Macro0, CA PI delay=32
2974 14:44:19.496808
2975 14:44:19.500062 [CBTSetCACLKResult] CA Dly = 32
2976 14:44:19.500142 CS Dly: 6 (0~37)
2977 14:44:19.500205 ==
2978 14:44:19.503446 Dram Type= 6, Freq= 0, CH_1, rank 1
2979 14:44:19.510017 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2980 14:44:19.510099 ==
2981 14:44:19.513402 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2982 14:44:19.520024 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2983 14:44:19.528464 [CA 0] Center 37 (7~68) winsize 62
2984 14:44:19.531756 [CA 1] Center 37 (6~68) winsize 63
2985 14:44:19.535064 [CA 2] Center 33 (3~64) winsize 62
2986 14:44:19.538327 [CA 3] Center 33 (3~64) winsize 62
2987 14:44:19.541733 [CA 4] Center 32 (2~63) winsize 62
2988 14:44:19.545045 [CA 5] Center 32 (2~63) winsize 62
2989 14:44:19.545126
2990 14:44:19.548461 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2991 14:44:19.548541
2992 14:44:19.551653 [CATrainingPosCal] consider 2 rank data
2993 14:44:19.555090 u2DelayCellTimex100 = 270/100 ps
2994 14:44:19.558507 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2995 14:44:19.561826 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2996 14:44:19.568369 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
2997 14:44:19.571762 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2998 14:44:19.575403 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2999 14:44:19.578485 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3000 14:44:19.578566
3001 14:44:19.581941 CA PerBit enable=1, Macro0, CA PI delay=32
3002 14:44:19.582022
3003 14:44:19.585112 [CBTSetCACLKResult] CA Dly = 32
3004 14:44:19.585192 CS Dly: 6 (0~38)
3005 14:44:19.585256
3006 14:44:19.588777 ----->DramcWriteLeveling(PI) begin...
3007 14:44:19.591843 ==
3008 14:44:19.595018 Dram Type= 6, Freq= 0, CH_1, rank 0
3009 14:44:19.598443 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3010 14:44:19.598528 ==
3011 14:44:19.601644 Write leveling (Byte 0): 21 => 21
3012 14:44:19.605027 Write leveling (Byte 1): 21 => 21
3013 14:44:19.608329 DramcWriteLeveling(PI) end<-----
3014 14:44:19.608411
3015 14:44:19.608474 ==
3016 14:44:19.611564 Dram Type= 6, Freq= 0, CH_1, rank 0
3017 14:44:19.615210 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3018 14:44:19.615293 ==
3019 14:44:19.618396 [Gating] SW mode calibration
3020 14:44:19.624941 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3021 14:44:19.628416 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3022 14:44:19.634978 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3023 14:44:19.638263 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3024 14:44:19.641522 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3025 14:44:19.648158 0 11 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
3026 14:44:19.651679 0 11 16 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
3027 14:44:19.654890 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3028 14:44:19.661597 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3029 14:44:19.664973 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3030 14:44:19.668628 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3031 14:44:19.675142 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3032 14:44:19.678523 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3033 14:44:19.681620 0 12 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3034 14:44:19.688365 0 12 16 | B1->B0 | 2e2e 4343 | 0 0 | (0 0) (0 0)
3035 14:44:19.691880 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3036 14:44:19.695072 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3037 14:44:19.701706 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3038 14:44:19.704895 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3039 14:44:19.708079 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3040 14:44:19.714822 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3041 14:44:19.718225 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3042 14:44:19.721415 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3043 14:44:19.728089 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3044 14:44:19.731415 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3045 14:44:19.734573 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3046 14:44:19.741128 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3047 14:44:19.744573 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3048 14:44:19.747830 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3049 14:44:19.754527 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3050 14:44:19.757987 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3051 14:44:19.761170 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3052 14:44:19.764422 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3053 14:44:19.771034 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3054 14:44:19.774300 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3055 14:44:19.777730 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3056 14:44:19.784305 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3057 14:44:19.787717 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3058 14:44:19.791141 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3059 14:44:19.797679 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3060 14:44:19.801034 Total UI for P1: 0, mck2ui 16
3061 14:44:19.804264 best dqsien dly found for B0: ( 0, 15, 14)
3062 14:44:19.807611 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3063 14:44:19.810878 Total UI for P1: 0, mck2ui 16
3064 14:44:19.813984 best dqsien dly found for B1: ( 0, 15, 18)
3065 14:44:19.817452 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3066 14:44:19.820762 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3067 14:44:19.820848
3068 14:44:19.824283 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3069 14:44:19.830930 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3070 14:44:19.831016 [Gating] SW calibration Done
3071 14:44:19.831101 ==
3072 14:44:19.834094 Dram Type= 6, Freq= 0, CH_1, rank 0
3073 14:44:19.840569 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3074 14:44:19.840655 ==
3075 14:44:19.840740 RX Vref Scan: 0
3076 14:44:19.840820
3077 14:44:19.844105 RX Vref 0 -> 0, step: 1
3078 14:44:19.844214
3079 14:44:19.847330 RX Delay -40 -> 252, step: 8
3080 14:44:19.850635 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3081 14:44:19.854201 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3082 14:44:19.857451 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3083 14:44:19.864559 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3084 14:44:19.867366 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3085 14:44:19.870866 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3086 14:44:19.873859 iDelay=208, Bit 6, Center 119 (40 ~ 199) 160
3087 14:44:19.877450 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3088 14:44:19.880640 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3089 14:44:19.887304 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3090 14:44:19.890632 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3091 14:44:19.893965 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3092 14:44:19.897392 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3093 14:44:19.900868 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3094 14:44:19.907410 iDelay=208, Bit 14, Center 111 (40 ~ 183) 144
3095 14:44:19.910544 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3096 14:44:19.910625 ==
3097 14:44:19.913957 Dram Type= 6, Freq= 0, CH_1, rank 0
3098 14:44:19.917244 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3099 14:44:19.917377 ==
3100 14:44:19.920612 DQS Delay:
3101 14:44:19.920692 DQS0 = 0, DQS1 = 0
3102 14:44:19.920755 DQM Delay:
3103 14:44:19.923945 DQM0 = 116, DQM1 = 107
3104 14:44:19.924033 DQ Delay:
3105 14:44:19.927486 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3106 14:44:19.930531 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3107 14:44:19.934016 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3108 14:44:19.940460 DQ12 =115, DQ13 =119, DQ14 =111, DQ15 =119
3109 14:44:19.940542
3110 14:44:19.940606
3111 14:44:19.940664 ==
3112 14:44:19.943913 Dram Type= 6, Freq= 0, CH_1, rank 0
3113 14:44:19.947165 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3114 14:44:19.947247 ==
3115 14:44:19.947311
3116 14:44:19.947369
3117 14:44:19.950854 TX Vref Scan disable
3118 14:44:19.950935 == TX Byte 0 ==
3119 14:44:19.957127 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3120 14:44:19.960421 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3121 14:44:19.960503 == TX Byte 1 ==
3122 14:44:19.967035 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3123 14:44:19.970424 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3124 14:44:19.970506 ==
3125 14:44:19.973841 Dram Type= 6, Freq= 0, CH_1, rank 0
3126 14:44:19.977258 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3127 14:44:19.977390 ==
3128 14:44:19.989616 TX Vref=22, minBit 3, minWin=25, winSum=413
3129 14:44:19.992893 TX Vref=24, minBit 9, minWin=25, winSum=417
3130 14:44:19.996213 TX Vref=26, minBit 9, minWin=25, winSum=427
3131 14:44:19.999316 TX Vref=28, minBit 0, minWin=26, winSum=429
3132 14:44:20.002578 TX Vref=30, minBit 9, minWin=25, winSum=428
3133 14:44:20.009284 TX Vref=32, minBit 9, minWin=26, winSum=431
3134 14:44:20.012603 [TxChooseVref] Worse bit 9, Min win 26, Win sum 431, Final Vref 32
3135 14:44:20.012684
3136 14:44:20.015761 Final TX Range 1 Vref 32
3137 14:44:20.015843
3138 14:44:20.015905 ==
3139 14:44:20.019240 Dram Type= 6, Freq= 0, CH_1, rank 0
3140 14:44:20.022551 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3141 14:44:20.025856 ==
3142 14:44:20.025936
3143 14:44:20.025999
3144 14:44:20.026057 TX Vref Scan disable
3145 14:44:20.029186 == TX Byte 0 ==
3146 14:44:20.032758 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3147 14:44:20.039034 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3148 14:44:20.039116 == TX Byte 1 ==
3149 14:44:20.042322 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3150 14:44:20.049130 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3151 14:44:20.049211
3152 14:44:20.049274 [DATLAT]
3153 14:44:20.049370 Freq=1200, CH1 RK0
3154 14:44:20.049429
3155 14:44:20.052224 DATLAT Default: 0xd
3156 14:44:20.052304 0, 0xFFFF, sum = 0
3157 14:44:20.055781 1, 0xFFFF, sum = 0
3158 14:44:20.059170 2, 0xFFFF, sum = 0
3159 14:44:20.059250 3, 0xFFFF, sum = 0
3160 14:44:20.062227 4, 0xFFFF, sum = 0
3161 14:44:20.062308 5, 0xFFFF, sum = 0
3162 14:44:20.065790 6, 0xFFFF, sum = 0
3163 14:44:20.065871 7, 0xFFFF, sum = 0
3164 14:44:20.068842 8, 0xFFFF, sum = 0
3165 14:44:20.068923 9, 0xFFFF, sum = 0
3166 14:44:20.072304 10, 0xFFFF, sum = 0
3167 14:44:20.072385 11, 0x0, sum = 1
3168 14:44:20.075495 12, 0x0, sum = 2
3169 14:44:20.075575 13, 0x0, sum = 3
3170 14:44:20.079275 14, 0x0, sum = 4
3171 14:44:20.079357 best_step = 12
3172 14:44:20.079420
3173 14:44:20.079478 ==
3174 14:44:20.082290 Dram Type= 6, Freq= 0, CH_1, rank 0
3175 14:44:20.085688 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3176 14:44:20.085768 ==
3177 14:44:20.088975 RX Vref Scan: 1
3178 14:44:20.089055
3179 14:44:20.092486 Set Vref Range= 32 -> 127
3180 14:44:20.092566
3181 14:44:20.092629 RX Vref 32 -> 127, step: 1
3182 14:44:20.092688
3183 14:44:20.095732 RX Delay -29 -> 252, step: 4
3184 14:44:20.095812
3185 14:44:20.098991 Set Vref, RX VrefLevel [Byte0]: 32
3186 14:44:20.102162 [Byte1]: 32
3187 14:44:20.105772
3188 14:44:20.105852 Set Vref, RX VrefLevel [Byte0]: 33
3189 14:44:20.109186 [Byte1]: 33
3190 14:44:20.114076
3191 14:44:20.114156 Set Vref, RX VrefLevel [Byte0]: 34
3192 14:44:20.117356 [Byte1]: 34
3193 14:44:20.121831
3194 14:44:20.121910 Set Vref, RX VrefLevel [Byte0]: 35
3195 14:44:20.125269 [Byte1]: 35
3196 14:44:20.129811
3197 14:44:20.129892 Set Vref, RX VrefLevel [Byte0]: 36
3198 14:44:20.132916 [Byte1]: 36
3199 14:44:20.137979
3200 14:44:20.138059 Set Vref, RX VrefLevel [Byte0]: 37
3201 14:44:20.141081 [Byte1]: 37
3202 14:44:20.145519
3203 14:44:20.145599 Set Vref, RX VrefLevel [Byte0]: 38
3204 14:44:20.148842 [Byte1]: 38
3205 14:44:20.153615
3206 14:44:20.153698 Set Vref, RX VrefLevel [Byte0]: 39
3207 14:44:20.156946 [Byte1]: 39
3208 14:44:20.161735
3209 14:44:20.161815 Set Vref, RX VrefLevel [Byte0]: 40
3210 14:44:20.164787 [Byte1]: 40
3211 14:44:20.169483
3212 14:44:20.169563 Set Vref, RX VrefLevel [Byte0]: 41
3213 14:44:20.173116 [Byte1]: 41
3214 14:44:20.177494
3215 14:44:20.177574 Set Vref, RX VrefLevel [Byte0]: 42
3216 14:44:20.181200 [Byte1]: 42
3217 14:44:20.185427
3218 14:44:20.185506 Set Vref, RX VrefLevel [Byte0]: 43
3219 14:44:20.188647 [Byte1]: 43
3220 14:44:20.193931
3221 14:44:20.194011 Set Vref, RX VrefLevel [Byte0]: 44
3222 14:44:20.196979 [Byte1]: 44
3223 14:44:20.201497
3224 14:44:20.201577 Set Vref, RX VrefLevel [Byte0]: 45
3225 14:44:20.204872 [Byte1]: 45
3226 14:44:20.209451
3227 14:44:20.209531 Set Vref, RX VrefLevel [Byte0]: 46
3228 14:44:20.212582 [Byte1]: 46
3229 14:44:20.217233
3230 14:44:20.217367 Set Vref, RX VrefLevel [Byte0]: 47
3231 14:44:20.220874 [Byte1]: 47
3232 14:44:20.225152
3233 14:44:20.225257 Set Vref, RX VrefLevel [Byte0]: 48
3234 14:44:20.228814 [Byte1]: 48
3235 14:44:20.233245
3236 14:44:20.233375 Set Vref, RX VrefLevel [Byte0]: 49
3237 14:44:20.236477 [Byte1]: 49
3238 14:44:20.241327
3239 14:44:20.241419 Set Vref, RX VrefLevel [Byte0]: 50
3240 14:44:20.244558 [Byte1]: 50
3241 14:44:20.249058
3242 14:44:20.249138 Set Vref, RX VrefLevel [Byte0]: 51
3243 14:44:20.252558 [Byte1]: 51
3244 14:44:20.257024
3245 14:44:20.257105 Set Vref, RX VrefLevel [Byte0]: 52
3246 14:44:20.260339 [Byte1]: 52
3247 14:44:20.264931
3248 14:44:20.265011 Set Vref, RX VrefLevel [Byte0]: 53
3249 14:44:20.268334 [Byte1]: 53
3250 14:44:20.273048
3251 14:44:20.273128 Set Vref, RX VrefLevel [Byte0]: 54
3252 14:44:20.276382 [Byte1]: 54
3253 14:44:20.280868
3254 14:44:20.280947 Set Vref, RX VrefLevel [Byte0]: 55
3255 14:44:20.284477 [Byte1]: 55
3256 14:44:20.288848
3257 14:44:20.288928 Set Vref, RX VrefLevel [Byte0]: 56
3258 14:44:20.292319 [Byte1]: 56
3259 14:44:20.296971
3260 14:44:20.297050 Set Vref, RX VrefLevel [Byte0]: 57
3261 14:44:20.300151 [Byte1]: 57
3262 14:44:20.304931
3263 14:44:20.305010 Set Vref, RX VrefLevel [Byte0]: 58
3264 14:44:20.308261 [Byte1]: 58
3265 14:44:20.312836
3266 14:44:20.312916 Set Vref, RX VrefLevel [Byte0]: 59
3267 14:44:20.316222 [Byte1]: 59
3268 14:44:20.320564
3269 14:44:20.320648 Set Vref, RX VrefLevel [Byte0]: 60
3270 14:44:20.323957 [Byte1]: 60
3271 14:44:20.329133
3272 14:44:20.329213 Set Vref, RX VrefLevel [Byte0]: 61
3273 14:44:20.332050 [Byte1]: 61
3274 14:44:20.336654
3275 14:44:20.336733 Set Vref, RX VrefLevel [Byte0]: 62
3276 14:44:20.339824 [Byte1]: 62
3277 14:44:20.344734
3278 14:44:20.344814 Set Vref, RX VrefLevel [Byte0]: 63
3279 14:44:20.347949 [Byte1]: 63
3280 14:44:20.352678
3281 14:44:20.352758 Set Vref, RX VrefLevel [Byte0]: 64
3282 14:44:20.355773 [Byte1]: 64
3283 14:44:20.360417
3284 14:44:20.360496 Set Vref, RX VrefLevel [Byte0]: 65
3285 14:44:20.363746 [Byte1]: 65
3286 14:44:20.368598
3287 14:44:20.368678 Final RX Vref Byte 0 = 53 to rank0
3288 14:44:20.371905 Final RX Vref Byte 1 = 49 to rank0
3289 14:44:20.375413 Final RX Vref Byte 0 = 53 to rank1
3290 14:44:20.378499 Final RX Vref Byte 1 = 49 to rank1==
3291 14:44:20.381933 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 14:44:20.385179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3293 14:44:20.388609 ==
3294 14:44:20.388689 DQS Delay:
3295 14:44:20.388752 DQS0 = 0, DQS1 = 0
3296 14:44:20.391972 DQM Delay:
3297 14:44:20.392052 DQM0 = 115, DQM1 = 104
3298 14:44:20.395561 DQ Delay:
3299 14:44:20.398682 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3300 14:44:20.401772 DQ4 =114, DQ5 =126, DQ6 =120, DQ7 =114
3301 14:44:20.405124 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3302 14:44:20.408334 DQ12 =112, DQ13 =116, DQ14 =112, DQ15 =114
3303 14:44:20.408414
3304 14:44:20.408477
3305 14:44:20.415404 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a1a, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3306 14:44:20.418554 CH1 RK0: MR19=404, MR18=1A1A
3307 14:44:20.425076 CH1_RK0: MR19=0x404, MR18=0x1A1A, DQSOSC=400, MR23=63, INC=40, DEC=27
3308 14:44:20.425157
3309 14:44:20.428396 ----->DramcWriteLeveling(PI) begin...
3310 14:44:20.428478 ==
3311 14:44:20.431630 Dram Type= 6, Freq= 0, CH_1, rank 1
3312 14:44:20.434971 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3313 14:44:20.438359 ==
3314 14:44:20.438439 Write leveling (Byte 0): 22 => 22
3315 14:44:20.441810 Write leveling (Byte 1): 22 => 22
3316 14:44:20.444887 DramcWriteLeveling(PI) end<-----
3317 14:44:20.444967
3318 14:44:20.445030 ==
3319 14:44:20.448296 Dram Type= 6, Freq= 0, CH_1, rank 1
3320 14:44:20.455204 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3321 14:44:20.455287 ==
3322 14:44:20.455351 [Gating] SW mode calibration
3323 14:44:20.464865 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3324 14:44:20.468319 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3325 14:44:20.472002 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3326 14:44:20.478340 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3327 14:44:20.481866 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3328 14:44:20.484830 0 11 12 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 1)
3329 14:44:20.491613 0 11 16 | B1->B0 | 3232 2323 | 0 0 | (0 0) (1 0)
3330 14:44:20.495070 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3331 14:44:20.498550 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3332 14:44:20.504871 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3333 14:44:20.508104 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3334 14:44:20.511504 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3335 14:44:20.518300 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3336 14:44:20.521443 0 12 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
3337 14:44:20.524919 0 12 16 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
3338 14:44:20.531737 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3339 14:44:20.534781 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3340 14:44:20.538203 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3341 14:44:20.545100 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3342 14:44:20.548126 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3343 14:44:20.551774 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3344 14:44:20.558311 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3345 14:44:20.561637 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3346 14:44:20.564954 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3347 14:44:20.568154 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3348 14:44:20.574904 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3349 14:44:20.578187 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3350 14:44:20.581630 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3351 14:44:20.588301 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3352 14:44:20.591823 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3353 14:44:20.594884 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3354 14:44:20.601584 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3355 14:44:20.604883 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3356 14:44:20.608273 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3357 14:44:20.615048 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3358 14:44:20.618237 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3359 14:44:20.621460 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3360 14:44:20.628213 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3361 14:44:20.631555 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3362 14:44:20.635032 Total UI for P1: 0, mck2ui 16
3363 14:44:20.638121 best dqsien dly found for B0: ( 0, 15, 12)
3364 14:44:20.641644 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3365 14:44:20.644760 Total UI for P1: 0, mck2ui 16
3366 14:44:20.648160 best dqsien dly found for B1: ( 0, 15, 16)
3367 14:44:20.651772 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3368 14:44:20.654934 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3369 14:44:20.655014
3370 14:44:20.661800 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3371 14:44:20.665257 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3372 14:44:20.665382 [Gating] SW calibration Done
3373 14:44:20.668041 ==
3374 14:44:20.668121 Dram Type= 6, Freq= 0, CH_1, rank 1
3375 14:44:20.674697 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3376 14:44:20.674777 ==
3377 14:44:20.674840 RX Vref Scan: 0
3378 14:44:20.674898
3379 14:44:20.678036 RX Vref 0 -> 0, step: 1
3380 14:44:20.678116
3381 14:44:20.681338 RX Delay -40 -> 252, step: 8
3382 14:44:20.684796 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3383 14:44:20.688168 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3384 14:44:20.691624 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3385 14:44:20.698109 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3386 14:44:20.701579 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3387 14:44:20.704832 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3388 14:44:20.708078 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3389 14:44:20.711571 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3390 14:44:20.718124 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3391 14:44:20.721555 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3392 14:44:20.724972 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3393 14:44:20.728365 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3394 14:44:20.731642 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3395 14:44:20.738145 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3396 14:44:20.741490 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3397 14:44:20.744766 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3398 14:44:20.744847 ==
3399 14:44:20.748428 Dram Type= 6, Freq= 0, CH_1, rank 1
3400 14:44:20.751380 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3401 14:44:20.751460 ==
3402 14:44:20.754812 DQS Delay:
3403 14:44:20.754892 DQS0 = 0, DQS1 = 0
3404 14:44:20.758329 DQM Delay:
3405 14:44:20.758409 DQM0 = 117, DQM1 = 107
3406 14:44:20.758471 DQ Delay:
3407 14:44:20.761651 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =119
3408 14:44:20.768251 DQ4 =119, DQ5 =123, DQ6 =123, DQ7 =115
3409 14:44:20.771358 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =103
3410 14:44:20.774697 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3411 14:44:20.774777
3412 14:44:20.774840
3413 14:44:20.774897 ==
3414 14:44:20.777980 Dram Type= 6, Freq= 0, CH_1, rank 1
3415 14:44:20.781410 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3416 14:44:20.781495 ==
3417 14:44:20.781558
3418 14:44:20.781616
3419 14:44:20.784627 TX Vref Scan disable
3420 14:44:20.788034 == TX Byte 0 ==
3421 14:44:20.791276 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3422 14:44:20.794679 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3423 14:44:20.797662 == TX Byte 1 ==
3424 14:44:20.801121 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3425 14:44:20.804722 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3426 14:44:20.804806 ==
3427 14:44:20.807719 Dram Type= 6, Freq= 0, CH_1, rank 1
3428 14:44:20.811168 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3429 14:44:20.814318 ==
3430 14:44:20.824197 TX Vref=22, minBit 7, minWin=25, winSum=421
3431 14:44:20.827433 TX Vref=24, minBit 7, minWin=25, winSum=425
3432 14:44:20.830870 TX Vref=26, minBit 0, minWin=26, winSum=428
3433 14:44:20.834438 TX Vref=28, minBit 8, minWin=26, winSum=432
3434 14:44:20.837441 TX Vref=30, minBit 9, minWin=26, winSum=431
3435 14:44:20.844454 TX Vref=32, minBit 0, minWin=26, winSum=428
3436 14:44:20.847154 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 28
3437 14:44:20.847235
3438 14:44:20.850502 Final TX Range 1 Vref 28
3439 14:44:20.850583
3440 14:44:20.850646 ==
3441 14:44:20.853929 Dram Type= 6, Freq= 0, CH_1, rank 1
3442 14:44:20.857517 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3443 14:44:20.857597 ==
3444 14:44:20.860468
3445 14:44:20.860547
3446 14:44:20.860609 TX Vref Scan disable
3447 14:44:20.863763 == TX Byte 0 ==
3448 14:44:20.867019 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3449 14:44:20.870578 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3450 14:44:20.873701 == TX Byte 1 ==
3451 14:44:20.877158 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3452 14:44:20.880501 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3453 14:44:20.883674
3454 14:44:20.883754 [DATLAT]
3455 14:44:20.883818 Freq=1200, CH1 RK1
3456 14:44:20.883877
3457 14:44:20.887149 DATLAT Default: 0xc
3458 14:44:20.887230 0, 0xFFFF, sum = 0
3459 14:44:20.890320 1, 0xFFFF, sum = 0
3460 14:44:20.890402 2, 0xFFFF, sum = 0
3461 14:44:20.893838 3, 0xFFFF, sum = 0
3462 14:44:20.893920 4, 0xFFFF, sum = 0
3463 14:44:20.896847 5, 0xFFFF, sum = 0
3464 14:44:20.900475 6, 0xFFFF, sum = 0
3465 14:44:20.900560 7, 0xFFFF, sum = 0
3466 14:44:20.903638 8, 0xFFFF, sum = 0
3467 14:44:20.903721 9, 0xFFFF, sum = 0
3468 14:44:20.907084 10, 0xFFFF, sum = 0
3469 14:44:20.907165 11, 0x0, sum = 1
3470 14:44:20.910532 12, 0x0, sum = 2
3471 14:44:20.910614 13, 0x0, sum = 3
3472 14:44:20.910679 14, 0x0, sum = 4
3473 14:44:20.913776 best_step = 12
3474 14:44:20.913856
3475 14:44:20.913919 ==
3476 14:44:20.917100 Dram Type= 6, Freq= 0, CH_1, rank 1
3477 14:44:20.920278 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3478 14:44:20.920359 ==
3479 14:44:20.923814 RX Vref Scan: 0
3480 14:44:20.923895
3481 14:44:20.926846 RX Vref 0 -> 0, step: 1
3482 14:44:20.926927
3483 14:44:20.926991 RX Delay -29 -> 252, step: 4
3484 14:44:20.934274 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3485 14:44:20.937734 iDelay=199, Bit 1, Center 112 (43 ~ 182) 140
3486 14:44:20.941227 iDelay=199, Bit 2, Center 106 (35 ~ 178) 144
3487 14:44:20.944537 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3488 14:44:20.947555 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3489 14:44:20.954196 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3490 14:44:20.957613 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3491 14:44:20.960927 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3492 14:44:20.964152 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3493 14:44:20.967492 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3494 14:44:20.974235 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3495 14:44:20.977572 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3496 14:44:20.980928 iDelay=199, Bit 12, Center 114 (43 ~ 186) 144
3497 14:44:20.984300 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3498 14:44:20.987824 iDelay=199, Bit 14, Center 116 (47 ~ 186) 140
3499 14:44:20.994323 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3500 14:44:20.994405 ==
3501 14:44:20.997435 Dram Type= 6, Freq= 0, CH_1, rank 1
3502 14:44:21.000761 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3503 14:44:21.000843 ==
3504 14:44:21.000906 DQS Delay:
3505 14:44:21.004157 DQS0 = 0, DQS1 = 0
3506 14:44:21.004239 DQM Delay:
3507 14:44:21.007514 DQM0 = 115, DQM1 = 104
3508 14:44:21.007597 DQ Delay:
3509 14:44:21.010977 DQ0 =116, DQ1 =112, DQ2 =106, DQ3 =112
3510 14:44:21.014038 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3511 14:44:21.017528 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3512 14:44:21.020707 DQ12 =114, DQ13 =112, DQ14 =116, DQ15 =110
3513 14:44:21.020788
3514 14:44:21.020852
3515 14:44:21.030964 [DQSOSCAuto] RK1, (LSB)MR18= 0x606, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
3516 14:44:21.034053 CH1 RK1: MR19=404, MR18=606
3517 14:44:21.037319 CH1_RK1: MR19=0x404, MR18=0x606, DQSOSC=407, MR23=63, INC=39, DEC=26
3518 14:44:21.040574 [RxdqsGatingPostProcess] freq 1200
3519 14:44:21.047341 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3520 14:44:21.051213 Pre-setting of DQS Precalculation
3521 14:44:21.054453 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3522 14:44:21.064106 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3523 14:44:21.070534 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3524 14:44:21.070618
3525 14:44:21.070682
3526 14:44:21.073970 [Calibration Summary] 2400 Mbps
3527 14:44:21.074053 CH 0, Rank 0
3528 14:44:21.077304 SW Impedance : PASS
3529 14:44:21.077384 DUTY Scan : NO K
3530 14:44:21.080735 ZQ Calibration : PASS
3531 14:44:21.084272 Jitter Meter : NO K
3532 14:44:21.084353 CBT Training : PASS
3533 14:44:21.087303 Write leveling : PASS
3534 14:44:21.090766 RX DQS gating : PASS
3535 14:44:21.090847 RX DQ/DQS(RDDQC) : PASS
3536 14:44:21.094064 TX DQ/DQS : PASS
3537 14:44:21.097346 RX DATLAT : PASS
3538 14:44:21.097439 RX DQ/DQS(Engine): PASS
3539 14:44:21.100555 TX OE : NO K
3540 14:44:21.100635 All Pass.
3541 14:44:21.100698
3542 14:44:21.103923 CH 0, Rank 1
3543 14:44:21.104003 SW Impedance : PASS
3544 14:44:21.107325 DUTY Scan : NO K
3545 14:44:21.107405 ZQ Calibration : PASS
3546 14:44:21.110580 Jitter Meter : NO K
3547 14:44:21.113880 CBT Training : PASS
3548 14:44:21.113960 Write leveling : PASS
3549 14:44:21.117395 RX DQS gating : PASS
3550 14:44:21.120746 RX DQ/DQS(RDDQC) : PASS
3551 14:44:21.120826 TX DQ/DQS : PASS
3552 14:44:21.123914 RX DATLAT : PASS
3553 14:44:21.127177 RX DQ/DQS(Engine): PASS
3554 14:44:21.127257 TX OE : NO K
3555 14:44:21.130695 All Pass.
3556 14:44:21.130775
3557 14:44:21.130837 CH 1, Rank 0
3558 14:44:21.134055 SW Impedance : PASS
3559 14:44:21.134135 DUTY Scan : NO K
3560 14:44:21.137458 ZQ Calibration : PASS
3561 14:44:21.140554 Jitter Meter : NO K
3562 14:44:21.140635 CBT Training : PASS
3563 14:44:21.144020 Write leveling : PASS
3564 14:44:21.147519 RX DQS gating : PASS
3565 14:44:21.147599 RX DQ/DQS(RDDQC) : PASS
3566 14:44:21.150494 TX DQ/DQS : PASS
3567 14:44:21.150575 RX DATLAT : PASS
3568 14:44:21.153962 RX DQ/DQS(Engine): PASS
3569 14:44:21.157321 TX OE : NO K
3570 14:44:21.157413 All Pass.
3571 14:44:21.157477
3572 14:44:21.157534 CH 1, Rank 1
3573 14:44:21.161093 SW Impedance : PASS
3574 14:44:21.163943 DUTY Scan : NO K
3575 14:44:21.164023 ZQ Calibration : PASS
3576 14:44:21.167027 Jitter Meter : NO K
3577 14:44:21.170624 CBT Training : PASS
3578 14:44:21.170704 Write leveling : PASS
3579 14:44:21.173871 RX DQS gating : PASS
3580 14:44:21.177239 RX DQ/DQS(RDDQC) : PASS
3581 14:44:21.177324 TX DQ/DQS : PASS
3582 14:44:21.180360 RX DATLAT : PASS
3583 14:44:21.183854 RX DQ/DQS(Engine): PASS
3584 14:44:21.183934 TX OE : NO K
3585 14:44:21.186956 All Pass.
3586 14:44:21.187035
3587 14:44:21.187098 DramC Write-DBI off
3588 14:44:21.190564 PER_BANK_REFRESH: Hybrid Mode
3589 14:44:21.190644 TX_TRACKING: ON
3590 14:44:21.200554 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3591 14:44:21.203989 [FAST_K] Save calibration result to emmc
3592 14:44:21.207644 dramc_set_vcore_voltage set vcore to 650000
3593 14:44:21.210489 Read voltage for 600, 5
3594 14:44:21.210569 Vio18 = 0
3595 14:44:21.213802 Vcore = 650000
3596 14:44:21.213899 Vdram = 0
3597 14:44:21.213963 Vddq = 0
3598 14:44:21.214021 Vmddr = 0
3599 14:44:21.220944 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3600 14:44:21.227332 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3601 14:44:21.227414 MEM_TYPE=3, freq_sel=19
3602 14:44:21.230717 sv_algorithm_assistance_LP4_1600
3603 14:44:21.233907 ============ PULL DRAM RESETB DOWN ============
3604 14:44:21.240697 ========== PULL DRAM RESETB DOWN end =========
3605 14:44:21.243831 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3606 14:44:21.247204 ===================================
3607 14:44:21.250951 LPDDR4 DRAM CONFIGURATION
3608 14:44:21.253732 ===================================
3609 14:44:21.253812 EX_ROW_EN[0] = 0x0
3610 14:44:21.257036 EX_ROW_EN[1] = 0x0
3611 14:44:21.257116 LP4Y_EN = 0x0
3612 14:44:21.260616 WORK_FSP = 0x0
3613 14:44:21.260696 WL = 0x2
3614 14:44:21.263943 RL = 0x2
3615 14:44:21.264022 BL = 0x2
3616 14:44:21.267118 RPST = 0x0
3617 14:44:21.267198 RD_PRE = 0x0
3618 14:44:21.270507 WR_PRE = 0x1
3619 14:44:21.273831 WR_PST = 0x0
3620 14:44:21.273912 DBI_WR = 0x0
3621 14:44:21.277222 DBI_RD = 0x0
3622 14:44:21.277324 OTF = 0x1
3623 14:44:21.280343 ===================================
3624 14:44:21.283799 ===================================
3625 14:44:21.283880 ANA top config
3626 14:44:21.287182 ===================================
3627 14:44:21.290824 DLL_ASYNC_EN = 0
3628 14:44:21.293553 ALL_SLAVE_EN = 1
3629 14:44:21.297040 NEW_RANK_MODE = 1
3630 14:44:21.300298 DLL_IDLE_MODE = 1
3631 14:44:21.300379 LP45_APHY_COMB_EN = 1
3632 14:44:21.303493 TX_ODT_DIS = 1
3633 14:44:21.307123 NEW_8X_MODE = 1
3634 14:44:21.310075 ===================================
3635 14:44:21.313547 ===================================
3636 14:44:21.316794 data_rate = 1200
3637 14:44:21.319983 CKR = 1
3638 14:44:21.320064 DQ_P2S_RATIO = 8
3639 14:44:21.323429 ===================================
3640 14:44:21.326776 CA_P2S_RATIO = 8
3641 14:44:21.330194 DQ_CA_OPEN = 0
3642 14:44:21.333500 DQ_SEMI_OPEN = 0
3643 14:44:21.336618 CA_SEMI_OPEN = 0
3644 14:44:21.339879 CA_FULL_RATE = 0
3645 14:44:21.339960 DQ_CKDIV4_EN = 1
3646 14:44:21.343350 CA_CKDIV4_EN = 1
3647 14:44:21.346705 CA_PREDIV_EN = 0
3648 14:44:21.349831 PH8_DLY = 0
3649 14:44:21.353294 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3650 14:44:21.356561 DQ_AAMCK_DIV = 4
3651 14:44:21.356642 CA_AAMCK_DIV = 4
3652 14:44:21.359953 CA_ADMCK_DIV = 4
3653 14:44:21.363248 DQ_TRACK_CA_EN = 0
3654 14:44:21.366498 CA_PICK = 600
3655 14:44:21.369908 CA_MCKIO = 600
3656 14:44:21.373240 MCKIO_SEMI = 0
3657 14:44:21.376497 PLL_FREQ = 2288
3658 14:44:21.379797 DQ_UI_PI_RATIO = 32
3659 14:44:21.379877 CA_UI_PI_RATIO = 0
3660 14:44:21.383052 ===================================
3661 14:44:21.386540 ===================================
3662 14:44:21.389587 memory_type:LPDDR4
3663 14:44:21.392894 GP_NUM : 10
3664 14:44:21.392975 SRAM_EN : 1
3665 14:44:21.396399 MD32_EN : 0
3666 14:44:21.399930 ===================================
3667 14:44:21.402911 [ANA_INIT] >>>>>>>>>>>>>>
3668 14:44:21.406199 <<<<<< [CONFIGURE PHASE]: ANA_TX
3669 14:44:21.409335 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3670 14:44:21.412876 ===================================
3671 14:44:21.412958 data_rate = 1200,PCW = 0X5800
3672 14:44:21.416015 ===================================
3673 14:44:21.419525 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3674 14:44:21.426096 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3675 14:44:21.432605 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3676 14:44:21.435852 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3677 14:44:21.439286 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3678 14:44:21.442664 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3679 14:44:21.445888 [ANA_INIT] flow start
3680 14:44:21.445969 [ANA_INIT] PLL >>>>>>>>
3681 14:44:21.449122 [ANA_INIT] PLL <<<<<<<<
3682 14:44:21.452625 [ANA_INIT] MIDPI >>>>>>>>
3683 14:44:21.455757 [ANA_INIT] MIDPI <<<<<<<<
3684 14:44:21.455837 [ANA_INIT] DLL >>>>>>>>
3685 14:44:21.459055 [ANA_INIT] flow end
3686 14:44:21.462679 ============ LP4 DIFF to SE enter ============
3687 14:44:21.465802 ============ LP4 DIFF to SE exit ============
3688 14:44:21.469027 [ANA_INIT] <<<<<<<<<<<<<
3689 14:44:21.472300 [Flow] Enable top DCM control >>>>>
3690 14:44:21.475889 [Flow] Enable top DCM control <<<<<
3691 14:44:21.479028 Enable DLL master slave shuffle
3692 14:44:21.486144 ==============================================================
3693 14:44:21.486226 Gating Mode config
3694 14:44:21.492447 ==============================================================
3695 14:44:21.492529 Config description:
3696 14:44:21.502585 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3697 14:44:21.509028 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3698 14:44:21.515654 SELPH_MODE 0: By rank 1: By Phase
3699 14:44:21.519129 ==============================================================
3700 14:44:21.522392 GAT_TRACK_EN = 1
3701 14:44:21.525569 RX_GATING_MODE = 2
3702 14:44:21.528930 RX_GATING_TRACK_MODE = 2
3703 14:44:21.532287 SELPH_MODE = 1
3704 14:44:21.535484 PICG_EARLY_EN = 1
3705 14:44:21.538898 VALID_LAT_VALUE = 1
3706 14:44:21.542133 ==============================================================
3707 14:44:21.545443 Enter into Gating configuration >>>>
3708 14:44:21.548812 Exit from Gating configuration <<<<
3709 14:44:21.552215 Enter into DVFS_PRE_config >>>>>
3710 14:44:21.565608 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3711 14:44:21.568600 Exit from DVFS_PRE_config <<<<<
3712 14:44:21.571980 Enter into PICG configuration >>>>
3713 14:44:21.575101 Exit from PICG configuration <<<<
3714 14:44:21.575182 [RX_INPUT] configuration >>>>>
3715 14:44:21.578426 [RX_INPUT] configuration <<<<<
3716 14:44:21.585078 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3717 14:44:21.588421 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3718 14:44:21.595030 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3719 14:44:21.601514 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3720 14:44:21.608223 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3721 14:44:21.614862 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3722 14:44:21.618271 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3723 14:44:21.621411 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3724 14:44:21.628102 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3725 14:44:21.631287 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3726 14:44:21.634676 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3727 14:44:21.641264 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3728 14:44:21.644437 ===================================
3729 14:44:21.644519 LPDDR4 DRAM CONFIGURATION
3730 14:44:21.647800 ===================================
3731 14:44:21.651142 EX_ROW_EN[0] = 0x0
3732 14:44:21.651223 EX_ROW_EN[1] = 0x0
3733 14:44:21.654538 LP4Y_EN = 0x0
3734 14:44:21.654619 WORK_FSP = 0x0
3735 14:44:21.658159 WL = 0x2
3736 14:44:21.658239 RL = 0x2
3737 14:44:21.661359 BL = 0x2
3738 14:44:21.661439 RPST = 0x0
3739 14:44:21.664733 RD_PRE = 0x0
3740 14:44:21.668151 WR_PRE = 0x1
3741 14:44:21.668232 WR_PST = 0x0
3742 14:44:21.671166 DBI_WR = 0x0
3743 14:44:21.671247 DBI_RD = 0x0
3744 14:44:21.674407 OTF = 0x1
3745 14:44:21.677822 ===================================
3746 14:44:21.681107 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3747 14:44:21.684653 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3748 14:44:21.688069 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3749 14:44:21.691226 ===================================
3750 14:44:21.694431 LPDDR4 DRAM CONFIGURATION
3751 14:44:21.697789 ===================================
3752 14:44:21.701196 EX_ROW_EN[0] = 0x10
3753 14:44:21.701278 EX_ROW_EN[1] = 0x0
3754 14:44:21.704308 LP4Y_EN = 0x0
3755 14:44:21.704389 WORK_FSP = 0x0
3756 14:44:21.707533 WL = 0x2
3757 14:44:21.707614 RL = 0x2
3758 14:44:21.710834 BL = 0x2
3759 14:44:21.710916 RPST = 0x0
3760 14:44:21.714347 RD_PRE = 0x0
3761 14:44:21.714430 WR_PRE = 0x1
3762 14:44:21.717518 WR_PST = 0x0
3763 14:44:21.720993 DBI_WR = 0x0
3764 14:44:21.721075 DBI_RD = 0x0
3765 14:44:21.724139 OTF = 0x1
3766 14:44:21.727630 ===================================
3767 14:44:21.730636 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3768 14:44:21.735937 nWR fixed to 30
3769 14:44:21.739480 [ModeRegInit_LP4] CH0 RK0
3770 14:44:21.739564 [ModeRegInit_LP4] CH0 RK1
3771 14:44:21.742928 [ModeRegInit_LP4] CH1 RK0
3772 14:44:21.746213 [ModeRegInit_LP4] CH1 RK1
3773 14:44:21.746295 match AC timing 16
3774 14:44:21.752723 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3775 14:44:21.755830 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3776 14:44:21.759136 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3777 14:44:21.766168 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3778 14:44:21.769182 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3779 14:44:21.769264 ==
3780 14:44:21.772573 Dram Type= 6, Freq= 0, CH_0, rank 0
3781 14:44:21.775680 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3782 14:44:21.775762 ==
3783 14:44:21.782332 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3784 14:44:21.789003 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3785 14:44:21.792225 [CA 0] Center 36 (6~66) winsize 61
3786 14:44:21.795773 [CA 1] Center 36 (6~66) winsize 61
3787 14:44:21.799506 [CA 2] Center 34 (4~65) winsize 62
3788 14:44:21.802159 [CA 3] Center 34 (4~65) winsize 62
3789 14:44:21.805578 [CA 4] Center 33 (3~64) winsize 62
3790 14:44:21.809087 [CA 5] Center 33 (3~64) winsize 62
3791 14:44:21.809168
3792 14:44:21.812308 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3793 14:44:21.812389
3794 14:44:21.816434 [CATrainingPosCal] consider 1 rank data
3795 14:44:21.819352 u2DelayCellTimex100 = 270/100 ps
3796 14:44:21.822358 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3797 14:44:21.825609 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3798 14:44:21.828905 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3799 14:44:21.832231 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3800 14:44:21.835505 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3801 14:44:21.842058 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3802 14:44:21.842143
3803 14:44:21.845582 CA PerBit enable=1, Macro0, CA PI delay=33
3804 14:44:21.845664
3805 14:44:21.848837 [CBTSetCACLKResult] CA Dly = 33
3806 14:44:21.848920 CS Dly: 6 (0~37)
3807 14:44:21.848984 ==
3808 14:44:21.851942 Dram Type= 6, Freq= 0, CH_0, rank 1
3809 14:44:21.855281 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3810 14:44:21.858565 ==
3811 14:44:21.861891 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3812 14:44:21.868471 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3813 14:44:21.871991 [CA 0] Center 36 (6~66) winsize 61
3814 14:44:21.874941 [CA 1] Center 35 (5~66) winsize 62
3815 14:44:21.878357 [CA 2] Center 34 (4~65) winsize 62
3816 14:44:21.881817 [CA 3] Center 34 (3~65) winsize 63
3817 14:44:21.884973 [CA 4] Center 33 (3~64) winsize 62
3818 14:44:21.888494 [CA 5] Center 33 (3~64) winsize 62
3819 14:44:21.888576
3820 14:44:21.891624 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3821 14:44:21.891706
3822 14:44:21.894746 [CATrainingPosCal] consider 2 rank data
3823 14:44:21.898175 u2DelayCellTimex100 = 270/100 ps
3824 14:44:21.901637 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3825 14:44:21.904707 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3826 14:44:21.911377 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3827 14:44:21.914712 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3828 14:44:21.918032 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3829 14:44:21.921494 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3830 14:44:21.921577
3831 14:44:21.924556 CA PerBit enable=1, Macro0, CA PI delay=33
3832 14:44:21.924640
3833 14:44:21.927882 [CBTSetCACLKResult] CA Dly = 33
3834 14:44:21.927965 CS Dly: 5 (0~35)
3835 14:44:21.928030
3836 14:44:21.931040 ----->DramcWriteLeveling(PI) begin...
3837 14:44:21.934550 ==
3838 14:44:21.937998 Dram Type= 6, Freq= 0, CH_0, rank 0
3839 14:44:21.941146 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3840 14:44:21.941249 ==
3841 14:44:21.944493 Write leveling (Byte 0): 32 => 32
3842 14:44:21.947636 Write leveling (Byte 1): 30 => 30
3843 14:44:21.950986 DramcWriteLeveling(PI) end<-----
3844 14:44:21.951067
3845 14:44:21.951130 ==
3846 14:44:21.954283 Dram Type= 6, Freq= 0, CH_0, rank 0
3847 14:44:21.957767 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3848 14:44:21.957849 ==
3849 14:44:21.961059 [Gating] SW mode calibration
3850 14:44:21.967410 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3851 14:44:21.974206 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3852 14:44:21.977573 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3853 14:44:21.980709 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3854 14:44:21.987405 0 5 8 | B1->B0 | 3232 2f2f | 1 1 | (1 0) (1 0)
3855 14:44:21.990611 0 5 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (1 0)
3856 14:44:21.993951 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3857 14:44:22.000981 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3858 14:44:22.004104 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3859 14:44:22.007394 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3860 14:44:22.010800 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3861 14:44:22.017358 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3862 14:44:22.020607 0 6 8 | B1->B0 | 2a2a 3333 | 0 0 | (0 0) (0 0)
3863 14:44:22.024499 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3864 14:44:22.030664 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3865 14:44:22.034027 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3866 14:44:22.037109 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3867 14:44:22.043975 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3868 14:44:22.047237 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3869 14:44:22.050531 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3870 14:44:22.057163 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3871 14:44:22.060453 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3872 14:44:22.063852 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3873 14:44:22.070516 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3874 14:44:22.073650 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3875 14:44:22.076904 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3876 14:44:22.083792 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3877 14:44:22.086847 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3878 14:44:22.090183 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3879 14:44:22.096808 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3880 14:44:22.100278 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3881 14:44:22.103586 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3882 14:44:22.109953 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3883 14:44:22.113437 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3884 14:44:22.116675 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3885 14:44:22.123204 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3886 14:44:22.126619 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3887 14:44:22.130045 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3888 14:44:22.133355 Total UI for P1: 0, mck2ui 16
3889 14:44:22.136563 best dqsien dly found for B0: ( 0, 9, 10)
3890 14:44:22.143011 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3891 14:44:22.143123 Total UI for P1: 0, mck2ui 16
3892 14:44:22.149816 best dqsien dly found for B1: ( 0, 9, 10)
3893 14:44:22.153209 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
3894 14:44:22.156314 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3895 14:44:22.156401
3896 14:44:22.159660 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
3897 14:44:22.162984 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3898 14:44:22.166529 [Gating] SW calibration Done
3899 14:44:22.166611 ==
3900 14:44:22.169736 Dram Type= 6, Freq= 0, CH_0, rank 0
3901 14:44:22.173154 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3902 14:44:22.173237 ==
3903 14:44:22.176466 RX Vref Scan: 0
3904 14:44:22.176548
3905 14:44:22.176614 RX Vref 0 -> 0, step: 1
3906 14:44:22.176675
3907 14:44:22.179499 RX Delay -230 -> 252, step: 16
3908 14:44:22.186323 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3909 14:44:22.189525 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
3910 14:44:22.192953 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
3911 14:44:22.196318 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3912 14:44:22.199524 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3913 14:44:22.206185 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
3914 14:44:22.209402 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3915 14:44:22.212752 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3916 14:44:22.216274 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3917 14:44:22.222809 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3918 14:44:22.226368 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3919 14:44:22.229203 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3920 14:44:22.232777 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3921 14:44:22.239226 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3922 14:44:22.242555 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3923 14:44:22.246060 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3924 14:44:22.246144 ==
3925 14:44:22.249415 Dram Type= 6, Freq= 0, CH_0, rank 0
3926 14:44:22.252493 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3927 14:44:22.252578 ==
3928 14:44:22.255698 DQS Delay:
3929 14:44:22.255815 DQS0 = 0, DQS1 = 0
3930 14:44:22.259054 DQM Delay:
3931 14:44:22.259137 DQM0 = 41, DQM1 = 33
3932 14:44:22.259202 DQ Delay:
3933 14:44:22.262356 DQ0 =33, DQ1 =41, DQ2 =41, DQ3 =33
3934 14:44:22.265604 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
3935 14:44:22.268981 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3936 14:44:22.272214 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3937 14:44:22.272299
3938 14:44:22.272363
3939 14:44:22.275846 ==
3940 14:44:22.278945 Dram Type= 6, Freq= 0, CH_0, rank 0
3941 14:44:22.282144 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3942 14:44:22.282259 ==
3943 14:44:22.282325
3944 14:44:22.282384
3945 14:44:22.285648 TX Vref Scan disable
3946 14:44:22.285731 == TX Byte 0 ==
3947 14:44:22.292176 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
3948 14:44:22.295516 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
3949 14:44:22.295602 == TX Byte 1 ==
3950 14:44:22.302212 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3951 14:44:22.305574 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3952 14:44:22.305660 ==
3953 14:44:22.308765 Dram Type= 6, Freq= 0, CH_0, rank 0
3954 14:44:22.312065 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3955 14:44:22.312148 ==
3956 14:44:22.312213
3957 14:44:22.312274
3958 14:44:22.315426 TX Vref Scan disable
3959 14:44:22.318764 == TX Byte 0 ==
3960 14:44:22.322167 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
3961 14:44:22.325687 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
3962 14:44:22.328653 == TX Byte 1 ==
3963 14:44:22.332060 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3964 14:44:22.335388 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3965 14:44:22.335475
3966 14:44:22.338805 [DATLAT]
3967 14:44:22.338887 Freq=600, CH0 RK0
3968 14:44:22.338952
3969 14:44:22.342042 DATLAT Default: 0x9
3970 14:44:22.342124 0, 0xFFFF, sum = 0
3971 14:44:22.345212 1, 0xFFFF, sum = 0
3972 14:44:22.345334 2, 0xFFFF, sum = 0
3973 14:44:22.348843 3, 0xFFFF, sum = 0
3974 14:44:22.348926 4, 0xFFFF, sum = 0
3975 14:44:22.352009 5, 0xFFFF, sum = 0
3976 14:44:22.352093 6, 0xFFFF, sum = 0
3977 14:44:22.355232 7, 0x0, sum = 1
3978 14:44:22.355318 8, 0x0, sum = 2
3979 14:44:22.358873 9, 0x0, sum = 3
3980 14:44:22.358956 10, 0x0, sum = 4
3981 14:44:22.361820 best_step = 8
3982 14:44:22.361902
3983 14:44:22.361966 ==
3984 14:44:22.365109 Dram Type= 6, Freq= 0, CH_0, rank 0
3985 14:44:22.368600 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3986 14:44:22.368682 ==
3987 14:44:22.368747 RX Vref Scan: 1
3988 14:44:22.372049
3989 14:44:22.372130 RX Vref 0 -> 0, step: 1
3990 14:44:22.372195
3991 14:44:22.375275 RX Delay -195 -> 252, step: 8
3992 14:44:22.375357
3993 14:44:22.378702 Set Vref, RX VrefLevel [Byte0]: 47
3994 14:44:22.381843 [Byte1]: 49
3995 14:44:22.385434
3996 14:44:22.385515 Final RX Vref Byte 0 = 47 to rank0
3997 14:44:22.388682 Final RX Vref Byte 1 = 49 to rank0
3998 14:44:22.392052 Final RX Vref Byte 0 = 47 to rank1
3999 14:44:22.395239 Final RX Vref Byte 1 = 49 to rank1==
4000 14:44:22.398740 Dram Type= 6, Freq= 0, CH_0, rank 0
4001 14:44:22.405027 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4002 14:44:22.405116 ==
4003 14:44:22.405181 DQS Delay:
4004 14:44:22.408416 DQS0 = 0, DQS1 = 0
4005 14:44:22.408503 DQM Delay:
4006 14:44:22.408568 DQM0 = 41, DQM1 = 30
4007 14:44:22.411691 DQ Delay:
4008 14:44:22.415239 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =36
4009 14:44:22.418465 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4010 14:44:22.421896 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4011 14:44:22.424868 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4012 14:44:22.424950
4013 14:44:22.425013
4014 14:44:22.431617 [DQSOSCAuto] RK0, (LSB)MR18= 0x5454, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4015 14:44:22.435059 CH0 RK0: MR19=808, MR18=5454
4016 14:44:22.441514 CH0_RK0: MR19=0x808, MR18=0x5454, DQSOSC=393, MR23=63, INC=169, DEC=113
4017 14:44:22.441602
4018 14:44:22.444767 ----->DramcWriteLeveling(PI) begin...
4019 14:44:22.444850 ==
4020 14:44:22.448040 Dram Type= 6, Freq= 0, CH_0, rank 1
4021 14:44:22.451540 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4022 14:44:22.451623 ==
4023 14:44:22.454596 Write leveling (Byte 0): 31 => 31
4024 14:44:22.457997 Write leveling (Byte 1): 30 => 30
4025 14:44:22.461269 DramcWriteLeveling(PI) end<-----
4026 14:44:22.461360
4027 14:44:22.461425 ==
4028 14:44:22.464525 Dram Type= 6, Freq= 0, CH_0, rank 1
4029 14:44:22.467742 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4030 14:44:22.471290 ==
4031 14:44:22.471372 [Gating] SW mode calibration
4032 14:44:22.477985 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4033 14:44:22.484349 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4034 14:44:22.487716 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4035 14:44:22.494349 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4036 14:44:22.497909 0 5 8 | B1->B0 | 3333 2f2f | 1 1 | (1 0) (1 0)
4037 14:44:22.501024 0 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
4038 14:44:22.507499 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 14:44:22.511004 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 14:44:22.514244 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 14:44:22.521059 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 14:44:22.524679 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 14:44:22.527468 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 14:44:22.534150 0 6 8 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
4045 14:44:22.537411 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 14:44:22.541122 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 14:44:22.547555 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 14:44:22.550721 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 14:44:22.553934 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 14:44:22.560900 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 14:44:22.564038 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 14:44:22.567342 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4053 14:44:22.570676 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4054 14:44:22.577447 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 14:44:22.580638 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 14:44:22.584024 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 14:44:22.590489 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 14:44:22.593861 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 14:44:22.597114 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 14:44:22.603784 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 14:44:22.607147 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 14:44:22.610393 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 14:44:22.617118 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 14:44:22.620143 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 14:44:22.623512 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 14:44:22.630224 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 14:44:22.633433 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 14:44:22.636668 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4069 14:44:22.643330 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4070 14:44:22.647192 Total UI for P1: 0, mck2ui 16
4071 14:44:22.650204 best dqsien dly found for B0: ( 0, 9, 8)
4072 14:44:22.653819 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 14:44:22.656855 Total UI for P1: 0, mck2ui 16
4074 14:44:22.660182 best dqsien dly found for B1: ( 0, 9, 10)
4075 14:44:22.663524 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4076 14:44:22.666799 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4077 14:44:22.666881
4078 14:44:22.670018 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4079 14:44:22.673403 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4080 14:44:22.676816 [Gating] SW calibration Done
4081 14:44:22.676898 ==
4082 14:44:22.680169 Dram Type= 6, Freq= 0, CH_0, rank 1
4083 14:44:22.686581 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4084 14:44:22.686664 ==
4085 14:44:22.686729 RX Vref Scan: 0
4086 14:44:22.686789
4087 14:44:22.690025 RX Vref 0 -> 0, step: 1
4088 14:44:22.690107
4089 14:44:22.693147 RX Delay -230 -> 252, step: 16
4090 14:44:22.696772 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4091 14:44:22.699682 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4092 14:44:22.702960 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4093 14:44:22.709639 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4094 14:44:22.712935 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4095 14:44:22.716099 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4096 14:44:22.719462 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4097 14:44:22.726050 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4098 14:44:22.729632 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4099 14:44:22.732651 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4100 14:44:22.736050 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4101 14:44:22.742705 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4102 14:44:22.746047 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4103 14:44:22.749240 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4104 14:44:22.752528 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4105 14:44:22.755881 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4106 14:44:22.759220 ==
4107 14:44:22.762656 Dram Type= 6, Freq= 0, CH_0, rank 1
4108 14:44:22.765886 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4109 14:44:22.765968 ==
4110 14:44:22.766032 DQS Delay:
4111 14:44:22.769088 DQS0 = 0, DQS1 = 0
4112 14:44:22.769170 DQM Delay:
4113 14:44:22.772676 DQM0 = 41, DQM1 = 34
4114 14:44:22.772758 DQ Delay:
4115 14:44:22.775631 DQ0 =33, DQ1 =41, DQ2 =41, DQ3 =33
4116 14:44:22.779165 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4117 14:44:22.782343 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4118 14:44:22.785580 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4119 14:44:22.785661
4120 14:44:22.785726
4121 14:44:22.785785 ==
4122 14:44:22.789000 Dram Type= 6, Freq= 0, CH_0, rank 1
4123 14:44:22.792359 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4124 14:44:22.792442 ==
4125 14:44:22.792520
4126 14:44:22.792581
4127 14:44:22.795747 TX Vref Scan disable
4128 14:44:22.798796 == TX Byte 0 ==
4129 14:44:22.802440 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4130 14:44:22.805656 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4131 14:44:22.808815 == TX Byte 1 ==
4132 14:44:22.812103 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4133 14:44:22.815332 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4134 14:44:22.815414 ==
4135 14:44:22.818557 Dram Type= 6, Freq= 0, CH_0, rank 1
4136 14:44:22.825249 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4137 14:44:22.825343 ==
4138 14:44:22.825407
4139 14:44:22.825467
4140 14:44:22.825524 TX Vref Scan disable
4141 14:44:22.829673 == TX Byte 0 ==
4142 14:44:22.833114 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4143 14:44:22.836388 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4144 14:44:22.839677 == TX Byte 1 ==
4145 14:44:22.843038 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4146 14:44:22.849711 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4147 14:44:22.849828
4148 14:44:22.849896 [DATLAT]
4149 14:44:22.849956 Freq=600, CH0 RK1
4150 14:44:22.850015
4151 14:44:22.852978 DATLAT Default: 0x8
4152 14:44:22.853060 0, 0xFFFF, sum = 0
4153 14:44:22.856807 1, 0xFFFF, sum = 0
4154 14:44:22.856891 2, 0xFFFF, sum = 0
4155 14:44:22.859601 3, 0xFFFF, sum = 0
4156 14:44:22.862909 4, 0xFFFF, sum = 0
4157 14:44:22.862992 5, 0xFFFF, sum = 0
4158 14:44:22.866170 6, 0xFFFF, sum = 0
4159 14:44:22.866253 7, 0x0, sum = 1
4160 14:44:22.866318 8, 0x0, sum = 2
4161 14:44:22.869809 9, 0x0, sum = 3
4162 14:44:22.869892 10, 0x0, sum = 4
4163 14:44:22.873601 best_step = 8
4164 14:44:22.873683
4165 14:44:22.873747 ==
4166 14:44:22.876183 Dram Type= 6, Freq= 0, CH_0, rank 1
4167 14:44:22.879690 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4168 14:44:22.879772 ==
4169 14:44:22.882786 RX Vref Scan: 0
4170 14:44:22.882868
4171 14:44:22.882932 RX Vref 0 -> 0, step: 1
4172 14:44:22.882991
4173 14:44:22.885874 RX Delay -179 -> 252, step: 8
4174 14:44:22.893232 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4175 14:44:22.896724 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4176 14:44:22.899876 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4177 14:44:22.903315 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4178 14:44:22.909801 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4179 14:44:22.912976 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4180 14:44:22.916425 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4181 14:44:22.919943 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4182 14:44:22.926464 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4183 14:44:22.929882 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4184 14:44:22.932893 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4185 14:44:22.936603 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4186 14:44:22.939476 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4187 14:44:22.946209 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4188 14:44:22.949651 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4189 14:44:22.952968 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4190 14:44:22.953050 ==
4191 14:44:22.956376 Dram Type= 6, Freq= 0, CH_0, rank 1
4192 14:44:22.962644 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4193 14:44:22.962726 ==
4194 14:44:22.962790 DQS Delay:
4195 14:44:22.962850 DQS0 = 0, DQS1 = 0
4196 14:44:22.965952 DQM Delay:
4197 14:44:22.966034 DQM0 = 40, DQM1 = 32
4198 14:44:22.969215 DQ Delay:
4199 14:44:22.972659 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4200 14:44:22.976081 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4201 14:44:22.979565 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4202 14:44:22.982650 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4203 14:44:22.982731
4204 14:44:22.982795
4205 14:44:22.989210 [DQSOSCAuto] RK1, (LSB)MR18= 0x6565, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
4206 14:44:22.992785 CH0 RK1: MR19=808, MR18=6565
4207 14:44:22.999060 CH0_RK1: MR19=0x808, MR18=0x6565, DQSOSC=390, MR23=63, INC=172, DEC=114
4208 14:44:23.002383 [RxdqsGatingPostProcess] freq 600
4209 14:44:23.005524 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4210 14:44:23.009293 Pre-setting of DQS Precalculation
4211 14:44:23.015526 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4212 14:44:23.015607 ==
4213 14:44:23.019136 Dram Type= 6, Freq= 0, CH_1, rank 0
4214 14:44:23.022258 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4215 14:44:23.022340 ==
4216 14:44:23.029067 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4217 14:44:23.032255 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4218 14:44:23.036907 [CA 0] Center 35 (5~66) winsize 62
4219 14:44:23.040054 [CA 1] Center 34 (4~65) winsize 62
4220 14:44:23.043395 [CA 2] Center 33 (3~64) winsize 62
4221 14:44:23.046753 [CA 3] Center 33 (3~64) winsize 62
4222 14:44:23.049990 [CA 4] Center 32 (2~63) winsize 62
4223 14:44:23.053244 [CA 5] Center 32 (2~63) winsize 62
4224 14:44:23.053332
4225 14:44:23.056702 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4226 14:44:23.056783
4227 14:44:23.059996 [CATrainingPosCal] consider 1 rank data
4228 14:44:23.063629 u2DelayCellTimex100 = 270/100 ps
4229 14:44:23.066762 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4230 14:44:23.073034 CA1 delay=34 (4~65),Diff = 2 PI (19 cell)
4231 14:44:23.076346 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4232 14:44:23.079659 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4233 14:44:23.083076 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4234 14:44:23.086259 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4235 14:44:23.086367
4236 14:44:23.090045 CA PerBit enable=1, Macro0, CA PI delay=32
4237 14:44:23.090168
4238 14:44:23.092957 [CBTSetCACLKResult] CA Dly = 32
4239 14:44:23.096347 CS Dly: 4 (0~35)
4240 14:44:23.096442 ==
4241 14:44:23.099561 Dram Type= 6, Freq= 0, CH_1, rank 1
4242 14:44:23.102813 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4243 14:44:23.102910 ==
4244 14:44:23.109425 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4245 14:44:23.112771 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4246 14:44:23.116752 [CA 0] Center 35 (5~65) winsize 61
4247 14:44:23.120000 [CA 1] Center 34 (4~65) winsize 62
4248 14:44:23.123512 [CA 2] Center 33 (3~64) winsize 62
4249 14:44:23.126830 [CA 3] Center 33 (3~64) winsize 62
4250 14:44:23.130072 [CA 4] Center 32 (2~63) winsize 62
4251 14:44:23.133407 [CA 5] Center 32 (2~63) winsize 62
4252 14:44:23.133487
4253 14:44:23.136632 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4254 14:44:23.136711
4255 14:44:23.139829 [CATrainingPosCal] consider 2 rank data
4256 14:44:23.143106 u2DelayCellTimex100 = 270/100 ps
4257 14:44:23.146495 CA0 delay=35 (5~65),Diff = 3 PI (28 cell)
4258 14:44:23.153003 CA1 delay=34 (4~65),Diff = 2 PI (19 cell)
4259 14:44:23.156386 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4260 14:44:23.159703 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4261 14:44:23.163099 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4262 14:44:23.166460 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4263 14:44:23.166539
4264 14:44:23.169872 CA PerBit enable=1, Macro0, CA PI delay=32
4265 14:44:23.169954
4266 14:44:23.173014 [CBTSetCACLKResult] CA Dly = 32
4267 14:44:23.173094 CS Dly: 4 (0~36)
4268 14:44:23.176392
4269 14:44:23.179570 ----->DramcWriteLeveling(PI) begin...
4270 14:44:23.179652 ==
4271 14:44:23.183144 Dram Type= 6, Freq= 0, CH_1, rank 0
4272 14:44:23.186265 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4273 14:44:23.186347 ==
4274 14:44:23.189422 Write leveling (Byte 0): 26 => 26
4275 14:44:23.192804 Write leveling (Byte 1): 26 => 26
4276 14:44:23.196095 DramcWriteLeveling(PI) end<-----
4277 14:44:23.196175
4278 14:44:23.196238 ==
4279 14:44:23.199515 Dram Type= 6, Freq= 0, CH_1, rank 0
4280 14:44:23.202703 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4281 14:44:23.202785 ==
4282 14:44:23.206100 [Gating] SW mode calibration
4283 14:44:23.212823 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4284 14:44:23.219204 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4285 14:44:23.222708 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4286 14:44:23.226006 0 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4287 14:44:23.232499 0 5 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4288 14:44:23.236081 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4289 14:44:23.239177 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4290 14:44:23.245776 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4291 14:44:23.249100 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4292 14:44:23.252345 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4293 14:44:23.258991 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4294 14:44:23.262439 0 6 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
4295 14:44:23.265656 0 6 8 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
4296 14:44:23.272239 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4297 14:44:23.275763 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4298 14:44:23.278876 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4299 14:44:23.285714 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4300 14:44:23.288666 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4301 14:44:23.291966 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4302 14:44:23.298716 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4303 14:44:23.301968 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4304 14:44:23.305147 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4305 14:44:23.312028 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 14:44:23.315447 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 14:44:23.318554 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 14:44:23.325498 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 14:44:23.328728 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 14:44:23.331989 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 14:44:23.338374 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 14:44:23.341700 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 14:44:23.345076 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 14:44:23.348664 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4315 14:44:23.355156 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4316 14:44:23.358245 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4317 14:44:23.361584 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4318 14:44:23.368329 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4319 14:44:23.371610 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4320 14:44:23.374842 Total UI for P1: 0, mck2ui 16
4321 14:44:23.378212 best dqsien dly found for B0: ( 0, 9, 4)
4322 14:44:23.381674 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4323 14:44:23.384738 Total UI for P1: 0, mck2ui 16
4324 14:44:23.388385 best dqsien dly found for B1: ( 0, 9, 8)
4325 14:44:23.391453 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4326 14:44:23.394769 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4327 14:44:23.398178
4328 14:44:23.401329 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4329 14:44:23.404638 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4330 14:44:23.408113 [Gating] SW calibration Done
4331 14:44:23.408195 ==
4332 14:44:23.411510 Dram Type= 6, Freq= 0, CH_1, rank 0
4333 14:44:23.414640 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4334 14:44:23.414722 ==
4335 14:44:23.414787 RX Vref Scan: 0
4336 14:44:23.414846
4337 14:44:23.418030 RX Vref 0 -> 0, step: 1
4338 14:44:23.418111
4339 14:44:23.421677 RX Delay -230 -> 252, step: 16
4340 14:44:23.424607 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4341 14:44:23.431573 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4342 14:44:23.434554 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4343 14:44:23.437880 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4344 14:44:23.441074 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4345 14:44:23.444513 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4346 14:44:23.451257 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4347 14:44:23.454357 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4348 14:44:23.457509 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4349 14:44:23.460905 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4350 14:44:23.467719 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4351 14:44:23.470893 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4352 14:44:23.474123 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4353 14:44:23.477821 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4354 14:44:23.484167 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4355 14:44:23.487598 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4356 14:44:23.487680 ==
4357 14:44:23.490670 Dram Type= 6, Freq= 0, CH_1, rank 0
4358 14:44:23.493988 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4359 14:44:23.494069 ==
4360 14:44:23.497554 DQS Delay:
4361 14:44:23.497635 DQS0 = 0, DQS1 = 0
4362 14:44:23.497699 DQM Delay:
4363 14:44:23.500682 DQM0 = 38, DQM1 = 31
4364 14:44:23.500763 DQ Delay:
4365 14:44:23.504070 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4366 14:44:23.507347 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4367 14:44:23.510537 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4368 14:44:23.513766 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =49
4369 14:44:23.513846
4370 14:44:23.513910
4371 14:44:23.513969 ==
4372 14:44:23.517217 Dram Type= 6, Freq= 0, CH_1, rank 0
4373 14:44:23.523671 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4374 14:44:23.523752 ==
4375 14:44:23.523816
4376 14:44:23.523874
4377 14:44:23.523931 TX Vref Scan disable
4378 14:44:23.527320 == TX Byte 0 ==
4379 14:44:23.530794 Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6)
4380 14:44:23.537325 Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6)
4381 14:44:23.537420 == TX Byte 1 ==
4382 14:44:23.540637 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4383 14:44:23.547354 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4384 14:44:23.547435 ==
4385 14:44:23.551104 Dram Type= 6, Freq= 0, CH_1, rank 0
4386 14:44:23.554102 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4387 14:44:23.554183 ==
4388 14:44:23.554247
4389 14:44:23.554305
4390 14:44:23.557096 TX Vref Scan disable
4391 14:44:23.557176 == TX Byte 0 ==
4392 14:44:23.563855 Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6)
4393 14:44:23.567297 Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6)
4394 14:44:23.570392 == TX Byte 1 ==
4395 14:44:23.573802 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4396 14:44:23.577646 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4397 14:44:23.577727
4398 14:44:23.577790 [DATLAT]
4399 14:44:23.580181 Freq=600, CH1 RK0
4400 14:44:23.580261
4401 14:44:23.580323 DATLAT Default: 0x9
4402 14:44:23.583552 0, 0xFFFF, sum = 0
4403 14:44:23.587058 1, 0xFFFF, sum = 0
4404 14:44:23.587142 2, 0xFFFF, sum = 0
4405 14:44:23.590260 3, 0xFFFF, sum = 0
4406 14:44:23.590341 4, 0xFFFF, sum = 0
4407 14:44:23.593565 5, 0xFFFF, sum = 0
4408 14:44:23.593647 6, 0xFFFF, sum = 0
4409 14:44:23.596831 7, 0x0, sum = 1
4410 14:44:23.596913 8, 0x0, sum = 2
4411 14:44:23.596978 9, 0x0, sum = 3
4412 14:44:23.600251 10, 0x0, sum = 4
4413 14:44:23.600332 best_step = 8
4414 14:44:23.600395
4415 14:44:23.600454 ==
4416 14:44:23.603446 Dram Type= 6, Freq= 0, CH_1, rank 0
4417 14:44:23.610144 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4418 14:44:23.610225 ==
4419 14:44:23.610286 RX Vref Scan: 1
4420 14:44:23.610344
4421 14:44:23.613432 RX Vref 0 -> 0, step: 1
4422 14:44:23.613511
4423 14:44:23.616749 RX Delay -195 -> 252, step: 8
4424 14:44:23.616827
4425 14:44:23.620039 Set Vref, RX VrefLevel [Byte0]: 53
4426 14:44:23.623271 [Byte1]: 49
4427 14:44:23.623377
4428 14:44:23.626715 Final RX Vref Byte 0 = 53 to rank0
4429 14:44:23.630061 Final RX Vref Byte 1 = 49 to rank0
4430 14:44:23.633188 Final RX Vref Byte 0 = 53 to rank1
4431 14:44:23.636706 Final RX Vref Byte 1 = 49 to rank1==
4432 14:44:23.640049 Dram Type= 6, Freq= 0, CH_1, rank 0
4433 14:44:23.643326 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4434 14:44:23.643408 ==
4435 14:44:23.646656 DQS Delay:
4436 14:44:23.646736 DQS0 = 0, DQS1 = 0
4437 14:44:23.649913 DQM Delay:
4438 14:44:23.649993 DQM0 = 36, DQM1 = 28
4439 14:44:23.650056 DQ Delay:
4440 14:44:23.653231 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4441 14:44:23.656405 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4442 14:44:23.659815 DQ8 =12, DQ9 =12, DQ10 =32, DQ11 =20
4443 14:44:23.663284 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =40
4444 14:44:23.663364
4445 14:44:23.663427
4446 14:44:23.672960 [DQSOSCAuto] RK0, (LSB)MR18= 0x7373, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4447 14:44:23.676492 CH1 RK0: MR19=808, MR18=7373
4448 14:44:23.682868 CH1_RK0: MR19=0x808, MR18=0x7373, DQSOSC=388, MR23=63, INC=174, DEC=116
4449 14:44:23.682949
4450 14:44:23.686336 ----->DramcWriteLeveling(PI) begin...
4451 14:44:23.686418 ==
4452 14:44:23.689840 Dram Type= 6, Freq= 0, CH_1, rank 1
4453 14:44:23.692724 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4454 14:44:23.692805 ==
4455 14:44:23.696340 Write leveling (Byte 0): 26 => 26
4456 14:44:23.699437 Write leveling (Byte 1): 27 => 27
4457 14:44:23.702738 DramcWriteLeveling(PI) end<-----
4458 14:44:23.702818
4459 14:44:23.702881 ==
4460 14:44:23.705945 Dram Type= 6, Freq= 0, CH_1, rank 1
4461 14:44:23.709212 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4462 14:44:23.709351 ==
4463 14:44:23.712649 [Gating] SW mode calibration
4464 14:44:23.719119 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4465 14:44:23.725812 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4466 14:44:23.729228 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4467 14:44:23.732322 0 5 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
4468 14:44:23.739096 0 5 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4469 14:44:23.742188 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 14:44:23.745871 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 14:44:23.752275 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 14:44:23.755468 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 14:44:23.759137 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 14:44:23.765814 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 14:44:23.769136 0 6 4 | B1->B0 | 2b2b 3333 | 0 0 | (0 0) (0 0)
4476 14:44:23.772274 0 6 8 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
4477 14:44:23.779100 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 14:44:23.782198 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 14:44:23.785668 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 14:44:23.792485 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 14:44:23.795603 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 14:44:23.798908 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 14:44:23.805868 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4484 14:44:23.808820 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 14:44:23.812390 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 14:44:23.818780 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 14:44:23.822060 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 14:44:23.825567 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 14:44:23.832040 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 14:44:23.835167 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 14:44:23.838458 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 14:44:23.845032 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 14:44:23.848466 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 14:44:23.851736 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 14:44:23.858322 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 14:44:23.861822 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 14:44:23.865262 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 14:44:23.872004 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 14:44:23.875183 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4500 14:44:23.878228 Total UI for P1: 0, mck2ui 16
4501 14:44:23.881454 best dqsien dly found for B0: ( 0, 9, 2)
4502 14:44:23.884770 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 14:44:23.888138 Total UI for P1: 0, mck2ui 16
4504 14:44:23.891585 best dqsien dly found for B1: ( 0, 9, 4)
4505 14:44:23.894729 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4506 14:44:23.898117 best DQS1 dly(MCK, UI, PI) = (0, 9, 4)
4507 14:44:23.898197
4508 14:44:23.901226 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4509 14:44:23.907941 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 4)
4510 14:44:23.908025 [Gating] SW calibration Done
4511 14:44:23.908090 ==
4512 14:44:23.911384 Dram Type= 6, Freq= 0, CH_1, rank 1
4513 14:44:23.918171 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4514 14:44:23.918253 ==
4515 14:44:23.918317 RX Vref Scan: 0
4516 14:44:23.918376
4517 14:44:23.921199 RX Vref 0 -> 0, step: 1
4518 14:44:23.921281
4519 14:44:23.924516 RX Delay -230 -> 252, step: 16
4520 14:44:23.928030 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4521 14:44:23.931193 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4522 14:44:23.937601 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4523 14:44:23.940887 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4524 14:44:23.944310 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4525 14:44:23.947567 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4526 14:44:23.950863 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4527 14:44:23.957506 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4528 14:44:23.960749 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4529 14:44:23.964412 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4530 14:44:23.967674 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4531 14:44:23.974175 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4532 14:44:23.977594 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4533 14:44:23.980817 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4534 14:44:23.984089 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4535 14:44:23.990830 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4536 14:44:23.990962 ==
4537 14:44:23.994061 Dram Type= 6, Freq= 0, CH_1, rank 1
4538 14:44:23.997562 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4539 14:44:23.997657 ==
4540 14:44:23.997723 DQS Delay:
4541 14:44:24.000606 DQS0 = 0, DQS1 = 0
4542 14:44:24.000691 DQM Delay:
4543 14:44:24.003884 DQM0 = 39, DQM1 = 32
4544 14:44:24.004029 DQ Delay:
4545 14:44:24.007182 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4546 14:44:24.010535 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4547 14:44:24.013995 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4548 14:44:24.017260 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4549 14:44:24.017361
4550 14:44:24.017427
4551 14:44:24.017487 ==
4552 14:44:24.020381 Dram Type= 6, Freq= 0, CH_1, rank 1
4553 14:44:24.023685 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4554 14:44:24.023794 ==
4555 14:44:24.023886
4556 14:44:24.027010
4557 14:44:24.027093 TX Vref Scan disable
4558 14:44:24.030326 == TX Byte 0 ==
4559 14:44:24.033658 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4560 14:44:24.036928 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4561 14:44:24.040411 == TX Byte 1 ==
4562 14:44:24.043381 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4563 14:44:24.046793 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4564 14:44:24.046878 ==
4565 14:44:24.050039 Dram Type= 6, Freq= 0, CH_1, rank 1
4566 14:44:24.056741 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4567 14:44:24.056843 ==
4568 14:44:24.056907
4569 14:44:24.056966
4570 14:44:24.059923 TX Vref Scan disable
4571 14:44:24.060006 == TX Byte 0 ==
4572 14:44:24.066577 Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6)
4573 14:44:24.070034 Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6)
4574 14:44:24.070130 == TX Byte 1 ==
4575 14:44:24.076468 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4576 14:44:24.080070 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4577 14:44:24.080161
4578 14:44:24.080225 [DATLAT]
4579 14:44:24.083394 Freq=600, CH1 RK1
4580 14:44:24.083479
4581 14:44:24.083542 DATLAT Default: 0x8
4582 14:44:24.086432 0, 0xFFFF, sum = 0
4583 14:44:24.086514 1, 0xFFFF, sum = 0
4584 14:44:24.089975 2, 0xFFFF, sum = 0
4585 14:44:24.090057 3, 0xFFFF, sum = 0
4586 14:44:24.093014 4, 0xFFFF, sum = 0
4587 14:44:24.096361 5, 0xFFFF, sum = 0
4588 14:44:24.096444 6, 0xFFFF, sum = 0
4589 14:44:24.096508 7, 0x0, sum = 1
4590 14:44:24.099533 8, 0x0, sum = 2
4591 14:44:24.099615 9, 0x0, sum = 3
4592 14:44:24.102803 10, 0x0, sum = 4
4593 14:44:24.102884 best_step = 8
4594 14:44:24.102947
4595 14:44:24.103005 ==
4596 14:44:24.106338 Dram Type= 6, Freq= 0, CH_1, rank 1
4597 14:44:24.113017 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4598 14:44:24.113126 ==
4599 14:44:24.113217 RX Vref Scan: 0
4600 14:44:24.113327
4601 14:44:24.116190 RX Vref 0 -> 0, step: 1
4602 14:44:24.116270
4603 14:44:24.119514 RX Delay -195 -> 252, step: 8
4604 14:44:24.123064 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4605 14:44:24.129347 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4606 14:44:24.132543 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4607 14:44:24.135934 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4608 14:44:24.139227 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4609 14:44:24.145846 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4610 14:44:24.149070 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4611 14:44:24.152406 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4612 14:44:24.155683 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4613 14:44:24.159051 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4614 14:44:24.165647 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4615 14:44:24.169306 iDelay=205, Bit 11, Center 16 (-147 ~ 180) 328
4616 14:44:24.172294 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4617 14:44:24.175836 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4618 14:44:24.182177 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4619 14:44:24.185506 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4620 14:44:24.185588 ==
4621 14:44:24.188670 Dram Type= 6, Freq= 0, CH_1, rank 1
4622 14:44:24.191975 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4623 14:44:24.192056 ==
4624 14:44:24.195587 DQS Delay:
4625 14:44:24.195667 DQS0 = 0, DQS1 = 0
4626 14:44:24.198560 DQM Delay:
4627 14:44:24.198641 DQM0 = 36, DQM1 = 27
4628 14:44:24.198704 DQ Delay:
4629 14:44:24.201914 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4630 14:44:24.205263 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =32
4631 14:44:24.208693 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =16
4632 14:44:24.211676 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4633 14:44:24.211757
4634 14:44:24.211819
4635 14:44:24.221665 [DQSOSCAuto] RK1, (LSB)MR18= 0x5252, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
4636 14:44:24.225013 CH1 RK1: MR19=808, MR18=5252
4637 14:44:24.231702 CH1_RK1: MR19=0x808, MR18=0x5252, DQSOSC=394, MR23=63, INC=168, DEC=112
4638 14:44:24.231785 [RxdqsGatingPostProcess] freq 600
4639 14:44:24.238496 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4640 14:44:24.241567 Pre-setting of DQS Precalculation
4641 14:44:24.244724 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4642 14:44:24.254903 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4643 14:44:24.261573 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4644 14:44:24.261655
4645 14:44:24.261719
4646 14:44:24.264629 [Calibration Summary] 1200 Mbps
4647 14:44:24.264710 CH 0, Rank 0
4648 14:44:24.268200 SW Impedance : PASS
4649 14:44:24.268281 DUTY Scan : NO K
4650 14:44:24.271272 ZQ Calibration : PASS
4651 14:44:24.274792 Jitter Meter : NO K
4652 14:44:24.274871 CBT Training : PASS
4653 14:44:24.277944 Write leveling : PASS
4654 14:44:24.281158 RX DQS gating : PASS
4655 14:44:24.281236 RX DQ/DQS(RDDQC) : PASS
4656 14:44:24.284557 TX DQ/DQS : PASS
4657 14:44:24.288098 RX DATLAT : PASS
4658 14:44:24.288177 RX DQ/DQS(Engine): PASS
4659 14:44:24.291194 TX OE : NO K
4660 14:44:24.291288 All Pass.
4661 14:44:24.291408
4662 14:44:24.294655 CH 0, Rank 1
4663 14:44:24.294733 SW Impedance : PASS
4664 14:44:24.297646 DUTY Scan : NO K
4665 14:44:24.300897 ZQ Calibration : PASS
4666 14:44:24.300991 Jitter Meter : NO K
4667 14:44:24.304610 CBT Training : PASS
4668 14:44:24.307809 Write leveling : PASS
4669 14:44:24.307909 RX DQS gating : PASS
4670 14:44:24.311035 RX DQ/DQS(RDDQC) : PASS
4671 14:44:24.314572 TX DQ/DQS : PASS
4672 14:44:24.314653 RX DATLAT : PASS
4673 14:44:24.317898 RX DQ/DQS(Engine): PASS
4674 14:44:24.321082 TX OE : NO K
4675 14:44:24.321163 All Pass.
4676 14:44:24.321226
4677 14:44:24.321285 CH 1, Rank 0
4678 14:44:24.324501 SW Impedance : PASS
4679 14:44:24.327572 DUTY Scan : NO K
4680 14:44:24.327651 ZQ Calibration : PASS
4681 14:44:24.330855 Jitter Meter : NO K
4682 14:44:24.330934 CBT Training : PASS
4683 14:44:24.334166 Write leveling : PASS
4684 14:44:24.337695 RX DQS gating : PASS
4685 14:44:24.337817 RX DQ/DQS(RDDQC) : PASS
4686 14:44:24.341227 TX DQ/DQS : PASS
4687 14:44:24.344387 RX DATLAT : PASS
4688 14:44:24.344467 RX DQ/DQS(Engine): PASS
4689 14:44:24.347534 TX OE : NO K
4690 14:44:24.347615 All Pass.
4691 14:44:24.347724
4692 14:44:24.350693 CH 1, Rank 1
4693 14:44:24.350772 SW Impedance : PASS
4694 14:44:24.354660 DUTY Scan : NO K
4695 14:44:24.357606 ZQ Calibration : PASS
4696 14:44:24.357686 Jitter Meter : NO K
4697 14:44:24.360779 CBT Training : PASS
4698 14:44:24.364138 Write leveling : PASS
4699 14:44:24.364218 RX DQS gating : PASS
4700 14:44:24.367389 RX DQ/DQS(RDDQC) : PASS
4701 14:44:24.370622 TX DQ/DQS : PASS
4702 14:44:24.370705 RX DATLAT : PASS
4703 14:44:24.374304 RX DQ/DQS(Engine): PASS
4704 14:44:24.377479 TX OE : NO K
4705 14:44:24.377561 All Pass.
4706 14:44:24.377626
4707 14:44:24.377686 DramC Write-DBI off
4708 14:44:24.380871 PER_BANK_REFRESH: Hybrid Mode
4709 14:44:24.384088 TX_TRACKING: ON
4710 14:44:24.390797 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4711 14:44:24.393997 [FAST_K] Save calibration result to emmc
4712 14:44:24.400436 dramc_set_vcore_voltage set vcore to 662500
4713 14:44:24.400518 Read voltage for 933, 3
4714 14:44:24.403814 Vio18 = 0
4715 14:44:24.403896 Vcore = 662500
4716 14:44:24.403983 Vdram = 0
4717 14:44:24.404058 Vddq = 0
4718 14:44:24.407151 Vmddr = 0
4719 14:44:24.410256 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4720 14:44:24.417024 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4721 14:44:24.420419 MEM_TYPE=3, freq_sel=17
4722 14:44:24.420519 sv_algorithm_assistance_LP4_1600
4723 14:44:24.427114 ============ PULL DRAM RESETB DOWN ============
4724 14:44:24.430368 ========== PULL DRAM RESETB DOWN end =========
4725 14:44:24.433617 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4726 14:44:24.436959 ===================================
4727 14:44:24.439992 LPDDR4 DRAM CONFIGURATION
4728 14:44:24.443675 ===================================
4729 14:44:24.446822 EX_ROW_EN[0] = 0x0
4730 14:44:24.446910 EX_ROW_EN[1] = 0x0
4731 14:44:24.449944 LP4Y_EN = 0x0
4732 14:44:24.450027 WORK_FSP = 0x0
4733 14:44:24.453676 WL = 0x3
4734 14:44:24.453759 RL = 0x3
4735 14:44:24.456855 BL = 0x2
4736 14:44:24.456938 RPST = 0x0
4737 14:44:24.460174 RD_PRE = 0x0
4738 14:44:24.460256 WR_PRE = 0x1
4739 14:44:24.465979 WR_PST = 0x0
4740 14:44:24.466905 DBI_WR = 0x0
4741 14:44:24.466985 DBI_RD = 0x0
4742 14:44:24.469771 OTF = 0x1
4743 14:44:24.473161 ===================================
4744 14:44:24.476556 ===================================
4745 14:44:24.476714 ANA top config
4746 14:44:24.479818 ===================================
4747 14:44:24.483406 DLL_ASYNC_EN = 0
4748 14:44:24.486596 ALL_SLAVE_EN = 1
4749 14:44:24.486680 NEW_RANK_MODE = 1
4750 14:44:24.489739 DLL_IDLE_MODE = 1
4751 14:44:24.493019 LP45_APHY_COMB_EN = 1
4752 14:44:24.496362 TX_ODT_DIS = 1
4753 14:44:24.496448 NEW_8X_MODE = 1
4754 14:44:24.499634 ===================================
4755 14:44:24.502801 ===================================
4756 14:44:24.506173 data_rate = 1866
4757 14:44:24.509761 CKR = 1
4758 14:44:24.512925 DQ_P2S_RATIO = 8
4759 14:44:24.516124 ===================================
4760 14:44:24.519423 CA_P2S_RATIO = 8
4761 14:44:24.523058 DQ_CA_OPEN = 0
4762 14:44:24.523203 DQ_SEMI_OPEN = 0
4763 14:44:24.526265 CA_SEMI_OPEN = 0
4764 14:44:24.529167 CA_FULL_RATE = 0
4765 14:44:24.532583 DQ_CKDIV4_EN = 1
4766 14:44:24.536126 CA_CKDIV4_EN = 1
4767 14:44:24.539341 CA_PREDIV_EN = 0
4768 14:44:24.539423 PH8_DLY = 0
4769 14:44:24.542659 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4770 14:44:24.545836 DQ_AAMCK_DIV = 4
4771 14:44:24.549126 CA_AAMCK_DIV = 4
4772 14:44:24.552626 CA_ADMCK_DIV = 4
4773 14:44:24.555965 DQ_TRACK_CA_EN = 0
4774 14:44:24.559097 CA_PICK = 933
4775 14:44:24.559180 CA_MCKIO = 933
4776 14:44:24.562280 MCKIO_SEMI = 0
4777 14:44:24.565719 PLL_FREQ = 3732
4778 14:44:24.568855 DQ_UI_PI_RATIO = 32
4779 14:44:24.572170 CA_UI_PI_RATIO = 0
4780 14:44:24.575521 ===================================
4781 14:44:24.578995 ===================================
4782 14:44:24.582323 memory_type:LPDDR4
4783 14:44:24.582415 GP_NUM : 10
4784 14:44:24.585422 SRAM_EN : 1
4785 14:44:24.585509 MD32_EN : 0
4786 14:44:24.588983 ===================================
4787 14:44:24.592289 [ANA_INIT] >>>>>>>>>>>>>>
4788 14:44:24.595533 <<<<<< [CONFIGURE PHASE]: ANA_TX
4789 14:44:24.598885 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4790 14:44:24.602337 ===================================
4791 14:44:24.605446 data_rate = 1866,PCW = 0X8f00
4792 14:44:24.609046 ===================================
4793 14:44:24.612205 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4794 14:44:24.619116 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4795 14:44:24.622149 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4796 14:44:24.628958 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4797 14:44:24.632149 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4798 14:44:24.635429 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4799 14:44:24.635522 [ANA_INIT] flow start
4800 14:44:24.638691 [ANA_INIT] PLL >>>>>>>>
4801 14:44:24.642060 [ANA_INIT] PLL <<<<<<<<
4802 14:44:24.642152 [ANA_INIT] MIDPI >>>>>>>>
4803 14:44:24.645245 [ANA_INIT] MIDPI <<<<<<<<
4804 14:44:24.648856 [ANA_INIT] DLL >>>>>>>>
4805 14:44:24.648948 [ANA_INIT] flow end
4806 14:44:24.655088 ============ LP4 DIFF to SE enter ============
4807 14:44:24.658359 ============ LP4 DIFF to SE exit ============
4808 14:44:24.661767 [ANA_INIT] <<<<<<<<<<<<<
4809 14:44:24.665108 [Flow] Enable top DCM control >>>>>
4810 14:44:24.668372 [Flow] Enable top DCM control <<<<<
4811 14:44:24.668455 Enable DLL master slave shuffle
4812 14:44:24.674940 ==============================================================
4813 14:44:24.678175 Gating Mode config
4814 14:44:24.681543 ==============================================================
4815 14:44:24.684879 Config description:
4816 14:44:24.694749 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4817 14:44:24.701418 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4818 14:44:24.704586 SELPH_MODE 0: By rank 1: By Phase
4819 14:44:24.711401 ==============================================================
4820 14:44:24.714713 GAT_TRACK_EN = 1
4821 14:44:24.717835 RX_GATING_MODE = 2
4822 14:44:24.721231 RX_GATING_TRACK_MODE = 2
4823 14:44:24.724427 SELPH_MODE = 1
4824 14:44:24.727845 PICG_EARLY_EN = 1
4825 14:44:24.727928 VALID_LAT_VALUE = 1
4826 14:44:24.734469 ==============================================================
4827 14:44:24.737820 Enter into Gating configuration >>>>
4828 14:44:24.741382 Exit from Gating configuration <<<<
4829 14:44:24.744233 Enter into DVFS_PRE_config >>>>>
4830 14:44:24.754210 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4831 14:44:24.757606 Exit from DVFS_PRE_config <<<<<
4832 14:44:24.760723 Enter into PICG configuration >>>>
4833 14:44:24.763906 Exit from PICG configuration <<<<
4834 14:44:24.767316 [RX_INPUT] configuration >>>>>
4835 14:44:24.770650 [RX_INPUT] configuration <<<<<
4836 14:44:24.777331 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4837 14:44:24.780517 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4838 14:44:24.787212 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4839 14:44:24.793797 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4840 14:44:24.800535 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4841 14:44:24.807188 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4842 14:44:24.810362 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4843 14:44:24.813699 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4844 14:44:24.817284 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4845 14:44:24.823971 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4846 14:44:24.827144 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4847 14:44:24.830633 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4848 14:44:24.833715 ===================================
4849 14:44:24.837093 LPDDR4 DRAM CONFIGURATION
4850 14:44:24.840459 ===================================
4851 14:44:24.840542 EX_ROW_EN[0] = 0x0
4852 14:44:24.844242 EX_ROW_EN[1] = 0x0
4853 14:44:24.847017 LP4Y_EN = 0x0
4854 14:44:24.847098 WORK_FSP = 0x0
4855 14:44:24.850470 WL = 0x3
4856 14:44:24.850551 RL = 0x3
4857 14:44:24.853555 BL = 0x2
4858 14:44:24.853636 RPST = 0x0
4859 14:44:24.856985 RD_PRE = 0x0
4860 14:44:24.857066 WR_PRE = 0x1
4861 14:44:24.860165 WR_PST = 0x0
4862 14:44:24.860246 DBI_WR = 0x0
4863 14:44:24.863507 DBI_RD = 0x0
4864 14:44:24.863588 OTF = 0x1
4865 14:44:24.866738 ===================================
4866 14:44:24.870117 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4867 14:44:24.876724 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4868 14:44:24.880247 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4869 14:44:24.883369 ===================================
4870 14:44:24.886868 LPDDR4 DRAM CONFIGURATION
4871 14:44:24.889986 ===================================
4872 14:44:24.890074 EX_ROW_EN[0] = 0x10
4873 14:44:24.893337 EX_ROW_EN[1] = 0x0
4874 14:44:24.893420 LP4Y_EN = 0x0
4875 14:44:24.896845 WORK_FSP = 0x0
4876 14:44:24.896929 WL = 0x3
4877 14:44:24.899994 RL = 0x3
4878 14:44:24.903237 BL = 0x2
4879 14:44:24.903323 RPST = 0x0
4880 14:44:24.906665 RD_PRE = 0x0
4881 14:44:24.906750 WR_PRE = 0x1
4882 14:44:24.909944 WR_PST = 0x0
4883 14:44:24.910023 DBI_WR = 0x0
4884 14:44:24.913223 DBI_RD = 0x0
4885 14:44:24.913327 OTF = 0x1
4886 14:44:24.916649 ===================================
4887 14:44:24.923066 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4888 14:44:24.927127 nWR fixed to 30
4889 14:44:24.930512 [ModeRegInit_LP4] CH0 RK0
4890 14:44:24.930593 [ModeRegInit_LP4] CH0 RK1
4891 14:44:24.933745 [ModeRegInit_LP4] CH1 RK0
4892 14:44:24.937167 [ModeRegInit_LP4] CH1 RK1
4893 14:44:24.937262 match AC timing 8
4894 14:44:24.943735 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4895 14:44:24.946953 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4896 14:44:24.950444 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4897 14:44:24.956924 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4898 14:44:24.960381 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4899 14:44:24.960463 ==
4900 14:44:24.963725 Dram Type= 6, Freq= 0, CH_0, rank 0
4901 14:44:24.967103 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4902 14:44:24.967194 ==
4903 14:44:24.973326 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4904 14:44:24.979980 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4905 14:44:24.983350 [CA 0] Center 38 (8~69) winsize 62
4906 14:44:24.986651 [CA 1] Center 38 (8~69) winsize 62
4907 14:44:24.989985 [CA 2] Center 36 (6~67) winsize 62
4908 14:44:24.993454 [CA 3] Center 36 (6~67) winsize 62
4909 14:44:24.996577 [CA 4] Center 35 (5~65) winsize 61
4910 14:44:24.999812 [CA 5] Center 34 (4~65) winsize 62
4911 14:44:24.999906
4912 14:44:25.003129 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4913 14:44:25.003218
4914 14:44:25.006411 [CATrainingPosCal] consider 1 rank data
4915 14:44:25.009711 u2DelayCellTimex100 = 270/100 ps
4916 14:44:25.013033 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4917 14:44:25.016386 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4918 14:44:25.019673 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4919 14:44:25.022925 CA3 delay=36 (6~67),Diff = 2 PI (12 cell)
4920 14:44:25.029554 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4921 14:44:25.032733 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4922 14:44:25.032814
4923 14:44:25.036162 CA PerBit enable=1, Macro0, CA PI delay=34
4924 14:44:25.036243
4925 14:44:25.039986 [CBTSetCACLKResult] CA Dly = 34
4926 14:44:25.040068 CS Dly: 7 (0~38)
4927 14:44:25.040132 ==
4928 14:44:25.042947 Dram Type= 6, Freq= 0, CH_0, rank 1
4929 14:44:25.049320 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4930 14:44:25.049405 ==
4931 14:44:25.052665 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4932 14:44:25.059496 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4933 14:44:25.062579 [CA 0] Center 38 (7~69) winsize 63
4934 14:44:25.066262 [CA 1] Center 38 (7~69) winsize 63
4935 14:44:25.069478 [CA 2] Center 36 (5~67) winsize 63
4936 14:44:25.072738 [CA 3] Center 35 (5~66) winsize 62
4937 14:44:25.076050 [CA 4] Center 34 (4~65) winsize 62
4938 14:44:25.079494 [CA 5] Center 34 (4~65) winsize 62
4939 14:44:25.079575
4940 14:44:25.082936 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4941 14:44:25.083018
4942 14:44:25.086103 [CATrainingPosCal] consider 2 rank data
4943 14:44:25.089397 u2DelayCellTimex100 = 270/100 ps
4944 14:44:25.092814 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4945 14:44:25.096221 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4946 14:44:25.099392 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4947 14:44:25.105967 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4948 14:44:25.109433 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4949 14:44:25.112528 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4950 14:44:25.112610
4951 14:44:25.115898 CA PerBit enable=1, Macro0, CA PI delay=34
4952 14:44:25.115980
4953 14:44:25.119325 [CBTSetCACLKResult] CA Dly = 34
4954 14:44:25.119406 CS Dly: 7 (0~39)
4955 14:44:25.119471
4956 14:44:25.122603 ----->DramcWriteLeveling(PI) begin...
4957 14:44:25.122687 ==
4958 14:44:25.125935 Dram Type= 6, Freq= 0, CH_0, rank 0
4959 14:44:25.132510 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4960 14:44:25.132592 ==
4961 14:44:25.135794 Write leveling (Byte 0): 31 => 31
4962 14:44:25.139049 Write leveling (Byte 1): 28 => 28
4963 14:44:25.142331 DramcWriteLeveling(PI) end<-----
4964 14:44:25.142412
4965 14:44:25.142476 ==
4966 14:44:25.145889 Dram Type= 6, Freq= 0, CH_0, rank 0
4967 14:44:25.149060 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4968 14:44:25.149142 ==
4969 14:44:25.152269 [Gating] SW mode calibration
4970 14:44:25.159201 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4971 14:44:25.162362 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4972 14:44:25.169114 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4973 14:44:25.172329 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4974 14:44:25.175675 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4975 14:44:25.182310 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4976 14:44:25.185533 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4977 14:44:25.188754 0 10 20 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
4978 14:44:25.195478 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4979 14:44:25.198893 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4980 14:44:25.202083 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4981 14:44:25.208600 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4982 14:44:25.211901 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4983 14:44:25.215616 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4984 14:44:25.222024 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4985 14:44:25.225244 0 11 20 | B1->B0 | 2323 2e2e | 1 0 | (0 0) (0 0)
4986 14:44:25.228774 0 11 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
4987 14:44:25.235267 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4988 14:44:25.238372 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4989 14:44:25.241620 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4990 14:44:25.248369 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4991 14:44:25.251692 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4992 14:44:25.255184 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4993 14:44:25.261641 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4994 14:44:25.264865 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4995 14:44:25.268116 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4996 14:44:25.275073 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4997 14:44:25.278239 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4998 14:44:25.282019 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4999 14:44:25.288146 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5000 14:44:25.291160 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5001 14:44:25.294881 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5002 14:44:25.301084 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5003 14:44:25.304434 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5004 14:44:25.307880 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5005 14:44:25.314471 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5006 14:44:25.317771 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5007 14:44:25.321085 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5008 14:44:25.327684 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5009 14:44:25.331120 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5010 14:44:25.334264 Total UI for P1: 0, mck2ui 16
5011 14:44:25.337480 best dqsien dly found for B1: ( 0, 14, 18)
5012 14:44:25.340687 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5013 14:44:25.344162 Total UI for P1: 0, mck2ui 16
5014 14:44:25.347555 best dqsien dly found for B0: ( 0, 14, 20)
5015 14:44:25.350746 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5016 14:44:25.353985 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5017 14:44:25.354069
5018 14:44:25.360896 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5019 14:44:25.364457 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5020 14:44:25.364541 [Gating] SW calibration Done
5021 14:44:25.367467 ==
5022 14:44:25.370712 Dram Type= 6, Freq= 0, CH_0, rank 0
5023 14:44:25.373967 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5024 14:44:25.374049 ==
5025 14:44:25.374113 RX Vref Scan: 0
5026 14:44:25.374173
5027 14:44:25.377458 RX Vref 0 -> 0, step: 1
5028 14:44:25.377540
5029 14:44:25.380691 RX Delay -80 -> 252, step: 8
5030 14:44:25.384095 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5031 14:44:25.387107 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5032 14:44:25.393635 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5033 14:44:25.396926 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5034 14:44:25.400424 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5035 14:44:25.403557 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5036 14:44:25.406932 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5037 14:44:25.410047 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5038 14:44:25.416872 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5039 14:44:25.420186 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5040 14:44:25.423336 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5041 14:44:25.426862 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5042 14:44:25.430102 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5043 14:44:25.436516 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5044 14:44:25.439979 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5045 14:44:25.443255 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5046 14:44:25.443337 ==
5047 14:44:25.446838 Dram Type= 6, Freq= 0, CH_0, rank 0
5048 14:44:25.449856 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5049 14:44:25.449938 ==
5050 14:44:25.453115 DQS Delay:
5051 14:44:25.453195 DQS0 = 0, DQS1 = 0
5052 14:44:25.456271 DQM Delay:
5053 14:44:25.456352 DQM0 = 95, DQM1 = 85
5054 14:44:25.456417 DQ Delay:
5055 14:44:25.459863 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5056 14:44:25.463026 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5057 14:44:25.466279 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =83
5058 14:44:25.469521 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5059 14:44:25.469601
5060 14:44:25.469664
5061 14:44:25.472979 ==
5062 14:44:25.476174 Dram Type= 6, Freq= 0, CH_0, rank 0
5063 14:44:25.479816 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5064 14:44:25.479897 ==
5065 14:44:25.479960
5066 14:44:25.480019
5067 14:44:25.482993 TX Vref Scan disable
5068 14:44:25.483073 == TX Byte 0 ==
5069 14:44:25.486175 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5070 14:44:25.492755 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5071 14:44:25.492836 == TX Byte 1 ==
5072 14:44:25.499631 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5073 14:44:25.502929 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5074 14:44:25.503010 ==
5075 14:44:25.506044 Dram Type= 6, Freq= 0, CH_0, rank 0
5076 14:44:25.509278 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5077 14:44:25.509369 ==
5078 14:44:25.509432
5079 14:44:25.509490
5080 14:44:25.512982 TX Vref Scan disable
5081 14:44:25.515857 == TX Byte 0 ==
5082 14:44:25.519080 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5083 14:44:25.522630 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5084 14:44:25.525810 == TX Byte 1 ==
5085 14:44:25.529084 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5086 14:44:25.532690 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5087 14:44:25.532771
5088 14:44:25.535857 [DATLAT]
5089 14:44:25.535937 Freq=933, CH0 RK0
5090 14:44:25.536001
5091 14:44:25.539000 DATLAT Default: 0xd
5092 14:44:25.539080 0, 0xFFFF, sum = 0
5093 14:44:25.542561 1, 0xFFFF, sum = 0
5094 14:44:25.542644 2, 0xFFFF, sum = 0
5095 14:44:25.545781 3, 0xFFFF, sum = 0
5096 14:44:25.545864 4, 0xFFFF, sum = 0
5097 14:44:25.549111 5, 0xFFFF, sum = 0
5098 14:44:25.549193 6, 0xFFFF, sum = 0
5099 14:44:25.552574 7, 0xFFFF, sum = 0
5100 14:44:25.552656 8, 0xFFFF, sum = 0
5101 14:44:25.555445 9, 0xFFFF, sum = 0
5102 14:44:25.555528 10, 0x0, sum = 1
5103 14:44:25.558745 11, 0x0, sum = 2
5104 14:44:25.558828 12, 0x0, sum = 3
5105 14:44:25.562111 13, 0x0, sum = 4
5106 14:44:25.562194 best_step = 11
5107 14:44:25.562258
5108 14:44:25.562317 ==
5109 14:44:25.565406 Dram Type= 6, Freq= 0, CH_0, rank 0
5110 14:44:25.572034 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5111 14:44:25.572123 ==
5112 14:44:25.572188 RX Vref Scan: 1
5113 14:44:25.572248
5114 14:44:25.575561 RX Vref 0 -> 0, step: 1
5115 14:44:25.575644
5116 14:44:25.578991 RX Delay -69 -> 252, step: 4
5117 14:44:25.579074
5118 14:44:25.582125 Set Vref, RX VrefLevel [Byte0]: 47
5119 14:44:25.585134 [Byte1]: 49
5120 14:44:25.585218
5121 14:44:25.588639 Final RX Vref Byte 0 = 47 to rank0
5122 14:44:25.591853 Final RX Vref Byte 1 = 49 to rank0
5123 14:44:25.595107 Final RX Vref Byte 0 = 47 to rank1
5124 14:44:25.598727 Final RX Vref Byte 1 = 49 to rank1==
5125 14:44:25.601736 Dram Type= 6, Freq= 0, CH_0, rank 0
5126 14:44:25.605242 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5127 14:44:25.605372 ==
5128 14:44:25.608376 DQS Delay:
5129 14:44:25.608464 DQS0 = 0, DQS1 = 0
5130 14:44:25.611790 DQM Delay:
5131 14:44:25.611875 DQM0 = 97, DQM1 = 87
5132 14:44:25.611940 DQ Delay:
5133 14:44:25.615418 DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =94
5134 14:44:25.618224 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =102
5135 14:44:25.621657 DQ8 =78, DQ9 =70, DQ10 =88, DQ11 =78
5136 14:44:25.624773 DQ12 =96, DQ13 =92, DQ14 =100, DQ15 =98
5137 14:44:25.624862
5138 14:44:25.628075
5139 14:44:25.634752 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5140 14:44:25.638257 CH0 RK0: MR19=505, MR18=1F1F
5141 14:44:25.644658 CH0_RK0: MR19=0x505, MR18=0x1F1F, DQSOSC=412, MR23=63, INC=63, DEC=42
5142 14:44:25.644750
5143 14:44:25.648083 ----->DramcWriteLeveling(PI) begin...
5144 14:44:25.648167 ==
5145 14:44:25.651514 Dram Type= 6, Freq= 0, CH_0, rank 1
5146 14:44:25.654526 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5147 14:44:25.654612 ==
5148 14:44:25.658367 Write leveling (Byte 0): 26 => 26
5149 14:44:25.661282 Write leveling (Byte 1): 24 => 24
5150 14:44:25.664464 DramcWriteLeveling(PI) end<-----
5151 14:44:25.664547
5152 14:44:25.664611 ==
5153 14:44:25.667850 Dram Type= 6, Freq= 0, CH_0, rank 1
5154 14:44:25.671000 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5155 14:44:25.671109 ==
5156 14:44:25.674317 [Gating] SW mode calibration
5157 14:44:25.681233 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5158 14:44:25.687647 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5159 14:44:25.691117 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5160 14:44:25.694663 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 14:44:25.700753 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 14:44:25.704345 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 14:44:25.707867 0 10 16 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5164 14:44:25.714088 0 10 20 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)
5165 14:44:25.717399 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5166 14:44:25.720584 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 14:44:25.727381 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 14:44:25.730454 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 14:44:25.733972 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 14:44:25.740615 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 14:44:25.743608 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 14:44:25.747032 0 11 20 | B1->B0 | 3030 3939 | 0 0 | (0 0) (0 0)
5173 14:44:25.753980 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 14:44:25.757076 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 14:44:25.760376 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 14:44:25.767102 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 14:44:25.770359 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 14:44:25.773692 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 14:44:25.780288 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 14:44:25.783466 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5181 14:44:25.786763 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5182 14:44:25.793412 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 14:44:25.796901 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 14:44:25.800164 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 14:44:25.806601 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 14:44:25.809900 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 14:44:25.813499 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 14:44:25.819959 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 14:44:25.823164 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 14:44:25.826365 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 14:44:25.832948 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 14:44:25.836636 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 14:44:25.839730 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 14:44:25.846592 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 14:44:25.849522 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 14:44:25.852876 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5197 14:44:25.859414 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5198 14:44:25.859496 Total UI for P1: 0, mck2ui 16
5199 14:44:25.866030 best dqsien dly found for B0: ( 0, 14, 20)
5200 14:44:25.869595 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 14:44:25.872986 Total UI for P1: 0, mck2ui 16
5202 14:44:25.876203 best dqsien dly found for B1: ( 0, 14, 22)
5203 14:44:25.879446 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5204 14:44:25.882599 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5205 14:44:25.882681
5206 14:44:25.885829 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5207 14:44:25.892749 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5208 14:44:25.892830 [Gating] SW calibration Done
5209 14:44:25.892894 ==
5210 14:44:25.895914 Dram Type= 6, Freq= 0, CH_0, rank 1
5211 14:44:25.902333 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5212 14:44:25.902415 ==
5213 14:44:25.902479 RX Vref Scan: 0
5214 14:44:25.902539
5215 14:44:25.905574 RX Vref 0 -> 0, step: 1
5216 14:44:25.905654
5217 14:44:25.909210 RX Delay -80 -> 252, step: 8
5218 14:44:25.912083 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5219 14:44:25.915742 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5220 14:44:25.918743 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5221 14:44:25.922117 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5222 14:44:25.928763 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5223 14:44:25.931984 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5224 14:44:25.935195 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5225 14:44:25.938547 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5226 14:44:25.941792 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5227 14:44:25.945231 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5228 14:44:25.952105 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5229 14:44:25.955357 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5230 14:44:25.958480 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5231 14:44:25.961907 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5232 14:44:25.968340 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5233 14:44:25.971512 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5234 14:44:25.971593 ==
5235 14:44:25.975189 Dram Type= 6, Freq= 0, CH_0, rank 1
5236 14:44:25.978254 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5237 14:44:25.978336 ==
5238 14:44:25.978400 DQS Delay:
5239 14:44:25.981391 DQS0 = 0, DQS1 = 0
5240 14:44:25.981472 DQM Delay:
5241 14:44:25.984779 DQM0 = 96, DQM1 = 84
5242 14:44:25.984859 DQ Delay:
5243 14:44:25.988229 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =87
5244 14:44:25.991635 DQ4 =99, DQ5 =91, DQ6 =103, DQ7 =107
5245 14:44:25.994796 DQ8 =71, DQ9 =71, DQ10 =87, DQ11 =79
5246 14:44:25.998250 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5247 14:44:25.998573
5248 14:44:25.998825
5249 14:44:25.999058 ==
5250 14:44:26.001732 Dram Type= 6, Freq= 0, CH_0, rank 1
5251 14:44:26.008316 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5252 14:44:26.008644 ==
5253 14:44:26.008898
5254 14:44:26.009131
5255 14:44:26.009397 TX Vref Scan disable
5256 14:44:26.011366 == TX Byte 0 ==
5257 14:44:26.014932 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5258 14:44:26.018099 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5259 14:44:26.021790 == TX Byte 1 ==
5260 14:44:26.024813 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5261 14:44:26.031458 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5262 14:44:26.031647 ==
5263 14:44:26.034610 Dram Type= 6, Freq= 0, CH_0, rank 1
5264 14:44:26.037979 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5265 14:44:26.038171 ==
5266 14:44:26.038330
5267 14:44:26.038468
5268 14:44:26.041278 TX Vref Scan disable
5269 14:44:26.041485 == TX Byte 0 ==
5270 14:44:26.048010 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5271 14:44:26.050973 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5272 14:44:26.051107 == TX Byte 1 ==
5273 14:44:26.057731 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5274 14:44:26.060928 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5275 14:44:26.061032
5276 14:44:26.061112 [DATLAT]
5277 14:44:26.064400 Freq=933, CH0 RK1
5278 14:44:26.064503
5279 14:44:26.064584 DATLAT Default: 0xb
5280 14:44:26.067596 0, 0xFFFF, sum = 0
5281 14:44:26.067691 1, 0xFFFF, sum = 0
5282 14:44:26.071035 2, 0xFFFF, sum = 0
5283 14:44:26.074273 3, 0xFFFF, sum = 0
5284 14:44:26.074358 4, 0xFFFF, sum = 0
5285 14:44:26.077592 5, 0xFFFF, sum = 0
5286 14:44:26.077674 6, 0xFFFF, sum = 0
5287 14:44:26.080564 7, 0xFFFF, sum = 0
5288 14:44:26.080645 8, 0xFFFF, sum = 0
5289 14:44:26.083910 9, 0xFFFF, sum = 0
5290 14:44:26.083992 10, 0x0, sum = 1
5291 14:44:26.087239 11, 0x0, sum = 2
5292 14:44:26.087321 12, 0x0, sum = 3
5293 14:44:26.090489 13, 0x0, sum = 4
5294 14:44:26.090571 best_step = 11
5295 14:44:26.090635
5296 14:44:26.090693 ==
5297 14:44:26.093883 Dram Type= 6, Freq= 0, CH_0, rank 1
5298 14:44:26.097171 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5299 14:44:26.097251 ==
5300 14:44:26.100604 RX Vref Scan: 0
5301 14:44:26.100684
5302 14:44:26.103824 RX Vref 0 -> 0, step: 1
5303 14:44:26.103904
5304 14:44:26.103966 RX Delay -69 -> 252, step: 4
5305 14:44:26.111734 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5306 14:44:26.114937 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5307 14:44:26.118425 iDelay=199, Bit 2, Center 96 (7 ~ 186) 180
5308 14:44:26.121666 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5309 14:44:26.125124 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5310 14:44:26.128475 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5311 14:44:26.135119 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5312 14:44:26.138258 iDelay=199, Bit 7, Center 108 (19 ~ 198) 180
5313 14:44:26.141757 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5314 14:44:26.144944 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5315 14:44:26.148331 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5316 14:44:26.155029 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5317 14:44:26.158103 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5318 14:44:26.161391 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5319 14:44:26.164869 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5320 14:44:26.168130 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5321 14:44:26.168211 ==
5322 14:44:26.171556 Dram Type= 6, Freq= 0, CH_0, rank 1
5323 14:44:26.178057 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5324 14:44:26.178138 ==
5325 14:44:26.178201 DQS Delay:
5326 14:44:26.181388 DQS0 = 0, DQS1 = 0
5327 14:44:26.181471 DQM Delay:
5328 14:44:26.181535 DQM0 = 97, DQM1 = 86
5329 14:44:26.184744 DQ Delay:
5330 14:44:26.188002 DQ0 =94, DQ1 =98, DQ2 =96, DQ3 =92
5331 14:44:26.191329 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =108
5332 14:44:26.194551 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5333 14:44:26.198012 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =96
5334 14:44:26.198092
5335 14:44:26.198155
5336 14:44:26.204448 [DQSOSCAuto] RK1, (LSB)MR18= 0x2929, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5337 14:44:26.207760 CH0 RK1: MR19=505, MR18=2929
5338 14:44:26.214296 CH0_RK1: MR19=0x505, MR18=0x2929, DQSOSC=408, MR23=63, INC=65, DEC=43
5339 14:44:26.217706 [RxdqsGatingPostProcess] freq 933
5340 14:44:26.221167 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5341 14:44:26.224091 Pre-setting of DQS Precalculation
5342 14:44:26.230780 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5343 14:44:26.230861 ==
5344 14:44:26.234123 Dram Type= 6, Freq= 0, CH_1, rank 0
5345 14:44:26.237562 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5346 14:44:26.237643 ==
5347 14:44:26.244198 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5348 14:44:26.250725 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5349 14:44:26.254810 [CA 0] Center 37 (6~68) winsize 63
5350 14:44:26.257819 [CA 1] Center 37 (6~68) winsize 63
5351 14:44:26.260883 [CA 2] Center 34 (4~65) winsize 62
5352 14:44:26.264082 [CA 3] Center 34 (4~65) winsize 62
5353 14:44:26.267428 [CA 4] Center 33 (2~64) winsize 63
5354 14:44:26.270704 [CA 5] Center 33 (2~64) winsize 63
5355 14:44:26.270785
5356 14:44:26.274169 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5357 14:44:26.274250
5358 14:44:26.277199 [CATrainingPosCal] consider 1 rank data
5359 14:44:26.280428 u2DelayCellTimex100 = 270/100 ps
5360 14:44:26.284104 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5361 14:44:26.287114 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5362 14:44:26.290651 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5363 14:44:26.293887 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5364 14:44:26.297215 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5365 14:44:26.300453 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5366 14:44:26.300532
5367 14:44:26.307034 CA PerBit enable=1, Macro0, CA PI delay=33
5368 14:44:26.307140
5369 14:44:26.310397 [CBTSetCACLKResult] CA Dly = 33
5370 14:44:26.310478 CS Dly: 5 (0~36)
5371 14:44:26.310542 ==
5372 14:44:26.313692 Dram Type= 6, Freq= 0, CH_1, rank 1
5373 14:44:26.316846 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5374 14:44:26.316952 ==
5375 14:44:26.323481 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5376 14:44:26.330056 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5377 14:44:26.333652 [CA 0] Center 37 (6~68) winsize 63
5378 14:44:26.337135 [CA 1] Center 37 (6~68) winsize 63
5379 14:44:26.340061 [CA 2] Center 34 (4~65) winsize 62
5380 14:44:26.343421 [CA 3] Center 34 (4~64) winsize 61
5381 14:44:26.346755 [CA 4] Center 33 (2~64) winsize 63
5382 14:44:26.350044 [CA 5] Center 32 (2~63) winsize 62
5383 14:44:26.350124
5384 14:44:26.353445 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5385 14:44:26.353525
5386 14:44:26.356574 [CATrainingPosCal] consider 2 rank data
5387 14:44:26.360078 u2DelayCellTimex100 = 270/100 ps
5388 14:44:26.363477 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5389 14:44:26.366723 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5390 14:44:26.370093 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5391 14:44:26.373357 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5392 14:44:26.379957 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5393 14:44:26.383305 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5394 14:44:26.383385
5395 14:44:26.386541 CA PerBit enable=1, Macro0, CA PI delay=32
5396 14:44:26.386621
5397 14:44:26.389664 [CBTSetCACLKResult] CA Dly = 32
5398 14:44:26.389744 CS Dly: 5 (0~37)
5399 14:44:26.389807
5400 14:44:26.393111 ----->DramcWriteLeveling(PI) begin...
5401 14:44:26.393192 ==
5402 14:44:26.396434 Dram Type= 6, Freq= 0, CH_1, rank 0
5403 14:44:26.403083 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5404 14:44:26.403164 ==
5405 14:44:26.406205 Write leveling (Byte 0): 28 => 28
5406 14:44:26.409505 Write leveling (Byte 1): 27 => 27
5407 14:44:26.409587 DramcWriteLeveling(PI) end<-----
5408 14:44:26.409649
5409 14:44:26.412694 ==
5410 14:44:26.416106 Dram Type= 6, Freq= 0, CH_1, rank 0
5411 14:44:26.419485 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5412 14:44:26.419594 ==
5413 14:44:26.422945 [Gating] SW mode calibration
5414 14:44:26.429222 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5415 14:44:26.432585 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5416 14:44:26.439207 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5417 14:44:26.442595 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5418 14:44:26.445783 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5419 14:44:26.452548 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5420 14:44:26.455933 0 10 16 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5421 14:44:26.459057 0 10 20 | B1->B0 | 3434 2424 | 0 0 | (0 0) (0 0)
5422 14:44:26.465741 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5423 14:44:26.469037 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5424 14:44:26.472400 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5425 14:44:26.479374 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5426 14:44:26.483034 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5427 14:44:26.485736 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5428 14:44:26.492497 0 11 16 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5429 14:44:26.495842 0 11 20 | B1->B0 | 2828 4545 | 0 0 | (0 0) (0 0)
5430 14:44:26.499220 0 11 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5431 14:44:26.505609 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5432 14:44:26.508662 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5433 14:44:26.512124 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5434 14:44:26.518739 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5435 14:44:26.522004 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5436 14:44:26.525150 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5437 14:44:26.532157 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5438 14:44:26.535211 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 14:44:26.538448 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 14:44:26.545259 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 14:44:26.548522 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 14:44:26.551666 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 14:44:26.558289 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 14:44:26.561817 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5445 14:44:26.564933 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 14:44:26.571607 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 14:44:26.574768 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 14:44:26.578159 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 14:44:26.584633 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 14:44:26.588222 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 14:44:26.591431 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 14:44:26.598393 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5453 14:44:26.601481 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5454 14:44:26.604697 Total UI for P1: 0, mck2ui 16
5455 14:44:26.608059 best dqsien dly found for B0: ( 0, 14, 18)
5456 14:44:26.611515 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5457 14:44:26.614609 Total UI for P1: 0, mck2ui 16
5458 14:44:26.618207 best dqsien dly found for B1: ( 0, 14, 20)
5459 14:44:26.621426 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5460 14:44:26.624897 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5461 14:44:26.624978
5462 14:44:26.628181 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5463 14:44:26.634672 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5464 14:44:26.634753 [Gating] SW calibration Done
5465 14:44:26.634816 ==
5466 14:44:26.638353 Dram Type= 6, Freq= 0, CH_1, rank 0
5467 14:44:26.645098 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5468 14:44:26.645179 ==
5469 14:44:26.645242 RX Vref Scan: 0
5470 14:44:26.645307
5471 14:44:26.648027 RX Vref 0 -> 0, step: 1
5472 14:44:26.648107
5473 14:44:26.651673 RX Delay -80 -> 252, step: 8
5474 14:44:26.654657 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5475 14:44:26.658108 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5476 14:44:26.661245 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5477 14:44:26.664615 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5478 14:44:26.671312 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5479 14:44:26.674438 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5480 14:44:26.677855 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5481 14:44:26.681107 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5482 14:44:26.684722 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5483 14:44:26.691178 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5484 14:44:26.694293 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5485 14:44:26.697510 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5486 14:44:26.700724 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5487 14:44:26.704028 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5488 14:44:26.711039 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5489 14:44:26.714505 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5490 14:44:26.714585 ==
5491 14:44:26.717269 Dram Type= 6, Freq= 0, CH_1, rank 0
5492 14:44:26.720856 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5493 14:44:26.720935 ==
5494 14:44:26.720997 DQS Delay:
5495 14:44:26.724242 DQS0 = 0, DQS1 = 0
5496 14:44:26.724321 DQM Delay:
5497 14:44:26.727399 DQM0 = 94, DQM1 = 87
5498 14:44:26.727477 DQ Delay:
5499 14:44:26.730694 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5500 14:44:26.733921 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5501 14:44:26.737273 DQ8 =71, DQ9 =79, DQ10 =91, DQ11 =79
5502 14:44:26.740910 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =95
5503 14:44:26.740988
5504 14:44:26.741050
5505 14:44:26.741108 ==
5506 14:44:26.743793 Dram Type= 6, Freq= 0, CH_1, rank 0
5507 14:44:26.750500 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5508 14:44:26.750579 ==
5509 14:44:26.750641
5510 14:44:26.750699
5511 14:44:26.750755 TX Vref Scan disable
5512 14:44:26.754017 == TX Byte 0 ==
5513 14:44:26.757152 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5514 14:44:26.763679 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5515 14:44:26.763759 == TX Byte 1 ==
5516 14:44:26.766999 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5517 14:44:26.773576 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5518 14:44:26.773657 ==
5519 14:44:26.776944 Dram Type= 6, Freq= 0, CH_1, rank 0
5520 14:44:26.780040 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5521 14:44:26.780122 ==
5522 14:44:26.780185
5523 14:44:26.780243
5524 14:44:26.783394 TX Vref Scan disable
5525 14:44:26.786652 == TX Byte 0 ==
5526 14:44:26.790136 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5527 14:44:26.793249 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5528 14:44:26.796652 == TX Byte 1 ==
5529 14:44:26.800251 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5530 14:44:26.803537 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5531 14:44:26.803617
5532 14:44:26.803680 [DATLAT]
5533 14:44:26.806674 Freq=933, CH1 RK0
5534 14:44:26.806755
5535 14:44:26.806818 DATLAT Default: 0xd
5536 14:44:26.810010 0, 0xFFFF, sum = 0
5537 14:44:26.813107 1, 0xFFFF, sum = 0
5538 14:44:26.813189 2, 0xFFFF, sum = 0
5539 14:44:26.816378 3, 0xFFFF, sum = 0
5540 14:44:26.816487 4, 0xFFFF, sum = 0
5541 14:44:26.819617 5, 0xFFFF, sum = 0
5542 14:44:26.819700 6, 0xFFFF, sum = 0
5543 14:44:26.823021 7, 0xFFFF, sum = 0
5544 14:44:26.823102 8, 0xFFFF, sum = 0
5545 14:44:26.826513 9, 0xFFFF, sum = 0
5546 14:44:26.826622 10, 0x0, sum = 1
5547 14:44:26.829786 11, 0x0, sum = 2
5548 14:44:26.829868 12, 0x0, sum = 3
5549 14:44:26.832858 13, 0x0, sum = 4
5550 14:44:26.832939 best_step = 11
5551 14:44:26.833002
5552 14:44:26.833060 ==
5553 14:44:26.836195 Dram Type= 6, Freq= 0, CH_1, rank 0
5554 14:44:26.839561 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5555 14:44:26.839647 ==
5556 14:44:26.843055 RX Vref Scan: 1
5557 14:44:26.843139
5558 14:44:26.846102 RX Vref 0 -> 0, step: 1
5559 14:44:26.846199
5560 14:44:26.846288 RX Delay -69 -> 252, step: 4
5561 14:44:26.849561
5562 14:44:26.849641 Set Vref, RX VrefLevel [Byte0]: 53
5563 14:44:26.852987 [Byte1]: 49
5564 14:44:26.857873
5565 14:44:26.857953 Final RX Vref Byte 0 = 53 to rank0
5566 14:44:26.860980 Final RX Vref Byte 1 = 49 to rank0
5567 14:44:26.864611 Final RX Vref Byte 0 = 53 to rank1
5568 14:44:26.867671 Final RX Vref Byte 1 = 49 to rank1==
5569 14:44:26.871058 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 14:44:26.877768 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5571 14:44:26.877849 ==
5572 14:44:26.877912 DQS Delay:
5573 14:44:26.877972 DQS0 = 0, DQS1 = 0
5574 14:44:26.881050 DQM Delay:
5575 14:44:26.881130 DQM0 = 94, DQM1 = 88
5576 14:44:26.884518 DQ Delay:
5577 14:44:26.887597 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =90
5578 14:44:26.891140 DQ4 =94, DQ5 =104, DQ6 =102, DQ7 =92
5579 14:44:26.894218 DQ8 =70, DQ9 =76, DQ10 =92, DQ11 =80
5580 14:44:26.897580 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5581 14:44:26.897688
5582 14:44:26.897781
5583 14:44:26.903959 [DQSOSCAuto] RK0, (LSB)MR18= 0x3636, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5584 14:44:26.907402 CH1 RK0: MR19=505, MR18=3636
5585 14:44:26.913775 CH1_RK0: MR19=0x505, MR18=0x3636, DQSOSC=404, MR23=63, INC=66, DEC=44
5586 14:44:26.913857
5587 14:44:26.917223 ----->DramcWriteLeveling(PI) begin...
5588 14:44:26.917344 ==
5589 14:44:26.920627 Dram Type= 6, Freq= 0, CH_1, rank 1
5590 14:44:26.923986 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5591 14:44:26.924068 ==
5592 14:44:26.927217 Write leveling (Byte 0): 23 => 23
5593 14:44:26.930454 Write leveling (Byte 1): 21 => 21
5594 14:44:26.933990 DramcWriteLeveling(PI) end<-----
5595 14:44:26.934071
5596 14:44:26.934133 ==
5597 14:44:26.937007 Dram Type= 6, Freq= 0, CH_1, rank 1
5598 14:44:26.940498 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5599 14:44:26.943654 ==
5600 14:44:26.943735 [Gating] SW mode calibration
5601 14:44:26.950204 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5602 14:44:26.956886 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5603 14:44:26.960277 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 14:44:26.966895 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 14:44:26.970249 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5606 14:44:26.973746 0 10 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5607 14:44:26.980065 0 10 16 | B1->B0 | 3434 2828 | 1 0 | (1 0) (1 0)
5608 14:44:26.983338 0 10 20 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
5609 14:44:26.986902 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 14:44:26.993306 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 14:44:26.996802 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 14:44:27.000083 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 14:44:27.006649 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5614 14:44:27.009860 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5615 14:44:27.013153 0 11 16 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
5616 14:44:27.019643 0 11 20 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5617 14:44:27.023239 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 14:44:27.026426 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 14:44:27.033274 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 14:44:27.036409 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 14:44:27.039926 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 14:44:27.046207 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 14:44:27.049739 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5624 14:44:27.052967 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5625 14:44:27.059494 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 14:44:27.062768 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 14:44:27.066085 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 14:44:27.072910 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 14:44:27.076054 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 14:44:27.079415 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 14:44:27.086092 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 14:44:27.089295 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 14:44:27.092680 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 14:44:27.096097 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 14:44:27.102797 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 14:44:27.105833 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 14:44:27.109486 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 14:44:27.115852 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 14:44:27.119238 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5640 14:44:27.122359 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5641 14:44:27.128947 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 14:44:27.132211 Total UI for P1: 0, mck2ui 16
5643 14:44:27.135620 best dqsien dly found for B0: ( 0, 14, 18)
5644 14:44:27.138979 Total UI for P1: 0, mck2ui 16
5645 14:44:27.142222 best dqsien dly found for B1: ( 0, 14, 18)
5646 14:44:27.145863 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5647 14:44:27.148913 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5648 14:44:27.148992
5649 14:44:27.152306 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5650 14:44:27.155643 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5651 14:44:27.158816 [Gating] SW calibration Done
5652 14:44:27.158895 ==
5653 14:44:27.162029 Dram Type= 6, Freq= 0, CH_1, rank 1
5654 14:44:27.165340 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5655 14:44:27.165420 ==
5656 14:44:27.168723 RX Vref Scan: 0
5657 14:44:27.168802
5658 14:44:27.171986 RX Vref 0 -> 0, step: 1
5659 14:44:27.172065
5660 14:44:27.172126 RX Delay -80 -> 252, step: 8
5661 14:44:27.178654 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5662 14:44:27.182111 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5663 14:44:27.185473 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5664 14:44:27.188619 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5665 14:44:27.191891 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5666 14:44:27.195380 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5667 14:44:27.201688 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5668 14:44:27.205070 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5669 14:44:27.208378 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5670 14:44:27.211746 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5671 14:44:27.214867 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5672 14:44:27.221525 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5673 14:44:27.224878 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5674 14:44:27.228046 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5675 14:44:27.231432 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5676 14:44:27.234805 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5677 14:44:27.234884 ==
5678 14:44:27.238000 Dram Type= 6, Freq= 0, CH_1, rank 1
5679 14:44:27.244799 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5680 14:44:27.244879 ==
5681 14:44:27.244941 DQS Delay:
5682 14:44:27.248180 DQS0 = 0, DQS1 = 0
5683 14:44:27.248259 DQM Delay:
5684 14:44:27.248321 DQM0 = 99, DQM1 = 91
5685 14:44:27.251416 DQ Delay:
5686 14:44:27.254762 DQ0 =99, DQ1 =95, DQ2 =91, DQ3 =95
5687 14:44:27.257924 DQ4 =99, DQ5 =111, DQ6 =107, DQ7 =95
5688 14:44:27.261200 DQ8 =75, DQ9 =79, DQ10 =95, DQ11 =83
5689 14:44:27.264519 DQ12 =99, DQ13 =103, DQ14 =95, DQ15 =99
5690 14:44:27.264598
5691 14:44:27.264659
5692 14:44:27.264717 ==
5693 14:44:27.267784 Dram Type= 6, Freq= 0, CH_1, rank 1
5694 14:44:27.271159 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5695 14:44:27.271239 ==
5696 14:44:27.271301
5697 14:44:27.271358
5698 14:44:27.274512 TX Vref Scan disable
5699 14:44:27.277818 == TX Byte 0 ==
5700 14:44:27.281185 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5701 14:44:27.284717 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5702 14:44:27.287848 == TX Byte 1 ==
5703 14:44:27.291007 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5704 14:44:27.294409 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5705 14:44:27.294488 ==
5706 14:44:27.297578 Dram Type= 6, Freq= 0, CH_1, rank 1
5707 14:44:27.301016 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5708 14:44:27.304238 ==
5709 14:44:27.304316
5710 14:44:27.304378
5711 14:44:27.304436 TX Vref Scan disable
5712 14:44:27.307770 == TX Byte 0 ==
5713 14:44:27.311241 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5714 14:44:27.317788 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5715 14:44:27.317868 == TX Byte 1 ==
5716 14:44:27.321044 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5717 14:44:27.327616 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5718 14:44:27.327695
5719 14:44:27.327757 [DATLAT]
5720 14:44:27.327815 Freq=933, CH1 RK1
5721 14:44:27.327872
5722 14:44:27.330984 DATLAT Default: 0xb
5723 14:44:27.331062 0, 0xFFFF, sum = 0
5724 14:44:27.334615 1, 0xFFFF, sum = 0
5725 14:44:27.337662 2, 0xFFFF, sum = 0
5726 14:44:27.337742 3, 0xFFFF, sum = 0
5727 14:44:27.341084 4, 0xFFFF, sum = 0
5728 14:44:27.341164 5, 0xFFFF, sum = 0
5729 14:44:27.344470 6, 0xFFFF, sum = 0
5730 14:44:27.344550 7, 0xFFFF, sum = 0
5731 14:44:27.347692 8, 0xFFFF, sum = 0
5732 14:44:27.347772 9, 0xFFFF, sum = 0
5733 14:44:27.350838 10, 0x0, sum = 1
5734 14:44:27.350919 11, 0x0, sum = 2
5735 14:44:27.354174 12, 0x0, sum = 3
5736 14:44:27.354296 13, 0x0, sum = 4
5737 14:44:27.354360 best_step = 11
5738 14:44:27.354417
5739 14:44:27.357599 ==
5740 14:44:27.360900 Dram Type= 6, Freq= 0, CH_1, rank 1
5741 14:44:27.364189 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5742 14:44:27.364305 ==
5743 14:44:27.364367 RX Vref Scan: 0
5744 14:44:27.364425
5745 14:44:27.367698 RX Vref 0 -> 0, step: 1
5746 14:44:27.367777
5747 14:44:27.371057 RX Delay -69 -> 252, step: 4
5748 14:44:27.374262 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5749 14:44:27.381018 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188
5750 14:44:27.384272 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5751 14:44:27.387615 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5752 14:44:27.390869 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5753 14:44:27.394222 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5754 14:44:27.397569 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5755 14:44:27.404071 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5756 14:44:27.407380 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5757 14:44:27.410489 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5758 14:44:27.413826 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5759 14:44:27.417177 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5760 14:44:27.423888 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5761 14:44:27.427220 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5762 14:44:27.430397 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5763 14:44:27.433691 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5764 14:44:27.433770 ==
5765 14:44:27.437032 Dram Type= 6, Freq= 0, CH_1, rank 1
5766 14:44:27.440390 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5767 14:44:27.443534 ==
5768 14:44:27.443613 DQS Delay:
5769 14:44:27.443675 DQS0 = 0, DQS1 = 0
5770 14:44:27.447421 DQM Delay:
5771 14:44:27.447500 DQM0 = 96, DQM1 = 87
5772 14:44:27.450372 DQ Delay:
5773 14:44:27.453739 DQ0 =98, DQ1 =92, DQ2 =88, DQ3 =92
5774 14:44:27.456861 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5775 14:44:27.460036 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5776 14:44:27.463669 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5777 14:44:27.463748
5778 14:44:27.463810
5779 14:44:27.470085 [DQSOSCAuto] RK1, (LSB)MR18= 0x2929, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5780 14:44:27.473482 CH1 RK1: MR19=505, MR18=2929
5781 14:44:27.480173 CH1_RK1: MR19=0x505, MR18=0x2929, DQSOSC=408, MR23=63, INC=65, DEC=43
5782 14:44:27.483706 [RxdqsGatingPostProcess] freq 933
5783 14:44:27.486757 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5784 14:44:27.489975 Pre-setting of DQS Precalculation
5785 14:44:27.496770 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5786 14:44:27.503076 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5787 14:44:27.510044 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5788 14:44:27.510148
5789 14:44:27.510250
5790 14:44:27.513130 [Calibration Summary] 1866 Mbps
5791 14:44:27.513209 CH 0, Rank 0
5792 14:44:27.516642 SW Impedance : PASS
5793 14:44:27.519865 DUTY Scan : NO K
5794 14:44:27.519944 ZQ Calibration : PASS
5795 14:44:27.522988 Jitter Meter : NO K
5796 14:44:27.526555 CBT Training : PASS
5797 14:44:27.526634 Write leveling : PASS
5798 14:44:27.529927 RX DQS gating : PASS
5799 14:44:27.533239 RX DQ/DQS(RDDQC) : PASS
5800 14:44:27.533357 TX DQ/DQS : PASS
5801 14:44:27.536303 RX DATLAT : PASS
5802 14:44:27.539575 RX DQ/DQS(Engine): PASS
5803 14:44:27.539654 TX OE : NO K
5804 14:44:27.543125 All Pass.
5805 14:44:27.543203
5806 14:44:27.543265 CH 0, Rank 1
5807 14:44:27.546252 SW Impedance : PASS
5808 14:44:27.546330 DUTY Scan : NO K
5809 14:44:27.549481 ZQ Calibration : PASS
5810 14:44:27.552969 Jitter Meter : NO K
5811 14:44:27.553048 CBT Training : PASS
5812 14:44:27.556372 Write leveling : PASS
5813 14:44:27.556463 RX DQS gating : PASS
5814 14:44:27.559411 RX DQ/DQS(RDDQC) : PASS
5815 14:44:27.562886 TX DQ/DQS : PASS
5816 14:44:27.562965 RX DATLAT : PASS
5817 14:44:27.566108 RX DQ/DQS(Engine): PASS
5818 14:44:27.569407 TX OE : NO K
5819 14:44:27.569486 All Pass.
5820 14:44:27.569548
5821 14:44:27.569605 CH 1, Rank 0
5822 14:44:27.572954 SW Impedance : PASS
5823 14:44:27.576036 DUTY Scan : NO K
5824 14:44:27.576114 ZQ Calibration : PASS
5825 14:44:27.579384 Jitter Meter : NO K
5826 14:44:27.582776 CBT Training : PASS
5827 14:44:27.582854 Write leveling : PASS
5828 14:44:27.585882 RX DQS gating : PASS
5829 14:44:27.589216 RX DQ/DQS(RDDQC) : PASS
5830 14:44:27.589320 TX DQ/DQS : PASS
5831 14:44:27.592587 RX DATLAT : PASS
5832 14:44:27.595835 RX DQ/DQS(Engine): PASS
5833 14:44:27.595914 TX OE : NO K
5834 14:44:27.599043 All Pass.
5835 14:44:27.599122
5836 14:44:27.599184 CH 1, Rank 1
5837 14:44:27.602311 SW Impedance : PASS
5838 14:44:27.602391 DUTY Scan : NO K
5839 14:44:27.605670 ZQ Calibration : PASS
5840 14:44:27.609007 Jitter Meter : NO K
5841 14:44:27.609086 CBT Training : PASS
5842 14:44:27.612510 Write leveling : PASS
5843 14:44:27.615635 RX DQS gating : PASS
5844 14:44:27.615714 RX DQ/DQS(RDDQC) : PASS
5845 14:44:27.618948 TX DQ/DQS : PASS
5846 14:44:27.622482 RX DATLAT : PASS
5847 14:44:27.622561 RX DQ/DQS(Engine): PASS
5848 14:44:27.625397 TX OE : NO K
5849 14:44:27.625476 All Pass.
5850 14:44:27.625538
5851 14:44:27.628707 DramC Write-DBI off
5852 14:44:27.632056 PER_BANK_REFRESH: Hybrid Mode
5853 14:44:27.632135 TX_TRACKING: ON
5854 14:44:27.642407 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5855 14:44:27.645481 [FAST_K] Save calibration result to emmc
5856 14:44:27.648492 dramc_set_vcore_voltage set vcore to 650000
5857 14:44:27.652093 Read voltage for 400, 6
5858 14:44:27.652172 Vio18 = 0
5859 14:44:27.652234 Vcore = 650000
5860 14:44:27.655442 Vdram = 0
5861 14:44:27.655520 Vddq = 0
5862 14:44:27.655583 Vmddr = 0
5863 14:44:27.661832 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5864 14:44:27.665344 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5865 14:44:27.668363 MEM_TYPE=3, freq_sel=20
5866 14:44:27.671953 sv_algorithm_assistance_LP4_800
5867 14:44:27.675164 ============ PULL DRAM RESETB DOWN ============
5868 14:44:27.678409 ========== PULL DRAM RESETB DOWN end =========
5869 14:44:27.684779 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5870 14:44:27.688234 ===================================
5871 14:44:27.688314 LPDDR4 DRAM CONFIGURATION
5872 14:44:27.691671 ===================================
5873 14:44:27.694790 EX_ROW_EN[0] = 0x0
5874 14:44:27.697710 EX_ROW_EN[1] = 0x0
5875 14:44:27.697791 LP4Y_EN = 0x0
5876 14:44:27.701106 WORK_FSP = 0x0
5877 14:44:27.701186 WL = 0x2
5878 14:44:27.704465 RL = 0x2
5879 14:44:27.704545 BL = 0x2
5880 14:44:27.707692 RPST = 0x0
5881 14:44:27.707772 RD_PRE = 0x0
5882 14:44:27.711020 WR_PRE = 0x1
5883 14:44:27.711101 WR_PST = 0x0
5884 14:44:27.714729 DBI_WR = 0x0
5885 14:44:27.714815 DBI_RD = 0x0
5886 14:44:27.717778 OTF = 0x1
5887 14:44:27.721299 ===================================
5888 14:44:27.724317 ===================================
5889 14:44:27.724398 ANA top config
5890 14:44:27.727658 ===================================
5891 14:44:27.731080 DLL_ASYNC_EN = 0
5892 14:44:27.734110 ALL_SLAVE_EN = 1
5893 14:44:27.737581 NEW_RANK_MODE = 1
5894 14:44:27.737662 DLL_IDLE_MODE = 1
5895 14:44:27.741088 LP45_APHY_COMB_EN = 1
5896 14:44:27.744138 TX_ODT_DIS = 1
5897 14:44:27.747670 NEW_8X_MODE = 1
5898 14:44:27.750651 ===================================
5899 14:44:27.754545 ===================================
5900 14:44:27.757302 data_rate = 800
5901 14:44:27.760896 CKR = 1
5902 14:44:27.760977 DQ_P2S_RATIO = 4
5903 14:44:27.763950 ===================================
5904 14:44:27.767396 CA_P2S_RATIO = 4
5905 14:44:27.770584 DQ_CA_OPEN = 0
5906 14:44:27.774177 DQ_SEMI_OPEN = 1
5907 14:44:27.777456 CA_SEMI_OPEN = 1
5908 14:44:27.780452 CA_FULL_RATE = 0
5909 14:44:27.780531 DQ_CKDIV4_EN = 0
5910 14:44:27.783848 CA_CKDIV4_EN = 1
5911 14:44:27.787166 CA_PREDIV_EN = 0
5912 14:44:27.790272 PH8_DLY = 0
5913 14:44:27.793968 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5914 14:44:27.797136 DQ_AAMCK_DIV = 0
5915 14:44:27.797215 CA_AAMCK_DIV = 0
5916 14:44:27.800277 CA_ADMCK_DIV = 4
5917 14:44:27.803506 DQ_TRACK_CA_EN = 0
5918 14:44:27.807099 CA_PICK = 800
5919 14:44:27.810328 CA_MCKIO = 400
5920 14:44:27.813559 MCKIO_SEMI = 400
5921 14:44:27.816935 PLL_FREQ = 3016
5922 14:44:27.817049 DQ_UI_PI_RATIO = 32
5923 14:44:27.820101 CA_UI_PI_RATIO = 32
5924 14:44:27.823326 ===================================
5925 14:44:27.826912 ===================================
5926 14:44:27.830251 memory_type:LPDDR4
5927 14:44:27.833277 GP_NUM : 10
5928 14:44:27.833413 SRAM_EN : 1
5929 14:44:27.836554 MD32_EN : 0
5930 14:44:27.840017 ===================================
5931 14:44:27.843135 [ANA_INIT] >>>>>>>>>>>>>>
5932 14:44:27.846550 <<<<<< [CONFIGURE PHASE]: ANA_TX
5933 14:44:27.849725 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5934 14:44:27.852990 ===================================
5935 14:44:27.853070 data_rate = 800,PCW = 0X7400
5936 14:44:27.856576 ===================================
5937 14:44:27.859724 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5938 14:44:27.866443 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5939 14:44:27.879444 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5940 14:44:27.882716 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5941 14:44:27.886246 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5942 14:44:27.889503 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5943 14:44:27.892598 [ANA_INIT] flow start
5944 14:44:27.892678 [ANA_INIT] PLL >>>>>>>>
5945 14:44:27.896459 [ANA_INIT] PLL <<<<<<<<
5946 14:44:27.899232 [ANA_INIT] MIDPI >>>>>>>>
5947 14:44:27.899317 [ANA_INIT] MIDPI <<<<<<<<
5948 14:44:27.902515 [ANA_INIT] DLL >>>>>>>>
5949 14:44:27.905828 [ANA_INIT] flow end
5950 14:44:27.909417 ============ LP4 DIFF to SE enter ============
5951 14:44:27.912414 ============ LP4 DIFF to SE exit ============
5952 14:44:27.915883 [ANA_INIT] <<<<<<<<<<<<<
5953 14:44:27.919161 [Flow] Enable top DCM control >>>>>
5954 14:44:27.922324 [Flow] Enable top DCM control <<<<<
5955 14:44:27.925731 Enable DLL master slave shuffle
5956 14:44:27.932141 ==============================================================
5957 14:44:27.932282 Gating Mode config
5958 14:44:27.938998 ==============================================================
5959 14:44:27.939104 Config description:
5960 14:44:27.948853 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5961 14:44:27.955491 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5962 14:44:27.961953 SELPH_MODE 0: By rank 1: By Phase
5963 14:44:27.965153 ==============================================================
5964 14:44:27.968448 GAT_TRACK_EN = 0
5965 14:44:27.972036 RX_GATING_MODE = 2
5966 14:44:27.975310 RX_GATING_TRACK_MODE = 2
5967 14:44:27.978637 SELPH_MODE = 1
5968 14:44:27.981953 PICG_EARLY_EN = 1
5969 14:44:27.985024 VALID_LAT_VALUE = 1
5970 14:44:27.988635 ==============================================================
5971 14:44:27.994876 Enter into Gating configuration >>>>
5972 14:44:27.998213 Exit from Gating configuration <<<<
5973 14:44:27.998294 Enter into DVFS_PRE_config >>>>>
5974 14:44:28.011572 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5975 14:44:28.014893 Exit from DVFS_PRE_config <<<<<
5976 14:44:28.018051 Enter into PICG configuration >>>>
5977 14:44:28.021444 Exit from PICG configuration <<<<
5978 14:44:28.021524 [RX_INPUT] configuration >>>>>
5979 14:44:28.024995 [RX_INPUT] configuration <<<<<
5980 14:44:28.031321 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5981 14:44:28.034940 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5982 14:44:28.041483 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5983 14:44:28.048064 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5984 14:44:28.054601 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5985 14:44:28.061105 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5986 14:44:28.064828 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5987 14:44:28.067988 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5988 14:44:28.074583 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5989 14:44:28.078070 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5990 14:44:28.081369 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5991 14:44:28.084568 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5992 14:44:28.087585 ===================================
5993 14:44:28.091172 LPDDR4 DRAM CONFIGURATION
5994 14:44:28.094411 ===================================
5995 14:44:28.097547 EX_ROW_EN[0] = 0x0
5996 14:44:28.097630 EX_ROW_EN[1] = 0x0
5997 14:44:28.100792 LP4Y_EN = 0x0
5998 14:44:28.100873 WORK_FSP = 0x0
5999 14:44:28.104212 WL = 0x2
6000 14:44:28.107251 RL = 0x2
6001 14:44:28.107336 BL = 0x2
6002 14:44:28.110713 RPST = 0x0
6003 14:44:28.110794 RD_PRE = 0x0
6004 14:44:28.113954 WR_PRE = 0x1
6005 14:44:28.114067 WR_PST = 0x0
6006 14:44:28.117510 DBI_WR = 0x0
6007 14:44:28.117591 DBI_RD = 0x0
6008 14:44:28.120696 OTF = 0x1
6009 14:44:28.123888 ===================================
6010 14:44:28.127168 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6011 14:44:28.130715 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6012 14:44:28.137183 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6013 14:44:28.137272 ===================================
6014 14:44:28.140728 LPDDR4 DRAM CONFIGURATION
6015 14:44:28.143806 ===================================
6016 14:44:28.147122 EX_ROW_EN[0] = 0x10
6017 14:44:28.147207 EX_ROW_EN[1] = 0x0
6018 14:44:28.150332 LP4Y_EN = 0x0
6019 14:44:28.150415 WORK_FSP = 0x0
6020 14:44:28.153609 WL = 0x2
6021 14:44:28.157016 RL = 0x2
6022 14:44:28.157113 BL = 0x2
6023 14:44:28.160176 RPST = 0x0
6024 14:44:28.160266 RD_PRE = 0x0
6025 14:44:28.163321 WR_PRE = 0x1
6026 14:44:28.163403 WR_PST = 0x0
6027 14:44:28.166674 DBI_WR = 0x0
6028 14:44:28.166756 DBI_RD = 0x0
6029 14:44:28.170074 OTF = 0x1
6030 14:44:28.173205 ===================================
6031 14:44:28.179996 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6032 14:44:28.183277 nWR fixed to 30
6033 14:44:28.183354 [ModeRegInit_LP4] CH0 RK0
6034 14:44:28.186529 [ModeRegInit_LP4] CH0 RK1
6035 14:44:28.189877 [ModeRegInit_LP4] CH1 RK0
6036 14:44:28.193242 [ModeRegInit_LP4] CH1 RK1
6037 14:44:28.193358 match AC timing 18
6038 14:44:28.196380 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6039 14:44:28.203223 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6040 14:44:28.206457 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6041 14:44:28.209726 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6042 14:44:28.216436 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6043 14:44:28.216543 ==
6044 14:44:28.219624 Dram Type= 6, Freq= 0, CH_0, rank 0
6045 14:44:28.222865 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6046 14:44:28.222955 ==
6047 14:44:28.229509 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6048 14:44:28.236020 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6049 14:44:28.239748 [CA 0] Center 36 (8~64) winsize 57
6050 14:44:28.239835 [CA 1] Center 36 (8~64) winsize 57
6051 14:44:28.242746 [CA 2] Center 36 (8~64) winsize 57
6052 14:44:28.246033 [CA 3] Center 36 (8~64) winsize 57
6053 14:44:28.249415 [CA 4] Center 36 (8~64) winsize 57
6054 14:44:28.252653 [CA 5] Center 36 (8~64) winsize 57
6055 14:44:28.252735
6056 14:44:28.256084 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6057 14:44:28.256165
6058 14:44:28.262440 [CATrainingPosCal] consider 1 rank data
6059 14:44:28.262524 u2DelayCellTimex100 = 270/100 ps
6060 14:44:28.268989 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6061 14:44:28.272273 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6062 14:44:28.275708 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6063 14:44:28.278972 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6064 14:44:28.282171 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6065 14:44:28.285606 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6066 14:44:28.285691
6067 14:44:28.288983 CA PerBit enable=1, Macro0, CA PI delay=36
6068 14:44:28.289065
6069 14:44:28.292145 [CBTSetCACLKResult] CA Dly = 36
6070 14:44:28.295524 CS Dly: 1 (0~32)
6071 14:44:28.295607 ==
6072 14:44:28.298939 Dram Type= 6, Freq= 0, CH_0, rank 1
6073 14:44:28.302187 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6074 14:44:28.302271 ==
6075 14:44:28.308963 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6076 14:44:28.311856 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6077 14:44:28.315254 [CA 0] Center 36 (8~64) winsize 57
6078 14:44:28.318536 [CA 1] Center 36 (8~64) winsize 57
6079 14:44:28.322065 [CA 2] Center 36 (8~64) winsize 57
6080 14:44:28.324966 [CA 3] Center 36 (8~64) winsize 57
6081 14:44:28.328468 [CA 4] Center 36 (8~64) winsize 57
6082 14:44:28.331590 [CA 5] Center 36 (8~64) winsize 57
6083 14:44:28.331673
6084 14:44:28.334937 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6085 14:44:28.335020
6086 14:44:28.338229 [CATrainingPosCal] consider 2 rank data
6087 14:44:28.341506 u2DelayCellTimex100 = 270/100 ps
6088 14:44:28.344951 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6089 14:44:28.348286 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6090 14:44:28.354768 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6091 14:44:28.358141 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6092 14:44:28.361415 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6093 14:44:28.364663 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6094 14:44:28.364745
6095 14:44:28.368365 CA PerBit enable=1, Macro0, CA PI delay=36
6096 14:44:28.368447
6097 14:44:28.371466 [CBTSetCACLKResult] CA Dly = 36
6098 14:44:28.371548 CS Dly: 1 (0~32)
6099 14:44:28.371610
6100 14:44:28.377829 ----->DramcWriteLeveling(PI) begin...
6101 14:44:28.377916 ==
6102 14:44:28.381213 Dram Type= 6, Freq= 0, CH_0, rank 0
6103 14:44:28.384405 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6104 14:44:28.384487 ==
6105 14:44:28.387740 Write leveling (Byte 0): 32 => 0
6106 14:44:28.391291 Write leveling (Byte 1): 32 => 0
6107 14:44:28.394234 DramcWriteLeveling(PI) end<-----
6108 14:44:28.394316
6109 14:44:28.394378 ==
6110 14:44:28.397646 Dram Type= 6, Freq= 0, CH_0, rank 0
6111 14:44:28.401056 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6112 14:44:28.401140 ==
6113 14:44:28.404332 [Gating] SW mode calibration
6114 14:44:28.410758 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6115 14:44:28.417475 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6116 14:44:28.420872 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6117 14:44:28.424439 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6118 14:44:28.430855 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6119 14:44:28.434138 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6120 14:44:28.437423 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6121 14:44:28.443996 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6122 14:44:28.447350 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6123 14:44:28.450465 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6124 14:44:28.457133 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6125 14:44:28.457257 Total UI for P1: 0, mck2ui 16
6126 14:44:28.460481 best dqsien dly found for B0: ( 0, 10, 16)
6127 14:44:28.463810 Total UI for P1: 0, mck2ui 16
6128 14:44:28.467184 best dqsien dly found for B1: ( 0, 10, 24)
6129 14:44:28.473649 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6130 14:44:28.476974 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6131 14:44:28.477084
6132 14:44:28.480312 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6133 14:44:28.483754 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6134 14:44:28.487036 [Gating] SW calibration Done
6135 14:44:28.487146 ==
6136 14:44:28.490202 Dram Type= 6, Freq= 0, CH_0, rank 0
6137 14:44:28.493563 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6138 14:44:28.493672 ==
6139 14:44:28.496862 RX Vref Scan: 0
6140 14:44:28.496972
6141 14:44:28.497095 RX Vref 0 -> 0, step: 1
6142 14:44:28.497207
6143 14:44:28.500049 RX Delay -410 -> 252, step: 16
6144 14:44:28.506923 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6145 14:44:28.510334 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6146 14:44:28.513754 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6147 14:44:28.516746 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6148 14:44:28.523430 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6149 14:44:28.526689 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6150 14:44:28.529938 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6151 14:44:28.533270 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6152 14:44:28.539826 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6153 14:44:28.543119 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6154 14:44:28.546375 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6155 14:44:28.549822 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6156 14:44:28.556280 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6157 14:44:28.559918 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6158 14:44:28.563124 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6159 14:44:28.569551 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6160 14:44:28.569648 ==
6161 14:44:28.572768 Dram Type= 6, Freq= 0, CH_0, rank 0
6162 14:44:28.576351 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6163 14:44:28.576447 ==
6164 14:44:28.576516 DQS Delay:
6165 14:44:28.579428 DQS0 = 43, DQS1 = 59
6166 14:44:28.579511 DQM Delay:
6167 14:44:28.582764 DQM0 = 5, DQM1 = 16
6168 14:44:28.582847 DQ Delay:
6169 14:44:28.586134 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6170 14:44:28.589241 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6171 14:44:28.592755 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6172 14:44:28.595925 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6173 14:44:28.596012
6174 14:44:28.596077
6175 14:44:28.596136 ==
6176 14:44:28.599306 Dram Type= 6, Freq= 0, CH_0, rank 0
6177 14:44:28.602480 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6178 14:44:28.602595 ==
6179 14:44:28.602690
6180 14:44:28.602782
6181 14:44:28.605767 TX Vref Scan disable
6182 14:44:28.605875 == TX Byte 0 ==
6183 14:44:28.612410 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6184 14:44:28.615829 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6185 14:44:28.615957 == TX Byte 1 ==
6186 14:44:28.622241 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6187 14:44:28.625862 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6188 14:44:28.625984 ==
6189 14:44:28.628995 Dram Type= 6, Freq= 0, CH_0, rank 0
6190 14:44:28.632664 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6191 14:44:28.632782 ==
6192 14:44:28.632878
6193 14:44:28.635637
6194 14:44:28.635746 TX Vref Scan disable
6195 14:44:28.639088 == TX Byte 0 ==
6196 14:44:28.642138 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6197 14:44:28.645555 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6198 14:44:28.648845 == TX Byte 1 ==
6199 14:44:28.651921 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6200 14:44:28.655496 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6201 14:44:28.655618
6202 14:44:28.658665 [DATLAT]
6203 14:44:28.658777 Freq=400, CH0 RK0
6204 14:44:28.658872
6205 14:44:28.662009 DATLAT Default: 0xf
6206 14:44:28.662118 0, 0xFFFF, sum = 0
6207 14:44:28.665227 1, 0xFFFF, sum = 0
6208 14:44:28.665357 2, 0xFFFF, sum = 0
6209 14:44:28.668467 3, 0xFFFF, sum = 0
6210 14:44:28.668552 4, 0xFFFF, sum = 0
6211 14:44:28.671921 5, 0xFFFF, sum = 0
6212 14:44:28.672006 6, 0xFFFF, sum = 0
6213 14:44:28.675239 7, 0xFFFF, sum = 0
6214 14:44:28.675326 8, 0xFFFF, sum = 0
6215 14:44:28.678464 9, 0xFFFF, sum = 0
6216 14:44:28.678549 10, 0xFFFF, sum = 0
6217 14:44:28.681749 11, 0xFFFF, sum = 0
6218 14:44:28.681834 12, 0x0, sum = 1
6219 14:44:28.685054 13, 0x0, sum = 2
6220 14:44:28.685138 14, 0x0, sum = 3
6221 14:44:28.688380 15, 0x0, sum = 4
6222 14:44:28.688465 best_step = 13
6223 14:44:28.688529
6224 14:44:28.688588 ==
6225 14:44:28.691774 Dram Type= 6, Freq= 0, CH_0, rank 0
6226 14:44:28.698234 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6227 14:44:28.698328 ==
6228 14:44:28.698393 RX Vref Scan: 1
6229 14:44:28.698452
6230 14:44:28.701477 RX Vref 0 -> 0, step: 1
6231 14:44:28.701559
6232 14:44:28.705268 RX Delay -359 -> 252, step: 8
6233 14:44:28.705361
6234 14:44:28.708160 Set Vref, RX VrefLevel [Byte0]: 47
6235 14:44:28.711450 [Byte1]: 49
6236 14:44:28.714813
6237 14:44:28.714909 Final RX Vref Byte 0 = 47 to rank0
6238 14:44:28.718128 Final RX Vref Byte 1 = 49 to rank0
6239 14:44:28.721424 Final RX Vref Byte 0 = 47 to rank1
6240 14:44:28.724758 Final RX Vref Byte 1 = 49 to rank1==
6241 14:44:28.728048 Dram Type= 6, Freq= 0, CH_0, rank 0
6242 14:44:28.734621 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6243 14:44:28.734723 ==
6244 14:44:28.734790 DQS Delay:
6245 14:44:28.737957 DQS0 = 52, DQS1 = 68
6246 14:44:28.738049 DQM Delay:
6247 14:44:28.738115 DQM0 = 9, DQM1 = 16
6248 14:44:28.741211 DQ Delay:
6249 14:44:28.744478 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6250 14:44:28.744565 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6251 14:44:28.748160 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6252 14:44:28.751222 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6253 14:44:28.751306
6254 14:44:28.751369
6255 14:44:28.760948 [DQSOSCAuto] RK0, (LSB)MR18= 0xa2a2, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6256 14:44:28.764357 CH0 RK0: MR19=C0C, MR18=A2A2
6257 14:44:28.771058 CH0_RK0: MR19=0xC0C, MR18=0xA2A2, DQSOSC=389, MR23=63, INC=390, DEC=260
6258 14:44:28.771159 ==
6259 14:44:28.774513 Dram Type= 6, Freq= 0, CH_0, rank 1
6260 14:44:28.777695 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6261 14:44:28.777782 ==
6262 14:44:28.780920 [Gating] SW mode calibration
6263 14:44:28.787566 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6264 14:44:28.793988 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6265 14:44:28.797416 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6266 14:44:28.800673 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6267 14:44:28.804131 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6268 14:44:28.810863 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6269 14:44:28.814217 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6270 14:44:28.817439 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6271 14:44:28.824223 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 14:44:28.827439 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6273 14:44:28.830863 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6274 14:44:28.833913 Total UI for P1: 0, mck2ui 16
6275 14:44:28.837309 best dqsien dly found for B0: ( 0, 10, 16)
6276 14:44:28.840927 Total UI for P1: 0, mck2ui 16
6277 14:44:28.843896 best dqsien dly found for B1: ( 0, 10, 16)
6278 14:44:28.847608 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6279 14:44:28.850585 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6280 14:44:28.853897
6281 14:44:28.857265 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6282 14:44:28.860333 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6283 14:44:28.863972 [Gating] SW calibration Done
6284 14:44:28.864060 ==
6285 14:44:28.867185 Dram Type= 6, Freq= 0, CH_0, rank 1
6286 14:44:28.870424 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6287 14:44:28.870511 ==
6288 14:44:28.874005 RX Vref Scan: 0
6289 14:44:28.874089
6290 14:44:28.874154 RX Vref 0 -> 0, step: 1
6291 14:44:28.874213
6292 14:44:28.876968 RX Delay -410 -> 252, step: 16
6293 14:44:28.880294 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6294 14:44:28.886863 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6295 14:44:28.890210 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6296 14:44:28.893456 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6297 14:44:28.897065 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6298 14:44:28.903693 iDelay=230, Bit 5, Center -51 (-314 ~ 213) 528
6299 14:44:28.906803 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6300 14:44:28.910039 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6301 14:44:28.916607 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6302 14:44:28.919956 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6303 14:44:28.923307 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6304 14:44:28.926451 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6305 14:44:28.933175 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6306 14:44:28.936757 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6307 14:44:28.939804 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6308 14:44:28.943645 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6309 14:44:28.943734 ==
6310 14:44:28.946474 Dram Type= 6, Freq= 0, CH_0, rank 1
6311 14:44:28.952864 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6312 14:44:28.952958 ==
6313 14:44:28.953023 DQS Delay:
6314 14:44:28.956344 DQS0 = 51, DQS1 = 59
6315 14:44:28.956427 DQM Delay:
6316 14:44:28.959754 DQM0 = 14, DQM1 = 14
6317 14:44:28.959838 DQ Delay:
6318 14:44:28.962936 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6319 14:44:28.966141 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6320 14:44:28.969444 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6321 14:44:28.972657 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6322 14:44:28.972741
6323 14:44:28.972803
6324 14:44:28.972863 ==
6325 14:44:28.976113 Dram Type= 6, Freq= 0, CH_0, rank 1
6326 14:44:28.979785 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6327 14:44:28.979871 ==
6328 14:44:28.979935
6329 14:44:28.979993
6330 14:44:28.982560 TX Vref Scan disable
6331 14:44:28.982642 == TX Byte 0 ==
6332 14:44:28.989624 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6333 14:44:28.992726 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6334 14:44:28.992812 == TX Byte 1 ==
6335 14:44:28.999153 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6336 14:44:29.002547 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6337 14:44:29.002656 ==
6338 14:44:29.005955 Dram Type= 6, Freq= 0, CH_0, rank 1
6339 14:44:29.009353 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6340 14:44:29.009442 ==
6341 14:44:29.009507
6342 14:44:29.009567
6343 14:44:29.012541 TX Vref Scan disable
6344 14:44:29.012622 == TX Byte 0 ==
6345 14:44:29.019094 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6346 14:44:29.022299 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6347 14:44:29.022389 == TX Byte 1 ==
6348 14:44:29.029216 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6349 14:44:29.032343 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6350 14:44:29.032429
6351 14:44:29.032493 [DATLAT]
6352 14:44:29.035621 Freq=400, CH0 RK1
6353 14:44:29.035706
6354 14:44:29.035770 DATLAT Default: 0xd
6355 14:44:29.038909 0, 0xFFFF, sum = 0
6356 14:44:29.038993 1, 0xFFFF, sum = 0
6357 14:44:29.042382 2, 0xFFFF, sum = 0
6358 14:44:29.042466 3, 0xFFFF, sum = 0
6359 14:44:29.045621 4, 0xFFFF, sum = 0
6360 14:44:29.045706 5, 0xFFFF, sum = 0
6361 14:44:29.048993 6, 0xFFFF, sum = 0
6362 14:44:29.049081 7, 0xFFFF, sum = 0
6363 14:44:29.052247 8, 0xFFFF, sum = 0
6364 14:44:29.055215 9, 0xFFFF, sum = 0
6365 14:44:29.055299 10, 0xFFFF, sum = 0
6366 14:44:29.058582 11, 0xFFFF, sum = 0
6367 14:44:29.058668 12, 0x0, sum = 1
6368 14:44:29.062101 13, 0x0, sum = 2
6369 14:44:29.062184 14, 0x0, sum = 3
6370 14:44:29.065296 15, 0x0, sum = 4
6371 14:44:29.065382 best_step = 13
6372 14:44:29.065446
6373 14:44:29.065506 ==
6374 14:44:29.068488 Dram Type= 6, Freq= 0, CH_0, rank 1
6375 14:44:29.071944 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6376 14:44:29.072029 ==
6377 14:44:29.075102 RX Vref Scan: 0
6378 14:44:29.075183
6379 14:44:29.078405 RX Vref 0 -> 0, step: 1
6380 14:44:29.078487
6381 14:44:29.078551 RX Delay -359 -> 252, step: 8
6382 14:44:29.087149 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6383 14:44:29.090728 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6384 14:44:29.093715 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6385 14:44:29.100491 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6386 14:44:29.103783 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6387 14:44:29.107052 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6388 14:44:29.110335 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6389 14:44:29.117106 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6390 14:44:29.120232 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6391 14:44:29.123498 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6392 14:44:29.126804 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6393 14:44:29.133697 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6394 14:44:29.136956 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6395 14:44:29.140148 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6396 14:44:29.143647 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6397 14:44:29.150039 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6398 14:44:29.150166 ==
6399 14:44:29.153194 Dram Type= 6, Freq= 0, CH_0, rank 1
6400 14:44:29.156755 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6401 14:44:29.156867 ==
6402 14:44:29.156961 DQS Delay:
6403 14:44:29.160007 DQS0 = 52, DQS1 = 64
6404 14:44:29.160115 DQM Delay:
6405 14:44:29.163231 DQM0 = 9, DQM1 = 14
6406 14:44:29.163339 DQ Delay:
6407 14:44:29.166409 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6408 14:44:29.169684 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6409 14:44:29.173031 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6410 14:44:29.176317 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6411 14:44:29.176426
6412 14:44:29.176518
6413 14:44:29.182882 [DQSOSCAuto] RK1, (LSB)MR18= 0xcaca, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6414 14:44:29.186257 CH0 RK1: MR19=C0C, MR18=CACA
6415 14:44:29.192846 CH0_RK1: MR19=0xC0C, MR18=0xCACA, DQSOSC=384, MR23=63, INC=400, DEC=267
6416 14:44:29.196086 [RxdqsGatingPostProcess] freq 400
6417 14:44:29.202713 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6418 14:44:29.206170 Pre-setting of DQS Precalculation
6419 14:44:29.209589 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6420 14:44:29.209699 ==
6421 14:44:29.212882 Dram Type= 6, Freq= 0, CH_1, rank 0
6422 14:44:29.216273 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6423 14:44:29.216389 ==
6424 14:44:29.223142 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6425 14:44:29.229245 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6426 14:44:29.232850 [CA 0] Center 36 (8~64) winsize 57
6427 14:44:29.235932 [CA 1] Center 36 (8~64) winsize 57
6428 14:44:29.239249 [CA 2] Center 36 (8~64) winsize 57
6429 14:44:29.242748 [CA 3] Center 36 (8~64) winsize 57
6430 14:44:29.245948 [CA 4] Center 36 (8~64) winsize 57
6431 14:44:29.249233 [CA 5] Center 36 (8~64) winsize 57
6432 14:44:29.249384
6433 14:44:29.252346 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6434 14:44:29.252427
6435 14:44:29.256074 [CATrainingPosCal] consider 1 rank data
6436 14:44:29.259292 u2DelayCellTimex100 = 270/100 ps
6437 14:44:29.262288 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6438 14:44:29.265714 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6439 14:44:29.268840 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6440 14:44:29.272593 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6441 14:44:29.275596 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6442 14:44:29.279006 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6443 14:44:29.279090
6444 14:44:29.282209 CA PerBit enable=1, Macro0, CA PI delay=36
6445 14:44:29.285432
6446 14:44:29.285519 [CBTSetCACLKResult] CA Dly = 36
6447 14:44:29.288915 CS Dly: 1 (0~32)
6448 14:44:29.289023 ==
6449 14:44:29.292048 Dram Type= 6, Freq= 0, CH_1, rank 1
6450 14:44:29.295188 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6451 14:44:29.295278 ==
6452 14:44:29.301880 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6453 14:44:29.308455 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6454 14:44:29.311860 [CA 0] Center 36 (8~64) winsize 57
6455 14:44:29.315345 [CA 1] Center 36 (8~64) winsize 57
6456 14:44:29.318517 [CA 2] Center 36 (8~64) winsize 57
6457 14:44:29.321967 [CA 3] Center 36 (8~64) winsize 57
6458 14:44:29.322059 [CA 4] Center 36 (8~64) winsize 57
6459 14:44:29.325072 [CA 5] Center 36 (8~64) winsize 57
6460 14:44:29.325181
6461 14:44:29.331634 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6462 14:44:29.331733
6463 14:44:29.334961 [CATrainingPosCal] consider 2 rank data
6464 14:44:29.338282 u2DelayCellTimex100 = 270/100 ps
6465 14:44:29.341579 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6466 14:44:29.344773 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6467 14:44:29.348025 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6468 14:44:29.351455 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6469 14:44:29.355175 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6470 14:44:29.358331 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6471 14:44:29.358418
6472 14:44:29.361247 CA PerBit enable=1, Macro0, CA PI delay=36
6473 14:44:29.361372
6474 14:44:29.364553 [CBTSetCACLKResult] CA Dly = 36
6475 14:44:29.368337 CS Dly: 1 (0~32)
6476 14:44:29.368423
6477 14:44:29.371588 ----->DramcWriteLeveling(PI) begin...
6478 14:44:29.371673 ==
6479 14:44:29.374578 Dram Type= 6, Freq= 0, CH_1, rank 0
6480 14:44:29.377839 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6481 14:44:29.377954 ==
6482 14:44:29.381646 Write leveling (Byte 0): 32 => 0
6483 14:44:29.384634 Write leveling (Byte 1): 32 => 0
6484 14:44:29.387962 DramcWriteLeveling(PI) end<-----
6485 14:44:29.388048
6486 14:44:29.388112 ==
6487 14:44:29.391050 Dram Type= 6, Freq= 0, CH_1, rank 0
6488 14:44:29.394353 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6489 14:44:29.394458 ==
6490 14:44:29.397642 [Gating] SW mode calibration
6491 14:44:29.404373 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6492 14:44:29.410897 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6493 14:44:29.414615 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6494 14:44:29.417550 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6495 14:44:29.424281 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6496 14:44:29.427589 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6497 14:44:29.430887 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6498 14:44:29.437697 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6499 14:44:29.440934 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6500 14:44:29.444174 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6501 14:44:29.450675 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 14:44:29.454015 Total UI for P1: 0, mck2ui 16
6503 14:44:29.457316 best dqsien dly found for B0: ( 0, 10, 16)
6504 14:44:29.460765 Total UI for P1: 0, mck2ui 16
6505 14:44:29.464292 best dqsien dly found for B1: ( 0, 10, 16)
6506 14:44:29.468803 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6507 14:44:29.470678 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6508 14:44:29.470761
6509 14:44:29.473968 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6510 14:44:29.477255 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6511 14:44:29.480361 [Gating] SW calibration Done
6512 14:44:29.480446 ==
6513 14:44:29.483747 Dram Type= 6, Freq= 0, CH_1, rank 0
6514 14:44:29.487079 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6515 14:44:29.490270 ==
6516 14:44:29.490354 RX Vref Scan: 0
6517 14:44:29.490417
6518 14:44:29.493577 RX Vref 0 -> 0, step: 1
6519 14:44:29.493661
6520 14:44:29.496741 RX Delay -410 -> 252, step: 16
6521 14:44:29.500037 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6522 14:44:29.503979 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6523 14:44:29.506847 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6524 14:44:29.513272 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6525 14:44:29.516842 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6526 14:44:29.520387 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6527 14:44:29.523549 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6528 14:44:29.530026 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6529 14:44:29.533239 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6530 14:44:29.536860 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6531 14:44:29.540049 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6532 14:44:29.546641 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6533 14:44:29.549813 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6534 14:44:29.553019 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6535 14:44:29.559623 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6536 14:44:29.562935 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6537 14:44:29.563028 ==
6538 14:44:29.566303 Dram Type= 6, Freq= 0, CH_1, rank 0
6539 14:44:29.569810 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6540 14:44:29.569895 ==
6541 14:44:29.572980 DQS Delay:
6542 14:44:29.573063 DQS0 = 43, DQS1 = 59
6543 14:44:29.573127 DQM Delay:
6544 14:44:29.576311 DQM0 = 6, DQM1 = 15
6545 14:44:29.576394 DQ Delay:
6546 14:44:29.579515 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6547 14:44:29.582848 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6548 14:44:29.586278 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6549 14:44:29.589336 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6550 14:44:29.589421
6551 14:44:29.589485
6552 14:44:29.589544 ==
6553 14:44:29.592865 Dram Type= 6, Freq= 0, CH_1, rank 0
6554 14:44:29.595995 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6555 14:44:29.596081 ==
6556 14:44:29.599341
6557 14:44:29.599424
6558 14:44:29.599487 TX Vref Scan disable
6559 14:44:29.602797 == TX Byte 0 ==
6560 14:44:29.605912 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6561 14:44:29.609219 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6562 14:44:29.612635 == TX Byte 1 ==
6563 14:44:29.615881 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6564 14:44:29.619434 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6565 14:44:29.619530 ==
6566 14:44:29.622437 Dram Type= 6, Freq= 0, CH_1, rank 0
6567 14:44:29.629217 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6568 14:44:29.629394 ==
6569 14:44:29.629491
6570 14:44:29.629582
6571 14:44:29.629670 TX Vref Scan disable
6572 14:44:29.632397 == TX Byte 0 ==
6573 14:44:29.635930 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6574 14:44:29.639087 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6575 14:44:29.642358 == TX Byte 1 ==
6576 14:44:29.645497 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6577 14:44:29.648757 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6578 14:44:29.652403
6579 14:44:29.652523 [DATLAT]
6580 14:44:29.652619 Freq=400, CH1 RK0
6581 14:44:29.652711
6582 14:44:29.655431 DATLAT Default: 0xf
6583 14:44:29.655539 0, 0xFFFF, sum = 0
6584 14:44:29.658880 1, 0xFFFF, sum = 0
6585 14:44:29.658988 2, 0xFFFF, sum = 0
6586 14:44:29.662341 3, 0xFFFF, sum = 0
6587 14:44:29.662451 4, 0xFFFF, sum = 0
6588 14:44:29.665248 5, 0xFFFF, sum = 0
6589 14:44:29.668898 6, 0xFFFF, sum = 0
6590 14:44:29.669008 7, 0xFFFF, sum = 0
6591 14:44:29.672075 8, 0xFFFF, sum = 0
6592 14:44:29.672183 9, 0xFFFF, sum = 0
6593 14:44:29.675330 10, 0xFFFF, sum = 0
6594 14:44:29.675437 11, 0xFFFF, sum = 0
6595 14:44:29.678906 12, 0x0, sum = 1
6596 14:44:29.679013 13, 0x0, sum = 2
6597 14:44:29.681806 14, 0x0, sum = 3
6598 14:44:29.681914 15, 0x0, sum = 4
6599 14:44:29.682007 best_step = 13
6600 14:44:29.685188
6601 14:44:29.685316 ==
6602 14:44:29.688299 Dram Type= 6, Freq= 0, CH_1, rank 0
6603 14:44:29.691804 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6604 14:44:29.691912 ==
6605 14:44:29.692003 RX Vref Scan: 1
6606 14:44:29.692090
6607 14:44:29.695291 RX Vref 0 -> 0, step: 1
6608 14:44:29.695395
6609 14:44:29.698527 RX Delay -359 -> 252, step: 8
6610 14:44:29.698633
6611 14:44:29.701719 Set Vref, RX VrefLevel [Byte0]: 53
6612 14:44:29.704859 [Byte1]: 49
6613 14:44:29.709162
6614 14:44:29.709271 Final RX Vref Byte 0 = 53 to rank0
6615 14:44:29.712305 Final RX Vref Byte 1 = 49 to rank0
6616 14:44:29.715648 Final RX Vref Byte 0 = 53 to rank1
6617 14:44:29.719081 Final RX Vref Byte 1 = 49 to rank1==
6618 14:44:29.722494 Dram Type= 6, Freq= 0, CH_1, rank 0
6619 14:44:29.729271 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6620 14:44:29.729522 ==
6621 14:44:29.729662 DQS Delay:
6622 14:44:29.729751 DQS0 = 48, DQS1 = 64
6623 14:44:29.732256 DQM Delay:
6624 14:44:29.732360 DQM0 = 9, DQM1 = 16
6625 14:44:29.735861 DQ Delay:
6626 14:44:29.739215 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6627 14:44:29.739327 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6628 14:44:29.742211 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6629 14:44:29.745690 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6630 14:44:29.745799
6631 14:44:29.745893
6632 14:44:29.755446 [DQSOSCAuto] RK0, (LSB)MR18= 0xe0e0, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6633 14:44:29.758828 CH1 RK0: MR19=C0C, MR18=E0E0
6634 14:44:29.765398 CH1_RK0: MR19=0xC0C, MR18=0xE0E0, DQSOSC=382, MR23=63, INC=404, DEC=269
6635 14:44:29.765526 ==
6636 14:44:29.768753 Dram Type= 6, Freq= 0, CH_1, rank 1
6637 14:44:29.771980 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6638 14:44:29.772090 ==
6639 14:44:29.775579 [Gating] SW mode calibration
6640 14:44:29.781845 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6641 14:44:29.785250 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6642 14:44:29.792068 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6643 14:44:29.795183 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6644 14:44:29.798655 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6645 14:44:29.805132 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6646 14:44:29.808625 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6647 14:44:29.811917 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6648 14:44:29.818316 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6649 14:44:29.821684 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6650 14:44:29.824996 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6651 14:44:29.828321 Total UI for P1: 0, mck2ui 16
6652 14:44:29.831706 best dqsien dly found for B0: ( 0, 10, 16)
6653 14:44:29.835076 Total UI for P1: 0, mck2ui 16
6654 14:44:29.838199 best dqsien dly found for B1: ( 0, 10, 16)
6655 14:44:29.841568 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6656 14:44:29.848105 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6657 14:44:29.848209
6658 14:44:29.851460 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6659 14:44:29.854874 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6660 14:44:29.858514 [Gating] SW calibration Done
6661 14:44:29.858600 ==
6662 14:44:29.861461 Dram Type= 6, Freq= 0, CH_1, rank 1
6663 14:44:29.864879 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6664 14:44:29.864962 ==
6665 14:44:29.868089 RX Vref Scan: 0
6666 14:44:29.868171
6667 14:44:29.868234 RX Vref 0 -> 0, step: 1
6668 14:44:29.868293
6669 14:44:29.871726 RX Delay -410 -> 252, step: 16
6670 14:44:29.874805 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6671 14:44:29.881194 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6672 14:44:29.884571 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6673 14:44:29.887819 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6674 14:44:29.891266 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6675 14:44:29.898256 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6676 14:44:29.901237 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6677 14:44:29.904777 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6678 14:44:29.907800 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6679 14:44:29.914486 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6680 14:44:29.917730 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6681 14:44:29.921126 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6682 14:44:29.927672 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6683 14:44:29.931015 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6684 14:44:29.934420 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6685 14:44:29.937870 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6686 14:44:29.937969 ==
6687 14:44:29.940756 Dram Type= 6, Freq= 0, CH_1, rank 1
6688 14:44:29.947423 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6689 14:44:29.947524 ==
6690 14:44:29.947589 DQS Delay:
6691 14:44:29.951113 DQS0 = 35, DQS1 = 59
6692 14:44:29.951197 DQM Delay:
6693 14:44:29.954069 DQM0 = 3, DQM1 = 18
6694 14:44:29.954151 DQ Delay:
6695 14:44:29.957482 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6696 14:44:29.960858 DQ4 =0, DQ5 =16, DQ6 =8, DQ7 =0
6697 14:44:29.960946 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6698 14:44:29.964146 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6699 14:44:29.967246
6700 14:44:29.967328
6701 14:44:29.967392 ==
6702 14:44:29.970756 Dram Type= 6, Freq= 0, CH_1, rank 1
6703 14:44:29.973899 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6704 14:44:29.973983 ==
6705 14:44:29.974047
6706 14:44:29.974107
6707 14:44:29.977219 TX Vref Scan disable
6708 14:44:29.977308 == TX Byte 0 ==
6709 14:44:29.980608 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6710 14:44:29.987139 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6711 14:44:29.987232 == TX Byte 1 ==
6712 14:44:29.990471 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6713 14:44:29.997134 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6714 14:44:29.997230 ==
6715 14:44:30.000321 Dram Type= 6, Freq= 0, CH_1, rank 1
6716 14:44:30.003742 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6717 14:44:30.003830 ==
6718 14:44:30.003894
6719 14:44:30.003952
6720 14:44:30.007169 TX Vref Scan disable
6721 14:44:30.007253 == TX Byte 0 ==
6722 14:44:30.013834 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6723 14:44:30.016830 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6724 14:44:30.016927 == TX Byte 1 ==
6725 14:44:30.023398 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6726 14:44:30.026808 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6727 14:44:30.026901
6728 14:44:30.026965 [DATLAT]
6729 14:44:30.030446 Freq=400, CH1 RK1
6730 14:44:30.030558
6731 14:44:30.030649 DATLAT Default: 0xd
6732 14:44:30.033559 0, 0xFFFF, sum = 0
6733 14:44:30.033642 1, 0xFFFF, sum = 0
6734 14:44:30.036788 2, 0xFFFF, sum = 0
6735 14:44:30.036878 3, 0xFFFF, sum = 0
6736 14:44:30.040169 4, 0xFFFF, sum = 0
6737 14:44:30.040254 5, 0xFFFF, sum = 0
6738 14:44:30.043328 6, 0xFFFF, sum = 0
6739 14:44:30.043412 7, 0xFFFF, sum = 0
6740 14:44:30.046846 8, 0xFFFF, sum = 0
6741 14:44:30.046932 9, 0xFFFF, sum = 0
6742 14:44:30.049973 10, 0xFFFF, sum = 0
6743 14:44:30.050058 11, 0xFFFF, sum = 0
6744 14:44:30.053187 12, 0x0, sum = 1
6745 14:44:30.053271 13, 0x0, sum = 2
6746 14:44:30.056453 14, 0x0, sum = 3
6747 14:44:30.056537 15, 0x0, sum = 4
6748 14:44:30.059976 best_step = 13
6749 14:44:30.060060
6750 14:44:30.060124 ==
6751 14:44:30.063000 Dram Type= 6, Freq= 0, CH_1, rank 1
6752 14:44:30.066500 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6753 14:44:30.066585 ==
6754 14:44:30.069576 RX Vref Scan: 0
6755 14:44:30.069660
6756 14:44:30.069724 RX Vref 0 -> 0, step: 1
6757 14:44:30.069785
6758 14:44:30.073104 RX Delay -359 -> 252, step: 8
6759 14:44:30.081207 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6760 14:44:30.084587 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6761 14:44:30.087686 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6762 14:44:30.094488 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6763 14:44:30.097697 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6764 14:44:30.100888 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6765 14:44:30.104456 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6766 14:44:30.111101 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6767 14:44:30.114471 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6768 14:44:30.117662 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6769 14:44:30.121037 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6770 14:44:30.127620 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6771 14:44:30.131036 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6772 14:44:30.134231 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6773 14:44:30.137621 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6774 14:44:30.143967 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6775 14:44:30.144074 ==
6776 14:44:30.147241 Dram Type= 6, Freq= 0, CH_1, rank 1
6777 14:44:30.150613 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6778 14:44:30.150703 ==
6779 14:44:30.150768 DQS Delay:
6780 14:44:30.153752 DQS0 = 48, DQS1 = 64
6781 14:44:30.153835 DQM Delay:
6782 14:44:30.156995 DQM0 = 9, DQM1 = 15
6783 14:44:30.157077 DQ Delay:
6784 14:44:30.160670 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6785 14:44:30.163784 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6786 14:44:30.166979 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6787 14:44:30.170393 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6788 14:44:30.170483
6789 14:44:30.170547
6790 14:44:30.176955 [DQSOSCAuto] RK1, (LSB)MR18= 0xaaaa, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6791 14:44:30.180088 CH1 RK1: MR19=C0C, MR18=AAAA
6792 14:44:30.187014 CH1_RK1: MR19=0xC0C, MR18=0xAAAA, DQSOSC=388, MR23=63, INC=392, DEC=261
6793 14:44:30.190153 [RxdqsGatingPostProcess] freq 400
6794 14:44:30.196778 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6795 14:44:30.200009 Pre-setting of DQS Precalculation
6796 14:44:30.203392 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6797 14:44:30.209974 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6798 14:44:30.216641 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6799 14:44:30.220168
6800 14:44:30.220270
6801 14:44:30.220336 [Calibration Summary] 800 Mbps
6802 14:44:30.223262 CH 0, Rank 0
6803 14:44:30.223349 SW Impedance : PASS
6804 14:44:30.226490 DUTY Scan : NO K
6805 14:44:30.229707 ZQ Calibration : PASS
6806 14:44:30.229794 Jitter Meter : NO K
6807 14:44:30.233234 CBT Training : PASS
6808 14:44:30.236494 Write leveling : PASS
6809 14:44:30.236578 RX DQS gating : PASS
6810 14:44:30.239731 RX DQ/DQS(RDDQC) : PASS
6811 14:44:30.243118 TX DQ/DQS : PASS
6812 14:44:30.243207 RX DATLAT : PASS
6813 14:44:30.246494 RX DQ/DQS(Engine): PASS
6814 14:44:30.249563 TX OE : NO K
6815 14:44:30.249650 All Pass.
6816 14:44:30.249715
6817 14:44:30.249775 CH 0, Rank 1
6818 14:44:30.253113 SW Impedance : PASS
6819 14:44:30.256368 DUTY Scan : NO K
6820 14:44:30.256455 ZQ Calibration : PASS
6821 14:44:30.259735 Jitter Meter : NO K
6822 14:44:30.262820 CBT Training : PASS
6823 14:44:30.262904 Write leveling : NO K
6824 14:44:30.266087 RX DQS gating : PASS
6825 14:44:30.269697 RX DQ/DQS(RDDQC) : PASS
6826 14:44:30.269779 TX DQ/DQS : PASS
6827 14:44:30.272593 RX DATLAT : PASS
6828 14:44:30.272676 RX DQ/DQS(Engine): PASS
6829 14:44:30.276086 TX OE : NO K
6830 14:44:30.276262 All Pass.
6831 14:44:30.276427
6832 14:44:30.279420 CH 1, Rank 0
6833 14:44:30.279501 SW Impedance : PASS
6834 14:44:30.282758 DUTY Scan : NO K
6835 14:44:30.286430 ZQ Calibration : PASS
6836 14:44:30.286513 Jitter Meter : NO K
6837 14:44:30.289560 CBT Training : PASS
6838 14:44:30.292816 Write leveling : PASS
6839 14:44:30.292900 RX DQS gating : PASS
6840 14:44:30.296276 RX DQ/DQS(RDDQC) : PASS
6841 14:44:30.299271 TX DQ/DQS : PASS
6842 14:44:30.299353 RX DATLAT : PASS
6843 14:44:30.302538 RX DQ/DQS(Engine): PASS
6844 14:44:30.305707 TX OE : NO K
6845 14:44:30.305790 All Pass.
6846 14:44:30.305853
6847 14:44:30.305912 CH 1, Rank 1
6848 14:44:30.309205 SW Impedance : PASS
6849 14:44:30.312409 DUTY Scan : NO K
6850 14:44:30.312491 ZQ Calibration : PASS
6851 14:44:30.315431 Jitter Meter : NO K
6852 14:44:30.319097 CBT Training : PASS
6853 14:44:30.319184 Write leveling : NO K
6854 14:44:30.322252 RX DQS gating : PASS
6855 14:44:30.325532 RX DQ/DQS(RDDQC) : PASS
6856 14:44:30.325615 TX DQ/DQS : PASS
6857 14:44:30.328957 RX DATLAT : PASS
6858 14:44:30.332124 RX DQ/DQS(Engine): PASS
6859 14:44:30.332207 TX OE : NO K
6860 14:44:30.332271 All Pass.
6861 14:44:30.335375
6862 14:44:30.335455 DramC Write-DBI off
6863 14:44:30.338619 PER_BANK_REFRESH: Hybrid Mode
6864 14:44:30.338701 TX_TRACKING: ON
6865 14:44:30.348830 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6866 14:44:30.352340 [FAST_K] Save calibration result to emmc
6867 14:44:30.355298 dramc_set_vcore_voltage set vcore to 725000
6868 14:44:30.358798 Read voltage for 1600, 0
6869 14:44:30.358879 Vio18 = 0
6870 14:44:30.361959 Vcore = 725000
6871 14:44:30.362040 Vdram = 0
6872 14:44:30.362102 Vddq = 0
6873 14:44:30.365571 Vmddr = 0
6874 14:44:30.368440 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6875 14:44:30.375202 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6876 14:44:30.375297 MEM_TYPE=3, freq_sel=13
6877 14:44:30.378737 sv_algorithm_assistance_LP4_3733
6878 14:44:30.384983 ============ PULL DRAM RESETB DOWN ============
6879 14:44:30.388167 ========== PULL DRAM RESETB DOWN end =========
6880 14:44:30.391772 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6881 14:44:30.395060 ===================================
6882 14:44:30.398362 LPDDR4 DRAM CONFIGURATION
6883 14:44:30.401838 ===================================
6884 14:44:30.401927 EX_ROW_EN[0] = 0x0
6885 14:44:30.404784 EX_ROW_EN[1] = 0x0
6886 14:44:30.408219 LP4Y_EN = 0x0
6887 14:44:30.408303 WORK_FSP = 0x1
6888 14:44:30.411542 WL = 0x5
6889 14:44:30.411625 RL = 0x5
6890 14:44:30.414959 BL = 0x2
6891 14:44:30.415047 RPST = 0x0
6892 14:44:30.418273 RD_PRE = 0x0
6893 14:44:30.418362 WR_PRE = 0x1
6894 14:44:30.421453 WR_PST = 0x1
6895 14:44:30.421570 DBI_WR = 0x0
6896 14:44:30.424574 DBI_RD = 0x0
6897 14:44:30.424681 OTF = 0x1
6898 14:44:30.427882 ===================================
6899 14:44:30.431401 ===================================
6900 14:44:30.434613 ANA top config
6901 14:44:30.438136 ===================================
6902 14:44:30.438226 DLL_ASYNC_EN = 0
6903 14:44:30.441409 ALL_SLAVE_EN = 0
6904 14:44:30.444483 NEW_RANK_MODE = 1
6905 14:44:30.447839 DLL_IDLE_MODE = 1
6906 14:44:30.451326 LP45_APHY_COMB_EN = 1
6907 14:44:30.451415 TX_ODT_DIS = 0
6908 14:44:30.454341 NEW_8X_MODE = 1
6909 14:44:30.457647 ===================================
6910 14:44:30.461221 ===================================
6911 14:44:30.464300 data_rate = 3200
6912 14:44:30.467737 CKR = 1
6913 14:44:30.471098 DQ_P2S_RATIO = 8
6914 14:44:30.474419 ===================================
6915 14:44:30.477515 CA_P2S_RATIO = 8
6916 14:44:30.477600 DQ_CA_OPEN = 0
6917 14:44:30.480770 DQ_SEMI_OPEN = 0
6918 14:44:30.484200 CA_SEMI_OPEN = 0
6919 14:44:30.487439 CA_FULL_RATE = 0
6920 14:44:30.490664 DQ_CKDIV4_EN = 0
6921 14:44:30.494552 CA_CKDIV4_EN = 0
6922 14:44:30.494658 CA_PREDIV_EN = 0
6923 14:44:30.497454 PH8_DLY = 12
6924 14:44:30.500794 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6925 14:44:30.503889 DQ_AAMCK_DIV = 4
6926 14:44:30.507316 CA_AAMCK_DIV = 4
6927 14:44:30.510633 CA_ADMCK_DIV = 4
6928 14:44:30.510719 DQ_TRACK_CA_EN = 0
6929 14:44:30.514190 CA_PICK = 1600
6930 14:44:30.517275 CA_MCKIO = 1600
6931 14:44:30.520441 MCKIO_SEMI = 0
6932 14:44:30.523874 PLL_FREQ = 3068
6933 14:44:30.527045 DQ_UI_PI_RATIO = 32
6934 14:44:30.530458 CA_UI_PI_RATIO = 0
6935 14:44:30.533885 ===================================
6936 14:44:30.537063 ===================================
6937 14:44:30.537185 memory_type:LPDDR4
6938 14:44:30.540288 GP_NUM : 10
6939 14:44:30.543558 SRAM_EN : 1
6940 14:44:30.543649 MD32_EN : 0
6941 14:44:30.546775 ===================================
6942 14:44:30.550152 [ANA_INIT] >>>>>>>>>>>>>>
6943 14:44:30.553709 <<<<<< [CONFIGURE PHASE]: ANA_TX
6944 14:44:30.556699 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6945 14:44:30.560214 ===================================
6946 14:44:30.563476 data_rate = 3200,PCW = 0X7600
6947 14:44:30.566700 ===================================
6948 14:44:30.569935 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6949 14:44:30.573196 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6950 14:44:30.579767 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6951 14:44:30.586508 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6952 14:44:30.589667 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6953 14:44:30.593003 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6954 14:44:30.593088 [ANA_INIT] flow start
6955 14:44:30.596484 [ANA_INIT] PLL >>>>>>>>
6956 14:44:30.599688 [ANA_INIT] PLL <<<<<<<<
6957 14:44:30.599775 [ANA_INIT] MIDPI >>>>>>>>
6958 14:44:30.603090 [ANA_INIT] MIDPI <<<<<<<<
6959 14:44:30.606219 [ANA_INIT] DLL >>>>>>>>
6960 14:44:30.606305 [ANA_INIT] DLL <<<<<<<<
6961 14:44:30.609495 [ANA_INIT] flow end
6962 14:44:30.613121 ============ LP4 DIFF to SE enter ============
6963 14:44:30.616190 ============ LP4 DIFF to SE exit ============
6964 14:44:30.619614 [ANA_INIT] <<<<<<<<<<<<<
6965 14:44:30.622745 [Flow] Enable top DCM control >>>>>
6966 14:44:30.626097 [Flow] Enable top DCM control <<<<<
6967 14:44:30.629377 Enable DLL master slave shuffle
6968 14:44:30.636162 ==============================================================
6969 14:44:30.636278 Gating Mode config
6970 14:44:30.642513 ==============================================================
6971 14:44:30.645847 Config description:
6972 14:44:30.652495 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6973 14:44:30.658986 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6974 14:44:30.665625 SELPH_MODE 0: By rank 1: By Phase
6975 14:44:30.672428 ==============================================================
6976 14:44:30.672547 GAT_TRACK_EN = 1
6977 14:44:30.675558 RX_GATING_MODE = 2
6978 14:44:30.678918 RX_GATING_TRACK_MODE = 2
6979 14:44:30.682231 SELPH_MODE = 1
6980 14:44:30.685521 PICG_EARLY_EN = 1
6981 14:44:30.688964 VALID_LAT_VALUE = 1
6982 14:44:30.695549 ==============================================================
6983 14:44:30.698740 Enter into Gating configuration >>>>
6984 14:44:30.702095 Exit from Gating configuration <<<<
6985 14:44:30.705189 Enter into DVFS_PRE_config >>>>>
6986 14:44:30.715567 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6987 14:44:30.718780 Exit from DVFS_PRE_config <<<<<
6988 14:44:30.722247 Enter into PICG configuration >>>>
6989 14:44:30.725315 Exit from PICG configuration <<<<
6990 14:44:30.728486 [RX_INPUT] configuration >>>>>
6991 14:44:30.731881 [RX_INPUT] configuration <<<<<
6992 14:44:30.735272 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6993 14:44:30.741848 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6994 14:44:30.748503 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6995 14:44:30.751925 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6996 14:44:30.758275 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6997 14:44:30.765224 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6998 14:44:30.768275 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6999 14:44:30.775077 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7000 14:44:30.778264 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7001 14:44:30.781615 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7002 14:44:30.784854 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7003 14:44:30.791551 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7004 14:44:30.794736 ===================================
7005 14:44:30.794859 LPDDR4 DRAM CONFIGURATION
7006 14:44:30.798044 ===================================
7007 14:44:30.801402 EX_ROW_EN[0] = 0x0
7008 14:44:30.805131 EX_ROW_EN[1] = 0x0
7009 14:44:30.805219 LP4Y_EN = 0x0
7010 14:44:30.807950 WORK_FSP = 0x1
7011 14:44:30.808033 WL = 0x5
7012 14:44:30.811347 RL = 0x5
7013 14:44:30.811432 BL = 0x2
7014 14:44:30.814521 RPST = 0x0
7015 14:44:30.814605 RD_PRE = 0x0
7016 14:44:30.817972 WR_PRE = 0x1
7017 14:44:30.818061 WR_PST = 0x1
7018 14:44:30.821283 DBI_WR = 0x0
7019 14:44:30.821403 DBI_RD = 0x0
7020 14:44:30.824530 OTF = 0x1
7021 14:44:30.828036 ===================================
7022 14:44:30.831222 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7023 14:44:30.834472 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7024 14:44:30.841225 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7025 14:44:30.844168 ===================================
7026 14:44:30.844262 LPDDR4 DRAM CONFIGURATION
7027 14:44:30.847524 ===================================
7028 14:44:30.851044 EX_ROW_EN[0] = 0x10
7029 14:44:30.854404 EX_ROW_EN[1] = 0x0
7030 14:44:30.854489 LP4Y_EN = 0x0
7031 14:44:30.857517 WORK_FSP = 0x1
7032 14:44:30.857600 WL = 0x5
7033 14:44:30.860828 RL = 0x5
7034 14:44:30.860911 BL = 0x2
7035 14:44:30.864195 RPST = 0x0
7036 14:44:30.864279 RD_PRE = 0x0
7037 14:44:30.867475 WR_PRE = 0x1
7038 14:44:30.867558 WR_PST = 0x1
7039 14:44:30.870861 DBI_WR = 0x0
7040 14:44:30.870945 DBI_RD = 0x0
7041 14:44:30.874107 OTF = 0x1
7042 14:44:30.877346 ===================================
7043 14:44:30.883732 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7044 14:44:30.883828 ==
7045 14:44:30.887169 Dram Type= 6, Freq= 0, CH_0, rank 0
7046 14:44:30.890607 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7047 14:44:30.890694 ==
7048 14:44:30.893946 [Duty_Offset_Calibration]
7049 14:44:30.894029 B0:0 B1:2 CA:1
7050 14:44:30.894093
7051 14:44:30.897192 [DutyScan_Calibration_Flow] k_type=0
7052 14:44:30.908023
7053 14:44:30.908150 ==CLK 0==
7054 14:44:30.911413 Final CLK duty delay cell = 0
7055 14:44:30.914838 [0] MAX Duty = 5187%(X100), DQS PI = 24
7056 14:44:30.918110 [0] MIN Duty = 4938%(X100), DQS PI = 54
7057 14:44:30.921136 [0] AVG Duty = 5062%(X100)
7058 14:44:30.921228
7059 14:44:30.924487 CH0 CLK Duty spec in!! Max-Min= 249%
7060 14:44:30.928147 [DutyScan_Calibration_Flow] ====Done====
7061 14:44:30.928235
7062 14:44:30.931120 [DutyScan_Calibration_Flow] k_type=1
7063 14:44:30.948406
7064 14:44:30.948556 ==DQS 0 ==
7065 14:44:30.951392 Final DQS duty delay cell = 0
7066 14:44:30.954723 [0] MAX Duty = 5125%(X100), DQS PI = 2
7067 14:44:30.957938 [0] MIN Duty = 5031%(X100), DQS PI = 8
7068 14:44:30.958026 [0] AVG Duty = 5078%(X100)
7069 14:44:30.961293
7070 14:44:30.961377 ==DQS 1 ==
7071 14:44:30.964696 Final DQS duty delay cell = 0
7072 14:44:30.968268 [0] MAX Duty = 5031%(X100), DQS PI = 6
7073 14:44:30.971149 [0] MIN Duty = 4876%(X100), DQS PI = 18
7074 14:44:30.971236 [0] AVG Duty = 4953%(X100)
7075 14:44:30.974672
7076 14:44:30.977896 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7077 14:44:30.977982
7078 14:44:30.981124 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7079 14:44:30.984630 [DutyScan_Calibration_Flow] ====Done====
7080 14:44:30.984718
7081 14:44:30.987710 [DutyScan_Calibration_Flow] k_type=3
7082 14:44:31.004991
7083 14:44:31.005146 ==DQM 0 ==
7084 14:44:31.008267 Final DQM duty delay cell = 0
7085 14:44:31.011426 [0] MAX Duty = 5187%(X100), DQS PI = 22
7086 14:44:31.015104 [0] MIN Duty = 4907%(X100), DQS PI = 42
7087 14:44:31.018578 [0] AVG Duty = 5047%(X100)
7088 14:44:31.018710
7089 14:44:31.018806 ==DQM 1 ==
7090 14:44:31.021699 Final DQM duty delay cell = 0
7091 14:44:31.024923 [0] MAX Duty = 5031%(X100), DQS PI = 50
7092 14:44:31.028345 [0] MIN Duty = 4782%(X100), DQS PI = 14
7093 14:44:31.031438 [0] AVG Duty = 4906%(X100)
7094 14:44:31.031528
7095 14:44:31.034969 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7096 14:44:31.035054
7097 14:44:31.038304 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7098 14:44:31.041487 [DutyScan_Calibration_Flow] ====Done====
7099 14:44:31.041574
7100 14:44:31.044720 [DutyScan_Calibration_Flow] k_type=2
7101 14:44:31.061687
7102 14:44:31.061837 ==DQ 0 ==
7103 14:44:31.064674 Final DQ duty delay cell = 0
7104 14:44:31.067897 [0] MAX Duty = 5218%(X100), DQS PI = 18
7105 14:44:31.071280 [0] MIN Duty = 4938%(X100), DQS PI = 56
7106 14:44:31.071368 [0] AVG Duty = 5078%(X100)
7107 14:44:31.074540
7108 14:44:31.074623 ==DQ 1 ==
7109 14:44:31.077763 Final DQ duty delay cell = -4
7110 14:44:31.081131 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7111 14:44:31.084401 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7112 14:44:31.087790 [-4] AVG Duty = 4953%(X100)
7113 14:44:31.087875
7114 14:44:31.091103 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7115 14:44:31.091187
7116 14:44:31.094442 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7117 14:44:31.097873 [DutyScan_Calibration_Flow] ====Done====
7118 14:44:31.097960 ==
7119 14:44:31.101145 Dram Type= 6, Freq= 0, CH_1, rank 0
7120 14:44:31.104315 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7121 14:44:31.104402 ==
7122 14:44:31.107564 [Duty_Offset_Calibration]
7123 14:44:31.107647 B0:0 B1:5 CA:-5
7124 14:44:31.107711
7125 14:44:31.110960 [DutyScan_Calibration_Flow] k_type=0
7126 14:44:31.121948
7127 14:44:31.122086 ==CLK 0==
7128 14:44:31.125125 Final CLK duty delay cell = 0
7129 14:44:31.128557 [0] MAX Duty = 5187%(X100), DQS PI = 20
7130 14:44:31.131961 [0] MIN Duty = 4906%(X100), DQS PI = 50
7131 14:44:31.135104 [0] AVG Duty = 5046%(X100)
7132 14:44:31.135191
7133 14:44:31.138538 CH1 CLK Duty spec in!! Max-Min= 281%
7134 14:44:31.141930 [DutyScan_Calibration_Flow] ====Done====
7135 14:44:31.142020
7136 14:44:31.145032 [DutyScan_Calibration_Flow] k_type=1
7137 14:44:31.160792
7138 14:44:31.160940 ==DQS 0 ==
7139 14:44:31.164062 Final DQS duty delay cell = 0
7140 14:44:31.167373 [0] MAX Duty = 5156%(X100), DQS PI = 20
7141 14:44:31.171164 [0] MIN Duty = 4876%(X100), DQS PI = 42
7142 14:44:31.174493 [0] AVG Duty = 5016%(X100)
7143 14:44:31.174581
7144 14:44:31.174644 ==DQS 1 ==
7145 14:44:31.177524 Final DQS duty delay cell = -4
7146 14:44:31.180646 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7147 14:44:31.184072 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7148 14:44:31.187317 [-4] AVG Duty = 4922%(X100)
7149 14:44:31.187404
7150 14:44:31.190709 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7151 14:44:31.190794
7152 14:44:31.193990 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7153 14:44:31.197326 [DutyScan_Calibration_Flow] ====Done====
7154 14:44:31.197411
7155 14:44:31.200809 [DutyScan_Calibration_Flow] k_type=3
7156 14:44:31.216509
7157 14:44:31.216658 ==DQM 0 ==
7158 14:44:31.219825 Final DQM duty delay cell = -4
7159 14:44:31.222972 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7160 14:44:31.226499 [-4] MIN Duty = 4813%(X100), DQS PI = 42
7161 14:44:31.229799 [-4] AVG Duty = 4937%(X100)
7162 14:44:31.229889
7163 14:44:31.229970 ==DQM 1 ==
7164 14:44:31.233055 Final DQM duty delay cell = -4
7165 14:44:31.236353 [-4] MAX Duty = 5062%(X100), DQS PI = 2
7166 14:44:31.239726 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7167 14:44:31.242876 [-4] AVG Duty = 4984%(X100)
7168 14:44:31.242961
7169 14:44:31.246457 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7170 14:44:31.246541
7171 14:44:31.249574 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7172 14:44:31.252734 [DutyScan_Calibration_Flow] ====Done====
7173 14:44:31.252819
7174 14:44:31.256142 [DutyScan_Calibration_Flow] k_type=2
7175 14:44:31.274422
7176 14:44:31.274575 ==DQ 0 ==
7177 14:44:31.277284 Final DQ duty delay cell = 0
7178 14:44:31.280710 [0] MAX Duty = 5093%(X100), DQS PI = 34
7179 14:44:31.284106 [0] MIN Duty = 4938%(X100), DQS PI = 48
7180 14:44:31.284194 [0] AVG Duty = 5015%(X100)
7181 14:44:31.287596
7182 14:44:31.287680 ==DQ 1 ==
7183 14:44:31.290727 Final DQ duty delay cell = 0
7184 14:44:31.293975 [0] MAX Duty = 5031%(X100), DQS PI = 2
7185 14:44:31.297516 [0] MIN Duty = 4875%(X100), DQS PI = 28
7186 14:44:31.297603 [0] AVG Duty = 4953%(X100)
7187 14:44:31.297668
7188 14:44:31.304184 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7189 14:44:31.304292
7190 14:44:31.307249 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7191 14:44:31.310424 [DutyScan_Calibration_Flow] ====Done====
7192 14:44:31.313705 nWR fixed to 30
7193 14:44:31.313793 [ModeRegInit_LP4] CH0 RK0
7194 14:44:31.316969 [ModeRegInit_LP4] CH0 RK1
7195 14:44:31.320454 [ModeRegInit_LP4] CH1 RK0
7196 14:44:31.323795 [ModeRegInit_LP4] CH1 RK1
7197 14:44:31.323884 match AC timing 4
7198 14:44:31.327125 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7199 14:44:31.333723 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7200 14:44:31.337030 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7201 14:44:31.343561 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7202 14:44:31.347614 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7203 14:44:31.347706 [MiockJmeterHQA]
7204 14:44:31.347770
7205 14:44:31.350322 [DramcMiockJmeter] u1RxGatingPI = 0
7206 14:44:31.353918 0 : 4365, 4137
7207 14:44:31.354005 4 : 4252, 4027
7208 14:44:31.357016 8 : 4363, 4138
7209 14:44:31.357101 12 : 4363, 4138
7210 14:44:31.357167 16 : 4252, 4026
7211 14:44:31.360207 20 : 4252, 4027
7212 14:44:31.360293 24 : 4253, 4026
7213 14:44:31.363554 28 : 4252, 4027
7214 14:44:31.363638 32 : 4252, 4027
7215 14:44:31.366874 36 : 4255, 4029
7216 14:44:31.366959 40 : 4363, 4137
7217 14:44:31.367025 44 : 4252, 4027
7218 14:44:31.370429 48 : 4252, 4027
7219 14:44:31.370513 52 : 4255, 4029
7220 14:44:31.373610 56 : 4255, 4030
7221 14:44:31.373696 60 : 4249, 4027
7222 14:44:31.376929 64 : 4363, 4139
7223 14:44:31.377015 68 : 4361, 4137
7224 14:44:31.380214 72 : 4253, 4029
7225 14:44:31.380300 76 : 4250, 4027
7226 14:44:31.380366 80 : 4250, 4027
7227 14:44:31.383458 84 : 4250, 4027
7228 14:44:31.383542 88 : 4253, 4029
7229 14:44:31.386657 92 : 4360, 4137
7230 14:44:31.386742 96 : 4250, 4026
7231 14:44:31.390380 100 : 4250, 1827
7232 14:44:31.390465 104 : 4360, 0
7233 14:44:31.390532 108 : 4363, 0
7234 14:44:31.393545 112 : 4252, 0
7235 14:44:31.393629 116 : 4250, 0
7236 14:44:31.396877 120 : 4363, 0
7237 14:44:31.396961 124 : 4250, 0
7238 14:44:31.397026 128 : 4250, 0
7239 14:44:31.400060 132 : 4250, 0
7240 14:44:31.400145 136 : 4253, 0
7241 14:44:31.403241 140 : 4250, 0
7242 14:44:31.403325 144 : 4250, 0
7243 14:44:31.403391 148 : 4253, 0
7244 14:44:31.406712 152 : 4360, 0
7245 14:44:31.406807 156 : 4361, 0
7246 14:44:31.409943 160 : 4363, 0
7247 14:44:31.410028 164 : 4250, 0
7248 14:44:31.410094 168 : 4250, 0
7249 14:44:31.413424 172 : 4250, 0
7250 14:44:31.413508 176 : 4250, 0
7251 14:44:31.416545 180 : 4250, 0
7252 14:44:31.416630 184 : 4250, 0
7253 14:44:31.416696 188 : 4253, 0
7254 14:44:31.420113 192 : 4250, 0
7255 14:44:31.420205 196 : 4250, 0
7256 14:44:31.420271 200 : 4253, 0
7257 14:44:31.423129 204 : 4360, 0
7258 14:44:31.423216 208 : 4361, 0
7259 14:44:31.426369 212 : 4363, 0
7260 14:44:31.426454 216 : 4250, 0
7261 14:44:31.426520 220 : 4250, 602
7262 14:44:31.429777 224 : 4250, 4002
7263 14:44:31.429862 228 : 4361, 4137
7264 14:44:31.433097 232 : 4250, 4027
7265 14:44:31.433209 236 : 4250, 4027
7266 14:44:31.436347 240 : 4250, 4026
7267 14:44:31.436433 244 : 4252, 4029
7268 14:44:31.439835 248 : 4250, 4026
7269 14:44:31.439920 252 : 4250, 4027
7270 14:44:31.442969 256 : 4360, 4137
7271 14:44:31.443056 260 : 4249, 4027
7272 14:44:31.446332 264 : 4250, 4026
7273 14:44:31.446419 268 : 4361, 4137
7274 14:44:31.449734 272 : 4250, 4027
7275 14:44:31.449820 276 : 4250, 4026
7276 14:44:31.449885 280 : 4362, 4140
7277 14:44:31.453276 284 : 4361, 4137
7278 14:44:31.453401 288 : 4250, 4027
7279 14:44:31.456692 292 : 4250, 4026
7280 14:44:31.456778 296 : 4253, 4029
7281 14:44:31.459721 300 : 4250, 4027
7282 14:44:31.459806 304 : 4250, 4027
7283 14:44:31.463059 308 : 4360, 4138
7284 14:44:31.463144 312 : 4249, 4027
7285 14:44:31.466402 316 : 4250, 4027
7286 14:44:31.466487 320 : 4361, 4137
7287 14:44:31.469755 324 : 4249, 4027
7288 14:44:31.469841 328 : 4250, 4026
7289 14:44:31.473232 332 : 4363, 4140
7290 14:44:31.473373 336 : 4250, 3847
7291 14:44:31.473440 340 : 4250, 1989
7292 14:44:31.476365
7293 14:44:31.476448 MIOCK jitter meter ch=0
7294 14:44:31.476513
7295 14:44:31.479593 1T = (340-100) = 240 dly cells
7296 14:44:31.486098 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7297 14:44:31.486201 ==
7298 14:44:31.489644 Dram Type= 6, Freq= 0, CH_0, rank 0
7299 14:44:31.492874 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7300 14:44:31.492959 ==
7301 14:44:31.499421 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7302 14:44:31.502847 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7303 14:44:31.506209 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7304 14:44:31.512608 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7305 14:44:31.521264 [CA 0] Center 41 (11~72) winsize 62
7306 14:44:31.524490 [CA 1] Center 41 (11~72) winsize 62
7307 14:44:31.527899 [CA 2] Center 37 (7~68) winsize 62
7308 14:44:31.531171 [CA 3] Center 37 (7~67) winsize 61
7309 14:44:31.534704 [CA 4] Center 35 (5~66) winsize 62
7310 14:44:31.538065 [CA 5] Center 35 (5~65) winsize 61
7311 14:44:31.538155
7312 14:44:31.541307 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7313 14:44:31.541394
7314 14:44:31.544474 [CATrainingPosCal] consider 1 rank data
7315 14:44:31.547850 u2DelayCellTimex100 = 271/100 ps
7316 14:44:31.551292 CA0 delay=41 (11~72),Diff = 6 PI (21 cell)
7317 14:44:31.558309 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7318 14:44:31.561490 CA2 delay=37 (7~68),Diff = 2 PI (7 cell)
7319 14:44:31.564473 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7320 14:44:31.567768 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7321 14:44:31.571281 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7322 14:44:31.571369
7323 14:44:31.574487 CA PerBit enable=1, Macro0, CA PI delay=35
7324 14:44:31.574573
7325 14:44:31.577692 [CBTSetCACLKResult] CA Dly = 35
7326 14:44:31.581230 CS Dly: 11 (0~42)
7327 14:44:31.584360 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7328 14:44:31.587853 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7329 14:44:31.587942 ==
7330 14:44:31.591150 Dram Type= 6, Freq= 0, CH_0, rank 1
7331 14:44:31.594271 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7332 14:44:31.597503 ==
7333 14:44:31.600917 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7334 14:44:31.604079 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7335 14:44:31.610827 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7336 14:44:31.614289 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7337 14:44:31.624123 [CA 0] Center 42 (12~73) winsize 62
7338 14:44:31.627043 [CA 1] Center 41 (11~72) winsize 62
7339 14:44:31.630678 [CA 2] Center 38 (8~68) winsize 61
7340 14:44:31.633682 [CA 3] Center 37 (7~67) winsize 61
7341 14:44:31.637469 [CA 4] Center 35 (5~65) winsize 61
7342 14:44:31.640185 [CA 5] Center 35 (5~66) winsize 62
7343 14:44:31.640298
7344 14:44:31.643713 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7345 14:44:31.643799
7346 14:44:31.646865 [CATrainingPosCal] consider 2 rank data
7347 14:44:31.650835 u2DelayCellTimex100 = 271/100 ps
7348 14:44:31.653791 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7349 14:44:31.660416 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7350 14:44:31.663692 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7351 14:44:31.667087 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7352 14:44:31.670394 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
7353 14:44:31.673811 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7354 14:44:31.673907
7355 14:44:31.676845 CA PerBit enable=1, Macro0, CA PI delay=35
7356 14:44:31.676931
7357 14:44:31.680239 [CBTSetCACLKResult] CA Dly = 35
7358 14:44:31.683465 CS Dly: 11 (0~43)
7359 14:44:31.687093 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7360 14:44:31.690217 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7361 14:44:31.690323
7362 14:44:31.693588 ----->DramcWriteLeveling(PI) begin...
7363 14:44:31.693674 ==
7364 14:44:31.696715 Dram Type= 6, Freq= 0, CH_0, rank 0
7365 14:44:31.703278 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7366 14:44:31.703381 ==
7367 14:44:31.706491 Write leveling (Byte 0): 31 => 31
7368 14:44:31.706577 Write leveling (Byte 1): 26 => 26
7369 14:44:31.710087 DramcWriteLeveling(PI) end<-----
7370 14:44:31.710198
7371 14:44:31.713257 ==
7372 14:44:31.713481 Dram Type= 6, Freq= 0, CH_0, rank 0
7373 14:44:31.719897 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7374 14:44:31.720020 ==
7375 14:44:31.723431 [Gating] SW mode calibration
7376 14:44:31.729759 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7377 14:44:31.733050 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7378 14:44:31.740037 0 12 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7379 14:44:31.743033 0 12 4 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)
7380 14:44:31.746391 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7381 14:44:31.752931 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7382 14:44:31.756399 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7383 14:44:31.759915 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7384 14:44:31.766406 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7385 14:44:31.769451 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
7386 14:44:31.773044 0 13 0 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
7387 14:44:31.779398 0 13 4 | B1->B0 | 3232 2323 | 0 0 | (1 0) (0 0)
7388 14:44:31.782744 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7389 14:44:31.786254 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7390 14:44:31.793004 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7391 14:44:31.796100 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7392 14:44:31.799443 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7393 14:44:31.805914 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7394 14:44:31.809166 0 14 0 | B1->B0 | 2424 3a3a | 0 0 | (0 0) (0 0)
7395 14:44:31.812717 0 14 4 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
7396 14:44:31.819102 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7397 14:44:31.822550 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7398 14:44:31.825843 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7399 14:44:31.832426 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7400 14:44:31.835686 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7401 14:44:31.839080 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7402 14:44:31.845570 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7403 14:44:31.848831 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7404 14:44:31.852391 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7405 14:44:31.858903 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7406 14:44:31.862537 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7407 14:44:31.865836 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7408 14:44:31.872298 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7409 14:44:31.875414 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7410 14:44:31.878694 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7411 14:44:31.885118 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7412 14:44:31.888662 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7413 14:44:31.891983 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7414 14:44:31.895358 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7415 14:44:31.901831 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7416 14:44:31.905175 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7417 14:44:31.908685 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7418 14:44:31.914999 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7419 14:44:31.918358 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7420 14:44:31.921736 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7421 14:44:31.925153 Total UI for P1: 0, mck2ui 16
7422 14:44:31.928610 best dqsien dly found for B0: ( 1, 1, 0)
7423 14:44:31.935104 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7424 14:44:31.938457 Total UI for P1: 0, mck2ui 16
7425 14:44:31.941293 best dqsien dly found for B1: ( 1, 1, 4)
7426 14:44:31.944631 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7427 14:44:31.948265 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7428 14:44:31.948359
7429 14:44:31.951480 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7430 14:44:31.955018 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7431 14:44:31.957847 [Gating] SW calibration Done
7432 14:44:31.957934 ==
7433 14:44:31.961011 Dram Type= 6, Freq= 0, CH_0, rank 0
7434 14:44:31.964584 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7435 14:44:31.964674 ==
7436 14:44:31.967740 RX Vref Scan: 0
7437 14:44:31.967825
7438 14:44:31.967890 RX Vref 0 -> 0, step: 1
7439 14:44:31.967950
7440 14:44:31.971104 RX Delay 0 -> 252, step: 8
7441 14:44:31.975045 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7442 14:44:31.981203 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7443 14:44:31.984453 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7444 14:44:31.987689 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7445 14:44:31.991075 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7446 14:44:31.994200 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
7447 14:44:32.000894 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7448 14:44:32.004385 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7449 14:44:32.007482 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7450 14:44:32.010815 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7451 14:44:32.014027 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7452 14:44:32.020855 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7453 14:44:32.024072 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7454 14:44:32.027381 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7455 14:44:32.030613 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7456 14:44:32.037456 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7457 14:44:32.037568 ==
7458 14:44:32.040563 Dram Type= 6, Freq= 0, CH_0, rank 0
7459 14:44:32.043977 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7460 14:44:32.044068 ==
7461 14:44:32.044134 DQS Delay:
7462 14:44:32.047169 DQS0 = 0, DQS1 = 0
7463 14:44:32.047255 DQM Delay:
7464 14:44:32.050402 DQM0 = 129, DQM1 = 124
7465 14:44:32.050489 DQ Delay:
7466 14:44:32.053957 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =127
7467 14:44:32.057075 DQ4 =135, DQ5 =115, DQ6 =139, DQ7 =139
7468 14:44:32.060364 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
7469 14:44:32.063890 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7470 14:44:32.063979
7471 14:44:32.064044
7472 14:44:32.066979 ==
7473 14:44:32.070326 Dram Type= 6, Freq= 0, CH_0, rank 0
7474 14:44:32.073975 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7475 14:44:32.074064 ==
7476 14:44:32.074130
7477 14:44:32.074190
7478 14:44:32.077184 TX Vref Scan disable
7479 14:44:32.077267 == TX Byte 0 ==
7480 14:44:32.080317 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7481 14:44:32.087001 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7482 14:44:32.087099 == TX Byte 1 ==
7483 14:44:32.093654 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7484 14:44:32.097071 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7485 14:44:32.097161 ==
7486 14:44:32.100096 Dram Type= 6, Freq= 0, CH_0, rank 0
7487 14:44:32.103551 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7488 14:44:32.103639 ==
7489 14:44:32.117085
7490 14:44:32.120321 TX Vref early break, caculate TX vref
7491 14:44:32.123862 TX Vref=16, minBit 8, minWin=22, winSum=373
7492 14:44:32.127007 TX Vref=18, minBit 8, minWin=22, winSum=380
7493 14:44:32.130214 TX Vref=20, minBit 8, minWin=23, winSum=386
7494 14:44:32.133442 TX Vref=22, minBit 8, minWin=23, winSum=397
7495 14:44:32.136722 TX Vref=24, minBit 9, minWin=24, winSum=406
7496 14:44:32.143686 TX Vref=26, minBit 8, minWin=24, winSum=411
7497 14:44:32.146834 TX Vref=28, minBit 0, minWin=25, winSum=413
7498 14:44:32.150243 TX Vref=30, minBit 3, minWin=24, winSum=409
7499 14:44:32.153432 TX Vref=32, minBit 8, minWin=23, winSum=397
7500 14:44:32.156721 TX Vref=34, minBit 7, minWin=23, winSum=390
7501 14:44:32.163314 [TxChooseVref] Worse bit 0, Min win 25, Win sum 413, Final Vref 28
7502 14:44:32.163439
7503 14:44:32.166695 Final TX Range 0 Vref 28
7504 14:44:32.166781
7505 14:44:32.166845 ==
7506 14:44:32.169920 Dram Type= 6, Freq= 0, CH_0, rank 0
7507 14:44:32.173258 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7508 14:44:32.173404 ==
7509 14:44:32.173472
7510 14:44:32.173532
7511 14:44:32.176615 TX Vref Scan disable
7512 14:44:32.183052 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7513 14:44:32.183181 == TX Byte 0 ==
7514 14:44:32.186607 u2DelayCellOfst[0]=14 cells (4 PI)
7515 14:44:32.189824 u2DelayCellOfst[1]=18 cells (5 PI)
7516 14:44:32.193190 u2DelayCellOfst[2]=14 cells (4 PI)
7517 14:44:32.196438 u2DelayCellOfst[3]=10 cells (3 PI)
7518 14:44:32.199880 u2DelayCellOfst[4]=10 cells (3 PI)
7519 14:44:32.203040 u2DelayCellOfst[5]=0 cells (0 PI)
7520 14:44:32.206313 u2DelayCellOfst[6]=18 cells (5 PI)
7521 14:44:32.209772 u2DelayCellOfst[7]=18 cells (5 PI)
7522 14:44:32.212939 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7523 14:44:32.216811 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7524 14:44:32.219383 == TX Byte 1 ==
7525 14:44:32.222824 u2DelayCellOfst[8]=3 cells (1 PI)
7526 14:44:32.226292 u2DelayCellOfst[9]=0 cells (0 PI)
7527 14:44:32.226379 u2DelayCellOfst[10]=10 cells (3 PI)
7528 14:44:32.229272 u2DelayCellOfst[11]=7 cells (2 PI)
7529 14:44:32.232668 u2DelayCellOfst[12]=14 cells (4 PI)
7530 14:44:32.236054 u2DelayCellOfst[13]=18 cells (5 PI)
7531 14:44:32.239277 u2DelayCellOfst[14]=18 cells (5 PI)
7532 14:44:32.242868 u2DelayCellOfst[15]=18 cells (5 PI)
7533 14:44:32.249430 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7534 14:44:32.252809 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7535 14:44:32.252902 DramC Write-DBI on
7536 14:44:32.252966 ==
7537 14:44:32.256099 Dram Type= 6, Freq= 0, CH_0, rank 0
7538 14:44:32.262411 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7539 14:44:32.262513 ==
7540 14:44:32.262597
7541 14:44:32.262693
7542 14:44:32.262788 TX Vref Scan disable
7543 14:44:32.266706 == TX Byte 0 ==
7544 14:44:32.270125 Update DQM dly =730 (2 ,6, 26) DQM OEN =(3 ,3)
7545 14:44:32.273306 == TX Byte 1 ==
7546 14:44:32.276632 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7547 14:44:32.280024 DramC Write-DBI off
7548 14:44:32.280112
7549 14:44:32.280175 [DATLAT]
7550 14:44:32.280235 Freq=1600, CH0 RK0
7551 14:44:32.280293
7552 14:44:32.283177 DATLAT Default: 0xf
7553 14:44:32.286675 0, 0xFFFF, sum = 0
7554 14:44:32.286763 1, 0xFFFF, sum = 0
7555 14:44:32.290023 2, 0xFFFF, sum = 0
7556 14:44:32.290107 3, 0xFFFF, sum = 0
7557 14:44:32.293281 4, 0xFFFF, sum = 0
7558 14:44:32.293375 5, 0xFFFF, sum = 0
7559 14:44:32.296440 6, 0xFFFF, sum = 0
7560 14:44:32.296524 7, 0xFFFF, sum = 0
7561 14:44:32.299967 8, 0xFFFF, sum = 0
7562 14:44:32.300052 9, 0xFFFF, sum = 0
7563 14:44:32.303012 10, 0xFFFF, sum = 0
7564 14:44:32.303096 11, 0xFFFF, sum = 0
7565 14:44:32.306358 12, 0xBFF, sum = 0
7566 14:44:32.306443 13, 0x0, sum = 1
7567 14:44:32.309675 14, 0x0, sum = 2
7568 14:44:32.309761 15, 0x0, sum = 3
7569 14:44:32.313138 16, 0x0, sum = 4
7570 14:44:32.313223 best_step = 14
7571 14:44:32.313297
7572 14:44:32.313372 ==
7573 14:44:32.316375 Dram Type= 6, Freq= 0, CH_0, rank 0
7574 14:44:32.319485 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7575 14:44:32.323044 ==
7576 14:44:32.323161 RX Vref Scan: 1
7577 14:44:32.323255
7578 14:44:32.326180 Set Vref Range= 24 -> 127
7579 14:44:32.326265
7580 14:44:32.329648 RX Vref 24 -> 127, step: 1
7581 14:44:32.329750
7582 14:44:32.329847 RX Delay 11 -> 252, step: 4
7583 14:44:32.329926
7584 14:44:32.332790 Set Vref, RX VrefLevel [Byte0]: 24
7585 14:44:32.335984 [Byte1]: 24
7586 14:44:32.339972
7587 14:44:32.340063 Set Vref, RX VrefLevel [Byte0]: 25
7588 14:44:32.343229 [Byte1]: 25
7589 14:44:32.347505
7590 14:44:32.347595 Set Vref, RX VrefLevel [Byte0]: 26
7591 14:44:32.350966 [Byte1]: 26
7592 14:44:32.355152
7593 14:44:32.355241 Set Vref, RX VrefLevel [Byte0]: 27
7594 14:44:32.358672 [Byte1]: 27
7595 14:44:32.362785
7596 14:44:32.362874 Set Vref, RX VrefLevel [Byte0]: 28
7597 14:44:32.366098 [Byte1]: 28
7598 14:44:32.370519
7599 14:44:32.370610 Set Vref, RX VrefLevel [Byte0]: 29
7600 14:44:32.373715 [Byte1]: 29
7601 14:44:32.378188
7602 14:44:32.378284 Set Vref, RX VrefLevel [Byte0]: 30
7603 14:44:32.381283 [Byte1]: 30
7604 14:44:32.385685
7605 14:44:32.385789 Set Vref, RX VrefLevel [Byte0]: 31
7606 14:44:32.389098 [Byte1]: 31
7607 14:44:32.393444
7608 14:44:32.393521 Set Vref, RX VrefLevel [Byte0]: 32
7609 14:44:32.396656 [Byte1]: 32
7610 14:44:32.400953
7611 14:44:32.401033 Set Vref, RX VrefLevel [Byte0]: 33
7612 14:44:32.404508 [Byte1]: 33
7613 14:44:32.408632
7614 14:44:32.408713 Set Vref, RX VrefLevel [Byte0]: 34
7615 14:44:32.411857 [Byte1]: 34
7616 14:44:32.416208
7617 14:44:32.416299 Set Vref, RX VrefLevel [Byte0]: 35
7618 14:44:32.419346 [Byte1]: 35
7619 14:44:32.423924
7620 14:44:32.424027 Set Vref, RX VrefLevel [Byte0]: 36
7621 14:44:32.427096 [Byte1]: 36
7622 14:44:32.431405
7623 14:44:32.431493 Set Vref, RX VrefLevel [Byte0]: 37
7624 14:44:32.434496 [Byte1]: 37
7625 14:44:32.438889
7626 14:44:32.438979 Set Vref, RX VrefLevel [Byte0]: 38
7627 14:44:32.442210 [Byte1]: 38
7628 14:44:32.446502
7629 14:44:32.446589 Set Vref, RX VrefLevel [Byte0]: 39
7630 14:44:32.449773 [Byte1]: 39
7631 14:44:32.454049
7632 14:44:32.454138 Set Vref, RX VrefLevel [Byte0]: 40
7633 14:44:32.457583 [Byte1]: 40
7634 14:44:32.461697
7635 14:44:32.461785 Set Vref, RX VrefLevel [Byte0]: 41
7636 14:44:32.464997 [Byte1]: 41
7637 14:44:32.469295
7638 14:44:32.469381 Set Vref, RX VrefLevel [Byte0]: 42
7639 14:44:32.472665 [Byte1]: 42
7640 14:44:32.477216
7641 14:44:32.477314 Set Vref, RX VrefLevel [Byte0]: 43
7642 14:44:32.480249 [Byte1]: 43
7643 14:44:32.484556
7644 14:44:32.484645 Set Vref, RX VrefLevel [Byte0]: 44
7645 14:44:32.487912 [Byte1]: 44
7646 14:44:32.492193
7647 14:44:32.492281 Set Vref, RX VrefLevel [Byte0]: 45
7648 14:44:32.495615 [Byte1]: 45
7649 14:44:32.499900
7650 14:44:32.499988 Set Vref, RX VrefLevel [Byte0]: 46
7651 14:44:32.503192 [Byte1]: 46
7652 14:44:32.507575
7653 14:44:32.507662 Set Vref, RX VrefLevel [Byte0]: 47
7654 14:44:32.510826 [Byte1]: 47
7655 14:44:32.515051
7656 14:44:32.515141 Set Vref, RX VrefLevel [Byte0]: 48
7657 14:44:32.518289 [Byte1]: 48
7658 14:44:32.522880
7659 14:44:32.522981 Set Vref, RX VrefLevel [Byte0]: 49
7660 14:44:32.526074 [Byte1]: 49
7661 14:44:32.530545
7662 14:44:32.530641 Set Vref, RX VrefLevel [Byte0]: 50
7663 14:44:32.533658 [Byte1]: 50
7664 14:44:32.537880
7665 14:44:32.537969 Set Vref, RX VrefLevel [Byte0]: 51
7666 14:44:32.541140 [Byte1]: 51
7667 14:44:32.545721
7668 14:44:32.545810 Set Vref, RX VrefLevel [Byte0]: 52
7669 14:44:32.548852 [Byte1]: 52
7670 14:44:32.553052
7671 14:44:32.553140 Set Vref, RX VrefLevel [Byte0]: 53
7672 14:44:32.556314 [Byte1]: 53
7673 14:44:32.560814
7674 14:44:32.560900 Set Vref, RX VrefLevel [Byte0]: 54
7675 14:44:32.563915 [Byte1]: 54
7676 14:44:32.568411
7677 14:44:32.568498 Set Vref, RX VrefLevel [Byte0]: 55
7678 14:44:32.571532 [Byte1]: 55
7679 14:44:32.575883
7680 14:44:32.575971 Set Vref, RX VrefLevel [Byte0]: 56
7681 14:44:32.579231 [Byte1]: 56
7682 14:44:32.583678
7683 14:44:32.583765 Set Vref, RX VrefLevel [Byte0]: 57
7684 14:44:32.586890 [Byte1]: 57
7685 14:44:32.591112
7686 14:44:32.591196 Set Vref, RX VrefLevel [Byte0]: 58
7687 14:44:32.594561 [Byte1]: 58
7688 14:44:32.599051
7689 14:44:32.599138 Set Vref, RX VrefLevel [Byte0]: 59
7690 14:44:32.602186 [Byte1]: 59
7691 14:44:32.606362
7692 14:44:32.606450 Set Vref, RX VrefLevel [Byte0]: 60
7693 14:44:32.610030 [Byte1]: 60
7694 14:44:32.613976
7695 14:44:32.614062 Set Vref, RX VrefLevel [Byte0]: 61
7696 14:44:32.617199 [Byte1]: 61
7697 14:44:32.621642
7698 14:44:32.621740 Set Vref, RX VrefLevel [Byte0]: 62
7699 14:44:32.625148 [Byte1]: 62
7700 14:44:32.629144
7701 14:44:32.629225 Set Vref, RX VrefLevel [Byte0]: 63
7702 14:44:32.632979 [Byte1]: 63
7703 14:44:32.636791
7704 14:44:32.636877 Set Vref, RX VrefLevel [Byte0]: 64
7705 14:44:32.640218 [Byte1]: 64
7706 14:44:32.644676
7707 14:44:32.644765 Set Vref, RX VrefLevel [Byte0]: 65
7708 14:44:32.648072 [Byte1]: 65
7709 14:44:32.652194
7710 14:44:32.652283 Set Vref, RX VrefLevel [Byte0]: 66
7711 14:44:32.655330 [Byte1]: 66
7712 14:44:32.659700
7713 14:44:32.659789 Set Vref, RX VrefLevel [Byte0]: 67
7714 14:44:32.663183 [Byte1]: 67
7715 14:44:32.667326
7716 14:44:32.667410 Set Vref, RX VrefLevel [Byte0]: 68
7717 14:44:32.670650 [Byte1]: 68
7718 14:44:32.675120
7719 14:44:32.675205 Set Vref, RX VrefLevel [Byte0]: 69
7720 14:44:32.678267 [Byte1]: 69
7721 14:44:32.682542
7722 14:44:32.682624 Set Vref, RX VrefLevel [Byte0]: 70
7723 14:44:32.685842 [Byte1]: 70
7724 14:44:32.690242
7725 14:44:32.690337 Final RX Vref Byte 0 = 53 to rank0
7726 14:44:32.693487 Final RX Vref Byte 1 = 54 to rank0
7727 14:44:32.696715 Final RX Vref Byte 0 = 53 to rank1
7728 14:44:32.700247 Final RX Vref Byte 1 = 54 to rank1==
7729 14:44:32.703779 Dram Type= 6, Freq= 0, CH_0, rank 0
7730 14:44:32.710313 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7731 14:44:32.710421 ==
7732 14:44:32.710487 DQS Delay:
7733 14:44:32.710546 DQS0 = 0, DQS1 = 0
7734 14:44:32.713595 DQM Delay:
7735 14:44:32.713678 DQM0 = 127, DQM1 = 120
7736 14:44:32.716542 DQ Delay:
7737 14:44:32.720054 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =124
7738 14:44:32.723422 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7739 14:44:32.726485 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
7740 14:44:32.729820 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7741 14:44:32.729908
7742 14:44:32.729972
7743 14:44:32.730031
7744 14:44:32.733222 [DramC_TX_OE_Calibration] TA2
7745 14:44:32.736697 Original DQ_B0 (3 6) =30, OEN = 27
7746 14:44:32.739778 Original DQ_B1 (3 6) =30, OEN = 27
7747 14:44:32.743527 24, 0x0, End_B0=24 End_B1=24
7748 14:44:32.743613 25, 0x0, End_B0=25 End_B1=25
7749 14:44:32.746393 26, 0x0, End_B0=26 End_B1=26
7750 14:44:32.749658 27, 0x0, End_B0=27 End_B1=27
7751 14:44:32.753072 28, 0x0, End_B0=28 End_B1=28
7752 14:44:32.756200 29, 0x0, End_B0=29 End_B1=29
7753 14:44:32.756294 30, 0x0, End_B0=30 End_B1=30
7754 14:44:32.759642 31, 0x4141, End_B0=30 End_B1=30
7755 14:44:32.762973 Byte0 end_step=30 best_step=27
7756 14:44:32.766334 Byte1 end_step=30 best_step=27
7757 14:44:32.769487 Byte0 TX OE(2T, 0.5T) = (3, 3)
7758 14:44:32.772861 Byte1 TX OE(2T, 0.5T) = (3, 3)
7759 14:44:32.772950
7760 14:44:32.773015
7761 14:44:32.779499 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
7762 14:44:32.782686 CH0 RK0: MR19=303, MR18=1E1E
7763 14:44:32.789606 CH0_RK0: MR19=0x303, MR18=0x1E1E, DQSOSC=394, MR23=63, INC=23, DEC=15
7764 14:44:32.789742
7765 14:44:32.792826 ----->DramcWriteLeveling(PI) begin...
7766 14:44:32.792929 ==
7767 14:44:32.796048 Dram Type= 6, Freq= 0, CH_0, rank 1
7768 14:44:32.799443 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7769 14:44:32.799530 ==
7770 14:44:32.802622 Write leveling (Byte 0): 28 => 28
7771 14:44:32.805945 Write leveling (Byte 1): 25 => 25
7772 14:44:32.809408 DramcWriteLeveling(PI) end<-----
7773 14:44:32.809499
7774 14:44:32.809564 ==
7775 14:44:32.812679 Dram Type= 6, Freq= 0, CH_0, rank 1
7776 14:44:32.815984 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7777 14:44:32.816107 ==
7778 14:44:32.819483 [Gating] SW mode calibration
7779 14:44:32.826018 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7780 14:44:32.832315 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7781 14:44:32.835614 0 12 0 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
7782 14:44:32.842401 0 12 4 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7783 14:44:32.845616 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7784 14:44:32.848956 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7785 14:44:32.855440 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7786 14:44:32.859008 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7787 14:44:32.862349 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7788 14:44:32.868735 0 12 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7789 14:44:32.872064 0 13 0 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
7790 14:44:32.875423 0 13 4 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
7791 14:44:32.882107 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7792 14:44:32.885506 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7793 14:44:32.888616 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7794 14:44:32.895183 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7795 14:44:32.898474 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7796 14:44:32.902096 0 13 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7797 14:44:32.908725 0 14 0 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
7798 14:44:32.911930 0 14 4 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
7799 14:44:32.915216 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7800 14:44:32.918915 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7801 14:44:32.925301 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7802 14:44:32.928518 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7803 14:44:32.931877 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7804 14:44:32.938356 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7805 14:44:32.941711 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7806 14:44:32.945000 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7807 14:44:32.951474 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7808 14:44:32.954892 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7809 14:44:32.958153 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7810 14:44:32.964697 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7811 14:44:32.968088 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7812 14:44:32.971398 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7813 14:44:32.977954 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7814 14:44:32.981474 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7815 14:44:32.984614 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7816 14:44:32.991460 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7817 14:44:32.994555 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7818 14:44:32.998118 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7819 14:44:33.004417 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7820 14:44:33.007731 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7821 14:44:33.010962 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7822 14:44:33.017590 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7823 14:44:33.020906 Total UI for P1: 0, mck2ui 16
7824 14:44:33.024505 best dqsien dly found for B0: ( 1, 0, 30)
7825 14:44:33.027439 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7826 14:44:33.030768 Total UI for P1: 0, mck2ui 16
7827 14:44:33.034233 best dqsien dly found for B1: ( 1, 1, 2)
7828 14:44:33.037557 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7829 14:44:33.040898 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7830 14:44:33.040989
7831 14:44:33.044025 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7832 14:44:33.047471 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7833 14:44:33.050489 [Gating] SW calibration Done
7834 14:44:33.050574 ==
7835 14:44:33.054042 Dram Type= 6, Freq= 0, CH_0, rank 1
7836 14:44:33.060531 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7837 14:44:33.060638 ==
7838 14:44:33.060704 RX Vref Scan: 0
7839 14:44:33.060764
7840 14:44:33.063997 RX Vref 0 -> 0, step: 1
7841 14:44:33.064082
7842 14:44:33.067062 RX Delay 0 -> 252, step: 8
7843 14:44:33.070310 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7844 14:44:33.073510 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7845 14:44:33.076954 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7846 14:44:33.080183 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7847 14:44:33.086905 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7848 14:44:33.090268 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7849 14:44:33.093596 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7850 14:44:33.096658 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7851 14:44:33.100092 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7852 14:44:33.106664 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7853 14:44:33.110003 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7854 14:44:33.113235 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7855 14:44:33.116709 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7856 14:44:33.123361 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7857 14:44:33.126751 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
7858 14:44:33.129888 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7859 14:44:33.129976 ==
7860 14:44:33.133184 Dram Type= 6, Freq= 0, CH_0, rank 1
7861 14:44:33.136588 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7862 14:44:33.136678 ==
7863 14:44:33.139821 DQS Delay:
7864 14:44:33.139906 DQS0 = 0, DQS1 = 0
7865 14:44:33.143147 DQM Delay:
7866 14:44:33.143231 DQM0 = 130, DQM1 = 123
7867 14:44:33.143322 DQ Delay:
7868 14:44:33.146442 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =123
7869 14:44:33.152993 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7870 14:44:33.156461 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7871 14:44:33.159966 DQ12 =131, DQ13 =131, DQ14 =131, DQ15 =131
7872 14:44:33.160055
7873 14:44:33.160119
7874 14:44:33.160179 ==
7875 14:44:33.163099 Dram Type= 6, Freq= 0, CH_0, rank 1
7876 14:44:33.166266 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7877 14:44:33.166352 ==
7878 14:44:33.166418
7879 14:44:33.166478
7880 14:44:33.169654 TX Vref Scan disable
7881 14:44:33.173066 == TX Byte 0 ==
7882 14:44:33.176245 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7883 14:44:33.179547 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7884 14:44:33.182876 == TX Byte 1 ==
7885 14:44:33.186069 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7886 14:44:33.189584 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7887 14:44:33.189689 ==
7888 14:44:33.192786 Dram Type= 6, Freq= 0, CH_0, rank 1
7889 14:44:33.196059 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7890 14:44:33.199334 ==
7891 14:44:33.211079
7892 14:44:33.214317 TX Vref early break, caculate TX vref
7893 14:44:33.217646 TX Vref=16, minBit 9, minWin=22, winSum=374
7894 14:44:33.220824 TX Vref=18, minBit 1, minWin=23, winSum=382
7895 14:44:33.223944 TX Vref=20, minBit 9, minWin=23, winSum=395
7896 14:44:33.227371 TX Vref=22, minBit 8, minWin=23, winSum=399
7897 14:44:33.230671 TX Vref=24, minBit 1, minWin=25, winSum=409
7898 14:44:33.237274 TX Vref=26, minBit 0, minWin=25, winSum=410
7899 14:44:33.240875 TX Vref=28, minBit 8, minWin=25, winSum=419
7900 14:44:33.244018 TX Vref=30, minBit 0, minWin=25, winSum=409
7901 14:44:33.247426 TX Vref=32, minBit 8, minWin=23, winSum=399
7902 14:44:33.250464 TX Vref=34, minBit 8, minWin=23, winSum=395
7903 14:44:33.257120 [TxChooseVref] Worse bit 8, Min win 25, Win sum 419, Final Vref 28
7904 14:44:33.257231
7905 14:44:33.260378 Final TX Range 0 Vref 28
7906 14:44:33.260462
7907 14:44:33.260526 ==
7908 14:44:33.263716 Dram Type= 6, Freq= 0, CH_0, rank 1
7909 14:44:33.267004 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7910 14:44:33.267089 ==
7911 14:44:33.267154
7912 14:44:33.267214
7913 14:44:33.270295 TX Vref Scan disable
7914 14:44:33.277030 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7915 14:44:33.277126 == TX Byte 0 ==
7916 14:44:33.280302 u2DelayCellOfst[0]=14 cells (4 PI)
7917 14:44:33.283648 u2DelayCellOfst[1]=18 cells (5 PI)
7918 14:44:33.287138 u2DelayCellOfst[2]=10 cells (3 PI)
7919 14:44:33.290359 u2DelayCellOfst[3]=14 cells (4 PI)
7920 14:44:33.293418 u2DelayCellOfst[4]=10 cells (3 PI)
7921 14:44:33.296684 u2DelayCellOfst[5]=0 cells (0 PI)
7922 14:44:33.300127 u2DelayCellOfst[6]=18 cells (5 PI)
7923 14:44:33.303543 u2DelayCellOfst[7]=18 cells (5 PI)
7924 14:44:33.306785 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7925 14:44:33.310284 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7926 14:44:33.313272 == TX Byte 1 ==
7927 14:44:33.316660 u2DelayCellOfst[8]=3 cells (1 PI)
7928 14:44:33.316746 u2DelayCellOfst[9]=0 cells (0 PI)
7929 14:44:33.320240 u2DelayCellOfst[10]=10 cells (3 PI)
7930 14:44:33.323326 u2DelayCellOfst[11]=7 cells (2 PI)
7931 14:44:33.326775 u2DelayCellOfst[12]=18 cells (5 PI)
7932 14:44:33.330059 u2DelayCellOfst[13]=18 cells (5 PI)
7933 14:44:33.333517 u2DelayCellOfst[14]=21 cells (6 PI)
7934 14:44:33.336929 u2DelayCellOfst[15]=18 cells (5 PI)
7935 14:44:33.340121 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7936 14:44:33.346752 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7937 14:44:33.346858 DramC Write-DBI on
7938 14:44:33.346925 ==
7939 14:44:33.350148 Dram Type= 6, Freq= 0, CH_0, rank 1
7940 14:44:33.356561 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7941 14:44:33.356660 ==
7942 14:44:33.356726
7943 14:44:33.356786
7944 14:44:33.356845 TX Vref Scan disable
7945 14:44:33.360175 == TX Byte 0 ==
7946 14:44:33.363483 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7947 14:44:33.366799 == TX Byte 1 ==
7948 14:44:33.370112 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7949 14:44:33.373604 DramC Write-DBI off
7950 14:44:33.373692
7951 14:44:33.373791 [DATLAT]
7952 14:44:33.373895 Freq=1600, CH0 RK1
7953 14:44:33.374001
7954 14:44:33.376798 DATLAT Default: 0xe
7955 14:44:33.376880 0, 0xFFFF, sum = 0
7956 14:44:33.380401 1, 0xFFFF, sum = 0
7957 14:44:33.383391 2, 0xFFFF, sum = 0
7958 14:44:33.383474 3, 0xFFFF, sum = 0
7959 14:44:33.386691 4, 0xFFFF, sum = 0
7960 14:44:33.386776 5, 0xFFFF, sum = 0
7961 14:44:33.390188 6, 0xFFFF, sum = 0
7962 14:44:33.390274 7, 0xFFFF, sum = 0
7963 14:44:33.393200 8, 0xFFFF, sum = 0
7964 14:44:33.393305 9, 0xFFFF, sum = 0
7965 14:44:33.396578 10, 0xFFFF, sum = 0
7966 14:44:33.396664 11, 0xFFFF, sum = 0
7967 14:44:33.399953 12, 0x8FFF, sum = 0
7968 14:44:33.400037 13, 0x0, sum = 1
7969 14:44:33.403450 14, 0x0, sum = 2
7970 14:44:33.403534 15, 0x0, sum = 3
7971 14:44:33.406632 16, 0x0, sum = 4
7972 14:44:33.406753 best_step = 14
7973 14:44:33.406818
7974 14:44:33.406877 ==
7975 14:44:33.410000 Dram Type= 6, Freq= 0, CH_0, rank 1
7976 14:44:33.413412 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7977 14:44:33.416861 ==
7978 14:44:33.416946 RX Vref Scan: 0
7979 14:44:33.417011
7980 14:44:33.420027 RX Vref 0 -> 0, step: 1
7981 14:44:33.420111
7982 14:44:33.420175 RX Delay 11 -> 252, step: 4
7983 14:44:33.427290 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7984 14:44:33.430745 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
7985 14:44:33.433980 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7986 14:44:33.437231 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7987 14:44:33.440855 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7988 14:44:33.447303 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7989 14:44:33.450558 iDelay=195, Bit 6, Center 136 (79 ~ 194) 116
7990 14:44:33.454033 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7991 14:44:33.457143 iDelay=195, Bit 8, Center 106 (51 ~ 162) 112
7992 14:44:33.460462 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7993 14:44:33.467217 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7994 14:44:33.470412 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7995 14:44:33.473734 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7996 14:44:33.477268 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7997 14:44:33.483845 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
7998 14:44:33.487060 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7999 14:44:33.487153 ==
8000 14:44:33.490525 Dram Type= 6, Freq= 0, CH_0, rank 1
8001 14:44:33.493807 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8002 14:44:33.493895 ==
8003 14:44:33.493961 DQS Delay:
8004 14:44:33.497245 DQS0 = 0, DQS1 = 0
8005 14:44:33.497367 DQM Delay:
8006 14:44:33.500537 DQM0 = 127, DQM1 = 120
8007 14:44:33.500621 DQ Delay:
8008 14:44:33.503771 DQ0 =122, DQ1 =130, DQ2 =126, DQ3 =122
8009 14:44:33.506997 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =138
8010 14:44:33.510357 DQ8 =106, DQ9 =106, DQ10 =122, DQ11 =112
8011 14:44:33.516880 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =130
8012 14:44:33.516972
8013 14:44:33.517037
8014 14:44:33.517097
8015 14:44:33.520158 [DramC_TX_OE_Calibration] TA2
8016 14:44:33.520243 Original DQ_B0 (3 6) =30, OEN = 27
8017 14:44:33.523418 Original DQ_B1 (3 6) =30, OEN = 27
8018 14:44:33.526776 24, 0x0, End_B0=24 End_B1=24
8019 14:44:33.530167 25, 0x0, End_B0=25 End_B1=25
8020 14:44:33.533400 26, 0x0, End_B0=26 End_B1=26
8021 14:44:33.536746 27, 0x0, End_B0=27 End_B1=27
8022 14:44:33.536837 28, 0x0, End_B0=28 End_B1=28
8023 14:44:33.540275 29, 0x0, End_B0=29 End_B1=29
8024 14:44:33.543325 30, 0x0, End_B0=30 End_B1=30
8025 14:44:33.546613 31, 0x4545, End_B0=30 End_B1=30
8026 14:44:33.549918 Byte0 end_step=30 best_step=27
8027 14:44:33.550005 Byte1 end_step=30 best_step=27
8028 14:44:33.553396 Byte0 TX OE(2T, 0.5T) = (3, 3)
8029 14:44:33.556540 Byte1 TX OE(2T, 0.5T) = (3, 3)
8030 14:44:33.556624
8031 14:44:33.556689
8032 14:44:33.566405 [DQSOSCAuto] RK1, (LSB)MR18= 0x2323, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
8033 14:44:33.566520 CH0 RK1: MR19=303, MR18=2323
8034 14:44:33.573488 CH0_RK1: MR19=0x303, MR18=0x2323, DQSOSC=392, MR23=63, INC=24, DEC=16
8035 14:44:33.576734 [RxdqsGatingPostProcess] freq 1600
8036 14:44:33.583150 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8037 14:44:33.586363 Pre-setting of DQS Precalculation
8038 14:44:33.589723 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8039 14:44:33.589811 ==
8040 14:44:33.593096 Dram Type= 6, Freq= 0, CH_1, rank 0
8041 14:44:33.599729 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8042 14:44:33.599827 ==
8043 14:44:33.603207 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8044 14:44:33.609575 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8045 14:44:33.613065 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8046 14:44:33.619434 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8047 14:44:33.626118 [CA 0] Center 41 (11~71) winsize 61
8048 14:44:33.629536 [CA 1] Center 40 (10~70) winsize 61
8049 14:44:33.632762 [CA 2] Center 36 (6~66) winsize 61
8050 14:44:33.636247 [CA 3] Center 35 (6~65) winsize 60
8051 14:44:33.639364 [CA 4] Center 33 (4~63) winsize 60
8052 14:44:33.642731 [CA 5] Center 33 (4~63) winsize 60
8053 14:44:33.642820
8054 14:44:33.646152 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8055 14:44:33.646238
8056 14:44:33.649360 [CATrainingPosCal] consider 1 rank data
8057 14:44:33.652563 u2DelayCellTimex100 = 271/100 ps
8058 14:44:33.659122 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8059 14:44:33.662620 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
8060 14:44:33.666267 CA2 delay=36 (6~66),Diff = 3 PI (10 cell)
8061 14:44:33.669162 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8062 14:44:33.672472 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8063 14:44:33.675743 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8064 14:44:33.675831
8065 14:44:33.679280 CA PerBit enable=1, Macro0, CA PI delay=33
8066 14:44:33.679367
8067 14:44:33.682436 [CBTSetCACLKResult] CA Dly = 33
8068 14:44:33.686017 CS Dly: 8 (0~39)
8069 14:44:33.689055 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8070 14:44:33.692236 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8071 14:44:33.692324 ==
8072 14:44:33.695655 Dram Type= 6, Freq= 0, CH_1, rank 1
8073 14:44:33.702439 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8074 14:44:33.702541 ==
8075 14:44:33.705951 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8076 14:44:33.709018 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8077 14:44:33.715942 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8078 14:44:33.722046 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8079 14:44:33.728586 [CA 0] Center 40 (10~70) winsize 61
8080 14:44:33.732008 [CA 1] Center 39 (9~70) winsize 62
8081 14:44:33.735279 [CA 2] Center 36 (7~65) winsize 59
8082 14:44:33.738576 [CA 3] Center 35 (6~65) winsize 60
8083 14:44:33.741864 [CA 4] Center 32 (3~62) winsize 60
8084 14:44:33.745340 [CA 5] Center 33 (3~63) winsize 61
8085 14:44:33.745428
8086 14:44:33.748781 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8087 14:44:33.748867
8088 14:44:33.752005 [CATrainingPosCal] consider 2 rank data
8089 14:44:33.755211 u2DelayCellTimex100 = 271/100 ps
8090 14:44:33.758583 CA0 delay=40 (11~70),Diff = 7 PI (25 cell)
8091 14:44:33.765119 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
8092 14:44:33.768420 CA2 delay=36 (7~65),Diff = 3 PI (10 cell)
8093 14:44:33.771710 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8094 14:44:33.775140 CA4 delay=33 (4~62),Diff = 0 PI (0 cell)
8095 14:44:33.778595 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8096 14:44:33.778682
8097 14:44:33.781814 CA PerBit enable=1, Macro0, CA PI delay=33
8098 14:44:33.781899
8099 14:44:33.784930 [CBTSetCACLKResult] CA Dly = 33
8100 14:44:33.788386 CS Dly: 9 (0~41)
8101 14:44:33.791781 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8102 14:44:33.794914 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8103 14:44:33.795001
8104 14:44:33.798507 ----->DramcWriteLeveling(PI) begin...
8105 14:44:33.798594 ==
8106 14:44:33.801562 Dram Type= 6, Freq= 0, CH_1, rank 0
8107 14:44:33.808045 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8108 14:44:33.808144 ==
8109 14:44:33.811387 Write leveling (Byte 0): 22 => 22
8110 14:44:33.811474 Write leveling (Byte 1): 22 => 22
8111 14:44:33.814906 DramcWriteLeveling(PI) end<-----
8112 14:44:33.814991
8113 14:44:33.815057 ==
8114 14:44:33.818090 Dram Type= 6, Freq= 0, CH_1, rank 0
8115 14:44:33.824778 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8116 14:44:33.824891 ==
8117 14:44:33.827920 [Gating] SW mode calibration
8118 14:44:33.834763 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8119 14:44:33.837876 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8120 14:44:33.844547 0 12 0 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
8121 14:44:33.847964 0 12 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8122 14:44:33.851377 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8123 14:44:33.857793 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8124 14:44:33.861211 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8125 14:44:33.864606 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8126 14:44:33.870797 0 12 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
8127 14:44:33.874121 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8128 14:44:33.877559 0 13 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
8129 14:44:33.884307 0 13 4 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8130 14:44:33.887256 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8131 14:44:33.890688 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8132 14:44:33.897267 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8133 14:44:33.900744 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8134 14:44:33.903835 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8135 14:44:33.910822 0 13 28 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
8136 14:44:33.913711 0 14 0 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
8137 14:44:33.917017 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8138 14:44:33.923669 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8139 14:44:33.927019 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8140 14:44:33.930648 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8141 14:44:33.937248 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8142 14:44:33.940467 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8143 14:44:33.943467 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8144 14:44:33.950091 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8145 14:44:33.953611 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8146 14:44:33.956656 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8147 14:44:33.963387 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 14:44:33.966697 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8149 14:44:33.969966 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 14:44:33.976749 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8151 14:44:33.979801 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8152 14:44:33.983321 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8153 14:44:33.989776 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8154 14:44:33.992987 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8155 14:44:33.996568 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8156 14:44:34.003058 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8157 14:44:34.006109 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8158 14:44:34.009428 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8159 14:44:34.016317 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8160 14:44:34.019428 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8161 14:44:34.022681 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8162 14:44:34.025916 Total UI for P1: 0, mck2ui 16
8163 14:44:34.029353 best dqsien dly found for B0: ( 1, 0, 28)
8164 14:44:34.032635 Total UI for P1: 0, mck2ui 16
8165 14:44:34.035915 best dqsien dly found for B1: ( 1, 0, 30)
8166 14:44:34.039032 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
8167 14:44:34.042426 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8168 14:44:34.042516
8169 14:44:34.045870 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
8170 14:44:34.052235 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8171 14:44:34.052342 [Gating] SW calibration Done
8172 14:44:34.055663 ==
8173 14:44:34.055751 Dram Type= 6, Freq= 0, CH_1, rank 0
8174 14:44:34.062410 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8175 14:44:34.062544 ==
8176 14:44:34.062643 RX Vref Scan: 0
8177 14:44:34.062776
8178 14:44:34.065711 RX Vref 0 -> 0, step: 1
8179 14:44:34.065795
8180 14:44:34.069038 RX Delay 0 -> 252, step: 8
8181 14:44:34.071989 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8182 14:44:34.075316 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8183 14:44:34.078901 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8184 14:44:34.085400 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8185 14:44:34.088654 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8186 14:44:34.092240 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8187 14:44:34.095207 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8188 14:44:34.098494 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8189 14:44:34.105397 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8190 14:44:34.108498 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8191 14:44:34.111741 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8192 14:44:34.115021 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8193 14:44:34.118365 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8194 14:44:34.125124 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8195 14:44:34.128442 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8196 14:44:34.131781 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8197 14:44:34.131872 ==
8198 14:44:34.135084 Dram Type= 6, Freq= 0, CH_1, rank 0
8199 14:44:34.138515 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8200 14:44:34.141508 ==
8201 14:44:34.141597 DQS Delay:
8202 14:44:34.141662 DQS0 = 0, DQS1 = 0
8203 14:44:34.145310 DQM Delay:
8204 14:44:34.145410 DQM0 = 130, DQM1 = 124
8205 14:44:34.148232 DQ Delay:
8206 14:44:34.151508 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8207 14:44:34.154968 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8208 14:44:34.158236 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8209 14:44:34.161517 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8210 14:44:34.161606
8211 14:44:34.161671
8212 14:44:34.161731 ==
8213 14:44:34.164538 Dram Type= 6, Freq= 0, CH_1, rank 0
8214 14:44:34.167983 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8215 14:44:34.171375 ==
8216 14:44:34.171464
8217 14:44:34.171528
8218 14:44:34.171588 TX Vref Scan disable
8219 14:44:34.174592 == TX Byte 0 ==
8220 14:44:34.177792 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8221 14:44:34.181192 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8222 14:44:34.184780 == TX Byte 1 ==
8223 14:44:34.187858 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8224 14:44:34.191173 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8225 14:44:34.191264 ==
8226 14:44:34.194411 Dram Type= 6, Freq= 0, CH_1, rank 0
8227 14:44:34.200919 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8228 14:44:34.201019 ==
8229 14:44:34.212520
8230 14:44:34.215559 TX Vref early break, caculate TX vref
8231 14:44:34.219118 TX Vref=16, minBit 3, minWin=21, winSum=367
8232 14:44:34.222620 TX Vref=18, minBit 1, minWin=22, winSum=372
8233 14:44:34.225744 TX Vref=20, minBit 0, minWin=23, winSum=383
8234 14:44:34.228946 TX Vref=22, minBit 1, minWin=23, winSum=391
8235 14:44:34.232517 TX Vref=24, minBit 0, minWin=24, winSum=403
8236 14:44:34.238889 TX Vref=26, minBit 1, minWin=24, winSum=406
8237 14:44:34.242277 TX Vref=28, minBit 3, minWin=23, winSum=411
8238 14:44:34.245593 TX Vref=30, minBit 0, minWin=25, winSum=406
8239 14:44:34.248962 TX Vref=32, minBit 3, minWin=23, winSum=395
8240 14:44:34.252246 TX Vref=34, minBit 0, minWin=23, winSum=389
8241 14:44:34.258726 [TxChooseVref] Worse bit 0, Min win 25, Win sum 406, Final Vref 30
8242 14:44:34.258866
8243 14:44:34.262084 Final TX Range 0 Vref 30
8244 14:44:34.262186
8245 14:44:34.262275 ==
8246 14:44:34.265313 Dram Type= 6, Freq= 0, CH_1, rank 0
8247 14:44:34.268971 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8248 14:44:34.269092 ==
8249 14:44:34.269158
8250 14:44:34.269218
8251 14:44:34.272372 TX Vref Scan disable
8252 14:44:34.278820 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8253 14:44:34.278924 == TX Byte 0 ==
8254 14:44:34.282068 u2DelayCellOfst[0]=14 cells (4 PI)
8255 14:44:34.285757 u2DelayCellOfst[1]=10 cells (3 PI)
8256 14:44:34.288593 u2DelayCellOfst[2]=0 cells (0 PI)
8257 14:44:34.291887 u2DelayCellOfst[3]=7 cells (2 PI)
8258 14:44:34.295206 u2DelayCellOfst[4]=7 cells (2 PI)
8259 14:44:34.298648 u2DelayCellOfst[5]=14 cells (4 PI)
8260 14:44:34.301806 u2DelayCellOfst[6]=14 cells (4 PI)
8261 14:44:34.301895 u2DelayCellOfst[7]=7 cells (2 PI)
8262 14:44:34.308733 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8263 14:44:34.311925 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8264 14:44:34.312015 == TX Byte 1 ==
8265 14:44:34.315029 u2DelayCellOfst[8]=0 cells (0 PI)
8266 14:44:34.318315 u2DelayCellOfst[9]=7 cells (2 PI)
8267 14:44:34.321697 u2DelayCellOfst[10]=10 cells (3 PI)
8268 14:44:34.325088 u2DelayCellOfst[11]=3 cells (1 PI)
8269 14:44:34.328137 u2DelayCellOfst[12]=18 cells (5 PI)
8270 14:44:34.331481 u2DelayCellOfst[13]=21 cells (6 PI)
8271 14:44:34.334915 u2DelayCellOfst[14]=21 cells (6 PI)
8272 14:44:34.338278 u2DelayCellOfst[15]=21 cells (6 PI)
8273 14:44:34.341615 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8274 14:44:34.348397 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8275 14:44:34.348500 DramC Write-DBI on
8276 14:44:34.348566 ==
8277 14:44:34.351394 Dram Type= 6, Freq= 0, CH_1, rank 0
8278 14:44:34.354582 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8279 14:44:34.358093 ==
8280 14:44:34.358181
8281 14:44:34.358246
8282 14:44:34.358306 TX Vref Scan disable
8283 14:44:34.361527 == TX Byte 0 ==
8284 14:44:34.364884 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8285 14:44:34.368228 == TX Byte 1 ==
8286 14:44:34.371273 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8287 14:44:34.374822 DramC Write-DBI off
8288 14:44:34.374909
8289 14:44:34.374974 [DATLAT]
8290 14:44:34.375034 Freq=1600, CH1 RK0
8291 14:44:34.375093
8292 14:44:34.377897 DATLAT Default: 0xf
8293 14:44:34.377979 0, 0xFFFF, sum = 0
8294 14:44:34.381175 1, 0xFFFF, sum = 0
8295 14:44:34.384563 2, 0xFFFF, sum = 0
8296 14:44:34.384657 3, 0xFFFF, sum = 0
8297 14:44:34.387815 4, 0xFFFF, sum = 0
8298 14:44:34.387899 5, 0xFFFF, sum = 0
8299 14:44:34.391104 6, 0xFFFF, sum = 0
8300 14:44:34.391189 7, 0xFFFF, sum = 0
8301 14:44:34.394933 8, 0xFFFF, sum = 0
8302 14:44:34.395019 9, 0xFFFF, sum = 0
8303 14:44:34.397817 10, 0xFFFF, sum = 0
8304 14:44:34.397901 11, 0xFFFF, sum = 0
8305 14:44:34.401164 12, 0xFFF, sum = 0
8306 14:44:34.401248 13, 0x0, sum = 1
8307 14:44:34.404532 14, 0x0, sum = 2
8308 14:44:34.404617 15, 0x0, sum = 3
8309 14:44:34.407809 16, 0x0, sum = 4
8310 14:44:34.407893 best_step = 14
8311 14:44:34.407958
8312 14:44:34.408016 ==
8313 14:44:34.411022 Dram Type= 6, Freq= 0, CH_1, rank 0
8314 14:44:34.414353 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8315 14:44:34.418098 ==
8316 14:44:34.418185 RX Vref Scan: 1
8317 14:44:34.418249
8318 14:44:34.421025 Set Vref Range= 24 -> 127
8319 14:44:34.421107
8320 14:44:34.424396 RX Vref 24 -> 127, step: 1
8321 14:44:34.424485
8322 14:44:34.424549 RX Delay 3 -> 252, step: 4
8323 14:44:34.424608
8324 14:44:34.427713 Set Vref, RX VrefLevel [Byte0]: 24
8325 14:44:34.430957 [Byte1]: 24
8326 14:44:34.434811
8327 14:44:34.434898 Set Vref, RX VrefLevel [Byte0]: 25
8328 14:44:34.437936 [Byte1]: 25
8329 14:44:34.442252
8330 14:44:34.442338 Set Vref, RX VrefLevel [Byte0]: 26
8331 14:44:34.445579 [Byte1]: 26
8332 14:44:34.450262
8333 14:44:34.450353 Set Vref, RX VrefLevel [Byte0]: 27
8334 14:44:34.453426 [Byte1]: 27
8335 14:44:34.457929
8336 14:44:34.458020 Set Vref, RX VrefLevel [Byte0]: 28
8337 14:44:34.461001 [Byte1]: 28
8338 14:44:34.465208
8339 14:44:34.468394 Set Vref, RX VrefLevel [Byte0]: 29
8340 14:44:34.471829 [Byte1]: 29
8341 14:44:34.471914
8342 14:44:34.475178 Set Vref, RX VrefLevel [Byte0]: 30
8343 14:44:34.478510 [Byte1]: 30
8344 14:44:34.478596
8345 14:44:34.481570 Set Vref, RX VrefLevel [Byte0]: 31
8346 14:44:34.484758 [Byte1]: 31
8347 14:44:34.488385
8348 14:44:34.488471 Set Vref, RX VrefLevel [Byte0]: 32
8349 14:44:34.491721 [Byte1]: 32
8350 14:44:34.495809
8351 14:44:34.495898 Set Vref, RX VrefLevel [Byte0]: 33
8352 14:44:34.499148 [Byte1]: 33
8353 14:44:34.503474
8354 14:44:34.503577 Set Vref, RX VrefLevel [Byte0]: 34
8355 14:44:34.506790 [Byte1]: 34
8356 14:44:34.511293
8357 14:44:34.511384 Set Vref, RX VrefLevel [Byte0]: 35
8358 14:44:34.514459 [Byte1]: 35
8359 14:44:34.518878
8360 14:44:34.518974 Set Vref, RX VrefLevel [Byte0]: 36
8361 14:44:34.522477 [Byte1]: 36
8362 14:44:34.526637
8363 14:44:34.526738 Set Vref, RX VrefLevel [Byte0]: 37
8364 14:44:34.529838 [Byte1]: 37
8365 14:44:34.534113
8366 14:44:34.534202 Set Vref, RX VrefLevel [Byte0]: 38
8367 14:44:34.537409 [Byte1]: 38
8368 14:44:34.541741
8369 14:44:34.541826 Set Vref, RX VrefLevel [Byte0]: 39
8370 14:44:34.545053 [Byte1]: 39
8371 14:44:34.549677
8372 14:44:34.549765 Set Vref, RX VrefLevel [Byte0]: 40
8373 14:44:34.552723 [Byte1]: 40
8374 14:44:34.557166
8375 14:44:34.557253 Set Vref, RX VrefLevel [Byte0]: 41
8376 14:44:34.560483 [Byte1]: 41
8377 14:44:34.564813
8378 14:44:34.564901 Set Vref, RX VrefLevel [Byte0]: 42
8379 14:44:34.567898 [Byte1]: 42
8380 14:44:34.572382
8381 14:44:34.572471 Set Vref, RX VrefLevel [Byte0]: 43
8382 14:44:34.575800 [Byte1]: 43
8383 14:44:34.580149
8384 14:44:34.580232 Set Vref, RX VrefLevel [Byte0]: 44
8385 14:44:34.583333 [Byte1]: 44
8386 14:44:34.587736
8387 14:44:34.587821 Set Vref, RX VrefLevel [Byte0]: 45
8388 14:44:34.591283 [Byte1]: 45
8389 14:44:34.595526
8390 14:44:34.595612 Set Vref, RX VrefLevel [Byte0]: 46
8391 14:44:34.598564 [Byte1]: 46
8392 14:44:34.603192
8393 14:44:34.603278 Set Vref, RX VrefLevel [Byte0]: 47
8394 14:44:34.606518 [Byte1]: 47
8395 14:44:34.610583
8396 14:44:34.610671 Set Vref, RX VrefLevel [Byte0]: 48
8397 14:44:34.614053 [Byte1]: 48
8398 14:44:34.618256
8399 14:44:34.618348 Set Vref, RX VrefLevel [Byte0]: 49
8400 14:44:34.621706 [Byte1]: 49
8401 14:44:34.626048
8402 14:44:34.626145 Set Vref, RX VrefLevel [Byte0]: 50
8403 14:44:34.629274 [Byte1]: 50
8404 14:44:34.633672
8405 14:44:34.633759 Set Vref, RX VrefLevel [Byte0]: 51
8406 14:44:34.636836 [Byte1]: 51
8407 14:44:34.641314
8408 14:44:34.641417 Set Vref, RX VrefLevel [Byte0]: 52
8409 14:44:34.644987 [Byte1]: 52
8410 14:44:34.648953
8411 14:44:34.649039 Set Vref, RX VrefLevel [Byte0]: 53
8412 14:44:34.652415 [Byte1]: 53
8413 14:44:34.656579
8414 14:44:34.656666 Set Vref, RX VrefLevel [Byte0]: 54
8415 14:44:34.659938 [Byte1]: 54
8416 14:44:34.664197
8417 14:44:34.664283 Set Vref, RX VrefLevel [Byte0]: 55
8418 14:44:34.667484 [Byte1]: 55
8419 14:44:34.671904
8420 14:44:34.671991 Set Vref, RX VrefLevel [Byte0]: 56
8421 14:44:34.675151 [Byte1]: 56
8422 14:44:34.679616
8423 14:44:34.679701 Set Vref, RX VrefLevel [Byte0]: 57
8424 14:44:34.682836 [Byte1]: 57
8425 14:44:34.687197
8426 14:44:34.687282 Set Vref, RX VrefLevel [Byte0]: 58
8427 14:44:34.690549 [Byte1]: 58
8428 14:44:34.694908
8429 14:44:34.694998 Set Vref, RX VrefLevel [Byte0]: 59
8430 14:44:34.698303 [Byte1]: 59
8431 14:44:34.702424
8432 14:44:34.702509 Set Vref, RX VrefLevel [Byte0]: 60
8433 14:44:34.705837 [Byte1]: 60
8434 14:44:34.710175
8435 14:44:34.710262 Set Vref, RX VrefLevel [Byte0]: 61
8436 14:44:34.713528 [Byte1]: 61
8437 14:44:34.717814
8438 14:44:34.717903 Set Vref, RX VrefLevel [Byte0]: 62
8439 14:44:34.721255 [Byte1]: 62
8440 14:44:34.725586
8441 14:44:34.725683 Set Vref, RX VrefLevel [Byte0]: 63
8442 14:44:34.728706 [Byte1]: 63
8443 14:44:34.733080
8444 14:44:34.733170 Set Vref, RX VrefLevel [Byte0]: 64
8445 14:44:34.736341 [Byte1]: 64
8446 14:44:34.740723
8447 14:44:34.740810 Set Vref, RX VrefLevel [Byte0]: 65
8448 14:44:34.743982 [Byte1]: 65
8449 14:44:34.748449
8450 14:44:34.748538 Set Vref, RX VrefLevel [Byte0]: 66
8451 14:44:34.751766 [Byte1]: 66
8452 14:44:34.756081
8453 14:44:34.756187 Set Vref, RX VrefLevel [Byte0]: 67
8454 14:44:34.759511 [Byte1]: 67
8455 14:44:34.763910
8456 14:44:34.764000 Set Vref, RX VrefLevel [Byte0]: 68
8457 14:44:34.767126 [Byte1]: 68
8458 14:44:34.771352
8459 14:44:34.771437 Set Vref, RX VrefLevel [Byte0]: 69
8460 14:44:34.774661 [Byte1]: 69
8461 14:44:34.779231
8462 14:44:34.779322 Set Vref, RX VrefLevel [Byte0]: 70
8463 14:44:34.782417 [Byte1]: 70
8464 14:44:34.786651
8465 14:44:34.786737 Set Vref, RX VrefLevel [Byte0]: 71
8466 14:44:34.790153 [Byte1]: 71
8467 14:44:34.794403
8468 14:44:34.794489 Set Vref, RX VrefLevel [Byte0]: 72
8469 14:44:34.797570 [Byte1]: 72
8470 14:44:34.802016
8471 14:44:34.802102 Set Vref, RX VrefLevel [Byte0]: 73
8472 14:44:34.805203 [Byte1]: 73
8473 14:44:34.809573
8474 14:44:34.809660 Set Vref, RX VrefLevel [Byte0]: 74
8475 14:44:34.812813 [Byte1]: 74
8476 14:44:34.817227
8477 14:44:34.817353 Set Vref, RX VrefLevel [Byte0]: 75
8478 14:44:34.820782 [Byte1]: 75
8479 14:44:34.825137
8480 14:44:34.825238 Final RX Vref Byte 0 = 58 to rank0
8481 14:44:34.828160 Final RX Vref Byte 1 = 53 to rank0
8482 14:44:34.831527 Final RX Vref Byte 0 = 58 to rank1
8483 14:44:34.834685 Final RX Vref Byte 1 = 53 to rank1==
8484 14:44:34.838111 Dram Type= 6, Freq= 0, CH_1, rank 0
8485 14:44:34.844555 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8486 14:44:34.844661 ==
8487 14:44:34.844731 DQS Delay:
8488 14:44:34.847986 DQS0 = 0, DQS1 = 0
8489 14:44:34.848074 DQM Delay:
8490 14:44:34.848140 DQM0 = 129, DQM1 = 123
8491 14:44:34.851382 DQ Delay:
8492 14:44:34.854463 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =128
8493 14:44:34.857885 DQ4 =128, DQ5 =142, DQ6 =138, DQ7 =126
8494 14:44:34.861086 DQ8 =106, DQ9 =114, DQ10 =124, DQ11 =112
8495 14:44:34.864327 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =134
8496 14:44:34.864412
8497 14:44:34.864478
8498 14:44:34.864538
8499 14:44:34.867739 [DramC_TX_OE_Calibration] TA2
8500 14:44:34.871113 Original DQ_B0 (3 6) =30, OEN = 27
8501 14:44:34.874483 Original DQ_B1 (3 6) =30, OEN = 27
8502 14:44:34.877591 24, 0x0, End_B0=24 End_B1=24
8503 14:44:34.877680 25, 0x0, End_B0=25 End_B1=25
8504 14:44:34.881069 26, 0x0, End_B0=26 End_B1=26
8505 14:44:34.884251 27, 0x0, End_B0=27 End_B1=27
8506 14:44:34.887566 28, 0x0, End_B0=28 End_B1=28
8507 14:44:34.890856 29, 0x0, End_B0=29 End_B1=29
8508 14:44:34.890940 30, 0x0, End_B0=30 End_B1=30
8509 14:44:34.894042 31, 0x4545, End_B0=30 End_B1=30
8510 14:44:34.897505 Byte0 end_step=30 best_step=27
8511 14:44:34.900682 Byte1 end_step=30 best_step=27
8512 14:44:34.904070 Byte0 TX OE(2T, 0.5T) = (3, 3)
8513 14:44:34.907306 Byte1 TX OE(2T, 0.5T) = (3, 3)
8514 14:44:34.907388
8515 14:44:34.907454
8516 14:44:34.914120 [DQSOSCAuto] RK0, (LSB)MR18= 0x2626, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
8517 14:44:34.917251 CH1 RK0: MR19=303, MR18=2626
8518 14:44:34.923698 CH1_RK0: MR19=0x303, MR18=0x2626, DQSOSC=390, MR23=63, INC=24, DEC=16
8519 14:44:34.923780
8520 14:44:34.926964 ----->DramcWriteLeveling(PI) begin...
8521 14:44:34.927050 ==
8522 14:44:34.930536 Dram Type= 6, Freq= 0, CH_1, rank 1
8523 14:44:34.933609 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8524 14:44:34.933692 ==
8525 14:44:34.937124 Write leveling (Byte 0): 21 => 21
8526 14:44:34.940237 Write leveling (Byte 1): 20 => 20
8527 14:44:34.943516 DramcWriteLeveling(PI) end<-----
8528 14:44:34.943599
8529 14:44:34.943663 ==
8530 14:44:34.947132 Dram Type= 6, Freq= 0, CH_1, rank 1
8531 14:44:34.953427 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8532 14:44:34.953510 ==
8533 14:44:34.953575 [Gating] SW mode calibration
8534 14:44:34.963413 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8535 14:44:34.966838 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8536 14:44:34.969861 0 12 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8537 14:44:34.976779 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8538 14:44:34.979997 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8539 14:44:34.983473 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8540 14:44:34.989973 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8541 14:44:34.993108 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8542 14:44:34.996348 0 12 24 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
8543 14:44:35.002868 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8544 14:44:35.006306 0 13 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8545 14:44:35.009809 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8546 14:44:35.016211 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8547 14:44:35.019282 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8548 14:44:35.022704 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8549 14:44:35.029479 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8550 14:44:35.032798 0 13 24 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8551 14:44:35.035856 0 13 28 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
8552 14:44:35.042652 0 14 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8553 14:44:35.045871 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8554 14:44:35.049021 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8555 14:44:35.055748 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8556 14:44:35.059031 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8557 14:44:35.062374 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8558 14:44:35.069187 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8559 14:44:35.072230 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8560 14:44:35.075669 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8561 14:44:35.082030 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8562 14:44:35.085540 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8563 14:44:35.088678 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8564 14:44:35.095320 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8565 14:44:35.099002 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8566 14:44:35.101831 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8567 14:44:35.108820 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8568 14:44:35.111814 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8569 14:44:35.115254 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8570 14:44:35.121957 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8571 14:44:35.125220 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8572 14:44:35.128708 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8573 14:44:35.135389 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8574 14:44:35.138301 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8575 14:44:35.141633 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8576 14:44:35.145165 Total UI for P1: 0, mck2ui 16
8577 14:44:35.148365 best dqsien dly found for B0: ( 1, 0, 24)
8578 14:44:35.155304 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8579 14:44:35.158181 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8580 14:44:35.161640 Total UI for P1: 0, mck2ui 16
8581 14:44:35.164827 best dqsien dly found for B1: ( 1, 1, 0)
8582 14:44:35.168134 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8583 14:44:35.171762 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8584 14:44:35.171844
8585 14:44:35.174555 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8586 14:44:35.177964 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8587 14:44:35.181229 [Gating] SW calibration Done
8588 14:44:35.181316 ==
8589 14:44:35.184519 Dram Type= 6, Freq= 0, CH_1, rank 1
8590 14:44:35.187776 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8591 14:44:35.191143 ==
8592 14:44:35.191225 RX Vref Scan: 0
8593 14:44:35.191290
8594 14:44:35.194352 RX Vref 0 -> 0, step: 1
8595 14:44:35.194434
8596 14:44:35.197668 RX Delay 0 -> 252, step: 8
8597 14:44:35.201170 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8598 14:44:35.204323 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8599 14:44:35.207575 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8600 14:44:35.210977 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8601 14:44:35.217534 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8602 14:44:35.220851 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8603 14:44:35.224055 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8604 14:44:35.227549 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8605 14:44:35.230784 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8606 14:44:35.237245 iDelay=200, Bit 9, Center 111 (48 ~ 175) 128
8607 14:44:35.240533 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8608 14:44:35.244070 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8609 14:44:35.247475 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8610 14:44:35.250611 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8611 14:44:35.257129 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8612 14:44:35.260445 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8613 14:44:35.260527 ==
8614 14:44:35.263822 Dram Type= 6, Freq= 0, CH_1, rank 1
8615 14:44:35.267473 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8616 14:44:35.267556 ==
8617 14:44:35.270810 DQS Delay:
8618 14:44:35.270891 DQS0 = 0, DQS1 = 0
8619 14:44:35.270956 DQM Delay:
8620 14:44:35.273783 DQM0 = 130, DQM1 = 124
8621 14:44:35.273865 DQ Delay:
8622 14:44:35.276974 DQ0 =135, DQ1 =123, DQ2 =115, DQ3 =131
8623 14:44:35.280368 DQ4 =131, DQ5 =139, DQ6 =139, DQ7 =131
8624 14:44:35.287028 DQ8 =107, DQ9 =111, DQ10 =127, DQ11 =115
8625 14:44:35.290230 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8626 14:44:35.290312
8627 14:44:35.290376
8628 14:44:35.290435 ==
8629 14:44:35.293623 Dram Type= 6, Freq= 0, CH_1, rank 1
8630 14:44:35.296803 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8631 14:44:35.296891 ==
8632 14:44:35.297002
8633 14:44:35.297063
8634 14:44:35.300046 TX Vref Scan disable
8635 14:44:35.303735 == TX Byte 0 ==
8636 14:44:35.307053 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8637 14:44:35.309971 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8638 14:44:35.313600 == TX Byte 1 ==
8639 14:44:35.317008 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8640 14:44:35.319899 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8641 14:44:35.319982 ==
8642 14:44:35.323488 Dram Type= 6, Freq= 0, CH_1, rank 1
8643 14:44:35.326544 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8644 14:44:35.329799 ==
8645 14:44:35.341611
8646 14:44:35.344812 TX Vref early break, caculate TX vref
8647 14:44:35.348203 TX Vref=16, minBit 7, minWin=22, winSum=377
8648 14:44:35.351746 TX Vref=18, minBit 1, minWin=23, winSum=386
8649 14:44:35.355000 TX Vref=20, minBit 3, minWin=23, winSum=397
8650 14:44:35.358143 TX Vref=22, minBit 0, minWin=24, winSum=406
8651 14:44:35.361281 TX Vref=24, minBit 7, minWin=24, winSum=413
8652 14:44:35.368113 TX Vref=26, minBit 1, minWin=25, winSum=417
8653 14:44:35.371291 TX Vref=28, minBit 0, minWin=25, winSum=422
8654 14:44:35.374459 TX Vref=30, minBit 0, minWin=25, winSum=419
8655 14:44:35.377803 TX Vref=32, minBit 0, minWin=24, winSum=413
8656 14:44:35.381135 TX Vref=34, minBit 0, minWin=23, winSum=406
8657 14:44:35.384577 TX Vref=36, minBit 0, minWin=23, winSum=398
8658 14:44:35.391088 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 28
8659 14:44:35.391170
8660 14:44:35.394545 Final TX Range 0 Vref 28
8661 14:44:35.394627
8662 14:44:35.394692 ==
8663 14:44:35.397750 Dram Type= 6, Freq= 0, CH_1, rank 1
8664 14:44:35.401102 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8665 14:44:35.401185 ==
8666 14:44:35.401249
8667 14:44:35.404462
8668 14:44:35.404544 TX Vref Scan disable
8669 14:44:35.411315 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8670 14:44:35.411427 == TX Byte 0 ==
8671 14:44:35.414763 u2DelayCellOfst[0]=18 cells (5 PI)
8672 14:44:35.417577 u2DelayCellOfst[1]=10 cells (3 PI)
8673 14:44:35.420920 u2DelayCellOfst[2]=0 cells (0 PI)
8674 14:44:35.424219 u2DelayCellOfst[3]=10 cells (3 PI)
8675 14:44:35.427593 u2DelayCellOfst[4]=10 cells (3 PI)
8676 14:44:35.431057 u2DelayCellOfst[5]=18 cells (5 PI)
8677 14:44:35.434416 u2DelayCellOfst[6]=18 cells (5 PI)
8678 14:44:35.437382 u2DelayCellOfst[7]=7 cells (2 PI)
8679 14:44:35.440812 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8680 14:44:35.443981 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8681 14:44:35.447263 == TX Byte 1 ==
8682 14:44:35.450805 u2DelayCellOfst[8]=0 cells (0 PI)
8683 14:44:35.454172 u2DelayCellOfst[9]=3 cells (1 PI)
8684 14:44:35.457378 u2DelayCellOfst[10]=10 cells (3 PI)
8685 14:44:35.460659 u2DelayCellOfst[11]=3 cells (1 PI)
8686 14:44:35.460743 u2DelayCellOfst[12]=14 cells (4 PI)
8687 14:44:35.463969 u2DelayCellOfst[13]=18 cells (5 PI)
8688 14:44:35.467600 u2DelayCellOfst[14]=18 cells (5 PI)
8689 14:44:35.470458 u2DelayCellOfst[15]=18 cells (5 PI)
8690 14:44:35.476977 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8691 14:44:35.480412 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8692 14:44:35.480493 DramC Write-DBI on
8693 14:44:35.483889 ==
8694 14:44:35.487058 Dram Type= 6, Freq= 0, CH_1, rank 1
8695 14:44:35.490312 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8696 14:44:35.490393 ==
8697 14:44:35.490456
8698 14:44:35.490514
8699 14:44:35.493730 TX Vref Scan disable
8700 14:44:35.493810 == TX Byte 0 ==
8701 14:44:35.500152 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8702 14:44:35.500234 == TX Byte 1 ==
8703 14:44:35.503817 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8704 14:44:35.506991 DramC Write-DBI off
8705 14:44:35.507071
8706 14:44:35.507134 [DATLAT]
8707 14:44:35.510077 Freq=1600, CH1 RK1
8708 14:44:35.510158
8709 14:44:35.510220 DATLAT Default: 0xe
8710 14:44:35.513608 0, 0xFFFF, sum = 0
8711 14:44:35.513691 1, 0xFFFF, sum = 0
8712 14:44:35.516805 2, 0xFFFF, sum = 0
8713 14:44:35.516886 3, 0xFFFF, sum = 0
8714 14:44:35.520188 4, 0xFFFF, sum = 0
8715 14:44:35.520271 5, 0xFFFF, sum = 0
8716 14:44:35.523359 6, 0xFFFF, sum = 0
8717 14:44:35.523441 7, 0xFFFF, sum = 0
8718 14:44:35.526938 8, 0xFFFF, sum = 0
8719 14:44:35.530366 9, 0xFFFF, sum = 0
8720 14:44:35.530449 10, 0xFFFF, sum = 0
8721 14:44:35.533429 11, 0xFFFF, sum = 0
8722 14:44:35.533511 12, 0x8F7F, sum = 0
8723 14:44:35.536948 13, 0x0, sum = 1
8724 14:44:35.537029 14, 0x0, sum = 2
8725 14:44:35.540489 15, 0x0, sum = 3
8726 14:44:35.540573 16, 0x0, sum = 4
8727 14:44:35.540638 best_step = 14
8728 14:44:35.543547
8729 14:44:35.543628 ==
8730 14:44:35.546570 Dram Type= 6, Freq= 0, CH_1, rank 1
8731 14:44:35.549899 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8732 14:44:35.549980 ==
8733 14:44:35.550043 RX Vref Scan: 0
8734 14:44:35.550101
8735 14:44:35.553063 RX Vref 0 -> 0, step: 1
8736 14:44:35.553144
8737 14:44:35.556373 RX Delay 3 -> 252, step: 4
8738 14:44:35.559632 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8739 14:44:35.566522 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8740 14:44:35.569676 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8741 14:44:35.573073 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
8742 14:44:35.576191 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8743 14:44:35.579486 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8744 14:44:35.586220 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8745 14:44:35.589493 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8746 14:44:35.592805 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8747 14:44:35.595968 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8748 14:44:35.599332 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8749 14:44:35.606175 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8750 14:44:35.609558 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8751 14:44:35.612706 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8752 14:44:35.616017 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8753 14:44:35.619348 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8754 14:44:35.622617 ==
8755 14:44:35.626031 Dram Type= 6, Freq= 0, CH_1, rank 1
8756 14:44:35.629413 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8757 14:44:35.629498 ==
8758 14:44:35.629562 DQS Delay:
8759 14:44:35.632502 DQS0 = 0, DQS1 = 0
8760 14:44:35.632584 DQM Delay:
8761 14:44:35.635880 DQM0 = 127, DQM1 = 122
8762 14:44:35.635962 DQ Delay:
8763 14:44:35.639388 DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =122
8764 14:44:35.642702 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8765 14:44:35.645898 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =112
8766 14:44:35.649187 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8767 14:44:35.649269
8768 14:44:35.649339
8769 14:44:35.649397
8770 14:44:35.652762 [DramC_TX_OE_Calibration] TA2
8771 14:44:35.655852 Original DQ_B0 (3 6) =30, OEN = 27
8772 14:44:35.659235 Original DQ_B1 (3 6) =30, OEN = 27
8773 14:44:35.662332 24, 0x0, End_B0=24 End_B1=24
8774 14:44:35.665846 25, 0x0, End_B0=25 End_B1=25
8775 14:44:35.665929 26, 0x0, End_B0=26 End_B1=26
8776 14:44:35.669017 27, 0x0, End_B0=27 End_B1=27
8777 14:44:35.672395 28, 0x0, End_B0=28 End_B1=28
8778 14:44:35.675686 29, 0x0, End_B0=29 End_B1=29
8779 14:44:35.679120 30, 0x0, End_B0=30 End_B1=30
8780 14:44:35.679205 31, 0x4141, End_B0=30 End_B1=30
8781 14:44:35.682513 Byte0 end_step=30 best_step=27
8782 14:44:35.685651 Byte1 end_step=30 best_step=27
8783 14:44:35.689049 Byte0 TX OE(2T, 0.5T) = (3, 3)
8784 14:44:35.692431 Byte1 TX OE(2T, 0.5T) = (3, 3)
8785 14:44:35.692514
8786 14:44:35.692578
8787 14:44:35.698995 [DQSOSCAuto] RK1, (LSB)MR18= 0x2020, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
8788 14:44:35.702202 CH1 RK1: MR19=303, MR18=2020
8789 14:44:35.708808 CH1_RK1: MR19=0x303, MR18=0x2020, DQSOSC=393, MR23=63, INC=23, DEC=15
8790 14:44:35.712295 [RxdqsGatingPostProcess] freq 1600
8791 14:44:35.718684 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8792 14:44:35.718775 Pre-setting of DQS Precalculation
8793 14:44:35.725205 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8794 14:44:35.731892 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8795 14:44:35.738403 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8796 14:44:35.738511
8797 14:44:35.738576
8798 14:44:35.741988 [Calibration Summary] 3200 Mbps
8799 14:44:35.745209 CH 0, Rank 0
8800 14:44:35.745322 SW Impedance : PASS
8801 14:44:35.748568 DUTY Scan : NO K
8802 14:44:35.751812 ZQ Calibration : PASS
8803 14:44:35.751903 Jitter Meter : NO K
8804 14:44:35.755062 CBT Training : PASS
8805 14:44:35.758302 Write leveling : PASS
8806 14:44:35.758391 RX DQS gating : PASS
8807 14:44:35.761639 RX DQ/DQS(RDDQC) : PASS
8808 14:44:35.764908 TX DQ/DQS : PASS
8809 14:44:35.764996 RX DATLAT : PASS
8810 14:44:35.768611 RX DQ/DQS(Engine): PASS
8811 14:44:35.771644 TX OE : PASS
8812 14:44:35.771736 All Pass.
8813 14:44:35.771801
8814 14:44:35.771861 CH 0, Rank 1
8815 14:44:35.775062 SW Impedance : PASS
8816 14:44:35.775149 DUTY Scan : NO K
8817 14:44:35.778355 ZQ Calibration : PASS
8818 14:44:35.781669 Jitter Meter : NO K
8819 14:44:35.781761 CBT Training : PASS
8820 14:44:35.784907 Write leveling : PASS
8821 14:44:35.788129 RX DQS gating : PASS
8822 14:44:35.788225 RX DQ/DQS(RDDQC) : PASS
8823 14:44:35.791656 TX DQ/DQS : PASS
8824 14:44:35.794700 RX DATLAT : PASS
8825 14:44:35.794788 RX DQ/DQS(Engine): PASS
8826 14:44:35.798090 TX OE : PASS
8827 14:44:35.798176 All Pass.
8828 14:44:35.798241
8829 14:44:35.801626 CH 1, Rank 0
8830 14:44:35.801716 SW Impedance : PASS
8831 14:44:35.804728 DUTY Scan : NO K
8832 14:44:35.808349 ZQ Calibration : PASS
8833 14:44:35.808445 Jitter Meter : NO K
8834 14:44:35.811624 CBT Training : PASS
8835 14:44:35.814662 Write leveling : PASS
8836 14:44:35.814756 RX DQS gating : PASS
8837 14:44:35.818063 RX DQ/DQS(RDDQC) : PASS
8838 14:44:35.821263 TX DQ/DQS : PASS
8839 14:44:35.821397 RX DATLAT : PASS
8840 14:44:35.824680 RX DQ/DQS(Engine): PASS
8841 14:44:35.827767 TX OE : PASS
8842 14:44:35.827860 All Pass.
8843 14:44:35.827924
8844 14:44:35.827982 CH 1, Rank 1
8845 14:44:35.831242 SW Impedance : PASS
8846 14:44:35.834437 DUTY Scan : NO K
8847 14:44:35.834519 ZQ Calibration : PASS
8848 14:44:35.837779 Jitter Meter : NO K
8849 14:44:35.837861 CBT Training : PASS
8850 14:44:35.840973 Write leveling : PASS
8851 14:44:35.844314 RX DQS gating : PASS
8852 14:44:35.844395 RX DQ/DQS(RDDQC) : PASS
8853 14:44:35.847778 TX DQ/DQS : PASS
8854 14:44:35.850938 RX DATLAT : PASS
8855 14:44:35.851020 RX DQ/DQS(Engine): PASS
8856 14:44:35.854245 TX OE : PASS
8857 14:44:35.854327 All Pass.
8858 14:44:35.854391
8859 14:44:35.857484 DramC Write-DBI on
8860 14:44:35.860878 PER_BANK_REFRESH: Hybrid Mode
8861 14:44:35.860959 TX_TRACKING: ON
8862 14:44:35.870979 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8863 14:44:35.877524 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8864 14:44:35.884094 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8865 14:44:35.890733 [FAST_K] Save calibration result to emmc
8866 14:44:35.890822 sync common calibartion params.
8867 14:44:35.894109 sync cbt_mode0:0, 1:0
8868 14:44:35.897227 dram_init: ddr_geometry: 0
8869 14:44:35.900495 dram_init: ddr_geometry: 0
8870 14:44:35.900577 dram_init: ddr_geometry: 0
8871 14:44:35.903997 0:dram_rank_size:80000000
8872 14:44:35.907079 1:dram_rank_size:80000000
8873 14:44:35.910569 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8874 14:44:35.913807 DFS_SHUFFLE_HW_MODE: ON
8875 14:44:35.917219 dramc_set_vcore_voltage set vcore to 725000
8876 14:44:35.920604 Read voltage for 1600, 0
8877 14:44:35.920687 Vio18 = 0
8878 14:44:35.920751 Vcore = 725000
8879 14:44:35.923700 Vdram = 0
8880 14:44:35.923782 Vddq = 0
8881 14:44:35.923847 Vmddr = 0
8882 14:44:35.926926 switch to 3200 Mbps bootup
8883 14:44:35.930318 [DramcRunTimeConfig]
8884 14:44:35.930402 PHYPLL
8885 14:44:35.930466 DPM_CONTROL_AFTERK: ON
8886 14:44:35.933677 PER_BANK_REFRESH: ON
8887 14:44:35.936849 REFRESH_OVERHEAD_REDUCTION: ON
8888 14:44:35.936947 CMD_PICG_NEW_MODE: OFF
8889 14:44:35.940389 XRTWTW_NEW_MODE: ON
8890 14:44:35.943522 XRTRTR_NEW_MODE: ON
8891 14:44:35.943603 TX_TRACKING: ON
8892 14:44:35.946858 RDSEL_TRACKING: OFF
8893 14:44:35.946940 DQS Precalculation for DVFS: ON
8894 14:44:35.950540 RX_TRACKING: OFF
8895 14:44:35.950627 HW_GATING DBG: ON
8896 14:44:35.953670 ZQCS_ENABLE_LP4: ON
8897 14:44:35.953753 RX_PICG_NEW_MODE: ON
8898 14:44:35.957085 TX_PICG_NEW_MODE: ON
8899 14:44:35.960089 ENABLE_RX_DCM_DPHY: ON
8900 14:44:35.963413 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8901 14:44:35.963496 DUMMY_READ_FOR_TRACKING: OFF
8902 14:44:35.966879 !!! SPM_CONTROL_AFTERK: OFF
8903 14:44:35.970099 !!! SPM could not control APHY
8904 14:44:35.973335 IMPEDANCE_TRACKING: ON
8905 14:44:35.973417 TEMP_SENSOR: ON
8906 14:44:35.976967 HW_SAVE_FOR_SR: OFF
8907 14:44:35.977049 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8908 14:44:35.983348 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8909 14:44:35.983434 Read ODT Tracking: ON
8910 14:44:35.986633 Refresh Rate DeBounce: ON
8911 14:44:35.990089 DFS_NO_QUEUE_FLUSH: ON
8912 14:44:35.993345 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8913 14:44:35.993427 ENABLE_DFS_RUNTIME_MRW: OFF
8914 14:44:35.996654 DDR_RESERVE_NEW_MODE: ON
8915 14:44:35.999836 MR_CBT_SWITCH_FREQ: ON
8916 14:44:35.999918 =========================
8917 14:44:36.019504 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8918 14:44:36.022654 dram_init: ddr_geometry: 0
8919 14:44:36.040710 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8920 14:44:36.044634 dram_init: dram init end (result: 0)
8921 14:44:36.050587 DRAM-K: Full calibration passed in 23398 msecs
8922 14:44:36.053894 MRC: failed to locate region type 0.
8923 14:44:36.053978 DRAM rank0 size:0x80000000,
8924 14:44:36.057573 DRAM rank1 size=0x80000000
8925 14:44:36.067193 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8926 14:44:36.073911 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8927 14:44:36.080484 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8928 14:44:36.087304 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8929 14:44:36.090459 DRAM rank0 size:0x80000000,
8930 14:44:36.093632 DRAM rank1 size=0x80000000
8931 14:44:36.093715 CBMEM:
8932 14:44:36.096909 IMD: root @ 0xfffff000 254 entries.
8933 14:44:36.100306 IMD: root @ 0xffffec00 62 entries.
8934 14:44:36.103811 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8935 14:44:36.107538 WARNING: RO_VPD is uninitialized or empty.
8936 14:44:36.113427 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8937 14:44:36.120449 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8938 14:44:36.133025 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8939 14:44:36.144436 BS: romstage times (exec / console): total (unknown) / 22942 ms
8940 14:44:36.144551
8941 14:44:36.144618
8942 14:44:36.154557 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8943 14:44:36.157795 ARM64: Exception handlers installed.
8944 14:44:36.161109 ARM64: Testing exception
8945 14:44:36.164310 ARM64: Done test exception
8946 14:44:36.164391 Enumerating buses...
8947 14:44:36.167682 Show all devs... Before device enumeration.
8948 14:44:36.170880 Root Device: enabled 1
8949 14:44:36.174252 CPU_CLUSTER: 0: enabled 1
8950 14:44:36.174334 CPU: 00: enabled 1
8951 14:44:36.177840 Compare with tree...
8952 14:44:36.177922 Root Device: enabled 1
8953 14:44:36.181037 CPU_CLUSTER: 0: enabled 1
8954 14:44:36.184203 CPU: 00: enabled 1
8955 14:44:36.184285 Root Device scanning...
8956 14:44:36.187512 scan_static_bus for Root Device
8957 14:44:36.190745 CPU_CLUSTER: 0 enabled
8958 14:44:36.194422 scan_static_bus for Root Device done
8959 14:44:36.197460 scan_bus: bus Root Device finished in 8 msecs
8960 14:44:36.197542 done
8961 14:44:36.204016 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8962 14:44:36.207279 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8963 14:44:36.214076 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8964 14:44:36.217339 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8965 14:44:36.220665 Allocating resources...
8966 14:44:36.224123 Reading resources...
8967 14:44:36.227229 Root Device read_resources bus 0 link: 0
8968 14:44:36.227315 DRAM rank0 size:0x80000000,
8969 14:44:36.230360 DRAM rank1 size=0x80000000
8970 14:44:36.233629 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8971 14:44:36.236993 CPU: 00 missing read_resources
8972 14:44:36.243740 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8973 14:44:36.246886 Root Device read_resources bus 0 link: 0 done
8974 14:44:36.246970 Done reading resources.
8975 14:44:36.253765 Show resources in subtree (Root Device)...After reading.
8976 14:44:36.256747 Root Device child on link 0 CPU_CLUSTER: 0
8977 14:44:36.260049 CPU_CLUSTER: 0 child on link 0 CPU: 00
8978 14:44:36.270138 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8979 14:44:36.270231 CPU: 00
8980 14:44:36.273261 Root Device assign_resources, bus 0 link: 0
8981 14:44:36.276722 CPU_CLUSTER: 0 missing set_resources
8982 14:44:36.283282 Root Device assign_resources, bus 0 link: 0 done
8983 14:44:36.283367 Done setting resources.
8984 14:44:36.289857 Show resources in subtree (Root Device)...After assigning values.
8985 14:44:36.293222 Root Device child on link 0 CPU_CLUSTER: 0
8986 14:44:36.296683 CPU_CLUSTER: 0 child on link 0 CPU: 00
8987 14:44:36.306407 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8988 14:44:36.306498 CPU: 00
8989 14:44:36.309675 Done allocating resources.
8990 14:44:36.316335 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8991 14:44:36.316420 Enabling resources...
8992 14:44:36.316485 done.
8993 14:44:36.322963 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8994 14:44:36.323047 Initializing devices...
8995 14:44:36.326260 Root Device init
8996 14:44:36.326342 init hardware done!
8997 14:44:36.329742 0x00000018: ctrlr->caps
8998 14:44:36.332709 52.000 MHz: ctrlr->f_max
8999 14:44:36.332794 0.400 MHz: ctrlr->f_min
9000 14:44:36.336045 0x40ff8080: ctrlr->voltages
9001 14:44:36.339450 sclk: 390625
9002 14:44:36.339532 Bus Width = 1
9003 14:44:36.339595 sclk: 390625
9004 14:44:36.342992 Bus Width = 1
9005 14:44:36.343074 Early init status = 3
9006 14:44:36.349821 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9007 14:44:36.352546 in-header: 03 fc 00 00 01 00 00 00
9008 14:44:36.355920 in-data: 00
9009 14:44:36.359148 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9010 14:44:36.364062 in-header: 03 fd 00 00 00 00 00 00
9011 14:44:36.367307 in-data:
9012 14:44:36.370687 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9013 14:44:36.375242 in-header: 03 fc 00 00 01 00 00 00
9014 14:44:36.378350 in-data: 00
9015 14:44:36.381636 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9016 14:44:36.387378 in-header: 03 fd 00 00 00 00 00 00
9017 14:44:36.391083 in-data:
9018 14:44:36.394211 [SSUSB] Setting up USB HOST controller...
9019 14:44:36.397435 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9020 14:44:36.400692 [SSUSB] phy power-on done.
9021 14:44:36.403951 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9022 14:44:36.410424 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9023 14:44:36.414024 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9024 14:44:36.420422 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9025 14:44:36.427516 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9026 14:44:36.433695 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9027 14:44:36.440434 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9028 14:44:36.446984 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9029 14:44:36.450443 SPM: binary array size = 0x9dc
9030 14:44:36.453644 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9031 14:44:36.460545 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9032 14:44:36.466802 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9033 14:44:36.473553 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9034 14:44:36.476633 configure_display: Starting display init
9035 14:44:36.510907 anx7625_power_on_init: Init interface.
9036 14:44:36.514251 anx7625_disable_pd_protocol: Disabled PD feature.
9037 14:44:36.517274 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9038 14:44:36.545199 anx7625_start_dp_work: Secure OCM version=00
9039 14:44:36.548427 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9040 14:44:36.563055 sp_tx_get_edid_block: EDID Block = 1
9041 14:44:36.666103 Extracted contents:
9042 14:44:36.669132 header: 00 ff ff ff ff ff ff 00
9043 14:44:36.672422 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9044 14:44:36.675759 version: 01 04
9045 14:44:36.678976 basic params: 95 1f 11 78 0a
9046 14:44:36.682441 chroma info: 76 90 94 55 54 90 27 21 50 54
9047 14:44:36.685441 established: 00 00 00
9048 14:44:36.692157 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9049 14:44:36.695422 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9050 14:44:36.702257 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9051 14:44:36.708508 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9052 14:44:36.715064 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9053 14:44:36.718363 extensions: 00
9054 14:44:36.718444 checksum: fb
9055 14:44:36.718507
9056 14:44:36.721913 Manufacturer: IVO Model 57d Serial Number 0
9057 14:44:36.725000 Made week 0 of 2020
9058 14:44:36.728251 EDID version: 1.4
9059 14:44:36.728334 Digital display
9060 14:44:36.731688 6 bits per primary color channel
9061 14:44:36.731771 DisplayPort interface
9062 14:44:36.734887 Maximum image size: 31 cm x 17 cm
9063 14:44:36.738223 Gamma: 220%
9064 14:44:36.738304 Check DPMS levels
9065 14:44:36.741611 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9066 14:44:36.748193 First detailed timing is preferred timing
9067 14:44:36.748276 Established timings supported:
9068 14:44:36.751510 Standard timings supported:
9069 14:44:36.754899 Detailed timings
9070 14:44:36.758216 Hex of detail: 383680a07038204018303c0035ae10000019
9071 14:44:36.764922 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9072 14:44:36.768279 0780 0798 07c8 0820 hborder 0
9073 14:44:36.771406 0438 043b 0447 0458 vborder 0
9074 14:44:36.774622 -hsync -vsync
9075 14:44:36.774703 Did detailed timing
9076 14:44:36.781524 Hex of detail: 000000000000000000000000000000000000
9077 14:44:36.784560 Manufacturer-specified data, tag 0
9078 14:44:36.787885 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9079 14:44:36.791044 ASCII string: InfoVision
9080 14:44:36.794473 Hex of detail: 000000fe00523134304e574635205248200a
9081 14:44:36.797674 ASCII string: R140NWF5 RH
9082 14:44:36.797756 Checksum
9083 14:44:36.801086 Checksum: 0xfb (valid)
9084 14:44:36.804567 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9085 14:44:36.807612 DSI data_rate: 832800000 bps
9086 14:44:36.814471 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9087 14:44:36.817865 anx7625_parse_edid: pixelclock(138800).
9088 14:44:36.821083 hactive(1920), hsync(48), hfp(24), hbp(88)
9089 14:44:36.824350 vactive(1080), vsync(12), vfp(3), vbp(17)
9090 14:44:36.827794 anx7625_dsi_config: config dsi.
9091 14:44:36.834325 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9092 14:44:36.847779 anx7625_dsi_config: success to config DSI
9093 14:44:36.851155 anx7625_dp_start: MIPI phy setup OK.
9094 14:44:36.854368 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9095 14:44:36.857750 mtk_ddp_mode_set invalid vrefresh 60
9096 14:44:36.861048 main_disp_path_setup
9097 14:44:36.861129 ovl_layer_smi_id_en
9098 14:44:36.864271 ovl_layer_smi_id_en
9099 14:44:36.864352 ccorr_config
9100 14:44:36.864416 aal_config
9101 14:44:36.867591 gamma_config
9102 14:44:36.867672 postmask_config
9103 14:44:36.870827 dither_config
9104 14:44:36.874213 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9105 14:44:36.880774 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9106 14:44:36.884034 Root Device init finished in 554 msecs
9107 14:44:36.887327 CPU_CLUSTER: 0 init
9108 14:44:36.894067 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9109 14:44:36.900705 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9110 14:44:36.900787 APU_MBOX 0x190000b0 = 0x10001
9111 14:44:36.904116 APU_MBOX 0x190001b0 = 0x10001
9112 14:44:36.907277 APU_MBOX 0x190005b0 = 0x10001
9113 14:44:36.910507 APU_MBOX 0x190006b0 = 0x10001
9114 14:44:36.916914 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9115 14:44:36.926618 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9116 14:44:36.939048 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9117 14:44:36.945754 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9118 14:44:36.957415 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9119 14:44:36.966393 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9120 14:44:36.969709 CPU_CLUSTER: 0 init finished in 81 msecs
9121 14:44:36.972973 Devices initialized
9122 14:44:36.976313 Show all devs... After init.
9123 14:44:36.976395 Root Device: enabled 1
9124 14:44:36.979609 CPU_CLUSTER: 0: enabled 1
9125 14:44:36.982933 CPU: 00: enabled 1
9126 14:44:36.986322 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9127 14:44:36.989393 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9128 14:44:36.992969 ELOG: NV offset 0x57f000 size 0x1000
9129 14:44:36.999747 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9130 14:44:37.006324 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9131 14:44:37.009486 ELOG: Event(17) added with size 13 at 2024-06-04 14:44:36 UTC
9132 14:44:37.012749 out: cmd=0x121: 03 db 21 01 00 00 00 00
9133 14:44:37.017508 in-header: 03 0a 00 00 2c 00 00 00
9134 14:44:37.030960 in-data: 59 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9135 14:44:37.037448 ELOG: Event(A1) added with size 10 at 2024-06-04 14:44:36 UTC
9136 14:44:37.044246 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9137 14:44:37.050806 ELOG: Event(A0) added with size 9 at 2024-06-04 14:44:36 UTC
9138 14:44:37.053980 elog_add_boot_reason: Logged dev mode boot
9139 14:44:37.057609 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9140 14:44:37.061162 Finalize devices...
9141 14:44:37.061246 Devices finalized
9142 14:44:37.067547 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9143 14:44:37.070701 Writing coreboot table at 0xffe64000
9144 14:44:37.074069 0. 000000000010a000-0000000000113fff: RAMSTAGE
9145 14:44:37.077211 1. 0000000040000000-00000000400fffff: RAM
9146 14:44:37.083895 2. 0000000040100000-000000004032afff: RAMSTAGE
9147 14:44:37.087142 3. 000000004032b000-00000000545fffff: RAM
9148 14:44:37.090774 4. 0000000054600000-000000005465ffff: BL31
9149 14:44:37.093858 5. 0000000054660000-00000000ffe63fff: RAM
9150 14:44:37.100614 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9151 14:44:37.103847 7. 0000000100000000-000000013fffffff: RAM
9152 14:44:37.103930 Passing 5 GPIOs to payload:
9153 14:44:37.110300 NAME | PORT | POLARITY | VALUE
9154 14:44:37.113629 EC in RW | 0x000000aa | low | undefined
9155 14:44:37.120408 EC interrupt | 0x00000005 | low | undefined
9156 14:44:37.123901 TPM interrupt | 0x000000ab | high | undefined
9157 14:44:37.126925 SD card detect | 0x00000011 | high | undefined
9158 14:44:37.133566 speaker enable | 0x00000093 | high | undefined
9159 14:44:37.137019 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9160 14:44:37.140525 in-header: 03 f8 00 00 02 00 00 00
9161 14:44:37.140621 in-data: 03 00
9162 14:44:37.143422 ADC[4]: Raw value=669327 ID=5
9163 14:44:37.146818 ADC[3]: Raw value=212549 ID=1
9164 14:44:37.146900 RAM Code: 0x51
9165 14:44:37.150047 ADC[6]: Raw value=74410 ID=0
9166 14:44:37.153238 ADC[5]: Raw value=211444 ID=1
9167 14:44:37.153341 SKU Code: 0x1
9168 14:44:37.160188 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 15c8
9169 14:44:37.163298 coreboot table: 964 bytes.
9170 14:44:37.166616 IMD ROOT 0. 0xfffff000 0x00001000
9171 14:44:37.169891 IMD SMALL 1. 0xffffe000 0x00001000
9172 14:44:37.173400 RO MCACHE 2. 0xffffc000 0x00001104
9173 14:44:37.176515 CONSOLE 3. 0xfff7c000 0x00080000
9174 14:44:37.180222 FMAP 4. 0xfff7b000 0x00000452
9175 14:44:37.183015 TIME STAMP 5. 0xfff7a000 0x00000910
9176 14:44:37.186645 VBOOT WORK 6. 0xfff66000 0x00014000
9177 14:44:37.189738 RAMOOPS 7. 0xffe66000 0x00100000
9178 14:44:37.193293 COREBOOT 8. 0xffe64000 0x00002000
9179 14:44:37.193375 IMD small region:
9180 14:44:37.196321 IMD ROOT 0. 0xffffec00 0x00000400
9181 14:44:37.199803 VPD 1. 0xffffeb80 0x0000006c
9182 14:44:37.203249 MMC STATUS 2. 0xffffeb60 0x00000004
9183 14:44:37.209480 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9184 14:44:37.213179 Probing TPM: done!
9185 14:44:37.216569 Connected to device vid:did:rid of 1ae0:0028:00
9186 14:44:37.226552 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9187 14:44:37.229866 Initialized TPM device CR50 revision 0
9188 14:44:37.233154 Checking cr50 for pending updates
9189 14:44:37.237061 Reading cr50 TPM mode
9190 14:44:37.245618 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9191 14:44:37.251899 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9192 14:44:37.292055 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9193 14:44:37.295422 Checking segment from ROM address 0x40100000
9194 14:44:37.298726 Checking segment from ROM address 0x4010001c
9195 14:44:37.305491 Loading segment from ROM address 0x40100000
9196 14:44:37.305585 code (compression=0)
9197 14:44:37.315477 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9198 14:44:37.322039 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9199 14:44:37.322127 it's not compressed!
9200 14:44:37.328797 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9201 14:44:37.332130 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9202 14:44:37.352611 Loading segment from ROM address 0x4010001c
9203 14:44:37.352733 Entry Point 0x80000000
9204 14:44:37.355852 Loaded segments
9205 14:44:37.359084 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9206 14:44:37.365742 Jumping to boot code at 0x80000000(0xffe64000)
9207 14:44:37.372336 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9208 14:44:37.378930 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9209 14:44:37.386917 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9210 14:44:37.390652 Checking segment from ROM address 0x40100000
9211 14:44:37.393665 Checking segment from ROM address 0x4010001c
9212 14:44:37.400382 Loading segment from ROM address 0x40100000
9213 14:44:37.400477 code (compression=1)
9214 14:44:37.406880 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9215 14:44:37.416789 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9216 14:44:37.416894 using LZMA
9217 14:44:37.425599 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9218 14:44:37.432191 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9219 14:44:37.435194 Loading segment from ROM address 0x4010001c
9220 14:44:37.435283 Entry Point 0x54601000
9221 14:44:37.438696 Loaded segments
9222 14:44:37.441887 NOTICE: MT8192 bl31_setup
9223 14:44:37.448908 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9224 14:44:37.452308 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9225 14:44:37.455586 WARNING: region 0:
9226 14:44:37.458999 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9227 14:44:37.459085 WARNING: region 1:
9228 14:44:37.465412 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9229 14:44:37.469154 WARNING: region 2:
9230 14:44:37.472206 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9231 14:44:37.475443 WARNING: region 3:
9232 14:44:37.478925 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9233 14:44:37.482237 WARNING: region 4:
9234 14:44:37.488896 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9235 14:44:37.488982 WARNING: region 5:
9236 14:44:37.492217 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9237 14:44:37.495489 WARNING: region 6:
9238 14:44:37.498887 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9239 14:44:37.498996 WARNING: region 7:
9240 14:44:37.505698 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9241 14:44:37.512238 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9242 14:44:37.515635 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9243 14:44:37.519030 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9244 14:44:37.525596 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9245 14:44:37.529012 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9246 14:44:37.532296 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9247 14:44:37.538866 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9248 14:44:37.542197 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9249 14:44:37.545548 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9250 14:44:37.552318 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9251 14:44:37.555555 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9252 14:44:37.562215 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9253 14:44:37.565585 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9254 14:44:37.568800 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9255 14:44:37.575554 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9256 14:44:37.578936 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9257 14:44:37.582150 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9258 14:44:37.588730 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9259 14:44:37.592146 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9260 14:44:37.598814 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9261 14:44:37.602230 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9262 14:44:37.605609 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9263 14:44:37.612299 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9264 14:44:37.615745 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9265 14:44:37.622697 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9266 14:44:37.625783 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9267 14:44:37.628852 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9268 14:44:37.635520 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9269 14:44:37.638819 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9270 14:44:37.642354 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9271 14:44:37.649158 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9272 14:44:37.652113 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9273 14:44:37.658797 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9274 14:44:37.662151 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9275 14:44:37.665603 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9276 14:44:37.668927 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9277 14:44:37.672420 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9278 14:44:37.678950 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9279 14:44:37.682298 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9280 14:44:37.685711 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9281 14:44:37.689030 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9282 14:44:37.695613 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9283 14:44:37.698844 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9284 14:44:37.702470 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9285 14:44:37.705542 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9286 14:44:37.712323 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9287 14:44:37.715729 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9288 14:44:37.718897 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9289 14:44:37.725511 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9290 14:44:37.728843 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9291 14:44:37.735671 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9292 14:44:37.738783 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9293 14:44:37.742000 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9294 14:44:37.748603 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9295 14:44:37.751850 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9296 14:44:37.758653 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9297 14:44:37.761892 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9298 14:44:37.768458 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9299 14:44:37.771798 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9300 14:44:37.778526 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9301 14:44:37.781814 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9302 14:44:37.785124 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9303 14:44:37.791721 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9304 14:44:37.795146 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9305 14:44:37.801855 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9306 14:44:37.805216 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9307 14:44:37.811857 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9308 14:44:37.815103 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9309 14:44:37.818389 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9310 14:44:37.825003 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9311 14:44:37.828427 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9312 14:44:37.835177 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9313 14:44:37.838332 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9314 14:44:37.844950 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9315 14:44:37.848451 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9316 14:44:37.851765 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9317 14:44:37.858318 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9318 14:44:37.861761 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9319 14:44:37.868440 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9320 14:44:37.871735 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9321 14:44:37.878582 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9322 14:44:37.881629 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9323 14:44:37.888766 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9324 14:44:37.891672 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9325 14:44:37.895203 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9326 14:44:37.901643 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9327 14:44:37.905091 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9328 14:44:37.911687 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9329 14:44:37.915214 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9330 14:44:37.918511 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9331 14:44:37.925027 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9332 14:44:37.928361 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9333 14:44:37.934911 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9334 14:44:37.938634 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9335 14:44:37.945150 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9336 14:44:37.948243 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9337 14:44:37.951656 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9338 14:44:37.958402 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9339 14:44:37.961887 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9340 14:44:37.965052 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9341 14:44:37.968300 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9342 14:44:37.975392 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9343 14:44:37.978430 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9344 14:44:37.984835 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9345 14:44:37.988264 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9346 14:44:37.991646 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9347 14:44:37.998516 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9348 14:44:38.001920 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9349 14:44:38.008173 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9350 14:44:38.011752 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9351 14:44:38.014996 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9352 14:44:38.021691 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9353 14:44:38.024884 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9354 14:44:38.031579 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9355 14:44:38.034918 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9356 14:44:38.038200 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9357 14:44:38.044723 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9358 14:44:38.048049 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9359 14:44:38.051514 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9360 14:44:38.058225 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9361 14:44:38.061564 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9362 14:44:38.064988 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9363 14:44:38.067986 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9364 14:44:38.071544 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9365 14:44:38.078104 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9366 14:44:38.081295 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9367 14:44:38.088006 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9368 14:44:38.091428 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9369 14:44:38.094751 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9370 14:44:38.101220 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9371 14:44:38.104677 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9372 14:44:38.111583 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9373 14:44:38.114792 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9374 14:44:38.118220 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9375 14:44:38.124743 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9376 14:44:38.128005 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9377 14:44:38.134737 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9378 14:44:38.138101 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9379 14:44:38.141364 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9380 14:44:38.148185 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9381 14:44:38.151357 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9382 14:44:38.154706 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9383 14:44:38.161641 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9384 14:44:38.164767 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9385 14:44:38.171485 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9386 14:44:38.174872 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9387 14:44:38.178154 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9388 14:44:38.184820 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9389 14:44:38.188400 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9390 14:44:38.194599 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9391 14:44:38.197884 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9392 14:44:38.201234 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9393 14:44:38.207993 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9394 14:44:38.211466 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9395 14:44:38.214692 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9396 14:44:38.221396 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9397 14:44:38.224693 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9398 14:44:38.231377 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9399 14:44:38.234573 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9400 14:44:38.237999 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9401 14:44:38.244799 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9402 14:44:38.247972 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9403 14:44:38.254506 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9404 14:44:38.257848 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9405 14:44:38.260993 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9406 14:44:38.267721 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9407 14:44:38.271001 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9408 14:44:38.277569 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9409 14:44:38.280927 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9410 14:44:38.284399 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9411 14:44:38.291010 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9412 14:44:38.294454 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9413 14:44:38.300682 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9414 14:44:38.304193 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9415 14:44:38.307405 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9416 14:44:38.314286 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9417 14:44:38.317210 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9418 14:44:38.323972 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9419 14:44:38.327275 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9420 14:44:38.330651 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9421 14:44:38.337127 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9422 14:44:38.340656 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9423 14:44:38.344062 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9424 14:44:38.350626 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9425 14:44:38.353795 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9426 14:44:38.360343 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9427 14:44:38.363627 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9428 14:44:38.367110 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9429 14:44:38.373976 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9430 14:44:38.377072 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9431 14:44:38.384113 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9432 14:44:38.387131 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9433 14:44:38.393699 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9434 14:44:38.396831 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9435 14:44:38.400265 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9436 14:44:38.406849 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9437 14:44:38.410065 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9438 14:44:38.416751 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9439 14:44:38.420075 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9440 14:44:38.426696 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9441 14:44:38.430027 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9442 14:44:38.433571 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9443 14:44:38.439993 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9444 14:44:38.443168 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9445 14:44:38.449972 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9446 14:44:38.453307 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9447 14:44:38.456547 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9448 14:44:38.463207 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9449 14:44:38.466745 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9450 14:44:38.473105 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9451 14:44:38.476393 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9452 14:44:38.482981 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9453 14:44:38.486269 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9454 14:44:38.489556 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9455 14:44:38.496315 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9456 14:44:38.499767 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9457 14:44:38.506253 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9458 14:44:38.509880 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9459 14:44:38.512960 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9460 14:44:38.519872 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9461 14:44:38.522842 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9462 14:44:38.529427 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9463 14:44:38.532650 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9464 14:44:38.539542 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9465 14:44:38.542553 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9466 14:44:38.545879 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9467 14:44:38.552575 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9468 14:44:38.555889 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9469 14:44:38.562495 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9470 14:44:38.565628 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9471 14:44:38.569141 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9472 14:44:38.572254 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9473 14:44:38.579195 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9474 14:44:38.582484 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9475 14:44:38.585607 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9476 14:44:38.592156 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9477 14:44:38.595951 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9478 14:44:38.599062 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9479 14:44:38.605469 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9480 14:44:38.609315 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9481 14:44:38.612113 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9482 14:44:38.618630 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9483 14:44:38.622099 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9484 14:44:38.625399 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9485 14:44:38.631848 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9486 14:44:38.635035 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9487 14:44:38.642017 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9488 14:44:38.645015 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9489 14:44:38.648602 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9490 14:44:38.654843 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9491 14:44:38.658361 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9492 14:44:38.664999 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9493 14:44:38.668166 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9494 14:44:38.671493 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9495 14:44:38.678011 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9496 14:44:38.681812 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9497 14:44:38.684583 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9498 14:44:38.691268 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9499 14:44:38.694558 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9500 14:44:38.698262 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9501 14:44:38.704757 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9502 14:44:38.708019 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9503 14:44:38.714370 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9504 14:44:38.717854 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9505 14:44:38.721176 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9506 14:44:38.727731 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9507 14:44:38.730991 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9508 14:44:38.737489 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9509 14:44:38.740761 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9510 14:44:38.744212 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9511 14:44:38.747639 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9512 14:44:38.750674 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9513 14:44:38.757262 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9514 14:44:38.760853 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9515 14:44:38.763981 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9516 14:44:38.767401 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9517 14:44:38.774617 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9518 14:44:38.777259 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9519 14:44:38.780575 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9520 14:44:38.783870 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9521 14:44:38.790527 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9522 14:44:38.794043 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9523 14:44:38.797624 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9524 14:44:38.803849 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9525 14:44:38.807260 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9526 14:44:38.813763 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9527 14:44:38.816978 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9528 14:44:38.823601 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9529 14:44:38.826955 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9530 14:44:38.830608 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9531 14:44:38.836988 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9532 14:44:38.840306 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9533 14:44:38.846823 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9534 14:44:38.850236 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9535 14:44:38.853662 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9536 14:44:38.860243 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9537 14:44:38.863612 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9538 14:44:38.870181 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9539 14:44:38.873270 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9540 14:44:38.876638 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9541 14:44:38.883284 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9542 14:44:38.886526 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9543 14:44:38.893246 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9544 14:44:38.896509 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9545 14:44:38.903636 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9546 14:44:38.906530 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9547 14:44:38.909697 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9548 14:44:38.916598 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9549 14:44:38.919672 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9550 14:44:38.926295 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9551 14:44:38.929711 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9552 14:44:38.933099 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9553 14:44:38.939405 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9554 14:44:38.942996 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9555 14:44:38.949568 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9556 14:44:38.952664 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9557 14:44:38.959630 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9558 14:44:38.962737 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9559 14:44:38.966201 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9560 14:44:38.972854 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9561 14:44:38.976336 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9562 14:44:38.982843 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9563 14:44:38.985965 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9564 14:44:38.989154 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9565 14:44:38.995811 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9566 14:44:38.998945 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9567 14:44:39.005519 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9568 14:44:39.009015 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9569 14:44:39.015715 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9570 14:44:39.019067 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9571 14:44:39.022237 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9572 14:44:39.029041 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9573 14:44:39.032084 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9574 14:44:39.038895 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9575 14:44:39.042429 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9576 14:44:39.045499 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9577 14:44:39.052082 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9578 14:44:39.055588 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9579 14:44:39.058733 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9580 14:44:39.065399 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9581 14:44:39.068892 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9582 14:44:39.075419 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9583 14:44:39.078699 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9584 14:44:39.085246 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9585 14:44:39.088607 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9586 14:44:39.092078 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9587 14:44:39.098523 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9588 14:44:39.101918 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9589 14:44:39.108584 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9590 14:44:39.111907 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9591 14:44:39.115372 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9592 14:44:39.121893 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9593 14:44:39.125248 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9594 14:44:39.131728 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9595 14:44:39.135138 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9596 14:44:39.141704 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9597 14:44:39.145041 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9598 14:44:39.148206 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9599 14:44:39.155038 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9600 14:44:39.158342 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9601 14:44:39.165073 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9602 14:44:39.168374 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9603 14:44:39.174901 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9604 14:44:39.178326 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9605 14:44:39.181751 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9606 14:44:39.188121 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9607 14:44:39.191319 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9608 14:44:39.198174 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9609 14:44:39.201257 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9610 14:44:39.207989 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9611 14:44:39.211387 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9612 14:44:39.217766 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9613 14:44:39.220957 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9614 14:44:39.224457 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9615 14:44:39.231019 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9616 14:44:39.234250 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9617 14:44:39.241045 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9618 14:44:39.244220 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9619 14:44:39.250999 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9620 14:44:39.254341 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9621 14:44:39.260866 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9622 14:44:39.264034 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9623 14:44:39.267287 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9624 14:44:39.274143 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9625 14:44:39.277251 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9626 14:44:39.283923 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9627 14:44:39.287346 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9628 14:44:39.294105 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9629 14:44:39.297610 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9630 14:44:39.300760 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9631 14:44:39.307149 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9632 14:44:39.310849 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9633 14:44:39.317531 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9634 14:44:39.320634 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9635 14:44:39.327226 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9636 14:44:39.330814 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9637 14:44:39.333964 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9638 14:44:39.340452 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9639 14:44:39.343887 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9640 14:44:39.350551 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9641 14:44:39.353859 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9642 14:44:39.360489 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9643 14:44:39.363649 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9644 14:44:39.367166 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9645 14:44:39.373781 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9646 14:44:39.376872 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9647 14:44:39.383744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9648 14:44:39.387009 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9649 14:44:39.393690 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9650 14:44:39.396730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9651 14:44:39.403787 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9652 14:44:39.406999 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9653 14:44:39.413369 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9654 14:44:39.416785 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9655 14:44:39.423216 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9656 14:44:39.426566 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9657 14:44:39.433357 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9658 14:44:39.436545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9659 14:44:39.443218 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9660 14:44:39.446549 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9661 14:44:39.453096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9662 14:44:39.456237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9663 14:44:39.462977 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9664 14:44:39.466218 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9665 14:44:39.472826 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9666 14:44:39.476168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9667 14:44:39.482675 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9668 14:44:39.485995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9669 14:44:39.492633 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9670 14:44:39.495893 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9671 14:44:39.502568 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9672 14:44:39.505851 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9673 14:44:39.512546 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9674 14:44:39.515794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9675 14:44:39.519507 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9676 14:44:39.522437 INFO: [APUAPC] vio 0
9677 14:44:39.529099 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9678 14:44:39.532240 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9679 14:44:39.535578 INFO: [APUAPC] D0_APC_0: 0x400510
9680 14:44:39.539047 INFO: [APUAPC] D0_APC_1: 0x0
9681 14:44:39.542269 INFO: [APUAPC] D0_APC_2: 0x1540
9682 14:44:39.545660 INFO: [APUAPC] D0_APC_3: 0x0
9683 14:44:39.549093 INFO: [APUAPC] D1_APC_0: 0xffffffff
9684 14:44:39.552382 INFO: [APUAPC] D1_APC_1: 0xffffffff
9685 14:44:39.555427 INFO: [APUAPC] D1_APC_2: 0x3fffff
9686 14:44:39.558642 INFO: [APUAPC] D1_APC_3: 0x0
9687 14:44:39.562136 INFO: [APUAPC] D2_APC_0: 0xffffffff
9688 14:44:39.565351 INFO: [APUAPC] D2_APC_1: 0xffffffff
9689 14:44:39.568593 INFO: [APUAPC] D2_APC_2: 0x3fffff
9690 14:44:39.572067 INFO: [APUAPC] D2_APC_3: 0x0
9691 14:44:39.575398 INFO: [APUAPC] D3_APC_0: 0xffffffff
9692 14:44:39.578615 INFO: [APUAPC] D3_APC_1: 0xffffffff
9693 14:44:39.582191 INFO: [APUAPC] D3_APC_2: 0x3fffff
9694 14:44:39.582273 INFO: [APUAPC] D3_APC_3: 0x0
9695 14:44:39.588737 INFO: [APUAPC] D4_APC_0: 0xffffffff
9696 14:44:39.591822 INFO: [APUAPC] D4_APC_1: 0xffffffff
9697 14:44:39.595426 INFO: [APUAPC] D4_APC_2: 0x3fffff
9698 14:44:39.595508 INFO: [APUAPC] D4_APC_3: 0x0
9699 14:44:39.598566 INFO: [APUAPC] D5_APC_0: 0xffffffff
9700 14:44:39.605129 INFO: [APUAPC] D5_APC_1: 0xffffffff
9701 14:44:39.605213 INFO: [APUAPC] D5_APC_2: 0x3fffff
9702 14:44:39.608399 INFO: [APUAPC] D5_APC_3: 0x0
9703 14:44:39.611914 INFO: [APUAPC] D6_APC_0: 0xffffffff
9704 14:44:39.614984 INFO: [APUAPC] D6_APC_1: 0xffffffff
9705 14:44:39.618547 INFO: [APUAPC] D6_APC_2: 0x3fffff
9706 14:44:39.621744 INFO: [APUAPC] D6_APC_3: 0x0
9707 14:44:39.624917 INFO: [APUAPC] D7_APC_0: 0xffffffff
9708 14:44:39.628334 INFO: [APUAPC] D7_APC_1: 0xffffffff
9709 14:44:39.631835 INFO: [APUAPC] D7_APC_2: 0x3fffff
9710 14:44:39.634892 INFO: [APUAPC] D7_APC_3: 0x0
9711 14:44:39.638199 INFO: [APUAPC] D8_APC_0: 0xffffffff
9712 14:44:39.641557 INFO: [APUAPC] D8_APC_1: 0xffffffff
9713 14:44:39.644849 INFO: [APUAPC] D8_APC_2: 0x3fffff
9714 14:44:39.648412 INFO: [APUAPC] D8_APC_3: 0x0
9715 14:44:39.651629 INFO: [APUAPC] D9_APC_0: 0xffffffff
9716 14:44:39.654673 INFO: [APUAPC] D9_APC_1: 0xffffffff
9717 14:44:39.658115 INFO: [APUAPC] D9_APC_2: 0x3fffff
9718 14:44:39.661573 INFO: [APUAPC] D9_APC_3: 0x0
9719 14:44:39.664713 INFO: [APUAPC] D10_APC_0: 0xffffffff
9720 14:44:39.668060 INFO: [APUAPC] D10_APC_1: 0xffffffff
9721 14:44:39.671445 INFO: [APUAPC] D10_APC_2: 0x3fffff
9722 14:44:39.674765 INFO: [APUAPC] D10_APC_3: 0x0
9723 14:44:39.677794 INFO: [APUAPC] D11_APC_0: 0xffffffff
9724 14:44:39.681198 INFO: [APUAPC] D11_APC_1: 0xffffffff
9725 14:44:39.684759 INFO: [APUAPC] D11_APC_2: 0x3fffff
9726 14:44:39.687626 INFO: [APUAPC] D11_APC_3: 0x0
9727 14:44:39.691113 INFO: [APUAPC] D12_APC_0: 0xffffffff
9728 14:44:39.694331 INFO: [APUAPC] D12_APC_1: 0xffffffff
9729 14:44:39.697718 INFO: [APUAPC] D12_APC_2: 0x3fffff
9730 14:44:39.701213 INFO: [APUAPC] D12_APC_3: 0x0
9731 14:44:39.704370 INFO: [APUAPC] D13_APC_0: 0xffffffff
9732 14:44:39.707830 INFO: [APUAPC] D13_APC_1: 0xffffffff
9733 14:44:39.710972 INFO: [APUAPC] D13_APC_2: 0x3fffff
9734 14:44:39.714480 INFO: [APUAPC] D13_APC_3: 0x0
9735 14:44:39.717882 INFO: [APUAPC] D14_APC_0: 0xffffffff
9736 14:44:39.721008 INFO: [APUAPC] D14_APC_1: 0xffffffff
9737 14:44:39.724259 INFO: [APUAPC] D14_APC_2: 0x3fffff
9738 14:44:39.727508 INFO: [APUAPC] D14_APC_3: 0x0
9739 14:44:39.731082 INFO: [APUAPC] D15_APC_0: 0xffffffff
9740 14:44:39.734106 INFO: [APUAPC] D15_APC_1: 0xffffffff
9741 14:44:39.737366 INFO: [APUAPC] D15_APC_2: 0x3fffff
9742 14:44:39.740813 INFO: [APUAPC] D15_APC_3: 0x0
9743 14:44:39.743980 INFO: [APUAPC] APC_CON: 0x4
9744 14:44:39.747376 INFO: [NOCDAPC] D0_APC_0: 0x0
9745 14:44:39.750728 INFO: [NOCDAPC] D0_APC_1: 0x0
9746 14:44:39.754218 INFO: [NOCDAPC] D1_APC_0: 0x0
9747 14:44:39.757273 INFO: [NOCDAPC] D1_APC_1: 0xfff
9748 14:44:39.760491 INFO: [NOCDAPC] D2_APC_0: 0x0
9749 14:44:39.763822 INFO: [NOCDAPC] D2_APC_1: 0xfff
9750 14:44:39.763905 INFO: [NOCDAPC] D3_APC_0: 0x0
9751 14:44:39.767174 INFO: [NOCDAPC] D3_APC_1: 0xfff
9752 14:44:39.770594 INFO: [NOCDAPC] D4_APC_0: 0x0
9753 14:44:39.773891 INFO: [NOCDAPC] D4_APC_1: 0xfff
9754 14:44:39.776981 INFO: [NOCDAPC] D5_APC_0: 0x0
9755 14:44:39.780319 INFO: [NOCDAPC] D5_APC_1: 0xfff
9756 14:44:39.783811 INFO: [NOCDAPC] D6_APC_0: 0x0
9757 14:44:39.786991 INFO: [NOCDAPC] D6_APC_1: 0xfff
9758 14:44:39.790318 INFO: [NOCDAPC] D7_APC_0: 0x0
9759 14:44:39.793705 INFO: [NOCDAPC] D7_APC_1: 0xfff
9760 14:44:39.796969 INFO: [NOCDAPC] D8_APC_0: 0x0
9761 14:44:39.797051 INFO: [NOCDAPC] D8_APC_1: 0xfff
9762 14:44:39.800337 INFO: [NOCDAPC] D9_APC_0: 0x0
9763 14:44:39.803809 INFO: [NOCDAPC] D9_APC_1: 0xfff
9764 14:44:39.806892 INFO: [NOCDAPC] D10_APC_0: 0x0
9765 14:44:39.810392 INFO: [NOCDAPC] D10_APC_1: 0xfff
9766 14:44:39.813683 INFO: [NOCDAPC] D11_APC_0: 0x0
9767 14:44:39.816956 INFO: [NOCDAPC] D11_APC_1: 0xfff
9768 14:44:39.820328 INFO: [NOCDAPC] D12_APC_0: 0x0
9769 14:44:39.823577 INFO: [NOCDAPC] D12_APC_1: 0xfff
9770 14:44:39.826960 INFO: [NOCDAPC] D13_APC_0: 0x0
9771 14:44:39.830173 INFO: [NOCDAPC] D13_APC_1: 0xfff
9772 14:44:39.833633 INFO: [NOCDAPC] D14_APC_0: 0x0
9773 14:44:39.837013 INFO: [NOCDAPC] D14_APC_1: 0xfff
9774 14:44:39.840302 INFO: [NOCDAPC] D15_APC_0: 0x0
9775 14:44:39.840385 INFO: [NOCDAPC] D15_APC_1: 0xfff
9776 14:44:39.843390 INFO: [NOCDAPC] APC_CON: 0x4
9777 14:44:39.846783 INFO: [APUAPC] set_apusys_apc done
9778 14:44:39.850050 INFO: [DEVAPC] devapc_init done
9779 14:44:39.856870 INFO: GICv3 without legacy support detected.
9780 14:44:39.860035 INFO: ARM GICv3 driver initialized in EL3
9781 14:44:39.863356 INFO: Maximum SPI INTID supported: 639
9782 14:44:39.866692 INFO: BL31: Initializing runtime services
9783 14:44:39.873603 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9784 14:44:39.876749 INFO: SPM: enable CPC mode
9785 14:44:39.880251 INFO: mcdi ready for mcusys-off-idle and system suspend
9786 14:44:39.886749 INFO: BL31: Preparing for EL3 exit to normal world
9787 14:44:39.889919 INFO: Entry point address = 0x80000000
9788 14:44:39.890002 INFO: SPSR = 0x8
9789 14:44:39.896655
9790 14:44:39.896738
9791 14:44:39.896802
9792 14:44:39.900004 Starting depthcharge on Spherion...
9793 14:44:39.900087
9794 14:44:39.900152 Wipe memory regions:
9795 14:44:39.900212
9796 14:44:39.900858 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9797 14:44:39.900962 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9798 14:44:39.901047 Setting prompt string to ['asurada:']
9799 14:44:39.901126 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9800 14:44:39.903465 [0x00000040000000, 0x00000054600000)
9801 14:44:40.025888
9802 14:44:40.026043 [0x00000054660000, 0x00000080000000)
9803 14:44:40.286213
9804 14:44:40.286369 [0x000000821a7280, 0x000000ffe64000)
9805 14:44:41.030922
9806 14:44:41.031127 [0x00000100000000, 0x00000140000000)
9807 14:44:41.411722
9808 14:44:41.414890 Initializing XHCI USB controller at 0x11200000.
9809 14:44:42.452979
9810 14:44:42.456014 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9811 14:44:42.456573
9812 14:44:42.456939
9813 14:44:42.457779 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9815 14:44:42.559217 asurada: tftpboot 192.168.201.1 14166991/tftp-deploy-4m917e0t/kernel/image.itb 14166991/tftp-deploy-4m917e0t/kernel/cmdline
9816 14:44:42.559828 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9817 14:44:42.560361 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9818 14:44:42.564978 tftpboot 192.168.201.1 14166991/tftp-deploy-4m917e0t/kernel/image.itbtp-deploy-4m917e0t/kernel/cmdline
9819 14:44:42.565557
9820 14:44:42.565896 Waiting for link
9821 14:44:42.725347
9822 14:44:42.725878 R8152: Initializing
9823 14:44:42.726210
9824 14:44:42.728541 Version 9 (ocp_data = 6010)
9825 14:44:42.728953
9826 14:44:42.731970 R8152: Done initializing
9827 14:44:42.732388
9828 14:44:42.732715 Adding net device
9829 14:44:44.708787
9830 14:44:44.709395 done.
9831 14:44:44.709769
9832 14:44:44.710103 MAC: 00:e0:4c:68:03:bd
9833 14:44:44.710542
9834 14:44:44.711907 Sending DHCP discover... done.
9835 14:44:44.712360
9836 14:44:44.714921 Waiting for reply... done.
9837 14:44:44.714999
9838 14:44:44.718148 Sending DHCP request... done.
9839 14:44:44.718233
9840 14:44:44.722014 Waiting for reply... done.
9841 14:44:44.722176
9842 14:44:44.722248 My ip is 192.168.201.16
9843 14:44:44.722311
9844 14:44:44.725081 The DHCP server ip is 192.168.201.1
9845 14:44:44.725250
9846 14:44:44.727995 TFTP server IP predefined by user: 192.168.201.1
9847 14:44:44.731526
9848 14:44:44.738350 Bootfile predefined by user: 14166991/tftp-deploy-4m917e0t/kernel/image.itb
9849 14:44:44.738548
9850 14:44:44.738650 Sending tftp read request... done.
9851 14:44:44.738744
9852 14:44:44.744951 Waiting for the transfer...
9853 14:44:44.745087
9854 14:44:45.036568 00000000 ################################################################
9855 14:44:45.036713
9856 14:44:45.303808 00080000 ################################################################
9857 14:44:45.303952
9858 14:44:45.557590 00100000 ################################################################
9859 14:44:45.557760
9860 14:44:45.810661 00180000 ################################################################
9861 14:44:45.810805
9862 14:44:46.061220 00200000 ################################################################
9863 14:44:46.061428
9864 14:44:46.311897 00280000 ################################################################
9865 14:44:46.312054
9866 14:44:46.561155 00300000 ################################################################
9867 14:44:46.561354
9868 14:44:46.811476 00380000 ################################################################
9869 14:44:46.811642
9870 14:44:47.061774 00400000 ################################################################
9871 14:44:47.061918
9872 14:44:47.312447 00480000 ################################################################
9873 14:44:47.312603
9874 14:44:47.561948 00500000 ################################################################
9875 14:44:47.562130
9876 14:44:47.811916 00580000 ################################################################
9877 14:44:47.812077
9878 14:44:48.062814 00600000 ################################################################
9879 14:44:48.062957
9880 14:44:48.295698 00680000 ################################################################
9881 14:44:48.295834
9882 14:44:48.536221 00700000 ################################################################
9883 14:44:48.536387
9884 14:44:48.793409 00780000 ################################################################
9885 14:44:48.793553
9886 14:44:49.043744 00800000 ################################################################
9887 14:44:49.043900
9888 14:44:49.294408 00880000 ################################################################
9889 14:44:49.294534
9890 14:44:49.578487 00900000 ################################################################
9891 14:44:49.578643
9892 14:44:49.833705 00980000 ################################################################
9893 14:44:49.833837
9894 14:44:50.086602 00a00000 ################################################################
9895 14:44:50.086770
9896 14:44:50.337122 00a80000 ################################################################
9897 14:44:50.337273
9898 14:44:50.601775 00b00000 ################################################################
9899 14:44:50.601914
9900 14:44:50.899486 00b80000 ################################################################
9901 14:44:50.899647
9902 14:44:51.186032 00c00000 ################################################################
9903 14:44:51.186167
9904 14:44:51.441579 00c80000 ################################################################
9905 14:44:51.441719
9906 14:44:51.696570 00d00000 ################################################################
9907 14:44:51.696727
9908 14:44:51.972176 00d80000 ################################################################
9909 14:44:51.972348
9910 14:44:52.246216 00e00000 ################################################################
9911 14:44:52.246352
9912 14:44:52.499727 00e80000 ################################################################
9913 14:44:52.499903
9914 14:44:52.761384 00f00000 ################################################################
9915 14:44:52.761550
9916 14:44:53.010981 00f80000 ################################################################
9917 14:44:53.011118
9918 14:44:53.261611 01000000 ################################################################
9919 14:44:53.261741
9920 14:44:53.517638 01080000 ################################################################
9921 14:44:53.517794
9922 14:44:53.769433 01100000 ################################################################
9923 14:44:53.769564
9924 14:44:54.041560 01180000 ################################################################
9925 14:44:54.041696
9926 14:44:54.344900 01200000 ################################################################
9927 14:44:54.345039
9928 14:44:54.626008 01280000 ################################################################
9929 14:44:54.626143
9930 14:44:54.886088 01300000 ################################################################
9931 14:44:54.886224
9932 14:44:55.146271 01380000 ################################################################
9933 14:44:55.146408
9934 14:44:55.413745 01400000 ################################################################
9935 14:44:55.413879
9936 14:44:55.667980 01480000 ################################################################
9937 14:44:55.668132
9938 14:44:55.918282 01500000 ################################################################
9939 14:44:55.918413
9940 14:44:56.195225 01580000 ################################################################
9941 14:44:56.195358
9942 14:44:56.466395 01600000 ################################################################
9943 14:44:56.466528
9944 14:44:56.755565 01680000 ################################################################
9945 14:44:56.755704
9946 14:44:57.022362 01700000 ################################################################
9947 14:44:57.022495
9948 14:44:57.299086 01780000 ################################################################
9949 14:44:57.299235
9950 14:44:57.565195 01800000 ################################################################
9951 14:44:57.565368
9952 14:44:57.821044 01880000 ################################################################
9953 14:44:57.821172
9954 14:44:58.090194 01900000 ################################################################
9955 14:44:58.090327
9956 14:44:58.377165 01980000 ################################################################
9957 14:44:58.377357
9958 14:44:58.649573 01a00000 ################################################################
9959 14:44:58.649764
9960 14:44:58.913283 01a80000 ################################################################
9961 14:44:58.913509
9962 14:44:59.151977 01b00000 ################################################################
9963 14:44:59.152114
9964 14:44:59.409666 01b80000 ################################################################
9965 14:44:59.409800
9966 14:44:59.672603 01c00000 ################################################################
9967 14:44:59.672746
9968 14:44:59.922108 01c80000 ################################################################
9969 14:44:59.922240
9970 14:45:00.177709 01d00000 ################################################################
9971 14:45:00.177873
9972 14:45:00.444603 01d80000 ################################################################
9973 14:45:00.444738
9974 14:45:00.643075 01e00000 ############################################### done.
9975 14:45:00.643211
9976 14:45:00.646261 The bootfile was 31840842 bytes long.
9977 14:45:00.646346
9978 14:45:00.649675 Sending tftp read request... done.
9979 14:45:00.649764
9980 14:45:00.649830 Waiting for the transfer...
9981 14:45:00.649890
9982 14:45:00.652983 00000000 # done.
9983 14:45:00.653062
9984 14:45:00.659660 Command line loaded dynamically from TFTP file: 14166991/tftp-deploy-4m917e0t/kernel/cmdline
9985 14:45:00.659734
9986 14:45:00.682888 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14166991/extract-nfsrootfs-__ac4z7s,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
9987 14:45:00.682993
9988 14:45:00.683064 Loading FIT.
9989 14:45:00.683125
9990 14:45:00.686124 Image ramdisk-1 has 18730931 bytes.
9991 14:45:00.686221
9992 14:45:00.689557 Image fdt-1 has 47258 bytes.
9993 14:45:00.689640
9994 14:45:00.692480 Image kernel-1 has 13060619 bytes.
9995 14:45:00.692562
9996 14:45:00.702619 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
9997 14:45:00.702704
9998 14:45:00.718976 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
9999 14:45:00.719064
10000 14:45:00.725591 Choosing best match conf-1 for compat google,spherion-rev3.
10001 14:45:00.729073
10002 14:45:00.733886 Connected to device vid:did:rid of 1ae0:0028:00
10003 14:45:00.740463
10004 14:45:00.743716 tpm_get_response: command 0x17b, return code 0x0
10005 14:45:00.743796
10006 14:45:00.746873 ec_init: CrosEC protocol v3 supported (256, 248)
10007 14:45:00.750880
10008 14:45:00.754454 tpm_cleanup: add release locality here.
10009 14:45:00.754566
10010 14:45:00.754635 Shutting down all USB controllers.
10011 14:45:00.757765
10012 14:45:00.757846 Removing current net device
10013 14:45:00.757911
10014 14:45:00.764451 Exiting depthcharge with code 4 at timestamp: 49073231
10015 14:45:00.764533
10016 14:45:00.767774 LZMA decompressing kernel-1 to 0x821a6718
10017 14:45:00.767856
10018 14:45:00.770968 LZMA decompressing kernel-1 to 0x40000000
10019 14:45:02.381646
10020 14:45:02.381787 jumping to kernel
10021 14:45:02.382249 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10022 14:45:02.382351 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
10023 14:45:02.382428 Setting prompt string to ['Linux version [0-9]']
10024 14:45:02.382497 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10025 14:45:02.382566 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10026 14:45:02.432425
10027 14:45:02.435824 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10028 14:45:02.439014 start: 2.2.5.1 login-action (timeout 00:04:04) [common]
10029 14:45:02.439112 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10030 14:45:02.439184 Setting prompt string to []
10031 14:45:02.439260 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10032 14:45:02.439334 Using line separator: #'\n'#
10033 14:45:02.439394 No login prompt set.
10034 14:45:02.439456 Parsing kernel messages
10035 14:45:02.439512 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10036 14:45:02.439616 [login-action] Waiting for messages, (timeout 00:04:04)
10037 14:45:02.439683 Waiting using forced prompt support (timeout 00:02:02)
10038 14:45:02.458710 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j216541-arm64-gcc-10-defconfig-arm64-chromebook-f7c97) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024
10039 14:45:02.462074 [ 0.000000] random: crng init done
10040 14:45:02.468734 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10041 14:45:02.472258 [ 0.000000] efi: UEFI not found.
10042 14:45:02.478733 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10043 14:45:02.488783 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10044 14:45:02.495233 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10045 14:45:02.505091 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10046 14:45:02.511780 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10047 14:45:02.518034 [ 0.000000] printk: bootconsole [mtk8250] enabled
10048 14:45:02.524905 [ 0.000000] NUMA: No NUMA configuration found
10049 14:45:02.531573 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10050 14:45:02.534670 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10051 14:45:02.537875 [ 0.000000] Zone ranges:
10052 14:45:02.545007 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10053 14:45:02.548049 [ 0.000000] DMA32 empty
10054 14:45:02.554514 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10055 14:45:02.557726 [ 0.000000] Movable zone start for each node
10056 14:45:02.561013 [ 0.000000] Early memory node ranges
10057 14:45:02.567847 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10058 14:45:02.574187 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10059 14:45:02.581028 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10060 14:45:02.587568 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10061 14:45:02.594098 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10062 14:45:02.600457 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10063 14:45:02.631454 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10064 14:45:02.637792 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10065 14:45:02.644745 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10066 14:45:02.647549 [ 0.000000] psci: probing for conduit method from DT.
10067 14:45:02.654387 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10068 14:45:02.657553 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10069 14:45:02.664123 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10070 14:45:02.667539 [ 0.000000] psci: SMC Calling Convention v1.2
10071 14:45:02.674299 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10072 14:45:02.677363 [ 0.000000] Detected VIPT I-cache on CPU0
10073 14:45:02.684345 [ 0.000000] CPU features: detected: GIC system register CPU interface
10074 14:45:02.690627 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10075 14:45:02.697013 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10076 14:45:02.703787 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10077 14:45:02.713481 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10078 14:45:02.720245 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10079 14:45:02.723553 [ 0.000000] alternatives: applying boot alternatives
10080 14:45:02.730127 [ 0.000000] Fallback order for Node 0: 0
10081 14:45:02.736688 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10082 14:45:02.739951 [ 0.000000] Policy zone: Normal
10083 14:45:02.763074 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14166991/extract-nfsrootfs-__ac4z7s,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10084 14:45:02.772841 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10085 14:45:02.782870 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10086 14:45:02.792613 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10087 14:45:02.799314 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10088 14:45:02.802552 <6>[ 0.000000] software IO TLB: area num 8.
10089 14:45:02.857965 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10090 14:45:02.938061 <6>[ 0.000000] Memory: 3831484K/4191232K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 326980K reserved, 32768K cma-reserved)
10091 14:45:02.944956 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10092 14:45:02.951399 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10093 14:45:02.954646 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10094 14:45:02.961470 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10095 14:45:02.967876 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10096 14:45:02.971319 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10097 14:45:02.981205 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10098 14:45:02.987769 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10099 14:45:02.994160 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10100 14:45:03.000819 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10101 14:45:03.004089 <6>[ 0.000000] GICv3: 608 SPIs implemented
10102 14:45:03.007438 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10103 14:45:03.014050 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10104 14:45:03.017359 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10105 14:45:03.024054 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10106 14:45:03.037347 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10107 14:45:03.050406 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10108 14:45:03.056696 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10109 14:45:03.064593 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10110 14:45:03.078200 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10111 14:45:03.084721 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10112 14:45:03.091318 <6>[ 0.009171] Console: colour dummy device 80x25
10113 14:45:03.101137 <6>[ 0.013926] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10114 14:45:03.107935 <6>[ 0.024367] pid_max: default: 32768 minimum: 301
10115 14:45:03.111217 <6>[ 0.029268] LSM: Security Framework initializing
10116 14:45:03.117600 <6>[ 0.034209] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10117 14:45:03.127623 <6>[ 0.041816] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10118 14:45:03.134565 <6>[ 0.051096] cblist_init_generic: Setting adjustable number of callback queues.
10119 14:45:03.141236 <6>[ 0.058584] cblist_init_generic: Setting shift to 3 and lim to 1.
10120 14:45:03.150768 <6>[ 0.064925] cblist_init_generic: Setting adjustable number of callback queues.
10121 14:45:03.157480 <6>[ 0.072397] cblist_init_generic: Setting shift to 3 and lim to 1.
10122 14:45:03.160587 <6>[ 0.078796] rcu: Hierarchical SRCU implementation.
10123 14:45:03.167329 <6>[ 0.083842] rcu: Max phase no-delay instances is 1000.
10124 14:45:03.173748 <6>[ 0.090869] EFI services will not be available.
10125 14:45:03.177074 <6>[ 0.095822] smp: Bringing up secondary CPUs ...
10126 14:45:03.185238 <6>[ 0.100899] Detected VIPT I-cache on CPU1
10127 14:45:03.191800 <6>[ 0.100967] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10128 14:45:03.198385 <6>[ 0.100997] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10129 14:45:03.201877 <6>[ 0.101328] Detected VIPT I-cache on CPU2
10130 14:45:03.208418 <6>[ 0.101377] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10131 14:45:03.215022 <6>[ 0.101393] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10132 14:45:03.221920 <6>[ 0.101647] Detected VIPT I-cache on CPU3
10133 14:45:03.228687 <6>[ 0.101695] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10134 14:45:03.235173 <6>[ 0.101708] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10135 14:45:03.238827 <6>[ 0.102011] CPU features: detected: Spectre-v4
10136 14:45:03.244667 <6>[ 0.102017] CPU features: detected: Spectre-BHB
10137 14:45:03.248207 <6>[ 0.102022] Detected PIPT I-cache on CPU4
10138 14:45:03.255038 <6>[ 0.102080] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10139 14:45:03.261392 <6>[ 0.102096] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10140 14:45:03.268536 <6>[ 0.102384] Detected PIPT I-cache on CPU5
10141 14:45:03.274586 <6>[ 0.102446] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10142 14:45:03.281132 <6>[ 0.102462] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10143 14:45:03.284555 <6>[ 0.102744] Detected PIPT I-cache on CPU6
10144 14:45:03.290948 <6>[ 0.102806] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10145 14:45:03.297786 <6>[ 0.102821] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10146 14:45:03.304207 <6>[ 0.103118] Detected PIPT I-cache on CPU7
10147 14:45:03.310560 <6>[ 0.103181] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10148 14:45:03.317157 <6>[ 0.103197] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10149 14:45:03.320535 <6>[ 0.103243] smp: Brought up 1 node, 8 CPUs
10150 14:45:03.327010 <6>[ 0.244666] SMP: Total of 8 processors activated.
10151 14:45:03.330580 <6>[ 0.249587] CPU features: detected: 32-bit EL0 Support
10152 14:45:03.340547 <6>[ 0.254950] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10153 14:45:03.347074 <6>[ 0.263750] CPU features: detected: Common not Private translations
10154 14:45:03.353652 <6>[ 0.270226] CPU features: detected: CRC32 instructions
10155 14:45:03.360545 <6>[ 0.275578] CPU features: detected: RCpc load-acquire (LDAPR)
10156 14:45:03.363510 <6>[ 0.281538] CPU features: detected: LSE atomic instructions
10157 14:45:03.370156 <6>[ 0.287319] CPU features: detected: Privileged Access Never
10158 14:45:03.376841 <6>[ 0.293135] CPU features: detected: RAS Extension Support
10159 14:45:03.383181 <6>[ 0.298743] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10160 14:45:03.386509 <6>[ 0.305965] CPU: All CPU(s) started at EL2
10161 14:45:03.393200 <6>[ 0.310282] alternatives: applying system-wide alternatives
10162 14:45:03.402192 <6>[ 0.320280] devtmpfs: initialized
10163 14:45:03.416938 <6>[ 0.328469] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10164 14:45:03.424068 <6>[ 0.338427] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10165 14:45:03.430237 <6>[ 0.346455] pinctrl core: initialized pinctrl subsystem
10166 14:45:03.433799 <6>[ 0.353103] DMI not present or invalid.
10167 14:45:03.440399 <6>[ 0.357508] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10168 14:45:03.450235 <6>[ 0.364365] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10169 14:45:03.456968 <6>[ 0.371810] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10170 14:45:03.463578 <6>[ 0.379904] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10171 14:45:03.470087 <6>[ 0.388057] audit: initializing netlink subsys (disabled)
10172 14:45:03.479898 <5>[ 0.393753] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10173 14:45:03.486830 <6>[ 0.394446] thermal_sys: Registered thermal governor 'step_wise'
10174 14:45:03.493102 <6>[ 0.401717] thermal_sys: Registered thermal governor 'power_allocator'
10175 14:45:03.496611 <6>[ 0.407970] cpuidle: using governor menu
10176 14:45:03.499651 <6>[ 0.418928] NET: Registered PF_QIPCRTR protocol family
10177 14:45:03.509880 <6>[ 0.424420] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10178 14:45:03.513192 <6>[ 0.431522] ASID allocator initialised with 32768 entries
10179 14:45:03.520268 <6>[ 0.438069] Serial: AMBA PL011 UART driver
10180 14:45:03.528803 <4>[ 0.446790] Trying to register duplicate clock ID: 134
10181 14:45:03.586857 <6>[ 0.508134] KASLR enabled
10182 14:45:03.601550 <6>[ 0.515940] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10183 14:45:03.607792 <6>[ 0.522953] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10184 14:45:03.614507 <6>[ 0.529443] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10185 14:45:03.620866 <6>[ 0.536446] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10186 14:45:03.627481 <6>[ 0.542930] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10187 14:45:03.634037 <6>[ 0.549934] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10188 14:45:03.640642 <6>[ 0.556422] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10189 14:45:03.647364 <6>[ 0.563429] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10190 14:45:03.650399 <6>[ 0.570884] ACPI: Interpreter disabled.
10191 14:45:03.659379 <6>[ 0.577269] iommu: Default domain type: Translated
10192 14:45:03.665981 <6>[ 0.582417] iommu: DMA domain TLB invalidation policy: strict mode
10193 14:45:03.669214 <5>[ 0.589071] SCSI subsystem initialized
10194 14:45:03.676070 <6>[ 0.593320] usbcore: registered new interface driver usbfs
10195 14:45:03.682851 <6>[ 0.599052] usbcore: registered new interface driver hub
10196 14:45:03.685894 <6>[ 0.604603] usbcore: registered new device driver usb
10197 14:45:03.692693 <6>[ 0.610714] pps_core: LinuxPPS API ver. 1 registered
10198 14:45:03.702564 <6>[ 0.615905] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10199 14:45:03.705813 <6>[ 0.625247] PTP clock support registered
10200 14:45:03.709061 <6>[ 0.629487] EDAC MC: Ver: 3.0.0
10201 14:45:03.716812 <6>[ 0.634656] FPGA manager framework
10202 14:45:03.723211 <6>[ 0.638334] Advanced Linux Sound Architecture Driver Initialized.
10203 14:45:03.726444 <6>[ 0.645109] vgaarb: loaded
10204 14:45:03.733319 <6>[ 0.648270] clocksource: Switched to clocksource arch_sys_counter
10205 14:45:03.736743 <5>[ 0.654712] VFS: Disk quotas dquot_6.6.0
10206 14:45:03.743093 <6>[ 0.658898] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10207 14:45:03.746776 <6>[ 0.666091] pnp: PnP ACPI: disabled
10208 14:45:03.754641 <6>[ 0.672719] NET: Registered PF_INET protocol family
10209 14:45:03.761278 <6>[ 0.678109] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10210 14:45:03.773828 <6>[ 0.688107] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10211 14:45:03.783407 <6>[ 0.696892] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10212 14:45:03.790053 <6>[ 0.704858] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10213 14:45:03.796271 <6>[ 0.713260] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10214 14:45:03.807383 <6>[ 0.721916] TCP: Hash tables configured (established 32768 bind 32768)
10215 14:45:03.813840 <6>[ 0.728772] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10216 14:45:03.820432 <6>[ 0.735789] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10217 14:45:03.827017 <6>[ 0.743288] NET: Registered PF_UNIX/PF_LOCAL protocol family
10218 14:45:03.833824 <6>[ 0.749427] RPC: Registered named UNIX socket transport module.
10219 14:45:03.837154 <6>[ 0.755577] RPC: Registered udp transport module.
10220 14:45:03.843541 <6>[ 0.760508] RPC: Registered tcp transport module.
10221 14:45:03.850223 <6>[ 0.765439] RPC: Registered tcp NFSv4.1 backchannel transport module.
10222 14:45:03.853525 <6>[ 0.772106] PCI: CLS 0 bytes, default 64
10223 14:45:03.856735 <6>[ 0.776432] Unpacking initramfs...
10224 14:45:03.873986 <6>[ 0.788772] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10225 14:45:03.883943 <6>[ 0.797400] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10226 14:45:03.887153 <6>[ 0.806219] kvm [1]: IPA Size Limit: 40 bits
10227 14:45:03.894036 <6>[ 0.810743] kvm [1]: GICv3: no GICV resource entry
10228 14:45:03.897275 <6>[ 0.815763] kvm [1]: disabling GICv2 emulation
10229 14:45:03.903669 <6>[ 0.820446] kvm [1]: GIC system register CPU interface enabled
10230 14:45:03.906950 <6>[ 0.826617] kvm [1]: vgic interrupt IRQ18
10231 14:45:03.913622 <6>[ 0.830973] kvm [1]: VHE mode initialized successfully
10232 14:45:03.920406 <5>[ 0.837471] Initialise system trusted keyrings
10233 14:45:03.926871 <6>[ 0.842278] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10234 14:45:03.934386 <6>[ 0.852231] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10235 14:45:03.940946 <5>[ 0.858636] NFS: Registering the id_resolver key type
10236 14:45:03.944225 <5>[ 0.863935] Key type id_resolver registered
10237 14:45:03.950950 <5>[ 0.868349] Key type id_legacy registered
10238 14:45:03.957384 <6>[ 0.872627] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10239 14:45:03.964332 <6>[ 0.879549] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10240 14:45:03.970429 <6>[ 0.887280] 9p: Installing v9fs 9p2000 file system support
10241 14:45:04.006859 <5>[ 0.924963] Key type asymmetric registered
10242 14:45:04.010448 <5>[ 0.929294] Asymmetric key parser 'x509' registered
10243 14:45:04.020330 <6>[ 0.934437] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10244 14:45:04.023952 <6>[ 0.942047] io scheduler mq-deadline registered
10245 14:45:04.026974 <6>[ 0.946825] io scheduler kyber registered
10246 14:45:04.045668 <6>[ 0.963847] EINJ: ACPI disabled.
10247 14:45:04.078601 <4>[ 0.990043] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10248 14:45:04.088240 <4>[ 1.000662] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10249 14:45:04.103508 <6>[ 1.021601] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10250 14:45:04.111538 <6>[ 1.029450] printk: console [ttyS0] disabled
10251 14:45:04.139661 <6>[ 1.054087] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10252 14:45:04.145949 <6>[ 1.063559] printk: console [ttyS0] enabled
10253 14:45:04.149439 <6>[ 1.063559] printk: console [ttyS0] enabled
10254 14:45:04.155879 <6>[ 1.072457] printk: bootconsole [mtk8250] disabled
10255 14:45:04.159294 <6>[ 1.072457] printk: bootconsole [mtk8250] disabled
10256 14:45:04.165707 <6>[ 1.083486] SuperH (H)SCI(F) driver initialized
10257 14:45:04.169108 <6>[ 1.088760] msm_serial: driver initialized
10258 14:45:04.182941 <6>[ 1.097656] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10259 14:45:04.193025 <6>[ 1.106206] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10260 14:45:04.199506 <6>[ 1.114749] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10261 14:45:04.209636 <6>[ 1.123375] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10262 14:45:04.219487 <6>[ 1.132081] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10263 14:45:04.226113 <6>[ 1.140796] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10264 14:45:04.235957 <6>[ 1.149335] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10265 14:45:04.242730 <6>[ 1.158139] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10266 14:45:04.252333 <6>[ 1.166683] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10267 14:45:04.263658 <6>[ 1.181878] loop: module loaded
10268 14:45:04.270360 <6>[ 1.187790] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10269 14:45:04.293135 <4>[ 1.211080] mtk-pmic-keys: Failed to locate of_node [id: -1]
10270 14:45:04.300248 <6>[ 1.217866] megasas: 07.719.03.00-rc1
10271 14:45:04.309884 <6>[ 1.227701] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10272 14:45:04.321599 <6>[ 1.239658] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10273 14:45:04.338579 <6>[ 1.256313] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10274 14:45:04.394874 <6>[ 1.306178] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10275 14:45:04.646989 <6>[ 1.565189] Freeing initrd memory: 18288K
10276 14:45:04.658693 <6>[ 1.576922] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10277 14:45:04.669683 <6>[ 1.587765] tun: Universal TUN/TAP device driver, 1.6
10278 14:45:04.673262 <6>[ 1.593820] thunder_xcv, ver 1.0
10279 14:45:04.676456 <6>[ 1.597323] thunder_bgx, ver 1.0
10280 14:45:04.679803 <6>[ 1.600820] nicpf, ver 1.0
10281 14:45:04.690156 <6>[ 1.604832] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10282 14:45:04.693309 <6>[ 1.612307] hns3: Copyright (c) 2017 Huawei Corporation.
10283 14:45:04.700301 <6>[ 1.617898] hclge is initializing
10284 14:45:04.703104 <6>[ 1.621484] e1000: Intel(R) PRO/1000 Network Driver
10285 14:45:04.710237 <6>[ 1.626613] e1000: Copyright (c) 1999-2006 Intel Corporation.
10286 14:45:04.713197 <6>[ 1.632625] e1000e: Intel(R) PRO/1000 Network Driver
10287 14:45:04.719835 <6>[ 1.637840] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10288 14:45:04.726654 <6>[ 1.644024] igb: Intel(R) Gigabit Ethernet Network Driver
10289 14:45:04.733068 <6>[ 1.649673] igb: Copyright (c) 2007-2014 Intel Corporation.
10290 14:45:04.740080 <6>[ 1.655510] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10291 14:45:04.746378 <6>[ 1.662029] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10292 14:45:04.749469 <6>[ 1.668495] sky2: driver version 1.30
10293 14:45:04.756713 <6>[ 1.673416] usbcore: registered new device driver r8152-cfgselector
10294 14:45:04.763190 <6>[ 1.679953] usbcore: registered new interface driver r8152
10295 14:45:04.769553 <6>[ 1.685765] VFIO - User Level meta-driver version: 0.3
10296 14:45:04.776284 <6>[ 1.694001] usbcore: registered new interface driver usb-storage
10297 14:45:04.782831 <6>[ 1.700442] usbcore: registered new device driver onboard-usb-hub
10298 14:45:04.791361 <6>[ 1.709563] mt6397-rtc mt6359-rtc: registered as rtc0
10299 14:45:04.801350 <6>[ 1.715022] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T14:45:04 UTC (1717512304)
10300 14:45:04.804740 <6>[ 1.724589] i2c_dev: i2c /dev entries driver
10301 14:45:04.821919 <6>[ 1.736353] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10302 14:45:04.828239 <4>[ 1.745078] cpu cpu0: supply cpu not found, using dummy regulator
10303 14:45:04.834679 <4>[ 1.751501] cpu cpu1: supply cpu not found, using dummy regulator
10304 14:45:04.841568 <4>[ 1.757907] cpu cpu2: supply cpu not found, using dummy regulator
10305 14:45:04.847997 <4>[ 1.764330] cpu cpu3: supply cpu not found, using dummy regulator
10306 14:45:04.854784 <4>[ 1.770734] cpu cpu4: supply cpu not found, using dummy regulator
10307 14:45:04.861732 <4>[ 1.777129] cpu cpu5: supply cpu not found, using dummy regulator
10308 14:45:04.868241 <4>[ 1.783524] cpu cpu6: supply cpu not found, using dummy regulator
10309 14:45:04.874597 <4>[ 1.789920] cpu cpu7: supply cpu not found, using dummy regulator
10310 14:45:04.892376 <6>[ 1.810555] cpu cpu0: EM: created perf domain
10311 14:45:04.895588 <6>[ 1.815471] cpu cpu4: EM: created perf domain
10312 14:45:04.902906 <6>[ 1.820998] sdhci: Secure Digital Host Controller Interface driver
10313 14:45:04.909326 <6>[ 1.827430] sdhci: Copyright(c) Pierre Ossman
10314 14:45:04.916154 <6>[ 1.832342] Synopsys Designware Multimedia Card Interface Driver
10315 14:45:04.922531 <6>[ 1.838934] sdhci-pltfm: SDHCI platform and OF driver helper
10316 14:45:04.926168 <6>[ 1.839098] mmc0: CQHCI version 5.10
10317 14:45:04.932699 <6>[ 1.849248] ledtrig-cpu: registered to indicate activity on CPUs
10318 14:45:04.939221 <6>[ 1.856300] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10319 14:45:04.945979 <6>[ 1.863328] usbcore: registered new interface driver usbhid
10320 14:45:04.949226 <6>[ 1.869158] usbhid: USB HID core driver
10321 14:45:04.955727 <6>[ 1.873342] spi_master spi0: will run message pump with realtime priority
10322 14:45:04.999297 <6>[ 1.911082] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10323 14:45:05.018158 <6>[ 1.926405] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10324 14:45:05.021963 <6>[ 1.939973] mmc0: Command Queue Engine enabled
10325 14:45:05.028876 <6>[ 1.944720] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10326 14:45:05.035247 <6>[ 1.951650] cros-ec-spi spi0.0: Chrome EC device registered
10327 14:45:05.038669 <6>[ 1.951960] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10328 14:45:05.048517 <6>[ 1.966602] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10329 14:45:05.055954 <6>[ 1.974017] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10330 14:45:05.062580 <6>[ 1.979866] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10331 14:45:05.069103 <6>[ 1.985765] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10332 14:45:05.082940 <6>[ 1.997527] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10333 14:45:05.089642 <6>[ 2.007763] NET: Registered PF_PACKET protocol family
10334 14:45:05.092942 <6>[ 2.013168] 9pnet: Installing 9P2000 support
10335 14:45:05.099767 <5>[ 2.017722] Key type dns_resolver registered
10336 14:45:05.102898 <6>[ 2.022710] registered taskstats version 1
10337 14:45:05.109563 <5>[ 2.027094] Loading compiled-in X.509 certificates
10338 14:45:05.138027 <4>[ 2.049277] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10339 14:45:05.147771 <4>[ 2.060084] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10340 14:45:05.162187 <6>[ 2.080390] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10341 14:45:05.169499 <6>[ 2.087367] xhci-mtk 11200000.usb: xHCI Host Controller
10342 14:45:05.176054 <6>[ 2.092875] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10343 14:45:05.185800 <6>[ 2.100699] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10344 14:45:05.192396 <6>[ 2.110121] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10345 14:45:05.198990 <6>[ 2.116200] xhci-mtk 11200000.usb: xHCI Host Controller
10346 14:45:05.205694 <6>[ 2.121683] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10347 14:45:05.212196 <6>[ 2.129331] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10348 14:45:05.219099 <6>[ 2.136995] hub 1-0:1.0: USB hub found
10349 14:45:05.222175 <6>[ 2.141012] hub 1-0:1.0: 1 port detected
10350 14:45:05.228853 <6>[ 2.145283] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10351 14:45:05.235856 <6>[ 2.153810] hub 2-0:1.0: USB hub found
10352 14:45:05.238986 <6>[ 2.157818] hub 2-0:1.0: 1 port detected
10353 14:45:05.246680 <6>[ 2.164836] mtk-msdc 11f70000.mmc: Got CD GPIO
10354 14:45:05.259777 <6>[ 2.174312] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10355 14:45:05.266485 <6>[ 2.182348] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10356 14:45:05.276419 <4>[ 2.190268] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10357 14:45:05.286281 <6>[ 2.199804] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10358 14:45:05.293165 <6>[ 2.207880] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10359 14:45:05.299423 <6>[ 2.215892] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10360 14:45:05.309498 <6>[ 2.223812] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10361 14:45:05.316124 <6>[ 2.231628] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10362 14:45:05.325964 <6>[ 2.239447] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10363 14:45:05.335960 <6>[ 2.249811] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10364 14:45:05.342626 <6>[ 2.258168] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10365 14:45:05.352430 <6>[ 2.266514] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10366 14:45:05.359129 <6>[ 2.274854] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10367 14:45:05.368807 <6>[ 2.283191] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10368 14:45:05.375613 <6>[ 2.291528] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10369 14:45:05.385498 <6>[ 2.299866] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10370 14:45:05.391933 <6>[ 2.308202] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10371 14:45:05.402247 <6>[ 2.316540] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10372 14:45:05.408698 <6>[ 2.324877] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10373 14:45:05.418574 <6>[ 2.333214] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10374 14:45:05.425230 <6>[ 2.341552] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10375 14:45:05.435184 <6>[ 2.349889] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10376 14:45:05.445109 <6>[ 2.358230] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10377 14:45:05.451697 <6>[ 2.366567] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10378 14:45:05.458596 <6>[ 2.375296] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10379 14:45:05.464697 <6>[ 2.382434] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10380 14:45:05.471627 <6>[ 2.389193] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10381 14:45:05.478105 <6>[ 2.395932] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10382 14:45:05.488056 <6>[ 2.402826] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10383 14:45:05.494625 <6>[ 2.409667] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10384 14:45:05.504855 <6>[ 2.418796] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10385 14:45:05.514762 <6>[ 2.427917] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10386 14:45:05.524294 <6>[ 2.437210] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10387 14:45:05.534276 <6>[ 2.446677] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10388 14:45:05.540921 <6>[ 2.456159] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10389 14:45:05.550611 <6>[ 2.465282] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10390 14:45:05.560521 <6>[ 2.474748] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10391 14:45:05.570817 <6>[ 2.483868] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10392 14:45:05.580359 <6>[ 2.493161] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10393 14:45:05.590244 <6>[ 2.503321] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10394 14:45:05.600012 <6>[ 2.514787] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10395 14:45:05.606805 <6>[ 2.524353] Trying to probe devices needed for running init ...
10396 14:45:05.649719 <6>[ 2.564535] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10397 14:45:05.804604 <6>[ 2.722437] hub 1-1:1.0: USB hub found
10398 14:45:05.807478 <6>[ 2.726972] hub 1-1:1.0: 4 ports detected
10399 14:45:05.817927 <6>[ 2.735811] hub 1-1:1.0: USB hub found
10400 14:45:05.821041 <6>[ 2.740198] hub 1-1:1.0: 4 ports detected
10401 14:45:05.929916 <6>[ 2.844915] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10402 14:45:05.956257 <6>[ 2.874586] hub 2-1:1.0: USB hub found
10403 14:45:05.959531 <6>[ 2.879100] hub 2-1:1.0: 3 ports detected
10404 14:45:05.969262 <6>[ 2.887379] hub 2-1:1.0: USB hub found
10405 14:45:05.972489 <6>[ 2.891840] hub 2-1:1.0: 3 ports detected
10406 14:45:06.145634 <6>[ 3.060596] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10407 14:45:06.278354 <6>[ 3.196483] hub 1-1.4:1.0: USB hub found
10408 14:45:06.281527 <6>[ 3.201185] hub 1-1.4:1.0: 2 ports detected
10409 14:45:06.291318 <6>[ 3.209501] hub 1-1.4:1.0: USB hub found
10410 14:45:06.294491 <6>[ 3.214151] hub 1-1.4:1.0: 2 ports detected
10411 14:45:06.361613 <6>[ 3.276696] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10412 14:45:06.470344 <6>[ 3.385262] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10413 14:45:06.506333 <4>[ 3.421294] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10414 14:45:06.515953 <4>[ 3.430486] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10415 14:45:06.559597 <6>[ 3.478114] r8152 2-1.3:1.0 eth0: v1.12.13
10416 14:45:06.601598 <6>[ 3.516594] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10417 14:45:06.793613 <6>[ 3.708403] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10418 14:45:08.214494 <6>[ 5.133165] r8152 2-1.3:1.0 eth0: carrier on
10419 14:45:11.210091 <5>[ 5.160395] Sending DHCP requests .., OK
10420 14:45:11.216752 <6>[ 8.132737] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10421 14:45:11.220164 <6>[ 8.141033] IP-Config: Complete:
10422 14:45:11.233225 <6>[ 8.144528] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10423 14:45:11.240070 <6>[ 8.155241] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10424 14:45:11.246548 <6>[ 8.163861] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10425 14:45:11.253092 <6>[ 8.163872] nameserver0=192.168.201.1
10426 14:45:11.256537 <6>[ 8.176060] clk: Disabling unused clocks
10427 14:45:11.259892 <6>[ 8.181616] ALSA device list:
10428 14:45:11.266607 <6>[ 8.184875] No soundcards found.
10429 14:45:11.274543 <6>[ 8.192510] Freeing unused kernel memory: 8512K
10430 14:45:11.277648 <6>[ 8.197540] Run /init as init process
10431 14:45:11.287762 Loading, please wait...
10432 14:45:11.320840 Starting systemd-udevd version 252.22-1~deb12u1
10433 14:45:11.543522 <6>[ 8.458447] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10434 14:45:11.560333 <6>[ 8.478603] remoteproc remoteproc0: scp is available
10435 14:45:11.566913 <6>[ 8.478986] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10436 14:45:11.573781 <6>[ 8.486687] remoteproc remoteproc0: powering up scp
10437 14:45:11.583179 <6>[ 8.491557] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10438 14:45:11.590236 <6>[ 8.496685] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10439 14:45:11.600140 <6>[ 8.505843] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10440 14:45:11.603670 <6>[ 8.507261] mc: Linux media interface: v0.10
10441 14:45:11.609945 <6>[ 8.514108] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10442 14:45:11.623488 <4>[ 8.538444] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10443 14:45:11.630645 <6>[ 8.548936] videodev: Linux video capture interface: v2.00
10444 14:45:11.640324 <4>[ 8.555114] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10445 14:45:11.650324 <6>[ 8.565674] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10446 14:45:11.670617 <3>[ 8.585660] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10447 14:45:11.680783 <4>[ 8.591766] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10448 14:45:11.683713 <4>[ 8.591766] Fallback method does not support PEC.
10449 14:45:11.694036 <3>[ 8.593988] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10450 14:45:11.701226 <3>[ 8.615754] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10451 14:45:11.711091 <3>[ 8.624197] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10452 14:45:11.718025 <3>[ 8.624221] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10453 14:45:11.724514 <3>[ 8.641123] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10454 14:45:11.731824 <6>[ 8.645576] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10455 14:45:11.741957 <3>[ 8.649327] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10456 14:45:11.751628 <6>[ 8.653342] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10457 14:45:11.758134 <6>[ 8.653698] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10458 14:45:11.768177 <3>[ 8.654671] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10459 14:45:11.774925 <6>[ 8.656400] pci_bus 0000:00: root bus resource [bus 00-ff]
10460 14:45:11.781396 <6>[ 8.658501] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10461 14:45:11.791730 <6>[ 8.658506] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10462 14:45:11.797858 <6>[ 8.658510] remoteproc remoteproc0: remote processor scp is now up
10463 14:45:11.804603 <3>[ 8.664607] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10464 14:45:11.811088 <6>[ 8.674340] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10465 14:45:11.820788 <6>[ 8.675624] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10466 14:45:11.827633 <6>[ 8.677999] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10467 14:45:11.837330 <6>[ 8.678799] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10468 14:45:11.844726 <3>[ 8.683327] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10469 14:45:11.853864 <6>[ 8.692431] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10470 14:45:11.863974 <3>[ 8.698031] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10471 14:45:11.870607 <6>[ 8.706415] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10472 14:45:11.876922 <3>[ 8.713452] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10473 14:45:11.880615 <6>[ 8.714619] Bluetooth: Core ver 2.22
10474 14:45:11.887099 <6>[ 8.714758] NET: Registered PF_BLUETOOTH protocol family
10475 14:45:11.893563 <6>[ 8.714761] Bluetooth: HCI device and connection manager initialized
10476 14:45:11.900317 <6>[ 8.714785] Bluetooth: HCI socket layer initialized
10477 14:45:11.903850 <6>[ 8.714796] Bluetooth: L2CAP socket layer initialized
10478 14:45:11.910012 <6>[ 8.714810] Bluetooth: SCO socket layer initialized
10479 14:45:11.917197 <6>[ 8.719849] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10480 14:45:11.923683 <3>[ 8.727916] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10481 14:45:11.933470 <6>[ 8.729695] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10482 14:45:11.943371 <6>[ 8.731147] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10483 14:45:11.949951 <6>[ 8.731237] usbcore: registered new interface driver uvcvideo
10484 14:45:11.956296 <6>[ 8.735102] pci 0000:00:00.0: supports D1 D2
10485 14:45:11.962880 <3>[ 8.743286] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10486 14:45:11.969363 <6>[ 8.751535] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10487 14:45:11.979730 <3>[ 8.760872] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10488 14:45:11.985981 <6>[ 8.769765] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10489 14:45:11.992585 <3>[ 8.778804] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10490 14:45:12.002653 <3>[ 8.778807] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10491 14:45:12.009343 <6>[ 8.779607] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10492 14:45:12.015503 <6>[ 8.787008] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10493 14:45:12.022275 <3>[ 8.793140] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10494 14:45:12.029100 <6>[ 8.793572] usbcore: registered new interface driver btusb
10495 14:45:12.038905 <4>[ 8.794731] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10496 14:45:12.045230 <3>[ 8.794737] Bluetooth: hci0: Failed to load firmware file (-2)
10497 14:45:12.051919 <3>[ 8.794739] Bluetooth: hci0: Failed to set up firmware (-2)
10498 14:45:12.062120 <4>[ 8.794740] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10499 14:45:12.068351 <6>[ 8.801243] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10500 14:45:12.078619 <3>[ 8.805040] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10501 14:45:12.084760 <3>[ 8.805060] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10502 14:45:12.091587 <6>[ 8.810615] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10503 14:45:12.101329 <6>[ 9.016141] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10504 14:45:12.104502 <6>[ 9.023727] pci 0000:01:00.0: supports D1 D2
10505 14:45:12.111127 <6>[ 9.028246] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10506 14:45:12.133092 <6>[ 9.048416] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10507 14:45:12.139659 <6>[ 9.055330] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10508 14:45:12.146422 <6>[ 9.063408] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10509 14:45:12.156376 <6>[ 9.071404] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10510 14:45:12.163067 <6>[ 9.079405] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10511 14:45:12.172888 <6>[ 9.087404] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10512 14:45:12.176611 <6>[ 9.095403] pci 0000:00:00.0: PCI bridge to [bus 01]
10513 14:45:12.186147 <6>[ 9.100619] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10514 14:45:12.192617 <6>[ 9.108740] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10515 14:45:12.199356 <6>[ 9.115537] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10516 14:45:12.205943 <6>[ 9.122367] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10517 14:45:12.220547 <5>[ 9.136020] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10518 14:45:12.247099 <5>[ 9.161849] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10519 14:45:12.253432 <5>[ 9.168865] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10520 14:45:12.263057 <4>[ 9.177270] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10521 14:45:12.266436 <6>[ 9.186139] cfg80211: failed to load regulatory.db
10522 14:45:12.306999 <6>[ 9.222322] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10523 14:45:12.313679 <6>[ 9.229861] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10524 14:45:12.338416 <6>[ 9.256563] mt7921e 0000:01:00.0: ASIC revision: 79610010
10525 14:45:12.440561 <6>[ 9.355586] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10526 14:45:12.443947 <6>[ 9.355586]
10527 14:45:12.447491 Begin: Loading essential drivers ... done.
10528 14:45:12.450316 Begin: Running /scripts/init-premount ... done.
10529 14:45:12.457353 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10530 14:45:12.466549 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10531 14:45:12.470568 Device /sys/class/net/eth0 found
10532 14:45:12.471136 done.
10533 14:45:12.477136 Begin: Waiting up to 180 secs for any network device to become available ... done.
10534 14:45:12.526162 IP-Config: eth0 hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10535 14:45:12.532601 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10536 14:45:12.539259 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10537 14:45:12.546280 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10538 14:45:12.552200 host : mt8192-asurada-spherion-r0-cbg-4
10539 14:45:12.558939 domain : lava-rack
10540 14:45:12.562385 rootserver: 192.168.201.1 rootpath:
10541 14:45:12.562797 filename :
10542 14:45:12.654918 done.
10543 14:45:12.661608 Begin: Running /scripts/nfs-bottom ... done.
10544 14:45:12.671605 Begin: Running /scripts/init-bottom ... done.
10545 14:45:12.710355 <6>[ 9.625995] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10546 14:45:14.023455 <6>[ 10.942316] NET: Registered PF_INET6 protocol family
10547 14:45:14.031277 <6>[ 10.949718] Segment Routing with IPv6
10548 14:45:14.034224 <6>[ 10.953727] In-situ OAM (IOAM) with IPv6
10549 14:45:14.209363 <30>[ 11.101313] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10550 14:45:14.215575 <30>[ 11.134454] systemd[1]: Detected architecture arm64.
10551 14:45:14.224976
10552 14:45:14.228161 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10553 14:45:14.228589
10554 14:45:14.252336 <30>[ 11.170476] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10555 14:45:15.394589 <30>[ 12.309903] systemd[1]: Queued start job for default target graphical.target.
10556 14:45:15.430752 <30>[ 12.346444] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10557 14:45:15.437426 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10558 14:45:15.458021 <30>[ 12.373175] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10559 14:45:15.467515 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10560 14:45:15.485922 <30>[ 12.401090] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10561 14:45:15.495398 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10562 14:45:15.514029 <30>[ 12.429150] systemd[1]: Created slice user.slice - User and Session Slice.
10563 14:45:15.519904 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10564 14:45:15.540564 <30>[ 12.452789] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10565 14:45:15.547258 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10566 14:45:15.568432 <30>[ 12.480864] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10567 14:45:15.575355 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10568 14:45:15.603054 <30>[ 12.508772] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10569 14:45:15.613130 <30>[ 12.528607] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10570 14:45:15.619730 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10571 14:45:15.637506 <30>[ 12.553031] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10572 14:45:15.647375 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10573 14:45:15.665193 <30>[ 12.580698] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10574 14:45:15.675274 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10575 14:45:15.690067 <30>[ 12.609160] systemd[1]: Reached target paths.target - Path Units.
10576 14:45:15.700604 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10577 14:45:15.718005 <30>[ 12.633047] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10578 14:45:15.724683 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10579 14:45:15.737991 <30>[ 12.656583] systemd[1]: Reached target slices.target - Slice Units.
10580 14:45:15.747974 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10581 14:45:15.762248 <30>[ 12.681094] systemd[1]: Reached target swap.target - Swaps.
10582 14:45:15.768789 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10583 14:45:15.789818 <30>[ 12.705124] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10584 14:45:15.799274 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10585 14:45:15.818351 <30>[ 12.733604] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10586 14:45:15.828750 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10587 14:45:15.848477 <30>[ 12.763945] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10588 14:45:15.858146 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10589 14:45:15.874545 <30>[ 12.790309] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10590 14:45:15.884878 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10591 14:45:15.901754 <30>[ 12.817317] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10592 14:45:15.908379 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10593 14:45:15.926895 <30>[ 12.842390] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10594 14:45:15.936678 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10595 14:45:15.957234 <30>[ 12.873071] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10596 14:45:15.967285 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10597 14:45:15.985870 <30>[ 12.901159] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10598 14:45:15.995556 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10599 14:45:16.049005 <30>[ 12.964800] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10600 14:45:16.055797 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10601 14:45:16.078200 <30>[ 12.993795] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10602 14:45:16.084509 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10603 14:45:16.110420 <30>[ 13.025965] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10604 14:45:16.116460 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10605 14:45:16.144378 <30>[ 13.053280] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10606 14:45:16.173861 <30>[ 13.089330] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10607 14:45:16.183778 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10608 14:45:16.207083 <30>[ 13.122965] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10609 14:45:16.214146 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10610 14:45:16.239141 <30>[ 13.154955] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10611 14:45:16.246214 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10612 14:45:16.271028 <30>[ 13.186748] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10613 14:45:16.284399 Starting [0;1;39mmodprobe@drm.service<6>[ 13.198072] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10614 14:45:16.287704 [0m - Load Kernel Module drm...
10615 14:45:16.311099 <30>[ 13.226892] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10616 14:45:16.321111 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10617 14:45:16.343285 <30>[ 13.259106] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10618 14:45:16.349863 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10619 14:45:16.375359 <30>[ 13.290953] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10620 14:45:16.381644 Startin<6>[ 13.299649] fuse: init (API version 7.37)
10621 14:45:16.388654 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10622 14:45:16.445941 <30>[ 13.361421] systemd[1]: Starting systemd-journald.service - Journal Service...
10623 14:45:16.452492 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10624 14:45:16.486355 <30>[ 13.402160] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10625 14:45:16.492926 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10626 14:45:16.519872 <30>[ 13.432240] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10627 14:45:16.526357 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10628 14:45:16.549098 <30>[ 13.464716] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10629 14:45:16.558901 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10630 14:45:16.581395 <30>[ 13.496976] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10631 14:45:16.587637 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10632 14:45:16.610326 <3>[ 13.525796] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10633 14:45:16.616992 <30>[ 13.531466] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10634 14:45:16.626887 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10635 14:45:16.645098 <30>[ 13.560951] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10636 14:45:16.655282 <3>[ 13.561042] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10637 14:45:16.661924 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10638 14:45:16.681850 <30>[ 13.597319] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10639 14:45:16.698220 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug <3>[ 13.610981] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10640 14:45:16.698659 File System.
10641 14:45:16.719145 <30>[ 13.634336] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10642 14:45:16.728920 <3>[ 13.640837] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10643 14:45:16.735520 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10644 14:45:16.754533 <30>[ 13.669531] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10645 14:45:16.760738 <3>[ 13.673760] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10646 14:45:16.770732 <30>[ 13.677715] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10647 14:45:16.777518 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10648 14:45:16.790558 <3>[ 13.705967] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10649 14:45:16.800837 <30>[ 13.716250] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10650 14:45:16.807422 <30>[ 13.724137] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10651 14:45:16.824061 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m <3>[ 13.737000] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10652 14:45:16.824618 - Load Kernel Module dm_mod.
10653 14:45:16.847363 <30>[ 13.765729] systemd[1]: modprobe@drm.service: Deactivated successfully.
10654 14:45:16.857790 <30>[ 13.773529] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10655 14:45:16.868112 <3>[ 13.781403] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10656 14:45:16.874434 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10657 14:45:16.894575 <3>[ 13.810406] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10658 14:45:16.905516 <30>[ 13.821296] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10659 14:45:16.915555 <30>[ 13.829614] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10660 14:45:16.922170 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10661 14:45:16.940996 <3>[ 13.856731] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10662 14:45:16.952251 <30>[ 13.867724] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10663 14:45:16.958493 <30>[ 13.875670] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10664 14:45:16.968397 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10665 14:45:16.990480 <30>[ 13.905396] systemd[1]: modprobe@loop.service: Deactivated successfully.
10666 14:45:16.997082 <30>[ 13.913153] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10667 14:45:17.003731 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10668 14:45:17.013917 <3>[ 13.928257] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10669 14:45:17.023489 <3>[ 13.929074] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
10670 14:45:17.037638 <4>[ 13.946106] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10671 14:45:17.044480 <30>[ 13.946968] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10672 14:45:17.055267 <3>[ 13.958249] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10673 14:45:17.062000 <3>[ 13.961743] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10674 14:45:17.072116 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10675 14:45:17.093776 <30>[ 14.005718] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10676 14:45:17.100262 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10677 14:45:17.117878 <30>[ 14.033368] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10678 14:45:17.128368 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10679 14:45:17.145207 <30>[ 14.060906] systemd[1]: Started systemd-journald.service - Journal Service.
10680 14:45:17.152093 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10681 14:45:17.173509 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10682 14:45:17.195215 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10683 14:45:17.265764 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10684 14:45:17.292496 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10685 14:45:17.319892 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10686 14:45:17.346969 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10687 14:45:17.378141 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10688 14:45:17.384907 <46>[ 14.301770] systemd-journald[304]: Received client request to flush runtime journal.
10689 14:45:17.413513 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10690 14:45:17.445634 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10691 14:45:17.461560 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10692 14:45:17.482572 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10693 14:45:17.502840 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10694 14:45:18.514666 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10695 14:45:18.585832 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10696 14:45:18.839309 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10697 14:45:18.949652 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10698 14:45:18.965427 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10699 14:45:18.985196 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10700 14:45:19.040778 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10701 14:45:19.062124 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10702 14:45:19.295405 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10703 14:45:19.337786 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10704 14:45:19.420992 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10705 14:45:19.733970 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10706 14:45:19.762171 <6>[ 16.681218] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10707 14:45:19.771434 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10708 14:45:19.792853 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10709 14:45:19.831695 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10710 14:45:19.885622 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10711 14:45:19.915865 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10712 14:45:19.934378 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10713 14:45:19.953836 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10714 14:45:20.001194 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10715 14:45:20.022744 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10716 14:45:20.077838 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10717 14:45:20.100430 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10718 14:45:20.116948 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10719 14:45:20.136608 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10720 14:45:20.157152 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10721 14:45:20.176565 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10722 14:45:20.192525 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10723 14:45:20.221072 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10724 14:45:20.240048 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10725 14:45:20.257220 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10726 14:45:20.276676 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10727 14:45:20.297278 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10728 14:45:20.312324 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10729 14:45:20.342927 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10730 14:45:20.360304 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10731 14:45:20.376795 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10732 14:45:20.414751 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10733 14:45:20.455715 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10734 14:45:20.537651 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10735 14:45:20.564705 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10736 14:45:20.610504 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10737 14:45:20.657838 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10738 14:45:20.718967 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10739 14:45:20.737142 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10740 14:45:20.754977 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10741 14:45:20.793670 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10742 14:45:20.873930 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10743 14:45:20.900043 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10744 14:45:20.917266 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10745 14:45:20.963810 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10746 14:45:21.011742 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10747 14:45:21.118412
10748 14:45:21.121366 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10749 14:45:21.121797
10750 14:45:21.124936 debian-bookworm-arm64 login: root (automatic login)
10751 14:45:21.125391
10752 14:45:21.424072 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024 aarch64
10753 14:45:21.424219
10754 14:45:21.430550 The programs included with the Debian GNU/Linux system are free software;
10755 14:45:21.437180 the exact distribution terms for each program are described in the
10756 14:45:21.440647 individual files in /usr/share/doc/*/copyright.
10757 14:45:21.440734
10758 14:45:21.447664 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10759 14:45:21.450618 permitted by applicable law.
10760 14:45:22.417051 Matched prompt #10: / #
10762 14:45:22.418255 Setting prompt string to ['/ #']
10763 14:45:22.418724 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10765 14:45:22.419898 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10766 14:45:22.420577 start: 2.2.6 expect-shell-connection (timeout 00:03:44) [common]
10767 14:45:22.420692 Setting prompt string to ['/ #']
10768 14:45:22.420785 Forcing a shell prompt, looking for ['/ #']
10770 14:45:22.471139 / #
10771 14:45:22.471653 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10772 14:45:22.472022 Waiting using forced prompt support (timeout 00:02:30)
10773 14:45:22.477004
10774 14:45:22.478033 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10775 14:45:22.478546 start: 2.2.7 export-device-env (timeout 00:03:44) [common]
10777 14:45:22.579762 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14166991/extract-nfsrootfs-__ac4z7s'
10778 14:45:22.586093 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14166991/extract-nfsrootfs-__ac4z7s'
10780 14:45:22.687716 / # export NFS_SERVER_IP='192.168.201.1'
10781 14:45:22.694324 export NFS_SERVER_IP='192.168.201.1'
10782 14:45:22.695201 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10783 14:45:22.695726 end: 2.2 depthcharge-retry (duration 00:01:16) [common]
10784 14:45:22.696223 end: 2 depthcharge-action (duration 00:01:16) [common]
10785 14:45:22.696716 start: 3 lava-test-retry (timeout 00:07:57) [common]
10786 14:45:22.697206 start: 3.1 lava-test-shell (timeout 00:07:57) [common]
10787 14:45:22.697686 Using namespace: common
10789 14:45:22.798900 / # #
10790 14:45:22.799546 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10791 14:45:22.805185 #
10792 14:45:22.806049 Using /lava-14166991
10794 14:45:22.907234 / # export SHELL=/bin/bash
10795 14:45:22.913599 export SHELL=/bin/bash
10797 14:45:23.015292 / # . /lava-14166991/environment
10798 14:45:23.021414 . /lava-14166991/environment
10800 14:45:23.129487 / # /lava-14166991/bin/lava-test-runner /lava-14166991/0
10801 14:45:23.130139 Test shell timeout: 10s (minimum of the action and connection timeout)
10802 14:45:23.135728 /lava-14166991/bin/lava-test-runner /lava-14166991/0
10803 14:45:23.396362 + export TESTRUN_ID=0_timesync-off
10804 14:45:23.399618 + TESTRUN_ID=0_timesync-off
10805 14:45:23.403173 + cd /lava-14166991/0/tests/0_timesync-off
10806 14:45:23.406410 ++ cat uuid
10807 14:45:23.410830 + UUID=14166991_1.6.2.3.1
10808 14:45:23.411282 + set +x
10809 14:45:23.417482 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14166991_1.6.2.3.1>
10810 14:45:23.418348 Received signal: <STARTRUN> 0_timesync-off 14166991_1.6.2.3.1
10811 14:45:23.418851 Starting test lava.0_timesync-off (14166991_1.6.2.3.1)
10812 14:45:23.419289 Skipping test definition patterns.
10813 14:45:23.420547 + systemctl stop systemd-timesyncd
10814 14:45:23.504620 + set +x
10815 14:45:23.507600 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14166991_1.6.2.3.1>
10816 14:45:23.507939 Received signal: <ENDRUN> 0_timesync-off 14166991_1.6.2.3.1
10817 14:45:23.508067 Ending use of test pattern.
10818 14:45:23.508170 Ending test lava.0_timesync-off (14166991_1.6.2.3.1), duration 0.09
10820 14:45:23.574295 + export TESTRUN_ID=1_kselftest-dt
10821 14:45:23.577190 + TESTRUN_ID=1_kselftest-dt
10822 14:45:23.580395 + cd /lava-14166991/0/tests/1_kselftest-dt
10823 14:45:23.583736 ++ cat uuid
10824 14:45:23.587429 + UUID=14166991_1.6.2.3.5
10825 14:45:23.587903 + set +x
10826 14:45:23.594194 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 14166991_1.6.2.3.5>
10827 14:45:23.594878 Received signal: <STARTRUN> 1_kselftest-dt 14166991_1.6.2.3.5
10828 14:45:23.595234 Starting test lava.1_kselftest-dt (14166991_1.6.2.3.5)
10829 14:45:23.595671 Skipping test definition patterns.
10830 14:45:23.597876 + cd ./automated/linux/kselftest/
10831 14:45:23.624092 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10832 14:45:23.661949 INFO: install_deps skipped
10833 14:45:24.166729 --2024-06-04 14:45:23-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10834 14:45:24.181683 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10835 14:45:24.312894 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10836 14:45:24.442660 HTTP request sent, awaiting response... 200 OK
10837 14:45:24.445882 Length: 1647736 (1.6M) [application/octet-stream]
10838 14:45:24.449003 Saving to: 'kselftest_armhf.tar.gz'
10839 14:45:24.449508
10840 14:45:24.449882
10841 14:45:24.701558 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
10842 14:45:24.960186 kselftest_armhf.tar 2%[ ] 47.81K 185KB/s
10843 14:45:25.217355 kselftest_armhf.tar 11%[=> ] 192.04K 371KB/s
10844 14:45:25.474409 kselftest_armhf.tar 20%[===> ] 324.96K 420KB/s
10845 14:45:25.737223 kselftest_armhf.tar 29%[====> ] 476.27K 461KB/s
10846 14:45:25.993848 kselftest_armhf.tar 39%[======> ] 640.30K 495KB/s
10847 14:45:26.252948 kselftest_armhf.tar 50%[=========> ] 809.99K 522KB/s
10848 14:45:26.512213 kselftest_armhf.tar 61%[===========> ] 986.75K 545KB/s
10849 14:45:26.770926 kselftest_armhf.tar 72%[=============> ] 1.14M 563KB/s
10850 14:45:27.028872 kselftest_armhf.tar 83%[===============> ] 1.32M 580KB/s
10851 14:45:27.035575 kselftest_armhf.tar 95%[==================> ] 1.50M 596KB/s
10852 14:45:27.041984 kselftest_armhf.tar 100%[===================>] 1.57M 621KB/s in 2.6s
10853 14:45:27.042083
10854 14:45:27.187603 2024-06-04 14:45:26 (621 KB/s) - 'kselftest_armhf.tar.gz' saved [1647736/1647736]
10855 14:45:27.187735
10856 14:45:31.638608 skiplist:
10857 14:45:31.642035 ========================================
10858 14:45:31.645007 ========================================
10859 14:45:31.712187 ============== Tests to run ===============
10860 14:45:31.715351 ===========End Tests to run ===============
10861 14:45:31.721704 shardfile-dt fail
10862 14:45:31.745558 ./kselftest.sh: 131: cannot open /lava-14166991/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
10863 14:45:31.749085 + ../../utils/send-to-lava.sh ./output/result.txt
10864 14:45:31.810326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
10865 14:45:31.810561 + set +x
10866 14:45:31.810903 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
10868 14:45:31.816854 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 14166991_1.6.2.3.5>
10869 14:45:31.817170 Received signal: <ENDRUN> 1_kselftest-dt 14166991_1.6.2.3.5
10870 14:45:31.817298 Ending use of test pattern.
10871 14:45:31.817401 Ending test lava.1_kselftest-dt (14166991_1.6.2.3.5), duration 8.22
10873 14:45:31.817739 ok: lava_test_shell seems to have completed
10874 14:45:31.817880 shardfile-dt: fail
10875 14:45:31.818009 end: 3.1 lava-test-shell (duration 00:00:09) [common]
10876 14:45:31.818136 end: 3 lava-test-retry (duration 00:00:09) [common]
10877 14:45:31.818269 start: 4 finalize (timeout 00:07:48) [common]
10878 14:45:31.818403 start: 4.1 power-off (timeout 00:00:30) [common]
10879 14:45:31.818631 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
10880 14:45:31.896903 >> Command sent successfully.
10881 14:45:31.899361 Returned 0 in 0 seconds
10882 14:45:31.999746 end: 4.1 power-off (duration 00:00:00) [common]
10884 14:45:32.000074 start: 4.2 read-feedback (timeout 00:07:48) [common]
10886 14:45:32.000625 Listened to connection for namespace 'common' for up to 1s
10887 14:45:33.001510 Finalising connection for namespace 'common'
10888 14:45:33.002170 Disconnecting from shell: Finalise
10889 14:45:33.002577 / #
10890 14:45:33.103554 end: 4.2 read-feedback (duration 00:00:01) [common]
10891 14:45:33.104243 end: 4 finalize (duration 00:00:01) [common]
10892 14:45:33.104864 Cleaning after the job
10893 14:45:33.105625 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166991/tftp-deploy-4m917e0t/ramdisk
10894 14:45:33.115897 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166991/tftp-deploy-4m917e0t/kernel
10895 14:45:33.148081 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166991/tftp-deploy-4m917e0t/dtb
10896 14:45:33.148409 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166991/tftp-deploy-4m917e0t/nfsrootfs
10897 14:45:33.217670 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166991/tftp-deploy-4m917e0t/modules
10898 14:45:33.223430 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14166991
10899 14:45:33.764222 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14166991
10900 14:45:33.764405 Job finished correctly